Integrated circuit package with lead structure and method of preparing the same

NASA Technical Reports Server (NTRS)

Kennedy, B. W. (Inventor)

1973-01-01

A beam-lead integrated circuit package assembly including a beam-lead integrated circuit chip, a lead frame array bonded to projecting fingers of the chip, a rubber potting compound disposed around the chip, and an encapsulating molded plastic is described. The lead frame array is prepared by photographically printing a lead pattern on a base metal sheet, selectively etching to remove metal between leads, and plating with gold. Joining of the chip to the lead frame array is carried out by thermocompression bonding of mating goldplated surfaces. A small amount of silicone rubber is then applied to cover the chip and bonded joints, and the package is encapsulated with epoxy resin, applied by molding.

Crosstalk-free operation of multielement superconducting nanowire single-photon detector array integrated with single-flux-quantum circuit in a 0.1 W Gifford-McMahon cryocooler.

PubMed

Yamashita, Taro; Miki, Shigehito; Terai, Hirotaka; Makise, Kazumasa; Wang, Zhen

2012-07-15

We demonstrate the successful operation of a multielement superconducting nanowire single-photon detector (SSPD) array integrated with a single-flux-quantum (SFQ) readout circuit in a compact 0.1 W Gifford-McMahon cryocooler. A time-resolved readout technique, where output signals from each element enter the SFQ readout circuit with finite time intervals, revealed crosstalk-free operation of the four-element SSPD array connected with the SFQ readout circuit. The timing jitter and the system detection efficiency were measured to be 50 ps and 11.4%, respectively, which were comparable to the performance of practical single-pixel SSPD systems.

Geiger-Mode Avalanche Photodiode Arrays Integrated to All-Digital CMOS Circuits.

PubMed

Aull, Brian

2016-04-08

This article reviews MIT Lincoln Laboratory's work over the past 20 years to develop photon-sensitive image sensors based on arrays of silicon Geiger-mode avalanche photodiodes. Integration of these detectors to all-digital CMOS readout circuits enable exquisitely sensitive solid-state imagers for lidar, wavefront sensing, and passive imaging.

Defense Industrial Base Assessment: U.S. Integrated Circuit Design and Fabrication Capability

DTIC Science & Technology

2009-05-01

in the U.S for the period 2003-2006, with projections to 2011.6 The resulting draft OTE survey was field tested for accuracy and usability with a...custom application specific integrated circuits (ASICs) to field programmable gate arrays (FPGAs). Companies of all sizes can manufacture these IC...able to design one-time Electronically Programmable Gate Arrays (EPGAs) while nine are able to design Field Programmable Gate Arrays (FPGAs). Eight

System-Level Integrated Circuit (SLIC) development for phased array antenna applications

NASA Technical Reports Server (NTRS)

Shalkhauser, K. A.; Raquet, C. A.

1991-01-01

A microwave/millimeter wave system-level integrated circuit (SLIC) being developed for use in phased array antenna applications is described. The program goal is to design, fabricate, test, and deliver an advanced integrated circuit that merges radio frequency (RF) monolithic microwave integrated circuit (MMIC) technologies with digital, photonic, and analog circuitry that provide control, support, and interface functions. As a whole, the SLIC will offer improvements in RF device performance, uniformity, and stability while enabling accurate, rapid, repeatable control of the RF signal. Furthermore, the SLIC program addresses issues relating to insertion of solid state devices into antenna systems, such as the reduction in number of bias, control, and signal lines. Program goals, approach, and status are discussed.

System-level integrated circuit (SLIC) development for phased array antenna applications

NASA Technical Reports Server (NTRS)

Shalkhauser, K. A.; Raquet, C. A.

1991-01-01

A microwave/millimeter wave system-level integrated circuit (SLIC) being developed for use in phased array antenna applications is described. The program goal is to design, fabricate, test, and deliver an advanced integrated circuit that merges radio frequency (RF) monolithic microwave integrated circuit (MMIC) technologies with digital, photonic, and analog circuitry that provide control, support, and interface functions. As a whole, the SLIC will offer improvements in RF device performance, uniformity, and stability while enabling accurate, rapid, repeatable control of the RF signal. Furthermore, the SLIC program addresses issues relating to insertion of solid state devices into antenna systems, such as the reduction in number of bias, control, and signal lines. Program goals, approach, and status are discussed.

Multi-channel detector readout method and integrated circuit

DOEpatents

Moses, William W.; Beuville, Eric; Pedrali-Noy, Marzio

2006-12-12

An integrated circuit which provides multi-channel detector readout from a detector array. The circuit receives multiple signals from the elements of a detector array and compares the sampled amplitudes of these signals against a noise-floor threshold and against one another. A digital signal is generated which corresponds to the location of the highest of these signal amplitudes which exceeds the noise floor threshold. The digital signal is received by a multiplexing circuit which outputs an analog signal corresponding the highest of the input signal amplitudes. In addition a digital control section provides for programmatic control of the multiplexer circuit, amplifier gain, amplifier reset, masking selection, and test circuit functionality on each input thereof.

Multi-channel detector readout method and integrated circuit

DOEpatents

Moses, William W.; Beuville, Eric; Pedrali-Noy, Marzio

2004-05-18

An integrated circuit which provides multi-channel detector readout from a detector array. The circuit receives multiple signals from the elements of a detector array and compares the sampled amplitudes of these signals against a noise-floor threshold and against one another. A digital signal is generated which corresponds to the location of the highest of these signal amplitudes which exceeds the noise floor threshold. The digital signal is received by a multiplexing circuit which outputs an analog signal corresponding the highest of the input signal amplitudes. In addition a digital control section provides for programmatic control of the multiplexer circuit, amplifier gain, amplifier reset, masking selection, and test circuit functionality on each input thereof.

A design concept for an MMIC (Monolithic Microwave Integrated Circuit) microstrip phased array

NASA Technical Reports Server (NTRS)

Lee, Richard Q.; Smetana, Jerry; Acosta, Roberto

1987-01-01

A conceptual design for a microstrip phased array with monolithic microwave integrated circuit (MMIC) amplitude and phase controls is described. The MMIC devices used are 20 GHz variable power amplifiers and variable phase shifters recently developed by NASA contractors for applications in future Ka proposed design, which concept is for a general NxN element array of rectangular lattice geometry. Subarray excitation is incorporated in the MMIC phased array design to reduce the complexity of the beam forming network and the number of MMIC components required.

ASIC Readout Circuit Architecture for Large Geiger Photodiode Arrays

NASA Technical Reports Server (NTRS)

Vasile, Stefan; Lipson, Jerold

2012-01-01

The objective of this work was to develop a new class of readout integrated circuit (ROIC) arrays to be operated with Geiger avalanche photodiode (GPD) arrays, by integrating multiple functions at the pixel level (smart-pixel or active pixel technology) in 250-nm CMOS (complementary metal oxide semiconductor) processes. In order to pack a maximum of functions within a minimum pixel size, the ROIC array is a full, custom application-specific integrated circuit (ASIC) design using a mixed-signal CMOS process with compact primitive layout cells. The ROIC array was processed to allow assembly in bump-bonding technology with photon-counting infrared detector arrays into 3-D imaging cameras (LADAR). The ROIC architecture was designed to work with either common- anode Si GPD arrays or common-cathode InGaAs GPD arrays. The current ROIC pixel design is hardwired prior to processing one of the two GPD array configurations, and it has the provision to allow soft reconfiguration to either array (to be implemented into the next ROIC array generation). The ROIC pixel architecture implements the Geiger avalanche quenching, bias, reset, and time to digital conversion (TDC) functions in full-digital design, and uses time domain over-sampling (vernier) to allow high temporal resolution at low clock rates, increased data yield, and improved utilization of the laser beam.

Microfabricated ion trap array

DOEpatents

Blain, Matthew G [Albuquerque, NM; Fleming, James G [Albuquerque, NM

2006-12-26

A microfabricated ion trap array, comprising a plurality of ion traps having an inner radius of order one micron, can be fabricated using surface micromachining techniques and materials known to the integrated circuits manufacturing and microelectromechanical systems industries. Micromachining methods enable batch fabrication, reduced manufacturing costs, dimensional and positional precision, and monolithic integration of massive arrays of ion traps with microscale ion generation and detection devices. Massive arraying enables the microscale ion traps to retain the resolution, sensitivity, and mass range advantages necessary for high chemical selectivity. The reduced electrode voltage enables integration of the microfabricated ion trap array with on-chip circuit-based rf operation and detection electronics (i.e., cell phone electronics). Therefore, the full performance advantages of the microfabricated ion trap array can be realized in truly field portable, handheld microanalysis systems.

Arrays of Carbon Nanotubes as RF Filters in Waveguides

NASA Technical Reports Server (NTRS)

Hoppe, Daniel; Hunt, Brian; Hoenk, Michael; Noca, Flavio; Xu, Jimmy

2003-01-01

Brushlike arrays of carbon nanotubes embedded in microstrip waveguides provide highly efficient (high-Q) mechanical resonators that will enable ultraminiature radio-frequency (RF) integrated circuits. In its basic form, this invention is an RF filter based on a carbon nanotube array embedded in a microstrip (or coplanar) waveguide, as shown in Figure 1. In addition, arrays of these nanotube-based RF filters can be used as an RF filter bank. Applications of this new nanotube array device include a variety of communications and signal-processing technologies. High-Q resonators are essential for stable, low-noise communications, and radar applications. Mechanical oscillators can exhibit orders of magnitude higher Qs than electronic resonant circuits, which are limited by resistive losses. This has motivated the development of a variety of mechanical resonators, including bulk acoustic wave (BAW) resonators, surface acoustic wave (SAW) resonators, and Si and SiC micromachined resonators (known as microelectromechanical systems or MEMS). There is also a strong push to extend the resonant frequencies of these oscillators into the GHz regime of state-of-the-art electronics. Unfortunately, the BAW and SAW devices tend to be large and are not easily integrated into electronic circuits. MEMS structures have been integrated into circuits, but efforts to extend MEMS resonant frequencies into the GHz regime have been difficult because of scaling problems with the capacitively-coupled drive and readout. In contrast, the proposed devices would be much smaller and hence could be more readily incorporated into advanced RF (more specifically, microwave) integrated circuits.

GaAs Optoelectronic Integrated-Circuit Neurons

NASA Technical Reports Server (NTRS)

Lin, Steven H.; Kim, Jae H.; Psaltis, Demetri

1992-01-01

Monolithic GaAs optoelectronic integrated circuits developed for use as artificial neurons. Neural-network computer contains planar arrays of optoelectronic neurons, and variable synaptic connections between neurons effected by diffraction of light from volume hologram in photorefractive material. Basic principles of neural-network computers explained more fully in "Optoelectronic Integrated Circuits For Neural Networks" (NPO-17652). In present circuits, devices replaced by metal/semiconductor field effect transistors (MESFET's), which consume less power.

Characteristics of Monolithically Integrated InGaAs Active Pixel Imager Array

NASA Technical Reports Server (NTRS)

Kim, Q.; Cunningham, T. J.; Pain, B.; Lange, M. J.; Olsen, G. H.

2000-01-01

Switching and amplifying characteristics of a newly developed monolithic InGaAs Active Pixel Imager Array are presented. The sensor array is fabricated from InGaAs material epitaxially deposited on an InP substrate. It consists of an InGaAs photodiode connected to InP depletion-mode junction field effect transistors (JFETs) for low leakage, low power, and fast control of circuit signal amplifying, buffering, selection, and reset. This monolithically integrated active pixel sensor configuration eliminates the need for hybridization with silicon multiplexer. In addition, the configuration allows the sensor to be front illuminated, making it sensitive to visible as well as near infrared signal radiation. Adapting the existing 1.55 micrometer fiber optical communication technology, this integration will be an ideal system of optoelectronic integration for dual band (Visible/IR) applications near room temperature, for use in atmospheric gas sensing in space, and for target identification on earth. In this paper, two different types of small 4 x 1 test arrays will be described. The effectiveness of switching and amplifying circuits will be discussed in terms of circuit effectiveness (leakage, operating frequency, and temperature) in preparation for the second phase demonstration of integrated, two-dimensional monolithic InGaAs active pixel sensor arrays for applications in transportable shipboard surveillance, night vision, and emission spectroscopy.

Readout circuit with novel background suppression for long wavelength infrared focal plane arrays

NASA Astrophysics Data System (ADS)

Xie, L.; Xia, X. J.; Zhou, Y. F.; Wen, Y.; Sun, W. F.; Shi, L. X.

2011-02-01

In this article, a novel pixel readout circuit using a switched-capacitor integrator mode background suppression technique is presented for long wavelength infrared focal plane arrays. This circuit can improve dynamic range and signal-to-noise ratio by suppressing the large background current during integration. Compared with other background suppression techniques, the new background suppression technique is less sensitive to the process mismatch and has no additional shot noise. The proposed circuit is theoretically analysed and simulated while taking into account the non-ideal characteristics. The result shows that the background suppression non-uniformity is ultra-low even for a large process mismatch. The background suppression non-uniformity of the proposed circuit can also remain very small with technology scaling.

Broadband image sensor array based on graphene-CMOS integration

NASA Astrophysics Data System (ADS)

Goossens, Stijn; Navickaite, Gabriele; Monasterio, Carles; Gupta, Shuchi; Piqueras, Juan José; Pérez, Raúl; Burwell, Gregory; Nikitskiy, Ivan; Lasanta, Tania; Galán, Teresa; Puma, Eric; Centeno, Alba; Pesquera, Amaia; Zurutuza, Amaia; Konstantatos, Gerasimos; Koppens, Frank

2017-06-01

Integrated circuits based on complementary metal-oxide-semiconductors (CMOS) are at the heart of the technological revolution of the past 40 years, enabling compact and low-cost microelectronic circuits and imaging systems. However, the diversification of this platform into applications other than microcircuits and visible-light cameras has been impeded by the difficulty to combine semiconductors other than silicon with CMOS. Here, we report the monolithic integration of a CMOS integrated circuit with graphene, operating as a high-mobility phototransistor. We demonstrate a high-resolution, broadband image sensor and operate it as a digital camera that is sensitive to ultraviolet, visible and infrared light (300-2,000 nm). The demonstrated graphene-CMOS integration is pivotal for incorporating 2D materials into the next-generation microelectronics, sensor arrays, low-power integrated photonics and CMOS imaging systems covering visible, infrared and terahertz frequencies.

Phased-Array Antenna With Optoelectronic Control Circuits

NASA Technical Reports Server (NTRS)

Kunath, Richard R.; Shalkhauser, Kurt A.; Martzaklis, Konstantinos; Lee, Richard Q.; Downey, Alan N.; Simons, Rainee N.

1995-01-01

Prototype phased-array antenna features control of amplitude and phase at each radiating element. Amplitude- and phase-control signals transmitted on optical fiber to optoelectronic interface circuit (OEIC), then to monolithic microwave integrated circuit (MMIC) at each element. Offers advantages of flexible, rapid electronic steering and shaping of beams. Furthermore, greater number of elements, less overall performance of antenna degraded by malfunction in single element.

Multispectral linear array visible and shortwave infrared sensors

NASA Astrophysics Data System (ADS)

Tower, J. R.; Warren, F. B.; Pellon, L. E.; Strong, R.; Elabd, H.; Cope, A. D.; Hoffmann, D. M.; Kramer, W. M.; Longsderff, R. W.

1984-08-01

All-solid state pushbroom sensors for multispectral linear array (MLA) instruments to replace mechanical scanners used on LANDSAT satellites are introduced. A buttable, four-spectral-band, linear-format charge coupled device (CCD) and a buttable, two-spectral-band, linear-format, shortwave infrared CCD are described. These silicon integrated circuits may be butted end to end to provide multispectral focal planes with thousands of contiguous, in-line photosites. The visible CCD integrated circuit is organized as four linear arrays of 1024 pixels each. Each array views the scene in a different spectral window, resulting in a four-band sensor. The shortwave infrared (SWIR) sensor is organized as 2 linear arrays of 512 detectors each. Each linear array is optimized for performance at a different wavelength in the SWIR band.

Active pixel sensor array with multiresolution readout

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Kemeny, Sabrina E. (Inventor); Pain, Bedabrata (Inventor)

1999-01-01

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node. There is also a readout circuit, part of which can be disposed at the bottom of each column of cells and be common to all the cells in the column. The imaging device can also include an electronic shutter formed on the substrate adjacent the photogate, and/or a storage section to allow for simultaneous integration. In addition, the imaging device can include a multiresolution imaging circuit to provide images of varying resolution. The multiresolution circuit could also be employed in an array where the photosensitive portion of each pixel cell is a photodiode. This latter embodiment could further be modified to facilitate low light imaging.

Integrating IR detector imaging systems

NASA Technical Reports Server (NTRS)

Bailey, G. C. (Inventor)

1984-01-01

An integrating IR detector array for imaging is provided in a hybrid circuit with InSb mesa diodes in a linear array, a single J-FET preamplifier for readout, and a silicon integrated circuit multiplexer. Thin film conductors in a fan out pattern deposited on an Al2O3 substrate connect the diodes to the multiplexer, and thick film conductors also connect the reset switch and preamplifier to the multiplexer. Two phase clock pulses are applied with a logic return signal to the multiplexer through triax comprised of three thin film conductors deposited between layers. A lens focuses a scanned image onto the diode array for horizontal read out while a scanning mirror provides vertical scan.

Chemistry integrated circuit: chemical system on a complementary metal oxide semiconductor integrated circuit.

PubMed

Nakazato, Kazuo

2014-03-28

By integrating chemical reactions on a large-scale integration (LSI) chip, new types of device can be created. For biomedical applications, monolithically integrated sensor arrays for potentiometric, amperometric and impedimetric sensing of biomolecules have been developed. The potentiometric sensor array detects pH and redox reaction as a statistical distribution of fluctuations in time and space. For the amperometric sensor array, a microelectrode structure for measuring multiple currents at high speed has been proposed. The impedimetric sensor array is designed to measure impedance up to 10 MHz. The multimodal sensor array will enable synthetic analysis and make it possible to standardize biosensor chips. Another approach is to create new functional devices by integrating molecular systems with LSI chips, for example image sensors that incorporate biological materials with a sensor array. The quantum yield of the photoelectric conversion of photosynthesis is 100%, which is extremely difficult to achieve by artificial means. In a recently developed process, a molecular wire is plugged directly into a biological photosynthetic system to efficiently conduct electrons to a gold electrode. A single photon can be detected at room temperature using such a system combined with a molecular single-electron transistor.

Integrated Avalanche Photodiode arrays

DOE Office of Scientific and Technical Information (OSTI.GOV)

Harmon, Eric S.

2017-04-18

The present disclosure includes devices for detecting photons, including avalanche photon detectors, arrays of such detectors, and circuits including such arrays. In some aspects, the detectors and arrays include a virtual beveled edge mesa structure surrounded by resistive material damaged by ion implantation and having side wall profiles that taper inwardly towards the top of the mesa structures, or towards the direction from which the ion implantation occurred. Other aspects are directed to masking and multiple implantation and/or annealing steps. Furthermore, methods for fabricating and using such devices, circuits and arrays are disclosed.

Integrated avalanche photodiode arrays

DOEpatents

Harmon, Eric S.

2015-07-07

The present disclosure includes devices for detecting photons, including avalanche photon detectors, arrays of such detectors, and circuits including such arrays. In some aspects, the detectors and arrays include a virtual beveled edge mesa structure surrounded by resistive material damaged by ion implantation and having side wall profiles that taper inwardly towards the top of the mesa structures, or towards the direction from which the ion implantation occurred. Other aspects are directed to masking and multiple implantation and/or annealing steps. Furthermore, methods for fabricating and using such devices, circuits and arrays are disclosed.

Geiger-Mode Avalanche Photodiode Arrays Integrated to All-Digital CMOS Circuits

DTIC Science & Technology

2016-01-20

Figure 7 4×4 GMAPD array wire bonded to CMOS timing circuits Figure 8 Low‐fill‐factor APD design used in lidar sensors The APD doping...epitaxial growth and the pixels are isolated by mesa etch. 128×32 lidar image sensors were built by bump bonding the APD arrays to a CMOS timing...passive image sensor with this large a format based on hybridization of a GMAPD array to a CMOS readout. Fig. 14 shows one of the first images taken

Optical waveguide circuit board with a surface-mounted optical receiver array

NASA Astrophysics Data System (ADS)

Thomson, J. E.; Levesque, Harold; Savov, Emil; Horwitz, Fred; Booth, Bruce L.; Marchegiano, Joseph E.

1994-03-01

A photonic circuit board is fabricated for potential application to interchip and interboard parallel optical links. The board comprises photolithographically patterned polymer optical waveguides on a conventional glass-epoxy electrical circuit board and a surface-mounted integrated circuit (IC) package that optically and electrically couples to an optoelectronic IC. The waveguide circuits include eight-channel arrays of straights, cross-throughs, curves, self- aligning interconnects to multi-fiber ribbon, and out-of-plane turning mirrors. A coherent, fused bundle of optical fibers couples light between 45-deg waveguide mirrors and a GaAs receiver array in the IC package. The fiber bundle is easily aligned to the mirrors and the receivers and is amenable to surface mounting and hermetic sealing. The waveguide-receiver- array board achieved error-free data rates up to 1.25 Gbits/s per channel, and modal noise was shown to be negligible.

Reconfigurable electro-optical directed-logic circuit using carrier-depletion micro-ring resonators.

PubMed

Qiu, Ciyuan; Gao, Weilu; Soref, Richard; Robinson, Jacob T; Xu, Qianfan

2014-12-15

Here we demonstrate a reconfigurable electro-optical directed-logic circuit based on a regular array of integrated optical switches. Each 1×1 optical switch consists of a micro-ring resonator with an embedded lateral p-n junction and a micro-heater. We achieve high-speed on-off switching by applying electrical logic signals to the p-n junction. We can configure the operation mode of each switch by thermal tuning the resonance wavelength. The result is an integrated optical circuit that can be reconfigured to perform any combinational logic operation. As a proof-of-principle, we fabricated a multi-spectral directed-logic circuit based on a fourfold array of switches and showed that this circuit can be reconfigured to perform arbitrary two-input logic functions with speeds up to 3  GB/s.

Realizing topological edge states in a silicon nitride microring-based photonic integrated circuit.

PubMed

Yin, Chenxuan; Chen, Yujie; Jiang, Xiaohui; Zhang, Yanfeng; Shao, Zengkai; Xu, Pengfei; Yu, Siyuan

2016-10-15

Topological edge states in a photonic integrated circuit based on the platform of silicon nitride are demonstrated with a two-dimensional coupled resonator optical waveguide array involving the synthetic magnetic field for photons at near-infrared wavelengths. Measurements indicate that the topological edge states can be observed at certain wavelengths, with light travelling around the boundary of the array. Combined with the induced disorders in fabrication near the edge, the system shows the defect immunity under the topological protection of edge states.

Scalable, Lightweight, Integrated and Quick-to-Assemble (SLIQ) Hyperdrives for Functional Circuit Dissection.

PubMed

Liang, Li; Oline, Stefan N; Kirk, Justin C; Schmitt, Lukas Ian; Komorowski, Robert W; Remondes, Miguel; Halassa, Michael M

2017-01-01

Independently adjustable multielectrode arrays are routinely used to interrogate neuronal circuit function, enabling chronic in vivo monitoring of neuronal ensembles in freely behaving animals at a single-cell, single spike resolution. Despite the importance of this approach, its widespread use is limited by highly specialized design and fabrication methods. To address this, we have developed a Scalable, Lightweight, Integrated and Quick-to-assemble multielectrode array platform. This platform additionally integrates optical fibers with independently adjustable electrodes to allow simultaneous single unit recordings and circuit-specific optogenetic targeting and/or manipulation. In current designs, the fully assembled platforms are scalable from 2 to 32 microdrives, and yet range 1-3 g, light enough for small animals. Here, we describe the design process starting from intent in computer-aided design, parameter testing through finite element analysis and experimental means, and implementation of various applications across mice and rats. Combined, our methods may expand the utility of multielectrode recordings and their continued integration with other tools enabling functional dissection of intact neural circuits.

A Readout Integrated Circuit (ROIC) employing self-adaptive background current compensation technique for Infrared Focal Plane Array (IRFPA)

NASA Astrophysics Data System (ADS)

Zhou, Tong; Zhao, Jian; He, Yong; Jiang, Bo; Su, Yan

2018-05-01

A novel self-adaptive background current compensation circuit applied to infrared focal plane array is proposed in this paper, which can compensate the background current generated in different conditions. Designed double-threshold detection strategy is to estimate and eliminate the background currents, which could significantly reduce the hardware overhead and improve the uniformity among different pixels. In addition, the circuit is well compatible to various categories of infrared thermo-sensitive materials. The testing results of a 4 × 4 experimental chip showed that the proposed circuit achieves high precision, wide application and high intelligence. Tape-out of the 320 × 240 readout circuit, as well as the bonding, encapsulation and imaging verification of uncooled infrared focal plane array, have also been completed.

A discrete component low-noise preamplifier readout for a linear (1×16) SiC photodiode array

NASA Astrophysics Data System (ADS)

Kahle, Duncan; Aslam, Shahid; Herrero, Federico A.; Waczynski, Augustyn

2016-09-01

A compact, low-noise and inexpensive preamplifier circuit has been designed and fabricated to optimally readout a common cathode (1×16) channel 4H-SiC Schottky photodiode array for use in ultraviolet experiments. The readout uses an operational amplifier with 10 pF capacitor in the feedback loop in parallel with a low leakage switch for each of the channels. This circuit configuration allows for reiterative sample, integrate and reset. A sampling technique is given to remove Johnson noise, enabling a femtoampere level readout noise performance. Commercial-off-the-shelf acquisition electronics are used to digitize the preamplifier analog signals. The data logging acquisition electronics has a different integration circuit, which allows the bandwidth and gain to be independently adjusted. Using this readout, photoresponse measurements across the array between spectral wavelengths 200 nm and 370 nm are made to establish the array pixels external quantum efficiency, current responsivity and noise equivalent power.

A Discrete Component Low-Noise Preamplifier Readout for a Linear (1x16) SiC Photodiode Array

NASA Technical Reports Server (NTRS)

Kahle, Duncan; Aslam, Shahid; Herrero, Frederico A.; Waczynski, Augustyn

2016-01-01

A compact, low-noise and inexpensive preamplifier circuit has been designed and fabricated to optimally readout a common cathode (1x16) channel 4H-SiC Schottky photodiode array for use in ultraviolet experiments. The readout uses an operational amplifier with 10 pF capacitor in the feedback loop in parallel with a low leakage switch for each of the channels. This circuit configuration allows for reiterative sample, integrate and reset. A sampling technique is given to remove Johnson noise, enabling a femtoampere level readout noise performance. Commercial-off-the-shelf acquisition electronics are used to digitize the preamplifier analogue signals. The data logging acquisition electronics has a different integration circuit, which allows the bandwidth and gain to be independently adjusted. Using this readout, photoresponse measurements across the array between spectral wavelengths 200 nm and 370 nm are made to establish the array pixels external quantum efficiency, current responsivity and noise equivalent power.

Operational considerations of the Advanced Photovoltaic Solar Array

NASA Technical Reports Server (NTRS)

Stella, Paul M.; Kurland, Richard M.

1992-01-01

Issues affecting the long-term operational performance of the Advanced Photovoltaic Solar Array (APSA) are discussed, with particular attention given to circuit electrical integrity from shadowed and cracked cell modules. The successful integration of individual advanced array components provides a doubling of array specific performance from the previous NASA-developed advanced array (SAFE). Flight test modules both recently fabricated and under fabrication are described. The development of advanced high-performance blanket technology for future APSA enhancement is presented.

Operational considerations of the Advanced Photovoltaic Solar Array

NASA Astrophysics Data System (ADS)

Stella, Paul M.; Kurland, Richard M.

Issues affecting the long-term operational performance of the Advanced Photovoltaic Solar Array (APSA) are discussed, with particular attention given to circuit electrical integrity from shadowed and cracked cell modules. The successful integration of individual advanced array components provides a doubling of array specific performance from the previous NASA-developed advanced array (SAFE). Flight test modules both recently fabricated and under fabrication are described. The development of advanced high-performance blanket technology for future APSA enhancement is presented.

PV Systems Reliability Final Technical Report: Ground Fault Detection

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lavrova, Olga; Flicker, Jack David; Johnson, Jay

We have examined ground faults in PhotoVoltaic (PV) arrays and the efficacy of fuse, current detection (RCD), current sense monitoring/relays (CSM), isolation/insulation (Riso) monitoring, and Ground Fault Detection and Isolation (GFID) using simulations based on a Simulation Program with Integrated Circuit Emphasis SPICE ground fault circuit model, experimental ground faults installed on real arrays, and theoretical equations.

Fast, High-Precision Readout Circuit for Detector Arrays

NASA Technical Reports Server (NTRS)

Rider, David M.; Hancock, Bruce R.; Key, Richard W.; Cunningham, Thomas J.; Wrigley, Chris J.; Seshadri, Suresh; Sander, Stanley P.; Blavier, Jean-Francois L.

2013-01-01

The GEO-CAPE mission described in NASA's Earth Science and Applications Decadal Survey requires high spatial, temporal, and spectral resolution measurements to monitor and characterize the rapidly changing chemistry of the troposphere over North and South Americas. High-frame-rate focal plane arrays (FPAs) with many pixels are needed to enable such measurements. A high-throughput digital detector readout integrated circuit (ROIC) that meets the GEO-CAPE FPA needs has been developed, fabricated, and tested. The ROIC is based on an innovative charge integrating, fast, high-precision analog-to-digital circuit that is built into each pixel. The 128×128-pixel ROIC digitizes all 16,384 pixels simultaneously at frame rates up to 16 kHz to provide a completely digital output on a single integrated circuit at an unprecedented rate of 262 million pixels per second. The approach eliminates the need for off focal plane electronics, greatly reducing volume, mass, and power compared to conventional FPA implementations. A focal plane based on this ROIC will require less than 2 W of power on a 1×1-cm integrated circuit. The ROIC is fabricated of silicon using CMOS technology. It is designed to be indium bump bonded to a variety of detector materials including silicon PIN diodes, indium antimonide (InSb), indium gallium arsenide (In- GaAs), and mercury cadmium telluride (HgCdTe) detector arrays to provide coverage over a broad spectral range in the infrared, visible, and ultraviolet spectral ranges.

Analog Module Architecture for Space-Qualified Field-Programmable Mixed-Signal Arrays

NASA Technical Reports Server (NTRS)

Edwards, R. Timothy; Strohbehn, Kim; Jaskulek, Steven E.; Katz, Richard

1999-01-01

Spacecraft require all manner of both digital and analog circuits. Onboard digital systems are constructed almost exclusively from field-programmable gate array (FPGA) circuits providing numerous advantages over discrete design including high integration density, high reliability, fast turn-around design cycle time, lower mass, volume, and power consumption, and lower parts acquisition and flight qualification costs. Analog and mixed-signal circuits perform tasks ranging from housekeeping to signal conditioning and processing. These circuits are painstakingly designed and built using discrete components due to a lack of options for field-programmability. FPAA (Field-Programmable Analog Array) and FPMA (Field-Programmable Mixed-signal Array) parts exist but not in radiation-tolerant technology and not necessarily in an architecture optimal for the design of analog circuits for spaceflight applications. This paper outlines an architecture proposed for an FPAA fabricated in an existing commercial digital CMOS process used to make radiation-tolerant antifuse-based FPGA devices. The primary concerns are the impact of the technology and the overall array architecture on the flexibility of programming, the bandwidth available for high-speed analog circuits, and the accuracy of the components for high-performance applications.

Integrated semiconductor-magnetic random access memory system

NASA Technical Reports Server (NTRS)

Katti, Romney R. (Inventor); Blaes, Brent R. (Inventor)

2001-01-01

The present disclosure describes a non-volatile magnetic random access memory (RAM) system having a semiconductor control circuit and a magnetic array element. The integrated magnetic RAM system uses CMOS control circuit to read and write data magnetoresistively. The system provides a fast access, non-volatile, radiation hard, high density RAM for high speed computing.

Faraday Cup Array Integrated with a Readout IC and Method for Manufacture Thereof

NASA Technical Reports Server (NTRS)

Temple, Dorota (Inventor); Bower, Christopher A. (Inventor); Hedgepath Gilchrist, Kristin (Inventor); Stoner, Brian R. (Inventor)

2014-01-01

A detector array and method for making the detector array. The array includes a substrate including a plurality of trenches formed therein, and includes a plurality of collectors electrically isolated from each other, formed on the walls of the trenches, and configured to collect charge particles incident on respective ones of the collectors and to output from said collectors signals indicative of charged particle collection. The array includes a plurality of readout circuits disposed on a side of the substrate opposite openings to the collectors. The readout circuits are configured to read charge collection signals from respective ones of the plurality of collectors.

Exploring the Use of the LT3480 (RH3480) Circuit as Low-Power, Low-Voltage Solar Array Regulator

NASA Astrophysics Data System (ADS)

Garrigos, A.; Lizan, J. L.; Blanes, J. M.; Gutierrez, R.

2014-08-01

With the advent of PoL technology, several commercial integrated switching regulators already have their space- qualified versions. Apart of PoL and secondary supply applications, other functions can be explored using those integrated circuits. In this work, the Solar Array Regulator function is analyzed using the commercial LT3480 circuit, which has the space counterpart (RH3480) commercialized by MSK and named MSK5058RH and later MSK5031 (but not rad-hard). Input voltage regulation, taper charge, protection functions and module parallelization are studied and verified experimentally in a low-voltage, low-power MPPT battery bus configuration. Potential users of this approach are micro and nano-satellites power systems.

Multilevel photonic modules for millimeter-wave phased-array antennas

NASA Astrophysics Data System (ADS)

Paolella, Arthur C.; Bauerle, Athena; Joshi, Abhay M.; Wright, James G.; Coryell, Louis A.

2000-09-01

Millimeter wave phased array systems have antenna element sizes and spacings similar to MMIC chip dimensions by virtue of the operating wavelength. Designing modules in traditional planar packaing techniques are therefore difficult to implement. An advantageous way to maintain a small module footprint compatible with Ka-Band and high frequency systems is to take advantage of two leading edge technologies, opto- electronic integrated circuits (OEICs) and multilevel packaging technology. Under a Phase II SBIR these technologies are combined to form photonic modules for optically controlled millimeter wave phased array antennas. The proposed module, consisting of an OEIC integrated with a planar antenna array will operate on the 40GHz region. The OEIC consists of an InP based dual-depletion PIN photodetector and distributed amplifier. The multi-level module will be fabricated using an enhanced circuit processing thick film process. Since the modules are batch fabricated using an enhanced circuit processing thick film process. Since the modules are batch fabricated, using standard commercial processes, it has the potential to be low cost while maintaining high performance, impacting both military and commercial communications systems.

Producibility of Vertically Integrated Photodiode (VIP)tm scanning focal plane arrays

NASA Astrophysics Data System (ADS)

Turner, Arthur M.; Teherani, Towfik; Ehmke, John C.; Pettitt, Cindy; Conlon, Peggy; Beck, Jeffrey D.; McCormack, Kent; Colombo, Luigi; Lahutsky, Tom; Murphy, Terry; Williams, Robert L.

1994-07-01

Vertically integrated photodiode, VIPTM, technology is now being used to produce second generation infrared focal plane arrays with high yields and performance. The VIPTM process employs planar, ion implanted, n on p diodes in HgCdTe which is epoxy hybridized directly to the read out integrated circuits on 100 mm Si wafers. The process parameters that are critical for high performance and yield include: HgCdTe dislocation density and thickness, backside passivation, frontside passivation, and junction formation. Producibility of infrared focal plane arrays (IRFPAs) is also significantly enhanced by read out integrated circuits (ROICs) which have the ability to deselect defective pixels. Cold probe screening before lab dewar assembly reduces costs and improves cycle times. The 240 X 1 and 240 X 2 scanning array formats are used to demonstrate the effect of process optimization, deselect, and cold probe screening on yield and cycle time. The versatility of the VIPTM technology and its extension to large area arrays is demonstrated using 240/288 X 4 and 480 X 5 TDI formats. Finally, the high performance of VIPTM IRFPAs is demonstrated by comparing data from a 480 X 5 to the SADA-II specification.

SiGe Integrated Circuit Developments for SQUID/TES Readout

NASA Astrophysics Data System (ADS)

Prêle, D.; Voisin, F.; Beillimaz, C.; Chen, S.; Piat, M.; Goldwurm, A.; Laurent, P.

2018-03-01

SiGe integrated circuits dedicated to the readout of superconducting bolometer arrays for astrophysics have been developed since more than 10 years at APC. Whether for Cosmic Microwave Background (CMB) observations with the QUBIC ground-based experiment (Aumont et al. in astro-ph.IM, 2016. arXiv:1609.04372) or for the Hot and Energetic Universe science theme with the X-IFU instrument on-board of the ATHENA space mission (Barret et al. in SPIE 9905, space telescopes & instrumentation 2016: UV to γ Ray, 2016. https://doi.org/10.1117/12.2232432), several kinds of Transition Edge Sensor (TES) (Irwin and Hilton, in ENSS (ed) Cryogenic particle detection, Springer, Berlin, 2005) arrays have been investigated. To readout such superconducting detector arrays, we use time or frequency domain multiplexers (TDM, FDM) (Prêle in JINST 10:C08015, 2016. https://doi.org/10.1088/1748-0221/10/08/C08015) with Superconducting QUantum Interference Devices (SQUID). In addition to the SQUID devices, low-noise biasing and amplification are needed. These last functions can be obtained by using BiCMOS SiGe technology in an Application Specific Integrated Circuit (ASIC). ASIC technology allows integration of highly optimised circuits specifically designed for a unique application. Moreover, we could reach very low-noise and wide band amplification using SiGe bipolar transistor either at room or cryogenic temperatures (Cressler in J Phys IV 04(C6):C6-101, 1994. https://doi.org/10.1051/jp4:1994616). This paper discusses the use of SiGe integrated circuits for SQUID/TES readout and gives an update of the last developments dedicated to the QUBIC telescope and to the X-IFU instrument. Both ASIC called SQmux128 and AwaXe are described showing the interest of such SiGe technology for SQUID multiplexer controls.

An array of virtual Frisch-grid CdZnTe detectors and a front-end application-specific integrated circuit for large-area position-sensitive gamma-ray cameras.

PubMed

Bolotnikov, A E; Ackley, K; Camarda, G S; Cherches, C; Cui, Y; De Geronimo, G; Fried, J; Hodges, D; Hossain, A; Lee, W; Mahler, G; Maritato, M; Petryk, M; Roy, U; Salwen, C; Vernon, E; Yang, G; James, R B

2015-07-01

We developed a robust and low-cost array of virtual Frisch-grid CdZnTe detectors coupled to a front-end readout application-specific integrated circuit (ASIC) for spectroscopy and imaging of gamma rays. The array operates as a self-reliant detector module. It is comprised of 36 close-packed 6 × 6 × 15 mm(3) detectors grouped into 3 × 3 sub-arrays of 2 × 2 detectors with the common cathodes. The front-end analog ASIC accommodates up to 36 anode and 9 cathode inputs. Several detector modules can be integrated into a single- or multi-layer unit operating as a Compton or a coded-aperture camera. We present the results from testing two fully assembled modules and readout electronics. The further enhancement of the arrays' performance and reduction of their cost are possible by using position-sensitive virtual Frisch-grid detectors, which allow for accurate corrections of the response of material non-uniformities caused by crystal defects.

Reliability Assessment of Critical Electronic Components

DTIC Science & Technology

1992-07-01

Failures FLHP - Full Horse Power FSN - Federal Stock Number I Current IC - Integrated Circuit IPB - Illustrated Parts Breakdown K - Boltzmans Constant L...Classified P - Power PC - Printed Circuit PCB - Printed Circuit Board PGA - Pin Grid Array PPM - Parts Per Million PWB - Printed Wiring Board 0...4-59 4.4.3.2.3 Circuit Brcakers ......................................................... 4-59 4.4.3.2.4 Thermal

Development of Nanomechanical Sensors for Breast Cancer Biomarkers

DTIC Science & Technology

2008-06-01

semiconductor industry in developing large scale integrated circuits at very lost cost can lead to similar breakthroughs in array sensors for biomolecules of...insulated from the serum or buffer. The entire device is mounted onto a semiconductor chip carrier, for easy integration with electronics. Figure 3...Keithley 2400 source meter. The ac modulation and the dc bias are added by a noninverting summing circuit, which is integrated with the preamplifier

Commercialisation of CMOS integrated circuit technology in multi-electrode arrays for neuroscience and cell-based biosensors.

PubMed

Graham, Anthony H D; Robbins, Jon; Bowen, Chris R; Taylor, John

2011-01-01

The adaptation of standard integrated circuit (IC) technology as a transducer in cell-based biosensors in drug discovery pharmacology, neural interface systems and electrophysiology requires electrodes that are electrochemically stable, biocompatible and affordable. Unfortunately, the ubiquitous Complementary Metal Oxide Semiconductor (CMOS) IC technology does not meet the first of these requirements. For devices intended only for research, modification of CMOS by post-processing using cleanroom facilities has been achieved. However, to enable adoption of CMOS as a basis for commercial biosensors, the economies of scale of CMOS fabrication must be maintained by using only low-cost post-processing techniques. This review highlights the methodologies employed in cell-based biosensor design where CMOS-based integrated circuits (ICs) form an integral part of the transducer system. Particular emphasis will be placed on the application of multi-electrode arrays for in vitro neuroscience applications. Identifying suitable IC packaging methods presents further significant challenges when considering specific applications. The various challenges and difficulties are reviewed and some potential solutions are presented.

Small, Optically-Driven Power Source

NASA Technical Reports Server (NTRS)

Cockrum, Richard H.; Wang, Ke-Li J.

1988-01-01

Power transmitted along fiber-optic cables. Transmitted as infrared light along fiber-optic cable, converted to electricity to supply small electronic circuit. Power source and circuit remains electrically isolated from each other for safety or reduces electromagnetic interference. Array of diodes made by standard integrated-circuit techniques and packaged for mounting at end of fiber-optic cable.

Configuration study for a 30 GHz monolithic receive array: Technical assessment

NASA Technical Reports Server (NTRS)

Nester, W. H.; Cleaveland, B.; Edward, B.; Gotkis, S.; Hesserbacker, G.; Loh, J.; Mitchell, B.

1984-01-01

The current status of monolithic microwave integrated circuits (MMICs) in phased array feeds is discussed from the point of view of cost performance, reliability, and design considerations. Transitions to MMICs, compatible antenna radiating elements and reliability considerations are addressed. Hybrid antennas, feed array antenna technology, and offset reflectors versus phased arrays are examined.

Design and Fabrication of an Implantable Cortical Semiconductor Integrated Circuit Electrode Array

DTIC Science & Technology

1990-12-01

25 Array Pads....................25 Polyimide ....................26 III. METHODOLOGY.........................27 Brain Chip Electronics...38 Ionic Permeation. .................. 38 Polyimide . ................... 38 Implantation. .................... 39 Wire Bonding...53 Pad Sensitivity ................. 53 Ionic Permeat:.on. .................. 54 Polyimide . ................... 54 Implantation

Plasmonic nanopatch array for optical integrated circuit applications.

PubMed

Qu, Shi-Wei; Nie, Zai-Ping

2013-11-08

Future plasmonic integrated circuits with the capability of extremely high-speed data processing at optical frequencies will be dominated by the efficient optical emission (excitation) from (of) plasmonic waveguides. Towards this goal, plasmonic nanoantennas, currently a hot topic in the field of plasmonics, have potential to bridge the mismatch between the wave vector of free-space photonics and that of the guided plasmonics. To manipulate light at will, plasmonic nanoantenna arrays will definitely be more efficient than isolated nanoantennas. In this article, the concepts of microwave antenna arrays are applied to efficiently convert plasmonic waves in the plasmonic waveguides into free-space optical waves or vice versa. The proposed plasmonic nanoantenna array, with nanopatch antennas and a coupled wedge plasmon waveguide, can also act as an efficient spectrometer to project different wavelengths into different directions, or as a spatial filter to absorb a specific wavelength at a specified incident angle.

Closed Loop solar array-ion thruster system with power control circuitry

NASA Technical Reports Server (NTRS)

Gruber, R. P. (Inventor)

1979-01-01

A power control circuit connected between a solar array and an ion thruster receives voltage and current signals from the solar array. The control circuit multiplies the voltage and current signals together to produce a power signal which is differentiated with respect to time. The differentiator output is detected by a zero crossing detector and, after suitable shaping, the detector output is phase compared with a clock in a phase demodulator. An integrator receives no output from the phase demodulator when the operating point is at the maximum power but is driven toward the maximum power point for non-optimum operation. A ramp generator provides minor variations in the beam current reference signal produced by the integrator in order to obtain the first derivative of power.

Carbon nanotube-based three-dimensional monolithic optoelectronic integrated system

NASA Astrophysics Data System (ADS)

Liu, Yang; Wang, Sheng; Liu, Huaping; Peng, Lian-Mao

2017-06-01

Single material-based monolithic optoelectronic integration with complementary metal oxide semiconductor-compatible signal processing circuits is one of the most pursued approaches in the post-Moore era to realize rapid data communication and functional diversification in a limited three-dimensional space. Here, we report an electrically driven carbon nanotube-based on-chip three-dimensional optoelectronic integrated circuit. We demonstrate that photovoltaic receivers, electrically driven transmitters and on-chip electronic circuits can all be fabricated using carbon nanotubes via a complementary metal oxide semiconductor-compatible low-temperature process, providing a seamless integration platform for realizing monolithic three-dimensional optoelectronic integrated circuits with diversified functionality such as the heterogeneous AND gates. These circuits can be vertically scaled down to sub-30 nm and operates in photovoltaic mode at room temperature. Parallel optical communication between functional layers, for example, bottom-layer digital circuits and top-layer memory, has been demonstrated by mapping data using a 2 × 2 transmitter/receiver array, which could be extended as the next generation energy-efficient signal processing paradigm.

Discrete Semiconductor Device Reliability

DTIC Science & Technology

1988-03-25

array or alphanumeric display. "--" indicates unknown diode count. Voc Open circuit voltage for photovoltaic modules . indicates unknown. Isc Short... circuit current for photovoltaic modules . "--" indicates unknown. Number Tested Quantity of parts under the described test or field conditions for that...information pertaining to electronic systems and parts used therein. The present scope includes integrated circuits , hybrids, discrete semiconductors

Highly integrated optical phased arrays: photonic integrated circuits for optical beam shaping and beam steering

NASA Astrophysics Data System (ADS)

Heck, Martijn J. R.

2017-01-01

Technologies for efficient generation and fast scanning of narrow free-space laser beams find major applications in three-dimensional (3D) imaging and mapping, like Lidar for remote sensing and navigation, and secure free-space optical communications. The ultimate goal for such a system is to reduce its size, weight, and power consumption, so that it can be mounted on, e.g. drones and autonomous cars. Moreover, beam scanning should ideally be done at video frame rates, something that is beyond the capabilities of current opto-mechanical systems. Photonic integrated circuit (PIC) technology holds the promise of achieving low-cost, compact, robust and energy-efficient complex optical systems. PICs integrate, for example, lasers, modulators, detectors, and filters on a single piece of semiconductor, typically silicon or indium phosphide, much like electronic integrated circuits. This technology is maturing fast, driven by high-bandwidth communications applications, and mature fabrication facilities. State-of-the-art commercial PICs integrate hundreds of elements, and the integration of thousands of elements has been shown in the laboratory. Over the last few years, there has been a considerable research effort to integrate beam steering systems on a PIC, and various beam steering demonstrators based on optical phased arrays have been realized. Arrays of up to thousands of coherent emitters, including their phase and amplitude control, have been integrated, and various applications have been explored. In this review paper, I will present an overview of the state of the art of this technology and its opportunities, illustrated by recent breakthroughs.

Heterojunction-Internal-Photoemission Infrared Detectors

NASA Technical Reports Server (NTRS)

Maserjian, Joseph

1991-01-01

New type of photodetector adds options for design of imaging devices. Heterojunction-internal-photoemission (HIP) infrared photodetectors proposed for incorporation into planar arrays in imaging devices required to function well at wavelengths from 8 to 17 micrometers and at temperatures above 65 K. Photoexcited electrons cross energy barrier at heterojunction and swept toward collection layer. Array of such detectors made by etching mesa structures. HIP layers stacked to increase quantum efficiency. Also built into integrated circuits including silicon multiplexer/readout circuits.

Phased array-fed antenna configuration study: Technology assessment

NASA Technical Reports Server (NTRS)

Croswell, W. F.; Ball, D. E.; Taylor, R. C.

1983-01-01

Spacecraft array fed reflector antenna systems were assessed for particular application to a multiple fixed spot beam/multiple scanning spot beam system. Reflector optics systems are reviewed in addition to an investigation of the feasibility of the use of monolithic microwave integrated circuit power amplifiers and phase shifters in each element of the array feed.

Performance and characterization of new micromachined high-frequency linear arrays.

PubMed

Lukacs, Marc; Yin, Jianhua; Pang, Guofeng; Garcia, Richard C; Cherin, Emmanuel; Williams, Ross; Mehi, Jim; Foster, F Stuart

2006-10-01

A new approach for fabricating high frequency (> 20 MHz) linear array transducers, based on laser micromachining, has been developed. A 30 MHz, 64-element, 74-microm pitch, linear array design is presented. The performance of the device is demonstrated by comparing electrical and acoustic measurements with analytical, equivalent circuit, and finite-element analysis (FEA) simulations. All FEA results for array performance have been generated using one global set of material parameters. Each fabricated array has been integrated onto a flex circuit for ease of handling, and the flex has been integrated onto a custom printed circuit board test card for ease of testing. For a fully assembled array, with an acoustic lens, the center frequency was 28.7 MHz with a one-way -3 dB and -6 dB bandwidth of 59% and 83%, respectively, and a -20 dB pulse width of -99 ns. The per-element peak acoustic power, for a +/- 30 V single cycle pulse, measured at the 10 mm focal length of the lens was 590 kPa with a -6 dB directivity span of about 30 degrees. The worst-case total cross talk of the combined array and flex assembly is for nearest neighboring elements and was measured to have an average level -40 dB across the -6 dB bandwidth of the device. Any significant deviation from simulation can be explained through limitations in apparatus calibration and in device packaging.

Development of a unit cell for a Ge:Ga detector array

NASA Technical Reports Server (NTRS)

1988-01-01

Two modules of gallium-doped germanium (Ge:Ga) infrared detectors with integrated multiplexing readouts and supporting drive electronics were designed and tested. This development investigated the feasibility of producing two-dimensional Ge:Ga arrays by stacking linear modules in a housing capable of providing uniaxial stress for enhanced long-wavelength response. Each module includes 8 detectors (1x1x2 mm) mounted to a sapphire board. The element spacing is 12 microns. The back faces of the detector elements are beveled with an 18 deg angle, which was proved to significantly enhance optical absorption. Each module includes a different silicon metal-oxide semiconductor field effect transistor (MOSFET) readout. The first circuit was built from discrete MOSFET components; the second incorporated devices taken from low-temperature integrated circuit multiplexers. The latter circuit exhibited much lower stray capacitance and improved stability. Using these switched-FET circuits, it was demonstrated that burst readout, with multiplexer active only during the readout period, could successfully be implemented at approximately 3.5 K.

All optical programmable logic array (PLA)

NASA Astrophysics Data System (ADS)

Hiluf, Dawit

2018-03-01

A programmable logic array (PLA) is an integrated circuit (IC) logic device that can be reconfigured to implement various kinds of combinational logic circuits. The device has a number of AND and OR gates which are linked together to give output or further combined with more gates or logic circuits. This work presents the realization of PLAs via the physics of a three level system interacting with light. A programmable logic array is designed such that a number of different logical functions can be combined as a sum-of-product or product-of-sum form. We present an all optical PLAs with the aid of laser light and observables of quantum systems, where encoded information can be considered as memory chip. The dynamics of the physical system is investigated using Lie algebra approach.

Commercialisation of CMOS Integrated Circuit Technology in Multi-Electrode Arrays for Neuroscience and Cell-Based Biosensors

PubMed Central

Graham, Anthony H. D.; Robbins, Jon; Bowen, Chris R.; Taylor, John

2011-01-01

The adaptation of standard integrated circuit (IC) technology as a transducer in cell-based biosensors in drug discovery pharmacology, neural interface systems and electrophysiology requires electrodes that are electrochemically stable, biocompatible and affordable. Unfortunately, the ubiquitous Complementary Metal Oxide Semiconductor (CMOS) IC technology does not meet the first of these requirements. For devices intended only for research, modification of CMOS by post-processing using cleanroom facilities has been achieved. However, to enable adoption of CMOS as a basis for commercial biosensors, the economies of scale of CMOS fabrication must be maintained by using only low-cost post-processing techniques. This review highlights the methodologies employed in cell-based biosensor design where CMOS-based integrated circuits (ICs) form an integral part of the transducer system. Particular emphasis will be placed on the application of multi-electrode arrays for in vitro neuroscience applications. Identifying suitable IC packaging methods presents further significant challenges when considering specific applications. The various challenges and difficulties are reviewed and some potential solutions are presented. PMID:22163884

Microbatteries for Combinatorial Studies of Conventional Lithium-Ion Batteries

NASA Technical Reports Server (NTRS)

West, William; Whitacre, Jay; Bugga, Ratnakumar

2003-01-01

Integrated arrays of microscopic solid-state batteries have been demonstrated in a continuing effort to develop microscopic sources of power and of voltage reference circuits to be incorporated into low-power integrated circuits. Perhaps even more importantly, arrays of microscopic batteries can be fabricated and tested in combinatorial experiments directed toward optimization and discovery of battery materials. The value of the combinatorial approach to optimization and discovery has been proven in the optoelectronic, pharmaceutical, and bioengineering industries. Depending on the specific application, the combinatorial approach can involve the investigation of hundreds or even thousands of different combinations; hence, it is time-consuming and expensive to attempt to implement the combinatorial approach by building and testing full-size, discrete cells and batteries. The conception of microbattery arrays makes it practical to bring the advantages of the combinatorial approach to the development of batteries.

Rapid evolution of analog circuits configured on a field programmable transistor array

NASA Technical Reports Server (NTRS)

Stoica, A.; Ferguson, M. I.; Zebulum, R. S.; Keymeulen, D.; Duong, V.; Daud, T.

2002-01-01

The purpose of this paper is to illustrate evolution of analog circuits on a stand-alone board-level evolvable system (SABLES). SABLES is part of an effort to achieve integrated evolvable systems. SABLES provides autonomous, fast (tens to hundreds of seconds), on-chip circuit evolution involving about 100,000 circuit evaluations. Its main components are a JPL Field Programmable Transistor Array (FPTA) chip used as transistor-level reconfigurable hardware, and a TI DSP that implements the evolutionary algorithm controlling the FPTA reconfiguration. The paper details an example of evolution on SABLES and points out to certain transient and memory effects that affect the stability of solutions obtained reusing the same piece of hardware for rapid testing of individuals during evolution.

Nonvolatile Array Of Synapses For Neural Network

NASA Technical Reports Server (NTRS)

Tawel, Raoul

1993-01-01

Elements of array programmed with help of ultraviolet light. A 32 x 32 very-large-scale integrated-circuit array of electronic synapses serves as building-block chip for analog neural-network computer. Synaptic weights stored in nonvolatile manner. Makes information content of array invulnerable to loss of power, and, by eliminating need for circuitry to refresh volatile synaptic memory, makes architecture simpler and more compact.

Implementation of a noise reduction circuit for spaceflight IR spectrometers

NASA Technical Reports Server (NTRS)

Ramirez, L.; Hickok, R.; Pain, B.; Staller, C.

1992-01-01

The paper discusses the implementation and analysis of a correlated triple sampling circuit using analog subtractor/integrators. The software and test setup for noise measurements are also described. The correlation circuitry is part of the signal chain for a 256-element InSb line array used in the Visible and Infrared Mapping Spectrometer. Using a focal-plane array (FPA) simulator, system noise measurements of 0.7 DN are obtained. A test setup for FPA/SPE (signal processing electronics) characterization along with noise measurements is demonstrated.

Two-Dimensional Planar Lightwave Circuit Integrated Spatial Filter Array and Method of Use Thereof

NASA Technical Reports Server (NTRS)

Dimov, Fedor (Inventor); Ai, Jun (Inventor)

2015-01-01

A large coherent two-dimensional (2D) spatial filter array (SFA), 30 by 30 or larger, is produced by coupling a 2D planar lightwave circuit (PLC) array with a pair of lenslet arrays at the input and output side. The 2D PLC array is produced by stacking a plurality of chips, each chip with a plural number of straight PLC waveguides. A pupil array is coated onto the focal plane of the lenslet array. The PLC waveguides are produced by deposition of a plural number of silica layers on the silicon wafer, followed by photolithography and reactive ion etching (RIE) processes. A plural number of mode filters are included in the silica-on-silicon waveguide such that the PLC waveguide is transparent to the fundamental mode but higher order modes are attenuated by 40 dB or more.

Operational compatibility of 30-centimeter-diameter ion thruster with integrally regulated solar array power source

NASA Technical Reports Server (NTRS)

Gooder, S. T.

1977-01-01

System tests were performed in which Integrally Regulated Solar Arrays (IRSA's) were used to directly power the beam and accelerator loads of a 30-cm-diameter, electron bombardment, mercury ion thruster. The remaining thruster loads were supplied from conventional power-processing circuits. This combination of IRSA's and conventional circuits formed a hybrid power processor. Thruster performance was evaluated at 3/4- and 1-A beam currents with both the IRSA-hybrid and conventional power processors and was found to be identical for both systems. Power processing is significantly more efficient with the hybrid system. System dynamics and IRSA response to thruster arcs are also examined.

Monolithic microwave integrated circuit devices for active array antennas

NASA Technical Reports Server (NTRS)

Mittra, R.

1984-01-01

Two different aspects of active antenna array design were investigated. The transition between monolithic microwave integrated circuits and rectangular waveguides was studied along with crosstalk in multiconductor transmission lines. The boundary value problem associated with a discontinuity in a microstrip line is formulated. This entailed, as a first step, the derivation of the propagating as well as evanescent modes of a microstrip line. The solution is derived to a simple discontinuity problem: change in width of the center strip. As for the multiconductor transmission line problem. A computer algorithm was developed for computing the crosstalk noise from the signal to the sense lines. The computation is based on the assumption that these lines are terminated in passive loads.

Temperature-Adaptive Circuits on Reconfigurable Analog Arrays

NASA Technical Reports Server (NTRS)

Stoica, Adrian; Zebulum, Ricardo S.; Keymeulen, Didier; Ramesham, Rajeshuni; Neff, Joseph; Katkoori, Srinivas

2006-01-01

Demonstration of a self-reconfigurable Integrated Circuit (IC) that would operate under extreme temperature (-180 C and 120 C) and radiation (300krad), without the protection of thermal controls and radiation shields. Self-Reconfigurable Electronics platform: a) Evolutionary Processor (EP) to run reconfiguration mechanism; b) Reconfigurable chip (FPGA, FPAA, etc).

High-performance integrated pick-up circuit for SPAD arrays in time-correlated single photon counting

NASA Astrophysics Data System (ADS)

Acconcia, Giulia; Cominelli, Alessandro; Peronio, Pietro; Rech, Ivan; Ghioni, Massimo

2017-05-01

The analysis of optical signals by means of Single Photon Avalanche Diodes (SPADs) has been subject to a widespread interest in recent years. The development of multichannel high-performance Time Correlated Single Photon Counting (TCSPC) acquisition systems has undergone a fast trend. Concerning the detector performance, best in class results have been obtained resorting to custom technologies leading also to a strong dependence of the detector timing jitter from the threshold used to determine the onset of the photogenerated current flow. In this scenario, the avalanche current pick-up circuit plays a key role in determining the timing performance of the TCSPC acquisition system, especially with a large array of SPAD detectors because of electrical crosstalk issues. We developed a new current pick-up circuit based on a transimpedance amplifier structure able to extract the timing information from a 50-μm-diameter custom technology SPAD with a state-of-art timing jitter as low as 32ps and suitable to be exploited with SPAD arrays. In this paper we discuss the key features of this structure and we present a new version of the pick-up circuit that also provides quenching capabilities in order to minimize the number of interconnections required, an aspect that becomes more and more crucial in densely integrated systems.

Monolithic Microwave Integrated Circuit (MMIC) Phased Array Demonstrated With ACTS

NASA Technical Reports Server (NTRS)

1996-01-01

Monolithic Microwave Integrated Circuit (MMIC) arrays developed by the NASA Lewis Research Center and the Air Force Rome Laboratory were demonstrated in aeronautical terminals and in mobile or fixed Earth terminals linked with NASA's Advanced Communications Technology Satellite (ACTS). Four K/Ka-band experimental arrays were demonstrated between May 1994 and May 1995. Each array had GaAs MMIC devices at each radiating element for electronic beam steering and distributed power amplification. The 30-GHz transmit array used in uplinks to ACTS was developed by Lewis and Texas Instruments. The three 20-GHz receive arrays used in downlinks from ACTS were developed in cooperation with the Air Force Rome Laboratory, taking advantage of existing Air Force integrated-circuit, active-phased-array development contracts with the Boeing Company and Lockheed Martin Corporation. Four demonstrations, each related to an application of high interest to both commercial and Department of Defense organizations, were conducted. The location, type of link, and the data rate achieved for each of the applications is shown. In one demonstration-- an aeronautical terminal experiment called AERO-X--a duplex voice link between an aeronautical terminal on the Lewis Learjet and ACTS was achieved. Two others demonstrated duplex voice links (and in one case, interactive video links as well) between ACTS and an Army high-mobility, multipurpose wheeled vehicle (HMMWV, or "humvee"). In the fourth demonstration, the array was on a fixed mount and was electronically steered toward ACTS. Lewis served as project manager for all demonstrations and as overall system integrator. Lewis engineers developed the array system including a controller for open-loop tracking of ACTS during flight and HMMWV motion, as well as a laptop data display and recording system used in all demonstrations. The Jet Propulsion Laboratory supported the AERO-X program, providing elements of the ACTS Mobile Terminal. The successful performance of experimental, proof-of-concept MMIC K/Ka-band arrays developed with U.S. industry in field demonstrations with ACTS indicates that high density MMIC integration at 20 and 30 GHz is indeed feasible. The successful development and demonstration of the MMIC array systems was possible only because of significant intergovernmental and Government/industry cooperation and the high level of teamwork within Lewis. The results provide a strong incentive for continuing the focused development of MMIC-array technology for satellite communications applications, with emphasis on packaging and cost issues, and for continuing the planning and conducting of other appropriate demonstrations or experiments of phased-array technology with ACTS. Given the present pressures on reducing funding for research and development in Government and industry, the extent to which this can be continued in a cooperative manner will determine whether MMIC array technology will make the transition from the proof-of-concept level to the operational system level.

Reprogrammable read only variable threshold transistor memory with isolated addressing buffer

DOEpatents

Lodi, Robert J.

1976-01-01

A monolithic integrated circuit, fully decoded memory comprises a rectangular array of variable threshold field effect transistors organized into a plurality of multi-bit words. Binary address inputs to the memory are decoded by a field effect transistor decoder into a plurality of word selection lines each of which activates an address buffer circuit. Each address buffer circuit, in turn, drives a word line of the memory array. In accordance with the word line selected by the decoder the activated buffer circuit directs reading or writing voltages to the transistors comprising the memory words. All of the buffer circuits additionally are connected to a common terminal for clearing all of the memory transistors to a predetermined state by the application to the common terminal of a large magnitude voltage of a predetermined polarity. The address decoder, the buffer and the memory array, as well as control and input/output control and buffer field effect transistor circuits, are fabricated on a common substrate with means provided to isolate the substrate of the address buffer transistors from the remainder of the substrate so that the bulk clearing function of simultaneously placing all of the memory transistors into a predetermined state can be performed.

A scalable neural chip with synaptic electronics using CMOS integrated memristors.

PubMed

Cruz-Albrecht, Jose M; Derosier, Timothy; Srinivasa, Narayan

2013-09-27

The design and simulation of a scalable neural chip with synaptic electronics using nanoscale memristors fully integrated with complementary metal-oxide-semiconductor (CMOS) is presented. The circuit consists of integrate-and-fire neurons and synapses with spike-timing dependent plasticity (STDP). The synaptic conductance values can be stored in memristors with eight levels, and the topology of connections between neurons is reconfigurable. The circuit has been designed using a 90 nm CMOS process with via connections to on-chip post-processed memristor arrays. The design has about 16 million CMOS transistors and 73 728 integrated memristors. We provide circuit level simulations of the entire chip performing neuronal and synaptic computations that result in biologically realistic functional behavior.

Phased Arrays 1985 Symposium - Proceedings

DTIC Science & Technology

1985-08-01

have served the logic industry well, and appropriate versions can do the same for micruwdve drid millimeter * wave technology, An aspect of phased...continuing revolutions of the logic industry and the microwave monolithic integrated circuit community are bringing relevant technology closer to the array...monolithic phased array antennas, and discuss their relative advantages and disadvantages . Considerations such as bandwidth, maxianiru scan range, feed

Betavoltaic effect in titanium dioxide nanotube arrays under build-in potential difference

NASA Astrophysics Data System (ADS)

Zhang, Qiang; Chen, Ranbin; San, Haisheng; Liu, Guohua; Wang, Kaiying

2015-05-01

We report the fabrication of sandwich-type metal/TiO2 nanotube (TNT) array/metal structures as well as their betavoltaic effects under build-in voltage through contact potential difference. The sandwiched structure is integrated by immobilized TNT arrays on Ti foil with radioisotope 63Ni planar source on Ni substrate (Ni-63Ni/TNT array/Ti). Under irradiation of the 63Ni source with activity of 8 mCi, the structure (TNT diameter ∼ 130 nm, length ∼ 11 μm) presents optimum energy conversion efficiency of 7.30% with open-circuit voltage of 1.54 V and short-circuit current of 12.43 nA. The TNT arrays exhibit a highly potential for developing betavoltaic batteries due to its wide band gap and nanotube array configuration. The TNT-betavoltaic concept offers a facile solution for micro/nano electronics with high efficiency and long life-time instead of conventional planar junction-type batteries.

Magnetophoretic circuits for digital control of single particles and cells

NASA Astrophysics Data System (ADS)

Lim, Byeonghwa; Reddy, Venu; Hu, Xinghao; Kim, Kunwoo; Jadhav, Mital; Abedini-Nassab, Roozbeh; Noh, Young-Woock; Lim, Yong Taik; Yellen, Benjamin B.; Kim, Cheolgi

2014-05-01

The ability to manipulate small fluid droplets, colloidal particles and single cells with the precision and parallelization of modern-day computer hardware has profound applications for biochemical detection, gene sequencing, chemical synthesis and highly parallel analysis of single cells. Drawing inspiration from general circuit theory and magnetic bubble technology, here we demonstrate a class of integrated circuits for executing sequential and parallel, timed operations on an ensemble of single particles and cells. The integrated circuits are constructed from lithographically defined, overlaid patterns of magnetic film and current lines. The magnetic patterns passively control particles similar to electrical conductors, diodes and capacitors. The current lines actively switch particles between different tracks similar to gated electrical transistors. When combined into arrays and driven by a rotating magnetic field clock, these integrated circuits have general multiplexing properties and enable the precise control of magnetizable objects.

Multi-format all-optical processing based on a large-scale, hybridly integrated photonic circuit.

PubMed

Bougioukos, M; Kouloumentas, Ch; Spyropoulou, M; Giannoulis, G; Kalavrouziotis, D; Maziotis, A; Bakopoulos, P; Harmon, R; Rogers, D; Harrison, J; Poustie, A; Maxwell, G; Avramopoulos, H

2011-06-06

We investigate through numerical studies and experiments the performance of a large scale, silica-on-silicon photonic integrated circuit for multi-format regeneration and wavelength-conversion. The circuit encompasses a monolithically integrated array of four SOAs inside two parallel Mach-Zehnder structures, four delay interferometers and a large number of silica waveguides and couplers. Exploiting phase-incoherent techniques, the circuit is capable of processing OOK signals at variable bit rates, DPSK signals at 22 or 44 Gb/s and DQPSK signals at 44 Gbaud. Simulation studies reveal the wavelength-conversion potential of the circuit with enhanced regenerative capabilities for OOK and DPSK modulation formats and acceptable quality degradation for DQPSK format. Regeneration of 22 Gb/s OOK signals with amplified spontaneous emission (ASE) noise and DPSK data signals degraded with amplitude, phase and ASE noise is experimentally validated demonstrating a power penalty improvement up to 1.5 dB.

Flexible circuits with integrated switches for robotic shape sensing

NASA Astrophysics Data System (ADS)

Harnett, C. K.

2016-05-01

Digital switches are commonly used for detecting surface contact and limb-position limits in robotics. The typical momentary-contact digital switch is a mechanical device made from metal springs, designed to connect with a rigid printed circuit board (PCB). However, flexible printed circuits are taking over from the rigid PCB in robotics because the circuits can bend while carrying signals and power through moving joints. This project is motivated by a previous work where an array of surface-mount momentary contact switches on a flexible circuit acted as an all-digital shape sensor compatible with the power resources of energy harvesting systems. Without a rigid segment, the smallest commercially-available surface-mount switches would detach from the flexible circuit after several bending cycles, sometimes violently. This report describes a low-cost, conductive fiber based method to integrate electromechanical switches into flexible circuits and other soft, bendable materials. Because the switches are digital (on/off), they differ from commercially-available continuous-valued bend/flex sensors. No amplification or analog-to-digital conversion is needed to read the signal, but the tradeoff is that the digital switches only give a threshold curvature value. Boundary conditions on the edges of the flexible circuit are key to setting the threshold curvature value for switching. This presentation will discuss threshold-setting, size scaling of the design, automation for inserting a digital switch into the flexible circuit fabrication process, and methods for reconstructing a shape from an array of digital switch states.

An application specific integrated circuit based multi-anode microchannel array readout system

NASA Technical Reports Server (NTRS)

Smeins, Larry G.; Stechman, John M.; Cole, Edward H.

1991-01-01

Size reduction of two new multi-anode microchannel array (MAMA) readout systems is described. The systems are based on two analog and one digital application specific integrated circuits (ASICs). The new readout systems reduce volume over previous discrete designs by 80 percent while improving electrical performance on virtually every significant parameter. Emphasis is made on the packaging used to achieve the volume reduction. Surface mount technology (SMT) is combined with modular construction for the analog portion of the readout. SMT reliability concerns and the board area impact of MIL SPEC SMT components is addressed. Package selection for the analog ASIC is discussed. Future sytems will require even denser packaging and the volume reduction progression is shown.

Split-cross-bridge resistor for testing for proper fabrication of integrated circuits

NASA Technical Reports Server (NTRS)

Buehler, M. G. (Inventor)

1985-01-01

An electrical testing structure and method is described whereby a test structure is fabricated on a large scale integrated circuit wafer along with the circuit components and has a van der Pauw cross resistor in conjunction with a bridge resistor and a split bridge resistor, the latter having two channels each a line width wide, corresponding to the line width of the wafer circuit components, and with the two channels separated by a space equal to the line spacing of the wafer circuit components. The testing structure has associated voltage and current contact pads arranged in a two by four array for conveniently passing currents through the test structure and measuring voltages at appropriate points to calculate the sheet resistance, line width, line spacing, and line pitch of the circuit components on the wafer electrically.

Development of an ultra-high temperature infrared scene projector at Santa Barbara Infrared Inc.

NASA Astrophysics Data System (ADS)

Franks, Greg; Laveigne, Joe; Danielson, Tom; McHugh, Steve; Lannon, John; Goodwin, Scott

2015-05-01

The rapid development of very-large format infrared detector arrays has challenged the IR scene projector community to develop correspondingly larger-format infrared emitter arrays to support the testing needs of systems incorporating these detectors. As with most integrated circuits, fabrication yields for the read-in integrated circuit (RIIC) that drives the emitter pixel array are expected to drop dramatically with increasing size, making monolithic RIICs larger than the current 1024x1024 format impractical and unaffordable. Additionally, many scene projector users require much higher simulated temperatures than current technology can generate to fully evaluate the performance of their systems and associated processing algorithms. Under the Ultra High Temperature (UHT) development program, Santa Barbara Infrared Inc. (SBIR) is developing a new infrared scene projector architecture capable of producing both very large format (>1024x1024) resistive emitter arrays and improved emitter pixel technology capable of simulating very high apparent temperatures. During an earlier phase of the program, SBIR demonstrated materials with MWIR apparent temperatures in excess of 1000K. New emitter materials have subsequently been selected to produce pixels that achieve even higher apparent temperatures. Test results from pixels fabricated using the new material set will be presented and discussed. Also in development under the same UHT program is a 'scalable' RIIC that will be used to drive the high temperature pixels. This RIIC will utilize through-silicon vias (TSVs) and quilt packaging (QP) technologies to allow seamless tiling of multiple chips to fabricate very large arrays, and thus overcome the inherent yield limitations of very-large-scale integrated circuits. Current status of the RIIC development effort will also be presented.

Innovative Magnetic-Field Array Probe for TRUST Integrated Circuits

DTIC Science & Technology

2017-03-01

real-time an IC device. This non-invasive solution is cost effective, with a small form factor. Keywords: Electromagnetic radiation; Near-Field...solicitation was to design, develop and fabricate a low cost electromagnetic probe array for ICs counterfeit. The probe array should operate in the near...Our overall effort was focus on modeling, designing, fabricating, and utilizing novel electromagnetic probes for the analysis, characterization

Testbed Experiment for SPIDER: A Photonic Integrated Circuit-based Interferometric imaging system

NASA Astrophysics Data System (ADS)

Badham, K.; Duncan, A.; Kendrick, R. L.; Wuchenich, D.; Ogden, C.; Chriqui, G.; Thurman, S. T.; Su, T.; Lai, W.; Chun, J.; Li, S.; Liu, G.; Yoo, S. J. B.

The Lockheed Martin Advanced Technology Center (LM ATC) and the University of California at Davis (UC Davis) are developing an electro-optical (EO) imaging sensor called SPIDER (Segmented Planar Imaging Detector for Electro-optical Reconnaissance) that seeks to provide a 10x to 100x size, weight, and power (SWaP) reduction alternative to the traditional bulky optical telescope and focal-plane detector array. The substantial reductions in SWaP would reduce cost and/or provide higher resolution by enabling a larger-aperture imager in a constrained volume. Our SPIDER imager replaces the traditional optical telescope and digital focal plane detector array with a densely packed interferometer array based on emerging photonic integrated circuit (PIC) technologies that samples the object being imaged in the Fourier domain (i.e., spatial frequency domain), and then reconstructs an image. Our approach replaces the large optics and structures required by a conventional telescope with PICs that are accommodated by standard lithographic fabrication techniques (e.g., complementary metal-oxide-semiconductor (CMOS) fabrication). The standard EO payload integration and test process that involves precision alignment and test of optical components to form a diffraction limited telescope is, therefore, replaced by in-process integration and test as part of the PIC fabrication, which substantially reduces associated schedule and cost. In this paper we describe the photonic integrated circuit design and the testbed used to create the first images of extended scenes. We summarize the image reconstruction steps and present the final images. We also describe our next generation PIC design for a larger (16x area, 4x field of view) image.

Metallization failures

NASA Technical Reports Server (NTRS)

Beatty, R.

1971-01-01

Metallization-related failure mechanisms were shown to be a major cause of integrated circuit failures under accelerated stress conditions, as well as in actual use under field operation. The integrated circuit industry is aware of the problem and is attempting to solve it in one of two ways: (1) better understanding of the aluminum system, which is the most widely used metallization material for silicon integrated circuits both as a single level and multilevel metallization, or (2) evaluating alternative metal systems. Aluminum metallization offers many advantages, but also has limitations particularly at elevated temperatures and high current densities. As an alternative, multilayer systems of the general form, silicon device-metal-inorganic insulator-metal, are being considered to produce large scale integrated arrays. The merits and restrictions of metallization systems in current usage and systems under development are defined.

Active C4 Electrodes for Local Field Potential Recording Applications

PubMed Central

Wang, Lu; Freedman, David; Sahin, Mesut; Ünlü, M. Selim; Knepper, Ronald

2016-01-01

Extracellular neural recording, with multi-electrode arrays (MEAs), is a powerful method used to study neural function at the network level. However, in a high density array, it can be costly and time consuming to integrate the active circuit with the expensive electrodes. In this paper, we present a 4 mm × 4 mm neural recording integrated circuit (IC) chip, utilizing IBM C4 bumps as recording electrodes, which enable a seamless active chip and electrode integration. The IC chip was designed and fabricated in a 0.13 μm BiCMOS process for both in vitro and in vivo applications. It has an input-referred noise of 4.6 μVrms for the bandwidth of 10 Hz to 10 kHz and a power dissipation of 11.25 mW at 2.5 V, or 43.9 μW per input channel. This prototype is scalable for implementing larger number and higher density electrode arrays. To validate the functionality of the chip, electrical testing results and acute in vivo recordings from a rat barrel cortex are presented. PMID:26861324

An IBM PC-based math model for space station solar array simulation

NASA Technical Reports Server (NTRS)

Emanuel, E. M.

1986-01-01

This report discusses and documents the design, development, and verification of a microcomputer-based solar cell math model for simulating the Space Station's solar array Initial Operational Capability (IOC) reference configuration. The array model is developed utilizing a linear solar cell dc math model requiring only five input parameters: short circuit current, open circuit voltage, maximum power voltage, maximum power current, and orbit inclination. The accuracy of this model is investigated using actual solar array on orbit electrical data derived from the Solar Array Flight Experiment/Dynamic Augmentation Experiment (SAFE/DAE), conducted during the STS-41D mission. This simulator provides real-time simulated performance data during the steady state portion of the Space Station orbit (i.e., array fully exposed to sunlight). Eclipse to sunlight transients and shadowing effects are not included in the analysis, but are discussed briefly. Integrating the Solar Array Simulator (SAS) into the Power Management and Distribution (PMAD) subsystem is also discussed.

Vibration energy harvester with sustainable power based on a single-crystal piezoelectric cantilever array.

PubMed

Kim, Moonkeun; Lee, Sang-Kyun; Ham, Yong-Hyun; Yang, Yil Suk; Kwon, Jong-Kee; Kwon, Kwang-Ho

2012-08-01

We designed and fabricated a bimorph cantilever array for sustainable power with an integrated Cu proof mass to obtain additional power and current. We fabricated a cantilever system using single-crystal piezoelectric material and compared the calculations for single and arrayed cantilevers to those obtained experimentally. The vibration energy harvester had resonant frequencies of 60.4 and 63.2 Hz for short and open circuits, respectively. The damping ratio and quality factor of the cantilever device were 0.012 and 41.66, respectively. The resonant frequency at maximum average power was 60.8 Hz. The current and highest average power of the harvester array were found to be 0.728 mA and 1.61 mW, respectively. The sustainable maximum power was obtained after slightly shifting the short-circuit frequency. In order to improve the current and power using an array of cantilevers, we also performed energy conversion experiments.

CMOS Active-Pixel Image Sensor With Simple Floating Gates

NASA Technical Reports Server (NTRS)

Fossum, Eric R.; Nakamura, Junichi; Kemeny, Sabrina E.

1996-01-01

Experimental complementary metal-oxide/semiconductor (CMOS) active-pixel image sensor integrated circuit features simple floating-gate structure, with metal-oxide/semiconductor field-effect transistor (MOSFET) as active circuit element in each pixel. Provides flexibility of readout modes, no kTC noise, and relatively simple structure suitable for high-density arrays. Features desirable for "smart sensor" applications.

Solid State Technology Branch of NASA Lewis Research Center

NASA Technical Reports Server (NTRS)

1991-01-01

Reprints of one year's production of research publications (June 1990 to June 1991) are presented. These are organized into three major sections: microwave circuits, both hybrid and monolithic microwave integrated circuits (MMICs); materials and device work; and superconductivity. The included papers also cover more specific topics involving waveguides, phase array antennas, dielectrics, and high temperature superconductors.

Contact CMOS imaging of gaseous oxygen sensor array

PubMed Central

Daivasagaya, Daisy S.; Yao, Lei; Yi Yung, Ka; Hajj-Hassan, Mohamad; Cheung, Maurice C.; Chodavarapu, Vamsy P.; Bright, Frank V.

2014-01-01

We describe a compact luminescent gaseous oxygen (O2) sensor microsystem based on the direct integration of sensor elements with a polymeric optical filter and placed on a low power complementary metal-oxide semiconductor (CMOS) imager integrated circuit (IC). The sensor operates on the measurement of excited-state emission intensity of O2-sensitive luminophore molecules tris(4,7-diphenyl-1,10-phenanthroline) ruthenium(II) ([Ru(dpp)3]2+) encapsulated within sol–gel derived xerogel thin films. The polymeric optical filter is made with polydimethylsiloxane (PDMS) that is mixed with a dye (Sudan-II). The PDMS membrane surface is molded to incorporate arrays of trapezoidal microstructures that serve to focus the optical sensor signals on to the imager pixels. The molded PDMS membrane is then attached with the PDMS color filter. The xerogel sensor arrays are contact printed on top of the PDMS trapezoidal lens-like microstructures. The CMOS imager uses a 32 × 32 (1024 elements) array of active pixel sensors and each pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. Correlated double sampling circuit, pixel address, digital control and signal integration circuits are also implemented on-chip. The CMOS imager data is read out as a serial coded signal. The CMOS imager consumes a static power of 320 µW and an average dynamic power of 625 µW when operating at 100 Hz sampling frequency and 1.8 V DC. This CMOS sensor system provides a useful platform for the development of miniaturized optical chemical gas sensors. PMID:24493909

Contact CMOS imaging of gaseous oxygen sensor array.

PubMed

Daivasagaya, Daisy S; Yao, Lei; Yi Yung, Ka; Hajj-Hassan, Mohamad; Cheung, Maurice C; Chodavarapu, Vamsy P; Bright, Frank V

2011-10-01

We describe a compact luminescent gaseous oxygen (O 2 ) sensor microsystem based on the direct integration of sensor elements with a polymeric optical filter and placed on a low power complementary metal-oxide semiconductor (CMOS) imager integrated circuit (IC). The sensor operates on the measurement of excited-state emission intensity of O 2 -sensitive luminophore molecules tris(4,7-diphenyl-1,10-phenanthroline) ruthenium(II) ([Ru(dpp) 3 ] 2+ ) encapsulated within sol-gel derived xerogel thin films. The polymeric optical filter is made with polydimethylsiloxane (PDMS) that is mixed with a dye (Sudan-II). The PDMS membrane surface is molded to incorporate arrays of trapezoidal microstructures that serve to focus the optical sensor signals on to the imager pixels. The molded PDMS membrane is then attached with the PDMS color filter. The xerogel sensor arrays are contact printed on top of the PDMS trapezoidal lens-like microstructures. The CMOS imager uses a 32 × 32 (1024 elements) array of active pixel sensors and each pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. Correlated double sampling circuit, pixel address, digital control and signal integration circuits are also implemented on-chip. The CMOS imager data is read out as a serial coded signal. The CMOS imager consumes a static power of 320 µW and an average dynamic power of 625 µW when operating at 100 Hz sampling frequency and 1.8 V DC. This CMOS sensor system provides a useful platform for the development of miniaturized optical chemical gas sensors.

Propagating gene expression fronts in a one-dimensional coupled system of artificial cells

NASA Astrophysics Data System (ADS)

Tayar, Alexandra M.; Karzbrun, Eyal; Noireaux, Vincent; Bar-Ziv, Roy H.

2015-12-01

Living systems employ front propagation and spatiotemporal patterns encoded in biochemical reactions for communication, self-organization and computation. Emulating such dynamics in minimal systems is important for understanding physical principles in living cells and in vitro. Here, we report a one-dimensional array of DNA compartments in a silicon chip as a coupled system of artificial cells, offering the means to implement reaction-diffusion dynamics by integrated genetic circuits and chip geometry. Using a bistable circuit we programmed a front of protein synthesis propagating in the array as a cascade of signal amplification and short-range diffusion. The front velocity is maximal at a saddle-node bifurcation from a bistable regime with travelling fronts to a monostable regime that is spatially homogeneous. Near the bifurcation the system exhibits large variability between compartments, providing a possible mechanism for population diversity. This demonstrates that on-chip integrated gene circuits are dynamical systems driving spatiotemporal patterns, cellular variability and symmetry breaking.

Hard and flexible optical printed circuit board

NASA Astrophysics Data System (ADS)

Lee, El-Hang; Lee, Hyun Sik; Lee, S. G.; O, B. H.; Park, S. G.; Kim, K. H.

2007-02-01

We report on the design and fabrication of hard and flexible optical printed circuit boards (O-PCBs). The objective is to realize generic and application-specific O-PCBs, either in hard form or flexible form, that are compact, light-weight, low-energy, high-speed, intelligent, and environmentally friendly, for low-cost and high-volume universal applications. The O-PCBs consist of 2-dimensional planar arrays of micro/nano-scale optical wires, circuits and devices that are interconnected and integrated to perform the functions of sensing, storing, transporting, processing, switching, routing and distributing optical signals on flat modular boards. For fabrication, the polymer and organic optical wires and waveguides are first fabricated on a board and are used to interconnect and integrate micro/nano-scale photonic devices. The micro/nano-optical functional devices include lasers, detectors, switches, sensors, directional couplers, multi-mode interference devices, ring-resonators, photonic crystal devices, plasmonic devices, and quantum devices. For flexible boards, the optical waveguide arrays are fabricated on flexible poly-ethylen terephthalate (PET) substrates by UV embossing. Electrical layer carrying VCSEL and PD array is laminated with the optical layer carrying waveguide arrays. Both hard and flexible electrical lines are replaced with high speed optical interconnection between chips over four waveguide channels up to 10Gbps on each. We discuss uses of hard or flexible O-PCBs for telecommunication systems, computer systems, transportation systems, space/avionic systems, and bio-sensor systems.

Method of acquiring an image from an optical structure having pixels with dedicated readout circuits

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Mendis, Sunetra (Inventor); Kemeny, Sabrina E. (Inventor)

2006-01-01

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node.

Space Power Amplification with Active Linearly Tapered Slot Antenna Array

NASA Technical Reports Server (NTRS)

Simons, Rainee N.; Lee, Richard Q.

1993-01-01

A space power amplifier composed of active linearly tapered slot antennas (LTSA's) has been demonstrated and shown to have a gain of 30 dB at 20 GHz. In each of the antenna elements, a GaAs monolithic microwave integrated circuit (MMIC) three-stage power amplifier is integrated with two LTSA's. The LTSA and the MMIC power amplifier has a gain of 11 dB and power added efficiency of 14 percent respectively. The design is suitable for constructing a large array using monolithic integration techniques.

Direct Fabrication of a-Si:H Thin Film Transistor Arrays on Plastic and Metal Foils for Flexible Displays

DTIC Science & Technology

2008-12-01

TFTs ) arrays for high information content active matrix flexible displays for Army applications. For all flexible substrates a manufacturable...impermeable flexible substrate systems “display-ready” materials and handling protocols, (ii) high performance TFT devices and circuits fabricated...processes for integration with the flexible TFT arrays. Approaches and solution to address each of these major challenges are described in the

A Thermally Powered ISFET Array for On-Body pH Measurement.

PubMed

Douthwaite, Matthew; Koutsos, Ermis; Yates, David C; Mitcheson, Paul D; Georgiou, Pantelis

2017-12-01

Recent advances in electronics and electrochemical sensors have led to an emerging class of next generation wearables, detecting analytes in biofluids such as perspiration. Most of these devices utilize ion-selective electrodes (ISEs) as a detection method; however, ion-sensitive field-effect transistors (ISFETs) offer a solution with improved integration and a low power consumption. This work presents a wearable, thermoelectrically powered system composed of an application-specific integrated circuit (ASIC), two commercial power management integrated circuits and a network of commercial thermoelectric generators (TEGs). The ASIC is fabricated in 0.35 m CMOS and contains an ISFET array designed to read pH as a current, a processing module which averages the signal to reduce noise and encodes it into a frequency, and a transmitter. The output frequency has a measured sensitivity of 6 to 8 kHz/pH for a pH range of 7-5. It is shown that the sensing array and processing module has a power consumption 6 W and, therefore, can be entirely powered by body heat using a TEG. Array averaging is shown to reduce noise at these low power levels to 104 V (input referred integrated noise), reducing the minimum detectable limit of the ASIC to 0.008 pH units. The work forms the foundation and proves the feasibility of battery-less, on-body electrochemical for perspiration analysis in sports science and healthcare applications.

Optical printed circuit board (O-PCB) and VLSI photonic integrated circuits: visions, challenges, and progresses

NASA Astrophysics Data System (ADS)

Lee, El-Hang; Lee, S. G.; O, B. H.; Park, S. G.; Noh, H. S.; Kim, K. H.; Song, S. H.

2006-09-01

A collective overview and review is presented on the original work conducted on the theory, design, fabrication, and in-tegration of micro/nano-scale optical wires and photonic devices for applications in a newly-conceived photonic systems called "optical printed circuit board" (O-PCBs) and "VLSI photonic integrated circuits" (VLSI-PIC). These are aimed for compact, high-speed, multi-functional, intelligent, light-weight, low-energy and environmentally friendly, low-cost, and high-volume applications to complement or surpass the capabilities of electrical PCBs (E-PCBs) and/or VLSI electronic integrated circuit (VLSI-IC) systems. These consist of 2-dimensional or 3-dimensional planar arrays of micro/nano-optical wires and circuits to perform the functions of all-optical sensing, storing, transporting, processing, switching, routing and distributing optical signals on flat modular boards or substrates. The integrated optical devices include micro/nano-scale waveguides, lasers, detectors, switches, sensors, directional couplers, multi-mode interference devices, ring-resonators, photonic crystal devices, plasmonic devices, and quantum devices, made of polymer, silicon and other semiconductor materials. For VLSI photonic integration, photonic crystals and plasmonic structures have been used. Scientific and technological issues concerning the processes of miniaturization, interconnection and integration of these systems as applicable to board-to-board, chip-to-chip, and intra-chip integration, are discussed along with applications for future computers, telecommunications, and sensor-systems. Visions and challenges toward these goals are also discussed.

Microfabricated cylindrical ion trap

DOEpatents

Blain, Matthew G.

2005-03-22

A microscale cylindrical ion trap, having an inner radius of order one micron, can be fabricated using surface micromachining techniques and materials known to the integrated circuits manufacturing and microelectromechanical systems industries. Micromachining methods enable batch fabrication, reduced manufacturing costs, dimensional and positional precision, and monolithic integration of massive arrays of ion traps with microscale ion generation and detection devices. Massive arraying enables the microscale cylindrical ion trap to retain the resolution, sensitivity, and mass range advantages necessary for high chemical selectivity. The microscale CIT has a reduced ion mean free path, allowing operation at higher pressures with less expensive and less bulky vacuum pumping system, and with lower battery power than conventional- and miniature-sized ion traps. The reduced electrode voltage enables integration of the microscale cylindrical ion trap with on-chip integrated circuit-based rf operation and detection electronics (i.e., cell phone electronics). Therefore, the full performance advantages of microscale cylindrical ion traps can be realized in truly field portable, handheld microanalysis systems.

Design, development and evaluation of a resistor-based multiplexing circuit for a 20×20 SiPM array

NASA Astrophysics Data System (ADS)

Wang, Zhonghai; Sun, Xishan; Lou, Kai; Meier, Joseph; Zhou, Rong; Yang, Chaowen; Zhu, Xiaorong; Shao, Yiping

2016-04-01

One technical challenge in developing a large-size scintillator detector with multiple Silicon Photomultiplier (SiPM) arrays is to read out a large number of detector output channels. To achieve this, different signal multiplexing circuits have been studied and applied with different performances and cost-effective tradeoffs. Resistor-based multiplexing circuits exhibit simplicity and signal integrity, but also present the disadvantage of timing shift among different channels. In this study, a resistor-based multiplexing circuit for a large-sized SiPM array readout was developed and evaluated by simulation and experimental studies. Similarly to a multiplexing circuit used for multi-anode PMT, grounding and branching resistors were connected to each SiPM output channel. The grounding resistor was used to simultaneously reduce the signal crosstalk among different channels and to improve timing performance. Both grounding and branching resistor values were optimized to maintain a balanced performance of the event energy, timing, and positioning. A multiplexing circuit was implemented on a compact PCB and applied for a flat-panel detector which consisted of a 32×32 LYSO scintillator crystals optically coupled to 5×5 SiPM arrays for a total 20×20 output channels. Test results showed excellent crystal identification for all 1024 LYSO crystals (each with 2×2×30 mm3 size) with 22Na flood-source irradiation. The measured peak-to-valley ratio from typical crystal map profile is around 3:1 to 6.6:1, an average single crystal energy resolution of about 17.3%, and an average single crystal timing resolution of about 2 ns. Timing shift among different crystals, as reported in some other resistor-based multiplexing circuit designs, was not observed. In summary, we have designed and implemented a practical resistor-based multiplexing circuit that can be readily applied for reading out a large SiPM array with good detector performance.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kay, Randolph R; Campbell, David V; Shinde, Subhash L

A modular, scalable focal plane array is provided as an array of integrated circuit dice, wherein each die includes a given amount of modular pixel array circuitry. The array of dice effectively multiplies the amount of modular pixel array circuitry to produce a larger pixel array without increasing die size. Desired pixel pitch across the enlarged pixel array is preserved by forming die stacks with each pixel array circuitry die stacked on a separate die that contains the corresponding signal processing circuitry. Techniques for die stack interconnections and die stack placement are implemented to ensure that the desired pixel pitchmore » is preserved across the enlarged pixel array.« less

An Electronic-Nose Sensor Node Based on a Polymer-Coated Surface Acoustic Wave Array for Wireless Sensor Network Applications

PubMed Central

Tang, Kea-Tiong; Li, Cheng-Han; Chiu, Shih-Wen

2011-01-01

This study developed an electronic-nose sensor node based on a polymer-coated surface acoustic wave (SAW) sensor array. The sensor node comprised an SAW sensor array, a frequency readout circuit, and an Octopus II wireless module. The sensor array was fabricated on a large K2 128° YX LiNbO3 sensing substrate. On the surface of this substrate, an interdigital transducer (IDT) was produced with a Cr/Au film as its metallic structure. A mixed-mode frequency readout application specific integrated circuit (ASIC) was fabricated using a TSMC 0.18 μm process. The ASIC output was connected to a wireless module to transmit sensor data to a base station for data storage and analysis. This sensor node is applicable for wireless sensor network (WSN) applications. PMID:22163865

An electronic-nose sensor node based on a polymer-coated surface acoustic wave array for wireless sensor network applications.

PubMed

Tang, Kea-Tiong; Li, Cheng-Han; Chiu, Shih-Wen

2011-01-01

This study developed an electronic-nose sensor node based on a polymer-coated surface acoustic wave (SAW) sensor array. The sensor node comprised an SAW sensor array, a frequency readout circuit, and an Octopus II wireless module. The sensor array was fabricated on a large K(2) 128° YX LiNbO3 sensing substrate. On the surface of this substrate, an interdigital transducer (IDT) was produced with a Cr/Au film as its metallic structure. A mixed-mode frequency readout application specific integrated circuit (ASIC) was fabricated using a TSMC 0.18 μm process. The ASIC output was connected to a wireless module to transmit sensor data to a base station for data storage and analysis. This sensor node is applicable for wireless sensor network (WSN) applications.

System-Level Integrated Circuit (SLIC) Technology Development for Phased Array Antenna Applications

NASA Technical Reports Server (NTRS)

Windyka, John A.; Zablocki, Ed G.

1997-01-01

This report documents the efforts and progress in developing a 'system-level' integrated circuit, or SLIC, for application in advanced phased array antenna systems. The SLIC combines radio-frequency (RF) microelectronics, digital and analog support circuitry, and photonic interfaces into a single micro-hybrid assembly. Together, these technologies provide not only the amplitude and phase control necessary for electronic beam steering in the phased array, but also add thermally-compensated automatic gain control, health and status feedback, bias regulation, and reduced interconnect complexity. All circuitry is integrated into a compact, multilayer structure configured for use as a two-by-four element phased array module, operating at 20 Gigahertz, using a Microwave High-Density Interconnect (MHDI) process. The resultant hardware is constructed without conventional wirebonds, maintains tight inter-element spacing, and leads toward low-cost mass production. The measured performances and development issues associated with both the two-by-four element module and the constituent elements are presented. Additionally, a section of the report describes alternative architectures and applications supported by the SLIC electronics. Test results show excellent yield and performance of RF circuitry and full automatic gain control for multiple, independent channels. Digital control function, while suffering from lower manufacturing yield, also proved successful.

Microwave integrated circuits for space applications

NASA Technical Reports Server (NTRS)

Leonard, Regis F.; Romanofsky, Robert R.

1991-01-01

Monolithic microwave integrated circuits (MMIC), which incorporate all the elements of a microwave circuit on a single semiconductor substrate, offer the potential for drastic reductions in circuit weight and volume and increased reliability, all of which make many new concepts in electronic circuitry for space applications feasible, including phased array antennas. NASA has undertaken an extensive program aimed at development of MMICs for space applications. The first such circuits targeted for development were an extension of work in hybrid (discrete component) technology in support of the Advanced Communication Technology Satellite (ACTS). It focused on power amplifiers, receivers, and switches at ACTS frequencies. More recent work, however, focused on frequencies appropriate for other NASA programs and emphasizes advanced materials in an effort to enhance efficiency, power handling capability, and frequency of operation or noise figure to meet the requirements of space systems.

Error modelling of quantum Hall array resistance standards

NASA Astrophysics Data System (ADS)

Marzano, Martina; Oe, Takehiko; Ortolano, Massimo; Callegaro, Luca; Kaneko, Nobu-Hisa

2018-04-01

Quantum Hall array resistance standards (QHARSs) are integrated circuits composed of interconnected quantum Hall effect elements that allow the realization of virtually arbitrary resistance values. In recent years, techniques were presented to efficiently design QHARS networks. An open problem is that of the evaluation of the accuracy of a QHARS, which is affected by contact and wire resistances. In this work, we present a general and systematic procedure for the error modelling of QHARSs, which is based on modern circuit analysis techniques and Monte Carlo evaluation of the uncertainty. As a practical example, this method of analysis is applied to the characterization of a 1 MΩ QHARS developed by the National Metrology Institute of Japan. Software tools are provided to apply the procedure to other arrays.

Flat-plate photovoltaic array design optimization

NASA Technical Reports Server (NTRS)

Ross, R. G., Jr.

1980-01-01

An analysis is presented which integrates the results of specific studies in the areas of photovoltaic structural design optimization, optimization of array series/parallel circuit design, thermal design optimization, and optimization of environmental protection features. The analysis is based on minimizing the total photovoltaic system life-cycle energy cost including repair and replacement of failed cells and modules. This approach is shown to be a useful technique for array optimization, particularly when time-dependent parameters such as array degradation and maintenance are involved.

Feasibility study, software design, layout and simulation of a two-dimensional Fast Fourier Transform machine for use in optical array interferometry

NASA Technical Reports Server (NTRS)

Boriakoff, Valentin

1994-01-01

The goal of this project was the feasibility study of a particular architecture of a digital signal processing machine operating in real time which could do in a pipeline fashion the computation of the fast Fourier transform (FFT) of a time-domain sampled complex digital data stream. The particular architecture makes use of simple identical processors (called inner product processors) in a linear organization called a systolic array. Through computer simulation the new architecture to compute the FFT with systolic arrays was proved to be viable, and computed the FFT correctly and with the predicted particulars of operation. Integrated circuits to compute the operations expected of the vital node of the systolic architecture were proven feasible, and even with a 2 micron VLSI technology can execute the required operations in the required time. Actual construction of the integrated circuits was successful in one variant (fixed point) and unsuccessful in the other (floating point).

A 60-GHz interferometer with a local oscillator integrated antenna array for divertor simulation experiments on GAMMA 10/PDX

NASA Astrophysics Data System (ADS)

Kohagura, J.; Yoshikawa, M.; Wang, X.; Kuwahara, D.; Ito, N.; Nagayama, Y.; Shima, Y.; Nojiri, K.; Sakamoto, M.; Nakashima, Y.; Mase, A.

2016-11-01

In conventional multichannel/imaging microwave diagnostics of interferometry, reflectometry, and electron cyclotron emission measurements, a local oscillator (LO) signal is commonly supplied to a receiver array via irradiation using LO optics. In this work, we present a 60-GHz interferometer with a new eight-channel receiver array, called a local oscillator integrated antenna array (LIA). An outstanding feature of LIA is that it incorporates a frequency quadrupler integrated circuit for LO supply to each channel. This enables simple and uniform LO supply to the receiver array using only a 15-GHz LO source and a coaxial cable transmission line instead of using an expensive 60-GHz source, LO optics, and a waveguide transmission line. The new interferometer system is first applied to measure electron line-averaged density inside the divertor simulation experimental module (D-module) on GAMMA 10/PDX tandem mirror device.

A 60-GHz interferometer with a local oscillator integrated antenna array for divertor simulation experiments on GAMMA 10/PDX

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kohagura, J., E-mail: kohagura@prc.tsukuba.ac.jp; Yoshikawa, M.; Shima, Y.

In conventional multichannel/imaging microwave diagnostics of interferometry, reflectometry, and electron cyclotron emission measurements, a local oscillator (LO) signal is commonly supplied to a receiver array via irradiation using LO optics. In this work, we present a 60-GHz interferometer with a new eight-channel receiver array, called a local oscillator integrated antenna array (LIA). An outstanding feature of LIA is that it incorporates a frequency quadrupler integrated circuit for LO supply to each channel. This enables simple and uniform LO supply to the receiver array using only a 15-GHz LO source and a coaxial cable transmission line instead of using an expensivemore » 60-GHz source, LO optics, and a waveguide transmission line. The new interferometer system is first applied to measure electron line-averaged density inside the divertor simulation experimental module (D-module) on GAMMA 10/PDX tandem mirror device.« less

A 60-GHz interferometer with a local oscillator integrated antenna array for divertor simulation experiments on GAMMA 10/PDX.

PubMed

Kohagura, J; Yoshikawa, M; Wang, X; Kuwahara, D; Ito, N; Nagayama, Y; Shima, Y; Nojiri, K; Sakamoto, M; Nakashima, Y; Mase, A

2016-11-01

In conventional multichannel/imaging microwave diagnostics of interferometry, reflectometry, and electron cyclotron emission measurements, a local oscillator (LO) signal is commonly supplied to a receiver array via irradiation using LO optics. In this work, we present a 60-GHz interferometer with a new eight-channel receiver array, called a local oscillator integrated antenna array (LIA). An outstanding feature of LIA is that it incorporates a frequency quadrupler integrated circuit for LO supply to each channel. This enables simple and uniform LO supply to the receiver array using only a 15-GHz LO source and a coaxial cable transmission line instead of using an expensive 60-GHz source, LO optics, and a waveguide transmission line. The new interferometer system is first applied to measure electron line-averaged density inside the divertor simulation experimental module (D-module) on GAMMA 10/PDX tandem mirror device.

Read-In Integrated Circuits for Large-Format Multi-Chip Emitter Arrays

DTIC Science & Technology

2015-03-31

chip has been designed and fabricated using ONSEMI C5N process to verify our approach. Keywords: Large scale arrays; Tiling; Mosaic; Abutment ...required. X and y addressing is not a sustainable and easily expanded addressing architecture nor will it work well with abutted RIICs. Abutment Method... Abutting RIICs into an array is challenging because of the precise positioning required to achieve a uniform image. This problem is a new design

Amplifier arrays for CMB polarization

NASA Technical Reports Server (NTRS)

Gaier, Todd; Lawrence, Charles R.; Seiffert, Michael D.; Wells, Mary M.; Kangaslahti, Pekka; Dawson, Douglas

2003-01-01

Cryogenic low noise amplifier technology has been successfully used in the study of the cosmic microwave background (CMB). MMIC (Monolithic Millimeter wave Integrated Circuit) technology makes the mass production of coherent detection receivers feasible.

High Density Polymer-Based Integrated Electgrode Array

DOEpatents

Maghribi, Mariam N.; Krulevitch, Peter A.; Davidson, James Courtney; Hamilton, Julie K.

2006-04-25

A high density polymer-based integrated electrode apparatus that comprises a central electrode body and a multiplicity of arms extending from the electrode body. The central electrode body and the multiplicity of arms are comprised of a silicone material with metal features in said silicone material that comprise electronic circuits.

670-GHz Schottky Diode-Based Subharmonic Mixer with CPW Circuits and 70-GHz IF

NASA Technical Reports Server (NTRS)

Chattopadhyay, Goutam; Schlecht, Erich T.; Lee, Choonsup; Lin, Robert H.; Gill, John J.; Mehdi, Imran; Sin, Seth; Deal, William; Loi, Kwok K.; Nam, Peta;

An integrated circuit with transmit beamforming flip-chip bonded to a 2-D CMUT array for 3-D ultrasound imaging.

PubMed

Wygant, Ira O; Jamal, Nafis S; Lee, Hyunjoo J; Nikoozadeh, Amin; Oralkan, Omer; Karaman, Mustafa; Khuri-Yakub, Butrus T

2009-10-01

State-of-the-art 3-D medical ultrasound imaging requires transmitting and receiving ultrasound using a 2-D array of ultrasound transducers with hundreds or thousands of elements. A tight combination of the transducer array with integrated circuitry eliminates bulky cables connecting the elements of the transducer array to a separate system of electronics. Furthermore, preamplifiers located close to the array can lead to improved receive sensitivity. A combined IC and transducer array can lead to a portable, high-performance, and inexpensive 3-D ultrasound imaging system. This paper presents an IC flip-chip bonded to a 16 x 16-element capacitive micromachined ultrasonic transducer (CMUT) array for 3-D ultrasound imaging. The IC includes a transmit beamformer that generates 25-V unipolar pulses with programmable focusing delays to 224 of the 256 transducer elements. One-shot circuits allow adjustment of the pulse widths for different ultrasound transducer center frequencies. For receiving reflected ultrasound signals, the IC uses the 32-elements along the array diagonals. The IC provides each receiving element with a low-noise 25-MHz-bandwidth transimpedance amplifier. Using a field-programmable gate array (FPGA) clocked at 100 MHz to operate the IC, the IC generated properly timed transmit pulses with 5-ns accuracy. With the IC flip-chip bonded to a CMUT array, we show that the IC can produce steered and focused ultrasound beams. We present 2-D and 3-D images of a wire phantom and 2-D orthogonal cross-sectional images (Bscans) of a latex heart phantom.

Solar cell circuit and method for manufacturing solar cells

NASA Technical Reports Server (NTRS)

Mardesich, Nick (Inventor)

2010-01-01

The invention is a novel manufacturing method for making multi-junction solar cell circuits that addresses current problems associated with such circuits by allowing the formation of integral diodes in the cells and allows for a large number of circuits to readily be placed on a single silicon wafer substrate. The standard Ge wafer used as the base for multi-junction solar cells is replaced with a thinner layer of Ge or a II-V semiconductor material on a silicon/silicon dioxide substrate. This allows high-voltage cells with multiple multi-junction circuits to be manufactured on a single wafer, resulting in less array assembly mass and simplified power management.

Digital MOS integrated circuits

NASA Astrophysics Data System (ADS)

Elmasry, M. I.

MOS in digital circuit design is considered along with aspects of digital VLSI, taking into account a comparison of MOSFET logic circuits, 1-micrometer MOSFET VLSI technology, a generalized guide for MOSFET miniaturization, processing technologies, novel circuit structures for VLSI, and questions of circuit and system design for VLSI. MOS memory cells and circuits are discussed, giving attention to a survey of high-density dynamic RAM cell concepts, one-device cells for dynamic random-access memories, variable resistance polysilicon for high density CMOS Ram, high performance MOS EPROMs using a stacked-gate cell, and the optimization of the latching pulse for dynamic flip-flop sensors. Programmable logic arrays are considered along with digital signal processors, microprocessors, static RAMs, and dynamic RAMs.

Modeling Charge Collection in Detector Arrays

NASA Technical Reports Server (NTRS)

Hardage, Donna (Technical Monitor); Pickel, J. C.

2003-01-01

A detector array charge collection model has been developed for use as an engineering tool to aid in the design of optical sensor missions for operation in the space radiation environment. This model is an enhancement of the prototype array charge collection model that was developed for the Next Generation Space Telescope (NGST) program. The primary enhancements were accounting for drift-assisted diffusion by Monte Carlo modeling techniques and implementing the modeling approaches in a windows-based code. The modeling is concerned with integrated charge collection within discrete pixels in the focal plane array (FPA), with high fidelity spatial resolution. It is applicable to all detector geometries including monolithc charge coupled devices (CCDs), Active Pixel Sensors (APS) and hybrid FPA geometries based on a detector array bump-bonded to a readout integrated circuit (ROIC).

Active pixel sensor with intra-pixel charge transfer

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Mendis, Sunetra (Inventor); Kemeny, Sabrina E. (Inventor)

1995-01-01

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node.

Active pixel sensor with intra-pixel charge transfer

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Mendis, Sunetra (Inventor); Kemeny, Sabrina E. (Inventor)

2003-01-01

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node.

Active pixel sensor with intra-pixel charge transfer

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Mendis, Sunetra (Inventor); Kemeny, Sabrina E. (Inventor)

2004-01-01

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node.

Quartz/fused silica chip carriers

NASA Technical Reports Server (NTRS)

1992-01-01

The primary objective of this research and development effort was to develop monolithic microwave integrated circuit (MMIC) packaging which will operate efficiently at millimeter-wave frequencies. The packages incorporated fused silica as the substrate material which was selected due to its favorable electrical properties and potential performance improvement over more conventional materials for Ka-band operation. The first step towards meeting this objective is to develop a package that meets standard mechanical and thermal requirements using fused silica and to be compatible with semiconductor devices operating up to at least 44 GHz. The second step is to modify the package design and add multilayer and multicavity capacity to allow for application specific integrated circuits (ASIC's) to control multiple phase shifters. The final step is to adapt the package design to a phased array module with integral radiating elements. The first task was a continuation of the SBIR Phase 1 work. Phase 1 identified fused silica as a viable substrate material by demonstrating various plating, machining, and adhesion properties. In Phase 2 Task 1, a package was designed and fabricated to validate these findings. Task 2 was to take the next step in packaging and fabricate a multilayer, multichip module (MCM). This package is the predecessor to the phased array module and demonstrates the ability to via fill, circuit print, laminate, and to form vertical interconnects. The final task was to build a phased array module. The radiating elements were to be incorporated into the package instead of connecting to it with wire or ribbon bonds.

High-Speed Binary-Output Image Sensor

NASA Technical Reports Server (NTRS)

Fossum, Eric; Panicacci, Roger A.; Kemeny, Sabrina E.; Jones, Peter D.

1996-01-01

Photodetector outputs digitized by circuitry on same integrated-circuit chip. Developmental special-purpose binary-output image sensor designed to capture up to 1,000 images per second, with resolution greater than 10 to the 6th power pixels per image. Lower-resolution but higher-frame-rate prototype of sensor contains 128 x 128 array of photodiodes on complementary metal oxide/semiconductor (CMOS) integrated-circuit chip. In application for which it is being developed, sensor used to examine helicopter oil to determine whether amount of metal and sand in oil sufficient to warrant replacement.

Performance of a 300 Mbps 1:16 serial/parallel optoelectronic receiver module

NASA Technical Reports Server (NTRS)

Richard, M. A.; Claspy, P. C.; Bhasin, K. B.; Bendett, M. B.

1990-01-01

Optical interconnects are being considered for the high speed distribution of multiplexed control signals in GaAs monolithic microwave integrated circuit (MMIC) based phased array antennas. The performance of a hybrid GaAs optoelectronic integrated circuit (OEIC) is described, as well as its design and fabrication. The OEIC converts a 16-bit serial optical input to a 16 parallel line electrical output using an on-board 1:16 demultiplexer and operates at data rates as high as 30b Mbps. The performance characteristics and potential applications of the device are presented.

High-performance packaging for monolithic microwave and millimeter-wave integrated circuits

NASA Technical Reports Server (NTRS)

Shalkhauser, K. A.; Li, K.; Shih, Y. C.

1992-01-01

Packaging schemes are developed that provide low-loss, hermetic enclosure for enhanced monolithic microwave and millimeter-wave integrated circuits. These package schemes are based on a fused quartz substrate material offering improved RF performance through 44 GHz. The small size and weight of the packages make them useful for a number of applications, including phased array antenna systems. As part of the packaging effort, a test fixture was developed to interface the single chip packages to conventional laboratory instrumentation for characterization of the packaged devices.

Analysis of microstrip dipoles and slots transversely coupled to a microstrip line using the FDTD method

NASA Technical Reports Server (NTRS)

Tulintseff, A. N.

1993-01-01

Printed dipole elements and their complement, linear slots, are elementary radiators that have found use in low-profile antenna arrays. Low-profile antenna arrays, in addition to their small size and low weight characteristics, offer the potential advantage of low-cost, high-volume production with easy integration with active integrated circuit components. The design of such arrays requires that the radiation and impedance characteristics of the radiating elements be known. The FDTD (Finite-Difference Time-Domain) method is a general, straight-forward implementation of Maxwell's equations and offers a relatively simple way of analyzing both printed dipole and slot elements. Investigated in this work is the application of the FDTD method to the analysis of printed dipole and slot elements transversely coupled to an infinite transmission line in a multilayered configuration. Such dipole and slot elements may be used in dipole and slot series-fed-type linear arrays, where element offsets and interelement line lengths are used to obtain the desired amplitude distribution and beam direction, respectively. The design of such arrays is achieved using transmission line theory with equivalent circuit models for the radiating elements. In an equivalent circuit model, the dipole represents a shunt impedance to the transmission line, where the impedance is a function of dipole offset, length, and width. Similarly, the slot represents a series impedance to the transmission line. The FDTD method is applied to single dipole and slot elements transversely coupled to an infinite microstrip line using a fixed rectangular grid with Mur's second order absorbing boundary conditions. Frequency-dependent circuit and scattering parameters are obtained by saving desired time-domain quantities and using the Fourier transform. A Gaussian pulse excitation is applied to the microstrip transmission line, where the resulting reflected signal due to the presence of the radiating element is used to determine the equivalent element impedance.

A 32 x 32 capacitive micromachined ultrasonic transducer array manufactured in standard CMOS.

PubMed

Lemmerhirt, David F; Cheng, Xiaoyang; White, Robert; Rich, Collin A; Zhang, Man; Fowlkes, J Brian; Kripfgans, Oliver D

2012-07-01

As ultrasound imagers become increasingly portable and lower cost, breakthroughs in transducer technology will be needed to provide high-resolution, real-time 3-D imaging while maintaining the affordability needed for portable systems. This paper presents a 32 x 32 ultrasound array prototype, manufactured using a CMUT-in-CMOS approach whereby ultrasonic transducer elements and readout circuits are integrated on a single chip using a standard integrated circuit manufacturing process in a commercial CMOS foundry. Only blanket wet-etch and sealing steps are added to complete the MEMS devices after the CMOS process. This process typically yields better than 99% working elements per array, with less than ±1.5 dB variation in receive sensitivity among the 1024 individually addressable elements. The CMUT pulseecho frequency response is typically centered at 2.1 MHz with a -6 dB fractional bandwidth of 60%, and elements are arranged on a 250 μm hexagonal grid (less than half-wavelength pitch). Multiplexers and CMOS buffers within the array are used to make on-chip routing manageable, reduce the number of physical output leads, and drive the transducer cable. The array has been interfaced to a commercial imager as well as a set of custom transmit and receive electronics, and volumetric images of nylon fishing line targets have been produced.

Common source cascode amplifiers for integrating IR-FPA applications

NASA Technical Reports Server (NTRS)

Woolaway, James T.; Young, Erick T.

1989-01-01

Space based astronomical infrared measurements present stringent performance requirements on the infrared detector arrays and their associated readout circuitry. To evaluate the usefulness of commercial CMOS technology for astronomical readout applications a theoretical and experimental evaluation was performed on source follower and common-source cascode integrating amplifiers. Theoretical analysis indicates that for conditions where the input amplifier integration capacitance is limited by the detectors capacitance the input referred rms noise electrons of each amplifier should be equivalent. For conditions of input gate limited capacitance the source follower should provide lower noise. Measurements of test circuits containing both source follower and common source cascode circuits showed substantially lower input referred noise for the common-source cascode input circuits. Noise measurements yielded 4.8 input referred rms noise electrons for an 8.5 minute integration. The signal and noise gain of the common-source cascode amplifier appears to offer substantial advantages in acheiving predicted noise levels.

III-V-on-Silicon Photonic Integrated Circuits for Spectroscopic Sensing in the 2-4 μm Wavelength Range.

PubMed

Wang, Ruijun; Vasiliev, Anton; Muneeb, Muhammad; Malik, Aditya; Sprengel, Stephan; Boehm, Gerhard; Amann, Markus-Christian; Šimonytė, Ieva; Vizbaras, Augustinas; Vizbaras, Kristijonas; Baets, Roel; Roelkens, Gunther

2017-08-04

The availability of silicon photonic integrated circuits (ICs) in the 2-4 μm wavelength range enables miniature optical sensors for trace gas and bio-molecule detection. In this paper, we review our recent work on III-V-on-silicon waveguide circuits for spectroscopic sensing in this wavelength range. We first present results on the heterogeneous integration of 2.3 μm wavelength III-V laser sources and photodetectors on silicon photonic ICs for fully integrated optical sensors. Then a compact 2 μm wavelength widely tunable external cavity laser using a silicon photonic IC for the wavelength selective feedback is shown. High-performance silicon arrayed waveguide grating spectrometers are also presented. Further we show an on-chip photothermal transducer using a suspended silicon-on-insulator microring resonator used for mid-infrared photothermal spectroscopy.

III–V-on-Silicon Photonic Integrated Circuits for Spectroscopic Sensing in the 2–4 μm Wavelength Range

PubMed Central

Wang, Ruijun; Vasiliev, Anton; Muneeb, Muhammad; Malik, Aditya; Sprengel, Stephan; Boehm, Gerhard; Amann, Markus-Christian; Šimonytė, Ieva; Vizbaras, Augustinas; Vizbaras, Kristijonas; Baets, Roel; Roelkens, Gunther

2017-01-01

The availability of silicon photonic integrated circuits (ICs) in the 2–4 μm wavelength range enables miniature optical sensors for trace gas and bio-molecule detection. In this paper, we review our recent work on III–V-on-silicon waveguide circuits for spectroscopic sensing in this wavelength range. We first present results on the heterogeneous integration of 2.3 μm wavelength III–V laser sources and photodetectors on silicon photonic ICs for fully integrated optical sensors. Then a compact 2 μm wavelength widely tunable external cavity laser using a silicon photonic IC for the wavelength selective feedback is shown. High-performance silicon arrayed waveguide grating spectrometers are also presented. Further we show an on-chip photothermal transducer using a suspended silicon-on-insulator microring resonator used for mid-infrared photothermal spectroscopy. PMID:28777291

High-performance packaging for monolithic microwave and millimeter-wave integrated circuits

NASA Technical Reports Server (NTRS)

Shalkhauser, K. A.; Li, K.; Shih, Y. C.

1992-01-01

Packaging schemes were developed that provide low-loss, hermetic enclosure for advanced monolithic microwave and millimeter-wave integrated circuits (MMICs). The package designs are based on a fused quartz substrate material that offers improved radio frequency (RF) performance through 44 gigahertz (GHz). The small size and weight of the packages make them appropriate for a variety of applications, including phased array antenna systems. Packages were designed in two forms; one for housing a single MMIC chip, the second in the form of a multi-chip phased array module. The single chip array module was developed in three separate sizes, for chips of different geometry and frequency requirements. The phased array module was developed to address packaging directly for antenna applications, and includes transmission line and interconnect structures to support multi-element operation. All packages are fabricated using fused quartz substrate materials. As part of the packaging effort, a test fixture was developed to interface the single chip packages to conventional laboratory instrumentation for characterization of the packaged devices. The package and test fixture designs were both developed in a generic sense, optimizing performance for a wide range of possible applications and devices.

Coherent optical monolithic phased-array antenna steering system

DOEpatents

Hietala, Vincent M.; Kravitz, Stanley H.; Vawter, Gregory A.

1994-01-01

An optical-based RF beam steering system for phased-array antennas comprising a photonic integrated circuit (PIC). The system is based on optical heterodyning employed to produce microwave phase shifting by a monolithic PIC constructed entirely of passive components. Microwave power and control signal distribution to the antenna is accomplished by optical fiber, permitting physical separation of the PIC and its control functions from the antenna. The system reduces size, weight, complexity, and cost of phased-array antenna systems.

Programmable nanowire circuits for nanoprocessors.

PubMed

Yan, Hao; Choe, Hwan Sung; Nam, SungWoo; Hu, Yongjie; Das, Shamik; Klemic, James F; Ellenbogen, James C; Lieber, Charles M

2011-02-10

A nanoprocessor constructed from intrinsically nanometre-scale building blocks is an essential component for controlling memory, nanosensors and other functions proposed for nanosystems assembled from the bottom up. Important steps towards this goal over the past fifteen years include the realization of simple logic gates with individually assembled semiconductor nanowires and carbon nanotubes, but with only 16 devices or fewer and a single function for each circuit. Recently, logic circuits also have been demonstrated that use two or three elements of a one-dimensional memristor array, although such passive devices without gain are difficult to cascade. These circuits fall short of the requirements for a scalable, multifunctional nanoprocessor owing to challenges in materials, assembly and architecture on the nanoscale. Here we describe the design, fabrication and use of programmable and scalable logic tiles for nanoprocessors that surmount these hurdles. The tiles were built from programmable, non-volatile nanowire transistor arrays. Ge/Si core/shell nanowires coupled to designed dielectric shells yielded single-nanowire, non-volatile field-effect transistors (FETs) with uniform, programmable threshold voltages and the capability to drive cascaded elements. We developed an architecture to integrate the programmable nanowire FETs and define a logic tile consisting of two interconnected arrays with 496 functional configurable FET nodes in an area of ∼960 μm(2). The logic tile was programmed and operated first as a full adder with a maximal voltage gain of ten and input-output voltage matching. Then we showed that the same logic tile can be reprogrammed and used to demonstrate full-subtractor, multiplexer, demultiplexer and clocked D-latch functions. These results represent a significant advance in the complexity and functionality of nanoelectronic circuits built from the bottom up with a tiled architecture that could be cascaded to realize fully integrated nanoprocessors with computing, memory and addressing capabilities.

Vacuum Microelectronic Field Emission Array Devices for Microwave Amplification.

NASA Astrophysics Data System (ADS)

Mancusi, Joseph Edward

This dissertation presents the design, analysis, and measurement of vacuum microelectronic devices which use field emission to extract an electron current from arrays of silicon cones. The arrays of regularly-spaced silicon cones, the field emission cathodes or emitters, are fabricated with an integrated gate electrode which controls the electric field at the tip of the cone, and thus the electron current. An anode or collector electrode is placed above the array to collect the emission current. These arrays, which are fabricated in a standard silicon processing facility, are developed for use as high power microwave amplifiers. Field emission has been studied extensively since it was first characterized in 1928, however due to the large electric fields required practical field emission devices are difficult to make. With the development of the semiconductor industry came the development of fabrication equipment and techniques which allow for the manufacture of the precision micron-scale structures necessary for practical field emission devices. The active region of a field emission device is a vacuum, therefore the electron travel is ballistic. This analysis of field emission devices includes electric field and electron emission modeling, development of a device equivalent circuit, analysis of the parameters in the equivalent circuit, and device testing. Variations in device structure are taken into account using a statistical model based upon device measurements. Measurements of silicon field emitter arrays at DC and RF are presented and analyzed. In this dissertation, the equivalent circuit is developed from the analysis of the device structure. The circuit parameters are calculated from geometrical considerations and material properties, or are determined from device measurements. It is necessary to include the emitter resistance in the equivalent circuit model since relatively high resistivity silicon wafers are used. As is demonstrated, the circuit model accurately predicts the magnitude of the emission current at a number of typical bias current levels when the device is operating at frequencies within the range of 10 MHz to 1 GHz. At low frequencies and at high frequencies within this range, certain parameters are negligible, and simplifications may be made in the equivalent circuit model.

Coherent Detector Arrays for Continuum and Spectral Line Applications

NASA Technical Reports Server (NTRS)

Gaier, Todd C.

2006-01-01

This viewgraph presentation reviews the requirements for improved coherent detector arrays for use in continuum and spectral line applications. With detectors approaching fundamental limits, large arrays offer the only path to sensitivity improvement. Monolithic Microwave Integrated Circuit (MMIC) technology offers a straightforward path to massive focal plane millimeter wave arrays: The technology will readily support continuum imagers, polarimeters and spectral line receivers from 30-110 GHz. Science programs, particularly large field blind surveys will benefit from simultaneous observations of hundreds or thousands of pixels 1000 element array is competitive with a cost less than $2M.

Metallic Nanowire Interconnections for Integrated Circuit Fabrication

NASA Technical Reports Server (NTRS)

Ng, Hou Tee (Inventor); Li, Jun (Inventor); Meyyappan, Meyya (Inventor)

2007-01-01

A method for fabricating an electrical interconnect between two or more electrical components. A conductive layer is provided on a substarte and a thin, patterned catalyst array is deposited on an exposed surface of the conductive layer. A gas or vapor of a metallic precursor of a metal nanowire (MeNW) is provided around the catalyst array, and MeNWs grow between the conductive layer and the catalyst array. The catalyst array and a portion of each of the MeNWs are removed to provide exposed ends of the MeNWs.

Monolithic circuits for barium fluoride detectors used in nuclear physics experiments. CRADA final report

DOE Office of Scientific and Technical Information (OSTI.GOV)

Varner, R.L.; Blankenship, J.L.; Beene, J.R.

1998-02-01

Custom monolithic electronic circuits have been developed recently for large detector applications in high energy physics where subsystems require tens of thousands of channels of signal processing and data acquisition. In the design and construction of these enormous detectors, it has been found that monolithic circuits offer significant advantages over discrete implementations through increased performance, flexible packaging, lower power and reduced cost per channel. Much of the integrated circuit design for the high energy physics community is directly applicable to intermediate energy heavy-ion and electron physics. This STTR project conducted in collaboration with researchers at the Holifield Radioactive Ion Beammore » Facility (HRIBF) at Oak Ridge National Laboratory, sought to develop a new integrated circuit chip set for barium fluoride (BaF{sub 2}) detector arrays based upon existing CMOS monolithic circuit designs created for the high energy physics experiments. The work under the STTR Phase 1 demonstrated through the design, simulation, and testing of several prototype chips the feasibility of using custom CMOS integrated circuits for processing signals from BaF{sub 2} detectors. Function blocks including charge-sensitive amplifiers, comparators, one shots, time-to-amplitude converters, analog memory circuits and buffer amplifiers were implemented during Phase 1 effort. Experimental results from bench testing and laboratory testing with sources were documented.« less

A low-power small-area ADC array for IRFPA readout

NASA Astrophysics Data System (ADS)

Zhong, Shengyou; Yao, Libin

2013-09-01

The readout integrated circuit (ROIC) is a bridge between the infrared focal plane array (IRFPA) and image processing circuit in an infrared imaging system. The ROIC is the first part of signal processing circuit and connected to detectors directly, so its performance will greatly affect the detector or even the whole imaging system performance. With the development of CMOS technologies, it's possible to digitalize the signal inside the ROIC and develop the digital ROIC. Digital ROIC can reduce complexity of the whole system and improve the system reliability. More importantly, it can accommodate variety of digital signal processing techniques which the traditional analog ROIC cannot achieve. The analog to digital converter (ADC) is the most important building block in the digital ROIC. The requirements for ADCs inside the ROIC are low power, high dynamic range and small area. In this paper we propose an RC hybrid Successive Approximation Register (SAR) ADC as the column ADC for digital ROIC. In our proposed ADC structure, a resistor ladder is used to generate several voltages. The proposed RC hybrid structure not only reduces the area of capacitor array but also releases requirement for capacitor array matching. Theory analysis and simulation show RC hybrid SAR ADC is suitable for ADC array applications

CMOS Active-Pixel Image Sensor With Intensity-Driven Readout

NASA Technical Reports Server (NTRS)

Langenbacher, Harry T.; Fossum, Eric R.; Kemeny, Sabrina

1996-01-01

Proposed complementary metal oxide/semiconductor (CMOS) integrated-circuit image sensor automatically provides readouts from pixels in order of decreasing illumination intensity. Sensor operated in integration mode. Particularly useful in number of image-sensing tasks, including diffractive laser range-finding, three-dimensional imaging, event-driven readout of sparse sensor arrays, and star tracking.

An analog integrated circuit beamformer for high-frequency medical ultrasound imaging.

PubMed

Gurun, Gokce; Zahorian, Jaime S; Sisman, Alper; Karaman, Mustafa; Hasler, Paul E; Degertekin, F Levent

2012-10-01

We designed and fabricated a dynamic receive beamformer integrated circuit (IC) in 0.35-μm CMOS technology. This beamformer IC is suitable for integration with an annular array transducer for high-frequency (30-50 MHz) intravascular ultrasound (IVUS) imaging. The beamformer IC consists of receive preamplifiers, an analog dynamic delay-and-sum beamformer, and buffers for 8 receive channels. To form an analog dynamic delay line we designed an analog delay cell based on the current-mode first-order all-pass filter topology, as the basic building block. To increase the bandwidth of the delay cell, we explored an enhancement technique on the current mirrors. This technique improved the overall bandwidth of the delay line by a factor of 6. Each delay cell consumes 2.1-mW of power and is capable of generating a tunable time delay between 1.75 ns to 2.5 ns. We successfully integrated the fabricated beamformer IC with an 8-element annular array. Experimental test results demonstrated the desired buffering, preamplification and delaying capabilities of the beamformer.

Fully chip-embedded automation of a multi-step lab-on-a-chip process using a modularized timer circuit.

PubMed

Kang, Junsu; Lee, Donghyeon; Heo, Young Jin; Chung, Wan Kyun

2017-11-07

For highly-integrated microfluidic systems, an actuation system is necessary to control the flow; however, the bulk of actuation devices including pumps or valves has impeded the broad application of integrated microfluidic systems. Here, we suggest a microfluidic process control method based on built-in microfluidic circuits. The circuit is composed of a fluidic timer circuit and a pneumatic logic circuit. The fluidic timer circuit is a serial connection of modularized timer units, which sequentially pass high pressure to the pneumatic logic circuit. The pneumatic logic circuit is a NOR gate array designed to control the liquid-controlling process. By using the timer circuit as a built-in signal generator, multi-step processes could be done totally inside the microchip without any external controller. The timer circuit uses only two valves per unit, and the number of process steps can be extended without limitation by adding timer units. As a demonstration, an automation chip has been designed for a six-step droplet treatment, which entails 1) loading, 2) separation, 3) reagent injection, 4) incubation, 5) clearing and 6) unloading. Each process was successfully performed for a pre-defined step-time without any external control device.

CMOS Integrated Lock-in Readout Circuit for FET Terahertz Detectors

NASA Astrophysics Data System (ADS)

Domingues, Suzana; Perenzoni, Daniele; Perenzoni, Matteo; Stoppa, David

2017-06-01

In this paper, a switched-capacitor readout circuit topology integrated with a THz antenna and field-effect transistor detector is analyzed, designed, and fabricated in a 0.13-μm standard CMOS technology. The main objective is to perform amplification and filtering of the signal, as well as subtraction of background in case of modulated source, in order to avoid the need for an external lock-in amplifier, in a compact implementation. A maximum responsivity of 139.7 kV/W, and a corresponding minimum NEP of 2.2 nW/√Hz, was obtained with a two-stage readout circuit at 1 kHz modulation frequency. The presented switched-capacitor circuit is suitable for implementation in pixel arrays due to its compact size and power consumption (0.014 mm2 and 36 μW).

Active pixel sensor having intra-pixel charge transfer with analog-to-digital converter

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Mendis, Sunetra K. (Inventor); Pain, Bedabrata (Inventor); Nixon, Robert H. (Inventor); Zhou, Zhimin (Inventor)

2003-01-01

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node and an analog-to-digital converter formed in the substrate connected to the output of the readout circuit.

Active pixel sensor having intra-pixel charge transfer with analog-to-digital converter

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Mendis, Sunetra K. (Inventor); Pain, Bedabrata (Inventor); Nixon, Robert H. (Inventor); Zhou, Zhimin (Inventor)

2000-01-01

An imaging device formed as a monolithic complementary metal oxide semiconductor Integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node and an analog-to-digital converter formed in the substrate connected to the output of the readout circuit.

High-voltage integrated active quenching circuit for single photon count rate up to 80 Mcounts/s.

PubMed

Acconcia, Giulia; Rech, Ivan; Gulinatti, Angelo; Ghioni, Massimo

2016-08-08

Single photon avalanche diodes (SPADs) have been subject to a fast improvement in recent years. In particular, custom technologies specifically developed to fabricate SPAD devices give the designer the freedom to pursue the best detector performance required by applications. A significant breakthrough in this field is represented by the recent introduction of a red enhanced SPAD (RE-SPAD) technology, capable of attaining a good photon detection efficiency in the near infrared range (e.g. 40% at a wavelength of 800 nm) while maintaining a remarkable timing resolution of about 100ps full width at half maximum. Being planar, the RE-SPAD custom technology opened the way to the development of SPAD arrays particularly suited for demanding applications in the field of life sciences. However, to achieve such excellent performance custom SPAD detectors must be operated with an external active quenching circuit (AQC) designed on purpose. Next steps toward the development of compact and practical multichannel systems will require a new generation of monolithically integrated AQC arrays. In this paper we present a new, fully integrated AQC fabricated in a high-voltage 0.18 µm CMOS technology able to provide quenching pulses up to 50 Volts with fast leading and trailing edges. Although specifically designed for optimal operation of RE-SPAD devices, the new AQC is quite versatile: it can be used with any SPAD detector, regardless its fabrication technology, reaching remarkable count rates up to 80 Mcounts/s and generating a photon detection pulse with a timing jitter as low as 119 ps full width at half maximum. The compact design of our circuit has been specifically laid out to make this IC a suitable building block for monolithically integrated AQC arrays.

A Distributed Amplifier System for Bilayer Lipid Membrane (BLM) Arrays With Noise and Individual Offset Cancellation.

PubMed

Crescentini, Marco; Thei, Frederico; Bennati, Marco; Saha, Shimul; de Planque, Maurits R R; Morgan, Hywel; Tartagni, Marco

2015-06-01

Lipid bilayer membrane (BLM) arrays are required for high throughput analysis, for example drug screening or advanced DNA sequencing. Complex microfluidic devices are being developed but these are restricted in terms of array size and structure or have integrated electronic sensing with limited noise performance. We present a compact and scalable multichannel electrophysiology platform based on a hybrid approach that combines integrated state-of-the-art microelectronics with low-cost disposable fluidics providing a platform for high-quality parallel single ion channel recording. Specifically, we have developed a new integrated circuit amplifier based on a novel noise cancellation scheme that eliminates flicker noise derived from devices under test and amplifiers. The system is demonstrated through the simultaneous recording of ion channel activity from eight bilayer membranes. The platform is scalable and could be extended to much larger array sizes, limited only by electronic data decimation and communication capabilities.

Sparsely-Bonded CMOS Hybrid Imager

NASA Technical Reports Server (NTRS)

Sun, Chao (Inventor); Jones, Todd J. (Inventor); Nikzad, Shouleh (Inventor); Newton, Kenneth W. (Inventor); Cunningham, Thomas J. (Inventor); Hancock, Bruce R. (Inventor); Dickie, Matthew R. (Inventor); Hoenk, Michael E. (Inventor); Wrigley, Christopher J. (Inventor); Pain, Bedabrata (Inventor)

2015-01-01

A method and device for imaging or detecting electromagnetic radiation is provided. A device structure includes a first chip interconnected with a second chip. The first chip includes a detector array, wherein the detector array comprises a plurality of light sensors and one or more transistors. The second chip includes a Read Out Integrated Circuit (ROIC) that reads out, via the transistors, a signal produced by the light sensors. A number of interconnects between the ROIC and the detector array can be less than one per light sensor or pixel.

Flexible Multiplexed Surface Temperature Sensor

NASA Technical Reports Server (NTRS)

Daryabeigi, Kamran; Dillon-Townes, L. A.; Johnson, Preston B.; Ash, Robert L.

1995-01-01

Unitary array of sensors measures temperatures at points distributed over designated area on surface. Useful in measuring surface temperatures of aerodynamic models and thermally controlled objects. Made of combination of integrated-circuit microchips and film circuitry. Temperature-sensing chips scanned at speeds approaching 10 kHz. Operating range minus 40 degrees C to 120 degrees C. Flexibility of array conforms to curved surfaces. Multiplexer eliminates numerous monitoring cables. Control of acquisition and recording of data effected by connecting array to microcomputers via suitable interface circuitry.

Method for Fabricating and Packaging an M.Times.N Phased-Array Antenna

NASA Technical Reports Server (NTRS)

Xu, Xiaochuan (Inventor); Chen, Yihong (Inventor); Chen, Ray T. (Inventor); Subbaraman, Harish (Inventor)

2017-01-01

A method for fabricating an M.times.N, P-bit phased-array antenna on a flexible substrate is disclosed. The method comprising ink jet printing and hardening alignment marks, antenna elements, transmission lines, switches, an RF coupler, and multilayer interconnections onto the flexible substrate. The substrate of the M.times.N, P-bit phased-array antenna may comprise an integrated control circuit of printed electronic components such as, photovoltaic cells, batteries, resistors, capacitors, etc. Other embodiments are described and claimed.

Planar waveguide integrated spatial filter array

NASA Astrophysics Data System (ADS)

Ai, Jun; Dimov, Fedor; Lyon, Richard; Rakuljic, Neven; Griffo, Chris; Xia, Xiaowei; Arik, Engin

2013-09-01

An innovative integrated spatial filter array (iSFA) was developed for the nulling interferometer for the detection of earth-like planets and life beyond our solar system. The coherent iSFA comprised a 2D planar lightwave circuit (PLC) array coupled with a pair of 2D lenslet arrays in a hexagonal grid to achieve the optimum fill factor and throughput. The silica-on-silicon waveguide mode field diameter and numerical aperture (NA) were designed to match with the Airy disc and NA of the microlens for optimum coupling. The lenslet array was coated with a chromium pinhole array at the focal plane to pass the single-mode waveguide but attenuate the higher modes. We assembled a 32 by 30 array by stacking 32 chips that were produced by photolithography from a 6-in. silicon wafer. Each chip has 30 planar waveguides. The PLC array is inherently polarization-maintaining (PM) and requires much less alignment in contrast to a fiber array, where each PM fiber must be placed individually and oriented correctly. The PLC array offers better scalability than the fiber bundle array for large arrays of over 1,000 waveguides.

Integration of Si-CMOS embedded photo detector array and mixed signal processing system with embedded optical waveguide input

NASA Astrophysics Data System (ADS)

Kim, Daeik D.; Thomas, Mikkel A.; Brooke, Martin A.; Jokerst, Nan M.

2004-06-01

Arrays of embedded bipolar junction transistor (BJT) photo detectors (PD) and a parallel mixed-signal processing system were fabricated as a silicon complementary metal oxide semiconductor (Si-CMOS) circuit for the integration optical sensors on the surface of the chip. The circuit was fabricated with AMI 1.5um n-well CMOS process and the embedded PNP BJT PD has a pixel size of 8um by 8um. BJT PD was chosen to take advantage of its higher gain amplification of photo current than that of PiN type detectors since the target application is a low-speed and high-sensitivity sensor. The photo current generated by BJT PD is manipulated by mixed-signal processing system, which consists of parallel first order low-pass delta-sigma oversampling analog-to-digital converters (ADC). There are 8 parallel ADCs on the chip and a group of 8 BJT PDs are selected with CMOS switches. An array of PD is composed of three or six groups of PDs depending on the number of rows.

Chaos in a neural network circuit

NASA Astrophysics Data System (ADS)

Kepler, Thomas B.; Datt, Sumeet; Meyer, Robert B.; Abott, L. F.

1990-12-01

We have constructed a neural network circuit of four clipped, high-grain, integrating operational amplifiers coupled to each other through an array of digitally programmable resistor ladders (MDACs). In addition to fixed-point and cyclic behavior, the circuit exhibits chaotic behavior with complex strange attractors which are approached through period doubling, intermittent attractor expansion and/or quasiperiodic pathways. Couplings between the nonlinear circuit elements are controlled by a computer which can automatically search through the space of couplings for interesting phenomena. We report some initial statistical results relating the behavior of the network to properties of its coupling matrix. Through these results and further research the circuit should help resolve fundamental issues concerning chaos in neural networks.

Focal plane infrared readout circuit

NASA Technical Reports Server (NTRS)

Pain, Bedabrata (Inventor)

2002-01-01

An infrared imager, such as a spectrometer, includes multiple infrared photodetectors and readout circuits for reading out signals from the photodetectors. Each readout circuit includes a buffered direct injection input circuit including a differential amplifier with active feedback provided through an injection transistor. The differential amplifier includes a pair of input transistors, a pair of cascode transistors and a current mirror load. Photocurrent from a photodetector can be injected onto an integration capacitor in the readout circuit with high injection efficiency at high speed. A high speed, low noise, wide dynamic range linear infrared multiplexer array for reading out infrared detectors with large capacitances can be achieved even when short exposure times are used. The effect of image lag can be reduced.

Two multichannel integrated circuits for neural recording and signal processing.

PubMed

Obeid, Iyad; Morizio, James C; Moxon, Karen A; Nicolelis, Miguel A L; Wolf, Patrick D

2003-02-01

We have developed, manufactured, and tested two analog CMOS integrated circuit "neurochips" for recording from arrays of densely packed neural electrodes. Device A is a 16-channel buffer consisting of parallel noninverting amplifiers with a gain of 2 V/V. Device B is a 16-channel two-stage analog signal processor with differential amplification and high-pass filtering. It features selectable gains of 250 and 500 V/V as well as reference channel selection. The resulting amplifiers on Device A had a mean gain of 1.99 V/V with an equivalent input noise of 10 microV(rms). Those on Device B had mean gains of 53.4 and 47.4 dB with a high-pass filter pole at 211 Hz and an equivalent input noise of 4.4 microV(rms). Both devices were tested in vivo with electrode arrays implanted in the somatosensory cortex.

A digital optical phase-locked loop for diode lasers based on field programmable gate array.

PubMed

Xu, Zhouxiang; Zhang, Xian; Huang, Kaikai; Lu, Xuanhui

2012-09-01

We have designed and implemented a highly digital optical phase-locked loop (OPLL) for diode lasers in atom interferometry. The three parts of controlling circuit in this OPLL, including phase and frequency detector (PFD), loop filter and proportional integral derivative (PID) controller, are implemented in a single field programmable gate array chip. A structure type compatible with the model MAX9382∕MCH12140 is chosen for PFD and pipeline and parallelism technology have been adapted in PID controller. Especially, high speed clock and twisted ring counter have been integrated in the most crucial part, the loop filter. This OPLL has the narrow beat note line width below 1 Hz, residual mean-square phase error of 0.14 rad(2) and transition time of 100 μs under 10 MHz frequency step. A main innovation of this design is the completely digitalization of the whole controlling circuit in OPLL for diode lasers.

A digital optical phase-locked loop for diode lasers based on field programmable gate array

NASA Astrophysics Data System (ADS)

Xu, Zhouxiang; Zhang, Xian; Huang, Kaikai; Lu, Xuanhui

2012-09-01

We have designed and implemented a highly digital optical phase-locked loop (OPLL) for diode lasers in atom interferometry. The three parts of controlling circuit in this OPLL, including phase and frequency detector (PFD), loop filter and proportional integral derivative (PID) controller, are implemented in a single field programmable gate array chip. A structure type compatible with the model MAX9382/MCH12140 is chosen for PFD and pipeline and parallelism technology have been adapted in PID controller. Especially, high speed clock and twisted ring counter have been integrated in the most crucial part, the loop filter. This OPLL has the narrow beat note line width below 1 Hz, residual mean-square phase error of 0.14 rad2 and transition time of 100 μs under 10 MHz frequency step. A main innovation of this design is the completely digitalization of the whole controlling circuit in OPLL for diode lasers.

Wavelength-division multiplexed optical integrated circuit with vertical diffraction grating

NASA Technical Reports Server (NTRS)

Lang, Robert J. (Inventor); Forouhar, Siamak (Inventor)

1994-01-01

A semiconductor optical integrated circuit for wave division multiplexing has a semiconductor waveguide layer, a succession of diffraction grating points in the waveguide layer along a predetermined diffraction grating contour, a semiconductor diode array in the waveguide layer having plural optical ports facing the succession of diffraction grating points along a first direction, respective semiconductor diodes in the array corresponding to respective ones of a predetermined succession of wavelengths, an optical fiber having one end thereof terminated at the waveguide layer, the one end of the optical fiber facing the succession of diffraction grating points along a second direction, wherein the diffraction grating points are spatially distributed along the predetermined contour in such a manner that the succession of diffraction grating points diffracts light of respective ones of the succession of wavelengths between the one end of the optical fiber and corresponding ones of the optical ports.

Interferometric imaging using Si3N4 photonic integrated circuits for a SPIDER imager.

PubMed

Su, Tiehui; Liu, Guangyao; Badham, Katherine E; Thurman, Samuel T; Kendrick, Richard L; Duncan, Alan; Wuchenich, Danielle; Ogden, Chad; Chriqui, Guy; Feng, Shaoqi; Chun, Jaeyi; Lai, Weicheng; Yoo, S J B

2018-05-14

This paper reports design, fabrication, and experimental demonstration of a silicon nitride photonic integrated circuit (PIC). The PIC is capable of conducting one-dimensional interferometric imaging with twelve baselines near λ = 1100-1600 nm. The PIC consists of twelve waveguide pairs, each leading to a multi-mode interferometer (MMI) that forms broadband interference fringes or each corresponding pair of the waveguides. Then an 18 channel arrayed waveguide grating (AWG) separates the combined signal into 18 signals of different wavelengths. A total of 103 sets of fringes are collected by the detector array at the output of the PIC. We keep the optical path difference (OPD) of each interferometer baseline to within 1 µm to maximize the visibility of the interference measurement. We also constructed a testbed to utilize the PIC for two-dimension complex visibility measurement with various targets. The experiment shows reconstructed images in good agreement with theoretical predictions.

Stacked Metal Silicide/Silicon Far-Infrared Detectors

NASA Technical Reports Server (NTRS)

Maserjian, Joseph

1988-01-01

Selective doping of silicon in proposed metal silicide/silicon Schottky-barrier infrared photodetector increases maximum detectable wavelength. Stacking layers to form multiple Schottky barriers increases quantum efficiency of detector. Detectors of new type enhance capabilities of far-infrared imaging arrays. Grows by molecular-beam epitaxy on silicon waferscontaining very-large-scale integrated circuits. Imaging arrays of detectors made in monolithic units with image-preprocessing circuitry.

Controlling system for smart hyper-spectral imaging array based on liquid-crystal Fabry-Perot device

NASA Astrophysics Data System (ADS)

Jiang, Xue; Chen, Xin; Rong, Xin; Liu, Kan; Zhang, Xinyu; Ji, An; Xie, Changsheng

2011-11-01

A research for developing a kind of smart spectral imaging detection technique based on the electrically tunable liquidcrystal (LC) FP structure is launched. It has some advantages of low cost, highly compact integration, perfuming wavelength selection without moving any micro-mirror of FP device, and the higher reliability and stability. The controlling system for hyper-spectral imaging array based on LC-FP device includes mainly a MSP430F5438 as its core. Considering the characteristics of LC-FP device, the controlling system can provide a driving signal of 1-10 kHz and 0- 30Vrms for the device in a static driving mode. This paper introduces the hardware designing of the control system in detail. It presents an overall hardware solutions including: (1) the MSP430 controlling circuit, and (2) the operational amplifier circuit, and (3) the power supply circuit, and (4) the AD conversion circuit. The techniques for the realization of special high speed digital circuits, which is necessary for the PCB employed, is also discussed.

Alternative Post-Processing on a CMOS Chip to Fabricate a Planar Microelectrode Array

PubMed Central

López-Huerta, Francisco; Herrera-May, Agustín L.; Estrada-López, Johan J.; Zuñiga-Islas, Carlos; Cervantes-Sanchez, Blanca; Soto, Enrique; Soto-Cruz, Blanca S.

2011-01-01

We present an alternative post-processing on a CMOS chip to release a planar microelectrode array (pMEA) integrated with its signal readout circuit, which can be used for monitoring the neuronal activity of vestibular ganglion neurons in newborn Wistar strain rats. This chip is fabricated through a 0.6 μm CMOS standard process and it has 12 pMEA through a 4 × 3 electrodes matrix. The alternative CMOS post-process includes the development of masks to protect the readout circuit and the power supply pads. A wet etching process eliminates the aluminum located on the surface of the p+-type silicon. This silicon is used as transducer for recording the neuronal activity and as interface between the readout circuit and neurons. The readout circuit is composed of an amplifier and tunable bandpass filter, which is placed on a 0.015 mm2 silicon area. The tunable bandpass filter has a bandwidth of 98 kHz and a common mode rejection ratio (CMRR) of 87 dB. These characteristics of the readout circuit are appropriate for neuronal recording applications. PMID:22346681

Alternative post-processing on a CMOS chip to fabricate a planar microelectrode array.

PubMed

López-Huerta, Francisco; Herrera-May, Agustín L; Estrada-López, Johan J; Zuñiga-Islas, Carlos; Cervantes-Sanchez, Blanca; Soto, Enrique; Soto-Cruz, Blanca S

2011-01-01

We present an alternative post-processing on a CMOS chip to release a planar microelectrode array (pMEA) integrated with its signal readout circuit, which can be used for monitoring the neuronal activity of vestibular ganglion neurons in newborn Wistar strain rats. This chip is fabricated through a 0.6 μm CMOS standard process and it has 12 pMEA through a 4 × 3 electrodes matrix. The alternative CMOS post-process includes the development of masks to protect the readout circuit and the power supply pads. A wet etching process eliminates the aluminum located on the surface of the p+ -type silicon. This silicon is used as transducer for recording the neuronal activity and as interface between the readout circuit and neurons. The readout circuit is composed of an amplifier and tunable bandpass filter, which is placed on a 0.015 mm2 silicon area. The tunable bandpass filter has a bandwidth of 98 kHz and a common mode rejection ratio (CMRR) of 87 dB. These characteristics of the readout circuit are appropriate for neuronal recording applications.

Magnetomicrofluidics Circuits for Organizing Bioparticle Arrays

NASA Astrophysics Data System (ADS)

Abedini-Nassab, Roozbeh

Single-cell analysis (SCA) tools have important applications in the analysis of phenotypic heterogeneity, which is difficult or impossible to analyze in bulk cell culture or patient samples. SCA tools thus have a myriad of applications ranging from better credentialing of drug therapies to the analysis of rare latent cells harboring HIV infection or in Cancer. However, existing SCA systems usually lack the required combination of programmability, flexibility, and scalability necessary to enable the study of cell behaviors and cell-cell interactions at the scales sufficient to analyze extremely rare events. To advance the field, I have developed a novel, programmable, and massively-parallel SCA tool which is based on the principles of computer circuits. By integrating these magnetic circuits with microfluidics channels, I developed a platform that can organize a large number of single particles into an array in a controlled manner. My magnetophoretic circuits use passive elements constructed in patterned magnetic thin films to move cells along programmed tracks with an external rotating magnetic field. Cell motion along these tracks is analogous to the motion of charges in an electrical conductor, following a rule similar to Ohm's law. I have also developed asymmetric conductors, similar to electrical diodes, and storage sites for cells that behave similarly to electrical capacitors. I have also developed magnetophoretic circuits which use an overlaid pattern of microwires to switch single cells between different tracks. This switching mechanism, analogous to the operation of electronic transistors, is achieved by establishing a semiconducting gap in the magnetic pattern which can be changed from an insulating state to a conducting state by application of electrical current to an overlaid electrode. I performed an extensive study on the operation of transistors to optimize their geometry and minimize the required gate currents. By combining these elements into integrated circuits, I have built devices which are capable of organizing a precise number of cells into individually addressable array sites, similar to how a random access memory (RAM) stores electronic data. My programmable magnetic circuits allow for the organization of both cells and single-cell pairs into large arrays. Single cells can also potentially be retrieved for downstream high-throughput genomic analysis. In order to enhance the efficiency of the tool and to increase the delivery speed of the particles, I have also developed microfluidics systems that are combined with the magnetophoretic circuits. This hybrid system, called magnetomicrofluidics, is capable of rapidly organizing an array of particles and cells with the high precision and control. I have also shown that cells can be grown inside these chips for multiple days, enabling the long-term phenotypic analysis of rare cellular events. These types of studies can reveal important insights about the intercellular signaling networks and answer crucial questions in biology and immunology.

CMOS-compatible InP/InGaAs digital photoreceiver

DOEpatents

Lovejoy, Michael L.; Rose, Benny H.; Craft, David C.; Enquist, Paul M.; Slater, Jr., David B.

1997-01-01

A digital photoreceiver is formed monolithically on an InP semiconductor substrate and comprises a p-i-n photodetector formed from a plurality of InP/InGaAs layers deposited by an epitaxial growth process and an adjacent heterojunction bipolar transistor (HBT) amplifier formed from the same InP/InGaAs layers. The photoreceiver amplifier operates in a large-signal mode to convert a detected photocurrent signal into an amplified output capable of directly driving integrated circuits such as CMOS. In combination with an optical transmitter, the photoreceiver may be used to establish a short-range channel of digital optical communications between integrated circuits with applications to multi-chip modules (MCMs). The photoreceiver may also be used with fiber optic coupling for establishing longer-range digital communications (i.e. optical interconnects) between distributed computers or the like. Arrays of digital photoreceivers may be formed on a common substrate for establishing a plurality of channels of digital optical communication, with each photoreceiver being spaced by less than about 1 mm and consuming less than about 20 mW of power, and preferably less than about 10 mW. Such photoreceiver arrays are useful for transferring huge amounts of digital data between integrated circuits at bit rates of up to about 1000 Mb/s or more.

CMOS-compatible InP/InGaAs digital photoreceiver

DOEpatents

Lovejoy, M.L.; Rose, B.H.; Craft, D.C.; Enquist, P.M.; Slater, D.B. Jr.

1997-11-04

A digital photoreceiver is formed monolithically on an InP semiconductor substrate and comprises a p-i-n photodetector formed from a plurality of InP/InGaAs layers deposited by an epitaxial growth process and an adjacent heterojunction bipolar transistor (HBT) amplifier formed from the same InP/InGaAs layers. The photoreceiver amplifier operates in a large-signal mode to convert a detected photocurrent signal into an amplified output capable of directly driving integrated circuits such as CMOS. In combination with an optical transmitter, the photoreceiver may be used to establish a short-range channel of digital optical communications between integrated circuits with applications to multi-chip modules (MCMs). The photoreceiver may also be used with fiber optic coupling for establishing longer-range digital communications (i.e. optical interconnects) between distributed computers or the like. Arrays of digital photoreceivers may be formed on a common substrate for establishing a plurality of channels of digital optical communication, with each photoreceiver being spaced by less than about 1 mm and consuming less than about 20 mW of power, and preferably less than about 10 mW. Such photoreceiver arrays are useful for transferring huge amounts of digital data between integrated circuits at bit rates of up to about 1,000 Mb/s or more. 4 figs.

Reconfigurable Cellular Photonic Crystal Arrays (RCPA)

DTIC Science & Technology

2013-03-01

signal processing based on reconfigurable integrated optics devices. This technology has the potential to revolutionize the design circle of optical...Accomplishments III.A. Design and fabrication of an accumulation-mode modulator Figure 1(a) shows the schematic of a compact resonator on the double-Si... integration of silicon nitride on silicon-on-insulator platform to enhance the arsenal of photonic circuit designers . The coherent integration of

Circuit for high resolution decoding of multi-anode microchannel array detectors

NASA Technical Reports Server (NTRS)

Kasle, David B. (Inventor)

1995-01-01

A circuit for high resolution decoding of multi-anode microchannel array detectors consisting of input registers accepting transient inputs from the anode array; anode encoding logic circuits connected to the input registers; midpoint pipeline registers connected to the anode encoding logic circuits; and pixel decoding logic circuits connected to the midpoint pipeline registers is described. A high resolution algorithm circuit operates in parallel with the pixel decoding logic circuit and computes a high resolution least significant bit to enhance the multianode microchannel array detector's spatial resolution by halving the pixel size and doubling the number of pixels in each axis of the anode array. A multiplexer is connected to the pixel decoding logic circuit and allows a user selectable pixel address output according to the actual multi-anode microchannel array detector anode array size. An output register concatenates the high resolution least significant bit onto the standard ten bit pixel address location to provide an eleven bit pixel address, and also stores the full eleven bit pixel address. A timing and control state machine is connected to the input registers, the anode encoding logic circuits, and the output register for managing the overall operation of the circuit.

Three-Dimensional Waveguide Arrays for Coupling Between Fiber-Optic Connectors and Surface-Mounted Optoelectronic Devices

NASA Astrophysics Data System (ADS)

Hiramatsu, Seiki; Kinoshita, Masao

2005-09-01

This paper describes the fabrication of novel surface-mountable waveguide connectors and presents test results for them. To ensure more highly integrated and low-cost fabrication, we propose new three-dimensional (3-D) waveguide arrays that feature two-dimensionally integrated optical inputs/outputs and optical path redirection. A wafer-level stack and lamination process was used to fabricate the waveguide arrays. Vertical-cavity surface-emitting lasers (VCSELs) and photodiodes were directly mounted on the arrays and combined with mechanical transferable ferrule using active alignment. With the help of a flip-chip bonder, the waveguide connectors were mounted on a printed circuit board by solder bumps. Using mechanical transferable connectors, which can easily plug into the waveguide connectors, we obtained multi-gigabits-per-second transmission performance.

Coherent photonic beamformer for a Ka-band phased array antenna receiver implemented in silicon photonic integrated circuit

NASA Astrophysics Data System (ADS)

Duarte, V. C.; Peczek, A.; Drummond, M. V.; Nogueira, R. N.; Winzer, G.; Petousi, D.; Zimmermann, L.

2017-09-01

The generation of satellite communications with flexible and efficient transmission of radio signals requires a large number of low interfering beams and a maximum exploitation of the available frequency spectrum.

Prototype Focal-Plane-Array Optoelectronic Image Processor

NASA Technical Reports Server (NTRS)

Fang, Wai-Chi; Shaw, Timothy; Yu, Jeffrey

1995-01-01

Prototype very-large-scale integrated (VLSI) planar array of optoelectronic processing elements combines speed of optical input and output with flexibility of reconfiguration (programmability) of electronic processing medium. Basic concept of processor described in "Optical-Input, Optical-Output Morphological Processor" (NPO-18174). Performs binary operations on binary (black and white) images. Each processing element corresponds to one picture element of image and located at that picture element. Includes input-plane photodetector in form of parasitic phototransistor part of processing circuit. Output of each processing circuit used to modulate one picture element in output-plane liquid-crystal display device. Intended to implement morphological processing algorithms that transform image into set of features suitable for high-level processing; e.g., recognition.

Design optimization of integrated BiDi triplexer optical filter based on planar lightwave circuit.

PubMed

Xu, Chenglin; Hong, Xiaobin; Huang, Wei-Ping

2006-05-29

Design optimization of a novel integrated bi-directional (BiDi) triplexer filter based on planar lightwave circuit (PLC) for fiber-to-the premise (FTTP) applications is described. A multi-mode interference (MMI) device is used to filter the up-stream 1310nm signal from the down-stream 1490nm and 1555nm signals. An array waveguide grating (AWG) device performs the dense WDM function by further separating the two down-stream signals. The MMI and AWG are built on the same substrate with monolithic integration. The design is validated by simulation, which shows excellent performance in terms of filter spectral characteristics (e.g., bandwidth, cross-talk, etc.) as well as insertion loss.

Design optimization of integrated BiDi triplexer optical filter based on planar lightwave circuit

NASA Astrophysics Data System (ADS)

Xu, Chenglin; Hong, Xiaobin; Huang, Wei-Ping

2006-05-01

Design optimization of a novel integrated bi-directional (BiDi) triplexer filter based on planar lightwave circuit (PLC) for fiber-to-the premise (FTTP) applications is described. A multi-mode interference (MMI) device is used to filter the up-stream 1310nm signal from the down-stream 1490nm and 1555nm signals. An array waveguide grating (AWG) device performs the dense WDM function by further separating the two down-stream signals. The MMI and AWG are built on the same substrate with monolithic integration. The design is validated by simulation, which shows excellent performance in terms of filter spectral characteristics (e.g., bandwidth, cross-talk, etc.) as well as insertion loss.

A readout integrated circuit based on DBI-CTIA and cyclic ADC for MEMS-array-based focal plane

NASA Astrophysics Data System (ADS)

Miao, Liu; Dong, Wu; Zheyao, Wang

2016-11-01

A readout integrated circuit (ROIC) for a MEMS (microelectromechanical system)-array-based focal plane (MAFP) intended for imaging applications is presented. The ROIC incorporates current sources for diode detectors, scanners, timing sequence controllers, differential buffered injection-capacitive trans-impedance amplifier (DBI-CTIA) and 10-bit cyclic ADCs, and is integrated with MAFP using 3-D integration technology. A small-signal equivalent model is built to include thermal detectors into circuit simulations. The biasing current is optimized in terms of signal-to-noise ratio and power consumption. Layout design is tailored to fulfill the requirements of 3-D integration and to adapt to the size of MAFP elements, with not all but only the 2 bottom metal layers to complete nearly all the interconnections in DBI-CTIA and ADC in a 40 μm wide column. Experimental chips are designed and fabricated in a 0.35 μm CMOS mixed signal process, and verified in a code density test of which the results indicate a (0.29/-0.31) LSB differential nonlinearity (DNL) and a (0.61/-0.45) LSB integral nonlinearity (INL). Spectrum analysis shows that the effective number of bits (ENOB) is 9.09. The ROIC consumes 248 mW of power at most if not to cut off quiescent current paths when not needed. Project supported by by National Natural Science Foundation of China (No. 61271130), the Beijing Municipal Science and Tech Project (No. D13110100290000), the Tsinghua University Initiative Scientific Research Program (No. 20131089225), and the Shenzhen Science and Technology Development Fund (No. CXZZ20130322170740736).

Achieving ultra-high temperatures with a resistive emitter array

NASA Astrophysics Data System (ADS)

Danielson, Tom; Franks, Greg; Holmes, Nicholas; LaVeigne, Joe; Matis, Greg; McHugh, Steve; Norton, Dennis; Vengel, Tony; Lannon, John; Goodwin, Scott

2016-05-01

The rapid development of very-large format infrared detector arrays has challenged the IR scene projector community to also develop larger-format infrared emitter arrays to support the testing of systems incorporating these detectors. In addition to larger formats, many scene projector users require much higher simulated temperatures than can be generated with current technology in order to fully evaluate the performance of their systems and associated processing algorithms. Under the Ultra High Temperature (UHT) development program, Santa Barbara Infrared Inc. (SBIR) is developing a new infrared scene projector architecture capable of producing both very large format (>1024 x 1024) resistive emitter arrays and improved emitter pixel technology capable of simulating very high apparent temperatures. During earlier phases of the program, SBIR demonstrated materials with MWIR apparent temperatures in excess of 1400 K. New emitter materials have subsequently been selected to produce pixels that achieve even higher apparent temperatures. Test results from pixels fabricated using the new material set will be presented and discussed. A 'scalable' Read In Integrated Circuit (RIIC) is also being developed under the same UHT program to drive the high temperature pixels. This RIIC will utilize through-silicon via (TSV) and Quilt Packaging (QP) technologies to allow seamless tiling of multiple chips to fabricate very large arrays, and thus overcome the yield limitations inherent in large-scale integrated circuits. Results of design verification testing of the completed RIIC will be presented and discussed.

Development of a 2K x 2K GaAs QWIP Focal Plane Array

NASA Technical Reports Server (NTRS)

Jhabvala, M.; Choi, K.; Jhabvala, C.; Kelly, D.; Hess, L.; Ewin, A.; La, A.; Wacynski, A.; Sun, J.; Adachi, T.;

Design and implementation of Gm-APD array readout integrated circuit for infrared 3D imaging

NASA Astrophysics Data System (ADS)

Zheng, Li-xia; Yang, Jun-hao; Liu, Zhao; Dong, Huai-peng; Wu, Jin; Sun, Wei-feng

2013-09-01

A single-photon detecting array of readout integrated circuit (ROIC) capable of infrared 3D imaging by photon detection and time-of-flight measurement is presented in this paper. The InGaAs avalanche photon diodes (APD) dynamic biased under Geiger operation mode by gate controlled active quenching circuit (AQC) are used here. The time-of-flight is accurately measured by a high accurate time-to-digital converter (TDC) integrated in the ROIC. For 3D imaging, frame rate controlling technique is utilized to the pixel's detection, so that the APD related to each pixel should be controlled by individual AQC to sense and quench the avalanche current, providing a digital CMOS-compatible voltage pulse. After each first sense, the detector is reset to wait for next frame operation. We employ counters of a two-segmental coarse-fine architecture, where the coarse conversion is achieved by a 10-bit pseudo-random linear feedback shift register (LFSR) in each pixel and a 3-bit fine conversion is realized by a ring delay line shared by all pixels. The reference clock driving the LFSR counter can be generated within the ring delay line Oscillator or provided by an external clock source. The circuit is designed and implemented by CSMC 0.5μm standard CMOS technology and the total chip area is around 2mm×2mm for 8×8 format ROIC with 150μm pixel pitch. The simulation results indicate that the relative time resolution of the proposed ROIC can achieve less than 1ns, and the preliminary test results show that the circuit function is correct.

Super-Lattice Light Emitting Diodes (SLEDS) on GaAs

DTIC Science & Technology

2016-03-31

Super-Lattice Light Emitting Diodes (SLEDS) on GaAs Kassem Nabha1, Russel Ricker2, Rodney McGee1, Nick Waite1, John Prineas2, Sydney Provence2...infrared light emitting diodes (LEDs). Typically, the LED arrays are mated with CMOS read-in integrated circuit (RIIC) chips using flip-chip bonding. In...circuit (RIIC) chips using flip-chip bonding. This established technology is called Hybrid-super-lattice light emitting diodes (Hybrid- SLEDS). In

Monolithic in-based III-V compound semiconductor focal plane array cell with single stage CCD output

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Cunningham, Thomas J. (Inventor); Krabach, Timothy N. (Inventor); Staller, Craig O. (Inventor)

1994-01-01

A monolithic semiconductor imager includes an indium-based III-V compound semiconductor monolithic active layer of a first conductivity type, an array of plural focal plane cells on the active layer, each of the focal plane cells including a photogate over a top surface of the active layer, a readout circuit dedicated to the focal plane cell including plural transistors formed monolithically with the monolithic active layer and a single-stage charge coupled device formed monolithically with the active layer between the photogate and the readout circuit for transferring photo-generated charge accumulated beneath the photogate during an integration period to the readout circuit. The photogate includes thin epitaxial semiconductor layer of a second conductivity type overlying the active layer and an aperture electrode overlying a peripheral portion of the thin epitaxial semiconductor layer, the aperture electrode being connectable to a photogate bias voltage.

Proceedings of the Antenna Applications Symposium (1993). Volume 1

DTIC Science & Technology

1994-02-01

Technology - Past and Future," by J. K. Schindler 2. * " Integrated Circuit Active Phased Array Antennas for Millimeter Wave Communications Applications...High Gain Antenna System has become the market leader in commercial aircraft installations. Two side-mounted phased arrays are employed on a single...production cost to be competitive in commercial markets . Antenna pattern and system performance are presented in this paper. 23 1.0 INTRODUCTION As

Design and realization of 144 x 7 TDI ROIC with hybrid integrated test structure

NASA Astrophysics Data System (ADS)

Ceylan, Omer; Kayahan, Huseyin; Yazici, Melik; Baran, Muhammet Burak; Gurbuz, Yasar

2012-06-01

Design and realization of a 144x7 silicon readout integrated circuit (ROIC) based on switched capacitor TDI for MCT LWIR scanning type focal plane arrays (FPAs) and its corresponding hybrid integrated test circuits are presented. TDI operation with 7 detectors improves the SNR of the system by a factor of √7, while oversampling rate of 3 improves the spatial resolution of the system. ROIC supports bidirectional scan, 5 adjustable gain settings, bypass operation, automatic gain adjustment in case of mulfunctioning pixels and pixel select/deselect properties. Integration time of the system can be determined by the help of an external clock. Programming of ROIC can be done in parallel or serial mode according to the needs of the system. All properties except pixel select/deselect property can be performed in parallel mode, while pixel select/deselect property can be performed only in serial mode. ROIC can handle up to 3.75V dynamic range with a load of 25pF and output settling time of 80ns. Input referred noise of the ROIC is less than 750 rms electrons, while the power consumption is less than 100mW. To test ROIC in absence of detector array, a process and temperature compensated current reference array, which supplies uniform input current in range of 1-50nA to ROIC, is designed and measured both in room and cryogenic (77ºK) temperatures. Standard deviations of current reference arrays are measured 3.26% for 1nA and 0.99% for 50nA. ROIC and current reference array are fabricated seperately, and then flip-chip bonded for the test of the system. Flip-chip bonded system including ROIC and current reference test array is successfully measured both in room and cryogenic temperatures, and measurement results are presented. The manufacturing technology is 0.35μm, double poly-Si, four metal, 5V CMOS process.

Lead sulfide - Silicon MOSFET infrared focal plane development

NASA Technical Reports Server (NTRS)

Barrett, J. R.; Jhabvala, M. D.

1983-01-01

A process for directly integrating photoconductive lead sulfide (PbS) infrared detector material with silicon MOS integrated circuits has been developed primarily for application in long (greater than 10,000 detector elements) linear arrays for pushbroom scanning applications. The processing technology is based on the conventional PMOS and CMOS technologies with a variation in the metallization. Results and measurements on a fully integrated eight-element multiplexer are shown.

Field-programmable lab-on-a-chip based on microelectrode dot array architecture.

PubMed

Wang, Gary; Teng, Daniel; Lai, Yi-Tse; Lu, Yi-Wen; Ho, Yingchieh; Lee, Chen-Yi

2014-09-01

The fundamentals of electrowetting-on-dielectric (EWOD) digital microfluidics are very strong: advantageous capability in the manipulation of fluids, small test volumes, precise dynamic control and detection, and microscale systems. These advantages are very important for future biochip developments, but the development of EWOD microfluidics has been hindered by the absence of: integrated detector technology, standard commercial components, on-chip sample preparation, standard manufacturing technology and end-to-end system integration. A field-programmable lab-on-a-chip (FPLOC) system based on microelectrode dot array (MEDA) architecture is presented in this research. The MEDA architecture proposes a standard EWOD microfluidic component called 'microelectrode cell', which can be dynamically configured into microfluidic components to perform microfluidic operations of the biochip. A proof-of-concept prototype FPLOC, containing a 30 × 30 MEDA, was developed by using generic integrated circuits computer aided design tools, and it was manufactured with standard low-voltage complementary metal-oxide-semiconductor technology, which allows smooth on-chip integration of microfluidics and microelectronics. By integrating 900 droplet detection circuits into microelectrode cells, the FPLOC has achieved large-scale integration of microfluidics and microelectronics. Compared to the full-custom and bottom-up design methods, the FPLOC provides hierarchical top-down design approach, field-programmability and dynamic manipulations of droplets for advanced microfluidic operations.

MMIC devices for active phased array antennas

NASA Technical Reports Server (NTRS)

Mittra, R.

1986-01-01

The use of finlines for microwave monolithic integrated circuit application in the 20 to 40 GHz frequency range. Other wave guiding structures, are also examined from a comparative point of view and some sonclusions are drawn on the basis of the results.

Telecom-Wavelength Bottom-up Nanobeam Lasers on Silicon-on-Insulator.

PubMed

Kim, Hyunseok; Lee, Wook-Jae; Farrell, Alan C; Balgarkashi, Akshay; Huffaker, Diana L

2017-09-13

Semiconductor nanowire lasers are considered promising ultracompact and energy-efficient light sources in the field of nanophotonics. Although the integration of nanowire lasers onto silicon photonic platforms is an innovative path toward chip-scale optical communications and photonic integrated circuits, operating nanowire lasers at telecom-wavelengths remains challenging. Here, we report on InGaAs nanowire array lasers on a silicon-on-insulator platform operating up to 1440 nm at room temperature. Bottom-up photonic crystal nanobeam cavities are formed by growing nanowires as ordered arrays using selective-area epitaxy, and single-mode lasing by optical pumping is demonstrated. We also show that arrays of nanobeam lasers with individually tunable wavelengths can be integrated on a single chip by the simple adjustment of the lithographically defined growth pattern. These results exemplify a practical approach toward nanowire lasers for silicon photonics.

Apparatus And Method Of Using Flexible Printed Circuit Board In Optical Transceiver Device

DOEpatents

Anderson, Gene R.; Armendariz, Marcelino G.; Bryan, Robert P.; Carson, Richard F.; Duckett, III, Edwin B.; McCormick, Frederick B.; Peterson, David W.; Peterson, Gary D.; Reysen, Bill H.

2005-03-15

This invention relates to a flexible printed circuit board that is used in connection with an optical transmitter, receiver or transceiver module. In one embodiment, the flexible printed circuit board has flexible metal layers in between flexible insulating layers, and the circuit board comprises: (1) a main body region orientated in a first direction having at least one electrical or optoelectronic device; (2) a plurality of electrical contact pads integrated into the main body region, where the electrical contact pads function to connect the flexible printed circuit board to an external environment; (3) a buckle region extending from one end of the main body region; and (4) a head region extending from one end of the buckle region, and where the head region is orientated so that it is at an angle relative to the direction of the main body region. The electrical contact pads may be ball grid arrays, solder balls or land-grid arrays, and they function to connect the circuit board to an external environment. A driver or amplifier chip may be adapted to the head region of the flexible printed circuit board. In another embodiment, a heat spreader passes along a surface of the head region of the flexible printed circuit board, and a window is formed in the head region of the flexible printed circuit board. Optoelectronic devices are adapted to the head spreader in such a manner that they are accessible through the window in the flexible printed circuit board.

Optical detectors for GaAs MMIC integration: Technology assessment

NASA Technical Reports Server (NTRS)

Claspy, P. C.; Bhasin, K. B.

1989-01-01

Fiber optic links are being considered to transmit digital and analog signals in phased array antenna feed networks in space communications systems. The radiating elements in these arrays will be GaAs monolithic microwave integrated circuits (MMIC's) in numbers ranging from a few hundred to several thousand. If such optical interconnects are to be practical it appears essential that the associated components, including detectors, be monolithically integrated on the same chip as the microwave circuitry. The general issue of monolithic integration of microwave and optoelectronic components is addressed from the point of view of fabrication technology and compatibility. Particular attention is given to the fabrication technology of various types of GaAs optical detectors that are designed to operate at a wavelength of 830 nm.

A hybrid nanomemristor/transistor logic circuit capable of self-programming

PubMed Central

Borghetti, Julien; Li, Zhiyong; Straznicky, Joseph; Li, Xuema; Ohlberg, Douglas A. A.; Wu, Wei; Stewart, Duncan R.; Williams, R. Stanley

2009-01-01

Memristor crossbars were fabricated at 40 nm half-pitch, using nanoimprint lithography on the same substrate with Si metal-oxide-semiconductor field effect transistor (MOS FET) arrays to form fully integrated hybrid memory resistor (memristor)/transistor circuits. The digitally configured memristor crossbars were used to perform logic functions, to serve as a routing fabric for interconnecting the FETs and as the target for storing information. As an illustrative demonstration, the compound Boolean logic operation (A AND B) OR (C AND D) was performed with kilohertz frequency inputs, using resistor-based logic in a memristor crossbar with FET inverter/amplifier outputs. By routing the output signal of a logic operation back onto a target memristor inside the array, the crossbar was conditionally configured by setting the state of a nonvolatile switch. Such conditional programming illuminates the way for a variety of self-programmed logic arrays, and for electronic synaptic computing. PMID:19171903

A hybrid nanomemristor/transistor logic circuit capable of self-programming.

PubMed

Borghetti, Julien; Li, Zhiyong; Straznicky, Joseph; Li, Xuema; Ohlberg, Douglas A A; Wu, Wei; Stewart, Duncan R; Williams, R Stanley

2009-02-10

Memristor crossbars were fabricated at 40 nm half-pitch, using nanoimprint lithography on the same substrate with Si metal-oxide-semiconductor field effect transistor (MOS FET) arrays to form fully integrated hybrid memory resistor (memristor)/transistor circuits. The digitally configured memristor crossbars were used to perform logic functions, to serve as a routing fabric for interconnecting the FETs and as the target for storing information. As an illustrative demonstration, the compound Boolean logic operation (A AND B) OR (C AND D) was performed with kilohertz frequency inputs, using resistor-based logic in a memristor crossbar with FET inverter/amplifier outputs. By routing the output signal of a logic operation back onto a target memristor inside the array, the crossbar was conditionally configured by setting the state of a nonvolatile switch. Such conditional programming illuminates the way for a variety of self-programmed logic arrays, and for electronic synaptic computing.

Multi-electrode array technologies for neuroscience and cardiology

NASA Astrophysics Data System (ADS)

Spira, Micha E.; Hai, Aviad

2013-02-01

At present, the prime methodology for studying neuronal circuit-connectivity, physiology and pathology under in vitro or in vivo conditions is by using substrate-integrated microelectrode arrays. Although this methodology permits simultaneous, cell-non-invasive, long-term recordings of extracellular field potentials generated by action potentials, it is 'blind' to subthreshold synaptic potentials generated by single cells. On the other hand, intracellular recordings of the full electrophysiological repertoire (subthreshold synaptic potentials, membrane oscillations and action potentials) are, at present, obtained only by sharp or patch microelectrodes. These, however, are limited to single cells at a time and for short durations. Recently a number of laboratories began to merge the advantages of extracellular microelectrode arrays and intracellular microelectrodes. This Review describes the novel approaches, identifying their strengths and limitations from the point of view of the end users -- with the intention to help steer the bioengineering efforts towards the needs of brain-circuit research.

Nuclear resonant scattering measurements on (57)Fe by multichannel scaling with a 64-pixel silicon avalanche photodiode linear-array detector.

PubMed

Kishimoto, S; Mitsui, T; Haruki, R; Yoda, Y; Taniguchi, T; Shimazaki, S; Ikeno, M; Saito, M; Tanaka, M

2014-11-01

We developed a silicon avalanche photodiode (Si-APD) linear-array detector for use in nuclear resonant scattering experiments using synchrotron X-rays. The Si-APD linear array consists of 64 pixels (pixel size: 100 × 200 μm(2)) with a pixel pitch of 150 μm and depletion depth of 10 μm. An ultrafast frontend circuit allows the X-ray detector to obtain a high output rate of >10(7) cps per pixel. High-performance integrated circuits achieve multichannel scaling over 1024 continuous time bins with a 1 ns resolution for each pixel without dead time. The multichannel scaling method enabled us to record a time spectrum of the 14.4 keV nuclear radiation at each pixel with a time resolution of 1.4 ns (FWHM). This method was successfully applied to nuclear forward scattering and nuclear small-angle scattering on (57)Fe.

Multi-electrode array technologies for neuroscience and cardiology.

PubMed

Spira, Micha E; Hai, Aviad

2013-02-01

At present, the prime methodology for studying neuronal circuit-connectivity, physiology and pathology under in vitro or in vivo conditions is by using substrate-integrated microelectrode arrays. Although this methodology permits simultaneous, cell-non-invasive, long-term recordings of extracellular field potentials generated by action potentials, it is 'blind' to subthreshold synaptic potentials generated by single cells. On the other hand, intracellular recordings of the full electrophysiological repertoire (subthreshold synaptic potentials, membrane oscillations and action potentials) are, at present, obtained only by sharp or patch microelectrodes. These, however, are limited to single cells at a time and for short durations. Recently a number of laboratories began to merge the advantages of extracellular microelectrode arrays and intracellular microelectrodes. This Review describes the novel approaches, identifying their strengths and limitations from the point of view of the end users--with the intention to help steer the bioengineering efforts towards the needs of brain-circuit research.

A low power, area efficient fpga based beamforming technique for 1-D CMUT arrays.

PubMed

Joseph, Bastin; Joseph, Jose; Vanjari, Siva Rama Krishna

2015-08-01

A low power area efficient digital beamformer targeting low frequency (2MHz) 1-D linear Capacitive Micromachined Ultrasonic Transducer (CMUT) array is developed. While designing the beamforming logic, the symmetry of the CMUT array is well exploited to reduce the area and power consumption. The proposed method is verified in Matlab by clocking an Arbitrary Waveform Generator(AWG). The architecture is successfully implemented in Xilinx Spartan 3E FPGA kit to check its functionality. The beamforming logic is implemented for 8, 16, 32, and 64 element CMUTs targeting Application Specific Integrated Circuit (ASIC) platform at Vdd 1.62V for UMC 90nm technology. It is observed that the proposed architecture consumes significantly lesser power and area (1.2895 mW power and 47134.4 μm(2) area for a 64 element digital beamforming circuit) compared to the conventional square root based algorithm.

Halbach array-based design and simulation of disc coreless permanen-magnet integrated starter generator

NASA Astrophysics Data System (ADS)

Li, Y. B.; Yang, Z. X.; Chen, W.; He, Q. Y.

2017-11-01

The functional performance, such as magnetic flux leakage, power density and efficiency, is related to the structural characteristics and design technique for the disc permanent magnet synchronous generators (PMSGs). Halbach array theory-based magnetic circuit structure is developed, and Maxwell3D simulation analysis approach of PMSG is proposed in this paper for integrated starter generator (ISG). The magnetization direction of adjacent permanent magnet is organized in difference of 45 degrees for focusing air gap side, and improving the performance of the generator. The magnetic field distribution and functional performance in load and/or unload conditions are simulated by Maxwell3D module. The proposed approach is verified by simulation analysis, the air gap flux density is 0.66T, and the phase voltage curve has the characteristics of a preferable sinusoidal wave and the voltage amplitude 335V can meet the design requirements while the disc coreless PMSG is operating at rated speed. And the developed magnetic circuit structure can be used for engineering design of the disc coreless PMSG to the integrated starter generator.

Low-noise heterodyne receiver for electron cyclotron emission imaging and microwave imaging reflectometry

NASA Astrophysics Data System (ADS)

Tobias, B.; Domier, C. W.; Luhmann, N. C.; Luo, C.; Mamidanna, M.; Phan, T.; Pham, A.-V.; Wang, Y.

2016-11-01

The critical component enabling electron cyclotron emission imaging (ECEI) and microwave imaging reflectometry (MIR) to resolve 2D and 3D electron temperature and density perturbations is the heterodyne imaging array that collects and downconverts radiated emission and/or reflected signals (50-150 GHz) to an intermediate frequency (IF) band (e.g. 0.1-18 GHz) that can be transmitted by a shielded coaxial cable for further filtering and detection. New circuitry has been developed for this task, integrating gallium arsenide (GaAs) monolithic microwave integrated circuits (MMICs) mounted on a liquid crystal polymer (LCP) substrate. The improved topology significantly increases electromagnetic shielding from out-of-band interference, leads to 10× improvement in the signal-to-noise ratio, and dramatic cost savings through integration. The current design, optimized for reflectometry and edge radiometry on mid-sized tokamaks, has demonstrated >20 dB conversion gain in upper V-band (60-75 GHz). Implementation of the circuit in a multi-channel electron cyclotron emission imaging (ECEI) array will improve the diagnosis of edge-localized modes and fluctuations of the high-confinement, or H-mode, pedestal.

A miniaturized neuroprosthesis suitable for implantation into the brain

NASA Technical Reports Server (NTRS)

Mojarradi, Mohammad; Binkley, David; Blalock, Benjamin; Andersen, Richard; Ulshoefer, Norbert; Johnson, Travis; Del Castillo, Linda

2003-01-01

This paper presents current research on a miniaturized neuroprosthesis suitable for implantation into the brain. The prosthesis is a heterogeneous integration of a 100-element microelectromechanical system (MEMS) electrode array, front-end complementary metal-oxide-semiconductor (CMOS) integrated circuit for neural signal preamplification, filtering, multiplexing and analog-to-digital conversion, and a second CMOS integrated circuit for wireless transmission of neural data and conditioning of wireless power. The prosthesis is intended for applications where neural signals are processed and decoded to permit the control of artificial or paralyzed limbs. This research, if successful, will allow implantation of the electronics into the brain, or subcutaneously on the skull, and eliminate all external signal and power wiring. The neuroprosthetic system design has strict size and power constraints with each of the front-end preamplifier channels fitting within the 400 x 400-microm pitch of the 100-element MEMS electrode array and power dissipation resulting in less than a 1 degree C temperature rise for the surrounding brain tissue. We describe the measured performance of initial micropower low-noise CMOS preamplifiers for the neuroprosthetic.

Low-noise heterodyne receiver for electron cyclotron emission imaging and microwave imaging reflectometry.

PubMed

Tobias, B; Domier, C W; Luhmann, N C; Luo, C; Mamidanna, M; Phan, T; Pham, A-V; Wang, Y

2016-11-01

The critical component enabling electron cyclotron emission imaging (ECEI) and microwave imaging reflectometry (MIR) to resolve 2D and 3D electron temperature and density perturbations is the heterodyne imaging array that collects and downconverts radiated emission and/or reflected signals (50-150 GHz) to an intermediate frequency (IF) band (e.g. 0.1-18 GHz) that can be transmitted by a shielded coaxial cable for further filtering and detection. New circuitry has been developed for this task, integrating gallium arsenide (GaAs) monolithic microwave integrated circuits (MMICs) mounted on a liquid crystal polymer (LCP) substrate. The improved topology significantly increases electromagnetic shielding from out-of-band interference, leads to 10× improvement in the signal-to-noise ratio, and dramatic cost savings through integration. The current design, optimized for reflectometry and edge radiometry on mid-sized tokamaks, has demonstrated >20 dB conversion gain in upper V-band (60-75 GHz). Implementation of the circuit in a multi-channel electron cyclotron emission imaging (ECEI) array will improve the diagnosis of edge-localized modes and fluctuations of the high-confinement, or H-mode, pedestal.

Enhancing Light Emission of ZnO-Nanofilm/Si-Micropillar Heterostructure Arrays by Piezo-Phototronic Effect.

PubMed

Li, Xiaoyi; Chen, Mengxiao; Yu, Ruomeng; Zhang, Taiping; Song, Dongsheng; Liang, Renrong; Zhang, Qinglin; Cheng, Shaobo; Dong, Lin; Pan, Anlian; Wang, Zhong Lin; Zhu, Jing; Pan, Caofeng

2015-06-22

n-ZnO nanofilm/p-Si micropillar heterostructure light-emitting diode (LED) arrays for white light emissions are achieved and the light emission intensity of LED array is enhanced by 120% under -0.05% compressive strains. These results indicate a promising approach to fabricate Si-based light-emitting components with high performances enhanced by piezo-phototronic effect, with potential applications in touchpad technology, personalized signatures, smart skin, and silicon-based photonic integrated circuits. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Design of Low Power CMOS Read-Out with TDI Function for Infrared Linear Photodiode Array Detectors

NASA Technical Reports Server (NTRS)

Vizcaino, Paul; Ramirez-Angulo, Jaime; Patel, Umesh D.

2007-01-01

A new low voltage CMOS infrared readout circuit using the buffer-direct injection method is presented. It uses a single supply voltage of 1.8 volts and a bias current of 1uA. The time-delay integration technique is used to increase the signal to noise ratio. A current memory circuit with faulty diode detection is used to remove dark current for background compensation and to disable a photodiode in a cell if detected as faulty. Simulations are shown that verify the circuit that is currently in fabrication in 0.5ym CMOS technology.

Wavelength selective switch array employing silica-based waveguide frontend with integrated polarization diversity optics.

PubMed

Sakamaki, Yohei; Shikama, Kota; Ikuma, Yuichiro; Suzuki, Kenya

2017-08-21

We propose a waveguide frontend with integrated polarization diversity optics for a wavelength selective switch (WSS) array with a liquid crystal on silicon switching engine to simplify the free space optics configuration and the alignment process in optical modules. The polarization diversity function is realized by the integration of a waveguide-type polarization beam splitter and a polarization rotating half-wave plate in a beam launcher using silica-based planar lightwave circuit technology. We confirmed experimentally the feasibility of using our proposed waveguide frontend in a two-in-one 1 × 20 WSS. The experimental results show that the fabricated waveguide frontend provides a polarization diversity function without any degradation in optical performance.

3D imaging LADAR with linear array devices: laser, detector and ROIC

NASA Astrophysics Data System (ADS)

Kameyama, Shumpei; Imaki, Masaharu; Tamagawa, Yasuhisa; Akino, Yosuke; Hirai, Akihito; Ishimura, Eitaro; Hirano, Yoshihito

2009-07-01

This paper introduces the recent development of 3D imaging LADAR (LAser Detection And Ranging) in Mitsubishi Electric Corporation. The system consists of in-house-made key devices which are linear array: the laser, the detector and the ROIC (Read-Out Integrated Circuit). The laser transmitter is the high power and compact planar waveguide array laser at the wavelength of 1.5 micron. The detector array consists of the low excess noise Avalanche Photo Diode (APD) using the InAlAs multiplication layer. The analog ROIC array, which is fabricated in the SiGe- BiCMOS process, includes the Trans-Impedance Amplifiers (TIA), the peak intensity detectors, the Time-Of-Flight (TOF) detectors, and the multiplexers for read-out. This device has the feature in its detection ability for the small signal by optimizing the peak intensity detection circuit. By combining these devices with the one dimensional fast scanner, the real-time 3D range image can be obtained. After the explanations about the key devices, some 3D imaging results are demonstrated using the single element key devices. The imaging using the developed array devices is planned in the near future.

Energy-efficient STDP-based learning circuits with memristor synapses

NASA Astrophysics Data System (ADS)

Wu, Xinyu; Saxena, Vishal; Campbell, Kristy A.

2014-05-01

It is now accepted that the traditional von Neumann architecture, with processor and memory separation, is ill suited to process parallel data streams which a mammalian brain can efficiently handle. Moreover, researchers now envision computing architectures which enable cognitive processing of massive amounts of data by identifying spatio-temporal relationships in real-time and solving complex pattern recognition problems. Memristor cross-point arrays, integrated with standard CMOS technology, are expected to result in massively parallel and low-power Neuromorphic computing architectures. Recently, significant progress has been made in spiking neural networks (SNN) which emulate data processing in the cortical brain. These architectures comprise of a dense network of neurons and the synapses formed between the axons and dendrites. Further, unsupervised or supervised competitive learning schemes are being investigated for global training of the network. In contrast to a software implementation, hardware realization of these networks requires massive circuit overhead for addressing and individually updating network weights. Instead, we employ bio-inspired learning rules such as the spike-timing-dependent plasticity (STDP) to efficiently update the network weights locally. To realize SNNs on a chip, we propose to use densely integrating mixed-signal integrate-andfire neurons (IFNs) and cross-point arrays of memristors in back-end-of-the-line (BEOL) of CMOS chips. Novel IFN circuits have been designed to drive memristive synapses in parallel while maintaining overall power efficiency (<1 pJ/spike/synapse), even at spike rate greater than 10 MHz. We present circuit design details and simulation results of the IFN with memristor synapses, its response to incoming spike trains and STDP learning characterization.

Analog storage integrated circuit

DOEpatents

Walker, J. T.; Larsen, R. S.; Shapiro, S. L.

1989-01-01

A high speed data storage array is defined utilizing a unique cell design for high speed sampling of a rapidly changing signal. Each cell of the array includes two input gates between the signal input and a storage capacitor. The gates are controlled by a high speed row clock and low speed column clock so that the instantaneous analog value of the signal is only sampled and stored by each cell on coincidence of the two clocks.

Analog storage integrated circuit

DOEpatents

Walker, J.T.; Larsen, R.S.; Shapiro, S.L.

1989-03-07

A high speed data storage array is defined utilizing a unique cell design for high speed sampling of a rapidly changing signal. Each cell of the array includes two input gates between the signal input and a storage capacitor. The gates are controlled by a high speed row clock and low speed column clock so that the instantaneous analog value of the signal is only sampled and stored by each cell on coincidence of the two clocks. 6 figs.

Memristor-CMOS hybrid integrated circuits for reconfigurable logic.

PubMed

Xia, Qiangfei; Robinett, Warren; Cumbie, Michael W; Banerjee, Neel; Cardinali, Thomas J; Yang, J Joshua; Wu, Wei; Li, Xuema; Tong, William M; Strukov, Dmitri B; Snider, Gregory S; Medeiros-Ribeiro, Gilberto; Williams, R Stanley

2009-10-01

Hybrid reconfigurable logic circuits were fabricated by integrating memristor-based crossbars onto a foundry-built CMOS (complementary metal-oxide-semiconductor) platform using nanoimprint lithography, as well as materials and processes that were compatible with the CMOS. Titanium dioxide thin-film memristors served as the configuration bits and switches in a data routing network and were connected to gate-level CMOS components that acted as logic elements, in a manner similar to a field programmable gate array. We analyzed the chips using a purpose-built testing system, and demonstrated the ability to configure individual devices, use them to wire up various logic gates and a flip-flop, and then reconfigure devices.

Optically controlled phased array antenna concepts using GaAs monolithic microwave integrated circuits

NASA Technical Reports Server (NTRS)

Kunath, R. R.; Bhasin, K. B.

1986-01-01

The desire for rapid beam reconfigurability and steering has led to the exploration of new techniques. Optical techniques have been suggested as potential candidates for implementing these needs. Candidates generally fall into one of two areas: those using fiber optic Beam Forming Networks (BFNs) and those using optically processed BFNs. Both techniques utilize GaAs Monolithic Microwave Integrated Circuits (MMICs) in the BFN, but the role of the MMIC for providing phase and amplitude variations is largely eliminated by some new optical processing techniques. This paper discusses these two types of optical BFN designs and provides conceptual designs of both systems.

High Voltage Dielectrophoretic and Magnetophoretic Hybrid Integrated Circuit / Microfluidic Chip

PubMed Central

Issadore, David; Franke, Thomas; Brown, Keith A.; Hunt, Thomas P.; Westervelt, Robert M.

2010-01-01

A hybrid integrated circuit (IC) / microfluidic chip is presented that independently and simultaneously traps and moves microscopic objects suspended in fluid using both electric and magnetic fields. This hybrid chip controls the location of dielectric objects, such as living cells and drops of fluid, on a 60 × 61 array of pixels that are 30 × 38 μm2 in size, each of which can be individually addressed with a 50 V peak-to-peak, DC to 10 MHz radio frequency voltage. These high voltage pixels produce electric fields above the chip’s surface with a magnitude , resulting in strong dielectrophoresis (DEP) forces . Underneath the array of DEP pixels there is a magnetic matrix that consists of two perpendicular sets of 60 metal wires running across the chip. Each wire can be sourced with 120 mA to trap and move magnetically susceptible objects using magnetophoresis (MP). The DEP pixel array and magnetic matrix can be used simultaneously to apply forces to microscopic objects, such as living cells or lipid vesicles, that are tagged with magnetic nanoparticles. The capabilities of the hybrid IC / microfluidic chip demonstrated in this paper provide important building blocks for a platform for biological and chemical applications. PMID:20625468

Fully digital routing logic for single-photon avalanche diode arrays in highly efficient time-resolved imaging

NASA Astrophysics Data System (ADS)

Cominelli, Alessandro; Acconcia, Giulia; Ghioni, Massimo; Rech, Ivan

2018-03-01

Time-correlated single-photon counting (TCSPC) is a powerful optical technique, which permits recording fast luminous signals with picosecond precision. Unfortunately, given its repetitive nature, TCSPC is recognized as a relatively slow technique, especially when a large time-resolved image has to be recorded. In recent years, there has been a fast trend toward the development of TCPSC imagers. Unfortunately, present systems still suffer from a trade-off between number of channels and performance. Even worse, the overall measurement speed is still limited well below the saturation of the transfer bandwidth toward the external processor. We present a routing algorithm that enables a smart connection between a 32×32 detector array and five shared high-performance converters able to provide an overall conversion rate up to 10 Gbit/s. The proposed solution exploits a fully digital logic circuit distributed in a tree structure to limit the number and length of interconnections, which is a major issue in densely integrated circuits. The behavior of the logic has been validated by means of a field-programmable gate array, while a fully integrated prototype has been designed in 180-nm technology and analyzed by means of postlayout simulations.

High Voltage Dielectrophoretic and Magnetophoretic Hybrid Integrated Circuit / Microfluidic Chip.

PubMed

Issadore, David; Franke, Thomas; Brown, Keith A; Hunt, Thomas P; Westervelt, Robert M

2009-12-01

A hybrid integrated circuit (IC) / microfluidic chip is presented that independently and simultaneously traps and moves microscopic objects suspended in fluid using both electric and magnetic fields. This hybrid chip controls the location of dielectric objects, such as living cells and drops of fluid, on a 60 × 61 array of pixels that are 30 × 38 μm(2) in size, each of which can be individually addressed with a 50 V peak-to-peak, DC to 10 MHz radio frequency voltage. These high voltage pixels produce electric fields above the chip's surface with a magnitude , resulting in strong dielectrophoresis (DEP) forces . Underneath the array of DEP pixels there is a magnetic matrix that consists of two perpendicular sets of 60 metal wires running across the chip. Each wire can be sourced with 120 mA to trap and move magnetically susceptible objects using magnetophoresis (MP). The DEP pixel array and magnetic matrix can be used simultaneously to apply forces to microscopic objects, such as living cells or lipid vesicles, that are tagged with magnetic nanoparticles. The capabilities of the hybrid IC / microfluidic chip demonstrated in this paper provide important building blocks for a platform for biological and chemical applications.

A Low Noise CMOS Readout Based on a Polymer-Coated SAW Array for Miniature Electronic Nose

PubMed Central

Wu, Cheng-Chun; Liu, Szu-Chieh; Chiu, Shih-Wen; Tang, Kea-Tiong

2016-01-01

An electronic nose (E-Nose) is one of the applications for surface acoustic wave (SAW) sensors. In this paper, we present a low-noise complementary metal–oxide–semiconductor (CMOS) readout application-specific integrated circuit (ASIC) based on an SAW sensor array for achieving a miniature E-Nose. The center frequency of the SAW sensors was measured to be approximately 114 MHz. Because of interference between the sensors, we designed a low-noise CMOS frequency readout circuit to enable the SAW sensor to obtain frequency variation. The proposed circuit was fabricated in Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 μm 1P6M CMOS process technology. The total chip size was nearly 1203 × 1203 μm2. The chip was operated at a supply voltage of 1 V for a digital circuit and 1.8 V for an analog circuit. The least measurable difference between frequencies was 4 Hz. The detection limit of the system, when estimated using methanol and ethanol, was 0.1 ppm. Their linearity was in the range of 0.1 to 26,000 ppm. The power consumption levels of the analog and digital circuits were 1.742 mW and 761 μW, respectively. PMID:27792131

A Low Noise CMOS Readout Based on a Polymer-Coated SAW Array for Miniature Electronic Nose.

PubMed

Wu, Cheng-Chun; Liu, Szu-Chieh; Chiu, Shih-Wen; Tang, Kea-Tiong

2016-10-25

An electronic nose (E-Nose) is one of the applications for surface acoustic wave (SAW) sensors. In this paper, we present a low-noise complementary metal-oxide-semiconductor (CMOS) readout application-specific integrated circuit (ASIC) based on an SAW sensor array for achieving a miniature E-Nose. The center frequency of the SAW sensors was measured to be approximately 114 MHz. Because of interference between the sensors, we designed a low-noise CMOS frequency readout circuit to enable the SAW sensor to obtain frequency variation. The proposed circuit was fabricated in Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 μm 1P6M CMOS process technology. The total chip size was nearly 1203 × 1203 μm². The chip was operated at a supply voltage of 1 V for a digital circuit and 1.8 V for an analog circuit. The least measurable difference between frequencies was 4 Hz. The detection limit of the system, when estimated using methanol and ethanol, was 0.1 ppm. Their linearity was in the range of 0.1 to 26,000 ppm. The power consumption levels of the analog and digital circuits were 1.742 mW and 761 μW, respectively.

CMOS Imaging of Temperature Effects on Pin-Printed Xerogel Sensor Microarrays.

PubMed

Lei Yao; Ka Yi Yung; Chodavarapu, Vamsy P; Bright, Frank V

2011-04-01

In this paper, we study the effect of temperature on the operation and performance of a xerogel-based sensor microarrays coupled to a complementary metal-oxide semiconductor (CMOS) imager integrated circuit (IC) that images the photoluminescence response from the sensor microarray. The CMOS imager uses a 32 × 32 (1024 elements) array of active pixel sensors and each pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. A correlated double sampling circuit and pixel address/digital control/signal integration circuit are also implemented on-chip. The CMOS imager data are read out as a serial coded signal. The sensor system uses a light-emitting diode to excite target analyte responsive organometallic luminophores doped within discrete xerogel-based sensor elements. As a proto type, we developed a 3 × 3 (9 elements) array of oxygen (O2) sensors. Each group of three sensor elements in the array (arranged in a column) is designed to provide a different and specific sensitivity to the target gaseous O2 concentration. This property of multiple sensitivities is achieved by using a mix of two O2 sensitive luminophores in each pin-printed xerogel sensor element. The CMOS imager is designed to be low noise and consumes a static power of 320.4 μW and an average dynamic power of 624.6 μW when operating at 100-Hz sampling frequency and 1.8-V dc power supply.

MOS Circuitry Would Detect Low-Energy Charged Particles

NASA Technical Reports Server (NTRS)

Sinha, Mahadeva; Wadsworth, Mark

2003-01-01

Metal oxide semiconductor (MOS) circuits for measuring spatially varying intensities of beams of low-energy charged particles have been developed. These circuits are intended especially for use in measuring fluxes of ions with spatial resolution along the focal planes of mass spectrometers. Unlike prior mass spectrometer focal-plane detectors, these MOS circuits would not be based on ion-induced generation of electrons, and photons; instead, they would be based on direct detection of the electric charges of the ions. Hence, there would be no need for microchannel plates (for ion-to-electron conversion), phosphors (for electron-to-photon conversion), and photodetectors (for final detection) -- components that degrade spatial resolution and contribute to complexity and size. The developmental circuits are based on linear arrays of charge-coupled devices (CCDs) with associated readout circuitry (see figure). They resemble linear CCD photodetector arrays, except that instead of a photodetector, each pixel contains a capacitive charge sensor. The capacitor in each sensor comprises two electrodes (typically made of aluminum) separated by a layer of insulating material. The exposed electrode captures ions and accumulates their electric charges during signal-integration periods.

Power semiconductor device with negative thermal feedback

NASA Technical Reports Server (NTRS)

Borky, J. M.; Thornton, R. D.

1970-01-01

Composite power semiconductor avoids second breakdown and provides stable operation. It consists of an array of parallel-connected integrated circuits fabricated in a single chip. The output power device and associated low-level amplifier are closely coupled thermally, so that they have a predetermined temperature relationship.

A high-speed trapezoid image sensor design for continuous traffic monitoring at signalized intersection approaches.

DOT National Transportation Integrated Search

2014-10-01

The goal of this project is to monitor traffic flow continuously with an innovative camera system composed of a custom : designed image sensor integrated circuit (IC) containing trapezoid pixel array and camera system that is capable of : intelligent...

A digital optical phase-locked loop for diode lasers based on field programmable gate array

DOE Office of Scientific and Technical Information (OSTI.GOV)

Xu Zhouxiang; Zhang Xian; Huang Kaikai

2012-09-15

We have designed and implemented a highly digital optical phase-locked loop (OPLL) for diode lasers in atom interferometry. The three parts of controlling circuit in this OPLL, including phase and frequency detector (PFD), loop filter and proportional integral derivative (PID) controller, are implemented in a single field programmable gate array chip. A structure type compatible with the model MAX9382/MCH12140 is chosen for PFD and pipeline and parallelism technology have been adapted in PID controller. Especially, high speed clock and twisted ring counter have been integrated in the most crucial part, the loop filter. This OPLL has the narrow beat notemore » line width below 1 Hz, residual mean-square phase error of 0.14 rad{sup 2} and transition time of 100 {mu}s under 10 MHz frequency step. A main innovation of this design is the completely digitalization of the whole controlling circuit in OPLL for diode lasers.« less

Directed self-assembly of block copolymers for nanolithography: fabrication of isolated features and essential integrated circuit geometries.

PubMed

Stoykovich, Mark P; Kang, Huiman; Daoulas, Kostas Ch; Liu, Guoliang; Liu, Chi-Chun; de Pablo, Juan J; Müller, Marcus; Nealey, Paul F

2007-10-01

Self-assembling block copolymers are of interest for nanomanufacturing due to the ability to realize sub-100 nm dimensions, thermodynamic control over the size and uniformity and density of features, and inexpensive processing. The insertion point of these materials in the production of integrated circuits, however, is often conceptualized in the short term for niche applications using the dense periodic arrays of spots or lines that characterize bulk block copolymer morphologies, or in the long term for device layouts completely redesigned into periodic arrays. Here we show that the domain structure of block copolymers in thin films can be directed to assemble into nearly the complete set of essential dense and isolated patterns as currently defined by the semiconductor industry. These results suggest that block copolymer materials, with their intrinsically advantageous self-assembling properties, may be amenable for broad application in advanced lithography, including device layouts used in existing nanomanufacturing processes.

Thin Film Transistor Control Circuitry for MEMS Acoustic Transducers

NASA Astrophysics Data System (ADS)

Daugherty, Robin

This work seeks to develop a practical solution for short range ultrasonic communications and produce an integrated array of acoustic transmitters on a flexible substrate. This is done using flexible thin film transistor (TFT) and micro electromechanical systems (MEMS). The goal is to develop a flexible system capable of communicating in the ultrasonic frequency range at a distance of 10-100 meters. This requires a great deal of innovation on the part of the FDC team developing the TFT driving circuitry and the MEMS team adapting the technology for fabrication on a flexible substrate. The technologies required for this research are independently developed. The TFT development is driven primarily by research into flexible displays. The MEMS development is driving by research in biosensors and micro actuators. This project involves the integration of TFT flexible circuit capabilities with MEMS micro actuators in the novel area of flexible acoustic transmitter arrays. This thesis focuses on the design, testing and analysis of the circuit components required for this project.

Antenna-coupled Superconducting Bolometers for Observations of the Cosmic Microwave Background Polarization

NASA Astrophysics Data System (ADS)

Myers, Michael James

We describe the development of a novel millimeter-wave cryogenic detector. The device integrates a planar antenna, superconducting transmission line, bandpass filter, and bolometer onto a single silicon wafer. The bolometer uses a superconducting Transition-Edge Sensor (TES) thermistor, which provides substantial advantages over conventional semiconductor bolometers. The detector chip is fabricated using standard micro-fabrication techniques. This highly-integrated detector architecture is particularly well-suited for use in the de- velopment of polarization-sensitive cryogenic receivers with thousands of pixels. Such receivers are needed to meet the sensitivity requirements of next-generation cosmic microwave background polarization experiments. The design, fabrication, and testing of prototype array pixels are described. Preliminary considerations for a full array design are also discussed. A set of on-chip millimeter-wave test structures were developed to help understand the performance of our millimeter-wave microstrip circuits. These test structures produce a calibrated transmission measurement for an arbitrary two-port circuit using optical techniques, rather than a network analyzer. Some results of fabricated test structures are presented.

A Prototype PZT Matrix Transducer With Low-Power Integrated Receive ASIC for 3-D Transesophageal Echocardiography.

PubMed

Chen, Chao; Raghunathan, Shreyas B; Yu, Zili; Shabanimotlagh, Maysam; Chen, Zhao; Chang, Zu-yao; Blaak, Sandra; Prins, Christian; Ponte, Jacco; Noothout, Emile; Vos, Hendrik J; Bosch, Johan G; Verweij, Martin D; de Jong, Nico; Pertijs, Michiel A P

2016-01-01

This paper presents the design, fabrication, and experimental evaluation of a prototype lead zirconium titanate (PZT) matrix transducer with an integrated receive ASIC, as a proof of concept for a miniature three-dimensional (3-D) transesophageal echocardiography (TEE) probe. It consists of an array of 9 ×12 piezoelectric elements mounted on the ASIC via an integration scheme that involves direct electrical connections between a bond-pad array on the ASIC and the transducer elements. The ASIC addresses the critical challenge of reducing cable count, and includes front-end amplifiers with adjustable gains and micro-beamformer circuits that locally process and combine echo signals received by the elements of each 3 ×3 subarray. Thus, an order-of-magnitude reduction in the number of receive channels is achieved. Dedicated circuit techniques are employed to meet the strict space and power constraints of TEE probes. The ASIC has been fabricated in a standard 0.18-μm CMOS process and consumes only 0.44 mW/channel. The prototype has been acoustically characterized in a water tank. The ASIC allows the array to be presteered across ±37° while achieving an overall dynamic range of 77 dB. Both the measured characteristics of the individual transducer elements and the performance of the ASIC are in good agreement with expectations, demonstrating the effectiveness of the proposed techniques.

Programmable resistive-switch nanowire transistor logic circuits.

PubMed

Shim, Wooyoung; Yao, Jun; Lieber, Charles M

2014-09-10

Programmable logic arrays (PLA) constitute a promising architecture for developing increasingly complex and functional circuits through nanocomputers from nanoscale building blocks. Here we report a novel one-dimensional PLA element that incorporates resistive switch gate structures on a semiconductor nanowire and show that multiple elements can be integrated to realize functional PLAs. In our PLA element, the gate coupling to the nanowire transistor can be modulated by the memory state of the resistive switch to yield programmable active (transistor) or inactive (resistor) states within a well-defined logic window. Multiple PLA nanowire elements were integrated and programmed to yield a working 2-to-4 demultiplexer with long-term retention. The well-defined, controllable logic window and long-term retention of our new one-dimensional PLA element provide a promising route for building increasingly complex circuits with nanoscale building blocks.

Microwave monolithic integrated circuit development for future spaceborne phased array antennas

NASA Astrophysics Data System (ADS)

Anzic, G.; Kascak, T. J.; Downey, A. N.; Liu, D. C.; Connolly, D. J.

1983-12-01

The development of fully monolithic gallium arsenide (GaAs) receive and transmit modules suitable for phased array antenna applications in the 30/20 gigahertz bands is presented. Specifications and various design approaches to achieve the design goals are described. Initial design and performance of submodules and associated active and passive components are presented. A tradeoff study summary is presented highlighting the advantages of distributed amplifier approach compared to the conventional single power source designs.

Microwave monolithic integrated circuit development for future spaceborne phased array antennas

NASA Technical Reports Server (NTRS)

Anzic, G.; Kascak, T. J.; Downey, A. N.; Liu, D. C.; Connolly, D. J.

1983-01-01

The development of fully monolithic gallium arsenide (GaAs) receive and transmit modules suitable for phased array antenna applications in the 30/20 gigahertz bands is presented. Specifications and various design approaches to achieve the design goals are described. Initial design and performance of submodules and associated active and passive components are presented. A tradeoff study summary is presented highlighting the advantages of distributed amplifier approach compared to the conventional single power source designs.

K-Band Phased Array Developed for Low- Earth-Orbit Satellite Communications

NASA Technical Reports Server (NTRS)

Anzic, Godfrey

1999-01-01

Future rapid deployment of low- and medium-Earth-orbit satellite constellations that will offer various narrow- to wide-band wireless communications services will require phased-array antennas that feature wide-angle and superagile electronic steering of one or more antenna beams. Antennas, which employ monolithic microwave integrated circuits (MMIC), are perfectly suited for this application. Under a cooperative agreement, an MMIC-based, K-band phased-array antenna is being developed with 50/50 cost sharing by the NASA Lewis Research Center and Raytheon Systems Company. The transmitting array, which will operate at 19 gigahertz (GHz), is a state-of-the-art design that features dual, independent, electronically steerable beam operation ( 42 ), a stand-alone thermal management, and a high-density tile architecture. This array can transmit 622 megabits per second (Mbps) in each beam from Earth orbit to small Earth terminals. The weight of the total array package is expected to be less than 8 lb. The tile integration technology (flip chip MMIC tile) chosen for this project represents a major advancement in phased-array engineering and holds much promise for reducing manufacturing costs.

Label-free silicon photonic biosensor system with integrated detector array.

PubMed

Yan, Rongjin; Mestas, Santano P; Yuan, Guangwei; Safaisini, Rashid; Dandy, David S; Lear, Kevin L

2009-08-07

An integrated, inexpensive, label-free photonic waveguide biosensor system with multi-analyte capability has been implemented on a silicon photonics integrated circuit from a commercial CMOS line and tested with nanofilms. The local evanescent array coupled (LEAC) biosensor is based on a new physical phenomenon that is fundamentally different from the mechanisms of other evanescent field sensors. Increased local refractive index at the waveguide's upper surface due to the formation of a biological nanofilm causes local modulation of the evanescent field coupled into an array of photodetectors buried under the waveguide. The planar optical waveguide biosensor system exhibits sensitivity of 20%/nm photocurrent modulation in response to adsorbed bovine serum albumin (BSA) layers less than 3 nm thick. In addition to response to BSA, an experiment with patterned photoresist as well as beam propagation method simulations support the evanescent field shift principle. The sensing mechanism enables the integration of all optical and electronic components for a multi-analyte biosensor system on a chip.

Label-free silicon photonic biosensor system with integrated detector array

PubMed Central

Yan, Rongjin; Mestas, Santano P.; Yuan, Guangwei; Safaisini, Rashid; Dandy, David S.

2010-01-01

An integrated, inexpensive, label-free photonic waveguide biosensor system with multi-analyte capability has been implemented on a silicon photonics integrated circuit from a commercial CMOS line and tested with nanofilms. The local evanescent array coupled (LEAC) biosensor is based on a new physical phenomenon that is fundamentally different from the mechanisms of other evanescent field sensors. Increased local refractive index at the waveguide’s upper surface due to the formation of a biological nanofilm causes local modulation of the evanescent field coupled into an array of photodetectors buried under the waveguide. The planar optical waveguide biosensor system exhibits sensitivity of 20%/nm photocurrent modulation in response to adsorbed bovine serum albumin (BSA) layers less than 3 nm thick. In addition to response to BSA, an experiment with patterned photoresist as well as beam propagation method simulations support the evanescent field shift principle. The sensing mechanism enables the integration of all optical and electronic components for a multi-analyte biosensor system on a chip. PMID:19606292

Detector Arrays for the James Webb Space Telescope Near-Infrared Spectrograph

NASA Technical Reports Server (NTRS)

Rauscher, Bernard J.; Alexander, David; Brambora, Clifford K.; Derro, Rebecca; Engler, Chuck; Fox, Ori; Garrison, Matthew B.; Henegar, Greg; Hill, robert J.; Johnson, Thomas;

Design, Fabrication and Integration of a NaK-Cooled Circuit

NASA Technical Reports Server (NTRS)

Garber, Anne; Godfroy, Thomas

2006-01-01

The Early Flight Fission Test Facilities (EFF-TF) team has been tasked by the NASA Marshall Space Flight Center Nuclear Systems Office to design, fabricate, and test an actively pumped alkali metal flow circuit. The system, which was originally designed for use with a eutectic mixture of sodium potassium (NaK), was redesigned to for use with lithium. Due to a shi$ in focus, it is once again being prepared for use with NaK. Changes made to the actively pumped, high temperature circuit include the replacement of the expansion reservoir, addition of remotely operated valves, and modification of the support table. Basic circuit components include: reactor segment, NaK to gas heat exchanger, electromagnetic (EM) liquid metal pump, load/drain reservoir, expansion reservoir, instrumentation, and a spill reservoir. A 37-pin partial-array core (pin and flow path dimensions are the same as those in a fill design) was selected for fabrication and test. This paper summarizes the integration and preparations for the fill of the pumped liquid metal NaK flow circuit.

Stainless Steel NaK Circuit Integration and Fill Submission

NASA Technical Reports Server (NTRS)

Garber, Anne E.

2006-01-01

The Early Flight Fission Test Facilities (EFF-TF) team has been tasked by the Marshall Space Flight Center Nuclear Systems Office to design, fabricate, and test an actively pumped alkali metal flow circuit. The system, which was originally designed to hold a eutectic mixture of sodium potassium (NaK), was redesigned to hold lithium; but due to a shift in focus, it is once again being prepared for use with NaK. Changes made to the actively pumped, high temperature loop include the replacement of the expansion reservoir, addition of remotely operated valves, and modification of the support table. Basic circuit components include: reactor segment, NaK to gas heat exchanger, electromagnetic (EM) liquid metal pump, load/drain reservoir, expansion reservoir, instrumentation, and a spill reservoir. A 37-pin partial-array core (pin and flow path dimensions are the same as those in a full design) was selected for fabrication and test. This document summarizes the integration and fill of the pumped liquid metal NaK flow circuit.

Multipurpose silicon photonics signal processor core.

PubMed

Pérez, Daniel; Gasulla, Ivana; Crudgington, Lee; Thomson, David J; Khokhar, Ali Z; Li, Ke; Cao, Wei; Mashanovich, Goran Z; Capmany, José

2017-09-21

Integrated photonics changes the scaling laws of information and communication systems offering architectural choices that combine photonics with electronics to optimize performance, power, footprint, and cost. Application-specific photonic integrated circuits, where particular circuits/chips are designed to optimally perform particular functionalities, require a considerable number of design and fabrication iterations leading to long development times. A different approach inspired by electronic Field Programmable Gate Arrays is the programmable photonic processor, where a common hardware implemented by a two-dimensional photonic waveguide mesh realizes different functionalities through programming. Here, we report the demonstration of such reconfigurable waveguide mesh in silicon. We demonstrate over 20 different functionalities with a simple seven hexagonal cell structure, which can be applied to different fields including communications, chemical and biomedical sensing, signal processing, multiprocessor networks, and quantum information systems. Our work is an important step toward this paradigm.Integrated optical circuits today are typically designed for a few special functionalities and require complex design and development procedures. Here, the authors demonstrate a reconfigurable but simple silicon waveguide mesh with different functionalities.

Frequency-multiplexed bias and readout of a 16-pixel superconducting nanowire single-photon detector array

NASA Astrophysics Data System (ADS)

Doerner, S.; Kuzmin, A.; Wuensch, S.; Charaev, I.; Boes, F.; Zwick, T.; Siegel, M.

2017-07-01

We demonstrate a 16-pixel array of microwave-current driven superconducting nanowire single-photon detectors with an integrated and scalable frequency-division multiplexing architecture, which reduces the required number of bias and readout lines to a single microwave feed line. The electrical behavior of the photon-sensitive nanowires, embedded in a resonant circuit, as well as the optical performance and timing jitter of the single detectors is discussed. Besides the single pixel measurements, we also demonstrate the operation of a 16-pixel array with a temporal, spatial, and photon-number resolution.

Laser-Ablated Ba(0.50)Sr(0.50)TiO3/LaAlO3 Films Analyzed Statistically for Microwave Applications

NASA Technical Reports Server (NTRS)

Romanofsky, Robert R.

2003-01-01

Scanning phased-array antennas represent a highly desirable solution for futuristic near-Earth and deep space communication scenarios requiring vibration-free, rapid beam steering and enhanced reliability. The current state-of-practice in scanning phased arrays is represented by gallium arsenide (GaAs) monolithic microwave integrated circuit (MMIC) technology or ferrite phase shifters. Cost and weight are significant impediments to space applications. Moreover, conventional manifold-fed arrays suffer from beam-forming loss that places considerable burden on MMIC amplifiers. The inefficiency can result in severe thermal management problems.

Fully Integrated Linear Single Photon Avalanche Diode (SPAD) Array with Parallel Readout Circuit in a Standard 180 nm CMOS Process

NASA Astrophysics Data System (ADS)

Isaak, S.; Bull, S.; Pitter, M. C.; Harrison, Ian.

2011-05-01

This paper reports on the development of a SPAD device and its subsequent use in an actively quenched single photon counting imaging system, and was fabricated in a UMC 0.18 μm CMOS process. A low-doped p- guard ring (t-well layer) encircling the active area to prevent the premature reverse breakdown. The array is a 16×1 parallel output SPAD array, which comprises of an active quenched SPAD circuit in each pixel with the current value being set by an external resistor RRef = 300 kΩ. The SPAD I-V response, ID was found to slowly increase until VBD was reached at excess bias voltage, Ve = 11.03 V, and then rapidly increase due to avalanche multiplication. Digital circuitry to control the SPAD array and perform the necessary data processing was designed in VHDL and implemented on a FPGA chip. At room temperature, the dark count was found to be approximately 13 KHz for most of the 16 SPAD pixels and the dead time was estimated to be 40 ns.

Prototype AEGIS: A Pixel-Array Readout Circuit for Gamma-Ray Imaging.

PubMed

Barber, H Bradford; Augustine, F L; Furenlid, L; Ingram, C M; Grim, G P

2005-07-31

Semiconductor detector arrays made of CdTe/CdZnTe are expected to be the main components of future high-performance, clinical nuclear medicine imaging systems. Such systems will require small pixel-pitch and much larger numbers of pixels than are available in current semiconductor-detector cameras. We describe the motivation for developing a new readout integrated circuit, AEGIS, for use in hybrid semiconductor detector arrays, that may help spur the development of future cameras. A basic design for AEGIS is presented together with results of an HSPICE ™ simulation of the performance of its unit cell. AEGIS will have a shaper-amplifier unit cell and neighbor pixel readout. Other features include the use of a single input power line with other biases generated on-board, a control register that allows digital control of all thresholds and chip configurations and an output approach that is compatible with list-mode data acquisition. An 8×8 prototype version of AEGIS is currently under development; the full AEGIS will be a 64×64 array with 300 μm pitch.

Optical techniques to feed and control GaAs MMIC modules for phased array antenna applications

NASA Astrophysics Data System (ADS)

Bhasin, K. B.; Anzic, G.; Kunath, R. R.; Connolly, D. J.

A complex signal distribution system is required to feed and control GaAs monolithic microwave integrated circuits (MMICs) for phased array antenna applications above 20 GHz. Each MMIC module will require one or more RF lines, one or more bias voltage lines, and digital lines to provide a minimum of 10 bits of combined phase and gain control information. In a closely spaced array, the routing of these multiple lines presents difficult topology problems as well as a high probability of signal interference. To overcome GaAs MMIC phased array signal distribution problems optical fibers interconnected to monolithically integrated optical components with GaAs MMIC array elements are proposed as a solution. System architecture considerations using optical fibers are described. The analog and digital optical links to respectively feed and control MMIC elements are analyzed. It is concluded that a fiber optic network will reduce weight and complexity, and increase reliability and performance, but higher power will be required.

Optical techniques to feed and control GaAs MMIC modules for phased array antenna applications

NASA Technical Reports Server (NTRS)

Bhasin, K. B.; Anzic, G.; Kunath, R. R.; Connolly, D. J.

1986-01-01

A complex signal distribution system is required to feed and control GaAs monolithic microwave integrated circuits (MMICs) for phased array antenna applications above 20 GHz. Each MMIC module will require one or more RF lines, one or more bias voltage lines, and digital lines to provide a minimum of 10 bits of combined phase and gain control information. In a closely spaced array, the routing of these multiple lines presents difficult topology problems as well as a high probability of signal interference. To overcome GaAs MMIC phased array signal distribution problems optical fibers interconnected to monolithically integrated optical components with GaAs MMIC array elements are proposed as a solution. System architecture considerations using optical fibers are described. The analog and digital optical links to respectively feed and control MMIC elements are analyzed. It is concluded that a fiber optic network will reduce weight and complexity, and increase reliability and performance, but higher power will be required.

Capacitive micromachined ultrasonic transducers for medical imaging and therapy.

PubMed

Khuri-Yakub, Butrus T; Oralkan, Omer

2011-05-01

Capacitive micromachined ultrasonic transducers (CMUTs) have been subject to extensive research for the last two decades. Although they were initially developed for air-coupled applications, today their main application space is medical imaging and therapy. This paper first presents a brief description of CMUTs, their basic structure, and operating principles. Our progression of developing several generations of fabrication processes is discussed with an emphasis on the advantages and disadvantages of each process. Monolithic and hybrid approaches for integrating CMUTs with supporting integrated circuits are surveyed. Several prototype transducer arrays with integrated frontend electronic circuits we developed and their use for 2-D and 3-D, anatomical and functional imaging, and ablative therapies are described. The presented results prove the CMUT as a MEMS technology for many medical diagnostic and therapeutic applications.

Capacitive micromachined ultrasonic transducers for medical imaging and therapy

PubMed Central

Khuri-Yakub, Butrus T.; Oralkan, Ömer

2011-01-01

Capacitive micromachined ultrasonic transducers (CMUTs) have been subject to extensive research for the last two decades. Although they were initially developed for air-coupled applications, today their main application space is medical imaging and therapy. This paper first presents a brief description of CMUTs, their basic structure, and operating principles. Our progression of developing several generations of fabrication processes is discussed with an emphasis on the advantages and disadvantages of each process. Monolithic and hybrid approaches for integrating CMUTs with supporting integrated circuits are surveyed. Several prototype transducer arrays with integrated frontend electronic circuits we developed and their use for 2-D and 3-D, anatomical and functional imaging, and ablative therapies are described. The presented results prove the CMUT as a MEMS technology for many medical diagnostic and therapeutic applications. PMID:21860542

Ultra-thin silicon (UTSi) on insulator CMOS transceiver and time-division multiplexed switch chips for smart pixel integration

NASA Astrophysics Data System (ADS)

Zhang, Liping; Sawchuk, Alexander A.

2001-12-01

We describe the design, fabrication and functionality of two different 0.5 micron CMOS optoelectronic integrated circuit (OEIC) chips based on the Peregrine Semiconductor Ultra-Thin Silicon on insulator technology. The Peregrine UTSi silicon- on-sapphire (SOS) technology is a member of the silicon-on- insulator (SOI) family. The low-loss synthetic sapphire substrate is optically transparent and has good thermal conductivity and coefficient of thermal expansion properties, which meet the requirements for flip-chip bonding of VCSELs and other optoelectronic input-output components. One chip contains transceiver and network components, including four channel high-speed CMOS transceiver modules, pseudo-random bit stream (PRBS) generators, a voltage controlled oscillator (VCO) and other test circuits. The transceiver chips can operate in both self-testing mode and networking mode. An on- chip clock and true-single-phase-clock (TSPC) D-flip-flop have been designed to generate a PRBS at over 2.5 Gb/s for the high-speed transceiver arrays to operate in self-testing mode. In the networking mode, an even number of transceiver chips forms a ring network through free-space or fiber ribbon interconnections. The second chip contains four channel optical time-division multiplex (TDM) switches, optical transceiver arrays, an active pixel detector and additional test devices. The eventual applications of these chips will require monolithic OEICs with integrated optical input and output. After fabrication and testing, the CMOS transceiver array dies will be packaged with 850 nm vertical cavity surface emitting lasers (VCSELs), and metal-semiconductor- metal (MSM) or GaAs p-i-n detector die arrays to achieve high- speed optical interconnections. The hybrid technique could be either wire bonding or flip-chip bonding of the CMOS SOS smart-pixel arrays with arrays of VCSELs and photodetectors onto an optoelectronic chip carrier as a multi-chip module (MCM).

Sensor readout detector circuit

DOEpatents

Chu, Dahlon D.; Thelen, Jr., Donald C.

1998-01-01

A sensor readout detector circuit is disclosed that is capable of detecting sensor signals down to a few nanoamperes or less in a high (microampere) background noise level. The circuit operates at a very low standby power level and is triggerable by a sensor event signal that is above a predetermined threshold level. A plurality of sensor readout detector circuits can be formed on a substrate as an integrated circuit (IC). These circuits can operate to process data from an array of sensors in parallel, with only data from active sensors being processed for digitization and analysis. This allows the IC to operate at a low power level with a high data throughput for the active sensors. The circuit may be used with many different types of sensors, including photodetectors, capacitance sensors, chemically-sensitive sensors or combinations thereof to provide a capability for recording transient events or for recording data for a predetermined period of time following an event trigger. The sensor readout detector circuit has applications for portable or satellite-based sensor systems.

Sensor readout detector circuit

DOEpatents

Chu, D.D.; Thelen, D.C. Jr.

1998-08-11

A sensor readout detector circuit is disclosed that is capable of detecting sensor signals down to a few nanoamperes or less in a high (microampere) background noise level. The circuit operates at a very low standby power level and is triggerable by a sensor event signal that is above a predetermined threshold level. A plurality of sensor readout detector circuits can be formed on a substrate as an integrated circuit (IC). These circuits can operate to process data from an array of sensors in parallel, with only data from active sensors being processed for digitization and analysis. This allows the IC to operate at a low power level with a high data throughput for the active sensors. The circuit may be used with many different types of sensors, including photodetectors, capacitance sensors, chemically-sensitive sensors or combinations thereof to provide a capability for recording transient events or for recording data for a predetermined period of time following an event trigger. The sensor readout detector circuit has applications for portable or satellite-based sensor systems. 6 figs.

How Small Is Too Small? Technology into 2035

DTIC Science & Technology

2010-12-01

by Arrayed Polyimide Joint Actuators,” Journal of Micromechanics and Microengineering 10, no. 3 [2000]: 337–49.) 6 A more integrated microrobot is...application-specific in- tegrated circuit used for overall control; three piezoelectric legs used for forward, reverse, and z-axis rotation move- ments...a piezoelectric touch sensor; and power storage Figure 3. Captured video image of an integrated and autonomous micro- robot. (Reproduced from Seth

Fully integrated wearable sensor arrays for multiplexed in situ perspiration analysis

DOE PAGES

Gao, Wei; Emaminejad, Sam; Nyein, Hnin Yin Yin; ...

2016-01-27

We report that wearable sensor technologies are essential to the realization of personalized medicine through continuously monitoring an individual’s state of health. Sampling human sweat, which is rich in physiological information13, could enable non-invasive monitoring. Previously reported sweat-based and other noninvasive biosensors either can only monitor a single analyte at a time or lack on-site signal processing circuitry and sensor calibration mechanisms for accurate analysis of the physiological state14–18. Given the complexity of sweat secretion, simultaneous and multiplexed screening of target biomarkers is critical and requires full system integration to ensure the accuracy of measurements. Here we present a mechanicallymore » flexible and fully integrated (that is, no external analysis is needed) sensor array for multiplexed in situ perspiration analysis, which simultaneously and selectively measures sweat metabolites (such as glucose and lactate) and electrolytes (such as sodium and potassium ions), as well as the skin temperature (to calibrate the response of the sensors). Lastly, our work bridges the technological gap between signal transduction, conditioning (amplification and filtering), processing and wireless transmission in wearable biosensors by merging plasticbased sensors that interface with the skin with silicon integrated circuits consolidated on a flexible circuit board for complex signal processing.« less

Fully integrated wearable sensor arrays for multiplexed in situ perspiration analysis

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gao, Wei; Emaminejad, Sam; Nyein, Hnin Yin Yin

We report that wearable sensor technologies are essential to the realization of personalized medicine through continuously monitoring an individual’s state of health. Sampling human sweat, which is rich in physiological information13, could enable non-invasive monitoring. Previously reported sweat-based and other noninvasive biosensors either can only monitor a single analyte at a time or lack on-site signal processing circuitry and sensor calibration mechanisms for accurate analysis of the physiological state14–18. Given the complexity of sweat secretion, simultaneous and multiplexed screening of target biomarkers is critical and requires full system integration to ensure the accuracy of measurements. Here we present a mechanicallymore » flexible and fully integrated (that is, no external analysis is needed) sensor array for multiplexed in situ perspiration analysis, which simultaneously and selectively measures sweat metabolites (such as glucose and lactate) and electrolytes (such as sodium and potassium ions), as well as the skin temperature (to calibrate the response of the sensors). Lastly, our work bridges the technological gap between signal transduction, conditioning (amplification and filtering), processing and wireless transmission in wearable biosensors by merging plasticbased sensors that interface with the skin with silicon integrated circuits consolidated on a flexible circuit board for complex signal processing.« less

Low-noise heterodyne receiver for electron cyclotron emission imaging and microwave imaging reflectometry

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tobias, B., E-mail: bjtobias@pppl.gov; Domier, C. W.; Luhmann, N. C.

2016-11-15

The critical component enabling electron cyclotron emission imaging (ECEI) and microwave imaging reflectometry (MIR) to resolve 2D and 3D electron temperature and density perturbations is the heterodyne imaging array that collects and downconverts radiated emission and/or reflected signals (50–150 GHz) to an intermediate frequency (IF) band (e.g. 0.1–18 GHz) that can be transmitted by a shielded coaxial cable for further filtering and detection. New circuitry has been developed for this task, integrating gallium arsenide (GaAs) monolithic microwave integrated circuits (MMICs) mounted on a liquid crystal polymer (LCP) substrate. The improved topology significantly increases electromagnetic shielding from out-of-band interference, leads tomore » 10× improvement in the signal-to-noise ratio, and dramatic cost savings through integration. The current design, optimized for reflectometry and edge radiometry on mid-sized tokamaks, has demonstrated >20 dB conversion gain in upper V-band (60-75 GHz). Implementation of the circuit in a multi-channel electron cyclotron emission imaging (ECEI) array will improve the diagnosis of edge-localized modes and fluctuations of the high-confinement, or H-mode, pedestal.« less

Low-noise heterodyne receiver for electron cyclotron emission imaging and microwave imaging reflectometry

DOE PAGES

Tobias, B.; Domier, C. W.; Luhmann, Jr., N. C.; ...

2016-07-25

The critical component enabling electron cyclotron emission imaging (ECEI) and microwave imaging reflectometry (MIR) to resolve 2D and 3D electron temperature and density perturbations is the heterodyne imaging array that collects and downconverts radiated emission and/or reflected signals (50-150 GHz) to an intermediate frequency (IF) band (e.g. 0.1-18 GHz) that can be transmitted by a shielded coaxial cable for further filtering and detection. New circuitry has been developed for this task, integrating gallium arsenide (GaAs) monolithic microwave integrated circuits (MMICs) mounted on a liquid crystal polymer (LCP) substrate. The improved topology significantly increases electromagnetic shielding from out-of-band interference, leads tomore » 10x improvement in the signal-to-noise ratio, and dramatic cost savings through integration. The current design, optimized for reflectometry and edge radiometry on mid-sized tokamaks, has demonstrated >20 dB conversion gain in upper V-band (60-75 GHz). As a result, implementation of the circuit in a multi-channel electron cyclotron emission imaging (ECEI) array will improve the diagnosis of edge-localized modes and fluctuations of the high-confinement, or H-mode, pedestal.« less

Laser programmable integrated circuit for forming synapses in neural networks

DOEpatents

Fu, C.Y.

1997-02-11

Customizable neural network in which one or more resistors form each synapse is disclosed. All the resistors in the synaptic array are identical, thus simplifying the processing issues. Highly doped, amorphous silicon is used as the resistor material, to create extremely high resistances occupying very small spaces. Connected in series with each resistor in the array is at least one severable conductor whose uppermost layer has a lower reflectivity of laser energy than typical metal conductors at a desired laser wavelength. 5 figs.

Microwave monolithic integrated circuit development for future spaceborne phased array antennas

NASA Astrophysics Data System (ADS)

Anzic, G.; Kascak, T. J.; Downey, A. N.; Liu, D. C.; Connolly, D. J.

The development of fully monolithic gallium arsenide (GaAs) receive and transmit modules suitable for phased array antenna applications in the 30/20 gigahertz bands is presented. Specifications and various design approaches to achieve the design goals are described. Initial design and performance of submodules and associated active and passive components are presented. A tradeoff study summary is presented, highlighting the advantages of a distributed amplifier approach compared to the conventional single power source designs. Previously announced in STAR as N84-13399

Microwave monolithic integrated circuit development for future spaceborne phased array antennas

NASA Technical Reports Server (NTRS)

Anzic, G.; Kascak, T. J.; Downey, A. N.; Liu, D. C.; Connolly, D. J.

1984-01-01

The development of fully monolithic gallium arsenide (GaAs) receive and transmit modules suitable for phased array antenna applications in the 30/20 gigahertz bands is presented. Specifications and various design approaches to achieve the design goals are described. Initial design and performance of submodules and associated active and passive components are presented. A tradeoff study summary is presented, highlighting the advantages of a distributed amplifier approach compared to the conventional single power source designs. Previously announced in STAR as N84-13399

Nanowire nanocomputer as a finite-state machine.

PubMed

Yao, Jun; Yan, Hao; Das, Shamik; Klemic, James F; Ellenbogen, James C; Lieber, Charles M

2014-02-18

Implementation of complex computer circuits assembled from the bottom up and integrated on the nanometer scale has long been a goal of electronics research. It requires a design and fabrication strategy that can address individual nanometer-scale electronic devices, while enabling large-scale assembly of those devices into highly organized, integrated computational circuits. We describe how such a strategy has led to the design, construction, and demonstration of a nanoelectronic finite-state machine. The system was fabricated using a design-oriented approach enabled by a deterministic, bottom-up assembly process that does not require individual nanowire registration. This methodology allowed construction of the nanoelectronic finite-state machine through modular design using a multitile architecture. Each tile/module consists of two interconnected crossbar nanowire arrays, with each cross-point consisting of a programmable nanowire transistor node. The nanoelectronic finite-state machine integrates 180 programmable nanowire transistor nodes in three tiles or six total crossbar arrays, and incorporates both sequential and arithmetic logic, with extensive intertile and intratile communication that exhibits rigorous input/output matching. Our system realizes the complete 2-bit logic flow and clocked control over state registration that are required for a finite-state machine or computer. The programmable multitile circuit was also reprogrammed to a functionally distinct 2-bit full adder with 32-set matched and complete logic output. These steps forward and the ability of our unique design-oriented deterministic methodology to yield more extensive multitile systems suggest that proposed general-purpose nanocomputers can be realized in the near future.

Nanowire nanocomputer as a finite-state machine

PubMed Central

Yao, Jun; Yan, Hao; Das, Shamik; Klemic, James F.; Ellenbogen, James C.; Lieber, Charles M.

2014-01-01

Implementation of complex computer circuits assembled from the bottom up and integrated on the nanometer scale has long been a goal of electronics research. It requires a design and fabrication strategy that can address individual nanometer-scale electronic devices, while enabling large-scale assembly of those devices into highly organized, integrated computational circuits. We describe how such a strategy has led to the design, construction, and demonstration of a nanoelectronic finite-state machine. The system was fabricated using a design-oriented approach enabled by a deterministic, bottom–up assembly process that does not require individual nanowire registration. This methodology allowed construction of the nanoelectronic finite-state machine through modular design using a multitile architecture. Each tile/module consists of two interconnected crossbar nanowire arrays, with each cross-point consisting of a programmable nanowire transistor node. The nanoelectronic finite-state machine integrates 180 programmable nanowire transistor nodes in three tiles or six total crossbar arrays, and incorporates both sequential and arithmetic logic, with extensive intertile and intratile communication that exhibits rigorous input/output matching. Our system realizes the complete 2-bit logic flow and clocked control over state registration that are required for a finite-state machine or computer. The programmable multitile circuit was also reprogrammed to a functionally distinct 2-bit full adder with 32-set matched and complete logic output. These steps forward and the ability of our unique design-oriented deterministic methodology to yield more extensive multitile systems suggest that proposed general-purpose nanocomputers can be realized in the near future. PMID:24469812

Reconfigurable SDM Switching Using Novel Silicon Photonic Integrated Circuit.

PubMed

Ding, Yunhong; Kamchevska, Valerija; Dalgaard, Kjeld; Ye, Feihong; Asif, Rameez; Gross, Simon; Withford, Michael J; Galili, Michael; Morioka, Toshio; Oxenløwe, Leif Katsuo

2016-12-21

Space division multiplexing using multicore fibers is becoming a more and more promising technology. In space-division multiplexing fiber network, the reconfigurable switch is one of the most critical components in network nodes. In this paper we for the first time demonstrate reconfigurable space-division multiplexing switching using silicon photonic integrated circuit, which is fabricated on a novel silicon-on-insulator platform with buried Al mirror. The silicon photonic integrated circuit is composed of a 7 × 7 switch and low loss grating coupler array based multicore fiber couplers. Thanks to the Al mirror, grating couplers with ultra-low coupling loss with optical multicore fibers is achieved. The lowest total insertion loss of the silicon integrated circuit is as low as 4.5 dB, with low crosstalk lower than -30 dB. Excellent performances in terms of low insertion loss and low crosstalk are obtained for the whole C-band. 1 Tb/s/core transmission over a 2-km 7-core fiber and space-division multiplexing switching is demonstrated successfully. Bit error rate performance below 10 -9 is obtained for all spatial channels with low power penalty. The proposed design can be easily upgraded to reconfigurable optical add/drop multiplexer capable of switching several multicore fibers.

Reconfigurable SDM Switching Using Novel Silicon Photonic Integrated Circuit

NASA Astrophysics Data System (ADS)

Ding, Yunhong; Kamchevska, Valerija; Dalgaard, Kjeld; Ye, Feihong; Asif, Rameez; Gross, Simon; Withford, Michael J.; Galili, Michael; Morioka, Toshio; Oxenløwe, Leif Katsuo

2016-12-01

Space division multiplexing using multicore fibers is becoming a more and more promising technology. In space-division multiplexing fiber network, the reconfigurable switch is one of the most critical components in network nodes. In this paper we for the first time demonstrate reconfigurable space-division multiplexing switching using silicon photonic integrated circuit, which is fabricated on a novel silicon-on-insulator platform with buried Al mirror. The silicon photonic integrated circuit is composed of a 7 × 7 switch and low loss grating coupler array based multicore fiber couplers. Thanks to the Al mirror, grating couplers with ultra-low coupling loss with optical multicore fibers is achieved. The lowest total insertion loss of the silicon integrated circuit is as low as 4.5 dB, with low crosstalk lower than -30 dB. Excellent performances in terms of low insertion loss and low crosstalk are obtained for the whole C-band. 1 Tb/s/core transmission over a 2-km 7-core fiber and space-division multiplexing switching is demonstrated successfully. Bit error rate performance below 10-9 is obtained for all spatial channels with low power penalty. The proposed design can be easily upgraded to reconfigurable optical add/drop multiplexer capable of switching several multicore fibers.

Reconfigurable SDM Switching Using Novel Silicon Photonic Integrated Circuit

PubMed Central

Ding, Yunhong; Kamchevska, Valerija; Dalgaard, Kjeld; Ye, Feihong; Asif, Rameez; Gross, Simon; Withford, Michael J.; Galili, Michael; Morioka, Toshio; Oxenløwe, Leif Katsuo

2016-01-01

Space division multiplexing using multicore fibers is becoming a more and more promising technology. In space-division multiplexing fiber network, the reconfigurable switch is one of the most critical components in network nodes. In this paper we for the first time demonstrate reconfigurable space-division multiplexing switching using silicon photonic integrated circuit, which is fabricated on a novel silicon-on-insulator platform with buried Al mirror. The silicon photonic integrated circuit is composed of a 7 × 7 switch and low loss grating coupler array based multicore fiber couplers. Thanks to the Al mirror, grating couplers with ultra-low coupling loss with optical multicore fibers is achieved. The lowest total insertion loss of the silicon integrated circuit is as low as 4.5 dB, with low crosstalk lower than −30 dB. Excellent performances in terms of low insertion loss and low crosstalk are obtained for the whole C-band. 1 Tb/s/core transmission over a 2-km 7-core fiber and space-division multiplexing switching is demonstrated successfully. Bit error rate performance below 10−9 is obtained for all spatial channels with low power penalty. The proposed design can be easily upgraded to reconfigurable optical add/drop multiplexer capable of switching several multicore fibers. PMID:28000735

Active pixel sensor pixel having a photodetector whose output is coupled to an output transistor gate

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Nakamura, Junichi (Inventor); Kemeny, Sabrina E. (Inventor)

2005-01-01

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node. There is also a readout circuit, part of which can be disposed at the bottom of each column of cells and be common to all the cells in the column. A Simple Floating Gate (SFG) pixel structure could also be employed in the imager to provide a non-destructive readout and smaller pixel sizes.

Nanoelectronics from the bottom up.

PubMed

Lu, Wei; Lieber, Charles M

2007-11-01

Electronics obtained through the bottom-up approach of molecular-level control of material composition and structure may lead to devices and fabrication strategies not possible with top-down methods. This review presents a brief summary of bottom-up and hybrid bottom-up/top-down strategies for nanoelectronics with an emphasis on memories based on the crossbar motif. First, we will discuss representative electromechanical and resistance-change memory devices based on carbon nanotube and core-shell nanowire structures, respectively. These device structures show robust switching, promising performance metrics and the potential for terabit-scale density. Second, we will review architectures being developed for circuit-level integration, hybrid crossbar/CMOS circuits and array-based systems, including experimental demonstrations of key concepts such lithography-independent, chemically coded stochastic demultipluxers. Finally, bottom-up fabrication approaches, including the opportunity for assembly of three-dimensional, vertically integrated multifunctional circuits, will be critically discussed.

High-temperature MIRAGE XL (LFRA) IRSP system development

NASA Astrophysics Data System (ADS)

McHugh, Steve; Franks, Greg; LaVeigne, Joe

2017-05-01

The development of very-large format infrared detector arrays has challenged the IR scene projector community to develop larger-format infrared emitter arrays. Many scene projector applications also require much higher simulated temperatures than can be generated with current technology. This paper will present an overview of resistive emitterbased (broadband) IR scene projector system development, as well as describe recent progress in emitter materials and pixel designs applicable for legacy MIRAGE XL Systems to achieve apparent temperatures >1000K in the MWIR. These new high temperature MIRAGE XL (LFRA) Digital Emitter Engines (DEE) will be "plug and play" equivalent with legacy MIRAGE XL DEEs, the rest of the system is reusable. Under the High Temperature Dynamic Resistive Array (HDRA) development program, Santa Barbara Infrared Inc. (SBIR) is developing a new infrared scene projector architecture capable of producing both very large format (>2k x 2k) resistive emitter arrays and improved emitter pixel technology capable of simulating very high apparent temperatures. During earlier phases of the program, SBIR demonstrated materials with MWIR apparent temperatures in excess of 1500 K. These new emitter materials can be utilized with legacy RIICs to produce pixels that can achieve 7X the radiance of the legacy systems with low cost and low risk. A 'scalable' Read-In Integrated Circuit (RIIC) is also being developed under the same HDRA program to drive the high temperature pixels. This RIIC will utilize through-silicon via (TSV) and Quilt Packaging (QP) technologies to allow seamless tiling of multiple chips to fabricate very large arrays, and thus overcome the yield limitations inherent in large-scale integrated circuits. These quilted arrays can be fabricated in any N x M size in 512 steps.

Microphotonic devices for compact planar lightwave circuits and sensor systems

NASA Astrophysics Data System (ADS)

Cardenas Gonzalez, Jaime

2005-07-01

Higher levels of integration in planar lightwave circuits and sensor systems can reduce fabrication costs and broaden viable applications for optical network and sensor systems. For example, increased integration and functionality can lead to sensor systems that are compact enough for easy transport, rugged enough for field applications, and sensitive enough even for laboratory applications. On the other hand, more functional and compact planar lightwave circuits can make optical networks components less expensive for the metro and access markets in urban areas and allow penetration of fiber to the home. Thus, there is an important area of opportunity for increased integration to provide low cost, compact solutions in both network components and sensor systems. In this dissertation, a novel splitting structure for microcantilever deflection detection is introduced. The splitting structure is designed so that its splitting ratio is dependent on the vertical position of the microcantilever. With this structure, microcantilevers sensitized to detect different analytes or biological agents can be integrated into an array on a single chip. Additionally, the integration of a depolarizer into the optoelectronic integrated circuit in an interferometric fiber optic gyroscope is presented as a means for cost reduction. The savings come in avoiding labor intensive fiber pigtailing steps by permitting batch fabrication of these components. In particular, this dissertation focuses on the design of the waveguides and polarization rotator, and the impact of imperfect components on the performance of the depolarizer. In the area of planar lightwave circuits, this dissertation presents the development of a fabrication process for single air interface bends (SAIBs). SAIBs can increase integration by reducing the area necessary to make a waveguide bend. Fabrication and measurement of a 45° SAIB with a bend efficiency of 93.4% for TM polarization and 92.7% for TE polarization are presented.

NeuroSeek dual-color image processing infrared focal plane array

NASA Astrophysics Data System (ADS)

McCarley, Paul L.; Massie, Mark A.; Baxter, Christopher R.; Huynh, Buu L.

1998-09-01

Several technologies have been developed in recent years to advance the state of the art of IR sensor systems including dual color affordable focal planes, on-focal plane array biologically inspired image and signal processing techniques and spectral sensing techniques. Pacific Advanced Technology (PAT) and the Air Force Research Lab Munitions Directorate have developed a system which incorporates the best of these capabilities into a single device. The 'NeuroSeek' device integrates these technologies into an IR focal plane array (FPA) which combines multicolor Midwave IR/Longwave IR radiometric response with on-focal plane 'smart' neuromorphic analog image processing. The readout and processing integrated circuit very large scale integration chip which was developed under this effort will be hybridized to a dual color detector array to produce the NeuroSeek FPA, which will have the capability to fuse multiple pixel-based sensor inputs directly on the focal plane. Great advantages are afforded by application of massively parallel processing algorithms to image data in the analog domain; the high speed and low power consumption of this device mimic operations performed in the human retina.

Integrated chemiresistor array for small sensor platforms

DOE Office of Scientific and Technical Information (OSTI.GOV)

HUGHES,ROBERT C.; CASALNUOVO,STEPHEN A.; WESSENDORF,KURT O.

2000-04-13

Chemiresistors are fabricated from materials that change their electrical resistance when exposed to certain chemical species. Composites of soluble polymers with metallic particles have shown remarkable sensitivity to many volatile organic chemicals, depending on the ability of the analyte molecules to swell the polymer matrix. These sensors can be made extremely small (< 100 square microns), operate at ambient temperatures, and require almost no power to read-out. However, the chemiresistor itself is only a part of a more complex sensor system that delivers chemical information to a user who can act on the information. The authors present the design, fabricationmore » and performance of a chemiresistor array chip with four different chemiresistor materials, heaters and a temperature sensor. They also show the design and fabrication of an integrated chemiresistor array, where the electronics to read-out the chemiresistors is on the same chip with the electrodes for the chemiresistors. The circuit was designed to perform several functions to make the sensor data more useful. This low-power, integrated chemiresistor array is small enough to be deployed on a Sandia-developed microrobot platform.« less

Dynamically re-configurable CMOS imagers for an active vision system

NASA Technical Reports Server (NTRS)

Yang, Guang (Inventor); Pain, Bedabrata (Inventor)

2005-01-01

A vision system is disclosed. The system includes a pixel array, at least one multi-resolution window operation circuit, and a pixel averaging circuit. The pixel array has an array of pixels configured to receive light signals from an image having at least one tracking target. The multi-resolution window operation circuits are configured to process the image. Each of the multi-resolution window operation circuits processes each tracking target within a particular multi-resolution window. The pixel averaging circuit is configured to sample and average pixels within the particular multi-resolution window.

Developing and Evaluating a Flexible Wireless Microcoil Array Based Integrated Interface for Epidural Cortical Stimulation.

PubMed

Wang, Xing; Chaudhry, Sharjeel A; Hou, Wensheng; Jia, Xiaofeng

2017-02-05

Stroke leads to serious long-term disability. Electrical epidural cortical stimulation has made significant improvements in stroke rehabilitation therapy. We developed a preliminary wireless implantable passive interface, which consists of a stimulating surface electrode, receiving coil, and single flexible passive demodulated circuit printed by flexible printed circuit (FPC) technique and output pulse voltage stimulus by inductively coupling an external circuit. The wireless implantable board was implanted in cats' unilateral epidural space for electrical stimulation of the primary visual cortex (V1) while the evoked responses were recorded on the contralateral V1 using a needle electrode. The wireless implantable board output stable monophasic voltage stimuli. The amplitude of the monophasic voltage output could be adjusted by controlling the voltage of the transmitter circuit within a range of 5-20 V. In acute experiment, cortico-cortical evoked potential (CCEP) response was recorded on the contralateral V1. The amplitude of N2 in CCEP was modulated by adjusting the stimulation intensity of the wireless interface. These results demonstrated that a wireless interface based on a microcoil array can offer a valuable tool for researchers to explore electrical stimulation in research and the dura mater-electrode interface can effectively transmit electrical stimulation.

Development of a gallium-doped germanium far-infrared photoconductor direct hybrid two-dimensional array.

PubMed

Fujiwara, Mikio; Hirao, Takanori; Kawada, Mitsunobu; Shibai, Hiroshi; Matsuura, Shuji; Kaneda, Hidehiro; Patrashin, Mikhail; Nakagawa, Takao

2003-04-20

To our knowledge, we are the first to successfully report a direct hybrid two-dimensional (2D) detector array in the far-infrared region. Gallium-doped germanium (Ge:Ga) has been used extensively to produce sensitive far-infrared detectors with a cutoff wavelength of approximately equal to 110 microm (2.7 THz). It is widely used in the fields of astronomy and molecular and solid spectroscopy. However, Ge:Ga photoconductors must be cooled below 4.2 K to reduce thermal noise, and this operating condition makes it difficult to develop a large format array because of the need for a warm amplifier. Development of Ge:Ga photoconductor arrays to take 2D terahertz images is now an important target in such research fields as space astronomy. We present the design of a 20 x 3 Ge:Ga far-infrared photoconductor array directly hybridized to a Si p-type metal-oxide-semiconductor readout integrated circuit using indium-bump technology. The main obstacles in creating this 2D array were (1) fabricating a monolithic Ge:Ga 2D array with a longitudinal configuration, (2) developing a cryogenic capacitive transimpedance amplifer, and (3) developing a technology for connecting the detector to the electronics. With this technology, a prototype Ge:Ga photoconductor with a direct hybrid structure has shown a responsivity as high as 14.6 A/W and a minimum detectable power of 5.6 x 10(-17) W for an integration time of 0.14 s when it was cooled to 2.1 K. Its noise is limited by the readout circuit with 20 microV/Hz(1/2) at 1 Hz. Vibration and cooling tests demonstrated that this direct hybrid structure is strong enough for spaceborne instruments. This detector array will be installed on the Japanese infrared satellite ASTRO-F.

A nanocryotron comparator can connect single-flux-quantum circuits to conventional electronics

NASA Astrophysics Data System (ADS)

Zhao, Qing-Yuan; McCaughan, Adam N.; Dane, Andrew E.; Berggren, Karl K.; Ortlepp, Thomas

2017-04-01

Integration with conventional electronics offers a straightforward and economical approach to upgrading existing superconducting technologies, such as scaling up superconducting detectors into large arrays and combining single flux quantum (SFQ) digital circuits with semiconductor logic gates and memories. However, direct output signals from superconducting devices (e.g., Josephson junctions) are usually not compatible with the input requirements of conventional devices (e.g., transistors). Here, we demonstrate the use of a single three-terminal superconducting-nanowire device, called the nanocryotron (nTron), as a digital comparator to combine SFQ circuits with mature semiconductor circuits such as complementary metal oxide semiconductor (CMOS) circuits. Since SFQ circuits can digitize output signals from general superconducting devices and CMOS circuits can interface existing CMOS-compatible electronics, our results demonstrate the feasibility of a general architecture that uses an nTron as an interface to realize a ‘super-hybrid’ system consisting of superconducting detectors, superconducting quantum electronics, CMOS logic gates and memories, and other conventional electronics.

Field-Programmable Gate Array-based fluxgate magnetometer with digital integration

NASA Astrophysics Data System (ADS)

Butta, Mattia; Janosek, Michal; Ripka, Pavel

2010-05-01

In this paper, a digital magnetometer based on printed circuit board fluxgate is presented. The fluxgate is pulse excited and the signal is extracted by gate integration. We investigate the possibility to perform integration on very narrow gates (typically 500 ns) by using digital techniques. The magnetometer is based on field-programmable gate array (FPGA) card: we will show all the advantages and disadvantages, given by digitalization of fluxgate output voltage by means of analog-to-digital converter on FPGA card, as well as digitalization performed by external digitizer. Due to very narrow gate, it is shown that a magnetometer entirely based on a FPGA card is preferable, because it avoids noise due to trigger instability. Both open loop and feedback operative mode are described and achieved results are presented.

VIRTEX-5 Fpga Implementation of Advanced Encryption Standard Algorithm

NASA Astrophysics Data System (ADS)

Rais, Muhammad H.; Qasim, Syed M.

2010-06-01

In this paper, we present an implementation of Advanced Encryption Standard (AES) cryptographic algorithm using state-of-the-art Virtex-5 Field Programmable Gate Array (FPGA). The design is coded in Very High Speed Integrated Circuit Hardware Description Language (VHDL). Timing simulation is performed to verify the functionality of the designed circuit. Performance evaluation is also done in terms of throughput and area. The design implemented on Virtex-5 (XC5VLX50FFG676-3) FPGA achieves a maximum throughput of 4.34 Gbps utilizing a total of 399 slices.

Interchip link system using an optical wiring method.

PubMed

Cho, In-Kui; Ryu, Jin-Hwa; Jeong, Myung-Yung

2008-08-15

A chip-scale optical link system is presented with a transmitter/receiver and optical wire link. The interchip link system consists of a metal optical bench, a printed circuit board module, a driver/receiver integrated circuit, a vertical cavity surface-emitting laser/photodiode array, and an optical wire link composed of plastic optical fibers (POFs). We have developed a downsized POF and an optical wiring method that allows on-site installation with a simple annealing as optical wiring technologies for achieving high-density optical interchip interconnection within such devices. Successful data transfer measurements are presented.

Characterization of silicon-gate CMOS/SOS integrated circuits processed with ion implantation

NASA Technical Reports Server (NTRS)

Woo, D. S.

1977-01-01

Progress in developing the application of ion implantation techniques to silicon gate CMOS/SOS processing is described. All of the conventional doping techniques such as in situ doping of the epi-film and diffusion by means of doped oxides are replaced by ion implantation. Various devices and process parameters are characterized to generate an optimum process by the use of an existing SOS test array. As a result, excellent circuit performance is achieved. A general description of the all ion implantation process is presented.

Plasmonic phased array feeder enabling ultra-fast beam steering at millimeter waves.

PubMed

Bonjour, R; Burla, M; Abrecht, F C; Welschen, S; Hoessbacher, C; Heni, W; Gebrewold, S A; Baeuerle, B; Josten, A; Salamin, Y; Haffner, C; Johnston, P V; Elder, D L; Leuchtmann, P; Hillerkuss, D; Fedoryshyn, Y; Dalton, L R; Hafner, C; Leuthold, J

2016-10-31

In this paper, we demonstrate an integrated microwave phoneeded for beamtonics phased array antenna feeder at 60 GHz with a record-low footprint. Our design is based on ultra-compact plasmonic phase modulators (active area <2.5µm²) that not only provide small size but also ultra-fast tuning speed. In our design, the integrated circuit footprint is in fact only limited by the contact pads of the electrodes and by the optical feeding waveguides. Using the high speed of the plasmonic modulators, we demonstrate beam steering with less than 1 ns reconfiguration time, i.e. the beam direction is reconfigured in-between 1 GBd transmitted symbols.

Analog bus driver and multiplexer

NASA Technical Reports Server (NTRS)

Pain, Bedabrata (Inventor); Hancock, Bruce (Inventor); Cunningham, Thomas J. (Inventor)

2012-01-01

For a source-follower signal chain, the ohmic drop in the selection switch causes unacceptable voltage offset, non-linearity, and reduced small signal gain. For an op amp signal chain, the required bias current and the output noise rises rapidly with increasing the array format due to a rapid increase in the effective capacitance caused by the Miller effect boosting up the contribution of the bus capacitance. A new switched source-follower signal chain circuit overcomes limitations of existing op-amp based or source follower based circuits used in column multiplexers and data readout. This will improve performance of CMOS imagers, and focal plane read-out integrated circuits for detectors of infrared or ultraviolet light.

A Fully Integrated Dual-Channel On-Coil CMOS Receiver for Array Coils in 1.5-10.5 T MRI.

PubMed

Sporrer, Benjamin; Wu, Lianbo; Bettini, Luca; Vogt, Christian; Reber, Jonas; Marjanovic, Josip; Burger, Thomas; Brunner, David O; Pruessmann, Klaas P; Troster, Gerhard; Huang, Qiuting

2017-12-01

Magnetic resonance imaging (MRI) is among the most important medical imaging modalities. Coil arrays and receivers with high channel counts (16 and more) have to be deployed to obtain the image quality and acquisition speed required by modern clinical protocols. In this paper, we report the theoretical analysis, the system-level design, and the circuit implementation of the first receiver IC (RXIC) for clinical MRI fully integrated in a modern CMOS technology. The dual-channel RXIC sits directly on the sensor coil, thus eliminating any RF cable otherwise required to transport the information out of the magnetic field. The first stage LNA was implemented using a noise-canceling architecture providing a highly reflective input used to decouple the individual channels of the array. Digitization is performed directly on-chip at base-band by means of a delta-sigma modulator, allowing the subsequent optical transmission of data. The presented receiver, implemented in a CMOS technology, is compatible with MRI scanners up to . It reaches sub- noise figure for MRI units and features a dynamic range up to at a power consumption below per channel, with an area occupation of . Mounted on a small-sized printed circuit board (PCB), the receiver IC has been employed in a commercial MRI scanner to acquire in-vivo images matching the quality of traditional systems, demonstrating the first step toward multichannel wearable MRI array coils.

The future of automation for high-volume wafer fabrication and ASIC manufacturing

NASA Astrophysics Data System (ADS)

Hughes, Randall A.; Shott, John D.

1986-12-01

A framework is given to analyze the future trends in semiconductor manufacturing automation systems, focusing specifically on the needs of ASIC (application-specific integrated circuit) or custom integrated circuit manufacturing. Advances in technologies such as gate arrays and standard cells now make it significantly easier to obtain system cost and performance advantages by integrating nonstandard functions on silicon. ASICs are attractive to U.S. manufacturers because they place a premium on sophisticated design tools, familiarity with customer needs and applications, and fast turn-around fabrication. These are areas where U.S. manufacturers believe they have an advantage and, consequently, will not suffer from the severe price/manufacturing competition encountered in conventional high-volume semiconductor products. Previously, automation was often considered viable only for high-volume manufacturing, but automation becomes a necessity in the new ASIC environment.

SVGA and XGA active matrix microdisplays for head-mounted applications

NASA Astrophysics Data System (ADS)

Alvelda, Phillip; Bolotski, Michael; Brown, Imani L.

2000-03-01

The MicroDisplay Corporation's liquid crystal on silicon (LCOS) display devices are based on the union of several technologies with the extreme integration capability of conventionally fabricated CMOS substrates. The fast liquid crystal operation modes and new scalable high-performance pixel addressing architectures presented in this paper enable substantially improved color, contrast, and brightness while still satisfying the optical, packaging, and power requirements of portable applications. The entire suite of MicroDisplay's technologies was devised to create a line of mixed-signal application-specific integrated circuits (ASICs) in single-chip display systems. Mixed-signal circuits can integrate computing, memory, and communication circuitry on the same substrate as the display drivers and pixel array for a multifunctional complete system-on-a-chip. System-on-a-chip benefits also include reduced head supported weight requirements through the elimination of off-chip drive electronics.

CMOS gate array characterization procedures

NASA Astrophysics Data System (ADS)

Spratt, James P.

1993-09-01

Present procedures are inadequate for characterizing the radiation hardness of gate array product lines prior to personalization because the selection of circuits to be used, from among all those available in the manufacturer's circuit library, is usually uncontrolled. (Some circuits are fundamentally more radiation resistant than others.) In such cases, differences in hardness can result between different designs of the same logic function. Hardness also varies because many gate arrays feature large custom-designed megacells (e.g., microprocessors and random access memories-MicroP's and RAM's). As a result, different product lines cannot be compared equally. A characterization strategy is needed, along with standardized test vehicle(s), methodology, and conditions, so that users can make informed judgments on which gate arrays are best suited for their needs. The program described developed preferred procedures for the radiation characterization of gate arrays, including a gate array evaluation test vehicle, featuring a canary circuit, designed to define the speed versus hardness envelope of the gate array. A multiplier was chosen for this role, and a baseline multiplier architecture is suggested that could be incorporated into an existing standard evaluation circuit chip.

ASIC For Complex Fixed-Point Arithmetic

NASA Technical Reports Server (NTRS)

Petilli, Stephen G.; Grimm, Michael J.; Olson, Erlend M.

1995-01-01

Application-specific integrated circuit (ASIC) performs 24-bit, fixed-point arithmetic operations on arrays of complex-valued input data. High-performance, wide-band arithmetic logic unit (ALU) designed for use in computing fast Fourier transforms (FFTs) and for performing ditigal filtering functions. Other applications include general computations involved in analysis of spectra and digital signal processing.

An Analysis of Heavy-Ion Single Event Effects for a Variety of Finite State-Machine Mitigation Strategies

NASA Technical Reports Server (NTRS)

Berg, Melanie D.; Label, Kenneth A.; Kim, Hak; Phan, Anthony; Seidleck, Christina

2014-01-01

Finite state-machines (FSMs) are used to control operational flow in application specific integrated circuits (ASICs) and field programmable gate array (FPGA) devices. Because of their ease of interpretation, FSMs simplify the design and verification process and consequently are significant components in a synchronous design.

Projecting light beams with 3D waveguide arrays

NASA Astrophysics Data System (ADS)

Crespi, Andrea; Bragheri, Francesca

2017-01-01

Free-space light beams with complex intensity patterns, or non-trivial phase structure, are demanded in diverse fields, ranging from classical and quantum optical communications, to manipulation and imaging of microparticles and cells. Static or dynamic spatial light modulators, acting on the phase or intensity of an incoming light wave, are the conventional choices to produce beams with such non-trivial characteristics. However, interfacing these devices with optical fibers or integrated optical circuits often requires difficult alignment or cumbersome optical setups. Here we explore theoretically and with numerical simulations the potentialities of directly using the output of engineered three-dimensional waveguide arrays, illuminated with linearly polarized light, to project light beams with peculiar structures. We investigate through a collection of illustrative configurations the far field distribution, showing the possibility to achieve orbital angular momentum, or to produce elaborate intensity or phase patterns with several singularity points. We also simulate the propagation of the projected beam, showing the possibility to concentrate light. We note that these devices should be at reach of current technology, thus perspectives are open for the generation of complex free-space optical beams from integrated waveguide circuits.

A 24-GHz portable FMCW radar with continuous beam steering phased array (Conference Presentation)

NASA Astrophysics Data System (ADS)

Peng, Zhengyu; Li, Changzhi

2017-05-01

A portable 24-GHz frequency-modulated continuous-wave (FMCW) radar with continuous beam steering phased array is presented. This board-level integrated radar system consists of a phased array antenna, a radar transceiver and a baseband. The phased array used by the receiver is a 4-element linear array. The beam of the phased array can be continuously steered with a range of ±30° on the H-plane through an array of vector controllers. The vector controller is based on the concept of vector sum with binary-phase-shift attenuators. Each vector controller is capable of independently controlling the phase and the amplitude of each element of the linear array. The radar transceiver is based on the six-port technique. A free-running voltage controlled oscillator (VCO) is controlled by an analog "sawtooth" voltage generator to produce frequency-modulated chirp signal. This chirp signal is used as the transmitter signal, as well as the local oscillator (LO) signal to drive the six-port circuit. The transmitter antenna is a single patch antenna. In the baseband, the beat signal of the FMCW radar is detected by the six-port circuit and then processed by a laptop in real time. Experiments have been performed to reveal the capabilities of the proposed radar system for applications including indoor inverse synthetic aperture radar (ISAR) imaging, vital sign detection, and short-range navigation, etc. (This abstract is for the profiles session.)

Four-to-one power combiner for 20 GHz phased array antenna using RADC MMIC phase shifters

NASA Technical Reports Server (NTRS)

1991-01-01

The design and microwave simulation of two-to-one microstrip power combiners is described. The power combiners were designed for use in a four element phase array receive antenna subarray at 20 GHz. Four test circuits are described which were designed to enable testing of the power combiner and the four element phased array antenna. Test Circuit 1 enables measurement of the two-to-one power combiner. Test Circuit 2 enables measurement of the four-to-one power combiner. Test Circuit 3 enables measurement of a four element antenna array without phase shifting MMIC's in order to characterize the power combiner with the antenna patch-to-microstrip coaxial feedthroughs. Test circuit 4 is the four element phased array antenna including the RADC MMIC phase shifters and appropriate interconnects to provide bias voltages and control phase bits.

Performance of an optical encoder based on a nondiffractive beam implemented with a specific photodetection integrated circuit and a diffractive optical element.

PubMed

Quintián, Fernando Perez; Calarco, Nicolás; Lutenberg, Ariel; Lipovetzky, José

2015-09-01

In this paper, we study the incremental signal produced by an optical encoder based on a nondiffractive beam (NDB). The NDB is generated by means of a diffractive optical element (DOE). The detection system is composed by an application specific integrated circuit (ASIC) sensor. The sensor consists of an array of eight concentric annular photodiodes, each one provided with a programmable gain amplifier. In this way, the system is able to synthesize a nonuniform detectivity. The contrast, amplitude, and harmonic content of the sinusoidal output signal are analyzed. The influence of the cross talk among the annular photodiodes is placed in evidence through the dependence of the signal contrast on the wavelength.

T/R Multi-Chip MMIC Modules for 150 GHz

NASA Technical Reports Server (NTRS)

Samoska, Lorene A.; Pukala, David M.; Soria, Mary M.; Sadowy, Gregory A.

2009-01-01

Modules containing multiple monolithic microwave integrated-circuit (MMIC) chips have been built as prototypes of transmitting/receiving (T/R) modules for millimeter-wavelength radar systems, including phased-array radar systems to be used for diverse purposes that could include guidance and avoidance of hazards for landing spacecraft, imaging systems for detecting hidden weapons, and hazard-avoidance systems for automobiles. Whereas prior landing radar systems have operated at frequencies around 35 GHz, the integrated circuits in this module operate in a frequency band centered at about 150 GHz. The higher frequency (and, hence, shorter wavelength), is expected to make it possible to obtain finer spatial resolution while also using smaller antennas and thereby reducing the sizes and masses of the affected systems.

Equivalent circuit-based analysis of CMUT cell dynamics in arrays.

PubMed

Oguz, H K; Atalar, Abdullah; Köymen, Hayrettin

2013-05-01

Capacitive micromachined ultrasonic transducers (CMUTs) are usually composed of large arrays of closely packed cells. In this work, we use an equivalent circuit model to analyze CMUT arrays with multiple cells. We study the effects of mutual acoustic interactions through the immersion medium caused by the pressure field generated by each cell acting upon the others. To do this, all the cells in the array are coupled through a radiation impedance matrix at their acoustic terminals. An accurate approximation for the mutual radiation impedance is defined between two circular cells, which can be used in large arrays to reduce computational complexity. Hence, a performance analysis of CMUT arrays can be accurately done with a circuit simulator. By using the proposed model, one can very rapidly obtain the linear frequency and nonlinear transient responses of arrays with an arbitrary number of CMUT cells. We performed several finite element method (FEM) simulations for arrays with small numbers of cells and showed that the results are very similar to those obtained by the equivalent circuit model.

CMOS Imaging of Pin-Printed Xerogel-Based Luminescent Sensor Microarrays.

PubMed

Yao, Lei; Yung, Ka Yi; Khan, Rifat; Chodavarapu, Vamsy P; Bright, Frank V

2010-12-01

We present the design and implementation of a luminescence-based miniaturized multisensor system using pin-printed xerogel materials which act as host media for chemical recognition elements. We developed a CMOS imager integrated circuit (IC) to image the luminescence response of the xerogel-based sensor array. The imager IC uses a 26 × 20 (520 elements) array of active pixel sensors and each active pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. The imager includes a correlated double sampling circuit and pixel address/digital control circuit; the image data is read-out as coded serial signal. The sensor system uses a light-emitting diode (LED) to excite the target analyte responsive luminophores doped within discrete xerogel-based sensor elements. As a prototype, we developed a 4 × 4 (16 elements) array of oxygen (O 2 ) sensors. Each group of 4 sensor elements in the array (arranged in a row) is designed to provide a different and specific sensitivity to the target gaseous O 2 concentration. This property of multiple sensitivities is achieved by using a strategic mix of two oxygen sensitive luminophores ([Ru(dpp) 3 ] 2+ and ([Ru(bpy) 3 ] 2+ ) in each pin-printed xerogel sensor element. The CMOS imager consumes an average power of 8 mW operating at 1 kHz sampling frequency driven at 5 V. The developed prototype system demonstrates a low cost and miniaturized luminescence multisensor system.

Integrated devices for quantum information and quantum simulation with polarization encoded qubits

NASA Astrophysics Data System (ADS)

Sansoni, Linda; Sciarrino, Fabio; Mataloni, Paolo; Crespi, Andrea; Ramponi, Roberta; Osellame, Roberto

2012-06-01

The ability to manipulate quantum states of light by integrated devices may open new perspectives both for fundamental tests of quantum mechanics and for novel technological applications. The technology for handling polarization-encoded qubits, the most commonly adopted approach, was still missing in quantum optical circuits until the ultrafast laser writing (ULW) technique was adopted for the first time to realize integrated devices able to support and manipulate polarization encoded qubits.1 Thanks to this method, polarization dependent and independent devices can be realized. In particular the maintenance of polarization entanglement was demonstrated in a balanced polarization independent integrated beam splitter1 and an integrated CNOT gate for polarization qubits was realized and carachterized.2 We also exploited integrated optics for quantum simulation tasks: by adopting the ULW technique an integrated quantum walk circuit was realized3 and, for the first time, we investigate how the particle statistics, either bosonic or fermionic, influences a two-particle discrete quantum walk. Such experiment has been realized by adopting two-photon entangled states and an array of integrated symmetric directional couplers. The polarization entanglement was exploited to simulate the bunching-antibunching feature of non interacting bosons and fermions. To this scope a novel three-dimensional geometry for the waveguide circuit is introduced, which allows accurate polarization independent behaviour, maintaining a remarkable control on both phase and balancement of the directional couplers.

Logarithmic current measurement circuit with improved accuracy and temperature stability and associated method

DOEpatents

Ericson, M. Nance; Rochelle, James M.

1994-01-01

A logarithmic current measurement circuit for operating upon an input electric signal utilizes a quad, dielectrically isolated, well-matched, monolithic bipolar transistor array. One group of circuit components within the circuit cooperate with two transistors of the array to convert the input signal logarithmically to provide a first output signal which is temperature-dependant, and another group of circuit components cooperate with the other two transistors of the array to provide a second output signal which is temperature-dependant. A divider ratios the first and second output signals to provide a resultant output signal which is independent of temperature. The method of the invention includes the operating steps performed by the measurement circuit.

Hybrid UV Imager Containing Face-Up AlGaN/GaN Photodiodes

NASA Technical Reports Server (NTRS)

Zheng, Xinyu; Pain, Bedabrata

2005-01-01

A proposed hybrid ultraviolet (UV) image sensor would comprise a planar membrane array of face-up AlGaN/GaN photodiodes integrated with a complementary metal oxide/semiconductor (CMOS) readout-circuit chip. Each pixel in the hybrid image sensor would contain a UV photodiode on the AlGaN/GaN membrane, metal oxide/semiconductor field-effect transistor (MOSFET) readout circuitry on the CMOS chip underneath the photodiode, and a metal via connection between the photodiode and the readout circuitry (see figure). The proposed sensor design would offer all the advantages of comparable prior CMOS active-pixel sensors and AlGaN UV detectors while overcoming some of the limitations of prior (AlGaN/sapphire)/CMOS hybrid image sensors that have been designed and fabricated according to the methodology of flip-chip integration. AlGaN is a nearly ideal UV-detector material because its bandgap is wide and adjustable and it offers the potential to attain extremely low dark current. Integration of AlGaN with CMOS is necessary because at present there are no practical means of realizing readout circuitry in the AlGaN/GaN material system, whereas the means of realizing readout circuitry in CMOS are well established. In one variant of the flip-chip approach to integration, an AlGaN chip on a sapphire substrate is inverted (flipped) and then bump-bonded to a CMOS readout circuit chip; this variant results in poor quantum efficiency. In another variant of the flip-chip approach, an AlGaN chip on a crystalline AlN substrate would be bonded to a CMOS readout circuit chip; this variant is expected to result in narrow spectral response, which would be undesirable in many applications. Two other major disadvantages of flip-chip integration are large pixel size (a consequence of the need to devote sufficient area to each bump bond) and severe restriction on the photodetector structure. The membrane array of AlGaN/GaN photodiodes and the CMOS readout circuit for the proposed image sensor would be fabricated separately.

Integrated circuit amplifiers for multi-electrode intracortical recording.

PubMed

Jochum, Thomas; Denison, Timothy; Wolf, Patrick

2009-02-01

Significant progress has been made in systems that interpret the electrical signals of the brain in order to control an actuator. One version of these systems senses neuronal extracellular action potentials with an array of up to 100 miniature probes inserted into the cortex. The impedance of each probe is high, so environmental electrical noise is readily coupled to the neuronal signal. To minimize this noise, an amplifier is placed close to each probe. Thus, the need has arisen for many amplifiers to be placed near the cortex. Commercially available integrated circuits do not satisfy the area, power and noise requirements of this application, so researchers have designed custom integrated-circuit amplifiers. This paper presents a comprehensive survey of the neural amplifiers described in publications prior to 2008. Methods to achieve high input impedance, low noise and a large time-constant high-pass filter are reviewed. A tutorial on the biological, electrochemical, mechanical and electromagnetic phenomena that influence amplifier design is provided. Areas for additional research, including sub-nanoampere electrolysis and chronic cortical heating, are discussed. Unresolved design concerns, including teraohm circuitry, electrical overstress and component failure, are identified.

An Improved Zero Potential Circuit for Readout of a Two-Dimensional Resistive Sensor Array.

PubMed

Wu, Jian-Feng; Wang, Feng; Wang, Qi; Li, Jian-Qing; Song, Ai-Guo

2016-12-06

With one operational amplifier (op-amp) in negative feedback, the traditional zero potential circuit could access one element in the two-dimensional (2-D) resistive sensor array with the shared row-column fashion but it suffered from the crosstalk problem for the non-scanned elements' bypass currents, which were injected into array's non-scanned electrodes from zero potential. Firstly, for suppressing the crosstalk problem, we designed a novel improved zero potential circuit with one more op-amp in negative feedback to sample the total bypass current and calculate the precision resistance of the element being tested (EBT) with it. The improved setting non-scanned-electrode zero potential circuit (S-NSE-ZPC) was given as an example for analyzing and verifying the performance of the improved zero potential circuit. Secondly, in the S-NSE-ZPC and the improved S-NSE-ZPC, the effects of different parameters of the resistive sensor arrays and their readout circuits on the EBT's measurement accuracy were simulated with the NI Multisim 12. Thirdly, part features of the improved circuit were verified with the experiments of a prototype circuit. Followed, the results were discussed and the conclusions were given. The experiment results show that the improved circuit, though it requires one more op-amp, one more resistor and one more sampling channel, can access the EBT in the 2-D resistive sensor array more accurately.

Experimental characterization of a bi-dimensional array of negative capacitance piezo-patches for vibroacoustic control

NASA Astrophysics Data System (ADS)

Tateo, F.; Collet, M.; Ouisse, M.; Ichchou, M. N.; Cunefare, K. A.

2013-04-01

A recent technological revolution in the fields of integrated MEMS has finally rendered possible the mechanical integration of active smart materials, electronics and power supply systems for the next generation of smart composite structures. Using a bi-dimensional array of electromechanical transducers, composed by piezo-patches connected to a synthetic negative capacitance, it is possible to modify the dynamics of the underlying structure. In this study, we present an application of the Floquet-Bloch theorem for vibroacoustic power flow optimization, by means of distributed shunted piezoelectric material. In the context of periodically distributed damped 2D mechanical systems, this numerical approach allows one to compute the multi-modal waves dispersion curves into the entire first Brillouin zone. This approach also permits optimization of the piezoelectric shunting electrical impedance, which controls energy diffusion into the proposed semi-active distributed set of cells. Furthermore, we present experimental evidence that proves the effectiveness of the proposed control method. The experiment requires a rectangular metallic plate equipped with seventy-five piezo-patches, controlled independently by electronic circuits. More specifically, the out-of-plane displacements and the averaged kinetic energy of the controlled plate are compared in two different cases (open-circuit and controlled circuit). The resulting data clearly show how this proposed technique is able to damp and selectively reflect the incident waves.

An approach for configuring space photovoltaic tandem arrays based on cell layer performance

NASA Technical Reports Server (NTRS)

Flora, C. S.; Dillard, P. A.

1991-01-01

Meeting solar array performance goals of 300 W/Kg requires use of solar cells with orbital efficiencies greater than 20 percent. Only multijunction cells and cell layers operating in tandem produce this required efficiency. An approach for defining solar array design concepts that use tandem cell layers involve the following: transforming cell layer performance at standard test conditions to on-orbit performance; optimizing circuit configuration with tandem cell layers; evaluating circuit sensitivity to cell current mismatch; developing array electrical design around selected circuit; and predicting array orbital performance including seasonal variations.

Pyroelectric Applications of the VDF-TrFE Copolymer

NASA Technical Reports Server (NTRS)

Simonne, J. J.; Bauer, Ph.; Audaire, L.; Bauer, F.

1995-01-01

VDF/TrFe pyroelectric sensors have now definitely reached the level of a product. Based on a bidimensional staring array, it can be considered as a whole system with a monolithic technology processed on a silicon substrate provided with the integrated read out circuit. The paper will describe the main procedure dealing with the elaboration of a 32 x 32 focal plane array developed, in the context of the PROMETHEUS PROCHIP European Program (EUREKA), as a passive infrared obstacle detection applied to automotive. Additional experimental data suggest that this microsystem could operate in space environment.

Transient Negative Optical Nonlinearity of Indium Oxide Nanorod Arrays in the Full-Visible Range

DOE PAGES

Guo, Peijun; Chang, Robert P. H.; Schaller, Richard D.

2017-06-09

Dynamic control of the optical response of materials at visible wavelengths is key to future metamaterials and photonic integrated circuits. Here we demonstrate large amplitude, negative optical nonlinearity (Δ n from -0.05 to -0.09) of indium oxide nanorod arrays in the full-visible range. We experimentally quantify and theoretically calculate the optical nonlinearity, which arises from the modifications of interband optical transitions. Furthermore, the approach towards negative optical nonlinearity can be generalized to other transparent semiconductors and opens door to reconfigurable, sub-wavelength optical components.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bolotnikov, A. E., E-mail: bolotnik@bnl.gov; Ackley, K.; Camarda, G. S.

We developed a robust and low-cost array of virtual Frisch-grid CdZnTe detectors coupled to a front-end readout application-specific integrated circuit (ASIC) for spectroscopy and imaging of gamma rays. The array operates as a self-reliant detector module. It is comprised of 36 close-packed 6 × 6 × 15 mm{sup 3} detectors grouped into 3 × 3 sub-arrays of 2 × 2 detectors with the common cathodes. The front-end analog ASIC accommodates up to 36 anode and 9 cathode inputs. Several detector modules can be integrated into a single- or multi-layer unit operating as a Compton or a coded-aperture camera. We presentmore » the results from testing two fully assembled modules and readout electronics. The further enhancement of the arrays’ performance and reduction of their cost are possible by using position-sensitive virtual Frisch-grid detectors, which allow for accurate corrections of the response of material non-uniformities caused by crystal defects.« less

Multilevel photonic modules for millimeter-wave phased-array antennas

NASA Astrophysics Data System (ADS)

Paolella, Arthur C.; Joshi, Abhay M.; Wright, James G.; Coryell, Louis A.

1998-11-01

Optical signal distribution for phased array antennas in communication system is advantageous to designers. By distributing the microwave and millimeter wave signal through optical fiber there is the potential for improved performance and lower weight. In addition when applied to communication satellites this weight saving translates into substantially reduced launch costs. The goal of the Phase I Small Business Innovation Research (SBIR) Program is the development of multi-level photonic modules for phased array antennas. The proposed module with ultimately comprise of a monolithic, InGaAs/InP p-i-n photodetector-p-HEMT power amplifier, opto-electronic integrated circuit, that has 44 GHz bandwidth and output power of 50 mW integrated with a planar antenna. The photodetector will have a high quantum efficiency and will be front-illuminated, thereby improved optical performance. Under Phase I a module was developed using standard MIC technology with a high frequency coaxial feed interconnect.

The design of high dynamic range ROIC for IRFPAs

NASA Astrophysics Data System (ADS)

Jiang, Dazhao; Liang, Qinghua; Zhang, Qiwen; Chen, Honglei; Ding, Ruijun

2015-10-01

The charge packet readout integrated circuit (ROIC) technology for the IRFPAs is introduced, which can realize that every pixel achieves a very high capacity of the electrons storage, and it also improves the performance of the SNR and reduces the saturation possibility of the pixels. The ROIC for the LWIR requires ability that obtaining high capacity for storing electrons. For the conventional ROIC, the maximum charge capacity is determined by the integration capacitance and the operating voltage, it can achieve a high charge capacity through increasing the area of the integration capacitor or raising the operating voltage. And this paper would introduce a digital method of ROIC that can achieve a very high charge capacity. The circuit architecture of this approach includes the following parts, a preamplifier, a comparator, a counter, and memory arrays. And the maximum charge capacity of the pixel is determined by the counter bits. This new method can achieve a high charge capacity more than 1Ge- every pixel and output the digital signal directly, while that of conventional ROIC is less than 50Me- and output the analog signal from the pixel. In this new circuit, the comparator is a important module, as the integration voltage value need compare with threshold voltage through the comparator all the time during the integration period, and we will discuss the influence of the comparator. This work design the circuit with the CSMC 0.35um CMOS technology, and the simulation use the spectre model.

System-on-Chip Considerations for Heterogeneous Integration of CMOS and Fluidic Bio-Interfaces.

PubMed

Datta-Chaudhuri, Timir; Smela, Elisabeth; Abshire, Pamela A

2016-12-01

CMOS chips are increasingly used for direct sensing and interfacing with fluidic and biological systems. While many biosensing systems have successfully combined CMOS chips for readout and signal processing with passive sensing arrays, systems that co-locate sensing with active circuits on a single chip offer significant advantages in size and performance but increase the complexity of multi-domain design and heterogeneous integration. This emerging class of lab-on-CMOS systems also poses distinct and vexing technical challenges that arise from the disparate requirements of biosensors and integrated circuits (ICs). Modeling these systems must address not only circuit design, but also the behavior of biological components on the surface of the IC and any physical structures. Existing tools do not support the cross-domain simulation of heterogeneous lab-on-CMOS systems, so we recommend a two-step modeling approach: using circuit simulation to inform physics-based simulation, and vice versa. We review the primary lab-on-CMOS implementation challenges and discuss practical approaches to overcome them. Issues include new versions of classical challenges in system-on-chip integration, such as thermal effects, floor-planning, and signal coupling, as well as new challenges that are specifically attributable to biological and fluidic domains, such as electrochemical effects, non-standard packaging, surface treatments, sterilization, microfabrication of surface structures, and microfluidic integration. We describe these concerns as they arise in lab-on-CMOS systems and discuss solutions that have been experimentally demonstrated.

Design of micro-ring optical sensors and circuits for integration on optical printed circuit boards (O-PCBs)

NASA Astrophysics Data System (ADS)

Lee, El-Hang; Lee, Hyun S.; Lee, S. G.; O, B. H.; Park, S. G.; Kim, K. H.

2007-05-01

We report on the design of micro-ring resonator optical sensors for integration on what we call optical printed circuit boards (O-PCBs). The objective is to realize application-specific O-PCBs, either on hard board or on flexible board, by integrating micro/nano-scale optical sensors for compact, light-weight, low-energy, high-speed, intelligent, and environmentally friendly processing of information. The O-PCBs consist of two-dimensional planar arrays of micro/nano-scale optical wires, circuits and devices that are interconnected and integrated to perform the functions of sensing and then storing, transporting, processing, switching, routing and distributing optical signals that have been collected by means of sensors. For fabrication, the polymer and organic optical wires and waveguides are first fabricated on a board and are used to interconnect and integrate sensors and other micro/ nano-scale photonic devices. Here, in our study, we focus on the sensors based on the micro-ring structures. We designed bio-sensors using silicon based micro-ring resonator. We investigate the characteristics such as sensitivity and selectivity (or quality factor) of micro-ring resonator for their use in bio-sensing application. We performed simulation studies on the quality factor of micro-ring resonators by varying the radius of the ring resonators and the separation between adjacent waveguides. We introduce the effective coupling coefficient as a realistic value to describe the strength of the coupling in micro-ring resonators.

Towards on-chip time-resolved thermal mapping with micro-/nanosensor arrays

PubMed Central

2012-01-01

In recent years, thin-film thermocouple (TFTC) array emerged as a versatile candidate in micro-/nanoscale local temperature sensing for its high resolution, passive working mode, and easy fabrication. However, some key issues need to be taken into consideration before real instrumentation and industrial applications of TFTC array. In this work, we will demonstrate that TFTC array can be highly scalable from micrometers to nanometers and that there are potential applications of TFTC array in integrated circuits, including time-resolvable two-dimensional thermal mapping and tracing the heat source of a device. Some potential problems and relevant solutions from a view of industrial applications will be discussed in terms of material selection, multiplexer reading, pattern designing, and cold-junction compensation. We show that the TFTC array is a powerful tool for research fields such as chip thermal management, lab-on-a-chip, and other novel electrical, optical, or thermal devices. PMID:22931306

Laterally stacked Schottky diodes for infrared sensor applications

NASA Technical Reports Server (NTRS)

Lin, True-Lon (Inventor)

1991-01-01

Laterally stacked Schottky diodes for infrared sensor applications are fabricated utilizing porous silicon having pores. A Schottky metal contract is formed in the pores, such as by electroplating. The sensors may be integrated with silicon circuits on the same chip with a high quantum efficiency, which is ideal for IR focal plane array applications due to uniformity and reproducibility.

Pentacene-based organic thin film transistors, integrated circuits, and active matrix displays on polymeric substrates

NASA Astrophysics Data System (ADS)

Sheraw, Christopher Duncan

2003-10-01

Organic thin film transistors are attractive candidates for a variety of low cost, large area commercial electronics including smart cards, RF identification tags, and flat panel displays. Of particular interest are high performance organic thin film transistors (TFTs) that can be fabricated on flexible polymeric substrates allowing low-cost, lightweight, rugged electronics such as flexible active matrix displays. This thesis reports pentacene organic thin film transistors fabricated on flexible polymeric substrates with record performance, the fastest photolithographically patterned organic TFT integrated circuits on polymeric substrates reported to date, and the fabrication of the organic TFT backplanes used to build the first organic TFT-driven active matrix liquid crystal display (AMLCD), also the first AMLCD on a flexible substrate, ever reported. In addition, the first investigation of functionalized pentacene derivatives used as the active layer in organic thin film transistors is reported. A low temperature (<110°C) process technology was developed allowing the fabrication of high performance organic TFTs, integrated circuits, and large TFT arrays on flexible polymeric substrates. This process includes the development of a novel water-based photolithographic active layer patterning process using polyvinyl alcohol that allows the patterning of organic semiconductor materials for elimination of active layer leakage current without causing device degradation. The small molecule aromatic hydrocarbon pentacene was used as the active layer material to fabricate organic TFTs on the polymeric material polyethylene naphthalate with field-effect mobility as large as 2.1 cm2/V-s and on/off current ratio of 108. These are the best values reported for organic TFTs on polymeric substrates and comparable to organic TFTs on rigid substrates. Analog and digital integrated circuits were also fabricated on polymeric substrates using pentacene TFTs with propagation delay as low as 38 musec and clocked digital circuits that operated at 1.1 kHz. These are the fastest photolithographically patterned organic TFT circuits on polymeric substrates reported to date. Finally, 16 x 16 pentacene TFT pixel arrays were fabricated on polymeric substrates and integrated with polymer dispersed liquid crystal to build an AMLCD. The pixel arrays showed good optical response to changing data signals when standard quarter-VGA display waveforms were applied. This result marks the first organic TFT-driven active matrix liquid crystal display ever reported as well as the first active matrix liquid crystal display on a flexible polymeric substrate. Lastly, functionalized pentacene derivatives were used as the active layer in organic thin film transistor materials. Functional groups were added to the pentacene molecule to influence the molecular ordering so that the amount of pi-orbital overlap would be increased allowing the potential for improved field-effect mobility. The functionalization of these materials also improves solubility allowing for the possibility of solution-processed devices and increased oxidative stability. Organic thin film transistors were fabricated using five different functionalized pentacene active layers. Devices based on the pentacene derivative triisopropylsilyl pentacene were found to have the best performance with field-effect mobility as large as 0.4 cm 2/V-s.

Development of a 1K x 1K GaAs QWIP Far IR Imaging Array

NASA Technical Reports Server (NTRS)

Jhabvala, M.; Choi, K.; Goldberg, A.; La, A.; Gunapala, S.

2003-01-01

In the on-going evolution of GaAs Quantum Well Infrared Photodetectors (QWIPs) we have developed a 1,024 x 1,024 (1K x1K), 8.4-9 microns infrared focal plane array (FPA). This 1 megapixel detector array is a hybrid using the Rockwell TCM 8050 silicon readout integrated circuit (ROIC) bump bonded to a GaAs QWIP array fabricated jointly by engineers at the Goddard Space Flight Center (GSFC) and the Army Research Laboratory (ARL). The finished hybrid is thinned at the Jet Propulsion Lab. Prior to this development the largest format array was a 512 x 640 FPA. We have integrated the 1K x 1K array into an imaging camera system and performed tests over the 40K-90K temperature range achieving BLIP performance at an operating temperature of 76K (f/2 camera system). The GaAs array is relatively easy to fabricate once the superlattice structure of the quantum wells has been defined and grown. The overall arrays costs are currently dominated by the costs associated with the silicon readout since the GaAs array fabrication is based on high yield, well-established GaAs processing capabilities. In this paper we will present the first results of our 1K x 1K QWIP array development including fabrication methodology, test data and our imaging results.

Single-cell recording and stimulation with a 16k micro-nail electrode array integrated on a 0.18 μm CMOS chip.

PubMed

Huys, Roeland; Braeken, Dries; Jans, Danny; Stassen, Andim; Collaert, Nadine; Wouters, Jan; Loo, Josine; Severi, Simone; Vleugels, Frank; Callewaert, Geert; Verstreken, Kris; Bartic, Carmen; Eberle, Wolfgang

2012-04-07

To cope with the growing needs in research towards the understanding of cellular function and network dynamics, advanced micro-electrode arrays (MEAs) based on integrated complementary metal oxide semiconductor (CMOS) circuits have been increasingly reported. Although such arrays contain a large number of sensors for recording and/or stimulation, the size of the electrodes on these chips are often larger than a typical mammalian cell. Therefore, true single-cell recording and stimulation remains challenging. Single-cell resolution can be obtained by decreasing the size of the electrodes, which inherently increases the characteristic impedance and noise. Here, we present an array of 16,384 active sensors monolithically integrated on chip, realized in 0.18 μm CMOS technology for recording and stimulation of individual cells. Successful recording of electrical activity of cardiac cells with the chip, validated with intracellular whole-cell patch clamp recordings are presented, illustrating single-cell readout capability. Further, by applying a single-electrode stimulation protocol, we could pace individual cardiac cells, demonstrating single-cell addressability. This novel electrode array could help pave the way towards solving complex interactions of mammalian cellular networks. This journal is © The Royal Society of Chemistry 2012

GaAs MMIC elements in phased-array antennas

NASA Technical Reports Server (NTRS)

Leonard, Regis F.

1988-01-01

Over the last six years NASA Lewis Research Center has carried out a program aimed at the development of advanced monolithic microwave integrated circuit technology, principally for use in phased-array antenna applications. Arising out of the Advanced Communications Technology Satellite (ACTS) program, the initial targets of the program were chips which operated at 30 and 20 GHz. Included in this group of activities were monolithic power modules with an output of 2 watts at GHz, variable phase shifters at both 20 and 30 GHz, low noise technology at 30 GHz, and a fully integrated (phase shifter, variable gain amplifier, power amplifier) transmit module at 20 GHz. Subsequent developments are centered on NASA mission requirements, particularly Space Station communications systems and deep space data communications.

High-speed logic integrated circuits with solution-processed self-assembled carbon nanotubes

NASA Astrophysics Data System (ADS)

Han, Shu-Jen; Tang, Jianshi; Kumar, Bharat; Falk, Abram; Farmer, Damon; Tulevski, George; Jenkins, Keith; Afzali, Ali; Oida, Satoshi; Ott, John; Hannon, James; Haensch, Wilfried

2017-09-01

As conventional monolithic silicon technology struggles to meet the requirements for the 7-nm technology node, there has been tremendous progress in demonstrating the scalability of carbon nanotube field-effect transistors down to the size that satisfies the 3-nm node and beyond. However, to date, circuits built with carbon nanotubes have overlooked key aspects of a practical logic technology and have stalled at simple functionality demonstrations. Here, we report high-performance complementary carbon nanotube ring oscillators using fully manufacturable processes, with a stage switching frequency of 2.82 GHz. The circuit was built on solution-processed, self-assembled carbon nanotube arrays with over 99.9% semiconducting purity, and the complementary feature was achieved by employing two different work function electrodes.

Multiple independent autonomous hydraulic oscillators driven by a common gravity head.

PubMed

Kim, Sung-Jin; Yokokawa, Ryuji; Lesher-Perez, Sasha Cai; Takayama, Shuichi

2015-06-15

Self-switching microfluidic circuits that are able to perform biochemical experiments in a parallel and autonomous manner, similar to instruction-embedded electronics, are rarely implemented. Here, we present design principles and demonstrations for gravity-driven, integrated, microfluidic pulsatile flow circuits. With a common gravity head as the only driving force, these fluidic oscillator arrays realize a wide range of periods (0.4 s-2 h) and flow rates (0.10-63 μl min(-1)) with completely independent timing between the multiple oscillator sub-circuits connected in parallel. As a model application, we perform systematic, parallel analysis of endothelial cell elongation response to different fluidic shearing patterns generated by the autonomous microfluidic pulsed flow generation system.

Modeling and analysis of cascade solar cells

NASA Technical Reports Server (NTRS)

Ho, F. D.

1986-01-01

A brief review is given of the present status of the development of cascade solar cells. It is known that photovoltaic efficiencies can be improved through this development. The designs and calculations of the multijunction cells, however, are quite complicated. The main goal is to find a method which is a compromise between accuracy and simplicity for modeling a cascade solar cell. Three approaches are presently under way, among them (1) equivalent circuit approach, (2) numerical approach, and (3) analytical approach. Here, the first and the second approaches are discussed. The equivalent circuit approach using SPICE (Simulation Program, Integrated Circuit Emphasis) to the cascade cells and the cascade-cell array is highlighted. The methods of extracting parameters for modeling are discussed.

High-speed logic integrated circuits with solution-processed self-assembled carbon nanotubes.

PubMed

Han, Shu-Jen; Tang, Jianshi; Kumar, Bharat; Falk, Abram; Farmer, Damon; Tulevski, George; Jenkins, Keith; Afzali, Ali; Oida, Satoshi; Ott, John; Hannon, James; Haensch, Wilfried

2017-09-01

As conventional monolithic silicon technology struggles to meet the requirements for the 7-nm technology node, there has been tremendous progress in demonstrating the scalability of carbon nanotube field-effect transistors down to the size that satisfies the 3-nm node and beyond. However, to date, circuits built with carbon nanotubes have overlooked key aspects of a practical logic technology and have stalled at simple functionality demonstrations. Here, we report high-performance complementary carbon nanotube ring oscillators using fully manufacturable processes, with a stage switching frequency of 2.82 GHz. The circuit was built on solution-processed, self-assembled carbon nanotube arrays with over 99.9% semiconducting purity, and the complementary feature was achieved by employing two different work function electrodes.

Advanced On-Board Processor (AOP). [for future spacecraft applications

NASA Technical Reports Server (NTRS)

1973-01-01

Advanced On-board Processor the (AOP) uses large scale integration throughout and is the most advanced space qualified computer of its class in existence today. It was designed to satisfy most spacecraft requirements which are anticipated over the next several years. The AOP design utilizes custom metallized multigate arrays (CMMA) which have been designed specifically for this computer. This approach provides the most efficient use of circuits, reduces volume, weight, assembly costs and provides for a significant increase in reliability by the significant reduction in conventional circuit interconnections. The required 69 CMMA packages are assembled on a single multilayer printed circuit board which together with associated connectors constitutes the complete AOP. This approach also reduces conventional interconnections thus further reducing weight, volume and assembly costs.

Microcoil Spring Interconnects for Ceramic Grid Array Integrated Circuits

NASA Technical Reports Server (NTRS)

Strickland, S. M.; Hester, J. D.; Gowan, A. K.; Montgomery, R. K.; Geist, D. L.; Blanche, J. F.; McGuire, G. D.; Nash, T. S.

2011-01-01

As integrated circuit miniaturization trends continue, they drive the need for smaller higher input/output (I/O) packages. Hermetically sealed ceramic area array parts are the package of choice by the space community for high reliability space flight electronic hardware. Unfortunately, the coefficient of thermal expansion mismatch between the ceramic area array package and the epoxy glass printed wiring board limits the life of the interconnecting solder joint. This work presents the results of an investigation by Marshall Space Flight Center into a method to increase the life of this second level interconnection by the use of compliant microcoil springs. The design of the spring and its attachment process are presented along with thermal cycling results of microcoil springs (MCS) compared with state-of-the-art ball and column interconnections. Vibration testing has been conducted on MCS and high lead column parts. Radio frequency simulation and measurements have been made and the MCS has been modeled and a stress analysis performed. Thermal cycling and vibration testing have shown MCS interconnects to be significantly more reliable than solder columns. Also, MCS interconnects are less prone to handling damage than solder columns. Future work that includes shock testing, incorporation into a digital signal processor board, and process evaluation of expansion from a 400 I/O device to a device with over 1,100 I/O is identified.

Medical telesensors

NASA Astrophysics Data System (ADS)

Ferrell, Trinidad L.; Crilly, P. B.; Smith, S. F.; Wintenberg, Alan L.; Britton, Charles L., Jr.; Morrison, Gilbert W.; Ericson, M. N.; Hedden, D.; Bouldin, Donald W.; Passian, A.; Downey, Todd R.; Wig, A. G.; Meriaudeau, Fabrice

1998-05-01

Medical telesensors are self-contained integrated circuits for measuring and transmitting vital signs over a distance of approximately 1-2 meters. The circuits are unhoused and contain a sensor, signal processing and modulation electronics, a spread-spectrum transmitter, an antenna and a thin-film battery. We report on a body-temperature telesensor, which is sufficiently small to be placed on a tympanic membrane in a child's ear. We also report on a pulse-oximeter telesensor and a micropack receiver/long- range transmitter unit, which receives form a telesensor array and analyzes and re-transmits the vital signs over a longer range. Signal analytics are presented for the pulse oximeter, which is currently in the form of a finger ring. A multichip module is presented as the basic signal-analysis component. The module contains a microprocessor, a field=programmable gate array, memory elements and other components necessary for determining trauma and reporting signals.

Multigigabit optical transceivers for high-data rate military applications

NASA Astrophysics Data System (ADS)

Catanzaro, Brian E.; Kuznia, Charlie

2012-01-01

Avionics has experienced an ever increasing demand for processing power and communication bandwidth. Currently deployed avionics systems require gigabit communication using opto-electronic transceivers connected with parallel optical fiber. Ultra Communications has developed a series of transceiver solutions combining ASIC technology with flip-chip bonding and advanced opto-mechanical molded optics. Ultra Communications custom high speed ASIC chips are developed using an SoS (silicon on sapphire) process. These circuits are flip chip bonded with sources (VCSEL arrays) and detectors (PIN diodes) to create an Opto-Electronic Integrated Circuit (OEIC). These have been combined with micro-optics assemblies to create transceivers with interfaces to standard fiber array (MT) cabling technology. We present an overview of the demands for transceivers in military applications and how new generation transceivers leverage both previous generation military optical transceivers as well as commercial high performance computing optical transceivers.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kishimoto, S., E-mail: syunji.kishimoto@kek.jp; Haruki, R.; Mitsui, T.

We developed a silicon avalanche photodiode (Si-APD) linear-array detector for use in nuclear resonant scattering experiments using synchrotron X-rays. The Si-APD linear array consists of 64 pixels (pixel size: 100 × 200 μm{sup 2}) with a pixel pitch of 150 μm and depletion depth of 10 μm. An ultrafast frontend circuit allows the X-ray detector to obtain a high output rate of >10{sup 7} cps per pixel. High-performance integrated circuits achieve multichannel scaling over 1024 continuous time bins with a 1 ns resolution for each pixel without dead time. The multichannel scaling method enabled us to record a time spectrummore » of the 14.4 keV nuclear radiation at each pixel with a time resolution of 1.4 ns (FWHM). This method was successfully applied to nuclear forward scattering and nuclear small-angle scattering on {sup 57}Fe.« less

Titanium dioxide nanowire sensor array integration on CMOS platform using deterministic assembly.

PubMed

Gall, Oren Z; Zhong, Xiahua; Schulman, Daniel S; Kang, Myungkoo; Razavieh, Ali; Mayer, Theresa S

2017-06-30

Nanosensor arrays have recently received significant attention due to their utility in a wide range of applications, including gas sensing, fuel cells, internet of things, and portable health monitoring systems. Less attention has been given to the production of sensor platforms in the μW range for ultra-low power applications. Here, we discuss how to scale the nanosensor energy demand by developing a process for integration of nanowire sensing arrays on a monolithic CMOS chip. This work demonstrates an off-chip nanowire fabrication method; subsequently nanowires link to a fused SiO 2 substrate using electric-field assisted directed assembly. The nanowire resistances shown in this work have the highest resistance uniformity reported to date of 18%, which enables a practical roadmap towards the coupling of nanosensors to CMOS circuits and signal processing systems. The article also presents the utility of optimizing annealing conditions of the off-chip metal-oxides prior to CMOS integration to avoid limitations of thermal budget and process incompatibility. In the context of the platform demonstrated here, directed assembly is a powerful tool that can realize highly uniform, cross-reactive arrays of different types of metal-oxide nanosensors suited for gas discrimination and signal processing systems.

Titanium dioxide nanowire sensor array integration on CMOS platform using deterministic assembly

NASA Astrophysics Data System (ADS)

Gall, Oren Z.; Zhong, Xiahua; Schulman, Daniel S.; Kang, Myungkoo; Razavieh, Ali; Mayer, Theresa S.

2017-06-01

Nanosensor arrays have recently received significant attention due to their utility in a wide range of applications, including gas sensing, fuel cells, internet of things, and portable health monitoring systems. Less attention has been given to the production of sensor platforms in the μW range for ultra-low power applications. Here, we discuss how to scale the nanosensor energy demand by developing a process for integration of nanowire sensing arrays on a monolithic CMOS chip. This work demonstrates an off-chip nanowire fabrication method; subsequently nanowires link to a fused SiO2 substrate using electric-field assisted directed assembly. The nanowire resistances shown in this work have the highest resistance uniformity reported to date of 18%, which enables a practical roadmap towards the coupling of nanosensors to CMOS circuits and signal processing systems. The article also presents the utility of optimizing annealing conditions of the off-chip metal-oxides prior to CMOS integration to avoid limitations of thermal budget and process incompatibility. In the context of the platform demonstrated here, directed assembly is a powerful tool that can realize highly uniform, cross-reactive arrays of different types of metal-oxide nanosensors suited for gas discrimination and signal processing systems.

Design automation techniques for custom LSI arrays

NASA Technical Reports Server (NTRS)

Feller, A.

1975-01-01

The standard cell design automation technique is described as an approach for generating random logic PMOS, CMOS or CMOS/SOS custom large scale integration arrays with low initial nonrecurring costs and quick turnaround time or design cycle. The system is composed of predesigned circuit functions or cells and computer programs capable of automatic placement and interconnection of the cells in accordance with an input data net list. The program generates a set of instructions to drive an automatic precision artwork generator. A series of support design automation and simulation programs are described, including programs for verifying correctness of the logic on the arrays, performing dc and dynamic analysis of MOS devices, and generating test sequences.

Optically interconnected phased arrays

NASA Technical Reports Server (NTRS)

Bhasin, Kul B.; Kunath, Richard R.

1988-01-01

Phased-array antennas are required for many future NASA missions. They will provide agile electronic beam forming for communications and tracking in the range of 1 to 100 GHz. Such phased arrays are expected to use several hundred GaAs monolithic integrated circuits (MMICs) as transmitting and receiving elements. However, the interconnections of these elements by conventional coaxial cables and waveguides add weight, reduce flexibility, and increase electrical interference. Alternative interconnections based on optical fibers, optical processing, and holography are under evaluation as possible solutions. In this paper, the current status of these techniques is described. Since high-frequency optical components such as photodetectors, lasers, and modulators are key elements in these interconnections, their performance and limitations are discussed.

Range imaging pulsed laser sensor with two-dimensional scanning of transmitted beam and scanless receiver using high-aspect avalanche photodiode array for eye-safe wavelength

NASA Astrophysics Data System (ADS)

Tsuji, Hidenobu; Imaki, Masaharu; Kotake, Nobuki; Hirai, Akihito; Nakaji, Masaharu; Kameyama, Shumpei

2017-03-01

We demonstrate a range imaging pulsed laser sensor with two-dimensional scanning of a transmitted beam and a scanless receiver using a high-aspect avalanche photodiode (APD) array for the eye-safe wavelength. The system achieves a high frame rate and long-range imaging with a relatively simple sensor configuration. We developed a high-aspect APD array for the wavelength of 1.5 μm, a receiver integrated circuit, and a range and intensity detector. By combining these devices, we realized 160×120 pixels range imaging with a frame rate of 8 Hz at a distance of about 50 m.

Integrated circuits for volumetric ultrasound imaging with 2-D CMUT arrays.

PubMed

Bhuyan, Anshuman; Choe, Jung Woo; Lee, Byung Chul; Wygant, Ira O; Nikoozadeh, Amin; Oralkan, Ömer; Khuri-Yakub, Butrus T

2013-12-01

Real-time volumetric ultrasound imaging systems require transmit and receive circuitry to generate ultrasound beams and process received echo signals. The complexity of building such a system is high due to requirement of the front-end electronics needing to be very close to the transducer. A large number of elements also need to be interfaced to the back-end system and image processing of a large dataset could affect the imaging volume rate. In this work, we present a 3-D imaging system using capacitive micromachined ultrasonic transducer (CMUT) technology that addresses many of the challenges in building such a system. We demonstrate two approaches in integrating the transducer and the front-end electronics. The transducer is a 5-MHz CMUT array with an 8 mm × 8 mm aperture size. The aperture consists of 1024 elements (32 × 32) with an element pitch of 250 μm. An integrated circuit (IC) consists of a transmit beamformer and receive circuitry to improve the noise performance of the overall system. The assembly was interfaced with an FPGA and a back-end system (comprising of a data acquisition system and PC). The FPGA provided the digital I/O signals for the IC and the back-end system was used to process the received RF echo data (from the IC) and reconstruct the volume image using a phased array imaging approach. Imaging experiments were performed using wire and spring targets, a ventricle model and a human prostrate. Real-time volumetric images were captured at 5 volumes per second and are presented in this paper.

Annual Conference on Nuclear and Space Radiation Effects, Gatlinburg, TN, July 18-21, 1983, Proceedings

NASA Technical Reports Server (NTRS)

1983-01-01

Topics discussed include radiation effects in devices; the basic mechanisms of radiation effects in structures and materials; radiation effects in integrated circuits; spacecraft charging and space radiation effects; hardness assurance for devices and systems; and radiation transport, energy deposition and charge collection. Papers are presented on the mechanisms of small instabilities in irradiated MOS transistors, on the radiation effects on oxynitride gate dielectrics, on the discharge characteristics of a simulated solar cell array, and on latchup in CMOS devices from heavy ions. Attention is also given to proton upsets in orbit, to the modeling of single-event upset in bipolar integrated circuits, to high-resolution studies of the electrical breakdown of soil, and to a finite-difference solution of Maxwell's equations in generalized nonorthogonal coordinates.

Towards a DNA Nanoprocessor: Reusable Tile-Integrated DNA Circuits.

PubMed

Gerasimova, Yulia V; Kolpashchikov, Dmitry M

2016-08-22

Modern electronic microprocessors use semiconductor logic gates organized on a silicon chip to enable efficient inter-gate communication. Here, arrays of communicating DNA logic gates integrated on a single DNA tile were designed and used to process nucleic acid inputs in a reusable format. Our results lay the foundation for the development of a DNA nanoprocessor, a small and biocompatible device capable of performing complex analyses of DNA and RNA inputs. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Design and fabrication of an infrared optical pyrometer ASIC as a diagnostic for shock physics experiments

NASA Astrophysics Data System (ADS)

Gordon, Jared

Optical pyrometry is the sensing of thermal radiation emitted from an object using a photoconductive device to convert photons into electrons, and is an important diagnostic tool in shock physics experiments. Data obtained from an optical pyrometer can be used to generate a blackbody curve of the material prior to and after being shocked by a high speed projectile. The sensing element consists of an InGaAs photodiode array, biasing circuitry, and multiple transimpedance amplifiers to boost the weak photocurrent from the noisy dark current into a signal that can eventually be digitized. Once the circuit elements have been defined, more often than not commercial-off-the-shelf (COTS) components are inadequate to satisfy every requirement for the diagnostic, and therefore a custom application specific design has to be considered. This thesis outlines the initial challenges with integrating the photodiode array block with multiple COTS transimpedance amplifiers onto a single chip, and offers a solution to a comparable optical pyrometer that uses the same type of photodiodes in conjunction with a re-designed transimpedance amplifier integrated onto a single chip. The final design includes a thorough analysis of the transimpedance amplifier along with modeling the circuit behavior which entails schematics, simulations, and layout. An alternative circuit is also investigated that incorporates an approach to multiplex the signals from each photodiode onto one data line and not only increases the viable real estate on the chip, but also improves the behavior of the photodiodes as they are subjected to less thermal load. The optical pyrometer application specific integrated circuit (ASIC) for shock physic experiments includes a transimpedance amplifier (TIA) with a 100 kΩ gain operating at bandwidth of 30 MHz, and an input-referred noise RMS current of 50 nA that is capable of driving a 50 Ω load.

Two-dimensional photonic crystal arrays for polymer:fullerene solar cells.

PubMed

Nam, Sungho; Han, Jiyoung; Do, Young Rag; Kim, Hwajeong; Yim, Sanggyu; Kim, Youngkyoo

2011-11-18

We report the application of two-dimensional (2D) photonic crystal (PC) array substrates for polymer:fullerene solar cells of which the active layer is made with blended films of poly(3-hexylthiophene) (P3HT) and [6,6]-phenyl-C61-butyric acid methyl ester (PCBM). The 2D PC array substrates were fabricated by employing a nanosphere lithography technique. Two different hole depths (200 and 300 nm) were introduced for the 2D PC arrays to examine the hole depth effect on the light harvesting (trapping). The optical effect by the 2D PC arrays was investigated by the measurement of optical transmittance either in the direction normal to the substrate (direct transmittance) or in all directions (integrated transmittance). The results showed that the integrated transmittance was higher for the 2D PC array substrates than the conventional planar substrate at the wavelengths of ca. 400 nm, even though the direct transmittance of 2D PC array substrates was much lower over the entire visible light range. The short circuit current density (J(SC)) was higher for the device with the 2D PC array (200 nm hole depth) than the reference device. However, the device with the 2D PC array (300 nm hole depth) showed a slightly lower J(SC) value at a high light intensity in spite of its light harvesting effect proven at a lower light intensity.

High-Accuracy, Compact Scanning Method and Circuit for Resistive Sensor Arrays.

PubMed

Kim, Jong-Seok; Kwon, Dae-Yong; Choi, Byong-Deok

2016-01-26

The zero-potential scanning circuit is widely used as read-out circuit for resistive sensor arrays because it removes a well known problem: crosstalk current. The zero-potential scanning circuit can be divided into two groups based on type of row drivers. One type is a row driver using digital buffers. It can be easily implemented because of its simple structure, but we found that it can cause a large read-out error which originates from on-resistance of the digital buffers used in the row driver. The other type is a row driver composed of operational amplifiers. It, very accurately, reads the sensor resistance, but it uses a large number of operational amplifiers to drive rows of the sensor array; therefore, it severely increases the power consumption, cost, and system complexity. To resolve the inaccuracy or high complexity problems founded in those previous circuits, we propose a new row driver which uses only one operational amplifier to drive all rows of a sensor array with high accuracy. The measurement results with the proposed circuit to drive a 4 × 4 resistor array show that the maximum error is only 0.1% which is remarkably reduced from 30.7% of the previous counterpart.

Infrared-Bolometer Arrays with Reflective Backshorts

NASA Technical Reports Server (NTRS)

Miller, Timothy M.; Abrahams, John; Allen, Christine A.

2011-01-01

Integrated circuits that incorporate square arrays of superconducting-transition- edge bolometers with optically reflective backshorts are being developed for use in image sensors in the spectral range from far infrared to millimeter wavelengths. To maximize the optical efficiency (and, thus, sensitivity) of such a sensor at a specific wavelength, resonant optical structures are created by placing the backshorts at a quarter wavelength behind the bolometer plane. The bolometer and backshort arrays are fabricated separately, then integrated to form a single unit denoted a backshort-under-grid (BUG) bolometer array. In a subsequent fabrication step, the BUG bolometer array is connected, by use of single-sided indium bump bonding, to a readout device that comprises mostly a superconducting quantum interference device (SQUID) multiplexer circuit. The resulting sensor unit comprising the BUG bolometer array and the readout device is operated at a temperature below 1 K. The concept of increasing optical efficiency by use of backshorts at a quarter wavelength behind the bolometers is not new. Instead, the novelty of the present development lies mainly in several features of the design of the BUG bolometer array and the fabrication sequence used to implement the design. Prior to joining with the backshort array, the bolometer array comprises, more specifically, a square grid of free-standing molybdenum/gold superconducting-transition-edge bolometer elements on a 1.4- m-thick top layer of silicon that is part of a silicon support frame made from a silicon-on-insulator wafer. The backshort array is fabricated separately as a frame structure that includes support beams and contains a correspond - ing grid of optically reflective patches on a single-crystal silicon substrate. The process used to fabricate the bolometer array includes standard patterning and etching steps that result in the formation of deep notches in the silicon support frame. These notches are designed to interlock with the support beams on the backshort-array structure to provide structural support and precise relative positioning. The backshort-array structure is inserted in the silicon support frame behind the bolometer array, and the notches in the frame serve to receive the support beams of the backshort-array structure and thus determine the distance between the backshort and bolometer planes. The depth of the notches and, thus, the distance between the backshort and bolometer planes, can be tailored to a value between 25 to 300 m adjusting only a few process steps. The backshort array is designed so as not to interfere with the placement of indium bumps for subsequent indium bump-bonding to the multiplexing readout circuitry

GaAs VLSI technology and circuit elements for DSP

NASA Astrophysics Data System (ADS)

Mikkelson, James M.

1990-10-01

Recent progress in digital GaAs circuit performance and complexity is presented to demonstrate the current capabilities of GaAs components. High density GaAs process technology and circuit design techniques are described and critical issues for achieving favorable complexity speed power and cost tradeoffs are reviewed. Some DSP building blocks are described to provide examples of what types of DSP systems could be implemented with present GaAs technology. DIGITAL GaAs CIRCUIT CAPABILITIES In the past few years the capabilities of digital GaAs circuits have dramatically increased to the VLSI level. Major gains in circuit complexity and power-delay products have been achieved by the use of silicon-like process technologies and simple circuit topologies. The very high speed and low power consumption of digital GaAs VLSI circuits have made GaAs a desirable alternative to high performance silicon in hardware intensive high speed system applications. An example of the performance and integration complexity available with GaAs VLSI circuits is the 64x64 crosspoint switch shown in figure 1. This switch which is the most complex GaAs circuit currently available is designed on a 30 gate GaAs gate array. It operates at 200 MHz and dissipates only 8 watts of power. The reasons for increasing the level of integration of GaAs circuits are similar to the reasons for the continued increase of silicon circuit complexity. The market factors driving GaAs VLSI are system design methodology system cost power and reliability. System designers are hesitant or unwilling to go backwards to previous design techniques and lower levels of integration. A more highly integrated system in a lower performance technology can often approach the performance of a system in a higher performance technology at a lower level of integration. Higher levels of integration also lower the system component count which reduces the system cost size and power consumption while improving the system reliability. For large gate count circuits the power per gate must be minimized to prevent reliability and cooling problems. The technical factors which favor increasing GaAs circuit complexity are primarily related to reducing the speed and power penalties incurred when crossing chip boundaries. Because the internal GaAs chip logic levels are not compatible with standard silicon I/O levels input receivers and output drivers are needed to convert levels. These I/O circuits add significant delay to logic paths consume large amounts of power and use an appreciable portion of the die area. The effects of these I/O penalties can be reduced by increasing the ratio of core logic to I/O on a chip. DSP operations which have a large number of logic stages between the input and the output are ideal candidates to take advantage of the performance of GaAs digital circuits. Figure 2 is a schematic representation of the I/O penalties encountered when converting from ECL levels to GaAs

Recent advances in superconducting-mixer simulations

NASA Technical Reports Server (NTRS)

Withington, S.; Kennedy, P. R.

1992-01-01

Over the last few years, considerable progress have been made in the development of techniques for fabricating high-quality superconducting circuits, and this success, together with major advances in the theoretical understanding of quantum detection and mixing at millimeter and submillimeter wavelengths, has made the development of CAD techniques for superconducting nonlinear circuits an important new enterprise. For example, arrays of quasioptical mixers are now being manufactured, where the antennas, matching networks, filters and superconducting tunnel junctions are all fabricated by depositing niobium and a variety of oxides on a single quartz substrate. There are no adjustable tuning elements on these integrated circuits, and therefore, one must be able to predict their electrical behavior precisely. This requirement, together with a general interest in the generic behavior of devices such as direct detectors and harmonic mixers, has lead us to develop a range of CAD tools for simulating the large-signal, small-signal, and noise behavior of superconducting tunnel junction circuits.

Heavy-Ion Microbeam Fault Injection into SRAM-Based FPGA Implementations of Cryptographic Circuits

NASA Astrophysics Data System (ADS)

Li, Huiyun; Du, Guanghua; Shao, Cuiping; Dai, Liang; Xu, Guoqing; Guo, Jinlong

2015-06-01

Transistors hit by heavy ions may conduct transiently, thereby introducing transient logic errors. Attackers can exploit these abnormal behaviors and extract sensitive information from the electronic devices. This paper demonstrates an ion irradiation fault injection attack experiment into a cryptographic field-programmable gate-array (FPGA) circuit. The experiment proved that the commercial FPGA chip is vulnerable to low-linear energy transfer carbon irradiation, and the attack can cause the leakage of secret key bits. A statistical model is established to estimate the possibility of an effective fault injection attack on cryptographic integrated circuits. The model incorporates the effects from temporal, spatial, and logical probability of an effective attack on the cryptographic circuits. The rate of successful attack calculated from the model conforms well to the experimental results. This quantitative success rate model can help evaluate security risk for designers as well as for the third-party assessment organizations.

Monolithic integrated circuit charge amplifier and comparator for MAMA readout

NASA Technical Reports Server (NTRS)

Cole, Edward H.; Smeins, Larry G.

1991-01-01

Prototype ICs for the Solar Heliospheric Observatory's Multi-Anode Microchannel Array (MAMA) have been developed; these ICs' charge-amplifier and comparator components were then tested with a view to pulse response and noise performance. All model performance predictions have been exceeded. Electrostatic discharge protection has been included on all IC connections; device operation over temperature has been consistent with model predictions.

Rad-Hard Structured ASIC Body of Knowledge

NASA Technical Reports Server (NTRS)

Heidecker, Jason

2013-01-01

Structured Application-Specific Integrated Circuit (ASIC) technology is a platform between traditional ASICs and Field-Programmable Gate Arrays (FPGA). The motivation behind structured ASICs is to combine the low nonrecurring engineering costs (NRE) costs of FPGAs with the high performance of ASICs. This report provides an overview of the structured ASIC platforms that are radiation-hardened and intended for space application

Handheld ultrasound array imaging device

NASA Astrophysics Data System (ADS)

Hwang, Juin-Jet; Quistgaard, Jens

1999-06-01

A handheld ultrasound imaging device, one that weighs less than five pounds, has been developed for diagnosing trauma in the combat battlefield as well as a variety of commercial mobile diagnostic applications. This handheld device consists of four component ASICs, each is designed using the state of the art microelectronics technologies. These ASICs are integrated with a convex array transducer to allow high quality imaging of soft tissues and blood flow in real time. The device is designed to be battery driven or ac powered with built-in image storage and cineloop playback capability. Design methodologies of a handheld device are fundamentally different to those of a cart-based system. As system architecture, signal and image processing algorithm as well as image control circuit and software in this device is deigned suitably for large-scale integration, the image performance of this device is designed to be adequate to the intent applications. To elongate the battery life, low power design rules and power management circuits are incorporated in the design of each component ASIC. The performance of the prototype device is currently being evaluated for various applications such as a primary image screening tool, fetal imaging in Obstetrics, foreign object detection and wound assessment for emergency care, etc.

A periodic piezoelectric smart structure with the integrated passive/active vibration-reduction performances

NASA Astrophysics Data System (ADS)

Wang, Yuxi; Niu, Shengkai; Hu, Yuantai

2017-06-01

The paper proposes a new piezoelectric smart structure with the integrated passive/active vibration-reduction performances, which is made of a series of periodic structural units. Every structural unit is made of two layers, one is an array of piezoelectric bimorphs (PBs) and one is an array of metal beams (MBs), both are connected as a whole by a metal plate. Analyses show that such a periodic smart structure possesses two aspects of vibration-reduction performance: one comes from its phonon crystal characteristics which can isolate those vibrations with the driving frequency inside the band gap(s). The other one comes from the electromechanical conversion of bent PBs, which is actively aimed at those vibrations with the driving frequency outside the band gap(s). By adjusting external inductance, the equivalent circuit of the proposed structure can be forced into parallel resonance such that most of the vibration energy is converted into electrical energy for dissipation by a resistance. Thus, an external circuit under the parallel resonance state is equivalent to a strong damping to the interrelated vibrating structure, which is just the action mechanism of the active vibration reduction performance of the proposed smart structure.

Multi-100 kW: Planar low cost solar array development

NASA Technical Reports Server (NTRS)

1982-01-01

The applicability of selected low cost options to solar array blanket design was studied by fabricating representative modules and submitting them to thermal cycle environment. Large area (5.9 x 5.9 cm) solar cells of 3 varieties were purchased: (1) Standard wraparound, (2) Copper contacts substituted for the conventional Titanium-Palladium-Silver, and (3) Standard wraparound except with gridded back contact instead of continuous metallization. The baseline cell was purchased to compare fabrication cost and to serve as a control cell during test evaluation of the other two cells. All cells were assembled into either substrate modules where the cell is individually filtered and welded to an integrated Kapton-copper circuit or into a superstrate configuration with 4 cells jointly adhered to a single sheet of microsheet and then welded to the integrated Kapton-copper circuit. Cell quality, particularly in the metallization of contacts, was less than desired. Problems were encountered with copper metallization in laying down a barrier metal which would ohmically bond to the silicon. The cells received were shunted (sintered) or with low contact pull strength (non-sintered), thus leading to the decision to solder rather than weld the copper cells to the Kapton substrate.

Simulation of quantum dynamics with integrated photonics

NASA Astrophysics Data System (ADS)

Sansoni, Linda; Sciarrino, Fabio; Mataloni, Paolo; Crespi, Andrea; Ramponi, Roberta; Osellame, Roberto

2012-12-01

In recent years, quantum walks have been proposed as promising resources for the simulation of physical quantum systems. In fact it is widely adopted to simulate quantum dynamics. Up to now single particle quantum walks have been experimentally demonstrated by different approaches, while only few experiments involving many-particle quantum walks have been realized. Here we simulate the 2-particle dynamics on a discrete time quantum walk, built on an array of integrated waveguide beam splitters. The polarization independence of the quantum walk circuit allowed us to exploit the polarization entanglement to encode the symmetry of the two-photon wavefunction, thus the bunching-antibunching behavior of non interacting bosons and fermions has been simulated. We have also characterized the possible distinguishability and decoherence effects arising in such a structure. This study is necessary in view of the realization of a quantum simulator based on an integrated optical array built on a large number of beam splitters.

Integrated Solar-Energy-Harvesting and -Storage Device

NASA Technical Reports Server (NTRS)

whitacre, Jay; Fleurial, Jean-Pierre; Mojarradi, Mohammed; Johnson, Travis; Ryan, Margaret Amy; Bugga, Ratnakumar; West, William; Surampudi, Subbarao; Blosiu, Julian

2004-01-01

A modular, integrated, completely solid-state system designed to harvest and store solar energy is under development. Called the power tile, the hybrid device consists of a photovoltaic cell, a battery, a thermoelectric device, and a charge-control circuit that are heterogeneously integrated to maximize specific energy capacity and efficiency. Power tiles could be used in a variety of space and terrestrial environments and would be designed to function with maximum efficiency in the presence of anticipated temperatures, temperature gradients, and cycles of sunlight and shadow. Because they are modular in nature, one could use a single power tile or could construct an array of as many tiles as needed. If multiple tiles are used in an array, the distributed and redundant nature of the charge control and distribution hardware provides an extremely fault-tolerant system. The figure presents a schematic view of the device.

Subwavelength grating enabled on-chip ultra-compact optical true time delay line

PubMed Central

Wang, Junjia; Ashrafi, Reza; Adams, Rhys; Glesk, Ivan; Gasulla, Ivana; Capmany, José; Chen, Lawrence R.

2016-01-01

An optical true time delay line (OTTDL) is a basic photonic building block that enables many microwave photonic and optical processing operations. The conventional design for an integrated OTTDL that is based on spatial diversity uses a length-variable waveguide array to create the optical time delays, which can introduce complexities in the integrated circuit design. Here we report the first ever demonstration of an integrated index-variable OTTDL that exploits spatial diversity in an equal length waveguide array. The approach uses subwavelength grating waveguides in silicon-on-insulator (SOI), which enables the realization of OTTDLs having a simple geometry and that occupy a compact chip area. Moreover, compared to conventional wavelength-variable delay lines with a few THz operation bandwidth, our index-variable OTTDL has an extremely broad operation bandwidth practically exceeding several tens of THz, which supports operation for various input optical signals with broad ranges of central wavelength and bandwidth. PMID:27457024

Subwavelength grating enabled on-chip ultra-compact optical true time delay line.

PubMed

Wang, Junjia; Ashrafi, Reza; Adams, Rhys; Glesk, Ivan; Gasulla, Ivana; Capmany, José; Chen, Lawrence R

2016-07-26

An optical true time delay line (OTTDL) is a basic photonic building block that enables many microwave photonic and optical processing operations. The conventional design for an integrated OTTDL that is based on spatial diversity uses a length-variable waveguide array to create the optical time delays, which can introduce complexities in the integrated circuit design. Here we report the first ever demonstration of an integrated index-variable OTTDL that exploits spatial diversity in an equal length waveguide array. The approach uses subwavelength grating waveguides in silicon-on-insulator (SOI), which enables the realization of OTTDLs having a simple geometry and that occupy a compact chip area. Moreover, compared to conventional wavelength-variable delay lines with a few THz operation bandwidth, our index-variable OTTDL has an extremely broad operation bandwidth practically exceeding several tens of THz, which supports operation for various input optical signals with broad ranges of central wavelength and bandwidth.

Large-Aperture Membrane Active Phased-Array Antennas

NASA Technical Reports Server (NTRS)

Karasik, Boris; McGrath, William; Leduc, Henry

2009-01-01

Large-aperture phased-array microwave antennas supported by membranes are being developed for use in spaceborne interferometric synthetic aperture radar systems. There may also be terrestrial uses for such antennas supported on stationary membranes, large balloons, and blimps. These antennas are expected to have areal mass densities of about 2 kg/sq m, satisfying a need for lightweight alternatives to conventional rigid phased-array antennas, which have typical areal mass densities between 8 and 15 kg/sq m. The differences in areal mass densities translate to substantial differences in total mass in contemplated applications involving aperture areas as large as 400 sq m. A membrane phased-array antenna includes patch antenna elements in a repeating pattern. All previously reported membrane antennas were passive antennas; this is the first active membrane antenna that includes transmitting/receiving (T/R) electronic circuits as integral parts. Other integral parts of the antenna include a network of radio-frequency (RF) feed lines (more specifically, a corporate feed network) and of bias and control lines, all in the form of flexible copper strip conductors on flexible polymeric membranes. Each unit cell of a prototype antenna (see Figure 1) contains a patch antenna element and a compact T/R module that is compatible with flexible membrane circuitry. There are two membrane layers separated by a 12.7-mm air gap. Each membrane layer is made from a commercially available flexible circuit material that, as supplied, comprises a 127-micron-thick polyimide dielectric layer clad on both sides with 17.5-micron-thick copper layers. The copper layers are patterned into RF, bias, and control conductors. The T/R module is located on the back side of the ground plane and is RF-coupled to the patch element via a slot. The T/R module is a hybrid multilayer module assembled and packaged independently and attached to the membrane array. At the time of reporting the information for this article, an 8 16 passive array (not including T/R modules) and a 2 4 active array (including T/R modules) had been demonstrated, and it was planned to fabricate and test larger arrays.

Digital Parallel Processor Array for Optimum Path Planning

NASA Technical Reports Server (NTRS)

Kremeny, Sabrina E. (Inventor); Fossum, Eric R. (Inventor); Nixon, Robert H. (Inventor)

1996-01-01

The invention computes the optimum path across a terrain or topology represented by an array of parallel processor cells interconnected between neighboring cells by links extending along different directions to the neighboring cells. Such an array is preferably implemented as a high-speed integrated circuit. The computation of the optimum path is accomplished by, in each cell, receiving stimulus signals from neighboring cells along corresponding directions, determining and storing the identity of a direction along which the first stimulus signal is received, broadcasting a subsequent stimulus signal to the neighboring cells after a predetermined delay time, whereby stimulus signals propagate throughout the array from a starting one of the cells. After propagation of the stimulus signal throughout the array, a master processor traces back from a selected destination cell to the starting cell along an optimum path of the cells in accordance with the identity of the directions stored in each of the cells.

Ka-band MMIC subarray technology program (Ka-Mist)

NASA Technical Reports Server (NTRS)

Pottenger, Warren

1995-01-01

The broad objective of this program was to demonstrate a proof of concept insertion of Monolithic Microwave Integrated Circuit (MMIC) device technology into an innovative (tile architecture) active phased array antenna application supporting advanced EHF communication systems. Ka-band MMIC arrays have long been considered as having high potential for increasing the capability of space, aircraft, and land mobile communication systems in terms of scan performance, data rate, link margin, and flexibility while offering a significant reduction in size, weight, and power consumption. Insertion of MMIC technology into antenna systems, particularly at millimeter wave frequencies using low power and low noise amplifiers in close proximity to the radiating elements, offers a significant improvement in the array transmit efficiency, receive system noise figure, and overall array reliability. Application of active array technology also leads to the use of advanced beamforming techniques that can improve beam agility, diversity, and adaptivity to complex signal environments.

Patterning two-dimensional chalcogenide crystals of Bi2Se3 and In2Se3 and efficient photodetectors

PubMed Central

Zheng, Wenshan; Xie, Tian; Zhou, Yu; Chen, Y.L.; Jiang, Wei; Zhao, Shuli; Wu, Jinxiong; Jing, Yumei; Wu, Yue; Chen, Guanchu; Guo, Yunfan; Yin, Jianbo; Huang, Shaoyun; Xu, H.Q.; Liu, Zhongfan; Peng, Hailin

2015-01-01

Patterning of high-quality two-dimensional chalcogenide crystals with unique planar structures and various fascinating electronic properties offers great potential for batch fabrication and integration of electronic and optoelectronic devices. However, it remains a challenge that requires accurate control of the crystallization, thickness, position, orientation and layout. Here we develop a method that combines microintaglio printing with van der Waals epitaxy to efficiently pattern various single-crystal two-dimensional chalcogenides onto transparent insulating mica substrates. Using this approach, we have patterned large-area arrays of two-dimensional single-crystal Bi2Se3 topological insulator with a record high Hall mobility of ∼1,750 cm2 V−1 s−1 at room temperature. Furthermore, our patterned two-dimensional In2Se3 crystal arrays have been integrated and packaged to flexible photodetectors, yielding an ultrahigh external photoresponsivity of ∼1,650 A W−1 at 633 nm. The facile patterning, integration and packaging of high-quality two-dimensional chalcogenide crystals hold promise for innovations of next-generation photodetector arrays, wearable electronics and integrated optoelectronic circuits. PMID:25898022

Micro-Electronic Nose System

NASA Astrophysics Data System (ADS)

Zee, Frank C.

2011-12-01

The ability to "smell" various gas vapors and complex odors is important for many applications such as environmental monitoring for detecting toxic gases as well as quality control in the processing of food, cosmetics, and other chemical products for commercial industries. Mimicking the architecture of the biological nose, a miniature electronic nose system was designed and developed consisting of an array of sensor devices, signal-processing circuits, and software pattern-recognition algorithms. The array of sensors used polymer/carbon-black composite thin-films, which would swell or expand reversibly and reproducibly and cause a resistance change upon exposure to a wide variety of gases. Two types of sensor devices were fabricated using silicon micromachining techniques to form "wells" that confined the polymer/carbon-black to a small and specific area. The first type of sensor device formed the "well" by etching into the silicon substrate using bulk micromachining. The second type built a high-aspect-ratio "well" on the surface of a silicon wafer using SU-8 photoresist. Two sizes of "wells" were fabricated: 500 x 600 mum² and 250 x 250 mum². Custom signal-processing circuits were implemented on a printed circuit board and as an application-specific integrated-circuit (ASIC) chip. The circuits were not only able to measure and amplify the small resistance changes, which corresponded to small ppm (parts-per-million) changes in gas concentrations, but were also adaptable to accommodate the various characteristics of the different thin-films. Since the thin-films were not specific to any one particular gas vapor, an array of sensors each containing a different thin-film was used to produce a distributed response pattern when exposed to a gas vapor. Pattern recognition, including a clustering algorithm and two artificial neural network algorithms, was used to classify the response pattern and identify the gas vapor or odor. Two gas experiments were performed, one at low gas concentrations between 100 and 600 ppm for two gas vapors and the other at high gas concentrations between 2000 ppm and the saturated vapor pressure of three gas vapors. The array of sensors and circuits were able to uniquely detect and measure these gas vapors and showed a linear response to their concentration levels for both experiments. The results also demonstrated that a reduction in the sensor area by two orders of magnitude (from 4.32 mm² to 0.0625 mm²) did not affect the sensor response. By applying pattern-recognition algorithms, the electronic nose system was able to correctly identify the different gas vapors from the pattern responses of the sensor array.

Banning PRF programmer's manual. [considering MOS integrated circuits

NASA Technical Reports Server (NTRS)

Kuelthau, R. L.

1970-01-01

This manual describes a modification of the Banning placement routing folding program. The modifications to this program have been made to implement it on a Sigma 5 computer. Flow charts of various levels, beginning with high level functional diagrams and working down to the level of detail deemed necessary to understand the operations of the various sections of the program are included. Along with the flow charts of each subroutine is a narrative description of its functional operation and definitions of its arrays and key variables, and a section to assist the programmer in dimensioning the program's arrays.

A control system based on field programmable gate array for papermaking sewage treatment

NASA Astrophysics Data System (ADS)

Zhang, Zi Sheng; Xie, Chang; Qing Xiong, Yan; Liu, Zhi Qiang; Li, Qing

2013-03-01

A sewage treatment control system is designed to improve the efficiency of papermaking wastewater treatment system. The automation control system is based on Field Programmable Gate Array (FPGA), coded with Very-High-Speed Integrate Circuit Hardware Description Language (VHDL), compiled and simulated with Quartus. In order to ensure the stability of the data used in FPGA, the data is collected through temperature sensors, water level sensor and online PH measurement system. The automatic control system is more sensitive, and both the treatment efficiency and processing power are increased. This work provides a new method for sewage treatment control.

A Spaceborne Synthetic Aperture Radar Partial Fixed-Point Imaging System Using a Field- Programmable Gate Array-Application-Specific Integrated Circuit Hybrid Heterogeneous Parallel Acceleration Technique.

PubMed

Yang, Chen; Li, Bingyi; Chen, Liang; Wei, Chunpeng; Xie, Yizhuang; Chen, He; Yu, Wenyue

2017-06-24

With the development of satellite load technology and very large scale integrated (VLSI) circuit technology, onboard real-time synthetic aperture radar (SAR) imaging systems have become a solution for allowing rapid response to disasters. A key goal of the onboard SAR imaging system design is to achieve high real-time processing performance with severe size, weight, and power consumption constraints. In this paper, we analyse the computational burden of the commonly used chirp scaling (CS) SAR imaging algorithm. To reduce the system hardware cost, we propose a partial fixed-point processing scheme. The fast Fourier transform (FFT), which is the most computation-sensitive operation in the CS algorithm, is processed with fixed-point, while other operations are processed with single precision floating-point. With the proposed fixed-point processing error propagation model, the fixed-point processing word length is determined. The fidelity and accuracy relative to conventional ground-based software processors is verified by evaluating both the point target imaging quality and the actual scene imaging quality. As a proof of concept, a field- programmable gate array-application-specific integrated circuit (FPGA-ASIC) hybrid heterogeneous parallel accelerating architecture is designed and realized. The customized fixed-point FFT is implemented using the 130 nm complementary metal oxide semiconductor (CMOS) technology as a co-processor of the Xilinx xc6vlx760t FPGA. A single processing board requires 12 s and consumes 21 W to focus a 50-km swath width, 5-m resolution stripmap SAR raw data with a granularity of 16,384 × 16,384.

A 128 x 128 CMOS Active Pixel Image Sensor for Highly Integrated Imaging Systems

NASA Technical Reports Server (NTRS)

Mendis, Sunetra K.; Kemeny, Sabrina E.; Fossum, Eric R.

1993-01-01

A new CMOS-based image sensor that is intrinsically compatible with on-chip CMOS circuitry is reported. The new CMOS active pixel image sensor achieves low noise, high sensitivity, X-Y addressability, and has simple timing requirements. The image sensor was fabricated using a 2 micrometer p-well CMOS process, and consists of a 128 x 128 array of 40 micrometer x 40 micrometer pixels. The CMOS image sensor technology enables highly integrated smart image sensors, and makes the design, incorporation and fabrication of such sensors widely accessible to the integrated circuit community.

Development of computer informational system of diagnostics integrated optical materials, elements, and devices

NASA Astrophysics Data System (ADS)

Volosovitch, Anatoly E.; Konopaltseva, Lyudmila I.

1995-11-01

Well-known methods of optical diagnostics, database for their storage, as well as expert system (ES) for their development are analyzed. A computer informational system is developed, which is based on a hybrid ES built on modern DBMS. As an example, the structural and constructive circuits of the hybrid integrated-optical devices based on laser diodes, diffusion waveguides, geodetic lenses, package-free linear photodiode arrays, etc. are presented. The features of methods and test results as well as the advanced directions of works related to the hybrid integrated-optical devices in the field of metrology are discussed.

Electrically driven monolithic subwavelength plasmonic interconnect circuits

PubMed Central

Liu, Yang; Zhang, Jiasen; Liu, Huaping; Wang, Sheng; Peng, Lian-Mao

2017-01-01

In the post-Moore era, an electrically driven monolithic optoelectronic integrated circuit (OEIC) fabricated from a single material is pursued globally to enable the construction of wafer-scale compact computing systems with powerful processing capabilities and low-power consumption. We report a monolithic plasmonic interconnect circuit (PIC) consisting of a photovoltaic (PV) cascading detector, Au-strip waveguides, and electrically driven surface plasmon polariton (SPP) sources. These components are fabricated from carbon nanotubes (CNTs) via a CMOS (complementary metal-oxide semiconductor)–compatible doping-free technique in the same feature size, which can be reduced to deep-subwavelength scale (~λ/7 to λ/95, λ = 1340 nm) compared with the 14-nm technique node. An OEIC could potentially be configured as a repeater for data transport because of its “photovoltaic” operation mode to transform SPP energy directly into electricity to drive subsequent electronic circuits. Moreover, chip-scale throughput capability has also been demonstrated by fabricating a 20 × 20 PIC array on a 10 mm × 10 mm wafer. Tailoring photonics for monolithic integration with electronics beyond the diffraction limit opens a new era of chip-level nanoscale electronic-photonic systems, introducing a new path to innovate toward much faster, smaller, and cheaper computing frameworks. PMID:29062890

Training and operation of an integrated neuromorphic network based on metal-oxide memristors.

PubMed

Prezioso, M; Merrikh-Bayat, F; Hoskins, B D; Adam, G C; Likharev, K K; Strukov, D B

2015-05-07

Despite much progress in semiconductor integrated circuit technology, the extreme complexity of the human cerebral cortex, with its approximately 10(14) synapses, makes the hardware implementation of neuromorphic networks with a comparable number of devices exceptionally challenging. To provide comparable complexity while operating much faster and with manageable power dissipation, networks based on circuits combining complementary metal-oxide-semiconductors (CMOSs) and adjustable two-terminal resistive devices (memristors) have been developed. In such circuits, the usual CMOS stack is augmented with one or several crossbar layers, with memristors at each crosspoint. There have recently been notable improvements in the fabrication of such memristive crossbars and their integration with CMOS circuits, including first demonstrations of their vertical integration. Separately, discrete memristors have been used as artificial synapses in neuromorphic networks. Very recently, such experiments have been extended to crossbar arrays of phase-change memristive devices. The adjustment of such devices, however, requires an additional transistor at each crosspoint, and hence these devices are much harder to scale than metal-oxide memristors, whose nonlinear current-voltage curves enable transistor-free operation. Here we report the experimental implementation of transistor-free metal-oxide memristor crossbars, with device variability sufficiently low to allow operation of integrated neural networks, in a simple network: a single-layer perceptron (an algorithm for linear classification). The network can be taught in situ using a coarse-grain variety of the delta rule algorithm to perform the perfect classification of 3 × 3-pixel black/white images into three classes (representing letters). This demonstration is an important step towards much larger and more complex memristive neuromorphic networks.

MIRAGE: developments in IRSP systems, RIIC design, emitter fabrication, and performance

NASA Astrophysics Data System (ADS)

Bryant, Paul; Oleson, Jim; James, Jay; McHugh, Steve; Lannon, John; Vellenga, David; Goodwin, Scott; Huffman, Alan; Solomon, Steve; Goldsmith, George C., II

2005-05-01

SBIR's family of MIRAGE infrared scene projection systems is undergoing significant growth and expansion. The first two lots of production IR emitters have completed fabrication at Microelectronics Center of North Carolina/Research and Development Institute (MCNC-RDI), and the next round(s) of emitter production has begun. These latest emitter arrays support programs such as Large Format Resistive Array (LFRA), Optimized Array for Space-based Infrared Simulation (OASIS), MIRAGE 1.5, and MIRAGE II. We present the latest performance data on emitters fabricated at MCNC-RDI, plus integrated system performance on recently completed IRSP systems. Teamed with FLIR Systems/Indigo Operations, SBIR and the Tri-Services IRSP Working Group have completed development of the CMOS Read-In Integrated Circuit (RIIC) portion of the Wide Format Resistive Array (WFRA) program-to extend LFRA performance to a 768 x 1536 "wide screen" projection configuration. WFRA RIIC architecture and performance is presented. Finally, we summarize development of the LFRA Digital Emitter Engine (DEE) and OASIS cryogenic package assemblies, the next-generation Command & Control Electronics (C&CE).

An array of virtual Frisch-grid CdZnTe detectors and a front-end application-specific integrated circuit for large-area position-sensitive gamma-ray cameras

DOE PAGES

Bolotnikov, A. E.; Ackley, K.; Camarda, G. S.; ...

2015-07-28

We developed a robust and low-cost array of virtual Frisch-grid CdZnTe (CZT) detectors coupled to a front-end readout ASIC for spectroscopy and imaging of gamma rays. The array operates as a self-reliant detector module. It is comprised of 36 close-packed 6x6x15 mm 3 detectors grouped into 3x3 sub-arrays of 2x2 detectors with the common cathodes. The front-end analog ASIC accommodates up to 36 anode and 9 cathode inputs. Several detector modules can be integrated into a single- or multi-layer unit operating as a Compton or a coded-aperture camera. We present the results from testing two fully assembled modules and readoutmore » electronics. The further enhancement of the arrays’ performance and reduction of their cost are made possible by using position-sensitive virtual Frisch-grid detectors, which allow for accurate corrections of the response of material non-uniformities caused by crystal defects.« less

An Improved Zero Potential Circuit for Readout of a Two-Dimensional Resistive Sensor Array

PubMed Central

Wu, Jian-Feng; Wang, Feng; Wang, Qi; Li, Jian-Qing; Song, Ai-Guo

2016-01-01

With one operational amplifier (op-amp) in negative feedback, the traditional zero potential circuit could access one element in the two-dimensional (2-D) resistive sensor array with the shared row-column fashion but it suffered from the crosstalk problem for the non-scanned elements’ bypass currents, which were injected into array’s non-scanned electrodes from zero potential. Firstly, for suppressing the crosstalk problem, we designed a novel improved zero potential circuit with one more op-amp in negative feedback to sample the total bypass current and calculate the precision resistance of the element being tested (EBT) with it. The improved setting non-scanned-electrode zero potential circuit (S-NSE-ZPC) was given as an example for analyzing and verifying the performance of the improved zero potential circuit. Secondly, in the S-NSE-ZPC and the improved S-NSE-ZPC, the effects of different parameters of the resistive sensor arrays and their readout circuits on the EBT’s measurement accuracy were simulated with the NI Multisim 12. Thirdly, part features of the improved circuit were verified with the experiments of a prototype circuit. Followed, the results were discussed and the conclusions were given. The experiment results show that the improved circuit, though it requires one more op-amp, one more resistor and one more sampling channel, can access the EBT in the 2-D resistive sensor array more accurately. PMID:27929410

High-Accuracy, Compact Scanning Method and Circuit for Resistive Sensor Arrays

PubMed Central

Kim, Jong-Seok; Kwon, Dae-Yong; Choi, Byong-Deok

2016-01-01

The zero-potential scanning circuit is widely used as read-out circuit for resistive sensor arrays because it removes a well known problem: crosstalk current. The zero-potential scanning circuit can be divided into two groups based on type of row drivers. One type is a row driver using digital buffers. It can be easily implemented because of its simple structure, but we found that it can cause a large read-out error which originates from on-resistance of the digital buffers used in the row driver. The other type is a row driver composed of operational amplifiers. It, very accurately, reads the sensor resistance, but it uses a large number of operational amplifiers to drive rows of the sensor array; therefore, it severely increases the power consumption, cost, and system complexity. To resolve the inaccuracy or high complexity problems founded in those previous circuits, we propose a new row driver which uses only one operational amplifier to drive all rows of a sensor array with high accuracy. The measurement results with the proposed circuit to drive a 4 × 4 resistor array show that the maximum error is only 0.1% which is remarkably reduced from 30.7% of the previous counterpart. PMID:26821029

A High-Voltage Integrated Circuit Engine for a Dielectrophoresis-based Programmable Micro-Fluidic Processor

PubMed Central

Current, K. Wayne; Yuk, Kelvin; McConaghy, Charles; Gascoyne, Peter R. C.; Schwartz, Jon A.; Vykoukal, Jody V.; Andrews, Craig

2010-01-01

A high-voltage (HV) integrated circuit has been demonstrated to transport droplets on programmable paths across its coated surface. This chip is the engine for a dielectrophoresis (DEP)-based micro-fluidic lab-on-a-chip system. This chip creates DEP forces that move and help inject droplets. Electrode excitation voltage and frequency are variable. With the electrodes driven with a 100V peak-to-peak periodic waveform, the maximum high-voltage electrode waveform frequency is about 200Hz. Data communication rate is variable up to 250kHz. This demonstration chip has a 32×32 array of nominally 100V electrode drivers. It is fabricated in a 130V SOI CMOS fabrication technology, dissipates a maximum of 1.87W, and is about 10.4 mm × 8.2 mm. PMID:23989241

Low-loss compact multilayer silicon nitride platform for 3D photonic integrated circuits.

PubMed

Shang, Kuanping; Pathak, Shibnath; Guan, Binbin; Liu, Guangyao; Yoo, S J B

2015-08-10

We design, fabricate, and demonstrate a silicon nitride (Si(3)N(4)) multilayer platform optimized for low-loss and compact multilayer photonic integrated circuits. The designed platform, with 200 nm thick waveguide core and 700 nm interlayer gap, is compatible for active thermal tuning and applicable to realizing compact photonic devices such as arrayed waveguide gratings (AWGs). We achieve ultra-low loss vertical couplers with 0.01 dB coupling loss, multilayer crossing loss of 0.167 dB at 90° crossing angle, 50 μm bending radius, 100 × 2 μm(2) footprint, lateral misalignment tolerance up to 400 nm, and less than -52 dB interlayer crosstalk at 1550 nm wavelength. Based on the designed platform, we demonstrate a 27 × 32 × 2 multilayer star coupler.

Twenty-four-micrometer-pitch microelectrode array with 6912-channel readout at 12 kHz via highly scalable implementation for high-spatial-resolution mapping of action potentials.

PubMed

Ogi, Jun; Kato, Yuri; Matoba, Yoshihisa; Yamane, Chigusa; Nagahata, Kazunori; Nakashima, Yusaku; Kishimoto, Takuya; Hashimoto, Shigeki; Maari, Koichi; Oike, Yusuke; Ezaki, Takayuki

2017-12-19

A 24-μm-pitch microelectrode array (MEA) with 6912 readout channels at 12 kHz and 23.2-μV rms random noise is presented. The aim is to reduce noise in a "highly scalable" MEA with a complementary metal-oxide-semiconductor integration circuit (CMOS-MEA), in which a large number of readout channels and a high electrode density can be expected. Despite the small dimension and the simplicity of the in-pixel circuit for the high electrode-density and the relatively large number of readout channels of the prototype CMOS-MEA chip developed in this work, the noise within the chip is successfully reduced to less than half that reported in a previous work, for a device with similar in-pixel circuit simplicity and a large number of readout channels. Further, the action potential was clearly observed on cardiomyocytes using the CMOS-MEA. These results indicate the high-scalability of the CMOS-MEA. The highly scalable CMOS-MEA provides high-spatial-resolution mapping of cell action potentials, and the mapping can aid understanding of complex activities in cells, including neuron network activities.

Infrared sensors for Earth observation missions

NASA Astrophysics Data System (ADS)

Ashcroft, P.; Thorne, P.; Weller, H.; Baker, I.

2007-10-01

SELEX S&AS is developing a family of infrared sensors for earth observation missions. The spectral bands cover shortwave infrared (SWIR) channels from around 1μm to long-wave infrared (LWIR) channels up to 15μm. Our mercury cadmium telluride (MCT) technology has enabled a sensor array design that can satisfy the requirements of all of the SWIR and medium-wave infrared (MWIR) bands with near-identical arrays. This is made possible by the combination of a set of existing technologies that together enable a high degree of flexibility in the pixel geometry, sensitivity, and photocurrent integration capacity. The solution employs a photodiode array under the control of a readout integrated circuit (ROIC). The ROIC allows flexible geometries and in-pixel redundancy to maximise operability and reliability, by combining the photocurrent from a number of photodiodes into a single pixel. Defective or inoperable diodes (or "sub-pixels") can be deselected with tolerable impact on the overall pixel performance. The arrays will be fabricated using the "loophole" process in MCT grown by liquid-phase epitaxy (LPE). These arrays are inherently robust, offer high quantum efficiencies and have been used in previous space programs. The use of loophole arrays also offers access to SELEX's avalanche photodiode (APD) technology, allowing low-noise, highly uniform gain at the pixel level where photon flux is very low.

Applications of SPICE for modeling miniaturized biomedical sensor systems

NASA Technical Reports Server (NTRS)

Mundt, C. W.; Nagle, H. T.

2000-01-01

This paper proposes a model for a miniaturized signal conditioning system for biopotential and ion-selective electrode arrays. The system consists of three main components: sensors, interconnections, and signal conditioning chip. The model for this system is based on SPICE. Transmission-line based equivalent circuits are used to represent the sensors, lumped resistance-capacitance circuits describe the interconnections, and a model for the signal conditioning chip is extracted from its layout. A system for measurements of biopotentials and ionic activities can be miniaturized and optimized for cardiovascular applications based on the development of an integrated SPICE system model of its electrochemical, interconnection, and electronic components.

Solid state television camera

NASA Technical Reports Server (NTRS)

1976-01-01

The design, fabrication, and tests of a solid state television camera using a new charge-coupled imaging device are reported. An RCA charge-coupled device arranged in a 512 by 320 format and directly compatible with EIA format standards was the sensor selected. This is a three-phase, sealed surface-channel array that has 163,840 sensor elements, which employs a vertical frame transfer system for image readout. Included are test results of the complete camera system, circuit description and changes to such circuits as a result of integration and test, maintenance and operation section, recommendations to improve the camera system, and a complete set of electrical and mechanical drawing sketches.

A novel high electrode count spike recording array using an 81,920 pixel transimpedance amplifier-based imaging chip.

PubMed

Johnson, Lee J; Cohen, Ethan; Ilg, Doug; Klein, Richard; Skeath, Perry; Scribner, Dean A

2012-04-15

Microelectrode recording arrays of 60-100 electrodes are commonly used to record neuronal biopotentials, and these have aided our understanding of brain function, development and pathology. However, higher density microelectrode recording arrays of larger area are needed to study neuronal function over broader brain regions such as in cerebral cortex or hippocampal slices. Here, we present a novel design of a high electrode count picocurrent imaging array (PIA), based on an 81,920 pixel Indigo ISC9809 readout integrated circuit camera chip. While originally developed for interfacing to infrared photodetector arrays, we have adapted the chip for neuron recording by bonding it to microwire glass resulting in an array with an inter-electrode pixel spacing of 30 μm. In a high density electrode array, the ability to selectively record neural regions at high speed and with good signal to noise ratio are both functionally important. A critical feature of our PIA is that each pixel contains a dedicated low noise transimpedance amplifier (∼0.32 pA rms) which allows recording high signal to noise ratio biocurrents comparable to single electrode voltage amplifier recordings. Using selective sampling of 256 pixel subarray regions, we recorded the extracellular biocurrents of rabbit retinal ganglion cell spikes at sampling rates up to 7.2 kHz. Full array local electroretinogram currents could also be recorded at frame rates up to 100 Hz. A PIA with a full complement of 4 readout circuits would span 1cm and could acquire simultaneous data from selected regions of 1024 electrodes at sampling rates up to 9.3 kHz. Published by Elsevier B.V.

Materials Integration and Doping of Carbon Nanotube-based Logic Circuits

NASA Astrophysics Data System (ADS)

Geier, Michael

Over the last 20 years, extensive research into the structure and properties of single- walled carbon nanotube (SWCNT) has elucidated many of the exceptional qualities possessed by SWCNTs, including record-setting tensile strength, excellent chemical stability, distinctive optoelectronic features, and outstanding electronic transport characteristics. In order to exploit these remarkable qualities, many application-specific hurdles must be overcome before the material can be implemented in commercial products. For electronic applications, recent advances in sorting SWCNTs by electronic type have enabled significant progress towards SWCNT-based integrated circuits. Despite these advances, demonstrations of SWCNT-based devices with suitable characteristics for large-scale integrated circuits have been limited. The processing methodologies, materials integration, and mechanistic understanding of electronic properties developed in this dissertation have enabled unprecedented scales of SWCNT-based transistor fabrication and integrated circuit demonstrations. Innovative materials selection and processing methods are at the core of this work and these advances have led to transistors with the necessary transport properties required for modern circuit integration. First, extensive collaborations with other research groups allowed for the exploration of SWCNT thin-film transistors (TFTs) using a wide variety of materials and processing methods such as new dielectric materials, hybrid semiconductor materials systems, and solution-based printing of SWCNT TFTs. These materials were integrated into circuit demonstrations such as NOR and NAND logic gates, voltage-controlled ring oscillators, and D-flip-flops using both rigid and flexible substrates. This dissertation explores strategies for implementing complementary SWCNT-based circuits, which were developed by using local metal gate structures that achieve enhancement-mode p-type and n-type SWCNT TFTs with widely separated and symmetric threshold voltages. Additionally, a novel n-type doping procedure for SWCNT TFTs was also developed utilizing a solution-processed organometallic small molecule to demonstrate the first network top-gated n-type SWCNT TFTs. Lastly, new doping and encapsulation layers were incorporated to stabilize both p-type and n-type SWCNT TFT electronic properties, which enabled the fabrication of large-scale memory circuits. Employing these materials and processing advances has addressed many application specific barriers to commercialization. For instance, the first thin-film SWCNT complementary metal-oxide-semi-conductor (CMOS) logic devices are demonstrated with sub-nanowatt static power consumption and full rail-to-rail voltage transfer characteristics. With the introduction of a new n-type Rh-based molecular dopant, the first SWCNT TFTs are fabricated in top-gate geometries over large areas with high yield. Then by utilizing robust encapsulation methods, stable and uniform electronic performance of both p-type and n-type SWCNT TFTs has been achieved. Based on these complementary SWCNT TFTs, it is possible to simulate, design, and fabricate arrays of low-power static random access memory (SRAM) circuits, achieving large-scale integration for the first time based on solution-processed semiconductors. Together, this work provides a direct pathway for solution processable, large scale, power-efficient advanced integrated logic circuits and systems.

CMOS array design automation techniques. [metal oxide semiconductors

NASA Technical Reports Server (NTRS)

Ramondetta, P.; Feller, A.; Noto, R.; Lombardi, T.

1975-01-01

A low cost, quick turnaround technique for generating custom metal oxide semiconductor arrays using the standard cell approach was developed, implemented, tested and validated. Basic cell design topology and guidelines are defined based on an extensive analysis that includes circuit, layout, process, array topology and required performance considerations particularly high circuit speed.

Compact and high-sensitivity 100-Gb/s (4 × 25 Gb/s) APD-ROSA with a LAN-WDM PLC demultiplexer.

PubMed

Yoshimatsu, Toshihide; Nada, Masahiro; Oguma, Manabu; Yokoyama, Haruki; Ohno, Tetsuichiro; Doi, Yoshiyuki; Ogawa, Ikuo; Takahashi, Hiroshi; Yoshida, Eiji

2012-12-10

We demonstrate an integrated 100 GbE receiver optical sub-assembly (ROSA) that incorporates a monolithic four-channel avalanche photodiode (APD) array and a planer lightwave circuit (PLC) based LAN-WDM demultiplexer. A record minimum receiver sensitivity of -20 dBm and 50-km error-free SMF transmission without an optical amplifier have been achieved.

Artificial Muscle (AM) Cilia Array for Underwater Systems

DTIC Science & Technology

2016-12-15

structures, including cilia-like structures. Specifically, a custom 3D printer was created that utilizes custom-made Nafion filament for 30 printing of custom... printing ) of IPMC material to create custom-shaped AM structures, including cilia-like structures. Various custom-shaped AM structures were fabricated via...integrating square cross-section IPMC actuators with a printed circuit board power delivery system. IV. Concise Accomplishments Performance

Microwave/millimeter wave technology

NASA Astrophysics Data System (ADS)

Abita, Joseph L.

1988-09-01

The microwave/millimeter-wave monolithic integrated-circuit (MIMIC) technology and systems are discussed along with the application of MIMICs in electronic warfare. The components of a MIMIC are described, with particular attention given to the active-array antenna transmit/receive module, which is at the focus of the MIMIC, and to the features of a typical MIMIC chip. The typical performance characteristics of MIMIC components are presented in tabular form.

FPGA Boot Loader and Scrubber

NASA Technical Reports Server (NTRS)

Wade, Randall S.; Jones, Bailey

2009-01-01

A computer program loads configuration code into a Xilinx field-programmable gate array (FPGA), reads back and verifies that code, reloads the code if an error is detected, and monitors the performance of the FPGA for errors in the presence of radiation. The program consists mainly of a set of VHDL files (wherein "VHDL" signifies "VHSIC Hardware Description Language" and "VHSIC" signifies "very-high-speed integrated circuit").

Performance of the QWIP Focal Plane Arrays for NASA's Landsat Data Continuity Mission

NASA Technical Reports Server (NTRS)

Jhabvala, M.; Choi, K.; Waczynski, A.; La, A.; Sundaram, M.; Costard, E.; Jhabvala, C.; Kan, E.; Kahle, D.; Foltz, R.;

Frontend Receiver Electronics for High Frequency Monolithic CMUT-on-CMOS Imaging Arrays

PubMed Central

Gurun, Gokce; Hasler, Paul; Degertekin, F. Levent

2012-01-01

This paper describes the design of CMOS receiver electronics for monolithic integration with capacitive micromachined ultrasonic transducer (CMUT) arrays for high-frequency intravascular ultrasound imaging. A custom 8-inch wafer is fabricated in a 0.35 μm two-poly, four-metal CMOS process and then CMUT arrays are built on top of the application specific integrated circuits (ASICs) on the wafer. We discuss advantages of the single-chip CMUT-on-CMOS approach in terms of receive sensitivity and SNR. Low-noise and high-gain design of a transimpedance amplifier (TIA) optimized for a forward-looking volumetric-imaging CMUT array element is discussed as a challenging design example. Amplifier gain, bandwidth, dynamic range and power consumption trade-offs are discussed in detail. With minimized parasitics provided by the CMUT-on-CMOS approach, the optimized TIA design achieves a 90 fA/√Hz input referred current noise, which is less than the thermal-mechanical noise of the CMUT element. We show successful system operation with a pulse-echo measurement. Transducer noise-dominated detection in immersion is also demonstrated through output noise spectrum measurement of the integrated system at different CMUT bias voltages. A noise figure of 1.8 dB is obtained in the designed CMUT bandwidth of 10 MHz to 20 MHz. PMID:21859585

Front-end receiver electronics for high-frequency monolithic CMUT-on-CMOS imaging arrays.

PubMed

Gurun, Gokce; Hasler, Paul; Degertekin, F

2011-08-01

This paper describes the design of CMOS receiver electronics for monolithic integration with capacitive micromachined ultrasonic transducer (CMUT) arrays for highfrequency intravascular ultrasound imaging. A custom 8-inch (20-cm) wafer is fabricated in a 0.35-μm two-poly, four-metal CMOS process and then CMUT arrays are built on top of the application specific integrated circuits (ASICs) on the wafer. We discuss advantages of the single-chip CMUT-on-CMOS approach in terms of receive sensitivity and SNR. Low-noise and high-gain design of a transimpedance amplifier (TIA) optimized for a forward-looking volumetric-imaging CMUT array element is discussed as a challenging design example. Amplifier gain, bandwidth, dynamic range, and power consumption trade-offs are discussed in detail. With minimized parasitics provided by the CMUT-on-CMOS approach, the optimized TIA design achieves a 90 fA/√Hz input-referred current noise, which is less than the thermal-mechanical noise of the CMUT element. We show successful system operation with a pulseecho measurement. Transducer-noise-dominated detection in immersion is also demonstrated through output noise spectrum measurement of the integrated system at different CMUT bias voltages. A noise figure of 1.8 dB is obtained in the designed CMUT bandwidth of 10 to 20 MHz.

Biasing of Capacitive Micromachined Ultrasonic Transducers.

PubMed

Caliano, Giosue; Matrone, Giulia; Savoia, Alessandro Stuart

2017-02-01

Capacitive micromachined ultrasonic transducers (CMUTs) represent an effective alternative to piezoelectric transducers for medical ultrasound imaging applications. They are microelectromechanical devices fabricated using silicon micromachining techniques, developed in the last two decades in many laboratories. The interest for this novel transducer technology relies on its full compatibility with standard integrated circuit technology that makes it possible to integrate on the same chip the transducers and the electronics, thus enabling the realization of extremely low-cost and high-performance devices, including both 1-D or 2-D arrays. Being capacitive transducers, CMUTs require a high bias voltage to be properly operated in pulse-echo imaging applications. The typical bias supply residual ripple of high-quality high-voltage (HV) generators is in the millivolt range, which is comparable with the amplitude of the received echo signals, and it is particularly difficult to minimize. The aim of this paper is to analyze the classical CMUT biasing circuits, highlighting the features of each one, and to propose two novel HV generator architectures optimized for CMUT biasing applications. The first circuit proposed is an ultralow-residual ripple (<5 [Formula: see text]) HV generator that uses an extremely stable sinusoidal power oscillator topology. The second circuit employs a commercially available integrated step-up converter characterized by a particularly efficient switching topology. The circuit is used to bias the CMUT by charging a buffer capacitor synchronously with the pulsing sequence, thus reducing the impact of the switching noise on the received echo signals. The small area of the circuit (about 1.5 cm 2 ) makes it possible to generate the bias voltage inside the probe, very close to the CMUT, making the proposed solution attractive for portable applications. Measurements and experiments are shown to demonstrate the effectiveness of the new approaches presented.

Photosensitive biosensor array system using optical addressing without an addressing circuit on array biochips

NASA Astrophysics Data System (ADS)

Ahn, Chang-Geun; Ah, Chil Seong; Kim, Tae-Youb; Park, Chan Woo; Yang, Jong-Heon; Kim, Ansoon; Sung, Gun Yong

2010-09-01

This paper introduces a photosensitive biosensor array system with a simple photodiode array that detects photocurrent changes caused by reactions between probe and target molecules. Using optical addressing, the addressing circuit on the array chip is removed for low-cost application, and real cell addressing is achieved using an externally located computer-controllable light-emitting diode array module. The fabricated biosensor array chip shows a good dynamic range of 1-100 ng/mL under prostate-specific antigen detection, with an on-chip resolution of roughly 1 ng/mL.

Gallium arsenide processing for gate array logic

NASA Technical Reports Server (NTRS)

Cole, Eric D.

1989-01-01

The development of a reliable and reproducible GaAs process was initiated for applications in gate array logic. Gallium Arsenide is an extremely important material for high speed electronic applications in both digital and analog circuits since its electron mobility is 3 to 5 times that of silicon, this allows for faster switching times for devices fabricated with it. Unfortunately GaAs is an extremely difficult material to process with respect to silicon and since it includes the arsenic component GaAs can be quite dangerous (toxic) especially during some heating steps. The first stage of the research was directed at developing a simple process to produce GaAs MESFETs. The MESFET (MEtal Semiconductor Field Effect Transistor) is the most useful, practical and simple active device which can be fabricated in GaAs. It utilizes an ohmic source and drain contact separated by a Schottky gate. The gate width is typically a few microns. Several process steps were required to produce a good working device including ion implantation, photolithography, thermal annealing, and metal deposition. A process was designed to reduce the total number of steps to a minimum so as to reduce possible errors. The first run produced no good devices. The problem occurred during an aluminum etch step while defining the gate contacts. It was found that the chemical etchant attacked the GaAs causing trenching and subsequent severing of the active gate region from the rest of the device. Thus all devices appeared as open circuits. This problem is being corrected and since it was the last step in the process correction should be successful. The second planned stage involves the circuit assembly of the discrete MESFETs into logic gates for test and analysis. Finally the third stage is to incorporate the designed process with the tested circuit in a layout that would produce the gate array as a GaAs integrated circuit.

Electronic readout system for the Belle II imaging Time-Of-Propagation detector

NASA Astrophysics Data System (ADS)

Kotchetkov, Dmitri

2017-07-01

The imaging Time-Of-Propagation (iTOP) detector, constructed for the Belle II experiment at the SuperKEKB e+e- collider, is an 8192-channel high precision Cherenkov particle identification detector with timing resolution below 50 ps. To acquire data from the iTOP, a novel front-end electronic readout system was designed, built, and integrated. Switched-capacitor array application-specific integrated circuits are used to sample analog signals. Triggering, digitization, readout, and data transfer are controlled by Xilinx Zynq-7000 system on a chip devices.

A novel readout integrated circuit for ferroelectric FPA detector

NASA Astrophysics Data System (ADS)

Bai, Piji; Li, Lihua; Ji, Yulong; Zhang, Jia; Li, Min; Liang, Yan; Hu, Yanbo; Li, Songying

2017-11-01

Uncooled infrared detectors haves some advantages such as low cost light weight low power consumption, and superior reliability, compared with cryogenically cooled ones Ferroelectric uncooled focal plane array(FPA) are being developed for its AC response and its high reliability As a key part of the ferroelectric assembly the ROIC determines the performance of the assembly. A top-down design model for uncooled ferroelectric readout integrated circuit(ROIC) has been developed. Based on the optical thermal and electrical properties of the ferroelectric detector the RTIA readout integrated circuit is designed. The noise bandwidth of RTIA readout circuit has been developed and analyzed. A novel high gain amplifier, a high pass filter and a low pass filter circuits are designed on the ROIC. In order to improve the ferroelectric FPA package performance and decrease of package cost a temperature sensor is designed on the ROIC chip At last the novel RTIA ROIC is implemented on 0.6μm 2P3M CMOS silicon techniques. According to the experimental chip test results the temporal root mean square(RMS)noise voltage is about 1.4mV the sensitivity of the on chip temperature sensor is 0.6 mV/K from -40°C to 60°C the linearity performance of the ROIC chip is better than 99% Based on the 320×240 RTIA ROIC, a 320×240 infrared ferroelectric FPA is fabricated and tested. Test results shows that the 320×240 RTIA ROIC meets the demand of infrared ferroelectric FPA.

Performance evaluation of an architecture for the characterisation of photo-devices: design, fabrication and test on a CMOS technology

NASA Astrophysics Data System (ADS)

Castillo-Cabrera, G.; García-Lamont, J.; Reyes-Barranca, M. A.; Moreno-Cadenas, J. A.; Escobosa-Echavarría, A.

2011-03-01

In this report, the performance of a particular pixel's architecture is evaluated. It consists mainly of an optical sensor coupled to an amplifier. The circuit contains photoreceptors such as phototransistors and photodiodes. The circuit integrates two main blocks: (a) the pixel architecture, containing four p-channel transistors and a photoreceptor, and (b) a current source for biasing the signal conditioning amplifier. The generated photocurrent is integrated through the gate capacitance of the input p-channel MOS transistor, then converted to voltage and amplified. Both input transistor and current source are implemented as a voltage amplifier having variable gain (between 10dB and 32dB). Considering characterisation purposes, this last fact is relevant since it gives a degree of freedom to the measurement of different kinds of photo-devices and is not limited to either a single operating point of the circuit or one kind and size of photo-sensor. The gain of the amplifier can be adjusted with an external DC power supply that also sets the DC quiescent point of the circuit. Design of the row-select transistor's aspect ratio used in the matrix array is critical for the pixel's amplifier performance. Based on circuit design data such as capacitance magnitude, time and voltage integration, and amplifier gain, characterisation of all the architecture can be readily carried out and evaluated. For the specific technology used in this work, the spectral response of photo-sensors reveals performance differences between phototransistors and photodiodes. Good approximation between simulation and measurement was obtained.

Resource and Performance Evaluations of Fixed Point QRD-RLS Systolic Array through FPGA Implementation

NASA Astrophysics Data System (ADS)

Yokoyama, Yoshiaki; Kim, Minseok; Arai, Hiroyuki

At present, when using space-time processing techniques with multiple antennas for mobile radio communication, real-time weight adaptation is necessary. Due to the progress of integrated circuit technology, dedicated processor implementation with ASIC or FPGA can be employed to implement various wireless applications. This paper presents a resource and performance evaluation of the QRD-RLS systolic array processor based on fixed-point CORDIC algorithm with FPGA. In this paper, to save hardware resources, we propose the shared architecture of a complex CORDIC processor. The required precision of internal calculation, the circuit area for the number of antenna elements and wordlength, and the processing speed will be evaluated. The resource estimation provides a possible processor configuration with a current FPGA on the market. Computer simulations assuming a fading channel will show a fast convergence property with a finite number of training symbols. The proposed architecture has also been implemented and its operation was verified by beamforming evaluation through a radio propagation experiment.

A pipelined architecture for real time correction of non-uniformity in infrared focal plane arrays imaging system using multiprocessors

NASA Astrophysics Data System (ADS)

Zou, Liang; Fu, Zhuang; Zhao, YanZheng; Yang, JunYan

2010-07-01

This paper proposes a kind of pipelined electric circuit architecture implemented in FPGA, a very large scale integrated circuit (VLSI), which efficiently deals with the real time non-uniformity correction (NUC) algorithm for infrared focal plane arrays (IRFPA). Dual Nios II soft-core processors and a DSP with a 64+ core together constitute this image system. Each processor undertakes own systematic task, coordinating its work with each other's. The system on programmable chip (SOPC) in FPGA works steadily under the global clock frequency of 96Mhz. Adequate time allowance makes FPGA perform NUC image pre-processing algorithm with ease, which has offered favorable guarantee for the work of post image processing in DSP. And at the meantime, this paper presents a hardware (HW) and software (SW) co-design in FPGA. Thus, this systematic architecture yields an image processing system with multiprocessor, and a smart solution to the satisfaction with the performance of the system.

Large-area, flexible imaging arrays constructed by light-charge organic memories

PubMed Central

Zhang, Lei; Wu, Ti; Guo, Yunlong; Zhao, Yan; Sun, Xiangnan; Wen, Yugeng; Yu, Gui; Liu, Yunqi

2013-01-01

Existing organic imaging circuits, which offer attractive benefits of light weight, low cost and flexibility, are exclusively based on phototransistor or photodiode arrays. One shortcoming of these photo-sensors is that the light signal should keep invariant throughout the whole pixel-addressing and reading process. As a feasible solution, we synthesized a new charge storage molecule and embedded it into a device, which we call light-charge organic memory (LCOM). In LCOM, the functionalities of photo-sensor and non-volatile memory are integrated. Thanks to the deliberate engineering of electronic structure and self-organization process at the interface, 92% of the stored charges, which are linearly controlled by the quantity of light, retain after 20000 s. The stored charges can also be non-destructively read and erased by a simple voltage program. These results pave the way to large-area, flexible imaging circuits and demonstrate a bright future of small molecular materials in non-volatile memory. PMID:23326636

Poly-4-vinylphenol (PVP) and Poly(melamine-co-formaldehyde) (PMF)-Based Atomic Switching Device and Its Application to Logic Gate Circuits with Low Operating Voltage.

PubMed

Kang, Dong-Ho; Choi, Woo-Young; Woo, Hyunsuk; Jang, Sungkyu; Park, Hyung-Youl; Shim, Jaewoo; Choi, Jae-Woong; Kim, Sungho; Jeon, Sanghun; Lee, Sungjoo; Park, Jin-Hong

2017-08-16

In this study, we demonstrate a high-performance solid polymer electrolyte (SPE) atomic switching device with low SET/RESET voltages (0.25 and -0.5 V, respectively), high on/off-current ratio (10 5 ), excellent cyclic endurance (>10 3 ), and long retention time (>10 4 s), where poly-4-vinylphenol (PVP)/poly(melamine-co-formaldehyde) (PMF) is used as an SPE layer. To accomplish these excellent device performance parameters, we reduce the off-current level of the PVP/PMF atomic switching device by improving the electrical insulating property of the PVP/PMF electrolyte through adjustment of the number of cross-linked chains. We then apply a titanium buffer layer to the PVP/PMF switching device for further improvement of bipolar switching behavior and device stability. In addition, we first implement SPE atomic switch-based logic AND and OR circuits with low operating voltages below 2 V by integrating 5 × 5 arrays of PVP/PMF switching devices on the flexible substrate. In particular, this low operating voltage of our logic circuits was much lower than that (>5 V) of the circuits configured by polymer resistive random access memory. This research successfully presents the feasibility of PVP/PMF atomic switches for flexible integrated circuits for next-generation electronic applications.

Evaluation and optimization of mass transport of redox species in silicon microwire-array photoelectrodes

PubMed Central

Xiang, Chengxiang; Meng, Andrew C.; Lewis, Nathan S.

2012-01-01

Physical integration of a Ag electrical contact internally into a metal/substrate/microstructured Si wire array/oxide/Ag/electrolyte photoelectrochemical solar cell has produced structures that display relatively low ohmic resistance losses, as well as highly efficient mass transport of redox species in the absence of forced convection. Even with front-side illumination, such wire-array based photoelectrochemical solar cells do not require a transparent conducting oxide top contact. In contact with a test electrolyte that contained 50 mM/5.0 mM of the cobaltocenium+/0 redox species in CH3CN–1.0 M LiClO4, when the counterelectrode was placed in the solution and separated from the photoelectrode, mass transport restrictions of redox species in the internal volume of the Si wire array photoelectrode produced low fill factors and limited the obtainable current densities to 17.6 mA cm-2 even under high illumination. In contrast, when the physically integrated internal Ag film served as the counter electrode, the redox couple species were regenerated inside the internal volume of the photoelectrode, especially in regions where depletion of the redox species due to mass transport limitations would have otherwise occurred. This behavior allowed the integrated assembly to operate as a two-terminal, stand-alone, photoelectrochemical solar cell. The current density vs. voltage behavior of the integrated photoelectrochemical solar cell produced short-circuit current densities in excess of 80 mA cm-2 at high light intensities, and resulted in relatively low losses due to concentration overpotentials at 1 Sun illumination. The integrated wire array-based device architecture also provides design guidance for tandem photoelectrochemical cells for solar-driven water splitting. PMID:22904185

Integrated Millimeter-Wave Frequency Multiplers

NASA Astrophysics Data System (ADS)

Schoenthal, Gerhard S.; Deaver, B. S.; Crowe, T. W.; Bishop, W. L.; Saini, K.; Bradley, R. F.

2001-11-01

Many of the molecules of interest to radio astronomers and atmospheric chemists resonate at frequencies in the millimeter and submillimeter wavelength bands. To measure the spectra of these molecules scientists rely on heterodyne receivers that convert the high frequency signal to the GHz band where it is readily amplified and analyzed. One of the challenges of developing suitable receiver systems is the development of compact, reliable and affordable sources of local oscillator power at frequencies in excess of 100 GHz. One useful solution is to use GaAs Schottky diodes, in their varactor mode, to generate high frequency harmonics of lower frequency sources such as Gunn oscillators. As a part of a multi-national radio astronomy project, the Atacama Millimeter Large Array (ALMA), we have designed and fabricated a broadband frequency tripler with an output centered at 240 GHz. It is integrated on a quartz substrate to greatly reduce the parasitic capacitance and thereby improve electrical performance. The integrated circuit was designed to require no oxides or ohmic contacts, thereby easing fabrication. This talk will discuss the novel millimeter-wave integrated circuit fabrication process and the initial results.

Roughness measurements on coupling structures for optical interconnections integrated on a printed circuit board

NASA Astrophysics Data System (ADS)

Hendrickx, Nina; Van Erps, Jürgen; Suyal, Himanshu; Taghizadeh, Mohammad; Thienpont, Hugo; Van Daele, Peter

2006-04-01

In this paper, laser ablation (at UGent), deep proton writing (at VUB) and laser direct writing (at HWU) are presented as versatile technologies that can be used for the fabrication of coupling structures for optical interconnections integrated on a printed circuit board (PCB). The optical layer, a highly cross-linked acrylate based polymer, is applied on an FR4 substrate. Both laser ablation and laser direct writing are used for the definition of arrays of multimode optical waveguides, which guide the light in the plane of the optical layer. In order to couple light vertically in/out of the plane of the optical waveguides, coupling structures have to be integrated into the optical layer. Out-of-plane turning mirrors, that deflect the light beam over 90°, are used for this purpose. The surface roughness and angle of three mirror configurations are evaluated: a laser ablated one that is integrated into the optical waveguide, a laser direct written one that is also directly written onto the waveguide and a DPW insert that is plugged into a cavity into the waveguiding layer.

Forward-Looking Intracardiac Ultrasound Imaging Using a 1-D CMUT Array Integrated With Custom Front-End Electronics

PubMed Central

Nikoozadeh, Amin; Wygant, Ira O.; Lin, Der-Song; Oralkan, Ömer; Ergun, A. Sanlı; Stephens, Douglas N.; Thomenius, Kai E.; Dentinger, Aaron M.; Wildes, Douglas; Akopyan, Gina; Shivkumar, Kalyanam; Mahajan, Aman; Sahn, David J.; Khuri-Yakub, Butrus T.

2009-01-01

Minimally invasive catheter-based electrophysiological (EP) interventions are becoming a standard procedure in diagnosis and treatment of cardiac arrhythmias. As a result of technological advances that enable small feature sizes and a high level of integration, nonfluoroscopic intracardiac echocardiography (ICE) imaging catheters are attracting increasing attention. ICE catheters improve EP procedural guidance while reducing the undesirable use of fluoroscopy, which is currently the common catheter guidance method. Phased-array ICE catheters have been in use for several years now, although only for side-looking imaging. We are developing a forward-looking ICE catheter for improved visualization. In this effort, we fabricate a 24-element, fine-pitch 1-D array of capacitive micromachined ultrasonic transducers (CMUT), with a total footprint of 1.73 mm × 1.27 mm. We also design a custom integrated circuit (IC) composed of 24 identical blocks of transmit/receive circuitry, measuring 2.1 mm × 2.1 mm. The transmit circuitry is capable of delivering 25-V unipolar pulses, and the receive circuitry includes a transimpedance preamplifier followed by an output buffer. The CMUT array and the custom IC are designed to be mounted at the tip of a 10-Fr catheter for high-frame-rate forward-looking intracardiac imaging. Through-wafer vias incorporated in the CMUT array provide access to individual array elements from the back side of the array. We successfully flip-chip bond a CMUT array to the custom IC with 100% yield. We coat the device with a layer of polydimethylsiloxane (PDMS) to electrically isolate the device for imaging in water and tissue. The pulse-echo in water from a total plane reflector has a center frequency of 9.2 MHz with a 96% fractional bandwidth. Finally, we demonstrate the imaging capability of the integrated device on commercial phantoms and on a beating ex vivo rabbit heart (Langendorff model) using a commercial ultrasound imaging system. PMID:19126489

A 400 KHz line rate 2048-pixel stitched SWIR linear array

NASA Astrophysics Data System (ADS)

Anchlia, Ankur; Vinella, Rosa M.; Gielen, Daphne; Wouters, Kristof; Vervenne, Vincent; Hooylaerts, Peter; Deroo, Pieter; Ruythooren, Wouter; De Gaspari, Danny; Das, Jo; Merken, Patrick

2016-05-01

Xenics has developed a family of stitched SWIR long linear arrays that operate up to 400 KHz of line rate. These arrays serve medical and industrial applications that require high line rates as well as space applications that require long linear arrays. The arrays are based on a modular ROIC design concept: modules of 512 pixels are stitched during fabrication to achieve 512, 1024 and 2048 pixel arrays. Each 512-pixel module has its own on-chip digital sequencer, analog readout chain and 4 output buffers. This modular concept enables a long array to run at a high line rates irrespective of the array length, which limits the line rate in a traditional linear array. The ROIC is flip-chipped with InGaAs detector arrays. The FPA has a pixel pitch of 12.5μm and has two pixel flavors: square (12.5μm) and rectangular (250μm). The frontend circuit is based on Capacitive Trans-impedance Amplifier (CTIA) to attain stable detector bias, and good linearity and signal integrity, especially at high speeds. The CTIA has an input auto-zero mechanism that allows to have low detector bias (<20mV). An on-chip Correlated Double Sample (CDS) facilitates removal of CTIA KTC and 1/f noise, and other offsets, achieving low noise performance. There are five gain modes in the FPA giving the full well range from 85Ke- to 40Me-. The measured input referred noise is 35e-rms in the highest gain mode. The FPA operates in Integrate While Read mode and, at a master clock rate of 60MHz and a minimum integration time of 1.4μs, achieves the highest line rate of 400 KHz. In this paper, design details and measurements results are presented in order to demonstrate the array performance.

Rectangular Array Of Digital Processors For Planning Paths

NASA Technical Reports Server (NTRS)

Kemeny, Sabrina E.; Fossum, Eric R.; Nixon, Robert H.

1993-01-01

Prototype 24 x 25 rectangular array of asynchronous parallel digital processors rapidly finds best path across two-dimensional field, which could be patch of terrain traversed by robotic or military vehicle. Implemented as single-chip very-large-scale integrated circuit. Excepting processors on edges, each processor communicates with four nearest neighbors along paths representing travel to north, south, east, and west. Each processor contains delay generator in form of 8-bit ripple counter, preset to 1 of 256 possible values. Operation begins with choice of processor representing starting point. Transmits signals to nearest neighbor processors, which retransmits to other neighboring processors, and process repeats until signals propagated across entire field.

Multi-element germanium detectors for synchrotron applications

NASA Astrophysics Data System (ADS)

Rumaiz, A. K.; Kuczewski, A. J.; Mead, J.; Vernon, E.; Pinelli, D.; Dooryhee, E.; Ghose, S.; Caswell, T.; Siddons, D. P.; Miceli, A.; Baldwin, J.; Almer, J.; Okasinski, J.; Quaranta, O.; Woods, R.; Krings, T.; Stock, S.

2018-04-01

We have developed a series of monolithic multi-element germanium detectors, based on sensor arrays produced by the Forschungzentrum Julich, and on Application-specific integrated circuits (ASICs) developed at Brookhaven. Devices have been made with element counts ranging from 64 to 384. These detectors are being used at NSLS-II and APS for a range of diffraction experiments, both monochromatic and energy-dispersive. Compact and powerful readout systems have been developed, based on the new generation of FPGA system-on-chip devices, which provide closely coupled multi-core processors embedded in large gate arrays. We will discuss the technical details of the systems, and present some of the results from them.

Displacement sensors using soft magnetostrictive alloys

NASA Astrophysics Data System (ADS)

Hristoforou, E.; Reilly, R. E.

1994-09-01

We report results on the response of a family of displacement sensors, which are based on the magentostrictive delay line (MDL) technique, using current conductors orthogonal to the MDL. Such sensing technique is based on the change of the magnetic circuit at the acoustic stress point of origin due to the displacement of a soft magnetic material above it. Integrated arrays of sensors can be obtained due to the acoustic delay line technique and they can be used as tactile arrays, digitizers or devices for medical applications (gait analysis etc.), while absence of hysteresis and low cost of manufacturing make them competent in this sector of sensor market.

Advanced InSb monolithic Charge Coupled Infrared Imaging Devices (CCIRID)

NASA Technical Reports Server (NTRS)

Koch, T. L.; Thom, R. D.; Parrish, W. D.

1981-01-01

The continued development of monolithic InSb charge coupled infrared imaging devices (CCIRIDs) is discussed. The processing sequence and structural design of 20-element linear arrays are discussed. Also, results obtained from radiometric testing of the 20-element arrays using a clamped sample-and-hold output circuit are reported. The design and layout of a next-generation CCIRID chip are discussed. The major devices on this chip are a 20 by 16 time-delay-and-integration (TDI) area array and a 100-element linear imaging array. The development of a process for incorporating an ion implanted S(+) planar channel stop into the CCIRID structure and the development of a thin film transparent photogate are also addressed. The transparent photogates will increase quantum efficiency to greater than 70% across the 2.5 to 5.4 micrometer spectral region in future front-side illuminated CCIRIDs.

Data acquisition system

DOEpatents

Shapiro, Stephen L.; Mani, Sudhindra; Atlas, Eugene L.; Cords, Dieter H. W.; Holbrook, Britt

1997-01-01

A data acquisition circuit for a particle detection system that allows for time tagging of particles detected by the system. The particle detection system screens out background noise and discriminate between hits from scattered and unscattered particles. The detection system can also be adapted to detect a wide variety of particle types. The detection system utilizes a particle detection pixel array, each pixel containing a back-biased PIN diode, and a data acquisition pixel array. Each pixel in the particle detection pixel array is in electrical contact with a pixel in the data acquisition pixel array. In response to a particle hit, the affected PIN diodes generate a current, which is detected by the corresponding data acquisition pixels. This current is integrated to produce a voltage across a capacitor, the voltage being related to the amount of energy deposited in the pixel by the particle. The current is also used to trigger a read of the pixel hit by the particle.

Techniques for control of long-term reliability of complex integrated circuits. I - Reliability assurance by test vehicle qualification.

NASA Technical Reports Server (NTRS)

Van Vonno, N. W.

1972-01-01

Development of an alternate approach to the conventional methods of reliability assurance for large-scale integrated circuits. The product treated is a large-scale T squared L array designed for space applications. The concept used is that of qualification of product by evaluation of the basic processing used in fabricating the product, providing an insight into its potential reliability. Test vehicles are described which enable evaluation of device characteristics, surface condition, and various parameters of the two-level metallization system used. Evaluation of these test vehicles is performed on a lot qualification basis, with the lot consisting of one wafer. Assembled test vehicles are evaluated by high temperature stress at 300 C for short time durations. Stressing at these temperatures provides a rapid method of evaluation and permits a go/no go decision to be made on the wafer lot in a timely fashion.

Unfolding an electronic integrate-and-fire circuit.

PubMed

Carrillo, Humberto; Hoppensteadt, Frank

2010-01-01

Many physical and biological phenomena involve accumulation and discharge processes that can occur on significantly different time scales. Models of these processes have contributed to understand excitability self-sustained oscillations and synchronization in arrays of oscillators. Integrate-and-fire (I+F) models are popular minimal fill-and-flush mathematical models. They are used in neuroscience to study spiking and phase locking in single neuron membranes, large scale neural networks, and in a variety of applications in physics and electrical engineering. We show here how the classical first-order I+F model fits into the theory of nonlinear oscillators of van der Pol type by demonstrating that a particular second-order oscillator having small parameters converges in a singular perturbation limit to the I+F model. In this sense, our study provides a novel unfolding of such models and it identifies a constructible electronic circuit that is closely related to I+F.

Real-time fast physical random number generator with a photonic integrated circuit.

PubMed

Ugajin, Kazusa; Terashima, Yuta; Iwakawa, Kento; Uchida, Atsushi; Harayama, Takahisa; Yoshimura, Kazuyuki; Inubushi, Masanobu

2017-03-20

Random number generators are essential for applications in information security and numerical simulations. Most optical-chaos-based random number generators produce random bit sequences by offline post-processing with large optical components. We demonstrate a real-time hardware implementation of a fast physical random number generator with a photonic integrated circuit and a field programmable gate array (FPGA) electronic board. We generate 1-Tbit random bit sequences and evaluate their statistical randomness using NIST Special Publication 800-22 and TestU01. All of the BigCrush tests in TestU01 are passed using 410-Gbit random bit sequences. A maximum real-time generation rate of 21.1 Gb/s is achieved for random bit sequences in binary format stored in a computer, which can be directly used for applications involving secret keys in cryptography and random seeds in large-scale numerical simulations.

Engineering integrated photonics for heralded quantum gates

NASA Astrophysics Data System (ADS)

Meany, Thomas; Biggerstaff, Devon N.; Broome, Matthew A.; Fedrizzi, Alessandro; Delanty, Michael; Steel, M. J.; Gilchrist, Alexei; Marshall, Graham D.; White, Andrew G.; Withford, Michael J.

2016-06-01

Scaling up linear-optics quantum computing will require multi-photon gates which are compact, phase-stable, exhibit excellent quantum interference, and have success heralded by the detection of ancillary photons. We investigate the design, fabrication and characterisation of the optimal known gate scheme which meets these requirements: the Knill controlled-Z gate, implemented in integrated laser-written waveguide arrays. We show device performance to be less sensitive to phase variations in the circuit than to small deviations in the coupler reflectivity, which are expected given the tolerance values of the fabrication method. The mode fidelity is also shown to be less sensitive to reflectivity and phase errors than the process fidelity. Our best device achieves a fidelity of 0.931 ± 0.001 with the ideal 4 × 4 unitary circuit and a process fidelity of 0.680 ± 0.005 with the ideal computational-basis process.

Engineering integrated photonics for heralded quantum gates

PubMed Central

Meany, Thomas; Biggerstaff, Devon N.; Broome, Matthew A.; Fedrizzi, Alessandro; Delanty, Michael; Steel, M. J.; Gilchrist, Alexei; Marshall, Graham D.; White, Andrew G.; Withford, Michael J.

2016-01-01

Scaling up linear-optics quantum computing will require multi-photon gates which are compact, phase-stable, exhibit excellent quantum interference, and have success heralded by the detection of ancillary photons. We investigate the design, fabrication and characterisation of the optimal known gate scheme which meets these requirements: the Knill controlled-Z gate, implemented in integrated laser-written waveguide arrays. We show device performance to be less sensitive to phase variations in the circuit than to small deviations in the coupler reflectivity, which are expected given the tolerance values of the fabrication method. The mode fidelity is also shown to be less sensitive to reflectivity and phase errors than the process fidelity. Our best device achieves a fidelity of 0.931 ± 0.001 with the ideal 4 × 4 unitary circuit and a process fidelity of 0.680 ± 0.005 with the ideal computational-basis process. PMID:27282928

Engineering integrated photonics for heralded quantum gates.

PubMed

Meany, Thomas; Biggerstaff, Devon N; Broome, Matthew A; Fedrizzi, Alessandro; Delanty, Michael; Steel, M J; Gilchrist, Alexei; Marshall, Graham D; White, Andrew G; Withford, Michael J

2016-06-10

Scaling up linear-optics quantum computing will require multi-photon gates which are compact, phase-stable, exhibit excellent quantum interference, and have success heralded by the detection of ancillary photons. We investigate the design, fabrication and characterisation of the optimal known gate scheme which meets these requirements: the Knill controlled-Z gate, implemented in integrated laser-written waveguide arrays. We show device performance to be less sensitive to phase variations in the circuit than to small deviations in the coupler reflectivity, which are expected given the tolerance values of the fabrication method. The mode fidelity is also shown to be less sensitive to reflectivity and phase errors than the process fidelity. Our best device achieves a fidelity of 0.931 ± 0.001 with the ideal 4 × 4 unitary circuit and a process fidelity of 0.680 ± 0.005 with the ideal computational-basis process.

Fabrication of Circuit QED Quantum Processors, Part 2: Advanced Semiconductor Manufacturing Perspectives

NASA Astrophysics Data System (ADS)

Michalak, D. J.; Bruno, A.; Caudillo, R.; Elsherbini, A. A.; Falcon, J. A.; Nam, Y. S.; Poletto, S.; Roberts, J.; Thomas, N. K.; Yoscovits, Z. R.; Dicarlo, L.; Clarke, J. S.

Experimental quantum computing is rapidly approaching the integration of sufficient numbers of quantum bits for interesting applications, but many challenges still remain. These challenges include: realization of an extensible design for large array scale up, sufficient material process control, and discovery of integration schemes compatible with industrial 300 mm fabrication. We present recent developments in extensible circuits with vertical delivery. Toward the goal of developing a high-volume manufacturing process, we will present recent results on a new Josephson junction process that is compatible with current tooling. We will then present the improvements in NbTiN material uniformity that typical 300 mm fabrication tooling can provide. While initial results on few-qubit systems are encouraging, advanced processing control is expected to deliver the improvements in qubit uniformity, coherence time, and control required for larger systems. Research funded by Intel Corporation.

Experimental demonstration of two-dimensional hybrid waveguide-integrated plasmonic crystals on silicon-on-insulator platform

NASA Astrophysics Data System (ADS)

Ren, Guanghui; Yudistira, Didit; Nguyen, Thach G.; Khodasevych, Iryna; Schoenhardt, Steffen; Berean, Kyle J.; Hamm, Joachim M.; Hess, Ortwin; Mitchell, Arnan

2017-07-01

Nanoscale plasmonic structures can offer unique functionality due to extreme sub-wavelength optical confinement, but the realization of complex plasmonic circuits is hampered by high propagation losses. Hybrid approaches can potentially overcome this limitation, but only few practical approaches based on either single or few element arrays of nanoantennas on dielectric nanowire have been experimentally demonstrated. In this paper, we demonstrate a two dimensional hybrid photonic plasmonic crystal interfaced with a standard silicon photonic platform. Off resonance, we observe low loss propagation through our structure, while on resonance we observe strong propagation suppression and intense concentration of light into a dense lattice of nanoscale hot-spots on the surface providing clear evidence of a hybrid photonic plasmonic crystal bandgap. This fully integrated approach is compatible with established silicon-on-insulator (SOI) fabrication techniques and constitutes a significant step toward harnessing plasmonic functionality within SOI photonic circuits.

Optimal Design of MPPT Controllers for Grid Connected Photovoltaic Array System

NASA Astrophysics Data System (ADS)

Ebrahim, M. A.; AbdelHadi, H. A.; Mahmoud, H. M.; Saied, E. M.; Salama, M. M.

2016-10-01

Integrating photovoltaic (PV) plants into electric power system exhibits challenges to power system dynamic performance. These challenges stem primarily from the natural characteristics of PV plants, which differ in some respects from the conventional plants. The most significant challenge is how to extract and regulate the maximum power from the sun. This paper presents the optimal design for the most commonly used Maximum Power Point Tracking (MPPT) techniques based on Proportional Integral tuned by Particle Swarm Optimization (PI-PSO). These suggested techniques are, (1) the incremental conductance, (2) perturb and observe, (3) fractional short circuit current and (4) fractional open circuit voltage techniques. This research work provides a comprehensive comparative study with the energy availability ratio from photovoltaic panels. The simulation results proved that the proposed controllers have an impressive tracking response. The system dynamic performance improved greatly using the proposed controllers.

CMOS image sensor with contour enhancement

NASA Astrophysics Data System (ADS)

Meng, Liya; Lai, Xiaofeng; Chen, Kun; Yuan, Xianghui

2010-10-01

Imitating the signal acquisition and processing of vertebrate retina, a CMOS image sensor with bionic pre-processing circuit is designed. Integration of signal-process circuit on-chip can reduce the requirement of bandwidth and precision of the subsequent interface circuit, and simplify the design of the computer-vision system. This signal pre-processing circuit consists of adaptive photoreceptor, spatial filtering resistive network and Op-Amp calculation circuit. The adaptive photoreceptor unit with a dynamic range of approximately 100 dB has a good self-adaptability for the transient changes in light intensity instead of intensity level itself. Spatial low-pass filtering resistive network used to mimic the function of horizontal cell, is composed of the horizontal resistor (HRES) circuit and OTA (Operational Transconductance Amplifier) circuit. HRES circuit, imitating dendrite of the neuron cell, comprises of two series MOS transistors operated in weak inversion region. Appending two diode-connected n-channel transistors to a simple transconductance amplifier forms the OTA Op-Amp circuit, which provides stable bias voltage for the gate of MOS transistors in HRES circuit, while serves as an OTA voltage follower to provide input voltage for the network nodes. The Op-Amp calculation circuit with a simple two-stage Op-Amp achieves the image contour enhancing. By adjusting the bias voltage of the resistive network, the smoothing effect can be tuned to change the effect of image's contour enhancement. Simulations of cell circuit and 16×16 2D circuit array are implemented using CSMC 0.5μm DPTM CMOS process.

22 W coherent GaAlAs amplifier array with 400 emitters

NASA Technical Reports Server (NTRS)

Krebs, D.; Herrick, R.; No, K.; Harting, W.; Struemph, F.

1991-01-01

Greater than 22 W of optical power has been demonstrated from a multiple-emitter, traveling-wave semiconductor amplifier, with approximately 87 percent of the output at the frequency of the injection source. The device integrates, in AlGaAs graded-index separate-confinement heterostructure single quantum well (GRINSCH-SQW) epitaxy, 400 ridge waveguide amplifiers with a coherent optical signal distribution circuit on a 12 x 6 mm chip.

338-GHz Semiconductor Amplifier Module

NASA Technical Reports Server (NTRS)

Samoska, Lorene A.; Gaier, Todd C.; Soria, Mary M.; Fung, King Man; Rasisic, Vesna; Deal, William; Leong, Kevin; Mei, Xiao Bing; Yoshida, Wayne; Liu, Po-Hsin;

On-chip photonic memory elements employing phase-change materials.

PubMed

Rios, Carlos; Hosseini, Peiman; Wright, C David; Bhaskaran, Harish; Pernice, Wolfram H P

2014-03-05

Phase-change materials integrated into nanophotonic circuits provide a flexible way to realize tunable optical components. Relying on the enormous refractive-index contrast between the amorphous and crystalline states, such materials are promising candidates for on-chip photonic memories. Nonvolatile memory operation employing arrays of microring resonators is demonstrated as a route toward all-photonic chipscale information processing. © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Hardware Evolution of Analog Speed Controllers for a DC Motor

NASA Technical Reports Server (NTRS)

Gwaltney, David A.; Ferguson, Michael I.

2003-01-01

Evolvable hardware provides the capability to evolve analog circuits to produce amplifier and filter functions. Conventional analog controller designs employ these same functions. Analog controllers for the control of the shaft speed of a DC motor are evolved on an evolvable hardware platform utilizing a Field Programmable Transistor Array (FPTA). The performance of these evolved controllers is compared to that of a conventional proportional-integral (PI) controller.

A Vibration-Based MEMS Piezoelectric Energy Harvester and Power Conditioning Circuit

PubMed Central

Yu, Hua; Zhou, Jielin; Deng, Licheng; Wen, Zhiyu

2014-01-01

This paper presents a micro-electro-mechanical system (MEMS) piezoelectric power generator array for vibration energy harvesting. A complete design flow of the vibration-based energy harvester using the finite element method (FEM) is proposed. The modal analysis is selected to calculate the resonant frequency of the harvester, and harmonic analysis is performed to investigate the influence of the geometric parameters on the output voltage. Based on simulation results, a MEMS Pb(Zr,Ti)O3 (PZT) cantilever array with an integrated large Si proof mass is designed and fabricated to improve output voltage and power. Test results show that the fabricated generator, with five cantilever beams (with unit dimensions of about 3 × 2.4 × 0.05 mm3) and an individual integrated Si mass dimension of about 8 × 12.4 × 0.5 mm3, produces a output power of 66.75 μW, or a power density of 5.19 μW·mm−3·g−2 with an optimal resistive load of 220 kΩ from 5 m/s2 vibration acceleration at its resonant frequency of 234.5 Hz. In view of high internal impedance characteristic of the PZT generator, an efficient autonomous power conditioning circuit, with the function of impedance matching, energy storage and voltage regulation, is then presented, finding that the efficiency of the energy storage is greatly improved and up to 64.95%. The proposed self-supplied energy generator with power conditioning circuit could provide a very promising complete power supply solution for wireless sensor node loads. PMID:24556670

A vibration-based MEMS piezoelectric energy harvester and power conditioning circuit.

PubMed

Yu, Hua; Zhou, Jielin; Deng, Licheng; Wen, Zhiyu

2014-02-19

This paper presents a micro-electro-mechanical system (MEMS) piezoelectric power generator array for vibration energy harvesting. A complete design flow of the vibration-based energy harvester using the finite element method (FEM) is proposed. The modal analysis is selected to calculate the resonant frequency of the harvester, and harmonic analysis is performed to investigate the influence of the geometric parameters on the output voltage. Based on simulation results, a MEMS Pb(Zr,Ti)O3 (PZT) cantilever array with an integrated large Si proof mass is designed and fabricated to improve output voltage and power. Test results show that the fabricated generator, with five cantilever beams (with unit dimensions of about 3 × 2.4 × 0.05 mm3) and an individual integrated Si mass dimension of about 8 × 12.4 × 0.5 mm3, produces a output power of 66.75 μW, or a power density of 5.19 μW∙mm-3∙g-2 with an optimal resistive load of 220 kΩ from 5 m/s2 vibration acceleration at its resonant frequency of 234.5 Hz. In view of high internal impedance characteristic of the PZT generator, an efficient autonomous power conditioning circuit, with the function of impedance matching, energy storage and voltage regulation, is then presented, finding that the efficiency of the energy storage is greatly improved and up to 64.95%. The proposed self-supplied energy generator with power conditioning circuit could provide a very promising complete power supply solution for wireless sensor node loads.

Fully integrated wearable sensor arrays for multiplexed in situ perspiration analysis.

PubMed

Gao, Wei; Emaminejad, Sam; Nyein, Hnin Yin Yin; Challa, Samyuktha; Chen, Kevin; Peck, Austin; Fahad, Hossain M; Ota, Hiroki; Shiraki, Hiroshi; Kiriya, Daisuke; Lien, Der-Hsien; Brooks, George A; Davis, Ronald W; Javey, Ali

2016-01-28

Wearable sensor technologies are essential to the realization of personalized medicine through continuously monitoring an individual's state of health. Sampling human sweat, which is rich in physiological information, could enable non-invasive monitoring. Previously reported sweat-based and other non-invasive biosensors either can only monitor a single analyte at a time or lack on-site signal processing circuitry and sensor calibration mechanisms for accurate analysis of the physiological state. Given the complexity of sweat secretion, simultaneous and multiplexed screening of target biomarkers is critical and requires full system integration to ensure the accuracy of measurements. Here we present a mechanically flexible and fully integrated (that is, no external analysis is needed) sensor array for multiplexed in situ perspiration analysis, which simultaneously and selectively measures sweat metabolites (such as glucose and lactate) and electrolytes (such as sodium and potassium ions), as well as the skin temperature (to calibrate the response of the sensors). Our work bridges the technological gap between signal transduction, conditioning (amplification and filtering), processing and wireless transmission in wearable biosensors by merging plastic-based sensors that interface with the skin with silicon integrated circuits consolidated on a flexible circuit board for complex signal processing. This application could not have been realized using either of these technologies alone owing to their respective inherent limitations. The wearable system is used to measure the detailed sweat profile of human subjects engaged in prolonged indoor and outdoor physical activities, and to make a real-time assessment of the physiological state of the subjects. This platform enables a wide range of personalized diagnostic and physiological monitoring applications.

Fully integrated wearable sensor arrays for multiplexed in situ perspiration analysis

NASA Astrophysics Data System (ADS)

Gao, Wei; Emaminejad, Sam; Nyein, Hnin Yin Yin; Challa, Samyuktha; Chen, Kevin; Peck, Austin; Fahad, Hossain M.; Ota, Hiroki; Shiraki, Hiroshi; Kiriya, Daisuke; Lien, Der-Hsien; Brooks, George A.; Davis, Ronald W.; Javey, Ali

2016-01-01

Wearable sensor technologies are essential to the realization of personalized medicine through continuously monitoring an individual’s state of health. Sampling human sweat, which is rich in physiological information, could enable non-invasive monitoring. Previously reported sweat-based and other non-invasive biosensors either can only monitor a single analyte at a time or lack on-site signal processing circuitry and sensor calibration mechanisms for accurate analysis of the physiological state. Given the complexity of sweat secretion, simultaneous and multiplexed screening of target biomarkers is critical and requires full system integration to ensure the accuracy of measurements. Here we present a mechanically flexible and fully integrated (that is, no external analysis is needed) sensor array for multiplexed in situ perspiration analysis, which simultaneously and selectively measures sweat metabolites (such as glucose and lactate) and electrolytes (such as sodium and potassium ions), as well as the skin temperature (to calibrate the response of the sensors). Our work bridges the technological gap between signal transduction, conditioning (amplification and filtering), processing and wireless transmission in wearable biosensors by merging plastic-based sensors that interface with the skin with silicon integrated circuits consolidated on a flexible circuit board for complex signal processing. This application could not have been realized using either of these technologies alone owing to their respective inherent limitations. The wearable system is used to measure the detailed sweat profile of human subjects engaged in prolonged indoor and outdoor physical activities, and to make a real-time assessment of the physiological state of the subjects. This platform enables a wide range of personalized diagnostic and physiological monitoring applications.

Circuit design for the retina-like image sensor based on space-variant lens array

NASA Astrophysics Data System (ADS)

Gao, Hongxun; Hao, Qun; Jin, Xuefeng; Cao, Jie; Liu, Yue; Song, Yong; Fan, Fan

2013-12-01

Retina-like image sensor is based on the non-uniformity of the human eyes and the log-polar coordinate theory. It has advantages of high-quality data compression and redundant information elimination. However, retina-like image sensors based on the CMOS craft have drawbacks such as high cost, low sensitivity and signal outputting efficiency and updating inconvenience. Therefore, this paper proposes a retina-like image sensor based on space-variant lens array, focusing on the circuit design to provide circuit support to the whole system. The circuit includes the following parts: (1) A photo-detector array with a lens array to convert optical signals to electrical signals; (2) a strobe circuit for time-gating of the pixels and parallel paths for high-speed transmission of the data; (3) a high-precision digital potentiometer for the I-V conversion, ratio normalization and sensitivity adjustment, a programmable gain amplifier for automatic generation control(AGC), and a A/D converter for the A/D conversion in every path; (4) the digital data is displayed on LCD and stored temporarily in DDR2 SDRAM; (5) a USB port to transfer the data to PC; (6) the whole system is controlled by FPGA. This circuit has advantages as lower cost, larger pixels, updating convenience and higher signal outputting efficiency. Experiments have proved that the grayscale output of every pixel basically matches the target and a non-uniform image of the target is ideally achieved in real time. The circuit can provide adequate technical support to retina-like image sensors based on space-variant lens array.

Bit-systolic arithmetic arrays using dynamic differential gallium arsenide circuits

NASA Technical Reports Server (NTRS)

Beagles, Grant; Winters, Kel; Eldin, A. G.

1992-01-01

A new family of gallium arsenide circuits for fine grained bit-systolic arithmetic arrays is introduced. This scheme combines features of two recent techniques of dynamic gallium arsenide FET logic and differential dynamic single-clock CMOS logic. The resulting circuits are fast and compact, with tightly constrained series FET propagation paths, low fanout, no dc power dissipation, and depletion FET implementation without level shifting diodes.

Neuropeptide Signaling Networks and Brain Circuit Plasticity.

PubMed

McClard, Cynthia K; Arenkiel, Benjamin R

2018-01-01

The brain is a remarkable network of circuits dedicated to sensory integration, perception, and response. The computational power of the brain is estimated to dwarf that of most modern supercomputers, but perhaps its most fascinating capability is to structurally refine itself in response to experience. In the language of computers, the brain is loaded with programs that encode when and how to alter its own hardware. This programmed "plasticity" is a critical mechanism by which the brain shapes behavior to adapt to changing environments. The expansive array of molecular commands that help execute this programming is beginning to emerge. Notably, several neuropeptide transmitters, previously best characterized for their roles in hypothalamic endocrine regulation, have increasingly been recognized for mediating activity-dependent refinement of local brain circuits. Here, we discuss recent discoveries that reveal how local signaling by corticotropin-releasing hormone reshapes mouse olfactory bulb circuits in response to activity and further explore how other local neuropeptide networks may function toward similar ends.

Hybrid CMOS/Molecular Integrated Circuits

NASA Astrophysics Data System (ADS)

Stan, M. R.; Rose, G. S.; Ziegler, M. M.

CMOS silicon technologies are likely to run out of steam in the next 10-15 years despite revolutionary advances in the past few decades. Molecular and other nanoscale technologies show significant promise but it is unlikely that they will completely replace CMOS, at least in the near term. This chapter explores opportunities for using CMOS and nanotechnology to enhance and complement each other in hybrid circuits. As an example of such a hybrid CMOS/nano system, a nanoscale programmable logic array (PLA) based on majority logic is described along with its supplemental CMOS circuitry. It is believed that such systems will be able to sustain the historical advances in the semiconductor industry while addressing manufacturability, yield, power, cost, and performance challenges.

Active feed array compensation for reflector antenna surface distortions. Ph.D. Thesis - Akron Univ., Ohio

NASA Technical Reports Server (NTRS)

Acosta, Roberto J.

1988-01-01

The feasibility of electromagnetic compensation for reflector antenna surface distortions is investigated. The performance characteristics of large satellite communication reflector antenna systems degrade as the reflector surface distorts, mainly due to thermal effects from solar radiation. The technique developed can be used to maintain the antenna boresight directivity and sidelobe level independent of thermal effects on the reflector surface. With the advent of monolithic microwave integrated circuits (MMIC), a greater flexibility in array fed reflector antenna systems can be achieved. MMIC arrays provide independent control of amplitude and phase for each of the many radiating elements in the feed array. By assuming a known surface distortion profile, a simulation study is carried out to examine the antenna performance as a function of feed array size and number of elements. Results indicate that the compensation technique can effectively control boresight directivity and sidelobe level under peak surface distortion in the order of tenth of a wavelength.

Impulse Testing of Corporate-Fed Patch Array Antennas

NASA Technical Reports Server (NTRS)

Chamberlain, Neil F.

2011-01-01

This paper discusses a novel method for detecting faults in antenna arrays. The method, termed Impulse Testing, was developed for corporate-fed patch arrays where the element is fed by a probe and is shorted at its center. Impulse Testing was devised to supplement conventional microwave measurements in order to quickly verify antenna integrity. The technique relies on exciting each antenna element in turn with a fast pulse (or impulse) that propagates through the feed network to the output port of the antenna. The resulting impulse response is characteristic of the path through the feed network. Using an oscilloscope, a simple amplitude measurement can be made to detect faults. A circuit model of the antenna elements and feed network was constructed to assess various fault scenarios and determine fault-detection thresholds. The experimental setup and impulse measurements for two patch array antennas are presented. Advantages and limitations of the technique are discussed along with applications to other antenna array topologies

Wide-area SWIR arrays and active illuminators

NASA Astrophysics Data System (ADS)

MacDougal, Michael; Hood, Andrew; Geske, Jon; Wang, Chad; Renner, Daniel; Follman, David; Heu, Paula

2012-01-01

We describe the factors that go into the component choices for a short wavelength (SWIR) imager, which include the SWIR sensor, the lens, and the illuminator. We have shown the factors for reducing dark current, and shown that we can achieve well below 1.5 nA/cm2 for 15 μm devices at 7°C. We have mated our InGaAs detector arrays to 640x512 readout integrated integrated circuits (ROICs) to make focal plane arrays (FPAs). In addition, we have fabricated high definition 1920x1080 FPAs for wide field of view imaging. The resulting FPAs are capable of imaging photon fluxes with wavelengths between 1 and 1.6 microns at low light levels. The dark current associated with these FPAs is extremely low, exhibiting a mean dark current density of 0.26 nA/cm2 at 0°C. FLIR has also developed a high definition, 1920x1080, 15 um pitch SWIR sensor. In addition, FLIR has developed laser arrays that provide flat illumination in scenes that are normally light-starved. The illuminators have 40% wall-plug efficiency and provide low-speckle illumination, provide artifact-free imagery versus conventional laser illuminators.

Short-wavelength infrared imaging using low dark current InGaAs detector arrays and vertical-cavity surface-emitting laser illuminators

NASA Astrophysics Data System (ADS)

Macdougal, Michael; Geske, Jon; Wang, Chad; Follman, David

2011-06-01

We describe the factors that go into the component choices for a short wavelength IR (SWIR) imager, which include the SWIR sensor, the lens, and the illuminator. We have shown the factors for reducing dark current, and shown that we can achieve well below 1.5 nA/cm2 for 15 μm devices at 7 °C. In addition, we have mated our InGaAs detector arrays to 640×512 readout integrated integrated circuits to make focal plane arrays (FPAs). The resulting FPAs are capable of imaging photon fluxes with wavelengths between 1 and 1.6 μm at low light levels. The dark current associated with these FPAs is extremely low, exhibiting a mean dark current density of 0.26 nA/cm2 at 0 °C. Noise due to the readout can be reduced from 95 to 57 electrons by using off-chip correlated double sampling. In addition, Aerius has developed laser arrays that provide flat illumination in scenes that are normally light-starved. The illuminators have 40% wall-plug efficiency and provide low-speckle illumination, and provide artifact-free imagery versus conventional laser illuminators.

Off-Line Quality Control In Integrated Circuit Fabrication Using Experimental Design

NASA Astrophysics Data System (ADS)

Phadke, M. S.; Kackar, R. N.; Speeney, D. V.; Grieco, M. J.

1987-04-01

Off-line quality control is a systematic method of optimizing production processes and product designs. It is widely used in Japan to produce high quality products at low cost. The method was introduced to us by Professor Genichi Taguchi who is a Deming-award winner and a former Director of the Japanese Academy of Quality. In this paper we will i) describe the off-line quality control method, and ii) document our efforts to optimize the process for forming contact windows in 3.5 Aim CMOS circuits fabricated in the Murray Hill Integrated Circuit Design Capability Laboratory. In the fabrication of integrated circuits it is critically important to produce contact windows of size very near the target dimension. Windows which are too small or too large lead to loss of yield. The off-line quality control method has improved both the process quality and productivity. The variance of the window size has been reduced by a factor of four. Also, processing time for window photolithography has been substantially reduced. The key steps of off-line quality control are: i) Identify important manipulatable process factors and their potential working levels. ii) Perform fractional factorial experiments on the process using orthogonal array designs. iii) Analyze the resulting data to determine the optimum operating levels of the factors. Both the process mean and the process variance are considered in this analysis. iv) Conduct an additional experiment to verify that the new factor levels indeed give an improvement.

HYMOSS signal processing for pushbroom spectral imaging

NASA Technical Reports Server (NTRS)

Ludwig, David E.

1991-01-01

The objective of the Pushbroom Spectral Imaging Program was to develop on-focal plane electronics which compensate for detector array non-uniformities. The approach taken was to implement a simple two point calibration algorithm on focal plane which allows for offset and linear gain correction. The key on focal plane features which made this technique feasible was the use of a high quality transimpedance amplifier (TIA) and an analog-to-digital converter for each detector channel. Gain compensation is accomplished by varying the feedback capacitance of the integrate and dump TIA. Offset correction is performed by storing offsets in a special on focal plane offset register and digitally subtracting the offsets from the readout data during the multiplexing operation. A custom integrated circuit was designed, fabricated, and tested on this program which proved that nonuniformity compensated, analog-to-digital converting circuits may be used to read out infrared detectors. Irvine Sensors Corporation (ISC) successfully demonstrated the following innovative on-focal-plane functions that allow for correction of detector non-uniformities. Most of the circuit functions demonstrated on this program are finding their way onto future IC's because of their impact on reduced downstream processing, increased focal plane performance, simplified focal plane control, reduced number of dewar connections, as well as the noise immunity of a digital interface dewar. The potential commercial applications for this integrated circuit are primarily in imaging systems. These imaging systems may be used for: security monitoring systems, manufacturing process monitoring, robotics, and for spectral imaging when used in analytical instrumentation.

HYMOSS signal processing for pushbroom spectral imaging

NASA Astrophysics Data System (ADS)

Ludwig, David E.

1991-06-01

The objective of the Pushbroom Spectral Imaging Program was to develop on-focal plane electronics which compensate for detector array non-uniformities. The approach taken was to implement a simple two point calibration algorithm on focal plane which allows for offset and linear gain correction. The key on focal plane features which made this technique feasible was the use of a high quality transimpedance amplifier (TIA) and an analog-to-digital converter for each detector channel. Gain compensation is accomplished by varying the feedback capacitance of the integrate and dump TIA. Offset correction is performed by storing offsets in a special on focal plane offset register and digitally subtracting the offsets from the readout data during the multiplexing operation. A custom integrated circuit was designed, fabricated, and tested on this program which proved that nonuniformity compensated, analog-to-digital converting circuits may be used to read out infrared detectors. Irvine Sensors Corporation (ISC) successfully demonstrated the following innovative on-focal-plane functions that allow for correction of detector non-uniformities. Most of the circuit functions demonstrated on this program are finding their way onto future IC's because of their impact on reduced downstream processing, increased focal plane performance, simplified focal plane control, reduced number of dewar connections, as well as the noise immunity of a digital interface dewar. The potential commercial applications for this integrated circuit are primarily in imaging systems. These imaging systems may be used for: security monitoring systems, manufacturing process monitoring, robotics, and for spectral imaging when used in analytical instrumentation.

High event rate ROICs (HEROICs) for astronomical UV photon counting detectors

NASA Astrophysics Data System (ADS)

Harwit, Alex; France, Kevin; Argabright, Vic; Franka, Steve; Freymiller, Ed; Ebbets, Dennis

2014-07-01

The next generation of astronomical photocathode / microchannel plate based UV photon counting detectors will overcome existing count rate limitations by replacing the anode arrays and external cabled electronics with anode arrays integrated into imaging Read Out Integrated Circuits (ROICs). We have fabricated a High Event Rate ROIC (HEROIC) consisting of a 32 by 32 array of 55 μm square pixels on a 60 μm pitch. The pixel sensitivity (threshold) has been designed to be globally programmable between 1 × 103 and 1 × 106 electrons. To achieve the sensitivity of 1 × 103 electrons, parasitic capacitances had to be minimized and this was achieved by fabricating the ROIC in a 65 nm CMOS process. The ROIC has been designed to support pixel counts up to 4096 events per integration period at rates up to 1 MHz per pixel. Integration time periods can be controlled via an external signal with a time resolution of less than 1 microsecond enabling temporally resolved imaging and spectroscopy of astronomical sources. An electrical injection port is provided to verify functionality and performance of each ROIC prior to vacuum integration with a photocathode and microchannel plate amplifier. Test results on the first ROICs using the electrical injection port demonstrate sensitivities between 3 × 103 and 4 × 105 electrons are achieved. A number of fixes are identified for a re-spin of this ROIC.

Piezoelectric micromachined ultrasonic transducers for fingerprint sensing

NASA Astrophysics Data System (ADS)

Lu, Yipeng

Fingerprint identification is the most prevalent biometric technology due to its uniqueness, universality and convenience. Over the past two decades, a variety of physical mechanisms have been exploited to capture an electronic image of a human fingerprint. Among these, capacitive fingerprint sensors are the ones most widely used in consumer electronics because they are fabricated using conventional complementary metal oxide semiconductor (CMOS) integrated circuit technology. However, capacitive fingerprint sensors are extremely sensitive to finger contamination and moisture. This thesis will introduce an ultrasonic fingerprint sensor using a PMUT array, which offers a potential solution to this problem. In addition, it has the potential to increase security, as it allows images to be collected at various depths beneath the epidermis, providing images of the sub-surface dermis layer and blood vessels. Firstly, PMUT sensitivity is maximized by optimizing the layer stack and electrode design, and the coupling coefficient is doubled via series transduction. Moreover, a broadband PMUT with 97% fractional bandwidth is achieved by utilizing a thinner structure excited at two adjacent mechanical vibration modes with overlapping bandwidth. In addition, we proposed waveguide PMUTs, which function to direct acoustic waves, confine acoustic energy, and provide mechanical protection for the PMUT array. Furthermore, PMUT arrays were fabricated with different processes to form the membrane, including front-side etching with a patterned sacrificial layer, front-side etching with additional anchor, cavity SOI wafers and eutectic bonding. Additionally, eutectic bonding allows the PMUT to be integrated with CMOS circuits. PMUTs were characterized in the mechanical, electrical and acoustic domains. Using transmit beamforming, a narrow acoustic beam was achieved, and high-resolution (sub-100 microm) and short-range (~1 mm) pulse-echo ultrasonic imaging was demonstrated using a steel phantom. Finally, a novel ultrasonic fingerprint sensor was demonstrated using a 24x8 array of 22 MHz PMUTs with 100 microm pitch, fully integrated with 180 nm CMOS circuitry through eutectic wafer bonding. Each PMUT is directly bonded to a dedicated CMOS receive amplifier, minimizing electrical parasitics and eliminating the need for through-silicon vias. Pulse-echo imaging of a 1D steel grating is demonstrated using electronic scanning of a 20x8 sub-array, resulting in 300 mV maximum received amplitude and 5:1 contrast ratio. Because the small size of this array limits the maximum image size, mechanical scanning was used to image a 2D PDMS fingerprint phantom (10 mm by 8 mm) at a 1.2 mm distance from the array.

RF Design of a Wideband CMOS Integrated Receiver for Phased Array Applications

NASA Astrophysics Data System (ADS)

Jackson, Suzy A.

2004-06-01

New silicon CMOS processes developed primarily for the burgeoning wireless networking market offer significant promise as a vehicle for the implementation of highly integrated receivers, especially at the lower end of the frequency range proposed for the Square Kilometre Array (SKA). An RF-CMOS ‘Receiver-on-a-Chip’ is being developed as part of an Australia Telescope program looking at technologies associated with the SKA. The receiver covers the frequency range 500 1700 MHz, with instantaneous IF bandwidth of 500 MHz and, on simulation, yields an input noise temperature of < 50 K at mid-band. The receiver will contain all active circuitry (LNA, bandpass filter, quadrature mixer, anti-aliasing filter, digitiser and serialiser) on one 0.18 μm RF-CMOS integrated circuit. This paper outlines receiver front-end development work undertaken to date, including design and simulation of an LNA using noise cancelling techniques to achieve a wideband input-power-match with little noise penalty.

A new generation of ultra-dense optical I/O for silicon photonics

NASA Astrophysics Data System (ADS)

Wlodawski, Mitchell S.; Kopp, Victor I.; Park, Jongchul; Singer, Jonathan; Hubner, Eric E.; Neugroschl, Daniel; Chao, Norman; Genack, Azriel Z.

2014-03-01

In response to the optical packaging needs of a rapidly growing silicon photonics market, Chiral Photonics, Inc. (CPI) has developed a new generation of ultra-dense-channel, bi-directional, all-optical, input/output (I/O) couplers that bridge the data transport gap between standard optical fibers and photonic integrated circuits. These couplers, called Pitch Reducing Optical Fiber Arrays (PROFAs), provide a means to simultaneously match both the mode field and channel spacing (i.e. pitch) between an optical fiber array and a photonic integrated circuit (PIC). Both primary methods for optically interfacing with PICs, via vertical grating couplers (VGCs) and edge couplers, can be addressed with PROFAs. PROFAs bring the signal-carrying cores, either multimode or singlemode, of many optical fibers into close proximity within an all-glass device that can provide low loss coupling to on-chip components, including waveguides, gratings, detectors and emitters. Two-dimensional (2D) PROFAs offer more than an order of magnitude enhancement in channel density compared to conventional one-dimensional (1D) fiber arrays. PROFAs can also be used with low vertical profile solutions that simplify optoelectronic packaging while reducing PIC I/O real estate usage requirements. PROFA technology is based on a scalable production process for microforming glass preform assemblies as they are pulled through a small oven. An innovative fiber design, called the "vanishing core," enables tailoring the mode field along the length of the PROFA to meet the coupling needs of disparate waveguide technologies, such as fiber and onchip. Examples of single- and multi-channel couplers fabricated using this technology will be presented.

Focal plane infrared readout circuit with automatic background suppression

NASA Technical Reports Server (NTRS)

Pain, Bedabrata (Inventor); Yang, Guang (Inventor); Sun, Chao (Inventor); Shaw, Timothy J. (Inventor); Wrigley, Chris J. (Inventor)

2002-01-01

A circuit for reading out a signal from an infrared detector includes a current-mode background-signal subtracting circuit having a current memory which can be enabled to sample and store a dark level signal from the infrared detector during a calibration phase. The signal stored by the current memory is subtracted from a signal received from the infrared detector during an imaging phase. The circuit also includes a buffered direct injection input circuit and a differential voltage readout section. By performing most of the background signal estimation and subtraction in a current mode, a low gain can be provided by the buffered direct injection input circuit to keep the gain of the background signal relatively small, while a higher gain is provided by the differential voltage readout circuit. An array of such readout circuits can be used in an imager having an array of infrared detectors. The readout circuits can provide a high effective handling capacity.

Architecturing hierarchical function layers on self-assembled viral templates as 3D nano-array electrodes for integrated Li-ion microbatteries.

PubMed

Liu, Yihang; Zhang, Wei; Zhu, Yujie; Luo, Yanting; Xu, Yunhua; Brown, Adam; Culver, James N; Lundgren, Cynthia A; Xu, Kang; Wang, Yuan; Wang, Chunsheng

2013-01-09

This work enables an elegant bottom-up solution to engineer 3D microbattery arrays as integral power sources for microelectronics. Thus, multilayers of functional materials were hierarchically architectured over tobacco mosaic virus (TMV) templates that were genetically modified to self-assemble in a vertical manner on current-collectors, so that optimum power and energy densities accompanied with excellent cycle-life could be achieved on a minimum footprint. The resultant microbattery based on self-aligned LiFePO(4) nanoforests of shell-core-shell structure, with precise arrangement of various auxiliary material layers including a central nanometric metal core as direct electronic pathway to current collector, delivers excellent energy density and stable cycling stability only rivaled by the best Li-ion batteries of conventional configurations, while providing rate performance per foot-print and on-site manufacturability unavailable from the latter. This approach could open a new avenue for microelectromechanical systems (MEMS) applications, which would significantly benefit from the concept that electrochemically active components be directly engineered and fabricated as an integral part of the integrated circuit (IC).

A 25μm pitch LWIR focal plane array with pixel-level 15-bit ADC providing high well capacity and targeting 2mK NETD

NASA Astrophysics Data System (ADS)

Guellec, Fabrice; Peizerat, Arnaud; Tchagaspanian, Michael; de Borniol, Eric; Bisotto, Sylvette; Mollard, Laurent; Castelein, Pierre; Zanatta, Jean-Paul; Maillart, Patrick; Zecri, Michel; Peyrard, Jean-Christophe

2010-04-01

CEA Leti has recently developed a new readout IC (ROIC) with pixel-level ADC for cooled infrared focal plane arrays (FPAs). It operates at 50Hz frame rate in a snapshot Integrate-While-Read (IWR) mode. It targets applications that provide a large amount of integrated charge thanks to a long integration time. The pixel-level analog-to-digital conversion is based on charge packets counting. This technique offers a large well capacity that paves the way for a breakthrough in NETD performances. The 15 bits ADC resolution preserves the excellent detector SNR at full well (3Ge-). These characteristics are essential for LWIR FPAs as broad intra-scene dynamic range imaging requires high sensitivity. The ROIC, featuring a 320x256 array with 25μm pixel pitch, has been designed in a standard 0.18μm CMOS technology. The main design challenges for this digital pixel array (SNR, power consumption and layout density) are discussed. The IC has been hybridized to a LWIR detector fabricated using our in-house HgCdTe process. The first electro-optical test results of the detector dewar assembly are presented. They validate both the pixel-level ADC concept and its circuit implementation. Finally, the benefit of this LWIR FPA in terms of NETD performance is demonstrated.

Maskless lithography

DOEpatents

Sweatt, William C.; Stulen, Richard H.

1999-01-01

The present invention provides a method for maskless lithography. A plurality of individually addressable and rotatable micromirrors together comprise a two-dimensional array of micromirrors. Each micromirror in the two-dimensional array can be envisioned as an individually addressable element in the picture that comprises the circuit pattern desired. As each micromirror is addressed it rotates so as to reflect light from a light source onto a portion of the photoresist coated wafer thereby forming a pixel within the circuit pattern. By electronically addressing a two-dimensional array of these micromirrors in the proper sequence a circuit pattern that is comprised of these individual pixels can be constructed on a microchip. The reflecting surface of the micromirror is configured in such a way as to overcome coherence and diffraction effects in order to produce circuit elements having straight sides.

Maskless lithography

DOEpatents

Sweatt, W.C.; Stulen, R.H.

1999-02-09

The present invention provides a method for maskless lithography. A plurality of individually addressable and rotatable micromirrors together comprise a two-dimensional array of micromirrors. Each micromirror in the two-dimensional array can be envisioned as an individually addressable element in the picture that comprises the circuit pattern desired. As each micromirror is addressed it rotates so as to reflect light from a light source onto a portion of the photoresist coated wafer thereby forming a pixel within the circuit pattern. By electronically addressing a two-dimensional array of these micromirrors in the proper sequence a circuit pattern that is comprised of these individual pixels can be constructed on a microchip. The reflecting surface of the micromirror is configured in such a way as to overcome coherence and diffraction effects in order to produce circuit elements having straight sides. 12 figs.

Method for maskless lithography

DOEpatents

Sweatt, William C.; Stulen, Richard H.

2000-01-01

The present invention provides a method for maskless lithography. A plurality of individually addressable and rotatable micromirrors together comprise a two-dimensional array of micromirrors. Each micromirror in the two-dimensional array can be envisioned as an individually addressable element in the picture that comprises the circuit pattern desired. As each micromirror is addressed it rotates so as to reflect light from a light source onto a portion of the photoresist coated wafer thereby forming a pixel within the circuit pattern. By electronically addressing a two-dimensional array of these micromirrors in the proper sequence a circuit pattern that is comprised of these individual pixels can be constructed on a microchip. The reflecting surface of the micromirror is configured in such a way as to overcome coherence and diffraction effects in order to produce circuit elements having straight sides.

A visually guided collision warning system with a neuromorphic architecture.

PubMed

Okuno, Hirotsugu; Yagi, Tetsuya

2008-12-01

We have designed a visually guided collision warning system with a neuromorphic architecture, employing an algorithm inspired by the visual nervous system of locusts. The system was implemented with mixed analog-digital integrated circuits consisting of an analog resistive network and field-programmable gate array (FPGA) circuits. The resistive network processes the interaction between the laterally spreading excitatory and inhibitory signals instantaneously, which is essential for real-time computation of collision avoidance with a low power consumption and a compact hardware. The system responded selectively to approaching objects of simulated movie images at close range. The system was, however, confronted with serious noise problems due to the vibratory ego-motion, when it was installed in a mobile miniature car. To overcome this problem, we developed the algorithm, which is also installable in FPGA circuits, in order for the system to respond robustly during the ego-motion.

Monolithic integration of a silica AWG and Ge photodiodes on Si photonic platform for one-chip WDM receiver.

PubMed

Nishi, Hidetaka; Tsuchizawa, Tai; Kou, Rai; Shinojima, Hiroyuki; Yamada, Takashi; Kimura, Hideaki; Ishikawa, Yasuhiko; Wada, Kazumi; Yamada, Koji

2012-04-09

On the silicon (Si) photonic platform, we monolithically integrated a silica-based arrayed-waveguide grating (AWG) and germanium (Ge) photodiodes (PDs) using low-temperature fabrication technology. We confirmed demultiplexing by the AWG, optical-electrical signal conversion by Ge PDs, and high-speed signal detection at all channels. In addition, we mounted a multichannel transimpedance amplifier/limiting amplifier (TIA/LA) circuit on the fabricated AWG-PD device using flip-chip bonding technology. The results show the promising potential of our Si photonic platform as a photonics-electronics convergence.

Electrically reconfigurable logic array

NASA Technical Reports Server (NTRS)

Agarwal, R. K.

1982-01-01

To compose the complicated systems using algorithmically specialized logic circuits or processors, one solution is to perform relational computations such as union, division and intersection directly on hardware. These relations can be pipelined efficiently on a network of processors having an array configuration. These processors can be designed and implemented with a few simple cells. In order to determine the state-of-the-art in Electrically Reconfigurable Logic Array (ERLA), a survey of the available programmable logic array (PLA) and the logic circuit elements used in such arrays was conducted. Based on this survey some recommendations are made for ERLA devices.

A closed-loop compressive-sensing-based neural recording system.

PubMed

Zhang, Jie; Mitra, Srinjoy; Suo, Yuanming; Cheng, Andrew; Xiong, Tao; Michon, Frederic; Welkenhuysen, Marleen; Kloosterman, Fabian; Chin, Peter S; Hsiao, Steven; Tran, Trac D; Yazicioglu, Firat; Etienne-Cummings, Ralph

2015-06-01

This paper describes a low power closed-loop compressive sensing (CS) based neural recording system. This system provides an efficient method to reduce data transmission bandwidth for implantable neural recording devices. By doing so, this technique reduces a majority of system power consumption which is dissipated at data readout interface. The design of the system is scalable and is a viable option for large scale integration of electrodes or recording sites onto a single device. The entire system consists of an application-specific integrated circuit (ASIC) with 4 recording readout channels with CS circuits, a real time off-chip CS recovery block and a recovery quality evaluation block that provides a closed feedback to adaptively adjust compression rate. Since CS performance is strongly signal dependent, the ASIC has been tested in vivo and with standard public neural databases. Implemented using efficient digital circuit, this system is able to achieve >10 times data compression on the entire neural spike band (500-6KHz) while consuming only 0.83uW (0.53 V voltage supply) additional digital power per electrode. When only the spikes are desired, the system is able to further compress the detected spikes by around 16 times. Unlike other similar systems, the characteristic spikes and inter-spike data can both be recovered which guarantes a >95% spike classification success rate. The compression circuit occupied 0.11mm(2)/electrode in a 180nm CMOS process. The complete signal processing circuit consumes <16uW/electrode. Power and area efficiency demonstrated by the system make it an ideal candidate for integration into large recording arrays containing thousands of electrode. Closed-loop recording and reconstruction performance evaluation further improves the robustness of the compression method, thus making the system more practical for long term recording.

Medium power amplifiers covering 90 - 130 GHz for telescope local oscillators

NASA Technical Reports Server (NTRS)

Samoska, Lorene A.; Bryerton, Eric; Pukala, David; Peralta, Alejandro; Hu, Ming; Schmitz, Adele

2005-01-01

This paper describes a set of power amplifier (PA) modules containing InP High Electron Mobility Transistor (HEMT) Monolithic Millimeter-wave Integrated Circuit (MMIC) chips. The chips were designed and optimized for local oscillator sources in the 90-130 GHz band for the Atacama Large Millimeter Array telescope. The modules feature 20-45 mW of output power, to date the highest power from solid state HEMT MMIC modules above 110 GHz.

Biomedical ultrasonoscope

NASA Technical Reports Server (NTRS)

Lee, R. D. (Inventor)

1976-01-01

An instrument with a single ultrasonic transducer probe and a linear array of transducer probes permitting three operator modes is described. An 'A' and an 'M' mode scanner were combined with a 'C' mode scanner and a single receiver is used. The 'C' scanner mode enables two-dimensional cross sections of the viewed organ. Video-produced markers enable measurement of the dimensions of the heart. COS/MOS integrated logic circuit components are used to minimize power consumption and permit battery operation.

Design and performance of single photon APD focal plane arrays for 3-D LADAR imaging

NASA Astrophysics Data System (ADS)

Itzler, Mark A.; Entwistle, Mark; Owens, Mark; Patel, Ketan; Jiang, Xudong; Slomkowski, Krystyna; Rangwala, Sabbir; Zalud, Peter F.; Senko, Tom; Tower, John; Ferraro, Joseph

2010-08-01

×We describe the design, fabrication, and performance of focal plane arrays (FPAs) for use in 3-D LADAR imaging applications requiring single photon sensitivity. These 32 × 32 FPAs provide high-efficiency single photon sensitivity for three-dimensional LADAR imaging applications at 1064 nm. Our GmAPD arrays are designed using a planarpassivated avalanche photodiode device platform with buried p-n junctions that has demonstrated excellent performance uniformity, operational stability, and long-term reliability. The core of the FPA is a chip stack formed by hybridizing the GmAPD photodiode array to a custom CMOS read-out integrated circuit (ROIC) and attaching a precision-aligned GaP microlens array (MLA) to the back-illuminated detector array. Each ROIC pixel includes an active quenching circuit governing Geiger-mode operation of the corresponding avalanche photodiode pixel as well as a pseudo-random counter to capture per-pixel time-of-flight timestamps in each frame. The FPA has been designed to operate at frame rates as high as 186 kHz for 2 μs range gates. Effective single photon detection efficiencies as high as 40% (including all optical transmission and MLA losses) are achieved for dark count rates below 20 kHz. For these planar-geometry diffused-junction GmAPDs, isolation trenches are used to reduce crosstalk due to hot carrier luminescence effects during avalanche events, and we present details of the crosstalk performance for different operating conditions. Direct measurement of temporal probability distribution functions due to cumulative timing uncertainties of the GmAPDs and ROIC circuitry has demonstrated a FWHM timing jitter as low as 265 ps (standard deviation is ~100 ps).

Silica-based, compact and variable-optical-attenuator integrated coherent receiver with stable optoelectronic coupling system.

PubMed

Tsunashima, Satoshi; Nakajima, Fumito; Nasu, Yusuke; Kasahara, Ryoichi; Nakanishi, Yasuhiko; Saida, Takashi; Yamada, Takashi; Sano, Kimikazu; Hashimoto, Toshikazu; Fukuyama, Hiroyuki; Nosaka, Hideaki; Murata, Koichi

2012-11-19

We demonstrate a compact and variable-optical-attenuator (VOA) integrated coherent receiver with a silica-based planar lightwave circuit (PLC). To realize the compact receiver, we integrate a VOA in a single PLC chip with polarization beam splitters and optical 90-degree hybrids, and employ a stable optoelectronic coupling system consisting of micro lens arrays and photodiode (PD) subcarriers with high-speed right-angled signal lines. We integrate a VOA and a coherent receiver in a 27x40x6 mm package, and successfully demodulate a 128-Gbit/s polarization division multiplexed (PDM) quadrature phase shift keying (QPSK) signal with a VOA-assisted wide dynamic range of more than 30 dB.

The electronics system for the LBNL positron emission mammography (PEM) camera

NASA Astrophysics Data System (ADS)

Moses, W. W.; Young, J. W.; Baker, K.; Jones, W.; Lenox, M.; Ho, M. H.; Weng, M.

2001-06-01

Describes the electronics for a high-performance positron emission mammography (PEM) camera. It is based on the electronics for a human brain positron emission tomography (PET) camera (the Siemens/CTI HRRT), modified to use a detector module that incorporates a photodiode (PD) array. An application-specified integrated circuit (ASIC) services the photodetector (PD) array, amplifying its signal and identifying the crystal of interaction. Another ASIC services the photomultiplier tube (PMT), measuring its output and providing a timing signal. Field-programmable gate arrays (FPGAs) and lookup RAMs are used to apply crystal-by-crystal correction factors and measure the energy deposit and the interaction depth (based on the PD/PMT ratio). Additional FPGAs provide event multiplexing, derandomization, coincidence detection, and real-time rebinning. Embedded PC/104 microprocessors provide communication, real-time control, and configure the system. Extensive use of FPGAs make the overall design extremely flexible, allowing many different functions (or design modifications) to be realized without hardware changes. Incorporation of extensive onboard diagnostics, implemented in the FPGAs, is required by the very high level of integration and density achieved by this system.

Albion: the UK 3rd generation high-performance thermal imaging programme

NASA Astrophysics Data System (ADS)

McEwen, R. K.; Lupton, M.; Lawrence, M.; Knowles, P.; Wilson, M.; Dennis, P. N. J.; Gordon, N. T.; Lees, D. J.; Parsons, J. F.

2007-04-01

The first generation of high performance thermal imaging sensors in the UK was based on two axis opto-mechanical scanning systems and small (4-16 element) arrays of the SPRITE detector, developed during the 1970s. Almost two decades later, a 2nd Generation system, STAIRS C was introduced, based on single axis scanning and a long linear array of approximately 3000 elements. The UK has now begun the industrialisation of 3 rd Generation High Performance Thermal Imaging under a programme known as "Albion". Three new high performance cadmium mercury telluride arrays are being manufactured. The CMT material is grown by MOVPE on low cost substrates and bump bonded to the silicon read out circuit (ROIC). To maintain low production costs, all three detectors are designed to fit with existing standard Integrated Detector Cooling Assemblies (IDCAs). The two largest focal planes are conventional devices operating in the MWIR and LWIR spectral bands. A smaller format LWIR device is also described which has a smart ROIC, enabling much longer stare times than are feasible with conventional pixel circuits, thus achieving very high sensitivity. A new reference surface technology for thermal imaging sensors is described, based on Negative Luminescence (NL), which offers several advantages over conventional peltier references, improving the quality of the Non-Uniformity Correction (NUC) algorithms.

An inverter-based capacitive trans-impedance amplifier readout with offset cancellation and temporal noise reduction for IR focal plane array

NASA Astrophysics Data System (ADS)

Chen, Hsin-Han; Hsieh, Chih-Cheng

2013-09-01

This paper presents a readout integrated circuit (ROIC) with inverter-based capacitive trans-impedance amplifier (CTIA) and pseudo-multiple sampling technique for infrared focal plane array (IRFPA). The proposed inverter-based CTIA with a coupling capacitor [1], executing auto-zeroing technique to cancel out the varied offset voltage from process variation, is used to substitute differential amplifier in conventional CTIA. The tunable detector bias is applied from a global external bias before exposure. This scheme not only retains stable detector bias voltage and signal injection efficiency, but also reduces the pixel area as well. Pseudo-multiple sampling technique [2] is adopted to reduce the temporal noise of readout circuit. The noise reduction performance is comparable to the conventional multiple sampling operation without need of longer readout time proportional to the number of samples. A CMOS image sensor chip with 55×65 pixel array has been fabricated in 0.18um CMOS technology. It achieves a 12um×12um pixel size, a frame rate of 72 fps, a power-per-pixel of 0.66uW/pixel, and a readout temporal noise of 1.06mVrms (16 times of pseudo-multiple sampling), respectively.

Vertically aligned p-type single-crystalline GaN nanorod arrays on n-type Si for heterojunction photovoltaic cells.

PubMed

Tang, Y B; Chen, Z H; Song, H S; Lee, C S; Cong, H T; Cheng, H M; Zhang, W J; Bello, I; Lee, S T

2008-12-01

Vertically aligned Mg-doped GaN nanorods have been epitaxially grown on n-type Si substrate to form a heterostructure for fabricating p-n heterojunction photovoltaic cells. The p-type GaN nanorod/n-Si heterojunction cell shows a well-defined rectifying behavior with a rectification ratio larger than 10(4) in dark. The cell has a high short-circuit photocurrent density of 7.6 mAlcm2 and energy conversion efficiency of 2.73% under AM 1.5G illumination at 100 mW/cm2. Moreover, the nanorod array may be used as an antireflection coating for solar cell applications to effectively reduce light loss due to reflection. This study provides an experimental demonstration for integrating one-dimensional nanostructure arrays with the substrate to directly fabricate heterojunction photovoltaic cells.

Microsensor research

NASA Astrophysics Data System (ADS)

Hughes, R. C.; Drebing, C. G.

1990-04-01

The technology that led to very large scale integrated circuits on silicon chips also provides a basis for new microsensors that are small, inexpensive, low power, rugged, and reliable. Two examples of microsensors Sandia is developing that take advantage of this technology are the microelectronic chemical sensor array and the radiation sensing field effect transistor (RADFET). Increasingly, the technology of chemical sensing needs new microsensor concepts. Applications in this area include environmental monitoring, criminal investigations, and state-of-health monitoring, both for equipment and living things. Chemical microsensors can satisfy sensing needs in the industrial, consumer, aerospace, and defense sectors. The microelectronic chemical-sensor array may address some of these applications. We have fabricated six separate chemical gas sensing areas on the microelectronic chemical sensor array. By using different catalytic metals on the gate areas of the diodes, we can selectively sense several gases.

NASA Tech Briefs, May 2003

NASA Technical Reports Server (NTRS)

2003-01-01

Topics covered include: Using Diffusion Bonding in Making Piezoelectric Actuators; Wireless Temperature-Monitoring System; Analog Binaural Circuits for Detecting and Locating Leaks; Mirrors Containing Biomimetic Shape-Control Actuators; Surface-Micromachined Planar Arrays of Thermopiles; Cascade Back-Propagation Learning in Neural Networks; Perovskite Superlattices as Tunable Microwave Devices; Rollable Thin-Shell Nanolaminate Mirrors; Flight Tests of a Ministick Controller in an F/A-18 Airplane; Piezoelectrically Actuated Shutter for High Vacuum; Bio-Inspired Engineering of Exploration Systems; Microscope Cells Containing Multiple Micromachined Wells; Electrophoretic Deposition for Fabricating Microbatteries; Integrated Arrays of Ion-Sensitive Electrodes; Model of Fluidized Bed Containing Reacting Solids and Gases; Membrane Mirrors With Bimorph Shape Actuators; Using Fractional Clock-Period Delays in Telemetry Arraying; Developing Generic Software for Spacecraft Avionics; Numerical Study of Pyrolysis of Biomass in Fluidized Beds; and Assessment of Models of Chemically Reacting Granular Flows.

Trade-offs between lens complexity and real estate utilization in a free-space multichip global interconnection module.

PubMed

Milojkovic, Predrag; Christensen, Marc P; Haney, Michael W

2006-07-01

The FAST-Net (Free-space Accelerator for Switching Terabit Networks) concept uses an array of wide-field-of-view imaging lenses to realize a high-density shuffle interconnect pattern across an array of smart-pixel integrated circuits. To simplify the optics we evaluated the efficiency gained in replacing spherical surfaces with aspherical surfaces by exploiting the large disparity between narrow vertical cavity surface emitting laser (VCSEL) beams and the wide field of view of the imaging optics. We then analyzed trade-offs between lens complexity and chip real estate utilization and determined that there exists an optimal numerical aperture for VCSELs that maximizes their area density. The results provide a general framework for the design of wide-field-of-view free-space interconnection systems that incorporate high-density VCSEL arrays.

III-nitride nanowire LEDs and diode lasers: monolithic light sources on (001) Si emitting in the 600-1300nm range

NASA Astrophysics Data System (ADS)

Bhattacharya, P.; Hazari, A.; Jahangir, S.

2018-02-01

GaN-based nanowire heterostructure arrays epitaxially grown on (001)Si substrates have unique properties and present the potential to realize useful devices. The active light-emitting region in the nanowire heterostructures are usually InGaN disks, whose composition can be varied to tune the emission wavelength. We have demonstrated light emitting diodes and edgeemitting diode lasers with power outputs 10mW with emission in the 600-1300nm wavelength range. These light sources are therefore useful for a variety of applications, including silicon photonics. Molecular beam epitaxial growth of the nanowire heterostructure arrays on (001)Si substrates and the characteristics of 1.3μm nanowire array edge emitting lasers, guided wave photodiodes and a monolithic photonic integrated circuit designed for 1.3μm operation are described.

A selective nanosensor device for exhaled breath analysis.

PubMed

Gouma, P; Prasad, A; Stanacevic, S

2011-09-01

This paper describes a novel concept of a three-nanosensor array microsystem that may potentially serve as a coarse diagnostic tool handheld breath analyzer to provide a first detection device. The specification and performance of a simple metal oxide nanosensor operating between three distinct temperatures are discussed, focusing on the need for a noninvasive blood cholesterol monitor. Interfacing the sensor array to an integrated circuit for electrical readout and temperature control provides a complete microsystem capable of capturing a single exhaled breath and analyzing it with respect to the relative content of isoprene, carbon dioxide and ammonia gas. This inexpensive sensor technology may be used as a personalized medical diagnostics tool in the near future.

Thin conformal antenna array for microwave power conversions

NASA Technical Reports Server (NTRS)

Dickinson, R. M. (Inventor)

1978-01-01

A structure of a circularly polarized, thin conformal, antenna array which may be mounted integrally with the skin of an aircraft employs microstrip elliptical elements and interconnecting feed lines spaced from a circuit ground plane by a thin dielectric layer. The feed lines are impedance matched to the elliptical antenna elements by selecting a proper feedpoint inside the periphery of the elliptical antenna elements. Diodes connected between the feed lines and the ground plane rectify the microwave power, and microstrip filters (low pass) connected in series with the feed lines provide dc current to a microstrip bus. Low impedance matching strips are included between the elliptical elements and the rectifying and filtering elements.

Displacement sensors using soft magnetostrictive alloys

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hristoforou, E.; Reilly, R.E.

1994-09-01

The authors report results on the response of a family of displacement sensors, which are based on the magnetostrictive delay line (MDL) technique, using current conductor orthogonal to the MDL. Such sensing technique is based on the change of the magnetic circuit and the acoustic stress point of origin due to the displacement of a soft magnetic material above it. Integrated arrays of sensors can be obtained due to the acoustic delay line technique and they can be used as tactile arrays, digitizers or devices for medical application (gait analysis etc.), while absence of hysteresis and low cost of manufacturingmore » make them competent in this sector of sensor market.« less

Battery Charge Equalizer with Transformer Array

NASA Technical Reports Server (NTRS)

Davies, Francis

2013-01-01

High-power batteries generally consist of a series connection of many cells or cell banks. In order to maintain high performance over battery life, it is desirable to keep the state of charge of all the cell banks equal. A method provides individual charging for battery cells in a large, high-voltage battery array with a minimum number of transformers while maintaining reasonable efficiency. This is designed to augment a simple highcurrent charger that supplies the main charge energy. The innovation will form part of a larger battery charge system. It consists of a transformer array connected to the battery array through rectification and filtering circuits. The transformer array is connected to a drive circuit and a timing and control circuit that allow individual battery cells or cell banks to be charged. The timing circuit and control circuit connect to a charge controller that uses battery instrumentation to determine which battery bank to charge. It is important to note that the innovation can charge an individual cell bank at the same time that the main battery charger is charging the high-voltage battery. The fact that the battery cell banks are at a non-zero voltage, and that they are all at similar voltages, can be used to allow charging of individual cell banks. A set of transformers can be connected with secondary windings in series to make weighted sums of the voltages on the primaries.

A miniature electronic nose system based on an MWNT-polymer microsensor array and a low-power signal-processing chip.

PubMed

Chiu, Shih-Wen; Wu, Hsiang-Chiu; Chou, Ting-I; Chen, Hsin; Tang, Kea-Tiong

2014-06-01

This article introduces a power-efficient, miniature electronic nose (e-nose) system. The e-nose system primarily comprises two self-developed chips, a multiple-walled carbon nanotube (MWNT)-polymer based microsensor array, and a low-power signal-processing chip. The microsensor array was fabricated on a silicon wafer by using standard photolithography technology. The microsensor array comprised eight interdigitated electrodes surrounded by SU-8 "walls," which restrained the material-solvent liquid in a defined area of 650 × 760 μm(2). To achieve a reliable sensor-manufacturing process, we used a two-layer deposition method, coating the MWNTs and polymer film as the first and second layers, respectively. The low-power signal-processing chip included array data acquisition circuits and a signal-processing core. The MWNT-polymer microsensor array can directly connect with array data acquisition circuits, which comprise sensor interface circuitry and an analog-to-digital converter; the signal-processing core consists of memory and a microprocessor. The core executes the program, classifying the odor data received from the array data acquisition circuits. The low-power signal-processing chip was designed and fabricated using the Taiwan Semiconductor Manufacturing Company 0.18-μm 1P6M standard complementary metal oxide semiconductor process. The chip consumes only 1.05 mW of power at supply voltages of 1 and 1.8 V for the array data acquisition circuits and the signal-processing core, respectively. The miniature e-nose system, which used a microsensor array, a low-power signal-processing chip, and an embedded k-nearest-neighbor-based pattern recognition algorithm, was developed as a prototype that successfully recognized the complex odors of tincture, sorghum wine, sake, whisky, and vodka.

Three-dimensional crossbar arrays of self-rectifying Si/SiO 2/Si memristors

DOE PAGES

Li, Can; Han, Lili; Jiang, Hao; ...

2017-06-05

Memristors are promising building blocks for the next generation memory, unconventional computing systems and beyond. Currently common materials used to build memristors are not necessarily compatible with the silicon dominant complementary metal-oxide-semiconductor (CMOS) technology. Furthermore, external selector devices or circuits are usually required in order for large memristor arrays to function properly, resulting in increased circuit complexity. Here we demonstrate fully CMOS-compatible, all-silicon based and self-rectifying memristors that negate the need for external selectors in large arrays. It consists of p- and n-type doped single crystalline silicon electrodes and a thin chemically produced silicon oxide switching layer. The device exhibitsmore » repeatable resistance switching behavior with high rectifying ratio (10 5), high ON/OFF conductance ratio (10 4) and attractive retention at 300 °C. We further build a 5-layer 3-dimensional (3D) crossbar array of 100 nm memristors by stacking fluid supported silicon membranes. The CMOS compatibility and self-rectifying behavior open up opportunities for mass production of memristor arrays and 3D hybrid circuits on full-wafer scale silicon and flexible substrates without increasing circuit complexity.« less

Method for maskless lithography

DOE Office of Scientific and Technical Information (OSTI.GOV)

NONE

The present invention provides a method for maskless lithography. A plurality of individually addressable and rotatable micromirrors together comprise a two-dimensional array of micromirrors. Each micromirror in the two-dimensional array can be envisioned as an individually addressable element in the picture that comprises the circuit pattern desired. As each micromirror is addressed it rotates so as to reflect light from a light source onto a portion of the photoresist coated wafer thereby forming a pixel within the circuit pattern. By electronically addressing a two-dimensional array of these micromirrors in the proper sequence a circuit pattern that is comprised of thesemore » individual pixels can be constructed on a microchip. The reflecting surface of the micromirror is configured in such a way as to overcome coherence and diffraction effects in order to produce circuit elements having straight sides.« less

Maskless lithography

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sweatt, W.C.; Stulen, R.H.

The present invention provides a method for maskless lithography. A plurality of individually addressable and rotatable micromirrors together comprise a two-dimensional array of micromirrors. Each micromirror in the two-dimensional array can be envisioned as an individually addressable element in the picture that comprises the circuit pattern desired. As each micromirror is addressed it rotates so as to reflect light from a light source onto a portion of the photoresist coated wafer thereby forming a pixel within the circuit pattern. By electronically addressing a two-dimensional array of these micromirrors in the proper sequence a circuit pattern that is comprised of thesemore » individual pixels can be constructed on a microchip. The reflecting surface of the micromirror is configured in such a way as to overcome coherence and diffraction effects in order to produce circuit elements having straight sides. 12 figs.« less

Three-Dimensional, Inkjet-Printed Organic Transistors and Integrated Circuits with 100% Yield, High Uniformity, and Long-Term Stability.

PubMed

Kwon, Jimin; Takeda, Yasunori; Fukuda, Kenjiro; Cho, Kilwon; Tokito, Shizuo; Jung, Sungjune

2016-11-22

In this paper, we demonstrate three-dimensional (3D) integrated circuits (ICs) based on a 3D complementary organic field-effect transistor (3D-COFET). The transistor-on-transistor structure was achieved by vertically stacking a p-type OFET over an n-type OFET with a shared gate joining the two transistors, effectively halving the footprint of printed transistors. All the functional layers including organic semiconductors, source/drain/gate electrodes, and interconnection paths were fully inkjet-printed except a parylene dielectric which was deposited by chemical vapor deposition. An array of printed 3D-COFETs and their inverter logic gates comprising over 100 transistors showed 100% yield, and the uniformity and long-term stability of the device were also investigated. A full-adder circuit, the most basic computing unit, has been successfully demonstrated using nine NAND gates based on the 3D structure. The present study fulfills the essential requirements for the fabrication of organic printed complex ICs (increased transistor density, 100% yield, high uniformity, and long-term stability), and the findings can be applied to realize more complex digital/analogue ICs and intelligent devices.

Communications technology

NASA Astrophysics Data System (ADS)

Sokoloski, Martin M.

1988-09-01

The objective of the Communications Technology Program is to enable data transmission to and from low Earth orbit, geostationary orbit, and solar and deep space missions. This can be achieved by maintaining an effective, balances effort in basic, applied, and demonstration prototype communications technology through work in theory, experimentation, and components. The program consists of three major research and development discipline areas which are: microwave and millimeter wave tube components; solid state monolithic integrated circuit; and free space laser communications components and devices. The research ranges from basic research in surface physics (to study the mechanisms of surface degradation from under high temperature and voltage operating conditions which impacts cathode tube reliability and lifetime) to generic research on the dynamics of electron beams and circuits (for exploitation in various micro- and millimeter wave tube devices). Work is also performed on advanced III-V semiconductor materials and devices for use in monolithic integrated analog circuits (used in adaptive, programmable phased arrays for microwave antenna feeds and receivers) - on the use of electromagnetic theory in antennas and on technology necessary for eventual employment of lasers for free space communications for future low earth, geostationary, and deep space missions requiring high data rates with corresponding directivity and reliability.

Communications technology

NASA Technical Reports Server (NTRS)

Sokoloski, Martin M.

1988-01-01

The objective of the Communications Technology Program is to enable data transmission to and from low Earth orbit, geostationary orbit, and solar and deep space missions. This can be achieved by maintaining an effective, balances effort in basic, applied, and demonstration prototype communications technology through work in theory, experimentation, and components. The program consists of three major research and development discipline areas which are: microwave and millimeter wave tube components; solid state monolithic integrated circuit; and free space laser communications components and devices. The research ranges from basic research in surface physics (to study the mechanisms of surface degradation from under high temperature and voltage operating conditions which impacts cathode tube reliability and lifetime) to generic research on the dynamics of electron beams and circuits (for exploitation in various micro- and millimeter wave tube devices). Work is also performed on advanced III-V semiconductor materials and devices for use in monolithic integrated analog circuits (used in adaptive, programmable phased arrays for microwave antenna feeds and receivers) - on the use of electromagnetic theory in antennas and on technology necessary for eventual employment of lasers for free space communications for future low earth, geostationary, and deep space missions requiring high data rates with corresponding directivity and reliability.

Materials and noncoplanar mesh designs for integrated circuits with linear elastic responses to extreme mechanical deformations.

PubMed

Kim, Dae-Hyeong; Song, Jizhou; Choi, Won Mook; Kim, Hoon-Sik; Kim, Rak-Hwan; Liu, Zhuangjian; Huang, Yonggang Y; Hwang, Keh-Chih; Zhang, Yong-wei; Rogers, John A

2008-12-02

Electronic systems that offer elastic mechanical responses to high-strain deformations are of growing interest because of their ability to enable new biomedical devices and other applications whose requirements are impossible to satisfy with conventional wafer-based technologies or even with those that offer simple bendability. This article introduces materials and mechanical design strategies for classes of electronic circuits that offer extremely high stretchability, enabling them to accommodate even demanding configurations such as corkscrew twists with tight pitch (e.g., 90 degrees in approximately 1 cm) and linear stretching to "rubber-band" levels of strain (e.g., up to approximately 140%). The use of single crystalline silicon nanomaterials for the semiconductor provides performance in stretchable complementary metal-oxide-semiconductor (CMOS) integrated circuits approaching that of conventional devices with comparable feature sizes formed on silicon wafers. Comprehensive theoretical studies of the mechanics reveal the way in which the structural designs enable these extreme mechanical properties without fracturing the intrinsically brittle active materials or even inducing significant changes in their electrical properties. The results, as demonstrated through electrical measurements of arrays of transistors, CMOS inverters, ring oscillators, and differential amplifiers, suggest a valuable route to high-performance stretchable electronics.

An integrated semiconductor device enabling non-optical genome sequencing.

PubMed

Rothberg, Jonathan M; Hinz, Wolfgang; Rearick, Todd M; Schultz, Jonathan; Mileski, William; Davey, Mel; Leamon, John H; Johnson, Kim; Milgrew, Mark J; Edwards, Matthew; Hoon, Jeremy; Simons, Jan F; Marran, David; Myers, Jason W; Davidson, John F; Branting, Annika; Nobile, John R; Puc, Bernard P; Light, David; Clark, Travis A; Huber, Martin; Branciforte, Jeffrey T; Stoner, Isaac B; Cawley, Simon E; Lyons, Michael; Fu, Yutao; Homer, Nils; Sedova, Marina; Miao, Xin; Reed, Brian; Sabina, Jeffrey; Feierstein, Erika; Schorn, Michelle; Alanjary, Mohammad; Dimalanta, Eileen; Dressman, Devin; Kasinskas, Rachel; Sokolsky, Tanya; Fidanza, Jacqueline A; Namsaraev, Eugeni; McKernan, Kevin J; Williams, Alan; Roth, G Thomas; Bustillo, James

2011-07-20

The seminal importance of DNA sequencing to the life sciences, biotechnology and medicine has driven the search for more scalable and lower-cost solutions. Here we describe a DNA sequencing technology in which scalable, low-cost semiconductor manufacturing techniques are used to make an integrated circuit able to directly perform non-optical DNA sequencing of genomes. Sequence data are obtained by directly sensing the ions produced by template-directed DNA polymerase synthesis using all-natural nucleotides on this massively parallel semiconductor-sensing device or ion chip. The ion chip contains ion-sensitive, field-effect transistor-based sensors in perfect register with 1.2 million wells, which provide confinement and allow parallel, simultaneous detection of independent sequencing reactions. Use of the most widely used technology for constructing integrated circuits, the complementary metal-oxide semiconductor (CMOS) process, allows for low-cost, large-scale production and scaling of the device to higher densities and larger array sizes. We show the performance of the system by sequencing three bacterial genomes, its robustness and scalability by producing ion chips with up to 10 times as many sensors and sequencing a human genome.

Active-Pixel Image Sensor With Analog-To-Digital Converters

NASA Technical Reports Server (NTRS)

Fossum, Eric R.; Mendis, Sunetra K.; Pain, Bedabrata; Nixon, Robert H.

1995-01-01

Proposed single-chip integrated-circuit image sensor contains 128 x 128 array of active pixel sensors at 50-micrometer pitch. Output terminals of all pixels in each given column connected to analog-to-digital (A/D) converter located at bottom of column. Pixels scanned in semiparallel fashion, one row at time; during time allocated to scanning row, outputs of all active pixel sensors in row fed to respective A/D converters. Design of chip based on complementary metal oxide semiconductor (CMOS) technology, and individual circuit elements fabricated according to 2-micrometer CMOS design rules. Active pixel sensors designed to operate at video rate of 30 frames/second, even at low light levels. A/D scheme based on first-order Sigma-Delta modulation.

Fully integrated wearable sensor arrays for multiplexed in situ perspiration analysis

PubMed Central

Nyein, Hnin Yin Yin; Challa, Samyuktha; Chen, Kevin; Peck, Austin; Fahad, Hossain M.; Ota, Hiroki; Shiraki, Hiroshi; Kiriya, Daisuke; Lien, Der-Hsien; Brooks, George A.; Davis, Ronald W.; Javey, Ali

2016-01-01

Wearable sensor technologies are essential to the realization of personalized medicine through continuously monitoring an individual's state of health1–12. Sampling human sweat, which is rich in physiological information13, could enable non-invasive monitoring. Previously reported sweat-based and other non-invasive biosensors either can only monitor a single analyte at a time or lack on-site signal processing circuitry and sensor calibration mechanisms for accurate analysis of the physiological state14–18. Given the complexity of sweat secretion, simultaneous and multiplexed screening of target biomarkers is critical and requires full system integration to ensure the accuracy of measurements. Here we present a mechanically flexible and fully integrated (that is, no external analysis is needed) sensor array for multiplexed in situ perspiration analysis, which simultaneously and selectively measures sweat metabolites (such as glucose and lactate) and electrolytes (such as sodium and potassium ions), as well as the skin temperature (to calibrate the response of the sensors). Our work bridges the technological gap between signal transduction, conditioning (amplification and filtering), processing and wireless transmission in wearable biosensors by merging plastic-based sensors that interface with the skin with silicon integrated circuits consolidated on a flexible circuit board for complex signal processing. This application could not have been realized using either of these technologies alone owing to their respective inherent limitations. The wearable system is used to measure the detailed sweat profile of human subjects engaged in prolonged indoor and outdoor physical activities, and to make a real-time assessment of the physiological state of the subjects. This platform enables a wide range of personalized diagnostic and physiological monitoring applications. PMID:26819044

Integrated electronics for time-resolved array of single-photon avalanche diodes

NASA Astrophysics Data System (ADS)

Acconcia, G.; Crotti, M.; Rech, I.; Ghioni, M.

2013-12-01

The Time Correlated Single Photon Counting (TCSPC) technique has reached a prominent position among analytical methods employed in a great variety of fields, from medicine and biology (fluorescence spectroscopy) to telemetry (laser ranging) and communication (quantum cryptography). Nevertheless the development of TCSPC acquisition systems featuring both a high number of parallel channels and very high performance is still an open challenge: to satisfy the tight requirements set by the applications, a fully parallel acquisition system requires not only high efficiency single photon detectors but also a read-out electronics specifically designed to obtain the highest performance in conjunction with these sensors. To this aim three main blocks have been designed: a gigahertz bandwidth front-end stage to directly read the custom technology SPAD array avalanche current, a reconfigurable logic to route the detectors output signals to the acquisition chain and an array of time measurement circuits capable of recording the photon arrival times with picoseconds time resolution and a very high linearity. An innovative architecture based on these three circuits will feature a very high number of detectors to perform a truly parallel spatial or spectral analysis and a smaller number of high performance time-to-amplitude converter offering very high performance and a very high conversion frequency while limiting the area occupation and power dissipation. The routing logic will make the dynamic connection between the two arrays possible in order to guarantee that no information gets lost.

Integration and manufacture of multifunctional planar lightwave circuits

NASA Astrophysics Data System (ADS)

Lipscomb, George F.; Ticknor, Anthony J.; Stiller, Marc A.; Chen, Wenjie; Schroeter, Paul

2001-11-01

The demands of exponentially growing Internet traffic, coupled with the advent of Dense Wavelength Division Multiplexing (DWDM) fiber optic systems to meet those demands, have triggered a revolution in the telecommunications industry. This dramatic change has been built upon, and has driven, improvements in fiber optic component technology. The next generation of systems for the all optical network will require higher performance components coupled with dramatically lower costs. One approach to achieve significantly lower costs per function is to employ Planar Lightwave Circuits (PLC) to integrate multiple optical functions in a single package. PLCs are optical circuits laid out on a silicon wafer, and are made using tools and techniques developed to extremely high levels by the semi-conductor industry. In this way multiple components can be fabricated and interconnected at once, significantly reducing both the manufacturing and the packaging/assembly costs. Currently, the predominant commercial application of PLC technology is arrayed-waveguide gratings (AWG's) for multiplexing and demultiplexing multiple wavelength channels in a DWDM system. Although this is generally perceived as a single-function device, it can be performing the function of more than 100 discrete fiber-optic components and already represents a considerable degree of integration. Furthermore, programmable functions such as variable-optical attenuators (VOAs) and switches made with compatible PLC technology are now moving into commercial production. In this paper, we present results on the integration of active and passive functions together using PLC technology, e.g. a 40 channel AWG multiplexer with 40 individually controllable VOAs.

Standard Transistor Array (STAR). Volume 1: Placement technique

NASA Technical Reports Server (NTRS)

Cox, G. W.; Caroll, B. D.

1979-01-01

A large scale integration (LSI) technology, the standard transistor array uses a prefabricated understructure of transistors and a comprehensive library of digital logic cells to allow efficient fabrication of semicustom digital LSI circuits. The cell placement technique for this technology involves formation of a one dimensional cell layout and "folding" of the one dimensional placement onto the chip. It was found that, by use of various folding methods, high quality chip layouts can be achieved. Methods developed to measure of the "goodness" of the generated placements include efficient means for estimating channel usage requirements and for via counting. The placement and rating techniques were incorporated into a placement program (CAPSTAR). By means of repetitive use of the folding methods and simple placement improvement strategies, this program provides near optimum placements in a reasonable amount of time. The program was tested on several typical LSI circuits to provide performance comparisons both with respect to input parameters and with respect to the performance of other placement techniques. The results of this testing indicate that near optimum placements can be achieved by use of the procedures incurring severe time penalties.

Performance of an on-chip superconducting circulator for quantum microwave systems

NASA Astrophysics Data System (ADS)

Chapman, Benjamin; Rosenthal, Eric; Moores, Bradley; Kerckhoff, Joseph; Mates, J. A. B.; Hilton, G. C.; Vale, L. R.; Ullom, J. N.; LalumíEre, Kevin; Blais, Alexandre; Lehnert, K. W.

Microwave circulators enforce a single propagation direction for signals in an electrical network. Unfortunately, commercial circulators are bulky, lossy, and cannot be integrated close to superconducting circuits because they require strong ( kOe) magnetic fields produced by permanent magnets. Here we report on the performance of an on-chip, active circulator for superconducting microwave circuits, which uses no permanent magnets. Non-reciprocity is achieved by actively modulating reactive elements around 100 MHz, giving roughly a factor of 50 in the separation between signal and control frequencies, which facilitates filtering. The circulator's active components are dynamically tunable inductors constructed with arrays of dc-SQUIDs in series. Array inductance is tuned by varying the magnetic flux through the SQUIDs with fields weaker than 1 Oe. Although the instantaneous bandwidth of the device is narrow, the operation frequency is tunable between 4 and 8 GHz. This presentation will describe the device's theory of operation and compare its measured performance to design goals. This work is supported by the ARO under contract W911NF-14-1-0079 and the National Science Foundation under Grant Number 1125844.

Wideband analytical equivalent circuit for one-dimensional periodic stacked arrays.

PubMed

Molero, Carlos; Rodríguez-Berral, Raúl; Mesa, Francisco; Medina, Francisco; Yakovlev, Alexander B

2016-01-01

A wideband equivalent circuit is proposed for the accurate analysis of scattering from a set of stacked slit gratings illuminated by a plane wave with transverse magnetic or electric polarization that impinges normally or obliquely along one of the principal planes of the structure. The slit gratings are printed on dielectric slabs of arbitrary thickness, including the case of closely spaced gratings that interact by higher-order modes. A Π-circuit topology is obtained for a pair of coupled arrays, with fully analytical expressions for all the circuit elements. This equivalent Π circuit is employed as the basis to derive the equivalent circuit of finite stacks with any given number of gratings. Analytical expressions for the Brillouin diagram and the Bloch impedance are also obtained for infinite periodic stacks.

Solid state lighting component

DOEpatents

Yuan, Thomas; Keller, Bernd; Ibbetson, James; Tarsa, Eric; Negley, Gerald

2010-10-26

An LED component comprising an array of LED chips mounted on a planar surface of a submount with the LED chips capable of emitting light in response to an electrical signal. The LED chips comprise respective groups emitting at different colors of light, with each of the groups interconnected in a series circuit. A lens is included over the LED chips. Other embodiments can comprise thermal spreading structures included integral to the submount and arranged to dissipate heat from the LED chips.

Solid state lighting component

DOEpatents

Yuan, Thomas; Keller, Bernd; Ibbetson, James; Tarsa, Eric; Negley, Gerald

2015-07-07

An LED component comprising an array of LED chips mounted on a planar surface of a submount with the LED chips capable of emitting light in response to an electrical signal. The LED chips comprise respective groups emitting at different colors of light, with each of the groups interconnected in a series circuit. A lens is included over the LED chips. Other embodiments can comprise thermal spreading structures included integral to the submount and arranged to dissipate heat from the LED chips.

Solid state lighting component

DOEpatents

Keller, Bernd; Ibbetson, James; Tarsa, Eric; Negley, Gerald; Yuan, Thomas

2012-07-10

An LED component comprising an array of LED chips mounted on a planar surface of a submount with the LED chips capable of emitting light in response to an electrical signal. The LED chips comprise respective groups emitting at different colors of light, with each of the groups interconnected in a series circuit. A lens is included over the LED chips. Other embodiments can comprise thermal spreading structures included integral to the submount and arranged to dissipate heat from the LED chips.

International Conference on Optical Computing Held in Edinburgh, Scotland on August 22-25, 1994. Technical Digest

DTIC Science & Technology

1994-08-24

Kusuda, T. Kishimoto and Y. Mitsuhashi, Nippon Sheet Glass Co. Ltd., lbaraki, Japan. A vertical and horizontal integration technique of free-space...transparent electrode on a piece of cover glass drives the liquid crystal into the desired state. Data are transferred to the SLM over 32 parallel...shows that the shift registers and clock generation circuits function as designed. A cover- glass was fixed over the pixel array, spaced with polyimide

Light emission from silicon: Some perspectives and applications

NASA Astrophysics Data System (ADS)

Fiory, A. T.; Ravindra, N. M.

2003-10-01

Research on efficient light emission from silicon devices is moving toward leading-edge advances in components for nano-optoelectronics and related areas. A silicon laser is being eagerly sought and may be at hand soon. A key advantage is in the use of silicon-based materials and processing, thereby using high yield and low-cost fabrication techniques. Anticipated applications include an optical emitter for integrated optical circuits, logic, memory, and interconnects; electro-optic isolators; massively parallel optical interconnects and cross connects for integrated circuit chips; lightwave components; high-power discrete and array emitters; and optoelectronic nanocell arrays for detecting biological and chemical agents. The new technical approaches resolve a basic issue with native interband electro-optical emission from bulk Si, which competes with nonradiative phonon- and defect-mediated pathways for electron-hole recombination. Some of the new ways to enhance optical emission efficiency in Si diode devices rely on carrier confinement, including defect and strain engineering in the bulk material. Others use Si nanocrystallites, nanowires, and alloying with Ge and crystal strain methods to achieve the carrier confinement required to boost radiative recombination efficiency. Another approach draws on the considerable progress that has been made in high-efficiency, solar-cell design and uses the reciprocity between photo- and light-emitting diodes. Important advances are also being made with silicon-oxide materials containing optically active rare-earth impurities.

Ka-Band MMIC Subarray Technology Program (Ka-Mist)

NASA Technical Reports Server (NTRS)

Pottinger, W.

1995-01-01

Ka-band monolithic microwave integrated circuit (MMIC) arrays have been considered as having high potential for increasing the capability of space, aircraft, and land mobile communication systems in terms of scan performance, data rate, link margin, and flexibility while offering a significant reduction in size, weight, and power consumption. Insertion of MMIC technology into antenna systems, particularly at millimeter wave frequencies using low power and low noise amplifiers in closed proximity to the radiating elements, offers a significant improvement in the array transmit efficiency, receive system noise figure, and overall array reliability. Application of active array technology also leads to the use of advanced beamforming techniques that can improve beam agility, diversity, and adaptivity to complex signal environments. The objective of this program was to demonstrate the technical feasibility of the 'tile' array packaging architecture at EHF via the insertion of 1990 MMIC technology into a functional tile array or subarray module. The means test of this objective was to demonstrate and deliver to NASA a minimum of two 4 x 4 (16 radiating element) subarray modules operating in a transmit mode at 29.6 GHz. Available (1990) MMIC technology was chosen to focus the program effort on the novel interconnect schemes and packaging requirements rather than focusing on MMIC development. Major technical achievements of this program include the successful integration of two 4 x 4 subarray modules into a single antenna array. This 32 element array demonstrates a transmit EIRP of over 300 watts yielding an effective directive power gain in excess of 55 dB at 29.63 GHz. The array has been actively used as the transmit link in airborne/terrestrial mobile communication experiments accomplished via the ACTS satellite launched in August 1993.

Arrays of Position-Sensitive Virtual Frisch-Grid CdZnTe Detectors: Results From a $$4\\times 4$$ Array Prototype

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ocampo Giraldo, L. A.; Bolotnikov, A. E.; Camarda, G. S.

Position-sensitive virtual Frisch-grid (VFG) CdZnTe (CZT) detectors offer a unique capability for correcting the response nonuniformities caused by crystal defects. This allowed us to achieve high energy resolution, while using typical-grade commercial CZT crystals with relaxed requirements to their quality, thus reducing the overall cost of detectors. Another advantage of the VFG detectors is that they can be integrated into arrays and used in small compact hand-held instruments or large-area gamma cameras that will enhance detection capability for many practical applications, including nonproliferation, medical imaging, and gamma-ray astronomy. Here in this paper, we present the results from testing small arraymore » prototypes coupled with front-end application-specified integrated circuit. Each detector in the array is furnished with 5-mm-wide charge-sensing pads placed near the anode. The pads signals are converted into XY coordinates, which combined with the cathode signals (for Z coordinates) provide 3-D position information of all interaction points. The basic array consists of a number of detectors grouped into 2×2 subarrays, each having a common cathode made by connecting together the cathodes of the individual detectors. Lastly, these features can significantly improve the performance of detectors while using typical-grade low-cost CZT crystals to reduce the overall cost of the proposed instrument.« less

Arrays of Position-Sensitive Virtual Frisch-Grid CdZnTe Detectors: Results From a $$4\\times 4$$ Array Prototype

DOE PAGES

Ocampo Giraldo, L. A.; Bolotnikov, A. E.; Camarda, G. S.; ...

2017-08-22

Position-sensitive virtual Frisch-grid (VFG) CdZnTe (CZT) detectors offer a unique capability for correcting the response nonuniformities caused by crystal defects. This allowed us to achieve high energy resolution, while using typical-grade commercial CZT crystals with relaxed requirements to their quality, thus reducing the overall cost of detectors. Another advantage of the VFG detectors is that they can be integrated into arrays and used in small compact hand-held instruments or large-area gamma cameras that will enhance detection capability for many practical applications, including nonproliferation, medical imaging, and gamma-ray astronomy. Here in this paper, we present the results from testing small arraymore » prototypes coupled with front-end application-specified integrated circuit. Each detector in the array is furnished with 5-mm-wide charge-sensing pads placed near the anode. The pads signals are converted into XY coordinates, which combined with the cathode signals (for Z coordinates) provide 3-D position information of all interaction points. The basic array consists of a number of detectors grouped into 2×2 subarrays, each having a common cathode made by connecting together the cathodes of the individual detectors. Lastly, these features can significantly improve the performance of detectors while using typical-grade low-cost CZT crystals to reduce the overall cost of the proposed instrument.« less

Dual-mode intracranial catheter integrating 3D ultrasound imaging and hyperthermia for neuro-oncology: feasibility study.

PubMed

Herickhoff, Carl D; Light, Edward D; Bing, Kristin F; Mukundan, Srinivasan; Grant, Gerald A; Wolf, Patrick D; Smith, Stephen W

2009-04-01

In this study, we investigated the feasibility of an intracranial catheter transducer with dual-mode capability of real-time 3D (RT3D) imaging and ultrasound hyperthermia, for application in the visualization and treatment of tumors in the brain. Feasibility is demonstrated in two ways: first by using a 50-element linear array transducer (17 mm x 3.1 mm aperture) operating at 4.4 MHz with our Volumetrics diagnostic scanner and custom, electrical impedance-matching circuits to achieve a temperature rise over 4 degrees C in excised pork muscle, and second, by designing and constructing a 12 Fr, integrated matrix and linear-array catheter transducer prototype for combined RT3D imaging and heating capability. This dual-mode catheter incorporated 153 matrix array elements and 11 linear array elements diced on a 0.2 mm pitch, with a total aperture size of 8.4 mm x 2.3 mm. This 3.64 MHz array achieved a 3.5 degrees C in vitro temperature rise at a 2 cm focal distance in tissue-mimicking material. The dual-mode catheter prototype was compared with a Siemens 10 Fr AcuNav catheter as a gold standard in experiments assessing image quality and therapeutic potential and both probes were used in an in vivo canine brain model to image anatomical structures and color Doppler blood flow and to attempt in vivo heating.

Dual-mode Intracranial Catheter Integrating 3D Ultrasound Imaging & Hyperthermia for Neuro-oncology: Feasibility Study

PubMed Central

Herickhoff, Carl D.; Light, Edward D.; Bing, Kristin F.; Mukundan, Srinivasan; Grant, Gerald A.; Wolf, Patrick D.; Smith, Stephen W.

2010-01-01

In this study, we investigated the feasibility of an intracranial catheter transducer with dual-mode capability of real-time 3D (RT3D) imaging and ultrasound hyperthermia, for application in the visualization and treatment of tumors in the brain. Feasibility is demonstrated in two ways: first by using a 50-element linear array transducer (17 mm × 3.1 mm aperture) operating at 4.4 MHz with our Volumetrics diagnostic scanner and custom electrical impedance matching circuits to achieve a temperature rise over 4°C in excised pork muscle, and second by designing and constructing a 12 Fr, integrated matrix and linear array catheter transducer prototype for combined RT3D imaging and heating capability. This dual-mode catheter incorporated 153 matrix array elements and 11 linear array elements diced on a 0.2 mm pitch, with a total aperture size of 8.4 mm × 2.3 mm. This array achieved a 3.5°C in vitro temperature rise at a 2 cm focal distance in tissue-mimicking material. The dual-mode catheter prototype was compared with a Siemens 10 Fr AcuNav™ catheter as a gold standard in experiments assessing image quality and therapeutic potential, and both probes were used in a canine brain model to image anatomical structures and color Doppler blood flow and to attempt in vivo heating. PMID:19630251

A low-noise low-power EEG acquisition node for scalable brain-machine interfaces

NASA Astrophysics Data System (ADS)

Sullivan, Thomas J.; Deiss, Stephen R.; Cauwenberghs, Gert; Jung, Tzyy-Ping

2007-05-01

Electroencephalograph (EEG) recording systems offer a versatile, noninvasive window on the brain's spatio-temporal activity for many neuroscience and clinical applications. Our research aims at improving the spatial resolution and mobility of EEG recording by reducing the form factor, power drain and signal fanout of the EEG acquisition node in a scalable sensor array architecture. We present such a node integrated onto a dimesized circuit board that contains a sensor's complete signal processing front-end, including amplifier, filters, and analog-to-digital conversion. A daisy-chain configuration between boards with bit-serial output reduces the wiring needed. The circuit's low power consumption of 423 μW supports EEG systems with hundreds of electrodes to operate from small batteries for many hours. Coupling between the bit-serial output and the highly sensitive analog input due to dense integration of analog and digital functions on the circuit board results in a deterministic noise component in the output, larger than the intrinsic sensor and circuit noise. With software correction of this noise contribution, the system achieves an input-referred noise of 0.277 μVrms in the signal band of 1 to 100 Hz, comparable to the best medical-grade systems in use. A chain of seven nodes using EEG dry electrodes created in micro-electrical-mechanical system (MEMS) technology is demonstrated in a real-world setting.

Development of Thermal Infrared Sensor to Supplement Operational Land Imager

NASA Technical Reports Server (NTRS)

Shu, Peter; Waczynski, Augustyn; Kan, Emily; Wen, Yiting; Rosenberry, Robert

2012-01-01

The thermal infrared sensor (TIRS) is a quantum well infrared photodetector (QWIP)-based instrument intended to supplement the Operational Land Imager (OLI) for the Landsat Data Continuity Mission (LDCM). The TIRS instrument is a far-infrared imager operating in the pushbroom mode with two IR channels: 10.8 and 12 m. The focal plane will contain three 640 512 QWIP arrays mounted onto a silicon substrate. The readout integrated circuit (ROIC) addresses each pixel on the QWIP arrays and reads out the pixel value (signal). The ROIC is controlled by the focal plane electronics (FPE) by means of clock signals and bias voltage value. The means of how the FPE is designed to control and interact with the TIRS focal plane assembly (FPA) is the basis for this work. The technology developed under the FPE is for the TIRS focal plane assembly (FPA). The FPE must interact with the FPA to command and control the FPA, extract analog signals from the FPA, and then convert the analog signals to digital format and send them via a serial link (USB) to a computer. The FPE accomplishes the described functions by converting electrical power from generic power supplies to the required bias power that is needed by the FPA. The FPE also generates digital clocking signals and shifts the typical transistor-to-transistor logic (TTL) to }5 V required by the FPA. The FPE also uses an application- specific integrated circuit (ASIC) named System Image, Digitizing, Enhancing, Controlling, And Retrieving (SIDECAR) from Teledyne Corp. to generate the clocking patterns commanded by the user. The uniqueness of the FPE for TIRS lies in that the TIRS FPA has three QWIP detector arrays, and all three detector arrays must be in synchronization while in operation. This is to avoid data skewing while observing Earth flying in space. The observing scenario may be customized by uploading new control software to the SIDECAR.

RF surface receive array coils: the art of an LC circuit.

PubMed

Fujita, Hiroyuki; Zheng, Tsinghua; Yang, Xiaoyu; Finnerty, Matthew J; Handa, Shinya

2013-07-01

The radiofrequency (RF) receive array coil is a complicated device with many inductors and capacitors and serves as one of the most critical magnetic resonance imaging (MRI) electronic devices. It directly determines the achievable level of signal-to-noise ratio (SNR). Simply put, however, the RF coil is nothing but an LC circuit. The receive array coil was first proposed more than 20 years ago, evolving from a simple arrangement with a few electronic channels to a complicated system of 128 channels, enabling highly sophisticated parallel imaging, at different field strengths. This article summarizes the basic concepts pertaining to RF receive coil arrays and their associated SNR and reviews the theories behind the major components of such arrays. This includes discussions of the intrinsic SNR of a receive coil, the matching circuits, low-noise preamplifiers, coupling/decoupling amongst coils, the coupling between receive and transmit coils, decoupling via preamplifiers, and baluns. An 8-channel receive array coil on a cylindrical former serves as a useful example for demonstrating various points in the review. Copyright © 2013 Wiley Periodicals, Inc.

Department of Defense statement on the X-ray Lithography Program to the Research and Development Subcommittee of the House Armed Services Committee of 100th Congress, second session

NASA Astrophysics Data System (ADS)

Maynard, E. D., Jr.

1988-03-01

The Department has a broad and necessarily diverse program in semiconductor science and technology. The three principal goals of that effort are: Reduce the gap between commercial integrated circuit usage and its deployment in military systems, assure a healthy on-shore industrial base to support our defense needs, enhance the producibility of specialized military semiconductor products. The major effort to achieve the first of these objectives is the Very High Speed Integrated Circuits (VHSIC) Program which is nearing completion. The Microwave/millimeter wave Monolithic Integrated Circuit (MIMIC) program has just completed a study program to define the product mix needed to meet military system requirements for radar, electronic warfare, smart weapons and telecommunications. We are bringing together the system requirements of all DoD with the device fabrication and product delivery capabilities of industry in an Infrared Focal Plane Array (IRFPA) program. The goal of the Software Initiative is to enhance our warfighting capability through development of efficient software generation technology and products plus the creation of a technology infusion infrastructure to couple the technology and products to system applications. The X-Ray Lithography Program will begin to establish the industrial base which will be required to sustain U.S. leadership in the semiconductor industry for the late 1990s.

Electrode array for neural stimulation

DOEpatents

Wessendorf, Kurt O [Albuquerque, NM; Okandan, Murat [Edgewood, NM; Stein, David J [Albuquerque, NM; Yang, Pin [Albuquerque, NM; Cesarano, III, Joseph; Dellinger, Jennifer [Albuquerque, NM

2011-08-16

An electrode array for neural stimulation is disclosed which has particular applications for use in a retinal prosthesis. The electrode array can be formed as a hermetically-sealed two-part ceramic package which includes an electronic circuit such as a demultiplexer circuit encapsulated therein. A relatively large number (up to 1000 or more) of individually-addressable electrodes are provided on a curved surface of a ceramic base portion the electrode array, while a much smaller number of electrical connections are provided on a ceramic lid of the electrode array. The base and lid can be attached using a metal-to-metal seal formed by laser brazing. Electrical connections to the electrode array can be provided by a flexible ribbon cable which can also be used to secure the electrode array in place.

High-density Schottky barrier IRCCD sensors for remote sensing applications

NASA Astrophysics Data System (ADS)

Elabd, H.; Tower, J. R.; McCarthy, B. M.

1983-01-01

It is pointed out that the ambitious goals envisaged for the next generation of space-borne sensors challenge the state-of-the-art in solid-state imaging technology. Studies are being conducted with the aim to provide focal plane array technology suitable for use in future Multispectral Linear Array (MLA) earth resource instruments. An important new technology for IR-image sensors involves the use of monolithic Schottky barrier infrared charge-coupled device arrays. This technology is suitable for earth sensing applications in which moderate quantum efficiency and intermediate operating temperatures are required. This IR sensor can be fabricated by using standard integrated circuit (IC) processing techniques, and it is possible to employ commercial IC grade silicon. For this reason, it is feasible to construct Schottky barrier area and line arrays with large numbers of elements and high-density designs. A Pd2Si Schottky barrier sensor for multispectral imaging in the 1 to 3.5 micron band is under development.

Antennas for mobile satellite communications

NASA Technical Reports Server (NTRS)

Huang, John

1991-01-01

A NASA sponsored program, called the Mobile Satellite (MSAT) system, has prompted the development of several innovative antennas at L-band frequencies. In the space segment of the MSAT system, an efficient, light weight, circularly polarized microstrip array that uses linearly polarized elements was developed as a multiple beam reflector feed system. In the ground segment, a low-cost, low-profile, and very efficient microstrip Yagi array was developed as a medium-gain mechanically steered vehicle antenna. Circularly shaped microstrip patches excited at higher-order modes were also developed as low-gain vehicle antennas. A more recent effort called for the development of a 20/30 GHz mobile terminal antenna for future-generation mobile satellite communications. To combat the high insertion loss encountered at 20/30 GHz, series-fed Monolithic Microwave Integrated Circuit (MMIC) microstrip array antennas are currently being developed. These MMIC arrays may lead to the development of several small but high-gain Ka-band antennas for the Personal Access Satellite Service planned for the 2000s.

A dual frequency microstrip antenna for Ka band

NASA Technical Reports Server (NTRS)

Lee, R. Q.; Baddour, M. F.

1985-01-01

For fixed satellite communication systems at Ka band with downlink at 17.7 to 20.2 GHz and uplink at 27.5 to 30.0 GHz, the focused optics and the unfocused optics configurations with monolithic phased array feeds have often been used to provide multiple fixed and multiple scanning spot beam coverages. It appears that a dual frequency microstrip antenna capable of transmitting and receiving simultaneously is highly desirable as an array feed element. This paper describes some early efforts on the development and experimental testing of a dual frequency annular microstrip antenna. The antenna has potential application for use in conjunction with a monolithic microwave integrated circuit device as an active radiating element in a phased array of phased array feeds. The antenna is designed to resonate at TM sub 12 and TM sub 13 modes and tuned with a circumferential microstrip ring to vary the frequency ratio. Radiation characteristics at both the high and low frequencies are examined. Experimental results including radiating patterns and swept frequency measurements are presented.