DOE Office of Scientific and Technical Information (OSTI.GOV)

Britton, C.L.; Jagadish, U.; Bryan, W.L.

An Integrated Circuit (IC) readout chip with four channels arranged so as to receive input charge from the corners of the chip was designed for use with 5- to 7-mm pixel detectors. This Application Specific IC (ASIC) can be used for cold neutron imaging, for study of structural order in materials using cold neutron scattering or for particle physics experiments. The ASIC is fabricated in a 0.5-{micro}m n-well AMI process. The design of the ASIC and the test measurements made is reported. Noise measurements are also reported.

pMUT+ASIC integrated platform for wide range ultrasonic imaging

NASA Astrophysics Data System (ADS)

Tillak, J.; Saeed, N.; Khazaaleh, S.; Viegas, J.; Yoo, J.

2017-03-01

We propose an integrated platform of Aluminum Nitrate (AlN) based Piezoelectric Micromachined Ultrasonic Transducer (pMUT) phased array with Application Specific Integrated Circuit (ASIC) for medical imaging and industrial diagnosis. The ASIC provides wide driving range for frequencies between 100 kHz and 5 MHz and channelscalable, programmable application adaptive transmitting beamformer. The system supports operation in various media, including gasses, liquids and biological tissue. The scan resolution for 5 MHz operation is 68 μm in air. The beamformer covers a test volume from -30° to +30° with a step of 3° and scan depth of 10 cm. The ASIC system features low noise receiver electronics, power saving transmission circuitry, and high-voltage drive of large capacitance transducer (up to 500 pF). Integrated pMUT phased array consists of 4 channels of single-membrane ultrasonic transducer of 400 nm deflection and 20 pF feed-thru capacitance, which produce 15 Pa pressure at 500 μm distance from the surface of the transducers. The active area of the ASIC is (700×1490) μm2, which includes channel scalable TX, 8-channale low noise RX, digital back end with autonomous beamformer and power management unit. The system is battery powered with 3.3V-5V standard supply, representing a truly portable solution for ultrasonic applications. Given the CMOS-compatible fabrication process for the AlN pMUTs, dense, miniaturized arrays are possible. Furthermore the smooth surface of dielectric AlN renders optical quality MEMS surfaces for integration in miniaturized photonic + ultrasound microsystems.

SODR Memory Control Buffer Control ASIC

NASA Technical Reports Server (NTRS)

Hodson, Robert F.

1994-01-01

The Spacecraft Optical Disk Recorder (SODR) is a state of the art mass storage system for future NASA missions requiring high transmission rates and a large capacity storage system. This report covers the design and development of an SODR memory buffer control applications specific integrated circuit (ASIC). The memory buffer control ASIC has two primary functions: (1) buffering data to prevent loss of data during disk access times, (2) converting data formats from a high performance parallel interface format to a small computer systems interface format. Ten 144 p in, 50 MHz CMOS ASIC's were designed, fabricated and tested to implement the memory buffer control function.

Smart Power: New power integrated circuit technologies and their applications

NASA Astrophysics Data System (ADS)

Kuivalainen, Pekka; Pohjonen, Helena; Yli-Pietilae, Timo; Lenkkeri, Jaakko

1992-05-01

Power Integrated Circuits (PIC) is one of the most rapidly growing branches of the semiconductor technology. The PIC markets has been forecast to grow from 660 million dollars in 1990 to 1658 million dollars in 1994. It has even been forecast that at the end of the 1990's the PIC markets would correspond to the value of the whole semiconductor production in 1990. Automotive electronics will play the leading role in the development of the standard PIC's. Integrated motor drivers (36 V/4 A), smart integrated switches (60 V/30 A), solenoid drivers, integrated switch-mode power supplies and regulators are the latest standard devices of the PIC manufactures. ASIC (Application Specific Integrated Circuits) PIC solutions are needed for the same reasons as other ASIC devices: there are no proper standard devices, a company has a lot of application knowhow, which should be kept inside the company, the size of the product must be reduced, and assembly costs are wished to be reduced by decreasing the number of discrete devices. During the next few years the most probable ASIC PIC applications in Finland will be integrated solenoid and motor drivers, an integrated electronic lamp ballast circuit and various sensor interface circuits. Application of the PIC technologies to machines and actuators will strongly be increased all over the world. This means that various PIC's, either standard PIC's or full custom ASIC circuits, will appear in many products which compete with the corresponding Finnish products. Therefore the development of the PIC technologies must be followed carefully in order to immediately be able to apply the latest development in the smart power technologies and their design methods.

A Wireless Capsule Endoscope System With Low-Power Controlling and Processing ASIC.

PubMed

Xinkai Chen; Xiaoyu Zhang; Linwei Zhang; Xiaowen Li; Nan Qi; Hanjun Jiang; Zhihua Wang

2009-02-01

This paper presents the design of a wireless capsule endoscope system. The proposed system is mainly composed of a CMOS image sensor, a RF transceiver and a low-power controlling and processing application specific integrated circuit (ASIC). Several design challenges involving system power reduction, system miniaturization and wireless wake-up method are resolved by employing optimized system architecture, integration of an area and power efficient image compression module, a power management unit (PMU) and a novel wireless wake-up subsystem with zero standby current in the ASIC design. The ASIC has been fabricated in 0.18-mum CMOS technology with a die area of 3.4 mm * 3.3 mm. The digital baseband can work under a power supply down to 0.95 V with a power dissipation of 1.3 mW. The prototype capsule based on the ASIC and a data recorder has been developed. Test result shows that proposed system architecture with local image compression lead to an average of 45% energy reduction for transmitting an image frame.

An application specific integrated circuit based multi-anode microchannel array readout system

NASA Technical Reports Server (NTRS)

Smeins, Larry G.; Stechman, John M.; Cole, Edward H.

1991-01-01

Size reduction of two new multi-anode microchannel array (MAMA) readout systems is described. The systems are based on two analog and one digital application specific integrated circuits (ASICs). The new readout systems reduce volume over previous discrete designs by 80 percent while improving electrical performance on virtually every significant parameter. Emphasis is made on the packaging used to achieve the volume reduction. Surface mount technology (SMT) is combined with modular construction for the analog portion of the readout. SMT reliability concerns and the board area impact of MIL SPEC SMT components is addressed. Package selection for the analog ASIC is discussed. Future sytems will require even denser packaging and the volume reduction progression is shown.

Vehicle-based vision sensors for intelligent highway systems

NASA Astrophysics Data System (ADS)

Masaki, Ichiro

1989-09-01

This paper describes a vision system, based on ASIC (Application Specific Integrated Circuit) approach, for vehicle guidance on highways. After reviewing related work in the fields of intelligent vehicles, stereo vision, and ASIC-based approaches, the paper focuses on a stereo vision system for intelligent cruise control. The system measures the distance to the vehicle in front using trinocular triangulation. An application specific processor architecture was developed to offer low mass-production cost, real-time operation, low power consumption, and small physical size. The system was installed in the trunk of a car and evaluated successfully on highways.

Hardware and software status of QCDOC

NASA Astrophysics Data System (ADS)

Boyle, P. A.; Chen, D.; Christ, N. H.; Clark, M.; Cohen, S. D.; Cristian, C.; Dong, Z.; Gara, A.; Joó, B.; Jung, C.; Kim, C.; Levkova, L.; Liao, X.; Liu, G.; Mawhinney, R. D.; Ohta, S.; Petrov, K.; Wettig, T.; Yamaguchi, A.

2004-03-01

QCDOC is a massively parallel supercomputer whose processing nodes are based on an application-specific integrated circuit (ASIC). This ASIC was custom-designed so that crucial lattice QCD kernels achieve an overall sustained performance of 50% on machines with several 10,000 nodes. This strong scalability, together with low power consumption and a price/performance ratio of $1 per sustained MFlops, enable QCDOC to attack the most demanding lattice QCD problems. The first ASICs became available in June of 2003, and the testing performed so far has shown all systems functioning according to specification. We review the hardware and software status of QCDOC and present performance figures obtained in real hardware as well as in simulation.

VHDL Modeling and Simulation of a Digital Image Synthesizer for Countering ISAR

DTIC Science & Technology

2003-06-01

This thesis discusses VHDL modeling and simulation of a full custom Application Specific Integrated Circuit (ASIC) for a Digital Image Synthesizer...necessary for a given application . With such a digital method, it is possible for a small ship to appear as large as an aircraft carrier or any high...INTRODUCTION TO DIGITAL IMAGE SYNTHESIZER (DIS) A. BACKGROUND The Digital Image Synthesizer (DIS) is an Application Specific Integrated Circuit

DOE Office of Scientific and Technical Information (OSTI.GOV)

De Geronimo, G.; Fried, J.; Rehak, P.

We present an application-specific integrated circuit (ASIC) for high-resolution x-ray spectrometers (XRS). The ASIC reads out signals from pixelated silicon drift detectors (SDDs). The pixel does not have an integrated field effect transistor (FET); rather, readout is accomplished by wire-bonding the anodes to the inputs of the ASIC. The ASIC dissipates 32 mW, and offers 16 channels of low-noise charge amplification, high-order shaping with baseline stabilization, discrimination, a novel pile-up rejector, and peak detection with an analog memory. The readout is sparse and based on custom low-power tristatable low-voltage differential signaling (LPT-LVDS). A unit of 64 SDD pixels, read outmore » by four ASICs, covers an area of 12.8 cm{sup 2} and dissipates with the sensor biased about 15 mW/cm{sup 2}. As a tile-based system, the 64-pixel units cover a large detection area. Our preliminary measurements at -44 C show a FWHM of 145 eV at the 5.9 keV peak of a {sup 55}Fe source, and less than 80 eV on a test-pulse line at 200 eV.« less

Development of n+-in-p planar pixel quadsensor flip-chipped with FE-I4 readout ASICs

NASA Astrophysics Data System (ADS)

Unno, Y.; Kamada, S.; Yamamura, K.; Yamamoto, H.; Hanagaki, K.; Hori, R.; Ikegami, Y.; Nakamura, K.; Takubo, Y.; Takashima, R.; Tojo, J.; Kono, T.; Nagai, R.; Saito, S.; Sugibayashi, K.; Hirose, M.; Jinnouchi, O.; Sato, S.; Sawai, H.; Hara, K.; Sato, Kz.; Sato, Kj.; Iwabuchi, S.; Suzuki, J.

2017-01-01

We have developed flip-chip modules applicable to the pixel detector for the HL-LHC. New radiation-tolerant n+-in-p planar pixel sensors of a size of four FE-I4 application-specific integrated circuits (ASICs) are laid out in a 6-in wafer. Variation in readout connection for the pixels at the boundary of ASICs is implemented in the design of quadsensors. Bump bonding technology is developed for four ASICs onto one quadsensor. Both sensors and ASICs are thinned to 150 μm before bump bonding, and are held flat with vacuum chucks. Using lead-free SnAg solder bumps, we encounter deficiency with large areas of disconnected bumps after thermal stress treatment, including irradiation. Surface oxidation of the solder bumps is identified as a critical source of this deficiency after bump bonding trials, using SnAg bumps with solder flux, indium bumps, and SnAg bumps with a newly-introduced hydrogen-reflow process. With hydrogen-reflow, we establish flux-less bump bonding technology with SnAg bumps, appropriate for mass production of the flip-chip modules with thin sensors and thin ASICs.

VMM - An ASIC for Micropattern Detectors

NASA Astrophysics Data System (ADS)

Iakovidis, George

2018-02-01

The VMM is a custom Application Specific Integrated Circuit (ASIC) that can be used in a variety of charge interpolating tracking detectors. It is designed to be used with the resistive strip micromegas and sTGC detectors in the New Small Wheel upgrade of the ATLAS Muon spectrometer. The ASIC is designed at Brookhaven National Laboratory and fabricated in the 130 nm Global Foundries 8RF-DM process. It is packaged in a Ball Grid Array with outline dimensions of 21×21 mm2. It integrates 64 channels, each providing charge amplification, discrimination, neighbour logic, amplitude and timing measurements, analog-to-digital conversions, and either direct output for trigger or multiplexed readout. The front-end amplifier can operate with a wide range of input capacitances, has adjustable polarity, gain and peaking time. The VMM1 and VMM2 are the first two versions of the VMM ASIC family fabricated in 2012 and 2014 respectively. The design, tests and qualification of the VMM1, VMM2 and roadmap to VMM3 are described.

Spacecraft optical disk recorder memory buffer control

NASA Technical Reports Server (NTRS)

Hodson, Robert F.

1993-01-01

This paper discusses the research completed under the NASA-ASEE summer faculty fellowship program. The project involves development of an Application Specific Integrated Circuit (ASIC) to be used as a Memory Buffer Controller (MBC) in the Spacecraft Optical Disk System (SODR). The SODR system has demanding capacity and data rate specifications requiring specialized electronics to meet processing demands. The system is being designed to support Gigabit transfer rates with Terabit storage capability. The complete SODR system is designed to exceed the capability of all existing mass storage systems today. The ASIC development for SODR consist of developing a 144 pin CMOS device to perform format conversion and data buffering. The final simulations of the MBC were completed during this summer's NASA-ASEE fellowship along with design preparations for fabrication to be performed by an ASIC manufacturer.

A High-Performance Application Specific Integrated Circuit for Electrical and Neurochemical Traumatic Brain Injury Monitoring.

PubMed

Pagkalos, Ilias; Rogers, Michelle L; Boutelle, Martyn G; Drakakis, Emmanuel M

2018-05-22

This paper presents the first application specific integrated chip (ASIC) for the monitoring of patients who have suffered a Traumatic Brain Injury (TBI). By monitoring the neurophysiological (ECoG) and neurochemical (glucose, lactate and potassium) signals of the injured human brain tissue, it is possible to detect spreading depolarisations, which have been shown to be associated with poor TBI patient outcome. This paper describes the testing of a new 7.5 mm 2 ASIC fabricated in the commercially available AMS 0.35 μm CMOS technology. The ASIC has been designed to meet the demands of processing the injured brain tissue's ECoG signals, recorded by means of depth or brain surface electrodes, and neurochemical signals, recorded using microdialysis coupled to microfluidics-based electrochemical biosensors. The potentiostats use switchedcapacitor charge integration to record currents with 100 fA resolution, and allow automatic gain changing to track the falling sensitivity of a biosensor. This work supports the idea of a "behind the ear" wireless microplatform modality, which could enable the monitoring of currently non-monitored mobile TBI patients for the onset of secondary brain injury. ©2018 The Authors. Published by Wiley-VCH Verlag GmbH & Co. KGaA.

Inspecting Engineering Samples

NASA Image and Video Library

2017-12-08

Goddard's Ritsko Wins 2011 SAVE Award The winner of the 2011 SAVE Award is Matthew Ritsko, a Goddard financial manager. His tool lending library would track and enable sharing of expensive space-flight tools and hardware after projects no longer need them. This set of images represents the types of tools used at NASA. To read more go to: www.nasa.gov/topics/people/features/ritsko-save.html Dr. Doug Rabin (Code 671) and PI La Vida Cooper (Code 564) inspect engineering samples of the HAS-2 imager which will be tested and readout using a custom ASIC with a 16-bit ADC (analog to digital converter) and CDS (correlated double sampling) circuit designed by the Code 564 ASIC group as a part of an FY10 IRAD. The purpose of the IRAD was to develop and high resolution digitizer for Heliophysics applications such as imaging. Future goals for the collaboration include characterization testing and eventually a sounding rocket flight of the integrated system. *ASIC= Application Specific Integrated Circuit NASA/GSFC/Chris Gunn

A front end readout electronics ASIC chip for position sensitive solid state detectors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kravis, S.D.; Tuemer, T.O.; Visser, G.J.

1998-12-31

A mixed signal Application Specific Integrated Circuit (ASIC) chip for front end readout electronics of position sensitive solid state detectors has been manufactured. It is called RENA (Readout Electronics for Nuclear Applications). This chip can be used for both medical and industrial imaging of X-rays and gamma rays. The RENA chip is a monolithic integrated circuit and has 32 channels with low noise high input impedance charge sensitive amplifiers. It works in pulse counting mode with good energy resolution. It also has a self triggering output which is essential for nuclear applications when the incident radiation arrives at random. Different,more » externally selectable, operational modes that includes a sparse readout mode is available to increase data throughput. It also has externally selectable shaping (peaking) times.« less

DOE Office of Scientific and Technical Information (OSTI.GOV)

Carlson, Thomas J.; Myjak, Mitchell J.

At the request of the U.S. Army Corps of Engineers, Portland District, researchers from Pacific Northwest National Laboratory investigated the use of an application-specific integrated circuit (ASIC) to reduce the weight and volume of Juvenile Salmon Acoustic Telemetry System (JSATS) transmitters while retaining current functionality. Review of the design of current JSATS transmitters identified components that could be replaced by an ASIC while retaining the function of the current transmitter and offering opportunities to extend function if desired. ASIC design alternatives were identified that could meet transmitter weight and volume targets of 200 mg and 100 mm3. If alternatives tomore » the cylindrical batteries used in current JSATS transmitters can be identified, it could be possible to implant ASIC-based JSATS transmitters by injection rather than surgery. Using criteria for the size of fish suitable for surgical implantation of current JSATS transmitters, it was concluded that fish as small as 70 mm in length could be implanted with an ASIC-based transmitter, particularly if implantation by injection became feasible.« less

DOE Office of Scientific and Technical Information (OSTI.GOV)

DE GERONIMO,G.; CHEN, W.; FRIED, J.

We present an application specific integrated circuit (ASIC) for high-resolution x-ray spectrometers. The ASIC is designed to read out signals from a pixelated silicon drift detector (SDD). Each hexagonal pixel has an area of 15 mmz and an anode capacitance of less than 100 fF. There is no integrated Field Effect transistor (FET) in the pixel, rather, the readout is done by wirebonding the anodes to the inputs of the ASIC. The ASIC provides 14 channels of low-noise charge amplification, high-order shaping with baseline stabilization, and peak detection with analog memory. The readout is sparse and based on low voltagemore » differential signaling. An interposer provides all the interconnections required to bias and operate the system. The channel dissipates 1.6 mW. The complete 14-pixel unit covers an area of 210 mm{sup 2}, dissipates 12 mW cm{sup -2}, and can be tiled to cover an arbitrarily large detection area. We measured a preliminary resolution of 172 eV at -35 C on the 6 keV peak of a {sup 55}Fe source.« less

Low power signal processing electronics for wearable medical devices.

PubMed

Casson, Alexander J; Rodriguez-Villegas, Esther

2010-01-01

Custom designed microchips, known as Application Specific Integrated Circuits (ASICs), offer the lowest possible power consumption electronics. However, this comes at the cost of a longer, more complex and more costly design process compared to one using generic, off-the-shelf components. Nevertheless, their use is essential in future truly wearable medical devices that must operate for long periods of time from physically small, energy limited batteries. This presentation will demonstrate the state-of-the-art in ASIC technology for providing online signal processing for use in these wearable medical devices.

Improved On-Chip Measurement of Delay in an FPGA or ASIC

NASA Technical Reports Server (NTRS)

Chen, Yuan; Burke, Gary; Sheldon, Douglas

2007-01-01

An improved design has been devised for on-chip-circuitry for measuring the delay through a chain of combinational logic elements in a field-programmable gate array (FPGA) or application-specific integrated circuit (ASIC). In the improved design, the delay chain does not include input and output buffers and is not configured as an oscillator. Instead, the delay chain is made part of the signal chain of an on-chip pulse generator. The duration of the pulse is measured on-chip and taken to equal the delay.

Multi-petascale highly efficient parallel supercomputer

DOE Office of Scientific and Technical Information (OSTI.GOV)

Asaad, Sameh; Bellofatto, Ralph E.; Blocksome, Michael A.

A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaflop-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC). The ASIC nodes are interconnected by a five dimensional torus network that optimally maximize the throughput of packet communications between nodes and minimize latency. The network implements collective network and a global asynchronous network that provides global barrier and notification functions. Integrated in the node design include a list-based prefetcher. The memory system implements transaction memory, thread level speculation, and multiversioning cache that improves soft error rate at the same time andmore » supports DMA functionality allowing for parallel processing message-passing.« less

An array of virtual Frisch-grid CdZnTe detectors and a front-end application-specific integrated circuit for large-area position-sensitive gamma-ray cameras.

PubMed

Bolotnikov, A E; Ackley, K; Camarda, G S; Cherches, C; Cui, Y; De Geronimo, G; Fried, J; Hodges, D; Hossain, A; Lee, W; Mahler, G; Maritato, M; Petryk, M; Roy, U; Salwen, C; Vernon, E; Yang, G; James, R B

2015-07-01

We developed a robust and low-cost array of virtual Frisch-grid CdZnTe detectors coupled to a front-end readout application-specific integrated circuit (ASIC) for spectroscopy and imaging of gamma rays. The array operates as a self-reliant detector module. It is comprised of 36 close-packed 6 × 6 × 15 mm(3) detectors grouped into 3 × 3 sub-arrays of 2 × 2 detectors with the common cathodes. The front-end analog ASIC accommodates up to 36 anode and 9 cathode inputs. Several detector modules can be integrated into a single- or multi-layer unit operating as a Compton or a coded-aperture camera. We present the results from testing two fully assembled modules and readout electronics. The further enhancement of the arrays' performance and reduction of their cost are possible by using position-sensitive virtual Frisch-grid detectors, which allow for accurate corrections of the response of material non-uniformities caused by crystal defects.

Development of a compact radiation-hardened low-noise front-end readout ASIC for CZT-based hard X-ray imager

NASA Astrophysics Data System (ADS)

Gao, W.; Gan, B.; Li, X.; Wei, T.; Gao, D.; Hu, Y.

2015-04-01

In this paper, we present the development and performances of a radiation-hardened front-end readout application-specific integrated circuit (ASIC) dedicated to CZT detectors for a hard X-ray imager in space applications. The readout channel consists of a charge sensitive amplifier (CSA), a CR-RC shaper, a fast shaper, a discriminator and a driving buffer. With the additional digital filtering, the readout channel can achieve very low noise performances and low power dissipation. An eight-channel prototype ASIC is designed and fabricated in 0.35 μm CMOS process. The energy range of the detected X-rays is evaluated as 1.45 keV to 281 keV. The gain is larger than 100 mV/fC. The equivalent noise charge (ENC) of the ASIC is 53 e- at zero farad plus 10 e- per picofarad. The power dissipation is less than 4.4 mW/channel. Through the measurement with a CZT detector, the energy resolution is less than 3.45 keV (FWHM) under the irradiation of the radioactive source 241Am. The radiation effect experiments indicate that the proposed ASIC can resist the total ionization dose (TID) irradiation of higher than 200 krad (Si).

An integrated signal conditioner for high-frequency inductive position sensors

NASA Astrophysics Data System (ADS)

Rahal, Mohamad; Demosthenous, Andreas

2010-01-01

This paper describes the design, implementation and evaluation of a signal conditioner application-specific integrated circuit (ASIC) for high-frequency inductive non-contact position sensors. These sensors employ a radio frequency technology based on an antenna planar arrangement and a resonant target, have a high inherent resolution (0.1% of antenna length) and can measure target position over a wide distance range (<0.1 mm to >10 m). However, due to the relatively high-frequency excitation (1 MHz typically) and to the specific layouts of these sensors, there is unwanted capacitive coupling between the transmitter and receiver coils; this type of distortion reduces linearity and resolution. The ASIC, which is the first generation of its kind for this type of sensor, employs a differential mixer topology which suppresses the capacitive coupling offsets. The system architecture and circuit details are presented. The ASIC was fabricated in a 0.6 µm high-voltage CMOS technology occupying an area of 8 mm2. It dissipates about 30 mA from a 24 V power supply. The ASIC was tested with a high-frequency inductive position sensor (with an antenna length of 10.8 cm). The measured input-referred offset due to transmitter crosstalk is on average about 22 µV over a wide phase difference variation (-99° to +117°) between the transmitter and demodulating signals.

A Thermally Powered ISFET Array for On-Body pH Measurement.

PubMed

Douthwaite, Matthew; Koutsos, Ermis; Yates, David C; Mitcheson, Paul D; Georgiou, Pantelis

2017-12-01

Recent advances in electronics and electrochemical sensors have led to an emerging class of next generation wearables, detecting analytes in biofluids such as perspiration. Most of these devices utilize ion-selective electrodes (ISEs) as a detection method; however, ion-sensitive field-effect transistors (ISFETs) offer a solution with improved integration and a low power consumption. This work presents a wearable, thermoelectrically powered system composed of an application-specific integrated circuit (ASIC), two commercial power management integrated circuits and a network of commercial thermoelectric generators (TEGs). The ASIC is fabricated in 0.35 m CMOS and contains an ISFET array designed to read pH as a current, a processing module which averages the signal to reduce noise and encodes it into a frequency, and a transmitter. The output frequency has a measured sensitivity of 6 to 8 kHz/pH for a pH range of 7-5. It is shown that the sensing array and processing module has a power consumption 6 W and, therefore, can be entirely powered by body heat using a TEG. Array averaging is shown to reduce noise at these low power levels to 104 V (input referred integrated noise), reducing the minimum detectable limit of the ASIC to 0.008 pH units. The work forms the foundation and proves the feasibility of battery-less, on-body electrochemical for perspiration analysis in sports science and healthcare applications.

A wireless capsule system with ASIC for monitoring the physiological signals of the human gastrointestinal tract.

PubMed

Xu, Fei; Yan, Guozheng; Zhao, Kai; Lu, Li; Gao, Jinyang; Liu, Gang

2014-12-01

This paper presents the design of a wireless capsule system for monitoring the physiological signals of the human gastrointestinal (GI) tract. The primary components of the system include a wireless capsule, a portable data recorder, and a workstation. Temperature, pH, and pressure sensors; an RF transceiver; a controlling and processing application specific integrated circuit (ASIC); and batteries were applied in a wireless capsule. Decreasing capsule size, improving sensor precision, and reducing power needs were the primary challenges; these were resolved by employing micro sensors, optimized architecture, and an ASIC design that include power management, clock management, a programmable gain amplifier (PGA), an A/D converter (ADC), and a serial peripheral interface (SPI) communication unit. The ASIC has been fabricated in 0.18- μm CMOS technology with a die area of 5.0 mm × 5.0 mm. The wireless capsule integrating the ASIC controller measures Φ 11 mm × 26 mm. A data recorder and a workstation were developed, and 20 cases of human experiments were conducted in hospitals. Preprocessing in the workstation can significantly improve the quality of the data, and 76 original features were determined by mathematical statistics. Based on the 13 optimal features achieved in the evaluation of the features, the clustering algorithm can identify the patients who lack GI motility with a recognition rate reaching 83.3%.

SiGe Integrated Circuit Developments for SQUID/TES Readout

NASA Astrophysics Data System (ADS)

Prêle, D.; Voisin, F.; Beillimaz, C.; Chen, S.; Piat, M.; Goldwurm, A.; Laurent, P.

2018-03-01

SiGe integrated circuits dedicated to the readout of superconducting bolometer arrays for astrophysics have been developed since more than 10 years at APC. Whether for Cosmic Microwave Background (CMB) observations with the QUBIC ground-based experiment (Aumont et al. in astro-ph.IM, 2016. arXiv:1609.04372) or for the Hot and Energetic Universe science theme with the X-IFU instrument on-board of the ATHENA space mission (Barret et al. in SPIE 9905, space telescopes & instrumentation 2016: UV to γ Ray, 2016. https://doi.org/10.1117/12.2232432), several kinds of Transition Edge Sensor (TES) (Irwin and Hilton, in ENSS (ed) Cryogenic particle detection, Springer, Berlin, 2005) arrays have been investigated. To readout such superconducting detector arrays, we use time or frequency domain multiplexers (TDM, FDM) (Prêle in JINST 10:C08015, 2016. https://doi.org/10.1088/1748-0221/10/08/C08015) with Superconducting QUantum Interference Devices (SQUID). In addition to the SQUID devices, low-noise biasing and amplification are needed. These last functions can be obtained by using BiCMOS SiGe technology in an Application Specific Integrated Circuit (ASIC). ASIC technology allows integration of highly optimised circuits specifically designed for a unique application. Moreover, we could reach very low-noise and wide band amplification using SiGe bipolar transistor either at room or cryogenic temperatures (Cressler in J Phys IV 04(C6):C6-101, 1994. https://doi.org/10.1051/jp4:1994616). This paper discusses the use of SiGe integrated circuits for SQUID/TES readout and gives an update of the last developments dedicated to the QUBIC telescope and to the X-IFU instrument. Both ASIC called SQmux128 and AwaXe are described showing the interest of such SiGe technology for SQUID multiplexer controls.

Possibilities for mixed mode chip manufacturing in EUROPRACTICE

NASA Astrophysics Data System (ADS)

Das, C.

1997-02-01

EUROPRACTICE is an EC initiative under the ESPRIT programme which aims to stimulate the wider exploitation of state-of-the-art microelectronics technologies by European industry and to enhance European industrial competitiveness in the global market-place. Through EUROPRACTICE, the EC has created a range of Basic Services that offer users a cost-effective and flexible means of accessing three main microelectronics-based technologies: Application Specific Integrated Circuit (ASICs), Multi-Chip Modules (MCMs) and Microsystems. EUROPRACTICE Basic Services reduce the cost and risk for companies wishing to begin using these technologies. EUROPRACTICE offers a fully supported, low cost route for companies to design and fabricate ASICs for their individual applications. Low cost is achieved by consolidating designs from many users onto a single semiconductor wafer (MPW: Multi Project Wafer). The EUROPRACTICE IC Manufacturing Service (ICMS) offers a broad range of fabrication technologies including CMOS, BiCMOS and GaAs. The Service extends from enabling users to produce prototype ASICs for testing and evaluation, through to low-volume production runs.

Driver ASIC Environmental Testing and Performance Optimization for SpaceBased Active Mirrors

NASA Astrophysics Data System (ADS)

Mejia Prada, Camilo

Direct imaging of Earth-like planets requires techniques for light suppression, such as coronagraphs or nulling interferometers, in which deformable mirrors (DM) are a principal component. On ground-based systems, DMs are used to correct for turbulence in the Earth’s atmosphere in addition to static aberrations in the optics. For space-based observations, DMs are used to correct for static and quasi- static aberrations in the optical train. State-of-the-art, high-actuator count deformable mirrors suffer from external heavy and bulky electronics in which electrical connections are made through thousands of wires. We are instead developing Application Specific Integrated Circuits (ASICs) capable of direct integration with the DM in a single small package. This integrated ASIC-DM is ideal for space missions, where it offers significant reduction in mass, power and complexity, and performance compatible with high-contrast observations of exoplanets. We have successfully prototyped and tested a 32x32 format Switch-Mode (SM) ASIC which consumes only 2mW static power (total, not per-actuator). A number of constraints were imposed on key parameters of this ASIC design, including sub-picoamp levels of leakage across turned-off switches and from switch-to-substrate, control resolution of 0.04 mV, satisfactory rise/fall times, and a near-zero on-chip crosstalk over a useful range of operating temperatures. This driver ASIC technology is currently at TRL 4. This Supporting Technology proposal will further develop the ASIC technology to TRL 5 by carrying on environmental tests and further optimizing performance, with the end goal of making ASICs suitable for space-based deployment. The effort will be led by JPL, which has considerable expertise with DMs used in highcontrast imaging systems for exoplanet missions and in adaptive optic systems, and in design of DM driver electronics. Microscale, which developed the prototype of the ASICDM, will continue its development. We propose a three-part program to advance the device maturity. The effort will cover (1) radiation hardness, (2) thermal-vacuum environment tests, and (3) parameter performance optimization. We expect to implement the results in an optimized ASIC design for NASA's space applications, expanding the current state-of-the-art into radiation-hardened electronics robust enough for a space environment. This effort will fill technology gaps listed in the Exoplanet Exploration Program Technology Plan 2017 : “The challenge is believed to not be the mosaicking of 48×48 devices or 32×32 devices (to reach 128×128) but rather dealing with the enormous number of interconnects and their electronics.”. After the close of this effort, continued ASIC development is of course planned, leading to further improvement in parameters.

JPRS Report: Science & Technology - Europe.

DTIC Science & Technology

1992-12-21

in the aero- nautical industry—through the use of hybrids, ASICs [application-specific integrated circuits ], etc. "The system will also have an... Module ], the cylinder-shaped pressurized cabin that can be firmly attached to the international space station), which is to be launched in 1999...34] [Excerpt] Two hundred scientists and $1 billion to design the chip of the future, an integrated circuit (IC) giving microcomputers power

An Electronic-Nose Sensor Node Based on a Polymer-Coated Surface Acoustic Wave Array for Wireless Sensor Network Applications

PubMed Central

Tang, Kea-Tiong; Li, Cheng-Han; Chiu, Shih-Wen

2011-01-01

This study developed an electronic-nose sensor node based on a polymer-coated surface acoustic wave (SAW) sensor array. The sensor node comprised an SAW sensor array, a frequency readout circuit, and an Octopus II wireless module. The sensor array was fabricated on a large K2 128° YX LiNbO3 sensing substrate. On the surface of this substrate, an interdigital transducer (IDT) was produced with a Cr/Au film as its metallic structure. A mixed-mode frequency readout application specific integrated circuit (ASIC) was fabricated using a TSMC 0.18 μm process. The ASIC output was connected to a wireless module to transmit sensor data to a base station for data storage and analysis. This sensor node is applicable for wireless sensor network (WSN) applications. PMID:22163865

An electronic-nose sensor node based on a polymer-coated surface acoustic wave array for wireless sensor network applications.

PubMed

Tang, Kea-Tiong; Li, Cheng-Han; Chiu, Shih-Wen

2011-01-01

This study developed an electronic-nose sensor node based on a polymer-coated surface acoustic wave (SAW) sensor array. The sensor node comprised an SAW sensor array, a frequency readout circuit, and an Octopus II wireless module. The sensor array was fabricated on a large K(2) 128° YX LiNbO3 sensing substrate. On the surface of this substrate, an interdigital transducer (IDT) was produced with a Cr/Au film as its metallic structure. A mixed-mode frequency readout application specific integrated circuit (ASIC) was fabricated using a TSMC 0.18 μm process. The ASIC output was connected to a wireless module to transmit sensor data to a base station for data storage and analysis. This sensor node is applicable for wireless sensor network (WSN) applications.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Heffner, M.; Riot, V.; Fabris, L.

Medium to large channel count detectors are usually faced with a few unattractive options for data acquisition (DAQ). Small to medium sized TPC experiments, for example, can be too small to justify the high expense and long development time of application specific integrated circuit (ASIC) development. In some cases an experiment can piggy-back on a larger experiment and the associated ASIC development, but this puts the time line of development out of the hands of the smaller experiment. Another option is to run perhaps thousands of cables to rack mounted equipment, which is clearly undesirable. The development of commercial high-speedmore » high-density FPGAs and ADCs combined with the small discrete components and robotic assembly open a new option that scales to tens of thousands of channels and is only slightly larger than ASICs using off-the-shelf components.« less

Single Event Effects Test Results for Advanced Field Programmable Gate Arrays

NASA Technical Reports Server (NTRS)

Allen, Gregory R.; Swift, Gary M.

2006-01-01

Reconfigurable Field Programmable Gate Arrays (FPGAs) from Altera and Actel and an FPGA-based quick-turnApplication Specific Integrated Circuit (ASIC) from Altera were subjected to single-event testing using heavy ions. Both Altera devices (Stratix II and HardCopy II) exhibited a low latchup threshold (below an LET of 3 MeV-cm2/mg) and thus are not recommended for applications in the space radiation environment. The flash-based Actel ProASIC Plus device did not exhibit latchup to an effective LET of 75 MeV-cm2/mg at room temperature. In addition, these tests did not show flash cell charge loss (upset) or retention damage. Upset characterization of the design-level flip-flops yielded an LET threshold below 10 MeV-cm2/mg and a high LET cross section of about lxlO-6 cm2/bit for storing ones and about lxl0-7 cm2/bit for storing zeros . Thus, the ProASIC device may be suitable for critical flight applications with appropriate triple modular redundancy mitigation techniques.

A High-Performance Deformable Mirror with Integrated Driver ASIC for Space Based Active Optics

NASA Astrophysics Data System (ADS)

Shelton, Chris

Direct imaging of exoplanets is key to fully understanding these systems through spectroscopy and astrometry. The primary impediment to direct imaging of exoplanets is the extremely high brightness ratio between the planet and its parent star. Direct imaging requires a technique for contrast suppression, which include coronagraphs, and nulling interferometers. Deformable mirrors (DMs) are essential to both of these techniques. With space missions in mind, Microscale is developing a novel DM with direct integration of DM and its electronic control functions in a single small envelope. The Application Specific Integrated Circuit (ASIC) is key to the shrinking of the electronic control functions to a size compatible with direct integration with the DM. Through a NASA SBIR project, Microscale, with JPL oversight, has successfully demonstrated a unique deformable mirror (DM) driver ASIC prototype based on an ultra-low power switch architecture. Microscale calls this the Switch-Mode ASIC, or SM-ASIC, and has characterized it for a key set of performance parameters, and has tested its operation with a variety of actuator loads, such as piezo stack and unimorph, and over a wide temperature range. These tests show the SM-ASIC's capability of supporting active optics in correcting aberrations of a telescope in space. Microscale has also developed DMs to go with the SM-ASIC driver. The latest DM version produced uses small piezo stack elements in an 8x8 array, bonded to a novel silicon facesheet structure fabricated monolithically into a polished mirror on one side and mechanical linkage posts that connect to the piezoelectric stack actuators on the other. In this Supporting Technology proposal we propose to further develop the ASIC-DM and have assembled a very capable team to do so. It will be led by JPL, which has considerable expertise with DMs used in Adaptive Optics systems, with high-contrast imaging systems for exoplanet missions, and with designing DM driver electronics. On its part Microscale will continue its design and fabrication of the ASIC-DM combination. Both the SM-ASIC and the DM are currently at a Technology Readiness Level (TRL) of 3; the major goal of the proposed effort is to raise the TRL of the combined system to 4 by scaling up the array formats and by testing, characterizing, and operating multiple generations of the integrated DM-ASIC systems in a laboratory environment. We propose a three year effort, with these tasks: Year 1: Optimize the influence function of an 8x8 DM for active / adaptive optics, by modeling and fabricating different geometric parameters of the facesheet, with its mechanical linkage posts. Fabricate an SM-ASIC and an 8x8 piezo stack DM, and evaluate their performance. Characterize and optimize the integration processes to achieve a driver/DM combination that can support high contrast imaging of exoplanets. Test the control resolution of the ASIC in driving actuators using a commercial interferometer, to ensure the ASIC can command the piezo stack actuator to nanometer levels. The goal, by year three, is control to a small number of picometers; 10-20 pm (surface) may be a practical goal, while 5 pm is the ultimate goal. Year 2: Fabricate 16x16 piezo stack DMs and matching driver ASICS, and repeat Year 1 tasks with the larger format devices. Year 3: Fabricate 32x32 DMs and SM-ASICs, and repeat Year 1 tasks with the larger format devices. Fabricate versions of the 32x32 devices that can be formed into a 2x2 array, to make a composite 64x64 DM/driver. Fabricate such a composite 64x64 DM/ASIC and evaluate its performance.

Development of a 32-channel ASIC for an X-ray APD detector onboard the ISS

NASA Astrophysics Data System (ADS)

Arimoto, Makoto; Harita, Shohei; Sugita, Satoshi; Yatsu, Yoichi; Kawai, Nobuyuki; Ikeda, Hirokazu; Tomida, Hiroshi; Isobe, Naoki; Ueno, Shiro; Mihara, Tatehiro; Serino, Motoko; Kohmura, Takayoshi; Sakamoto, Takanori; Yoshida, Atsumasa; Tsunemi, Hiroshi; Hatori, Satoshi; Kume, Kyo; Hasegawa, Takashi

2018-02-01

We report on the design and performance of a mixed-signal application specific integrated circuit (ASIC) dedicated to avalanche photodiodes (APDs) in order to detect hard X-ray emissions in a wide energy band onboard the International Space Station. To realize wide-band detection from 20 keV to 1 MeV, we use Ce:GAGG scintillators, each coupled to an APD, with low-noise front-end electronics capable of achieving a minimum energy detection threshold of 20 keV. The developed ASIC has the ability to read out 32-channel APD signals using 0.35 μm CMOS technology, and an analog amplifier at the input stage is designed to suppress the capacitive noise primarily arising from the large detector capacitance of the APDs. The ASIC achieves a performance of 2099 e- + 1.5 e-/pF at root mean square (RMS) with a wide 300 fC dynamic range. Coupling a reverse-type APD with a Ce:GAGG scintillator, we obtain an energy resolution of 6.7% (FWHM) at 662 keV and a minimum detectable energy of 20 keV at room temperature (20 °C). Furthermore, we examine the radiation tolerance for space applications by using a 90 MeV proton beam, confirming that the ASIC is free of single-event effects and can operate properly without serious degradation in analog and digital processing.

Radiation-Hardened Solid-State Drive

NASA Technical Reports Server (NTRS)

Sheldon, Douglas J.

2010-01-01

A method is provided for a radiationhardened (rad-hard) solid-state drive for space mission memory applications by combining rad-hard and commercial off-the-shelf (COTS) non-volatile memories (NVMs) into a hybrid architecture. The architecture is controlled by a rad-hard ASIC (application specific integrated circuit) or a FPGA (field programmable gate array). Specific error handling and data management protocols are developed for use in a rad-hard environment. The rad-hard memories are smaller in overall memory density, but are used to control and manage radiation-induced errors in the main, and much larger density, non-rad-hard COTS memory devices. Small amounts of rad-hard memory are used as error buffers and temporary caches for radiation-induced errors in the large COTS memories. The rad-hard ASIC/FPGA implements a variety of error-handling protocols to manage these radiation-induced errors. The large COTS memory is triplicated for protection, and CRC-based counters are calculated for sub-areas in each COTS NVM array. These counters are stored in the rad-hard non-volatile memory. Through monitoring, rewriting, regeneration, triplication, and long-term storage, radiation-induced errors in the large NV memory are managed. The rad-hard ASIC/FPGA also interfaces with the external computer buses.

An Analysis of Heavy-Ion Single Event Effects for a Variety of Finite State-Machine Mitigation Strategies

NASA Technical Reports Server (NTRS)

Berg, Melanie D.; Label, Kenneth A.; Kim, Hak; Phan, Anthony; Seidleck, Christina

2014-01-01

Finite state-machines (FSMs) are used to control operational flow in application specific integrated circuits (ASICs) and field programmable gate array (FPGA) devices. Because of their ease of interpretation, FSMs simplify the design and verification process and consequently are significant components in a synchronous design.

A demonstration of CMOS VLSI circuit prototyping in support of the site facility using the 1.2 micron standard cell library developed by National Security Agency

NASA Technical Reports Server (NTRS)

Smith, Edwyn D.

1991-01-01

Two silicon CMOS application specific integrated circuits (ASICs), a data generation chip, and a data checker chip were designed. The conversion of the data generator circuitry into a pair of CMOS ASIC chips using the 1.2 micron standard cell library is documented. The logic design of the data checker is discussed. The functions of the control circuitry is described. An accurate estimate of timing relationships is essential to make sure that the logic design performs correctly under practical conditions. Timing and delay information are examined.

A Compact, Flexible, High Channel Count DAQ Built From Off-the-Shelf Components

DOE PAGES

Heffner, M.; Riot, V.; Fabris, L.

2013-06-01

Medium to large channel count detectors are usually faced with a few unattractive options for data acquisition (DAQ). Small to medium sized TPC experiments, for example, can be too small to justify the high expense and long development time of application specific integrated circuit (ASIC) development. In some cases an experiment can piggy-back on a larger experiment and the associated ASIC development, but this puts the time line of development out of the hands of the smaller experiment. Another option is to run perhaps thousands of cables to rack mounted equipment, which is clearly undesirable. The development of commercial high-speedmore » high-density FPGAs and ADCs combined with the small discrete components and robotic assembly open a new option that scales to tens of thousands of channels and is only slightly larger than ASICs using off-the-shelf components.« less

Development of slew-rate-limited time-over-threshold (ToT) ASIC for a multi-channel silicon-based ion detector

NASA Astrophysics Data System (ADS)

Uenomachi, M.; Orita, T.; Shimazoe, K.; Takahashi, H.; Ikeda, H.; Tsujita, K.; Sekiba, D.

2018-01-01

High-resolution Elastic Recoil Detection Analysis (HERDA), which consists of a 90o sector magnetic spectrometer and a position-sensitive detector (PSD), is a method of quantitative hydrogen analysis. In order to increase sensitivity, a HERDA system using a multi-channel silicon-based ion detector has been developed. Here, as a parallel and fast readout circuit from a multi-channel silicon-based ion detector, a slew-rate-limited time-over-threshold (ToT) application-specific integrated circuit (ASIC) was designed, and a new slew-rate-limited ToT method is proposed. The designed ASIC has 48 channels and each channel consists of a preamplifier, a slew-rate-limited shaping amplifier, which makes ToT response linear, and a comparator. The measured equivalent noise charges (ENCs) of the preamplifier, the shaper, and the ToT on no detector capacitance were 253±21, 343±46, and 560±56 electrons RMS, respectively. The spectra from a 241Am source measured using a slew-rate-limited ToT ASIC are also reported.

Controller and data acquisition system for SIDECAR ASIC driven HAWAII detectors

NASA Astrophysics Data System (ADS)

Ramaprakash, Anamparambu; Burse, Mahesh; Chordia, Pravin; Chillal, Kalpesh; Kohok, Abhay; Mestry, Vilas; Punnadi, Sujit; Sinha, Sakya

2010-07-01

SIDECAR is an Application Specific Integrated Circuit (ASIC), which can be used for control and data acquisition from near-IR HAWAII detectors offered by Teledyne Imaging Sensors (TIS), USA. The standard interfaces provided by Teledyne are COM API and socket servers running under MS Windows platform. These interfaces communicate to the ASIC (and the detector) through an intermediate card called JWST ASIC Drive Electronics (JADE2). As part of an ongoing programme of several years, for developing astronomical focal plane array (CCDs, CMOS and Hybrid) controllers and data acquisition systems (CDAQs), IUCAA is currently developing the next generation controllers employing Virtex-5 family FPGA devices. We present here the capabilities which are built into these new CDAQs for handling HAWAII detectors. In our system, the computer which hosts the application programme, user interface and device drivers runs on a Linux platform. It communicates through a hot-pluggable USB interface (with an optional optical fibre extender) to the FPGA-based card which replaces the JADE2. The FPGA board in turn, controls the SIDECAR ASIC and through it a HAWAII-2RG detector, both of which are located in a cryogenic test Dewar set up which is liquid nitrogen cooled. The system can acquire data over 1, 4, or 32 readout channels, with or without binning, at different speeds, can define sub-regions for readout, offers various readout schemes like Fowler sampling, up-theramp etc. In this paper, we present the performance results obtained from a prototype system.

Defense Industrial Base Assessment: U.S. Integrated Circuit Design and Fabrication Capability

DTIC Science & Technology

2009-05-01

in the U.S for the period 2003-2006, with projections to 2011.6 The resulting draft OTE survey was field tested for accuracy and usability with a...custom application specific integrated circuits (ASICs) to field programmable gate arrays (FPGAs). Companies of all sizes can manufacture these IC...able to design one-time Electronically Programmable Gate Arrays (EPGAs) while nine are able to design Field Programmable Gate Arrays (FPGAs). Eight

ePix: a class of architectures for second generation LCLS cameras

DOE PAGES

Dragone, A.; Caragiulo, P.; Markovic, B.; ...

2014-03-31

ePix is a novel class of ASIC architectures, based on a common platform, optimized to build modular scalable detectors for LCLS. The platform architecture is composed of a random access analog matrix of pixel with global shutter, fast parallel column readout, and dedicated sigma-delta analog-to-digital converters per column. It also implements a dedicated control interface and all the required support electronics to perform configuration, calibration and readout of the matrix. Based on this platform a class of front-end ASICs and several camera modules, meeting different requirements, can be developed by designing specific pixel architectures. This approach reduces development time andmore » expands the possibility of integration of detector modules with different size, shape or functionality in the same camera. The ePix platform is currently under development together with the first two integrating pixel architectures: ePix100 dedicated to ultra low noise applications and ePix10k for high dynamic range applications.« less

Stability of the Baseline Holder in Readout Circuits For Radiation Detectors

PubMed Central

Chen, Y.; Cui, Y.; O’Connor, P.; Seo, Y.; Camarda, G. S.; Hossain, A.; Roy, U.; Yang, G.; James, R. B.

2016-01-01

Baseline holder (BLH) circuits are used widely to stabilize the analog output of application-specific integrated circuits (ASICs) for high-count-rate applications. The careful design of BLH circuits is vital to the overall stability of the analog-signal-processing chain in ASICs. Recently, we observed self-triggered fluctuations in an ASIC in which the shaping circuits have a BLH circuit in the feedback loop. In fact, further investigations showed that methods of enhancing small-signal stabilities cause an even worse situation. To resolve this problem, we used large-signal analyses to study the circuit’s stability. We found that a relatively small gain for the error amplifier and a small current in the non-linear stage of the BLH are required to enhance stability in large-signal analysis, which will compromise the properties of the BLH. These findings were verified by SPICE simulations. In this paper, we present our detailed analysis of the BLH circuits, and propose an improved version of them that have only minimal self-triggered fluctuations. We summarize the design considerations both for the stability and the properties of the BLH circuits. PMID:27182081

Small Microprocessor for ASIC or FPGA Implementation

NASA Technical Reports Server (NTRS)

Kleyner, Igor; Katz, Richard; Blair-Smith, Hugh

2011-01-01

A small microprocessor, suitable for use in applications in which high reliability is required, was designed to be implemented in either an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA). The design is based on commercial microprocessor architecture, making it possible to use available software development tools and thereby to implement the microprocessor at relatively low cost. The design features enhancements, including trapping during execution of illegal instructions. The internal structure of the design yields relatively high performance, with a significant decrease, relative to other microprocessors that perform the same functions, in the number of microcycles needed to execute macroinstructions. The problem meant to be solved in designing this microprocessor was to provide a modest level of computational capability in a general-purpose processor while adding as little as possible to the power demand, size, and weight of a system into which the microprocessor would be incorporated. As designed, this microprocessor consumes very little power and occupies only a small portion of a typical modern ASIC or FPGA. The microprocessor operates at a rate of about 4 million instructions per second with clock frequency of 20 MHz.

A One Chip Hardened Solution for High Speed SpaceWire System Implementations. Session: Components

NASA Technical Reports Server (NTRS)

Marshall, Joseph R.; Berger, Richard W.; Rakow, Glenn P.

2007-01-01

An Application Specific Integrated Circuit (ASIC) that implements the SpaceWire protocol has been developed in a radiation hardened 0.25 micron CMOS technology. This effort began in March 2003 as a joint development between the NASA Goddard Space Flight Center (GSFC) and BAE Systems. The BAE Systems SpaceWire ASIC is comprised entirely of reusable core elements, many of which are already flight-proven. It incorporates a router with 4 SpaceWire ports and two local ports, dual PC1 bus interfaces, a microcontroller, 32KB of internal memory, and a memory controller for additional external memory use. The SpaceWire cores are also reused in other ASICs under development. The SpaceWire ASIC is planned for use on the Geostationary Operational Environmental Satellites (GOES)-R, the Lunar Reconnaissance Orbiter (LRO) and other missions. Engineering and flight parts have been delivered to programs and users. This paper reviews the SpaceWire protocol and those elements of it that have been built into the current and next SpaceWire reusable cores and features within the core that go beyond the current standard and can be enabled or disabled by the user. The adaptation of SpaceWire to BAE Systems' On Chip Bus (OCB) for compatibility with the other reusable cores will be reviewed and highlighted. Optional configurations within user systems and test boards will be shown. The physical implementation of the design will be described and test results from the hardware will be discussed. Application of this ASIC and other ASICs containing the SpaceWire cores and embedded microcontroller to Plug and Play and reconfigurable implementations will be described. Finally, the BAE Systems roadmap for SpaceWire developments will be updated, including some products already in design as well as longer term plans.

Burst Mode ASIC-Based Modem

NASA Technical Reports Server (NTRS)

1997-01-01

The NASA Lewis Research Center is sponsoring the Advanced Communication Technology Insertion (ACTION) for Commercial Space Applications program. The goal of the program is to expedite the development of new technology with a clear path towards productization and enhancing the competitiveness of U.S. manufacturers. The industry has made significant investment in developing ASIC-based modem technology for continuous-mode applications and has made investigations into East, reliable acquisition of burst-mode digital communication signals. With rapid advances in analog and digital communications ICs, it is expected that more functions will be integrated onto these parts in the near future. In addition custom ASIC's can also be developed to address the areas not covered by the other IC's. Using the commercial chips and custom ASIC's, lower-cost, compact, reliable, and high-performance modems can be built for demanding satellite communication application. This report outlines a frequency-hop burst modem design based on commercially available chips.

Integrated Cryogenic Electronics Testbed (ICE-T) for Evaluation of Superconductor and Cryo-Semiconductor Integrated Circuits

NASA Astrophysics Data System (ADS)

Dotsenko, V. V.; Sahu, A.; Chonigman, B.; Tang, J.; Lehmann, A. E.; Gupta, V.; Talalevskii, A.; Ruotolo, S.; Sarwana, S.; Webber, R. J.; Gupta, D.

2017-02-01

Research and development of cryogenic application-specific integrated circuits (ASICs), such as high-frequency (tens of GHz) semiconductor and superconductor mixed-signal circuits and large-scale (>10,000 Josephson Junctions) superconductor digital circuits, have long been hindered by the absence of specialized cryogenic test apparatus. During their iterative development phase, most ASICs require many additional input-output lines for applying independent bias controls, injecting test signals, and monitoring outputs of different sub-circuits. We are developing a full suite of modular test apparatus based on cryocoolers that do not consume liquid helium, and support extensive electrical interfaces to standard and custom test equipment. Our design separates the cryogenics from electrical connections, allowing even inexperienced users to conduct testing by simply mounting their ASIC on a removable electrical insert. Thermal connections between the cold stages and the inserts are made with robust thermal links. ICE-T accommodates two independent electrical inserts at the same time. We have designed various inserts, such as universal ones with all 40 or 80 coaxial cables and those with customized wiring and temperature-controlled stages. ICE-T features fast thermal cycling for rapid testing, enables detailed testing over long periods (days to months, if necessary), and even supports automated testing of digital ICs with modular additions.

Neuro-Prosthetic Implants With Adjustable Electrode Arrays

NASA Technical Reports Server (NTRS)

Whitacre, Jay; DelCastillo, Linda Y.; Mojarradi, Mohammad; Johnson, Travis; West, William; Andersen, Richard

2006-01-01

Brushlike arrays of electrodes packaged with application-specific integrated circuits (ASICs) are undergoing development for use as electronic implants especially as neuro-prosthetic devices that might be implanted in brains to detect weak electrical signals generated by neurons. These implants partly resemble the ones reported in Integrated Electrode Arrays for Neuro-Prosthetic Implants (NPO-21198), NASA Tech Briefs, Vol. 27, No. 2 (February 2003), page 48. The basic idea underlying both the present and previously reported implants is that the electrodes would pick up signals from neurons and the ASICs would amplify and otherwise preprocess the signals for monitoring by external equipment. The figure presents a simplified and partly schematic view of an implant according to the present concept. Whereas the electrodes in an implant according to the previously reported concept would be microscopic wires, the electrodes according to the present concept are in the form of microscopic needles. An even more important difference would be that, unlike the previously reported concept, the present concept calls for the inclusion of microelectromechanical actuators for adjusting the depth of penetration of the electrodes into brain tissue. The prototype implant now under construction includes an array of 100 electrodes and corresponding array of electrode contact pads formed on opposite faces of a plate fabricated by techniques that are established in the art of microelectromechanical systems (MEMS). A mixed-signal ASIC under construction at the time of reporting the information for this article will include 100 analog amplifier channels (one amplifier per electrode). On one face of the mixed-signal ASIC there will be a solder-bump/micro-pad array that will have the same pitch as that of the electrode array, and that will be used to make the electrical and mechanical connections between the electrode array and the ASIC. Once the electrode array and the ASIC are soldered together, the remaining empty space between them will be filled with a biocompatible epoxy, the remaining exposed portions of the ASIC will be covered with micromachined plates for protection against corrosive bodily fluids, and then the ASIC and its covering micromachined plates will be coated with parylene

VEGA: A low-power front-end ASIC for large area multi-linear X-ray silicon drift detectors: Design and experimental characterization

NASA Astrophysics Data System (ADS)

Ahangarianabhari, Mahdi; Macera, Daniele; Bertuccio, Giuseppe; Malcovati, Piero; Grassi, Marco

2015-01-01

We present the design and the first experimental characterization of VEGA, an Application Specific Integrated Circuit (ASIC) designed to read out large area monolithic linear Silicon Drift Detectors (SDD's). VEGA consists of an analog and a digital/mixed-signal section to accomplish all the functionalities and specifications required for high resolution X-ray spectroscopy in the energy range between 500 eV and 50 keV. The analog section includes a charge sensitive preamplifier, a shaper with 3-bit digitally selectable shaping times from 1.6 μs to 6.6 μs and a peak stretcher/sample-and-hold stage. The digital/mixed-signal section includes an amplitude discriminator with coarse and fine threshold level setting, a peak discriminator and a logic circuit to fulfill pile-up rejection, signal sampling, trigger generation, channel reset and the preamplifier and discriminators disabling functionalities. A Serial Peripherical Interface (SPI) is integrated in VEGA for loading and storing all configuration parameters in an internal register within few microseconds. The VEGA ASIC has been designed and manufactured in 0.35 μm CMOS mixed-signal technology in single and 32 channel versions with dimensions of 200 μm×500 μm per channel. A minimum intrinsic Equivalent Noise Charge (ENC) of 12 electrons r.m.s. at 3.6 μs peaking time and room temperature is measured and the linearity error is between -0.9% and +0.6% in the whole input energy range. The total power consumption is 481 μW and 420 μW per channel for the single and 32 channels version, respectively. A comparison with other ASICs for X-ray SDD's shows that VEGA has a suitable low noise and offers high functionality as ADC-ready signal processing but at a power consumption that is a factor of four lower than other similar existing ASICs.

CWICOM: A Highly Integrated & Innovative CCSDS Image Compression ASIC

NASA Astrophysics Data System (ADS)

Poupat, Jean-Luc; Vitulli, Raffaele

2013-08-01

The space market is more and more demanding in terms of on image compression performances. The earth observation satellites instrument resolution, the agility and the swath are continuously increasing. It multiplies by 10 the volume of picture acquired on one orbit. In parallel, the satellites size and mass are decreasing, requiring innovative electronic technologies reducing size, mass and power consumption. Astrium, leader on the market of the combined solutions for compression and memory for space application, has developed a new image compression ASIC which is presented in this paper. CWICOM is a high performance and innovative image compression ASIC developed by Astrium in the frame of the ESA contract n°22011/08/NLL/LvH. The objective of this ESA contract is to develop a radiation hardened ASIC that implements the CCSDS 122.0-B-1 Standard for Image Data Compression, that has a SpaceWire interface for configuring and controlling the device, and that is compatible with Sentinel-2 interface and with similar Earth Observation missions. CWICOM stands for CCSDS Wavelet Image COMpression ASIC. It is a large dynamic, large image and very high speed image compression ASIC potentially relevant for compression of any 2D image with bi-dimensional data correlation such as Earth observation, scientific data compression… The paper presents some of the main aspects of the CWICOM development, such as the algorithm and specification, the innovative memory organization, the validation approach and the status of the project.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Flory, John Andrew; Padilla, Denise D.; Gauthier, John H.

Upcoming weapon programs require an aggressive increase in Application Specific Integrated Circuit (ASIC) production at Sandia National Laboratories (SNL). SNL has developed unique modeling and optimization tools that have been instrumental in improving ASIC production productivity and efficiency, identifying optimal operational and tactical execution plans under resource constraints, and providing confidence in successful mission execution. With ten products and unprecedented levels of demand, a single set of shared resources, highly variable processes, and the need for external supplier task synchronization, scheduling is an integral part of successful manufacturing. The scheduler uses an iterative multi-objective genetic algorithm and a multi-dimensional performancemore » evaluator. Schedule feasibility is assessed using a discrete event simulation (DES) that incorporates operational uncertainty, variability, and resource availability. The tools provide rapid scenario assessments and responses to variances in the operational environment, and have been used to inform major equipment investments and workforce planning decisions in multiple SNL facilities.« less

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bolotnikov, A. E., E-mail: bolotnik@bnl.gov; Ackley, K.; Camarda, G. S.

We developed a robust and low-cost array of virtual Frisch-grid CdZnTe detectors coupled to a front-end readout application-specific integrated circuit (ASIC) for spectroscopy and imaging of gamma rays. The array operates as a self-reliant detector module. It is comprised of 36 close-packed 6 × 6 × 15 mm{sup 3} detectors grouped into 3 × 3 sub-arrays of 2 × 2 detectors with the common cathodes. The front-end analog ASIC accommodates up to 36 anode and 9 cathode inputs. Several detector modules can be integrated into a single- or multi-layer unit operating as a Compton or a coded-aperture camera. We presentmore » the results from testing two fully assembled modules and readout electronics. The further enhancement of the arrays’ performance and reduction of their cost are possible by using position-sensitive virtual Frisch-grid detectors, which allow for accurate corrections of the response of material non-uniformities caused by crystal defects.« less

Robust Multivariable Optimization and Performance Simulation for ASIC Design

NASA Technical Reports Server (NTRS)

DuMonthier, Jeffrey; Suarez, George

2013-01-01

Application-specific-integrated-circuit (ASIC) design for space applications involves multiple challenges of maximizing performance, minimizing power, and ensuring reliable operation in extreme environments. This is a complex multidimensional optimization problem, which must be solved early in the development cycle of a system due to the time required for testing and qualification severely limiting opportunities to modify and iterate. Manual design techniques, which generally involve simulation at one or a small number of corners with a very limited set of simultaneously variable parameters in order to make the problem tractable, are inefficient and not guaranteed to achieve the best possible results within the performance envelope defined by the process and environmental requirements. What is required is a means to automate design parameter variation, allow the designer to specify operational constraints and performance goals, and to analyze the results in a way that facilitates identifying the tradeoffs defining the performance envelope over the full set of process and environmental corner cases. The system developed by the Mixed Signal ASIC Group (MSAG) at the Goddard Space Flight Center is implemented as a framework of software modules, templates, and function libraries. It integrates CAD tools and a mathematical computing environment, and can be customized for new circuit designs with only a modest amount of effort as most common tasks are already encapsulated. Customization is required for simulation test benches to determine performance metrics and for cost function computation.

Note: A 102 dB dynamic-range charge-sampling readout for ionizing particle/radiation detectors based on an application-specific integrated circuit (ASIC)

NASA Astrophysics Data System (ADS)

Pullia, A.; Zocca, F.; Capra, S.

2018-02-01

An original technique for the measurement of charge signals from ionizing particle/radiation detectors has been implemented in an application-specific integrated circuit form. The device performs linear measurements of the charge both within and beyond its output voltage swing. The device features an unprecedented spectroscopic dynamic range of 102 dB and is suitable for high-resolution ion and X-γ ray spectroscopy. We believe that this approach may change a widespread paradigm according to which no high-resolution spectroscopy is possible when working close to or beyond the limit of the preamplifier's output voltage swing.

Note: A 102 dB dynamic-range charge-sampling readout for ionizing particle/radiation detectors based on an application-specific integrated circuit (ASIC).

PubMed

Pullia, A; Zocca, F; Capra, S

2018-02-01

An original technique for the measurement of charge signals from ionizing particle/radiation detectors has been implemented in an application-specific integrated circuit form. The device performs linear measurements of the charge both within and beyond its output voltage swing. The device features an unprecedented spectroscopic dynamic range of 102 dB and is suitable for high-resolution ion and X-γ ray spectroscopy. We believe that this approach may change a widespread paradigm according to which no high-resolution spectroscopy is possible when working close to or beyond the limit of the preamplifier's output voltage swing.

Single software platform used for high speed data transfer implementation in a 65k pixel camera working in single photon counting mode

NASA Astrophysics Data System (ADS)

Maj, P.; Kasiński, K.; Gryboś, P.; Szczygieł, R.; Kozioł, A.

2015-12-01

Integrated circuits designed for specific applications generally use non-standard communication methods. Hybrid pixel detector readout electronics produces a huge amount of data as a result of number of frames per seconds. The data needs to be transmitted to a higher level system without limiting the ASIC's capabilities. Nowadays, the Camera Link interface is still one of the fastest communication methods, allowing transmission speeds up to 800 MB/s. In order to communicate between a higher level system and the ASIC with a dedicated protocol, an FPGA with dedicated code is required. The configuration data is received from the PC and written to the ASIC. At the same time, the same FPGA should be able to transmit the data from the ASIC to the PC at the very high speed. The camera should be an embedded system enabling autonomous operation and self-monitoring. In the presented solution, at least three different hardware platforms are used—FPGA, microprocessor with real-time operating system and the PC with end-user software. We present the use of a single software platform for high speed data transfer from 65k pixel camera to the personal computer.

Insulator photocurrents: Application to dose rate hardening of CMOS/SOI integrated circuits

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dupont-Nivet, E.; Coiec, Y.M.; Flament, O.

1998-06-01

Irradiation of insulators with a pulse of high energy x-rays can induce photocurrents in the interconnections of integrated circuits. The authors present, here, a new method to measure and analyze this effect together with a simple model. They also demonstrate that these insulator photocurrents have to be taken into account to obtain high levels of dose-rate hardness with CMOS on SOI integrated circuits, especially flip-flops or memory blocks of ASICs. They show that it explains some of the upsets observed in a SRAM embedded in an ASIC.

Effects of high-energy particle showers on the embedded front-end electronics of an electromagnetic calorimeter for a future lepton collider

NASA Astrophysics Data System (ADS)

Adloff, C.; Francis, K.; Repond, J.; Smith, J.; Trojand, D.; Xia, L.; Baldolemar, E.; Li, J.; Park, S. T.; Sosebee, M.; White, A. P.; Yu, J.; Mikami, Y.; Watson, N. K.; Mavromanolakis, G.; Thomson, M. A.; Ward, D. R.; Yan, W.; Benchekroun, D.; Hoummada, A.; Khoulaki, Y.; Benyamna, M.; Cârloganu, C.; Fehr, F.; Gay, P.; Manen, S.; Royer, L.; Blazey, G. C.; Dyshkant, A.; Zutshi, V.; Hostachy, J.-Y.; Morin, L.; Cornett, U.; David, D.; Fabbri, R.; Falley, G.; Gadow, K.; Garutti, E.; Göttlicher, P.; Günter, C.; Karstensen, S.; Krivan, F.; Lucaci-Timoce, A.-I.; Lu, S.; Lutz, B.; Marchesini, I.; Meyer, N.; Morozov, S.; Morgunov, V.; Reinecke, M.; Sefkow, F.; Smirnov, P.; Terwort, M.; Vargas-Trevino, A.; Wattimena, N.; Wendt, O.; Feege, N.; Haller, J.; Richter, S.; Samson, J.; Eckert, P.; Kaplan, A.; Schultz-Coulon, H.-Ch.; Shen, W.; Stamen, R.; Tadday, A.; Bilki, B.; Norbeck, E.; Onel, Y.; Kawagoe, K.; Uozumi, S.; Dauncey, P. D.; Magnan, A.-M.; Bartsch, V.; Salvatore, F.; Laktineh, I.; Calvo Alamillo, E.; Fouz, M.-C.; Puerta-Pelayo, J.; Frey, A.; Kiesling, C.; Simon, F.; Bonis, J.; Bouquet, B.; Callier, S.; Cornebise, P.; Doublet, Ph.; Dulucq, F.; Faucci Giannelli, M.; Fleury, J.; Li, H.; Martin-Chassard, G.; Richard, F.; de La Taille, Ch.; Pöschl, R.; Raux, L.; Seguin-Moreau, N.; Wicek, F.; Anduze, M.; Boudry, V.; Brient, J.-C.; Jeans, D.; Mora de Freitas, P.; Musat, G.; Reinhard, M.; Ruan, M.; Videau, H.; Marcisovsky, M.; Sicho, P.; Vrba, V.; Zalesak, J.; Belhorma, B.; Ghazlane, H.; Calice Collaboration

2011-10-01

Application Specific Integrated Circuits, ASICs, similar to those envisaged for the readout electronics of the central calorimeters of detectors for a future lepton collider have been exposed to high-energy electromagnetic showers. A salient feature of these calorimeters is that the readout electronics will be embedded into the calorimeter layers. In this article it is shown that interactions of shower particles in the volume of the readout electronics do not alter the noise pattern of the ASICs. No signal at or above the MIP level has been observed during the exposure. The upper limit at the 95% confidence level on the frequency of fake signals is smaller than 1×10-5 for a noise threshold of about 60% of a MIP. For ASICs with similar design to those which were tested, it can thus be largely excluded that the embedding of the electronics into the calorimeter layers compromises the performance of the calorimeters.

Ultra-Reliable Digital Avionics (URDA) processor

NASA Astrophysics Data System (ADS)

Branstetter, Reagan; Ruszczyk, William; Miville, Frank

1994-10-01

Texas Instruments Incorporated (TI) developed the URDA processor design under contract with the U.S. Air Force Wright Laboratory and the U.S. Army Night Vision and Electro-Sensors Directorate. TI's approach couples advanced packaging solutions with advanced integrated circuit (IC) technology to provide a high-performance (200 MIPS/800 MFLOPS) modular avionics processor module for a wide range of avionics applications. TI's processor design integrates two Ada-programmable, URDA basic processor modules (BPM's) with a JIAWG-compatible PiBus and TMBus on a single F-22 common integrated processor-compatible form-factor SEM-E avionics card. A separate, high-speed (25-MWord/second 32-bit word) input/output bus is provided for sensor data. Each BPM provides a peak throughput of 100 MIPS scalar concurrent with 400-MFLOPS vector processing in a removable multichip module (MCM) mounted to a liquid-flowthrough (LFT) core and interfacing to a processor interface module printed wiring board (PWB). Commercial RISC technology coupled with TI's advanced bipolar complementary metal oxide semiconductor (BiCMOS) application specific integrated circuit (ASIC) and silicon-on-silicon packaging technologies are used to achieve the high performance in a miniaturized package. A Mips R4000-family reduced instruction set computer (RISC) processor and a TI 100-MHz BiCMOS vector coprocessor (VCP) ASIC provide, respectively, the 100 MIPS of a scalar processor throughput and 400 MFLOPS of vector processing throughput for each BPM. The TI Aladdim ASIC chipset was developed on the TI Aladdin Program under contract with the U.S. Army Communications and Electronics Command and was sponsored by the Advanced Research Projects Agency with technical direction from the U.S. Army Night Vision and Electro-Sensors Directorate.

Capturing a failure of an ASIC in-situ, using infrared radiometry and image processing software

NASA Technical Reports Server (NTRS)

Ruiz, Ronald P.

2003-01-01

Failures in electronic devices can sometimes be tricky to locate-especially if they are buried inside radiation-shielded containers designed to work in outer space. Such was the case with a malfunctioning ASIC (Application Specific Integrated Circuit) that was drawing excessive power at a specific temperature during temperature cycle testing. To analyze the failure, infrared radiometry (thermography) was used in combination with image processing software to locate precisely where the power was being dissipated at the moment the failure took place. The IR imaging software was used to make the image of the target and background, appear as unity. As testing proceeded and the failure mode was reached, temperature changes revealed the precise location of the fault. The results gave the design engineers the information they needed to fix the problem. This paper describes the techniques and equipment used to accomplish this failure analysis.

Asic developments for radiation imaging applications: The medipix and timepix family

NASA Astrophysics Data System (ADS)

Ballabriga, Rafael; Campbell, Michael; Llopart, Xavier

2018-01-01

Hybrid pixel detectors were developed to meet the requirements for tracking in the inner layers at the LHC experiments. With low input capacitance per channel (10-100 fF) it is relatively straightforward to design pulse processing readout electronics with input referred noise of ∼ 100 e-rms and pulse shaping times consistent with tagging of events to a single LHC bunch crossing providing clean 'images' of the ionising tracks generated. In the Medipix Collaborations the same concept has been adapted to provide practically noise hit free imaging in a wide range of applications. This paper reports on the development of three generations of readout ASICs. Two distinctive streams of development can be identified: the Medipix ASICs which integrate data from multiple hits on a pixel and provide the images in the form of frames and the Timepix ASICs who aim to send as much information about individual interactions as possible off-chip for further processing. One outstanding circumstance in the use of these devices has been their numerous successful applications, thanks to a large and active community of developers and users. That process has even permitted new developments for detectors for High Energy Physics. This paper reviews the ASICs themselves and details some of the many applications.

Validation of a highly integrated SiPM readout system with a TOF-PET demonstrator

NASA Astrophysics Data System (ADS)

Niknejad, T.; Setayeshi, S.; Tavernier, S.; Bugalho, R.; Ferramacho, L.; Di Francesco, A.; Leong, C.; Rolo, M. D.; Shamshirsaz, M.; Silva, J. C.; Silva, R.; Silveira, M.; Zorraquino, C.; Varela, J.

2016-12-01

We have developed a highly integrated, fast and compact readout electronics for Silicon Photomultiplier (SiPM) based Time of Flight Positron Emission Tomography (TOF-PET) scanners. The readout is based on the use of TOP-PET Application Specific Integrated Circuit (PETsys TOFPET1 ASIC) with 64 channels, each with its amplifier, discriminator, Time to Digital Converter (TDC) and amplitude determination using Time Over Threshold (TOT). The ASIC has 25 ps r.m.s. intrinsic time resolution and fully digital output. The system is optimised for high rates, good timing, low power consumption and low cost. For validating the readout electronics, we have built a technical PET scanner, hereafter called ``demonstrator'', with 2'048 SiPM channels. The PET demonstrator has 16 compact Detector Modules (DM). Each DM has two ASICs reading 128 SiPM pixels in one-to-one coupling to 128 Lutetium Yttrium Orthosilicate (LYSO) crystals measuring 3.1 × 3.1 × 15 mm3 each. The data acquisition system for the demonstrator has two Front End Boards type D (FEB/D), each collecting the data of 1'024 channels (8 DMs), and transmitting assembled data frames through a serial link (4.8 Gbps), to a single Data Acquisition (DAQ) board plugged into the Peripheral Component Interconnect Express (PCIe) bus of the data acquisition PC. Results obtained with this PET demonstrator are presented.

A Differential Monolithically Integrated Inductive Linear Displacement Measurement Microsystem

PubMed Central

Podhraški, Matija; Trontelj, Janez

2016-01-01

An inductive linear displacement measurement microsystem realized as a monolithic Application-Specific Integrated Circuit (ASIC) is presented. The system comprises integrated microtransformers as sensing elements, and analog front-end electronics for signal processing and demodulation, both jointly fabricated in a conventional commercially available four-metal 350-nm CMOS process. The key novelty of the presented system is its full integration, straightforward fabrication, and ease of application, requiring no external light or magnetic field source. Such systems therefore have the possibility of substituting certain conventional position encoder types. The microtransformers are excited by an AC signal in MHz range. The displacement information is modulated into the AC signal by a metal grating scale placed over the microsystem, employing a differential measurement principle. Homodyne mixing is used for the demodulation of the scale displacement information, returned by the ASIC as a DC signal in two quadrature channels allowing the determination of linear position of the target scale. The microsystem design, simulations, and characterization are presented. Various system operating conditions such as frequency, phase, target scale material and distance have been experimentally evaluated. The best results have been achieved at 4 MHz, demonstrating a linear resolution of 20 µm with steel and copper scale, having respective sensitivities of 0.71 V/mm and 0.99 V/mm. PMID:26999146

A Differential Monolithically Integrated Inductive Linear Displacement Measurement Microsystem.

PubMed

Podhraški, Matija; Trontelj, Janez

2016-03-17

An inductive linear displacement measurement microsystem realized as a monolithic Application-Specific Integrated Circuit (ASIC) is presented. The system comprises integrated microtransformers as sensing elements, and analog front-end electronics for signal processing and demodulation, both jointly fabricated in a conventional commercially available four-metal 350-nm CMOS process. The key novelty of the presented system is its full integration, straightforward fabrication, and ease of application, requiring no external light or magnetic field source. Such systems therefore have the possibility of substituting certain conventional position encoder types. The microtransformers are excited by an AC signal in MHz range. The displacement information is modulated into the AC signal by a metal grating scale placed over the microsystem, employing a differential measurement principle. Homodyne mixing is used for the demodulation of the scale displacement information, returned by the ASIC as a DC signal in two quadrature channels allowing the determination of linear position of the target scale. The microsystem design, simulations, and characterization are presented. Various system operating conditions such as frequency, phase, target scale material and distance have been experimentally evaluated. The best results have been achieved at 4 MHz, demonstrating a linear resolution of 20 µm with steel and copper scale, having respective sensitivities of 0.71 V/mm and 0.99 V/mm.

A CMOS application-specified-integrated-circuit for 40 GHz high-electron-mobility-transistors automatic biasing

NASA Astrophysics Data System (ADS)

De Matteis, M.; De Blasi, M.; Vallicelli, E. A.; Zannoni, M.; Gervasi, M.; Bau, A.; Passerini, A.; Baschirotto, A.

2017-02-01

This paper presents the design and the experimental results of a CMOS Automatic Control System (ACS) for the biasing of High-Electron-Mobility-Transistors (HEMT). The ACS is the first low-power mixed-signal Application-Specified-Integrated-Circuit (ASIC) able to automatically set and regulate the operating point of an off-chip 6 HEMT Low-Noise-Amplifiers (LNAs), hence it composes a two-chip system (the ACS+LNAs) to be used in the Large Scale Polarization Explorer (LSPE) stratospheric balloon for Cosmic Microwave Background (CMB) signal observation. The hereby presented ACS ASIC provides a reliable instrumentation for gradual and very stable LNAs characterization, switching-on, and operating point (<4 mV accuracy). Moreover, it simplifies the electronic instrumentation needed for biasing the LNAs, since it replaces several off-the-shelf and digital programmable device components. The ASIC prototype has been implemented in a CMOS 0.35 μ m technology (12 mm2 area occupancy). It operates at 4 kHz clock frequency. The power consumption of one-channel ASIC (biasing one LNA) is 3.6 mW, whereas 30 mW are consumed by a single LNA device.

A CMOS application-specified-integrated-circuit for 40 GHz high-electron-mobility-transistors automatic biasing.

PubMed

De Matteis, M; De Blasi, M; Vallicelli, E A; Zannoni, M; Gervasi, M; Bau, A; Passerini, A; Baschirotto, A

2017-02-01

This paper presents the design and the experimental results of a CMOS Automatic Control System (ACS) for the biasing of High-Electron-Mobility-Transistors (HEMT). The ACS is the first low-power mixed-signal Application-Specified-Integrated-Circuit (ASIC) able to automatically set and regulate the operating point of an off-chip 6 HEMT Low-Noise-Amplifiers (LNAs), hence it composes a two-chip system (the ACS+LNAs) to be used in the Large Scale Polarization Explorer (LSPE) stratospheric balloon for Cosmic Microwave Background (CMB) signal observation. The hereby presented ACS ASIC provides a reliable instrumentation for gradual and very stable LNAs characterization, switching-on, and operating point (<4 mV accuracy). Moreover, it simplifies the electronic instrumentation needed for biasing the LNAs, since it replaces several off-the-shelf and digital programmable device components. The ASIC prototype has been implemented in a CMOS 0.35 μm technology (12 mm 2 area occupancy). It operates at 4 kHz clock frequency. The power consumption of one-channel ASIC (biasing one LNA) is 3.6 mW, whereas 30 mW are consumed by a single LNA device.

Design of a video capsule endoscopy system with low-power ASIC for monitoring gastrointestinal tract.

PubMed

Liu, Gang; Yan, Guozheng; Zhu, Bingquan; Lu, Li

2016-11-01

In recent years, wireless capsule endoscopy (WCE) has been a state-of-the-art tool to examine disorders of the human gastrointestinal tract painlessly. However, system miniaturization, enhancement of the image-data transfer rate and power consumption reduction for the capsule are still key challenges. In this paper, a video capsule endoscopy system with a low-power controlling and processing application-specific integrated circuit (ASIC) is designed and fabricated. In the design, these challenges are resolved by employing a microimage sensor, a novel radio frequency transmitter with an on-off keying modulation rate of 20 Mbps, and an ASIC structure that includes a clock management module, a power-efficient image compression module and a power management unit. An ASIC-based prototype capsule, which measures Φ11 mm × 25 mm, has been developed here. Test results show that the designed ASIC consumes much less power than most of the other WCE systems and that its total power consumption per frame is the least. The image compression module can realize high near-lossless compression rate (3.69) and high image quality (46.2 dB). The proposed system supports multi-spectral imaging, including white light imaging and autofluorescence imaging, at a maximum frame rate of 24 fps and with a resolution of 400 × 400. Tests and in vivo trials in pigs have proved the feasibility of the entire system, but further improvements in capsule control and compression performance inside the ASIC are needed in the future.

End-of-fabrication CMOS process monitor

NASA Technical Reports Server (NTRS)

Buehler, M. G.; Allen, R. A.; Blaes, B. R.; Hannaman, D. J.; Lieneweg, U.; Lin, Y.-S.; Sayah, H. R.

1990-01-01

A set of test 'modules' for verifying the quality of a complementary metal oxide semiconductor (CMOS) process at the end of the wafer fabrication is documented. By electrical testing of specific structures, over thirty parameters are collected characterizing interconnects, dielectrics, contacts, transistors, and inverters. Each test module contains a specification of its purpose, the layout of the test structure, the test procedures, the data reduction algorithms, and exemplary results obtained from 3-, 2-, or 1.6-micrometer CMOS/bulk processes. The document is intended to establish standard process qualification procedures for Application Specific Integrated Circuits (ASIC's).

Design and performances of a low-noise and radiation-hardened readout ASIC for CdZnTe detectors

NASA Astrophysics Data System (ADS)

Bo, Gan; Tingcun, Wei; Wu, Gao; Yongcai, Hu

2016-06-01

In this paper, we present the design and performances of a low-noise and radiation-hardened front-end readout application specific integrated circuit (ASIC) dedicated to CdZnTe detectors for a hard X-ray imager in space applications. The readout channel is comprised of a charge sensitive amplifier, a CR-RC shaping amplifier, an analog output buffer, a fast shaper, and a discriminator. An 8-channel prototype ASIC is designed and fabricated in TSMC 0.35-μm mixed-signal CMOS technology, the die size of the prototype chip is 2.2 × 2.2 mm2. The input energy range is from 5 to 350 keV. For this 8-channel prototype ASIC, the measured electrical characteristics are as follows: the overall gain of the readout channel is 210 V/pC, the linearity error is less than 2%, the crosstalk is less than 0.36%, The equivalent noise charge of a typical channel is 52.9 e- at zero farad plus 8.2 e- per picofarad, and the power consumption is less than 2.4 mW/channel. Through the measurement together with a CdZnTe detector, the energy resolution is 5.9% at the 59.5-keV line under the irradiation of the radioactive source 241Am. The radiation effect experiments show that the proposed ASIC can resist the total ionization dose (TID) irradiation of higher than 200 krad(Si). Project supported by the National Key Scientific Instrument and Equipment Development Project (No. 2011YQ040082), the National Natural Science Foundation of China (Nos. 11475136, 11575144, 61176094), and the Shaanxi Natural Science Foundation of China (No. 2015JM1016).

Management of Microcircuit Obsolescence in a Pre-Production ACAT-ID Missile Program

DTIC Science & Technology

2002-12-01

and Engineering Center ASIC Application Specific Integrated Circuit AVCOM Avionics Component Obsolescence Management BRU Battery Replaceable Unit...then just a paper qualification, e.g. Board or Battery Replaceable Unit ( BRU ) testing. 5 After-market Package The Die is Available and Can Be...Encapsulated Microcircuits (PEM), speed change, failure rate) 8 Emulation Manufacture or re-engineering of a FFF Replacement 9 CCA or BRU Redesign Board

Ultrascalable petaflop parallel supercomputer

DOEpatents

Blumrich, Matthias A [Ridgefield, CT; Chen, Dong [Croton On Hudson, NY; Chiu, George [Cross River, NY; Cipolla, Thomas M [Katonah, NY; Coteus, Paul W [Yorktown Heights, NY; Gara, Alan G [Mount Kisco, NY; Giampapa, Mark E [Irvington, NY; Hall, Shawn [Pleasantville, NY; Haring, Rudolf A [Cortlandt Manor, NY; Heidelberger, Philip [Cortlandt Manor, NY; Kopcsay, Gerard V [Yorktown Heights, NY; Ohmacht, Martin [Yorktown Heights, NY; Salapura, Valentina [Chappaqua, NY; Sugavanam, Krishnan [Mahopac, NY; Takken, Todd [Brewster, NY

2010-07-20

A massively parallel supercomputer of petaOPS-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC) having up to four processing elements. The ASIC nodes are interconnected by multiple independent networks that optimally maximize the throughput of packet communications between nodes with minimal latency. The multiple networks may include three high-speed networks for parallel algorithm message passing including a Torus, collective network, and a Global Asynchronous network that provides global barrier and notification functions. These multiple independent networks may be collaboratively or independently utilized according to the needs or phases of an algorithm for optimizing algorithm processing performance. The use of a DMA engine is provided to facilitate message passing among the nodes without the expenditure of processing resources at the node.

Video data compression using artificial neural network differential vector quantization

NASA Technical Reports Server (NTRS)

Krishnamurthy, Ashok K.; Bibyk, Steven B.; Ahalt, Stanley C.

1991-01-01

An artificial neural network vector quantizer is developed for use in data compression applications such as Digital Video. Differential Vector Quantization is used to preserve edge features, and a new adaptive algorithm, known as Frequency-Sensitive Competitive Learning, is used to develop the vector quantizer codebook. To develop real time performance, a custom Very Large Scale Integration Application Specific Integrated Circuit (VLSI ASIC) is being developed to realize the associative memory functions needed in the vector quantization algorithm. By using vector quantization, the need for Huffman coding can be eliminated, resulting in superior performance against channel bit errors than methods that use variable length codes.

Multiplexed, High Density Electrophysiology with Nanofabricated Neural Probes

PubMed Central

Du, Jiangang; Blanche, Timothy J.; Harrison, Reid R.; Lester, Henry A.; Masmanidis, Sotiris C.

2011-01-01

Extracellular electrode arrays can reveal the neuronal network correlates of behavior with single-cell, single-spike, and sub-millisecond resolution. However, implantable electrodes are inherently invasive, and efforts to scale up the number and density of recording sites must compromise on device size in order to connect the electrodes. Here, we report on silicon-based neural probes employing nanofabricated, high-density electrical leads. Furthermore, we address the challenge of reading out multichannel data with an application-specific integrated circuit (ASIC) performing signal amplification, band-pass filtering, and multiplexing functions. We demonstrate high spatial resolution extracellular measurements with a fully integrated, low noise 64-channel system weighing just 330 mg. The on-chip multiplexers make possible recordings with substantially fewer external wires than the number of input channels. By combining nanofabricated probes with ASICs we have implemented a system for performing large-scale, high-density electrophysiology in small, freely behaving animals that is both minimally invasive and highly scalable. PMID:22022568

Design of the PET-MR system for head imaging of the DREAM Project

NASA Astrophysics Data System (ADS)

González, A. J.; Conde, P.; Hernández, L.; Herrero, V.; Moliner, L.; Monzó, J. M.; Orero, A.; Peiró, A.; Rodríguez-Álvarez, M. J.; Ros, A.; Sánchez, F.; Soriano, A.; Vidal, L. F.; Benlloch, J. M.

2013-02-01

In this paper we describe the overall design of a PET-MR system for head imaging within the framework of the DREAM Project as well as the first detector module tests. The PET system design consists of 4 rings of 16 detector modules each and it is expected to be integrated in a head dedicated radio frequency coil of an MR scanner. The PET modules are based on monolithic LYSO crystals coupled by means of optical devices to an array of 256 Silicon Photomultipliers. These types of crystals allow to preserve the scintillation light distribution and, thus, to recover the exact photon impact position with the proper characterization of such a distribution. Every module contains 4 Application Specific Integrated Circuits (ASICs) which return detailed information of several light statistical momenta. The preliminary tests carried out on this design and controlled by means of ASICs have shown promising results towards the suitability of hybrid PET-MR systems.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Vernon, E.; De Geronimo, G.; Ackley, K.

We report on the development of an application specific integrated circuit (ASIC) for 3D position sensitive detectors (3D PSD). The ASIC is designed to operate with pixelated wide bandgap sensors like Cadmium-Zinc-Telluride (CZT), Mercuric Iodide (Hgl2) and Thallium Bromide (TIBr). It measures the amplitudes and timings associated with an ionizing event on 128 anodes, the anode grid, and the cathode. Each channel provides low-noise charge amplification, high-order shaping with peaking time adjustable from 250 ns to 12 {micro}s, gain adjustable to 20 mV/fC or 120 mV/fC (for a dynamic range of 3.2 MeV and 530 keV in CZT), amplitude discriminationmore » with 5-bit trimming, and positive and negative peak and timing detections. The readout can be full or sparse, based on a flag and single- or multi-cycle token passing. All channels, triggered channels only, or triggered with neighbors can be read out thus increasing the rate capability of the system to more than 10 kcps. The ASIC dissipates 330 mW which corresponds to about 2.5 mW per channel.« less

Memory-Based Structured Application Specific Integrated Circuit (ASIC) Study

DTIC Science & Technology

2008-10-01

memory interface, arbiter/ schedulers for rescheduling the memory requests according to some schedule policy, and memory channels for communicating...between the power-savings and the wakeup overhead with respect to both wakeup power and wakeup delay. For example, dream mode can save 50% more static...power than sleep mode, but at the expense of twice the wake delay and three times the wakeup energy. The user can specify power-gating modes for various components.

Challenges Regarding IP Core Functional Reliability

NASA Technical Reports Server (NTRS)

Berg, Melanie D.; LaBel, Kenneth A.

2017-01-01

For many years, intellectual property (IP) cores have been incorporated into field programmable gate array (FPGA) and application specific integrated circuit (ASIC) design flows. However, the usage of large complex IP cores were limited within products that required a high level of reliability. This is no longer the case. IP core insertion has become mainstream including their use in highly reliable products. Due to limited visibility and control, challenges exist when using IP cores and subsequently compromise product reliability. We discuss challenges and suggest potential solutions to critical application IP insertion.

RF-DC converter for HF RFID sensing applications powered by a near-field loop antenna

NASA Astrophysics Data System (ADS)

Colella, R.; Pasca, M.; Catarinucci, L.; Tarricone, L.; D'Amico, S.

2016-07-01

In this paper, an RF-DC converter operating at 13.56 MHz (HF radio frequency identification (RFID) frequency band) is presented. Its architecture provides RF to load isolation, reducing the losses due to the reverse saturation current and improving the sensitivity. Fed by a loop antenna, the RF-DC converter is made by a Dickson's RF-DC rectifier and an additional Pelliconi's charge pump driven by a fully integrated 50 kHz ring oscillator realized using an application-specific integrated circuit (ASIC). The input RF signal from the reader is converted to DC supply voltage and stored on a 1 μF capacitor. Mathematical model of the converter is developed and verified through measurements. Silicon prototypes of the ASIC have been realized in 350 nm complementary metal-oxide semiconductor technology. Measurements have been done on 10 different samples showing an output voltage in the range of 0.5 V-3.11 V in correspondence of an RF input signal power in the range of -19 dBm-0 dBm. These output voltage levels are suitable to power HF RFID sensing platforms and sensor nodes of body sensor networks.

Architecture design of the multi-functional wavelet-based ECG microprocessor for realtime detection of abnormal cardiac events.

PubMed

Cheng, Li-Fang; Chen, Tung-Chien; Chen, Liang-Gee

2012-01-01

Most of the abnormal cardiac events such as myocardial ischemia, acute myocardial infarction (AMI) and fatal arrhythmia can be diagnosed through continuous electrocardiogram (ECG) analysis. According to recent clinical research, early detection and alarming of such cardiac events can reduce the time delay to the hospital, and the clinical outcomes of these individuals can be greatly improved. Therefore, it would be helpful if there is a long-term ECG monitoring system with the ability to identify abnormal cardiac events and provide realtime warning for the users. The combination of the wireless body area sensor network (BASN) and the on-sensor ECG processor is a possible solution for this application. In this paper, we aim to design and implement a digital signal processor that is suitable for continuous ECG monitoring and alarming based on the continuous wavelet transform (CWT) through the proposed architectures--using both programmable RISC processor and application specific integrated circuits (ASIC) for performance optimization. According to the implementation results, the power consumption of the proposed processor integrated with an ASIC for CWT computation is only 79.4 mW. Compared with the single-RISC processor, about 91.6% of the power reduction is achieved.

Low-power wireless micromanometer system for acute and chronic bladder-pressure monitoring.

PubMed

Majerus, Steve J A; Fletter, Paul C; Damaser, Margot S; Garverick, Steven L

2011-03-01

This letter describes the design, fabrication, and testing of a wireless bladder-pressure-sensing system for chronic, point-of-care applications, such as urodynamics or closed-loop neuromodulation. The system consists of a miniature implantable device and an external RF receiver and wireless battery charger. The implant is small enough to be cystoscopically implanted within the bladder wall, where it is securely held and shielded from the urine stream. The implant consists of a custom application-specific integrated circuit (ASIC), a pressure transducer, a rechargeable battery, and wireless telemetry and recharging antennas. The ASIC includes instrumentation, wireless transmission, and power-management circuitry, and on an average draws less than 9 μA from the 3.6-V battery. The battery charge can be wirelessly replenished with daily 6-h recharge periods that can occur during the periods of sleep. Acute in vivo evaluation of the pressure-sensing system in canine models has demonstrated that the system can accurately capture lumen pressure from a submucosal implant location.

New Generation Power System for Space Applications

NASA Technical Reports Server (NTRS)

Jones, Loren; Carr, Greg; Deligiannis, Frank; Lam, Barbara; Nelson, Ron; Pantaleon, Jose; Ruiz, Ian; Treicler, John; Wester, Gene; Sauers, Jim;

Design and characterization of the ePix10k: a high dynamic range integrating pixel ASIC for LCLS detectors

NASA Astrophysics Data System (ADS)

Caragiulo, P.; Dragone, A.; Markovic, B.; Herbst, R.; Nishimura, K.; Reese, B.; Herrmann, S.; Hart, P.; Blaj, G.; Segal, J.; Tomada, A.; Hasi, J.; Carini, G.; Kenney, C.; Haller, G.

2015-05-01

ePix10k is a variant of a novel class of integrating pixel ASICs architectures optimized for the processing of signals in second generation LINAC Coherent Light Source (LCLS) X-Ray cameras. The ASIC is optimized for high dynamic range application requiring high spatial resolution and fast frame rates. ePix ASICs are based on a common platform composed of a random access analog matrix of pixel with global shutter, fast parallel column readout, and dedicated sigma-delta analog to digital converters per column. The ePix10k variant has 100um×100um pixels arranged in a 176×192 matrix, a resolution of 140e- r.m.s. and a signal range of 3.5pC (10k photons at 8keV). In its final version it will be able to sustain a frame rate of 2kHz. A first prototype has been fabricated and characterized. Performance in terms of noise, linearity, uniformity, cross-talk, together with preliminary measurements with bump bonded sensors are reported here.

An Integrated Thermal Compensation System for MEMS Inertial Sensors

PubMed Central

Chiu, Sheng-Ren; Teng, Li-Tao; Chao, Jen-Wei; Sue, Chung-Yang; Lin, Chih-Hsiou; Chen, Hong-Ren; Su, Yan-Kuin

2014-01-01

An active thermal compensation system for a low temperature-bias-drift (TBD) MEMS-based gyroscope is proposed in this study. First, a micro-gyroscope is fabricated by a high-aspect-ratio silicon-on-glass (SOG) process and vacuum packaged by glass frit bonding. Moreover, a drive/readout ASIC, implemented by the 0.25 μm 1P5M standard CMOS process, is designed and integrated with the gyroscope by directly wire bonding. Then, since the temperature effect is one of the critical issues in the high performance gyroscope applications, the temperature-dependent characteristics of the micro-gyroscope are discussed. Furthermore, to compensate the TBD of the micro-gyroscope, a thermal compensation system is proposed and integrated in the aforementioned ASIC to actively tune the parameters in the digital trimming mechanism, which is designed in the readout ASIC. Finally, some experimental results demonstrate that the TBD of the micro-gyroscope can be compensated effectively by the proposed compensation system. PMID:24599191

Handheld ultrasound array imaging device

NASA Astrophysics Data System (ADS)

Hwang, Juin-Jet; Quistgaard, Jens

1999-06-01

A handheld ultrasound imaging device, one that weighs less than five pounds, has been developed for diagnosing trauma in the combat battlefield as well as a variety of commercial mobile diagnostic applications. This handheld device consists of four component ASICs, each is designed using the state of the art microelectronics technologies. These ASICs are integrated with a convex array transducer to allow high quality imaging of soft tissues and blood flow in real time. The device is designed to be battery driven or ac powered with built-in image storage and cineloop playback capability. Design methodologies of a handheld device are fundamentally different to those of a cart-based system. As system architecture, signal and image processing algorithm as well as image control circuit and software in this device is deigned suitably for large-scale integration, the image performance of this device is designed to be adequate to the intent applications. To elongate the battery life, low power design rules and power management circuits are incorporated in the design of each component ASIC. The performance of the prototype device is currently being evaluated for various applications such as a primary image screening tool, fetal imaging in Obstetrics, foreign object detection and wound assessment for emergency care, etc.

The design and development of low- and high-voltage ASICs for space-borne CCD cameras

NASA Astrophysics Data System (ADS)

Waltham, N.; Morrissey, Q.; Clapp, M.; Bell, S.; Jones, L.; Torbet, M.

2017-12-01

The CCD remains the pre-eminent visible and UV wavelength image sensor in space science, Earth and planetary remote sensing. However, the design of space-qualified CCD readout electronics is a significant challenge with requirements for low-volume, low-mass, low-power, high-reliability and tolerance to space radiation. Space-qualified components are frequently unavailable and up-screened commercial components seldom meet project or international space agency requirements. In this paper, we describe an alternative approach of designing and space-qualifying a series of low- and high-voltage mixed-signal application-specific integrated circuits (ASICs), the ongoing development of two low-voltage ASICs with successful flight heritage, and two new high-voltage designs. A challenging sub-system of any CCD camera is the video processing and digitisation electronics. We describe recent developments to improve performance and tolerance to radiation-induced single event latchup of a CCD video processing ASIC originally developed for NASA's Solar Terrestrial Relations Observatory and Solar Dynamics Observatory. We also describe a programme to develop two high-voltage ASICs to address the challenges presented with generating a CCD's bias voltages and drive clocks. A 0.35 μm, 50 V tolerant, CMOS process has been used to combine standard low-voltage 3.3 V transistors with high-voltage 50 V diffused MOSFET transistors that enable output buffers to drive CCD bias drains, gates and clock electrodes directly. We describe a CCD bias voltage generator ASIC that provides 24 independent and programmable 0-32 V outputs. Each channel incorporates a 10-bit digital-to-analogue converter, provides current drive of up to 20 mA into loads of 10 μF, and includes current-limiting and short-circuit protection. An on-chip telemetry system with a 12-bit analogue-to-digital converter enables the outputs and multiple off-chip camera voltages to be monitored. The ASIC can drive one or more CCDs and replaces the many discrete components required in current cameras. We also describe a CCD clock driver ASIC that provides six independent and programmable drivers with high-current capacity. The device enables various CCD clock parameters to be programmed independently, for example the clock-low and clock-high voltage levels, and the clock-rise and clock-fall times, allowing configuration for serial clock frequencies in the range 0.1-2 MHz and image clock frequencies in the range 10-100 kHz. Finally, we demonstrate the impact and importance of this technology for the development of compact, high-performance and low-power integrated focal plane electronics.

Linearity enhancement design of a 16-channel low-noise front-end readout ASIC for CdZnTe detectors

NASA Astrophysics Data System (ADS)

Zeng, Huiming; Wei, Tingcun; Wang, Jia

2017-03-01

A 16-channel front-end readout application-specific integrated circuit (ASIC) with linearity enhancement design for cadmium zinc telluride (CdZnTe) detectors is presented in this paper. The resistors in the slow shaper are realized using a high-Z circuit to obtain constant resistance value instead of using only a metal-oxide-semiconductor (MOS) transistor, thus the shaping time of the slow shaper can be kept constant for different amounts of input energies. As a result, the linearity of conversion gain is improved significantly. The ASIC was designed and fabricated in a 0.35 μm CMOS process with a die size of 2.60 mm×3.53 mm. The tested results show that a typical channel provides an equivalent noise charge (ENC) of 109.7e-+16.3e-/pF with a power consumption of 4 mW and achieves a conversion gain of 87 mV/fC with a nonlinearity of <0.4%. The linearity of conversion gain is improved by at least 86.6% as compared with the traditional approaches using the same front-end readout architecture and manufacture process. Moreover, the inconsistency among channels is <0.3%. An energy resolution of 2.975 keV (FWHM) for gamma rays of 59.5 keV was measured by connecting the ASIC to a 5 mm×5 mm ×2 mm CdZnTe detector at room temperature. The front-end readout ASIC presented in this paper achieves an outstanding linearity performance without compromising the noise, power consumption, and chip size performances.

SVGA and XGA active matrix microdisplays for head-mounted applications

NASA Astrophysics Data System (ADS)

Alvelda, Phillip; Bolotski, Michael; Brown, Imani L.

2000-03-01

The MicroDisplay Corporation's liquid crystal on silicon (LCOS) display devices are based on the union of several technologies with the extreme integration capability of conventionally fabricated CMOS substrates. The fast liquid crystal operation modes and new scalable high-performance pixel addressing architectures presented in this paper enable substantially improved color, contrast, and brightness while still satisfying the optical, packaging, and power requirements of portable applications. The entire suite of MicroDisplay's technologies was devised to create a line of mixed-signal application-specific integrated circuits (ASICs) in single-chip display systems. Mixed-signal circuits can integrate computing, memory, and communication circuitry on the same substrate as the display drivers and pixel array for a multifunctional complete system-on-a-chip. System-on-a-chip benefits also include reduced head supported weight requirements through the elimination of off-chip drive electronics.

Front End Spectroscopy ASIC for Germanium Detectors

NASA Astrophysics Data System (ADS)

Wulf, Eric

Large-area, tracking, semiconductor detectors with excellent spatial and spectral resolution enable exciting new access to soft (0.2-5 MeV) gamma-ray astrophysics. The improvements from semiconductor tracking detectors come with the burden of high density of strips and/or pixels that require high-density, low-power, spectroscopy quality readout electronics. CMOS ASIC technologies are a natural fit to this requirement and have led to high-quality readout systems for all current semiconducting tracking detectors except for germanium detectors. The Compton Spectrometer and Imager (COSI), formerly NCT, at University of California Berkeley and the Gamma-Ray Imager/Polarimeter for Solar flares (GRIPS) at Goddard Space Flight Center utilize germanium cross-strip detectors and are on the forefront of NASA's Compton telescope research with funded missions of long duration balloon flights. The development of a readout ASIC for germanium detectors would allow COSI to replace their discrete electronics readout and would enable the proposed Gamma-Ray Explorer (GRX) mission utilizing germanium strip-detectors. We propose a 3-year program to develop and test a germanium readout ASIC to TRL 5 and to integrate the ASIC readout onto a COSI detector allowing a TRL 6 demonstration for the following COSI balloon flight. Our group at NRL led a program, sponsored by another government agency, to produce and integrate a cross-strip silicon detector ASIC, designed and fabricated by Dr. De Geronimo at Brookhaven National Laboratory. The ASIC was designed to handle the large (>30 pF) capacitance of three 10 cm^2 detectors daisy-chained together. The front-end preamplifier, selectable inverter, shaping times, and gains make this ASIC compatible with a germanium cross-strip detector as well. We therefore have the opportunity and expertise to leverage the previous investment in the silicon ASIC for a new mission. A germanium strip detector ASIC will also require precise timing of the signals at the anode and cathode of the device to allow the depth of the interaction within the crystal to be determined. Dr. De Geronimo has developed similar timing circuits for CZT detector ASICs. Furthermore, the timing circuitry of the ASIC is at the very end of the analog section, simplifying and mitigating risks in the redesign. In the first year, we propose to tweak the gain settings and to add timing to the silicon ASIC to match the requirements of a germanium detector. The design specifications of the ASIC will include advice from our collaborators Dr. Boggs from COSI and Dr. Shih from GRIPS. By using a master ASIC designer to integrate his proven front-end and back-end with only minor modifications, we are maximizing the probability of success. NRL has a commercial cross-strip germanium detector with 30 pF of capacitance per strip, including the flex circuit from the detector to the outside of the cryostat. The COSI and GRIPS detectors have a similar capacitance per strip on the outside of their mechanically cooled cryostat. The second year of the program will be devoted to testing the newly fabricated germanium cross-strip ASIC with the NRL germanium detector. At the end of the second year, NASA will have a TRL 5 ASIC for germanium detectors, allowing future missions, including COSI, GRX, and GRIPS, to operate within their thermal and electrical envelopes. At the end of the third year, a detector on COSI will be instrumented with the new ASIC allowing for a TRL 6 demonstration during the following COSI balloon flight.

SpaceWire Driver Software for Special DSPs

NASA Technical Reports Server (NTRS)

Clark, Douglas; Lux, James; Nishimoto, Kouji; Lang, Minh

2003-01-01

A computer program provides a high-level C-language interface to electronics circuitry that controls a SpaceWire interface in a system based on a space qualified version of the ADSP-21020 digital signal processor (DSP). SpaceWire is a spacecraft-oriented standard for packet-switching data-communication networks that comprise nodes connected through bidirectional digital serial links that utilize low-voltage differential signaling (LVDS). The software is tailored to the SMCS-332 application-specific integrated circuit (ASIC) (also available as the TSS901E), which provides three highspeed (150 Mbps) serial point-to-point links compliant with the proposed Institute of Electrical and Electronics Engineers (IEEE) Standard 1355.2 and equivalent European Space Agency (ESA) Standard ECSS-E-50-12. In the specific application of this software, the SpaceWire ASIC was combined with the DSP processor, memory, and control logic in a Multi-Chip Module DSP (MCM-DSP). The software is a collection of low-level driver routines that provide a simple message-passing application programming interface (API) for software running on the DSP. Routines are provided for interrupt-driven access to the two styles of interface provided by the SMCS: (1) the "word at a time" conventional host interface (HOCI); and (2) a higher performance "dual port memory" style interface (COMI).

Design of the Wind Tunnel Model Communication Controller Board. Degree awarded by Christopher Newport Univ. on Dec. 1998

NASA Technical Reports Server (NTRS)

Wilson, William C.

1999-01-01

The NASA Langley Research Center's Wind Tunnel Reinvestment project plans to shrink the existing data acquisition electronics to fit inside a wind tunnel model. Space limitations within a model necessitate a distributed system of Application Specific Integrated Circuits (ASICs) rather than a centralized system based on PC boards. This thesis will focus on the design of the prototype of the communication Controller board. A portion of the communication Controller board is to be used as the basis of an ASIC design. The communication Controller board will communicate between the internal model modules and the external data acquisition computer. This board is based around an Field Programmable Gate Array (FPGA), to allow for reconfigurability. In addition to the FPGA, this board contains buffer Random Access Memory (RAM), configuration memory (EEPROM), drivers for the communications ports, and passive components.

Replication of Space-Shuttle Computers in FPGAs and ASICs

NASA Technical Reports Server (NTRS)

Ferguson, Roscoe C.

2008-01-01

A document discusses the replication of the functionality of the onboard space-shuttle general-purpose computers (GPCs) in field-programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs). The purpose of the replication effort is to enable utilization of proven space-shuttle flight software and software-development facilities to the extent possible during development of software for flight computers for a new generation of launch vehicles derived from the space shuttles. The replication involves specifying the instruction set of the central processing unit and the input/output processor (IOP) of the space-shuttle GPC in a hardware description language (HDL). The HDL is synthesized to form a "core" processor in an FPGA or, less preferably, in an ASIC. The core processor can be used to create a flight-control card to be inserted into a new avionics computer. The IOP of the GPC as implemented in the core processor could be designed to support data-bus protocols other than that of a multiplexer interface adapter (MIA) used in the space shuttle. Hence, a computer containing the core processor could be tailored to communicate via the space-shuttle GPC bus and/or one or more other buses.

Software solution for autonomous observations with H2RG detectors and SIDECAR ASICs for the RATIR camera

NASA Astrophysics Data System (ADS)

Klein, Christopher R.; Kubánek, Petr; Butler, Nathaniel R.; Fox, Ori D.; Kutyrev, Alexander S.; Rapchun, David A.; Bloom, Joshua S.; Farah, Alejandro; Gehrels, Neil; Georgiev, Leonid; González, J. Jesús; Lee, William H.; Lotkin, Gennadiy N.; Moseley, Samuel H.; Prochaska, J. Xavier; Ramirez-Ruiz, Enrico; Richer, Michael G.; Robinson, Frederick D.; Román-Zúñiga, Carlos; Samuel, Mathew V.; Sparr, Leroy M.; Tucker, Corey; Watson, Alan M.

2012-07-01

The Reionization And Transients InfraRed (RATIR) camera has been built for rapid Gamma-Ray Burst (GRB) followup and will provide quasi-simultaneous imaging in ugriZY JH. The optical component uses two 2048 × 2048 pixel Finger Lakes Imaging ProLine detectors, one optimized for the SDSS u, g, and r bands and one optimized for the SDSS i band. The infrared portion incorporates two 2048 × 2048 pixel Teledyne HgCdTe HAWAII-2RG detectors, one with a 1.7-micron cutoff and one with a 2.5-micron cutoff. The infrared detectors are controlled by Teledyne's SIDECAR (System for Image Digitization Enhancement Control And Retrieval) ASICs (Application Specific Integrated Circuits). While other ground-based systems have used the SIDECAR before, this system also utilizes Teledyne's JADE2 (JWST ASIC Drive Electronics) interface card and IDE (Integrated Development Environment). Here we present a summary of the software developed to interface the RATIR detectors with Remote Telescope System, 2nd Version (RTS2) software. RTS2 is an integrated open source package for remote observatory control under the Linux operating system and will autonomously coordinate observatory dome, telescope pointing, detector, filter wheel, focus stage, and dewar vacuum compressor operations. Where necessary we have developed custom interfaces between RTS2 and RATIR hardware, most notably for cryogenic focus stage motor drivers and temperature controllers. All detector and hardware interface software developed for RATIR is freely available and open source as part of the RTS2 distribution.

An array of virtual Frisch-grid CdZnTe detectors and a front-end application-specific integrated circuit for large-area position-sensitive gamma-ray cameras

DOE PAGES

Bolotnikov, A. E.; Ackley, K.; Camarda, G. S.; ...

2015-07-28

We developed a robust and low-cost array of virtual Frisch-grid CdZnTe (CZT) detectors coupled to a front-end readout ASIC for spectroscopy and imaging of gamma rays. The array operates as a self-reliant detector module. It is comprised of 36 close-packed 6x6x15 mm 3 detectors grouped into 3x3 sub-arrays of 2x2 detectors with the common cathodes. The front-end analog ASIC accommodates up to 36 anode and 9 cathode inputs. Several detector modules can be integrated into a single- or multi-layer unit operating as a Compton or a coded-aperture camera. We present the results from testing two fully assembled modules and readoutmore » electronics. The further enhancement of the arrays’ performance and reduction of their cost are made possible by using position-sensitive virtual Frisch-grid detectors, which allow for accurate corrections of the response of material non-uniformities caused by crystal defects.« less

Automated Design of Board and MCM Level Digital Systems.

DTIC Science & Technology

1997-10-01

Partitioning for Multicomponent Synthesis 159 Appendix K: Resource Constrained RTL Partitioning for Synthesis of Multi- FPGA Designs 169 Appendix L...digital signal processing) ar- chitectures. These target architectures, illustrated in Figure 1, can contain application-specific ASICS, FPGAs ...synthesis tools for ASIC, FPGA and MCM synthesis (Figure 8). Multicomponent Partitioning Engine The par- titioning engine is a hierarchical partitioning

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dragone, A; /SLAC; Pratte, J.F.

An ASIC for the readout of signals from X-ray Active Matrix Pixel Sensor (XAMPS) detectors to be used at the Linac Coherent Light Source (LCLS) is presented. The X-ray Pump Probe (XPP) instrument, for which the ASIC has been designed, requires a large input dynamic range on the order of 104 photons at 8 keV with a resolution of half a photon FWHM. Due to the size of the pixel and the length of the readout line, large input capacitance is expected, leading to stringent requirement on the noise optimization. Furthermore, the large number of pixels needed for a goodmore » position resolution and the fixed LCLS beam period impose limitations on the time available for the single pixel readout. Considering the periodic nature of the LCLS beam, the ASIC developed for this application is a time-variant system providing low-noise charge integration, filtering and correlated double sampling. In order to cope with the large input dynamic range a charge pump scheme implementing a zero-balance measurement method has been introduced. It provides an on chip 3-bit coarse digital conversion of the integrated charge. The residual charge is sampled using correlated double sampling into analog memory and measured with the required resolution. The first 64 channel prototype of the ASIC has been fabricated in TSMC CMOS 0.25 {micro}m technology. In this paper, the ASIC architecture and performances are presented.« less

ASICs for the Pluto Energetic Particle Spectrometer Science Investigation on NASA's New Horizons mission to Pluto

NASA Astrophysics Data System (ADS)

Paschalidis, Nicholas; McNutt, Ralph

One of the most critical challenges of the Pluto Energetic Particle Spectrometer Science Inves-tigation (PEPSSI) was to meet the science requirements with a total mass and power of ¡1.5 kg and ¡2.5 W, respectively. A key, enabling technology to achieve these goals was the exten-sive use of high-performance, low-power, application-specific integrated circuits (ASICs) for the miniaturization of the 12-channel solid state detector (SSD) readout system, the time-of-flight (TOF) system, and the power supply and housekeeping systems. The PEPSSI instrument is a TOF-versus-energy, compact particle spectrometer that provides measurements of ions and electrons from 20keV to 1MeV in a 160 x 12 solid angle field of view divided into six dual-channel sectors. TOF, constant fraction discriminator (CFD), energy, peak detector, and temperature, remote input/output (TRIO, housekeeping) ASICs were all used synergistically in the instrument enabling the high science performance within the resource constraints. The ASICs were space qualified in accord with military specifications (Class S) for total radiation dose and single-event effects (SEEs), and, most importantly, for a 2000-hour life test to increase the reliability for the long duration of the mission. PEPSSI flies on-board the New Horizons NASA spacecraft to measure pick-up ions from the Pluto's outgassing atmosphere. The space-craft was launched 19 Jan 2006 and presently is en route to Pluto, having passed Jupiter in early 2007. Closest approach to Pluto will occur in mid-July 2015. The instrument has already produced excellent measurements in interplanetary space and during the traversal of Jupiter's magnetotail in 2007.

Performance of an optical encoder based on a nondiffractive beam implemented with a specific photodetection integrated circuit and a diffractive optical element.

PubMed

Quintián, Fernando Perez; Calarco, Nicolás; Lutenberg, Ariel; Lipovetzky, José

2015-09-01

In this paper, we study the incremental signal produced by an optical encoder based on a nondiffractive beam (NDB). The NDB is generated by means of a diffractive optical element (DOE). The detection system is composed by an application specific integrated circuit (ASIC) sensor. The sensor consists of an array of eight concentric annular photodiodes, each one provided with a programmable gain amplifier. In this way, the system is able to synthesize a nonuniform detectivity. The contrast, amplitude, and harmonic content of the sinusoidal output signal are analyzed. The influence of the cross talk among the annular photodiodes is placed in evidence through the dependence of the signal contrast on the wavelength.

High-performance electronics for time-of-flight PET systems

NASA Astrophysics Data System (ADS)

Choong, W.-S.; Peng, Q.; Vu, C. Q.; Turko, B. T.; Moses, W. W.

2013-01-01

We have designed and built a high-performance readout electronics system for time-of-flight positron emission tomography (TOF PET) cameras. The electronics architecture is based on the electronics for a commercial whole-body PET camera (Siemens/CPS Cardinal electronics), modified to improve the timing performance. The fundamental contributions in the electronics that can limit the timing resolution include the constant fraction discriminator (CFD), which converts the analog electrical signal from the photo-detector to a digital signal whose leading edge is time-correlated with the input signal, and the time-to-digital converter (TDC), which provides a time stamp for the CFD output. Coincident events are identified by digitally comparing the values of the time stamps. In the Cardinal electronics, the front-end processing electronics are performed by an Analog subsection board, which has two application-specific integrated circuits (ASICs), each servicing a PET block detector module. The ASIC has a built-in CFD and TDC. We found that a significant degradation in the timing resolution comes from the ASIC's CFD and TDC. Therefore, we have designed and built an improved Analog subsection board that replaces the ASIC's CFD and TDC with a high-performance CFD (made with discrete components) and TDC (using the CERN high-performance TDC ASIC). The improved Analog subsection board is used in a custom single-ring LSO-based TOF PET camera. The electronics system achieves a timing resolution of 60 ps FWHM. Prototype TOF detector modules are read out with the electronics system and give coincidence timing resolutions of 259 ps FWHM and 156 ps FWHM for detector modules coupled to LSO and LaBr3 crystals respectively.

High-performance electronics for time-of-flight PET systems.

PubMed

Choong, W-S; Peng, Q; Vu, C Q; Turko, B T; Moses, W W

2013-01-01

We have designed and built a high-performance readout electronics system for time-of-flight positron emission tomography (TOF PET) cameras. The electronics architecture is based on the electronics for a commercial whole-body PET camera (Siemens/CPS Cardinal electronics), modified to improve the timing performance. The fundamental contributions in the electronics that can limit the timing resolution include the constant fraction discriminator (CFD), which converts the analog electrical signal from the photo-detector to a digital signal whose leading edge is time-correlated with the input signal, and the time-to-digital converter (TDC), which provides a time stamp for the CFD output. Coincident events are identified by digitally comparing the values of the time stamps. In the Cardinal electronics, the front-end processing electronics are performed by an Analog subsection board, which has two application-specific integrated circuits (ASICs), each servicing a PET block detector module. The ASIC has a built-in CFD and TDC. We found that a significant degradation in the timing resolution comes from the ASIC's CFD and TDC. Therefore, we have designed and built an improved Analog subsection board that replaces the ASIC's CFD and TDC with a high-performance CFD (made with discrete components) and TDC (using the CERN high-performance TDC ASIC). The improved Analog subsection board is used in a custom single-ring LSO-based TOF PET camera. The electronics system achieves a timing resolution of 60 ps FWHM. Prototype TOF detector modules are read out with the electronics system and give coincidence timing resolutions of 259 ps FWHM and 156 ps FWHM for detector modules coupled to LSO and LaBr 3 crystals respectively.

Application-specific coarse-grained reconfigurable array: architecture and design methodology

NASA Astrophysics Data System (ADS)

Zhou, Li; Liu, Dongpei; Zhang, Jianfeng; Liu, Hengzhu

2015-06-01

Coarse-grained reconfigurable arrays (CGRAs) have shown potential for application in embedded systems in recent years. Numerous reconfigurable processing elements (PEs) in CGRAs provide flexibility while maintaining high performance by exploring different levels of parallelism. However, a difference remains between the CGRA and the application-specific integrated circuit (ASIC). Some application domains, such as software-defined radios (SDRs), require flexibility with performance demand increases. More effective CGRA architectures are expected to be developed. Customisation of a CGRA according to its application can improve performance and efficiency. This study proposes an application-specific CGRA architecture template composed of generic PEs (GPEs) and special PEs (SPEs). The hardware of the SPE can be customised to accelerate specific computational patterns. An automatic design methodology that includes pattern identification and application-specific function unit generation is also presented. A mapping algorithm based on ant colony optimisation is provided. Experimental results on the SDR target domain show that compared with other ordinary and application-specific reconfigurable architectures, the CGRA generated by the proposed method performs more efficiently for given applications.

180-GHz Interferometric Imager

NASA Technical Reports Server (NTRS)

Kangaslahti, Pekka P.; Lim, Boon H.; O'Dwyer, Ian J.; Soria, Mary M.; Owen, Heather R.; Gaier, Todd C.; Lambrigtsen, Bjorn, H.; Tanner, Alan B.; Ruf, Christopher

2011-01-01

A 180-GHz interferometric imager uses compact receiver modules, combined high- and low-gain antennas, and ASIC (application specific integrated circuit) correlator technology, enabling continuous, all-weather observations of water vapor with 25-km resolution and 0.3-K noise in 15 minutes of observation for numerical weather forecasting and tropical storm prediction. The GeoSTAR-II prototype instrument is broken down into four major subsystems: the compact, low-noise receivers; sub-array modules; IF signal distribution; and the digitizer/correlator. Instead of the single row of antennas adopted in GeoSTAR, this version has four rows of antennas on a coarser grid. This dramatically improves the sensitivity in the desired field of view. The GeoSTAR-II instrument is a 48-element, synthetic, thinned aperture radiometer operating at 165-183 GHz. The instrument has compact receivers integrated into tiles of 16 elements in a 4x4 arrangement. These tiles become the building block of larger arrays. The tiles contain signal distribution for bias controls, IF signal, and local oscillator signals. The IF signals are digitized and correlated using an ASIC correlator to minimize power consumption. Previous synthetic aperture imagers have used comparatively large multichip modules, whereas this approach uses chip-scale modules mounted on circuit boards, which are in turn mounted on the distribution manifolds. This minimizes the number of connectors and reduces system mass. The use of ASIC technology in the digitizers and correlators leads to a power reduction close to an order of magnitude.

Role of ASIC1a in Aβ-induced synaptic alterations in the hippocampus.

PubMed

Mango, D; Nisticò, R

2018-05-01

Acid-sensing ion channels (ASICs) are widely expressed in the mammalian central nervous system where they play a key role in synaptic transmission and in specific forms of memory. On the other hand, ASICs can be persistently active under pathological conditions contributing to neuronal damage in ischemic stroke, brain trauma, epilepsy and Parkinson's disease. However, to date no experimental evidence has linked ASICs to Alzheimer's disease (AD). Aim of the present work was to investigate, in CA1 pyramidal neurons, the possible involvement of ASIC1a in the Aβ-mediated effect on metabotropic glutamate (mGlu) receptor dependent transmission. We found that, in slices pretreated with Aβ, the pharmacological blockade of ASIC1a restored the increased intrinsic excitability following group I mGlu receptor activation. This suggests that, under certain conditions, ASIC1a might further contribute to the Aβ-related depolarizing response. We have recently demonstrated that ASIC1a is also involved long-term depression (LTD) induced either by low-frequency stimulation or by application of the group I mGlu receptor agonist DHPG. Here, we have shown that psalmotoxin-1, a selective blocker of ASIC1a, rescued the DHPG-LTD facilitation associated with genetic and non-genetic models of AD. Overall, these results suggest that a functional coupling between ASIC1a and mGlu receptors occurs and might contribute to the synaptic alterations associated with AD. Copyright © 2018 Elsevier Ltd. All rights reserved.

Integrated circuit cell library

NASA Technical Reports Server (NTRS)

Whitaker, Sterling R. (Inventor); Miles, Lowell H. (Inventor)

2005-01-01

According to the invention, an ASIC cell library for use in creation of custom integrated circuits is disclosed. The ASIC cell library includes some first cells and some second cells. Each of the second cells includes two or more kernel cells. The ASIC cell library is at least 5% comprised of second cells. In various embodiments, the ASIC cell library could be 10% or more, 20% or more, 30% or more, 40% or more, 50% or more, 60% or more, 70% or more, 80% or more, 90% or more, or 95% or more comprised of second cells.

Characterization of the ePix100 prototype: a front-end ASIC for second-generation LCLS integrating hybrid pixel detectors

NASA Astrophysics Data System (ADS)

Caragiulo, P.; Dragone, A.; Markovic, B.; Herbst, R.; Nishimura, K.; Reese, B.; Herrmann, S.; Hart, P.; Blaj, G.; Segal, J.; Tomada, A.; Hasi, J.; Carini, G.; Kenney, C.; Haller, G.

2014-09-01

ePix100 is the first variant of a novel class of integrating pixel ASICs architectures optimized for the processing of signals in second generation LINAC Coherent Light Source (LCLS) X-Ray cameras. ePix100 is optimized for ultra-low noise application requiring high spatial resolution. ePix ASICs are based on a common platform composed of a random access analog matrix of pixel with global shutter, fast parallel column readout, and dedicated sigma-delta analog to digital converters per column. The ePix100 variant has 50μmx50μm pixels arranged in a 352x384 matrix, a resolution of 50e- r.m.s. and a signal range of 35fC (100 photons at 8keV). In its final version it will be able to sustain a frame rate of 1kHz. A first prototype has been fabricated and characterized and the measurement results are reported here.

Energy dispersive CdTe and CdZnTe detectors for spectral clinical CT and NDT applications

NASA Astrophysics Data System (ADS)

Barber, W. C.; Wessel, J. C.; Nygard, E.; Iwanczyk, J. S.

2015-06-01

We are developing room temperature compound semiconductor detectors for applications in energy-resolved high-flux single x-ray photon-counting spectral computed tomography (CT), including functional imaging with nanoparticle contrast agents for medical applications and non-destructive testing (NDT) for security applications. Energy-resolved photon-counting can provide reduced patient dose through optimal energy weighting for a particular imaging task in CT, functional contrast enhancement through spectroscopic imaging of metal nanoparticles in CT, and compositional analysis through multiple basis function material decomposition in CT and NDT. These applications produce high input count rates from an x-ray generator delivered to the detector. Therefore, in order to achieve energy-resolved single photon counting in these applications, a high output count rate (OCR) for an energy-dispersive detector must be achieved at the required spatial resolution and across the required dynamic range for the application. The required performance in terms of the OCR, spatial resolution, and dynamic range must be obtained with sufficient field of view (FOV) for the application thus requiring the tiling of pixel arrays and scanning techniques. Room temperature cadmium telluride (CdTe) and cadmium zinc telluride (CdZnTe) compound semiconductors, operating as direct conversion x-ray sensors, can provide the required speed when connected to application specific integrated circuits (ASICs) operating at fast peaking times with multiple fixed thresholds per pixel provided the sensors are designed for rapid signal formation across the x-ray energy ranges of the application at the required energy and spatial resolutions, and at a sufficiently high detective quantum efficiency (DQE). We have developed high-flux energy-resolved photon-counting x-ray imaging array sensors using pixellated CdTe and CdZnTe semiconductors optimized for clinical CT and security NDT. We have also fabricated high-flux ASICs with a two dimensional (2D) array of inputs for readout from the sensors. The sensors are guard ring free and have a 2D array of pixels and can be tiled in 2D while preserving pixel pitch. The 2D ASICs have four energy bins with a linear energy response across sufficient dynamic range for clinical CT and some NDT applications. The ASICs can also be tiled in 2D and are designed to fit within the active area of the sensors. We have measured several important performance parameters including: the output count rate (OCR) in excess of 20 million counts per second per square mm with a minimum loss of counts due to pulse pile-up, an energy resolution of 7 keV full width at half-maximum (FWHM) across the entire dynamic range, and a noise floor about 20 keV. This is achieved by directly interconnecting the ASIC inputs to the pixels of the CdZnTe sensors incurring very little input capacitance to the ASICs. We present measurements of the performance of the CdTe and CdZnTe sensors including the OCR, FWHM energy resolution, noise floor, as well as the temporal stability and uniformity under the rapidly varying high flux expected in CT and NDT applications.

Energy dispersive CdTe and CdZnTe detectors for spectral clinical CT and NDT applications

PubMed Central

Barber, W. C.; Wessel, J. C.; Nygard, E.; Iwanczyk, J. S.

2014-01-01

We are developing room temperature compound semiconductor detectors for applications in energy-resolved high-flux single x-ray photon-counting spectral computed tomography (CT), including functional imaging with nanoparticle contrast agents for medical applications and non destructive testing (NDT) for security applications. Energy-resolved photon-counting can provide reduced patient dose through optimal energy weighting for a particular imaging task in CT, functional contrast enhancement through spectroscopic imaging of metal nanoparticles in CT, and compositional analysis through multiple basis function material decomposition in CT and NDT. These applications produce high input count rates from an x-ray generator delivered to the detector. Therefore, in order to achieve energy-resolved single photon counting in these applications, a high output count rate (OCR) for an energy-dispersive detector must be achieved at the required spatial resolution and across the required dynamic range for the application. The required performance in terms of the OCR, spatial resolution, and dynamic range must be obtained with sufficient field of view (FOV) for the application thus requiring the tiling of pixel arrays and scanning techniques. Room temperature cadmium telluride (CdTe) and cadmium zinc telluride (CdZnTe) compound semiconductors, operating as direct conversion x-ray sensors, can provide the required speed when connected to application specific integrated circuits (ASICs) operating at fast peaking times with multiple fixed thresholds per pixel provided the sensors are designed for rapid signal formation across the x-ray energy ranges of the application at the required energy and spatial resolutions, and at a sufficiently high detective quantum efficiency (DQE). We have developed high-flux energy-resolved photon-counting x-ray imaging array sensors using pixellated CdTe and CdZnTe semiconductors optimized for clinical CT and security NDT. We have also fabricated high-flux ASICs with a two dimensional (2D) array of inputs for readout from the sensors. The sensors are guard ring free and have a 2D array of pixels and can be tiled in 2D while preserving pixel pitch. The 2D ASICs have four energy bins with a linear energy response across sufficient dynamic range for clinical CT and some NDT applications. The ASICs can also be tiled in 2D and are designed to fit within the active area of the sensors. We have measured several important performance parameters including; the output count rate (OCR) in excess of 20 million counts per second per square mm with a minimum loss of counts due to pulse pile-up, an energy resolution of 7 keV full width at half maximum (FWHM) across the entire dynamic range, and a noise floor about 20keV. This is achieved by directly interconnecting the ASIC inputs to the pixels of the CdZnTe sensors incurring very little input capacitance to the ASICs. We present measurements of the performance of the CdTe and CdZnTe sensors including the OCR, FWHM energy resolution, noise floor, as well as the temporal stability and uniformity under the rapidly varying high flux expected in CT and NDT applications. PMID:25937684

Energy dispersive CdTe and CdZnTe detectors for spectral clinical CT and NDT applications.

PubMed

Barber, W C; Wessel, J C; Nygard, E; Iwanczyk, J S

2015-06-01

We are developing room temperature compound semiconductor detectors for applications in energy-resolved high-flux single x-ray photon-counting spectral computed tomography (CT), including functional imaging with nanoparticle contrast agents for medical applications and non destructive testing (NDT) for security applications. Energy-resolved photon-counting can provide reduced patient dose through optimal energy weighting for a particular imaging task in CT, functional contrast enhancement through spectroscopic imaging of metal nanoparticles in CT, and compositional analysis through multiple basis function material decomposition in CT and NDT. These applications produce high input count rates from an x-ray generator delivered to the detector. Therefore, in order to achieve energy-resolved single photon counting in these applications, a high output count rate (OCR) for an energy-dispersive detector must be achieved at the required spatial resolution and across the required dynamic range for the application. The required performance in terms of the OCR, spatial resolution, and dynamic range must be obtained with sufficient field of view (FOV) for the application thus requiring the tiling of pixel arrays and scanning techniques. Room temperature cadmium telluride (CdTe) and cadmium zinc telluride (CdZnTe) compound semiconductors, operating as direct conversion x-ray sensors, can provide the required speed when connected to application specific integrated circuits (ASICs) operating at fast peaking times with multiple fixed thresholds per pixel provided the sensors are designed for rapid signal formation across the x-ray energy ranges of the application at the required energy and spatial resolutions, and at a sufficiently high detective quantum efficiency (DQE). We have developed high-flux energy-resolved photon-counting x-ray imaging array sensors using pixellated CdTe and CdZnTe semiconductors optimized for clinical CT and security NDT. We have also fabricated high-flux ASICs with a two dimensional (2D) array of inputs for readout from the sensors. The sensors are guard ring free and have a 2D array of pixels and can be tiled in 2D while preserving pixel pitch. The 2D ASICs have four energy bins with a linear energy response across sufficient dynamic range for clinical CT and some NDT applications. The ASICs can also be tiled in 2D and are designed to fit within the active area of the sensors. We have measured several important performance parameters including; the output count rate (OCR) in excess of 20 million counts per second per square mm with a minimum loss of counts due to pulse pile-up, an energy resolution of 7 keV full width at half maximum (FWHM) across the entire dynamic range, and a noise floor about 20keV. This is achieved by directly interconnecting the ASIC inputs to the pixels of the CdZnTe sensors incurring very little input capacitance to the ASICs. We present measurements of the performance of the CdTe and CdZnTe sensors including the OCR, FWHM energy resolution, noise floor, as well as the temporal stability and uniformity under the rapidly varying high flux expected in CT and NDT applications.

ASIC1A in neurons is critical for fear-related behaviors.

PubMed

Taugher, R J; Lu, Y; Fan, R; Ghobbeh, A; Kreple, C J; Faraci, F M; Wemmie, J A

2017-11-01

Acid-sensing ion channels (ASICs) have been implicated in fear-, addiction- and depression-related behaviors in mice. While these effects have been attributed to ASIC1A in neurons, it has been reported that ASICs may also function in nonneuronal cells. To determine if ASIC1A in neurons is indeed required, we generated neuron-specific knockout (KO) mice with floxed Asic1a alleles disrupted by Cre recombinase driven by the neuron-specific synapsin I promoter (SynAsic1a KO mice). We confirmed that Cre expression occurred in neurons, but not all neurons, and not in nonneuronal cells including astrocytes. Consequent loss of ASIC1A in some but not all neurons was verified by western blotting, immunohistochemistry and electrophysiology. We found ASIC1A was disrupted in fear circuit neurons, and SynAsic1a KO mice exhibited prominent deficits in multiple fear-related behaviors including Pavlovian fear conditioning to cue and context, predator odor-evoked freezing and freezing responses to carbon dioxide inhalation. In contrast, in the nucleus accumbens ASIC1A expression was relatively normal in SynAsic1a KO mice, and consistent with this observation, cocaine conditioned place preference (CPP) was normal. Interestingly, depression-related behavior in the forced swim test, which has been previously linked to ASIC1A in the amygdala, was also normal. Together, these data suggest neurons are an important site of ASIC1A action in fear-related behaviors, whereas other behaviors likely depend on ASIC1A in other neurons or cell types not targeted in SynAsic1a KO mice. These findings highlight the need for further work to discern the roles of ASICs in specific cell types and brain sites. © 2017 John Wiley & Sons Ltd and International Behavioural and Neural Genetics Society.

Science Enabling ASICs and FEEs for the JUICE and JEO Missions

NASA Technical Reports Server (NTRS)

Paschalidis, Nicholas; Sittler, Ed; Cooper, John; Christian, Eric; Moore, Tom

2011-01-01

A family of science enabling radiation hard Application Specific Integrated Circuits (ASICs), Front End Electronics (FEEs) and Event Processing Systems, with flight heritage on many NASA missions, is presented. These technologies play an important role in the miniaturization of instruments -and spacecraft systems- at the same time increasing performance and reducing power. The technologies target time of flight, position sensing, and energy measurements as well as standard housekeeping and telemetry functions for particle and fields instruments, but find applications in other instrument categories too. More specifically the technologies include: the TOF chip, 1D and 2D Delay Lines with MCP detectors, for high precision fast and low power time of flight and position sensing; the Energy chip for multichannel SSD readout with time over threshold and standard voltage read out for TDC and ADC digitization; Fast multi channel read out chip with commandable thresholds; the TRIO chip for multiplexed ADC and housekeeping etc. It should be mentioned that the ASICs include basic trigger capabilities to enable random event processing in a heavy background of penetrators and UV foreground. Typical instruments include time of flight versus energy and look angle particle analyzers such as: plasma composition, energetic particle, neutral atom imaging as well as fast plasma and deltaE/E ion/electron telescopes. Flight missions include: Cassini/LEMMS, IMAGE/HENA, MESSENGER/EPPS/MLA/X-ray/MLA, STEREO, PLUTO-NH/PEPSSI/LORI, IBEX-Lo, JUNO/JEDI, RBSP/RBSPICE, MMS/HPCA/EPD, SO/SIS. Given the proven capability on heavy radiation missions such as JUNO, MMS and RBSB, as well diverse long duration missions such as MESSENGER, PLUTO and Cassini, it is expected that these technologies will play an important role in the particle and fields (at least) instruments on the upcoming JUICE and JEO missions.

A Prototype PZT Matrix Transducer With Low-Power Integrated Receive ASIC for 3-D Transesophageal Echocardiography.

PubMed

Chen, Chao; Raghunathan, Shreyas B; Yu, Zili; Shabanimotlagh, Maysam; Chen, Zhao; Chang, Zu-yao; Blaak, Sandra; Prins, Christian; Ponte, Jacco; Noothout, Emile; Vos, Hendrik J; Bosch, Johan G; Verweij, Martin D; de Jong, Nico; Pertijs, Michiel A P

2016-01-01

This paper presents the design, fabrication, and experimental evaluation of a prototype lead zirconium titanate (PZT) matrix transducer with an integrated receive ASIC, as a proof of concept for a miniature three-dimensional (3-D) transesophageal echocardiography (TEE) probe. It consists of an array of 9 ×12 piezoelectric elements mounted on the ASIC via an integration scheme that involves direct electrical connections between a bond-pad array on the ASIC and the transducer elements. The ASIC addresses the critical challenge of reducing cable count, and includes front-end amplifiers with adjustable gains and micro-beamformer circuits that locally process and combine echo signals received by the elements of each 3 ×3 subarray. Thus, an order-of-magnitude reduction in the number of receive channels is achieved. Dedicated circuit techniques are employed to meet the strict space and power constraints of TEE probes. The ASIC has been fabricated in a standard 0.18-μm CMOS process and consumes only 0.44 mW/channel. The prototype has been acoustically characterized in a water tank. The ASIC allows the array to be presteered across ±37° while achieving an overall dynamic range of 77 dB. Both the measured characteristics of the individual transducer elements and the performance of the ASIC are in good agreement with expectations, demonstrating the effectiveness of the proposed techniques.

Command Interface ASIC - Analog Interface ASIC Chip Set

NASA Technical Reports Server (NTRS)

Ruiz, Baldes; Jaffe, Burton; Burke, Gary; Lung, Gerald; Pixler, Gregory; Plummer, Joe; Katanyoutanant,, Sunant; Whitaker, William

2003-01-01

A command interface application-specific integrated circuit (ASIC) and an analog interface ASIC have been developed as a chip set for remote actuation and monitoring of a collection of switches, which can be used to control generic loads, pyrotechnic devices, and valves in a high-radiation environment. The command interface ASIC (CIA) can be used alone or in combination with the analog interface ASIC (AIA). Designed primarily for incorporation into spacecraft control systems, they are also suitable for use in high-radiation terrestrial environments (e.g., in nuclear power plants and facilities that process radioactive materials). The primary role of the CIA within a spacecraft or other power system is to provide a reconfigurable means of regulating the power bus, actuating all valves, firing all pyrotechnic devices, and controlling the switching of power to all switchable loads. The CIA is a mixed-signal (analog and digital) ASIC that includes an embedded microcontroller with supporting fault-tolerant switch control and monitoring circuitry that is capable of connecting to a redundant set of interintegrated circuit (I(sup 2)C) buses. Commands and telemetry requests are communicated to the CIA. Adherence to the I(sup 2)C bus standard helps to reduce development costs by facilitating the use of previously developed, commercially available components. The AIA is a mixed-signal ASIC that includes the analog circuitry needed to connect the CIA to a custom higher powered version of the I(sup 2)C bus. The higher-powered version is designed to enable operation with bus cables longer than those contemplated in the I(sup 2)C standard. If there are multiple higher-power I(sup 2)C-like buses, then there must an AIA between the CIA and each such bus. The AIA includes two identical interface blocks: one for the side-A I(sup 2)C clock and data buses and the other for the side B buses. All the AIAs on each side are powered from a common power converter module (PCM). Sides A and B of the I(sup 2)C buses are electrically isolated from each other (see figure). They are also isolated from the CIA by use of transformer coupling of signals between the AIA blocks and the CIA.

A Muscle Fibre Conduction Velocity Tracking ASIC for Local Fatigue Monitoring.

PubMed

Koutsos, Ermis; Cretu, Vlad; Georgiou, Pantelis

2016-12-01

Electromyography analysis can provide information about a muscle's fatigue state by estimating Muscle Fibre Conduction Velocity (MFCV), a measure of the travelling speed of Motor Unit Action Potentials (MUAPs) in muscle tissue. MFCV better represents the physical manifestations of muscle fatigue, compared to the progressive compression of the myoelectic Power Spectral Density, hence it is more suitable for a muscle fatigue tracking system. This paper presents a novel algorithm for the estimation of MFCV using single threshold bit-stream conversion and a dedicated application-specified integrated circuit (ASIC) for its implementation, suitable for a compact, wearable and easy to use muscle fatigue monitor. The presented ASIC is implemented in a commercially available AMS 0.35 [Formula: see text] CMOS technology and utilizes a bit-stream cross-correlator that estimates the conduction velocity of the myoelectric signal in real time. A test group of 20 subjects was used to evaluate the performance of the developed ASIC, achieving good accuracy with an error of only 3.2% compared to Matlab.

Multi-element germanium detectors for synchrotron applications

NASA Astrophysics Data System (ADS)

Rumaiz, A. K.; Kuczewski, A. J.; Mead, J.; Vernon, E.; Pinelli, D.; Dooryhee, E.; Ghose, S.; Caswell, T.; Siddons, D. P.; Miceli, A.; Baldwin, J.; Almer, J.; Okasinski, J.; Quaranta, O.; Woods, R.; Krings, T.; Stock, S.

2018-04-01

We have developed a series of monolithic multi-element germanium detectors, based on sensor arrays produced by the Forschungzentrum Julich, and on Application-specific integrated circuits (ASICs) developed at Brookhaven. Devices have been made with element counts ranging from 64 to 384. These detectors are being used at NSLS-II and APS for a range of diffraction experiments, both monochromatic and energy-dispersive. Compact and powerful readout systems have been developed, based on the new generation of FPGA system-on-chip devices, which provide closely coupled multi-core processors embedded in large gate arrays. We will discuss the technical details of the systems, and present some of the results from them.

MiniDSS: a low-power and high-precision miniaturized digital sun sensor

NASA Astrophysics Data System (ADS)

de Boer, B. M.; Durkut, M.; Laan, E.; Hakkesteegt, H.; Theuwissen, A.; Xie, N.; Leijtens, J. L.; Urquijo, E.; Bruins, P.

2017-11-01

A high-precision and low-power miniaturized digital sun sensor has been developed at TNO. The single-chip sun sensor comprises an application specific integrated circuit (ASIC) on which an active pixel sensor (APS), read-out and processing circuitry as well as communication circuitry are combined. The design was optimized for low recurrent cost. The sensor is albedo insensitive and the prototype combines an accuracy in the order of 0.03° with a mass of just 72 g and a power consumption of only 65 mW.

Distributed Motor Controller (DMC) for Operation in Extreme Environments

NASA Technical Reports Server (NTRS)

McKinney, Colin M.; Yager, Jeremy A.; Mojarradi, Mohammad M.; Some, Rafi; Sirota, Allen; Kopf, Ted; Stern, Ryan; Hunter, Don

2012-01-01

This paper presents an extreme environment capable Distributed Motor Controller (DMC) module suitable for operation with a distributed architecture of future spacecraft systems. This motor controller is designed to be a bus-based electronics module capable of operating a single Brushless DC motor in extreme space environments: temperature (-120 C to +85 C required, -180 C to +100 C stretch goal); radiation (>;20K required, >;100KRad stretch goal); >;360 cycles of operation. Achieving this objective will result in a scalable modular configuration for motor control with enhanced reliability that will greatly lower cost during the design, fabrication and ATLO phases of future missions. Within the heart of the DMC lies a pair of cold-capable Application Specific Integrated Circuits (ASICs) and a Field Programmable Gate Array (FPGA) that enable its miniaturization and operation in extreme environments. The ASICs are fabricated in the IBM 0.5 micron Silicon Germanium (SiGe) BiCMOS process and are comprised of Analog circuitry to provide telemetry information, sensor interface, and health and status of DMC. The FPGA contains logic to provide motor control, status monitoring and spacecraft interface. The testing and characterization of these ASICs have yielded excellent functionality in cold temperatures (-135 C). The DMC module has demonstrated successful operation of a motor at temperature.

ASIC Readout Circuit Architecture for Large Geiger Photodiode Arrays

NASA Technical Reports Server (NTRS)

Vasile, Stefan; Lipson, Jerold

2012-01-01

The objective of this work was to develop a new class of readout integrated circuit (ROIC) arrays to be operated with Geiger avalanche photodiode (GPD) arrays, by integrating multiple functions at the pixel level (smart-pixel or active pixel technology) in 250-nm CMOS (complementary metal oxide semiconductor) processes. In order to pack a maximum of functions within a minimum pixel size, the ROIC array is a full, custom application-specific integrated circuit (ASIC) design using a mixed-signal CMOS process with compact primitive layout cells. The ROIC array was processed to allow assembly in bump-bonding technology with photon-counting infrared detector arrays into 3-D imaging cameras (LADAR). The ROIC architecture was designed to work with either common- anode Si GPD arrays or common-cathode InGaAs GPD arrays. The current ROIC pixel design is hardwired prior to processing one of the two GPD array configurations, and it has the provision to allow soft reconfiguration to either array (to be implemented into the next ROIC array generation). The ROIC pixel architecture implements the Geiger avalanche quenching, bias, reset, and time to digital conversion (TDC) functions in full-digital design, and uses time domain over-sampling (vernier) to allow high temporal resolution at low clock rates, increased data yield, and improved utilization of the laser beam.

DOE Office of Scientific and Technical Information (OSTI.GOV)

De Geronimo, G.; Li, S.; D'Andragora, A.

We present a front-end application-specific integrated circuit (ASIC) for a wire based time-projection-chamber (TPC) operating in liquid Argon (LAr). The LAr TPC will be used for long baseline neutrino oscillation experiments. The ASIC must provide a low-noise readout of the signals induced on the TPC wires, digitization of those signals at 2 MSamples/s, compression, buffering and multiplexing. A resolution of better than 1000 rms electrons at 200 pF input capacitance for an input range of 300 fC is required, along with low power and operation in LAr (at 87 K). We include the characterization of a commercial technology for operationmore » in the cryogenic environment and the first experimental results on the analog front end. The results demonstrate that complementary metal-oxide semiconductor transistors have lower noise and much improved dc characteristics at LAr temperature. Finally, we introduce the concept of '1/f equivalent' to model the low-frequency component of the noise spectral density, for use in the input metal-oxide semiconductor field-effect transistor optimization.« less

High-speed MCP anodes for high time resolution low-energy charged particle spectrometers

NASA Astrophysics Data System (ADS)

Saito, Yoshifumi; Yokota, Shoichiro; Asamura, Kazushi; Krieger, Amanda

2017-02-01

The time resolution of low-energy charged particle measurements is becoming higher and higher. In order to realize high time resolution measurements, a 1-D circular delay line anode has been developed as a high-speed microchannel plate (MCP) anode. The maximum count rate of the 1-D circular delay line anode is around 1 × 107/s/360°, which is much higher than the widely used resistive anode, whose maximum count rate is around 1 × 106/s/360°. In order to achieve much higher speeds, an MCP anode with application-specific integrated circuit (ASIC) has been developed. We have decided to adopt an anode configuration in which a discrete anode is formed on a ceramic substrate, and a bare ASIC chip is installed on the back of the ceramic. It has been found that the anode can detect at a high count rate of 2 × 108/s/360°. Developments in both delay line and discrete anodes, as well as readout electronics, will be reviewed.

Space Debris Detection on the HPDP, a Coarse-Grained Reconfigurable Array Architecture for Space

NASA Astrophysics Data System (ADS)

Suarez, Diego Andres; Bretz, Daniel; Helfers, Tim; Weidendorfer, Josef; Utzmann, Jens

2016-08-01

Stream processing, widely used in communications and digital signal processing applications, requires high- throughput data processing that is achieved in most cases using Application-Specific Integrated Circuit (ASIC) designs. Lack of programmability is an issue especially in space applications, which use on-board components with long life-cycles requiring applications updates. To this end, the High Performance Data Processor (HPDP) architecture integrates an array of coarse-grained reconfigurable elements to provide both flexible and efficient computational power suitable for stream-based data processing applications in space. In this work the capabilities of the HPDP architecture are demonstrated with the implementation of a real-time image processing algorithm for space debris detection in a space-based space surveillance system. The implementation challenges and alternatives are described making trade-offs to improve performance at the expense of negligible degradation of detection accuracy. The proposed implementation uses over 99% of the available computational resources. Performance estimations based on simulations show that the HPDP can amply match the application requirements.

Certification of highly complex safety-related systems.

PubMed

Reinert, D; Schaefer, M

1999-01-01

The BIA has now 15 years of experience with the certification of complex electronic systems for safety-related applications in the machinery sector. Using the example of machining centres this presentation will show the systematic procedure for verifying and validating control systems using Application Specific Integrated Circuits (ASICs) and microcomputers for safety functions. One section will describe the control structure of machining centres with control systems using "integrated safety." A diverse redundant architecture combined with crossmonitoring and forced dynamization is explained. In the main section the steps of the systematic certification procedure are explained showing some results of the certification of drilling machines. Specification reviews, design reviews with test case specification, statistical analysis, and walk-throughs are the analytical measures in the testing process. Systematic tests based on the test case specification, Electro Magnetic Interference (EMI), and environmental testing, and site acceptance tests on the machines are the testing measures for validation. A complex software driven system is always undergoing modification. Most of the changes are not safety-relevant but this has to be proven. A systematic procedure for certifying software modifications is presented in the last section of the paper.

Characteristics of a semi-custom library development system

NASA Technical Reports Server (NTRS)

Yancey, M.; Cannon, R.

1990-01-01

Standard cell and gate array macro libraries are in common use with workstation computer aided design (CAD) tools for application specific integrated circuit (ASIC) semi-custom application and have resulted in significant improvements in the overall design efficiencies as contrasted with custom design methodologies. Similar design methodology enhancements in providing for the efficient development of the library cells is an important factor in responding to the need for continuous technology improvement. The characteristics of a library development system that provides design flexibility and productivity enhancements for the library development engineer as he provides libraries in the state-of-the-art process technologies are presented. An overview of Gould's library development system ('Accolade') is also presented.

A CMOS Neural Interface for a Multichannel Vestibular Prosthesis

PubMed Central

Hageman, Kristin N.; Kalayjian, Zaven K.; Tejada, Francisco; Chiang, Bryce; Rahman, Mehdi A.; Fridman, Gene Y.; Dai, Chenkai; Pouliquen, Philippe O.; Georgiou, Julio; Della Santina, Charles C.; Andreou, Andreas G.

2015-01-01

We present a high-voltage CMOS neural-interface chip for a multichannel vestibular prosthesis (MVP) that measures head motion and modulates vestibular nerve activity to restore vision- and posture-stabilizing reflexes. This application specific integrated circuit neural interface (ASIC-NI) chip was designed to work with a commercially available microcontroller, which controls the ASIC-NI via a fast parallel interface to deliver biphasic stimulation pulses with 9-bit programmable current amplitude via 16 stimulation channels. The chip was fabricated in the ONSemi C5 0.5 micron, high-voltage CMOS process and can accommodate compliance voltages up to 12 V, stimulating vestibular nerve branches using biphasic current pulses up to 1.45 ± 0.06 mA with durations as short as 10 µs/phase. The ASIC-NI includes a dedicated digital-to-analog converter for each channel, enabling it to perform complex multipolar stimulation. The ASIC-NI replaces discrete components that cover nearly half of the 2nd generation MVP (MVP2) printed circuit board, reducing the MVP system size by 48% and power consumption by 17%. Physiological tests of the ASIC-based MVP system (MVP2A) in a rhesus monkey produced reflexive eye movement responses to prosthetic stimulation similar to those observed when using the MVP2. Sinusoidal modulation of stimulus pulse rate from 68–130 pulses per second at frequencies from 0.1 to 5 Hz elicited appropriately-directed slow phase eye velocities ranging in amplitude from 1.9–16.7°/s for the MVP2 and 2.0–14.2°/s for the MVP2A. The eye velocities evoked by MVP2 and MVP2A showed no significant difference (t-test, p = 0.034), suggesting that the MVP2A achieves performance at least as good as the larger MVP2. PMID:25974945

The GBT-SCA, a radiation tolerant ASIC for detector control and monitoring applications in HEP experiments

NASA Astrophysics Data System (ADS)

Caratelli, A.; Bonacini, S.; Kloukinas, K.; Marchioro, A.; Moreira, P.; De Oliveira, R.; Paillard, C.

2015-03-01

The future upgrades of the LHC experiments will increase the beam luminosity leading to a corresponding growth of the amounts of data to be treated by the data acquisition systems. To address these needs, the GBT (Giga-Bit Transceiver optical link [1,2]) architecture was developed to provide the simultaneous transfer of readout data, timing and trigger signals as well as slow control and monitoring data. The GBT-SCA ASIC, part of the GBT chip-set, has the purpose to distribute control and monitoring signals to the on-detector front-end electronics and perform monitoring operations of detector environmental parameters. In order to meet the requirements of different front-end ASICs used in the experiments, it provides various user-configurable interfaces capable to perform simultaneous operations. It is designed employing radiation tolerant design techniques to ensure robustness against SEUs and TID radiation effects and is implemented in a commercial 130 nm CMOS technology. This work presents the GBT-SCA architecture, the ASIC interfaces, the data transfer protocol, and its integration with the GBT optical link.

A reconfigurable multicarrier demodulator architecture

NASA Technical Reports Server (NTRS)

Kwatra, S. C.; Jamali, M. M.

1991-01-01

An architecture based on parallel and pipline design approaches has been developed for the Frequency Division Multiple Access/Time Domain Multiplexed (FDMA/TDM) conversion system. The architecture has two main modules namely the transmultiplexer and the demodulator. The transmultiplexer has two pipelined modules. These are the shared multiplexed polyphase filter and the Fast Fourier Transform (FFT). The demodulator consists of carrier, clock, and data recovery modules which are interactive. Progress on the design of the MultiCarrier Demodulator (MCD) using commercially available chips and Application Specific Integrated Circuits (ASIC) and simulation studies using Viewlogic software will be presented at the conference.

Feasibility study of a ``4H'' X-ray camera based on GaAs:Cr sensor

NASA Astrophysics Data System (ADS)

Dragone, A.; Kenney, C.; Lozinskaya, A.; Tolbanov, O.; Tyazhev, A.; Zarubin, A.; Wang, Zhehui

2016-11-01

A multilayer stacked X-ray camera concept is described. This type of technology is called `4H' X-ray cameras, where 4H stands for high-Z (Z>30) sensor, high-resolution (less than 300 micron pixel pitch), high-speed (above 100 MHz), and high-energy (above 30 keV in photon energy). The components of the technology, similar to the popular two-dimensional (2D) hybrid pixelated array detectors, consists of GaAs:Cr sensors bonded to high-speed ASICs. 4H cameras based on GaAs also use integration mode of X-ray detection. The number of layers, on the order of ten, is smaller than an earlier configuration for single-photon-counting (SPC) mode of detection [1]. High-speed ASIC based on modification to the ePix family of ASIC is discussed. Applications in X-ray free electron lasers (XFELs), synchrotrons, medicine and non-destructive testing are possible.

A fast, low power and low noise charge sensitive amplifier ASIC for a UV imaging single photon detector

NASA Astrophysics Data System (ADS)

Seljak, A.; Cumming, H. S.; Varner, G.; Vallerga, J.; Raffanti, R.; Virta, V.

2017-04-01

NASA has funded, through their Strategic Astrophysics Technology (SAT) program, the development of a cross strip (XS) microchannel plate (MCP) detector with the intention to increase its technology readiness level (TRL), enabling prototyping for future NASA missions. One aspect of the development is to convert the large and high powered laboratory Parallel Cross Strip (PXS) readout electronics into application specific integrated circuits (ASICs) to decrease their mass, volume, and power consumption (all limited resources in space) and to make them more robust to the environments of rocket launch and space. The redesign also foresees to increase the overall readout event rate, and decrease the noise contribution of the readout system. This work presents the design and verification of the first stage for the new readout system, the 16 channel charge sensitive amplifier ASIC, called the CSAv3. The single channel amplifier is composed of a charge sensitive amplifier (pre-amplifier), a pole zero cancellation circuit and a shaping amplifier. An additional output stage buffer allows polarity selection of the output analog signal. The operation of the amplifier is programmable via serial bus. It provides an equivalent noise charge (ENC) of around 600 e^- and a baseline gain of 10 mV/fC. The full scale pulse shaped output signal is confined within 100 ns, without long recovery tails, enabling up to 10 MHz periodic event rates without signal pile up. This ASIC was designed and fabricated in 130 nm, TSMC CMOS 1.2 V technology. In addition, we briefly discuss the construction of the readout system and plans for the future work.

Design and Measurement of a Low-Noise 64-Channels Front-End Readout ASIC for CdZnTe Detectors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gan, Bo; Wei, Tingcun; Gao, Wu

Cadmium zinc telluride (CdZnTe) detectors, as one of the principal detectors for the next-generation X-ray and γ-ray imagers, have high energy resolution and supporting electrode patterning in the radiation environment at room-temperature. In the present, a number of internationally renowned research institutions and universities are actively using these detector systems to carry out researches of energy spectrum analysis, medical imaging, materials characterization, high-energy physics, nuclear plant monitoring, and astrophysics. As the most important part of the readout system for the CdZnTe detector, the front-end readout application specific integrated circuit (ASIC) would have an important impact on the performances of themore » whole detector system. In order to ensure the small signal to noise ratio (SNR) and sufficient range of the output signal, it is necessary to design a front-end readout ASIC with very low noise and very high dynamic range. In addition, radiation hardness should be considered when the detectors are utilized in the space applications and high energy physics experiments. In this paper, we present measurements and performances of a novel multi-channel radiation-hardness low-noise front-end readout ASIC for CdZnTe detectors. The readout circuits in each channel consist of charge sensitive amplifier, leakage current compensation circuit (LCC), CR-RC shaper, S-K filter, inverse proportional amplifier, peak detect and hold circuit (PDH), discriminator and trigger logic, time sequence control circuit and driving buffer. All of 64 readout channels' outputs enter corresponding inputs of a 64 channel multiplexer. The output of the mux goes directly out of the chip via the output buffer. The 64-channel readout ASIC is implemented using the TSMC 0.35 μm mixed-signal CMOS technology. The die size of the prototype chip is 2.7 mm x 8 mm. At room temperature, the equivalent noise level of a typical channel reaches 66 e{sup -} (rms) at zero farad for a power consumption of 8 mW per channel. The linearity error is lower than 1% and the overall gain of the readout channel is 165 V/pC. The crosstalk between the channels is less than 3%. By connecting the readout ASIC to a CdZnTe detector, we obtained a γ-ray spectrum, the energy resolution is 5.1% at the 59.5-keV line of {sup 241}Am source. (authors)« less

Characteristics of a multichannel low-noise front-end ASIC for CZT-based small animal PET imaging

NASA Astrophysics Data System (ADS)

Gao, W.; Liu, H.; Gan, B.; Hu, Y.

2014-05-01

In this paper, we present the design and characteristics of a novel low-noise front-end readout application-specific integrated circuit dedicated to CdZnTe (CZT) detectors for a small animal PET imaging system. A low-noise readout method based on the charge integration and the delayed peak detection is proposed. An eight-channel front-end readout prototype chip is designed and implemented in a 0.35 μm CMOS process. The die size is 2.3 mm ×2.3 mm. The prototype chip is tested in different methods including electronic test, energy spectrum test and irradiation test. The input range of the ASIC is from 2000e- to 180,000e-, reflecting the energy of the gamma ray from 11.2 keV to 1 MeV. The gain of the readout channel is 65 mV/fC at the shaping time of 1 μs. The best test result of the equivalent noise charge (ENC) is 58.9 e- at zero farad plus 5.4 e- per picofarad. The nonlinearity and the crosstalk are less than 3% and less than 2%, respectively, at the room temperature. The static power dissipation is about 3 mW/channel.

DOE Office of Scientific and Technical Information (OSTI.GOV)

DE GERONIMO,G.; VERNON, E.; ACKLEY, K.

We describe an application specific integrated circuit (ASIC) for 3D position-sensitive detectors. It was optimized for pixelated CZT sensors, and it measures, corresponding to an ionizing event, the energy and timing of signals from 121 anodes and one cathode. Each channel provides low-noise charge amplification, high-order shaping, along with peak- and timing-detection. The cathode's timing can be measured in three different ways: the first is based on multiple thresholds on the charge amplifier's voltage output; the second uses the threshold crossing of a fast-shaped signal; and the third measures the peak amplitude and timing from a bipolar shaper. With itsmore » power of 2 mW per channel the ASIC measures, on a CZT sensor Connected and biased, charges up to 100 fC with an electronic resolution better than 200 e{sup -} rms. Our preliminary spectral measurements applying a simple cathode/mode ratio correction demonstrated a single-pixel resolution of 4.8 keV (0.72 %) at 662 keV, with the electronics and leakage current contributing in total with 2.1 keV.« less

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gao, W.; Yin, J.; Li, C.

This paper presents a novel front-end electronics based on a front-end ASIC with post digital filtering and calibration dedicated to CZT detectors for PET imaging. A cascade amplifier based on split-leg topology is selected to realize the charge-sensitive amplifier (CSA) for the sake of low noise performances and the simple scheme of the power supplies. The output of the CSA is connected to a variable-gain amplifier to generate the compatible signals for the A/D conversion. A multi-channel single-slope ADC is designed to sample multiple points for the digital filtering and shaping. The digital signal processing algorithms are implemented by amore » FPGA. To verify the proposed scheme, a front-end readout prototype ASIC is designed and implemented in 0.35 μm CMOS process. In a single readout channel, a CSA, a VGA, a 10-bit ADC and registers are integrated. Two dummy channels, bias circuits, and time controller are also integrated. The die size is 2.0 mm x 2.1 mm. The input range of the ASIC is from 2000 e{sup -} to 100000 e{sup -}, which is suitable for the detection of the X-and gamma ray from 11.2 keV to 550 keV. The linearity of the output voltage is less than 1 %. The gain of the readout channel is 40.2 V/pC. The static power dissipation is about 10 mW/channel. The above tested results show that the electrical performances of the ASIC can well satisfy PET imaging applications. (authors)« less

Multi-element germanium detectors for synchrotron applications

DOE PAGES

Rumaiz, A. K.; Kuczewski, A. J.; Mead, J.; ...

2018-04-27

In this paper, we have developed a series of monolithic multi-element germanium detectors, based on sensor arrays produced by the Forschungzentrum Julich, and on Application-specific integrated circuits (ASICs) developed at Brookhaven. Devices have been made with element counts ranging from 64 to 384. These detectors are being used at NSLS-II and APS for a range of diffraction experiments, both monochromatic and energy-dispersive. Compact and powerful readout systems have been developed, based on the new generation of FPGA system-on-chip devices, which provide closely coupled multi-core processors embedded in large gate arrays. Finally, we will discuss the technical details of the systems,more » and present some of the results from them.« less

Multi-element germanium detectors for synchrotron applications

DOE Office of Scientific and Technical Information (OSTI.GOV)

Rumaiz, A. K.; Kuczewski, A. J.; Mead, J.

In this paper, we have developed a series of monolithic multi-element germanium detectors, based on sensor arrays produced by the Forschungzentrum Julich, and on Application-specific integrated circuits (ASICs) developed at Brookhaven. Devices have been made with element counts ranging from 64 to 384. These detectors are being used at NSLS-II and APS for a range of diffraction experiments, both monochromatic and energy-dispersive. Compact and powerful readout systems have been developed, based on the new generation of FPGA system-on-chip devices, which provide closely coupled multi-core processors embedded in large gate arrays. Finally, we will discuss the technical details of the systems,more » and present some of the results from them.« less

A 160 μA biopotential acquisition IC with fully integrated IA and motion artifact suppression.

PubMed

Van Helleputte, Nick; Kim, Sunyoung; Kim, Hyejung; Kim, Jong Pal; Van Hoof, Chris; Yazicioglu, Refet Firat

2012-12-01

This paper proposes a 3-channel biopotential monitoring ASIC with simultaneous electrode-tissue impedance measurements which allows real-time estimation of motion artifacts on each channel using an an external μC. The ASIC features a high performance instrumentation amplifier with fully integrated sub-Hz HPF rejecting rail-to-rail electrode-offset voltages. Each readout channel further has a programmable gain amplifier and programmable 4th order low-pass filter. Time-multiplexed 12 b SAR-ADCs are used to convert all the analog data to digital. The ASIC achieves >; 115 dB of CMRR (at 50/60 Hz), a high input impedance of >; 1 GΩ and low noise (1.3 μVrms in 100 Hz). Unlike traditional methods, the ASIC is capable of actual motion artifact suppression in the analog domain before final amplification. The complete ASIC core operates from 1.2 V with 2 V digital IOs and consumes 200 μW when all 3 channels are active.

Design and fabrication of an infrared optical pyrometer ASIC as a diagnostic for shock physics experiments

NASA Astrophysics Data System (ADS)

Gordon, Jared

Optical pyrometry is the sensing of thermal radiation emitted from an object using a photoconductive device to convert photons into electrons, and is an important diagnostic tool in shock physics experiments. Data obtained from an optical pyrometer can be used to generate a blackbody curve of the material prior to and after being shocked by a high speed projectile. The sensing element consists of an InGaAs photodiode array, biasing circuitry, and multiple transimpedance amplifiers to boost the weak photocurrent from the noisy dark current into a signal that can eventually be digitized. Once the circuit elements have been defined, more often than not commercial-off-the-shelf (COTS) components are inadequate to satisfy every requirement for the diagnostic, and therefore a custom application specific design has to be considered. This thesis outlines the initial challenges with integrating the photodiode array block with multiple COTS transimpedance amplifiers onto a single chip, and offers a solution to a comparable optical pyrometer that uses the same type of photodiodes in conjunction with a re-designed transimpedance amplifier integrated onto a single chip. The final design includes a thorough analysis of the transimpedance amplifier along with modeling the circuit behavior which entails schematics, simulations, and layout. An alternative circuit is also investigated that incorporates an approach to multiplex the signals from each photodiode onto one data line and not only increases the viable real estate on the chip, but also improves the behavior of the photodiodes as they are subjected to less thermal load. The optical pyrometer application specific integrated circuit (ASIC) for shock physic experiments includes a transimpedance amplifier (TIA) with a 100 kΩ gain operating at bandwidth of 30 MHz, and an input-referred noise RMS current of 50 nA that is capable of driving a 50 Ω load.

KLauS: an ASIC for silicon photomultiplier readout and its application in a setup for production testing of scintillating tiles

NASA Astrophysics Data System (ADS)

Briggl, K.; Dorn, M.; Hagdorn, R.; Harion, T.; Schultz-Coulon, H. C.; Shen, W.

2014-02-01

KLauS is an ASIC produced in the AMS 0.35 μm SiGe process to read out the charge signals from silicon photomultipliers. Developed as an analog front-end for future calorimeters with high granularity as pursued by the AHCAL concept in the CALICE collaboration, the ASIC is designed to measure the charge signal of the sensors in a large dynamic range and with low electronic noise contributions. In order to tune the operation voltage of each sensor individually, an 8-bit DAC to tune the voltage at the input terminal within a range of 2V is implemented. Using an integrated fast comparator with low jitter, the time information can be measured with sub-nanosecond resolution. The low power consumption of the ASIC can be further decreased using power gating techniques. Future versions of KLauS are under development and will incorporate an ADC with a resolution of up to 12-bits and blocks for digital data transmission. The chip is used in a setup for mass testing and characterization of scintillator tiles for the AHCAL test beam program.

Abnormal cardiac autonomic regulation in mice lacking ASIC3.

PubMed

Cheng, Ching-Feng; Kuo, Terry B J; Chen, Wei-Nan; Lin, Chao-Chieh; Chen, Chih-Cheng

2014-01-01

Integration of sympathetic and parasympathetic outflow is essential in maintaining normal cardiac autonomic function. Recent studies demonstrate that acid-sensing ion channel 3 (ASIC3) is a sensitive acid sensor for cardiac ischemia and prolonged mild acidification can open ASIC3 and evoke a sustained inward current that fires action potentials in cardiac sensory neurons. However, the physiological role of ASIC3 in cardiac autonomic regulation is not known. In this study, we elucidate the role of ASIC3 in cardiac autonomic function using Asic3(-/-) mice. Asic3(-/-) mice showed normal baseline heart rate and lower blood pressure as compared with their wild-type littermates. Heart rate variability analyses revealed imbalanced autonomic regulation, with decreased sympathetic function. Furthermore, Asic3(-/-) mice demonstrated a blunted response to isoproterenol-induced cardiac tachycardia and prolonged duration to recover to baseline heart rate. Moreover, quantitative RT-PCR analysis of gene expression in sensory ganglia and heart revealed that no gene compensation for muscarinic acetylcholines receptors and beta-adrenalin receptors were found in Asic3(-/-) mice. In summary, we unraveled an important role of ASIC3 in regulating cardiac autonomic function, whereby loss of ASIC3 alters the normal physiological response to ischemic stimuli, which reveals new implications for therapy in autonomic nervous system-related cardiovascular diseases.

A high-throughput, multi-channel photon-counting detector with picosecond timing

NASA Astrophysics Data System (ADS)

Lapington, J. S.; Fraser, G. W.; Miller, G. M.; Ashton, T. J. R.; Jarron, P.; Despeisse, M.; Powolny, F.; Howorth, J.; Milnes, J.

2009-06-01

High-throughput photon counting with high time resolution is a niche application area where vacuum tubes can still outperform solid-state devices. Applications in the life sciences utilizing time-resolved spectroscopies, particularly in the growing field of proteomics, will benefit greatly from performance enhancements in event timing and detector throughput. The HiContent project is a collaboration between the University of Leicester Space Research Centre, the Microelectronics Group at CERN, Photek Ltd., and end-users at the Gray Cancer Institute and the University of Manchester. The goal is to develop a detector system specifically designed for optical proteomics, capable of high content (multi-parametric) analysis at high throughput. The HiContent detector system is being developed to exploit this niche market. It combines multi-channel, high time resolution photon counting in a single miniaturized detector system with integrated electronics. The combination of enabling technologies; small pore microchannel plate devices with very high time resolution, and high-speed multi-channel ASIC electronics developed for the LHC at CERN, provides the necessary building blocks for a high-throughput detector system with up to 1024 parallel counting channels and 20 ps time resolution. We describe the detector and electronic design, discuss the current status of the HiContent project and present the results from a 64-channel prototype system. In the absence of an operational detector, we present measurements of the electronics performance using a pulse generator to simulate detector events. Event timing results from the NINO high-speed front-end ASIC captured using a fast digital oscilloscope are compared with data taken with the proposed electronic configuration which uses the multi-channel HPTDC timing ASIC.

Preliminary evaluation of a novel energy-resolved photon-counting gamma ray detector.

PubMed

Meng, L-J; Tan, J W; Spartiotis, K; Schulman, T

2009-06-11

In this paper, we present the design and preliminary performance evaluation of a novel energy-resolved photon-counting (ERPC) detector for gamma ray imaging applications. The prototype ERPC detector has an active area of 4.4 cm × 4.4 cm, which is pixelated into 128 × 128 square pixels with a pitch size of 350 µm × 350µm. The current detector consists of multiple detector hybrids, each with a CdTe crystal of 1.1 cm × 2.2 cm × 1 mm, bump-bonded onto a custom-designed application-specific integrated circuit (ASIC). The ERPC ASIC has 2048 readout channels arranged in a 32 × 64 array. Each channel is equipped with pre- and shaping-amplifiers, a discriminator, peak/hold circuitry and an analog-to-digital converter (ADC) for digitizing the signal amplitude. In order to compensate for the pixel-to-pixel variation, two 8-bit digital-to-analog converters (DACs) are implemented into each channel for tuning the gain and offset. The ERPC detector is designed to offer a high spatial resolution, a wide dynamic range of 12-200 keV and a good energy resolution of 3-4 keV. The hybrid detector configuration provides a flexible detection area that can be easily tailored for different imaging applications. The intrinsic performance of a prototype ERPC detector was evaluated with various gamma ray sources, and the results are presented.

Fuzzy efficiency optimization of AC induction motors

NASA Technical Reports Server (NTRS)

Jani, Yashvant; Sousa, Gilberto; Turner, Wayne; Spiegel, Ron; Chappell, Jeff

1993-01-01

This paper describes the early states of work to implement a fuzzy logic controller to optimize the efficiency of AC induction motor/adjustable speed drive (ASD) systems running at less than optimal speed and torque conditions. In this paper, the process by which the membership functions of the controller were tuned is discussed and a controller which operates on frequency as well as voltage is proposed. The membership functions for this dual-variable controller are sketched. Additional topics include an approach for fuzzy logic to motor current control which can be used with vector-controlled drives. Incorporation of a fuzzy controller as an application-specific integrated circuit (ASIC) microchip is planned.

Engineering Trade-off Considerations Regarding Design-for-Security, Design-for-Verification, and Design-for-Test

NASA Technical Reports Server (NTRS)

Berg, Melanie; Label, Kenneth

2018-01-01

The United States government has identified that application specific integrated circuit (ASIC) and field programmable gate array (FPGA) hardware are at risk from a variety of adversary attacks. This finding affects system security and trust. Consequently, processes are being developed for system mitigation and countermeasure application. The scope of this tutorial pertains to potential vulnerabilities and countermeasures within the ASIC/FPGA design cycle. The presentation demonstrates how design practices can affect the risk for the adversary to: change circuitry, steal intellectual property, and listen to data operations. An important portion of the design cycle is assuring the design is working as specified or as expected. This is accomplished by exhaustive testing of the target design. Alternatively, it has been shown that well established schemes for test coverage enhancement (design-for-verification (DFV) and design-for-test (DFT)) can create conduits for adversary accessibility. As a result, it is essential to perform a trade between robust test coverage versus reliable design implementation. The goal of this tutorial is to explain the evolution of design practices; review adversary accessibility points due to DFV and DFT circuitry insertion (back door circuitry); and to describe common engineering trade-off considerations for test versus adversary threats.

An Efficient, FPGA-Based, Cluster Detection Algorithm Implementation for a Strip Detector Readout System in a Time Projection Chamber Polarimeter

NASA Technical Reports Server (NTRS)

Gregory, Kyle J.; Hill, Joanne E. (Editor); Black, J. Kevin; Baumgartner, Wayne H.; Jahoda, Keith

2016-01-01

A fundamental challenge in a spaceborne application of a gas-based Time Projection Chamber (TPC) for observation of X-ray polarization is handling the large amount of data collected. The TPC polarimeter described uses the APV-25 Application Specific Integrated Circuit (ASIC) to readout a strip detector. Two dimensional photoelectron track images are created with a time projection technique and used to determine the polarization of the incident X-rays. The detector produces a 128x30 pixel image per photon interaction with each pixel registering 12 bits of collected charge. This creates challenging requirements for data storage and downlink bandwidth with only a modest incidence of photons and can have a significant impact on the overall mission cost. An approach is described for locating and isolating the photoelectron track within the detector image, yielding a much smaller data product, typically between 8x8 pixels and 20x20 pixels. This approach is implemented using a Microsemi RT-ProASIC3-3000 Field-Programmable Gate Array (FPGA), clocked at 20 MHz and utilizing 10.7k logic gates (14% of FPGA), 20 Block RAMs (17% of FPGA), and no external RAM. Results will be presented, demonstrating successful photoelectron track cluster detection with minimal impact to detector dead-time.

X-ray fluorescence imaging system for fast mapping of pigment distributions in cultural heritage paintings

NASA Astrophysics Data System (ADS)

Zielińska, A.; Dąbrowski, W.; Fiutowski, T.; Mindur, B.; Wiącek, P.; Wróbel, P.

2013-10-01

Conventional X-ray fluorescence imaging technique uses a focused X-ray beam to scan through the sample and an X-ray detector with high energy resolution but no spatial resolution. The spatial resolution of the image is then determined by the size of the exciting beam, which can be obtained either from a synchrotron source or from an X-ray tube with a micro-capillary lens. Such a technique based on a pixel-by-pixel measurement is very slow and not suitable for imaging large area samples. The goal of this work is to develop a system capable of simultaneous imaging of large area samples by using a wide field uniform excitation X-ray beam and a position sensitive and energy dispersive detector. The development is driven by possible application of such a system to imaging of distributions of hidden pigments containing specific elements in cultural heritage paintings, which is of great interest for the cultural heritage research. The fluorescence radiation from the area of 10 × 10 cm2 is projected through a pinhole camera on the Gas Electron Multiplier detector of the same area. The detector is equipped with two sets of orthogonal readout strips. The strips are read out by the GEMROC Application Specific Integrated Circuits (ASIC)s, which deliver time and amplitude information for each hit. This ASIC architecture combined with a Field Programmable Gate Array (FPGA) based readout system allows us to reconstruct the position and the total energy of each detected photon for high count rates up to 5 × 106 cps. Energy resolution better than 20% FWHM for the 5.9 keV line and spatial resolution of 1 mm FWHM have been achieved for the prototype system. Although the energy resolution of the Gas Electron Multiplier (GEM) detector is, by principle, not competitive with that of specialised high energy resolution semiconductor detectors, it is sufficient for a number of applications. Compared to conventional micro-XRF techniques the developed system allows shortening of the measurement time by 2-3 orders of magnitude.

Three Realizations and Comparison of Hardware for Piezoresistive Tactile Sensors

PubMed Central

Vidal-Verdú, Fernando; Oballe-Peinado, Óscar; Sánchez-Durán, José A.; Castellanos-Ramos, Julián; Navas-González, Rafael

2011-01-01

Tactile sensors are basically arrays of force sensors that are intended to emulate the skin in applications such as assistive robotics. Local electronics are usually implemented to reduce errors and interference caused by long wires. Realizations based on standard microcontrollers, Programmable Systems on Chip (PSoCs) and Field Programmable Gate Arrays (FPGAs) have been proposed by the authors for the case of piezoresistive tactile sensors. The solution employing FPGAs is especially relevant since their performance is closer to that of Application Specific Integrated Circuits (ASICs) than that of the other devices. This paper presents an implementation of such an idea for a specific sensor. For the purpose of comparison, the circuitry based on the other devices is also made for the same sensor. This paper discusses the implementation issues, provides details regarding the design of the hardware based on the three devices and compares them. PMID:22163797

Feasibility study of a ``4H'' X-ray camera based on GaAs:Cr sensor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dragone, Angelo; Kenney, Chris; Lozinskaya, Anastassiya

Here, we describe a multilayer stacked X-ray camera concept. This type of technology is called `4H' X-ray cameras, where 4H stands for high-Z (Z>30) sensor, high-resolution (less than 300 micron pixel pitch), high-speed (above 100 MHz), and high-energy (above 30 keV in photon energy). The components of the technology, similar to the popular two-dimensional (2D) hybrid pixelated array detectors, consists of GaAs:Cr sensors bonded to high-speed ASICs. 4H cameras based on GaAs also use integration mode of X-ray detection. The number of layers, on the order of ten, is smaller than an earlier configuration for single-photon-counting (SPC) mode of detectionmore » [1]. High-speed ASIC based on modification to the ePix family of ASIC is discussed. Applications in X-ray free electron lasers (XFELs), synchrotrons, medicine and non-destructive testing are possible.« less

Feasibility study of a ``4H'' X-ray camera based on GaAs:Cr sensor

DOE PAGES

Dragone, Angelo; Kenney, Chris; Lozinskaya, Anastassiya; ...

2016-11-29

Here, we describe a multilayer stacked X-ray camera concept. This type of technology is called `4H' X-ray cameras, where 4H stands for high-Z (Z>30) sensor, high-resolution (less than 300 micron pixel pitch), high-speed (above 100 MHz), and high-energy (above 30 keV in photon energy). The components of the technology, similar to the popular two-dimensional (2D) hybrid pixelated array detectors, consists of GaAs:Cr sensors bonded to high-speed ASICs. 4H cameras based on GaAs also use integration mode of X-ray detection. The number of layers, on the order of ten, is smaller than an earlier configuration for single-photon-counting (SPC) mode of detectionmore » [1]. High-speed ASIC based on modification to the ePix family of ASIC is discussed. Applications in X-ray free electron lasers (XFELs), synchrotrons, medicine and non-destructive testing are possible.« less

A Framework for Robust Multivariable Optimization of Integrated Circuits in Space Applications

NASA Technical Reports Server (NTRS)

DuMonthier, Jeffrey; Suarez, George

2013-01-01

Application Specific Integrated Circuit (ASIC) design for space applications involves multiple challenges of maximizing performance, minimizing power and ensuring reliable operation in extreme environments. This is a complex multidimensional optimization problem which must be solved early in the development cycle of a system due to the time required for testing and qualification severely limiting opportunities to modify and iterate. Manual design techniques which generally involve simulation at one or a small number of corners with a very limited set of simultaneously variable parameters in order to make the problem tractable are inefficient and not guaranteed to achieve the best possible results within the performance envelope defined by the process and environmental requirements. What is required is a means to automate design parameter variation, allow the designer to specify operational constraints and performance goals, and to analyze the results in a way which facilitates identifying the tradeoffs defining the performance envelope over the full set of process and environmental corner cases. The system developed by the Mixed Signal ASIC Group (MSAG) at the Goddard Space Flight Center is implemented as framework of software modules, templates and function libraries. It integrates CAD tools and a mathematical computing environment, and can be customized for new circuit designs with only a modest amount of effort as most common tasks are already encapsulated. Customization is required for simulation test benches to determine performance metrics and for cost function computation. Templates provide a starting point for both while toolbox functions minimize the code required. Once a test bench has been coded to optimize a particular circuit, it is also used to verify the final design. The combination of test bench and cost function can then serve as a template for similar circuits or be re-used to migrate the design to different processes by re-running it with the new process specific device models. The system has been used in the design of time to digital converters for laser ranging and time-of-flight mass spectrometry to optimize analog, mixed signal and digital circuits such as charge sensitive amplifiers, comparators, delay elements, radiation tolerant dual interlocked (DICE) flip-flops and two of three voter gates.

On-chip enzymatic microbiofuel cell-powered integrated circuits.

PubMed

Mark, Andrew G; Suraniti, Emmanuel; Roche, Jérôme; Richter, Harald; Kuhn, Alexander; Mano, Nicolas; Fischer, Peer

2017-05-16

A variety of diagnostic and therapeutic medical technologies rely on long term implantation of an electronic device to monitor or regulate a patient's condition. One proposed approach to powering these devices is to use a biofuel cell to convert the chemical energy from blood nutrients into electrical current to supply the electronics. We present here an enzymatic microbiofuel cell whose electrodes are directly integrated into a digital electronic circuit. Glucose oxidizing and oxygen reducing enzymes are immobilized on microelectrodes of an application specific integrated circuit (ASIC) using redox hydrogels to produce an enzymatic biofuel cell, capable of harvesting electrical power from just a single droplet of 5 mM glucose solution. Optimisation of the fuel cell voltage and power to match the requirements of the electronics allow self-powered operation of the on-board digital circuitry. This study represents a step towards implantable self-powered electronic devices that gather their energy from physiological fluids.

ASIC3 Channels Integrate Agmatine and Multiple Inflammatory Signals through the Nonproton Ligand Sensing Domain

PubMed Central

2010-01-01

Background Acid-sensing ion channels (ASICs) have long been known to sense extracellular protons and contribute to sensory perception. Peripheral ASIC3 channels represent natural sensors of acidic and inflammatory pain. We recently reported the use of a synthetic compound, 2-guanidine-4-methylquinazoline (GMQ), to identify a novel nonproton sensing domain in the ASIC3 channel, and proposed that, based on its structural similarity with GMQ, the arginine metabolite agmatine (AGM) may be an endogenous nonproton ligand for ASIC3 channels. Results Here, we present further evidence for the physiological correlation between AGM and ASIC3. Among arginine metabolites, only AGM and its analog arcaine (ARC) activated ASIC3 channels at neutral pH in a sustained manner similar to GMQ. In addition to the homomeric ASIC3 channels, AGM also activated heteromeric ASIC3 plus ASIC1b channels, extending its potential physiological relevance. Importantly, the process of activation by AGM was highly sensitive to mild acidosis, hyperosmolarity, arachidonic acid (AA), lactic acid and reduced extracellular Ca2+. AGM-induced ASIC3 channel activation was not through the chelation of extracellular Ca2+ as occurs with increased lactate, but rather through a direct interaction with the newly identified nonproton ligand sensing domain. Finally, AGM cooperated with the multiple inflammatory signals to cause pain-related behaviors in an ASIC3-dependent manner. Conclusions Nonproton ligand sensing domain might represent a novel mechanism for activation or sensitization of ASIC3 channels underlying inflammatory pain-sensing under in vivo conditions. PMID:21143836

Integrated input protection against discharges for Micro Pattern Gas Detectors readout ASICs

NASA Astrophysics Data System (ADS)

Fiutowski, T.; Dąbrowski, W.; Koperny, S.; Wiącek, P.

2017-02-01

Immunity against possible random discharges inside active detector volume of MPGDs is one of the key aspects that should be addressed in the design of the front-end electronics. This issue becomes particularly critical for systems with high channel counts and high density readout employing the front-end electronics built as multichannel ASICs implemented in modern CMOS technologies, for which the breakdown voltages are in the range of a few Volts. The paper presents the design of various input protection structures integrated in the ASIC manufactured in a 350 nm CMOS process and test results using an electrical circuit to mimic discharges in the detectors.

Micro-miniature radio frequency transmitter for communication and tracking applications

DOE Office of Scientific and Technical Information (OSTI.GOV)

Crutcher, R.I.; Emery, M.S.; Falter, K.G.

1996-12-31

A micro-miniature radio frequency (rf) transmitter has been developed and demonstrated by the Oak Ridge National Laboratory. The objective of the rf transmitter development was to maximize the transmission distance while drastically shrinking the overall transmitter size, including antenna. Based on analysis and testing, an application-specific integrated circuit (ASIC) with a 16-GHz gallium arsenide (GaAs) oscillator and integrated on-chip antenna was designed and fabricated using microwave monolithic integrated circuit (MMIC) technology. Details of the development and the results of various field tests will be discussed. The rf transmitter is applicable to covert surveillance and tracking scenarios due to its smallmore » size of 2.2 x 2.2 mm, including the antenna. Additionally, the 16-GHz frequency is well above the operational range of consumer-grade radio scanners, providing a degree of protection from unauthorized interception. Variations of the transmitter design have been demonstrated for tracking and tagging beacons, transmission of digital data, and transmission of real-time analog video from a surveillance camera. Preliminary laboratory measurements indicate adaptability to direct-sequence spread-spectrum transmission, providing a low probability of intercept and/or detection. Concepts related to law enforcement applications will be presented.« less

Radiation hardness assessment of the charge-integrating hybrid pixel detector JUNGFRAU 1.0 for photon science

NASA Astrophysics Data System (ADS)

Jungmann-Smith, J. H.; Bergamaschi, A.; Brückner, M.; Cartier, S.; Dinapoli, R.; Greiffenberg, D.; Jaggi, A.; Maliakal, D.; Mayilyan, D.; Medjoubi, K.; Mezza, D.; Mozzanica, A.; Ramilli, M.; Ruder, Ch.; Schädler, L.; Schmitt, B.; Shi, X.; Tinti, G.

2015-12-01

JUNGFRAU (adJUstiNg Gain detector FoR the Aramis User station) is a two-dimensional hybrid pixel detector for photon science applications in free electron lasers, particularly SwissFEL, and synchrotron light sources. JUNGFRAU is an automatic gain switching, charge-integrating detector which covers a dynamic range of more than 104 photons of an energy of 12 keV with a good linearity, uniformity of response, and spatial resolving power. The JUNGFRAU 1.0 application-specific integrated circuit (ASIC) features a 256 × 256 pixel matrix of 75 × 75 μm2 pixels and is bump-bonded to a 320 μm thick Si sensor. Modules of 2 × 4 chips cover an area of about 4 × 8 cm2. Readout rates in excess of 2 kHz enable linear count rate capabilities of 20 MHz (at 12 keV) and 50 MHz (at 5 keV). The tolerance of JUNGFRAU to radiation is a key issue to guarantee several years of operation at free electron lasers and synchrotrons. The radiation hardness of JUNGFRAU 1.0 is tested with synchrotron radiation up to 10 MGy of delivered dose. The effect of radiation-induced changes on the noise, baseline, gain, and gain switching is evaluated post-irradiation for both the ASIC and the hybridized assembly. The bare JUNGFRAU 1.0 chip can withstand doses as high as 10 MGy with minor changes to its noise and a reduction in the preamplifier gain. The hybridized assembly, in particular the sensor, is affected by the photon irradiation which mainly shows as an increase in the leakage current. Self-healing of the system is investigated during a period of 11 weeks after the delivery of the radiation dose. Annealing radiation-induced changes by bake-out at 100 °C is investigated. It is concluded that the JUNGFRAU 1.0 pixel is sufficiently radiation-hard for its envisioned applications at SwissFEL and synchrotron beam lines.

Fabrication Security and Trust of Domain-Specific ASIC Processors

DTIC Science & Technology

2016-10-30

embedded in the design. For example , an ASIC processor potentially has a 10-1,000X performance advantage over its FPGA and GPP counterparts, but...paper by summarizing our lessons learned from this project and suggests a few research directions. II. DOMAIN-SPECIFIC ASIC PROCESSORS As Figure 1 has...sponsored by the Assistant Secretary of Defense for Research & Engineering under Air Force Contract #FA8721-05-C-0002. Opinions, interpretations

The development of the miniaturized waveform receiver with the function measuring Antenna Impedance in space plasmas

NASA Astrophysics Data System (ADS)

Ishii, H.; Kojima, H.; Fukuhara, H.; Okada, S.; Yamakawa, H.

2012-04-01

Plasma wave is one of the most essential physical quantities in the solar terrestrial physics. The role of plasma wave receiver onboard satellites is to detect plasma waves in space with a good signal to noise ratio. There are two types of plasma wave receivers, the sweep frequency analyzer and the waveform capture. While the sweep frequency analyzer provides plasma wave spectra, the waveform capture obtains waveforms with phase information that is significant in studying nonlinear phenomena. Antenna sensors to observe electric fields of the plasma waves show different features in plasmas from in vacuum. The antenna impedances have specific characteristics in the frequency domain because of the dispersion of plasmas. These antenna impedances are expressed with complex number. We need to know not only the antenna impedances but also the transfer functions of plasma wave receiver's circuits in order to calibrate observed waveforms precisely. The impedances of the electric field antennas are affected by a state of surrounding plasmas. Since satellites run through various regions with different plasma parameters, we precisely should measure the antenna impedances onboard spacecraft. On the contrary, we can obtain the plasma density and by measuring the antenna impedances. Several formulas of the antenna impedance measurement system were proposed. A synchronous detection method is used on the BepiColombo Mercury Magnetospheric Orbiter (MMO), which will be launched in 2014. The digital data are stored in the onboard memory. They are read out and converted to the analog waveforms by D/A converter. They are fed into the input of the preamplifiers of antenna sensors through a resistor. We can calculate a transfer function of the circuit by applying the synchronous detection method to the output waveform from waveform receivers and digital data as a signal source. The size of this system is same as an A5 board. In recent years, Application Specific Integrated Circuit (ASIC) is in attention which is a technique to integrate large scale and complicated circuits. Lots of ASICs have been applied to high energy astrophysics. In this paper, we show our attempt to miniaturize the antennas impedances measurement system and Waveform Capture using the analogue ASIC. We design 8bits segment D/A converter that is implemented inside the waveform receiver ASIC chip. We improve input logic of the D/A converter to generate very weak signals accurately. The designed chip realizes the measurement of the antenna impedance as well as the waveform observation in the board size of business cards.

Acid-sensing ion channels in trigeminal ganglion neurons innervating the orofacial region contribute to orofacial inflammatory pain.

PubMed

Fu, Hui; Fang, Peng; Zhou, Hai-Yun; Zhou, Jun; Yu, Xiao-Wei; Ni, Ming; Zheng, Jie-Yan; Jin, You; Chen, Jian-Guo; Wang, Fang; Hu, Zhuang-Li

2016-02-01

Orofacial pain is a common clinical symptom that is accompanied by tooth pain, migraine and gingivitis. Accumulating evidence suggests that acid-sensing ion channels (ASICs), especially ASIC3, can profoundly affect the physiological properties of nociception in peripheral sensory neurons. The aim of this study is to examine the contribution of ASICs in trigeminal ganglion (TG) neurons to orofacial inflammatory pain. A Western blot (WB), immunofluorescence assay of labelled trigeminal ganglion neurons, orofacial formalin test, cell preparation and electrophysiological experiments are performed. This study demonstrated that ASIC1, ASIC2a and ASIC3 are highly expressed in TG neurons innervating the orofacial region of rats. The amplitude of ASIC currents in these neurons increased 119.72% (for ASIC1-like current) and 230.59% (for ASIC3-like current) in the formalin-induced orofacial inflammatory pain model. In addition, WB and immunofluorescence assay demonstrated a significantly augmented expression of ASICs in orofacial TG neurons during orofacial inflammation compared with the control group. The relative protein density of ASIC1, ASIC2a and ASIC3 also increased 58.82 ± 8.92%, 45.30 ± 11.42% and 55.32 ± 14.71%, respectively, compared with the control group. Furthermore, pharmacological blockade of ASICs and genetic deletion of ASIC1 attenuated the inflammation response. These findings indicate that peripheral inflammation can induce the upregulation of ASICs in TG neurons, causing orofacial inflammatory pain. Additionally, the specific inhibitor of ASICs may have a significant analgesic effect on orofacial inflammatory pain. © 2016 John Wiley & Sons Australia, Ltd.

Multigigabit optical transceivers for high-data rate military applications

NASA Astrophysics Data System (ADS)

Catanzaro, Brian E.; Kuznia, Charlie

2012-01-01

Avionics has experienced an ever increasing demand for processing power and communication bandwidth. Currently deployed avionics systems require gigabit communication using opto-electronic transceivers connected with parallel optical fiber. Ultra Communications has developed a series of transceiver solutions combining ASIC technology with flip-chip bonding and advanced opto-mechanical molded optics. Ultra Communications custom high speed ASIC chips are developed using an SoS (silicon on sapphire) process. These circuits are flip chip bonded with sources (VCSEL arrays) and detectors (PIN diodes) to create an Opto-Electronic Integrated Circuit (OEIC). These have been combined with micro-optics assemblies to create transceivers with interfaces to standard fiber array (MT) cabling technology. We present an overview of the demands for transceivers in military applications and how new generation transceivers leverage both previous generation military optical transceivers as well as commercial high performance computing optical transceivers.

Flexible High Speed Codec (FHSC)

NASA Technical Reports Server (NTRS)

Segallis, G. P.; Wernlund, J. V.

1991-01-01

The ongoing NASA/Harris Flexible High Speed Codec (FHSC) program is described. The program objectives are to design and build an encoder decoder that allows operation in either burst or continuous modes at data rates of up to 300 megabits per second. The decoder handles both hard and soft decision decoding and can switch between modes on a burst by burst basis. Bandspreading is low since the code rate is greater than or equal to 7/8. The encoder and a hard decision decoder fit on a single application specific integrated circuit (ASIC) chip. A soft decision applique is implemented using 300 K emitter coupled logic (ECL) which can be easily translated to an ECL gate array.

Hardware description languages

NASA Technical Reports Server (NTRS)

Tucker, Jerry H.

1994-01-01

Hardware description languages are special purpose programming languages. They are primarily used to specify the behavior of digital systems and are rapidly replacing traditional digital system design techniques. This is because they allow the designer to concentrate on how the system should operate rather than on implementation details. Hardware description languages allow a digital system to be described with a wide range of abstraction, and they support top down design techniques. A key feature of any hardware description language environment is its ability to simulate the modeled system. The two most important hardware description languages are Verilog and VHDL. Verilog has been the dominant language for the design of application specific integrated circuits (ASIC's). However, VHDL is rapidly gaining in popularity.

Circuit design and simulation of a transmit beamforming ASIC for high-frequency ultrasonic imaging systems.

PubMed

Athanasopoulos, Georgios I; Carey, Stephen J; Hatfield, John V

2011-07-01

This paper describes the design of a programmable transmit beamformer application-specific integrated circuit (ASIC) with 8 channels for ultrasound imaging systems. The system uses a 20-MHz reference clock. A digital delay-locked loop (DLL) was designed with 50 variable delay elements, each of which provides a clock with different phase from a single reference. Two phase detectors compare the phase difference of the reference clock with the feedback clock, adjusting the delay of the delay elements to bring the feedback clock signal in phase with the reference clock signal. Two independent control voltages for the delay elements ensure that the mark space ratio of the pulses remain at 50%. By combining a 10- bit asynchronous counter with the delays from the DLL, each channel can be programmed to give a maximum time delay of 51 μs with 1 ns resolution. It can also give bursts of up to 64 pulses. Finally, for a single pulse, it can adjust the pulse width between 9 ns and 100 ns by controlling the current flowing through a capacitor in a one-shot circuit, for use with 40-MHz and 5-MHz transducers, respectively.

Development of the hard x-ray monitor onboard WF-MAXI

NASA Astrophysics Data System (ADS)

Arimoto, Makoto; Yatsu, Yoichi; Kawai, Nobuyuki; Ikeda, Hirokazu; Harayama, Atsushi; Takeda, Shin'ichiro; Takahashi, Tadayuki; Tomida, Hiroshi; Ueno, Shiro; Kimura, Masashi; Mihara, Tatehiro; Serino, Motoko; Tsunemi, Hiroshi; Yoshida, Atsumasa; Sakamoto, Takanori; Kohmura, Tadayoshi; Negoro, Hitoshi; Ueda, Yoshihiro

2014-07-01

WF-MAXI is a mission to detect and localize X-ray transients with short-term variability as gravitational-wave (GW) candidates including gamma-ray bursts, supernovae etc. We are planning on starting observations by WF-MAXI to be ready for the initial operation of the next generation GW telescopes (e.g., KAGRA, Advanced LIGO etc.). WF-MAXI consists of two main instruments, Soft X-ray Large Solid Angle Camera (SLC) and Hard X-ray Monitor (HXM) which totally cover 0.7 keV to 1 MeV band. HXM is a multi-channel array of crystal scintillators coupled with APDs observing photons in the hard X-ray band with an effective area of above 100 cm2. We have developed an analog application specific integrated circuit (ASIC) dedicated for the readout of 32-channel APDs' signals using 0.35 μm CMOS technology based on Open IP project and an analog amplifier was designed to achieve a low-noise readout. The developed ASIC showed a low-noise performance of 2080 e- + 2.3 e-/pF at root mean square and with a reverse-type APD coupled to a Ce:GAGG crystal a good FWHM energy resolution of 6.9% for 662 keV -rays.

Design and FPGA implementation for MAC layer of Ethernet PON

NASA Astrophysics Data System (ADS)

Zhu, Zengxi; Lin, Rujian; Chen, Jian; Ye, Jiajun; Chen, Xinqiao

2004-04-01

Ethernet passive optical network (EPON), which represents the convergence of low-cost, high-bandwidth and supporting multiple services, appears to be one of the best candidates for the next-generation access network. The work of standardizing EPON as a solution for access network is still underway in the IEEE802.3ah Ethernet in the first mile (EFM) task force. The final release is expected in 2004. Up to now, there has been no standard application specific integrated circuit (ASIC) chip available which fulfills the functions of media access control (MAC) layer of EPON. The MAC layer in EPON system has many functions, such as point-to-point emulation (P2PE), Ethernet MAC functionality, multi-point control protocol (MPCP), network operation, administration and maintenance (OAM) and link security. To implement those functions mentioned above, an embedded real-time operating system (RTOS) and a flexible programmable logic device (PLD) with an embedded processor are used. The software and hardware functions in MAC layer are realized through programming embedded microprocessor and field programmable gate array(FPGA). Finally, some experimental results are given in this paper. The method stated here can provide a valuable reference for developing EPON MAC layer ASIC.

Micro-Electromechanical Instrument and Systems Development at the Charles Stark Draper Laboratory

NASA Technical Reports Server (NTRS)

Connelly, J. H.; Gilmore, J. P.; Weinberg, M. S.

1995-01-01

Several generations of micromechanical gyros and accelerometers have been developed at Draper. Current design effort centers on tuning-fork gyro design and pendulous accelerometer configurations. Over 200 gyros of different generations have been packaged and tested. These units have successfully performed across a temperature range of -40 to 85 degrees C, and have survived 30,000-g shock tests along all axes. Draper is currently under contract to develop an integrated micro-mechanical inertial sensor assembly (MMISA) and global positioning system (GPS) receiver configuration. The ultimate projections for size, weight, and power for an MMISA, after electronic design of the application specific integrated circuit (ASIC ) is completed, are 2 x 2 x 0.5 cm, 5 gm, and less than 1 W, respectively. This paper describes the fabrication process, the current gyro and accelerometer designs, and system configurations.

Design of a Multichannel Low-Noise Front-End Readout ASIC Dedicated to CZT Detectors for PET Imaging

NASA Astrophysics Data System (ADS)

Gao, W.; Liu, H.; Gan, B.; Wei, T.; Gao, D.; Hu, Y.

2014-10-01

In this paper, we present the design and preliminary results of a novel low-noise front-end readout application-specific integrated circuit (ASIC) for a PET imaging system whose objective is to achieve the following performances: the spatial resolution of 1 mm3, the detection efficiency of 15% and the time resolution of 1 ns. A cascode amplifier based on the PMOS input transistor is selected to realize the charge-sensitive amplifier (CSA) for the sake of good noise performances. The output of the CSA is split into two branches. One is connected to a slow shaper for energy measurements. The other is connected to a fast shaper for time acquisition. A novel monostable circuits is designed to adjust the time delay of the trigger signals so that the peak value of the shaped voltages can be sampled and stored. An eight-channel front-end readout prototype chip is designed and implemented in 0.35 μm CMOS process. The die size is 2.286 mm ×2.282 mm. The input range of the ASIC is from 2000 e- to 180000 e-, reflecting to the energy level of the gamma ray from 11.2 keV to 1 MeV. The gain of the readout channel is 65 mV/fC. The tested result of ENC is 86.5 e- at zero farad plus 9.3 e- per picofarad. The nonlinearity is less than 3%. The crosstalk is less than 2%. The power dissipation is about 3 mW/channel.

ASIC or PIC? Implantable stimulators based on semi-custom CMOS technology or low-power microcontroller architecture.

PubMed

Salmons, S; Gunning, G T; Taylor, I; Grainger, S R; Hitchings, D J; Blackhurst, J; Jarvis, J C

2001-01-01

To gain a better understanding of the effects of chronic stimulation on mammalian muscles we needed to generate patterns of greater variety and complexity than simple constant-frequency or burst patterns. We describe here two approaches to the design of implantable neuromuscular stimulators that can satisfy these requirements. Devices of both types were developed and used in long-term experiments. The first device was based on a semi-custom Application Specific Integrated Circuit (ASIC). This approach has the advantage that the circuit can be completely tested at every stage of development and production, assuring a high degree of reliability. It has the drawback of inflexibility: the patterns are produced by state machines implemented in silicon, so each new set of patterns requires a fresh production run, which is costly and time-consuming. The second device was based on a commercial microcontroller (Microchip PIC16C84). The functionality of this type of circuit is specified in software rather than in silicon hardware, allowing a single device to be programmed for different functions. With the use of features designed to improve fault-tolerance we found this approach to be as reliable as that based on ASICs. The encapsulated devices can easily be accommodated subcutaneously on the flank of a rabbit and a recent version is small enough to implant into the peritoneal cavity of rats. The current devices are programmed with a predetermined set of 12 patterns before assembly; the desired pattern is selected after implantation with an electronic flash gun. The operating current drain is less than 40 microA.

Development of a low-energy charged particle detector with on-anode ASIC for in-situ plasma measurement in the Earth's magnetosphere

NASA Astrophysics Data System (ADS)

Saito, M.; Saito, Y.; Mukai, T.; Asamura, K.

2009-06-01

The future magnetospheric exploration missions (ex. SCOPE: cross Scale COupling in the Plasma universE) aim to obtain electron 3D distribution function with very fast time resolution below 10 ms to investigate the electron dynamics that is regarded as pivotal in understanding the space plasma phenomena such as magnetic reconnection. This can be achieved by developing a new plasma detector system which is fast in signal processing with small size, light weight and low power consumption. The new detector system consists of stacked micro channel plates and a position sensitive multi-anode detector with on-anode analogue ASIC (Application Specific Integrated Circuits). Multi-anode system usually suffers from false signals caused by mainly two effects. One is the effect of the electrostatic crosstalk between the discrete anodes since our new detector consists of many adjacent anodes with small gaps to increase the detection areas. Our experimental results show that there exists electrostatic crosstalk effect of approximately 10% from the adjacent anodes. The effect of 10% electrostatic crosstalk can be effectively avoided by a suitable discrimination level of the signal processing circuit. Non negligible charge cloud size on the anode also causes false counts. Optimized ASIC for in-situ plasma measurement in the Earth's magnetosphere is under development. The initial electron cloud at the MCP output has angular divergence. Furthermore, space charge effects may broaden the size of the charge cloud. We have obtained the charge cloud size both experimentally and theoretically. Our test model detector shows expected performance that is explained by our studies above.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Rahman, Taufiq, E-mail: mtur2@cam.ac.uk; Smith, Ewan St. John

Highlights: • We have made a reasonable model of rat ASIC3 using published structure of chicken ASIC1. • We have docked sea anemone toxin APETx2 on the model. • We have identified two putative sites for toxin binding. • We have argued for plausibility one site over the other. • We have identified the residues that are likely to be critical for APETx2–ASIC3 interaction. - Abstract: Acid sensing ion channels (ASICs) are proton-gated cation channels that are expressed throughout the nervous system and have been implicated in mediating sensory perception of noxious stimuli. Amongst the six ASIC isoforms, ASIC1a, 1b,more » 2a and 3 form proton-gated homomers, which differ in their activation and inactivation kinetics, expression profiles and pharmacological modulation; protons do not gate ASIC2b and ASIC4. As with many other ion channels, structure-function studies of ASICs have been greatly aided by the discovery of some toxins that act in isoform-specific ways. ASIC3 is predominantly expressed by sensory neurons of the peripheral nervous system where it acts to detect acid as a noxious stimulus and thus plays an important role in nociception. ASIC3 is the only ASIC subunit that is inhibited by the sea anemone (Anthopleura elegantissima)-derived toxin APETx2. However, the molecular mechanism by which APETx2 interacts with ASIC3 remains largely unknown. In this study, we made a homology model of ASIC3 and used extensive protein–protein docking to predict for the first time, the probable sites of APETx2 interaction on ASIC3. Additionally, using computational alanine scanning, we also suggest the ‘hot-spots’ that are likely to be critical for ASIC3–APETx2 interaction.« less

Digital Radar-Signal Processors Implemented in FPGAs

NASA Technical Reports Server (NTRS)

Berkun, Andrew; Andraka, Ray

2004-01-01

High-performance digital electronic circuits for onboard processing of return signals in an airborne precipitation- measuring radar system have been implemented in commercially available field-programmable gate arrays (FPGAs). Previously, it was standard practice to downlink the radar-return data to a ground station for postprocessing a costly practice that prevents the nearly-real-time use of the data for automated targeting. In principle, the onboard processing could be performed by a system of about 20 personal- computer-type microprocessors; relative to such a system, the present FPGA-based processor is much smaller and consumes much less power. Alternatively, the onboard processing could be performed by an application-specific integrated circuit (ASIC), but in comparison with an ASIC implementation, the present FPGA implementation offers the advantages of (1) greater flexibility for research applications like the present one and (2) lower cost in the small production volumes typical of research applications. The generation and processing of signals in the airborne precipitation measuring radar system in question involves the following especially notable steps: The system utilizes a total of four channels two carrier frequencies and two polarizations at each frequency. The system uses pulse compression: that is, the transmitted pulse is spread out in time and the received echo of the pulse is processed with a matched filter to despread it. The return signal is band-limited and digitally demodulated to a complex baseband signal that, for each pulse, comprises a large number of samples. Each complex pair of samples (denoted a range gate in radar terminology) is associated with a numerical index that corresponds to a specific time offset from the beginning of the radar pulse, so that each such pair represents the energy reflected from a specific range. This energy and the average echo power are computed. The phase of each range bin is compared to the previous echo by complex conjugate multiplication to obtain the mean Doppler shift (and hence the mean and variance of the velocity of precipitation) of the echo at that range.

Interface and protocol development for STS read-out ASIC in the CBM experiment at FAIR

NASA Astrophysics Data System (ADS)

Kasinski, Krzysztof; Zabolotny, Wojciech; Szczygiel, Robert

2014-11-01

This paper presents a proposal of a protocol for communication between the read-out integrated circuit for the STS (Silicon Tracking System) and the Data Processing Board (DPB) at CBM (Compressed Baryonic Matter) experiment at FAIR, GSI (Helmholtzzentrum fuer Schwerionenforschung GmbH) in Germany. The application background, objectives and proposed solution is presented.

An investigation of nonuniform dose deposition from an electron beam

NASA Astrophysics Data System (ADS)

Lilley, William; Luu, Kieu X.

1994-08-01

In a search for an explanation of nonuniform electron-beam dose deposition, the integrated tiger series (ITS) of coupled electron/photon Monte Carlo transport codes was used to calculate energy deposition in the package materials of an application-specific integrated circuit (ASIC) while the thicknesses of some of the materials were varied. The thicknesses of three materials that were in the path of an electron-beam pulse were varied independently so that analysis could determine how the radiation dose measurements using thermoluminescent dosimeters (TLD's) would be affected. The three materials were chosen because they could vary during insertion of the die into the package or during the process of taking dose measurements. The materials were aluminum, HIPEC (a plastic), and silver epoxy. The calculations showed that with very small variations in thickness, the silver epoxy had a large effect on the dose uniformity over the area of the die.

A second generation 50 Mbps VLSI level zero processing system prototype

NASA Technical Reports Server (NTRS)

Harris, Jonathan C.; Shi, Jeff; Speciale, Nick; Bennett, Toby

1994-01-01

Level Zero Processing (LZP) generally refers to telemetry data processing functions performed at ground facilities to remove all communication artifacts from instrument data. These functions typically include frame synchronization, error detection and correction, packet reassembly and sorting, playback reversal, merging, time-ordering, overlap deletion, and production of annotated data sets. The Data Systems Technologies Division (DSTD) at Goddard Space Flight Center (GSFC) has been developing high-performance Very Large Scale Integration Level Zero Processing Systems (VLSI LZPS) since 1989. The first VLSI LZPS prototype demonstrated 20 Megabits per second (Mbp's) capability in 1992. With a new generation of high-density Application-specific Integrated Circuits (ASIC) and a Mass Storage System (MSS) based on the High-performance Parallel Peripheral Interface (HiPPI), a second prototype has been built that achieves full 50 Mbp's performance. This paper describes the second generation LZPS prototype based upon VLSI technologies.

Inhibition of Acid Sensing Ion Channel Currents by Lidocaine in Cultured Mouse Cortical Neurons

PubMed Central

Lin, Jun; Chu, Xiangping; Maysami, Samaneh; Li, Minghua; Si, Hongfang; Cottrell, James E.; Simon, Roger P.; Xiong, Zhigang

2012-01-01

BACKGROUND Lidocaine is a local anesthetic that has multiple pharmacological effects including antiarrhythmia, antinociception, and neuroprotection. Acid sensing ion channels (ASICs) are proton-gated cation channels that belong to the epithelial sodium channel/degenerin superfamily. Activation of ASICs by protons results in sodium and calcium influx. ASICs have been implicated in various physiological processes including learning/memory, nociception, and in acidosis-mediated neuron injury. In this study, we examined the effect of lidocaine on ASICs in cultured mouse cortical neurons. METHODS ASIC currents were activated and recorded using a whole-cell patch-clamp technique in cultured mouse cortical neurons. The effects of lidocaine at different concentrations were examined. To determine whether the inhibition of lidocaine on ASIC currents is subunit specific, we examined the effect of lidocaine on homomeric ASIC1a and ASIC2a currents expressed in Chinese hamster ovary cells. RESULTS Lidocaine significantly inhibits the ASIC currents in mouse cortical neurons. The inhibition was reversible and dose dependent. A detectable effect was noticed at a concentration of 0.3 mM lidocaine. At 30 mM, ASIC current was inhibited by approximately 90%. Analysis of the complete dose-response relationship yielded a half-maximal inhibitory concentration of 11.79 ± 1.74 mM and a Hill coefficient of 2.7 ± 0.5 (n = 10). The effect is rapid and does not depend on pH. In Chinese hamster ovary cells expressing different ASIC subunits, lidocaine inhibits the ASIC1a current without affecting the ASIC2a current. CONCLUSION ASIC currents are significantly inhibited by lidocaine. Our finding reveals a new pharmacological effect of lidocaine in neurons. PMID:21385979

DSB Task Force on Cyber Supply Chain

DTIC Science & Technology

2017-04-01

seeking to exploit a maliciously inserted vulnerability must execute each step in the kill chain:  Intelligence and planning: gathering...are intended to take a comprehensive approach in considering all aspects of system security, including cybersecurity , and address initial steps to...specific integrated circuits (ASICs). That need is likely to grow for systems that support intelligent or autonomous capabilities. The current

A comparative study of the time performance between NINO and FlexToT ASICs

NASA Astrophysics Data System (ADS)

Sarasola, I.; Nemallapudi, M. V.; Gundacker, S.; Sánchez, D.; Gascón, D.; Rato, P.; Marín, J.; Auffray, E.

2017-04-01

Universitat de Barcelona (UB) and CIEMAT have designed the FlexToT ASIC for the front-end readout of SiPM-based scintillator detectors. This ASIC is aimed at time of flight (ToF) positron emission tomography (PET) applications. In this work we have evaluated the time performance of the FlexToT v2 ASIC compared to the NINO ASIC, a fast ASIC developped at CERN. NINO electronics give 64 ps sigma for single-photon time resolution (SPTR) and 93 ps FWHM for coincidence time resolution (CTR) with 2 × 2 × 5 mm3 LSO:Ce,Ca crystals and S13360-3050CS SiPMs. Using the same SiPMs and crystals, the FlexToT v2 ASIC yields 91 ps sigma for SPTR and 123 ps FWHM for CTR. Despite worse time performace than NINO, FlexToT v2 features lower power consumption (11 vs. 27 mW/ch) and linear ToT energy measurement.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Huan, E-mail: wanghuan7@126.com; Institute for Liver Diseases of Anhui Medical University; Wang, Ying-hong

Metabolic syndrome characterized by hyperglycemia contributes to nonalcoholic steatohepatitis-associated liver fibrosis. This study was to investigate the effects of Acid-sensing ion Channel 1a (ASIC1a) on the process of liver fibrosis under hyperglycemia. Results showed that high glucose significantly worsen the pathology of liver fibrosis in vivo. In vitro, high glucose stimulated proliferation, activation and extracellular matrix (ECM) production in HSCs, and enhanced the effect of PDGF-BB on the activation and proliferation of HSCs. These effects could be attenuated by ASIC1a specific inhibitor Psalmotoxin-1(PcTx1) or specific ShRNA for ASIC1a through Notch1/Hes-1 pathways. These data indicate that ASIC1a plays an important role in diabetesmore » complication liver fibrosis. - Highlights: • Hyperglycemia is a risk factor for the process of liver fibrosis. • ASIC1a may be a key factor linking between high glucose and liver fibrosis. • Notch1/Hes-1 may involve to the process of liver fibrosis under hyperglycemia.« less

The role of periodontal ASIC3 in orofacial pain induced by experimental tooth movement in rats.

PubMed

Gao, Meiya; Long, Hu; Ma, Wenqiang; Liao, Lina; Yang, Xin; Zhou, Yang; Shan, Di; Huang, Renhuan; Jian, Fan; Wang, Yan; Lai, Wenli

2016-12-01

This study aimed to clarify the roles of Acid-sensing ion channel 3 (ASIC3) in orofacial pain following experimental tooth movement. Sixty male Sprague-Dawley rats were divided into the experimental group (40g, n = 30) and the sham group (0g, n = 30). Closed coil springs were ligated between maxillary incisor and molars to achieve experimental tooth movement. Rat grimace scale (RGS) scores were assessed at 0, 1, 3, 5, 7, and 14 days after the placement of the springs. ASIC3 immunostaining was performed and the expression levels of ASIC3 were measured through integrated optical density/area in Image-Pro Plus 6.0. Moreover, 18 rats were divided into APETx2 group (n = 6), amiloride group (n = 6), and vehicle group (n = 6), and RGS scores were obtained compared among them to verify the roles of ASIC3 in orofacial pain following tooth movement. ASIC3 expression levels became significantly higher in the experimental group than in sham group on 1, 3, and 5 days and became similar on 7 and 14 days. Pain levels (RGS scores) increased in both groups and were significantly higher in the experimental group on 1, 3, 5, and 7 days and were similar on 14 days. Periodontal ASIC3 expression levels were correlated with orofacial pain levels following experimental tooth movement. Periodontal administrations of ASIC3 antagonists (APETx2 and amiloride) could alleviate pain. This study needs to be better evidenced by RNA interference of ASIC3 in periodontal tissues in rats following experimental tooth movement. Moreover, we hope further studies would concentrate on the pain perception of ASIC3 knockout (ASIC3 -/- ) mice. Our results suggest that periodontal ASIC3 plays an important role in orofacial pain induced by experimental tooth movement. © The Author 2015. Published by Oxford University Press on behalf of the European Orthodontic Society. All rights reserved. For permissions, please email: journals.permissions@oup.com.

Optogenetic analysis of a nociceptor neuron and network reveals ion channels acting downstream of primary sensors.

PubMed

Husson, Steven J; Costa, Wagner Steuer; Wabnig, Sebastian; Stirman, Jeffrey N; Watson, Joseph D; Spencer, W Clay; Akerboom, Jasper; Looger, Loren L; Treinin, Millet; Miller, David M; Lu, Hang; Gottschalk, Alexander

2012-05-08

Nociception generally evokes rapid withdrawal behavior in order to protect the tissue from harmful insults. Most nociceptive neurons responding to mechanical insults display highly branched dendrites, an anatomy shared by Caenorhabditis elegans FLP and PVD neurons, which mediate harsh touch responses. Although several primary molecular nociceptive sensors have been characterized, less is known about modulation and amplification of noxious signals within nociceptor neurons. First, we analyzed the FLP/PVD network by optogenetics and studied integration of signals from these cells in downstream interneurons. Second, we investigated which genes modulate PVD function, based on prior single-neuron mRNA profiling of PVD. Selectively photoactivating PVD, FLP, and downstream interneurons via Channelrhodopsin-2 (ChR2) enabled the functional dissection of this nociceptive network, without interfering signals by other mechanoreceptors. Forward or reverse escape behaviors were determined by PVD and FLP, via integration by command interneurons. To identify mediators of PVD function, acting downstream of primary nocisensor molecules, we knocked down PVD-specific transcripts by RNAi and quantified light-evoked PVD-dependent behavior. Cell-specific disruption of synaptobrevin or voltage-gated Ca(2+) channels (VGCCs) showed that PVD signals chemically to command interneurons. Knocking down the DEG/ENaC channel ASIC-1 and the TRPM channel GTL-1 indicated that ASIC-1 may extend PVD's dynamic range and that GTL-1 may amplify its signals. These channels act cell autonomously in PVD, downstream of primary mechanosensory molecules. Our work implicates TRPM channels in modifying excitability of and DEG/ENaCs in potentiating signal output from a mechano-nociceptor neuron. ASIC-1 and GTL-1 homologs, if functionally conserved, may denote valid targets for novel analgesics. Copyright © 2012 Elsevier Ltd. All rights reserved.

Ultrasonic Fingerprint Sensor With Transmit Beamforming Based on a PMUT Array Bonded to CMOS Circuitry.

PubMed

Jiang, Xiaoyue; Tang, Hao-Yen; Lu, Yipeng; Ng, Eldwin J; Tsai, Julius M; Boser, Bernhard E; Horsley, David A

2017-09-01

In this paper, we present a single-chip 65 ×42 element ultrasonic pulse-echo fingerprint sensor with transmit (TX) beamforming based on piezoelectric micromachined ultrasonic transducers directly bonded to a CMOS readout application-specific integrated circuit (ASIC). The readout ASIC was realized in a standard 180-nm CMOS process with a 24-V high-voltage transistor option. Pulse-echo measurements are performed column-by-column in sequence using either one column or five columns to TX the ultrasonic pulse at 20 MHz. TX beamforming is used to focus the ultrasonic beam at the imaging plane where the finger is located, increasing the ultrasonic pressure and narrowing the 3-dB beamwidth to [Formula: see text], a factor of 6.4 narrower than nonbeamformed measurements. The surface of the sensor is coated with a poly-dimethylsiloxane (PDMS) layer to provide good acoustic impedance matching to skin. Scanning laser Doppler vibrometry of the PDMS surface was used to map the ultrasonic pressure field at the imaging surface, demonstrating the expected increase in pressure, and reduction in beamwidth. Imaging experiments were conducted using both PDMS phantoms and real fingerprints. The average image contrast is increased by a factor of 1.5 when beamforming is used.

Performance overview of the Euclid infrared focal plane detector subsystems

NASA Astrophysics Data System (ADS)

Waczynski, A.; Barbier, R.; Cagiano, S.; Chen, J.; Cheung, S.; Cho, H.; Cillis, A.; Clémens, J.-C.; Dawson, O.; Delo, G.; Farris, M.; Feizi, A.; Foltz, R.; Hickey, M.; Holmes, W.; Hwang, T.; Israelsson, U.; Jhabvala, M.; Kahle, D.; Kan, Em.; Kan, Er.; Loose, M.; Lotkin, G.; Miko, L.; Nguyen, L.; Piquette, E.; Powers, T.; Pravdo, S.; Runkle, A.; Seiffert, M.; Strada, P.; Tucker, C.; Turck, K.; Wang, F.; Weber, C.; Williams, J.

2016-07-01

In support of the European space agency (ESA) Euclid mission, NASA is responsible for the evaluation of the H2RG mercury cadmium telluride (MCT) detectors and electronics assemblies fabricated by Teledyne imaging systems. The detector evaluation is performed in the detector characterization laboratory (DCL) at the NASA Goddard space flight center (GSFC) in close collaboration with engineers and scientists from the jet propulsion laboratory (JPL) and the Euclid project. The Euclid near infrared spectrometer and imaging photometer (NISP) will perform large area optical and spectroscopic sky surveys in the 0.9-2.02 μm infrared (IR) region. The NISP instrument will contain sixteen detector arrays each coupled to a Teledyne SIDECAR application specific integrated circuit (ASIC). The focal plane will operate at 100K and the SIDECAR ASIC will be in close proximity operating at a slightly higher temperature of 137K. This paper will describe the test configuration, performance tests and results of the latest engineering run, also known as pilot run 3 (PR3), consisting of four H2RG detectors operating simultaneously. Performance data will be presented on; noise, spectral quantum efficiency, dark current, persistence, pixel yield, pixel to pixel uniformity, linearity, inter pixel crosstalk, full well and dynamic range, power dissipation, thermal response and unit cell input sensitivity.

Extracellular Spermine Exacerbates Ischemic Neuronal Injury through Sensitization of ASIC1a Channels to Extracellular Acidosis

PubMed Central

Duan, Bo; Wang, Yi-Zhi; Yang, Tao; Chu, Xiang-Ping; Yu, Ye; Huang, Yu; Cao, Hui; Hansen, Jillian; Simon, Roger P.; Zhu, Michael X.; Xiong, Zhi-Gang; Xu, Tian-Le

2011-01-01

Ischemic brain injury is a major problem associated with stroke. It has been increasingly recognized that acid-sensing ion channels (ASICs) contribute significantly to ischemic neuronal damage, but the underlying mechanism has remained elusive. Here, we show that extracellular spermine, one of the endogenous polyamines, exacerbates ischemic neuronal injury through sensitization of ASIC1a channels to extracellular acidosis. Pharmacological blockade of ASIC1a or deletion of the ASIC1 gene greatly reduces the enhancing effect of spermine in ischemic neuronal damage both in cultures of dissociated neurons and in a mouse model of focal ischemia. Mechanistically, spermine profoundly reduces desensitization of ASIC1a by slowing down desensitization in the open state, shifting steady-state desensitization to more acidic pH, and accelerating recovery between repeated periods of acid stimulation. Spermine-mediated potentiation of ASIC1a activity is occluded by PcTX1 (psalmotoxin 1), a specific ASIC1a inhibitor binding to its extracellular domain. Functionally, the enhanced channel activity is accompanied by increased acid-induced neuronal membrane depolarization and cytoplasmic Ca2+ overload, which may partially explain the exacerbated neuronal damage caused by spermine. More importantly, blocking endogenous spermine synthesis significantly attenuates ischemic brain injury mediated by ASIC1a but not that by NMDA receptors. Thus, extracellular spermine contributes significantly to ischemic neuronal injury through enhancing ASIC1a activity. Our data suggest new neuroprotective strategies for stroke patients via inhibition of polyamine synthesis and subsequent spermine–ASIC interaction. PMID:21307247

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jungmann-Smith, J. H., E-mail: jsmith@magnet.fsu.edu; Bergamaschi, A.; Brückner, M.

JUNGFRAU (adJUstiNg Gain detector FoR the Aramis User station) is a two-dimensional hybrid pixel detector for photon science applications in free electron lasers, particularly SwissFEL, and synchrotron light sources. JUNGFRAU is an automatic gain switching, charge-integrating detector which covers a dynamic range of more than 10{sup 4} photons of an energy of 12 keV with a good linearity, uniformity of response, and spatial resolving power. The JUNGFRAU 1.0 application-specific integrated circuit (ASIC) features a 256 × 256 pixel matrix of 75 × 75 μm{sup 2} pixels and is bump-bonded to a 320 μm thick Si sensor. Modules of 2 ×more » 4 chips cover an area of about 4 × 8 cm{sup 2}. Readout rates in excess of 2 kHz enable linear count rate capabilities of 20 MHz (at 12 keV) and 50 MHz (at 5 keV). The tolerance of JUNGFRAU to radiation is a key issue to guarantee several years of operation at free electron lasers and synchrotrons. The radiation hardness of JUNGFRAU 1.0 is tested with synchrotron radiation up to 10 MGy of delivered dose. The effect of radiation-induced changes on the noise, baseline, gain, and gain switching is evaluated post-irradiation for both the ASIC and the hybridized assembly. The bare JUNGFRAU 1.0 chip can withstand doses as high as 10 MGy with minor changes to its noise and a reduction in the preamplifier gain. The hybridized assembly, in particular the sensor, is affected by the photon irradiation which mainly shows as an increase in the leakage current. Self-healing of the system is investigated during a period of 11 weeks after the delivery of the radiation dose. Annealing radiation-induced changes by bake-out at 100 °C is investigated. It is concluded that the JUNGFRAU 1.0 pixel is sufficiently radiation-hard for its envisioned applications at SwissFEL and synchrotron beam lines.« less

Progress in a novel architecture for high performance processing

NASA Astrophysics Data System (ADS)

Zhang, Zhiwei; Liu, Meng; Liu, Zijun; Du, Xueliang; Xie, Shaolin; Ma, Hong; Ding, Guangxin; Ren, Weili; Zhou, Fabiao; Sun, Wenqin; Wang, Huijuan; Wang, Donglin

2018-04-01

The high performance processing (HPP) is an innovative architecture which targets on high performance computing with excellent power efficiency and computing performance. It is suitable for data intensive applications like supercomputing, machine learning and wireless communication. An example chip with four application-specific integrated circuit (ASIC) cores which is the first generation of HPP cores has been taped out successfully under Taiwan Semiconductor Manufacturing Company (TSMC) 40 nm low power process. The innovative architecture shows great energy efficiency over the traditional central processing unit (CPU) and general-purpose computing on graphics processing units (GPGPU). Compared with MaPU, HPP has made great improvement in architecture. The chip with 32 HPP cores is being developed under TSMC 16 nm field effect transistor (FFC) technology process and is planed to use commercially. The peak performance of this chip can reach 4.3 teraFLOPS (TFLOPS) and its power efficiency is up to 89.5 gigaFLOPS per watt (GFLOPS/W).

A closed-loop compressive-sensing-based neural recording system.

PubMed

Zhang, Jie; Mitra, Srinjoy; Suo, Yuanming; Cheng, Andrew; Xiong, Tao; Michon, Frederic; Welkenhuysen, Marleen; Kloosterman, Fabian; Chin, Peter S; Hsiao, Steven; Tran, Trac D; Yazicioglu, Firat; Etienne-Cummings, Ralph

2015-06-01

This paper describes a low power closed-loop compressive sensing (CS) based neural recording system. This system provides an efficient method to reduce data transmission bandwidth for implantable neural recording devices. By doing so, this technique reduces a majority of system power consumption which is dissipated at data readout interface. The design of the system is scalable and is a viable option for large scale integration of electrodes or recording sites onto a single device. The entire system consists of an application-specific integrated circuit (ASIC) with 4 recording readout channels with CS circuits, a real time off-chip CS recovery block and a recovery quality evaluation block that provides a closed feedback to adaptively adjust compression rate. Since CS performance is strongly signal dependent, the ASIC has been tested in vivo and with standard public neural databases. Implemented using efficient digital circuit, this system is able to achieve >10 times data compression on the entire neural spike band (500-6KHz) while consuming only 0.83uW (0.53 V voltage supply) additional digital power per electrode. When only the spikes are desired, the system is able to further compress the detected spikes by around 16 times. Unlike other similar systems, the characteristic spikes and inter-spike data can both be recovered which guarantes a >95% spike classification success rate. The compression circuit occupied 0.11mm(2)/electrode in a 180nm CMOS process. The complete signal processing circuit consumes <16uW/electrode. Power and area efficiency demonstrated by the system make it an ideal candidate for integration into large recording arrays containing thousands of electrode. Closed-loop recording and reconstruction performance evaluation further improves the robustness of the compression method, thus making the system more practical for long term recording.

Simulation environment based on the Universal Verification Methodology

NASA Astrophysics Data System (ADS)

Fiergolski, A.

2017-01-01

Universal Verification Methodology (UVM) is a standardized approach of verifying integrated circuit designs, targeting a Coverage-Driven Verification (CDV). It combines automatic test generation, self-checking testbenches, and coverage metrics to indicate progress in the design verification. The flow of the CDV differs from the traditional directed-testing approach. With the CDV, a testbench developer, by setting the verification goals, starts with an structured plan. Those goals are targeted further by a developed testbench, which generates legal stimuli and sends them to a device under test (DUT). The progress is measured by coverage monitors added to the simulation environment. In this way, the non-exercised functionality can be identified. Moreover, the additional scoreboards indicate undesired DUT behaviour. Such verification environments were developed for three recent ASIC and FPGA projects which have successfully implemented the new work-flow: (1) the CLICpix2 65 nm CMOS hybrid pixel readout ASIC design; (2) the C3PD 180 nm HV-CMOS active sensor ASIC design; (3) the FPGA-based DAQ system of the CLICpix chip. This paper, based on the experience from the above projects, introduces briefly UVM and presents a set of tips and advices applicable at different stages of the verification process-cycle.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jeggle, Pia; Smith, Ewan St. J.; Stewart, Andrew P.

ASIC and ENaC are co-expressed in various cell types, and there is evidence for a close association between them. Here, we used atomic force microscopy (AFM) to determine whether ASIC1a and ENaC subunits are able to form cross-clade hybrid ion channels. ASIC1a and ENaC could be co-isolated from detergent extracts of tsA 201 cells co-expressing the two subunits. Isolated proteins were incubated with antibodies against ENaC and Fab fragments against ASIC1a. AFM imaging revealed proteins that were decorated by both an antibody and a Fab fragment with an angle of ∼120° between them, indicating the formation of ASIC1a/ENaC heterotrimers. -more » Highlights: • There is evidence for a close association between ASIC and ENaC. • We used AFM to test whether ASIC1a and ENaC subunits form cross-clade ion channels. • Isolated proteins were incubated with subunit-specific antibodies and Fab fragments. • Some proteins were doubly decorated at ∼120° by an antibody and a Fab fragment. • Our results indicate the formation of ASIC1a/ENaC heterotrimers.« less

Dural afferents express acid-sensing ion channels: a role for decreased meningeal pH in migraine headache.

PubMed

Yan, Jin; Edelmayer, Rebecca M; Wei, Xiaomei; De Felice, Milena; Porreca, Frank; Dussor, Gregory

2011-01-01

Migraine headache is one of the most common neurological disorders. The pathological conditions that directly initiate afferent pain signaling are poorly understood. In trigeminal neurons retrogradely labeled from the cranial meninges, we have recorded pH-evoked currents using whole-cell patch-clamp electrophysiology. Approximately 80% of dural-afferent neurons responded to a pH 6.0 application with a rapidly activating and rapidly desensitizing ASIC-like current that often exceeded 20nA in amplitude. Inward currents were observed in response to a wide range of pH values and 30% of the neurons exhibited inward currents at pH 7.1. These currents led to action potentials in 53%, 30% and 7% of the dural afferents at pH 6.8, 6.9 and 7.0, respectively. Small decreases in extracellular pH were also able to generate sustained window currents and sustained membrane depolarizations. Amiloride, a non-specific blocker of ASIC channels, inhibited the peak currents evoked upon application of decreased pH while no inhibition was observed upon application of TRPV1 antagonists. The desensitization time constant of pH 6.0-evoked currents in the majority of dural afferents was less than 500ms which is consistent with that reported for ASIC3 homomeric or heteromeric channels. Finally, application of pH 5.0 synthetic-interstitial fluid to the dura produced significant decreases in facial and hind-paw withdrawal threshold, an effect blocked by amiloride but not TRPV1 antagonists, suggesting that ASIC activation produces migraine-related behavior in vivo. These data provide a cellular mechanism by which decreased pH in the meninges following ischemic or inflammatory events directly excites afferent pain-sensing neurons potentially contributing to migraine headache. Copyright © 2010 International Association for the Study of Pain. Published by Elsevier B.V. All rights reserved.

Advanced testing of the DEPFET minimatrix particle detector

NASA Astrophysics Data System (ADS)

Andricek, L.; Kodyš, P.; Koffmane, C.; Ninkovic, J.; Oswald, C.; Richter, R.; Ritter, A.; Rummel, S.; Scheirich, J.; Wassatsch, A.

2012-01-01

The DEPFET (DEPleted Field Effect Transistor) is an active pixel particle detector with a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) integrated in each pixel, providing first amplification stage of readout electronics. Excellent signal over noise performance is gained this way. The DEPFET sensor will be used as a vertex detector in the Belle II experiment at SuperKEKB, electron-positron collider in Japan. The vertex detector will be composed of two layers of pixel detectors (DEPFET) and four layers of strip detectors. The DEPFET sensor requires switching and current readout circuits for its operation. These circuits have been designed as ASICs (Application Specific Integrated Circuits) in several different versions, but they provide insufficient flexibility for precise detector testing. Therefore, a test system with a flexible control cycle range and minimal noise has been designed for testing and characterizing of small detector prototypes (Minimatrices). Sensors with different design layouts and thicknesses are produced in order to evaluate and select the one with the best performance for the Belle II application. Description of the test system as well as measurement results are presented.

Downsampling Photodetector Array with Windowing

NASA Technical Reports Server (NTRS)

Patawaran, Ferze D.; Farr, William H.; Nguyen, Danh H.; Quirk, Kevin J.; Sahasrabudhe, Adit

2012-01-01

In a photon counting detector array, each pixel in the array produces an electrical pulse when an incident photon on that pixel is detected. Detection and demodulation of an optical communication signal that modulated the intensity of the optical signal requires counting the number of photon arrivals over a given interval. As the size of photon counting photodetector arrays increases, parallel processing of all the pixels exceeds the resources available in current application-specific integrated circuit (ASIC) and gate array (GA) technology; the desire for a high fill factor in avalanche photodiode (APD) detector arrays also precludes this. Through the use of downsampling and windowing portions of the detector array, the processing is distributed between the ASIC and GA. This allows demodulation of the optical communication signal incident on a large photon counting detector array, as well as providing architecture amenable to algorithmic changes. The detector array readout ASIC functions as a parallel-to-serial converter, serializing the photodetector array output for subsequent processing. Additional downsampling functionality for each pixel is added to this ASIC. Due to the large number of pixels in the array, the readout time of the entire photodetector is greater than the time between photon arrivals; therefore, a downsampling pre-processing step is done in order to increase the time allowed for the readout to occur. Each pixel drives a small counter that is incremented at every detected photon arrival or, equivalently, the charge in a storage capacitor is incremented. At the end of a user-configurable counting period (calculated independently from the ASIC), the counters are sampled and cleared. This downsampled photon count information is then sent one counter word at a time to the GA. For a large array, processing even the downsampled pixel counts exceeds the capabilities of the GA. Windowing of the array, whereby several subsets of pixels are designated for processing, is used to further reduce the computational requirements. The grouping of the designated pixel frame as the photon count information is sent one word at a time to the GA, the aggregation of the pixels in a window can be achieved by selecting only the designated pixel counts from the serial stream of photon counts, thereby obviating the need to store the entire frame of pixel count in the gate array. The pixel count se quence from each window can then be processed, forming lower-rate pixel statistics for each window. By having this processing occur in the GA rather than in the ASIC, future changes to the processing algorithm can be readily implemented. The high-bandwidth requirements of a photon counting array combined with the properties of the optical modulation being detected by the array present a unique problem that has not been addressed by current CCD or CMOS sensor array solutions.

Si-strip photon counting detectors for contrast-enhanced spectral mammography

NASA Astrophysics Data System (ADS)

Chen, Buxin; Reiser, Ingrid; Wessel, Jan C.; Malakhov, Nail; Wawrzyniak, Gregor; Hartsough, Neal E.; Gandhi, Thulasi; Chen, Chin-Tu; Iwanczyk, Jan S.; Barber, William C.

2015-08-01

We report on the development of silicon strip detectors for energy-resolved clinical mammography. Typically, X-ray integrating detectors based on scintillating cesium iodide CsI(Tl) or amorphous selenium (a-Se) are used in most commercial systems. Recently, mammography instrumentation has been introduced based on photon counting Si strip detectors. The required performance for mammography in terms of the output count rate, spatial resolution, and dynamic range must be obtained with sufficient field of view for the application, thus requiring the tiling of pixel arrays and particular scanning techniques. Room temperature Si strip detector, operating as direct conversion x-ray sensors, can provide the required speed when connected to application specific integrated circuits (ASICs) operating at fast peaking times with multiple fixed thresholds per pixel, provided that the sensors are designed for rapid signal formation across the X-ray energy ranges of the application. We present our methods and results from the optimization of Si-strip detectors for contrast enhanced spectral mammography. We describe the method being developed for quantifying iodine contrast using the energy-resolved detector with fixed thresholds. We demonstrate the feasibility of the method by scanning an iodine phantom with clinically relevant contrast levels.

The electronics system for the LBNL positron emission mammography (PEM) camera

NASA Astrophysics Data System (ADS)

Moses, W. W.; Young, J. W.; Baker, K.; Jones, W.; Lenox, M.; Ho, M. H.; Weng, M.

2001-06-01

Describes the electronics for a high-performance positron emission mammography (PEM) camera. It is based on the electronics for a human brain positron emission tomography (PET) camera (the Siemens/CTI HRRT), modified to use a detector module that incorporates a photodiode (PD) array. An application-specified integrated circuit (ASIC) services the photodetector (PD) array, amplifying its signal and identifying the crystal of interaction. Another ASIC services the photomultiplier tube (PMT), measuring its output and providing a timing signal. Field-programmable gate arrays (FPGAs) and lookup RAMs are used to apply crystal-by-crystal correction factors and measure the energy deposit and the interaction depth (based on the PD/PMT ratio). Additional FPGAs provide event multiplexing, derandomization, coincidence detection, and real-time rebinning. Embedded PC/104 microprocessors provide communication, real-time control, and configure the system. Extensive use of FPGAs make the overall design extremely flexible, allowing many different functions (or design modifications) to be realized without hardware changes. Incorporation of extensive onboard diagnostics, implemented in the FPGAs, is required by the very high level of integration and density achieved by this system.

A Compact, Multi-view Net Flux Radiometer for Future Uranus and Neptune Probes

NASA Technical Reports Server (NTRS)

Aslam, S.; Amato, M.; Atkinson, D. H.; Hewagama, T.; Jennings, D. E.; Nixon, C. A.; Mousis, O.

2017-01-01

A Net Flux Radiometer (NFR) is presented that can be included in an atmospheric structure instrument suite for future probe missions to the icy giants Uranus and Neptune. The baseline design has two spectral channels i.e., a solar channel (0.4-to-3.5 m) and a thermal channel (4-to-300 m). The NFR is capable of viewing five distinct viewing angles during the descent. Non-imaging Winston cones with band-pass filters are used for each spectral channel and to define a 5 angular acceptance. Uncooled thermopile detectors are used in each spectral channel and are read out using a custom radiation hard application specific integrated circuit (ASIC). The baseline design can easily be changed to increase the number of detector channels from two to seven.

LSST camera readout chip ASPIC: test tools

NASA Astrophysics Data System (ADS)

Antilogus, P.; Bailly, Ph; Jeglot, J.; Juramy, C.; Lebbolo, H.; Martin, D.; Moniez, M.; Tocut, V.; Wicek, F.

2012-02-01

The LSST camera will have more than 3000 video-processing channels. The readout of this large focal plane requires a very compact readout chain. The correlated ''Double Sampling technique'', which is generally used for the signal readout of CCDs, is also adopted for this application and implemented with the so called ''Dual Slope integrator'' method. We have designed and implemented an ASIC for LSST: the Analog Signal Processing asIC (ASPIC). The goal is to amplify the signal close to the output, in order to maximize signal to noise ratio, and to send differential outputs to the digitization. Others requirements are that each chip should process the output of half a CCD, that is 8 channels and should operate at 173 K. A specific Back End board has been designed especially for lab test purposes. It manages the clock signals, digitizes the analog differentials outputs of ASPIC and stores data into a memory. It contains 8 ADCs (18 bits), 512 kwords memory and an USB interface. An FPGA manages all signals from/to all components on board and generates the timing sequence for ASPIC. Its firmware is written in Verilog and VHDL languages. Internals registers permit to define various tests parameters of the ASPIC. A Labview GUI allows to load or update these registers and to check a proper operation. Several series of tests, including linearity, noise and crosstalk, have been performed over the past year to characterize the ASPIC at room and cold temperature. At present, the ASPIC, Back-End board and CCD detectors are being integrated to perform a characterization of the whole readout chain.

Antinociception produced by Thalassia testudinum extract BM-21 is mediated by the inhibition of acid sensing ionic channels by the phenolic compound thalassiolin B

PubMed Central

2011-01-01

Background Acid-sensing ion channels (ASICs) have a significant role in the sensation of pain and constitute an important target for the search of new antinociceptive drugs. In this work we studied the antinociceptive properties of the BM-21 extract, obtained from the sea grass Thalassia testudinum, in chemical and thermal models of nociception in mice. The action of the BM-21 extract and the major phenolic component isolated from this extract, a sulphated flavone glycoside named thalassiolin B, was studied in the chemical nociception test and in the ASIC currents of the dorsal root ganglion (DRG) neurons obtained from Wistar rats. Results Behavioral antinociceptive experiments were made on male OF-1 mice. Single oral administration of BM-21 produced a significant inhibition of chemical nociception caused by acetic acid and formalin (specifically during its second phase), and increased the reaction time in the hot plate test. Thalassiolin B reduced the licking behavior during both the phasic and tonic phases in the formalin test. It was also found that BM-21 and thalassiolin B selectively inhibited the fast desensitizing (τ < 400 ms) ASIC currents in DRG neurons obtained from Wistar rats, with a nonsignificant action on ASIC currents with a slow desensitizing time-course. The action of thalassiolin B shows no pH or voltage dependence nor is it modified by steady-state ASIC desensitization or voltage. The high concentration of thalassiolin B in the extract may account for the antinociceptive action of BM-21. Conclusions To our knowledge, this is the first report of an ASIC-current inhibitor derived of a marine-plant extract, and in a phenolic compound. The antinociceptive effects of BM-21 and thalassiolin B may be partially because of this action on the ASICs. That the active components of the extract are able to cross the blood-brain barrier gives them an additional advantage for future uses as tools to study pain mechanisms with a potential therapeutic application. PMID:21261973

Antinociception produced by Thalassia testudinum extract BM-21 is mediated by the inhibition of acid sensing ionic channels by the phenolic compound thalassiolin B.

PubMed

Garateix, Anoland; Salceda, Emilio; Menéndez, Roberto; Regalado, Erik L; López, Omar; García, Teidy; Morales, Ruth A; Laguna, Abilio; Thomas, Olivier P; Soto, Enrique

2011-01-24

Acid-sensing ion channels (ASICs) have a significant role in the sensation of pain and constitute an important target for the search of new antinociceptive drugs. In this work we studied the antinociceptive properties of the BM-21 extract, obtained from the sea grass Thalassia testudinum, in chemical and thermal models of nociception in mice. The action of the BM-21 extract and the major phenolic component isolated from this extract, a sulphated flavone glycoside named thalassiolin B, was studied in the chemical nociception test and in the ASIC currents of the dorsal root ganglion (DRG) neurons obtained from Wistar rats. Behavioral antinociceptive experiments were made on male OF-1 mice. Single oral administration of BM-21 produced a significant inhibition of chemical nociception caused by acetic acid and formalin (specifically during its second phase), and increased the reaction time in the hot plate test. Thalassiolin B reduced the licking behavior during both the phasic and tonic phases in the formalin test. It was also found that BM-21 and thalassiolin B selectively inhibited the fast desensitizing (τ < 400 ms) ASIC currents in DRG neurons obtained from Wistar rats, with a nonsignificant action on ASIC currents with a slow desensitizing time-course. The action of thalassiolin B shows no pH or voltage dependence nor is it modified by steady-state ASIC desensitization or voltage. The high concentration of thalassiolin B in the extract may account for the antinociceptive action of BM-21. To our knowledge, this is the first report of an ASIC-current inhibitor derived of a marine-plant extract, and in a phenolic compound. The antinociceptive effects of BM-21 and thalassiolin B may be partially because of this action on the ASICs. That the active components of the extract are able to cross the blood-brain barrier gives them an additional advantage for future uses as tools to study pain mechanisms with a potential therapeutic application.

Cryogenic and radiation hard ASIC design for large format NIR/SWIR detector

NASA Astrophysics Data System (ADS)

Gao, Peng; Dupont, Benoit; Dierickx, Bart; Müller, Eric; Verbruggen, Geert; Gielis, Stijn; Valvekens, Ramses

2014-10-01

An ASIC is developed to control and data quantization for large format NIR/SWIR detector arrays. Both cryogenic and space radiation environment issue are considered during the design. Therefore it can be integrated in the cryogenic chamber, which reduces significantly the vast amount of long wires going in and out the cryogenic chamber, i.e. benefits EMI and noise concerns, as well as the power consumption of cooling system and interfacing circuits. In this paper, we will describe the development of this prototype ASIC for image sensor driving and signal processing as well as the testing in both room and cryogenic temperature.

Cryogenic and radiation-hard asic for interfacing large format NIR/SWIR detector arrays

NASA Astrophysics Data System (ADS)

Gao, Peng; Dupont, Benoit; Dierickx, Bart; Müller, Eric; Verbruggen, Geert; Gielis, Stijn; Valvekens, Ramses

2017-11-01

For scientific and earth observation space missions, weight and power consumption is usually a critical factor. In order to obtain better vehicle integration, efficiency and controllability for large format NIR/SWIR detector arrays, a prototype ASIC is designed. It performs multiple detector array interfacing, power regulation and data acquisition operations inside the cryogenic chambers. Both operation commands and imaging data are communicated via the SpaceWire interface which will significantly reduce the number of wire goes in and out the cryogenic chamber. This "ASIC" prototype is realized in 0.18um CMOS technology and is designed for radiation hardness.

TOFPET2: a high-performance ASIC for time and amplitude measurements of SiPM signals in time-of-flight applications

NASA Astrophysics Data System (ADS)

Di Francesco, A.; Bugalho, R.; Oliveira, L.; Pacher, L.; Rivetti, A.; Rolo, M.; Silva, J. C.; Silva, R.; Varela, J.

2016-03-01

We present a readout and digitization ASIC featuring low-noise and low-power for time-of flight (TOF) applications using SiPMs. The circuit is designed in standard CMOS 110 nm technology, has 64 independent channels and is optimized for time-of-flight measurement in Positron Emission Tomography (TOF-PET). The input amplifier is a low impedance current conveyor based on a regulated common-gate topology. Each channel has quad-buffered analogue interpolation TDCs (time binning 20 ps) and charge integration ADCs with linear response at full scale (1500 pC). The signal amplitude can also be derived from the measurement of time-over-threshold (ToT). Simulation results show that for a single photo-electron signal with charge 200 (550) fC generated by a SiPM with 320 pF capacitance the circuit has 24 (30) dB SNR, 75(39) ps r.m.s. resolution, and 4(8) mW power consumption. The event rate is 600 kHz per channel, with up to 2 MHz dark counts rejection.

Design and Implementation of a New Real-Time Frequency Sensor Used as Hardware Countermeasure

PubMed Central

Jiménez-Naharro, Raúl; Gómez-Galán, Juan Antonio; Sánchez-Raya, Manuel; Gómez-Bravo, Fernando; Pedro-Carrasco, Manuel

2013-01-01

A new digital countermeasure against attacks related to the clock frequency is –presented. This countermeasure, known as frequency sensor, consists of a local oscillator, a transition detector, a measurement element and an output block. The countermeasure has been designed using a full-custom technique implemented in an Application-Specific Integrated Circuit (ASIC), and the implementation has been verified and characterized with an integrated design using a 0.35 μm standard Complementary Metal Oxide Semiconductor (CMOS) technology (Very Large Scale Implementation—VLSI implementation). The proposed solution is configurable in resolution time and allowed range of period, achieving a minimum resolution time of only 1.91 ns and an initialization time of 5.84 ns. The proposed VLSI implementation shows better results than other solutions, such as digital ones based on semi-custom techniques and analog ones based on band pass filters, all design parameters considered. Finally, a counter has been used to verify the good performance of the countermeasure in avoiding the success of an attack. PMID:24008285

Thermal Neutron Imaging Using A New Pad-Based Position Sensitive Neutron Detector

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dioszegi I.; Vanier P.E.; Salwen C.

2016-10-29

Thermal neutrons (with mean energy of 25 meV) have a scattering mean free path of about 20 m in air. Therefore it is feasible to find localized thermal neutron sources up to ~30 m standoff distance using thermal neutron imaging. Coded aperture thermal neutron imaging was developed in our laboratory in the nineties, using He-3 filled wire chambers. Recently a new generation of coded-aperture neutron imagers has been developed. In the new design the ionization chamber has anode and cathode planes, where the anode is composed of an array of individual pads. The charge is collected on each of themore » individual 5x5 mm2 anode pads, (48x48 in total, corresponding to 24x24 cm2 sensitive area) and read out by application specific integrated circuits (ASICs). The high sensitivity of the ASICs allows unity gain operation mode. The new design has several advantages for field deployable imaging applications, compared to the previous generation of wire-grid based neutron detectors. Among these are the rugged design, lighter weight and use of non-flammable stopping gas. For standoff localization of thermalized neutron sources a low resolution (11x11 pixel) coded aperture mask has been fabricated. Using the new larger area detector and the coarse resolution mask we performed several standoff experiments using moderated californium and plutonium sources at Idaho National Laboratory. In this paper we will report on the development and performance of the new pad-based neutron camera, and present long range coded-aperture images of various thermalized neutron sources.« less

Fine-Pitch Semiconductor Detector for the FOXSI Mission

NASA Astrophysics Data System (ADS)

Ishikawa, S.; Saito, S.; Tajima, H.; Tanaka, T.; Watanabe, S.; Odaka, H.; Fukuyama, T.; Kokubun, M.; Takahashi, T.; Terada, Y.; Krucker, S.; Christe, S.; McBride, S.; Glesener, L.

2011-08-01

The Focusing Optics X-ray Solar Imager (FOXSI) is a NASA sounding rocket mission which will study particle acceleration and coronal heating on the Sun through high sensitivity observations in the hard X-ray energy band (5-15 keV). Combining high-resolution focusing X-ray optics and fine-pitch imaging sensors, FOXSI will achieve superior sensitivity; two orders of magnitude better than that of the RHESSI satellite. As the focal plane detector, a Double-sided Si Strip Detector (DSSD) with a front-end ASIC (Application Specific Integrated Circuit) will fulfill the scientific requirements of spatial and energy resolution, low energy threshold and time resolution. We have designed and fabricated a DSSD with a thickness of 500 μm and a dimension of 9.6 mm × 9.6 mm, containing 128 strips with a pitch of 75 μm, which corresponds to 8 arcsec at the focal length of 2 m. We also developed a low-noise ASIC specified to FOXSI. The detector was successfully operated in the laboratory at a temperature of -20°C and with an applied bias voltage of 300 V. Extremely good energy resolutions of 430 eV for the p-side and 1.6 keV for the n-side at a 14 keV line were achieved for the detector. We also demonstrated fine-pitch imaging successfully by obtaining a shadow image. Hence the implementation of scientific requirements was confirmed.

Acid-sensing ion channels contribute to chemosensitivity of breathing-related neurons of the nucleus of the solitary tract.

PubMed

Huda, Rafiq; Pollema-Mays, Sarah L; Chang, Zheng; Alheid, George F; McCrimmon, Donald R; Martina, Marco

2012-10-01

Cellular mechanisms of central pH chemosensitivity remain largely unknown. The nucleus of the solitary tract (NTS) integrates peripheral afferents with central pathways controlling breathing; NTS neurons function as central chemosensors, but only limited information exists concerning the ionic mechanisms involved. Acid-sensing ion channels (ASICs) mediate chemosensitivity in nociceptive terminals, where pH values ∼6.5 are not uncommon in inflammation, but are also abundantly expressed throughout the brain where pHi s tightly regulated and their role is less clear. Here we test the hypothesis that ASICs are expressed in NTS neurons and contribute to intrinsic chemosensitivity and control of breathing. In electrophysiological recordings from acute rat NTS slices, ∼40% of NTS neurons responded to physiological acidification (pH 7.0) with a transient depolarization. This response was also present in dissociated neurons suggesting an intrinsic mechanism. In voltage clamp recordings in slices, a pH drop from 7.4 to 7.0 induced ASIC-like inward currents (blocked by 100 μM amiloride) in ∼40% of NTS neurons, while at pH ≤ 6.5 these currents were detected in all neurons tested; RT-PCR revealed expression of ASIC1 and, less abundantly, ASIC2 in the NTS. Anatomical analysis of dye-filled neurons showed that ASIC-dependent chemosensitive cells (cells responding to pH 7.0) cluster dorsally in the NTS. Using in vivo retrograde labelling from the ventral respiratory column, 90% (9/10) of the labelled neurons showed an ASIC-like response to pH 7.0, suggesting that ASIC currents contribute to control of breathing. Accordingly, amiloride injection into the NTS reduced phrenic nerve activity of anaesthetized rats with an elevated arterial P(CO(2)) .

Data Concentrator

NASA Technical Reports Server (NTRS)

Willett, Mike

2015-01-01

Orbital Research, Inc., developed, built, and tested three high-temperature components for use in the design of a data concentrator module in distributed turbine engine control. The concentrator receives analog and digital signals related to turbine engine control and communicates with a full authority digital engine control (FADEC) or high-level command processor. This data concentrator follows the Distributed Engine Controls Working Group (DECWG) roadmap for turbine engine distributed controls communication development that operates at temperatures at least up to 225 C. In Phase I, Orbital Research developed detailed specifications for each component needed for the system and defined the total system specifications. This entailed a combination of system design, compiling existing component specifications, laboratory testing, and simulation. The results showed the feasibility of the data concentrator. Phase II of this project focused on three key objectives. The first objective was to update the data concentrator design modifications from DECWG and prime contractors. Secondly, the project defined requirements for the three new high-temperature, application-specific integrated circuits (ASICs): one-time programmable (OTP), transient voltage suppression (TVS), and 3.3V. Finally, the project validated each design by testing over temperature and under load.

Latest generation of ASICs for photodetector readout

NASA Astrophysics Data System (ADS)

Seguin-Moreau, N.

2013-08-01

The OMEGA microelectronics group has designed a new generation of multichannel integrated circuits, the "ROC" family, in AustrianMicroSystem (AMS) SiGe 0.35 μm technology to read out signals from various families of photodetectors. The chip named MAROC (standing for Multi Anode ReadOut Chip) has been designed to read out MultiAnode Photomultipliers (MAPMT), Photomultiplier ARray In SiGe ReadOut Chip (PARISROC) to read out Photomultipliers (PMTs) and SiPM Integrated ReadOut Chip (SPIROC) to readout Silicon PhotoMultiplier (SiPM) detectors and which was the first ASIC to do so. The three of them fulfill the stringent requirements of the future photodetectors, in particular in terms of low noise, radiation hardness, large dynamic range, high density and high speed while keeping low power thanks to the SiGe technology. These multi-channel ASICs are real System on Chip (SoC) as they provide charge, time and photon-counting information which are digitized internally. Their complexity and versatility enable innovative frontier detectors and also cover spin off of these detectors in adjacent fields such as medical or material imaging as well as smart detectors. In this presentation, the three ASIC architectures and test results will be described to give a general panorama of the "ROC" chips.

A 4×8-Gbps VCSEL array driver ASIC and integration with a custom array transmitter module for the LHC front-end transmission

DOE Office of Scientific and Technical Information (OSTI.GOV)

Guo, Di; Liu, Chonghan; Chen, Jinghong

This paper describes the design, fabrication and experiment results of a 4×8-Gbps Vertical-Cavity Surface-Emitting Laser (VCSEL) array driver ASIC with the adjustable active-shunt peaking technique and the novel balanced output structure under the Silicon-on-Sapphire (SOS) process, and a custom array optical transmitter module, featuring a compact size of 10 mm×15 mm×5.3 mm. Both the array driver ASIC and the module have been fully tested after integration as a complete parallel transmitter. Optical eye diagram of each channel passes the eye mask at 8 Gbps/ch with adjacent channel working simultaneously with a power consumption of 150 mW/ch. As a result, themore » optical transmission of Bit-Error Rate (BER) less than 10E-12 is achieved at an aggregated data rate of 4×8-Gbps.« less

A 4×8-Gbps VCSEL array driver ASIC and integration with a custom array transmitter module for the LHC front-end transmission

DOE PAGES

Guo, Di; Liu, Chonghan; Chen, Jinghong; ...

2016-03-21

This paper describes the design, fabrication and experiment results of a 4×8-Gbps Vertical-Cavity Surface-Emitting Laser (VCSEL) array driver ASIC with the adjustable active-shunt peaking technique and the novel balanced output structure under the Silicon-on-Sapphire (SOS) process, and a custom array optical transmitter module, featuring a compact size of 10 mm×15 mm×5.3 mm. Both the array driver ASIC and the module have been fully tested after integration as a complete parallel transmitter. Optical eye diagram of each channel passes the eye mask at 8 Gbps/ch with adjacent channel working simultaneously with a power consumption of 150 mW/ch. As a result, themore » optical transmission of Bit-Error Rate (BER) less than 10E-12 is achieved at an aggregated data rate of 4×8-Gbps.« less

The New CCSDS Image Compression Recommendation

NASA Technical Reports Server (NTRS)

Yeh, Pen-Shu; Armbruster, Philippe; Kiely, Aaron; Masschelein, Bart; Moury, Gilles; Schaefer, Christoph

2005-01-01

The Consultative Committee for Space Data Systems (CCSDS) data compression working group has recently adopted a recommendation for image data compression, with a final release expected in 2005. The algorithm adopted in the recommendation consists of a two-dimensional discrete wavelet transform of the image, followed by progressive bit-plane coding of the transformed data. The algorithm can provide both lossless and lossy compression, and allows a user to directly control the compressed data volume or the fidelity with which the wavelet-transformed data can be reconstructed. The algorithm is suitable for both frame-based image data and scan-based sensor data, and has applications for near-Earth and deep-space missions. The standard will be accompanied by free software sources on a future web site. An Application-Specific Integrated Circuit (ASIC) implementation of the compressor is currently under development. This paper describes the compression algorithm along with the requirements that drove the selection of the algorithm. Performance results and comparisons with other compressors are given for a test set of space images.

Software-Reconfigurable Processors for Spacecraft

NASA Technical Reports Server (NTRS)

Farrington, Allen; Gray, Andrew; Bell, Bryan; Stanton, Valerie; Chong, Yong; Peters, Kenneth; Lee, Clement; Srinivasan, Jeffrey

2005-01-01

A report presents an overview of an architecture for a software-reconfigurable network data processor for a spacecraft engaged in scientific exploration. When executed on suitable electronic hardware, the software performs the functions of a physical layer (in effect, acts as a software radio in that it performs modulation, demodulation, pulse-shaping, error correction, coding, and decoding), a data-link layer, a network layer, a transport layer, and application-layer processing of scientific data. The software-reconfigurable network processor is undergoing development to enable rapid prototyping and rapid implementation of communication, navigation, and scientific signal-processing functions; to provide a long-lived communication infrastructure; and to provide greatly improved scientific-instrumentation and scientific-data-processing functions by enabling science-driven in-flight reconfiguration of computing resources devoted to these functions. This development is an extension of terrestrial radio and network developments (e.g., in the cellular-telephone industry) implemented in software running on such hardware as field-programmable gate arrays, digital signal processors, traditional digital circuits, and mixed-signal application-specific integrated circuits (ASICs).

Triroc: A Multi-Channel SiPM Read-Out ASIC for PET/PET-ToF Application

NASA Astrophysics Data System (ADS)

Ahmad, Salleh; Fleury, Julien; de la Taille, Christophe; Seguin-Moreau, Nathalie; Dulucq, Frederic; Martin-Chassard, Gisele; Callier, Stephane; Thienpont, Damien; Raux, Ludovic

2015-06-01

Triroc is the latest addition to SiPM readout ASICs family developed at Weeroc, a start-up company from the Omega microelectronics group of IN2P3/CNRS. This chip is developed under the framework TRIMAGE European project which is aimed for building a cost effective tri-modal PET/MR/EEG brain scan. To ensure the flexibility and compatibility with any SiPM in the market, the ASIC is designed to be capable of accepting negative and positive polarity input signals. This 64-channel ASIC, is suitable for SiPM readout which requires high accuracy timing and charge measurements. Targeted applications would be PET prototyping with time-of-flight capability. Main features of Triroc includes high dynamic range ADC up to 2500 photoelectrons and TDC fine time binning of 40 ps. Triroc requires very minimal external components which means it is a good contender for compact multichannel PET prototyping. Triroc is designed by using AMS 0.35 μm SiGe technology and it was submitted in March 2014. The detail design of this chip will be presented.

Osthole, a herbal compound, alleviates nucleus pulposus-evoked nociceptive responses through the suppression of overexpression of acid-sensing ion channel 3 (ASIC3) in rat dorsal root ganglion

PubMed Central

He, Qiu-Lan; Chen, Yuling; Qin, Jian; Mo, Sui-Lin; Wei, Ming; Zhang, Jin-Jun; Li, Mei-Na; Zou, Xue-Nong; Zhou, Shu-Feng; Chen, Xiao-Wu; Sun, Lai-Bao

2012-01-01

Summary Background Osthole (Ost), a natural coumarin derivative, has been shown to inhibit many pro-inflammatory mediators and block voltage-gated Na+ channels. During inflammation, acidosis is an important pain inducer which activates nociceptors by gating depolarizing cationic channels, such as acid-sensing ion channel 3 (ASIC3). The aim of this study was to examine the effects of Ost on nucleus pulposus-evoked nociceptive responses and ASIC3 over-expression in the rat dorsal root ganglion, and to investigate the possible mechanism. Material/Methods Radicular pain was generated with application of nucleus pulposus (NP) to nerve root. Mechanical allodynia was evaluated using von Frey filaments with logarithmically incremental rigidity to calculate the 50% probability thresholds for mechanical paw withdrawal. ASIC3 protein expression in dorsal root ganglions (DRGs) was assessed with Western blot and immunohistochemistry. Membrane potential (MP) shift of DRG neurons induced by ASIC3-sensitive acid (pH6.5) was determined by DiBAC4 (3) fluorescence intensity (F.I.). Results The NP-evoked mechanical hyperalgesia model showed allodynia for 3 weeks, and ASIC3 expression was up-regulated in DRG neurons, reaching peak on Day 7. Epidural administration of Ost induced a remarkable and prolonged antinociceptive effect, accompanied by an inhibition of over-expressed ASIC3 protein and of abnormal shift of MP. Amiloride (Ami), an antagonist of ASIC3, strengthened the antinociceptive effect of Ost. Conclusions Up-regulation of ASIC3 expression may be associated with NP-evoked mechanical hyperalgesia. A single epidural injection of Ost decreased ASIC3 expression in DGR neurons and the pain in the NP-evoked mechanical hyperalgesia model. Osthole may be of great benefit for preventing chronic pain status often seen in lumbar disc herniation (LDH). PMID:22648244

Micromachined piezoresistive inclinometer with oscillator-based integrated interface circuit and temperature readout

NASA Astrophysics Data System (ADS)

Dalola, Simone; Ferrari, Vittorio; Marioli, Daniele

2012-03-01

In this paper a dual-chip system for inclination measurement is presented. It consists of a MEMS (microelectromechanical system) piezoresistive accelerometer manufactured in silicon bulk micromachining and a CMOS (complementary metal oxide semiconductor) ASIC (application specific integrated circuit) interface designed for resistive-bridge sensors. The sensor is composed of a seismic mass symmetrically suspended by means of four flexure beams that integrate two piezoresistors each to detect the applied static acceleration, which is related to inclination with respect to the gravity vector. The ASIC interface is based on a relaxation oscillator where the frequency and the duty cycle of a rectangular-wave output signal are related to the fractional bridge imbalance and the overall bridge resistance of the sensor, respectively. The latter is a function of temperature; therefore the sensing element itself can be advantageously used to derive information for its own thermal compensation. DC current excitation of the sensor makes the configuration unaffected by wire resistances and parasitic capacitances. Therefore, a modular system results where the sensor can be placed remotely from the electronics without suffering accuracy degradation. The inclination measurement system has been characterized as a function of the applied inclination angle at different temperatures. At room temperature, the experimental sensitivity of the system results in about 148 Hz/g, which corresponds to an angular sensitivity around zero inclination angle of about 2.58 Hz deg-1. This is in agreement with finite element method simulations. The measured output fluctuations at constant temperature determine an equivalent resolution of about 0.1° at midrange. In the temperature range of 25-65 °C the system sensitivity decreases by about 10%, which is less than the variation due to the microsensor alone thanks to thermal compensation provided by the current excitation of the bridge and the positive temperature coefficient of resistance of the piezoresistors.

High performance VLSI telemetry data systems

NASA Technical Reports Server (NTRS)

Chesney, J.; Speciale, N.; Horner, W.; Sabia, S.

1990-01-01

NASA's deployment of major space complexes such as Space Station Freedom (SSF) and the Earth Observing System (EOS) will demand increased functionality and performance from ground based telemetry acquisition systems well above current system capabilities. Adaptation of space telemetry data transport and processing standards such as those specified by the Consultative Committee for Space Data Systems (CCSDS) standards and those required for commercial ground distribution of telemetry data, will drive these functional and performance requirements. In addition, budget limitations will force the requirement for higher modularity, flexibility, and interchangeability at lower cost in new ground telemetry data system elements. At NASA's Goddard Space Flight Center (GSFC), the design and development of generic ground telemetry data system elements, over the last five years, has resulted in significant solutions to these problems. This solution, referred to as the functional components approach includes both hardware and software components ready for end user application. The hardware functional components consist of modern data flow architectures utilizing Application Specific Integrated Circuits (ASIC's) developed specifically to support NASA's telemetry data systems needs and designed to meet a range of data rate requirements up to 300 Mbps. Real-time operating system software components support both embedded local software intelligence, and overall system control, status, processing, and interface requirements. These components, hardware and software, form the superstructure upon which project specific elements are added to complete a telemetry ground data system installation. This paper describes the functional components approach, some specific component examples, and a project example of the evolution from VLSI component, to basic board level functional component, to integrated telemetry data system.

Differential regulation of ASICs and TRPV1 by zinc in rat bronchopulmonary sensory neurons.

PubMed

Vysotskaya, Zhanna V; Moss, Charles R; Gu, Qihai

2014-12-01

Zinc has been known to act as a signaling molecule that regulates a variety of neuronal functions. In this study, we aimed to study the effect of zinc on two populations of acid-sensitive ion channels, acid-sensing ion channels (ASICs), and transient receptor potential vanilloid receptor-1 (TRPV1), in vagal bronchopulmonary sensory neurons. Rat vagal sensory neurons innervating lungs and airways were retrogradely labeled with a fluorescent tracer. Whole-cell perforated patch-clamp recordings were carried out in primarily cultured bronchopulmonary sensory neurons. The acid-evoked ASIC and TRPV1 currents were measured and compared between before and after the zinc pretreatment. ASIC currents were induced by a pH drop from 7.4 to 6.8 or 6.5 in the presence of capsazepine (10 µM), a specific TRPV1 antagonist. Pretreatment with zinc (50 or 300 µM, 2 min) displayed different effects on the two distinct phenotypes of ASIC currents: a marked potentiation on ASIC channels with fast kinetics of activation and inactivation or no significant effect on ASIC currents with slow activation and inactivation. On the other hand, pretreatment with zinc significantly inhibited the acid (pH 5.5 or 5.3)-induced TRPV1 currents. The inhibition was abolished by intracellular chelation of zinc by TPEN (25 µM), indicating that intracellular accumulation of zinc was likely required for its inhibitory effect on TRPV1 channels. Our study showed that zinc differentially regulates the activities of ASICs and TRPV1 channels in rat vagal bronchopulmonary sensory neurons.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Averyanov, A. V.; Bajajin, A. G.; Chepurnov, V. F.

The time-projection chamber (TPC) is the main tracking detector in the MPD/NICA. The information on charge-particle tracks in the TPC is registered by the MWPG with cathode pad readout. The frontend electronics (FEE) are developed with use of modern technologies such as application specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), and data transfer to a concentrator via a fast optical interface. The main parameters of the FEE are as follows: total number of channels, ∼95 000; data stream from the whole TPC, 5 GB/s; low power consumption, less than 100 mW/ch; signal to noise ratio (S/N), 30; equivalent noisemore » charge (ENC), <1000e{sup –} (C{sub in} = 10–20 pF); and zero suppression (pad signal rejection ∼90%). The article presents the status of the readout chamber construction and the data acquisition system. The results of testing FEE prototypes are presented.« less

4 Gbps Scalable Low-Voltage Signaling (SLVS) transceiver for pixel radiation detectors

NASA Astrophysics Data System (ADS)

Kadlubowski, Lukasz A.; Kmon, Piotr

2017-08-01

We report on the design of 4 Gbps Scalable Low-Voltage Signaling (SLVS) transceiver in 40nm CMOS technology for application-specific integrated circuits (ASICs) dedicated to pixel radiation detectors. Serial data are transmitted with +/-200mV differential swing around 200mV nominal common-mode level. The common-mode interference minimization is crucial in such a design, due to EMC requirements. For multi-gigabit-per-second speeds, the influence of power supply path becomes one of the most challenging design issues. Accurate modeling of supply pads at each step of the design is necessary. Our analysis shows that the utilization of multiple bond wires as well as separate power supply pads for bulk terminals connection of the transistors is essential to ensure proper operation of the transceiver. The design is a result of various trade-offs between speed, required operating conditions, common-mode interference as well as power and area consumption.

Hardware Architecture Study for NASA's Space Software Defined Radios

NASA Technical Reports Server (NTRS)

Reinhart, Richard C.; Scardelletti, Maximilian C.; Mortensen, Dale J.; Kacpura, Thomas J.; Andro, Monty; Smith, Carl; Liebetreu, John

2008-01-01

This study defines a hardware architecture approach for software defined radios to enable commonality among NASA space missions. The architecture accommodates a range of reconfigurable processing technologies including general purpose processors, digital signal processors, field programmable gate arrays (FPGAs), and application-specific integrated circuits (ASICs) in addition to flexible and tunable radio frequency (RF) front-ends to satisfy varying mission requirements. The hardware architecture consists of modules, radio functions, and and interfaces. The modules are a logical division of common radio functions that comprise a typical communication radio. This paper describes the architecture details, module definitions, and the typical functions on each module as well as the module interfaces. Trade-offs between component-based, custom architecture and a functional-based, open architecture are described. The architecture does not specify the internal physical implementation within each module, nor does the architecture mandate the standards or ratings of the hardware used to construct the radios.

Radiation Effects on Current Field Programmable Technologies

NASA Technical Reports Server (NTRS)

Katz, R.; LaBel, K.; Wang, J. J.; Cronquist, B.; Koga, R.; Penzin, S.; Swift, G.

1997-01-01

Manufacturers of field programmable gate arrays (FPGAS) take different technological and architectural approaches that directly affect radiation performance. Similar y technological and architectural features are used in related technologies such as programmable substrates and quick-turn application specific integrated circuits (ASICs). After analyzing current technologies and architectures and their radiation-effects implications, this paper includes extensive test data quantifying various devices total dose and single event susceptibilities, including performance degradation effects and temporary or permanent re-configuration faults. Test results will concentrate on recent technologies being used in space flight electronic systems and those being developed for use in the near term. This paper will provide the first extensive study of various configuration memories used in programmable devices. Radiation performance limits and their impacts will be discussed for each design. In addition, the interplay between device scaling, process, bias voltage, design, and architecture will be explored. Lastly, areas of ongoing research will be discussed.

Space Telecommunications Radio Systems (STRS) Hardware Architecture Standard: Release 1.0 Hardware Section

NASA Technical Reports Server (NTRS)

Reinhart, Richard C.; Kacpura, Thomas J.; Smith, Carl R.; Liebetreu, John; Hill, Gary; Mortensen, Dale J.; Andro, Monty; Scardelletti, Maximilian C.; Farrington, Allen

2008-01-01

This report defines a hardware architecture approach for software-defined radios to enable commonality among NASA space missions. The architecture accommodates a range of reconfigurable processing technologies including general-purpose processors, digital signal processors, field programmable gate arrays, and application-specific integrated circuits (ASICs) in addition to flexible and tunable radiofrequency front ends to satisfy varying mission requirements. The hardware architecture consists of modules, radio functions, and interfaces. The modules are a logical division of common radio functions that compose a typical communication radio. This report describes the architecture details, the module definitions, the typical functions on each module, and the module interfaces. Tradeoffs between component-based, custom architecture and a functional-based, open architecture are described. The architecture does not specify a physical implementation internally on each module, nor does the architecture mandate the standards or ratings of the hardware used to construct the radios.

A low power, area efficient fpga based beamforming technique for 1-D CMUT arrays.

PubMed

Joseph, Bastin; Joseph, Jose; Vanjari, Siva Rama Krishna

2015-08-01

A low power area efficient digital beamformer targeting low frequency (2MHz) 1-D linear Capacitive Micromachined Ultrasonic Transducer (CMUT) array is developed. While designing the beamforming logic, the symmetry of the CMUT array is well exploited to reduce the area and power consumption. The proposed method is verified in Matlab by clocking an Arbitrary Waveform Generator(AWG). The architecture is successfully implemented in Xilinx Spartan 3E FPGA kit to check its functionality. The beamforming logic is implemented for 8, 16, 32, and 64 element CMUTs targeting Application Specific Integrated Circuit (ASIC) platform at Vdd 1.62V for UMC 90nm technology. It is observed that the proposed architecture consumes significantly lesser power and area (1.2895 mW power and 47134.4 μm(2) area for a 64 element digital beamforming circuit) compared to the conventional square root based algorithm.

Angular Positioning Sensor for Space Mechanisms

NASA Astrophysics Data System (ADS)

Steiner, Nicolas; Chapuis, Dominique

2013-09-01

Angular position sensors are used on various rotating mechanisms such as solar array drive mechanisms, antenna pointing mechanisms, scientific instruments, motors or actuators.Now a days, potentiometers and encoders are mainly used for angular measurement purposes. Both of them have their own pros and cons.As alternative, Ruag Space Switzerland Nyon (RSSN) is developing and qualifying two innovative technologies of angular position sensors which offer easy implementation, medium to very high lifetime and high flexibility with regards to the output signal shape/type.The Brushed angular position sensor uses space qualified processes which are already flying on RSSN's sliprings for many years. A large variety of output signal shape can be implemented to fulfill customer requirements (digital, analog, customized, etc.).The contactless angular position sensor consists in a new radiation hard Application Specific Integrated Circuit (ASIC) based on the Hall effect and providing the angular position without complex processing algorithm.

Localization and Behaviors in Null Mice Suggest that ASIC1 and ASIC2 Modulate Responses to Aversive Stimuli

PubMed Central

Price, Margaret P.; Gong, Huiyu; Parsons, Meredith G.; Kundert, Jacob R.; Reznikov, Leah R.; Bernardinelli, Luisa; Chaloner, Kathryn; Buchanan, Gordon F.; Wemmie, John A.; Richerson, George B.; Cassell, Martin D.; Welsh, Michael J.

2014-01-01

Acid sensing ion channels (ASICs) generate H+-gated Na+ currents that contribute to neuronal function and animal behavior. Like ASIC1, ASIC2 subunits are expressed in the brain and multimerize with ASIC1 to influence acid-evoked currents and facilitate ASIC1 localization to dendritic spines. To better understand how ASIC2 contributes to brain function, we localized the protein and tested the behavioral consequences of ASIC2 gene disruption. For comparison, we also localized ASIC1 and studied ASIC1−/− mice. ASIC2 was prominently expressed in areas of high synaptic density, and with a few exceptions, ASIC1 and ASIC2 localization exhibited substantial overlap. Loss of ASIC1 or ASIC2 decreased freezing behavior in contextual and auditory cue fear conditioning assays, in response to predator odor, and in response to CO2 inhalation. In addition, loss of ASIC1 or ASIC2 increased activity in a forced swim assay. These data suggest that ASIC2, like ASIC1, plays a key role in determining the defensive response to aversive stimuli. They also raise the question of whether gene variations in both ASIC1 and ASIC2 might affect fear and panic in humans. PMID:24256442

BAE Systems Radiation Hardened SpaceWire ASIC and Roadmap

NASA Technical Reports Server (NTRS)

Berger, Richard; Milliser, Myrna; Kapcio, Paul; Stanley, Dan; Moser, David; Koehler, Jennifer; Rakow, Glenn; Schnurr, Richard

2006-01-01

An Application Specific Integrated Circuit (ASIC) that implements the SpaceWire protocol has been developed in a radiation hardened 0.25 micron CMOS, technology. This effort began in March 2003 as a joint development between the NASA Goddard Space Flight Center (GSFC) and BAE Systems. The BAE Systems SpaceWire ASlC is comprised entirely of reusable core elements, many of which are already flight-proven. It incorporates a 4-port SpaceWire router with two local ports, dual PC1 bus interfaces, a microcontroller, 32KB of internal memory, -and a memory controller for additional external memory use. The SpaceWire ASlC is planned for use on both the Geostationary Operational Environmental Satellites (GOES)-R and the Lunar Reconnaissance Orbiter (LRO). Engineering parts have already been delivered to both programs. This paper discusses the SpaceWire protocol and those elements of it that have been built into the current SpaceWire reusable core. There are features within the core that go beyond the current standard that can be enabled or disabled by the user and these will be described. The adaptation of SpaceWire to BAE Systems' On Chip Bus (OCB) for compatibility with the other reusable cores will be discussed. Optional configurations within user systems will be shown. The physical imp!ementation of the design will be described and test results from the hardware will be discussed. Finally, the BAE Systems roadmap for SpaceWire developments will be discussed, including some products already in design as well as longer term plans.

A novel CMOS transducer for giant magnetoresistance sensors.

PubMed

Luong, Van Su; Lu, Chih-Cheng; Yang, Jing-Wen; Jeng, Jen-Tzong

2017-02-01

In this work, an ASIC (application specific integrated circuits) transducer circuit for field modulated giant magnetoresistance (GMR) sensors was designed and fabricated using a 0.18-μm CMOS process. The transducer circuits consist of a frequency divider, a digital phase shifter, an instrument amplifier, and an analog mixer. These comprise a mix of analog and digital circuit techniques. The compact chip size of 1.5 mm × 1.5 mm for both analog and digital parts was achieved using the TSMC18 1P6M (1-polysilicon 6-metal) process design kit, and the characteristics of the system were simulated using an HSpice simulator. The output of the transducer circuit is the result of the first harmonic detection, which resolves the modulated field using a phase sensitive detection (PSD) technique and is proportional to the measured magnetic field. When the dual-bridge GMR sensor is driven by the transducer circuit with a current of 10 mA at 10 kHz, the observed sensitivity of the field sensor is 10.2 mV/V/Oe and the nonlinearity error was 3% in the linear range of ±1 Oe. The performance of the system was also verified by rotating the sensor system horizontally in earth's magnetic field and recording the sinusoidal output with respect to the azimuth angle, which exhibits an error of less than ±0.04 Oe. These results prove that the ASIC transducer is suitable for driving the AC field modulated GMR sensors applied to geomagnetic measurement.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dondero, Rachel Elizabeth

The increased use of Field Programmable Gate Arrays (FPGAs) in critical systems brings new challenges in securing the diversely programmable fabric from cyber-attacks. FPGAs are an inexpensive, efficient, and flexible alternative to Application Specific Integrated Circuits (ASICs), which are becoming increasingly expensive and impractical for low volume manufacturing as technology nodes continue to shrink. Unfortunately, FPGAs are not designed for high security applications, and their high-flexibility lends itself to low security and vulnerability to malicious attacks. Similar to securing an ASIC’s functionality, FPGA programmers can exploit the inherent randomness introduced into hardware structures during fabrication for security applications. Physically Unclonablemore » Functions (PUFs) are one such solution that uses the die specific variability in hardware fabrication for both secret key generation and verification. PUFs strive to be random, unique, and reliable. Throughout recent years many PUF structures have been presented to try and maximize these three design constraints, reliability being the most difficult of the three to achieve. This thesis presents a new PUF structure that combines two elementary PUF concepts (a bi-stable SRAM PUF and a delay-based arbiter PUF) to create a PUF with increased reliability, while maintaining both random and unique qualities. Properties of the new PUF will be discussed as well as the various design modifications that can be made to tweak the desired performance and overhead.« less

Development of 4-Sides Buttable CdTe-ASIC Hybrid Module for X-ray Flat Panel Detector

NASA Astrophysics Data System (ADS)

Tamaki, Mitsuru; Mito, Yoshio; Shuto, Yasuhiro; Kiyuna, Tatsuya; Yamamoto, Masaya; Sagae, Kenichi; Kina, Tooru; Koizumi, Tatsuhiro; Ohno, Ryoichi

2009-08-01

A 4-sides buttable CdTe-ASIC hybrid module suitable for use in an X-ray flat panel detector (FPD) has been developed by applying through silicon via (TSV) technology to the readout ASIC. The ASIC has 128 times 256 channels of charge integration type readout circuitry and an area of 12.9 mm times 25.7 mm. The CdTe sensor of 1 mm thickness, having the same area and pixel of 100 mum pitch, was fabricated from the Cl-doped CdTe single crystal grown by traveling heater method (THM). Then the CdTe pixel sensor was hybridized with the ASIC using the bump-bonding technology. The basic performance of this 4-sides buttable module was evaluated by taking X-ray images, and it was compared with that of a commercially available indirect type CsI(Tl) FPD. A prototype CdTe FPD was made by assembling 9 pieces of the 4-sides buttable modules into 3 times 3 arrays in which the neighboring modules were mounted on the interface board. The FPD covers an active area of 77 mm times 39 mm. The results showed the great potential of this 4-sides buttable module for the new real time X-ray FPD with high spatial resolution.

Data encryption standard ASIC design and development report.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Robertson, Perry J.; Pierson, Lyndon George; Witzke, Edward L.

2003-10-01

This document describes the design, fabrication, and testing of the SNL Data Encryption Standard (DES) ASIC. This device was fabricated in Sandia's Microelectronics Development Laboratory using 0.6 {micro}m CMOS technology. The SNL DES ASIC was modeled using VHDL, then simulated, and synthesized using Synopsys, Inc. software and finally IC layout was performed using Compass Design Automation's CAE tools. IC testing was performed by Sandia's Microelectronic Validation Department using a HP 82000 computer aided test system. The device is a single integrated circuit, pipelined realization of DES encryption and decryption capable of throughputs greater than 6.5 Gb/s. Several enhancements accommodate ATMmore » or IP network operation and performance scaling. This design is the latest step in the evolution of DES modules.« less

Design and implementation of the ATLAS TRT front end electronics

NASA Astrophysics Data System (ADS)

Newcomer, Mitch; Atlas TRT Collaboration

2006-07-01

The ATLAS TRT subsystem is comprised of 380,000 4 mm straw tube sensors ranging in length from 30 to 80 cm. Polypropelene plastic layers between straws and a xenon-based gas mixture in the straws allow the straws to be used for both tracking and transition radiation detection. Detector-mounted electronics with data sparsification was chosen to minimize the cable plant inside the super-conducting solenoid of the ATLAS inner tracker. The "on detector" environment required a small footprint, low noise, low power and radiation-tolerant readout capable of triggering at rates up to 20 MHz with an analog signal dynamic range of >300 times the discriminator setting. For tracking, a position resolution better than 150 μm requires leading edge trigger timing with ˜1 ns precision and for transition radiation detection, a charge collection time long enough to integrate the direct and reflected signal from the unterminated straw tube is needed for position-independent energy measurement. These goals have been achieved employing two custom Application-specific integrated circuits (ASICS) and board design techniques that successfully separate analog and digital functionality while providing an integral part of the straw tube shielding.

Spacewire Routers Implemented with FPGA Technology

NASA Astrophysics Data System (ADS)

Habinc, Sandi; Isomaki, Marko

2011-08-01

Routers are an integral part of SpaceWire networks. Aeroflex Gaisler has developed a highly configurable SpaceWire router VHDL IP core to meet the needs for technology independent router designs. The main design goals have been configurability, technology independence, support of the standard and expandability. The IP core being technologically independent allows it to be used in both ASIC and FPGA technology. The latter is now being used to produce versatile standard products that can reach the market faster than for example an ASIC based product.

Acid mediates a prolonged antinociception via substance P signaling in acid-induced chronic widespread pain.

PubMed

Chen, Wei-Nan; Chen, Chih-Cheng

2014-05-21

Substance P is an important neuropeptide released from nociceptors to mediate pain signals. We recently revealed antinociceptive signaling by substance P in acid-sensing ion channel 3 (ASIC3)-expressing muscle nociceptors in a mouse model of acid-induced chronic widespread pain. However, methods to specifically trigger the substance P antinociception were still lacking. Here we show that acid could induce antinociceptive signaling via substance P release in muscle. We prevented the intramuscular acid-induced hyperalgesia by pharmacological inhibition of ASIC3 and transient receptor potential V1 (TRPV1). The antinociceptive effect of non-ASIC3, non-TRPV1 acid signaling lasted for 2 days. The non-ASIC3, non-TRPV1 acid antinociception was largely abolished in mice lacking substance P. Moreover, pretreatment with substance P in muscle mimicked the acid antinociceptive effect and prevented the hyperalgesia induced by next-day acid injection. Acid could mediate a prolonged antinociceptive signaling via the release of substance P from muscle afferent neurons in a non-ASIC3, non-TRPV1 manner.

Receptor for protons: First observations on Acid Sensing Ion Channels.

PubMed

Krishtal, Oleg

2015-07-01

The history of ASICs began in 1980 with unexpected observation. The concept of highly selective Na(+) current gated by specific receptors for protons was not easily accepted. It took 16 years to get these receptor/channels cloned and start a new stage in their investigation. "The receptor for protons" became ASIC comprising under this name a family of receptor/channels ubiquitous for mammalian nervous system, both peripheral and central. The role of ASICs as putative nociceptors was suggested almost immediately after their discovery. This role subsequently was proven in many forms of pain-related phenomena. Many other functions of ASICs have been also found or primed for speculations both in physiology and in disease. Despite the width of field and strength of efforts, numerous basic questions are to be answered before we understand how the local changes in pH in the nervous tissue transform into electric and messenger signaling via ASICs as transducers. This article is part of the Special Issue entitled 'Acid-Sensing Ion Channels in the Nervous System'. Copyright © 2015. Published by Elsevier Ltd.

Active counter electrode in a-SiC electrochemical metallization memory

NASA Astrophysics Data System (ADS)

Morgan, K. A.; Fan, J.; Huang, R.; Zhong, L.; Gowers, R.; Ou, J. Y.; Jiang, L.; De Groot, C. H.

2017-08-01

Cu/amorphous-SiC (a-SiC) electrochemical metallization memory cells have been fabricated with two different counter electrode (CE) materials, W and Au, in order to investigate the role of CEs in a non-oxide semiconductor switching matrix. In a positive bipolar regime with Cu filaments forming and rupturing, the CE influences the OFF state resistance and minimum current compliance. Nevertheless, a similarity in SET kinetics is seen for both CEs, which differs from previously published SiO2 memories, confirming that CE effects are dependent on the switching layer material or type. Both a-SiC memories are able to switch in the negative bipolar regime, indicating Au and W filaments. This confirms that CEs can play an active role in a non-oxide semiconducting switching matrix, such as a-SiC. By comparing both Au and W CEs, this work shows that W is superior in terms of a higher R OFF/R ON ratio, along with the ability to switch at lower current compliances making it a favourable material for future low energy applications. With its CMOS compatibility, a-SiC/W is an excellent choice for future resistive memory applications.

PAR-2 activation enhances weak acid-induced ATP release through TRPV1 and ASIC sensitization in human esophageal epithelial cells.

PubMed

Wu, Liping; Oshima, Tadayuki; Shan, Jing; Sei, Hiroo; Tomita, Toshihiko; Ohda, Yoshio; Fukui, Hirokazu; Watari, Jiro; Miwa, Hiroto

2015-10-15

Esophageal visceral hypersensitivity has been proposed to be the pathogenesis of heartburn sensation in nonerosive reflux disease. Protease-activated receptor-2 (PAR-2) is expressed in human esophageal epithelial cells and is believed to play a role in inflammation and sensation. PAR-2 activation may modulate these responses through adenosine triphosphate (ATP) release, which is involved in transduction of sensation and pain. The transient receptor potential vanilloid receptor 1 (TRPV1) and acid-sensing ion channels (ASICs) are both acid-sensitive nociceptors. However, the interaction among these molecules and the mechanisms of heartburn sensation are still not clear. We therefore examined whether ATP release in human esophageal epithelial cells in response to acid is modulated by TRPV1 and ASICs and whether PAR-2 activation influences the sensitivity of TRPV1 and ASICs. Weak acid (pH 5) stimulated the release of ATP from primary human esophageal epithelial cells (HEECs). This effect was significantly reduced after pretreatment with 5-iodoresiniferatoxin (IRTX), a TRPV1-specific antagonist, or with amiloride, a nonselective ASIC blocker. TRPV1 and ASIC3 small interfering RNA (siRNA) transfection also decreased weak acid-induced ATP release. Pretreatment of HEECs with trypsin, tryptase, or a PAR-2 agonist enhanced weak acid-induced ATP release. Trypsin treatment led to the phosphorylation of TRPV1. Acid-induced ATP release enhancement by trypsin was partially blocked by IRTX, amiloride, or a PAR-2 antagonist. Conversely, acid-induced ATP release was augmented by PAR-2 activation through TRPV1 and ASICs. These findings suggested that the pathophysiology of heartburn sensation or esophageal hypersensitivity may be associated with the activation of PAR-2, TRPV1, and ASICs. Copyright © 2015 the American Physiological Society.

Acid-sensing ion channels (ASICs) in the taste buds of adult zebrafish.

PubMed

Viña, E; Parisi, V; Cabo, R; Laurà, R; López-Velasco, S; López-Muñiz, A; García-Suárez, O; Germanà, A; Vega, J A

2013-03-01

In detecting chemical properties of food, different molecules and ion channels are involved including members of the acid-sensing ion channels (ASICs) family. Consistently ASICs are present in sensory cells of taste buds of mammals. In the present study the presence of ASICs (ASIC1, ASIC2, ASIC3 and ASIC4) was investigated in the taste buds of adult zebrafish (zASICs) using Western blot and immunohistochemistry. zASIC1 and zASIC3 were regularly absent from taste buds, whereas faint zASIC2 and robust zASIC4 immunoreactivities were detected in sensory cells. Moreover, zASIC2 also immunolabelled nerves supplying taste buds. The present results demonstrate for the first time the presence of zASICs in taste buds of teleosts, with different patterns to that occurring in mammals, probably due to the function of taste buds in aquatic environment and feeding. Nevertheless, the role of zASICs in taste remains to be demonstrated. Copyright © 2013 Elsevier Ireland Ltd. All rights reserved.

JPIC-Rad-Hard JPEG2000 Image Compression ASIC

NASA Astrophysics Data System (ADS)

Zervas, Nikos; Ginosar, Ran; Broyde, Amitai; Alon, Dov

2010-08-01

JPIC is a rad-hard high-performance image compression ASIC for the aerospace market. JPIC implements tier 1 of the ISO/IEC 15444-1 JPEG2000 (a.k.a. J2K) image compression standard [1] as well as the post compression rate-distortion algorithm, which is part of tier 2 coding. A modular architecture enables employing a single JPIC or multiple coordinated JPIC units. JPIC is designed to support wide data sources of imager in optical, panchromatic and multi-spectral space and airborne sensors. JPIC has been developed as a collaboration of Alma Technologies S.A. (Greece), MBT/IAI Ltd (Israel) and Ramon Chips Ltd (Israel). MBT IAI defined the system architecture requirements and interfaces, The JPEG2K-E IP core from Alma implements the compression algorithm [2]. Ramon Chips adds SERDES interfaces and host interfaces and integrates the ASIC. MBT has demonstrated the full chip on an FPGA board and created system boards employing multiple JPIC units. The ASIC implementation, based on Ramon Chips' 180nm CMOS RadSafe[TM] RH cell library enables superior radiation hardness.

Photon Counting Energy Dispersive Detector Arrays for X-ray Imaging

PubMed Central

Iwanczyk, Jan S.; Nygård, Einar; Meirav, Oded; Arenson, Jerry; Barber, William C.; Hartsough, Neal E.; Malakhov, Nail; Wessel, Jan C.

2009-01-01

The development of an innovative detector technology for photon-counting in X-ray imaging is reported. This new generation of detectors, based on pixellated cadmium telluride (CdTe) and cadmium zinc telluride (CZT) detector arrays electrically connected to application specific integrated circuits (ASICs) for readout, will produce fast and highly efficient photon-counting and energy-dispersive X-ray imaging. There are a number of applications that can greatly benefit from these novel imagers including mammography, planar radiography, and computed tomography (CT). Systems based on this new detector technology can provide compositional analysis of tissue through spectroscopic X-ray imaging, significantly improve overall image quality, and may significantly reduce X-ray dose to the patient. A very high X-ray flux is utilized in many of these applications. For example, CT scanners can produce ~100 Mphotons/mm2/s in the unattenuated beam. High flux is required in order to collect sufficient photon statistics in the measurement of the transmitted flux (attenuated beam) during the very short time frame of a CT scan. This high count rate combined with a need for high detection efficiency requires the development of detector structures that can provide a response signal much faster than the transit time of carriers over the whole detector thickness. We have developed CdTe and CZT detector array structures which are 3 mm thick with 16×16 pixels and a 1 mm pixel pitch. These structures, in the two different implementations presented here, utilize either a small pixel effect or a drift phenomenon. An energy resolution of 4.75% at 122 keV has been obtained with a 30 ns peaking time using discrete electronics and a 57Co source. An output rate of 6×106 counts per second per individual pixel has been obtained with our ASIC readout electronics and a clinical CT X-ray tube. Additionally, the first clinical CT images, taken with several of our prototype photon-counting and energy-dispersive detector modules, are shown. PMID:19920884

Photon Counting Energy Dispersive Detector Arrays for X-ray Imaging.

PubMed

Iwanczyk, Jan S; Nygård, Einar; Meirav, Oded; Arenson, Jerry; Barber, William C; Hartsough, Neal E; Malakhov, Nail; Wessel, Jan C

2009-01-01

The development of an innovative detector technology for photon-counting in X-ray imaging is reported. This new generation of detectors, based on pixellated cadmium telluride (CdTe) and cadmium zinc telluride (CZT) detector arrays electrically connected to application specific integrated circuits (ASICs) for readout, will produce fast and highly efficient photon-counting and energy-dispersive X-ray imaging. There are a number of applications that can greatly benefit from these novel imagers including mammography, planar radiography, and computed tomography (CT). Systems based on this new detector technology can provide compositional analysis of tissue through spectroscopic X-ray imaging, significantly improve overall image quality, and may significantly reduce X-ray dose to the patient. A very high X-ray flux is utilized in many of these applications. For example, CT scanners can produce ~100 Mphotons/mm(2)/s in the unattenuated beam. High flux is required in order to collect sufficient photon statistics in the measurement of the transmitted flux (attenuated beam) during the very short time frame of a CT scan. This high count rate combined with a need for high detection efficiency requires the development of detector structures that can provide a response signal much faster than the transit time of carriers over the whole detector thickness. We have developed CdTe and CZT detector array structures which are 3 mm thick with 16×16 pixels and a 1 mm pixel pitch. These structures, in the two different implementations presented here, utilize either a small pixel effect or a drift phenomenon. An energy resolution of 4.75% at 122 keV has been obtained with a 30 ns peaking time using discrete electronics and a (57)Co source. An output rate of 6×10(6) counts per second per individual pixel has been obtained with our ASIC readout electronics and a clinical CT X-ray tube. Additionally, the first clinical CT images, taken with several of our prototype photon-counting and energy-dispersive detector modules, are shown.

Highest integration in microelectronics: Development of digital ASICs for PARS3-LR

NASA Astrophysics Data System (ADS)

Scholler, Peter; Vonlutz, Rainer

Essential electronic system components by PARS3-LR, show high requirements in calculation power, power consumption and reliability, by immediately increasing integration thicknesses. These problems are solved by using integrated circuits, developed by LSI LOGIC, that uses the technical and economic advantages of this leading edge technology.

Enhanced maximal exercise capacity, vasodilation to electrical muscle contraction, and hind limb vascular density in ASIC1a null mice.

PubMed

Drummond, Heather A; Xiang, Lusha; Chade, Alejandro R; Hester, Robert

2017-08-01

Acid-sensing ion channel (ASIC) proteins form extracellular proton-gated, cation-selective channels in neurons and vascular smooth muscle cells and are proposed to act as extracellular proton sensors. However, their importance to vascular responses under conditions associated with extracellular acidosis, such as strenuous exercise, is unclear. Therefore, the purpose of this study was to determine if one ASIC protein, ASIC1a, contributes to extracellular proton-gated vascular responses and exercise tolerance. To determine if ASIC1a contributes to exercise tolerance, we determined peak oxygen (O 2 ) uptake in conscious ASIC1a -/- mice during exhaustive treadmill running. Loss of ASIC1a was associated with a greater peak running speed (60 ± 2 vs. 53 ± 3 m·min -1 , P  = 0.049) and peak oxygen (O 2 ) uptake during exhaustive treadmill running (9563 ± 120 vs. 8836 ± 276 mL·kg -1 ·h -1 , n  = 6-7, P  = 0.0082). There were no differences in absolute or relative lean body mass, as determined by EchoMRI. To determine if ASIC1a contributes to vascular responses during muscle contraction, we measured femoral vascular conductance (FVC) during a stepwise electrical stimulation (0.5-5.0 Hz at 3 V for 60 sec) of the left major hind limb muscles. FVC increased to a greater extent in ASIC1a -/- versus ASIC1a +/+ mice (0.44 ± 0.03 vs. 0.30 ± 0.04 mL·min -1 ·100 g hind limb mass -1 · mmHg -1 , n  = 5 each, P  = 0.0009). Vasodilation following local application of external protons in the spinotrapezius muscle increased the duration, but not the magnitude, of the vasodilatory response in ASIC1a -/- mice. Finally, we examined hind limb vascular density using micro-CT and found increased density of 0-80  μ m vessels ( P  <   0.05). Our findings suggest an increased vascular density and an enhanced vasodilatory response to local protons, to a lesser degree, may contribute to the enhanced vascular conductance and increased peak exercise capacity in ASIC1a -/- mice. © 2017 The Authors. Physiological Reports published by Wiley Periodicals, Inc. on behalf of The Physiological Society and the American Physiological Society.

NASA's spacecraft data system

NASA Technical Reports Server (NTRS)

Cudmore, Alan; Flanegan, Mark

1993-01-01

The NASA Small Explorer Data System (SEDS), a space flight data system developed to support the Small Explorer (SMEX) project, is addressed. The system was flown on the Solar Anomalous Magnetospheric Particle Explorer (SAMPEX) SMEX mission, and with reconfiguration for different requirements will fly on the X-ray Timing Explorer (XTE) and the Tropical Rainfall Measuring Mission (TRMM). SEDS is also foreseen for the Hubble repair mission. Its name was changed to Spacecraft Data System (SDS) in view of expansions. Objectives, SDS hardware, and software are described. Each SDS box contains two computers, data storage memory, uplink (command) reception circuitry, downlink (telemetry) encoding circuitry, Instrument Telemetry Controller (ITC), and spacecraft timing circuitry. The SDS communicates with other subsystems over the MIL-STD-1773 data bus. The SDS software uses a real time Operating System (OS) and the C language. The OS layer, communications and scheduling layer, application task layer, and diagnostic software, are described. Decisions on the use of advanced technologies, such as ASIC's (Application Specific Integrated Circuits) and fiber optics, led to technical improvements, such as lower power and weight, without increasing the risk associated with the data system. The result was a successful SAMPEX development, integration and test, and mission using SEDS, and the upgrading of that system to SDS for TRMM and XTE.

Automated Test Requirement Document Generation

DTIC Science & Technology

1987-11-01

DIAGNOSTICS BASED ON THE PRINCIPLES OF ARTIFICIAL INTELIGENCE ", 1984 International Test Conference, 01Oct84, (A3, 3, Cs D3, E2, G2, H2, 13, J6, K) 425...j0O GLOSSARY OF ACRONYMS 0 ABBREVIATION DEFINITION AFSATCOM Air Force Satellite Communication Al Artificial Intelligence ASIC Application Specific...In-Test Equipment (BITE) and AI ( Artificial Intelligence) - Expert Systems - need to be fully applied before a completely automated process can be

Secure ASIC Architecture for Optimized Utilization of a Trusted Supply Chain for Common Architecture A and D Applications

DTIC Science & Technology

2017-03-01

overseas. Concurrently, time to market and complex system requirements are increasingly outside the budget range of standalone DoD projects. This paper...expense and delay to market concerns, a major FPGA vendor has offered an FPGA specifically targeting the A&D market . Architecturally, this offering...time-to- market Such services could individually be engaged, each spanning commercial to Trusted handling levels, as appropriate for balancing

In vivo Characterization of Amorphous Silicon Carbide As a Biomaterial for Chronic Neural Interfaces

PubMed Central

Knaack, Gretchen L.; McHail, Daniel G.; Borda, German; Koo, Beomseo; Peixoto, Nathalia; Cogan, Stuart F.; Dumas, Theodore C.; Pancrazio, Joseph J.

2016-01-01

Implantable microelectrode arrays (MEAs) offer clinical promise for prosthetic devices by enabling restoration of communication and control of artificial limbs. While proof-of-concept recordings from MEAs have been promising, work in animal models demonstrates that the obtained signals degrade over time. Both material robustness and tissue response are acknowledged to have a role in device lifetime. Amorphous Silicon carbide (a-SiC), a robust material that is corrosion resistant, has emerged as an alternative encapsulation layer for implantable devices. We systematically examined the impact of a-SiC coating on Si probes by immunohistochemical characterization of key markers implicated in tissue-device response. After implantation, we performed device capture immunohistochemical labeling of neurons, astrocytes, and activated microglia/macrophages after 4 and 8 weeks of implantation. Neuron loss and microglia activation were similar between Si and a-SiC coated probes, while tissue implanted with a-SiC displayed a reduction in astrocytes adjacent to the probe. These results suggest that a-SiC has a similar biocompatibility profile as Si, and may be suitable for implantable MEA applications as a hermetic coating to prevent material degradation. PMID:27445672

In vivo Characterization of Amorphous Silicon Carbide As a Biomaterial for Chronic Neural Interfaces.

PubMed

Knaack, Gretchen L; McHail, Daniel G; Borda, German; Koo, Beomseo; Peixoto, Nathalia; Cogan, Stuart F; Dumas, Theodore C; Pancrazio, Joseph J

2016-01-01

Implantable microelectrode arrays (MEAs) offer clinical promise for prosthetic devices by enabling restoration of communication and control of artificial limbs. While proof-of-concept recordings from MEAs have been promising, work in animal models demonstrates that the obtained signals degrade over time. Both material robustness and tissue response are acknowledged to have a role in device lifetime. Amorphous Silicon carbide (a-SiC), a robust material that is corrosion resistant, has emerged as an alternative encapsulation layer for implantable devices. We systematically examined the impact of a-SiC coating on Si probes by immunohistochemical characterization of key markers implicated in tissue-device response. After implantation, we performed device capture immunohistochemical labeling of neurons, astrocytes, and activated microglia/macrophages after 4 and 8 weeks of implantation. Neuron loss and microglia activation were similar between Si and a-SiC coated probes, while tissue implanted with a-SiC displayed a reduction in astrocytes adjacent to the probe. These results suggest that a-SiC has a similar biocompatibility profile as Si, and may be suitable for implantable MEA applications as a hermetic coating to prevent material degradation.

Adjustable Nyquist-rate System for Single-Bit Sigma-Delta ADC with Alternative FIR Architecture

NASA Astrophysics Data System (ADS)

Frick, Vincent; Dadouche, Foudil; Berviller, Hervé

2016-09-01

This paper presents a new smart and compact system dedicated to control the output sampling frequency of an analogue-to-digital converters (ADC) based on single-bit sigma-delta (ΣΔ) modulator. This system dramatically improves the spectral analysis capabilities of power network analysers (power meters) by adjusting the ADC's sampling frequency to the input signal's fundamental frequency with a few parts per million accuracy. The trade-off between straightforwardness and performance that motivated the choice of the ADC's architecture are preliminary discussed. It particularly comes along with design considerations of an ultra-steep direct-form FIR that is optimised in terms of size and operating speed. Thanks to compact standard VHDL language description, the architecture of the proposed system is particularly suitable for application-specific integrated circuit (ASIC) implementation-oriented low-power and low-cost power meter applications. Field programmable gate array (FPGA) prototyping and experimental results validate the adjustable sampling frequency concept. They also show that the system can perform better in terms of implementation and power capabilities compared to dedicated IP resources.

A forward error correction technique using a high-speed, high-rate single chip codec

NASA Astrophysics Data System (ADS)

Boyd, R. W.; Hartman, W. F.; Jones, Robert E.

The authors describe an error-correction coding approach that allows operation in either burst or continuous modes at data rates of multiple hundreds of megabits per second. Bandspreading is low since the code rate is 7/8 or greater, which is consistent with high-rate link operation. The encoder, along with a hard-decision decoder, fits on a single application-specific integrated circuit (ASIC) chip. Soft-decision decoding is possible utilizing applique hardware in conjunction with the hard-decision decoder. Expected coding gain is a function of the application and is approximately 2.5 dB for hard-decision decoding at 10-5 bit-error rate with phase-shift-keying modulation and additive Gaussian white noise interference. The principal use envisioned for this technique is to achieve a modest amount of coding gain on high-data-rate, bandwidth-constrained channels. Data rates of up to 300 Mb/s can be accommodated by the codec chip. The major objective is burst-mode communications, where code words are composed of 32 n data bits followed by 32 overhead bits.

On DESTINY Science Instrument Electrical and Electronics Subsystem Framework

NASA Technical Reports Server (NTRS)

Kizhner, Semion; Benford, Dominic J.; Lauer, Tod R.

2009-01-01

Future space missions are going to require large focal planes with many sensing arrays and hundreds of millions of pixels all read out at high data rates'' . This will place unique demands on the electrical and electronics (EE) subsystem design and it will be critically important to have high technology readiness level (TRL) EE concepts ready to support such missions. One such omission is the Joint Dark Energy Mission (JDEM) charged with making precise measurements of the expansion rate of the universe to reveal vital clues about the nature of dark energy - a hypothetical form of energy that permeates all of space and tends to increase the rate of the expansion. One of three JDEM concept studies - the Dark Energy Space Telescope (DESTINY) was conducted in 2008 at the NASA's Goddard Space Flight Center (GSFC) in Greenbelt, Maryland. This paper presents the EE subsystem framework, which evolved from the DESTINY science instrument study. It describes the main challenges and implementation concepts related to the design of an EE subsystem featuring multiple focal planes populated with dozens of large arrays and millions of pixels. The focal planes are passively cooled to cryogenic temperatures (below 140 K). The sensor mosaic is controlled by a large number of Readout Integrated Circuits and Application Specific Integrated Circuits - the ROICs/ASICs in near proximity to their sensor focal planes. The ASICs, in turn, are serviced by a set of "warm" EE subsystem boxes performing Field Programmable Gate Array (FPGA) based digital signal processing (DSP) computations of complex algorithms, such as sampling-up-the-ramp algorithm (SUTR), over large volumes of fast data streams. The SUTR boxes are supported by the Instrument Control/Command and Data Handling box (ICDH Primary and Backup boxes) for lossless data compression, command and low volume telemetry handling, power conversion and for communications with the spacecraft. The paper outlines how the JDEM DESTINY concept instrument EE subsystem can be built now, a design; which is generally U.S. Government work not protected by U.S. copyright IEEEAC paper # 1429. Version 4. Updated October 19, 2009 applicable to a wide variety of missions using large focal planes with lar ge mosaics of sensors.

Acid-Sensing Ion Channels Expression, Identity and Role in the Excitability of the Cochlear Afferent Neurons

PubMed Central

González-Garrido, Antonia; Vega, Rosario; Mercado, Francisco; López, Iván A.; Soto, Enrique

2015-01-01

Acid-sensing ion channels (ASICs) are activated by an increase in the extracellular proton concentration. There are four genes (ASIC1-4) that encode six subunits, and they are involved in diverse neuronal functions, such as mechanosensation, learning and memory, nociception, and modulation of retinal function. In this study, we characterize the ASIC currents of spiral ganglion neurons (SGNs). These ASIC currents are primarily carried by Na+, exhibit fast activation and desensitization, display a pH50 of 6.2 and are blocked by amiloride, indicating that these are ASIC currents. The ASIC currents were further characterized using several pharmacological tools. Gadolinium and acetylsalicylic acid reduced these currents, and FMRFamide, zinc (at high concentrations) and N,N,N’,N’–tetrakis-(2-piridilmetil)-ethylenediamine increased them, indicating that functional ASICs are composed of the subunits ASIC1, ASIC2, and ASIC3. Neomycin and streptomycin reduced the desensitization rate of the ASIC current in SGNs, indicating that ASICs may contribute to the ototoxic action of aminoglycosides. RT-PCR of the spiral ganglion revealed significant expression of all ASIC subunits. By immunohistochemistry the expression of the ASIC1a, ASIC2a, ASIC2b, and ASIC3 subunits was detected in SGNs. Although only a few SGNs exhibited action potential firing in response to an acidic stimulus, protons in the extracellular solution modulated SGN activity during sinusoidal stimulation. Our results show that protons modulate the excitability of SGNs via ASICs. PMID:26733809

Development of a flight qualified 100 x 100 mm MCP UV detector using advanced cross strip anodes and associated ASIC electronics

NASA Astrophysics Data System (ADS)

Vallerga, John; McPhate, Jason; Tremsin, Anton; Siegmund, Oswald; Raffanti, Rick; Cumming, Harley; Seljak, Andrej; Virta, Vihtori; Varner, Gary

2016-07-01

Photon counting microchannel plate (MCP) imagers have been the detector of choice for most UV astronomical missions over the last three decades (e.g. EUVE, FUSE, COS on Hubble etc.) and been mentioned for instruments on future large telescopes in space such as LUVOIR14. Using cross strip anodes, improvements in the MCP laboratory readout technology have resulted in better spatial resolution (x10), temporal resolution (x 1000) and output event rate (x100), all the while operating at lower gain (x10) resulting in lower high voltage requirements and longer MCP lifetimes. A crossed strip anode MCP readout starts with a set of orthogonal conducting strips (e.g. 80 x 80), typically spaced at a 635 micron pitch onto which charge clouds from MCP amplified events land. Each strip has its own charge sensitive amplifier that is sampled continuously by a dedicated analog to digital converter (ADC). All of the ADC digital output lines are fed into a field programmable gate array (FGPA) which can detect charge events landing on the strips, measure the peak amplitudes of those charge events and calculate their spatial centroid along with their time of arrival (X,Y,T) and pass this information to a downstream computer. Laboratory versions of these electronics have demonstrated < 20 microns FWHM spatial resolution, count rates on the order of 2 MHz, and temporal resolution of 1ns. In 2012 our group at U.C. Berkeley, along with our partners at the U. Hawaii, received a NASA Strategic Astrophysics Technology (SAT) grant to raise the TRL of a cross strip detector from 4 to 6 by replacing most of the 19" rack mounted, high powered electronics with application specific integrated circuits (ASICs) which will lower the power, mass, and volume requirements of the detector electronics. We were also tasked to design and fabricate a "standard" 50mm square active area MCP detector incorporating these electronics that can be environmentally qualified for flight (temperature, vacuum, vibration). ASICs designed for this program have been successfully fabricated and are undergoing extensive testing. We will present the latest progress on these ASIC designs and their performance. We will also show our preliminary work on scaling these designs (detector and electronics) to a flight qualified 100 x 100 mm cross strip detector, which has recently been funded through a follow on SAT grant.

GET: A generic electronics system for TPCs and nuclear physics instrumentation

NASA Astrophysics Data System (ADS)

Pollacco, E. C.; Grinyer, G. F.; Abu-Nimeh, F.; Ahn, T.; Anvar, S.; Arokiaraj, A.; Ayyad, Y.; Baba, H.; Babo, M.; Baron, P.; Bazin, D.; Beceiro-Novo, S.; Belkhiria, C.; Blaizot, M.; Blank, B.; Bradt, J.; Cardella, G.; Carpenter, L.; Ceruti, S.; De Filippo, E.; Delagnes, E.; De Luca, S.; De Witte, H.; Druillole, F.; Duclos, B.; Favela, F.; Fritsch, A.; Giovinazzo, J.; Gueye, C.; Isobe, T.; Hellmuth, P.; Huss, C.; Lachacinski, B.; Laffoley, A. T.; Lebertre, G.; Legeard, L.; Lynch, W. G.; Marchi, T.; Martina, L.; Maugeais, C.; Mittig, W.; Nalpas, L.; Pagano, E. V.; Pancin, J.; Poleshchuk, O.; Pedroza, J. L.; Pibernat, J.; Primault, S.; Raabe, R.; Raine, B.; Rebii, A.; Renaud, M.; Roger, T.; Roussel-Chomaz, P.; Russotto, P.; Saccà, G.; Saillant, F.; Sizun, P.; Suzuki, D.; Swartz, J. A.; Tizon, A.; Usher, N.; Wittwer, G.; Yang, J. C.

2018-04-01

General Electronics for TPCs (GET) is a generic, reconfigurable and comprehensive electronics and data-acquisition system for nuclear physics instrumentation of up to 33792 channels. The system consists of a custom-designed ASIC for signal processing, front-end cards that each house 4 ASIC chips and digitize the data in parallel through 12-bit ADCs, concentration boards to read and process the digital data from up to 16 ASICs, a 3-level trigger and master clock module to trigger the system and synchronize the data, as well as all of the associated firmware, communication and data-acquisition software. An overview of the system including its specifications and measured performances are presented.

CdZnTe Image Detectors for Hard-X-Ray Telescopes

NASA Technical Reports Server (NTRS)

Chen, C. M. Hubert; Cook, Walter R.; Harrison, Fiona A.; Lin, Jiao Y. Y.; Mao, Peter H.; Schindler, Stephen M.

2005-01-01

Arrays of CdZnTe photodetectors and associated electronic circuitry have been built and tested in a continuing effort to develop focal-plane image sensor systems for hard-x-ray telescopes. Each array contains 24 by 44 pixels at a pitch of 498 m. The detector designs are optimized to obtain low power demand with high spectral resolution in the photon- energy range of 5 to 100 keV. More precisely, each detector array is a hybrid of a CdZnTe photodetector array and an application-specific integrated circuit (ASIC) containing an array of amplifiers in the same pixel pattern as that of the detectors. The array is fabricated on a single crystal of CdZnTe having dimensions of 23.6 by 12.9 by 2 mm. The detector-array cathode is a monolithic platinum contact. On the anode plane, the contact metal is patterned into the aforementioned pixel array, surrounded by a guard ring that is 1 mm wide on three sides and is 0.1 mm wide on the fourth side so that two such detector arrays can be placed side-by-side to form a roughly square sensor area with minimal dead area between them. Figure 1 shows two anode patterns. One pattern features larger pixel anode contacts, with a 30-m gap between them. The other pattern features smaller pixel anode contacts plus a contact for a shaping electrode in the form of a grid that separates all the pixels. In operation, the grid is held at a potential intermediate between the cathode and anode potentials to steer electric charges toward the anode in order to reduce the loss of charges in the inter-anode gaps. The CdZnTe photodetector array is mechanically and electrically connected to the ASIC (see Figure 2), either by use of indium bump bonds or by use of conductive epoxy bumps on the CdZnTe array joined to gold bumps on the ASIC. Hence, the output of each pixel detector is fed to its own amplifier chain.

A Spaceborne Synthetic Aperture Radar Partial Fixed-Point Imaging System Using a Field- Programmable Gate Array—Application-Specific Integrated Circuit Hybrid Heterogeneous Parallel Acceleration Technique

PubMed Central

Li, Bingyi; Chen, Liang; Wei, Chunpeng; Xie, Yizhuang; Chen, He; Yu, Wenyue

2017-01-01

With the development of satellite load technology and very large scale integrated (VLSI) circuit technology, onboard real-time synthetic aperture radar (SAR) imaging systems have become a solution for allowing rapid response to disasters. A key goal of the onboard SAR imaging system design is to achieve high real-time processing performance with severe size, weight, and power consumption constraints. In this paper, we analyse the computational burden of the commonly used chirp scaling (CS) SAR imaging algorithm. To reduce the system hardware cost, we propose a partial fixed-point processing scheme. The fast Fourier transform (FFT), which is the most computation-sensitive operation in the CS algorithm, is processed with fixed-point, while other operations are processed with single precision floating-point. With the proposed fixed-point processing error propagation model, the fixed-point processing word length is determined. The fidelity and accuracy relative to conventional ground-based software processors is verified by evaluating both the point target imaging quality and the actual scene imaging quality. As a proof of concept, a field- programmable gate array—application-specific integrated circuit (FPGA-ASIC) hybrid heterogeneous parallel accelerating architecture is designed and realized. The customized fixed-point FFT is implemented using the 130 nm complementary metal oxide semiconductor (CMOS) technology as a co-processor of the Xilinx xc6vlx760t FPGA. A single processing board requires 12 s and consumes 21 W to focus a 50-km swath width, 5-m resolution stripmap SAR raw data with a granularity of 16,384 × 16,384. PMID:28672813

A Spaceborne Synthetic Aperture Radar Partial Fixed-Point Imaging System Using a Field- Programmable Gate Array-Application-Specific Integrated Circuit Hybrid Heterogeneous Parallel Acceleration Technique.

PubMed

Yang, Chen; Li, Bingyi; Chen, Liang; Wei, Chunpeng; Xie, Yizhuang; Chen, He; Yu, Wenyue

2017-06-24

With the development of satellite load technology and very large scale integrated (VLSI) circuit technology, onboard real-time synthetic aperture radar (SAR) imaging systems have become a solution for allowing rapid response to disasters. A key goal of the onboard SAR imaging system design is to achieve high real-time processing performance with severe size, weight, and power consumption constraints. In this paper, we analyse the computational burden of the commonly used chirp scaling (CS) SAR imaging algorithm. To reduce the system hardware cost, we propose a partial fixed-point processing scheme. The fast Fourier transform (FFT), which is the most computation-sensitive operation in the CS algorithm, is processed with fixed-point, while other operations are processed with single precision floating-point. With the proposed fixed-point processing error propagation model, the fixed-point processing word length is determined. The fidelity and accuracy relative to conventional ground-based software processors is verified by evaluating both the point target imaging quality and the actual scene imaging quality. As a proof of concept, a field- programmable gate array-application-specific integrated circuit (FPGA-ASIC) hybrid heterogeneous parallel accelerating architecture is designed and realized. The customized fixed-point FFT is implemented using the 130 nm complementary metal oxide semiconductor (CMOS) technology as a co-processor of the Xilinx xc6vlx760t FPGA. A single processing board requires 12 s and consumes 21 W to focus a 50-km swath width, 5-m resolution stripmap SAR raw data with a granularity of 16,384 × 16,384.

Frontend Receiver Electronics for High Frequency Monolithic CMUT-on-CMOS Imaging Arrays

PubMed Central

Gurun, Gokce; Hasler, Paul; Degertekin, F. Levent

2012-01-01

This paper describes the design of CMOS receiver electronics for monolithic integration with capacitive micromachined ultrasonic transducer (CMUT) arrays for high-frequency intravascular ultrasound imaging. A custom 8-inch wafer is fabricated in a 0.35 μm two-poly, four-metal CMOS process and then CMUT arrays are built on top of the application specific integrated circuits (ASICs) on the wafer. We discuss advantages of the single-chip CMUT-on-CMOS approach in terms of receive sensitivity and SNR. Low-noise and high-gain design of a transimpedance amplifier (TIA) optimized for a forward-looking volumetric-imaging CMUT array element is discussed as a challenging design example. Amplifier gain, bandwidth, dynamic range and power consumption trade-offs are discussed in detail. With minimized parasitics provided by the CMUT-on-CMOS approach, the optimized TIA design achieves a 90 fA/√Hz input referred current noise, which is less than the thermal-mechanical noise of the CMUT element. We show successful system operation with a pulse-echo measurement. Transducer noise-dominated detection in immersion is also demonstrated through output noise spectrum measurement of the integrated system at different CMUT bias voltages. A noise figure of 1.8 dB is obtained in the designed CMUT bandwidth of 10 MHz to 20 MHz. PMID:21859585

Front-end receiver electronics for high-frequency monolithic CMUT-on-CMOS imaging arrays.

PubMed

Gurun, Gokce; Hasler, Paul; Degertekin, F

2011-08-01

This paper describes the design of CMOS receiver electronics for monolithic integration with capacitive micromachined ultrasonic transducer (CMUT) arrays for highfrequency intravascular ultrasound imaging. A custom 8-inch (20-cm) wafer is fabricated in a 0.35-μm two-poly, four-metal CMOS process and then CMUT arrays are built on top of the application specific integrated circuits (ASICs) on the wafer. We discuss advantages of the single-chip CMUT-on-CMOS approach in terms of receive sensitivity and SNR. Low-noise and high-gain design of a transimpedance amplifier (TIA) optimized for a forward-looking volumetric-imaging CMUT array element is discussed as a challenging design example. Amplifier gain, bandwidth, dynamic range, and power consumption trade-offs are discussed in detail. With minimized parasitics provided by the CMUT-on-CMOS approach, the optimized TIA design achieves a 90 fA/√Hz input-referred current noise, which is less than the thermal-mechanical noise of the CMUT element. We show successful system operation with a pulseecho measurement. Transducer-noise-dominated detection in immersion is also demonstrated through output noise spectrum measurement of the integrated system at different CMUT bias voltages. A noise figure of 1.8 dB is obtained in the designed CMUT bandwidth of 10 to 20 MHz.

Parallel ICA and its hardware implementation in hyperspectral image analysis

NASA Astrophysics Data System (ADS)

Du, Hongtao; Qi, Hairong; Peterson, Gregory D.

2004-04-01

Advances in hyperspectral images have dramatically boosted remote sensing applications by providing abundant information using hundreds of contiguous spectral bands. However, the high volume of information also results in excessive computation burden. Since most materials have specific characteristics only at certain bands, a lot of these information is redundant. This property of hyperspectral images has motivated many researchers to study various dimensionality reduction algorithms, including Projection Pursuit (PP), Principal Component Analysis (PCA), wavelet transform, and Independent Component Analysis (ICA), where ICA is one of the most popular techniques. It searches for a linear or nonlinear transformation which minimizes the statistical dependence between spectral bands. Through this process, ICA can eliminate superfluous but retain practical information given only the observations of hyperspectral images. One hurdle of applying ICA in hyperspectral image (HSI) analysis, however, is its long computation time, especially for high volume hyperspectral data sets. Even the most efficient method, FastICA, is a very time-consuming process. In this paper, we present a parallel ICA (pICA) algorithm derived from FastICA. During the unmixing process, pICA divides the estimation of weight matrix into sub-processes which can be conducted in parallel on multiple processors. The decorrelation process is decomposed into the internal decorrelation and the external decorrelation, which perform weight vector decorrelations within individual processors and between cooperative processors, respectively. In order to further improve the performance of pICA, we seek hardware solutions in the implementation of pICA. Until now, there are very few hardware designs for ICA-related processes due to the complicated and iterant computation. This paper discusses capacity limitation of FPGA implementations for pICA in HSI analysis. A synthesis of Application-Specific Integrated Circuit (ASIC) is designed for pICA-based dimensionality reduction in HSI analysis. The pICA design is implemented using standard-height cells and aimed at TSMC 0.18 micron process. During the synthesis procedure, three ICA-related reconfigurable components are developed for the reuse and retargeting purpose. Preliminary results show that the standard-height cell based ASIC synthesis provide an effective solution for pICA and ICA-related processes in HSI analysis.

Using Spare Logic Resources To Create Dynamic Test Points

NASA Technical Reports Server (NTRS)

Katz, Richard; Kleyner, Igor

2011-01-01

A technique has been devised to enable creation of a dynamic set of test points in an embedded digital electronic system. As a result, electronics contained in an application specific circuit [e.g., gate array, field programmable gate array (FPGA)] can be internally probed, even when contained in a closed housing during all phases of test. In the present technique, the test points are not fixed and limited to a small number; the number of test points can vastly exceed the number of buffers or pins, resulting in a compact footprint. Test points are selected by means of spare logic resources within the ASIC(s) and/or FPGA(s). A register is programmed with a command, which is used to select the signals that are sent off-chip and out of the housing for monitoring by test engineers and external test equipment. The register can be commanded by any suitable means: for example, it could be commanded through a command port that would normally be used in the operation of the system. In the original application of the technique, commanding of the register is performed via a MIL-STD-1553B communication subsystem.

The Panda Strip Asic: Pasta

NASA Astrophysics Data System (ADS)

Lai, A.

2018-01-01

PASTA is the 64 channel front-end chip, designed in a 110 nm CMOS technology to read out the strip sensors of the Micro Vertex Detector (MVD) of the PANDA experiment. This chip provides high resolution timestamp and deposited charge information by means of the time-over-threshold technique. Its working principle is based on a predecessor, the TOFPET ASIC, that was designed for medical applications. A general restructuring of the architecture was needed, in order to meet the specific requirements imposed by the physics programme of PANDA, especially in terms of radiation tolerance, spatial constraints, and readout in absence of a first level hardware trigger. The first revision of PASTA is currently under evaluation at the Forschungszentrum Jülich, where a data acquisition system dedicated to the MVD prototypes has been developed. This paper describes the main aspect of the chip design, gives an overview of the data acquisition system used for the verification, and shows the first results regarding the performance of PASTA.

Evidence for the involvement of ASIC3 in sensory mechanotransduction in proprioceptors

PubMed Central

Lin, Shing-Hong; Cheng, Yuan-Ren; Banks, Robert W.; Min, Ming-Yuan; Bewick, Guy S.; Chen, Chih-Cheng

2016-01-01

Acid-sensing ion channel 3 (ASIC3) is involved in acid nociception, but its possible role in neurosensory mechanotransduction is disputed. We report here the generation of Asic3-knockout/eGFPf-knockin mice and subsequent characterization of heterogeneous expression of ASIC3 in the dorsal root ganglion (DRG). ASIC3 is expressed in parvalbumin (Pv+) proprioceptor axons innervating muscle spindles. We further generate a floxed allele of Asic3 (Asic3f/f) and probe the role of ASIC3 in mechanotransduction in neurite-bearing Pv+ DRG neurons through localized elastic matrix movements and electrophysiology. Targeted knockout of Asic3 disrupts spindle afferent sensitivity to dynamic stimuli and impairs mechanotransduction in Pv+ DRG neurons because of substrate deformation-induced neurite stretching, but not to direct neurite indentation. In behavioural tasks, global knockout (Asic3−/−) and Pv-Cre::Asic3f/f mice produce similar deficits in grid and balance beam walking tasks. We conclude that, at least in mouse, ASIC3 is a molecular determinant contributing to dynamic mechanosensitivity in proprioceptors. PMID:27161260

Proton and non-proton activation of ASIC channels

PubMed Central

Gautschi, Ivan; van Bemmelen, Miguel Xavier; Schild, Laurent

2017-01-01

The Acid-Sensing Ion Channels (ASIC) exhibit a fast desensitizing current when activated by pH values below 7.0. By contrast, non-proton ligands are able to trigger sustained ASIC currents at physiological pHs. To analyze the functional basis of the ASIC desensitizing and sustained currents, we have used ASIC1a and ASIC2a mutants with a cysteine in the pore vestibule for covalent binding of different sulfhydryl reagents. We found that ASIC1a and ASIC2a exhibit two distinct currents, a proton-induced desensitizing current and a sustained current triggered by sulfhydryl reagents. These currents differ in their pH dependency, their sensitivity to the sulfhydryl reagents, their ionic selectivity and their relative magnitude. We propose a model for ASIC1 and ASIC2 activity where the channels can function in two distinct modes, a desensitizing mode and a sustained mode depending on the activating ligands. The pore vestibule of the channel represents a functional site for binding non-proton ligands to activate ASIC1 and ASIC2 at neutral pH and to prevent channel desensitization. PMID:28384246

DOE Office of Scientific and Technical Information (OSTI.GOV)

DE GERONIMO,G.; FRIED, J.; FROST, E.

We describe a front-end application specific integrated circuit (ASIC) developed for a silicon Compton telescope. Composed of 32 channels, it reads out signals in both polarities from each side of a Silicon strip sensor, 2 mm thick 27 cm long, characterized by a strip capacitance of 30 pF. Each front-end channel provides low-noise charge amplification, shaping with a stabilized baseline, discrimination, and peak detection with an analog memory. The channels can process events simultaneously, and the read out is sparsified. The charge amplifier makes uses a dual-cascode configuration and dual-polarity adaptive reset, The low-hysteresis discriminator and the multi-phase peak detectormore » process signals with a dynamic range in excess of four hundred. An equivalent noise charge (ENC) below 200 electrons was measured at 30 pF, with a slope of about 4.5 electrons/pF at a peaking time of 4 {micro}s. With a total dissipated power of 5 mW the channel covers an energy range up to 3.2 MeV.« less

An Efficient Hardware Circuit for Spike Sorting Based on Competitive Learning Networks.

PubMed

Chen, Huan-Yuan; Chen, Chih-Chang; Hwang, Wen-Jyi

2017-09-28

This study aims to present an effective VLSI circuit for multi-channel spike sorting. The circuit supports the spike detection, feature extraction and classification operations. The detection circuit is implemented in accordance with the nonlinear energy operator algorithm. Both the peak detection and area computation operations are adopted for the realization of the hardware architecture for feature extraction. The resulting feature vectors are classified by a circuit for competitive learning (CL) neural networks. The CL circuit supports both online training and classification. In the proposed architecture, all the channels share the same detection, feature extraction, learning and classification circuits for a low area cost hardware implementation. The clock-gating technique is also employed for reducing the power dissipation. To evaluate the performance of the architecture, an application-specific integrated circuit (ASIC) implementation is presented. Experimental results demonstrate that the proposed circuit exhibits the advantages of a low chip area, a low power dissipation and a high classification success rate for spike sorting.

An Efficient VLSI Architecture for Multi-Channel Spike Sorting Using a Generalized Hebbian Algorithm

PubMed Central

Chen, Ying-Lun; Hwang, Wen-Jyi; Ke, Chi-En

2015-01-01

A novel VLSI architecture for multi-channel online spike sorting is presented in this paper. In the architecture, the spike detection is based on nonlinear energy operator (NEO), and the feature extraction is carried out by the generalized Hebbian algorithm (GHA). To lower the power consumption and area costs of the circuits, all of the channels share the same core for spike detection and feature extraction operations. Each channel has dedicated buffers for storing the detected spikes and the principal components of that channel. The proposed circuit also contains a clock gating system supplying the clock to only the buffers of channels currently using the computation core to further reduce the power consumption. The architecture has been implemented by an application-specific integrated circuit (ASIC) with 90-nm technology. Comparisons to the existing works show that the proposed architecture has lower power consumption and hardware area costs for real-time multi-channel spike detection and feature extraction. PMID:26287193

An Efficient Hardware Circuit for Spike Sorting Based on Competitive Learning Networks

PubMed Central

Chen, Huan-Yuan; Chen, Chih-Chang

2017-01-01

This study aims to present an effective VLSI circuit for multi-channel spike sorting. The circuit supports the spike detection, feature extraction and classification operations. The detection circuit is implemented in accordance with the nonlinear energy operator algorithm. Both the peak detection and area computation operations are adopted for the realization of the hardware architecture for feature extraction. The resulting feature vectors are classified by a circuit for competitive learning (CL) neural networks. The CL circuit supports both online training and classification. In the proposed architecture, all the channels share the same detection, feature extraction, learning and classification circuits for a low area cost hardware implementation. The clock-gating technique is also employed for reducing the power dissipation. To evaluate the performance of the architecture, an application-specific integrated circuit (ASIC) implementation is presented. Experimental results demonstrate that the proposed circuit exhibits the advantages of a low chip area, a low power dissipation and a high classification success rate for spike sorting. PMID:28956859

An Efficient VLSI Architecture for Multi-Channel Spike Sorting Using a Generalized Hebbian Algorithm.

PubMed

Chen, Ying-Lun; Hwang, Wen-Jyi; Ke, Chi-En

2015-08-13

A novel VLSI architecture for multi-channel online spike sorting is presented in this paper. In the architecture, the spike detection is based on nonlinear energy operator (NEO), and the feature extraction is carried out by the generalized Hebbian algorithm (GHA). To lower the power consumption and area costs of the circuits, all of the channels share the same core for spike detection and feature extraction operations. Each channel has dedicated buffers for storing the detected spikes and the principal components of that channel. The proposed circuit also contains a clock gating system supplying the clock to only the buffers of channels currently using the computation core to further reduce the power consumption. The architecture has been implemented by an application-specific integrated circuit (ASIC) with 90-nm technology. Comparisons to the existing works show that the proposed architecture has lower power consumption and hardware area costs for real-time multi-channel spike detection and feature extraction.

Monolithic integration of GMR sensors for standard CMOS-IC current sensing

NASA Astrophysics Data System (ADS)

De Marcellis, A.; Reig, C.; Cubells-Beltrán, M.-D.; Madrenas, J.; Santos, J. D.; Cardoso, S.; Freitas, P. P.

2017-09-01

In this work we report on the development of Giant Magnetoresistive (GMR) sensors for off-line current measurements in standard integrated circuits. An ASIC has been specifically designed and fabricated in the well-known AMS-0.35 μm CMOS technology, including the electronic circuitry for sensor interfacing. It implements an oscillating circuit performing a voltage-to-frequency conversion. Subsequently, a fully CMOS-compatible low temperature post-process has been applied for depositing the GMR sensing devices in a full-bridge configuration onto the buried current straps. Sensitivity and resolution of these sensors have been investigated achieving experimental results that show a detection sensitivity of about 100 Hz/mA, with a resolution of about 5 μA.

A 1280×1024-15μm CTIA ROIC for SWIR FPAs

NASA Astrophysics Data System (ADS)

Eminoglu, Selim; Isikhan, Murat; Bayhan, Nusret; Gulden, M. A.; Incedere, O. S.; Soyer, S. T.; Kocak, Serhat; Yalcin, Cem; Ustundag, M. Cem B.; Turan, Ozge; Eksi, Umut; Akin, Tayfun

2015-06-01

This paper reports the development of a new SXGA format low-noise CTIA ROIC (MT12815CA-3G) suitable for mega-pixel SWIR InGaAs detector arrays for low-light imaging applications. MT12815CA-3G is the first mega-pixel standard ROIC product from Mikro-Tasarim, which is a fabless semiconductor company specialized in the development of ROICs and ASICs for visible and infrared hybrid imaging sensors. MT12815CA-3G is a low-noise snapshot mega-pixel CTIA ROIC, has a format of 1280 × 1024 (SXGA) and pixel pitch of 15 μm. MT12815CA-3G has been developed with the system-on-chip architecture in mind, where all the timing and biasing for this ROIC are generated on-chip without requiring any special external inputs. MT12815CA-3G is a highly configurable ROIC, where many of its features can be programmed through a 3-wire serial interface allowing on-the-fly configuration of many ROIC features. It performs snapshot operation both using Integrate-Then-Read (ITR) and Integrate-While-Read (IWR) modes. The CTIA type pixel input circuitry has 3 gain modes with programmable full-well-capacity (FWC) values of 10K e-, 20K e-, and 350K e- in the very high gain (VHG), high-gain (HG), and low-gain (LG) modes, respectively. MT12815CA-3G has an input referred noise level of less than 5 e- in the very high gain (VHG) mode, suitable for very low-noise SWIR imaging applications. MT12815CA-3G has 8 analog video outputs that can be programmed in 8, 4, or 2-output modes with a selectable analog reference for pseudo-differential operation. The ROIC runs at 10 MHz and supports frame rate values up to 55 fps in the 8-output mode. The integration time of the ROIC can be programmed up to 1s in steps of 0.1 μs. The ROIC uses 3.3 V and 1.8V supply voltages and dissipates less than 350 mW in the 4-output mode. MT12815CA-3G is fabricated using a modern mixed-signal CMOS process on 200 mm CMOS wafers, and there are 44 ROIC parts per wafer. The probe tests show that the die yield is higher than 70%, which corresponds to more than 30 working ROIC parts per wafer typically. MT12815CA-3G ROIC is available as tested wafers or dies, where a detailed test report and wafer map are provided for each wafer. A compact USB 3.0 based test camera and imaging software are also available for the customers to test and evaluate the imaging performance of SWIR sensors built using MT12815CA-3G ROICs. Mikro-Tasarim has also recently developed a programmable mixed-signal application specific integrated circuit (ASIC), called MTAS1410X8, which is designed to perform ROIC driving and digitization functions for ROICs with analog outputs, such as MT12815CA-3G and MT6415CA ROIC products of Mikro-Tasarim. MTAS1410X8 has 8 simultaneously working 14-bit analog-to-digital converters (ADCs) with integrated programmable gain amplifiers (PGAs), video input buffers, programmable controller, and high-speed digital video interface supporting various formats including Camera-Link. MT12815CA-3G ROIC together with MTAS1410X8 ASIC can be used to develop low-noise high-resolution SWIR imaging sensors with low power dissipation and reduced board area for the camera electronics.

Parallel-Processing Equalizers for Multi-Gbps Communications

NASA Technical Reports Server (NTRS)

Gray, Andrew; Ghuman, Parminder; Hoy, Scott; Satorius, Edgar H.

2004-01-01

Architectures have been proposed for the design of frequency-domain least-mean-square complex equalizers that would be integral parts of parallel- processing digital receivers of multi-gigahertz radio signals and other quadrature-phase-shift-keying (QPSK) or 16-quadrature-amplitude-modulation (16-QAM) of data signals at rates of multiple gigabits per second. Equalizers as used here denotes receiver subsystems that compensate for distortions in the phase and frequency responses of the broad-band radio-frequency channels typically used to convey such signals. The proposed architectures are suitable for realization in very-large-scale integrated (VLSI) circuitry and, in particular, complementary metal oxide semiconductor (CMOS) application- specific integrated circuits (ASICs) operating at frequencies lower than modulation symbol rates. A digital receiver of the type to which the proposed architecture applies (see Figure 1) would include an analog-to-digital converter (A/D) operating at a rate, fs, of 4 samples per symbol period. To obtain the high speed necessary for sampling, the A/D and a 1:16 demultiplexer immediately following it would be constructed as GaAs integrated circuits. The parallel-processing circuitry downstream of the demultiplexer, including a demodulator followed by an equalizer, would operate at a rate of only fs/16 (in other words, at 1/4 of the symbol rate). The output from the equalizer would be four parallel streams of in-phase (I) and quadrature (Q) samples.

Upregulation of nuclear factor‑κB and acid sensing ion channel 3 in dorsal root ganglion following application of nucleus pulposus onto the nerve root in rats.

PubMed

Wang, Dong; Pan, Hao; Zhu, Hang; Zhu, Li; He, Yong-Jiang; Wang, Jian; Jia, Gao-Yong

2017-10-01

The nucleus pulposus (NP) is an avascular, hydrated tissue that permits the intervertebral disc to resist compressive loads to the spine. To determine the mechanisms by which intervertebral disc degeneration is caused by the nucleus pulposus, the expression and regulation of nuclear factor (NF)‑κB and acid sensing ion channel 3 (ASIC3) were examined. For the intervertebral disc degeneration model, NP was harvested from the tail of rats and applied to the L5 dorsal root ganglion (DRG). The mechanical pain withdrawal threshold (PWT) in NP model rats was assessed. Reverse transcription‑quantitative polymerase chain reaction and western blotting were used to examine NF‑κB and ASIC3 expression levels in DRG. Finally, the effect of the NF‑κB inhibitor pyrrolidine dithiocarbamate (PDTC) and the ASIC3 signaling pathway blocker amiloride were examined. Rats exposed to NP exhibited decreased PWT for 12 days, and NF‑κB and ASIC3 was upregulated in DRG induced by NP 14 days after surgery. After administration of amiloride and PDTC to DRG affected by NP, the levels of nitric oxide (NO), tumor necrosis factor‑α (TNF‑α), interleukin‑6 (IL‑6), NF‑κB and ASIC3 were downregulated, and the levels of aquaporin (AQP) 1 and AQP3 were significantly increased for 14 days. In conclusion, these results suggested that NF‑κB and ASIC3 may serve an important role in intervertebral disc degeneration caused by NP.

Human ASIC3 channel dynamically adapts its activity to sense the extracellular pH in both acidic and alkaline directions.

PubMed

Delaunay, Anne; Gasull, Xavier; Salinas, Miguel; Noël, Jacques; Friend, Valérie; Lingueglia, Eric; Deval, Emmanuel

2012-08-07

In rodent sensory neurons, acid-sensing ion channel 3 (ASIC3) has recently emerged as a particularly important sensor of nonadaptive pain associated with tissue acidosis. However, little is known about the human ASIC3 channel, which includes three splice variants differing in their C-terminal domain (hASIC3a, hASIC3b, and hASIC3c). hASIC3a transcripts represent the main mRNAs expressed in both peripheral and central neuronal tissues (dorsal root ganglia [DRG], spinal cord, and brain), where a small proportion of hASIC3c transcripts is also detected. We show that hASIC3 channels (hASIC3a, hASIC3b, or hASIC3c) are able to directly sense extracellular pH changes not only during acidification (up to pH 5.0), but also during alkalization (up to pH 8.0), an original and inducible property yet unknown. When the external pH decreases, hASIC3 display a transient acid mode with brief activation that is relevant to the classical ASIC currents, as previously described. On the other hand, an external pH increase activates a sustained alkaline mode leading to a constitutive activity at resting pH. Both modes are inhibited by the APETx2 toxin, an ASIC3-type channel inhibitor. The alkaline sensitivity of hASIC3 is an intrinsic property of the channel, which is supported by the extracellular loop and involves two arginines (R68 and R83) only present in the human clone. hASIC3 is thus able to sense the extracellular pH in both directions and therefore to dynamically adapt its activity between pH 5.0 and 8.0, a property likely to participate in the fine tuning of neuronal membrane potential and to neuron sensitization in various pH environments.

In situ hybridization evidence for the coexistence of ASIC and TRPV1 within rat single sensory neurons.

PubMed

Ugawa, Shinya; Ueda, Takashi; Yamamura, Hisao; Shimada, Shoichi

2005-05-20

The activation of nociceptors by protons plays a crucial role in the initiation and maintenance of acidosis-linked pain. Acid-sensing ion channel (ASIC) and transient receptor potential/vanilloid receptor subtype-1 (TRPV1) encode proton-activated cation channels expressed by nociceptors and the opening of these channels results in nociceptor excitation. Histological relations among ASIC clones and the colocalization of each ASIC subunit and TRPV1 within single sensory neurons were examined on serial sections of rat dorsal root ganglia (DRG) using in situ hybridization histochemistry. ASIC1a transcripts were expressed in 20-25% of the DRG neurons, and most of the neurons had small (<30 microm)-diameter cell bodies. ASIC1b transcripts and ASIC3 transcripts were expressed in approximately 10% and 30-35% of the DRG neurons, respectively, and the greater part of each population was located in small-to-medium (30-50 microm)-diameter cells. The ASIC1a transcripts and ASIC1b transcripts were basically localized in the distinct populations of the DRG neurons, while approximately 20% of the ASIC1a-positive neurons and approximately 10% of the ASIC1b-positive neurons expressed ASIC3 transcripts. TRPV1 transcripts were expressed in 35-40% of the DRG neurons, and most of the TRPV1-positive neurons had small-diameter cell bodies. Intense expression signals for ASIC1a transcripts were detected in 40-45% of the TRPV1-positive neurons. Neurons expressing both ASIC1b and TRPV1 transcripts were barely detected in the DRG. Approximately 30% of the TRPV1-positive neurons expressed ASIC3 transcripts, and the double-labeled neurons were comprised of both small-diameter and medium-diameter cells. Approximately 13% of the TRPV1-positive neurons expressed both ASIC1a and ASIC3 transcripts.

NASA/BAE SYSTEMS SpaceWire Effort

NASA Technical Reports Server (NTRS)

Rakow, Glenn Parker; Schnurr, Richard G.; Kapcio, Paul

2003-01-01

This paper discusses the state of the NASA and BAE SYSTEMS developments of SpaceWire. NASA has developed intellectual property that implements SpaceWire in Register Transfer Level (RTL) VHDL for a SpaceWire link and router. This design has been extensively verified using directed tests from the SpaceWire Standard and design specification, as well as being randomly tested to flush out hard to find bugs in the code. The high level features of the design will be discussed, including the support for multiple time code masters, which will be useful for the James Webb Space Telescope electrical architecture. This design is now ready to be targeted to FPGA's and ASICs. Target utilization and performance information will be presented for Spaceflight worthy FPGA's and a discussion of the ASIC implementations will be addressed. In particular, the BAE SYSTEMS ASIC will be highlighted which will be implemented on their .25micron rad-hard line. The chip will implement a 4-port router with the ability to tie chips together to make larger routers without external glue logic. This part will have integrated LVDS drivers/receivers, include a PLL and include skew control logic. It will be targeted to run at greater than 300 MHz and include the implementation for the proposed SpaceWire transport layer. The need to provide a reliable transport mechanism for SpaceWire has been identified by both NASA And ESA, who are attempting to define a transport layer standard that utilizes a low overhead, low latency connection oriented approach that works end-to-end. This layer needs to be implemented in hardware to prevent bottlenecks.

NASA/BAE Systems SpaceWire Efforts

NASA Technical Reports Server (NTRS)

Rakow, Glenn Parker; Schnurr, Richard G.; Kapcio, Paul

2003-01-01

This paper discusses the state of the NASA and BAE SYSTEMS developments using Spacewire. NASA has developed intellectual property that implements Spacewire in Register Transfer Level VHDL for a Spacewire link and router. This design has been extensively verified using directed tests from the Spacewire Standard and design specification, as well as being randomly tested to flush out hard to find bugs in the code. The high level features of the design will be discussed, including the support for multiple time code masters, which will be useful for the James Webb Space Telescope electrical architecture. This design is now ready to be targeted to FPGA's and ASICs. Target utilization and performance information will be presented for some spaceflight qualified FPGA's and a discussion of the ASIC implementations will be addressed. In particular, the BAE SYSTEMS ASIC will be highlighted which will be implemented in their 0.25 micron rad-hard line. The chip will implement a 4-port router with the ability to tie chips together to make larger routers without external glue logic. This part will have integrated LVDS driver/receivers, include a PLL and include skew control logic. It will be targeted to run at greater than 300 MHz and include the implementation for the proposed Spacewire transport layer. The need to provide a reliable transport mechanism for Spacewire has been identified by both NASA and ESA, who are attempting to define a transport layer standard that utilizes a low overhead, low latency connection oriented approach. The Transport layer needs to be implemented in hardware-to prevent bottlenecks.

SFERA: An Integrated Circuit for the Readout of X and gamma -Ray Detectors

NASA Astrophysics Data System (ADS)

Schembari, Filippo; Quaglia, Riccardo; Bellotti, Giovanni; Fiorini, Carlo

2016-06-01

In this work we present SFERA, a low-noise fully-programmable 16 channel readout ASIC designed for both Xand y-ray spectroscopy and imaging applications. The chip is designed to process signals coming from solid-state detectors and CMOS preamplifiers. The design has been guided by the use of Silicon Drift Detectors (SDDs) and CUBE charge sensitive amplifiers (CSAs), although we consider the ASIC sufficiently versatile to be used with other types of detectors. Five different gains are implemented, namely 2800 e-, 4400 e-, 10000 e-, 14000 e- and 20000 e-, considering the input connected to a 25 fF feedback capacitance CMOS preamplifier. Filter peaking times (tP) are also programmable among 0.5, 1, 2, 3, 4 and 6 μs. Each readout channel is the cascade of a 9th order semi-Gaussian shaping-amplifier (SA) and a peak detector (PKS), followed by a dedicated pile-up rejection (PUR) digital logic. Three data multiplexing strategies are implemented: the so-called polling X, intended for high-rate X-ray applications, the polling y, for scintillation light detection and the sparse, for signals derandomization. The spectroscopic characterization has shown an energy resolution of 122.1 eV FWHM on the Mn-Ku line of an 55Fe X-ray source using a 10 mm2 SDD cooled at -35 °C at 4 μs filter peaking time. The measured resolution is 130 eV at the peaking time of 500 ns. At 1 Mcps input count rate and 500 ns peaking time, we have measured 42% of processed events at the output of the ASIC after the PUR selection. Output data can be digitized on-chip by means of an embedded 12-bit successive-approximation ADC. The effective resolution of the data converter is 10.75-bit when operated at 4.5 MS/s. The chosen technology is the AMS 0.35 μm CMOS and the chip area occupancy is 5 × 5 mm2.

An acid-sensing ion channel from shark (Squalus acanthias) mediates transient and sustained responses to protons.

PubMed

Springauf, Andreas; Gründer, Stefan

2010-03-01

Acid-sensing ion channels (ASICs) are proton-gated Na(+) channels. They are implicated in synaptic transmission, detection of painful acidosis, and possibly sour taste. The typical ASIC current is a transient, completely desensitizing current that can be blocked by the diuretic amiloride. ASICs are present in chordates but are absent in other animals. They have been cloned from urochordates, jawless vertebrates, cartilaginous shark and bony fish, from chicken and different mammals. Strikingly, all ASICs that have so far been characterized from urochordates, jawless vertebrates and shark are not gated by protons, suggesting that proton gating evolved relatively late in bony fish and that primitive ASICs had a different and unknown gating mechanism. Recently, amino acids that are crucial for the proton gating of rat ASIC1a have been identified. These residues are completely conserved in shark ASIC1b (sASIC1b), prompting us to re-evaluate the proton sensitivity of sASIC1b. Here we show that, contrary to previous findings, sASIC1b is indeed gated by protons with half-maximal activation at pH 6.0. sASIC1b desensitizes quickly but incompletely, efficiently encoding transient as well as sustained proton signals. Our results show that the conservation of the amino acids crucial for proton gating can predict proton sensitivity of an ASIC and increase our understanding of the evolution of ASICs.

SPIDR, a general-purpose readout system for pixel ASICs

NASA Astrophysics Data System (ADS)

van der Heijden, B.; Visser, J.; van Beuzekom, M.; Boterenbrood, H.; Kulis, S.; Munneke, B.; Schreuder, F.

2017-02-01

The SPIDR (Speedy PIxel Detector Readout) system is a flexible general-purpose readout platform that can be easily adapted to test and characterize new and existing detector readout ASICs. It is originally designed for the readout of pixel ASICs from the Medipix/Timepix family, but other types of ASICs or front-end circuits can be read out as well. The SPIDR system consists of an FPGA board with memory and various communication interfaces, FPGA firmware, CPU subsystem and an API library on the PC . The FPGA firmware can be adapted to read out other ASICs by re-using IP blocks. The available IP blocks include a UDP packet builder, 1 and 10 Gigabit Ethernet MAC's and a "soft core" CPU . Currently the firmware is targeted at the Xilinx VC707 development board and at a custom board called Compact-SPIDR . The firmware can easily be ported to other Xilinx 7 series and ultra scale FPGAs. The gap between an ASIC and the data acquisition back-end is bridged by the SPIDR system. Using the high pin count VITA 57 FPGA Mezzanine Card (FMC) connector only a simple chip carrier PCB is required. A 1 and a 10 Gigabit Ethernet interface handle the connection to the back-end. These can be used simultaneously for high-speed data and configuration over separate channels. In addition to the FMC connector, configurable inputs and outputs are available for synchronization with other detectors. A high resolution (≈ 27 ps bin size) Time to Digital converter is provided for time stamping events in the detector. The SPIDR system is frequently used as readout for the Medipix3 and Timepix3 ASICs. Using the 10 Gigabit Ethernet interface it is possible to read out a single chip at full bandwidth or up to 12 chips at a reduced rate. Another recent application is the test-bed for the VeloPix ASIC, which is developed for the Vertex Detector of the LHCb experiment. In this case the SPIDR system processes the 20 Gbps scrambled data stream from the VeloPix and distributes it over four 10 Gigabit Ethernet links, and in addition provides the slow and fast control for the chip.

Modulation of Acid-sensing Ion Channel 1a by Intracellular pH and Its Role in Ischemic Stroke.

PubMed

Li, Ming-Hua; Leng, Tian-Dong; Feng, Xue-Chao; Yang, Tao; Simon, Roger P; Xiong, Zhi-Gang

2016-08-26

An important contributor to brain ischemia is known to be extracellular acidosis, which activates acid-sensing ion channels (ASICs), a family of proton-gated sodium channels. Lines of evidence suggest that targeting ASICs may lead to novel therapeutic strategies for stroke. Investigations of the role of ASICs in ischemic brain injury have naturally focused on the role of extracellular pH in ASIC activation. By contrast, intracellular pH (pHi) has received little attention. This is a significant gap in our understanding because the ASIC response to extracellular pH is modulated by pHi, and activation of ASICs by extracellular protons is paradoxically enhanced by intracellular alkalosis. Our previous studies show that acidosis-induced cell injury in in vitro models is attenuated by intracellular acidification. However, whether pHi affects ischemic brain injury in vivo is completely unknown. Furthermore, whereas ASICs in native neurons are composed of different subunits characterized by distinct electrophysiological/pharmacological properties, the subunit-dependent modulation of ASIC activity by pHi has not been investigated. Using a combination of in vitro and in vivo ischemic brain injury models, electrophysiological, biochemical, and molecular biological approaches, we show that the intracellular alkalizing agent quinine potentiates, whereas the intracellular acidifying agent propionate inhibits, oxygen-glucose deprivation-induced cell injury in vitro and brain ischemia-induced infarct volume in vivo Moreover, we find that the potentiation of ASICs by quinine depends on the presence of the ASIC1a, ASIC2a subunits, but not ASIC1b, ASIC3 subunits. Furthermore, we have determined the amino acids in ASIC1a that are involved in the modulation of ASICs by pHi. © 2016 by The American Society for Biochemistry and Molecular Biology, Inc.

Development of a dedicated readout ASIC for TPC based X-ray polarimeter

NASA Astrophysics Data System (ADS)

Zhang, Hongyan; Deng, Zhi; Li, Hong; Liu, Yinong; Feng, Hua

2016-07-01

X-ray polarimetry with time projection chambers was firstly proposed by JK Black in 2007 and has been greatly developed since then. It measured two dimensional photoelectron tracks with one dimensional strip and the other dimension was estimated by the drift time from the signal waveforms. A readout ASIC, APV25, originally developed for CMS silicon trackers was used and has shown some limitations such as waveform sampling depth. A dedicated ASIC was developed for TPC based X-ray polarimeters in this paper. It integrated 32 channel circuits and each channel consisted of an analog front-end and a waveform sampler based on switched capacitor array. The analog front-end has a charge sensitive preamplifier with a gain of 25 mV/fC, a CR-RC shaper with a peaking time of 25 ns, a baseline holder and a discriminator for self-triggering. The SCA has a buffer latency of 3.2 μs with 64 cells operating at 20 MSPS. The ASIC was fabricated in a 0.18 μm CMOS process. The equivalent noise charge (ENC) of the analog front-end was measured to be 274.8 e+34.6 e/pF. The effective resolution of the SCA was 8.8 bits at sampling rate up to 50 MSPS. The total power consumption was 2.8 mW per channel. The ASIC was also tested with real TPC detectors and two dimensional photoelectron tracks have been successfully acquired. More tests and analysis on the sensitivity to the polarimetry are undergoing and will be presented in this paper.

α-Dendrotoxin inhibits the ASIC current in dorsal root ganglion neurons from rat.

PubMed

Báez, Adriana; Salceda, Emilio; Fló, Martín; Graña, Martín; Fernández, Cecilia; Vega, Rosario; Soto, Enrique

2015-10-08

Dendrotoxins are a group of peptide toxins purified from the venom of several mamba snakes. α-Dendrotoxin (α-DTx, from the Eastern green mamba Dendroaspis angusticeps) is a well-known blocker of voltage-gated K(+) channels and specifically of K(v)1.1, K(v)1.2 and K(v)1.6. In this work we show that α-DTx inhibited the ASIC currents in DRG neurons (IC50=0.8 μM) when continuously perfused during 25 s (including a 5 s pulse to pH 6.1), but not when co-applied with the pH drop. Additionally, we show that α-DTx abolished a transient component of the outward current that, in some experiments, appeared immediately after the end of the acid pulse. Our data indicate that α-DTx inhibits ASICs in the high nM range while some Kv are inhibited in the low nM range. The α-DTx selectivity and its potential interaction with ASICs should be taken in consideration when DTx is used in the high nM range. Copyright © 2015 Elsevier Ireland Ltd. All rights reserved.

Amorphous silicon carbide ultramicroelectrode arrays for neural stimulation and recording

NASA Astrophysics Data System (ADS)

Deku, Felix; Cohen, Yarden; Joshi-Imre, Alexandra; Kanneganti, Aswini; Gardner, Timothy J.; Cogan, Stuart F.

2018-02-01

Objective. Foreign body response to indwelling cortical microelectrodes limits the reliability of neural stimulation and recording, particularly for extended chronic applications in behaving animals. The extent to which this response compromises the chronic stability of neural devices depends on many factors including the materials used in the electrode construction, the size, and geometry of the indwelling structure. Here, we report on the development of microelectrode arrays (MEAs) based on amorphous silicon carbide (a-SiC). Approach. This technology utilizes a-SiC for its chronic stability and employs semiconductor manufacturing processes to create MEAs with small shank dimensions. The a-SiC films were deposited by plasma enhanced chemical vapor deposition and patterned by thin-film photolithographic techniques. To improve stimulation and recording capabilities with small contact areas, we investigated low impedance coatings on the electrode sites. The assembled devices were characterized in phosphate buffered saline for their electrochemical properties. Main results. MEAs utilizing a-SiC as both the primary structural element and encapsulation were fabricated successfully. These a-SiC MEAs had 16 penetrating shanks. Each shank has a cross-sectional area less than 60 µm2 and electrode sites with a geometric surface area varying from 20 to 200 µm2. Electrode coatings of TiN and SIROF reduced 1 kHz electrode impedance to less than 100 kΩ from ~2.8 MΩ for 100 µm2 Au electrode sites and increased the charge injection capacities to values greater than 3 mC cm‑2. Finally, we demonstrated functionality by recording neural activity from basal ganglia nucleus of Zebra Finches and motor cortex of rat. Significance. The a-SiC MEAs provide a significant advancement in the development of microelectrodes that over the years has relied on silicon platforms for device manufacture. These flexible a-SiC MEAs have the potential for decreased tissue damage and reduced foreign body response. The technique is promising and has potential for clinical translation and large scale manufacturing.

Performance of CATIROC: ASIC for smart readout of large photomultiplier arrays

NASA Astrophysics Data System (ADS)

Blin, S.; Callier, S.; Conforti Di Lorenzo, S.; Dulucq, F.; De La Taille, C.; Martin-Chassard, G.; Seguin-Moreau, N.

2017-03-01

CATIROC (Charge And Time Integrated Read Out Chip) is a complete read-out chip manufactured in AustriaMicroSystem (AMS) SiGe 0.35 μm technology, designed to read arrays of 16 photomultipliers (PMTs). It is an upgraded version of PARISROC2 [1] designed in 2010 in the context of the PMm2 (square meter PhotoMultiplier) project [2]. CATIROC is a SoC (System on Chip) that processes analog signals up to the digitization and sparsification to reduce the cost and cable number. The ASIC is composed of 16 independent channels that work in triggerless mode, auto-triggering on the single photo-electron. It provides a charge measurement up to 400 photoelectrons (70 pC) on two scales of 10 bits and a timing information with an accuracy of 200 ps rms. The ASIC was sent for fabrication in February 2015 and then received in September 2015. It is a good candidate for two Chinese projects (LHAASO and JUNO). The architecture and the measurements will be detailed in the paper.

SEDHI: development status of the Pléiades detection electronics

NASA Astrophysics Data System (ADS)

Dantes, Didier; Biffi, Jean-Marc; Neveu, Claude; Renard, Christophe

2017-11-01

In the framework of the Pléiades program, Alcatel Space is developping with CNES a new concept of Highly Integrated Detection Electronic Subsystem (SEDHI) which lead to very high gains in term of camera mass, volume and power consumption. This paper presents the design of this new concept and summarizes its main performances. The electrical, mechanical and thermal aspects of the SEDHI concept are described, including the basic technologies: panchromatic detector, multispectral detector, butting technology, ASIC for phase shift of detector clocks, ASIC for video processing, ASIC for phase trimming, hybrids, video modules... This concept and these technologies can be adapted to a large scale of missions and instruments. Design, performance and budgets of the subsystem are given for the Pléiades mission for which the SEDHI concept has been selected. The detailed performances of each critical component are provided, focusing on the most critical performances which have been obtained at this level of the Pléiades development.

Physiological and pathological functions of acid-sensing ion channels in the central nervous system

PubMed Central

Chu, Xiang-Ping; Xiong, Zhi-Gang

2012-01-01

Protons are important signals for neuronal function. In the central nervous system (CNS), proton concentrations change locally when synaptic vesicles release their acidic contents into the synaptic cleft, and globally in ischemia, seizures, traumatic brain injury, and other neurological disorders due to lactic acid accumulation. The finding that protons gate a distinct family of ion channels, the acid-sensing ion channels (ASICs), has shed new light on the mechanism of acid signaling and acidosis-associated neuronal injury. Accumulating evidence has suggested that ASICs play important roles in physiological processes such as synaptic plasticity, learning/memory, fear conditioning, and retinal integrity, and in pathological conditions such as brain ischemia, multiple sclerosis, epileptic seizures, and malignant glioma. Thus, targeting these channels may lead to novel therapeutic interventions for neurological disorders. The goal of this review is to provide an update on recent advances in our understanding of the functions of ASICs in the CNS. PMID:22204324

MICROROC: MICRO-mesh gaseous structure Read-Out Chip

NASA Astrophysics Data System (ADS)

Adloff, C.; Blaha, J.; Chefdeville, M.; Dalmaz, A.; Drancourt, C.; Dulucq, F.; Espargilière, A.; Gaglione, R.; Geffroy, N.; Jacquemier, J.; Karyotakis, Y.; Martin-Chassard, G.; Prast, J.; Seguin-Moreau, N.; de La Taille, Ch; Vouters, G.

2012-01-01

MICRO MEsh GAseous Structure (MICROMEGAS) and Gas Electron Multipliers (GEM) detectors are two candidates for the active medium of a Digital Hadronic CALorimeter (DHCAL) as part of a high energy physics experiment at a future linear collider (ILC/CLIC). Physics requirements lead to a highly granular hadronic calorimeter with up to thirty million channels with probably only hit information (digital readout calorimeter). To validate the concept of digital hadronic calorimetry with such small cell size, the construction and test of a cubic meter technological prototype, made of 40 planes of one square meter each, is necessary. This technological prototype would contain about 400 000 electronic channels, thus requiring the development of front-end ASIC. Based on the experience gained with previous ASIC that were mounted on detectors and tested in particle beams, a new ASIC called MICROROC has been developped. This paper summarizes the caracterisation campaign that was conducted on this new chip as well as its integration into a large area Micromegas chamber of one square meter.

An acid-sensing ion channel from shark (Squalus acanthias) mediates transient and sustained responses to protons

PubMed Central

Springauf, Andreas; Gründer, Stefan

2010-01-01

Acid-sensing ion channels (ASICs) are proton-gated Na+ channels. They are implicated in synaptic transmission, detection of painful acidosis, and possibly sour taste. The typical ASIC current is a transient, completely desensitizing current that can be blocked by the diuretic amiloride. ASICs are present in chordates but are absent in other animals. They have been cloned from urochordates, jawless vertebrates, cartilaginous shark and bony fish, from chicken and different mammals. Strikingly, all ASICs that have so far been characterized from urochordates, jawless vertebrates and shark are not gated by protons, suggesting that proton gating evolved relatively late in bony fish and that primitive ASICs had a different and unknown gating mechanism. Recently, amino acids that are crucial for the proton gating of rat ASIC1a have been identified. These residues are completely conserved in shark ASIC1b (sASIC1b), prompting us to re-evaluate the proton sensitivity of sASIC1b. Here we show that, contrary to previous findings, sASIC1b is indeed gated by protons with half-maximal activation at pH 6.0. sASIC1b desensitizes quickly but incompletely, efficiently encoding transient as well as sustained proton signals. Our results show that the conservation of the amino acids crucial for proton gating can predict proton sensitivity of an ASIC and increase our understanding of the evolution of ASICs. PMID:20064854

Effects of Conformal Nanoscale Coatings on Thermal Performance of Vertically Aligned Carbon Nanotubes.

PubMed

Silvestri, Cinzia; Riccio, Michele; Poelma, René H; Jovic, Aleksandar; Morana, Bruno; Vollebregt, Sten; Irace, Andrea; Zhang, Guo Qi; Sarro, Pasqualina M

2018-04-17

The high aspect ratio and the porous nature of spatially oriented forest-like carbon nanotube (CNT) structures represent a unique opportunity to engineer a novel class of nanoscale assemblies. By combining CNTs and conformal coatings, a 3D lightweight scaffold with tailored behavior can be achieved. The effect of nanoscale coatings, aluminum oxide (Al 2 O 3 ) and nonstoichiometric amorphous silicon carbide (a-SiC), on the thermal transport efficiency of high aspect ratio vertically aligned CNTs, is reported herein. The thermal performance of the CNT-based nanostructure strongly depends on the achieved porosity, the coating material and its infiltration within the nanotube network. An unprecedented enhancement in terms of effective thermal conductivity in a-SiC coated CNTs has been obtained: 181% compared to the as-grown CNTs and Al 2 O 3 coated CNTs. Furthermore, the integration of coated high aspect ratio CNTs in an epoxy molding compound demonstrates that, next to the required thermal conductivity, the mechanical compliance for thermal interface applications can also be achieved through coating infiltration into foam-like CNT forests. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Onboard calibration circuit for the DAMPE BGO calorimeter front-end electronics

NASA Astrophysics Data System (ADS)

Zhang, De-Liang; Feng, Chang-Qing; Zhang, Jun-Bin; Wang, Qi; Ma, Si-Yuan; Shen, Zhong-Tao; Jiang, Di; Gao, Shan-Shan; Zhang, Yun-Long; Guo, Jian-Hua; Liu, Shu-Bin; An, Qi

2016-05-01

DAMPE (DArk Matter Particle Explorer) is a scientific satellite which is mainly aimed at indirectly searching for dark matter in space. One critical sub-detector of the DAMPE payload is the BGO (bismuth germanium oxide) calorimeter, which contains 1848 PMT (photomultiplier tube) dynodes and 16 FEE (Front-End Electronics) boards. VA160 and VATA160, two 32-channel low power ASICs (Application Specific Integrated Circuits), are adopted as the key components on the FEEs to perform charge measurement for the PMT signals. In order to monitor the parameter drift which may be caused by temperature variation, aging, or other environmental factors, an onboard calibration circuit is designed for the VA160 and VATA160 ASICs. It is mainly composed of a 12-bit DAC (Digital to Analog Converter), an operational amplifier and an analog switch. Test results showed that a dynamic range of 0-30 pC with a precision of 5 fC (Root Meam Square, RMS) was achieved, which covers the VA160’s input range. It can be used to compensate for the temperature drift and test the trigger function of the FEEs. The calibration circuit has been implemented for the front-end electronics of the BGO Calorimeter and verified by all the environmental tests for both Qualification Model and Flight Model of DAMPE. The DAMPE satellite was launched at the end of 2015 and the calibration circuit will operate periodically in space. Supported by Strategic Priority Research Program on Space Science of Chinese Academy of Sciences (XDA04040202-4), and National Basic Research Program (973 Program) of China (2010CB833002) and National Natural Science Foundation of China (11273070)

A 32-channel front-end ASIC for GEM detectors used in beam monitoring applications

NASA Astrophysics Data System (ADS)

Ciciriello, F.; Altieri, P. R.; Corsi, F.; De Robertis, G.; Felici, G.; Loddo, F.; Lorusso, L.; Marzocca, C.; Matarrese, G.; Ranieri, A.; Stamerra, A.

2017-11-01

A multichannel, mixed-signal, front-end ASIC for GEM detectors, intended for beam monitoring in hadron therapy applications, has been designed and prototyped in a standard 0.35 μm CMOS technology. The analog channels are based on the classic CSA + shaper processing chain, followed by a peak detector which can work as an analog memory, to simplifiy the analog-to-digital conversion of the peak voltage of the output pulse, proportional to the energy of the detected event. The available hardware resources include an 8-bit A/D converter and a standard-cell digital part, which manages the read-out procedure, in sparse or serial mode. The ASIC is self-triggered and transfers energy and address data to the external DAQ via a fast 100 MHz LVDS link. Preliminary characterization results show that the non-linearity error is limited to 5% for a maximum input charge of about 70 fC, the measured ENC is about 1400e- and the time jitter of the trigger signal generated in response to an injected charge of 60 fC is close to 200 ps.

Implementation of a Synchronized Oscillator Circuit for Fast Sensing and Labeling of Image Objects

PubMed Central

Kowalski, Jacek; Strzelecki, Michal; Kim, Hyongsuk

2011-01-01

We present an application-specific integrated circuit (ASIC) CMOS chip that implements a synchronized oscillator cellular neural network with a matrix size of 32 × 32 for object sensing and labeling in binary images. Networks of synchronized oscillators are a recently developed tool for image segmentation and analysis. Its parallel network operation is based on a “temporary correlation” theory that attempts to describe scene recognition as if performed by the human brain. The synchronized oscillations of neuron groups attract a person’s attention if he or she is focused on a coherent stimulus (image object). For more than one perceived stimulus, these synchronized patterns switch in time between different neuron groups, thus forming temporal maps that code several features of the analyzed scene. In this paper, a new oscillator circuit based on a mathematical model is proposed, and the network architecture and chip functional blocks are presented and discussed. The proposed chip is implemented in AMIS 0.35 μm C035M-D 5M/1P technology. An application of the proposed network chip for the segmentation of insulin-producing pancreatic islets in magnetic resonance liver images is presented. PMID:22163803

20-GFLOPS QR processor on a Xilinx Virtex-E FPGA

NASA Astrophysics Data System (ADS)

Walke, Richard L.; Smith, Robert W. M.; Lightbody, Gaye

2000-11-01

Adaptive beamforming can play an important role in sensor array systems in countering directional interference. In high-sample rate systems, such as radar and comms, the calculation of adaptive weights is a very computational task that requires highly parallel solutions. For systems where low power consumption and volume are important the only viable implementation is as an Application Specific Integrated Circuit (ASIC). However, the rapid advancement of Field Programmable Gate Array (FPGA) technology is enabling highly credible re-programmable solutions. In this paper we present the implementation of a scalable linear array processor for weight calculation using QR decomposition. We employ floating-point arithmetic with mantissa size optimized to the target application to minimize component size, and implement them as relationally placed macros (RPMs) on Xilinx Virtex FPGAs to achieve predictable dense layout and high-speed operation. We present results that show that 20GFLOPS of sustained computation on a single XCV3200E-8 Virtex-E FPGA is possible. We also describe the parameterized implementation of the floating-point operators and QR-processor, and the design methodology that enables us to rapidly generate complex FPGA implementations using the industry standard hardware description language VHDL.

Parkin-mediated Monoubiquitination of the PDZ Protein PICK1 Regulates the Activity of Acid-sensing Ion Channels

PubMed Central

Joch, Monica; Ase, Ariel R.; Chen, Carol X.-Q.; MacDonald, Penny A.; Kontogiannea, Maria; Corera, Amadou T.; Brice, Alexis

2007-01-01

Mutations in the parkin gene result in an autosomal recessive juvenile-onset form of Parkinson's disease. As an E3 ubiquitin-ligase, parkin promotes the attachment of ubiquitin onto specific substrate proteins. Defects in the ubiquitination of parkin substrates are therefore believed to lead to neurodegeneration in Parkinson's disease. Here, we identify the PSD-95/Discs-large/Zona Occludens-1 (PDZ) protein PICK1 as a novel parkin substrate. We find that parkin binds PICK1 via a PDZ-mediated interaction, which predominantly promotes PICK1 monoubiquitination rather than polyubiquitination. Consistent with monoubiquitination and recent work implicating parkin in proteasome-independent pathways, parkin does not promote PICK1 degradation. However, parkin regulates the effects of PICK1 on one of its other PDZ partners, the acid-sensing ion channel (ASIC). Overexpression of wild-type, but not PDZ binding– or E3 ubiquitin-ligase–defective parkin abolishes the previously described, protein kinase C-induced, PICK1-dependent potentiation of ASIC2a currents in non-neuronal cells. Conversely, the loss of parkin in hippocampal neurons from parkin knockout mice unmasks prominent potentiation of native ASIC currents, which is normally suppressed by endogenous parkin in wild-type neurons. Given that ASIC channels contribute to excitotoxicity, our work provides a mechanism explaining how defects in parkin-mediated PICK1 monoubiquitination could enhance ASIC activity and thereby promote neurodegeneration in Parkinson's disease. PMID:17553932

A wireless beta-microprobe based on pixelated silicon for in vivo brain studies in freely moving rats

NASA Astrophysics Data System (ADS)

Märk, J.; Benoit, D.; Balasse, L.; Benoit, M.; Clémens, J. C.; Fieux, S.; Fougeron, D.; Graber-Bolis, J.; Janvier, B.; Jevaud, M.; Genoux, A.; Gisquet-Verrier, P.; Menouni, M.; Pain, F.; Pinot, L.; Tourvielle, C.; Zimmer, L.; Morel, C.; Laniece, P.

2013-07-01

The investigation of neurophysiological mechanisms underlying the functional specificity of brain regions requires the development of technologies that are well adjusted to in vivo studies in small animals. An exciting challenge remains the combination of brain imaging and behavioural studies, which associates molecular processes of neuronal communications to their related actions. A pixelated intracerebral probe (PIXSIC) presents a novel strategy using a submillimetric probe for beta+ radiotracer detection based on a pixelated silicon diode that can be stereotaxically implanted in the brain region of interest. This fully autonomous detection system permits time-resolved high sensitivity measurements of radiotracers with additional imaging features in freely moving rats. An application-specific integrated circuit (ASIC) allows for parallel signal processing of each pixel and enables the wireless operation. All components of the detector were tested and characterized. The beta+ sensitivity of the system was determined with the probe dipped into radiotracer solutions. Monte Carlo simulations served to validate the experimental values and assess the contribution of gamma noise. Preliminary implantation tests on anaesthetized rats proved PIXSIC's functionality in brain tissue. High spatial resolution allows for the visualization of radiotracer concentration in different brain regions with high temporal resolution.

ASIC3 channels in multimodal sensory perception.

PubMed

Li, Wei-Guang; Xu, Tian-Le

2011-01-19

Acid-sensing ion channels (ASICs), which are members of the sodium-selective cation channels belonging to the epithelial sodium channel/degenerin (ENaC/DEG) family, act as membrane-bound receptors for extracellular protons as well as nonproton ligands. At least five ASIC subunits have been identified in mammalian neurons, which form both homotrimeric and heterotrimeric channels. The highly proton sensitive ASIC3 channels are predominantly distributed in peripheral sensory neurons, correlating with their roles in multimodal sensory perception, including nociception, mechanosensation, and chemosensation. Different from other ASIC subunit composing ion channels, ASIC3 channels can mediate a sustained window current in response to mild extracellular acidosis (pH 7.3-6.7), which often occurs accompanied by many sensory stimuli. Furthermore, recent evidence indicates that the sustained component of ASIC3 currents can be enhanced by nonproton ligands including the endogenous metabolite agmatine. In this review, we first summarize the growing body of evidence for the involvement of ASIC3 channels in multimodal sensory perception and then discuss the potential mechanisms underlying ASIC3 activation and mediation of sensory perception, with a special emphasis on its role in nociception. We conclude that ASIC3 activation and modulation by diverse sensory stimuli represent a new avenue for understanding the role of ASIC3 channels in sensory perception. Furthermore, the emerging implications of ASIC3 channels in multiple sensory dysfunctions including nociception allow the development of new pharmacotherapy.

SVGA and XGA LCOS microdisplays for HMD applications

NASA Astrophysics Data System (ADS)

Bolotski, Michael; Alvelda, Phillip

1999-07-01

MicroDisplay liquid crystal on silicon (LCOS) display devices are based on a combination of technologies combined with the extreme integration capability of conventionally fabricated CMOS substrates. Two recent SVGA (800 X 600) pixel resolution designs were demonstrated based on 10 micron and 12.5-micron pixel pitch architectures. The resulting microdisplays measure approximately 10 mm and 12 mm in diagonal respectively. Further, an XGA (1024 X 768) resolution display fabricated with a 12.5-micron pixel pitch with a 16-mm diagonal was also demonstrated. Both the larger SVGA and the XGA design were based on the same 12.5-micron pixel-pitch design, demonstrating a quickly scalable design architecture for rapid prototyping life-cycles. All three microdisplay designs described above function in grayscale and high-performance Field-Sequential-Color (FSC) operating modes. The fast liquid crystal operating modes and new scalable high- performance pixel addressing architectures presented in this paper enable substantially improved color, contrast, and brightness while still satisfying the optical, packaging, and power requirements of portable commercial and defense applications including ultra-portable helmet, eyeglass, and heat-mounted systems. The entire suite of The MicroDisplay Corporation's technologies was devised to create a line of mixed-signal application-specific integrated circuits (ASIC) in single-chip display systems. Mixed-signal circuits can integrate computing, memory, and communication circuitry on the same substrate as the display drivers and pixel array for a multifunctional complete system-on-a-chip. For helmet and head-mounted displays this can include capabilities such as the incorporation of customized symbology and information storage directly on the display substrate. System-on-a-chip benefits also include reduced head supported weight requirements through the elimination of off-chip drive electronics.

Seizure Termination by Acidosis Depends on ASIC1a

PubMed Central

Ziemann, Adam E.; Schnizler, Mikael K.; Albert, Gregory W.; Severson, Meryl A.; Howard, Matthew A.; Welsh, Michael J.; Wemmie, John A.

2008-01-01

SUMMARY Most seizures stop spontaneously. However, the molecular mechanisms remain unknown. Earlier observations that seizures reduce brain pH and that acidosis inhibits seizures indicated that acidosis halts epileptic activity. Because acid–sensing ion channel–1a (ASIC1a) shows exquisite sensitivity to extracellular pH and regulates neuron excitability, we hypothesized that acidosis might activate ASIC1a to terminate seizures. Disrupting mouse ASIC1a increased the severity of chemoconvulsant–induced seizures, whereas overexpressing ASIC1a had the opposite effect. ASIC1a did not affect seizure threshold or onset, but shortened seizure duration and prevented progression. CO2 inhalation, long known to lower brain pH and inhibit seizures, also required ASIC1a to interrupt tonic–clonic seizures. Acidosis activated inhibitory interneurons through ASIC1a, suggesting that ASIC1a might limit seizures by increasing inhibitory tone. These findings identify ASIC1a as a key element in seizure termination when brain pH falls. The results suggest a molecular mechanism for how the brain stops seizures and suggest new therapeutic strategies. PMID:18536711

DOE Office of Scientific and Technical Information (OSTI.GOV)

Shinde, Subhash L.; Teifel, John; Flores, Richard S.

A 3D stacked sASIC is provided that includes a plurality of 2D reconfigurable structured structured ASIC (sASIC) levels interconnected through hard-wired arrays of 3D vias. The 2D sASIC levels may contain logic, memory, analog functions, and device input/output pad circuitry. During fabrication, these 2D sASIC levels are stacked on top of each other and fused together with 3D metal vias. Such 3D vias may be fabricated as through-silicon vias (TSVs). They may connect to the back-side of the 2D sASIC level, or they may be connected to top metal pads on the front-side of the 2D sASIC level.

Spinal afferent neurons projecting to the rat lung and pleura express acid sensitive channels

PubMed Central

Groth, Michael; Helbig, Tanja; Grau, Veronika; Kummer, Wolfgang; Haberberger, Rainer V

2006-01-01

Background The acid sensitive ion channels TRPV1 (transient receptor potential vanilloid receptor-1) and ASIC3 (acid sensing ion channel-3) respond to tissue acidification in the range that occurs during painful conditions such as inflammation and ischemia. Here, we investigated to which extent they are expressed by rat dorsal root ganglion neurons projecting to lung and pleura, respectively. Methods The tracer DiI was either injected into the left lung or applied to the costal pleura. Retrogradely labelled dorsal root ganglion neurons were subjected to triple-labelling immunohistochemistry using antisera against TRPV1, ASIC3 and neurofilament 68 (marker for myelinated neurons), and their soma diameter was measured. Results Whereas 22% of pulmonary spinal afferents contained neither channel-immunoreactivity, at least one is expressed by 97% of pleural afferents. TRPV1+/ASIC3- neurons with probably slow conduction velocity (small soma, neurofilament 68-negative) were significantly more frequent among pleural (35%) than pulmonary afferents (20%). TRPV1+/ASIC3+ neurons amounted to 14 and 10% respectively. TRPV1-/ASIC3+ neurons made up between 44% (lung) and 48% (pleura) of neurons, and half of them presumably conducted in the A-fibre range (larger soma, neurofilament 68-positive). Conclusion Rat pleural and pulmonary spinal afferents express at least two different acid-sensitive channels that make them suitable to monitor tissue acidification. Patterns of co-expression and structural markers define neuronal subgroups that can be inferred to subserve different functions and may initiate specific reflex responses. The higher prevalence of TRPV1+/ASIC3- neurons among pleural afferents probably reflects the high sensitivity of the parietal pleura to painful stimuli. PMID:16813657

ASIC-dependent LTP at multiple glutamatergic synapses in amygdala network is required for fear memory

PubMed Central

Chiang, Po-Han; Chien, Ta-Chun; Chen, Chih-Cheng; Yanagawa, Yuchio; Lien, Cheng-Chang

2015-01-01

Genetic variants in the human ortholog of acid-sensing ion channel-1a subunit (ASIC1a) gene are associated with panic disorder and amygdala dysfunction. Both fear learning and activity-induced long-term potentiation (LTP) of cortico-basolateral amygdala (BLA) synapses are impaired in ASIC1a-null mice, suggesting a critical role of ASICs in fear memory formation. In this study, we found that ASICs were differentially expressed within the amygdala neuronal population, and the extent of LTP at various glutamatergic synapses correlated with the level of ASIC expression in postsynaptic neurons. Importantly, selective deletion of ASIC1a in GABAergic cells, including amygdala output neurons, eliminated LTP in these cells and reduced fear learning to the same extent as that found when ASIC1a was selectively abolished in BLA glutamatergic neurons. Thus, fear learning requires ASIC-dependent LTP at multiple amygdala synapses, including both cortico-BLA input synapses and intra-amygdala synapses on output neurons. PMID:25988357

Knockdown of acid-sensing ion channel 1a (ASIC1a) suppresses disease phenotype in SCA1 mouse model.

PubMed

Vig, Parminder J S; Hearst, Scoty M; Shao, Qingmei; Lopez, Maripar E

2014-08-01

The mutated ataxin-1 protein in spinocerebellar ataxia 1 (SCA1) targets Purkinje cells (PCs) of the cerebellum and causes progressive ataxia due to loss of PCs and neurons of the brainstem. The exact mechanism of this cellular loss is still not clear. Currently, there are no treatments for SCA1; however, understanding of the mechanisms that regulate SCA1 pathology is essential for devising new therapies for SCA1 patients. We previously established a connection between the loss of intracellular calcium-buffering and calcium-signalling proteins with initiation of neurodegeneration in SCA1 transgenic (Tg) mice. Recently, acid-sensing ion channel 1a (ASIC1a) have been implicated in calcium-mediated toxicity in many brain disorders. Here, we report generating SCA1 Tg mice in the ASIC1a knockout (KO) background and demonstrate that the deletion of ASIC1a gene expression causes suppression of the SCA1 disease phenotype. Loss of the ASIC1a channel in SCA1/ASIC1a KO mice resulted in the improvement of motor deficit and decreased PC degeneration. Interestingly, the expression of the ASIC1 variant, ASIC1b, was upregulated in the cerebellum of both SCA1/ASIC1a KO and ASIC1a KO animals as compared to the wild-type (WT) and SCA1 Tg mice. Further, these SCA1/ASIC1a KO mice exhibited translocation of PC calcium-binding protein calbindin-D28k from the nucleus to the cytosol in young animals, which otherwise have both cytosolic and nuclear localization. Furthermore, in addition to higher expression of calcium-buffering protein parvalbumin, PCs of the older SCA1/ASIC1a KO mice showed a decrease in morphologic abnormalities as compared to the age-matched SCA1 animals. Our data suggest that ASIC1a may be a mediator of SCA1 pathogenesis and targeting ASIC1a could be a novel approach to treat SCA1.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Braga, D.; Coleman-Smith, P. J.; Davinson, T.

We have designed a read-out ASIC for nuclear decay spectroscopy as part of the AIDA project - the Advanced Implantation Detector Array. AIDA will be installed in experiments at the Facility for Antiproton and Ion Research in GSI, Darmstadt. The AIDA ASIC will measure the signals when unstable nuclei are implanted into the detector, followed by the much smaller signals when the nuclei subsequently decay. Implant energies can be as high as 20 GeV; decay products need to be measured down to 25 keV within just a few microseconds of the initial implants. The ASIC uses two amplifiers per detectormore » channel, one covering the 20 GeV dynamic range, the other selectable over a 20 MeV or 1 GeV range. The amplifiers are linked together by bypass transistors which are normally switched off. The arrival of a large signal causes saturation of the low-energy amplifier and a fluctuation of the input voltage, which activates the link to the high-energy amplifier. The bypass transistors switch on and the input charge is integrated by the high-energy amplifier. The signal is shaped and stored by a peak-hold, then read out on a multiplexed output. Control logic resets the amplifiers and bypass circuit, allowing the low-energy amplifier to measure the subsequent decay signal. We present simulations and test results, demonstrating the AIDA ASIC operation over a wide range of input signals. (authors)« less

Lignan from Thyme Possesses Inhibitory Effect on ASIC3 Channel Current*

PubMed Central

Dubinnyi, Maxim A.; Osmakov, Dmitry I.; Koshelev, Sergey G.; Kozlov, Sergey A.; Andreev, Yaroslav A.; Zakaryan, Naira A.; Dyachenko, Igor A.; Bondarenko, Dmitry A.; Arseniev, Alexander S.; Grishin, Eugene V.

2012-01-01

A novel compound was identified in the acidic extract of Thymus armeniacus collected in the Lake Sevan region of Armenia. This compound, named “sevanol,” to our knowledge is the first low molecular weight natural molecule that has a reversible inhibition effect on both the transient and the sustained current of human ASIC3 channels expressed in Xenopus laevis oocytes. Sevanol completely blocked the transient component (IC50 353 ± 23 μm) and partially (∼45%) inhibited the amplitude of the sustained component (IC50 of 234 ± 53 μm). Other types of acid-sensing ion channel (ASIC) channels were intact to sevanol application, except ASIC1a, which showed more than six times less affinity to it as compared with the inhibitory action on the ASIC3 channel. To elucidate the structure of sevanol, the set of NMR spectra in two solvents (d6-DMSO and D2O) was collected, and the complete chemical structure was confirmed by liquid chromatography-mass spectrometry with electrospray ionization (LC-ESI+-MS) fragmentation. This compound is a new lignan built up of epiphyllic acid and two isocitryl esters in positions 9 and 10. In vivo administration of sevanol (1–10 mg/kg) significantly reversed thermal hyperalgesia induced by complete Freund's adjuvant injection and reduced response to acid in a writhing test. Thus, we assume the probable considerable role of sevanol in known analgesic and anti-inflammatory properties of thyme. PMID:22854960

Development of a low-noise, 4th-order readout ASIC for CdZnTe detectors in gamma spectrometer applications

NASA Astrophysics Data System (ADS)

Wang, Jia; Su, Lin; Wei, Xiaomin; Zheng, Ran; Hu, Yann

2016-09-01

This paper presents an ASIC readout circuit development, which aims to achieve low noise. In order to compensate the leakage current and improve gain, a dual-stage CSA has been utilized. A 4th-order high-linearity shaper is proposed to obtain a Semi-Gaussian wave and further decrease the noise induced by the leakage current. The ASIC has been designed and fabricated in a standard commercial 2P4M 0.35 μm CMOS process. Die area of one channel is about 1190 μm×147 μm. The input charge range is 1.8 fC. The peaking time can be adjusted from 1 μs to 3 μs. Measured ENC is about 55e- (rms) at input capacitor of 0 F. The gain is 271 mV/fC at the peaking time of 1 μs.

Dedicated multichannel readout ASIC coupled with single crystal diamond for dosimeter application

NASA Astrophysics Data System (ADS)

Fabbri, A.; Falco, M. D.; De Notaristefani, F.; Galasso, M.; Marinelli, M.; Orsolini Cencelli, V.; Tortora, L.; Verona, C.; Verona Rinati, G.

2013-02-01

This paper reports on the tests of a low-noise, multi-channel readout integrated circuit used as a readout electronic front-end for a diamond multi-pixel dosimeter. The system is developed for dose distribution measurement in radiotherapy applications. The first 10-channel prototype chip was designed and fabricated in a 0.18 um CMOS process. Every channel includes a charge integrator with a 10 pF capacitor and a double slope A/D converter. The diamond multi-pixel detector, based on CVD synthetic single crystal diamond Schottky diodes, is made by a 3 × 3 sensor matrix. The overall device has been tested under irradiation with 6 MeV radio therapeutic photon beams at the Policlinico ``Tor Vergata'' (PTV) hospital. Measurements show a 20 fA RMS leakage current from the front-end input stage and a negligible dark current from the diamond detector, a stable temporal response and a good linear behaviour as a function of both dose and dose rate. These characteristics were common to each tested channel.

Performance and Calibration of H2RG Detectors and SIDECAR ASICs for the RATIR Camera

NASA Technical Reports Server (NTRS)

Fox, Ori D.; Kutyrev, Alexander S.; Rapchun, David A.; Klein, Christopher R.; Butler, Nathaniel R.; Bloom, Josh; de Diego, Jos A.; Simn Farah, Alejandro D.; Gehrels, Neil A.; Georgiev, Leonid;

Acid-Sensing Ion Channels Activated by Evoked Released Protons Modulate Synaptic Transmission at the Mouse Calyx of Held Synapse.

PubMed

González-Inchauspe, Carlota; Urbano, Francisco J; Di Guilmi, Mariano N; Uchitel, Osvaldo D

2017-03-08

Acid-sensing ion channels (ASICs) regulate synaptic activities and play important roles in neurodegenerative diseases. We found that these channels can be activated in neurons of the medial nucleus of the trapezoid body (MNTB) of the auditory system in the CNS. A drop in extracellular pH induces transient inward ASIC currents (I ASIC s) in postsynaptic MNTB neurons from wild-type mice. The inhibition of I ASIC s by psalmotoxin-1 (PcTx1) and the absence of these currents in knock-out mice for ASIC-1a subunit (ASIC1a -/- ) suggest that homomeric ASIC-1as are mediating these currents in MNTB neurons. Furthermore, we detect ASIC1a-dependent currents during synaptic transmission, suggesting an acidification of the synaptic cleft due to the corelease of neurotransmitter and H + from synaptic vesicles. These currents are capable of eliciting action potentials in the absence of glutamatergic currents. A significant characteristic of these homomeric ASIC-1as is their permeability to Ca 2+ Activation of ASIC-1a in MNTB neurons by exogenous H + induces an increase in intracellular Ca 2+ Furthermore, the activation of postsynaptic ASIC-1as during high-frequency stimulation (HFS) of the presynaptic nerve terminal leads to a PcTx1-sensitive increase in intracellular Ca 2+ in MNTB neurons, which is independent of glutamate receptors and is absent in neurons from ASIC1a -/- mice. During HFS, the lack of functional ASICs in synaptic transmission results in an enhanced short-term depression of glutamatergic EPSCs. These results strongly support the hypothesis of protons as neurotransmitters and demonstrate that presynaptic released protons modulate synaptic transmission by activating ASIC-1as at the calyx of Held-MNTB synapse. SIGNIFICANCE STATEMENT The manuscript demonstrates that postsynaptic neurons of the medial nucleus of the trapezoid body at the mouse calyx of Held synapse express functional homomeric Acid-sensing ion channel-1a (ASIC-1as) that can be activated by protons (coreleased with neurotransmitter from acidified synaptic vesicles). These ASIC-1as contribute to the generation of postsynaptic currents and, more relevant, to calcium influx, which could be involved in the modulation of presynaptic transmitter release. Inhibition or deletion of ASIC-1a leads to enhanced short-term depression, demonstrating that they are concerned with short-term plasticity of the synapse. ASICs represent a widespread communication system with unique properties. We expect that our experiments will have an impact in the neurobiology field and will spread in areas related to neuronal plasticity. Copyright © 2017 the authors 0270-6474/17/372589-11$15.00/0.

Implementation of the Timepix ASIC in the Scalable Readout System

NASA Astrophysics Data System (ADS)

Lupberger, M.; Desch, K.; Kaminski, J.

2016-09-01

We report on the development of electronics hardware, FPGA firmware and software to provide a flexible multi-chip readout of the Timepix ASIC within the framework of the Scalable Readout System (SRS). The system features FPGA-based zero-suppression and the possibility to read out up to 4×8 chips with a single Front End Concentrator (FEC). By operating several FECs in parallel, in principle an arbitrary number of chips can be read out, exploiting the scaling features of SRS. Specifically, we tested the system with a setup consisting of 160 Timepix ASICs, operated as GridPix devices in a large TPC field cage in a 1 T magnetic field at a DESY test beam facility providing an electron beam of up to 6 GeV. We discuss the design choices, the dedicated hardware components, the FPGA firmware as well as the performance of the system in the test beam.

The SIRIUS mixed analog-digital ASIC developed for the LOFT LAD and WFM instruments

NASA Astrophysics Data System (ADS)

Cros, A.; Rambaud, D.; Moutaye, E.; Ravera, L.; Barret, D.; Caïs, P.; Clédassou, R.; Bodin, P.; Seyler, J. Y.; Bonzo, A.; Feroci, M.; Labanti, C.; Evangelista, Y.; Favre, Y.

2014-07-01

We report on the development and characterization of the low-noise, low power, mixed analog-digital SIRIUS ASICs for both the LAD and WFM X-ray instruments of LOFT. The ASICs we developed are reading out large area silicon drift detectors (SDD). Stringent requirements in terms of noise (ENC of 17 e- to achieve an energy resolution on the LAD of 200 eV FWHM at 6 keV) and power consumption (650 μW per channel) were basis for the ASICs design. These SIRIUS ASICs are developed to match SDD detectors characteristics: 16 channels ASICs adapted for the LAD (970 microns pitch) and 64 channels for the WFM (145 microns pitch) will be fabricated. The ASICs were developed with the 180nm mixed technology of TSMC.

A Micromechanical INS/GPS System for Small Satellites

NASA Technical Reports Server (NTRS)

Barbour, N.; Brand, T.; Haley, R.; Socha, M.; Stoll, J.; Ward, P.; Weinberg, M.

1995-01-01

The cost and complexity of large satellite space missions continue to escalate. To reduce costs, more attention is being directed toward small lightweight satellites where future demand is expected to grow dramatically. Specifically, micromechanical inertial systems and microstrip global positioning system (GPS) antennas incorporating flip-chip bonding, application specific integrated circuits (ASIC) and MCM technologies will be required. Traditional microsatellite pointing systems do not employ active control. Many systems allow the satellite to point coarsely using gravity gradient, then attempt to maintain the image on the focal plane with fast-steering mirrors. Draper's approach is to actively control the line of sight pointing by utilizing on-board attitude determination with micromechanical inertial sensors and reaction wheel control actuators. Draper has developed commercial and tactical-grade micromechanical inertial sensors, The small size, low weight, and low cost of these gyroscopes and accelerometers enable systems previously impractical because of size and cost. Evolving micromechanical inertial sensors can be applied to closed-loop, active control of small satellites for micro-radian precision-pointing missions. An inertial reference feedback control loop can be used to determine attitude and line of sight jitter to provide error information to the controller for correction. At low frequencies, the error signal is provided by GPS. At higher frequencies, feedback is provided by the micromechanical gyros. This blending of sensors provides wide-band sensing from dc to operational frequencies. First order simulation has shown that the performance of existing micromechanical gyros, with integrated GPS, is feasible for a pointing mission of 10 micro-radians of jitter stability and approximately 1 milli-radian absolute error, for a satellite with 1 meter antenna separation. Improved performance micromechanical sensors currently under development will be suitable for a range of micro-nano-satellite applications.

SPD very front end electronics

NASA Astrophysics Data System (ADS)

Luengo, S.; Gascón, D.; Comerma, A.; Garrido, L.; Riera, J.; Tortella, S.; Vilasís, X.

2006-11-01

The Scintillator Pad Detector (SPD) is part of the LHCb calorimetry system [D. Breton, The front-end electronics for LHCb calorimeters, Tenth International Conference on Calorimetry in Particle Physics, CALOR, Pasadena, 2002] that provides high-energy hadron, electron and photon candidates for the first level trigger. The SPD is designed to distinguish electrons from photons. It consists of a plastic scintillator layer, divided into about 6000 cells of different size to obtain better granularity near the beam [S. Amato, et al., LHCb technical design report, CERN/LHCC/2000-0036, 2000]. Charged particles will produce, and photons will not, ionization in the scintillator. This ionization generates a light pulse that is collected by a WaveLength Shifting (WLS) fiber that is coiled inside the scintillator cell. The light is transmitted through a clear fiber to the readout system that is placed at the periphery of the detector. Due to space constraints, and in order to reduce costs, these 6000 cells are divided in groups using a MAPMT [Z. Ajaltouni, et al., Nucl. Instr. and Meth. A 504 (2003) 9] of 64 channels that provides information to the VFE readout electronics. The SPD signal has rather large statistical fluctuations because of the low number (20-30) of photoelectrons per MIP. Therefore the signal is integrated over the whole bunch crossing length of 25 ns in order to have the maximum value. Since in average about 85% of the SPD signal is within 25 ns, 15% of a sample is subtracted from the following one using an operational amplifier. The SPD VFE readout system that will be presented consists of the following components. A specific ASIC [D. Gascon, et al., Discriminator ASIC for the VFE SPD of the LHCb Calorimeter, LHCB Technical Note, LHCB 2004-xx] integrates the signal, makes the signal-tail subtraction, and compares the level obtained to a programmable threshold (to distinguish electrons from photons). A FPGA programmes the ASIC threshold and the value for signal-tail subtraction. Finally, a LVDS serializer sends the information to the first level trigger system.

Advanced High-Definition Video Cameras

NASA Technical Reports Server (NTRS)

Glenn, William

2007-01-01

A product line of high-definition color video cameras, now under development, offers a superior combination of desirable characteristics, including high frame rates, high resolutions, low power consumption, and compactness. Several of the cameras feature a 3,840 2,160-pixel format with progressive scanning at 30 frames per second. The power consumption of one of these cameras is about 25 W. The size of the camera, excluding the lens assembly, is 2 by 5 by 7 in. (about 5.1 by 12.7 by 17.8 cm). The aforementioned desirable characteristics are attained at relatively low cost, largely by utilizing digital processing in advanced field-programmable gate arrays (FPGAs) to perform all of the many functions (for example, color balance and contrast adjustments) of a professional color video camera. The processing is programmed in VHDL so that application-specific integrated circuits (ASICs) can be fabricated directly from the program. ["VHDL" signifies VHSIC Hardware Description Language C, a computing language used by the United States Department of Defense for describing, designing, and simulating very-high-speed integrated circuits (VHSICs).] The image-sensor and FPGA clock frequencies in these cameras have generally been much higher than those used in video cameras designed and manufactured elsewhere. Frequently, the outputs of these cameras are converted to other video-camera formats by use of pre- and post-filters.

Expression of acid-sensing ion channels and selection of reference genes in mouse and naked mole rat.

PubMed

Schuhmacher, Laura-Nadine; Smith, Ewan St John

2016-12-13

Acid-sensing ion channels (ASICs) are a family of ion channels comprised of six subunits encoded by four genes and they are expressed throughout the peripheral and central nervous systems. ASICs have been implicated in a wide range of physiological and pathophysiological processes: pain, breathing, synaptic plasticity and excitotoxicity. Unlike mice and humans, naked mole-rats do not perceive acid as a noxious stimulus, even though their sensory neurons express functional ASICs, likely an adaptation to living in a hypercapnic subterranean environment. Previous studies of ASIC expression in the mammalian nervous system have often not examined all subunits, or have failed to adequately quantify expression between tissues; to date there has been no attempt to determine ASIC expression in the central nervous system of the naked mole-rat. Here we perform a geNorm study to identify reliable housekeeping genes in both mouse and naked mole-rat and then use quantitative real-time PCR to estimate the relative amounts of ASIC transcripts in different tissues of both species. We identify RPL13A (ribosomal protein L13A) and CANX (calnexin), and β-ACTIN and EIF4A (eukaryotic initiation factor 4a) as being the most stably expressed housekeeping genes in mouse and naked mole-rat, respectively. In both species, ASIC3 was most highly expressed in dorsal root ganglia (DRG), and ASIC1a, ASIC2b and ASIC3 were more highly expressed across all brain regions compared to the other subunits. We also show that ASIC4, a proton-insensitive subunit of relatively unknown function, was highly expressed in all mouse tissues apart from DRG and hippocampus, but was by contrast the lowliest expressed ASIC in all naked mole-rat tissues.

A CMOS ASIC Design for SiPM Arrays

PubMed Central

Dey, Samrat; Banks, Lushon; Chen, Shaw-Pin; Xu, Wenbin; Lewellen, Thomas K.; Miyaoka, Robert S.; Rudell, Jacques C.

2012-01-01

Our lab has previously reported on novel board-level readout electronics for an 8×8 silicon photomultiplier (SiPM) array featuring row/column summation technique to reduce the hardware requirements for signal processing. We are taking the next step by implementing a monolithic CMOS chip which is based on the row-column architecture. In addition, this paper explores the option of using diagonal summation as well as calibration to compensate for temperature and process variations. Further description of a timing pickoff signal which aligns all of the positioning (spatial channels) pulses in the array is described. The ASIC design is targeted to be scalable with the detector size and flexible to accommodate detectors from different vendors. This paper focuses on circuit implementation issues associated with the design of the ASIC to interface our Phase II MiCES FPGA board with a SiPM array. Moreover, a discussion is provided for strategies to eventually integrate all the analog and mixed-signal electronics with the SiPM, on either a single-silicon substrate or multi-chip module (MCM). PMID:24825923

An efficient ASIC implementation of 16-channel on-line recursive ICA processor for real-time EEG system.

PubMed

Fang, Wai-Chi; Huang, Kuan-Ju; Chou, Chia-Ching; Chang, Jui-Chung; Cauwenberghs, Gert; Jung, Tzyy-Ping

2014-01-01

This is a proposal for an efficient very-large-scale integration (VLSI) design, 16-channel on-line recursive independent component analysis (ORICA) processor ASIC for real-time EEG system, implemented with TSMC 40 nm CMOS technology. ORICA is appropriate to be used in real-time EEG system to separate artifacts because of its highly efficient and real-time process features. The proposed ORICA processor is composed of an ORICA processing unit and a singular value decomposition (SVD) processing unit. Compared with previous work [1], this proposed ORICA processor has enhanced effectiveness and reduced hardware complexity by utilizing a deeper pipeline architecture, shared arithmetic processing unit, and shared registers. The 16-channel random signals which contain 8-channel super-Gaussian and 8-channel sub-Gaussian components are used to analyze the dependence of the source components, and the average correlation coefficient is 0.95452 between the original source signals and extracted ORICA signals. Finally, the proposed ORICA processor ASIC is implemented with TSMC 40 nm CMOS technology, and it consumes 15.72 mW at 100 MHz operating frequency.

Localized Triple Modular Redundancy vs. Distributed Triple Modular Redundancy on a ProASIC3E Reprogrammable FPGA

NASA Technical Reports Server (NTRS)

McGuffey, Alex; Berg, Melanie; Pellish, Jonathan

2010-01-01

Field programmable gate arrays (FPGA) are used in every space application. Currently, most space flight applications use radiation hardened (RH) FPGAs, which are very expensive. There is a desire to use cheaper, commercial off the shelf reprogrammable FPGAs, which are more susceptible to radiation effects known as single-event effects (SEE). The RH parts have SEE and total ionizing dose (TID) hardened elements pre-integrated into the part. This means that the designer does not need to implement any hardening techniques while configuring the device. The COTS parts on the other hand must be mitigated by design in order to insure any form of mitigation. The design techniques this project examines concern the use of localized triple modular redundancy (LTMR) and distributed triple modular redundancy (DTMR). LTMR triples every flip flop in the device architecture while DTMR triples everything except for the global routes (clocks, resets, and enables). The testing was performed on a ProASIC3E FPGA at the Texas A&M cyclotron facility. Two design architectures were used: shift registers and counters, both with LTMR and DTMR mitigation techniques. The test results prove that DTMR is more effective at reducing SEE than LTMR. We also determined that there was not a significant difference between the use of shift registers and counters for test purposes. More testing is required to obtain additional linear energy transfer values for each architecture and mitigation technique in order to determine the most cost-effective method of SEE mitigation.

CZT sensors for Computed Tomography: from crystal growth to image quality

NASA Astrophysics Data System (ADS)

Iniewski, K.

2016-12-01

Recent advances in Traveling Heater Method (THM) growth and device fabrication that require additional processing steps have enabled to dramatically improve hole transport properties and reduce polarization effects in Cadmium Zinc Telluride (CZT) material. As a result high flux operation of CZT sensors at rates in excess of 200 Mcps/mm2 is now possible and has enabled multiple medical imaging companies to start building prototype Computed Tomography (CT) scanners. CZT sensors are also finding new commercial applications in non-destructive testing (NDT) and baggage scanning. In order to prepare for high volume commercial production we are moving from individual tile processing to whole wafer processing using silicon methodologies, such as waxless processing, cassette based/touchless wafer handling. We have been developing parametric level screening at the wafer stage to ensure high wafer quality before detector fabrication in order to maximize production yields. These process improvements enable us, and other CZT manufacturers who pursue similar developments, to provide high volume production for photon counting applications in an economically feasible manner. CZT sensors are capable of delivering both high count rates and high-resolution spectroscopic performance, although it is challenging to achieve both of these attributes simultaneously. The paper discusses material challenges, detector design trade-offs and ASIC architectures required to build cost-effective CZT based detection systems. Photon counting ASICs are essential part of the integrated module platforms as charge-sensitive electronics needs to deal with charge-sharing and pile-up effects.

Identification of a unique Ca2+-binding site in rat acid-sensing ion channel 3.

PubMed

Zuo, Zhicheng; Smith, Rachel N; Chen, Zhenglan; Agharkar, Amruta S; Snell, Heather D; Huang, Renqi; Liu, Jin; Gonzales, Eric B

2018-05-25

Acid-sensing ion channels (ASICs) evolved to sense changes in extracellular acidity with the divalent cation calcium (Ca 2+ ) as an allosteric modulator and channel blocker. The channel-blocking activity is most apparent in ASIC3, as removing Ca 2+ results in channel opening, with the site's location remaining unresolved. Here we show that a ring of rat ASIC3 (rASIC3) glutamates (Glu435), located above the channel gate, modulates proton sensitivity and contributes to the formation of the elusive Ca 2+ block site. Mutation of this residue to glycine, the equivalent residue in chicken ASIC1, diminished the rASIC3 Ca 2+ block effect. Atomistic molecular dynamic simulations corroborate the involvement of this acidic residue in forming a high-affinity Ca 2+ site atop the channel pore. Furthermore, the reported observations provide clarity for past controversies regarding ASIC channel gating. Our findings enhance understanding of ASIC gating mechanisms and provide structural and energetic insights into this unique calcium-binding site.

Acid-Sensing Ion Channel 1a Contributes to Airway Hyperreactivity in Mice

PubMed Central

Reznikov, Leah R.; Meyerholz, David K.; Adam, Ryan J.; Abou Alaiwa, Mahmoud; Jaffer, Omar; Michalski, Andrew S.; Powers, Linda S.; Price, Margaret P.; Stoltz, David A.; Welsh, Michael J.

2016-01-01

Neurons innervating the airways contribute to airway hyperreactivity (AHR), a hallmark feature of asthma. Several observations suggested that acid-sensing ion channels (ASICs), neuronal cation channels activated by protons, might contribute to AHR. For example, ASICs are found in vagal sensory neurons that innervate airways, and asthmatic airways can become acidic. Moreover, airway acidification activates ASIC currents and depolarizes neurons innervating airways. We found ASIC1a protein in vagal ganglia neurons, but not airway epithelium or smooth muscle. We induced AHR by sensitizing mice to ovalbumin and found that ASIC1a-/- mice failed to exhibit AHR despite a robust inflammatory response. Loss of ASIC1a also decreased bronchoalveolar lavage fluid levels of substance P, a sensory neuropeptide secreted from vagal sensory neurons that contributes to AHR. These findings suggest that ASIC1a is an important mediator of AHR and raise the possibility that inhibiting ASIC channels might be beneficial in asthma. PMID:27820848

Ultrasound phase rotation beamforming on multi-core DSP.

PubMed

Ma, Jieming; Karadayi, Kerem; Ali, Murtaza; Kim, Yongmin

2014-01-01

Phase rotation beamforming (PRBF) is a commonly-used digital receive beamforming technique. However, due to its high computational requirement, it has traditionally been supported by hardwired architectures, e.g., application-specific integrated circuits (ASICs) or more recently field-programmable gate arrays (FPGAs). In this study, we investigated the feasibility of supporting software-based PRBF on a multi-core DSP. To alleviate the high computing requirement, the analog front-end (AFE) chips integrating quadrature demodulation in addition to analog-to-digital conversion were defined and used. With these new AFE chips, only delay alignment and phase rotation need to be performed by DSP, substantially reducing the computational load. We implemented the delay alignment and phase rotation modules on a Texas Instruments C6678 DSP with 8 cores. We found it takes 200 μs to beamform 2048 samples from 64 channels using 2 cores. With 4 cores, 20 million samples can be beamformed in one second. Therefore, ADC frequencies up to 40 MHz with 2:1 decimation in AFE chips or up to 20 MHz with no decimation can be supported as long as the ADC-to-DSP I/O requirement can be met. The remaining 4 cores can work on back-end processing tasks and applications, e.g., color Doppler or ultrasound elastography. One DSP being able to handle both beamforming and back-end processing could lead to low-power and low-cost ultrasound machines, benefiting ultrasound imaging in general, particularly portable ultrasound machines. Copyright © 2013 Elsevier B.V. All rights reserved.

Evolutionary and Neural Computing Based Decision Support System for Disease Diagnosis from Clinical Data Sets in Medical Practice.

PubMed

Sudha, M

2017-09-27

As a recent trend, various computational intelligence and machine learning approaches have been used for mining inferences hidden in the large clinical databases to assist the clinician in strategic decision making. In any target data the irrelevant information may be detrimental, causing confusion for the mining algorithm and degrades the prediction outcome. To address this issue, this study attempts to identify an intelligent approach to assist disease diagnostic procedure using an optimal set of attributes instead of all attributes present in the clinical data set. In this proposed Application Specific Intelligent Computing (ASIC) decision support system, a rough set based genetic algorithm is employed in pre-processing phase and a back propagation neural network is applied in training and testing phase. ASIC has two phases, the first phase handles outliers, noisy data, and missing values to obtain a qualitative target data to generate appropriate attribute reduct sets from the input data using rough computing based genetic algorithm centred on a relative fitness function measure. The succeeding phase of this system involves both training and testing of back propagation neural network classifier on the selected reducts. The model performance is evaluated with widely adopted existing classifiers. The proposed ASIC system for clinical decision support has been tested with breast cancer, fertility diagnosis and heart disease data set from the University of California at Irvine (UCI) machine learning repository. The proposed system outperformed the existing approaches attaining the accuracy rate of 95.33%, 97.61%, and 93.04% for breast cancer, fertility issue and heart disease diagnosis.

A 2.4-GHz ISM RF and UWB hybrid RFID real-time locating system for industrial enterprise Internet of Things

NASA Astrophysics Data System (ADS)

Zhai, Chuanying; Zou, Zhuo; Zhou, Qin; Mao, Jia; Chen, Qiang; Tenhunen, Hannu; Zheng, Lirong; Xu, Lida

2017-07-01

This paper presents a 2.4-GHz radio frequency (RF) and ultra-wide bandwidth (UWB) hybrid real-time locating system (RTLS) for industrial enterprise Internet of Things (IoT). It employs asymmetric wireless link, that is, UWB radio is utilised for accurate positioning up to 10 cm in critical sites, whereas 2.4-GHz RF is used for tag control and coarse positioning in non-critical sites. The specified communication protocol and the adaptive tag synchronisation rate ensure reliable and deterministic access with a scalable system capacity and avoid unpredictable latency and additional energy consumption of retransmissions due to collisions. The tag, consisting of a commercial 2.4-GHz transceiver and a customised application-specific integrated circuit (ASIC) UWB transmitter (Tx), is able to achieve up to 3 years' battery life at 1600 tags per position update second with 1000 mAh battery in one cluster. The time difference of arrival (TDoA)-based positioning experiment at UWB radio is performed on the designed software-defined radio (SDR) platform.

Miniaturized neural sensing and optogenetic stimulation system for behavioral studies in the rat

NASA Astrophysics Data System (ADS)

Kim, Min Hyuck; Nam, Ilho; Ryu, Youngki; Wellman, Laurie W.; Sanford, Larry D.; Yoon, Hargsoon

2015-04-01

Real time sensing of localized electrophysiological and neurochemical signals associated with spontaneous and evoked neural activity is critically important for understanding neural networks in the brain. Our goal is to enhance the functionality and flexibility of a neural sensing and stimulation system for the observation of brain activity that will enable better understanding from the level of individual cells to that of global structures. We have thus developed a miniaturized electronic system for in-vivo neurotransmitter sensing and optogenetic stimulation amenable to behavioral studies in the rat. The system contains a potentiostat, a data acquisition unit, a control unit, and a wireless data transfer unit. For the potentiostat, we applied embedded op-amps to build single potential amperometry for electrochemical sensing of dopamine. A light emitting diode is controlled by a microcontroller and pulse width modulation utilized to control optogenetic stimulation within a sub-millisecond level. In addition, this proto-typed electronic system contains a Bluetooth module for wireless data communication. In the future, an application-specific integrated circuit (ASIC) will be designed for further miniaturization of the system.

External unit for a semi-implantable middle ear hearing device.

PubMed

Garverick, S L; Kane, M; Ko, W H; Maniglia, A J

1997-06-01

A miniaturized, low-power external unit has been developed for the clinical trials of a semi-implantable middle ear electromagnetic hearing device (SIMEHD) which uses radio-frequency telemetry to couple sound signals to the internal unit. The external unit is based on a commercial hearing aid which provides proven audio amplification and compression. Its receiver is replaced by an application-specific integrated circuit (ASIC) which: 1) adjusts the direct-current bias of the audio input according to its peak value; 2) converts the audio signal to a one-bit digital form using sigma-delta modulation; 3) modulates the sigma-delta output with a radio-frequency (RF) oscillator; and 4) drives the external RF coil and tuning capacitor using a field-effect transistor operated in class D. The external unit functions as expected and has been used to operate bench-top tests to the SIMEHD. Measured current consumption is 1.65-2.15 mA, which projects to a battery lifetime of about 15 days. Bandwidth is 6 kHz and harmonic distortion is about 2%.

Digital control of magnetic bearings in a cryogenic cooler

NASA Technical Reports Server (NTRS)

Feeley, J.; Law, A.; Lind, F.

1990-01-01

This paper describes the design of a digital control system for control of magnetic bearings used in a spaceborne cryogenic cooler. The cooler was developed by Philips Laboratories for the NASA Goddard Space Flight Center. Six magnetic bearing assemblies are used to levitate the piston, displacer, and counter-balance of the cooler. The piston and displacer are driven by linear motors in accordance with Stirling cycle thermodynamic principles to produce the desired cooling effect. The counter-balance is driven by a third linear motor to cancel motion induced forces that would otherwise be transmitted to the spacecraft. An analog control system is currently used for bearing control. The purpose of this project is to investigate the possibilities for improved performance using digital control. Areas for potential improvement include transient and steady state control characteristics, robustness, reliability, adaptability, alternate control modes, size, weight, and cost. The present control system is targeted for the Intel 80196 microcontroller family. The eventual introduction of application specific integrated circuit (ASIC) technology to this problem may produce a unique and elegant solution both here and in related industrial problems.

The Belle II imaging Time-of-Propagation (iTOP) detector

NASA Astrophysics Data System (ADS)

Fast, J.; Belle II Barrel Particle Identification Group

2017-12-01

High precision flavor physics measurements are an essential complement to the direct searches for new physics at the LHC ATLAS and CMS experiments. Such measurements will be performed using the upgraded Belle II detector that will take data at the SuperKEKB accelerator. With 40x the luminosity of KEKB, the detector systems must operate efficiently at much higher rates than the original Belle detector. A central element of the upgrade is the barrel particle identification system. Belle II has built and installed an imaging-Time-of-Propagation (iTOP) detector. The iTOP uses quartz optics as Cherenkov radiators. The photons are transported down the quartz bars via total internal reflection with a spherical mirror at the forward end to reflect photons to the backward end where they are imaged onto an array of segmented Micro-Channel Plate Photo-Multiplier Tubes (MCP-PMTs). The system is read out using giga-samples per second waveform sampling Application-Specific Integrated Circuits (ASICs). The combined timing and spatial distribution of the photons for each event are used to determine particle species. This paper provides an overview of the iTOP system.

Radiation Hardened Electronics Destined For Severe Nuclear Reactor Environments

DOE Office of Scientific and Technical Information (OSTI.GOV)

Holbert, Keith E.; Clark, Lawrence T.

Post nuclear accident conditions represent a harsh environment for electronics. The full station blackout experience at Fukushima shows the necessity for emergency sensing capabilities in a radiation-enhanced environment. This NEET (Nuclear Energy Enabling Technologies) research project developed radiation hardened by design (RHBD) electronics using commercially available technology that employs commercial off-the-shelf (COTS) devices and present generation circuit fabrication techniques to improve the total ionizing dose (TID) hardness of electronics. Such technology not only has applicability to severe accident conditions but also to facilities throughout the nuclear fuel cycle in which radiation tolerance is required. For example, with TID tolerance tomore » megarads of dose, electronics could be deployed for long-term monitoring, inspection and decontamination missions. The present work has taken a two-pronged approach, specifically, development of both board and application-specific integrated circuit (ASIC) level RHBD techniques. The former path has focused on TID testing of representative microcontroller ICs with embedded flash (eFlash) memory, as well as standalone flash devices that utilize the same fabrication technologies. The standalone flash devices are less complicated, allowing better understanding of the TID response of the crucial circuits. Our TID experiments utilize biased components that are in-situ tested, and in full operation during irradiation. A potential pitfall in the qualification of memory circuits is the lack of rigorous testing of the possible memory states. For this reason, we employ test patterns that include all ones, all zeros, a checkerboard of zeros and ones, an inverse checkerboard, and random data. With experimental evidence of improved radiation response for unbiased versus biased conditions, a demonstration-level board using the COTS devices was constructed. Through a combination of redundancy and power gating, the demonstration board exhibits radiation resilience to over 200 krad. Furthermore, our ASIC microprocessor using RHBD techniques was shown to be fully functional after an exposure of 2.5 Mrad whereas the COTS microcontroller units failed catastrophically at <100 krad. The methods developed in this work can facilitate the long-term viability of radiation-hard robotic systems, thereby avoiding obsolescence issues. As a case in point, the nuclear industry with its low purchasing power does not drive the semiconductor industry strategic plans, and the rapid advancements in electronics technology can leave legacy systems stranded.« less

PFM2: a 32 × 32 processor for X-ray diffraction imaging at FELs

NASA Astrophysics Data System (ADS)

Manghisoni, M.; Fabris, L.; Re, V.; Traversi, G.; Ratti, L.; Grassi, M.; Lodola, L.; Malcovati, P.; Vacchi, C.; Pancheri, L.; Benkechcache, M. E. A.; Dalla Betta, G.-F.; Xu, H.; Verzellesi, G.; Ronchin, S.; Boscardin, M.; Batignani, G.; Bettarini, S.; Casarosa, G.; Forti, F.; Giorgi, M.; Paladino, A.; Paoloni, E.; Rizzo, G.; Morsani, F.

2016-11-01

This work is concerned with the design of a readout chip for application to experiments at the next generation X-ray Free Electron Lasers (FEL). The ASIC, named PixFEL Matrix (PFM2), has been designed in a 65 nm CMOS technology and consists of 32 × 32 pixels. Each cell covers an area of 110 × 110 μm2 and includes a low-noise charge sensitive amplifier (CSA) with dynamic signal compression, a time-variant shaper used to process the preamplifier output signal, a 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) and digital circuitry for channel control and data readout. Two different solutions for the readout channel, based on different versions of the time-variant filter, have been integrated in the chip. Both solutions can be operated in such a way to cope with the high frame rate (exceeding 1 MHz) foreseen for future X-ray FEL machines. The ASIC will be bump bonded to a slim/active edge pixel sensor to form the first demonstrator for the PixFEL X-ray imager. This work has been carried out in the frame of the PixFEL project funded by Istituto Nazionale di Fisica Nucleare (INFN), Italy.

X-ray and gamma ray detector readout system

DOEpatents

Tumer, Tumay O; Clajus, Martin; Visser, Gerard

2010-10-19

A readout electronics scheme is under development for high resolution, compact PET (positron emission tomography) imagers based on LSO (lutetium ortho-oxysilicate, Lu.sub.2SiO.sub.5) scintillator and avalanche photodiode (APD) arrays. The key is to obtain sufficient timing and energy resolution at a low power level, less than about 30 mW per channel, including all required functions. To this end, a simple leading edge level crossing discriminator is used, in combination with a transimpedance preamplifier. The APD used has a gain of order 1,000, and an output noise current of several pA/ Hz, allowing bipolar technology to be used instead of CMOS, for increased speed and power efficiency. A prototype of the preamplifier and discriminator has been constructed, achieving timing resolution of 1.5 ns FWHM, 2.7 ns full width at one tenth maximum, relative to an LSO/PMT detector, and an energy resolution of 13.6% FWHM at 511 keV, while operating at a power level of 22 mW per channel. Work is in progress towards integration of this preamplifier and discriminator with appropriate coincidence logic and amplitude measurement circuits in an ASIC suitable for a high resolution compact PET instrument. The detector system and/or ASIC can also be used for many other applications for medical to industrial imaging.

Acid-sensing ion channels in mouse olfactory bulb M/T neurons

PubMed Central

Li, Ming-Hua; Liu, Selina Qiuying; Inoue, Koichi; Lan, Jinquan; Simon, Roger P.

2014-01-01

The olfactory bulb contains the first synaptic relay in the olfactory pathway, the sensory system in which odorants are detected enabling these chemical stimuli to be transformed into electrical signals and, ultimately, the perception of odor. Acid-sensing ion channels (ASICs), a family of proton-gated cation channels, are widely expressed in neurons of the central nervous system. However, no direct electrophysiological and pharmacological characterizations of ASICs in olfactory bulb neurons have been described. Using a combination of whole-cell patch-clamp recordings and biochemical and molecular biological analyses, we demonstrated that functional ASICs exist in mouse olfactory bulb mitral/tufted (M/T) neurons and mainly consist of homomeric ASIC1a and heteromeric ASIC1a/2a channels. ASIC activation depolarized cultured M/T neurons and increased their intracellular calcium concentration. Thus, ASIC activation may play an important role in normal olfactory function. PMID:24821964

Acid-sensing ion channels: trafficking and synaptic function.

PubMed

Zha, Xiang-ming

2013-01-02

Extracellular acidification occurs in the brain with elevated neural activity, increased metabolism, and neuronal injury. This reduction in pH can have profound effects on brain function because pH regulates essentially every single biochemical reaction. Therefore, it is not surprising to see that Nature evolves a family of proteins, the acid-sensing ion channels (ASICs), to sense extracellular pH reduction. ASICs are proton-gated cation channels that are mainly expressed in the nervous system. In recent years, a growing body of literature has shown that acidosis, through activating ASICs, contributes to multiple diseases, including ischemia, multiple sclerosis, and seizures. In addition, ASICs play a key role in fear and anxiety related psychiatric disorders. Several recent reviews have summarized the importance and therapeutic potential of ASICs in neurological diseases, as well as the structure-function relationship of ASICs. However, there is little focused coverage on either the basic biology of ASICs or their contribution to neural plasticity. This review will center on these topics, with an emphasis on the synaptic role of ASICs and molecular mechanisms regulating the spatial distribution and function of these ion channels.

Flexible high speed codec

NASA Technical Reports Server (NTRS)

Boyd, R. W.; Hartman, W. F.

1992-01-01

The project's objective is to develop an advanced high speed coding technology that provides substantial coding gains with limited bandwidth expansion for several common modulation types. The resulting technique is applicable to several continuous and burst communication environments. Decoding provides a significant gain with hard decisions alone and can utilize soft decision information when available from the demodulator to increase the coding gain. The hard decision codec will be implemented using a single application specific integrated circuit (ASIC) chip. It will be capable of coding and decoding as well as some formatting and synchronization functions at data rates up to 300 megabits per second (Mb/s). Code rate is a function of the block length and can vary from 7/8 to 15/16. Length of coded bursts can be any multiple of 32 that is greater than or equal to 256 bits. Coding may be switched in or out on a burst by burst basis with no change in the throughput delay. Reliability information in the form of 3-bit (8-level) soft decisions, can be exploited using applique circuitry around the hard decision codec. This applique circuitry will be discrete logic in the present contract. However, ease of transition to LSI is one of the design guidelines. Discussed here is the selected coding technique. Its application to some communication systems is described. Performance with 4, 8, and 16-ary Phase Shift Keying (PSK) modulation is also presented.

Ex-vivo HIFU experiments using a 32 × 32-element CMUT array

PubMed Central

Yoon, Hyo-Seon; Chang, Chienliu; Jang, Ji Hoon; Bhuyan, Anshuman; Choe, Jung Woo; Nikoozadeh, Amin; Watkins, Ronald D.; Stephens, Douglas N.; Pauly, Kim Butts; Khuri-Yakub, Butrus T.

2016-01-01

High-intensity focused ultrasound (HIFU) has been used as noninvasive treatment for various diseases. For these therapeutic applications, capacitive micromachined ultrasonic transducers (CMUTs) have advantages that make them potentially preferred transducers over traditional piezoelectric transducers. In this paper, we present the design and the fabrication process of an 8 × 8-mm2, 32 × 32-element 2-D CMUT array for HIFU applications. To reduce the system complexity for addressing the 1024 transducer elements, we propose to group the CMUT array elements into eight HIFU channels based on the phase delay from the CMUT element to the targeted focal point. Designed to focus at an 8-mm depth with a 5-MHz exciting frequency, this grouping scheme was realized using a custom application-specific integrated circuit (ASIC). With a 40-V DC bias and a 60-V peak-to-peak AC excitation, the surface pressure was measured 1.2 MPa peak-to-peak and stayed stable for a long enough time to create a lesion. With this DC and AC voltage combination, the measured peak-to-peak output pressure at the focus was 8.5 MPa, which is expected to generate a lesion in a minute according to the temperature simulation. Following ex-vivo tissue experiments successfully demonstrated its capability to make lesions in both bovine muscle and liver tissue. PMID:27913330

A Low Noise CMOS Readout Based on a Polymer-Coated SAW Array for Miniature Electronic Nose

PubMed Central

Wu, Cheng-Chun; Liu, Szu-Chieh; Chiu, Shih-Wen; Tang, Kea-Tiong

2016-01-01

An electronic nose (E-Nose) is one of the applications for surface acoustic wave (SAW) sensors. In this paper, we present a low-noise complementary metal–oxide–semiconductor (CMOS) readout application-specific integrated circuit (ASIC) based on an SAW sensor array for achieving a miniature E-Nose. The center frequency of the SAW sensors was measured to be approximately 114 MHz. Because of interference between the sensors, we designed a low-noise CMOS frequency readout circuit to enable the SAW sensor to obtain frequency variation. The proposed circuit was fabricated in Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 μm 1P6M CMOS process technology. The total chip size was nearly 1203 × 1203 μm2. The chip was operated at a supply voltage of 1 V for a digital circuit and 1.8 V for an analog circuit. The least measurable difference between frequencies was 4 Hz. The detection limit of the system, when estimated using methanol and ethanol, was 0.1 ppm. Their linearity was in the range of 0.1 to 26,000 ppm. The power consumption levels of the analog and digital circuits were 1.742 mW and 761 μW, respectively. PMID:27792131

A Low Noise CMOS Readout Based on a Polymer-Coated SAW Array for Miniature Electronic Nose.

PubMed

Wu, Cheng-Chun; Liu, Szu-Chieh; Chiu, Shih-Wen; Tang, Kea-Tiong

2016-10-25

An electronic nose (E-Nose) is one of the applications for surface acoustic wave (SAW) sensors. In this paper, we present a low-noise complementary metal-oxide-semiconductor (CMOS) readout application-specific integrated circuit (ASIC) based on an SAW sensor array for achieving a miniature E-Nose. The center frequency of the SAW sensors was measured to be approximately 114 MHz. Because of interference between the sensors, we designed a low-noise CMOS frequency readout circuit to enable the SAW sensor to obtain frequency variation. The proposed circuit was fabricated in Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 μm 1P6M CMOS process technology. The total chip size was nearly 1203 × 1203 μm². The chip was operated at a supply voltage of 1 V for a digital circuit and 1.8 V for an analog circuit. The least measurable difference between frequencies was 4 Hz. The detection limit of the system, when estimated using methanol and ethanol, was 0.1 ppm. Their linearity was in the range of 0.1 to 26,000 ppm. The power consumption levels of the analog and digital circuits were 1.742 mW and 761 μW, respectively.

Charge-sensitive front-end electronics with operational amplifiers for CdZnTe detectors

NASA Astrophysics Data System (ADS)

Födisch, P.; Berthel, M.; Lange, B.; Kirschke, T.; Enghardt, W.; Kaever, P.

2016-09-01

Cadmium zinc telluride (CdZnTe, CZT) radiation detectors are suitable for a variety of applications, due to their high spatial resolution and spectroscopic energy performance at room temperature. However, state-of-the-art detector systems require high-performance readout electronics. Though an application-specific integrated circuit (ASIC) is an adequate solution for the readout, requirements of high dynamic range and high throughput are not available in any commercial circuit. Consequently, the present study develops the analog front-end electronics with operational amplifiers for an 8×8 pixelated CZT detector. For this purpose, we modeled an electrical equivalent circuit of the CZT detector with the associated charge-sensitive amplifier (CSA). Based on a detailed network analysis, the circuit design is completed by numerical values for various features such as ballistic deficit, charge-to-voltage gain, rise time, and noise level. A verification of the performance is carried out by synthetic detector signals and a pixel detector. The experimental results with the pixel detector assembly and a 22Na radioactive source emphasize the depth dependence of the measured energy. After pulse processing with depth correction based on the fit of the weighting potential, the energy resolution is 2.2% (FWHM) for the 511 keV photopeak.

SEDHI: a new generation of detection electronics for earth observation satellites

NASA Astrophysics Data System (ADS)

Dantes, Didier; Neveu, Claude; Biffi, Jean-Marc; Devilliers, Christophe; Andre, Serge

2017-11-01

Future earth observation optical systems will be more and more demanding in terms of ground sampling distance, swath width, number of spectral bands, duty cycle. Existing architectures of focal planes and video processing electronics are hardly compatible with these new requirements: electronic functions are split in several units, and video processing is limited to frequencies around 5 MHz in order to fulfil the radiometric requirements expected for high performance image quality systems. This frequency limitation induces a high number of video chains operated in parallel to process the huge amount of pixels at focal plane output, and leads to unacceptable mass and power consumption budgets. Furthermore, splitting the detection electronics functions into several units (at least one for the focal plane and proximity electronics, and one for the video processing functions) does not optimise the production costs : specific development efforts must be performed on critical analogue electronics at each equipment level and operations of assembly, integration and tests are duplicated at equipment and subsystem levels. Alcatel Space Industries has proposed to CNES a new concept of highly integrated detection electronics (SEDHI), and is developing for CNES a breadboard which will allow to confirm its potentialities. This paper presents the trade-off study which have been performed before selection of this new concept and summarises the main advantages and drawbacks of each possible architecture. The electrical, mechanical and thermal aspects of the SEDHI concept are described, including the basic technologies : ASIC for phase shift of detector clocks, ASIC for video processing, hybrids, microchip module... The adaptability to a large amount of missions and optical instruments is also discussed.

A Cs2LiYCl6:Ce-based advanced radiation monitoring device

NASA Astrophysics Data System (ADS)

Budden, B. S.; Stonehill, L. C.; Dallmann, N.; Baginski, M. J.; Best, D. J.; Smith, M. B.; Graham, S. A.; Dathy, C.; Frank, J. M.; McClish, M.

2015-06-01

Cs2LiYCl6:Ce3+ (CLYC) scintillator has gained recent interest because of its ability to perform simultaneous gamma spectroscopy and thermal neutron detection. Discrimination between the two incident particle types owes to the fundamentally unique emission waveforms, a consequence of the interaction and subsequent scintillation mechanisms within the crystal. Due to this dual-mode detector capability, CLYC was selected for the development of an Advanced Radiation Monitoring Device (ARMD), a compact handheld instrument for radioisotope identification and localization. ARMD consists of four 1 in.-right cylindrical CLYC crystals, custom readout electronics including a suitable multi-window application specific integrated circuit (ASIC), battery pack, proprietary software, and Android-based tablet for high-level analysis and display. We herein describe the motivation of the work and engineering design of the unit, and we explain the software embedded in the core module and for radioisotope analysis. We report an operational range of tens of keV to 8.5 MeV with approximately 5.3% gamma energy resolution at 662 keV, thermal neutron detection efficiency of 10%, battery lifetime of up to 10 h, manageable rates of 20 kHz; further, we describe in greater detail time to identify specific gamma source setups.

Smart image sensors: an emerging key technology for advanced optical measurement and microsystems

NASA Astrophysics Data System (ADS)

Seitz, Peter

1996-08-01

Optical microsystems typically include photosensitive devices, analog preprocessing circuitry and digital signal processing electronics. The advances in semiconductor technology have made it possible today to integrate all photosensitive and electronical devices on one 'smart image sensor' or photo-ASIC (application-specific integrated circuits containing photosensitive elements). It is even possible to provide each 'smart pixel' with additional photoelectronic functionality, without compromising the fill factor substantially. This technological capability is the basis for advanced cameras and optical microsystems showing novel on-chip functionality: Single-chip cameras with on- chip analog-to-digital converters for less than $10 are advertised; image sensors have been developed including novel functionality such as real-time selectable pixel size and shape, the capability of performing arbitrary convolutions simultaneously with the exposure, as well as variable, programmable offset and sensitivity of the pixels leading to image sensors with a dynamic range exceeding 150 dB. Smart image sensors have been demonstrated offering synchronous detection and demodulation capabilities in each pixel (lock-in CCD), and conventional image sensors are combined with an on-chip digital processor for complete, single-chip image acquisition and processing systems. Technological problems of the monolithic integration of smart image sensors include offset non-uniformities, temperature variations of electronic properties, imperfect matching of circuit parameters, etc. These problems can often be overcome either by designing additional compensation circuitry or by providing digital correction routines. Where necessary for technological or economic reasons, smart image sensors can also be combined with or realized as hybrids, making use of commercially available electronic components. It is concluded that the possibilities offered by custom smart image sensors will influence the design and the performance of future electronic imaging systems in many disciplines, reaching from optical metrology to machine vision on the factory floor and in robotics applications.

An integrated multichannel neural recording analog front-end ASIC with area-efficient driven right leg circuit.

PubMed

Tao Tang; Wang Ling Goh; Lei Yao; Jia Hao Cheong; Yuan Gao

2017-07-01

This paper describes an integrated multichannel neural recording analog front end (AFE) with a novel area-efficient driven right leg (DRL) circuit to improve the system common mode rejection ratio (CMRR). The proposed AFE consists of an AC-coupled low-noise programmable-gain amplifier, an area-efficient DRL block and a 10-bit SAR ADC. Compared to conventional DRL circuit, the proposed capacitor-less DRL design achieves 90% chip area reduction with enhanced CMRR performance, making it ideal for multichannel biomedical recording applications. The AFE circuit has been designed in a standard 0.18-μm CMOS process. Post-layout simulation results show that the AFE provides two gain settings of 54dB/60dB while consuming 1 μA per channel under a supply voltage of 1 V. The input-referred noise of the AFE integrated from 1 Hz to 10k Hz is only 4 μVrms and the CMRR is 110 dB.

Analog front-end design of the STS/MUCH-XYTER2—full size prototype ASIC for the CBM experiment

NASA Astrophysics Data System (ADS)

Kleczek, Rafal

2017-01-01

The design of the analog front-end of the STS/MUCH-XYTER2 ASIC, a full-size prototype chip for the Silicon Tracking System (STS, based on double-sided silicon strip sensors) and Muon Chamber (MUCH, based on gas sensors) detectors is presented. The ASIC contains 128 charge processing channels, each built of a charge sensitive amplifier, a polarity selection circuit and two pulse shaping amplifiers forming two parallel signal paths. The first path is used for timing measurement with a fast discriminator. The second path allows low-noise amplitude measurement with a 5-bit continuous-time flash ADC. Different operating conditions and constraints posed by two target detectors' applications require front-end electronics flexibility to meet extended system-wise requirements. The presented circuit implements switchable shaper peaking time, gain switching and trimming, input amplifier pulsed reset circuit, fail-safe measures. The power consumption is scalable (for the STS and the MUCH modes), but limited to 10 mW/channel.

Activation of acid-sensing ion channels by localized proton transient reveals their role in proton signaling.

PubMed

Zeng, Wei-Zheng; Liu, Di-Shi; Liu, Lu; She, Liang; Wu, Long-Jun; Xu, Tian-Le

2015-09-15

Extracellular transients of pH alterations likely mediate signal transduction in the nervous system. Neuronal acid-sensing ion channels (ASICs) act as sensors for extracellular protons, but the mechanism underlying ASIC activation remains largely unknown. Here, we show that, following activation of a light-activated proton pump, Archaerhodopsin-3 (Arch), proton transients induced ASIC currents in both neurons and HEK293T cells co-expressing ASIC1a channels. Using chimera proteins that bridge Arch and ASIC1a by a glycine/serine linker, we found that successful coupling occurred within 15 nm distance. Furthermore, two-cell sniffer patch recording revealed that regulated release of protons through either Arch or voltage-gated proton channel Hv1 activated neighbouring cells expressing ASIC1a channels. Finally, computational modelling predicted the peak proton concentration at the intercellular interface to be at pH 6.7, which is acidic enough to activate ASICs in vivo. Our results highlight the pathophysiological role of proton signalling in the nervous system.

Quartz/fused silica chip carriers

NASA Technical Reports Server (NTRS)

1992-01-01

The primary objective of this research and development effort was to develop monolithic microwave integrated circuit (MMIC) packaging which will operate efficiently at millimeter-wave frequencies. The packages incorporated fused silica as the substrate material which was selected due to its favorable electrical properties and potential performance improvement over more conventional materials for Ka-band operation. The first step towards meeting this objective is to develop a package that meets standard mechanical and thermal requirements using fused silica and to be compatible with semiconductor devices operating up to at least 44 GHz. The second step is to modify the package design and add multilayer and multicavity capacity to allow for application specific integrated circuits (ASIC's) to control multiple phase shifters. The final step is to adapt the package design to a phased array module with integral radiating elements. The first task was a continuation of the SBIR Phase 1 work. Phase 1 identified fused silica as a viable substrate material by demonstrating various plating, machining, and adhesion properties. In Phase 2 Task 1, a package was designed and fabricated to validate these findings. Task 2 was to take the next step in packaging and fabricate a multilayer, multichip module (MCM). This package is the predecessor to the phased array module and demonstrates the ability to via fill, circuit print, laminate, and to form vertical interconnects. The final task was to build a phased array module. The radiating elements were to be incorporated into the package instead of connecting to it with wire or ribbon bonds.

BOREHOLE FLOWMETERS: FIELD APPLICATION AND DATA ANALYSIS

EPA Science Inventory

This paper reviews application of borehole flowmeters in granular and fractured rocks. asic data obtained in the field are the ambient flow log and the pumping-induced flow log. hese basic logs may then be used to calculate other quantities of interest. he paper describes the app...

Evidence that activation of ASIC1a by acidosis increases osteoclast migration and adhesion by modulating integrin/Pyk2/Src signaling pathway.

PubMed

Li, X; Ye, J-X; Xu, M-H; Zhao, M-D; Yuan, F-L

2017-07-01

Activated acid-sensing ion channel 1a (ASIC1a) is involved in acid-induced osteoclastogenesis by regulating activation of the transcription factor NFATc1. These results indicated that ASIC1a activation by extracellular acid may cause osteoclast migration and adhesion through Ca 2+ -dependent integrin/Pyk2/Src signaling pathway. Osteoclast adhesion and migration are responsible for osteoporotic bone loss. Acidic conditions promote osteoclastogenesis. ASIC1a in osteoclasts is associated with acid-induced osteoclastogenesis through modulating transcription factor NFATc1 activation. However, the influence and the detailed mechanism of ASIC1a in regulating osteoclast adhesion and migration, in response to extracellular acid, are not well characterized. In this study, knockdown of ASIC1a was achieved in bone marrow macrophage cells using small interfering RNA (siRNA). The adhesion and migration abilities of osteoclast precursors and osteoclasts were determined by adhesion and migration assays, in vitro. Bone resorption was performed to measure osteoclast function. Cytoskeletal changes were assessed by F-actin ring formation. αvβ3 integrin expression in osteoclasts was measured by flow cytometry. Western blotting and co-immunoprecipitation were performed to measure alterations in integrin/Pyk2/Src signaling pathway. Our results showed that blockade of ASIC1a using ASIC1a-siRNA inhibited acid-induced osteoclast precursor migration and adhesion, as well as osteoclast adhesion and bone resorption; we also demonstrated that inhibition of ASIC1a decreased the cell surface αvβ3 integrin and β3 protein expression. Moreover, blocking of ASIC1a inhibited acidosis-induced actin ring formation and reduced Pyk2 and Src phosphorylation in osteoclasts and also inhibited the acid-induced association of the αvβ3 integrin/Src/Pyk2. Together, these results highlight a key functional role of ASIC1a/αvβ3 integrin/Pyk2/Src signaling pathway in migration and adhesion of osteoclasts.

Acid-Sensing Ion Channel 1a Regulates Fate of Rat Nucleus Pulposus Cells in Acid Stimulus Through Endoplasmic Reticulum Stress.

PubMed

Xie, Zhi-Yang; Chen, Lu; Zhang, Cong; Liu, Lei; Wang, Feng; Cai, Feng; Wang, Xiao-Hu; Shi, Rui; Sinkemani, Arjun; Yu, Hao-Min; Hong, Xin; Wu, Xiao-Tao

2018-01-01

Acid-sensing ion channel 1a (ASIC1a) participates in human intervertebral disc degeneration (IVDD) and regulates the destiny of nucleus pulposus cells (NPCs) in acid stimulus. However, the mechanism of ASIC1a activation and its downstream pathway remain unclear. Endoplasmic reticulum (ER) stress also participates in the acid-induced apoptosis of NPCs. The main purpose of this study was to investigate whether there is any connection between ASIC1a and ER stress in an acid-induced nucleus pulposus degeneration model. The IVDs of Sprague-Dawley rats were stained by immunohistochemical staining to evaluate the expression of ASIC1a in normal and degenerated rat nucleus pulposus. ASIC1a expression was also quantified by quantitative real-time-polymerase chain reaction and Western blotting analysis. NPCs were exposed to the culture media with acidity at pH 7.2 and 6.5 for 24 h, with or without 4-phenylbutyrate (4-PBA, a blocker of the ER stress pathway). Cell apoptosis was examined by Annexin V/Propidium Iodide (PI) staining and was quantified using flow cytometry analysis. ASIC1a-mediated intracellular calcium was determined by Ca 2+ imaging using Fura-2-AM. Acidity-induced changes in ER stress markers were studied using Western blotting analysis. In vivo , ASIC1a expression was upregulated in natural degeneration. In vitro , acid stimulus increased intracellular calcium levels, but this effect was blocked by knockdown of ASIC1a, and this reversal was partly inhibited by 4-PBA. In addition, blockade of ASIC1a reduced expression of ER stress markers, especially the proapoptotic markers. ASIC1a partly regulates ER stress and promotes apoptosis of NPCs under acid stimulus and may be a novel therapeutic target in IVDD.

Acute stress enhances learning and memory by activating acid-sensing ion channels in rats.

PubMed

Ye, Shunjie; Yang, Rong; Xiong, Qiuju; Yang, Youhua; Zhou, Lianying; Gong, Yeli; Li, Changlei; Ding, Zhenhan; Ye, Guohai; Xiong, Zhe

2018-04-15

Acute stress has been shown to enhance learning and memory ability, predominantly through the action of corticosteroid stress hormones. However, the valuable targets for promoting learning and memory induced by acute stress and the underlying molecular mechanisms remain unclear. Acid-sensing ion channels (ASICs) play an important role in central neuronal systems and involves in depression, synaptic plasticity and learning and memory. In the current study, we used a combination of electrophysiological and behavioral approaches in an effort to explore the effects of acute stress on ASICs. We found that corticosterone (CORT) induced by acute stress caused a potentiation of ASICs current via glucocorticoid receptors (GRs) not mineralocorticoid receptors (MRs). Meanwhile, CORT did not produce an increase of ASICs current by pretreated with GF109203X, an antagonist of protein kinase C (PKC), whereas CORT did result in a markedly enhancement of ASICs current by bryostatin 1, an agonist of PKC, suggesting that potentiation of ASICs function may be depended on PKC activating. More importantly, an antagonist of ASICs, amiloride (10 μM) reduced the performance of learning and memory induced by acute stress, which is further suggesting that ASICs as the key components involves in cognitive processes induced by acute stress. These results indicate that acute stress causes the enhancement of ASICs function by activating PKC signaling pathway, which leads to potentiated learning and memory. Copyright © 2018 Elsevier Inc. All rights reserved.

The BlueGene/L supercomputer

NASA Astrophysics Data System (ADS)

Bhanota, Gyan; Chen, Dong; Gara, Alan; Vranas, Pavlos

2003-05-01

The architecture of the BlueGene/L massively parallel supercomputer is described. Each computing node consists of a single compute ASIC plus 256 MB of external memory. The compute ASIC integrates two 700 MHz PowerPC 440 integer CPU cores, two 2.8 Gflops floating point units, 4 MB of embedded DRAM as cache, a memory controller for external memory, six 1.4 Gbit/s bi-directional ports for a 3-dimensional torus network connection, three 2.8 Gbit/s bi-directional ports for connecting to a global tree network and a Gigabit Ethernet for I/O. 65,536 of such nodes are connected into a 3-d torus with a geometry of 32×32×64. The total peak performance of the system is 360 Teraflops and the total amount of memory is 16 TeraBytes.

Evaluating noise performance of the IUCAA sidecar drive electronics controller (ISDEC) based system for TMT on-instrument wavefront sensing (OIWFS) application

NASA Astrophysics Data System (ADS)

Burse, Mahesh; Chattopadhyay, Sabyasachi; Ramaprakash, A. N.; Sinha, Sakya; Prabhudesai, Swapnil; Punnadi, Sujit; Chordia, Pravin; Kohok, Abhay

2016-07-01

As a part of a design study for the On-Instrument Low Order Wave-front Sensor (OIWFS) for the TMT Infra-Red Imaging Spectrograph (IRIS), we recently evaluated the noise performance of a detector control system consisting of IUCAA SIDECAR DRIVE ELECRONICS CONTROLLER (ISDEC), SIDECAR ASIC and HAWAII-2RG (H2RG) MUX. To understand and improve the performance of this system to serve as a near infrared wavefront sensor, we implemented new read out modes like multiple regions of interest with differential multi-accumulate readout schemes for the HAWAII-2RG (H2RG) detector. In this system, the firmware running in SIDECAR ASIC programs the detector for ROI readout, reads the detector, processes the detector output and writes the digitized data into its internal memory. ISDEC reads the digitized data from ASIC, performs the differential multi-accumulate operations and then sends the processed data to a PC over a USB interface. A special loopback board was designed and used to measure and reduce the noise from SIDECAR ASIC DC biases2. We were able to reduce the mean r.m.s read noise of this system down to 1-2 e. for any arbitrary window frame of 4x4 size at frame rates below about 200 Hz.

Activation of acid-sensing ion channels by localized proton transient reveals their role in proton signaling

PubMed Central

Zeng, Wei-Zheng; Liu, Di-Shi; Liu, Lu; She, Liang; Wu, Long-Jun; Xu, Tian-Le

2015-01-01

Extracellular transients of pH alterations likely mediate signal transduction in the nervous system. Neuronal acid-sensing ion channels (ASICs) act as sensors for extracellular protons, but the mechanism underlying ASIC activation remains largely unknown. Here, we show that, following activation of a light-activated proton pump, Archaerhodopsin-3 (Arch), proton transients induced ASIC currents in both neurons and HEK293T cells co-expressing ASIC1a channels. Using chimera proteins that bridge Arch and ASIC1a by a glycine/serine linker, we found that successful coupling occurred within 15 nm distance. Furthermore, two-cell sniffer patch recording revealed that regulated release of protons through either Arch or voltage-gated proton channel Hv1 activated neighbouring cells expressing ASIC1a channels. Finally, computational modelling predicted the peak proton concentration at the intercellular interface to be at pH 6.7, which is acidic enough to activate ASICs in vivo. Our results highlight the pathophysiological role of proton signalling in the nervous system. PMID:26370138

Low-power grating detection system chip for high-speed low-cost length and angle precision measurement

NASA Astrophysics Data System (ADS)

Hou, Ligang; Luo, Rengui; Wu, Wuchen

2006-11-01

This paper forwards a low power grating detection chip (EYAS) on length and angle precision measurement. Traditional grating detection method, such as resister chain divide or phase locked divide circuit are difficult to design and tune. The need of an additional CPU for control and display makes these methods' implementation more complex and costly. Traditional methods also suffer low sampling speed for the complex divide circuit scheme and CPU software compensation. EYAS is an application specific integrated circuit (ASIC). It integrates micro controller unit (MCU), power management unit (PMU), LCD controller, Keyboard interface, grating detection unit and other peripherals. Working at 10MHz, EYAS can afford 5MHz internal sampling rate and can handle 1.25MHz orthogonal signal from grating sensor. With a simple control interface by keyboard, sensor parameter, data processing and system working mode can be configured. Two LCD controllers can adapt to dot array LCD or segment bit LCD, which comprised output interface. PMU alters system between working and standby mode by clock gating technique to save power. EYAS in test mode (system action are more frequently than real world use) consumes 0.9mw, while 0.2mw in real world use. EYAS achieved the whole grating detection system function, high-speed orthogonal signal handling in a single chip with very low power consumption.

Development of cryogenic CMOS Readout ASICs for the Point-Contact HPGe Detectors for Dark Matter Search and Neutrino Experiments

NASA Astrophysics Data System (ADS)

Deng, Zhi; He, Li; Liu, Feng; Liu, Yinong; Xue, Tao; Li, Yulan; Yue, Qian

2017-05-01

The paper presents the developments of two cryogenic readout ASICs for the point-contact HPGe detectors for dark matter search and neutrino experiments. Extremely low noise readout electronics were demanded and the capability of working at cryogenic temperatures may bring great advantages. The first ASIC was a monolithic CMOS charge sensitive preamplifier with its noise optimized for ∼1 pF input capacitance. The second ASIC was a waveform recorder based on switched capacitor array. These two ASICs were fabricated in CMOS 350 nm and 180 nm processes respectively. The prototype chips were tested and showed promising results. Both ASICs worked well at low temperature. The preamplifier had achieved ENC of 10.3 electrons with 0.7 pF input capacitance and the SCA chip could run at 9 bit effective resolution and 25 MSPS sampling rate.

The function and regulation of acid‐sensing ion channels (ASICs) and the epithelial Na+ channel (ENaC): IUPHAR Review 19

PubMed Central

Boscardin, Emilie; Alijevic, Omar; Hummler, Edith

2016-01-01

Acid‐sensing ion channels (ASICs) and the epithelial Na+ channel (ENaC) are both members of the ENaC/degenerin family of amiloride‐sensitive Na+ channels. ASICs act as proton sensors in the nervous system where they contribute, besides other roles, to fear behaviour, learning and pain sensation. ENaC mediates Na+ reabsorption across epithelia of the distal kidney and colon and of the airways. ENaC is a clinically used drug target in the context of hypertension and cystic fibrosis, while ASIC is an interesting potential target. Following a brief introduction, here we will review selected aspects of ASIC and ENaC function. We discuss the origin and nature of pH changes in the brain and the involvement of ASICs in synaptic signalling. We expose how in the peripheral nervous system, ASICs cover together with other ion channels a wide pH range as proton sensors. We introduce the mechanisms of aldosterone‐dependent ENaC regulation and the evidence for an aldosterone‐independent control of ENaC activity, such as regulation by dietary K+. We then provide an overview of the regulation of ENaC by proteases, a topic of increasing interest over the past few years. In spite of the profound differences in the physiological and pathological roles of ASICs and ENaC, these channels share many basic functional and structural properties. It is likely that further research will identify physiological contexts in which ASICs and ENaC have similar or overlapping roles. PMID:27278329

Protons are a neurotransmitter that regulates synaptic plasticity in the lateral amygdala.

PubMed

Du, Jianyang; Reznikov, Leah R; Price, Margaret P; Zha, Xiang-ming; Lu, Yuan; Moninger, Thomas O; Wemmie, John A; Welsh, Michael J

2014-06-17

Stimulating presynaptic terminals can increase the proton concentration in synapses. Potential receptors for protons are acid-sensing ion channels (ASICs), Na(+)- and Ca(2+)-permeable channels that are activated by extracellular acidosis. Those observations suggest that protons might be a neurotransmitter. We found that presynaptic stimulation transiently reduced extracellular pH in the amygdala. The protons activated ASICs in lateral amygdala pyramidal neurons, generating excitatory postsynaptic currents. Moreover, both protons and ASICs were required for synaptic plasticity in lateral amygdala neurons. The results identify protons as a neurotransmitter, and they establish ASICs as the postsynaptic receptor. They also indicate that protons and ASICs are a neurotransmitter/receptor pair critical for amygdala-dependent learning and memory.

Wireless microsensors for health monitoring of aircraft structures

NASA Astrophysics Data System (ADS)

Varadan, Vijay K.

2003-01-01

The integration of MEMS, IDTs (interdigital transducers) and required microelectronics and conformal antennas to realize programmable, robust and low cost passive microsensors suitable for many military structures and systems including aircraft, missiles and munitions is presented in this paper. The technology is currently being applied to the structural health monitoring of critical aircraft components. The approach integrates acoustic emission, strain gauges, MEMS accelerometers, gyroscopes and vibration monitoring devices with signal processing electronics to provide real-time indicators of incipient failure of aircraft components with a known history of catastrophic failure due to fracture. Recently a combination of the need for safety in the air and the desire to control costs is encouraging the use of in-flight monitoring of aircraft components and systems using light-weight, wireless and cost effective microsensors and MEMS. An in-situ Aircraft structural health monitoring (ASHM) system, with sensors embedded in the composite structure or surface-mounted on the structure, would permit the timely detection of damage in aircraft. Micromachining offers the potential for fabricating a range of microsensors and MEMS for structural applications including load, vibration and acoustics characterization and monitoring. Such microsensors are extremely small; they can be embedded into structural materials, can be mass-produced and are therefore potentially cheap. Additionally a range of sensor types can be integrated onto a single chip with built-in electronics and ASIC (Application Specific Integrated Circuit), providing a low power Microsystems. The smart sensors are being developed using the standard microelectronics and micromachining in conjunction with novel Penn State smart electronics or wireless communication systems suitable for condition monitoring of aircraft structures in-flight. A hybrid accelerometer and gyroscope in a single chip suitable for inertial navigation system and other microsensors for health monitoring and condition-based maintenance of structures, drag sensing and control of aircraft, strain and deflection of structures and systems, ice sensing on aircraft, remote temperature and humidity measurement of propellant in munitions, chemical sensing, etc. are discussed.

A Flexible VHDL Floating Point Module for Control Algorithm Implementation in Space Applications

NASA Astrophysics Data System (ADS)

Padierna, A.; Nicoleau, C.; Sanchez, J.; Hidalgo, I.; Elvira, S.

2012-08-01

The implementation of control loops for space applications is an area with great potential. However, the characteristics of this kind of systems, such as its wide dynamic range of numeric values, make inadequate the use of fixed-point algorithms.However, because the generic chips available for the treatment of floating point data are, in general, not qualified to operate in space environments and the possibility of using an IP module in a FPGA/ASIC qualified for space is not viable due to the low amount of logic cells available for these type of devices, it is necessary to find a viable alternative.For these reasons, in this paper a VHDL Floating Point Module is presented. This proposal allows the design and execution of floating point algorithms with acceptable occupancy to be implemented in FPGAs/ASICs qualified for space environments.

MuTRiG: a mixed signal Silicon Photomultiplier readout ASIC with high timing resolution and gigabit data link

NASA Astrophysics Data System (ADS)

Chen, H.; Briggl, K.; Eckert, P.; Harion, T.; Munwes, Y.; Shen, W.; Stankova, V.; Schultz-Coulon, H. C.

2017-01-01

MuTRiG is a mixed signal Silicon Photomultiplier readout ASIC designed in UMC 180 nm CMOS technology for precise timing and high event rate applications in high energy physics experiments and medical imaging. It is dedicated to the readout of the scintillating fiber detector and the scintillating tile detector of the Mu3e experiment. The MuTRiG chip extends the excellent timing performance of the STiCv3 chip with a fast digital readout for high rate applications. The high timing performance of the fully differential SiPM readout channels and 50 ps time binning TDCs are complemented by an upgraded digital readout logic and a 1.28 Gbps LVDS serial data link. The design of the chip and the characterization results of the analog front-end, TDC and the LVDS data link are presented.

Novel NI-Based Ohmic Contacts To a-SiC for High Temperature and High Power Device Applications

DTIC Science & Technology

2002-01-01

Temperature and High Power Device Applications DISTRIBUTION: Approved for public release, distribution unlimited This paper is part of the following report...retained omnicity after 100 h of aging and was found to be chemically and microstructurally stable. These findings indicate that the 1000,’C annealed

ASIC1a Deficient Mice Show Unaltered Neurodegeneration in the Subacute MPTP Model of Parkinson Disease.

PubMed

Komnig, Daniel; Imgrund, Silke; Reich, Arno; Gründer, Stefan; Falkenburger, Björn H

2016-01-01

Inflammation contributes to the death of dopaminergic neurons in Parkinson disease and can be accompanied by acidification of extracellular pH, which may activate acid-sensing ion channels (ASIC). Accordingly, amiloride, a non-selective inhibitor of ASIC, was protective in an acute 1-methyl-4-phenyl-1,2,3,6-tetrahydropyridine (MPTP) mouse model of Parkinson disease. To complement these findings we determined MPTP toxicity in mice deficient for ASIC1a, the most common ASIC isoform in neurons. MPTP was applied i.p. in doses of 30 mg per kg on five consecutive days. We determined the number of dopaminergic neurons in the substantia nigra, assayed by stereological counting 14 days after the last MPTP injection, the number of Nissl positive neurons in the substantia nigra, and the concentration of catecholamines in the striatum. There was no difference between ASIC1a-deficient mice and wildtype controls. We are therefore not able to confirm that ASIC1a are involved in MPTP toxicity. The difference might relate to the subacute MPTP model we used, which more closely resembles the pathogenesis of Parkinson disease, or to further targets of amiloride.

An 8-PSK TDMA uplink modulation and coding system

NASA Technical Reports Server (NTRS)

Ames, S. A.

1992-01-01

The combination of 8-phase shift keying (8PSK) modulation and greater than 2 bits/sec/Hz drove the design of the Nyquist filter to one specified to have a rolloff factor of 0.2. This filter when built and tested was found to produce too much intersymbol interference and was abandoned for a design with a rolloff factor of 0.4. The preamble is limited to 100 bit periods of the uncoded bit period of 5 ns for a maximum preamble length of 500 ns or 40 8PSK symbol times at 12.5 ns per symbol. For 8PSK modulation, the required maximum degradation of 1 dB in -20 dB cochannel interference (CCI) drove the requirement for forward error correction coding. In this contract, the funding was not sufficient to develop the proposed codec so the codec was limited to a paper design during the preliminary design phase. The mechanization of the demodulator is digital, starting from the output of the analog to digital converters which quantize the outputs of the quadrature phase detectors. This approach is amenable to an application specific integrated circuit (ASIC) replacement in the next phase of development.

A brief test of the Hewlett-Packard MEMS seismic accelerometer

USGS Publications Warehouse

Homeijer, Brian D.; Milligan, Donald J.; Hutt, Charles R.

2014-01-01

Testing was performed on a prototype of Hewlett-Packard (HP) Micro-Electro-Mechanical Systems (MEMS) seismic accelerometer at the U.S. Geological Survey’s Albuquerque Seismological Laboratory. This prototype was built using discrete electronic components. The self-noise level was measured during low seismic background conditions and found to be 9.8 ng/√Hz at periods below 0.2 s (frequencies above 5 Hz). The six-second microseism noise was also discernible. The HP MEMS accelerometer was compared to a Geotech Model GS-13 reference seismometer during seismic noise and signal levels well above the self-noise of the accelerometer. Matching power spectral densities (corrected for accelerometer and seismometer responses to represent true ground motion) indicated that the HP MEMS accelerometer has a flat (constant) response to acceleration from 0.0125 Hz to at least 62.5 Hz. Tilt calibrations of the HP MEMS accelerometer verified that the flat response to acceleration extends to 0 Hz. Future development of the HP MEMS accelerometer includes replacing the discreet electronic boards with a low power application-specific integrated circuit (ASIC) and increasing the dynamic range of the sensor to detect strong motion signals above one gravitational acceleration, while maintaining the self-noise observed during these tests.

The Belle II imaging Time-of-Propagation (iTOP) detector

DOE PAGES

Fast, J.

2017-02-16

High precision flavor physics measurements are an essential complement to the direct searches for new physics at the LHC ATLAS and CMS experiments. We will perform these measurements using the upgraded Belle II detector that will take data at the SuperKEKB accelerator. With 40x the luminosity of KEKB, the detector systems must operate efficiently at much higher rates than the original Belle detector. A central element of the upgrade is the barrel particle identification system. Belle II has built and installed an imaging-Time-of-Propagation (iTOP) detector. The iTOP uses quartz optics as Cherenkov radiators. The photons are transported down the quartzmore » bars via total internal reflection with a spherical mirror at the forward end to reflect photons to the backward end where they are imaged onto an array of segmented Micro-Channel Plate Photo-Multiplier Tubes (MCP-PMTs). The system is read out using giga-samples per second waveform sampling Application-Specific Integrated Circuits (ASICs). Furthermore, we used the combined timing and spatial distribution of the photons for each event to determine particle species. This paper provides an overview of the iTOP system.« less

IEEE 1393 Spaceborne Fiber Optic Data Bus: A Standard Approach to On-Board Payload Data Handling Networks for the AIAA Space Technology Conference and Exposition "Partnering in the 21th Century"

NASA Technical Reports Server (NTRS)

Andrucyk, Dennis J.; Orlando, Fred J.; Chalfant, Charles H.

1999-01-01

The Spaceborne Fiber Optic Data Bus (SFODB) is the next generation in on-board data handling networks. It will do for high speed payloads what SAE 1773 has done for on-board command and telemetry systems. That is, it will significantly reduce the cost of payload development, integration and test through interface standardization. As defined in IEEE 1393, SFODB is a 1 Gb/s, fiber optic network specifically designed to support the real-time, on-board data handling requirements of remote sensing spacecraft. The network is highly reliable, fault tolerant, and capable of withstanding the rigors of launch and the harsh space environment. SFODB achieves this operational and environmental performance while maintaining the small size, light weight, and low power necessary for spaceborne applications. SFODB was developed jointly by DoD and NASA GSFC to meet the on-board data handling needs of Remote Sensing satellites. This jointly funded project produced a complete set of flight transmitters, receivers and protocol ASICS; a complete Development & Evaluation System; and, the IEEE 1393 standard.

Radiation hard programmable delay line for LHCb calorimeter upgrade

NASA Astrophysics Data System (ADS)

Mauricio, J.; Gascón, D.; Vilasís, X.; Picatoste, E.; Machefert, F.; Lefrancois, J.; Duarte, O.; Beigbeder, C.

2014-01-01

This paper describes the implementation of a SPI-programmable clock delay chip based on a Delay Locked Loop (DLL) in order to shift the phase of the LHC clock (25 ns) in steps of 1ns, with less than 5 ps jitter and 23 ps of DNL. The delay lines will be integrated into ICECAL, the LHCb calorimeter front-end analog signal processing ASIC in the near future. The stringent noise requirements on the ASIC imply minimizing the noise contribution of digital components. This is accomplished by implementing the DLL in differential mode. To achieve the required radiation tolerance several techniques are applied: double guard rings between PMOS and NMOS transistors as well as glitch suppressors and TMR Registers. This 5.7 mm2 chip has been implemented in CMOS 0.35 μm technology.

Digital circuits using universal logic gates

NASA Technical Reports Server (NTRS)

Whitaker, Sterling R. (Inventor); Miles, Lowell H. (Inventor); Cameron, Eric G. (Inventor); Donohoe, Gregory W. (Inventor); Gambles, Jody W. (Inventor)

2004-01-01

According to the invention, a digital circuit design embodied in at least one of a structural netlist, a behavioral netlist, a hardware description language netlist, a full-custom ASIC, a semi-custom ASIC, an IP core, an integrated circuit, a hybrid of chips, one or more masks, a FPGA, and a circuit card assembly is disclosed. The digital circuit design includes first and second sub-circuits. The first sub-circuits comprise a first percentage of the digital circuit design and the second sub-circuits comprise a second percentage of the digital circuit design. Each of the second sub-circuits is substantially comprised of one or more kernel circuits. The kernel circuits are comprised of selection circuits. The second percentage is at least 5%. In various embodiments, the second percentage could be at least 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, or 95%.

Protons are a neurotransmitter that regulates synaptic plasticity in the lateral amygdala

PubMed Central

Du, Jianyang; Reznikov, Leah R.; Price, Margaret P.; Zha, Xiang-ming; Lu, Yuan; Moninger, Thomas O.; Wemmie, John A.; Welsh, Michael J.

2014-01-01

Stimulating presynaptic terminals can increase the proton concentration in synapses. Potential receptors for protons are acid-sensing ion channels (ASICs), Na+- and Ca2+-permeable channels that are activated by extracellular acidosis. Those observations suggest that protons might be a neurotransmitter. We found that presynaptic stimulation transiently reduced extracellular pH in the amygdala. The protons activated ASICs in lateral amygdala pyramidal neurons, generating excitatory postsynaptic currents. Moreover, both protons and ASICs were required for synaptic plasticity in lateral amygdala neurons. The results identify protons as a neurotransmitter, and they establish ASICs as the postsynaptic receptor. They also indicate that protons and ASICs are a neurotransmitter/receptor pair critical for amygdala-dependent learning and memory. PMID:24889629

FPGA Based Adaptive Rate and Manifold Pattern Projection for Structured Light 3D Camera System †

PubMed Central

Lee, Sukhan

2018-01-01

The quality of the captured point cloud and the scanning speed of a structured light 3D camera system depend upon their capability of handling the object surface of a large reflectance variation in the trade-off of the required number of patterns to be projected. In this paper, we propose and implement a flexible embedded framework that is capable of triggering the camera single or multiple times for capturing single or multiple projections within a single camera exposure setting. This allows the 3D camera system to synchronize the camera and projector even for miss-matched frame rates such that the system is capable of projecting different types of patterns for different scan speed applications. This makes the system capturing a high quality of 3D point cloud even for the surface of a large reflectance variation while achieving a high scan speed. The proposed framework is implemented on the Field Programmable Gate Array (FPGA), where the camera trigger is adaptively generated in such a way that the position and the number of triggers are automatically determined according to camera exposure settings. In other words, the projection frequency is adaptive to different scanning applications without altering the architecture. In addition, the proposed framework is unique as it does not require any external memory for storage because pattern pixels are generated in real-time, which minimizes the complexity and size of the application-specific integrated circuit (ASIC) design and implementation. PMID:29642506

Wrist sensor for warfighter status monitor

NASA Astrophysics Data System (ADS)

Chen, Wuping

2000-04-01

There is a pressing need to improve human status monitoring in the medical and military communities. The heart rate and breading rate are the most important human vital signs. The current heart rate and breading rate monitors are rather cumbersome, expensive, and usually confined to the intensive care unit or ambulatory setting. These techniques are therefore unavailable to certain applications, such as home care and military applications. The purpose of this work is to develop new methods and new technologies for heart rate and breathing rate monitoring. To accomplish this task, a novel optical acoustic laser sensor (OALS) is characterized and used to generate an optical signal corresponding to human heart beat and breathing. An application specific integrated circuit (ASIC) is developed for this unique compact human status monitor Extensive experimental data analysis and simulation are conducted to investigate robust digital signal processing (DSP) methods. The Gauss-Hermite wavelet transform (GHWT) is utilized as a time-frequency representative technique to provide a method for the detection of the very low frequency heart rate and breathing rate from the large and noisy biomedical lasergram (BLG) signal. A 915MHz RF transceiver provides a reliable wireless link for the monitor to receive commands or transmit the measurement results to a remote commander center. A complete micro-instrument based on the ideas and methods above are developed and tested. The results show that the heart rate and breathing rate could be measured under difficult environmental situations.

Detector Control and Data Acquisition for the Wide-Field Infrared Survey Telescope (WFIRST) with a Custom ASIC

NASA Technical Reports Server (NTRS)

Smith, Brian S.; Loose, Markus; Alkire, Greg; Joshi, Atul; Kelly, Daniel; Siskind, Eric; Rossetti, Dino; Mah, Jonathan; Cheng, Edward; Miko, Laddawan;

Prototype readout system for a multi Mpixels UV single-photon imaging detector capable of space flight operation

NASA Astrophysics Data System (ADS)

Seljak, A.; Cumming, H. S.; Varner, G.; Vallerga, J.; Raffanti, R.; Virta, V.

2018-02-01

Our collaboration works on the development of a large aperture, high resolution, UV single-photon imaging detector, funded through NASA's Strategic Astrophysics Technology (SAT) program. The detector uses a microchannel plate for charge multiplication, and orthogonal cross strip (XS) anodes for charge readout. Our target is to make an advancement in the technology readiness level (TRL), which enables real scale prototypes to be tested for future NASA missions. The baseline detector has an aperture of 50×50 mm and requires 160 low-noise charge-sensitive channels, in order to extrapolate the incoming photon position with a spatial resolution of about 20 μm FWHM. Technologies involving space flight require highly integrated electronic systems operating at very low power. We have designed two ASICs which enable the construction of such readout system. First, a charge sensitive amplifier (CSAv3) ASIC provides an equivalent noise charge (ENC) of around 600 e-, and a baseline gain of 10 mV/fC. The second, a Giga Sample per Second (GSPS) ASIC, called HalfGRAPH, is a 12-bit analog to digital converter. Its architecture is based on waveform sampling capacitor arrays and has about 8 μs of analog storage memory per channel. Both chips encapsulate 16 measurement channels. Using these chips, a small scale prototype readout system has been constructed on a FPGA Mezzanine Board (FMC), equipped with 32 measurement channels for system evaluation. We describe the construction of HalfGRAPH ASIC, detector's readout system concept and obtained results from the prototype system. As part of the space flight qualification, these chips were irradiated with a Cobalt gamma-ray source, to verify functional operation under ionizing radiation exposure.

Improved bandwidth and quantum efficiency in silicon photodiodes using photon-manipulating micro/nanostructures operating in the range of 700-1060 nm

NASA Astrophysics Data System (ADS)

Cansizoglu, Hilal; Gao, Yang; Ghandiparsi, Soroush; Kaya, Ahmet; Perez, Cesar Bartolo; Mayet, Ahmed; Ponizovskaya Devine, Ekaterina; Cansizoglu, Mehmet F.; Yamada, Toshishige; Elrefaie, Aly F.; Wang, Shih-Yuan; Islam, M. Saif

2017-08-01

Nanostructures allow broad spectrum and near-unity optical absorption and contributed to high performance low-cost Si photovoltaic devices. However, the efficiency is only a few percent higher than a conventional Si solar cell with thicker absorption layers. For high speed surface illuminated photodiodes, the thickness of the absorption layer is critical for short transit time and RC time. Recently a CMOS-compatible micro/nanohole silicon (Si) photodiode (PD) with more than 20 Gb/s data rate and with 52 % quantum efficiency (QE) at 850 nm was demonstrated. The achieved QE is over 400% higher than a similar Si PD with the same thickness but without absorption enhancement microstructure holes. The micro/nanoholes increases the QE by photon trapping, slow wave effects and generate a collective assemble of modes that radiate laterally, resulting in absorption enhancement and therefore increase in QE. Such Si PDs can be further designed to enhance the bandwidth (BW) of the PDs by reducing the device capacitance with etched holes in the pin junction. Here we present the BW and QE of Si PDs achievable with micro/nanoholes based on a combination of empirical evidence and device modeling. Higher than 50 Gb/s data rate with greater than 40% QE at 850 nm is conceivable in transceivers designed with such Si PDs that are integrated with photon trapping micro and nanostructures. By monolithic integration with CMOS/BiCMOS integrated circuits such as transimpedance amplifiers, equalizers, limiting amplifiers and other application specific integrated circuits (ASIC), the data rate can be increased to more than 50 Gb/s.

EndoTOFPET-US - A Miniaturised Calorimeter for Endoscopic Time-of-Flight Positron Emission Tomography

NASA Astrophysics Data System (ADS)

Zvolský, Milan; EndoTOFPET-US Collaboration

2015-02-01

In the scope of the EndoTOFPET-US project, a novel multimodal device for Ultrasound (US) Endoscopy and Positron Emission Tomography (PET) is being developed. The project aims at detecting and quantifying morphologic and functional markers and developing new biomarkers for pancreas and prostate oncology. Exploiting the Time-of-Flight (TOF) information of the gamma rays allows for a more sensitive, more precise and lower radiation- dose imaging and intervention on small internal structures. The detection of the gamma rays is realised with the help of scintillator crystals with Silicon Photomultiplier (SiPM) read-out, aiming at a coincidence time resolution of 200 ps and a spatial resolution of ≈ 1 mm. For the endoscopic detector, digital SiPMs are utilised for the first time in an instrument planned for clinical applications. The functionality of the instrument as well as the challenges that accompany the high miniaturisation of the endoscopic detector and the asymmetric and variable geometry of the system, are presented. The demands on the system involve the fields of scintillating crystallography, ultra-fast photon detection, highly integrated electronics, system integration as well as image reconstruction. The single detector components have been fully characterised and are performing up to specifications. Two dedicated ASIC chips have been developed for the project. The first PET images have been acquired with a test setup that consists solely of hardware and software developed within the collaboration and demonstrate that the data acquisition and reconstruction chain is operational. In this talk, the characterisation of the single components and the status of the detector integration and comissioning is presented.

Epithelial Sodium and Acid-Sensing Ion Channels

NASA Astrophysics Data System (ADS)

Kellenberger, Stephan

The epithelial Na+ channel (ENaC) and acid-sensing ion channels (ASICs) are non-voltage-gated Na+ channels that form their own subfamilies within the ENaC/degenerin ion channel family. ASICs are sensors of extracellular pH, and ENaC, whose main function is trans-epithelial Na+ transport, can sense extra- and intra-cellular Na+. In aldosterone-responsive epithelial cells of the kidney, ENaC plays a critical role in the control of sodium balance, blood volume and blood pressure. In airway epithelia, ENaC has a distinct role in controlling fluid reabsorption at the air-liquid interface, thereby determining the rate of mucociliary transport. In taste receptor cells of the tongue, ENaC is involved in salt taste sensation. ASICs have emerged as key sensors for extracellular protons in central and peripheral neurons. Although not all of their physiological and pathological functions are firmly established yet, there is good evidence for a role of ASICs in the brain in learning, expression of fear, and in neurodegeneration after ischaemic stroke. In sensory neurons, ASICs are involved in nociception and mechanosensation. ENaC and ASIC subunits share substantial sequence homology and the conservation of several functional domains. This chapter summarises our current understanding of the physiological functions and of the mechanisms of ion permeation, gating and regulation of ENaC and ASICs.

Parallel design patterns for a low-power, software-defined compressed video encoder

NASA Astrophysics Data System (ADS)

Bruns, Michael W.; Hunt, Martin A.; Prasad, Durga; Gunupudi, Nageswara R.; Sonachalam, Sekar

2011-06-01

Video compression algorithms such as H.264 offer much potential for parallel processing that is not always exploited by the technology of a particular implementation. Consumer mobile encoding devices often achieve real-time performance and low power consumption through parallel processing in Application Specific Integrated Circuit (ASIC) technology, but many other applications require a software-defined encoder. High quality compression features needed for some applications such as 10-bit sample depth or 4:2:2 chroma format often go beyond the capability of a typical consumer electronics device. An application may also need to efficiently combine compression with other functions such as noise reduction, image stabilization, real time clocks, GPS data, mission/ESD/user data or software-defined radio in a low power, field upgradable implementation. Low power, software-defined encoders may be implemented using a massively parallel memory-network processor array with 100 or more cores and distributed memory. The large number of processor elements allow the silicon device to operate more efficiently than conventional DSP or CPU technology. A dataflow programming methodology may be used to express all of the encoding processes including motion compensation, transform and quantization, and entropy coding. This is a declarative programming model in which the parallelism of the compression algorithm is expressed as a hierarchical graph of tasks with message communication. Data parallel and task parallel design patterns are supported without the need for explicit global synchronization control. An example is described of an H.264 encoder developed for a commercially available, massively parallel memorynetwork processor device.

Design Approach and Implementation of Application Specific Instruction Set Processor for SHA-3 BLAKE Algorithm

NASA Astrophysics Data System (ADS)

Zhang, Yuli; Han, Jun; Weng, Xinqian; He, Zhongzhu; Zeng, Xiaoyang

This paper presents an Application Specific Instruction-set Processor (ASIP) for the SHA-3 BLAKE algorithm family by instruction set extensions (ISE) from an RISC (reduced instruction set computer) processor. With a design space exploration for this ASIP to increase the performance and reduce the area cost, we accomplish an efficient hardware and software implementation of BLAKE algorithm. The special instructions and their well-matched hardware function unit improve the calculation of the key section of the algorithm, namely G-functions. Also, relaxing the time constraint of the special function unit can decrease its hardware cost, while keeping the high data throughput of the processor. Evaluation results reveal the ASIP achieves 335Mbps and 176Mbps for BLAKE-256 and BLAKE-512. The extra area cost is only 8.06k equivalent gates. The proposed ASIP outperforms several software approaches on various platforms in cycle per byte. In fact, both high throughput and low hardware cost achieved by this programmable processor are comparable to that of ASIC implementations.

A Low Cost Single Chip VDL Compatible Transceiver ASIC

NASA Technical Reports Server (NTRS)

Becker, Robert

2004-01-01

Recent trends in commercial communications system components have focussed almost exclusively on cellular telephone technology. As many of the traditional sources of receiver components have discontinued non-cellular telephone products, the designers of avionics and other low volume radio applications find themselves increasingly unable to find highly integrated components. This is particularly true for low power, low cost applications which cannot afford the lavish current consumption of the software defined radio approach increasingly taken by certified device manufacturers. In this paper, we describe a low power transceiver chip targeting applications from low VHF to low UHF frequencies typical of avionics systems. The chip encompasses a selectable single or double conversion design for the receiver and a low power IF upconversion transmitter. All local oscillators are synthesized and integrated into the chip. An on-chip I-Q modulator and demodulator provide baseband modulation and demodulation capability allowing the use of low power, fixed point signal processing components for signal demodulation. The goal of this program is to demonstrate a low cost VDL mode-3 transceiver using this chip to receive text weather information sent using 4-slot TDMA with no support for voice. The data will be sent from an experimental ground station. This work is funded by NASA Glenn Research Center.

Coxsackievirus and adenovirus receptor (CAR) mediates trafficking of acid sensing ion channel 3 (ASIC3) via PSD-95.

PubMed

Excoffon, Katherine J D A; Kolawole, Abimbola O; Kusama, Nobuyoshi; Gansemer, Nicholas D; Sharma, Priyanka; Hruska-Hageman, Alesia M; Petroff, Elena; Benson, Christopher J

2012-08-17

We have previously shown that the Coxsackievirus and adenovirus receptor (CAR) can interact with post-synaptic density 95 (PSD-95) and localize PSD-95 to cell-cell junctions. We have also shown that activity of the acid sensing ion channel (ASIC3), a H(+)-gated cation channel that plays a role in mechanosensation and pain signaling, is negatively modulated by PSD-95 through a PDZ-based interaction. We asked whether CAR and ASIC3 simultaneously interact with PSD-95, and if so, whether co-expression of these proteins alters their cellular distribution and localization. Results indicate that CAR and ASIC3 co-immunoprecipitate only when co-expressed with PSD-95. CAR also brings both PSD-95 and ASIC3 to the junctions of heterologous cells. Moreover, CAR rescues PSD-95-mediated inhibition of ASIC3 currents. These data suggest that, in addition to activity as a viral receptor and adhesion molecule, CAR can play a role in trafficking proteins, including ion channels, in a PDZ-based scaffolding complex. Copyright © 2012 Elsevier Inc. All rights reserved.

An ultra low power ECG signal processor design for cardiovascular disease detection.

PubMed

Jain, Sanjeev Kumar; Bhaumik, Basabi

2015-08-01

This paper presents an ultra low power ASIC design based on a new cardiovascular disease diagnostic algorithm. This new algorithm based on forward search is designed for real time ECG signal processing. The algorithm is evaluated for Physionet PTB database from the point of view of cardiovascular disease diagnosis. The failed detection rate of QRS complex peak detection of our algorithm ranges from 0.07% to 0.26% for multi lead ECG signal. The ASIC is designed using 130-nm CMOS low leakage process technology. The area of ASIC is 1.21 mm(2). This ASIC consumes only 96 nW at an operating frequency of 1 kHz with a supply voltage of 0.9 V. Due to ultra low power consumption, our proposed ASIC design is most suitable for energy efficient wearable ECG monitoring devices.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bolotnikov, A. E.; Ackley, K.; Camarda, G. S.

We developed a robust and low-cost array of virtual Frisch-grid CdZnTe (CZT) detectors coupled to a front-end readout ASIC for spectroscopy and imaging of gamma rays. The array operates as a self-reliant detector module. It is comprised of 36 close-packed 6x6x15 mm 3 detectors grouped into 3x3 sub-arrays of 2x2 detectors with the common cathodes. The front-end analog ASIC accommodates up to 36 anode and 9 cathode inputs. Several detector modules can be integrated into a single- or multi-layer unit operating as a Compton or a coded-aperture camera. We present the results from testing two fully assembled modules and readoutmore » electronics. The further enhancement of the arrays’ performance and reduction of their cost are made possible by using position-sensitive virtual Frisch-grid detectors, which allow for accurate corrections of the response of material non-uniformities caused by crystal defects.« less

Optimization and performance of the Robert Stobie Spectrograph Near-InfraRed detector system

NASA Astrophysics Data System (ADS)

Mosby, Gregory; Indahl, Briana; Eggen, Nathan; Wolf, Marsha; Hooper, Eric; Jaehnig, Kurt; Thielman, Don; Burse, Mahesh

2018-01-01

At the University of Wisconsin-Madison, we are building and testing the near-infrared (NIR) spectrograph for the Southern African Large Telescope-RSS-NIR. RSS-NIR will be an enclosed cooled integral field spectrograph. The RSS-NIR detector system uses a HAWAII-2RG (H2RG) HgCdTe detector from Teledyne controlled by the SIDECAR ASIC and an Inter-University Centre for Astronomy and Astrophysics (IUCCA) ISDEC card. We have successfully characterized and optimized the detector system and report on the optimization steps and performance of the system. We have reduced the CDS read noise to ˜20 e- for 200 kHz operation by optimizing ASIC settings. We show an additional factor of 3 reduction of read noise using Fowler sampling techniques and a factor of 2 reduction using up-the-ramp group sampling techniques. We also provide calculations to quantify the conditions for sky-limited observations using these sampling techniques.

Resveratrol attenuates bone cancer pain through regulating the expression levels of ASIC3 and activating cell autophagy.

PubMed

Zhu, Haili; Ding, Jieqiong; Wu, Ji; Liu, Tingting; Liang, Jing; Tang, Qiong; Jiao, Ming

2017-11-01

Bone cancer pain (BCP) is one of the most common pains in patients with malignant cancers. The mechanism underlying BCP is largely unknown. Our previous studies and the increasing evidence both have shown that acid-sensing ion channels 3 (ASIC3) is an important protein in the pathological pain state in some pain models. We hypothesized that the expression change of ASIC3 might be one of the factors related to BCP. In this study, we established the BCP model through intrathecally injecting rat mammary gland carcinoma cells (MRMT-1) into the left tibia of Sprague-Dawley female rats, and found that the BCP rats showed bone destruction, increased mechanical pain sensitivities and up-regulated ASIC3 protein expression levels in L4-L6 dorsal root ganglion. Then, resveratrol, which was intraperitoneally injected into the BCP rats on post-operative Day 21, dose-dependently increased the paw withdrawal threshold of BCP rats, reversed the pain behavior, and had an antinociceptive effect on BCP rats. In ASIC3-transfected SH-SY5Y cells, the ASIC3 protein expression levels were regulated by resveratrol in a dose- and time-dependent manner. Meanwhile, resveratrol also had an antinociceptive effect in ASIC3-mediated pain rat model. Furthermore, resveratrol also enhanced the phosphorylation of AMPK, SIRT1, and LC3-II levels in ASIC3-transfected SH-SY5Y cells, indicating that resveratrol could activate the AMPK-SIRT1-autophagy signal pathway in ASIC3-transfected SH-SY5Y cells. In BCP rats, SIRT1 and LC3-II were also down-regulated. These findings provide new evidence for the use of resveratrol as a therapeutic treatment during BCP states. © The Author 2017. Published by Oxford University Press on behalf of the Institute of Biochemistry and Cell Biology, Shanghai Institutes for Biological Sciences, Chinese Academy of Sciences. All rights reserved. For permissions, please e-mail: journals.permissions@oup.com.

A low-latency optical switch architecture using integrated μm SOI-based contention resolution and switching

NASA Astrophysics Data System (ADS)

Mourgias-Alexandris, G.; Moralis-Pegios, M.; Terzenidis, N.; Cherchi, M.; Harjanne, M.; Aalto, T.; Vyrsokinos, K.; Pleros, N.

2018-02-01

The urgent need for high-bandwidth and high-port connectivity in Data Centers has boosted the deployment of optoelectronic packet switches towards bringing high data-rate optics closer to the ASIC, realizing optical transceiver functions directly at the ASIC package for high-rate, low-energy and low-latency interconnects. Even though optics can offer a broad range of low-energy integrated switch fabrics for replacing electronic switches and seamlessly interface with the optical I/Os, the use of energy- and latency-consuming electronic SerDes continues to be a necessity, mainly dictated by the absence of integrated and reliable optical buffering solutions. SerDes undertakes the role of optimally synergizing the lower-speed electronic buffers with the incoming and outgoing optical streams, suggesting that a SerDes-released chip-scale optical switch fabric can be only realized in case all necessary functions including contention resolution and switching can be implemented on a common photonic integration platform. In this paper, we demonstrate experimentally a hybrid Broadcast-and-Select (BS) / wavelength routed optical switch that performs both the optical buffering and switching functions with μm-scale Silicon-integrated building blocks. Optical buffering is carried out in a silicon-integrated variable delay line bank with a record-high on-chip delay/footprint efficiency of 2.6ns/mm2 and up to 17.2 nsec delay capability, while switching is executed via a BS design and a silicon-integrated echelle grating, assisted by SOA-MZI wavelength conversion stages and controlled by a FPGA header processing module. The switch has been experimentally validated in a 3x3 arrangement with 10Gb/s NRZ optical data packets, demonstrating error-free switching operation with a power penalty of <5dB.

Correlations between properties and applications of the CVD amorphous silicon carbide films

NASA Astrophysics Data System (ADS)

Kleps, Irina; Angelescu, Anca

2001-12-01

The aim of this paper is to emphasise the correlation between film preparation conditions, film properties and their applications. Low pressure chemical vapour deposition amorphous silicon carbide (a-SiC) and silicon carbonitride (SiCN) films obtained from liquid precursors have different structure and composition depending on deposition conditions. Thus, the films deposited under kinetic working conditions reveal a stable structure and composition. Deposition at moderate temperature leads to stoichiometric SiC, while the films deposited at high temperatures have a composition closer to Si 1- xC x, with x=0.75. These films form a very reactive interface with metallic layers. The films realised under kinetic working regime can be used in Si membrane fabrication process or as coating films for field emission applications. SiC layers field emission properties were investigated; the field emission current density of the a-SiC/Si structures was 2.4 mA/cm 2 at 25 V/μm. An Si membrane technology based on moderate temperatures (770-850 °C) a-SiC etching mask is presented.

Implementation and Performance of GaAs Digital Signal Processing ASICs

NASA Technical Reports Server (NTRS)

Whitaker, William D.; Buchanan, Jeffrey R.; Burke, Gary R.; Chow, Terrance W.; Graham, J. Scott; Kowalski, James E.; Lam, Barbara; Siavoshi, Fardad; Thompson, Matthew S.; Johnson, Robert A.

1993-01-01

The feasibility of performing high speed digital signal processing in GaAs gate array technology has been demonstrated with the successful implementation of a VLSI communications chip set for NASA's Deep Space Network. This paper describes the techniques developed to solve some of the technology and implementation problems associated with large scale integration of GaAs gate arrays.

Terahertz Radiometer for Outer Planet and Moon Atmospheres (TROPA)

NASA Technical Reports Server (NTRS)

Schlecht, E. T.; Jamnejad, V.; Jarnot, R. F.; Raffanti, R.; Lin, R.

2012-01-01

We are developing a prototype instrument platform to demonstrate the feasibility of a wideband spectrometer for planetary applications under a three-year NASA research program. This development focuses on three specific areas needing advancement. First, the terahertz portion consists of an optical bench with dual heterodyne Schottky-mixer based receivers, one for each band. The beams entering the horns of the two receivers are de-multiplexed from the input beam by a polarizing beam splitter. The blocks containing the 560 and 1200 GHz mixer are more highly integrated than previous space instruments to reduce mass and volume. The receivers take a fundamental pump frequency near 30 GHz and multiply up to the submillimeter range. Second, a rapid-tuning, low-phase noise, and low-power 33 GHz range LO synthesizer is being prototyped. The low phase noise requirement is needed because of the factor of 36 multiplication to reach 1200 GHz, giving a requirement that the integrated phase noise from 100 kHz up be less than 0.6 degrees. The synthesizer will require about 6 watts. Finally, we are developing an advanced polyphase filter back-end spectrum analyzer with a bandwidth of 750 MHz, and power consumption of about 3 Watts and 4096 channels. This system is based on a simple three-chip architecture, having a commercial 1.5 GS/s analog-to-digital converter, an ASIC to do the filtering and an advanced FPGA for data processing and control.

15 CFR Supplement No. 5 to Part 742 - Encryption Registration

Code of Federal Regulations, 2013 CFR

2013-01-01

... registration, i.e., the information as described in this Supplement, submitted as a support documentation... (h) Smartcards or other identity management (i) Computer or network forensics (j) Software (i) Operating systems (ii) Applications (k) Toolkits/ASICs/components (l) Information security including secure...

15 CFR Supplement No. 5 to Part 742 - Encryption Registration

Code of Federal Regulations, 2011 CFR

2011-01-01

... registration, i.e., the information as described in this Supplement, submitted as a support documentation... (h) Smartcards or other identity management (i) Computer or network forensics (j) Software (i) Operating systems (ii) Applications (k) Toolkits/ASICs/components (l) Information security including secure...

15 CFR Supplement No. 5 to Part 742 - Encryption Registration

Code of Federal Regulations, 2014 CFR

2014-01-01

... registration, i.e., the information as described in this Supplement, submitted as a support documentation... (h) Smartcards or other identity management (i) Computer or network forensics (j) Software (i) Operating systems (ii) Applications (k) Toolkits/ASICs/components (l) Information security including secure...

15 CFR Supplement No. 5 to Part 742 - Encryption Registration

Code of Federal Regulations, 2012 CFR

2012-01-01

... registration, i.e., the information as described in this Supplement, submitted as a support documentation... (h) Smartcards or other identity management (i) Computer or network forensics (j) Software (i) Operating systems (ii) Applications (k) Toolkits/ASICs/components (l) Information security including secure...

Parallel processing architecture for H.264 deblocking filter on multi-core platforms

NASA Astrophysics Data System (ADS)

Prasad, Durga P.; Sonachalam, Sekar; Kunchamwar, Mangesh K.; Gunupudi, Nageswara Rao

2012-03-01

Massively parallel computing (multi-core) chips offer outstanding new solutions that satisfy the increasing demand for high resolution and high quality video compression technologies such as H.264. Such solutions not only provide exceptional quality but also efficiency, low power, and low latency, previously unattainable in software based designs. While custom hardware and Application Specific Integrated Circuit (ASIC) technologies may achieve lowlatency, low power, and real-time performance in some consumer devices, many applications require a flexible and scalable software-defined solution. The deblocking filter in H.264 encoder/decoder poses difficult implementation challenges because of heavy data dependencies and the conditional nature of the computations. Deblocking filter implementations tend to be fixed and difficult to reconfigure for different needs. The ability to scale up for higher quality requirements such as 10-bit pixel depth or a 4:2:2 chroma format often reduces the throughput of a parallel architecture designed for lower feature set. A scalable architecture for deblocking filtering, created with a massively parallel processor based solution, means that the same encoder or decoder will be deployed in a variety of applications, at different video resolutions, for different power requirements, and at higher bit-depths and better color sub sampling patterns like YUV, 4:2:2, or 4:4:4 formats. Low power, software-defined encoders/decoders may be implemented using a massively parallel processor array, like that found in HyperX technology, with 100 or more cores and distributed memory. The large number of processor elements allows the silicon device to operate more efficiently than conventional DSP or CPU technology. This software programing model for massively parallel processors offers a flexible implementation and a power efficiency close to that of ASIC solutions. This work describes a scalable parallel architecture for an H.264 compliant deblocking filter for multi core platforms such as HyperX technology. Parallel techniques such as parallel processing of independent macroblocks, sub blocks, and pixel row level are examined in this work. The deblocking architecture consists of a basic cell called deblocking filter unit (DFU) and dependent data buffer manager (DFM). The DFU can be used in several instances, catering to different performance needs the DFM serves the data required for the different number of DFUs, and also manages all the neighboring data required for future data processing of DFUs. This approach achieves the scalability, flexibility, and performance excellence required in deblocking filters.

A multichannel integrated circuit for electrical recording of neural activity, with independent channel programmability.

PubMed

Mora Lopez, Carolina; Prodanov, Dimiter; Braeken, Dries; Gligorijevic, Ivan; Eberle, Wolfgang; Bartic, Carmen; Puers, Robert; Gielen, Georges

2012-04-01

Since a few decades, micro-fabricated neural probes are being used, together with microelectronic interfaces, to get more insight in the activity of neuronal networks. The need for higher temporal and spatial recording resolutions imposes new challenges on the design of integrated neural interfaces with respect to power consumption, data handling and versatility. In this paper, we present an integrated acquisition system for in vitro and in vivo recording of neural activity. The ASIC consists of 16 low-noise, fully-differential input channels with independent programmability of its amplification (from 100 to 6000 V/V) and filtering (1-6000 Hz range) capabilities. Each channel is AC-coupled and implements a fourth-order band-pass filter in order to steeply attenuate out-of-band noise and DC input offsets. The system achieves an input-referred noise density of 37 nV/√Hz, a NEF of 5.1, a CMRR > 60 dB, a THD < 1% and a sampling rate of 30 kS/s per channel, while consuming a maximum of 70 μA per channel from a single 3.3 V. The ASIC was implemented in a 0.35 μm CMOS technology and has a total area of 5.6 × 4.5 mm². The recording system was successfully validated in in vitro and in vivo experiments, achieving simultaneous multichannel recordings of cell activity with satisfactory signal-to-noise ratios.

Missile signal processing common computer architecture for rapid technology upgrade

NASA Astrophysics Data System (ADS)

Rabinkin, Daniel V.; Rutledge, Edward; Monticciolo, Paul

2004-10-01

Interceptor missiles process IR images to locate an intended target and guide the interceptor towards it. Signal processing requirements have increased as the sensor bandwidth increases and interceptors operate against more sophisticated targets. A typical interceptor signal processing chain is comprised of two parts. Front-end video processing operates on all pixels of the image and performs such operations as non-uniformity correction (NUC), image stabilization, frame integration and detection. Back-end target processing, which tracks and classifies targets detected in the image, performs such algorithms as Kalman tracking, spectral feature extraction and target discrimination. In the past, video processing was implemented using ASIC components or FPGAs because computation requirements exceeded the throughput of general-purpose processors. Target processing was performed using hybrid architectures that included ASICs, DSPs and general-purpose processors. The resulting systems tended to be function-specific, and required custom software development. They were developed using non-integrated toolsets and test equipment was developed along with the processor platform. The lifespan of a system utilizing the signal processing platform often spans decades, while the specialized nature of processor hardware and software makes it difficult and costly to upgrade. As a result, the signal processing systems often run on outdated technology, algorithms are difficult to update, and system effectiveness is impaired by the inability to rapidly respond to new threats. A new design approach is made possible three developments; Moore's Law - driven improvement in computational throughput; a newly introduced vector computing capability in general purpose processors; and a modern set of open interface software standards. Today's multiprocessor commercial-off-the-shelf (COTS) platforms have sufficient throughput to support interceptor signal processing requirements. This application may be programmed under existing real-time operating systems using parallel processing software libraries, resulting in highly portable code that can be rapidly migrated to new platforms as processor technology evolves. Use of standardized development tools and 3rd party software upgrades are enabled as well as rapid upgrade of processing components as improved algorithms are developed. The resulting weapon system will have a superior processing capability over a custom approach at the time of deployment as a result of a shorter development cycles and use of newer technology. The signal processing computer may be upgraded over the lifecycle of the weapon system, and can migrate between weapon system variants enabled by modification simplicity. This paper presents a reference design using the new approach that utilizes an Altivec PowerPC parallel COTS platform. It uses a VxWorks-based real-time operating system (RTOS), and application code developed using an efficient parallel vector library (PVL). A quantification of computing requirements and demonstration of interceptor algorithm operating on this real-time platform are provided.

An Offload NIC for NASA, NLR, and Grid Computing

NASA Technical Reports Server (NTRS)

Awrach, James

2013-01-01

This work addresses distributed data management and access dynamically configurable high-speed access to data distributed and shared over wide-area high-speed network environments. An offload engine NIC (network interface card) is proposed that scales at nX10-Gbps increments through 100-Gbps full duplex. The Globus de facto standard was used in projects requiring secure, robust, high-speed bulk data transport. Novel extension mechanisms were derived that will combine these technologies for use by GridFTP, bandwidth management resources, and host CPU (central processing unit) acceleration. The result will be wire-rate encrypted Globus grid data transactions through offload for splintering, encryption, and compression. As the need for greater network bandwidth increases, there is an inherent need for faster CPUs. The best way to accelerate CPUs is through a network acceleration engine. Grid computing data transfers for the Globus tool set did not have wire-rate encryption or compression. Existing technology cannot keep pace with the greater bandwidths of backplane and network connections. Present offload engines with ports to Ethernet are 32 to 40 Gbps f-d at best. The best of ultra-high-speed offload engines use expensive ASICs (application specific integrated circuits) or NPUs (network processing units). The present state of the art also includes bonding and the use of multiple NICs that are also in the planning stages for future portability to ASICs and software to accommodate data rates at 100 Gbps. The remaining industry solutions are for carrier-grade equipment manufacturers, with costly line cards having multiples of 10-Gbps ports, or 100-Gbps ports such as CFP modules that interface to costly ASICs and related circuitry. All of the existing solutions vary in configuration based on requirements of the host, motherboard, or carriergrade equipment. The purpose of the innovation is to eliminate data bottlenecks within cluster, grid, and cloud computing systems, and to add several more capabilities while reducing space consumption and cost. Provisions were designed for interoperability with systems used in the NASA HEC (High-End Computing) program. The new acceleration engine consists of state-ofthe- art FPGA (field-programmable gate array) core IP, C, and Verilog code; novel communication protocol; and extensions to the Globus structure. The engine provides the functions of network acceleration, encryption, compression, packet-ordering, and security added to Globus grid or for cloud data transfer. This system is scalable in nX10-Gbps increments through 100-Gbps f-d. It can be interfaced to industry-standard system-side or network-side devices or core IP in increments of 10 GigE, scaling to provide IEEE 40/100 GigE compliance.

A programmable time alignment scheme for detector signals from the upgraded muon spectrometer at the ATLAS experiment

NASA Astrophysics Data System (ADS)

Wang, Jinhong; Guan, Liang; Chapman, J.; Zhou, Bing; Zhu, Junjie

2017-11-01

We present a programmable time alignment scheme used in an ASIC for the ATLAS forward muon trigger development. The scheme utilizes regenerated clocks with programmable phases to compensate for the timing offsets introduced by different detector trace lengths. Each ASIC used in the design has 104 input channels with delay compensation circuitry providing steps of ∼3 ns and a full range of 25 ns for each channel. Detailed implementation of the scheme including majority logic to suppress single-event effects is presented. The scheme is flexible and fully synthesizable. The approach is adaptable to other applications with similar phase shifting requirements. In addition, the design is resource efficient and is suitable for cost-effective digital implementation with a large number of channels.

Fast particles identification in programmable form at level-0 trigger by means of the 3D-Flow system

DOE Office of Scientific and Technical Information (OSTI.GOV)

Crosetto, Dario B.

1998-10-30

The 3D-Flow Processor system is a new, technology-independent concept in very fast, real-time system architectures. Based on either an FPGA or an ASIC implementation, it can address, in a fully programmable manner, applications where commercially available processors would fail because of throughput requirements. Possible applications include filtering-algorithms (pattern recognition) from the input of multiple sensors, as well as moving any input validated by these filtering-algorithms to a single output channel. Both operations can easily be implemented on a 3D-Flow system to achieve a real-time processing system with a very short lag time. This system can be built either with off-the-shelfmore » FPGAs or, for higher data rates, with CMOS chips containing 4 to 16 processors each. The basic building block of the system, a 3D-Flow processor, has been successfully designed in VHDL code written in ''Generic HDL'' (mostly made of reusable blocks that are synthesizable in different technologies, or FPGAs), to produce a netlist for a four-processor ASIC featuring 0.35 micron CBA (Ceil Base Array) technology at 3.3 Volts, 884 mW power dissipation at 60 MHz and 63.75 mm sq. die size. The same VHDL code has been targeted to three FPGA manufacturers (Altera EPF10K250A, ORCA-Lucent Technologies 0R3T165 and Xilinx XCV1000). A complete set of software tools, the 3D-Flow System Manager, equally applicable to ASIC or FPGA implementations, has been produced to provide full system simulation, application development, real-time monitoring, and run-time fault recovery. Today's technology can accommodate 16 processors per chip in a medium size die, at a cost per processor of less than $5 based on the current silicon die/size technology cost.« less

Development of a Low-cost, FPGA-based, Delay Line Particle Detector for Satellite and Sounding Rocket Applications

NASA Astrophysics Data System (ADS)

Harrington, M.; Kujawski, J. T.; Adrian, M. L.; Weatherwax, A. T.

2013-12-01

Electrons are, by definition, a fundamental, chemical and electromagnetic constituent of any plasma. This is especially true within the partially ionized plasmas of Earth's ionosphere where electrons are a critical component of a vast array of plasma processes. Siena College is working on a novel method of processing information from electron spectrometer anodes using delay line techniques and inexpensive COTS electronics to track the movement of high-energy particles. Electron spectrometers use a variety of techniques to determine where an amplified electron cloud falls onto a collecting surface. One traditional method divides the collecting surface into sectors and uses a single detector for each sector. However, as the angular and spatial resolution increases, so does the number of detectors, increasing power consumption, cost, size, and weight of the system. An alternative approach is to connect each sector with a delay line built within the PCB material which is shielded from cross talk by a flooded ground plane. Only one pair of detectors (e.g., one at each end of the chain) are needed with the delay line technique which is different from traditional delay line detectors which use either Application Specific Integrated Circuits (ASICs) or very fast clocks. In this paper, we report on the implementation and testing of a delay line detector using a low-cost Xilinx FPGA and a thirty-two sector delay system. This Delay Line Detector has potential satellite and rocket flight applications due to its low cost, small size and power efficiency

Knockout of the ASIC2 channel in mice does not impair cutaneous mechanosensation, visceral mechanonociception and hearing

PubMed Central

Roza, Carolina; Puel, Jean-Luc; Kress, Michaela; Baron, Anne; Diochot, Sylvie; Lazdunski, Michel; Waldmann, Rainer

2004-01-01

Mechanosensitive cation channels are thought to be crucial for different aspects of mechanoperception, such as hearing and touch sensation. In the nematode C. elegans, the degenerins MEC-4 and MEC-10 are involved in mechanosensation and were proposed to form mechanosensitive cation channels. Mammalian degenerin homologues, the H+-gated ASIC channels, are expressed in sensory neurones and are therefore interesting candidates for mammalian mechanosensors. We investigated the effect of an ASIC2 gene knockout in mice on hearing and on cutaneous mechanosensation and visceral mechanonociception. However, our data do not support a role of ASIC2 in those facets of mechanoperception. PMID:15169849

Energy efficiency analysis and implementation of AES on an FPGA

NASA Astrophysics Data System (ADS)

Kenney, David

The Advanced Encryption Standard (AES) was developed by Joan Daemen and Vincent Rjimen and endorsed by the National Institute of Standards and Technology in 2001. It was designed to replace the aging Data Encryption Standard (DES) and be useful for a wide range of applications with varying throughput, area, power dissipation and energy consumption requirements. Field Programmable Gate Arrays (FPGAs) are flexible and reconfigurable integrated circuits that are useful for many different applications including the implementation of AES. Though they are highly flexible, FPGAs are often less efficient than Application Specific Integrated Circuits (ASICs); they tend to operate slower, take up more space and dissipate more power. There have been many FPGA AES implementations that focus on obtaining high throughput or low area usage, but very little research done in the area of low power or energy efficient FPGA based AES; in fact, it is rare for estimates on power dissipation to be made at all. This thesis presents a methodology to evaluate the energy efficiency of FPGA based AES designs and proposes a novel FPGA AES implementation which is highly flexible and energy efficient. The proposed methodology is implemented as part of a novel scripting tool, the AES Energy Analyzer, which is able to fully characterize the power dissipation and energy efficiency of FPGA based AES designs. Additionally, this thesis introduces a new FPGA power reduction technique called Opportunistic Combinational Operand Gating (OCOG) which is used in the proposed energy efficient implementation. The AES Energy Analyzer was able to estimate the power dissipation and energy efficiency of the proposed AES design during its most commonly performed operations. It was found that the proposed implementation consumes less energy per operation than any previous FPGA based AES implementations that included power estimations. Finally, the use of Opportunistic Combinational Operand Gating on an AES cipher was found to reduce its dynamic power consumption by up to 17% when compared to an identical design that did not employ the technique.

The readout electronics for Plastic Scintillator Detector of DAMPE

NASA Astrophysics Data System (ADS)

Kong, Jie; Yang, Haibo; Zhao, Hongyun; Su, Hong; Sun, Zhiyu; Yu, Yuhong; JingZhe, Zhang; Wang, XiaoHui; Liu, Jie; Xiao, Guoqing; Ma, Xinwen

2016-07-01

The Dark Matter Particle Explorer (DAMPE) satellite, which launched in December 2015, is designed to find the evidence of the existence of dark matter particles in the universe via the detection of the high-energy electrons and gamma-ray particles produced possibly by the annihilation of dark matter particles. Plastic Scintillator Detector (PSD) is one of major part of the satellite payload, which is comprised of a crossed pair of layers with 41 plastic scintillator-strips, each read out from both ends by the same Hamamatsu R4443MOD2 photo-multiplier tubes (PMTs). In order to extend linear dynamic range of detector, PMTs read out each plastic scintillator-strip separately with two dynode pickoffs. Therefore, the readout electronics system comprises of four Front-end boards to receive the pulses from 328 PMTs and implement charge measurement, which is based on the Application Specific Integrated Circuit (ASIC) chip VA160, 16 bits ADC and FPGA. The electronics of the detector has been designed following stringent requirements on mechanical and thermal stability, power consumption, radiation hardness and double redundancy. Various experiments are designed and implemented to check the performance of the electronics, some excellent results has been achieved.According to experimental results analysis, it is proved that the readout electronics works well.

3D track reconstruction capability of a silicon hybrid active pixel detector

NASA Astrophysics Data System (ADS)

Bergmann, Benedikt; Pichotka, Martin; Pospisil, Stanislav; Vycpalek, Jiri; Burian, Petr; Broulim, Pavel; Jakubek, Jan

2017-06-01

Timepix3 detectors are the latest generation of hybrid active pixel detectors of the Medipix/Timepix family. Such detectors consist of an active sensor layer which is connected to the readout ASIC (application specific integrated circuit), segmenting the detector into a square matrix of 256 × 256 pixels (pixel pitch 55 μm). Particles interacting in the active sensor material create charge carriers, which drift towards the pixelated electrode, where they are collected. In each pixel, the time of the interaction (time resolution 1.56 ns) and the amount of created charge carriers are measured. Such a device was employed in an experiment in a 120 GeV/c pion beam. It is demonstrated, how the drift time information can be used for "4D" particle tracking, with the three spatial dimensions and the energy losses along the particle trajectory (dE/dx). Since the coordinates in the detector plane are given by the pixelation ( x, y), the x- and y-resolution is determined by the pixel pitch (55 μm). A z-resolution of 50.4 μm could be achieved (for a 500 μm thick silicon sensor at 130 V bias), whereby the drift time model independent z-resolution was found to be 28.5 μm.

Silicon ball grid array chip carrier

DOEpatents

Palmer, David W.; Gassman, Richard A.; Chu, Dahwey

2000-01-01

A ball-grid-array integrated circuit (IC) chip carrier formed from a silicon substrate is disclosed. The silicon ball-grid-array chip carrier is of particular use with ICs having peripheral bond pads which can be reconfigured to a ball-grid-array. The use of a semiconductor substrate such as silicon for forming the ball-grid-array chip carrier allows the chip carrier to be fabricated on an IC process line with, at least in part, standard IC processes. Additionally, the silicon chip carrier can include components such as transistors, resistors, capacitors, inductors and sensors to form a "smart" chip carrier which can provide added functionality and testability to one or more ICs mounted on the chip carrier. Types of functionality that can be provided on the "smart" chip carrier include boundary-scan cells, built-in test structures, signal conditioning circuitry, power conditioning circuitry, and a reconfiguration capability. The "smart" chip carrier can also be used to form specialized or application-specific ICs (ASICs) from conventional ICs. Types of sensors that can be included on the silicon ball-grid-array chip carrier include temperature sensors, pressure sensors, stress sensors, inertia or acceleration sensors, and/or chemical sensors. These sensors can be fabricated by IC processes and can include microelectromechanical (MEM) devices.

A Low Cost VLSI Architecture for Spike Sorting Based on Feature Extraction with Peak Search.

PubMed

Chang, Yuan-Jyun; Hwang, Wen-Jyi; Chen, Chih-Chang

2016-12-07

The goal of this paper is to present a novel VLSI architecture for spike sorting with high classification accuracy, low area costs and low power consumption. A novel feature extraction algorithm with low computational complexities is proposed for the design of the architecture. In the feature extraction algorithm, a spike is separated into two portions based on its peak value. The area of each portion is then used as a feature. The algorithm is simple to implement and less susceptible to noise interference. Based on the algorithm, a novel architecture capable of identifying peak values and computing spike areas concurrently is proposed. To further accelerate the computation, a spike can be divided into a number of segments for the local feature computation. The local features are subsequently merged with the global ones by a simple hardware circuit. The architecture can also be easily operated in conjunction with the circuits for commonly-used spike detection algorithms, such as the Non-linear Energy Operator (NEO). The architecture has been implemented by an Application-Specific Integrated Circuit (ASIC) with 90-nm technology. Comparisons to the existing works show that the proposed architecture is well suited for real-time multi-channel spike detection and feature extraction requiring low hardware area costs, low power consumption and high classification accuracy.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lecomte, Roger; Arpin, Louis; Beaudoin, Jean-Franç

Purpose: LabPET II is a new generation APD-based PET scanner designed to achieve sub-mm spatial resolution using truly pixelated detectors and highly integrated parallel front-end processing electronics. Methods: The basic element uses a 4×8 array of 1.12×1.12 mm{sup 2} Lu{sub 1.9}Y{sub 0.1}SiO{sub 5}:Ce (LYSO) scintillator pixels with one-to-one coupling to a 4×8 pixelated monolithic APD array mounted on a ceramic carrier. Four detector arrays are mounted on a daughter board carrying two flip-chip, 64-channel, mixed-signal, application-specific integrated circuits (ASIC) on the backside interfacing to two detector arrays each. Fully parallel signal processing was implemented in silico by encoding time andmore » energy information using a dual-threshold Time-over-Threshold (ToT) scheme. The self-contained 128-channel detector module was designed as a generic component for ultra-high resolution PET imaging of small to medium-size animals. Results: Energy and timing performance were optimized by carefully setting ToT thresholds to minimize the noise/slope ratio. ToT spectra clearly show resolved 511 keV photopeak and Compton edge with ToT resolution well below 10%. After correction for nonlinear ToT response, energy resolution is typically 24±2% FWHM. Coincidence time resolution between opposing 128-channel modules is below 4 ns FWHM. Initial imaging results demonstrate that 0.8 mm hot spots of a Derenzo phantom can be resolved. Conclusion: A new generation PET scanner featuring truly pixelated detectors was developed and shown to achieve a spatial resolution approaching the physical limit of PET. Future plans are to integrate a small-bore dedicated mouse version of the scanner within a PET/CT platform.« less

MicroCT with energy-resolved photon-counting detectors

PubMed Central

Wang, X; Meier, D; Mikkelsen, S; Maehlum, G E; Wagenaar, D J; Tsui, BMW; Patt, B E; Frey, E C

2011-01-01

The goal of this paper was to investigate the benefits that could be realistically achieved on a microCT imaging system with an energy-resolved photon-counting x-ray detector. To this end, we built and evaluated a prototype microCT system based on such a detector. The detector is based on cadmium telluride (CdTe) radiation sensors and application-specific integrated circuit (ASIC) readouts. Each detector pixel can simultaneously count x-ray photons above six energy thresholds, providing the capability for energy-selective x-ray imaging. We tested the spectroscopic performance of the system using polychromatic x-ray radiation and various filtering materials with Kabsorption edges. Tomographic images were then acquired of a cylindrical PMMA phantom containing holes filled with various materials. Results were also compared with those acquired using an intensity-integrating x-ray detector and single-energy (i.e. non-energy-selective) CT. This paper describes the functionality and performance of the system, and presents preliminary spectroscopic and tomographic results. The spectroscopic experiments showed that the energy-resolved photon-counting detector was capable of measuring energy spectra from polychromatic sources like a standard x-ray tube, and resolving absorption edges present in the energy range used for imaging. However, the spectral quality was degraded by spectral distortions resulting from degrading factors, including finite energy resolution and charge sharing. We developed a simple charge-sharing model to reproduce these distortions. The tomographic experiments showed that the availability of multiple energy thresholds in the photon-counting detector allowed us to simultaneously measure target-to-background contrasts in different energy ranges. Compared with single-energy CT with an integrating detector, this feature was especially useful to improve differentiation of materials with different attenuation coefficient energy dependences. PMID:21464527

MicroCT with energy-resolved photon-counting detectors.

PubMed

Wang, X; Meier, D; Mikkelsen, S; Maehlum, G E; Wagenaar, D J; Tsui, B M W; Patt, B E; Frey, E C

2011-05-07

The goal of this paper was to investigate the benefits that could be realistically achieved on a microCT imaging system with an energy-resolved photon-counting x-ray detector. To this end, we built and evaluated a prototype microCT system based on such a detector. The detector is based on cadmium telluride (CdTe) radiation sensors and application-specific integrated circuit (ASIC) readouts. Each detector pixel can simultaneously count x-ray photons above six energy thresholds, providing the capability for energy-selective x-ray imaging. We tested the spectroscopic performance of the system using polychromatic x-ray radiation and various filtering materials with K-absorption edges. Tomographic images were then acquired of a cylindrical PMMA phantom containing holes filled with various materials. Results were also compared with those acquired using an intensity-integrating x-ray detector and single-energy (i.e. non-energy-selective) CT. This paper describes the functionality and performance of the system, and presents preliminary spectroscopic and tomographic results. The spectroscopic experiments showed that the energy-resolved photon-counting detector was capable of measuring energy spectra from polychromatic sources like a standard x-ray tube, and resolving absorption edges present in the energy range used for imaging. However, the spectral quality was degraded by spectral distortions resulting from degrading factors, including finite energy resolution and charge sharing. We developed a simple charge-sharing model to reproduce these distortions. The tomographic experiments showed that the availability of multiple energy thresholds in the photon-counting detector allowed us to simultaneously measure target-to-background contrasts in different energy ranges. Compared with single-energy CT with an integrating detector, this feature was especially useful to improve differentiation of materials with different attenuation coefficient energy dependences.

Centering a DDR Strobe in the Middle of a Data Packet

NASA Technical Reports Server (NTRS)

Johnson, Michael; Nelson, Dave; Seefeldt, James; Roper, Weston; Passow, Craig

2014-01-01

The Orion CEV Northstar ASIC (application- specific integrated circuit) project required a DDR (double data rate) memory bus driver/receiver (DDR PHY block) to interface with external DDR memory. The DDR interface (JESD79C) is based on a source synchronous strobe (DQS\\) that is sent along with each packet of data (DQ). New data is provided concurrently with each edge of strobe and is sent irregularly. In order to capture this data, the strobe needs to be delayed and used to latch the data into a register. A circuit solves the need for training a DDR PRY block by incorporating a PVT-compensated delay element in the strobe path. This circuit takes an external reference clock signal and uses the regular clock to calibrate a known delay through a data path. The compensated delay DQS signal is then used to capture the DQ data in a normal register. This register structure can be configured as a FIFO (first in first out), in order to transfer data from the DDR domain to the system clock domain. This design is different in that it does not rely upon the need for training the system response, nor does it use a PLL (phase locked loop) or a DLL (delay locked loop) to provide an offset of the strobe signal. The circuit is created using standard ASIC building blocks, plus the PVT (process, voltage, and temperature) compensated delay line. The design uses a globally available system clock as a reference, alleviating the need to operate synchronously with the remote memory. The reference clock conditions the PVT compensated delay line to provide a pre-determined amount of delay to any data signal that passes through this delay line. The delay line is programmed in degrees of offset, so that one could think of the clock period representing 360deg of delay. In an ideal environment, delaying the strobe 1/4 of a clock cycle (90deg) would place the strobe in the middle of the data packet. This delayed strobe can then be used to clock the data into a register, satisfying setup and hold requirements of the system.

Cross strip anode readouts for microchannel plate detectors: developing flight qualified prototypes

NASA Astrophysics Data System (ADS)

Vallerga, John; Cooney, M.; Raffanti, R.; Varner, G.; Siegmund, O.; McPhate, J. B.; Tremsin, A.

2014-01-01

Photon counting microchannel plate (MCP) imagers have been the detector of choice for most UV astronomical missions over the last two decades (eg. EUVE, FUSE, COS on Hubble etc.). Over this duration, improvements in the MCP laboratory readout technology have resulted in better spatial resolution (x10), temporal resolution (x 1000) and output event rate (x100), all the while operating at lower gain (x 10) resulting in lower high voltage requirements and longer MCP lifetimes. One such technology is the parallel cross strip (PXS) readout. The PXS anode is a set of orthogonal conducting strips (80 x 80), typically spaced at a 635 micron pitch onto which charge clouds from MCP amplified events land. Each strip has its own charge sensitive amplifier that is sampled continuously by a dedicated analog to digital (ADC) converter at 50MHz. All of the 160 ADC digital output lines are fed into a field programmable gate array (FGPA) which can detect charge events landing on the strips, measure the peak amplitudes of those charge events and calculate their spatial centroid along with their time of arrival (X,Y,T). Laboratory versions of these electronics have demonstrated < 20 microns FWHM spatial resolution, count rates on the order of 2 MHz, and temporal resolution of ~ 1ns. In 2012 the our group at U.C. Berkeley, along with our partners at the U. Hawaii, received a Strategic Astrophysics Technology grant to raise the TRL of the PXS detector from 4 to 6 by replacing most of the 19" rack mounted, high powered electronics with application specific integrated circuits (ASICs) which will lower the power, mass and volume requirements of the PXS detector. We were also tasked to design and fabricate a "standard" 50mm square active area MCP detector incorporating these electronics that can be environmentally qualified for flight (temperature, vacuum, vibration). This detector design could then be modified for individual flight opportunities with a higher level of confidence than starting from scratch. We will present the latest progress on the ASIC designs, fabrication and performance and show imaging results from the 50mm XS detector using our current laboratory PXS electronics.

MicroChemLab, A Novel Approach for Handheld Chemical Sensing

NASA Astrophysics Data System (ADS)

Lewis, Patrick

2003-03-01

In 1996, Sandia National Laboratories began development of a chemical sensing platform based on microfabricated components. The goal of the project was to develop a handheld system for the detection of chemical warfare (CW) agent vapors in air. The components developed for this project are analogous to devices used in analytical laboratories. The benefit of microfabrication is that the resulting components are small and require little power to operate. The key elements of MicroChemLab are a sample collector - preconcentrator, a GC column and a surface acoustic wave (SAW) array detector. The preconcentrator is a thermally isolated silicon nitride membrane with a resistive heater patterned on one side and a sorptive sol gel film deposited on the other. Since the membrane has a very small mass, the resistive heater can ballistically elevate the temperature of the sorptive film to 200° C in approximately 10 ms. The sol gel film collects target compounds efficiently, but rejects volatile industrial solvents like alcohols, ketones, etc. The GC column is a one-meter high aspect ratio spiral channel etched in silicon with an anodically bonded pyrex lid completing the channel. A heater patterned on the silicon allows the column to be temperature ramped. Analytes injected from the preconcentrator are separated in this stage. The SAW array detector contains 3 delay lines used for sensing and 1 reference delay line. Each delay line is driven by an application specific integrated circuit (ASIC) at 500 MHz. Instead of counting frequency, additional ASICs incorporate a phase comparator that delivers a DC signal proportional to the amount of phase change. The three sensing elements of the detector provide a pattern that is indicative of the class of compound detected i.e. nerve agents or blister agents. Combined, these components provide a selective and sensitive handheld solution for the detection of chemical warfare agents. We will present lab data showing the performance of individual components and field data demonstrating the performance of this system. Sandia is a multiprogram laboratory operated by Sandia Corporation, a Lockheed Martin Company, for the United States Department of Energy under Contract DE-AC04-94AL85000.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Khalid, Farah F.; Deptuch, Grzegorz; Shenai, Alpana

Monolithic Active Matrix with Binary Counters (MAMBO) is a counting ASIC designed for detecting and measuring low energy X-rays from 6-12 keV. Each pixel contains analogue functionality implemented with a charge preamplifier, CR-RC{sup 2} shaper and a baseline restorer. It also contains a window comparator which can be trimmed by 4 bit DACs to remove systematic offsets. The hits are registered by a 12 bit ripple counter which is reconfigured as a shift register to serially output the data from the entire ASIC. Each pixel can be tested individually. Two diverse approaches have been used to prevent coupling between themore » detector and electronics in MAMBO III and MAMBO IV. MAMBO III is a 3D ASIC, the bottom ASIC consists of diodes which are connected to the top ASIC using {mu}-bump bonds. The detector is decoupled from the electronics by physically separating them on two tiers and using several metal layers as a shield. MAMBO IV is a monolithic structure which uses a nested well approach to isolate the detector from the electronics. The ASICs are being fabricated using the SOI 0.2 {micro}m OKI process, MAMBO III is 3D bonded at T-Micro and MAMBO IV nested well structure was developed in collaboration between OKI and Fermilab.« less

DOE Office of Scientific and Technical Information (OSTI.GOV)

Khalid, Farah; Deptuch, Grzegorz; Shenai, Alpana

Monolithic Active Matrix with Binary Counters (MAMBO) is a counting ASIC designed for detecting and measuring low energy X-rays from 6-12keV. Each pixel contains analogue functionality implemented with a charge preamplifier, CR-RC{sup 2} shaper and a baseline restorer. It also contains a window comparator which can be trimmed by 4 bit DACs to remove systematic offsets. The hits are registered by a 12 bit ripple counter which is reconfigured as a shift register to serially output the data from the entire ASIC. Each pixel can be tested individually. Two diverse approaches have been used to prevent coupling between the detectormore » and electronics in MAMBO III and MAMBO IV. MAMBO III is a 3D ASIC, the bottom ASIC consists of diodes which are connected to the top ASIC using {mu}-bump bonds. The detector is decoupled from the electronics by physically separating them on two tiers and using several metal layers as a shield. MAMBO IV is a monolithic structure which uses a nested well approach to isolate the detector from the electronics. The ASICs are being fabricated using the SOI 0.2 {micro}m OKI process, MAMBO III is 3D bonded at T-Micro and MAMBO IV nested well structure was developed in collaboration between OKI and Fermilab.« less

Parallel heterogeneous architectures for efficient OMP compressive sensing reconstruction

NASA Astrophysics Data System (ADS)

Kulkarni, Amey; Stanislaus, Jerome L.; Mohsenin, Tinoosh

2014-05-01

Compressive Sensing (CS) is a novel scheme, in which a signal that is sparse in a known transform domain can be reconstructed using fewer samples. The signal reconstruction techniques are computationally intensive and have sluggish performance, which make them impractical for real-time processing applications . The paper presents novel architectures for Orthogonal Matching Pursuit algorithm, one of the popular CS reconstruction algorithms. We show the implementation results of proposed architectures on FPGA, ASIC and on a custom many-core platform. For FPGA and ASIC implementation, a novel thresholding method is used to reduce the processing time for the optimization problem by at least 25%. Whereas, for the custom many-core platform, efficient parallelization techniques are applied, to reconstruct signals with variant signal lengths of N and sparsity of m. The algorithm is divided into three kernels. Each kernel is parallelized to reduce execution time, whereas efficient reuse of the matrix operators allows us to reduce area. Matrix operations are efficiently paralellized by taking advantage of blocked algorithms. For demonstration purpose, all architectures reconstruct a 256-length signal with maximum sparsity of 8 using 64 measurements. Implementation on Xilinx Virtex-5 FPGA, requires 27.14 μs to reconstruct the signal using basic OMP. Whereas, with thresholding method it requires 18 μs. ASIC implementation reconstructs the signal in 13 μs. However, our custom many-core, operating at 1.18 GHz, takes 18.28 μs to complete. Our results show that compared to the previous published work of the same algorithm and matrix size, proposed architectures for FPGA and ASIC implementations perform 1.3x and 1.8x respectively faster. Also, the proposed many-core implementation performs 3000x faster than the CPU and 2000x faster than the GPU.

ASIC/FPGA Trust Assessment Framework

NASA Technical Reports Server (NTRS)

Berg, Melanie

2018-01-01

NASA Electronic Parts and Packaging (NEPP) is developing a process to be employed in critical applications. The framework assesses levels of Trust and assurance in microelectronic systems. The process is being created with participation from a variety of organizations. We present a synopsis of the framework that includes contributions from The Aerospace Corporation.

Deactivation kinetics of acid-sensing ion channel 1a are strongly pH-sensitive.

PubMed

MacLean, David M; Jayaraman, Vasanthi

2017-03-21

Acid-sensing ion channels (ASICs) are trimeric cation-selective ion channels activated by protons in the physiological range. Recent reports have revealed that postsynaptically localized ASICs contribute to the excitatory postsynaptic current by responding to the transient acidification of the synaptic cleft that accompanies neurotransmission. In response to such brief acidic transients, both recombinant and native ASICs show extremely rapid deactivation in outside-out patches when jumping from a pH 5 stimulus to a single resting pH of 8. Given that the resting pH of the synaptic cleft is highly dynamic and depends on recent synaptic activity, we explored the kinetics of ASIC1a and 1a/2a heteromers to such brief pH transients over a wider [H + ] range to approximate neuronal conditions better. Surprisingly, the deactivation of ASICs was steeply dependent on the pH, spanning nearly three orders of magnitude from extremely fast (<1 ms) at pH 8 to very slow (>300 ms) at pH 7. This study provides an example of a ligand-gated ion channel whose deactivation is sensitive to agonist concentrations that do not directly activate the receptor. Kinetic simulations and further mutagenesis provide evidence that ASICs show such steeply agonist-dependent deactivation because of strong cooperativity in proton binding. This capacity to signal across such a large synaptically relevant bandwidth enhances the response to small-amplitude acidifications likely to occur at the cleft and may provide ASICs with the ability to shape activity in response to the recent history of the synapse.

Implementation of a cone-beam backprojection algorithm on the cell broadband engine processor

NASA Astrophysics Data System (ADS)

Bockenbach, Olivier; Knaup, Michael; Kachelrieß, Marc

2007-03-01

Tomographic image reconstruction is computationally very demanding. In all cases the backprojection represents the performance bottleneck due to the high operational count and due to the high demand put on the memory subsystem. In the past, solving this problem has lead to the implementation of specific architectures, connecting Application Specific Integrated Circuits (ASICs) or Field Programmable Gate Arrays (FPGAs) to memory through dedicated high speed busses. More recently, there have also been attempt to use Graphic Processing Units (GPUs) to perform the backprojection step. Originally aimed at the gaming market, IBM, Toshiba and Sony have introduced the Cell Broadband Engine (CBE) processor, often considered as a multicomputer on a chip. Clocked at 3 GHz, the Cell allows for a theoretical performance of 192 GFlops and a peak data transfer rate over the internal bus of 200 GB/s. This performance indeed makes the Cell a very attractive architecture for implementing tomographic image reconstruction algorithms. In this study, we investigate the relative performance of a perspective backprojection algorithm when implemented on a standard PC and on the Cell processor. We compare these results to the performance achievable with FPGAs based boards and high end GPUs. The cone-beam backprojection performance was assessed by backprojecting a full circle scan of 512 projections of 1024x1024 pixels into a volume of size 512x512x512 voxels. It took 3.2 minutes on the PC (single CPU) and is as fast as 13.6 seconds on the Cell.

Responses of glomus cells to hypoxia and acidosis are uncoupled, reciprocal and linked to ASIC3 expression: selectivity of chemosensory transduction

PubMed Central

Lu, Yongjun; Whiteis, Carol A; Sluka, Kathleen A; Chapleau, Mark W; Abboud, François M

2013-01-01

Carotid body glomus cells are the primary sites of chemotransduction of hypoxaemia and acidosis in peripheral arterial chemoreceptors. They exhibit pronounced morphological heterogeneity. A quantitative assessment of their functional capacity to differentiate between these two major chemical signals has remained undefined. We tested the hypothesis that there is a differential sensory transduction of hypoxia and acidosis at the level of glomus cells. We measured cytoplasmic Ca2+ concentration in individual glomus cells, isolated in clusters from rat carotid bodies, in response to hypoxia ( mmHg) and to acidosis at pH 6.8. More than two-thirds (68%) were sensitive to both hypoxia and acidosis, 19% were exclusively sensitive to hypoxia and 13% exclusively sensitive to acidosis. Those sensitive to both revealed significant preferential sensitivity to either hypoxia or to acidosis. This uncoupling and reciprocity was recapitulated in a mouse model by altering the expression of the acid-sensing ion channel 3 (ASIC3) which we had identified earlier in glomus cells. Increased expression of ASIC3 in transgenic mice increased pH sensitivity while reducing cyanide sensitivity. Conversely, deletion of ASIC3 in the knockout mouse reduced pH sensitivity while the relative sensitivity to cyanide or to hypoxia was increased. In this work, we quantify functional differences among glomus cells and show reciprocal sensitivity to acidosis and hypoxia in most glomus cells. We speculate that this selective chemotransduction of glomus cells by either stimulus may result in the activation of different afferents that are preferentially more sensitive to either hypoxia or acidosis, and thus may evoke different and more specific autonomic adjustments to either stimulus. PMID:23165770

Limits of intravascular contrast extravasation on computed tomography scan to define the need for pelvic angioembolization in pelvic blunt trauma: a specific assessment on the risk of false-positives.

PubMed

Ramin, Séverin; Hermida, Margaux; Millet, Ingrid; Murez, Thibault; Monnin, Valérie; Hamoui, Mazen; Capdevila, Xavier; Charbit, Jonathan

2018-06-12

The objective was to assess the predictive performance of different intravascular contrast extravasation (ICE) characteristics for need for pelvic transarterial embolization (TAE) to determine the risk factors of false-positives. A retrospective study was performed in our trauma center between 2010 and 2015. All severe trauma patients with pelvic fracture were included. Pelvic ICE characteristics on computed tomography (CT) scan were studied: arterial (aSICE), portal surface (pSICE), and extension (exSICE) anatomic relationships. The overall predictive performance of ICE surfaces for pelvic TAE was analyzed using receiver operating characteristic curves. The analysis focused on risk factors for false-positives. Among 311 severe trauma patients with pelvic ring fracture (mean age, 42 ± 19 years, mean Injury Severity Score, 27 ± 19), 94 (30%) had at least one pelvic ICE on the initial CT scan. Patients requiring pelvic TAE had significantly larger aSICE and pSICE than others (P=0.001 and P=0.035, respectively). The overall ability of ICE surfaces to predict pelvic TAE was modest (aSICE AUC, 0.76 [95% CI, 0.64-0.90]; P=0.011) or non-significant (pSICE and exSICE). The high-sensitivity threshold was defined as aSICE ≥20 mm. Using this threshold, 76% of patients were false-positives. Risk factors for false-positives were: admission systolic blood pressure ≥90 mmHg (63% versus 20%; P=0.03) and low transfusion needs (63% versus 10%; P=0.009), extravasation in contact with complex bone fracture (78% versus 30%; P=0.008) or the absence of a direct relationship between extravasation and a large retroperitoneal hematoma (100% versus 38%; P<0.001). A significant pelvic ICE during the arterial phase does not guarantee the need for pelvic TAE. Three-quarter of patients with aSICE ≥20 mm did not need pelvic TAE. Several complementary CT scan criteria will help to identify this risk of false-positives to determine adequate hemostatic pelvic procedures.This work is an original article, retrospective study Level II of evidence, Therapeutic/Critical Care management.

PixonVision real-time video processor

NASA Astrophysics Data System (ADS)

Puetter, R. C.; Hier, R. G.

2007-09-01

PixonImaging LLC and DigiVision, Inc. have developed a real-time video processor, the PixonVision PV-200, based on the patented Pixon method for image deblurring and denoising, and DigiVision's spatially adaptive contrast enhancement processor, the DV1000. The PV-200 can process NTSC and PAL video in real time with a latency of 1 field (1/60 th of a second), remove the effects of aerosol scattering from haze, mist, smoke, and dust, improve spatial resolution by up to 2x, decrease noise by up to 6x, and increase local contrast by up to 8x. A newer version of the processor, the PV-300, is now in prototype form and can handle high definition video. Both the PV-200 and PV-300 are FPGA-based processors, which could be spun into ASICs if desired. Obvious applications of these processors include applications in the DOD (tanks, aircraft, and ships), homeland security, intelligence, surveillance, and law enforcement. If developed into an ASIC, these processors will be suitable for a variety of portable applications, including gun sights, night vision goggles, binoculars, and guided munitions. This paper presents a variety of examples of PV-200 processing, including examples appropriate to border security, battlefield applications, port security, and surveillance from unmanned aerial vehicles.

Slow Computing Simulation of Bio-plausible Control

DTIC Science & Technology

2012-03-01

information networks, neuromorphic chips would become necessary. Small unstable flying platforms currently require RTK, GPS, or Vicon closed-circuit...Visual, and IR Sensing FPGA ASIC Neuromorphic Chip Simulation Quad Rotor Robotic Insect Uniform Independent Network Single Modality Neural Network... neuromorphic Processing across parallel computational elements =0.54 N u m b e r o f c o m p u ta tio n s - No info 14 integrated circuit

Histone Modifications in a Mouse Model of Early Adversities and Panic Disorder: Role for Asic1 and Neurodevelopmental Genes.

PubMed

Cittaro, Davide; Lampis, Valentina; Luchetti, Alessandra; Coccurello, Roberto; Guffanti, Alessandro; Felsani, Armando; Moles, Anna; Stupka, Elia; D' Amato, Francesca R; Battaglia, Marco

2016-04-28

Hyperventilation following transient, CO2-induced acidosis is ubiquitous in mammals and heritable. In humans, respiratory and emotional hypersensitivity to CO2 marks separation anxiety and panic disorders, and is enhanced by early-life adversities. Mice exposed to the repeated cross-fostering paradigm (RCF) of interference with maternal environment show heightened separation anxiety and hyperventilation to 6% CO2-enriched air. Gene-environment interactions affect CO2 hypersensitivity in both humans and mice. We therefore hypothesised that epigenetic modifications and increased expression of genes involved in pH-detection could explain these relationships. Medullae oblongata of RCF- and normally-reared female outbred mice were assessed by ChIP-seq for H3Ac, H3K4me3, H3K27me3 histone modifications, and by SAGE for differential gene expression. Integration of multiple experiments by network analysis revealed an active component of 148 genes pointing to the mTOR signalling pathway and nociception. Among these genes, Asic1 showed heightened mRNA expression, coherent with RCF-mice's respiratory hypersensitivity to CO2 and altered nociception. Functional enrichment and mRNA transcript analyses yielded a consistent picture of enhancement for several genes affecting chemoception, neurodevelopment, and emotionality. Particularly, results with Asic1 support recent human findings with panic and CO2 responses, and provide new perspectives on how early adversities and genes interplay to affect key components of panic and related disorders.

New APETx-like peptides from sea anemone Heteractis crispa modulate ASIC1a channels.

PubMed

Kalina, Rimma; Gladkikh, Irina; Dmitrenok, Pavel; Chernikov, Oleg; Koshelev, Sergey; Kvetkina, Aleksandra; Kozlov, Sergey; Kozlovskaya, Emma; Monastyrnaya, Margarita

2018-06-01

Sea anemones are an abundant source of various biologically active peptides. The hydrophobic 20% ethanol fraction of tropical sea anemone Heteractis crispa was shown to contain at least 159 peptide compounds including neurotoxins, proteinase and α-amylase inhibitors, as well as modulators of acid-sensing ion channels (ASICs). The three new peptides, π-AnmTX Hcr 1b-2, -3, and -4 (41 aa) (short names Hcr 1b-2, -3, -4), identified by a combination of reversed-phase liquid chromatography and mass spectrometry were found to belong to the class 1b sea anemone neurotoxins. The amino acid sequences of these peptides were determined by Edman degradation and tandem mass spectrometry. The percent of identity of Hcr 1b-2, -3, and -4 with well-known ASIC3 inhibitors Hcr 1b-1 from H. crispa and APETx2 from Anthopleura elegantissima is 95-78% and 46-49%, respectively. Electrophysiological experiments on homomeric ASIC channels expressed in Xenopus laevis oocytes establish that these peptides are the first inhibitors of ASIC1a derived from sea anemone venom. The major peptide, Hcr 1b-2, inhibited both rASIC1a (IC 50 4.8 ± 0.3 μM; nH 0.92 ± 0.05) and rASIC3 (IC 50 15.9 ± 1.1 μM; nH 1.0 ± 0.05). The maximum inhibition at saturating peptide concentrations reached 64% and 81%, respectively. In the model of acid-induced muscle pain Hcr 1b-2 was also shown to exhibit an antihyperalgesic effect, significantly reducing of the pain threshold of experimental animals. Copyright © 2018 Elsevier Inc. All rights reserved.

Macro Pixel ASIC (MPA): the readout ASIC for the pixel-strip (PS) module of the CMS outer tracker at HL-LHC

NASA Astrophysics Data System (ADS)

Ceresa, D.; Marchioro, A.; Kloukinas, K.; Kaplon, J.; Bialas, W.; Re, V.; Traversi, G.; Gaioni, L.; Ratti, L.

2014-11-01

The CMS tracker at HL-LHC is required to provide prompt information on particles with high transverse momentum to the central Level 1 trigger. For this purpose, the innermost part of the outer tracker is based on a combination of a pixelated sensor with a short strip sensor, the so-called Pixel-Strip module (PS). The readout of these sensors is carried out by distinct ASICs, the Strip Sensor ASIC (SSA), for the strip layer, and the Macro Pixel ASIC (MPA) for the pixel layer. The processing of the data directly on the front-end module represents a design challenge due to the large data volume (30720 pixels and 1920 strips per module) and the limited power budget. This is the reason why several studies have been carried out to find the best compromise between ASICs performance and power consumption. This paper describes the current status of the MPA ASIC development where the logic for generating prompt information on particles with high transverse momentum is implemented. An overview of the readout method is presented with particular attention on the cluster reduction, position encoding and momentum discrimination logic. Concerning the architectural studies, a software test bench capable of reading physics Monte-Carlo generated events has been developed and used to validate the MPA design and to evaluate the MPA performance. The MPA-Light is scheduled to be submitted for fabrication this year and will include the full analog functions and a part of the digital logic of the final version in order to qualify the chosen VLSI technology for the analog front-end, the module assembly and the low voltage digital supply.

Integration of Low-Power ASIC and MEMS Sensors for Monitoring Gastrointestinal Tract Using a Wireless Capsule System.

PubMed

Arefin, Md Shamsul; Redoute, Jean-Michel; Yuce, Mehmet Rasit

2018-01-01

This paper presents a wireless capsule microsystem to detect and monitor the pH, pressure, and temperature of the gastrointestinal tract in real time. This research contributes to the integration of sensors (microfabricated capacitive pH, capacitive pressure, and resistive temperature sensors), frequency modulation and pulse width modulation based interface IC circuits, microcontroller, and transceiver with meandered conformal antenna for the development of a capsule system. The challenges associated with the system miniaturization, higher sensitivity and resolution of sensors, and lower power consumption of interface circuits are addressed. The layout, PCB design, and packaging of a miniaturized wireless capsule, having diameter of 13 mm and length of 28 mm, have successfully been implemented. A data receiver and recorder system is also designed to receive physiological data from the wireless capsule and to send it to a computer for real-time display and recording. Experiments are performed in vitro using a stomach model and minced pork as tissue simulating material. The real-time measurements also validate the suitability of sensors, interface circuits, and meandered antenna for wireless capsule applications.

Physical and functional interactions between a glioma cation channel and integrin-β1 require α-actinin

PubMed Central

Rooj, Arun K.; Liu, Zhiyong; McNicholas, Carmel M.

2015-01-01

Major plasma membrane components of the tumor cell, ion channels, and integrins play crucial roles in metastasis. Glioma cells express an amiloride-sensitive nonselective cation channel composed of acid-sensing ion channel (ASIC)-1 and epithelial Na+ channel (ENaC) α- and γ-subunits. Inhibition of this channel is associated with reduced cell migration and proliferation. Using the ASIC-1 subunit as a reporter for the channel complex, we found a physical and functional interaction between this channel and integrin-β1. Short hairpin RNA knockdown of integrin-β1 attenuated the amiloride-sensitive current, which was due to loss of surface expression of ASIC-1. In contrast, upregulation of membrane expression of integrin-β1 increased the surface expression of ASIC-1. The link between the amiloride-sensitive channel and integrin-β1 was mediated by α-actinin. Downregulation of α-actinin-1 or -4 attenuated the amiloride-sensitive current. Mutation of the putative binding site for α-actinin on the COOH terminus of ASIC-1 reduced the membrane localization of ASIC-1 and also resulted in attenuation of the amiloride-sensitive current. Our data suggest a novel interaction between the amiloride-sensitive glioma cation channel and integrin-β1, mediated by α-actinin. This interaction may form a mechanism by which channel activity can regulate glioma cell proliferation and migration. PMID:26108662

Structural plasticity and dynamic selectivity of acid-sensing ion channel-spider toxin complexes

DOE Office of Scientific and Technical Information (OSTI.GOV)

Baconguis, Isabelle; Gouaux, Eric

2012-07-29

Acid-sensing ion channels (ASICs) are voltage-independent, amiloride-sensitive channels involved in diverse physiological processes ranging from nociception to taste. Despite the importance of ASICs in physiology, we know little about the mechanism of channel activation. Here we show that psalmotoxin activates non-selective and Na +-selective currents in chicken ASIC1a at pH7.25 and 5.5, respectively. Crystal structures of ASIC1a–psalmotoxin complexes map the toxin binding site to the extracellular domain and show how toxin binding triggers an expansion of the extracellular vestibule and stabilization of the open channel pore. At pH7.25 the pore is approximately 10Å in diameter, whereas at pH5.5 the poremore » is largely hydrophobic and elliptical in cross-section with dimensions of approximately 5 by 7Å, consistent with a barrier mechanism for ion selectivity. These studies define mechanisms for activation of ASICs, illuminate the basis for dynamic ion selectivity and provide the blueprints for new therapeutic agents.« less

The Amygdala is a Chemosensor that Detects Carbon Dioxide and Acidosis to Elicit Fear Behavior

PubMed Central

Ziemann, Adam E.; Allen, Jason E.; Dahdaleh, Nader S.; Drebot, Iuliia I.; Coryell, Matt; Wunsch, Amanda M.; Lynch, Cynthia M.; Faraci, Frank M.; Howard, Matthew A.; Welsh, Michael J.; Wemmie, John A.

2009-01-01

SUMMARY The amygdala processes and directs inputs and outputs that are key to fear behavior. However, whether it directly senses fear-evoking stimuli is unknown. Because the amygdala expresses acid sensing ion channel-1a (ASIC1a), and ASIC1a is required for normal fear responses, we hypothesized that the amygdala might detect a reduced pH. We found that inhaled CO2 reduced brain pH and evoked fear behavior in mice. Eliminating or inhibiting ASIC1a markedly impaired this activity, and localized ASIC1a expression in the amygdala rescued the CO2- induced fear deficit of ASIC1a-null animals. Buffering pH attenuated fear behavior, whereas directly reducing pH with amygdala microinjections reproduced the effect of CO2. These data identify the amygdala as an important chemosensor that detects hypercarbia and acidosis and initiates behavioral responses. They also give a molecular explanation for how rising CO2 concentrations elicit intense fear and provide a foundation for dissecting the bases of anxiety and panic disorders. PMID:19945383

Rodent wearable ultrasound system for wireless neural recording.

PubMed

Piech, David K; Kay, Joshua E; Boser, Bernhard E; Maharbiz, Michel M

2017-07-01

Advances in minimally-invasive, distributed biological interface nodes enable possibilities for networks of sensors and actuators to connect the brain with external devices. The recent development of the neural dust sensor mote has shown that utilizing ultrasound backscatter communication enables untethered sub-mm neural recording devices. These implanted sensor motes require a wearable external ultrasound interrogation device to enable in-vivo, freely-behaving neural interface experiments. However, minimizing the complexity and size of the implanted sensors shifts the power and processing burden to the external interrogator. In this paper, we present an ultrasound backscatter interrogator that supports real-time backscatter processing in a rodent-wearable, completely wireless device. We demonstrate a generic digital encoding scheme which is intended for transmitting neural information. The system integrates a front-end ultrasonic interface ASIC with off-the-shelf components to enable a highly compact ultrasound interrogation device intended for rodent neural interface experiments but applicable to other model systems.

Endomorphins potentiate acid-sensing ion channel currents and enhance the lactic acid-mediated increase in arterial blood pressure: effects amplified in hindlimb ischaemia.

PubMed

Farrag, Mohamed; Drobish, Julie K; Puhl, Henry L; Kim, Joyce S; Herold, Paul B; Kaufman, Marc P; Ruiz-Velasco, Victor

2017-12-01

Chronic limb ischaemia, characterized by inflammatory mediator release and a low extracellular pH, leads to acid-sensing ion channel (ASIC) activation and reflexively increases mean arterial pressure; endomorphin release is also increased under inflammatory conditions. We examined the modulation of ASIC currents by endomorphins in sensory neurons from rats with freely perfused and ligated femoral arteries: peripheral artery disease (PAD) model. Endomorphins potentiated sustained ASIC currents in both groups of dorsal root ganglion neurons, independent of mu opioid receptor stimulation or G protein activation. Intra-arterial administration of lactic acid (to simulate exercising muscle and evoke a pressor reflex), endomorphin-2 and naloxone resulted in a significantly greater pressor response than lactic acid alone, while administration of APETx2 inhibited endomorphin's enhancing effect in both groups. These results suggest a novel role for endomorphins in modulating ASIC function to effect lactic acid-mediated reflex increase in arterial pressure in patients with PAD. Chronic muscle ischaemia leads to accumulation of lactic acid and other inflammatory mediators with a subsequent drop in interstitial pH. Acid-sensing ion channels (ASICs), expressed in thin muscle afferents, sense the decrease in pH and evoke a pressor reflex known to increase mean arterial pressure. The naturally occurring endomorphins are also released by primary afferents under ischaemic conditions. We examined whether high affinity mu opioid receptor (MOR) agonists, endomorphin-1 (E-1) and -2 (E-2), modulate ASIC currents and the lactic acid-mediated pressor reflex. In rat dorsal root ganglion (DRG) neurons, exposure to E-2 in acidic solutions significantly potentiated ASIC currents when compared to acidic solutions alone. The potentiation was significantly greater in DRG neurons isolated from rats whose femoral arteries were ligated for 72 h. Sustained ASIC current potentiation was also observed in neurons pretreated with pertussis toxin, an uncoupler of G proteins and MOR. The endomorphin-mediated potentiation was a result of a leftward shift of the activation curve to higher pH values and a slight shift of the inactivation curve to lower pH values. Intra-arterial co-administration of lactic acid and E-2 led to a significantly greater pressor reflex than lactic acid alone in the presence of naloxone. Finally, E-2 effects were inhibited by pretreatment with the ASIC3 blocker APETx2 and enhanced by pretreatment with the ASIC1a blocker psalmotoxin-1. These findings have uncovered a novel role of endomorphins by which the opioids can enhance the lactic acid-mediated reflex increase in arterial pressure that is MOR stimulation-independent and APETx2-sensitive. © 2017 The Authors. The Journal of Physiology © 2017 The Physiological Society.

Mongoose ASIC microcontroller programming guide

NASA Astrophysics Data System (ADS)

Smith, Brian S.

1993-09-01

The 'Mongoose' ASIC microcontroller is a radiation-hard implementation of the R3000 microprocessor. This document describes the internals of the microcontroller in a level of detail necessary for someone implementing a software design.

Mongoose ASIC microcontroller programming guide

NASA Technical Reports Server (NTRS)

Smith, Brian S.

1993-01-01

The 'Mongoose' ASIC microcontroller is a radiation-hard implementation of the R3000 microprocessor. This document describes the internals of the microcontroller in a level of detail necessary for someone implementing a software design.

Life Cycle Cost Model for Very High Speed Integrated Circuits.

DTIC Science & Technology

1984-09-01

Intermediate CDFD =Cost to Ship $3.13 (CONUS) N/A All L/Global Tml. XXIX from Factory to $6.00 (Europe) Depot. Dollars/ $6.00 (Asia) * Pound/Trip CDID =Cost... ANALISIS -10%) 179360. 28. 634. 180021. 209 i. , . . - TITL EN~WURfG P1U1’V E PRM CNa TOAL 00g SIGAL P- M ’ASIC C2UP-BIKAR LMLI =MI~D MT2MSIS-10

Naked mole-rat cortical neurons are resistant to acid-induced cell death.

PubMed

Husson, Zoé; Smith, Ewan St John

2018-05-09

Regulation of brain pH is a critical homeostatic process and changes in brain pH modulate various ion channels and receptors and thus neuronal excitability. Tissue acidosis, resulting from hypoxia or hypercapnia, can activate various proteins and ion channels, among which acid-sensing ion channels (ASICs) a family of primarily Na + permeable ion channels, which alongside classical excitotoxicity causes neuronal death. Naked mole-rats (NMRs, Heterocephalus glaber) are long-lived, fossorial, eusocial rodents that display remarkable behavioral/cellular hypoxia and hypercapnia resistance. In the central nervous system, ASIC subunit expression is similar between mouse and NMR with the exception of much lower expression of ASIC4 throughout the NMR brain. However, ASIC function and neuronal sensitivity to sustained acidosis has not been examined in the NMR brain. Here, we show with whole-cell patch-clamp electrophysiology of cultured NMR and mouse cortical and hippocampal neurons that NMR neurons have smaller voltage-gated Na + channel currents and more hyperpolarized resting membrane potentials. We further demonstrate that acid-mediated currents in NMR neurons are of smaller magnitude than in mouse, and that all currents in both species are reversibly blocked by the ASIC antagonist benzamil. We further demonstrate that NMR neurons show greater resistance to acid-induced cell death than mouse neurons. In summary, NMR neurons show significant cellular resistance to acidotoxicity compared to mouse neurons, contributing factors likely to be smaller ASIC-mediated currents and reduced NaV activity.

A design of a valid signal selecting and position decoding ASIC for PET using silicon photomultipliers

NASA Astrophysics Data System (ADS)

Cho, M.; Lim, K.-t.; Kim, H.; Yeom, J.-y.; Kim, J.; Lee, C.; Choi, H.; Cho, G.

2017-01-01

In most cases, a PET system has numerous electrical components and channel circuits and thus it would rather be a bulky product. Also, most existing systems receive analog signals from detectors which make them vulnerable to signal distortions. For these reasons, channel reduction techniques are important. In this work, an ASIC for PET module is being proposed. An ASIC chip for 16 PET detector channels, VSSPDC, has been designed and simulated. The main function of the chip is 16-to-1 channel reduction, i.e., finding the position of only the valid signals, signal timing, and magnitudes in all 16 channels at every recorded event. The ASIC comprises four of 4-channel modules and a 2nd 4-to-1 router. A single channel module comprises a transimpedance amplifier for the silicon photomultipliers, dual comparators with high and low level references, and a logic circuitry. While the high level reference was used to test the validity of the signal, the low level reference was used for the timing. The 1-channel module of the ASIC produced an energy pulse by time-over-threshold method and it also produced a time pulse with a fixed delayed time. Since the ASIC chip outputs only a few digital pulses and does not require an external clock, it has an advantage over noise properties. The cadence simulation showed the good performance of the chip as designed.

An Unexpected Function of the Prader-Willi Syndrome Imprinting Center in Maternal Imprinting in Mice

PubMed Central

Wu, Mei-Yi; Jiang, Ming; Zhai, Xiaodong; Beaudet, Arthur L.; Wu, Ray-Chang

2012-01-01

Genomic imprinting is a phenomenon that some genes are expressed differentially according to the parent of origin. Prader-Willi syndrome (PWS) and Angelman syndrome (AS) are neurobehavioral disorders caused by deficiency of imprinted gene expression from paternal and maternal chromosome 15q11–q13, respectively. Imprinted genes at the PWS/AS domain are regulated through a bipartite imprinting center, the PWS-IC and AS-IC. The PWS-IC activates paternal-specific gene expression and is responsible for the paternal imprint, whereas the AS-IC functions in the maternal imprint by allele-specific repression of the PWS-IC to prevent the paternal imprinting program. Although mouse chromosome 7C has a conserved PWS/AS imprinted domain, the mouse equivalent of the human AS-IC element has not yet been identified. Here, we suggest another dimension that the PWS-IC also functions in maternal imprinting by negatively regulating the paternally expressed imprinted genes in mice, in contrast to its known function as a positive regulator for paternal-specific gene expression. Using a mouse model carrying a 4.8-kb deletion at the PWS-IC, we demonstrated that maternal transmission of the PWS-IC deletion resulted in a maternal imprinting defect with activation of the paternally expressed imprinted genes and decreased expression of the maternally expressed imprinted gene on the maternal chromosome, accompanied by alteration of the maternal epigenotype toward a paternal state spread over the PWS/AS domain. The functional significance of this acquired paternal pattern of gene expression was demonstrated by the ability to complement PWS phenotypes by maternal inheritance of the PWS-IC deletion, which is in stark contrast to paternal inheritance of the PWS-IC deletion that resulted in the PWS phenotypes. Importantly, low levels of expression of the paternally expressed imprinted genes are sufficient to rescue postnatal lethality and growth retardation in two PWS mouse models. These findings open the opportunity for a novel approach to the treatment of PWS. PMID:22496793

An unexpected function of the Prader-Willi syndrome imprinting center in maternal imprinting in mice.

PubMed

Wu, Mei-Yi; Jiang, Ming; Zhai, Xiaodong; Beaudet, Arthur L; Wu, Ray-Chang

2012-01-01

Genomic imprinting is a phenomenon that some genes are expressed differentially according to the parent of origin. Prader-Willi syndrome (PWS) and Angelman syndrome (AS) are neurobehavioral disorders caused by deficiency of imprinted gene expression from paternal and maternal chromosome 15q11-q13, respectively. Imprinted genes at the PWS/AS domain are regulated through a bipartite imprinting center, the PWS-IC and AS-IC. The PWS-IC activates paternal-specific gene expression and is responsible for the paternal imprint, whereas the AS-IC functions in the maternal imprint by allele-specific repression of the PWS-IC to prevent the paternal imprinting program. Although mouse chromosome 7C has a conserved PWS/AS imprinted domain, the mouse equivalent of the human AS-IC element has not yet been identified. Here, we suggest another dimension that the PWS-IC also functions in maternal imprinting by negatively regulating the paternally expressed imprinted genes in mice, in contrast to its known function as a positive regulator for paternal-specific gene expression. Using a mouse model carrying a 4.8-kb deletion at the PWS-IC, we demonstrated that maternal transmission of the PWS-IC deletion resulted in a maternal imprinting defect with activation of the paternally expressed imprinted genes and decreased expression of the maternally expressed imprinted gene on the maternal chromosome, accompanied by alteration of the maternal epigenotype toward a paternal state spread over the PWS/AS domain. The functional significance of this acquired paternal pattern of gene expression was demonstrated by the ability to complement PWS phenotypes by maternal inheritance of the PWS-IC deletion, which is in stark contrast to paternal inheritance of the PWS-IC deletion that resulted in the PWS phenotypes. Importantly, low levels of expression of the paternally expressed imprinted genes are sufficient to rescue postnatal lethality and growth retardation in two PWS mouse models. These findings open the opportunity for a novel approach to the treatment of PWS.

Low-power low-noise mixed-mode VLSI ASIC for infinite dynamic range imaging applications

NASA Astrophysics Data System (ADS)

Turchetta, Renato; Hu, Y.; Zinzius, Y.; Colledani, C.; Loge, A.

1998-11-01

Solid state solutions for imaging are mainly represented by CCDs and, more recently, by CMOS imagers. Both devices are based on the integration of the total charge generated by the impinging radiation, with no processing of the single photon information. The dynamic range of these devices is intrinsically limited by the finite value of noise. Here we present the design of an architecture which allows efficient, in-pixel, noise reduction to a practically zero level, thus allowing infinite dynamic range imaging. A detailed calculation of the dynamic range is worked out, showing that noise is efficiently suppressed. This architecture is based on the concept of single-photon counting. In each pixel, we integrate both the front-end, low-noise, low-power analog part and the digital part. The former consists of a charge preamplifier, an active filter for optimal noise bandwidth reduction, a buffer and a threshold comparator, and the latter is simply a counter, which can be programmed to act as a normal shift register for the readout of the counters' contents. Two different ASIC's based on this concept have been designed for different applications. The first one has been optimized for silicon edge-on microstrips detectors, used in a digital mammography R and D project. It is a 32-channel circuit, with a 16-bit binary static counter.It has been optimized for a relatively large detector capacitance of 5 pF. Noise has been measured to be equal to 100 + 7*Cd (pF) electron rms with the digital part, showing no degradation of the noise performances with respect to the design values. The power consumption is 3.8mW/channel for a peaking time of about 1 microsecond(s) . The second circuit is a prototype for pixel imaging. The total active area is about (250 micrometers )**2. The main differences of the electronic architecture with respect to the first prototype are: i) different optimization of the analog front-end part for low-capacitance detectors, ii) in- pixel 4-bit comparator-offset compensation, iii) 15-bit pseudo-random counter. The power consumption is 255 (mu) W/channel for a peaking time of 300 ns and an equivalent noise charge of 185 + 97*Cd electrons rms. Simulation and experimental result as well as imaging results will be presented.

Design of a Multi-Channel Low-Noise Readout ASIC for CdZnTe-Based X-Ray and γ-Ray Spectrum Analyzer

NASA Astrophysics Data System (ADS)

Gan, B.; Wei, T.; Gao, W.; Zheng, R.; Hu, Y.

2015-10-01

In this paper, we report on the recent development of a 32-channel low-noise front-end readout ASIC for cadmium zinc telluride (CdZnTe) X-ray and γ-ray detectors. Each readout channel includes a charge sensitive amplifier, a CR-RC shaping amplifier and an analog output buffer. The readout ASIC is implemented using TSMC 0.35 - μm mixed-signal CMOS technology, the die size of the prototype chip is 2.2 mm ×4.8 mm. At room temperature, the equivalent noise level of a typical channel reaches 133 e- (rms) with the input parasitic capacitance of 0 pF for the average power consumption of 2.8 mW per channel. The linearity error is less than ±2% and the input energy dynamic range of the readout ASIC is from 10 keV to 1 MeV. The crosstalk between the channels is less than 0.4%. By connecting the readout ASIC to a CdZnTe detector, we obtained a γ-ray spectrum, the energy resolution is 1.8% at the 662-keV line of 137Cs source.

X-ray structure of acid-sensing ion channel 1-snake toxin complex reveals open state of a Na(+)-selective channel.

PubMed

Baconguis, Isabelle; Bohlen, Christopher J; Goehring, April; Julius, David; Gouaux, Eric

2014-02-13

Acid-sensing ion channels (ASICs) detect extracellular protons produced during inflammation or ischemic injury and belong to the superfamily of degenerin/epithelial sodium channels. Here, we determine the cocrystal structure of chicken ASIC1a with MitTx, a pain-inducing toxin from the Texas coral snake, to define the structure of the open state of ASIC1a. In the MitTx-bound open state and in the previously determined low-pH desensitized state, TM2 is a discontinuous α helix in which the Gly-Ala-Ser selectivity filter adopts an extended, belt-like conformation, swapping the cytoplasmic one-third of TM2 with an adjacent subunit. Gly 443 residues of the selectivity filter provide a ring of three carbonyl oxygen atoms with a radius of ∼3.6 Å, presenting an energetic barrier for hydrated ions. The ASIC1a-MitTx complex illuminates the mechanism of MitTx action, defines the structure of the selectivity filter of voltage-independent, sodium-selective ion channels, and captures the open state of an ASIC. Copyright © 2014 Elsevier Inc. All rights reserved.

Cryogenic low noise and low dissipation multiplexing electronics, using HEMT+SiGe ASICs, for the readout of high impedance sensors: New version

NASA Astrophysics Data System (ADS)

de la Broïse, Xavier; Lugiez, Francis; Bounab, Ayoub; Le Coguie, Alain

2015-07-01

High Electron Mobility Transistors (HEMTs), optimized by CNRS/LPN laboratory for ultra-low noise at very low temperature, have demonstrated their capacity to be used in place of Si JFETs when working temperatures below 100 K are required. We associated them with specific SiGe ASICs that we developed, to implement a complete readout channel able to read highly segmented high impedance detectors within a framework of very low thermal dissipation. Our electronics is dimensioned to read 4096 detection channels, of typically 1 MΩ impedance, and performs 32:1 multiplexing and amplifying, dissipating only 6 mW at 2.5 K and 100 mW at 15 K thanks to high impedance commuting of input stage, with a typical noise of 1 nV/√Hz at 1 kHz.

A Low-Power ASIC Signal Processor for a Vestibular Prosthesis.

PubMed

Töreyin, Hakan; Bhatti, Pamela T

2016-06-01

A low-power ASIC signal processor for a vestibular prosthesis (VP) is reported. Fabricated with TI 0.35 μm CMOS technology and designed to interface with implanted inertial sensors, the digitally assisted analog signal processor operates extensively in the CMOS subthreshold region. During its operation the ASIC encodes head motion signals captured by the inertial sensors as electrical pulses ultimately targeted for in-vivo stimulation of vestibular nerve fibers. To achieve this, the ASIC implements a coordinate system transformation to correct for misalignment between natural sensors and implanted inertial sensors. It also mimics the frequency response characteristics and frequency encoding mappings of angular and linear head motions observed at the peripheral sense organs, semicircular canals and otolith. Overall the design occupies an area of 6.22 mm (2) and consumes 1.24 mW when supplied with ± 1.6 V.

A Low-Power ASIC Signal Processor for a Vestibular Prosthesis

PubMed Central

Töreyin, Hakan; Bhatti, Pamela T.

2017-01-01

A low-power ASIC signal processor for a vestibular prosthesis (VP) is reported. Fabricated with TI 0.35 μm CMOS technology and designed to interface with implanted inertial sensors, the digitally assisted analog signal processor operates extensively in the CMOS subthreshold region. During its operation the ASIC encodes head motion signals captured by the inertial sensors as electrical pulses ultimately targeted for in-vivo stimulation of vestibular nerve fibers. To achieve this, the ASIC implements a coordinate system transformation to correct for misalignment between natural sensors and implanted inertial sensors. It also mimics the frequency response characteristics and frequency encoding mappings of angular and linear head motions observed at the peripheral sense organs, semicircular canals and otolith. Overall the design occupies an area of 6.22 mm2 and consumes 1.24 mW when supplied with ± 1.6 V. PMID:26800546

Readout ASICs and Electronics for the 144-channel HAPDs for the Aerogel RICH at Belle II

NASA Astrophysics Data System (ADS)

Nishida, S.; Adachi, I.; Ikeda, H.; Hara, K.; Iijima, T.; Iwata, S.; Korpar, S.; Križan, P.; Kuroda, E.; Pestotnik, R.; Seljak, A.; Sumiyoshi, T.; Takagaki, H.

The particle identification (PID) device in the endcap of the Belle detector will be upgraded to a ring imaging Cherenkov counter (RICH) using aerogel as a radiator at the Belle II experiment. We develop the electronics to read out the 70,000 channels of hit information from the 144-channel hybrid avalanche photodetectors (HAPD), of the aerogel RICH detector. A readout ASIC is developed to digitize the HAPD signals, and was used in a beam test with the prototype detector. The performance and plan of the ASIC is reported in this study. We have also designed the readout electronics for the aerogel RICH, which consist of front-end boards with the ASICs merger boards to collect data from the front-end boards. A front-end board that fits in the actual available space for the aerogel RICH electronics was produced.

Identification of acid-sensing ion channels in adenoid cystic carcinomas

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ye Jinhai; Department of Oral and Maxillofacial Surgery, School of Stomatology, Nanjing Medical University, Research Institute of Stomatology, Nanjing 210029; Gao Jun

2007-04-20

Tissue acidosis is an important feature of tumor. The response of adenoid cystic carcinoma (ACC) cells to acidic solution was studied using whole-cell patch-clamp recording in the current study. An inward, amiloride-sensitive Na{sup +} current was identified in cultured ACC-2 cells while not in normal human salivary gland epithelial cells. Electrophysiological and pharmacological properties of the currents suggest that heteromeric acid-sensing ion channels (ASICs) containing 2a and 3 may be responsible for the proton-induced currents in the majority of ACC-2 cells. Consistent with it, analyses of RT-PCR and Western blotting demonstrated the presences of ASIC2a and 3 in ACC-2 cells.more » Furthermore, we observed the enhanced expression of ASIC2a and 3 in the sample of ACC tissues. These results indicate that the functional expression of ASICs is characteristic feature of ACC cells.« less

Acid-sensing ion channels and transient-receptor potential ion channels in zebrafish taste buds.

PubMed

Levanti, M; Randazzo, B; Viña, E; Montalbano, G; Garcia-Suarez, O; Germanà, A; Vega, J A; Abbate, F

2016-09-01

Sensory information from the environment is required for life and survival, and it is detected by specialized cells which together make up the sensory system. The fish sensory system includes specialized organs that are able to detect mechanical and chemical stimuli. In particular, taste buds are small organs located on the tongue in terrestrial vertebrates that function in the perception of taste. In fish, taste buds occur on the lips, the flanks, and the caudal (tail) fins of some species and on the barbels of others. In fish taste receptor cells, different classes of ion channels have been detected which, like in mammals, presumably participate in the detection and/or transduction of chemical gustatory signals. However, since some of these ion channels are involved in the detection of additional sensory modalities, it can be hypothesized that taste cells sense stimuli other than those specific for taste. This mini-review summarizes current knowledge on the presence of transient-receptor potential (TRP) and acid-sensing (ASIC) ion channels in the taste buds of teleosts, especially adult zebrafish. Up to now ASIC4, TRPC2, TRPA1, TRPV1 and TRPV4 ion channels have been found in the sensory cells, while ASIC2 was detected in the nerves supplying the taste buds. Copyright © 2016 Elsevier GmbH. All rights reserved.

OSCAR: A Compact, Powerful and Versatile On Board Computer Based on LEON3 Core

NASA Astrophysics Data System (ADS)

Poupat, Jean-Luc; Lefevre, Aurelien; Koebel, Franck

2011-08-01

Satellites are controlled via a platform On Board Computer (OBC) that manages different parameters (attitude, orbit, modes, temperatures ...) with respect to its payload mission (telecommunication, earth observation, scientific mission). The platform OBC is connected to the satellite and the ground control via digital links, and executes on board software.The main functions of a platform OBC are to provide the satellite flight segment with the following features: o Processing resources for the flight mission software o TM/TC services and interfaces with the RF communication chaino General communication services with the Avionicsand payload equipments through an on-board communication bus based on the MIL-1553B standard or CANo Time synchronization and distributiono Failure tolerant architecture based on the use of redounded reconfiguration units and redundancyimplementationFrom a hardware point of view, it groups a lot of digital functions usually dispatched on numerous chips (processor, co-processor, digital links IP ...) together. In order to reach an ultimate level of integration, Astrium has designed an ASIC gathering on a single chip all the required digital functions: the SCOC3 ASIC.Astrium has developed an OBC based on this SCOC3 ASIC: the OSCAR (Optimized Spacecraft Computer Architecture with Reconfiguration). It is now available off-the-shelf as the new OBC product family of Astrium.This paper presents the major innovations introduced by Astrium for SCOC3 and OSCAR with the objective to save cost and mass through a solution compatible with any class quality project, using a unique software development environment for user.

Product assurance technology for procuring reliable, radiation-hard, custom LSI/VLSI electronics

NASA Technical Reports Server (NTRS)

Buehler, M. G.; Allen, R. A.; Blaes, B. R.; Hicks, K. A.; Jennings, G. A.; Lin, Y.-S.; Pina, C. A.; Sayah, H. R.; Zamani, N.

1989-01-01

Advanced measurement methods using microelectronic test chips are described. These chips are intended to be used in acquiring the data needed to qualify Application Specific Integrated Circuits (ASIC's) for space use. Efforts were focused on developing the technology for obtaining custom IC's from CMOS/bulk silicon foundries. A series of test chips were developed: a parametric test strip, a fault chip, a set of reliability chips, and the CRRES (Combined Release and Radiation Effects Satellite) chip, a test circuit for monitoring space radiation effects. The technical accomplishments of the effort include: (1) development of a fault chip that contains a set of test structures used to evaluate the density of various process-induced defects; (2) development of new test structures and testing techniques for measuring gate-oxide capacitance, gate-overlap capacitance, and propagation delay; (3) development of a set of reliability chips that are used to evaluate failure mechanisms in CMOS/bulk: interconnect and contact electromigration and time-dependent dielectric breakdown; (4) development of MOSFET parameter extraction procedures for evaluating subthreshold characteristics; (5) evaluation of test chips and test strips on the second CRRES wafer run; (6) two dedicated fabrication runs for the CRRES chip flight parts; and (7) publication of two papers: one on the split-cross bridge resistor and another on asymmetrical SRAM (static random access memory) cells for single-event upset analysis.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ross, Steve; Haji-Sheikh, Michael; Huntington, Andrew

The Voxtel VX-798 is a prototype X-ray pixel array detector (PAD) featuring a silicon sensor photodiode array of 48 x 48 pixels, each 130 mu m x 130 mu m x 520 mu m thick, coupled to a CMOS readout application specific integrated circuit (ASIC). The first synchrotron X-ray characterization of this detector is presented, and its ability to selectively count individual X-rays within two independent arrival time windows, a programmable energy range, and localized to a single pixel is demonstrated. During our first trial run at Argonne National Laboratory's Advance Photon Source, the detector achieved a 60 ns gatingmore » time and 700 eV full width at half-maximum energy resolution in agreement with design parameters. Each pixel of the PAD holds two independent digital counters, and the discriminator for X-ray energy features both an upper and lower threshold to window the energy of interest discarding unwanted background. This smart-pixel technology allows energy and time resolution to be set and optimized in software. It is found that the detector linearity follows an isolated dead-time model, implying that megahertz count rates should be possible in each pixel. Measurement of the line and point spread functions showed negligible spatial blurring. When combined with the timing structure of the synchrotron storage ring, it is demonstrated that the area detector can perform both picosecond time-resolved X-ray diffraction and fluorescence spectroscopy measurements.« less

Circuit for Communication Over Power Lines

NASA Technical Reports Server (NTRS)

Krasowski, Michael J.; Prokop, Normal F.; Greer, Lawrence C., III; Nappier, Jennifer

2011-01-01

Many distributed systems share common sensors and instruments along with a common power line supplying current to the system. A communication technique and circuit has been developed that allows for the simple inclusion of an instrument, sensor, or actuator node within any system containing a common power bus. Wherever power is available, a node can be added, which can then draw power for itself, its associated sensors, and actuators from the power bus all while communicating with other nodes on the power bus. The technique modulates a DC power bus through capacitive coupling using on-off keying (OOK), and receives and demodulates the signal from the DC power bus through the same capacitive coupling. The circuit acts as serial modem for the physical power line communication. The circuit and technique can be made of commercially available components or included in an application specific integrated circuit (ASIC) design, which allows for the circuit to be included in current designs with additional circuitry or embedded into new designs. This device and technique moves computational, sensing, and actuation abilities closer to the source, and allows for the networking of multiple similar nodes to each other and to a central processor. This technique also allows for reconfigurable systems by adding or removing nodes at any time. It can do so using nothing more than the in situ power wiring of the system.

A noiseless, kHz frame rate imaging detector for AO wavefront sensors based on MCPs read out with the Medipix2 CMOS pixel chip

NASA Astrophysics Data System (ADS)

Vallerga, J. V.; McPhate, J. B.; Tremsin, A. S.; Siegmund, O. H. W.; Mikulec, B.; Clark, A. G.

2004-12-01

Future wavefront sensors in adaptive optics (AO) systems for the next generation of large telescopes (> 30 m diameter) will require large formats (512x512) , kHz frame rates, low readout noise (<3 electrons) and high optical QE. The current generation of CCDs cannot achieve the first three of these specifications simultaneously. We present a detector scheme that can meet the first three requirements with an optical QE > 40%. This detector consists of a vacuum tube with a proximity focused GaAs photocathode whose photoelectrons are amplified by microchannel plates and the resulting output charge cloud counted by a pixelated CMOS application specific integrated circuit (ASIC) called the Medipix2 (http://medipix.web.cern.ch/MEDIPIX/). Each 55 micron square pixel of the Medipix2 chip has an amplifier, discriminator and 14 bit counter and the 256x256 array can be read out in 287 microseconds. The chip is 3 side abuttable so a 512x512 array is feasible in one vacuum tube. We will present the first results with an open-faced, demountable version of the detector where we have mounted a pair of MCPs 500 microns above a Medipix2 readout inside a vacuum chamber and illuminated it with UV light. The results include: flat field response, spatial resolution, spatial linearity on the sub-pixel level and global event counting rate. We will also discuss the vacuum tube design and the fabrication issues associated with the Medipix2 surviving the tube making process.

THOR Ion Mass Spectrometer instrument - IMS

NASA Astrophysics Data System (ADS)

Retinò, Alessandro; Kucharek, Harald; Saito, Yoshifumi; Fraenz, Markus; Verdeil, Christophe; Leblanc, Frederic; Techer, Jean-Denis; Jeandet, Alexis; Macri, John; Gaidos, John; Granoff, Mark; Yokota, Shoichiro; Fontaine, Dominique; Berthomier, Matthieu; Delcourt, Dominique; Kistler, Lynn; Galvin, Antoniette; Kasahara, Satoshi; Kronberg, Elena

2016-04-01

Turbulence Heating ObserveR (THOR) is the first mission ever flown in space dedicated to plasma turbulence. Specifically, THOR will study how turbulent fluctuations at kinetic scales heat and accelerate particles in different turbulent environments within the near-Earth space. To achieve this goal, THOR payload is being designed to measure electromagnetic fields and particle distribution functions with unprecedented resolution and accuracy. Here we present the Ion Mass Spectrometer (IMS) instrument that will measure the full three-dimensional distribution functions of near-Earth main ion species (H+, He+, He++ and O+) at high time resolution (~ 150 ms for H+ , ~ 300 ms for He++) with energy resolution down to ~ 10% in the range 10 eV/q to 30 keV/q and angular resolution ~ 10°. Such high time resolution is achieved by mounting multiple sensors around the spacecraft body, in similar fashion to the MMS/FPI instrument. Each sensor combines a top-hat electrostatic analyzer with deflectors at the entrance together with a time-of-flight section to perform mass selection. IMS electronics includes a fast sweeping high voltage board that is required to make measurements at high cadence. Ion detection includes Micro Channel Plates (MCP) combined with Application-Specific Integrated Circuits (ASICs) for charge amplification, discrimination and time-to-digital conversion (TDC). IMS is being designed to address many of THOR science requirements, in particular ion heating and acceleration by turbulent fluctuations in foreshock, shock and magnetosheath regions. The IMS instrument is being designed and will be built by an international consortium of scientific institutes with main hardware contributions from France, USA, Japan and Germany.

Baseband pulse shaping techniques for nonlinearly amplified pi/4-QPSK and QAM systems

NASA Technical Reports Server (NTRS)

Feher, Kamilo

1991-01-01

A new generation of multi-stage pi/4-shifted QPSK and of superposed quadrature-amplitude-modulated (SQAM) modulators-coherent demodulators (modems) and of continuous phase modulated (CPM)-gaussian premodulation filtered minimum-shift-keying (MGMSK) systems is proposed and studied. These modems will lead to bandwidth and power efficient satellite communications systems designs. As an illustrative application, a baseband processing technique pi/4-controlled transition PSK (pi/4-CTPSK) is described. To develop a cost and power efficient design strategy, we assume that nonlinear, fully saturated high power amplifiers (HPA) are utilized in the satellite earth station transmitter and in the satellite transponder. Modem structures which could lead to application specific integrated circuit (ASIC) satellite on-board processing universal modem applications are also considered. Multistate GMSK (i.e., MGMSK) signal generation methods by means of two or more RF combined nonlinearly amplified SQAM modems and by one multistate (in-phase and quadrature-baseband premodulation filtered-superposed) SQAM architecture and one RF nonlinear amplifier are studied. During the SQAM modem development phase we investigate the potential system advantages of the pi/4-shifted logic. The bandwidth efficiency of the proposed multistate GMSK and baseband filtered PAM-FM modulator (a new class in the CPM family) will be significantly higher than that of conventional G-MSK systems. To optimize the practical P(sub e) = f((E sub b)/(N sub o)) performance we consider improved coherent demodulation MGMSK structures such as deviated-frequency locking coherent demodulators. For relative low bit rate SATCOM applications, e.g., bit rates less than 300 kb/s, phase noise tracking cancellation (for fixed site earth station) and phase noise cancellation as well as Doppler compensation (for satellite to mobile earth station) applications may be required. We study digital channel sounding methods which could cancel the phase noise-caused degradations of CPM and GMSK modems.

Flexible Architecture for FPGAs in Embedded Systems

NASA Technical Reports Server (NTRS)

Clark, Duane I.; Lim, Chester N.

2012-01-01

Commonly, field-programmable gate arrays (FPGAs) being developed in cPCI embedded systems include the bus interface in the FPGA. This complicates the development because the interface is complicated and requires a lot of development time and FPGA resources. In addition, flight qualification requires a substantial amount of time be devoted to just this interface. Another complication of putting the cPCI interface into the FPGA being developed is that configuration information loaded into the device by the cPCI microprocessor is lost when a new bit file is loaded, requiring cumbersome operations to return the system to an operational state. Finally, SRAM-based FPGAs are typically programmed via specialized cables and software, with programming files being loaded either directly into the FPGA, or into PROM devices. This can be cumbersome when doing FPGA development in an embedded environment, and does not have an easy path to flight. Currently, FPGAs used in space applications are usually programmed via multiple space-qualified PROM devices that are physically large and require extra circuitry (typically including a separate one-time programmable FPGA) to enable them to be used for this application. This technology adds a cPCI interface device with a simple, flexible, high-performance backend interface supporting multiple backend FPGAs. It includes a mechanism for programming the FPGAs directly via the microprocessor in the embedded system, eliminating specialized hardware, software, and PROM devices and their associated circuitry. It has a direct path to flight, and no extra hardware and minimal software are required to support reprogramming in flight. The device added is currently a small FPGA, but an advantage of this technology is that the design of the device does not change, regardless of the application in which it is being used. This means that it needs to be qualified for flight only once, and is suitable for one-time programmable devices or an application specific integrated circuit (ASIC). An application programming interface (API) further reduces the development time needed to use the interface device in a system.

SCOC3: A Brand New Heart for Space Mission

NASA Astrophysics Data System (ADS)

Poupat, Jean-Luc; Lefevre, Aurelien

2012-08-01

Satellites are controlled via a platform On Board Computer (OBC) that manages different parameters (attitude, orbit, modes, temperatures ...) with respect to its payload mission (telecommunication, earth observation, scientific mission). The platform OBC is connected to the satellite and the ground control via digital links, and executes on board software.The main functions of a platform OBC are to provide the satellite flight segment with the following features: o Processing resources for the flight mission softwareo TM/TC services and interfaces with the RF communication chaino General communication services with the Avionics and payload equipments through on- board communication buso Time synchronization and distributiono Failure tolerant architecture based on the use of redounded reconfiguration units and redundancy implementationIn order to reach an ultimate level of integration, Astrium has designed an ASIC gathering on a single chip all these required digital functions: the SCOC3 ASIC.This paper presents in a first part the major innovations introduced by Astrium for SCOC3, in a second part the development tools associated to SCOC3, and in a third part the status concerning its commercialization.

The endo-rectal probe prototype for the TOPEM project

NASA Astrophysics Data System (ADS)

Musico, Paolo; TOPEM Collaboration

2016-07-01

The TOPEM project was funded by INFN with the aim of studying the design of a TOF-PET system dedicated to prostate imaging. During last year a big effort was put into building the prototype of the endo-rectal probe from all point of view: mechanical, thermal, electrical. A dedicated integrated circuit was adopted to have the minimum dimensions: the TOFPET ASIC. The system is composed by a LYSO pixellated crystal which is seen by a 128 SiPM matrix on both surfaces: this permits Depth Of Interaction (DOI) measurement. The 4 needed ASICs are handled by a FPGA board which transmits the acquired data over an UDP connection. The external container was made using 3-D printing technology: internal channels on the external surface permit the flowing of controlled temperature (≈35 °C) water. Electronic components power is dissipated using an internal air flow kept at lower temperature (≈20 °C). The probe is MR compatible: a dedicated small antenna can be accommodated in the container. This will permit simultaneous imaging in MRI and PET systems.

Design and performance of a custom ASIC digitizer for wire chamber readout in 65 nm CMOS technology

NASA Astrophysics Data System (ADS)

Lee, M. J.; Brown, D. N.; Chang, J. K.; Ding, D.; Gnani, D.; Grace, C. R.; Jones, J. A.; Kolomensky, Y. G.; von der Lippe, H.; Mcvittie, P. J.; Stettler, M. W.; Walder, J.-P.

2015-06-01

We present the design and performance of a prototype ASIC digitizer for integrated wire chamber readout, implemented in 65 nm commercial CMOS technology. Each channel of the 4-channel prototype is composed of two 16-bit Time-to-Digital Converters (TDCs), one 8-bit Analog-to-Digital Converter (ADC), a front-end preamplifier and shaper, plus digital and analog buffers that support a variety of digitization chains. The prototype has a multiplexed digital backend that executes a state machine, distributes control and timing signals, and buffers data for serial output. Laboratory bench tests measure the absolute TDC resolution between 74 ps and 480 ps, growing with the absolute delay, and a relative time resolution of 19 ps. Resolution outliers due to cross-talk between clock signals and supply or reference voltages are seen. After calibration, the ADC displays good linearity and noise performance, with an effective number of bits of 6.9. Under normal operating conditions the circuit consumes 32 mW per channel. Potential design improvements to address the resolution drift and tails are discussed.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lemley, James; Furey, Michael

The BNL Microelectronics group has designed a series of custom ASICs in CMOS technol­ogy for use with Cadmium-Zink-Telluride (CdZnTe) radiation detectors, primarily in the field of nuclear spectroscopy. An increased demand for CdZnTe based detection systems that can operate in high flux X-ray inspection equipment makes it necessary to develop a new type of signal processing ASIC, one which can achieve moderate energy resolution at very high count rate. This work covers the development of a high-rate, low power ASIC that classifies events into one of five energy windows at rates up to 2 MHz/channel.

Performance study of SKIROC2/A ASIC for ILD Si-W ECAL

NASA Astrophysics Data System (ADS)

Suehara, T.; Sekiya, I.; Callier, S.; Balagura, V.; Boudry, V.; Brient, J.-C.; de la Taille, C.; Kawagoe, K.; Irles, A.; Magniette, F.; Nanni, J.; Pöschl, R.; Yoshioka, T.

2018-03-01

The ILD Si-W ECAL is a sampling calorimeter with tungsten absorber and highly segmented silicon layers for the International Large Detector (ILD), one of the two detector concepts for the International Linear Collider. SKIROC2 is an ASIC for the ILD Si-W ECAL. To investigate the issues found in prototype detectors, we prepared dedicated ASIC evaluation boards with either BGA sockets or directly soldered SKIROC2. We report a performance study with the evaluation boards, including signal-to-noise ratio and TDC performance with comparing SKIROC2 and an updated version, SKIROC2A.

Acid-sensing ion channels in pain and disease

PubMed Central

Wemmie, John A.; Taugher, Rebecca J.; Kreple, Collin J.

2015-01-01

Why do neurons sense extracellular acid? In large part, this question has driven increasing investigation on acid-sensing ion channels (ASICs) in the CNS and the peripheral nervous system for the past two decades. Significant progress has been made in understanding the structure and function of ASICs at the molecular level. Studies aimed at clarifying their physiological importance have suggested roles for ASICs in pain, neurological and psychiatric disease. This Review highlights recent findings linking these channels to physiology and disease. In addition, it discusses some of the implications for therapy and points out questions that remain unanswered. PMID:23783197

Acid-sensing ion channels in pain and disease.

PubMed

Wemmie, John A; Taugher, Rebecca J; Kreple, Collin J

2013-07-01

Why do neurons sense extracellular acid? In large part, this question has driven increasing investigation on acid-sensing ion channels (ASICs) in the CNS and the peripheral nervous system for the past two decades. Significant progress has been made in understanding the structure and function of ASICs at the molecular level. Studies aimed at clarifying their physiological importance have suggested roles for ASICs in pain, neurological and psychiatric disease. This Review highlights recent findings linking these channels to physiology and disease. In addition, it discusses some of the implications for therapy and points out questions that remain unanswered.

Genetic variation in the ASIC3 gene influences blood pressure levels in Taiwanese.

PubMed

Ko, Yu-Lin; Hsu, Lung-An; Wu, Semon; Teng, Ming-Sheng; Chang, Hsien-Hsun; Chen, Chih-Cheng; Cheng, Ching-Feng

2008-11-01

The acid-sensing ion channel 3 (ASIC3) is a ligand-gated cation channel activated by extracellular protons, and is associated with an exercise-induced pressor reflex and possibly autonomic imbalance. To test the statistical association between genetic polymorphisms of the ASIC3 gene and blood pressure (BP) variations in Taiwanese, 551 unrelated individuals (286 men and 265 women) were recruited from a routine health examination. The participants had no prior history of cardiovascular disease or medication use for hypertension. Six ASIC3 gene polymorphisms were genotyped; three were polymorphic, and only the rs2288646 polymorphism was associated with variations in BP among participants. Significantly higher systolic, diastolic, and mean BP were observed in participants carrying the rs2288646-A allele (P=0.034, 0.023, and 0.010, respectively). Significantly higher frequencies of the rs2288646-A-containing genotype were observed in normotensive, prehypertensive, and hypertensive subgroups (P for trend=0.026); and in those with higher systolic and diastolic BPs (P for trend=0.005 and P for trend=0.002, respectively). The association between the rs2288646-A allele and BP persisted even after adjustment for age, sex, BMI, and other metabolic factors. When a second independent group of 403 individuals was combined with the first group of 551 (n=954), a significantly higher frequency of the rs2288646-A-containing genotype was observed in participants with hypertension (9.7 vs. 4.0%, P=0.003). Our data showed an independent association between an ASIC3 genetic polymorphism and BP variations in Taiwanese. These results suggest that the ASIC3 may be involved in BP regulation.

A heteromeric Texas coral snake toxin targets acid-sensing ion channels to produce pain.

PubMed

Bohlen, Christopher J; Chesler, Alexander T; Sharif-Naeini, Reza; Medzihradszky, Katalin F; Zhou, Sharleen; King, David; Sánchez, Elda E; Burlingame, Alma L; Basbaum, Allan I; Julius, David

2011-11-16

Natural products that elicit discomfort or pain represent invaluable tools for probing molecular mechanisms underlying pain sensation. Plant-derived irritants have predominated in this regard, but animal venoms have also evolved to avert predators by targeting neurons and receptors whose activation produces noxious sensations. As such, venoms provide a rich and varied source of small molecule and protein pharmacophores that can be exploited to characterize and manipulate key components of the pain-signalling pathway. With this in mind, here we perform an unbiased in vitro screen to identify snake venoms capable of activating somatosensory neurons. Venom from the Texas coral snake (Micrurus tener tener), whose bite produces intense and unremitting pain, excites a large cohort of sensory neurons. The purified active species (MitTx) consists of a heteromeric complex between Kunitz- and phospholipase-A2-like proteins that together function as a potent, persistent and selective agonist for acid-sensing ion channels (ASICs), showing equal or greater efficacy compared with acidic pH. MitTx is highly selective for the ASIC1 subtype at neutral pH; under more acidic conditions (pH < 6.5), MitTx massively potentiates (>100-fold) proton-evoked activation of ASIC2a channels. These observations raise the possibility that ASIC channels function as coincidence detectors for extracellular protons and other, as yet unidentified, endogenous factors. Purified MitTx elicits robust pain-related behaviour in mice by activation of ASIC1 channels on capsaicin-sensitive nerve fibres. These findings reveal a mechanism whereby snake venoms produce pain, and highlight an unexpected contribution of ASIC1 channels to nociception. © 2011 Macmillan Publishers Limited. All rights reserved

Synthesis, Characterization and Optical Constants of Silicon Oxycarbide

NASA Astrophysics Data System (ADS)

Memon, Faisal Ahmed; Morichetti, Francesco; Abro, Muhammad Ishaque; Iseni, Giosue; Somaschini, Claudio; Aftab, Umair; Melloni, Andrea

2017-03-01

High refractive index glasses are preferred in integrated photonics applications to realize higher integration scale of passive devices. With a refractive index that can be tuned between SiO2 (1.45) and a-SiC (3.2), silicon oxycarbide SiOC offers this flexibility. In the present work, silicon oxycarbide thin films from 0.1 - 2.0 μm thickness are synthesized by reactive radio frequency magnetron sputtering a silicon carbide SiC target in a controlled argon and oxygen environment. The refractive index n and material extinction coefficient k of the silicon oxycarbide films are acquired with variable angle spectroscopic ellipsometry over the UV-Vis-NIR wavelength range. Keeping argon and oxygen gases in the constant ratio, the refractive index n is found in the range from 1.41 to 1.93 at 600 nm which is almost linearly dependent on RF power of sputtering. The material extinction coefficient k has been estimated to be less than 10-4 for the deposited silicon oxycarbide films in the visible and near-infrared wavelength regions. Morphological and structural characterizations with SEM and XRD confirms the amorphous phase of the SiOC films.

Radiation Effects and Hardening Techniques for Spacecraft Microelectronics

NASA Astrophysics Data System (ADS)

Gambles, J. W.; Maki, G. K.

2002-01-01

The natural radiation from the Van Allen belts, solar flares, and cosmic rays found outside of the protection of the earth's atmosphere can produce deleterious effects on microelectronics used in space systems. Historically civil space agencies and the commercial satellite industry have been able to utilize components produced in special radiation hardened fabrication process foundries that were developed during the 1970s and 1980s under sponsorship of the Departments of Defense (DoD) and Energy (DoE). In the post--cold war world the DoD and DoE push to advance the rad--hard processes has waned. Today the available rad--hard components lag two-plus technology node generations behind state- of-the-art commercial technologies. As a result space craft designers face a large performance gap when trying to utilize available rad--hard components. Compounding the performance gap problems, rad--hard components are becoming increasingly harder to get. Faced with the economic pitfalls associated with low demand versus the ever increasing investment required for integrated circuit manufacturing equipment most sources of rad--hard parts have simply exited this market in recent years, leaving only two domestic US suppliers of digital rad--hard components. This paper summarizes the radiation induced mechanisms that can cause digital microelectronics to fail in space, techniques that can be applied to mitigate these failure mechanisms, and ground based testing used to validate radiation hardness/tolerance. The radiation hardening techniques can be broken down into two classes, Hardness By Process (HBP) and Hardness By Design (HBD). Fortunately many HBD techniques can be applied to commercial fabrication processes providing space craft designer with radiation tolerant Application Specific Integrated Circuits (ASICs) that can bridge the performance gap between the special HBP foundries and the commercial state-of-the-art performance.

DS Sentry: an acquisition ASIC for smart, micro-power sensing applications

NASA Astrophysics Data System (ADS)

Liobe, John; Fiscella, Mark; Moule, Eric; Balon, Mark; Bocko, Mark; Ignjatovic, Zeljko

2011-06-01

Unattended ground monitoring that combines seismic and acoustic information can be a highly valuable tool in intelligence gathering; however there are several prerequisites for this approach to be viable. The first is high sensitivity as well as the ability to discriminate real threats from noise and other spurious signals. By combining ground sensing with acoustic and image monitoring this requirement may be achieved. Moreover, the DS Sentry®provides innate spurious signal rejection by the "active-filtering" technique employed as well as embedding some basic statistical analysis. Another primary requirement is spatial and temporal coverage. The ideal is uninterrupted, long-term monitoring of an area. Therefore, sensors should be densely deployed and consume very little power. Furthermore, sensors must be inexpensive and easily deployed to allow dense placements in critical areas. The ADVIS DS Sentry®, which is a fully-custom integrated circuit that enables smart, micro-power monitoring of dynamic signals, is the foundation of the proposed system. The core premise behind this technology is the use of an ultra-low power front-end for active monitoring of dynamic signals in conjunction with a highresolution, Σ Δ-based analog-to-digital converter, which utilizes a novel noise rejection technique and is only employed when a potential threat has been detected. The DS Sentry® can be integrated with seismic accelerometers and microphones and user-programmed to continuously monitor for signals with specific signatures such as impacts, footsteps, excavation noise, vehicle-induced ground vibrations, or speech, while consuming only microwatts of power. This will enable up to several years of continuous monitoring on a single small battery while concurrently mitigating false threats.

Introduction to the Special Issue on Digital Signal Processing in Radio Astronomy

NASA Astrophysics Data System (ADS)

Price, D. C.; Kocz, J.; Bailes, M.; Greenhill, L. J.

2016-03-01

Advances in astronomy are intimately linked to advances in digital signal processing (DSP). This special issue is focused upon advances in DSP within radio astronomy. The trend within that community is to use off-the-shelf digital hardware where possible and leverage advances in high performance computing. In particular, graphics processing units (GPUs) and field programmable gate arrays (FPGAs) are being used in place of application-specific circuits (ASICs); high-speed Ethernet and Infiniband are being used for interconnect in place of custom backplanes. Further, to lower hurdles in digital engineering, communities have designed and released general-purpose FPGA-based DSP systems, such as the CASPER ROACH board, ASTRON Uniboard, and CSIRO Redback board. In this introductory paper, we give a brief historical overview, a summary of recent trends, and provide an outlook on future directions.

Flexible high speed CODEC

NASA Technical Reports Server (NTRS)

Wernlund, James V.

1993-01-01

HARRIS, under contract with NASA Lewis, has developed a hard decision BCH (Bose-Chaudhuri-Hocquenghem) triple error correcting block CODEC ASIC, that can be used in either a bursted or continuous mode. the ASIC contains both encoder and decoder functions, programmable lock thresholds, and PSK related functions. The CODEC provides up to 4 dB of coding gain for data rates up to 300 Mbps. The overhead is selectable from 7/8 to 15/16 resulting in minimal band spreading, for a given BER. Many of the internal calculations are brought out enabling the CODEC to be incorporated in more complex designs. The ASIC has been tested in BPSK, QPSK and 16-ary PSK link simulators and found to perform to within 0.1 dB of theory for BER's of 10(exp -2) to 10(exp -9). The ASIC itself, being a hard decision CODEC, is not limited to PSK modulation formats. Unlike most hard decision CODEC's, the HARRIS CODEC doesn't upgrade BER performance significantly at high BER's but rather becomes transparent.

Test systems of the STS-XYTER2 ASIC: from wafer-level to in-system verification

NASA Astrophysics Data System (ADS)

Kasinski, Krzysztof; Zubrzycka, Weronika

2016-09-01

The STS/MUCH-XYTER2 ASIC is a full-size prototype chip for the Silicon Tracking System (STS) and Muon Chamber (MUCH) detectors in the new fixed-target experiment Compressed Baryonic Matter (CBM) at FAIR-center, Darmstadt, Germany. The STS assembly includes more than 14000 ASICs. The complicated, time-consuming, multi-step assembly process of the detector building blocks and tight quality assurance requirements impose several intermediate testing to be performed for verifying crucial assembly steps (e.g. custom microcable tab-bonding before wire-bonding to the PCB) and - if necessary - identifying channels or modules for rework. The chip supports the multi-level testing with different probing / contact methods (wafer probe-card, pogo-probes, in-system tests). A huge number of ASICs to be tested restricts the number and kind of tests possible to be performed within a reasonable time. The proposed architectures of test stand equipment and a brief summary of methodologies are presented in this paper.

ASICs Approach for the Implementation of a Symmetric Triangular Fuzzy Coprocessor and Its Application to Adaptive Filtering

NASA Technical Reports Server (NTRS)

Starks, Scott; Abdel-Hafeez, Saleh; Usevitch, Bryan

1997-01-01

This paper discusses the implementation of a fuzzy logic system using an ASICs design approach. The approach is based upon combining the inherent advantages of symmetric triangular membership functions and fuzzy singleton sets to obtain a novel structure for fuzzy logic system application development. The resulting structure utilizes a fuzzy static RAM to store the rule-base and the end-points of the triangular membership functions. This provides advantages over other approaches in which all sampled values of membership functions for all universes must be stored. The fuzzy coprocessor structure implements the fuzzification and defuzzification processes through a two-stage parallel pipeline architecture which is capable of executing complex fuzzy computations in less than 0.55us with an accuracy of more than 95%, thus making it suitable for a wide range of applications. Using the approach presented in this paper, a fuzzy logic rule-base can be directly downloaded via a host processor to an onchip rule-base memory with a size of 64 words. The fuzzy coprocessor's design supports up to 49 rules for seven fuzzy membership functions associated with each of the chip's two input variables. This feature allows designers to create fuzzy logic systems without the need for additional on-board memory. Finally, the paper reports on simulation studies that were conducted for several adaptive filter applications using the least mean squared adaptive algorithm for adjusting the knowledge rule-base.

Configurable test bed design for nanosats to qualify commercial and customized integrated circuits

NASA Astrophysics Data System (ADS)

Guareschi, W.; Azambuja, J.; Kastensmidt, F.; Reis, R.; Durao, O.; Schuch, N.; Dessbesel, G.

The use of small satellites has increased substantially in recent years due to the reduced cost of their development and launch, as well to the flexibility offered by commercial components. The test bed is a platform that allows components to be evaluated and tested in space. It is a flexible platform, which can be adjusted to a wide quantity of components and interfaces. This work proposes the design and implementation of a test bed suitable for test and evaluation of commercial circuits used in nanosatellites. The development of such a platform allows developers to reduce the efforts in the integration of components and therefore speed up the overall system development time. The proposed test bed is a configurable platform implemented using a Field Programmable Gate Array (FPGA) that controls the communication protocols and connections to the devices under test. The Flash-based ProASIC3E FPGA from Microsemi is used as a control system. This adaptive system enables the control of new payloads and softcores for test and validation in space. Thus, the integration can be easily performed through configuration parameters. It is intended for modularity. Each component connected to the test bed can have a specific interface programmed using a hardware description language (HDL). The data of each component is stored in embedded memories. Each component has its own memory space. The size of the allocated memory can be also configured. The data transfer priority can be set and packaging can be added to the logic, when needed. Communication with peripheral devices and with the Onboard Computer (OBC) is done through the pre-implemented protocols, such as I2C (Inter-Integrated Circuit), SPI (Serial Peripheral Interface) and external memory control. In loco primary tests demonstrated the control system's functionality. The commercial ProASIC3E FPGA family is not space-flight qualified, but tests have been made under Total Ionizing Dose (TID) showing its robustness up to 25 kr- ds (Si). When considering proton and heavy ions, flash-based FPGAs provide immunity to configuration loss and low bit-flips susceptibility in flash memory. In this first version of the test bed two components are connected to the controller FPGA: a commercial magnetometer and a hardened test chip. The embedded FPGA implements a Single Event Effects (SEE) hardened microprocessor and few other soft-cores to be used in space. This test bed will be used in the NanoSatC-BR1, the first Brazilian Cubesat scheduled to be launched in mid-2013.

Acid-Sensing Ion Channel Pharmacology, Past, Present, and Future ….

PubMed

Rash, Lachlan D

2017-01-01

pH is one of the most strictly controlled parameters in mammalian physiology. An extracellular pH of ~7.4 is crucial for normal physiological processes, and perturbations to this have profound effects on cell function. Acidic microenvironments occur in many physiological and pathological conditions, including inflammation, bone remodeling, ischemia, trauma, and intense synaptic activity. Cells exposed to these conditions respond in different ways, from tumor cells that thrive to neurons that are either suppressed or hyperactivated, often fatally. Acid-sensing ion channels (ASICs) are primary pH sensors in mammals and are expressed widely in neuronal and nonneuronal cells. There are six main subtypes of ASICs in rodents that can form homo- or heteromeric channels resulting in many potential combinations. ASICs are present and activated under all of the conditions mentioned earlier, suggesting that they play an important role in how cells respond to acidosis. Compared to many other ion channel families, ASICs were relatively recently discovered-1997-and there is a substantial lack of potent, subtype-selective ligands that can be used to elucidate their structural and functional properties. In this chapter I cover the history of ASIC channel pharmacology, which began before the proteins were even identified, and describe the current arsenal of tools available, their limitations, and take a glance into the future to predict from where new tools are likely to emerge. © 2017 Elsevier Inc. All rights reserved.

Architecture of a general purpose embedded Slow-Control Adapter ASIC for future high-energy physics experiments

NASA Astrophysics Data System (ADS)

Gabrielli, Alessandro; Loddo, Flavio; Ranieri, Antonio; De Robertis, Giuseppe

2008-10-01

This work is aimed at defining the architecture of a new digital ASIC, namely Slow-Control Adapter (SCA), which will be designed in a commercial 130-nm CMOS technology. This chip will be embedded within a high-speed data acquisition optical link (GBT) to control and monitor the front-end electronics in future high-energy physics experiments. The GBT link provides a transparent transport layer between the SCA and control electronics in the counting room. The proposed SCA supports a variety of common bus protocols to interface with end-user general-purpose electronics. Between the GBT and the SCA a standard 100 Mb/s IEEE-802.3 compatible protocol will be implemented. This standard protocol allows off-line tests of the prototypes using commercial components that support the same standard. The project is justified because embedded applications in modern large HEP experiments require particular care to assure the lowest possible power consumption, still offering the highest reliability demanded by very large particle detectors.

Scalable, efficient ASICS for the square kilometre array: From A/D conversion to central correlation

NASA Astrophysics Data System (ADS)

Schmatz, M. L.; Jongerius, R.; Dittmann, G.; Anghel, A.; Engbersen, T.; van Lunteren, J.; Buchmann, P.

2014-05-01

The Square Kilometre Array (SKA) is a future radio telescope, currently being designed by the worldwide radio-astronomy community. During the first of two construction phases, more than 250,000 antennas will be deployed, clustered in aperture-array stations. The antennas will generate 2.5 Pb/s of data, which needs to be processed in real time. For the processing stages from A/D conversion to central correlation, we propose an ASIC solution using only three chip architectures. The architecture is scalable - additional chips support additional antennas or beams - and versatile - it can relocate its receiver band within a range of a few MHz up to 4GHz. This flexibility makes it applicable to both SKA phases 1 and 2. The proposed chips implement an antenna and station processor for 289 antennas with a power consumption on the order of 600W and a correlator, including corner turn, for 911 stations on the order of 90 kW.

Integration of LCoS-SLM and LabVIEW based software to simulate fundamental optics, wave optics, and Fourier optics

NASA Astrophysics Data System (ADS)

Lyu, Bo-Han; Wang, Chen; Tsai, Chun-Wei

2017-08-01

Jasper Display Corp. (JDC) offer high reflectivity, high resolution Liquid Crystal on Silicon - Spatial Light Modulator (LCoS-SLM) which include an associated controller ASIC and LabVIEW based modulation software. Based on this LCoS-SLM, also called Education Kit (EDK), we provide a training platform which includes a series of optical theory and experiments to university students. This EDK not only provides a LabVIEW based operation software to produce Computer Generated Holograms (CGH) to generate some basic diffraction image or holographic image, but also provides simulation software to verity the experiment results simultaneously. However, we believe that a robust LCoSSLM, operation software, simulation software, training system, and training course can help students to study the fundamental optics, wave optics, and Fourier optics more easily. Based on these fundamental knowledges, they could develop their unique skills and create their new innovations on the optoelectronic application in the future.

Mobile Ultrasound Plane Wave Beamforming on iPhone or iPad using Metal- based GPU Processing

NASA Astrophysics Data System (ADS)

Hewener, Holger J.; Tretbar, Steffen H.

Mobile and cost effective ultrasound devices are being used in point of care scenarios or the drama room. To reduce the costs of such devices we already presented the possibilities of consumer devices like the Apple iPad for full signal processing of raw data for ultrasound image generation. Using technologies like plane wave imaging to generate a full image with only one excitation/reception event the acquisition times and power consumption of ultrasound imaging can be reduced for low power mobile devices based on consumer electronics realizing the transition from FPGA or ASIC based beamforming into more flexible software beamforming. The massive parallel beamforming processing can be done with the Apple framework "Metal" for advanced graphics and general purpose GPU processing for the iOS platform. We were able to integrate the beamforming reconstruction into our mobile ultrasound processing application with imaging rates up to 70 Hz on iPad Air 2 hardware.

Resource and Performance Evaluations of Fixed Point QRD-RLS Systolic Array through FPGA Implementation

NASA Astrophysics Data System (ADS)

Yokoyama, Yoshiaki; Kim, Minseok; Arai, Hiroyuki

At present, when using space-time processing techniques with multiple antennas for mobile radio communication, real-time weight adaptation is necessary. Due to the progress of integrated circuit technology, dedicated processor implementation with ASIC or FPGA can be employed to implement various wireless applications. This paper presents a resource and performance evaluation of the QRD-RLS systolic array processor based on fixed-point CORDIC algorithm with FPGA. In this paper, to save hardware resources, we propose the shared architecture of a complex CORDIC processor. The required precision of internal calculation, the circuit area for the number of antenna elements and wordlength, and the processing speed will be evaluated. The resource estimation provides a possible processor configuration with a current FPGA on the market. Computer simulations assuming a fading channel will show a fast convergence property with a finite number of training symbols. The proposed architecture has also been implemented and its operation was verified by beamforming evaluation through a radio propagation experiment.

TOFPET 2: A high-performance circuit for PET time-of-flight

NASA Astrophysics Data System (ADS)

Di Francesco, Agostino; Bugalho, Ricardo; Oliveira, Luis; Rivetti, Angelo; Rolo, Manuel; Silva, Jose C.; Varela, Joao

2016-07-01

We present a readout and digitization ASIC featuring low-noise and low-power for time-of flight (TOF) applications using SiPMs. The circuit is designed in standard CMOS 110 nm technology, has 64 independent channels and is optimized for time-of-flight measurement in Positron Emission Tomography (TOF-PET). The input amplifier is a low impedance current conveyor based on a regulated common-gate topology. Each channel has quad-buffered analogue interpolation TDCs (time binning 20 ps) and charge integration ADCs with linear response at full scale (1500 pC). The signal amplitude can also be derived from the measurement of time-over-threshold (ToT). Simulation results show that for a single photo-electron signal with charge 200 (550) fC generated by a SiPM with (320 pF) capacitance the circuit has 24 (30) dB SNR, 75 (39) ps r.m.s. resolution, and 4 (8) mW power consumption. The event rate is 600 kHz per channel, with up to 2 MHz dark counts rejection.

Smart sensors development based on a distributed bus for microsystems applications

NASA Astrophysics Data System (ADS)

Ferrer, Carles; Lorente, Bibiana

2003-04-01

Our main objective in this work has been to develop a comunication system applicable between sensors and actuators and the data processing circuitry inside the microsystem in order to develop a flexible and modular architecture. This communication system is based on the use of a dedicated sensor bus composed by only two wires (a bidirectional data line and a clock line for sincronization). The basic philosophy of this development has been to create an IP model with VHDL for the bus driver that can be added to the sensor or the actuator to create an smart device that could be easily plugged with the other componets of the microsystem architecture. This methodology can be applied to a high integrated microsystem based on an extensively use of microelectronics technologies (ASICs, SoCs & MCMs). The reduced number of wires is an extraordinary advatage because produce a minimal interconnection between all the components and as a consequence the size of the microinstrument becomes smaller. The second aspect that we have considered in this development has been to reach a communication protocol that permits to built-up a very simple but robust bus driver interface that minimize the circuit overhead. This interconnection system has been applied to biomedical and aerospatial microsystems applications.

Hardware Acceleration of Sparse Cognitive Algorithms

DTIC Science & Technology

2016-05-01

Processor in Memory (PiM) extensions and a 65 nm ASIC version. They were compared against a 28 nm GPU baseline using the KTH video action recognition...30 Table 17. Memory Requirement of Proposed ASIC...for improvement of performance per unit of power for customized implementations of the Sparsey and Numenta Hierarchical Temporal Memory (HTM

Radiation Hardened Structured ASIC Platform with Compensation of Delay for Temperature and Voltage Variations for Multiple Redundant Temporal Voting Latch Technology

NASA Technical Reports Server (NTRS)

Ardalan, Sasan (Inventor)

2018-01-01

The invention relates to devices and methods of maintaining the current starved delay at a constant value across variations in voltage and temperature to increase the speed of operation of the sequential logic in the radiation hardened ASIC design.

CLARO: an ASIC for high rate single photon counting with multi-anode photomultipliers

NASA Astrophysics Data System (ADS)

Baszczyk, M.; Carniti, P.; Cassina, L.; Cotta Ramusino, A.; Dorosz, P.; Fiorini, M.; Gotti, C.; Kucewicz, W.; Malaguti, R.; Pessina, G.

2017-08-01

The CLARO is a radiation-hard 8-channel ASIC designed for single photon counting with multi-anode photomultiplier tubes. Each channel outputs a digital pulse when the input signal from the photomultiplier crosses a configurable threshold. The fast return to baseline, typically within 25 ns, and below 50 ns in all conditions, allows to count up to 107 hits/s on each channel, with a power consumption of about 1 mW per channel. The ASIC presented here is a much improved version of the first 4-channel prototype. The threshold can be precisely set in a wide range, between 30 ke- (5 fC) and 16 Me- (2.6 pC). The noise of the amplifier with a 10 pF input capacitance is 3.5 ke- (0.6 fC) RMS. All settings are stored in a 128-bit configuration and status register, protected against soft errors with triple modular redundancy. The paper describes the design of the ASIC at transistor-level, and demonstrates its performance on the test bench.

Loss of Acid Sensing Ion Channel-1a and Bicarbonate Administration Attenuate the Severity of Traumatic Brain Injury

PubMed Central

Yin, Terry; Lindley, Timothy E.; Albert, Gregory W.; Ahmed, Raheel; Schmeiser, Peter B.; Grady, M. Sean; Howard, Matthew A.; Welsh, Michael J.

2013-01-01

Traumatic brain injury (TBI) is a common cause of morbidity and mortality in people of all ages. Following the acute mechanical insult, TBI evolves over the ensuing minutes and days. Understanding the secondary factors that contribute to TBI might suggest therapeutic strategies to reduce the long-term consequences of brain trauma. To assess secondary factors that contribute to TBI, we studied a lateral fluid percussion injury (FPI) model in mice. Following FPI, the brain cortex became acidic, consistent with data from humans following brain trauma. Administering HCO3 − after FPI prevented the acidosis and reduced the extent of neurodegeneration. Because acidosis can activate acid sensing ion channels (ASICs), we also studied ASIC1a−/− mice and found reduced neurodegeneration after FPI. Both HCO3 − administration and loss of ASIC1a also reduced functional deficits caused by FPI. These results suggest that FPI induces cerebral acidosis that activates ASIC channels and contributes to secondary injury in TBI. They also suggest a therapeutic strategy to attenuate the adverse consequences of TBI. PMID:23991103

Chemical synthesis, 3D structure, and ASIC binding site of the toxin mambalgin-2.

PubMed

Schroeder, Christina I; Rash, Lachlan D; Vila-Farrés, Xavier; Rosengren, K Johan; Mobli, Mehdi; King, Glenn F; Alewood, Paul F; Craik, David J; Durek, Thomas

2014-01-20

Mambalgins are a novel class of snake venom components that exert potent analgesic effects mediated through the inhibition of acid-sensing ion channels (ASICs). The 57-residue polypeptide mambalgin-2 (Ma-2) was synthesized by using a combination of solid-phase peptide synthesis and native chemical ligation. The structure of the synthetic toxin, determined using homonuclear NMR, revealed an unusual three-finger toxin fold reminiscent of functionally unrelated snake toxins. Electrophysiological analysis of Ma-2 on wild-type and mutant ASIC1a receptors allowed us to identify α-helix 5, which borders on the functionally critical acidic pocket of the channel, as a major part of the Ma-2 binding site. This region is also crucial for the interaction of ASIC1a with the spider toxin PcTx1, thus suggesting that the binding sites for these toxins substantially overlap. This work lays the foundation for structure-activity relationship (SAR) studies and further development of this promising analgesic peptide. Copyright © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Antagonists to TRPV1, ASICs and P2X have a potential role to prevent the triggering of regional bone metabolic disorder and pain-like behavior in tail-suspended mice.

PubMed

Hanaka, Megumi; Iba, Kousuke; Dohke, Takayuki; Kanaya, Kumiko; Okazaki, Shunichiro; Yamashita, Toshihiko

2018-05-01

Our recent studies demonstrated that regional bone loss in the unloaded hind limbs of tail-suspended mice triggered pain-like behaviors due to the acidic environment in the bone induced by osteoclast activation. The aims of the present study were to examine whether TRPV1, ASIC and P2X (known as nociceptors) are expressed in bone, and whether the antagonists to those receptors affect the expression of osteoblast and osteoclast regulators, and prevent the triggering of not only pain-like behaviors but also high bone turnover conditions in tail-suspension model mice. The hind limb-unloaded mice were subjected to tail suspension with the hind limbs elevated for 14days. The effects of the TRPV1, ASIC3, P2X2/3 antagonists on pain-like behaviors as assessed by the von Frey test, paw flick test and spontaneous pain scale; the expressions of TRPV1, ASICs, and P2X2 in the bone; and the effects of those antagonists on osteoblast and osteoclast regulators were examined. In addition, we evaluated the preventive effect of continuous treatment with a TRPV1 antagonist on the trigger for pain-like behavior and bone loss in tail-suspended mice. Pain-like behaviors were significantly improved by the treatment with TRPV1, ASIC, P2X antagonists; TRPV1, ASICs and P2X were expressed in the bone tissues; and the antagonists to these receptors down-regulated the expression of osteoblast and osteoclast regulators in tail-suspended mice. In addition, continuous treatment with a TRPV1 antagonist during tail-suspension prevented the induction of pain-like behaviors and regional bone loss in the unloaded hind limbs. We, therefore, believe that those receptor antagonists have a potential role in preventing the triggering of skeletal pain with associated regional bone metabolic disorder. Copyright © 2018 Elsevier Inc. All rights reserved.

X-ray characterization of a multichannel smart-pixel array detector.

PubMed

Ross, Steve; Haji-Sheikh, Michael; Huntington, Andrew; Kline, David; Lee, Adam; Li, Yuelin; Rhee, Jehyuk; Tarpley, Mary; Walko, Donald A; Westberg, Gregg; Williams, George; Zou, Haifeng; Landahl, Eric

2016-01-01

The Voxtel VX-798 is a prototype X-ray pixel array detector (PAD) featuring a silicon sensor photodiode array of 48 × 48 pixels, each 130 µm × 130 µm × 520 µm thick, coupled to a CMOS readout application specific integrated circuit (ASIC). The first synchrotron X-ray characterization of this detector is presented, and its ability to selectively count individual X-rays within two independent arrival time windows, a programmable energy range, and localized to a single pixel is demonstrated. During our first trial run at Argonne National Laboratory's Advance Photon Source, the detector achieved a 60 ns gating time and 700 eV full width at half-maximum energy resolution in agreement with design parameters. Each pixel of the PAD holds two independent digital counters, and the discriminator for X-ray energy features both an upper and lower threshold to window the energy of interest discarding unwanted background. This smart-pixel technology allows energy and time resolution to be set and optimized in software. It is found that the detector linearity follows an isolated dead-time model, implying that megahertz count rates should be possible in each pixel. Measurement of the line and point spread functions showed negligible spatial blurring. When combined with the timing structure of the synchrotron storage ring, it is demonstrated that the area detector can perform both picosecond time-resolved X-ray diffraction and fluorescence spectroscopy measurements.

Parallel point-multiplication architecture using combined group operations for high-speed cryptographic applications

PubMed Central

Saeedi, Ehsan; Kong, Yinan

2017-01-01

In this paper, we propose a novel parallel architecture for fast hardware implementation of elliptic curve point multiplication (ECPM), which is the key operation of an elliptic curve cryptography processor. The point multiplication over binary fields is synthesized on both FPGA and ASIC technology by designing fast elliptic curve group operations in Jacobian projective coordinates. A novel combined point doubling and point addition (PDPA) architecture is proposed for group operations to achieve high speed and low hardware requirements for ECPM. It has been implemented over the binary field which is recommended by the National Institute of Standards and Technology (NIST). The proposed ECPM supports two Koblitz and random curves for the key sizes 233 and 163 bits. For group operations, a finite-field arithmetic operation, e.g. multiplication, is designed on a polynomial basis. The delay of a 233-bit point multiplication is only 3.05 and 3.56 μs, in a Xilinx Virtex-7 FPGA, for Koblitz and random curves, respectively, and 0.81 μs in an ASIC 65-nm technology, which are the fastest hardware implementation results reported in the literature to date. In addition, a 163-bit point multiplication is also implemented in FPGA and ASIC for fair comparison which takes around 0.33 and 0.46 μs, respectively. The area-time product of the proposed point multiplication is very low compared to similar designs. The performance (1Area×Time=1AT) and Area × Time × Energy (ATE) product of the proposed design are far better than the most significant studies found in the literature. PMID:28459831