Poly(methyl methacrylate) as a self-assembled gate dielectric for graphene field-effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sanne, A.; Movva, H. C. P.; Kang, S.

We investigate poly(methyl methacrylate) (PMMA) as a low thermal budget organic gate dielectric for graphene field effect-transistors (GFETs) based on a simple process flow. We show that high temperature baking steps above the glass transition temperature (∼130 °C) can leave a self-assembled, thin PMMA film on graphene, where we get a gate dielectric almost for “free” without additional atomic layer deposition type steps. Electrical characterization of GFETs with PMMA as a gate dielectric yields a dielectric constant of k = 3.0. GFETs with thinner PMMA dielectrics have a lower dielectric constant due to decreased polarization arising from neutralization of dipoles and charged carriersmore » as baking temperatures increase. The leakage through PMMA gate dielectric increases with decreasing dielectric thickness and increasing electric field. Unlike conventional high-k gate dielectrics, such low-k organic gate dielectrics are potentially attractive for devices such as the proposed Bilayer pseudoSpin Field-Effect Transistor or flexible high speed graphene electronics.« less

Effects of HfO2 encapsulation on electrical performances of few-layered MoS2 transistor with ALD HfO2 as back-gate dielectric.

PubMed

Xu, Jingping; Wen, Ming; Zhao, Xinyuan; Liu, Lu; Song, Xingjuan; Lai, Pui-To; Tang, Wing-Man

2018-08-24

The carrier mobility of MoS 2 transistors can be greatly improved by the screening role of high-k gate dielectric. In this work, atomic-layer deposited (ALD) HfO 2 annealed in NH 3 is used to replace SiO 2 as the gate dielectric to fabricate back-gated few-layered MoS 2 transistors, and good electrical properties are achieved with field-effect mobility (μ) of 19.1 cm 2 V -1 s -1 , subthreshold swing (SS) of 123.6 mV dec -1 and on/off ratio of 3.76 × 10 5 . Furthermore, enhanced device performance is obtained when the surface of the MoS 2 channel is coated by an ALD HfO 2 layer with different thicknesses (10, 15 and 20 nm), where the transistor with a 15 nm HfO 2 encapsulation layer exhibits the best overall electrical properties: μ = 42.1 cm 2 V -1 s -1 , SS = 87.9 mV dec -1 and on/off ratio of 2.72 × 10 6 . These improvements should be associated with the enhanced screening effect on charged-impurity scattering and protection from absorption of environmental gas molecules by the high-k encapsulation. The capacitance equivalent thickness of the back-gate dielectric (HfO 2 ) is only 6.58 nm, which is conducive to scaling of the MoS 2 transistors.

Nonvolatile MoS2 field effect transistors directly gated by single crystalline epitaxial ferroelectric

NASA Astrophysics Data System (ADS)

Lu, Zhongyuan; Serrao, Claudy; Khan, Asif Islam; You, Long; Wong, Justin C.; Ye, Yu; Zhu, Hanyu; Zhang, Xiang; Salahuddin, Sayeef

2017-07-01

We demonstrate non-volatile, n-type, back-gated, MoS2 transistors, placed directly on an epitaxial grown, single crystalline, PbZr0.2Ti0.8O3 (PZT) ferroelectric. The transistors show decent ON current (19 μA/μm), high on-off ratio (107), and a subthreshold swing of (SS ˜ 92 mV/dec) with a 100 nm thick PZT layer as the back gate oxide. Importantly, the ferroelectric polarization can directly control the channel charge, showing a clear anti-clockwise hysteresis. We have self-consistently confirmed the switching of the ferroelectric and corresponding change in channel current from a direct time-dependent measurement. Our results demonstrate that it is possible to obtain transistor operation directly on polar surfaces, and therefore, it should be possible to integrate 2D electronics with single crystalline functional oxides.

Top-gate pentacene-based organic field-effect transistor with amorphous rubrene gate insulator

NASA Astrophysics Data System (ADS)

Hiroki, Mizuha; Maeda, Yasutaka; Ohmi, Shun-ichiro

2018-02-01

The scaling of organic field-effect transistors (OFETs) is necessary for high-density integration and for this, OFETs with a top-gate configuration are required. There have been several reports of damageless lithography processes for organic semiconductor or insulator layers. However, it is still difficult to fabricate scaled OFETs with a top-gate configuration. In this study, the lift-off process and the device characteristics of the OFETs with a top-gate configuration utilizing an amorphous (α) rubrene gate insulator were investigated. We have confirmed that α-rubrene shows an insulating property, and its extracted linear mobility was 2.5 × 10-2 cm2/(V·s). The gate length and width were 10 and 60 µm, respectively. From these results, the OFET with a top-gate configuration utilizing an α-rubrene gate insulator is promising for the high-density integration of scaled OFETs.

Ion-selective electrolyte-gated field-effect transistors: prerequisites for proper functioning

NASA Astrophysics Data System (ADS)

Kofler, Johannes; Schmoltner, Kerstin; List-Kratochvil, Emil J. W.

2014-10-01

Electrolyte-gated organic field-effect transistors (EGOFETs) used as transducers and amplifiers in potentiometric sensors have recently attracted a significant amount of scientific interest. For that reason, the fundamental prerequisites to achieve a proper potentiometric signal amplification and transduction are examined. First, polarizable as well as non-polarizable semiconductor- and gate-electrolyte- interface combinations are investigated by normal pulse voltammetry. The results of these measurements are correlated with the corresponding transistor characteristics, clarifying the functional principle of EGOFETs and the requirements for high signal amplification. In addition to a good electrical performance, the EGOFET-transducers should also be compatible with the targeted sensing application. Accordingly, the influence of different gate materials and electrolytes on the sensing abilities, are discussed. Even though all physical requirements are met, EGOFETs typically exhibit irreversible degradation, if the gate potential exceeds a certain level. For that reason, EGOFETs have to be operated using a constant source-drain operation mode which is presented by means of an H+ (pH) sensitive ion-sensor.

Interface-Dependent Effective Mobility in Graphene Field-Effect Transistors

NASA Astrophysics Data System (ADS)

Ahlberg, Patrik; Hinnemo, Malkolm; Zhang, Shi-Li; Olsson, Jörgen

2018-03-01

By pretreating the substrate of a graphene field-effect transistor (G-FET), a stable unipolar transfer characteristic, instead of the typical V-shape ambipolar behavior, has been demonstrated. This behavior is achieved through functionalization of the SiO2/Si substrate that changes the SiO2 surface from hydrophilic to hydrophobic, in combination with postdeposition of an Al2O3 film by atomic layer deposition (ALD). Consequently, the back-gated G-FET is found to have increased apparent hole mobility and suppressed apparent electron mobility. Furthermore, with addition of a top-gate electrode, the G-FET is in a double-gate configuration with independent top- or back-gate control. The observed difference in mobility is shown to also be dependent on the top-gate bias, with more pronounced effect at higher electric field. Thus, the combination of top and bottom gates allows control of the G-FET's electron and hole mobilities, i.e., of the transfer behavior. Based on these observations, it is proposed that polar ligands are introduced during the ALD step and, depending on their polarization, result in an apparent increase of the effective hole mobility and an apparent suppressed effective electron mobility.

Sensing small neurotransmitter-enzyme interaction with nanoporous gated ion-sensitive field effect transistors.

PubMed

Kisner, Alexandre; Stockmann, Regina; Jansen, Michael; Yegin, Ugur; Offenhäusser, Andreas; Kubota, Lauro Tatsuo; Mourzina, Yulia

2012-01-15

Ion-sensitive field effect transistors with gates having a high density of nanopores were fabricated and employed to sense the neurotransmitter dopamine with high selectivity and detectability at micromolar range. The nanoporous structure of the gates was produced by applying a relatively simple anodizing process, which yielded a porous alumina layer with pores exhibiting a mean diameter ranging from 20 to 35 nm. Gate-source voltages of the transistors demonstrated a pH-dependence that was linear over a wide range and could be understood as changes in surface charges during protonation and deprotonation. The large surface area provided by the pores allowed the physical immobilization of tyrosinase, which is an enzyme that oxidizes dopamine, on the gates of the transistors, and thus, changes the acid-base behavior on their surfaces. Concentration-dependent dopamine interacting with immobilized tyrosinase showed a linear dependence into a physiological range of interest for dopamine concentration in the changes of gate-source voltages. In comparison with previous approaches, a response time relatively fast for detecting dopamine was obtained. Additionally, selectivity assays for other neurotransmitters that are abundantly found in the brain were examined. These results demonstrate that the nanoporous structure of ion-sensitive field effect transistors can easily be used to immobilize specific enzyme that can readily and selectively detect small neurotransmitter molecule based on its acid-base interaction with the receptor. Therefore, it could serve as a technology platform for molecular studies of neurotransmitter-enzyme binding and drugs screening. Copyright © 2011 Elsevier B.V. All rights reserved.

N-Channel field-effect transistors with floating gates for extracellular recordings.

PubMed

Meyburg, Sven; Goryll, Michael; Moers, Jürgen; Ingebrandt, Sven; Böcker-Meffert, Simone; Lüth, Hans; Offenhäusser, Andreas

2006-01-15

A field-effect transistor (FET) for recording extracellular signals from electrogenic cells is presented. The so-called floating gate architecture combines a complementary metal oxide semiconductor (CMOS)-type n-channel transistor with an independent sensing area. This concept allows the transistor and sensing area to be optimised separately. The devices are robust and can be reused several times. The noise level of the devices was smaller than of comparable non-metallised gate FETs. In addition to the usual drift of FET devices, we observed a long-term drift that has to be controlled for future long-term measurements. The device performance for extracellular signal recording was tested using embryonic rat cardiac myocytes cultured on fibronectin-coated chips. The extracellular cell signals were recorded before and after the addition of the cardioactive isoproterenol. The signal shapes of the measured action potentials were comparable to the non-metallised gate FETs previously used in similar experiments. The fabrication of the devices involved the process steps of standard CMOS that were necessary to create n-channel transistors. The implementation of a complete CMOS process would facilitate the integration of the logical circuits necessary for signal pre-processing on a chip, which is a prerequisite for a greater number of sensor spots in future layouts.

Leakage and field emission in side-gate graphene field effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Di Bartolomeo, A., E-mail: dibant@sa.infn.it; Iemmo, L.; Romeo, F.

We fabricate planar graphene field-effect transistors with self-aligned side-gate at 100 nm from the 500 nm wide graphene conductive channel, using a single lithographic step. We demonstrate side-gating below 1 V with conductance modulation of 35% and transconductance up to 0.5 mS/mm at 10 mV drain bias. We measure the planar leakage along the SiO{sub 2}/vacuum gate dielectric over a wide voltage range, reporting rapidly growing current above 15 V. We unveil the microscopic mechanisms driving the leakage, as Frenkel-Poole transport through SiO{sub 2} up to the activation of Fowler-Nordheim tunneling in vacuum, which becomes dominant at higher voltages. We report a field-emission current densitymore » as high as 1 μA/μm between graphene flakes. These findings are important for the miniaturization of atomically thin devices.« less

Frequency Response of Graphene Electrolyte-Gated Field-Effect Transistors

PubMed Central

McVay, Elaine; Palacios, Tomás

2018-01-01

This work develops the first frequency-dependent small-signal model for graphene electrolyte-gated field-effect transistors (EGFETs). Graphene EGFETs are microfabricated to measure intrinsic voltage gain, frequency response, and to develop a frequency-dependent small-signal model. The transfer function of the graphene EGFET small-signal model is found to contain a unique pole due to a resistive element, which stems from electrolyte gating. Intrinsic voltage gain, cutoff frequency, and transition frequency for the microfabricated graphene EGFETs are approximately 3.1 V/V, 1.9 kHz, and 6.9 kHz, respectively. This work marks a critical step in the development of high-speed chemical and biological sensors using graphene EGFETs. PMID:29414868

Utilizing self-assembled-monolayer-based gate dielectrics to fabricate molybdenum disulfide field-effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kawanago, Takamasa, E-mail: kawanago.t.ab@m.titech.ac.jp; Oda, Shunri

In this study, we apply self-assembled-monolayer (SAM)-based gate dielectrics to the fabrication of molybdenum disulfide (MoS{sub 2}) field-effect transistors. A simple fabrication process involving the selective formation of a SAM on metal oxides in conjunction with the dry transfer of MoS{sub 2} flakes was established. A subthreshold slope (SS) of 69 mV/dec and no hysteresis were demonstrated with the ultrathin SAM-based gate dielectrics accompanied by a low gate leakage current. The small SS and no hysteresis indicate the superior interfacial properties of the MoS{sub 2}/SAM structure. Cross-sectional transmission electron microscopy revealed a sharp and abrupt interface of the MoS{sub 2}/SAM structure.more » The SAM-based gate dielectrics are found to be applicable to the fabrication of low-voltage MoS{sub 2} field-effect transistors and can also be extended to various layered semiconductor materials. This study opens up intriguing possibilities of SAM-based gate dielectrics in functional electronic devices.« less

Stable Low-Voltage Operation Top-Gate Organic Field-Effect Transistors on Cellulose Nanocrystal Substrates

Treesearch

Cheng-Yin Wang; Canek Fuentes-Hernandez; Jen-Chieh Liu; Amir Dindar; Sangmoo Choi; Jeffrey P. Youngblood; Robert J. Moon; Bernard Kippelen

2015-01-01

We report on the performance and the characterization of top-gate organic field-effect transistors (OFETs), comprising a bilayer gate dielectric of CYTOP/ Al2O3 and a solution-processed semiconductor layer made of a blend of TIPS-pentacene:PTAA, fabricated on recyclable cellulose nanocrystal−glycerol (CNC/glycerol...

A pH sensor with a double-gate silicon nanowire field-effect transistor

NASA Astrophysics Data System (ADS)

Ahn, Jae-Hyuk; Kim, Jee-Yeon; Seol, Myeong-Lok; Baek, David J.; Guo, Zheng; Kim, Chang-Hoon; Choi, Sung-Jin; Choi, Yang-Kyu

2013-02-01

A pH sensor composed of a double-gate silicon nanowire field-effect transistor (DG Si-NW FET) is demonstrated. The proposed DG Si-NW FET allows the independent addressing of the gate voltage and hence improves the sensing capability through an application of asymmetric gate voltage between the two gates. One gate is a driving gate which controls the current flow, and the other is a supporting gate which amplifies the shift of the threshold voltage, which is a sensing metric, and which arises from changes in the pH. The pH signal is also amplified through modulation of the gate oxide thickness.

Low electron mobility of field-effect transistor determined by modulated magnetoresistance

NASA Astrophysics Data System (ADS)

Tauk, R.; Łusakowski, J.; Knap, W.; Tiberj, A.; Bougrioua, Z.; Azize, M.; Lorenzini, P.; Sakowicz, M.; Karpierz, K.; Fenouillet-Beranger, C.; Cassé, M.; Gallon, C.; Boeuf, F.; Skotnicki, T.

2007-11-01

Room temperature magnetotransport experiments were carried out on field-effect transistors in magnetic fields up to 10 T. It is shown that measurements of the transistor magnetoresistance and its first derivative with respect to the gate voltage allow the derivation of the electron mobility in the gated part of the transistor channel, while the access/contact resistances and the transistor gate length need not be known. We demonstrate the potential of this method using GaN and Si field-effect transistors and discuss its importance for mobility measurements in transistors with nanometer gate length.

Ultrathin strain-gated field effect transistor based on In-doped ZnO nanobelts

NASA Astrophysics Data System (ADS)

Zhang, Zheng; Du, Junli; Li, Bing; Zhang, Shuhao; Hong, Mengyu; Zhang, Xiaomei; Liao, Qingliang; Zhang, Yue

2017-08-01

In this work, we fabricated a strain-gated piezoelectric transistor based on single In-doped ZnO nanobelt with ±(0001) top/bottom polar surfaces. In the vertical structured transistor, the Pt tip of the AFM and Au film are used as source and drain electrode. The electrical transport performance of the transistor is gated by compressive strains. The working mechanism is attributed to the Schottky barrier height changed under the coupling effect of piezoresistive and piezoelectric. Uniquely, the transistor turns off under the compressive stress of 806 nN. The strain-gated transistor is likely to have important applications in high resolution mapping device and MEMS devices.

Strain-Gated Field Effect Transistor of a MoS2-ZnO 2D-1D Hybrid Structure.

PubMed

Chen, Libo; Xue, Fei; Li, Xiaohui; Huang, Xin; Wang, Longfei; Kou, Jinzong; Wang, Zhong Lin

2016-01-26

Two-dimensional (2D) molybdenum disulfide (MoS2) is an exciting material due to its unique electrical, optical, and piezoelectric properties. Owing to an intrinsic band gap of 1.2-1.9 eV, monolayer or a-few-layer MoS2 is used for fabricating field effect transistors (FETs) with high electron mobility and on/off ratio. However, the traditional FETs are controlled by an externally supplied gate voltage, which may not be sensitive enough to directly interface with a mechanical stimulus for applications in electronic skin. Here we report a type of top-pressure/force-gated field effect transistors (PGFETs) based on a hybrid structure of a 2D MoS2 flake and 1D ZnO nanowire (NW) array. Once an external pressure is applied, the piezoelectric polarization charges created at the tips of ZnO NWs grown on MoS2 act as a gate voltage to tune/control the source-drain transport property in MoS2. At a 6.25 MPa applied stimulus on a packaged device, the source-drain current can be tuned for ∼25%, equivalent to the results of applying an extra -5 V back gate voltage. Another type of PGFET with a dielectric layer (Al2O3) sandwiched between MoS2 and ZnO also shows consistent results. A theoretical model is proposed to interpret the received data. This study sets the foundation for applying the 2D material-based FETs in the field of artificial intelligence.

Phosphorus oxide gate dielectric for black phosphorus field effect transistors

NASA Astrophysics Data System (ADS)

Dickerson, W.; Tayari, V.; Fakih, I.; Korinek, A.; Caporali, M.; Serrano-Ruiz, M.; Peruzzini, M.; Heun, S.; Botton, G. A.; Szkopek, T.

2018-04-01

The environmental stability of the layered semiconductor black phosphorus (bP) remains a challenge. Passivation of the bP surface with phosphorus oxide, POx, grown by a reactive ion etch with oxygen plasma is known to improve photoluminescence efficiency of exfoliated bP flakes. We apply phosphorus oxide passivation in the fabrication of bP field effect transistors using a gate stack consisting of a POx layer grown by reactive ion etching followed by atomic layer deposition of Al2O3. We observe room temperature top-gate mobilities of 115 cm2 V-1 s-1 in ambient conditions, which we attribute to the low defect density of the bP/POx interface.

Tunable Mobility in Double-Gated MoTe2 Field-Effect Transistor: Effect of Coulomb Screening and Trap Sites.

PubMed

Ji, Hyunjin; Joo, Min-Kyu; Yi, Hojoon; Choi, Homin; Gul, Hamza Zad; Ghimire, Mohan Kumar; Lim, Seong Chu

2017-08-30

There is a general consensus that the carrier mobility in a field-effect transistor (FET) made of semiconducting transition-metal dichalcogenides (s-TMDs) is severely degraded by the trapping/detrapping and Coulomb scattering of carriers by ionic charges in the gate oxides. Using a double-gated (DG) MoTe 2 FET, we modulated and enhanced the carrier mobility by adjusting the top- and bottom-gate biases. The relevant mechanism for mobility tuning in this device was explored using static DC and low-frequency (LF) noise characterizations. In the investigations, LF-noise analysis revealed that for a strong back-gate bias the Coulomb scattering of carriers by ionized traps in the gate dielectrics is strongly screened by accumulation charges. This significantly reduces the electrostatic scattering of channel carriers by the interface trap sites, resulting in increased mobility. The reduction of the number of effective trap sites also depends on the gate bias, implying that owing to the gate bias, the carriers are shifted inside the channel. Thus, the number of active trap sites decreases as the carriers are repelled from the interface by the gate bias. The gate-controlled Coulomb-scattering parameter and the trap-site density provide new handles for improving the carrier mobility in TMDs, in a fundamentally different way from dielectric screening observed in previous studies.

Variations of Contact Resistance in Dual-Gated Monolayer Molybdenum Disulfide Transistors Depending on Gate Bias Selection

NASA Astrophysics Data System (ADS)

Tran, P. X.

2017-06-01

Monolayer molybdenum disulfide (MoS2) is considered an alternative two-dimensional material for high performance ultra-thin field-effect transistors. MoS2 is a triple atomic layer with a direct 1.8 eV bandgap. Bulk MoS2 has an additional indirect bandgap of 1.2 eV, which leads to high current on/off ratio around 108. Flakes of MoS2 can be obtained by mechanical exfoliation or grown by chemical vapor deposition. Intrinsic cut-off frequency of multilayer MoS2 transistor has reached 42 GHz. Chemical doping of MoS2 is challenging and results in reduction of contact resistance. This paper focuses on modeling of dual-gated monolayer MoS2 transistors with effective mobility of carriers varying from 0.6 cm2/V s to 750 cm2/V s. In agreement with experimental data, the model demonstrates that in back-gate bias devices, the contact resistance decreases almost exponentially with increasing gate bias, whereas in top-gate bias devices, the contact resistance stays invariant when varying gate bias.

Gate frequency sweep: An effective method to evaluate the dynamic performance of AlGaN/GaN power heterojunction field effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Santi, C. de; Meneghini, M., E-mail: matteo.meneghini@dei.unipd.it; Meneghesso, G.

2014-08-18

With this paper we propose a test method for evaluating the dynamic performance of GaN-based transistors, namely, gate-frequency sweep measurements: the effectiveness of the method is verified by characterizing the dynamic performance of Gate Injection Transistors. We demonstrate that this method can provide an effective description of the impact of traps on the transient performance of Heterojunction Field Effect Transistors, and information on the properties (activation energy and cross section) of the related defects. Moreover, we discuss the relation between the results obtained by gate-frequency sweep measurements and those collected by conventional drain current transients and double pulse characterization.

An analysis of the temperature dependence of the gate current in complementary heterojunction field-effect transistors

NASA Technical Reports Server (NTRS)

Cunningham, Thomas J.; Fossum, Eric R.; Baier, Steven M.

1992-01-01

The temperature dependence of the gate current versus the gate voltage in complementary heterojunction field-effect transistors (CHFET's) is examined. An analysis indicates that the gate conduction is due to a combination of thermionic emission, thermionic-field emission, and conduction through a temperature-activated resistance. The thermionic-field emission is consistent with tunneling through the AlGaAs insulator. The activation energy of the resistance is consistent with the ionization energy associated with the DX center in the AlGaAs. Methods reducing the gate current are discussed.

Scanning gate study of organic thin-film field-effect transistor

NASA Astrophysics Data System (ADS)

Aoki, N.; Sudou, K.; Matsusaki, K.; Okamoto, K.; Ochiai, Y.

2008-03-01

Scanning gate microscopy (SGM) has been applied for a study of organic thin-film field effect transistor (OFET). In contrast to one-dimensional nano-material such a carbon nanonube or nano-structure such a quantum point contact, visualization a transport characteristic of OFET channel is basically rather difficult since the channel width is much larger than the size of the SGM tip. Nevertheless, Schottky barriers are successfully visualized at the boundary between the metal electrodes and the OFET channel at ambient atmosphere.

A Probe for Measuring Spacecraft Surface Potentials Using a Direct-Gate Field Effect Transistor.

DTIC Science & Technology

1983-09-30

SURFACE POTENTIALS USING A DIRECT-GATE FIELD EFFECT TRANSISTOR Mark N. Horenstein Anton Havretic Trustees of Boston University 881 Commonwealth Avenue...1933 Transistor 6. PERFORMING ORG. REPORT NUMBER 7. AUTHOR(s) S. CONTRACT OR GRANT NUMBER(&) ’_5 Mark N. Horenstein Anton Mavretic F19628-82-K-00 34...at AFGL. These tests can be considered the bench mark tests for device performance, with all elements of the monitoring system optimized to eliminate

Extended Gate Field-Effect Transistor Biosensors for Point-Of-Care Testing of Uric Acid.

PubMed

Guan, Weihua; Reed, Mark A

2017-01-01

An enzyme-free redox potential sensor using off-chip extended-gate field effect transistor (EGFET) with a ferrocenyl-alkanethiol modified gold electrode has been used to quantify uric acid concentration in human serum and urine. Hexacyanoferrate (II) and (III) ions are used as redox reagent. The potentiometric sensor measures the interface potential on the ferrocene immobilized gold electrode, which is modulated by the redox reaction between uric acid and hexacyanoferrate ions. The device shows a near Nernstian response to uric acid and is highly specific to uric acid in human serum and urine. The interference that comes from glucose, bilirubin, ascorbic acid, and hemoglobin is negligible in the normal concentration range of these interferents. The sensor also exhibits excellent long term reliability and is regenerative. This extended gate field effect transistor based sensor is promising for point-of-care detection of uric acid due to the small size, low cost, and low sample volume consumption.

Influence of gate width on gate-channel carrier mobility in AlGaN/GaN heterostructure field-effect transistors

NASA Astrophysics Data System (ADS)

Yang, Ming; Ji, Qizheng; Gao, Zhiliang; Zhang, Shufeng; Lin, Zhaojun; Yuan, Yafei; Song, Bo; Mei, Gaofeng; Lu, Ziwei; He, Jihao

2017-11-01

For the fabricated AlGaN/GaN heterostructure field-effect transistors (HFETs) with different gate widths, the gate-channel carrier mobility is experimentally obtained from the measured current-voltage and capacitance-voltage curves. Under each gate voltage, the mobility gets lower with gate width increasing. Analysis shows that the phenomenon results from the polarization Coulomb field (PCF) scattering, which originates from the irregularly distributed polarization charges at the AlGaN/GaN interface. The device with a larger gate width is with a larger PCF scattering potential and a stronger PCF scattering intensity. As a function of gate width, PCF scattering potential shows a same trend with the mobility variation. And the theoretically calculated mobility values fits well with the experimentally obtained values. Varying gate widths will be a new perspective for the improvement of device characteristics by modulating the gate-channel carrier mobility.

H-terminated diamond field effect transistor with ferroelectric gate insulator

DOE Office of Scientific and Technical Information (OSTI.GOV)

Karaya, Ryota; Furuichi, Hiroki; Nakajima, Takashi

2016-06-13

An H-terminated diamond field-effect-transistor (FET) with a ferroelectric vinylidene fluoride (VDF)-trifluoroethylene (TrFE) copolymer gate insulator was fabricated. The VDF-TrFE film was deposited on the H-terminated diamond by the spin-coating method and low-temperature annealing was performed to suppress processing damage to the H-terminated diamond surface channel layer. The fabricated FET structure showed the typical properties of depletion-type p-channel FET and showed clear saturation of the drain current with a maximum value of 50 mA/mm. The drain current versus gate voltage curves of the proposed FET showed clockwise hysteresis loops due to the ferroelectricity of the VDF-TrFE gate insulator, and the memory windowmore » width was 19 V, when the gate voltage was swept from 20 to −20 V. The maximum on/off current ratio and the linear mobility were 10{sup 8} and 398 cm{sup 2}/V s, respectively. In addition, we modulated the drain current of the fabricated FET structure via the remnant polarization of the VDF-TrFE gate and obtained an on/off current ratio of 10{sup 3} without applying a DC gate voltage.« less

Tunable SnSe2 /WSe2 Heterostructure Tunneling Field Effect Transistor.

PubMed

Yan, Xiao; Liu, Chunsen; Li, Chao; Bao, Wenzhong; Ding, Shijin; Zhang, David Wei; Zhou, Peng

2017-09-01

The burgeoning 2D semiconductors can maintain excellent device electrostatics with an ultranarrow channel length and can realize tunneling by electrostatic gating to avoid deprivation of band-edge sharpness resulting from chemical doping, which make them perfect candidates for tunneling field effect transistors. Here this study presents SnSe 2 /WSe 2 van der Waals heterostructures with SnSe 2 as the p-layer and WSe 2 as the n-layer. The energy band alignment changes from a staggered gap band offset (type-II) to a broken gap (type-III) when changing the negative back-gate voltage to positive, resulting in the device operating as a rectifier diode (rectification ratio ~10 4 ) or an n-type tunneling field effect transistor, respectively. A steep average subthreshold swing of 80 mV dec -1 for exceeding two decades of drain current with a minimum of 37 mV dec -1 at room temperature is observed, and an evident trend toward negative differential resistance is also accomplished for the tunneling field effect transistor due to the high gate efficiency of 0.36 for single gate devices. The I ON /I OFF ratio of the transfer characteristics is >10 6 , accompanying a high ON current >10 -5 A. This work presents original phenomena of multilayer 2D van der Waals heterostructures which can be applied to low-power consumption devices. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Deep-submicron Graphene Field-Effect Transistors with State-of-Art fmax

PubMed Central

Lyu, Hongming; Lu, Qi; Liu, Jinbiao; Wu, Xiaoming; Zhang, Jinyu; Li, Junfeng; Niu, Jiebin; Yu, Zhiping; Wu, Huaqiang; Qian, He

2016-01-01

In order to conquer the short-channel effects that limit conventional ultra-scale semiconductor devices, two-dimensional materials, as an option of ultimate thin channels, receive wide attention. Graphene, in particular, bears great expectations because of its supreme carrier mobility and saturation velocity. However, its main disadvantage, the lack of bandgap, has not been satisfactorily solved. As a result, maximum oscillation frequency (fmax) which indicates transistors’ power amplification ability has been disappointing. Here, we present submicron field-effect transistors with specially designed low-resistance gate and excellent source/drain contact, and therefore significantly improved fmax. The fabrication was assisted by the advanced 8-inch CMOS back-end-of-line technology. A 200-nm-gate-length GFET achieves fT/fmax = 35.4/50 GHz. All GFET samples with gate lengths ranging from 200 nm to 400 nm possess fmax 31–41% higher than fT, closely resembling Si n-channel MOSFETs at comparable technology nodes. These results re-strengthen the promise of graphene field-effect transistors in next generation semiconductor electronics. PMID:27775009

Ferroelectric field-effect transistors based on solution-processed electrochemically exfoliated graphene

NASA Astrophysics Data System (ADS)

Heidler, Jonas; Yang, Sheng; Feng, Xinliang; Müllen, Klaus; Asadi, Kamal

2018-06-01

Memories based on graphene that could be mass produced using low-cost methods have not yet received much attention. Here we demonstrate graphene ferroelectric (dual-gate) field effect transistors. The graphene has been obtained using electrochemical exfoliation of graphite. Field-effect transistors are realized using a monolayer of graphene flakes deposited by the Langmuir-Blodgett protocol. Ferroelectric field effect transistor memories are realized using a random ferroelectric copolymer poly(vinylidenefluoride-co-trifluoroethylene) in a top gated geometry. The memory transistors reveal ambipolar behaviour with both electron and hole accumulation channels. We show that the non-ferroelectric bottom gate can be advantageously used to tune the on/off ratio.

Coupling between electrolyte and organic semiconductor in electrolyte-gated organic field effect transistors (Conference Presentation)

NASA Astrophysics Data System (ADS)

Biscarini, Fabio; Di Lauro, Michele; Berto, Marcello; Bortolotti, Carlo A.; Geerts, Yves H.; Vuillaume, Dominique

2016-11-01

Organic field effect transistors (OFET) operated in aqueous environments are emerging as ultra-sensitive biosensors and transducers of electrical and electrochemical signals from a biological environment. Their applications range from detection of biomarkers in bodily fluids to implants for bidirectional communication with the central nervous system. They can be used in diagnostics, advanced treatments and theranostics. Several OFET layouts have been demonstrated to be effective in aqueous operations, which are distinguished either by their architecture or by the respective mechanism of doping by the ions in the electrolyte solution. In this work we discuss the unification of the seemingly different architectures, such as electrolyte-gated OFET (EGOFET), organic electrochemical transistor (OECT) and dual-gate ion-sensing FET. We first demonstrate that these architectures give rise to the frequency-dependent response of a synapstor (synapse-like transistor), with enhanced or depressed modulation of the output current depending on the frequency of the time-dependent gate voltage. This behavior that was reported for OFETs with embedded metal nanoparticles shows the existence of a capacitive coupling through an equivalent network of RC elements. Upon the systematic change of ions in the electrolyte and the morphology of the charge transport layer, we show how the time scale of the synapstor is changed. We finally show how the substrate plays effectively the role of a second bottom gate, whose potential is actually fixed by the pH/composition of the electrolyte and the gate voltage applied.

Using Ultrathin Parylene Films as an Organic Gate Insulator in Nanowire Field-Effect Transistors.

PubMed

Gluschke, J G; Seidl, J; Lyttleton, R W; Carrad, D J; Cochrane, J W; Lehmann, S; Samuelson, L; Micolich, A P

2018-06-27

We report the development of nanowire field-effect transistors featuring an ultrathin parylene film as a polymer gate insulator. The room temperature, gas-phase deposition of parylene is an attractive alternative to oxide insulators prepared at high temperatures using atomic layer deposition. We discuss our custom-built parylene deposition system, which is designed for reliable and controlled deposition of <100 nm thick parylene films on III-V nanowires standing vertically on a growth substrate or horizontally on a device substrate. The former case gives conformally coated nanowires, which we used to produce functional Ω-gate and gate-all-around structures. These give subthreshold swings as low as 140 mV/dec and on/off ratios exceeding 10 3 at room temperature. For the gate-all-around structure, we developed a novel fabrication strategy that overcomes some of the limitations with previous lateral wrap-gate nanowire transistors. Finally, we show that parylene can be deposited over chemically treated nanowire surfaces, a feature generally not possible with oxides produced by atomic layer deposition due to the surface "self-cleaning" effect. Our results highlight the potential for parylene as an alternative ultrathin insulator in nanoscale electronic devices more broadly, with potential applications extending into nanobioelectronics due to parylene's well-established biocompatible properties.

Universal core model for multiple-gate field-effect transistors with short channel and quantum mechanical effects

NASA Astrophysics Data System (ADS)

Shin, Yong Hyeon; Bae, Min Soo; Park, Chuntaek; Park, Joung Won; Park, Hyunwoo; Lee, Yong Ju; Yun, Ilgu

2018-06-01

A universal core model for multiple-gate (MG) field-effect transistors (FETs) with short channel effects (SCEs) and quantum mechanical effects (QMEs) is proposed. By using a Young’s approximation based solution for one-dimensional Poisson’s equations the total inversion charge density (Q inv ) in the channel is modeled for double-gate (DG) and surrounding-gate SG (SG) FETs, following which a universal charge model is derived based on the similarity of the solutions, including for quadruple-gate (QG) FETs. For triple-gate (TG) FETs, the average of DG and QG FETs are used. A SCEs model is also proposed considering the potential difference between the channel’s surface and center. Finally, a QMEs model for MG FETs is developed using the quantum correction compact model. The proposed universal core model is validated on commercially available three-dimensional ATLAS numerical simulations.

Ambipolar transport of silver nanoparticles decorated graphene oxide field effect transistors

NASA Astrophysics Data System (ADS)

Sarkar, Kalyan Jyoti; Sarkar, K.; Pal, B.; Kumar, Aparabal; Das, Anish; Banerji, P.

2018-05-01

In this article, we report ambipolar field effect transistor (FET) by using graphene oxide (GO) as a gate dielectric material for silver nanoparticles (AgNPs) decorated GO channel layer. GO was synthesized by Hummers' method. The AgNPs were prepared via photochemical reduction of silver nitrate solution by using monoethanolamine as a reducing agent. Morphological properties of channel layer were characterized by Field Effect Scanning Electron Microscopy (FESEM). Fourier Transform Infrared Spectroscopy (FTIR) was carried out to characterize GO thin film. For device fabrication gold (Au) was deposited as source-drain contact and aluminum (Al) was taken as bottom contact. Electrical measurements were performed by back gate configuration. Ambipolar transport behavior was explained from transfer characteristics. A maximum electron mobiliy of 6.65 cm2/Vs and a hole mobility of 2.46 cm2/Vs were extracted from the transfer characteristics. These results suggest that GO is a potential candidate as a gate dielectric material for thin film transistor applications and also provides new insights in GO based research.

Physical Modeling of Gate-Controlled Schottky Barrier Lowering of Metal-Graphene Contacts in Top-Gated Graphene Field-Effect Transistors

NASA Astrophysics Data System (ADS)

Mao, Ling-Feng; Ning, Huansheng; Huo, Zong-Liang; Wang, Jin-Yan

2015-12-01

A new physical model of the gate controlled Schottky barrier height (SBH) lowering in top-gated graphene field-effect transistors (GFETs) under saturation bias condition is proposed based on the energy conservation equation with the balance assumption. The theoretical prediction of the SBH lowering agrees well with the experimental data reported in literatures. The reduction of the SBH increases with the increasing of gate voltage and relative dielectric constant of the gate oxide, while it decreases with the increasing of oxide thickness, channel length and acceptor density. The magnitude of the reduction is slightly enhanced under high drain voltage. Moreover, it is found that the gate oxide materials with large relative dielectric constant (>20) have a significant effect on the gate controlled SBH lowering, implying that the energy relaxation of channel electrons should be taken into account for modeling SBH in GFETs.

Physical Modeling of Gate-Controlled Schottky Barrier Lowering of Metal-Graphene Contacts in Top-Gated Graphene Field-Effect Transistors.

PubMed

Mao, Ling-Feng; Ning, Huansheng; Huo, Zong-Liang; Wang, Jin-Yan

2015-12-17

A new physical model of the gate controlled Schottky barrier height (SBH) lowering in top-gated graphene field-effect transistors (GFETs) under saturation bias condition is proposed based on the energy conservation equation with the balance assumption. The theoretical prediction of the SBH lowering agrees well with the experimental data reported in literatures. The reduction of the SBH increases with the increasing of gate voltage and relative dielectric constant of the gate oxide, while it decreases with the increasing of oxide thickness, channel length and acceptor density. The magnitude of the reduction is slightly enhanced under high drain voltage. Moreover, it is found that the gate oxide materials with large relative dielectric constant (>20) have a significant effect on the gate controlled SBH lowering, implying that the energy relaxation of channel electrons should be taken into account for modeling SBH in GFETs.

Continuous adjustment of threshold voltage in carbon nanotube field-effect transistors through gate engineering

NASA Astrophysics Data System (ADS)

Zhong, Donglai; Zhao, Chenyi; Liu, Lijun; Zhang, Zhiyong; Peng, Lian-Mao

2018-04-01

In this letter, we report a gate engineering method to adjust threshold voltage of carbon nanotube (CNT) based field-effect transistors (FETs) continuously in a wide range, which makes the application of CNT FETs especially in digital integrated circuits (ICs) easier. Top-gated FETs are fabricated using solution-processed CNT network films with stacking Pd and Sc films as gate electrodes. By decreasing the thickness of the lower layer metal (Pd) from 20 nm to zero, the effective work function of the gate decreases, thus tuning the threshold voltage (Vt) of CNT FETs from -1.0 V to 0.2 V. The continuous adjustment of threshold voltage through gate engineering lays a solid foundation for multi-threshold technology in CNT based ICs, which then can simultaneously provide high performance and low power circuit modules on one chip.

Extended-gate organic field-effect transistor for the detection of histamine in water

NASA Astrophysics Data System (ADS)

Minamiki, Tsukuru; Minami, Tsuyoshi; Yokoyama, Daisuke; Fukuda, Kenjiro; Kumaki, Daisuke; Tokito, Shizuo

2015-04-01

As part of our ongoing research program to develop health care sensors based on organic field-effect transistor (OFET) devices, we have attempted to detect histamine using an extended-gate OFET. Histamine is found in spoiled or decayed fish, and causes foodborne illness known as scombroid food poisoning. The new OFET device possesses an extended gate functionalized by carboxyalkanethiol that can interact with histamine. As a result, we have succeeded in detecting histamine in water through a shift in OFET threshold voltage. This result indicates the potential utility of the designed OFET devices in food freshness sensing.

I-V Characteristics of a Ferroelectric Field Effect Transistor

NASA Technical Reports Server (NTRS)

MacLeod, Todd C.; Ho, Fat Duen

1999-01-01

There are many possible uses for ferroelectric field effect transistors.To understand their application, a fundamental knowledge of their basic characteristics must first be found. In this research, the current and voltage characteristics of a field effect transistor are described. The effective gate capacitance and charge are derived from experimental data on an actual FFET. The general equation for a MOSFET is used to derive the internal characteristics of the transistor: This equation is modified slightly to describe the FFET characteristics. Experimental data derived from a Radiant Technologies FFET is used to calculate the internal transistor characteristics using fundamental MOSFET equations. The drain current was measured under several different gate and drain voltages and with different initial polarizations on the ferroelectric material in the transistor. Two different polarization conditions were used. One with the gate ferroelectric material polarized with a +9.0 volt write pulse and one with a -9.0 volt pulse.

Graphene-graphite oxide field-effect transistors.

PubMed

Standley, Brian; Mendez, Anthony; Schmidgall, Emma; Bockrath, Marc

2012-03-14

Graphene's high mobility and two-dimensional nature make it an attractive material for field-effect transistors. Previous efforts in this area have used bulk gate dielectric materials such as SiO(2) or HfO(2). In contrast, we have studied the use of an ultrathin layered material, graphene's insulating analogue, graphite oxide. We have fabricated transistors comprising single or bilayer graphene channels, graphite oxide gate insulators, and metal top-gates. The graphite oxide layers show relatively minimal leakage at room temperature. The breakdown electric field of graphite oxide was found to be comparable to SiO(2), typically ~1-3 × 10(8) V/m, while its dielectric constant is slightly higher, κ ≈ 4.3. © 2012 American Chemical Society

Design and fabrication of high-performance diamond triple-gate field-effect transistors

PubMed Central

Liu, Jiangwei; Ohsato, Hirotaka; Wang, Xi; Liao, Meiyong; Koide, Yasuo

2016-01-01

The lack of large-area single-crystal diamond wafers has led us to downscale diamond electronic devices. Here, we design and fabricate a hydrogenated diamond (H-diamond) triple-gate metal-oxide-semiconductor field-effect transistor (MOSFET) to extend device downscaling and increase device output current. The device’s electrical properties are compared with those of planar-type MOSFETs, which are fabricated simultaneously on the same substrate. The triple-gate MOSFET’s output current (174.2 mA mm−1) is much higher than that of the planar-type device (45.2 mA mm−1), and the on/off ratio and subthreshold swing are more than 108 and as low as 110 mV dec−1, respectively. The fabrication of these H-diamond triple-gate MOSFETs will drive diamond electronic device development forward towards practical applications. PMID:27708372

Plasma Deposited SiO2 for Planar Self-Aligned Gate Metal-Insulator-Semiconductor Field Effect Transistors on Semi-Insulating InP

NASA Technical Reports Server (NTRS)

Tabory, Charles N.; Young, Paul G.; Smith, Edwyn D.; Alterovitz, Samuel A.

1994-01-01

Metal-insulator-semiconductor (MIS) field effect transistors were fabricated on InP substrates using a planar self-aligned gate process. A 700-1000 A gate insulator of Si02 doped with phosphorus was deposited by a direct plasma enhanced chemical vapor deposition at 400 mTorr, 275 C, 5 W, and power density of 8.5 MW/sq cm. High frequency capacitance-voltage measurements were taken on MIS capacitors which have been subjected to a 700 C anneal and an interface state density of lxl0(exp 11)/eV/cq cm was found. Current-voltage measurements of the capacitors show a breakdown voltage of 107 V/cm and a insulator resistivity of 10(exp 14) omega cm. Transistors were fabricated on semi-insulating InP using a standard planar self-aligned gate process in which the gate insulator was subjected to an ion implantation activation anneal of 700 C. MIS field effect transistors gave a maximum extrinsic transconductance of 23 mS/mm for a gate length of 3 microns. The drain current drift saturated at 87.5% of the initial current, while reaching to within 1% of the saturated value after only 1x10(exp 3). This is the first reported viable planar InP self-aligned gate transistor process reported to date.

The electrical and interfacial properties of metal-high-k oxide-semiconductor field effect transistors with CeO2/HfO2 laminated gate dielectrics

NASA Astrophysics Data System (ADS)

Chang, Ingram Yin-ku; Chen, Chun-Heng; Chiu, Fu-Chien; Lee, Joseph Ya-min

2007-11-01

Metal-oxide-semiconductor field-effect transistors with CeO2/HfO2 laminated gate dielectrics were fabricated. The transistors have a subthreshold slope of 74.9mV/decade. The interfacial properties were measured using gated diodes. The surface state density Dit was 9.78×1011cm-2eV-1. The surface-recombination velocity (s0) and the minority carrier lifetime in the field-induced depletion region (τ0,FIJ) measured from the gated diode were about 6.11×103cm /s and 1.8×10-8s, respectively. The effective capture cross section of surface state (σs) extracted using the subthreshold-swing measurement and the gated diode was about 7.69×10-15cm2. The effective electron mobility of CeO2/HfO2 laminated gated transistors was determined to be 212cm2/Vs.

Catalytic activity of enzymes immobilized on AlGaN /GaN solution gate field-effect transistors

NASA Astrophysics Data System (ADS)

Baur, B.; Howgate, J.; von Ribbeck, H.-G.; Gawlina, Y.; Bandalo, V.; Steinhoff, G.; Stutzmann, M.; Eickhoff, M.

2006-10-01

Enzyme-modified field-effect transistors (EnFETs) were prepared by immobilization of penicillinase on AlGaN /GaN solution gate field-effect transistors. The influence of the immobilization process on enzyme functionality was analyzed by comparing covalent immobilization and physisorption. Covalent immobilization by Schiff base formation on GaN surfaces modified with an aminopropyltriethoxysilane monolayer exhibits high reproducibility with respect to the enzyme/substrate affinity. Reductive amination of the Schiff base bonds to secondary amines significantly increases the stability of the enzyme layer. Electronic characterization of the EnFET response to penicillin G indicates that covalent immobilization leads to the formation of an enzyme (sub)monolayer.

Vertical Silicon Nanowire Field Effect Transistors with Nanoscale Gate-All-Around

NASA Astrophysics Data System (ADS)

Guerfi, Youssouf; Larrieu, Guilhem

2016-04-01

Nanowires are considered building blocks for the ultimate scaling of MOS transistors, capable of pushing devices until the most extreme boundaries of miniaturization thanks to their physical and geometrical properties. In particular, nanowires' suitability for forming a gate-all-around (GAA) configuration confers to the device an optimum electrostatic control of the gate over the conduction channel and then a better immunity against the short channel effects (SCE). In this letter, a large-scale process of GAA vertical silicon nanowire (VNW) MOSFETs is presented. A top-down approach is adopted for the realization of VNWs with an optimum reproducibility followed by thin layer engineering at nanoscale. Good overall electrical performances were obtained, with excellent electrostatic behavior (a subthreshold slope (SS) of 95 mV/dec and a drain induced barrier lowering (DIBL) of 25 mV/V) for a 15-nm gate length. Finally, a first demonstration of dual integration of n-type and p-type VNW transistors for the realization of CMOS inverter is proposed.

Field Effect Transistors Using Atomically Thin Layers of Copper Indium Selenide (CuInSe)

NASA Astrophysics Data System (ADS)

Patil, Prasanna; Ghosh, Sujoy; Wasala, Milinda; Lei, Sidong; Vajtai, Robert; Ajayan, Pulickel; Talapatra, Saikat

We will report fabrication of field-effect transistors (FETs) using few-layers of Copper Indium Selenide (CuInSe) flakes exfoliated from crystals grown using chemical vapor transport technique. Our transport measurements indicate n-type FET with electron mobility µ ~ 3 cm2 V-1 s-1 at room temperature when Silicon dioxide (SiO2) is used as a back gate. Mobility can be further increased significantly when ionic liquid 1-Butyl-3-methylimidazolium hexafluorophosphate (BMIM-PF6) is used as top gate. Similarly subthreshold swing can be further improved from 103 V/dec to 0.55 V/dec by using ionic liquid as a top gate. We also found ON/OFF ratio of ~ 102 for both top and back gate. Comparison between ionic liquid top gate and SiO2 back gate will be presented and discussed. This work is supported by the U.S. Army Research Office through a MURI Grant # W911NF-11-1-0362.

Ultrashort Channel Length Black Phosphorus Field-Effect Transistors.

PubMed

Miao, Jinshui; Zhang, Suoming; Cai, Le; Scherr, Martin; Wang, Chuan

2015-09-22

This paper reports high-performance top-gated black phosphorus (BP) field-effect transistors with channel lengths down to 20 nm fabricated using a facile angle evaporation process. By controlling the evaporation angle, the channel length of the transistors can be reproducibly controlled to be anywhere between 20 and 70 nm. The as-fabricated 20 nm top-gated BP transistors exhibit respectable on-state current (174 μA/μm) and transconductance (70 μS/μm) at a VDS of 0.1 V. Due to the use of two-dimensional BP as the channel material, the transistors exhibit relatively small short channel effects, preserving a decent on-off current ratio of 10(2) even at an extremely small channel length of 20 nm. Additionally, unlike the unencapsulated BP devices, which are known to be chemically unstable in ambient conditions, the top-gated BP transistors passivated by the Al2O3 gate dielectric layer remain stable without noticeable degradation in device performance after being stored in ambient conditions for more than 1 week. This work demonstrates the great promise of atomically thin BP for applications in ultimately scaled transistors.

Solution-processed nanoparticle super-float-gated organic field-effect transistor as un-cooled ultraviolet and infrared photon counter.

PubMed

Yuan, Yongbo; Dong, Qingfeng; Yang, Bin; Guo, Fawen; Zhang, Qi; Han, Ming; Huang, Jinsong

2013-01-01

High sensitivity photodetectors in ultraviolet (UV) and infrared (IR) range have broad civilian and military applications. Here we report on an un-cooled solution-processed UV-IR photon counter based on modified organic field-effect transistors. This type of UV detectors have light absorbing zinc oxide nanoparticles (NPs) sandwiched between two gate dielectric layers as a floating gate. The photon-generated charges on the floating gate cause high resistance regions in the transistor channel and tune the source-drain output current. This "super-float-gating" mechanism enables very high sensitivity photodetectors with a minimum detectable ultraviolet light intensity of 2.6 photons/μm(2)s at room temperature as well as photon counting capability. Based on same mechansim, infrared photodetectors with lead sulfide NPs as light absorbing materials have also been demonstrated.

Mathematical Models of the Common-Source and Common-Gate Amplifiers using a Metal-Ferroelectric-Semiconductor Field effect Transistor

NASA Technical Reports Server (NTRS)

Hunt, Mitchell; Sayyah, Rana; Mitchell, Cody; Laws, Crystal; MacLeod, Todd C.; Ho, Fat D.

2013-01-01

Mathematical models of the common-source and common-gate amplifiers using metal-ferroelectric- semiconductor field effect transistors (MOSFETs) are developed in this paper. The models are compared against data collected with MOSFETs of varying channel lengths and widths, and circuit parameters such as biasing conditions are varied as well. Considerations are made for the capacitance formed by the ferroelectric layer present between the gate and substrate of the transistors. Comparisons between the modeled and measured data are presented in depth as well as differences and advantages as compared to the performance of each circuit using a MOSFET.

Gate bias stress in pentacene field-effect-transistors: Charge trapping in the dielectric or semiconductor

NASA Astrophysics Data System (ADS)

Häusermann, R.; Batlogg, B.

2011-08-01

Gate bias stress instability in organic field-effect transistors (OFETs) is a major conceptual and device issue. This effect manifests itself by an undesirable shift of the transfer characteristics and is associated with long term charge trapping. We study the role of the dielectric and the semiconductor separately by producing OFETs with the same semiconductor (pentacene) combined with different dielectrics (SiO2 and Cytop). We show that it is possible to fabricate devices which are immune to gate bias stress. For other material combinations, charge trapping occurs in the semiconductor alone or in the dielectric.

The origin of excellent gate-bias stress stability in organic field-effect transistors employing fluorinated-polymer gate dielectrics.

PubMed

Kim, Jiye; Jang, Jaeyoung; Kim, Kyunghun; Kim, Haekyoung; Kim, Se Hyun; Park, Chan Eon

2014-11-12

Tuning of the energetic barriers to charge transfer at the semiconductor/dielectric interface in organic field-effect transistors (OFETs) is achieved by varying the dielectric functionality. Based on this, the correlation between the magnitude of the energy barrier and the gate-bias stress stability of the OFETs is demonstrated, and the origin of the excellent device stability of OFETs employing fluorinated dielectrics is revealed. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Pseudo 2-transistor active pixel sensor using an n-well/gate-tied p-channel metal oxide semiconductor field eeffect transistor-type photodetector with built-in transfer gate

NASA Astrophysics Data System (ADS)

Seo, Sang-Ho; Seo, Min-Woong; Kong, Jae-Sung; Shin, Jang-Kyoo; Choi, Pyung

2008-11-01

In this paper, a pseudo 2-transistor active pixel sensor (APS) has been designed and fabricated by using an n-well/gate-tied p-channel metal oxide semiconductor field effect transistor (PMOSFET)-type photodetector with built-in transfer gate. The proposed sensor has been fabricated using a 0.35 μm 2-poly 4-metal standard complementary metal oxide semiconductor (CMOS) logic process. The pseudo 2-transistor APS consists of two NMOSFETs and one photodetector which can amplify the generated photocurrent. The area of the pseudo 2-transistor APS is 7.1 × 6.2 μm2. The sensitivity of the proposed pixel is 49 lux/(V·s). By using this pixel, a smaller pixel area and a higher level of sensitivity can be realized when compared with a conventional 3-transistor APS which uses a pn junction photodiode.

Microwave annealing effect for highly reliable biosensor: dual-gate ion-sensitive field-effect transistor using amorphous InGaZnO thin-film transistor.

PubMed

Lee, In-Kyu; Lee, Kwan Hyi; Lee, Seok; Cho, Won-Ju

2014-12-24

We used a microwave annealing process to fabricate a highly reliable biosensor using amorphous-InGaZnO (a-IGZO) thin-film transistors (TFTs), which usually experience threshold voltage instability. Compared with furnace-annealed a-IGZO TFTs, the microwave-annealed devices showed superior threshold voltage stability and performance, including a high field-effect mobility of 9.51 cm(2)/V·s, a low threshold voltage of 0.99 V, a good subthreshold slope of 135 mV/dec, and an outstanding on/off current ratio of 1.18 × 10(8). In conclusion, by using the microwave-annealed a-IGZO TFT as the transducer in an extended-gate ion-sensitive field-effect transistor biosensor, we developed a high-performance biosensor with excellent sensing properties in terms of pH sensitivity, reliability, and chemical stability.

Field effect transistor with HfO2/Parylene-C bilayer hybrid gate insulator

NASA Astrophysics Data System (ADS)

Kumar, Neeraj; Kito, Ai; Inoue, Isao

2015-03-01

We have investigated the electric field control of the carrier density and the mobility at the surface of SrTiO3, a well known transition-metal oxide, in a field effect transistor (FET) geometry. We have used a Parylene-C (8 nm)/HfO2 (20 nm) double-layer gate insulator (GI), which can be a potential candidate for a solid state GI for the future Mott FETs. So far, only examples of the Mott FET used liquid electrolyte or ferroelectric oxides for the GI. However, possible electrochemical reaction at the interface causes damage to the surface of the Mott insulator. Thus, an alternative GI has been highly desired. We observed that even an ultra thin Parylene-C layer is effective for keeping the channel surface clean and free from oxygen vacancies. The 8 nm Parylene-C film has a relatively low resistance and consequentially its capacitance does not dominate the total capacitance of the Parylene-C/HfO2 GI. The breakdown gate voltage at 300 K is usually more than 10 V (~ 3.4 MV/cm). At gate voltage of 3 V the carrier density measured by the Hall effect is about 3 ×1013 cm-2, competent to cause the Mott transition. Moreover, the field effect mobility reaches in the range of 10 cm2/Vs indicating the Parylene-C passivated surface is actually very clean.

Comparative studies of Ge and Si p-channel metal-oxide-semiconductor field-effect-transistors with HfSiON dielectric and TaN metal gate

NASA Astrophysics Data System (ADS)

Hu, Ai-Bin; Xu, Qiu-Xia

2010-05-01

Ge and Si p-channel metal-oxide-semiconductor field-effect-transistors (p-MOSFETs) with hafnium silicon oxynitride (HfSiON) gate dielectric and tantalum nitride (TaN) metal gate are fabricated. Self-isolated ring-type transistor structures with two masks are employed. W/TaN metal stacks are used as gate electrode and shadow masks of source/drain implantation separately. Capacitance-voltage curve hysteresis of Ge metal-oxide-semiconductor (MOS) capacitors may be caused by charge trapping centres in GeO2 (1 < x < 2). Effective hole mobilities of Ge and Si transistors are extracted by using a channel conductance method. The peak hole mobilities of Si and Ge transistors are 33.4 cm2/(V · s) and 81.0 cm2/(V · s), respectively. Ge transistor has a hole mobility 2.4 times higher than that of Si control sample.

Differential-Mode Biosensor Using Dual Extended-Gate Metal-Oxide-Semiconductor Field-Effect Transistors

NASA Astrophysics Data System (ADS)

Choi, Jinhyeon; Lee, Hee Ho; Ahn, Jungil; Seo, Sang-Ho; Shin, Jang-Kyoo

2012-06-01

In this paper, we present a differential-mode biosensor using dual extended-gate metal-oxide-semiconductor field-effect transistors (MOSFETs), which possesses the advantages of both the extended-gate structure and the differential-mode operation. The extended-gate MOSFET was fabricated using a 0.6 µm standard complementary metal oxide semiconductor (CMOS) process. The Au extended gate is the sensing gate on which biomolecules are immobilized, while the Pt extended gate is the dummy gate for use in the differential-mode detection circuit. The differential-mode operation offers many advantages such as insensitivity to the variation of temperature and light, as well as low noise. The outputs were measured using a semiconductor parameter analyzer in a phosphate buffered saline (PBS; pH 7.4) solution. A standard Ag/AgCl reference electrode was used to apply the gate bias. We measured the variation of output voltage with time, temperature, and light intensity. The bindings of self-assembled monolayer (SAM), streptavidin, and biotin caused a variation in the output voltage of the differential-mode detection circuit and this was confirmed by surface plasmon resonance (SPR) experiment. Biotin molecules could be detected up to a concentration of as low as 0.001 µg/ml.

Low temperature mobility in hafnium-oxide gated germanium p-channel metal-oxide-semiconductor field-effect transistors

NASA Astrophysics Data System (ADS)

Beer, Chris; Whall, Terry; Parker, Evan; Leadley, David; De Jaeger, Brice; Nicholas, Gareth; Zimmerman, Paul; Meuris, Marc; Szostak, Slawomir; Gluszko, Grzegorz; Lukasiak, Lidia

2007-12-01

Effective mobility measurements have been made at 4.2K on high performance high-k gated germanium p-type metal-oxide-semiconductor field effect transistors with a range of Ge/gate dielectric interface state densities. The mobility is successfully modelled by assuming surface roughness and interface charge scattering at the SiO2 interlayer/Ge interface. The deduced interface charge density is approximately equal to the values obtained from the threshold voltage and subthreshold slope measurements on each device. A hydrogen anneal reduces both the interface state density and the surface root mean square roughness by 20%.

Pentacene-based low voltage organic field-effect transistors with anodized Ta2O5 gate dielectric

NASA Astrophysics Data System (ADS)

Jeong, Yeon Taek; Dodabalapur, Ananth

2007-11-01

Pentacene-based low voltage organic field-effect transistors were realized using an anodized Ta2O5 gate dielectric. The Ta2O5 gate dielectric layer with a surface roughness of 1.3Å was obtained by anodizing an e-beam evaporated Ta film. The device exhibited values of saturation mobility, threshold voltage, and Ion/Ioff ratio of 0.45cm2/Vs, 0.56V, and 7.5×101, respectively. The gate leakage current was reduced by more than 70% with a hexamethyldisilazane (HMDS) treatment on the Ta2O5 layer. The HMDS treatment also resulted in enhanced mobility values and a larger pentacene grain size.

Modeling of Gate Bias Modulation in Carbon Nanotube Field-Effect-Transistor

NASA Technical Reports Server (NTRS)

Toshishige, Yamada; Biegel, Bryan A. (Technical Monitor)

2002-01-01

The threshold voltages of a carbon-nanotube (CNT) field-effect transistor (FET) are studied. The CNT channel is so thin that there is no voltage drop perpendicular to the gate electrode plane, and this makes the device characteristics quite unique. The relation between the voltage and the electrochemical potentials, and the mass action law for electrons and holes are examined in the context of CNTs, and inversion and accumulation threshold voltages (V(sub Ti), and V(sub Ta)) are derived. V(sub Ti) of the CNTFETs has a much stronger doping dependence than that of the metal-oxide- semiconductor FETs, while V(sub Ta) of both devices depends weakly on doping with the same functional form.

Ferroelectric polarization induces electric double layer bistability in electrolyte-gated field-effect transistors.

PubMed

Fabiano, Simone; Crispin, Xavier; Berggren, Magnus

2014-01-08

The dense surface charges expressed by a ferroelectric polymeric thin film induce ion displacement within a polyelectrolyte layer and vice versa. This is because the density of dipoles along the surface of the ferroelectric thin film and its polarization switching time matches that of the (Helmholtz) electric double layers formed at the ferroelectric/polyelectrolyte and polyelectrolyte/semiconductor interfaces. This combination of materials allows for introducing hysteresis effects in the capacitance of an electric double layer capacitor. The latter is advantageously used to control the charge accumulation in the semiconductor channel of an organic field-effect transistor. The resulting memory transistors can be written at a gate voltage of around 7 V and read out at a drain voltage as low as 50 mV. The technological implication of this large difference between write and read-out voltages lies in the non-destructive reading of this ferroelectric memory.

α,ω-dihexyl-sexithiophene thin films for solution-gated organic field-effect transistors

NASA Astrophysics Data System (ADS)

Schamoni, Hannah; Noever, Simon; Nickel, Bert; Stutzmann, Martin; Garrido, Jose A.

2016-02-01

While organic semiconductors are being widely investigated for chemical and biochemical sensing applications, major drawbacks such as the poor device stability and low charge carrier mobility in aqueous electrolytes have not yet been solved to complete satisfaction. In this work, solution-gated organic field-effect transistors (SGOFETs) based on the molecule α,ω-dihexyl-sexithiophene (DH6T) are presented as promising platforms for in-electrolyte sensing. Thin films of DH6T were investigated with regard to the influence of the substrate temperature during deposition on the grain size and structural order. The performance of SGOFETs can be improved by choosing suitable growth parameters that lead to a two-dimensional film morphology and a high degree of structural order. Furthermore, the capability of the SGOFETs to detect changes in the pH or ionic strength of the gate electrolyte is demonstrated and simulated. Finally, excellent transistor stability is confirmed by continuously operating the device over a period of several days, which is a consequence of the low threshold voltage of DH6T-based SGOFETs. Altogether, our results demonstrate the feasibility of high performance and highly stable organic semiconductor devices for chemical or biochemical applications.

Current conduction in junction gate field effect transistors. Ph.D. Thesis

NASA Technical Reports Server (NTRS)

Kim, C.

1970-01-01

The internal physical mechanism that governs the current conduction in junction-gate field effect transistors is studied. A numerical method of analyzing the devices with different length-to-width ratios and doping profiles is developed. This method takes into account the two dimensional character of the electric field and the field dependent mobility. Application of the method to various device models shows that the channel width and the carrier concentration in the conductive channel decrease with increasing drain-to-source voltage for conventional devices. It also shows larger differential drain conductances for shorter devices when the drift velocity is not saturated. The interaction of the source and the drain gives the carrier accumulation in the channel which leads to the space-charge-limited current flow. The important parameters for the space-charge-limited current flow are found to be the L/L sub DE ratio and the crossover voltage.

Lead iodide perovskite light-emitting field-effect transistor

PubMed Central

Chin, Xin Yu; Cortecchia, Daniele; Yin, Jun; Bruno, Annalisa; Soci, Cesare

2015-01-01

Despite the widespread use of solution-processable hybrid organic–inorganic perovskites in photovoltaic and light-emitting applications, determination of their intrinsic charge transport parameters has been elusive due to the variability of film preparation and history-dependent device performance. Here we show that screening effects associated to ionic transport can be effectively eliminated by lowering the operating temperature of methylammonium lead iodide perovskite (CH3NH3PbI3) field-effect transistors. Field-effect carrier mobility is found to increase by almost two orders of magnitude below 200 K, consistent with phonon scattering-limited transport. Under balanced ambipolar carrier injection, gate-dependent electroluminescence is also observed from the transistor channel, with spectra revealing the tetragonal to orthorhombic phase transition. This demonstration of CH3NH3PbI3 light-emitting field-effect transistors provides intrinsic transport parameters to guide materials and solar cell optimization, and will drive the development of new electro-optic device concepts, such as gated light-emitting diodes and lasers operating at room temperature. PMID:26108967

B-doped diamond field-effect transistor with ferroelectric vinylidene fluoride-trifluoroethylene gate insulator

NASA Astrophysics Data System (ADS)

Karaya, Ryota; Baba, Ikki; Mori, Yosuke; Matsumoto, Tsubasa; Nakajima, Takashi; Tokuda, Norio; Kawae, Takeshi

2017-10-01

A B-doped diamond field-effect transistor (FET) with a ferroelectric vinylidene fluoride-trifluoroethylene (VDF-TrFE) copolymer gate insulator was fabricated. The VDF-TrFE film deposited on the B-doped diamond showed good insulating and ferroelectric properties. Also, a Pt/VDF-TrFE/B-doped diamond layered structure showed ideal behavior as a metal-ferroelectric-semiconductor (MFS) capacitor, and the memory window width was 11 V, when the gate voltage was swept from 20 to -20 V. The fabricated MFS-type FET structure showed the typical properties of a depletion-type p-channel FET and a maximum drain current density of 0.87 mA/mm at room temperature. The drain current versus gate voltage curves of the proposed FET showed a clockwise hysteresis loop owing to the ferroelectricity of the VDF-TrFE gate insulator. In addition, we demonstrated the logic inverter with the MFS-type diamond FET coupled with a load resistor, and obtained the inversion behavior of the input signal and a maximum gain of 18.4 for the present circuit.

Direct probing of electron and hole trapping into nano-floating-gate in organic field-effect transistor nonvolatile memories

NASA Astrophysics Data System (ADS)

Cui, Ze-Qun; Wang, Shun; Chen, Jian-Mei; Gao, Xu; Dong, Bin; Chi, Li-Feng; Wang, Sui-Dong

2015-03-01

Electron and hole trapping into the nano-floating-gate of a pentacene-based organic field-effect transistor nonvolatile memory is directly probed by Kelvin probe force microscopy. The probing is straightforward and non-destructive. The measured surface potential change can quantitatively profile the charge trapping, and the surface characterization results are in good accord with the corresponding device behavior. Both electrons and holes can be trapped into the nano-floating-gate, with a preference of electron trapping than hole trapping. The trapped charge quantity has an approximately linear relation with the programming/erasing gate bias, indicating that the charge trapping in the device is a field-controlled process.

Enzyme-modified electrolyte-gated organic field-effect transistors

NASA Astrophysics Data System (ADS)

Buth, Felix; Donner, Andreas; Stutzmann, Martin; Garrido, Jose A.

2012-10-01

Organic solution-gated field-effect transistors (SGFETs) can be operated at low voltages in aqueous environments, paving the way to the use of organic semiconductors in bio-sensing applications. However, it has been shown that these devices exhibit only a rather weak sensitivity to standard electrolyte parameters such as pH and ionic strength. In order to increase the sensitivity and to add specificity towards a given analyte, the covalent attachment of functional groups and enzymes to the device surface would be desirable. In this contribution we demonstrate that enzyme modified organic SGFETs can be used for the in-situ detection of penicillin in the low μM regime. In a first step, silane molecules with amine terminal groups are grafted to α-sexithiophene-based thin film transistors. Surface characterization techniques like X-ray photoemission confirm the modification of the surface with these functional groups, which are stable in standard aqueous electrolytes. We show that the presence of surface-bound amphoteric groups (e.g. amino or carboxylic moieties) increases the pH-sensitivity of the organic SGFETs. In addition, these groups serve as anchoring sites for the attachment of the enzyme penicillinase. The resulting enzyme-FETs are used for the detection of penicillin, enabling the study of the influence of the buffer strength and the pH of the electrolyte on the enzyme kinetics. The functionalization of the organic FETs shown here can be extended to a large variety of enzymes, allowing the specific detection of different chemical and biochemical analytes.

Dual metal gate tunneling field effect transistors based on MOSFETs: A 2-D analytical approach

NASA Astrophysics Data System (ADS)

Ramezani, Zeinab; Orouji, Ali A.

2018-01-01

A novel 2-D analytical drain current model of novel Dual Metal Gate Tunnel Field Effect Transistors Based on MOSFETs (DMG-TFET) is presented in this paper. The proposed Tunneling FET is extracted from a MOSFET structure by employing an additional electrode in the source region with an appropriate work function to induce holes in the N+ source region and hence makes it as a P+ source region. The electric field is derived which is utilized to extract the expression of the drain current by analytically integrating the band to band tunneling generation rate in the tunneling region based on the potential profile by solving the Poisson's equation. Through this model, the effects of the thin film thickness and gate voltage on the potential, the electric field, and the effects of the thin film thickness on the tunneling current can be studied. To validate our present model we use SILVACO ATLAS device simulator and the analytical results have been compared with it and found a good agreement.

High-performance silicon nanowire field-effect transistor with silicided contacts

NASA Astrophysics Data System (ADS)

Rosaz, G.; Salem, B.; Pauc, N.; Gentile, P.; Potié, A.; Solanki, A.; Baron, T.

2011-08-01

Undoped silicon nanowire (Si NW) field-effect transistors (FETs) with a back-gate configuration have been fabricated and characterized. A thick (200 nm) Si3N4 layer was used as a gate insulator and a p++ silicon substrate as a back gate. Si NWs have been grown by the chemical vapour deposition method using the vapour-liquid-solid mechanism and gold as a catalyst. Metallic contacts have been deposited using Ni/Al (80 nm/120 nm) and characterized before and after an optimized annealing step at 400 °C, which resulted in a great decrease in the contact resistance due to the newly formed nickel silicide/Si interface at source and drain. These optimized devices show a good hole mobility of around 200 cm2 V-1 s-1, in the same range as the bulk material, with a good ON current density of about 28 kA cm-2. Finally, hysteretic behaviour of NW channel conductance is discussed to explain the importance of NW surface passivation.

Device optimization and scaling properties of a gate-on-germanium source tunnel field-effect transistor

NASA Astrophysics Data System (ADS)

Chattopadhyay, Avik; Mallik, Abhijit; Omura, Yasuhisa

2015-06-01

A gate-on-germanium source (GoGeS) tunnel field-effect transistor (TFET) shows great promise for low-power (sub-0.5 V) applications. A detailed investigation, with the help of a numerical device simulator, on the effects of variation in different structural parameters of a GoGeS TFET on its electrical performance is reported in this paper. Structural parameters such as κ-value of the gate dielectric, length and κ-value of the spacer, and doping concentrations of both the substrate and source are considered. A low-κ symmetric spacer and a high-κ gate dielectric are found to yield better device performance. The substrate doping influences only the p-i-n leakage floor. The source doping is found to significantly affect performance parameters such as OFF-state current, ON-state current and subthreshold swing, in addition to a threshold voltage shift. Results of the investigation on the gate length scaling of such devices are also reported in this paper.

Effect of gate bias sweep rate on the threshold voltage of in-plane gate nanowire transistor

NASA Astrophysics Data System (ADS)

Liu, H. X.; Li, J.; Tan, R. R.

2018-01-01

In2O3 nanowire electric-double-layer (EDL) transistors with in-plane gate gated by SiO2 solid-electrolyte are fabricated on transparent glass substrates. The gate voltage sweep rates can effectively modulate the threshold voltage (Vth) of nanowire device. Both depletion mode and enhancement mode are realized, and the Vth shift of the nanowire transistors is estimated to be 0.73V (without light). This phenomenon is due to increased adsorption of oxygen on the nanowire surface by the slower gate voltage sweep rates. Adsorbed oxygens capture electrons and cause a surface of nanowire channel was depleted. The operation voltage of transistor was 1.0 V, because the EDL gate dielectric can lead to high gate dielectric capacitance. These transparent in-plane gate nanowire transistors are promising for “see-through” nanoscale sensors.

Light-effect transistor (LET) with multiple independent gating controls for optical logic gates and optical amplification

NASA Astrophysics Data System (ADS)

Marmon, Jason; Rai, Satish; Wang, Kai; Zhou, Weilie; Zhang, Yong

2016-03-01

Modern electronics are developing electronic-optical integrated circuits, while their electronic backbone, e.g. field-effect transistors (FETs), remains the same. However, further FET down scaling is facing physical and technical challenges. A light-effect transistor (LET) offers electronic-optical hybridization at the component level, which can continue Moore’s law to quantum region without requiring a FET’s fabrication complexity, e.g. physical gate and doping, by employing optical gating and photoconductivity. Multiple independent gates are therefore readily realized to achieve unique functionalities without increasing chip space. Here we report LET device characteristics and novel digital and analog applications, such as optical logic gates and optical amplification. Prototype CdSe-nanowire-based LETs show output and transfer characteristics resembling advanced FETs, e.g. on/off ratios up to ~1.0x106 with a source-drain voltage of ~1.43 V, gate-power of ~260 nW, and subthreshold swing of ~0.3 nW/decade (excluding losses). Our work offers new electronic-optical integration strategies and electronic and optical computing approaches.

Hydrogen-terminated diamond vertical-type metal oxide semiconductor field-effect transistors with a trench gate

DOE Office of Scientific and Technical Information (OSTI.GOV)

Inaba, Masafumi, E-mail: inaba-ma@ruri.waseda.jp; Muta, Tsubasa; Kobayashi, Mikinori

2016-07-18

The hydrogen-terminated diamond surface (C-H diamond) has a two-dimensional hole gas (2DHG) layer independent of the crystal orientation. A 2DHG layer is ubiquitously formed on the C-H diamond surface covered by atomic-layer-deposited-Al{sub 2}O{sub 3}. Using Al{sub 2}O{sub 3} as a gate oxide, C-H diamond metal oxide semiconductor field-effect transistors (MOSFETs) operate in a trench gate structure where the diamond side-wall acts as a channel. MOSFETs with a side-wall channel exhibit equivalent performance to the lateral C-H diamond MOSFET without a side-wall channel. Here, a vertical-type MOSFET with a drain on the bottom is demonstrated in diamond with channel current modulationmore » by the gate and pinch off.« less

Carrier mobility in organic field-effect transistors

NASA Astrophysics Data System (ADS)

Xu, Yong; Benwadih, Mohamed; Gwoziecki, Romain; Coppard, Romain; Minari, Takeo; Liu, Chuan; Tsukagoshi, Kazuhito; Chroboczek, Jan; Balestra, Francis; Ghibaudo, Gerard

2011-11-01

A study of carrier transport in top-gate and bottom-contact TIPS-pentacene organic field-effect transistors (OFETs) based on mobility is presented. Among three mobilities extracted by different methods, the low-field mobility obtained by the Y function exhibits the best reliability and ease for use, whereas the widely applied field-effect mobility is not reliable, particularly in short-channel transistors and at low temperatures. A detailed study of contact transport reveals its strong impact on short-channel transistors, suggesting that a more intrinsic transport analysis is better implemented in relatively longer-channel devices. The observed temperature dependences of mobility are well explained by a transport model with Gaussian-like diffusivity band tails, different from diffusion in localized states band tails. This model explicitly interprets the non-zero constant mobility at low temperatures and clearly demonstrates the effects of disorder and hopping transport on temperature and carrier density dependences of mobility in organic transistors.

Investigation of Electronic and Opto-Electronic Properties of Two-Dimensional (2D) Layers of Copper Indium Selenide Field Effect Transistors

NASA Astrophysics Data System (ADS)

Patil, Prasanna Dnyaneshwar

Investigations performed in order to understand the electronic and optoelectronic properties of field effect transistors based on few layers of 2D Copper Indium Selenide (CuIn7Se11) are reported. In general, field effect transistors (FETs), electric double layer field effect transistors (EDL-FETs), and photodetectors are crucial part of several electronics based applications such as tele-communication, bio-sensing, and opto-electronic industry. After the discovery of graphene, several 2D semiconductor materials like TMDs (MoS2, WS2, and MoSe2 etc.), group III-VI materials (InSe, GaSe, and SnS2 etc.) are being studied rigorously in order to develop them as components in next generation FETs. Traditionally, thin films of ternary system of Copper Indium Selenide have been extensively studied and used in optoelectronics industry as photoactive component in solar cells. Thus, it is expected that atomically thin 2D layered structure of Copper Indium Selenide can have optical properties that could potentially be more advantageous than its thin film counterpart and could find use for developing next generation nano devices with utility in opto/nano electronics. Field effect transistors were fabricated using few-layers of CuIn7Se11 flakes, which were mechanically exfoliated from bulk crystals grown using chemical vapor transport technique. Our FET transport characterization measurements indicate n-type behavior with electron field effect mobility microFE ≈ 36 cm2 V-1 s-1 at room temperature when Silicon dioxide (SiO2) is used as a back gate. We found that in such back gated field effect transistor an on/off ratio of 104 and a subthreshold swing ≈ 1 V/dec can be obtained. Our investigations further indicate that Electronic performance of these materials can be increased significantly when gated from top using an ionic liquid electrolyte [1-Butyl-3-methylimidazolium hexafluorophosphate (BMIM-PF6)]. We found that electron field effect mobility microFE can be increased from

Influence of trap-assisted tunneling on trap-assisted tunneling current in double gate tunnel field-effect transistor

NASA Astrophysics Data System (ADS)

Zhi, Jiang; Yi-Qi, Zhuang; Cong, Li; Ping, Wang; Yu-Qi, Liu

2016-02-01

Trap-assisted tunneling (TAT) has attracted more and more attention, because it seriously affects the sub-threshold characteristic of tunnel field-effect transistor (TFET). In this paper, we assess subthreshold performance of double gate TFET (DG-TFET) through a band-to-band tunneling (BTBT) model, including phonon-assisted scattering and acoustic surface phonons scattering. Interface state density profile (Dit) and the trap level are included in the simulation to analyze their effects on TAT current and the mechanism of gate leakage current. Project supported by the National Natural Science Foundation of China (Grant Nos. 61574109 and 61204092).

Electrolyte-gated transistors based on conducting polymer nanowire junction arrays.

PubMed

Alam, Maksudul M; Wang, Jun; Guo, Yaoyao; Lee, Stephanie P; Tseng, Hsian-Rong

2005-07-07

In this study, we describe the electrolyte gating and doping effects of transistors based on conducting polymer nanowire electrode junction arrays in buffered aqueous media. Conducting polymer nanowires including polyaniline, polypyrrole, and poly(ethylenedioxythiophene) were investigated. In the presence of a positive gate bias, the device exhibits a large on/off current ratio of 978 for polyaniline nanowire-based transistors; these values vary according to the acidity of the gate medium. We attribute these efficient electrolyte gating and doping effects to the electrochemically fabricated nanostructures of conducting polymer nanowires. This study demonstrates that two-terminal devices can be easily converted into three-terminal transistors by simply immersing the device into an electrolyte solution along with a gate electrode. Here, the field-induced modulation can be applied for signal amplification to enhance the device performance.

Lateral energy band profile modulation in tunnel field effect transistors based on gate structure engineering

NASA Astrophysics Data System (ADS)

Cui, Ning; Liang, Renrong; Wang, Jing; Xu, Jun

2012-06-01

Choosing novel materials and structures is important for enhancing the on-state current in tunnel field-effect transistors (TFETs). In this paper, we reveal that the on-state performance of TFETs is mainly determined by the energy band profile of the channel. According to this interpretation, we present a new concept of energy band profile modulation (BPM) achieved with gate structure engineering. It is believed that this approach can be used to suppress the ambipolar effect. Based on this method, a Si TFET device with a symmetrical tri-material-gate (TMG) structure is proposed. Two-dimensional numerical simulations demonstrated that the special band profile in this device can boost on-state performance, and it also suppresses the off-state current induced by the ambipolar effect. These unique advantages are maintained over a wide range of gate lengths and supply voltages. The BPM concept can serve as a guideline for improving the performance of nanoscale TFET devices.

Interface trap of p-type gate integrated AlGaN/GaN heterostructure field effect transistors

NASA Astrophysics Data System (ADS)

Kim, Kyu Sang

2017-09-01

In this work, the impact of trap states at the p-(Al)GaN/AlGaN interface has been investigated for the normally-off mode p-(Al)GaN/AlGaN/GaN heterostructure field-effect transistors (HFETs) by means of frequency dependent conductance. From the current-voltage (I-V) measurement, it was found that the p-AlGaN gate integrated device has higher drain current and lower gate leakage current compared to the p-GaN gate integrated device. We obtained the interface trap density and the characteristic time constant for the p-type gate integrated HFETs under the forward gate voltage of up to 6 V. As a result, the interface trap density (characteristic time constant) of the p-GaN gate device was lower (longer) than that of the p-AlGaN. Furthermore, it was analyzed that the trap state energy level of the p-GaN gate device was located at the shallow level relative to the p-AlGaN gate device, which accounts for different gate leakage current of each devices.

Graphene Field Effect Transistor for Radiation Detection

NASA Technical Reports Server (NTRS)

Li, Mary J. (Inventor); Chen, Zhihong (Inventor)

2016-01-01

The present invention relates to a graphene field effect transistor-based radiation sensor for use in a variety of radiation detection applications, including manned spaceflight missions. The sensing mechanism of the radiation sensor is based on the high sensitivity of graphene in the local change of electric field that can result from the interaction of ionizing radiation with a gated undoped silicon absorber serving as the supporting substrate in the graphene field effect transistor. The radiation sensor has low power and high sensitivity, a flexible structure, and a wide temperature range, and can be used in a variety of applications, particularly in space missions for human exploration.

Field-Effect Transistors Based on Networks of Highly Aligned, Chemically Synthesized N = 7 Armchair Graphene Nanoribbons.

PubMed

Passi, Vikram; Gahoi, Amit; Senkovskiy, Boris V; Haberer, Danny; Fischer, Felix R; Grüneis, Alexander; Lemme, Max C

2018-03-28

We report on the experimental demonstration and electrical characterization of N = 7 armchair graphene nanoribbon (7-AGNR) field effect transistors. The back-gated transistors are fabricated from atomically precise and highly aligned 7-AGNRs, synthesized with a bottom-up approach. The large area transfer process holds the promise of scalable device fabrication with atomically precise nanoribbons. The channels of the FETs are approximately 30 times longer than the average nanoribbon length of 30 nm to 40 nm. The density of the GNRs is high, so that transport can be assumed well-above the percolation threshold. The long channel transistors exhibit a maximum I ON / I OFF current ratio of 87.5.

Solution processed flexible organic thin film back-gated transistors based on polyimide dielectric films

NASA Astrophysics Data System (ADS)

Park, Janghoon; Min, Yoonki; Lee, Dongjin

2018-04-01

An organic thin film back-gated transistor (OBGT) was fabricated and characterized. The gate electrode was printed on the back side of substrate, and the dielectric layer was omitted by substituting the dielectric layer with the polyimide (PI) film substrate. Roll-to-roll (R2R) gravure printing, doctor blading, and drop casting methods were used to fabricate the OBGT. The printed OBGT device shows better performance compared with an OTFT device based on dielectric layer of BaTiO3. Additionally, a calendering process enhanced the performance by a factor of 3 to 7 (mobility: 0.016 cm2/V.s, on/off ratio: 9.17×103). A bending test was conducted to confirm the flexibility and durability of the OBGT device. The results show the fabricated device endures 20000-cyclic motions. The realized OBGT device was successfully fabricated and working, which is meaningful for production engineering from the viewpoint of process development.

Field effect transistor and method of construction thereof

NASA Technical Reports Server (NTRS)

Fletner, W. R. (Inventor)

1978-01-01

A field effect transistor is constructed by placing a semi-conductor layer on an insulating substrate so that the gate region is separated from source and drain regions. The gate electrode and gate region of the layer are of generally reduced length, the gate region being of greatest length on its surface closest to the gate electrode. This is accomplished by initially creating a relatively large gate region of one polarity, and then reversing the polarity of a central portion of this gate region by ion bombardment, thus achieving a narrower final gate region of the stated configuration.

Effect of liquid gate bias rising time in pH sensors based on Si nanowire ion sensitive field effect transistors

NASA Astrophysics Data System (ADS)

Jang, Jungkyu; Choi, Sungju; Kim, Jungmok; Park, Tae Jung; Park, Byung-Gook; Kim, Dong Myong; Choi, Sung-Jin; Lee, Seung Min; Kim, Dae Hwan; Mo, Hyun-Sun

2018-02-01

In this study, we investigate the effect of rising time (TR) of liquid gate bias (VLG) on transient responses in pH sensors based on Si nanowire ion-sensitive field-effect transistors (ISFETs). As TR becomes shorter and pH values decrease, the ISFET current takes a longer time to saturate to the pH-dependent steady-state value. By correlating VLG with the internal gate-to-source voltage of the ISFET, we found that this effect occurs when the drift/diffusion of mobile ions in analytes in response to VLG is delayed. This gives us useful insight on the design of ISFET-based point-of-care circuits and systems, particularly with respect to determining an appropriate rising time for the liquid gate bias.

GaN metal-oxide-semiconductor field-effect transistors on AlGaN/GaN heterostructure with recessed gate

NASA Astrophysics Data System (ADS)

Wang, Qingpeng; Ao, Jin-Ping; Wang, Pangpang; Jiang, Ying; Li, Liuan; Kawaharada, Kazuya; Liu, Yang

2015-04-01

GaN metal-oxide-semiconductor field-effect transistors (MOSFETs) on AlGaN/GaN heterostructure with a recess gate were fabricated and characterized. The device showed good pinch-off characteristics and a maximum field-effect mobility of 145.2 cm2·V-1·s-1. The effects of etching gas of Cl2 and SiCl4 were investigated in the gate recess process. SiCl4-etched devices showed higher channel mobility and lower threshold voltage. Atomic force microscope measurement was done to investigate the etching profile with different etching protection mask. Compared with photoresist, SiO2-masked sample showed lower surface roughness and better profile with stepper sidewall and weaker trenching effect resulting in higher channel mobility in the MOSFET.

Human dopamine receptor nanovesicles for gate-potential modulators in high-performance field-effect transistor biosensors

NASA Astrophysics Data System (ADS)

Park, Seon Joo; Song, Hyun Seok; Kwon, Oh Seok; Chung, Ji Hyun; Lee, Seung Hwan; An, Ji Hyun; Ahn, Sae Ryun; Lee, Ji Eun; Yoon, Hyeonseok; Park, Tai Hyun; Jang, Jyongsik

2014-03-01

The development of molecular detection that allows rapid responses with high sensitivity and selectivity remains challenging. Herein, we demonstrate the strategy of novel bio-nanotechnology to successfully fabricate high-performance dopamine (DA) biosensor using DA Receptor-containing uniform-particle-shaped Nanovesicles-immobilized Carboxylated poly(3,4-ethylenedioxythiophene) (CPEDOT) NTs (DRNCNs). DA molecules are commonly associated with serious diseases, such as Parkinson's and Alzheimer's diseases. For the first time, nanovesicles containing a human DA receptor D1 (hDRD1) were successfully constructed from HEK-293 cells, stably expressing hDRD1. The nanovesicles containing hDRD1 as gate-potential modulator on the conducting polymer (CP) nanomaterial transistors provided high-performance responses to DA molecule owing to their uniform, monodispersive morphologies and outstanding discrimination ability. Specifically, the DRNCNs were integrated into a liquid-ion gated field-effect transistor (FET) system via immobilization and attachment processes, leading to high sensitivity and excellent selectivity toward DA in liquid state. Unprecedentedly, the minimum detectable level (MDL) from the field-induced DA responses was as low as 10 pM in real- time, which is 10 times more sensitive than that of previously reported CP based-DA biosensors. Moreover, the FET-type DRNCN biosensor had a rapid response time (<1 s) and showed excellent selectivity in human serum.

Design of double gate vertical tunnel field effect transistor using HDB and its performance estimation

NASA Astrophysics Data System (ADS)

Seema; Chauhan, Sudakar Singh

2018-05-01

In this paper, we demonstrate the double gate vertical tunnel field-effect transistor using homo/hetero dielectric buried oxide (HDB) to obtain the optimized device characteristics. In this concern, the existence of double gate, HDB and electrode work-function engineering enhances DC performance and Analog/RF performance. The use of electrostatic doping helps to achieve higher on-current owing to occurrence of higher tunneling generation rate of charge carriers at the source/epitaxial interface. Further, lightly doped drain region and high- k dielectric below channel and drain region are responsible to suppress the ambipolar current. Simulated results clarifies that proposed device have achieved the tremendous performance in terms of driving current capability, steeper subthreshold slope (SS), drain induced barrier lowering (DIBL), hot carrier effects (HCEs) and high frequency parameters for better device reliability.

Osteoblastic cells trigger gate currents on nanocrystalline diamond transistor.

PubMed

Izak, Tibor; Krátká, Marie; Kromka, Alexander; Rezek, Bohuslav

2015-05-01

We show the influence of osteoblastic SAOS-2 cells on the transfer characteristics of nanocrystalline diamond solution-gated field-effect transistors (SGFET) prepared on glass substrates. Channels of these fully transparent SGFETs are realized by hydrogen termination of undoped diamond film. After cell cultivation, the transistors exhibit about 100× increased leakage currents (up to 10nA). During and after the cell delamination, the transistors return to original gate currents. We propose a mechanism where this triggering effect is attributed to ions released from adhered cells, which depends on the cell adhesion morphology, and could be used for cell culture monitoring. Copyright © 2015 Elsevier B.V. All rights reserved.

A compact quantum correction model for symmetric double gate metal-oxide-semiconductor field-effect transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Cho, Edward Namkyu; Shin, Yong Hyeon; Yun, Ilgu, E-mail: iyun@yonsei.ac.kr

2014-11-07

A compact quantum correction model for a symmetric double gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET) is investigated. The compact quantum correction model is proposed from the concepts of the threshold voltage shift (ΔV{sub TH}{sup QM}) and the gate capacitance (C{sub g}) degradation. First of all, ΔV{sub TH}{sup QM} induced by quantum mechanical (QM) effects is modeled. The C{sub g} degradation is then modeled by introducing the inversion layer centroid. With ΔV{sub TH}{sup QM} and the C{sub g} degradation, the QM effects are implemented in previously reported classical model and a comparison between the proposed quantum correction model and numerical simulationmore » results is presented. Based on the results, the proposed quantum correction model can be applicable to the compact model of DG MOSFET.« less

High performance tunnel field-effect transistor by gate and source engineering.

PubMed

Huang, Ru; Huang, Qianqian; Chen, Shaowen; Wu, Chunlei; Wang, Jiaxin; An, Xia; Wang, Yangyuan

2014-12-19

As one of the most promising candidates for future nanoelectronic devices, tunnel field-effect transistors (TFET) can overcome the subthreshold slope (SS) limitation of MOSFET, whereas high ON-current, low OFF-current and steep switching can hardly be obtained at the same time for experimental TFETs. In this paper, we developed a new nanodevice technology based on TFET concepts. By designing the gate configuration and introducing the optimized Schottky junction, a multi-finger-gate TFET with a dopant-segregated Schottky source (mFSB-TFET) is proposed and experimentally demonstrated. A steeper SS can be achieved in the fabricated mFSB-TFET on the bulk Si substrate benefiting from the coupled quantum band-to-band tunneling (BTBT) mechanism, as well as a high I(ON)/I(OFF) ratio (∼ 10(7)) at V(DS) = 0.2 V without an area penalty. By compatible SOI CMOS technology, the fabricated Si mFSB-TFET device was further optimized with a high ION/IOFF ratio of ∼ 10(8) and a steeper SS of over 5.5 decades of current. A minimum SS of below 60 mV dec(-1) was experimentally obtained, indicating its dominant quantum BTBT mechanism for switching.

Perspective analysis of tri gate germanium tunneling field-effect transistor with dopant segregation region at source/drain

NASA Astrophysics Data System (ADS)

Liu, Liang-kui; Shi, Cheng; Zhang, Yi-bo; Sun, Lei

2017-04-01

A tri gate Ge-based tunneling field-effect transistor (TFET) has been numerically studied with technology computer aided design (TCAD) tools. Dopant segregated Schottky source/drain is applied to the device structure design (DS-TFET). The characteristics of the DS-TFET are compared and analyzed comprehensively. It is found that the performance of n-channel tri gate DS-TFET with a positive bias is insensitive to the dopant concentration and barrier height at n-type drain, and that the dopant concentration and barrier height at a p-type source considerably affect the device performance. The domination of electron current in the entire BTBT current of this device accounts for this phenomenon and the tri-gate DS-TFET is proved to have a higher performance than its dual-gate counterpart.

Effects of drain bias on the statistical variation of double-gate tunnel field-effect transistors

NASA Astrophysics Data System (ADS)

Choi, Woo Young

2017-04-01

The effects of drain bias on the statistical variation of double-gate (DG) tunnel field-effect transistors (TFETs) are discussed in comparison with DG metal-oxide-semiconductor FETs (MOSFETs). Statistical variation corresponds to the variation of threshold voltage (V th), subthreshold swing (SS), and drain-induced barrier thinning (DIBT). The unique statistical variation characteristics of DG TFETs and DG MOSFETs with the variation of drain bias are analyzed by using full three-dimensional technology computer-aided design (TCAD) simulation in terms of the three dominant variation sources: line-edge roughness (LER), random dopant fluctuation (RDF) and workfunction variation (WFV). It is observed than DG TFETs suffer from less severe statistical variation as drain voltage increases unlike DG MOSFETs.

Polarization-Engineered Ga-Face GaN-Based Heterostructures for Normally-Off Heterostructure Field-Effect Transistors

NASA Astrophysics Data System (ADS)

Kim, Hyeongnam; Nath, Digbijoy; Rajan, Siddharth; Lu, Wu

2013-01-01

Polarization-engineered Ga-face GaN-based heterostructures with a GaN cap layer and an AlGaN/ p-GaN back barrier have been designed for normally-off field-effect transistors (FETs). The simulation results show that an unintentionally doped GaN cap and p-GaN layer in the buffer primarily deplete electrons in the channel and the Al0.2Ga0.8N back barrier helps to pinch off the channel. Experimentally, we have demonstrated a normally-off GaN-based field-effect transistor on the designed GaN cap/Al0.3Ga0.7N/GaN channel/Al0.2Ga0.8N/ p-GaN/GaN heterostructure. A positive threshold voltage of 0.2 V and maximum transconductance of 2.6 mS/mm were achieved for 80- μm-long gate devices. The device fabrication process does not require a dry etching process for gate recessing, while highly selective etching of the GaN cap against a very thin Al0.3GaN0.7N top barrier has to be performed to create a two-dimensional electron gas for both the ohmic and access regions. A self-aligned, selective etch of the GaN cap in the access region is introduced, using the gate metal as an etch mask. The absence of gate recess etching is promising for uniform and repeatable threshold voltage control in normally-off AlGaN/GaN heterostructure FETs for power switching applications.

In2O3 nanowire based field effect transistor for biological sensors.

NASA Astrophysics Data System (ADS)

Zeng, Zhongming; Wang, Kai; Zhou, Weilie

2008-03-01

Semiconductor nanowires (NWs) are attracting considerable attention due to their nanoscale dimensions and enormous surface-to-volume ratios. Many applications have been demonstrated in toxic gas, protein, small molecule and viruses sensing because of their superior sensing performances. Indium oxide (In2O3) NWs have been successfully applied for toxic gas and small organic molecule sensing. In our experiment, In2O3 NWs based field effect transistors (FET) are fabricated for virus (Ricin) detections. Single-crystalline In2O3 NWs with diameters around 100 nm were synthesized by the thermal evaporation. The nanodevice based on In2O3 NWs bridges the source/drain electrodes with a channel length of ˜5 μm. Basic transport properties of devices were measured before biological detection. The I-V curves with the gate voltage Vg=0 shows good ohmic contact and the resistance is about 10 Mφ. The back-gate effect on the conductivity showed that In2O3 NW is working as n-type channel with obvious back-gate effect, which is much stronger than the reported results. The nanodevices used as virus detection will be also discussed.

Electrically Tunable Energy Bandgap in Dual-Gated Ultra-Thin Black Phosphorus Field Effect Transistors

NASA Astrophysics Data System (ADS)

Yan, Shi-Li; Xie, Zhi-Jian; Chen, Jian-Hao; Taniguchi, Takashi; Watanabe, Kenji

2017-03-01

The energy bandgap is an intrinsic character of semiconductors, which largely determines their properties. The ability to continuously and reversibly tune the bandgap of a single device during real time operation is of great importance not only to device physics but also to technological applications. Here we demonstrate a widely tunable bandgap of few-layer black phosphorus (BP) by the application of vertical electric field in dual-gated BP field-effect transistors. A total bandgap reduction of 124 meV is observed when the electrical displacement field is increased from 0.10V/nm to 0.83V/nm. Our results suggest appealing potential for few-layer BP as a tunable bandgap material in infrared optoelectronics, thermoelectric power generation and thermal imaging.

Triggering the Electrolyte-Gated Organic Field-Effect Transistor output characteristics through gate functionalization using diazonium chemistry: Application to biodetection of 2,4-dichlorophenoxyacetic acid.

PubMed

Nguyen, T T K; Nguyen, T N; Anquetin, G; Reisberg, S; Noël, V; Mattana, G; Touzeau, J; Barbault, F; Pham, M C; Piro, B

2018-08-15

We investigated an Electrolyte-Gated Organic Field-Effect transistor based on poly(N-alkyldiketopyrrolo-pyrrole dithienylthieno[3,2-b]thiophene) as organic semiconductor whose gate electrode was functionalized by electrografting a functional diazonium salt capable to bind an antibody specific to 2,4-dichlorophenoxyacetic acid (2,4-D), an herbicide well-known to be a soil and water pollutant. Molecular docking computations were performed to design the functional diazonium salt to rationalize the antibody capture on the gate surface. Sensing of 2,4-D was performed through a displacement immunoassay. The limit of detection was estimated at around 2.5 fM. Copyright © 2018 Elsevier B.V. All rights reserved.

Organic transistors making use of room temperature ionic liquids as gating medium

NASA Astrophysics Data System (ADS)

Hoyos, Jonathan Javier Sayago

biases. We systematically investigated EG transistors employing RTILs belonging to the same family, i.e. based on a common anion and different cations. The transistor characteristics showed a limited cation influence in establishing the p-type doping of the conducting polymer. Interestingly, we observed that the transistor response time depends on at least two processes: the redistribution of ions from the electrolyte into the transistor channel, affecting the gate-source current (I gs); and the redistribution of charges in the transistor channel, affecting the drain-source current (Ids), as a function of time. The two processes have different rates, with the latter being the slowest. Incorporating propylene carbonate in the electrolyte proved to be an effective solution to increase the ionic conductivity, to lower the viscosity and, consequently, to reduce the transistor response time. Finally, we were able to demonstrate a multifunctional device integrating the transistor logic function with that of energy storage in a supercapacitor: the TransCap. The polymer/electrolyte/carbon vertical stacking of the EG transistor features the cell configuration of a hybrid supercapacitor. Supercapacitors are high specific power systems that, for their ability to store/deliver charge within short times may outperform batteries in applications having high power demand. When the TransCap is ON (open transistor channel), the polymer and the carbon gate electrodes store charge (Q) at a given Vgs, hence the stored energy equals Q˙V gs. When the TransCap is switched OFF, the channel and the gate are discharged and the energy can be delivered back to power other electronic components. EG transistors, making use of activated carbon as gate electrode and different RTILs as well as RTIL solvent mixtures as electrolyte gating medium, are interesting towards low voltage printable electronics. The high capacitance at the interface between the electrolyte and the transistor channel enables

Fabrication and independent control of patterned polymer gate for a few-layer WSe{sub 2} field-effect transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hong, Sung Ju; Park, Min; Kang, Hojin

We report the fabrication of a patterned polymer electrolyte for a two-dimensional (2D) semiconductor, few-layer tungsten diselenide (WSe{sub 2}) field-effect transistor (FET). We expose an electron-beam in a desirable region to form the patterned structure. The WSe{sub 2} FET acts as a p-type semiconductor in both bare and polymer-covered devices. We observe a highly efficient gating effect in the polymer-patterned device with independent gate control. The patterned polymer gate operates successfully in a molybdenum disulfide (MoS{sub 2}) FET, indicating the potential for general applications to 2D semiconductors. The results of this study can contribute to large-scale integration and better flexibilitymore » in transition metal dichalcogenide (TMD)-based electronics.« less

Graphene field effect transistor without an energy gap.

PubMed

Jang, Min Seok; Kim, Hyungjun; Son, Young-Woo; Atwater, Harry A; Goddard, William A

2013-05-28

Graphene is a room temperature ballistic electron conductor and also a very good thermal conductor. Thus, it has been regarded as an ideal material for postsilicon electronic applications. A major complication is that the relativistic massless electrons in pristine graphene exhibit unimpeded Klein tunneling penetration through gate potential barriers. Thus, previous efforts to realize a field effect transistor for logic applications have assumed that introduction of a band gap in graphene is a prerequisite. Unfortunately, extrinsic treatments designed to open a band gap seriously degrade device quality, yielding very low mobility and uncontrolled on/off current ratios. To solve this dilemma, we propose a gating mechanism that leads to a hundredfold enhancement in on/off transmittance ratio for normally incident electrons without any band gap engineering. Thus, our saw-shaped geometry gate potential (in place of the conventional bar-shaped geometry) leads to switching to an off state while retaining the ultrahigh electron mobility in the on state. In particular, we report that an on/off transmittance ratio of 130 is achievable for a sawtooth gate with a gate length of 80 nm. Our switching mechanism demonstrates that intrinsic graphene can be used in designing logic devices without serious alteration of the conventional field effect transistor architecture. This suggests a new variable for the optimization of the graphene-based device--geometry of the gate electrode.

Significance of the gate voltage-dependent mobility in the electrical characterization of organic field effect transistors

NASA Astrophysics Data System (ADS)

Kim, Jong Beom; Lee, Dong Ryeol

2018-04-01

We studied the effect of the addition of free hole- and electron-rich organic molecules to organic semiconductors (OSCs) in organic field effect transistors (OFETs) on the gate voltage-dependent mobility. The drain current versus gate voltage characteristics were quantitatively analyzed using an OFET mobility model of power law behavior based on hopping transport in an OSC. This analysis distinguished the threshold voltage shifts, depending on the materials and structures of the OFET device, and properly estimated the hopping transport of the charge carriers induced by the gate bias within the OSC from the power law exponent parameter. The addition of pentacene or C60 molecules to a one-monolayer pentacene-based OFET shifted the threshold voltages negatively or positively, respectively, due to the structural changes that occurred in the OFET device. On the other hand, the power law parameters revealed that the addition of charge carriers of the same or opposite polarity enhanced or hindered hopping transport, respectively. This study revealed the need for a quantitative analysis of the gate voltage-dependent mobility while distinguishing this effect from the threshold voltage effect in order to understand OSC hopping transport in OFETs.

Characterization of a vertically movable gate field effect transistor using a silicon-on-insulator wafer

NASA Astrophysics Data System (ADS)

Song, In-Hyouk; Forfang, William B. D.; Cole, Bryan; You, Byoung Hee

2014-10-01

The vertically movable gate field effect transistor (VMGFET) is a FET-based sensing element, whose gate moves in a vertical direction over the channel. A VMGFET gate covers the region between source and drain. A 1 μm thick air layer separates the gate and the substrate of the VMGFET. A novel fabrication process to form a VMGFET using a silicon-on-insulator (SOI) wafer provides minimal internal stress of the gate structure. The enhancement-type n-channel VMGFET is fabricated with the threshold voltage of 2.32 V in steady state. A non-inverting amplifier is designed and integrated on a printable circuit board (PCB) to characterize device sensitivity and mechanical properties. The VMGFET is mechanically coupled to a speaker membrane to apply mechanical vibration. The oscillated drain current of FET are monitored and sampled with NI LabVIEW. The frequency of the output signal correlates with that of the input stimulus. The resonance frequency of the fabricated VMGFET is measured to be 1.11 kHz. The device sensitivity linearly increases by 0.106 mV/g Hz in the range of 150 Hz and 1 kHz.

Effects of floating gate structures on the two-dimensional electron gas density and electron mobility in AlGaN/AlN/GaN heterostructure field-effect transistors

NASA Astrophysics Data System (ADS)

Zhao, Jingtao; Zhao, Zhenguo; Chen, Zidong; Lin, Zhaojun; Xu, Fukai

2017-12-01

In this study, we have investigated the electrical properties of the AlGaN/AlN/GaN heterostructure field-effect transistors (HFETs) with floating gate structures using the measured capacitancevoltage (C-V) and current-voltage (I-V) characteristics. It is found that the two-dimensional electron gas (2DEG) density under the central gate cannot be changed by the floating gate structures. However, the floating gate structures can cause the strain variation in the barrier layer, which lead to the non-uniform distribution of the polarization charges, then induce a polarization Coulomb field and scatter the 2DEG. More floating gate structures and closer distance between the floating gates and the central gate will result in stronger scattering effect of the 2DEG.

Hopping and trapping mechanisms in organic field-effect transistors

NASA Astrophysics Data System (ADS)

Konezny, S. J.; Bussac, M. N.; Zuppiroli, L.

2010-01-01

A charge carrier in the channel of an organic field-effect transistor (OFET) is coupled to the electric polarization of the gate in the form of a surface Fröhlich polaron [N. Kirova and M. N. Bussac, Phys. Rev. B 68, 235312 (2003)]. We study the effects of the dynamical field of polarization on both small-polaron hopping and trap-limited transport mechanisms. We present numerical calculations of polarization energies, band-narrowing effects due to polarization, hopping barriers, and interface trap depths in pentacene and rubrene transistors as functions of the dielectric constant of the gate insulator and demonstrate that a trap-and-release mechanism more appropriately describes transport in high-mobility OFETs. For mobilities on the order 0.1cm2/Vs and below, all states are highly localized and hopping becomes the predominant mechanism.

'Soft' amplifier circuits based on field-effect ionic transistors.

PubMed

Boon, Niels; Olvera de la Cruz, Monica

2015-06-28

Soft materials can be used as the building blocks for electronic devices with extraordinary properties. We introduce a theoretical model for a field-effect transistor in which ions are the gated species instead of electrons. Our model incorporates readily-available soft materials, such as conductive porous membranes and polymer-electrolytes to represent a device that regulates ion currents and can be integrated as a component in larger circuits. By means of Nernst-Planck numerical simulations as well as an analytical description of the steady-state current we find that the responses of the system to various input voltages can be categorized into ohmic, sub-threshold, and active modes. This is fully analogous to what is known for the electronic field-effect transistor (FET). Pivotal FET properties such as the threshold voltage and the transconductance crucially depend on the half-cell redox potentials of the source and drain electrodes as well as on the polyelectrolyte charge density and the gate material work function. We confirm the analogy with the electronic FETs through numerical simulations of elementary amplifier circuits in which we successfully substitute the electronic transistor by an ionic transistor.

Microscopic gate-modulation imaging of charge and field distribution in polycrystalline organic transistors

NASA Astrophysics Data System (ADS)

Matsuoka, Satoshi; Tsutsumi, Jun'ya; Kamata, Toshihide; Hasegawa, Tatsuo

2018-04-01

In this work, a high-resolution microscopic gate-modulation imaging (μ-GMI) technique is successfully developed to visualize inhomogeneous charge and electric field distributions in operating organic thin-film transistors (TFTs). We conduct highly sensitive and diffraction-limit gate-modulation sensing for acquiring difference images of semiconducting channels between at gate-on and gate-off states that are biased at an alternate frequency of 15 Hz. As a result, we observe unexpectedly inhomogeneous distribution of positive and negative local gate-modulation (GM) signals at a probe photon energy of 1.85 eV in polycrystalline pentacene TFTs. Spectroscopic analyses based on a series of μ-GMI at various photon energies reveal that two distinct effects appear, simultaneously, within the polycrystalline pentacene channel layers: Negative GM signals at 1.85 eV originate from the second-derivative-like GM spectrum which is caused by the effect of charge accumulation, whereas positive GM signals originate from the first-derivative-like GM spectrum caused by the effect of leaked gate fields. Comparisons with polycrystalline morphologies indicate that grain centers are predominated by areas with high leaked gate fields due to the low charge density, whereas grain edges are predominantly high-charge-density areas with a certain spatial extension as associated with the concentrated carrier traps. Consequently, it is reasonably understood that larger grains lead to higher device mobility, but with greater inhomogeneity in charge distribution. These findings provide a clue to understand and improve device characteristics of polycrystalline TFTs.

A comparative study on top-gated and bottom-gated multilayer MoS2 transistors with gate stacked dielectric of Al2O3/HfO2.

PubMed

Zou, Xiao; Xu, Jingping; Huang, Hao; Zhu, Ziqang; Wang, Hongjiu; Li, Borui; Liao, Lei; Fang, Guojia

2018-06-15

Top-gated and bottom-gated transistors with multilayer MoS 2 channel fully encapsulated by stacked Al 2 O 3 /HfO 2 (9 nm/6 nm) were fabricated and comparatively studied. Excellent electrical properties are demonstrated for the TG transistors with high on-off current ratio of 10 8 , high field-effect mobility of 10 2 cm 2 V -1 s -1 , and low subthreshold swing of 93 mV dec -1 . Also, enhanced reliability has been achieved for the TG transistors with threshold voltage shift of 10 -3 -10 -2 V MV -1 cm -1 after 6 MV cm -1 gate-biased stressing. All improvement for the TG device can be ascribed to the formed device structure and dielectric environment. Degradation of the performance for the BG transistors should be attributed to reduced gate capacitance density and deteriorated interface properties related to vdW gap with a thickness about 0.4 nm. So, the TG transistor with MoS 2 channel fully encapsulated by stacked Al 2 O 3 /HfO 2 is a promising way to fabricate high-performance ML MoS 2 field-effect transistors for practical electron device applications.

A comparative study on top-gated and bottom-gated multilayer MoS2 transistors with gate stacked dielectric of Al2O3/HfO2

NASA Astrophysics Data System (ADS)

Zou, Xiao; Xu, Jingping; Huang, Hao; Zhu, Ziqang; Wang, Hongjiu; Li, Borui; Liao, Lei; Fang, Guojia

2018-06-01

Top-gated and bottom-gated transistors with multilayer MoS2 channel fully encapsulated by stacked Al2O3/HfO2 (9 nm/6 nm) were fabricated and comparatively studied. Excellent electrical properties are demonstrated for the TG transistors with high on–off current ratio of 108, high field-effect mobility of 102 cm2 V‑1 s‑1, and low subthreshold swing of 93 mV dec–1. Also, enhanced reliability has been achieved for the TG transistors with threshold voltage shift of 10‑3–10‑2 V MV–1 cm–1 after 6 MV cm‑1 gate-biased stressing. All improvement for the TG device can be ascribed to the formed device structure and dielectric environment. Degradation of the performance for the BG transistors should be attributed to reduced gate capacitance density and deteriorated interface properties related to vdW gap with a thickness about 0.4 nm. So, the TG transistor with MoS2 channel fully encapsulated by stacked Al2O3/HfO2 is a promising way to fabricate high-performance ML MoS2 field-effect transistors for practical electron device applications.

Interfacial fields in organic field-effect transistors and sensors

NASA Astrophysics Data System (ADS)

Dawidczyk, Thomas J.

Organic electronics are currently being commercialized and present a viable alternative to conventional electronics. These organic materials offer the ability to chemically manipulate the molecule, allowing for more facile mass processing techniques, which in turn reduces the cost. One application where organic semiconductors (OSCs) are being investigated is sensors. This work evaluates an assortment of n- and p-channel semiconductors as organic field-effect transistor (OFET) sensors. The sensor responses to dinitrotoluene (DNT) vapor and solid along with trinitrotoluene (TNT) solid were studied. Different semiconductor materials give different magnitude and direction of electrical current response upon exposure to DNT. Additional OFET parameters---mobility and threshold voltage---further refine the response to the DNT with each OFET sensor requiring a certain gate voltage for an optimized response to the vapor. The pattern of responses has sufficient diversity to distinguish DNT from other vapors. To effectively use these OFET sensors in a circuit, the threshold voltage needs to be tuned for each transistor to increase the efficiency of the circuit and maximize the sensor response. The threshold voltage can be altered by embedding charges into the dielectric layer of the OFET. To study the quantity and energy of charges needed to alter the threshold voltage, charge carriers were injected into polystyrene (PS) and investigated with scanning Kelvin probe microscopy (SKPM) and thermally stimulated discharge current (TSDC). Lateral heterojunctions of pentacene/PS were scanned using SKPM, effectively observing polarization along a side view of a lateral nonvolatile organic field-effect transistor dielectric interface. TSDC was used to observe charge migration out of PS films and to estimate the trap energy level inside the PS, using the initial rise method. The process was further refined to create lateral heterojunctions that were actual working OFETs, consisting of a

Programmable Schottky Junctions Based on Ferroelectric Gated MoS2 Transistors

NASA Astrophysics Data System (ADS)

Xiao, Zhiyong; Song, Jingfeng; Drcharme, Stephen; Hong, Xia

We report a programmable Schottky junction based on MoS2 field effect transistors with a SiO2 back gate and a ferroelectric copolymer poly(vinylidene-fluoride-trifluorethylene) (PVDF) top gate. We fabricated mechanically exfoliated single layer MoS2 flakes into two point devices via e-beam lithography, and deposited on the top of the devices ~20 nm PVDF thin films. The polarization of the PVDF layer is controlled locally by conducting atomic force microscopy. The devices exhibit linear ID-VD characteristics when the ferroelectric gate is uniformly polarized in one direction. We then polarized the gate into two domains with opposite polarization directions, and observed that the ID-VD characteristics of the MoS2 channel can be modulated between linear and rectified behaviors depending on the back gate voltage. The nonlinear ID-VD relation emerges when half of the channel is in the semiconductor phase while the other half is in the metallic phase, and it can be well described by the thermionic emission model with a Schottky barrier of ~0.5 eV. The Schottky junction can be erased by re-write the entire channel in the uniform polarization state. Our study facilitates the development of programmable, multifunctional nanoelectronics based on layered 2D TMDs..

Capacitorless one-transistor dynamic random-access memory based on asymmetric double-gate Ge/GaAs-heterojunction tunneling field-effect transistor with n-doped boosting layer and drain-underlap structure

NASA Astrophysics Data System (ADS)

Yoon, Young Jun; Seo, Jae Hwa; Kang, In Man

2018-04-01

In this work, we present a capacitorless one-transistor dynamic random-access memory (1T-DRAM) based on an asymmetric double-gate Ge/GaAs-heterojunction tunneling field-effect transistor (TFET) for DRAM applications. The n-doped boosting layer and gate2 drain-underlap structure is employed in the device to obtain an excellent 1T-DRAM performance. The n-doped layer inserted between the source and channel regions improves the sensing margin because of a high rate of increase in the band-to-band tunneling (BTBT) probability. Furthermore, because the gate2 drain-underlap structure reduces the recombination rate that occurs between the gate2 and drain regions, a device with a gate2 drain-underlap length (L G2_D-underlap) of 10 nm exhibited a longer retention performance. As a result, by applying the n-doped layer and gate2 drain-underlap structure, the proposed device exhibited not only a high sensing margin of 1.11 µA/µm but also a long retention time of greater than 100 ms at a temperature of 358 K (85 °C).

High performance top-gated ferroelectric field effect transistors based on two-dimensional ZnO nanosheets

NASA Astrophysics Data System (ADS)

Tian, Hongzheng; Wang, Xudong; Zhu, Yuankun; Liao, Lei; Wang, Xianying; Wang, Jianlu; Hu, Weida

2017-01-01

High quality ultrathin two-dimensional zinc oxide (ZnO) nanosheets (NSs) are synthesized, and the ZnO NS ferroelectric field effect transistors (FeFETs) are demonstrated based on the P(VDF-TrFE) polymer film used as the top gate insulating layer. The ZnO NSs exhibit a maximum field effect mobility of 588.9 cm2/Vs and a large transconductance of 2.5 μS due to their high crystalline quality and ultrathin two-dimensional structure. The polarization property of the P(VDF-TrFE) film is studied, and a remnant polarization of >100 μC/cm2 is achieved with a P(VDF-TrFE) thickness of 300 nm. Because of the ultrahigh remnant polarization field generated in the P(VDF-TrFE) film, the FeFETs show a large memory window of 16.9 V and a high source-drain on/off current ratio of more than 107 at zero gate voltage and a source-drain bias of 0.1 V. Furthermore, a retention time of >3000 s of the polarization state is obtained, inspiring a promising candidate for applications in data storage with non-volatile features.

Slowing DNA Translocation in a Nanofluidic Field-Effect Transistor.

PubMed

Liu, Yifan; Yobas, Levent

2016-04-26

Here, we present an experimental demonstration of slowing DNA translocation across a nanochannel by modulating the channel surface charge through an externally applied gate bias. The experiments were performed on a nanofluidic field-effect transistor, which is a monolithic integrated platform featuring a 50 nm-diameter in-plane alumina nanocapillary whose entire length is surrounded by a gate electrode. The field-effect transistor behavior was validated on the gating of ionic conductance and protein transport. The gating of DNA translocation was subsequently studied by measuring discrete current dips associated with single λ-DNA translocation events under a source-to-drain bias of 1 V. The translocation speeds under various gate bias conditions were extracted by fitting event histograms of the measured translocation time to the first passage time distributions obtained from a simple 1D biased diffusion model. A positive gate bias was observed to slow the translocation of single λ-DNA chains markedly; the translocation speed was reduced by an order of magnitude from 18.4 mm/s obtained under a floating gate down to 1.33 mm/s under a positive gate bias of 9 V. Therefore, a dynamic and flexible regulation of the DNA translocation speed, which is vital for single-molecule sequencing, can be achieved on this device by simply tuning the gate bias. The device is realized in a conventional semiconductor microfabrication process without the requirement of advanced lithography, and can be potentially further developed into a compact electronic single-molecule sequencer.

Improving the radiation hardness of graphene field effect transistors

DOE PAGES

Alexandrou, Konstantinos; Masurkar, Amrita; Edrees, Hassan; ...

2016-10-11

Ionizing radiation poses a significant challenge to the operation and reliability of conventional silicon-based devices. In this paper, we report the effects of gamma radiation on graphene field-effect transistors (GFETs), along with a method to mitigate those effects by developing a radiation-hardened version of our back-gated GFETs. We demonstrate that activated atmospheric oxygen from the gamma ray interaction with air damages the semiconductor device, and damage to the substrate contributes additional threshold voltage instability. Our radiation-hardened devices, which have protection against these two effects, exhibit minimal performance degradation, improved stability, and significantly reduced hysteresis after prolonged gamma radiation exposure. Finally,more » we believe this work provides an insight into graphene's interactions with ionizing radiation that could enable future graphene-based electronic devices to be used for space, military, and other radiation-sensitive applications.« less

Improving the radiation hardness of graphene field effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Alexandrou, Konstantinos; Masurkar, Amrita; Edrees, Hassan

Ionizing radiation poses a significant challenge to the operation and reliability of conventional silicon-based devices. In this paper, we report the effects of gamma radiation on graphene field-effect transistors (GFETs), along with a method to mitigate those effects by developing a radiation-hardened version of our back-gated GFETs. We demonstrate that activated atmospheric oxygen from the gamma ray interaction with air damages the semiconductor device, and damage to the substrate contributes additional threshold voltage instability. Our radiation-hardened devices, which have protection against these two effects, exhibit minimal performance degradation, improved stability, and significantly reduced hysteresis after prolonged gamma radiation exposure. Finally,more » we believe this work provides an insight into graphene's interactions with ionizing radiation that could enable future graphene-based electronic devices to be used for space, military, and other radiation-sensitive applications.« less

Influence of the gate position on source-to-drain resistance in AlGaN/AlN/GaN heterostructure field-effect transistors

NASA Astrophysics Data System (ADS)

Liu, Yan; Lin, Zhaojun; Cui, Peng; Zhao, Jingtao; Fu, Chen; Yang, Ming; Lv, Yuanjie

2017-08-01

Using a suitable dual-gate structure, the source-to-drain resistance (RSD) of AlGaN/AlN/GaN heterostructure field-effect transistor (HFET) with varying gate position has been studied at room temperature. The theoretical and experimental results have revealed a dependence of RSD on the gate position. The variation of RSD with the gate position is found to stem from the polarization Coulomb field (PCF) scattering. This finding is of great benefit to the optimization of the performance of AlGaN/AlN/GaN HFET. Especially, when the AlGaN/AlN/GaN HFET works as a microwave device, it is beneficial to achieve the impedance matching by designing the appropriate gate position based on PCF scattering.

Demonstration of large field effect in topological insulator films via a high-κ back gate

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, C. Y.; Lin, H. Y.; Yang, S. R.

2016-05-16

The spintronics applications long anticipated for topological insulators (TIs) has been hampered due to the presence of high density intrinsic defects in the bulk states. In this work we demonstrate the back-gating effect on TIs by integrating Bi{sub 2}Se{sub 3} films 6–10 quintuple layer (QL) thick with amorphous high-κ oxides of Al{sub 2}O{sub 3} and Y{sub 2}O{sub 3}. Large gating effect of tuning the Fermi level E{sub F} to very close to the band gap was observed, with an applied bias of an order of magnitude smaller than those of the SiO{sub 2} back gate, and the modulation of filmmore » resistance can reach as high as 1200%. The dependence of the gating effect on the TI film thickness was investigated, and ΔN{sub 2D}/ΔV{sub g} varies with TI film thickness as ∼t{sup −0.75}. To enhance the gating effect, a Y{sub 2}O{sub 3} layer thickness 4 nm was inserted into Al{sub 2}O{sub 3} gate stack to increase the total κ value to 13.2. A 1.4 times stronger gating effect is observed, and the increment of induced carrier numbers is in good agreement with additional charges accumulated in the higher κ oxides. Moreover, we have reduced the intrinsic carrier concentration in the TI film by doping Te to Bi{sub 2}Se{sub 3} to form Bi{sub 2}Te{sub x}Se{sub 1−x}. The observation of a mixed state of ambipolar field that both electrons and holes are present indicates that we have tuned the E{sub F} very close to the Dirac Point. These results have demonstrated that our capability of gating TIs with high-κ back gate to pave the way to spin devices of tunable E{sub F} for dissipationless spintronics based on well-established semiconductor technology.« less

Method for double-sided processing of thin film transistors

DOEpatents

Yuan, Hao-Chih; Wang, Guogong; Eriksson, Mark A.; Evans, Paul G.; Lagally, Max G.; Ma, Zhenqiang

2008-04-08

This invention provides methods for fabricating thin film electronic devices with both front- and backside processing capabilities. Using these methods, high temperature processing steps may be carried out during both frontside and backside processing. The methods are well-suited for fabricating back-gate and double-gate field effect transistors, double-sided bipolar transistors and 3D integrated circuits.

Short-channel field-effect transistors with 9-atom and 13-atom wide graphene nanoribbons

DOE Office of Scientific and Technical Information (OSTI.GOV)

Llinas, Juan Pablo; Fairbrother, Andrew; Borin Barin, Gabriela

Bottom-up synthesized graphene nanoribbons and graphene nanoribbon heterostructures have promising electronic properties for high-performance field-effect transistors and ultra-low power devices such as tunneling field-effect transistors. However, the short length and wide band gap of these graphene nanoribbons have prevented the fabrication of devices with the desired performance and switching behavior. Here, by fabricating short channel (L ch ~ 20 nm) devices with a thin, high-κ gate dielectric and a 9-atom wide (0.95 nm) armchair graphene nanoribbon as the channel material, we demonstrate field-effect transistors with high on-current (I on > 1 μA at V d = -1 V) and highmore » I on /I off ~ 10 5 at room temperature. We find that the performance of these devices is limited by tunneling through the Schottky barrier at the contacts and we observe an increase in the transparency of the barrier by increasing the gate field near the contacts. Our results thus demonstrate successful fabrication of high-performance short-channel field-effect transistors with bottom-up synthesized armchair graphene nanoribbons.« less

Short-channel field-effect transistors with 9-atom and 13-atom wide graphene nanoribbons

DOE PAGES

Llinas, Juan Pablo; Fairbrother, Andrew; Borin Barin, Gabriela; ...

2017-09-21

Bottom-up synthesized graphene nanoribbons and graphene nanoribbon heterostructures have promising electronic properties for high-performance field-effect transistors and ultra-low power devices such as tunneling field-effect transistors. However, the short length and wide band gap of these graphene nanoribbons have prevented the fabrication of devices with the desired performance and switching behavior. Here, by fabricating short channel (L ch ~ 20 nm) devices with a thin, high-κ gate dielectric and a 9-atom wide (0.95 nm) armchair graphene nanoribbon as the channel material, we demonstrate field-effect transistors with high on-current (I on > 1 μA at V d = -1 V) and highmore » I on /I off ~ 10 5 at room temperature. We find that the performance of these devices is limited by tunneling through the Schottky barrier at the contacts and we observe an increase in the transparency of the barrier by increasing the gate field near the contacts. Our results thus demonstrate successful fabrication of high-performance short-channel field-effect transistors with bottom-up synthesized armchair graphene nanoribbons.« less

Role of deposition and annealing of the top gate dielectric in a-IGZO TFT-based dual-gate ion-sensitive field-effect transistors

NASA Astrophysics Data System (ADS)

Kumar, Narendra; Sutradhar, Moitri; Kumar, Jitendra; Panda, Siddhartha

2017-03-01

The deposition of the top gate dielectric in thin film transistor (TFT)-based dual-gate ion-sensitive field-effect transistors (DG ISFETs) is critical, and expected not to affect the bottom gate TFT characteristics, while providing a higher pH sensitive surface and efficient capacitive coupling between the gates. Amorphous Ta2O5, in addition to having good sensing properties, possesses a high dielectric constant of ˜25 making it well suited as the top gate dielectric in a DG ISFET by providing higher capacitive coupling (ratio of C top/C bottom) leading to higher amplification. To avoid damage of the a-IGZO channel reported to be caused by plasma exposure, deposition of Ta2O5 by e-beam evaporation followed by annealing was investigated in this work to obtain sensitivity over the Nernst limit. The deteriorated bottom gate TFT characteristics, indicated by an increase in the channel conductance, confirmed that plasma exposure is not the sole contributor to the changes. Oxygen vacancies at the Ta2O5/a-IGZO interface, which emerged during processing, increased the channel conductivity, became filled by optimum annealing in oxygen at 400 °C for 1 h, which was confirmed by an x-ray photoelectron spectroscopy depth profiling analysis. The obtained pH sensitivity of the TFT-based DG ISFET was 402 mV pH-1, which is about 6.8 times the Nernst limit (59 mV pH-1). The concept of capacitive coupling was also demonstrated by simulating an a-IGZO-based DG TFT structure. Here, the exposure of the top gate dielectric to the electrolyte without applying any top gate bias led to changes in the measured threshold voltage of the bottom gate TFT, and this obviated the requirement of a reference electrode needed in conventional ISFETs and other reported DG ISFETs. These devices, with high sensitivities and requiring low volumes (˜2 μl) of analyte solution, could be potential candidates for utilization as chemical sensors and biosensors.

Carbon nanotube feedback-gate field-effect transistor: suppressing current leakage and increasing on/off ratio.

PubMed

Qiu, Chenguang; Zhang, Zhiyong; Zhong, Donglai; Si, Jia; Yang, Yingjun; Peng, Lian-Mao

2015-01-27

Field-effect transistors (FETs) based on moderate or large diameter carbon nanotubes (CNTs) usually suffer from ambipolar behavior, large off-state current and small current on/off ratio, which are highly undesirable for digital electronics. To overcome these problems, a feedback-gate (FBG) FET structure is designed and tested. This FBG FET differs from normal top-gate FET by an extra feedback-gate, which is connected directly to the drain electrode of the FET. It is demonstrated that a FBG FET based on a semiconducting CNT with a diameter of 1.5 nm may exhibit low off-state current of about 1 × 10(-13) A, high current on/off ratio of larger than 1 × 10(8), negligible drain-induced off-state leakage current, and good subthreshold swing of 75 mV/DEC even at large source-drain bias and room temperature. The FBG structure is promising for CNT FETs to meet the standard for low-static-power logic electronics applications, and could also be utilized for building FETs using other small band gap semiconductors to suppress leakage current.

CMOS integration of high-k/metal gate transistors in diffusion and gate replacement (D&GR) scheme for dynamic random access memory peripheral circuits

NASA Astrophysics Data System (ADS)

Dentoni Litta, Eugenio; Ritzenthaler, Romain; Schram, Tom; Spessot, Alessio; O’Sullivan, Barry; Machkaoutsan, Vladimir; Fazan, Pierre; Ji, Yunhyuck; Mannaert, Geert; Lorant, Christophe; Sebaai, Farid; Thiam, Arame; Ercken, Monique; Demuynck, Steven; Horiguchi, Naoto

2018-04-01

Integration of high-k/metal gate stacks in peripheral transistors is a major candidate to ensure continued scaling of dynamic random access memory (DRAM) technology. In this paper, the CMOS integration of diffusion and gate replacement (D&GR) high-k/metal gate stacks is investigated, evaluating four different approaches for the critical patterning step of removing the N-type field effect transistor (NFET) effective work function (eWF) shifter stack from the P-type field effect transistor (PFET) area. The effect of plasma exposure during the patterning step is investigated in detail and found to have a strong impact on threshold voltage tunability. A CMOS integration scheme based on an experimental wet-compatible photoresist is developed and the fulfillment of the main device metrics [equivalent oxide thickness (EOT), eWF, gate leakage current density, on/off currents, short channel control] is demonstrated.

P-channel differential multiple-time programmable memory cells by laterally coupled floating metal gate fin field-effect transistors

NASA Astrophysics Data System (ADS)

Wang, Tai-Min; Chien, Wei-Yu; Hsu, Chia-Ling; Lin, Chrong Jung; King, Ya-Chin

2018-04-01

In this paper, we present a new differential p-channel multiple-time programmable (MTP) memory cell that is fully compatible with advanced 16 nm CMOS fin field-effect transistors (FinFET) logic processes. This differential MTP cell stores complementary data in floating gates coupled by a slot contact structure, which make different read currents possible on a single cell. In nanoscale CMOS FinFET logic processes, the gate dielectric layer becomes too thin to retain charges inside floating gates for nonvolatile data storage. By using a differential architecture, the sensing window of the cell can be extended and maintained by an advanced blanket boost scheme. The charge retention problem in floating gate cells can be improved by periodic restoring lost charges when significant read window narrowing occurs. In addition to high programming efficiency, this p-channel MTP cells also exhibit good cycling endurance as well as disturbance immunity. The blanket boost scheme can remedy the charge loss problem under thin gate dielectrics.

Nanopore extended field-effect transistor for selective single-molecule biosensing.

PubMed

Ren, Ren; Zhang, Yanjun; Nadappuram, Binoy Paulose; Akpinar, Bernice; Klenerman, David; Ivanov, Aleksandar P; Edel, Joshua B; Korchev, Yuri

2017-09-19

There has been a significant drive to deliver nanotechnological solutions to biosensing, yet there remains an unmet need in the development of biosensors that are affordable, integrated, fast, capable of multiplexed detection, and offer high selectivity for trace analyte detection in biological fluids. Herein, some of these challenges are addressed by designing a new class of nanoscale sensors dubbed nanopore extended field-effect transistor (nexFET) that combine the advantages of nanopore single-molecule sensing, field-effect transistors, and recognition chemistry. We report on a polypyrrole functionalized nexFET, with controllable gate voltage that can be used to switch on/off, and slow down single-molecule DNA transport through a nanopore. This strategy enables higher molecular throughput, enhanced signal-to-noise, and even heightened selectivity via functionalization with an embedded receptor. This is shown for selective sensing of an anti-insulin antibody in the presence of its IgG isotype.Efficient detection of single molecules is vital to many biosensing technologies, which require analytical platforms with high selectivity and sensitivity. Ren et al. combine a nanopore sensor and a field-effect transistor, whereby gate voltage mediates DNA and protein transport through the nanopore.

Cycle of charge carrier states with formation and extinction of a floating gate in an ambipolar tetracyanoquaterthienoquinoid-based field-effect transistor

NASA Astrophysics Data System (ADS)

Itoh, Takuro; Toyota, Taro; Higuchi, Hiroyuki; Matsushita, Michio M.; Suzuki, Kentaro; Sugawara, Tadashi

2017-03-01

A tetracyanoquaterthienoquinoid (TCT4Q)-based field effect transistor is characterized by the ambipolar transfer characteristics and the facile shift of the threshold voltage induced by the bias stress. The trapping and detrapping kinetics of charge carriers was investigated in detail by the temperature dependence of the decay of source-drain current (ISD). We found a repeatable formation of a molecular floating gate is derived from a 'charge carrier-and-gate' cycle comprising four stages, trapping of mobile carriers, formation of a floating gate, induction of oppositely charged mobile carriers, and recombination between mobile and trapped carriers to restore the initial state.

Highly stable organic field-effect transistors with engineered gate dielectrics (Conference Presentation)

NASA Astrophysics Data System (ADS)

Kippelen, Bernard; Wang, Cheng-Yin; Fuentes-Hernandez, Canek; Yun, Minseong; Singh, Ankit K.; Dindar, Amir; Choi, Sangmoo; Graham, Samuel

2016-11-01

Organic field-effect transistors (OFETs) have the potential to lead to low-cost flexible displays, wearable electronics, and sensors. While recent efforts have focused greatly on improving the maximum charge mobility that can be achieved in such devices, studies about the stability and reliability of such high performance devices are relatively scarce. In this talk, we will discuss the results of recent studies aimed at improving the stability of OFETs under operation and their shelf lifetime. In particular, we will focus on device architectures where the gate dielectric is engineered to act simultaneously as an environmental barrier layer. In the past, our group had demonstrated solution-processed top-gate OFETs using TIPS-pentacene and PTAA blends as a semiconductor layer with a bilayer gate dielectric layer of CYTOP/Al2O3, where the oxide layer was fabricated by atomic layer deposition, ALD. Such devices displayed high operational stability with little degradation after 20,000 on/off scan cycles or continuous operation (24 h), and high environmental stability when kept in air for more than 2 years, with unchanged carrier mobility. Using this stable device geometry, simple circuits and sensors operating in aqueous conditions were demonstrated. However, the Al2O3 layer was found to degrade due to corrosion under prolonged exposure in aqueous solutions. In this talk, we will report on the use of a nanolaminate (NL) composed of Al2O3 and HfO2 by ALD to replace the Al2O3 single layer in the bilayer gate dielectric use in top-gate OFETs. Such OFETs were found to operate under harsh condition such as immersion in water at 95 °C. This work was funded by the Department of Energy (DOE) through the Bay Area Photovoltaics Consortium (BAPVC) under Award Number DE-EE0004946.

Development of paper-gate transistor toward direct detection from microbiological fluids

NASA Astrophysics Data System (ADS)

Kajisa, Taira; Sakata, Toshiya

2017-04-01

In this study, a paper-gate transistor was developed to detect glucose using an extended-gate field-effect transistor (FET). A filter paper was used as an extended gate electrode, in which Au nanoparticles (AuNPs) modified with phenylboronic acids (PBAs) were included. PBA-AuNPs play an important role as a support to not only be entrapped in cellulose fibrils but also bind to the targeted glucose in a paper. The surface properties of PBA-AuNPs were investigated to elucidate the electrical properties of the paper-gate electrode using an absorption spectrum and a zeta potential analysis. Moreover, the paper-gate electrode enabled us to detect glucose at the micromolar level on the basis of the principle of FET devices. A platform based on the paper-gate transistor is suitable for a highly sensitive system to detect glucose in trace samples such as tears, sweat, and saliva in the future.

Interface passivation and trap reduction via hydrogen fluoride for molybdenum disulfide on silicon oxide back-gate transistors

NASA Astrophysics Data System (ADS)

Hu, Yaoqiao; San Yip, Pak; Tang, Chak Wah; Lau, Kei May; Li, Qiang

2018-04-01

Layered semiconductor molybdenum disulfide (MoS2) has recently emerged as a promising material for flexible electronic and optoelectronic devices because of its finite bandgap and high degree of gate control. Here, we report a hydrogen fluoride (HF) passivation technique for improving the carrier mobility and interface quality of chemical vapor deposited monolayer MoS2 on a SiO2/Si substrate. After passivation, the fabricated MoS2 back-gate transistors demonstrate a more than double improvement in average electron mobility, a reduced gate hysteresis gap of 3 V, and a low interface trapped charge density of ˜5.8 × 1011 cm-2. The improvements are attributed to the satisfied interface dangling bonds, thus a reduction of interface trap states and trapped charges. Surface x-ray photoelectron spectroscopy analysis and first-principles simulation were performed to verify the HF passivation effect. The results here highlight the necessity of a MoS2/dielectric passivation strategy and provides a viable route for enhancing the performance of MoS2 nano-electronic devices.

Transport Properties of Anatase-TiO2 Polycrystalline-Thin-Film Field-Effect Transistors with Electrolyte Gate Layers

NASA Astrophysics Data System (ADS)

Horita, Ryohei; Ohtani, Kyosuke; Kai, Takahiro; Murao, Yusuke; Nishida, Hiroya; Toya, Taku; Seo, Kentaro; Sakai, Mio; Okuda, Tetsuji

2013-11-01

We have fabricated anatase-TiO2 polycrystalline-thin-film field-effect transistors (FETs) with poly(vinyl alcohol) (PVA), ion-liquid (IL), and ion-gel (IG) gate layers, and have tried to improve the response to gate voltage by varying the concentration of mobile ions in these electrolyte gate layers. The increase in the concentration of mobile ions by doping NaOH into the PVA gate layer or reducing the gelator in the IG gate layer markedly increases the drain-source current and reduces the driving gate voltage, which show that the mobile ions in the PVA, IL, and IG gate layers cause the formation of electric double layers (EDLs), which act as nanogap capacitors. In these TiO2-EDL-FETs, the slow formation of EDLs and the oxidation reaction at the interface between the surface of the TiO2 film and the electrolytes cause unideal FET properties. In the optimized IL and IG TiO2-EDL-FETs, the driving gate voltage is less than 1 V and the ON/OFF ratios of the transfer characteristics are about 1×104 at RT, and the nearly metallic state is realized at the interface purely by applying a gate voltage.

Spin-dependent transport and current modulation in a current-in-plane spin-valve field-effect transistor

NASA Astrophysics Data System (ADS)

Kanaki, Toshiki; Koyama, Tomohiro; Chiba, Daichi; Ohya, Shinobu; Tanaka, Masaaki

2016-10-01

We propose a current-in-plane spin-valve field-effect transistor (CIP-SV-FET), which is composed of a ferromagnet/nonferromagnet/ferromagnet trilayer structure and a gate electrode. This is a promising device alternative to spin metal-oxide-semiconductor field-effect transistors. Here, we fabricate a ferromagnetic-semiconductor GaMnAs-based CIP-SV-FET and demonstrate its basic operation of the resistance modulation both by the magnetization configuration and by the gate electric field. Furthermore, we present the electric-field-assisted magnetization reversal in this device.

Performance analysis of InGaAs/GaAsP heterojunction double gate tunnel field effect transistor

NASA Astrophysics Data System (ADS)

Ahish, S.; Sharma, Dheeraj; Vasantha, M. H.; Kumar, Y. B. N.

2017-03-01

In this paper, analog/RF performance of InGaAs/GaAsP heterojunction double gate tunnel field effect transistor (HJTFET) has been explored. A highly doped n+ layer is placed at the Source-Channel junction in order to improve the horizontal electric field component and thus, improve the realiability of the device. The analog performance of the device is analysed by extracting current-voltage characteristics, transcondutance (gm), gate-to-drain capacitance (Cgd) and gate-to-source capacitance (Cgs). Further, RF performance of the device is evaluated by obtaining cut-off frequency (fT) and Gain Bandwidth (GBW) product. ION /IOFF ratio equal to ≈ 109, subthreshold slope of 27 mV/dec, maximum fT of 2.1 THz and maximum GBW of 484 GHz were achieved. Also, the impact of temperature variation on the linearity performance of the device has been investigated. Furthermore, the circuit level performance of the device is performed by implementing a Common Source (CS) amplifier; maximum gain of 31.11 dB and 3-dB cut-off frequency equal to 91.2 GHz were achieved for load resistance (RL) = 17.5 KΩ.

Highly sensitive protein detection using a plasmonic field effect transistor (Conference Presentation)

NASA Astrophysics Data System (ADS)

Shokri-Kojori, Hossein; Ji, Yiwen; Han, Xu; Paik, Younghun; Braunschweig, Adam; Kim, Sung Jin

2016-03-01

Localized surface Plasmon Resonance (LSPR) is a nanoscale phenomenon which presents strong resonance associated with noble metal nanostructures. This plasmon resonance based technology enables highly sensitive detection for chemical and biological applications. Recently, we have developed a plasmon field effect transistor (FET) that enables direct plasmonic-to-electric signal conversion with signal amplification. The plasmon FET consists of back-gated field effect transistor incorporated with gold nanoparticles on top of the FET channel. The gold nanostructures are physically separated from transistor electrodes and can be functionalized for a specific biological application. In this presentation, we report a successful demonstration of a model system to detect Con A proteins using Carbohydrate linkers as a capture molecule. The plasmon FET detected a very low concentration of Con A (0.006 mg/L) while it offers a wide dynamic range of 0.006-50 mg/L. In this demonstration, we used two-color light sources instead of a bulky spectrometer to achieve high sensitivity and wide dynamic range. The details of two-color based differential measurement method will be discussed. This novel protein-based sensor has several advantages such as extremely small size for point-of-care system, multiplexing capability, no need of complex optical geometry.

Water-Gated n-Type Organic Field-Effect Transistors for Complementary Integrated Circuits Operating in an Aqueous Environment.

PubMed

Porrazzo, Rossella; Luzio, Alessandro; Bellani, Sebastiano; Bonacchini, Giorgio Ernesto; Noh, Yong-Young; Kim, Yun-Hi; Lanzani, Guglielmo; Antognazza, Maria Rosa; Caironi, Mario

2017-01-31

The first demonstration of an n-type water-gated organic field-effect transistor (WGOFET) is here reported, along with simple water-gated complementary integrated circuits, in the form of inverting logic gates. For the n-type WGOFET active layer, high-electron-affinity organic semiconductors, including naphthalene diimide co-polymers and a soluble fullerene derivative, have been compared, with the latter enabling a high electric double layer capacitance in the range of 1 μF cm -2 in full accumulation and a mobility-capacitance product of 7 × 10 -3 μF/V s. Short-term stability measurements indicate promising cycling robustness, despite operating the device in an environment typically considered harsh, especially for electron-transporting organic molecules. This work paves the way toward advanced circuitry design for signal conditioning and actuation in an aqueous environment and opens new perspectives in the implementation of active bio-organic interfaces for biosensing and neuromodulation.

Extended Characterization of the Common-Source and Common-Gate Amplifiers using a Metal-Ferroelectric-Semiconductor Field Effect Transistor

NASA Technical Reports Server (NTRS)

Hunt, Mitchell; Sayyah, Rana; Mitchell, Cody; Laws, Crystal; MacLeod, Todd C.; Ho, Fat D.

2013-01-01

Collected data for both common-source and common-gate amplifiers is presented in this paper. Characterizations of the two amplifier circuits using metal-ferroelectric-semiconductor field effect transistors (MFSFETs) are developed with wider input frequency ranges and varying device sizes compared to earlier characterizations. The effects of the ferroelectric layer's capacitance and variation load, quiescent point, or input signal on each circuit are discussed. Comparisons between the MFSFET and MOSFET circuit operation and performance are discussed at length as well as applications and advantages for the MFSFETs.

Low-voltage operation of Si-based ferroelectric field effect transistors using organic ferroelectrics, poly(vinylidene fluoride-trifluoroethylene), as a gate dielectric

NASA Astrophysics Data System (ADS)

Miyata, Yusuke; Yoshimura, Takeshi; Ashida, Atsushi; Fujimura, Norifumi

2016-04-01

Si-based metal-ferroelectric-semiconductor (MFS) capacitors have been fabricated using poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] as a ferroelectric gate. The pinhole-free P(VDF-TrFE) thin films with high resistivity were able to be prepared by spin-coating directly onto hydrogen-terminated Si. The capacitance-voltage (C-V) characteristics of the ferroelectric gate field effect transistor (FeFET) using this MFS structure clearly show butterfly-shaped hysteresis originating from the ferroelectricity, indicating carrier modulation on the Si surface at gate voltages below 2 V. The drain current-gate voltage (I D-V G) characteristics also show counterclockwise hysteresis at gate voltages below 5 V. This is the first report on the low-voltage operation of a Si-based FeFET using P(VDF-TrFE) as a gate dielectric. This organic gate FeFET without any insulator layer at the ferroelectric/Si interface should be one of the promising devices for overcoming the critical issues of the FeFET, such as depolarization field and a decrease in the gate voltage.

Improved transfer of graphene for gated Schottky-junction, vertical, organic, field-effect transistors.

PubMed

Lemaitre, Maxime G; Donoghue, Evan P; McCarthy, Mitchell A; Liu, Bo; Tongay, Sefaattin; Gila, Brent; Kumar, Purushottam; Singh, Rajiv K; Appleton, Bill R; Rinzler, Andrew G

2012-10-23

An improved process for graphene transfer was used to demonstrate high performance graphene enabled vertical organic field effect transistors (G-VFETs). The process reduces disorder and eliminates the polymeric residue that typically plagues transferred films. The method also allows for purposely creating pores in the graphene of a controlled areal density. Transconductance observed in G-VFETs fabricated with a continuous (pore-free) graphene source electrode is attributed to modulation of the contact barrier height between the graphene and organic semiconductor due to a gate field induced Fermi level shift in the low density of electronic-states graphene electrode. Pores introduced in the graphene source electrode are shown to boost the G-VFET performance, which scales with the areal pore density taking advantage of both barrier height lowering and tunnel barrier thinning. Devices with areal pore densities of 20% exhibit on/off ratios and output current densities exceeding 10(6) and 200 mA/cm(2), respectively, at drain voltages below 5 V.

Solvothermal synthesis of gallium-indium-zinc-oxide nanoparticles for electrolyte-gated transistors.

PubMed

Santos, Lídia; Nunes, Daniela; Calmeiro, Tomás; Branquinho, Rita; Salgueiro, Daniela; Barquinha, Pedro; Pereira, Luís; Martins, Rodrigo; Fortunato, Elvira

2015-01-14

Solution-processed field-effect transistors are strategic building blocks when considering low-cost sustainable flexible electronics. Nevertheless, some challenges (e.g., processing temperature, reliability, reproducibility in large areas, and cost effectiveness) are requirements that must be surpassed in order to achieve high-performance transistors. The present work reports electrolyte-gated transistors using as channel layer gallium-indium-zinc-oxide nanoparticles produced by solvothermal synthesis combined with a solid-state electrolyte based on aqueous dispersions of vinyl acetate stabilized with cellulose derivatives, acrylic acid ester in styrene and lithium perchlorate. The devices fabricated using this approach display a ION/IOFF up to 1 × 10(6), threshold voltage (VTh) of 0.3-1.9 V, and mobility up to 1 cm(2)/(V s), as a function of gallium-indium-zinc-oxide ink formulation and two different annealing temperatures. These results validates the usage of electrolyte-gated transistors as a viable and promising alternative for nanoparticle based semiconductor devices as the electrolyte improves the interface and promotes a more efficient step coverage of the channel layer, reducing the operating voltage when compared with conventional dielectrics gating. Moreover, it is shown that by controlling the applied gate potential, the operation mechanism of the electrolyte-gated transistors can be modified from electric double layer to electrochemical doping.

Liquid-Solid Dual-Gate Organic Transistors with Tunable Threshold Voltage for Cell Sensing.

PubMed

Zhang, Yu; Li, Jun; Li, Rui; Sbircea, Dan-Tiberiu; Giovannitti, Alexander; Xu, Junling; Xu, Huihua; Zhou, Guodong; Bian, Liming; McCulloch, Iain; Zhao, Ni

2017-11-08

Liquid electrolyte-gated organic field effect transistors and organic electrochemical transistors have recently emerged as powerful technology platforms for sensing and simulation of living cells and organisms. For such applications, the transistors are operated at a gate voltage around or below 0.3 V because prolonged application of a higher voltage bias can lead to membrane rupturing and cell death. This constraint often prevents the operation of the transistors at their maximum transconductance or most sensitive regime. Here, we exploit a solid-liquid dual-gate organic transistor structure, where the threshold voltage of the liquid-gated conduction channel is controlled by an additional gate that is separated from the channel by a metal-oxide gate dielectric. With this design, the threshold voltage of the "sensing channel" can be linearly tuned in a voltage window exceeding 0.4 V. We have demonstrated that the dual-gate structure enables a much better sensor response to the detachment of human mesenchymal stem cells. In general, the capability of tuning the optimal sensing bias will not only improve the device performance but also broaden the material selection for cell-based organic bioelectronics.

Effects of negative gate-bias stress on the performance of solution-processed zinc-oxide transistors

NASA Astrophysics Data System (ADS)

Kim, Dongwook; Lee, Woo-Sub; Shin, Hyunji; Choi, Jong Sun; Zhang, Xue; Park, Jaehoon; Hwang, Jaeeun; Kim, Hongdoo; Bae, Jin-Hyuk

2014-08-01

We studied the effects of negative gate-bias stress on the electrical characteristics of top-contact zinc-oxide (ZnO) thin-film transistors (TFTs), which were fabricated by spin coating a ZnO solution onto a silicon-nitride gate dielectric layer. The negative gate-bias stress caused characteristic degradations in the on-state currents and the field-effect mobility of the fabricated ZnO TFTs. Additionally, a decrease in the off-state currents and a positive shift in the threshold voltage occurred with increasing stress time. These results indicate that the negative gate-bias stress caused an injection of electrons into the gate dielectric, thereby deteriorating the TFT's performance.

Short-channel field-effect transistors with 9-atom and 13-atom wide graphene nanoribbons.

PubMed

Llinas, Juan Pablo; Fairbrother, Andrew; Borin Barin, Gabriela; Shi, Wu; Lee, Kyunghoon; Wu, Shuang; Yong Choi, Byung; Braganza, Rohit; Lear, Jordan; Kau, Nicholas; Choi, Wonwoo; Chen, Chen; Pedramrazi, Zahra; Dumslaff, Tim; Narita, Akimitsu; Feng, Xinliang; Müllen, Klaus; Fischer, Felix; Zettl, Alex; Ruffieux, Pascal; Yablonovitch, Eli; Crommie, Michael; Fasel, Roman; Bokor, Jeffrey

2017-09-21

Bottom-up synthesized graphene nanoribbons and graphene nanoribbon heterostructures have promising electronic properties for high-performance field-effect transistors and ultra-low power devices such as tunneling field-effect transistors. However, the short length and wide band gap of these graphene nanoribbons have prevented the fabrication of devices with the desired performance and switching behavior. Here, by fabricating short channel (L ch  ~ 20 nm) devices with a thin, high-κ gate dielectric and a 9-atom wide (0.95 nm) armchair graphene nanoribbon as the channel material, we demonstrate field-effect transistors with high on-current (I on  > 1 μA at V d  = -1 V) and high I on /I off  ~ 10 5 at room temperature. We find that the performance of these devices is limited by tunneling through the Schottky barrier at the contacts and we observe an increase in the transparency of the barrier by increasing the gate field near the contacts. Our results thus demonstrate successful fabrication of high-performance short-channel field-effect transistors with bottom-up synthesized armchair graphene nanoribbons.Graphene nanoribbons show promise for high-performance field-effect transistors, however they often suffer from short lengths and wide band gaps. Here, the authors use a bottom-up synthesis approach to fabricate 9- and 13-atom wide ribbons, enabling short-channel transistors with 10 5 on-off current ratio.

Performance evaluation of parallel electric field tunnel field-effect transistor by a distributed-element circuit model

NASA Astrophysics Data System (ADS)

Morita, Yukinori; Mori, Takahiro; Migita, Shinji; Mizubayashi, Wataru; Tanabe, Akihito; Fukuda, Koichi; Matsukawa, Takashi; Endo, Kazuhiko; O'uchi, Shin-ichi; Liu, Yongxun; Masahara, Meishoku; Ota, Hiroyuki

2014-12-01

The performance of parallel electric field tunnel field-effect transistors (TFETs), in which band-to-band tunneling (BTBT) was initiated in-line to the gate electric field was evaluated. The TFET was fabricated by inserting an epitaxially-grown parallel-plate tunnel capacitor between heavily doped source wells and gate insulators. Analysis using a distributed-element circuit model indicated there should be a limit of the drain current caused by the self-voltage-drop effect in the ultrathin channel layer.

100-nm gate lithography for double-gate transistors

NASA Astrophysics Data System (ADS)

Krasnoperova, Azalia A.; Zhang, Ying; Babich, Inna V.; Treichler, John; Yoon, Jung H.; Guarini, Kathryn; Solomon, Paul M.

2001-09-01

The double gate field effect transistor (FET) is an exploratory device that promises certain performance advantages compared to traditional CMOS FETs. It can be scaled down further than the traditional devices because of the greater electrostatic control by the gates on the channel (about twice as short a channel length for the same gate oxide thickness), has steeper sub-threshold slope and about double the current for the same width. This paper presents lithographic results for double gate FET's developed at IBM's T. J. Watson Research Center. The device is built on bonded wafers with top and bottom gates self-aligned to each other. The channel is sandwiched between the top and bottom polysilicon gates and the gate length is defined using DUV lithography. An alternating phase shift mask was used to pattern gates with critical dimensions of 75 nm, 100 nm and 125 nm in photoresist. 50 nm gates in photoresist have also been patterned by 20% over-exposure of nominal 100 nm lines. No trim mask was needed because of a specific way the device was laid out. UV110 photoresist from Shipley on AR-3 antireflective layer were used. Process windows, developed and etched patterns are presented.

Strain and deformations engineered germanene bilayer double gate-field effect transistor by first principles

NASA Astrophysics Data System (ADS)

Meher Abhinav, E.; Chandrasekaran, Gopalakrishnan; Kasmir Raja, S. V.

2017-10-01

Germanene, silicene, stanene, phosphorene and graphene are some of single atomic materials with novel properties. In this paper, we explored bilayer germanene-based Double Gate-Field Effect Transistor (DG-FET) with various strains and deformations using Density Functional Theory (DFT) and Green's approach by first-principle calculations. The DG-FET of 1.6 nm width, 6 nm channel length (Lch) and HfO2 as gate dielectric has been modeled. For intrinsic deformation of germanene bilayer, we have enforced minute mechanical deformation of wrap and twist (5°) and ripple (0.5 Å) on germanene bilayer channel material. By using NEGF formalism, I-V Characteristics of various strains and deformation tailored DG-FET was calculated. Our results show that rough edge and single vacancy (5-9) in bilayer germanene diminishes the current around 47% and 58% respectively as compared with pristine bilayer germanene. In case of strain tailored bilayer DG-FET, multiple NDR regions were observed which can be utilized in building stable multiple logic states in digital circuits and high frequency oscillators using negative resistive techniques.

Superconductivity in two-dimensional NbSe2 field effect transistors

NASA Astrophysics Data System (ADS)

El-Bana, Mohammed S.; Wolverson, Daniel; Russo, Saverio; Balakrishnan, Geetha; Mck Paul, Don; Bending, Simon J.

2013-12-01

We describe investigations of superconductivity in few molecular layer NbSe2 field effect transistors. While devices fabricated from NbSe2 flakes less than eight molecular layers thick did not conduct, thicker flakes were superconducting with an onset Tc that was only slightly depressed from the bulk value for 2H-NbSe2 (7.2 K). The resistance typically showed a small, sharp high temperature transition followed by one or more broader transitions which usually ended in a wide tail to zero resistance at low temperatures. We speculate that these multiple resistive transitions are related to disorder in the layer stacking. The behavior of several flakes has been characterized as a function of temperature, applied field and back-gate voltage. We find that the conductance in the normal state and transition temperature depend weakly on the gate voltage, with both conductivity and Tc decreasing as the electron concentration is increased. The application of a perpendicular magnetic field allows the evolution of different resistive transitions to be tracked and values of the zero temperature upper critical field, Hc2(0), and coherence length, ξ(0), to be independently estimated. Our results are analyzed in terms of available theories for these phenomena.

Water-Gated n-Type Organic Field-Effect Transistors for Complementary Integrated Circuits Operating in an Aqueous Environment

PubMed Central

2017-01-01

The first demonstration of an n-type water-gated organic field-effect transistor (WGOFET) is here reported, along with simple water-gated complementary integrated circuits, in the form of inverting logic gates. For the n-type WGOFET active layer, high-electron-affinity organic semiconductors, including naphthalene diimide co-polymers and a soluble fullerene derivative, have been compared, with the latter enabling a high electric double layer capacitance in the range of 1 μF cm–2 in full accumulation and a mobility–capacitance product of 7 × 10–3 μF/V s. Short-term stability measurements indicate promising cycling robustness, despite operating the device in an environment typically considered harsh, especially for electron-transporting organic molecules. This work paves the way toward advanced circuitry design for signal conditioning and actuation in an aqueous environment and opens new perspectives in the implementation of active bio-organic interfaces for biosensing and neuromodulation. PMID:28180187

Improved Performance of h-BN Encapsulated Double Gate Graphene Nanomesh Field Effect Transistor for Short Channel Length

NASA Astrophysics Data System (ADS)

Tiwari, Durgesh Laxman; Sivasankaran, K.

This paper presents improved performance of Double Gate Graphene Nanomesh Field Effect Transistor (DG-GNMFET) with h-BN as substrate and gate oxide material. The DC characteristics of 0.95μm and 5nm channel length devices are studied for SiO2 and h-BN substrate and oxide material. For analyzing the ballistic behavior of electron for 5nm channel length, von Neumann boundary condition is considered near source and drain contact region. The simulated results show improved saturation current for h-BN encapsulated structure with two times higher on current value (0.375 for SiO2 and 0.621 for h-BN) as compared to SiO2 encapsulated structure. The obtained result shows h-BN to be a better substrate and oxide material for graphene electronics with improved device characteristics.

A Novel Metal-Ferroelectric-Semiconductor Field-Effect Transistor Memory Cell Design

NASA Technical Reports Server (NTRS)

Phillips, Thomas A.; Bailey, Mark; Ho, Fat Duen

2004-01-01

The use of a Metal-Ferroelectric-Semiconductor Field-Effect Transistor (MFSFET) in a resistive-load SRAM memory cell has been investigated A typical two-transistor resistive-load SRAM memory cell architecture is modified by replacing one of the NMOS transistors with an n-channel MFSFET. The gate of the MFSFET is connected to a polling voltage pulse instead of the other NMOS transistor drain. The polling voltage pulses are of sufficient magnitude to saturate the ferroelectric gate material and force the MFSFET into a particular logic state. The memory cell circuit is further modified by the addition of a PMOS transistor and a load resistor in order to improve the retention characteristics of the memory cell. The retention characteristics of both the "1" and "0" logic states are simulated. The simulations show that the MFSFET memory cell design can maintain both the "1" and "0" logic states for a long period of time.

Interface and gate bias dependence responses of sensing organic thin-film transistors.

PubMed

Tanese, Maria Cristina; Fine, Daniel; Dodabalapur, Ananth; Torsi, Luisa

2005-11-15

The effects of the exposure of organic thin-film transistors, comprising different organic semiconductors and gate dielectrics, to 1-pentanol are investigated. The transistor sensors exhibited an increase or a decrease of the transient source-drain current in the presence of the analyte, most likely as a result of a trapping or of a doping process of the organic active layer. The occurrence of these two effects, that can also coexist, depend on the gate-dielectric/organic semiconductor interface and on the applied gate field. Evidence of a systematic and sizable response enhancement for an OTFT sensor operated in the enhanced mode is also presented.

P-type field effect transistor based on Na-doped BaSnO3

NASA Astrophysics Data System (ADS)

Jang, Yeaju; Hong, Sungyun; Park, Jisung; Char, Kookrin

We fabricated field effect transistors (FET) based on the p-type Na-doped BaSnO3 (BNSO) channel layer. The properties of epitaxial BNSO channel layer were controlled by the doping rate. In order to modulate the p-type FET, we used amorphous HfOx and epitaxial BaHfO3 (BHO) gate oxides, both of which have high dielectric constants. HfOx was deposited by atomic-layer-deposition and BHO was epitaxially grown by pulsed laser deposition. The pulsed laser deposited SrRuO3 (SRO) was used as the source and the drain contacts. Indium-tin oxide and La-doped BaSnO3 were used as the gate electrodes on top of the HfOx and the BHO gate oxides, respectively. We will analyze and present the performances of the BNSO field effect transistor such as the IDS-VDS, the IDS-VGS, the Ion/Ioff ratio, and the field effect mobility. Samsung Science and Technology Foundation.

Probing organic field effect transistors in situ during operation using SFG.

PubMed

Ye, Hongke; Abu-Akeel, Ashraf; Huang, Jia; Katz, Howard E; Gracias, David H

2006-05-24

In this communication, we report results obtained using surface-sensitive IR+Visible Sum Frequency Generation (SFG) nonlinear optical spectroscopy on interfaces of organic field effect transistors during operation. We observe remarkable correlations between trends in the surface vibrational spectra and electrical properties of the transistor, with changes in gate voltage (VG). These results suggest that field effects on electronic conduction in thin film organic semiconductor devices are correlated to interfacial nonlinear optical characteristics and point to the possibility of using SFG spectroscopy to monitor electronic properties of OFETs.

A Single Polyaniline Nanofiber Field Effect Transistor and Its Gas Sensing Mechanisms

PubMed Central

Chen, Dajing; Lei, Sheng; Chen, Yuquan

2011-01-01

A single polyaniline nanofiber field effect transistor (FET) gas sensor fabricated by means of electrospinning was investigated to understand its sensing mechanisms and optimize its performance. We studied the morphology, field effect characteristics and gas sensitivity of conductive nanofibers. The fibers showed Schottky and Ohmic contacts based on different electrode materials. Higher applied gate voltage contributes to an increase in gas sensitivity. The nanofiber transistor showed a 7% reversible resistance change to 1 ppm NH3 with 10 V gate voltage. The FET characteristics of the sensor when exposed to different gas concentrations indicate that adsorption of NH3 molecules reduces the carrier mobility in the polyaniline nanofiber. As such, nanofiber-based sensors could be promising for environmental and industrial applications. PMID:22163969

Synthesis of bilayer MoS2 and corresponding field effect characteristics

NASA Astrophysics Data System (ADS)

Fang, Mingxu; Feng, Yulin; Wang, Fang; Yang, Zhengchun; Zhang, Kailiang

2017-06-01

Two-dimensional transition-metal dichalcogenides such as MoS2 are promising materials for next-generation nano-electronic devices. The physical properties of MoS2 are determined by layer number according to the variation of band-gap. Here, we synthesize large-size bilayer-MoS2 with triangle and hexagonal nanosheets in one step by chemical vapor deposition, Monolayer and bilayer-MoS2 back-gate field effect transistors are also fabricated and the performance including mobility and on/off ratios are compared. The bilayer-MoS2 back-gate field effect transistor shows superior performance with field effect mobility of ∼21.27cm2V-1s-1, and Ion/Ioff ratio of ∼3.9×107.

An Al₂O₃ Gating Substrate for the Greater Performance of Field Effect Transistors Based on Two-Dimensional Materials.

PubMed

Yang, Hang; Qin, Shiqiao; Zheng, Xiaoming; Wang, Guang; Tan, Yuan; Peng, Gang; Zhang, Xueao

2017-09-22

We fabricated 70 nm Al₂O₃ gated field effect transistors based on two-dimensional (2D) materials and characterized their optical and electrical properties. Studies show that the optical contrast of monolayer graphene on an Al₂O₃/Si substrate is superior to that on a traditional 300 nm SiO₂/Si substrate (2.4 times). Significantly, the transconductance of monolayer graphene transistors on the Al₂O₃/Si substrate shows an approximately 10-fold increase, due to a smaller dielectric thickness and a higher dielectric constant. Furthermore, this substrate is also suitable for other 2D materials, such as WS₂, and can enhance the transconductance remarkably by 61.3 times. These results demonstrate a new and ideal substrate for the fabrication of 2D materials-based electronic logic devices.

High sensitivity measurement system for the direct-current, capacitance-voltage, and gate-drain low frequency noise characterization of field effect transistors.

PubMed

Giusi, G; Giordano, O; Scandurra, G; Rapisarda, M; Calvi, S; Ciofi, C

2016-04-01

Measurements of current fluctuations originating in electron devices have been largely used to understand the electrical properties of materials and ultimate device performances. In this work, we propose a high-sensitivity measurement setup topology suitable for the automatic and programmable Direct-Current (DC), Capacitance-Voltage (CV), and gate-drain low frequency noise characterization of field effect transistors at wafer level. Automatic and programmable operation is particularly useful when the device characteristics relax or degrade with time due to optical, bias, or temperature stress. The noise sensitivity of the proposed topology is in the order of fA/Hz(1/2), while DC performances are limited only by the source and measurement units used to bias the device under test. DC, CV, and NOISE measurements, down to 1 pA of DC gate and drain bias currents, in organic thin film transistors are reported to demonstrate system operation and performances.

High Sensitivity pH Sensor Based on Porous Silicon (PSi) Extended Gate Field-Effect Transistor

PubMed Central

Al-Hardan, Naif H.; Abdul Hamid, Muhammad Azmi; Ahmed, Naser M.; Jalar, Azman; Shamsudin, Roslinda; Othman, Norinsan Kamil; Kar Keng, Lim; Chiu, Weesiong; Al-Rawi, Hamzah N.

2016-01-01

In this study, porous silicon (PSi) was prepared and tested as an extended gate field-effect transistor (EGFET) for pH sensing. The prepared PSi has pore sizes in the range of 500 to 750 nm with a depth of approximately 42 µm. The results of testing PSi for hydrogen ion sensing in different pH buffer solutions reveal that the PSi has a sensitivity value of 66 mV/pH that is considered a super Nernstian value. The sensor considers stability to be in the pH range of 2 to 12. The hysteresis values of the prepared PSi sensor were approximately 8.2 and 10.5 mV in the low and high pH loop, respectively. The result of this study reveals a promising application of PSi in the field for detecting hydrogen ions in different solutions. PMID:27338381

High Sensitivity pH Sensor Based on Porous Silicon (PSi) Extended Gate Field-Effect Transistor.

PubMed

Al-Hardan, Naif H; Abdul Hamid, Muhammad Azmi; Ahmed, Naser M; Jalar, Azman; Shamsudin, Roslinda; Othman, Norinsan Kamil; Kar Keng, Lim; Chiu, Weesiong; Al-Rawi, Hamzah N

2016-06-07

In this study, porous silicon (PSi) was prepared and tested as an extended gate field-effect transistor (EGFET) for pH sensing. The prepared PSi has pore sizes in the range of 500 to 750 nm with a depth of approximately 42 µm. The results of testing PSi for hydrogen ion sensing in different pH buffer solutions reveal that the PSi has a sensitivity value of 66 mV/pH that is considered a super Nernstian value. The sensor considers stability to be in the pH range of 2 to 12. The hysteresis values of the prepared PSi sensor were approximately 8.2 and 10.5 mV in the low and high pH loop, respectively. The result of this study reveals a promising application of PSi in the field for detecting hydrogen ions in different solutions.

Nano-textured high sensitivity ion sensitive field effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hajmirzaheydarali, M.; Sadeghipari, M.; Akbari, M.

2016-02-07

Nano-textured gate engineered ion sensitive field effect transistors (ISFETs), suitable for high sensitivity pH sensors, have been realized. Utilizing a mask-less deep reactive ion etching results in ultra-fine poly-Si features on the gate of ISFET devices where spacing of the order of 10 nm and less is achieved. Incorporation of these nano-sized features on the gate is responsible for high sensitivities up to 400 mV/pH in contrast to conventional planar structures. The fabrication process for this transistor is inexpensive, and it is fully compatible with standard complementary metal oxide semiconductor fabrication procedure. A theoretical modeling has also been presented to predict themore » extension of the diffuse layer into the electrolyte solution for highly featured structures and to correlate this extension with the high sensitivity of the device. The observed ultra-fine features by means of scanning electron microscopy and transmission electron microscopy tools corroborate the theoretical prediction.« less

Simulation study of short-channel effects of tunnel field-effect transistors

NASA Astrophysics Data System (ADS)

Fukuda, Koichi; Asai, Hidehiro; Hattori, Junichi; Mori, Takahiro; Morita, Yukinori; Mizubayashi, Wataru; Masahara, Meishoku; Migita, Shinji; Ota, Hiroyuki; Endo, Kazuhiro; Matsukawa, Takashi

2018-04-01

Short-channel effects of tunnel field-effect transistors (FETs) are investigated in detail using simulations of a nonlocal band-to-band tunneling model. Discussion is limited to silicon. Several simulation scenarios were considered to address different effects, such as source overlap and drain offset effects. Adopting the drain offset to suppress the drain leakage current suppressed the short channel effects. The physical mechanism underlying the short-channel behavior of the tunnel FETs (TFETs) was very different from that of metal-oxide-semiconductor FETs (MOSFETs). The minimal gate lengths that do not lose on-state current by one order are shown to be 3 nm for single-gate structures and 2 nm for double gate structures, as determined from the drain offset structure.

High-mobility solution-processed copper phthalocyanine-based organic field-effect transistors.

PubMed

Chaure, Nandu B; Cammidge, Andrew N; Chambrier, Isabelle; Cook, Michael J; Cain, Markys G; Murphy, Craig E; Pal, Chandana; Ray, Asim K

2011-04-01

Solution-processed films of 1,4,8,11,15,18,22,25-octakis(hexyl) copper phthalocyanine (CuPc 6 ) were utilized as an active semiconducting layer in the fabrication of organic field-effect transistors (OFETs) in the bottom-gate configurations using chemical vapour deposited silicon dioxide (SiO 2 ) as gate dielectrics. The surface treatment of the gate dielectric with a self-assembled monolayer of octadecyltrichlorosilane (OTS) resulted in values of 4×10 -2 cm 2 V -1 s -1 and 10 6 for saturation mobility and on/off current ratio, respectively. This improvement was accompanied by a shift in the threshold voltage from 3 V for untreated devices to -2 V for OTS treated devices. The trap density at the interface between the gate dielectric and semiconductor decreased by about one order of magnitude after the surface treatment. The transistors with the OTS treated gate dielectrics were more stable over a 30-day period in air than untreated ones.

High-mobility solution-processed copper phthalocyanine-based organic field-effect transistors

PubMed Central

Chaure, Nandu B; Cammidge, Andrew N; Chambrier, Isabelle; Cook, Michael J; Cain, Markys G; Murphy, Craig E; Pal, Chandana; Ray, Asim K

2011-01-01

Solution-processed films of 1,4,8,11,15,18,22,25-octakis(hexyl) copper phthalocyanine (CuPc6) were utilized as an active semiconducting layer in the fabrication of organic field-effect transistors (OFETs) in the bottom-gate configurations using chemical vapour deposited silicon dioxide (SiO2) as gate dielectrics. The surface treatment of the gate dielectric with a self-assembled monolayer of octadecyltrichlorosilane (OTS) resulted in values of 4×10−2 cm2 V−1 s−1 and 106 for saturation mobility and on/off current ratio, respectively. This improvement was accompanied by a shift in the threshold voltage from 3 V for untreated devices to -2 V for OTS treated devices. The trap density at the interface between the gate dielectric and semiconductor decreased by about one order of magnitude after the surface treatment. The transistors with the OTS treated gate dielectrics were more stable over a 30-day period in air than untreated ones. PMID:27877383

Benzocyclobutene (BCB) Polymer as Amphibious Buffer Layer for Graphene Field-Effect Transistor.

PubMed

Wu, Yun; Zou, Jianjun; Huo, Shuai; Lu, Haiyan; Kong, Yuecan; Chen, Tangshen; Wu, Wei; Xu, Jingxia

2015-08-01

Owing to the scattering and trapping effects, the interfaces of dielectric/graphene or substrate/graphene can tailor the performance of field-effect transistor (FET). In this letter, the polymer of benzocyclobutene (BCB) was used as an amphibious buffer layer and located at between the layers of substrate and graphene and between the layers of dielectric and graphene. Interestingly, with the help of nonpolar and hydrophobic BCB buffer layer, the large-scale top-gated, chemical vapor deposited (CVD) graphene transistors was prepared on Si/SiO2 substrate, its cutoff frequency (fT) and the maximum cutoff frequency (fmax) of the graphene field-effect transistor (GFET) can be reached at 12 GHz and 11 GHz, respectively.

Performance and Design Considerations of a Novel Dual-Material Gate Carbon Nanotube Field-Effect Transistors: Nonequilibrium Green's Function Approach

NASA Astrophysics Data System (ADS)

Arefinia, Zahra; Orouji, Ali A.

2009-02-01

The concept of dual-material gate (DMG) is applied to the carbon nanotube field-effect transistor (CNTFET) with doped source and drain extensions, and the features exhibited by the resulting new structure, i.e., the DMG-CNTFET structure, have been examined for the first time by developing a two-dimensional (2D) full quantum simulation. The simulations have been done by the self-consistent solution of 2D Poisson-Schrödinger equations, within the nonequilibrium Green's function (NEGF) formalism. The results show DMG-CNTFET decreases significantly leakage current and drain conductance and increases on-off current ratio and voltage gain as compared to the single material gate counterparts CNTFET. It is seen that short channel effects in this structure are suppressed because of the perceivable step in the surface potential profile, which screens the drain potential. Moreover, these unique features can be controlled by engineering the workfunction and length of the gate metals. Therefore, this work provides an incentive for further experimental exploration.

Environmental Effects on Hysteresis of Transfer Characteristics in Molybdenum Disulfide Field-Effect Transistors

NASA Astrophysics Data System (ADS)

Shimazu, Yoshihiro; Tashiro, Mitsuki; Sonobe, Satoshi; Takahashi, Masaki

2016-07-01

Molybdenum disulfide (MoS2) has recently received much attention for nanoscale electronic and photonic applications. To explore the intrinsic properties and enhance the performance of MoS2-based field-effect transistors, thorough understanding of extrinsic effects such as environmental gas and contact resistance of the electrodes is required. Here, we report the effects of environmental gases on the transport properties of back-gated multilayered MoS2 field-effect transistors. Comparisons between different gases (oxygen, nitrogen, and air and nitrogen with varying relative humidities) revealed that water molecules acting as charge-trapping centers are the main cause of hysteresis in the transfer characteristics. While the hysteresis persisted even after pumping out the environmental gas for longer than 10 h at room temperature, it disappeared when the device was cooled to 240 K, suggesting a considerable increase in the time constant of the charge trapping/detrapping at these modestly low temperatures. The suppression of the hysteresis or instability in the easily attainable temperature range without surface passivation is highly advantageous for the device application of this system. The humidity dependence of the threshold voltages in the transfer curves indicates that the water molecules dominantly act as hole-trapping centers. A strong dependence of the on-state current on oxygen pressure was also observed.

Piezoelectric potential gated field-effect transistor based on a free-standing ZnO wire.

PubMed

Fei, Peng; Yeh, Ping-Hung; Zhou, Jun; Xu, Sheng; Gao, Yifan; Song, Jinhui; Gu, Yudong; Huang, Yanyi; Wang, Zhong Lin

2009-10-01

We report an external force triggered field-effect transistor based on a free-standing piezoelectric fine wire (PFW). The device consists of an Ag source electrode and an Au drain electrode at two ends of a ZnO PFW, which were separated by an insulating polydimethylsiloxane (PDMS) thin layer. The working principle of the sensor is proposed based on the piezoelectric potential gating effect. Once subjected to a mechanical impact, the bent ZnO PFW cantilever creates a piezoelectric potential distribution across it width at its root and simultaneously produces a local reverse depletion layer with much higher donor concentration than normal, which can dramatically change the current flowing from the source electrode to drain electrode when the device is under a fixed voltage bias. Due to the free-standing structure of the sensor device, it has a prompt response time less than 20 ms and quite high and stable sensitivity of 2%/microN. The effect from contact resistance has been ruled out.

Noise and current-voltage characterization of complementary heterojunction field-effect transistor (CHFET) structures below 8 K

NASA Technical Reports Server (NTRS)

Cunningham, Thomas J.; Fossum, Eric R.; Baier, Steven M.

1992-01-01

Noise and current-voltage characterization of complementary heterojunction field-effect transistor (CHFET) structures below 8 K are presented. It is shown that the CHFET exhibits normal transistor operation down to 6 K. Some of the details of the transistor operation, such as the gate-voltage dependence of the channel potential, are analyzed. The gate current is examined and is shown to be due to several mechanisms acting in parallel. These include field-emission and thermionic-field-emission, conduction through a temperature-activated resistance, and thermionic emission. The input referred noise for n-channel CHFETs is presented and discussed. The noise has the spectral dependence of 1/f noise, but does not exhibit the usual area dependence.

High sensitivity measurement system for the direct-current, capacitance-voltage, and gate-drain low frequency noise characterization of field effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Giusi, G.; Giordano, O.; Scandurra, G.

Measurements of current fluctuations originating in electron devices have been largely used to understand the electrical properties of materials and ultimate device performances. In this work, we propose a high-sensitivity measurement setup topology suitable for the automatic and programmable Direct-Current (DC), Capacitance-Voltage (CV), and gate-drain low frequency noise characterization of field effect transistors at wafer level. Automatic and programmable operation is particularly useful when the device characteristics relax or degrade with time due to optical, bias, or temperature stress. The noise sensitivity of the proposed topology is in the order of fA/Hz{sup 1/2}, while DC performances are limited only bymore » the source and measurement units used to bias the device under test. DC, CV, and NOISE measurements, down to 1 pA of DC gate and drain bias currents, in organic thin film transistors are reported to demonstrate system operation and performances.« less

Hysteresis free negative total gate capacitance in junctionless transistors

NASA Astrophysics Data System (ADS)

Gupta, Manish; Kranti, Abhinav

2017-09-01

In this work, we report on the hysteresis free impact ionization induced off-to-on transition while preserving sub-60 mV/decade Subthreshold swing (S-swing) using asymmetric mode operation in double gate silicon (Si) and germanium (Ge) junctionless (JL) transistor. It is shown that sub-60 mV/decade steep switching due to impact ionization implies a negative value of the total gate capacitance. The performance of asymmetric gate JL transistor is compared with symmetric gate operation of JL device, and the condition for hysteresis free current transition with a sub-60 mV/decade switching is analyzed through the product of current density (J) and electric field (E). It is shown that asymmetric gate operation limits the degree of impact ionization inherent in the semiconductor film to levels sufficient for negative total gate capacitance but lower than that required for the occurrence of hysteresis. The work highlights new viewpoints related to the suppression of hysteresis associated with steep switching JL transistors while maintaining S-swing within the range 6-15 mV/decade leading to the negative value of total gate capacitance.

An All-Solid-State pH Sensor Employing Fluorine-Terminated Polycrystalline Boron-Doped Diamond as a pH-Insensitive Solution-Gate Field-Effect Transistor.

PubMed

Shintani, Yukihiro; Kobayashi, Mikinori; Kawarada, Hiroshi

2017-05-05

A fluorine-terminated polycrystalline boron-doped diamond surface is successfully employed as a pH-insensitive SGFET (solution-gate field-effect transistor) for an all-solid-state pH sensor. The fluorinated polycrystalline boron-doped diamond (BDD) channel possesses a pH-insensitivity of less than 3mV/pH compared with a pH-sensitive oxygenated channel. With differential FET (field-effect transistor) sensing, a sensitivity of 27 mv/pH was obtained in the pH range of 2-10; therefore, it demonstrated excellent performance for an all-solid-state pH sensor with a pH-sensitive oxygen-terminated polycrystalline BDD SGFET and a platinum quasi-reference electrode, respectively.

High on/off ratios in bilayer graphene field effect transistors realized by surface dopants.

PubMed

Szafranek, B N; Schall, D; Otto, M; Neumaier, D; Kurz, H

2011-07-13

The unique property of bilayer graphene to show a band gap tunable by external electrical fields enables a variety of different device concepts with novel functionalities for electronic, optoelectronic, and sensor applications. So far the operation of bilayer graphene-based field effect transistors requires two individual gates to vary the channel's conductance and to create a band gap. In this paper, we report on a method to increase the on/off ratio in single gated bilayer graphene field effect transistors by adsorbate doping. The adsorbate dopants on the upper side of the graphene establish a displacement field perpendicular to the graphene surface breaking the inversion symmetry of the two graphene layers. Low-temperature measurements indicate that the increased on/off ratio is caused by the opening of a mobility gap.

Electrical characteristics of silicon percolating nanonet-based field effect transistors in the presence of dispersion

NASA Astrophysics Data System (ADS)

Cazimajou, T.; Legallais, M.; Mouis, M.; Ternon, C.; Salem, B.; Ghibaudo, G.

2018-05-01

We studied the current-voltage characteristics of percolating networks of silicon nanowires (nanonets), operated in back-gated transistor mode, for future use as gas or biosensors. These devices featured P-type field-effect characteristics. It was found that a Lambert W function-based compact model could be used for parameter extraction of electrical parameters such as apparent low field mobility, threshold voltage and subthreshold slope ideality factor. Their variation with channel length and nanowire density was related to the change of conduction regime from direct source/drain connection by parallel nanowires to percolating channels. Experimental results could be related in part to an influence of the threshold voltage dispersion of individual nanowires.

Low Temperature Noise and Electrical Characterization of the Company Heterojunction Field-Effect Transistor

NASA Technical Reports Server (NTRS)

Cunningham, Thomas J.; Gee, Russell C.; Fossum, Eric R.; Baier, Steven M.

1993-01-01

This paper discusses the electrical properties of the complementary heterojunction field-effect transistor (CHFET) at 4K, including the gate leakage current, the subthreshold transconductance, and the input-referred noise voltage.

Camel Gate Field Effect Transistors.

DTIC Science & Technology

1983-01-01

CAMFETs can be designed to yield relatively voltage independent transconductances, large for- * ward turn-on voltages, and large gate-drain breakdown...doping. The FATFET area is 4.6 x 10- 4 cm2. I.- . - . . - , - 36 80 * Camel Gate U_-- Eperimental 60 * -Theoretical % Schottky Gate ~--Experimental CL 4...in the design of other devices. Finally, a comparative study of the reliabil- ities of CAMFETs, JFETs, and MESFETs should be attempted. 43 VII

Flexible, Low-Cost Sensor Based on Electrolyte Gated Carbon Nanotube Field Effect Transistor for Organo-Phosphate Detection

PubMed Central

Bhatt, Vijay Deep; Joshi, Saumya; Becherer, Markus; Lugli, Paolo

2017-01-01

A flexible enzymatic acetylcholinesterase biosensor based on an electrolyte-gated carbon nanotube field effect transistor is demonstrated. The enzyme immobilization is done on a planar gold gate electrode using 3-mercapto propionic acid as the linker molecule. The sensor showed good sensing capability as a sensor for the neurotransmitter acetylcholine, with a sensitivity of 5.7 μA/decade, and demonstrated excellent specificity when tested against interfering analytes present in the body. As the flexible sensor is supposed to suffer mechanical deformations, the endurance of the sensor was measured by putting it under extensive mechanical stress. The enzymatic activity was inhibited by more than 70% when the phosphate-buffered saline (PBS) buffer was spiked with 5 mg/mL malathion (an organophosphate) solution. The biosensor was successfully challenged with tap water and strawberry juice, demonstrating its usefulness as an analytical tool for organophosphate detection. PMID:28524071

Low-power bacteriorhodopsin-silicon n-channel metal-oxide field-effect transistor photoreceiver.

PubMed

Shin, Jonghyun; Bhattacharya, Pallab; Yuan, Hao-Chih; Ma, Zhenqiang; Váró, György

2007-03-01

A bacteriorhodopsin (bR)-silicon n-channel metal-oxide field-effect transistor (NMOSFET) monolithically integrated photoreceiver is demonstrated. The bR film is selectively formed on an external gate electrode of the transistor by electrophoretic deposition. A modified biasing circuit is incorporated, which helps to match the resistance of the bR film to the input impedance of the NMOSFET and to shift the operating point of the transistor to coincide with the maximum gain. The photoreceiver exhibits a responsivity of 4.7 mA/W.

Temperature-dependent degradation mechanisms of threshold voltage in La2O3-gated n-channel metal-oxide-semiconductor field-effect transistors

NASA Astrophysics Data System (ADS)

Wang, Ming-Tsong; Hsu, De-Cheng; Juan, Pi-Chun; Wang, Y. L.; Lee, Joseph Ya-min

2010-09-01

Metal-oxide-semiconductor capacitors and n-channel metal-oxide-semiconductor field-effect transistors with La2O3 gate dielectric were fabricated. The positive bias temperature instability was studied. The degradation of threshold voltage (ΔVT) showed an exponential dependence on the stress time in the temperature range from 25 to 75 °C. The degradation of subthreshold slope (ΔS) and gate leakage (IG) with stress voltage was also measured. The degradation of VT is attributed to the oxide trap charges Qot. The extracted activation energy of 0.2 eV is related to a degradation dominated by the release of atomic hydrogen in La2O3 thin films.

Feasibility Study of Extended-Gate-Type Silicon Nanowire Field-Effect Transistors for Neural Recording

PubMed Central

Kang, Hongki; Kim, Jee-Yeon; Choi, Yang-Kyu; Nam, Yoonkey

2017-01-01

In this research, a high performance silicon nanowire field-effect transistor (transconductance as high as 34 µS and sensitivity as 84 nS/mV) is extensively studied and directly compared with planar passive microelectrode arrays for neural recording application. Electrical and electrochemical characteristics are carefully characterized in a very well-controlled manner. We especially focused on the signal amplification capability and intrinsic noise of the transistors. A neural recording system using both silicon nanowire field-effect transistor-based active-type microelectrode array and platinum black microelectrode-based passive-type microelectrode array are implemented and compared. An artificial neural spike signal is supplied as input to both arrays through a buffer solution and recorded simultaneously. Recorded signal intensity by the silicon nanowire transistor was precisely determined by an electrical characteristic of the transistor, transconductance. Signal-to-noise ratio was found to be strongly dependent upon the intrinsic 1/f noise of the silicon nanowire transistor. We found how signal strength is determined and how intrinsic noise of the transistor determines signal-to-noise ratio of the recorded neural signals. This study provides in-depth understanding of the overall neural recording mechanism using silicon nanowire transistors and solid design guideline for further improvement and development. PMID:28350370

Feasibility Study of Extended-Gate-Type Silicon Nanowire Field-Effect Transistors for Neural Recording.

PubMed

Kang, Hongki; Kim, Jee-Yeon; Choi, Yang-Kyu; Nam, Yoonkey

2017-03-28

In this research, a high performance silicon nanowire field-effect transistor (transconductance as high as 34 µS and sensitivity as 84 nS/mV) is extensively studied and directly compared with planar passive microelectrode arrays for neural recording application. Electrical and electrochemical characteristics are carefully characterized in a very well-controlled manner. We especially focused on the signal amplification capability and intrinsic noise of the transistors. A neural recording system using both silicon nanowire field-effect transistor-based active-type microelectrode array and platinum black microelectrode-based passive-type microelectrode array are implemented and compared. An artificial neural spike signal is supplied as input to both arrays through a buffer solution and recorded simultaneously. Recorded signal intensity by the silicon nanowire transistor was precisely determined by an electrical characteristic of the transistor, transconductance. Signal-to-noise ratio was found to be strongly dependent upon the intrinsic 1/f noise of the silicon nanowire transistor. We found how signal strength is determined and how intrinsic noise of the transistor determines signal-to-noise ratio of the recorded neural signals. This study provides in-depth understanding of the overall neural recording mechanism using silicon nanowire transistors and solid design guideline for further improvement and development.

Bio-fabrication of nanomesh channels of single-walled carbon nanotubes for locally gated field-effect transistors

NASA Astrophysics Data System (ADS)

Byeon, Hye-Hyeon; Lee, Woo Chul; Kim, Wonbin; Kim, Seong Keun; Kim, Woong; Yi, Hyunjung

2017-01-01

Single-walled carbon nanotubes (SWNTs) are one of the promising electronic components for nanoscale electronic devices such as field-effect transistors (FETs) owing to their excellent device characteristics such as high conductivity, high carrier mobility and mechanical flexibility. Localized gating gemometry of FETs enables individual addressing of active channels and allows for better electrostatics via thinner dielectric layer of high k-value. For localized gating of SWNTs, it becomes critical to define SWNTs of controlled nanostructures and functionality onto desired locations in high precision. Here, we demonstrate that a biologically templated approach in combination of microfabrication processes can successfully produce a nanostructured channels of SWNTs for localized active devices such as local bottom-gated FETs. A large-scale nanostructured network, nanomesh, of SWNTs were assembled in solution using an M13 phage with strong binding affinity toward SWNTs and micrometer-scale nanomesh channels were defined using negative photolithography and plasma-etching processes. The bio-fabrication approach produced local bottom-gated FETs with remarkably controllable nanostructures and successfully enabled semiconducting behavior out of unsorted SWNTs. In addition, the localized gating scheme enhanced the device performances such as operation voltage and I on/I off ratio. We believe that our approach provides a useful and integrative method for fabricating electronic devices out of nanoscale electronic materials for applications in which tunable electrical properties, mechanical flexibility, ambient stability, and chemical stability are of crucial importance.

Ultrahigh near infrared photoresponsive organic field-effect transistors with lead phthalocyanine/C60 heterojunction on poly(vinyl alcohol) gate dielectric.

PubMed

Sun, Lei; Zhang, Jianping; Zhao, Feiyu; Luo, Xiao; Lv, Wenli; li, Yao; Ren, Qiang; Wen, Zhanwei; Peng, Yingquan; Liu, Xingyuan

2015-05-08

Performances of photoresponsive organic field-effect transistors (photOFETs) operating in the near infrared (NIR) region utilizing SiO2 as the gate dielectric is generally low due to low carrier mobility of the channel. We report on NIR photOFETs based on lead phthalocyanine (PbPc)/C60 heterojunction with ultrahigh photoresponsivity by utilizing poly(vinyl alcohol) (PVA) as the gate dielectric. For 808 nm NIR illumination of 1.69 mW cm(-2), an ultrahigh photoresponsivity of 21 A W(-1), and an external quantum efficiency of 3230% were obtained at a gate voltage of 30 V and a drain voltage of 80 V, which are 124 times and 126 times as large as the reference device with SiO2 as the gate dielectric, respectively. The ultrahigh enhancement of photoresponsivity is resulted from the huge increase of electron mobility of C60 film grown on PVA dielectric. AFM investigations revealed that the C60 film grown on PVA is much smooth and uniform and the grain size is much larger than that grown on SiO2 dielectric, which together results in four orders of magnitude increase of the field-effect electron mobility of C60 film.

SiC Optically Modulated Field-Effect Transistor

NASA Technical Reports Server (NTRS)

Tabib-Azar, Massood

2009-01-01

An optically modulated field-effect transistor (OFET) based on a silicon carbide junction field-effect transistor (JFET) is under study as, potentially, a prototype of devices that could be useful for detecting ultraviolet light. The SiC OFET is an experimental device that is one of several devices, including commercial and experimental photodiodes, that were initially evaluated as detectors of ultraviolet light from combustion and that could be incorporated into SiC integrated circuits to be designed to function as combustion sensors. The ultraviolet-detection sensitivity of the photodiodes was found to be less than desired, such that it would be necessary to process their outputs using high-gain amplification circuitry. On the other hand, in principle, the function of the OFET could be characterized as a combination of detection and amplification. In effect, its sensitivity could be considerably greater than that of a photodiode, such that the need for amplification external to the photodetector could be reduced or eliminated. The experimental SiC OFET was made by processes similar to JFET-fabrication processes developed at Glenn Research Center. The gate of the OFET is very long, wide, and thin, relative to the gates of typical prior SiC JFETs. Unlike in prior SiC FETs, the gate is almost completely transparent to near-ultraviolet and visible light. More specifically: The OFET includes a p+ gate layer less than 1/4 m thick, through which photons can be transported efficiently to the p+/p body interface. The gate is relatively long and wide (about 0.5 by 0.5 mm), such that holes generated at the body interface form a depletion layer that modulates the conductivity of the channel between the drain and the source. The exact physical mechanism of modulation of conductivity is a subject of continuing research. It is known that injection of minority charge carriers (in this case, holes) at the interface exerts a strong effect on the channel, resulting in amplification

Vacuum lamination approach to fabrication of high-performance single-crystal organic field-effect transistors.

PubMed

Yi, H T; Chen, Y; Czelen, K; Podzorov, V

2011-12-22

A novel vacuum lamination approach to fabrication of high-performance single-crystal organic field-effect transistors has been developed. The non-destructive nature of this method allows a direct comparison of field-effect mobilities achieved with various gate dielectrics using the same single-crystal sample. The method also allows gating delicate systems, such as n -type crystals and SAM-coated surfaces, without perturbation. Copyright © 2011 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Silicon nanowire biologically sensitive field effect transistors: electrical characteristics and applications.

PubMed

Rim, Taiuk; Baek, Chang-Ki; Kim, Kihyun; Jeong, Yoon-Ha; Lee, Jeong-Soo; Meyyappan, M

2014-01-01

The interest in biologically sensitive field effect transistors (BioFETs) is growing explosively due to their potential as biosensors in biomedical, environmental monitoring and security applications. Recently, adoption of silicon nanowires in BioFETs has enabled enhancement of sensitivity, device miniaturization, decreasing power consumption and emerging applications such as the 3D cell probe. In this review, we describe the device physics and operation of the silicon nanowire BioFETs along with recent advances in the field. The silicon nanowire BioFETs are basically the same as the conventional field-effect transistors (FETs) with the exceptions of nanowire channel instead of thin film and a liquid gate instead of the conventional gate. Therefore, the silicon device physics is important to understand the operation of the BioFETs. Herein, physical characteristics of the silicon nanowire FETs are described and the operational principles of the BioFETs are classified according to the number of gates and the analysis domain of the measured signal. Even the bottom-up process has merits on low-cost fabrication; the top-down process technique is highlighted here due to its reliability and reproducibility. Finally, recent advances in the silicon nanowire BioFETs in the literature are described and key features for commercialization are discussed.

A novel gate and drain engineered charge plasma tunnel field-effect transistor for low sub-threshold swing and ambipolar nature

NASA Astrophysics Data System (ADS)

Yadav, Dharmendra Singh; Raad, Bhagwan Ram; Sharma, Dheeraj

2016-12-01

In this paper, we focus on the improvement of figures of merit for charge plasma based tunnel field-effect transistor (TFET) in terms of ON-state current, threshold voltage, sub-threshold swing, ambipolar nature, and gate to drain capacitance which provides better channel controlling of the device with improved high frequency response at ultra-low supply voltages. Regarding this, we simultaneously employ work function engineering on the drain and gate electrode of the charge plasma TFET. The use of gate work function engineering modulates the barrier on the source/channel interface leads to improvement in the ON-state current, threshold voltage, and sub-threshold swing. Apart from this, for the first time use of work function engineering on the drain electrode increases the tunneling barrier for the flow of holes on the drain/channel interface, it results into suppression of ambipolar behavior. The lowering of gate to drain capacitance therefore enhanced high frequency parameters. Whereas, the presence of dual work functionality at the gate electrode and over the drain region improves the overall performance of the charge plasma based TFET.

Reconfigurable Complementary Monolayer MoTe2 Field-Effect Transistors for Integrated Circuits.

PubMed

Larentis, Stefano; Fallahazad, Babak; Movva, Hema C P; Kim, Kyounghwan; Rai, Amritesh; Taniguchi, Takashi; Watanabe, Kenji; Banerjee, Sanjay K; Tutuc, Emanuel

2017-05-23

Transition metal dichalcogenides are of interest for next generation switches, but the lack of low resistance electron and hole contacts in the same material has hindered the development of complementary field-effect transistors and circuits. We demonstrate an air-stable, reconfigurable, complementary monolayer MoTe 2 field-effect transistor encapsulated in hexagonal boron nitride, using electrostatically doped contacts. The introduction of a multigate design with prepatterned bottom contacts allows us to independently achieve low contact resistance and threshold voltage tuning, while also decoupling the Schottky contacts and channel gating. We illustrate a complementary inverter and a p-i-n diode as potential applications.

Quasi-Two-Dimensional h-BN/β-Ga2O3 Heterostructure Metal-Insulator-Semiconductor Field-Effect Transistor.

PubMed

Kim, Janghyuk; Mastro, Michael A; Tadjer, Marko J; Kim, Jihyun

2017-06-28

β-gallium oxide (β-Ga 2 O 3 ) and hexagonal boron nitride (h-BN) heterostructure-based quasi-two-dimensional metal-insulator-semiconductor field-effect transistors (MISFETs) were demonstrated by integrating mechanical exfoliation of (quasi)-two-dimensional materials with a dry transfer process, wherein nanothin flakes of β-Ga 2 O 3 and h-BN were utilized as the channel and gate dielectric, respectively, of the MISFET. The h-BN dielectric, which has an extraordinarily flat and clean surface, provides a minimal density of charged impurities on the interface between β-Ga 2 O 3 and h-BN, resulting in superior device performances (maximum transconductance, on/off ratio, subthreshold swing, and threshold voltage) compared to those of the conventional back-gated configurations. Also, double-gating of the fabricated device was demonstrated by biasing both top and bottom gates, achieving the modulation of the threshold voltage. This heterostructured wide-band-gap nanodevice shows a new route toward stable and high-power nanoelectronic devices.

Contact Resistance and Channel Conductance of Graphene Field-Effect Transistors under Low-Energy Electron Irradiation

PubMed Central

Giubileo, Filippo; Di Bartolomeo, Antonio; Martucciello, Nadia; Romeo, Francesco; Iemmo, Laura; Romano, Paola; Passacantando, Maurizio

2016-01-01

We studied the effects of low-energy electron beam irradiation up to 10 keV on graphene-based field effect transistors. We fabricated metallic bilayer electrodes to contact mono- and bi-layer graphene flakes on SiO2, obtaining specific contact resistivity ρc≈19 kΩ·µm2 and carrier mobility as high as 4000 cm2·V−1·s−1. By using a highly doped p-Si/SiO2 substrate as the back gate, we analyzed the transport properties of the device and the dependence on the pressure and on the electron bombardment. We demonstrate herein that low energy irradiation is detrimental to the transistor current capability, resulting in an increase in contact resistance and a reduction in carrier mobility, even at electron doses as low as 30 e−/nm2. We also show that irradiated devices recover their pristine state after few repeated electrical measurements. PMID:28335335

The four-gate transistor

NASA Technical Reports Server (NTRS)

Mojarradi, M. M.; Cristoveanu, S.; Allibert, F.; France, G.; Blalock, B.; Durfrene, B.

2002-01-01

The four-gate transistor or G4-FET combines MOSFET and JFET principles in a single SOI device. Experimental results reveal that each gate can modulate the drain current. Numerical simulations are presented to clarify the mechanisms of operation. The new device shows enhanced functionality, due to the combinatorial action of the four gates, and opens rather revolutionary applications.

Electron transporting water-gated thin film transistors

NASA Astrophysics Data System (ADS)

Al Naim, Abdullah; Grell, Martin

2012-10-01

We demonstrate an electron-transporting water-gated thin film transistor, using thermally converted precursor-route zinc-oxide (ZnO) intrinsic semiconductors with hexamethyldisilazene (HMDS) hydrophobic surface modification. Water gated HMDS-ZnO thin film transistors (TFT) display low threshold and high electron mobility. ZnO films constitute an attractive alternative to organic semiconductors for TFT transducers in sensor applications for waterborne analytes. Despite the use of an electrolyte as gate medium, the gate geometry (shape of gate electrode and distance between gate electrode and TFT channel) is relevant for optimum performance of water-gated TFTs.

Hysteresis-Free Carbon Nanotube Field-Effect Transistors.

PubMed

Park, Rebecca S; Hills, Gage; Sohn, Joon; Mitra, Subhasish; Shulaker, Max M; Wong, H-S Philip

2017-05-23

While carbon nanotube (CNT) field-effect transistors (CNFETs) promise high-performance and energy-efficient digital systems, large hysteresis degrades these potential CNFET benefits. As hysteresis is caused by traps surrounding the CNTs, previous works have shown that clean interfaces that are free of traps are important to minimize hysteresis. Our previous findings on the sources and physics of hysteresis in CNFETs enabled us to understand the influence of gate dielectric scaling on hysteresis. To begin with, we validate through simulations how scaling the gate dielectric thickness results in greater-than-expected benefits in reducing hysteresis. Leveraging this insight, we experimentally demonstrate reducing hysteresis to <0.5% of the gate-source voltage sweep range using a very large-scale integration compatible and solid-state technology, simply by fabricating CNFETs with a thin effective oxide thickness of 1.6 nm. However, even with negligible hysteresis, large subthreshold swing is still observed in the CNFETs with multiple CNTs per transistor. We show that the cause of large subthreshold swing is due to threshold voltage variation between individual CNTs. We also show that the source of this threshold voltage variation is not explained solely by variations in CNT diameters (as is often ascribed). Rather, other factors unrelated to the CNTs themselves (i.e., process variations, random fixed charges at interfaces) are a significant factor in CNT threshold voltage variations and thus need to be further improved.

Improving pH sensitivity by field-induced charge regulation in flexible biopolymer electrolyte gated oxide transistors

NASA Astrophysics Data System (ADS)

Liu, Ning; Gan, Lu; Liu, Yu; Gui, Weijun; Li, Wei; Zhang, Xiaohang

2017-10-01

Electrical manipulation of charged ions in electrolyte-gated transistors is crucial for enhancing the electric-double-layer (EDL) gating effect, thereby improving their sensing abilities. Here, indium-zinc-oxide (IZO) based thin-film-transistors (TFTs) are fabricated on flexible plastic substrate. Acid doped chitosan-based biopolymer electrolyte is used as the gate dielectric, exhibiting an extremely high EDL capacitance. By regulating the dynamic EDL charging process with special gate potential profiles, the EDL gating effect of the chitosan-gated TFT is enhanced, and then resulting in higher pH sensitivities. An extremely high sensitivity of ∼57.8 mV/pH close to Nernst limit is achieved when the gate bias of the TFT sensor sweeps at a rate of 10 mV/s. Additionally, an enhanced sensitivity of 2630% in terms of current variation with pH range from 11 to 3 is realized when the device is operated in the ion depletion mode with a negative gate bias of -0.7 V. Robust ionic modulation is demonstrated in such chitosan-gated sensors. Efficiently driving the charged ions in the chitosan-gated IZO-TFT provides a new route for ultrasensitive, low voltage, and low-cost biochemical sensing technologies.

INTERDISCIPLINARY PHYSICS AND RELATED AREAS OF SCIENCE AND TECHNOLOGY: Quantum-Mechanical Study on Surrounding-Gate Metal-Oxide-Semiconductor Field-Effect Transistors

NASA Astrophysics Data System (ADS)

Hu, Guang-Xi; Wang, Ling-Li; Liu, Ran; Tang, Ting-Ao; Qiu, Zhi-Jun

2010-10-01

As the channel length of metal-oxide-semiconductor field-effect transistors (MOSFETs) scales into the nanometer regime, quantum mechanical effects are becoming more and more significant. In this work, a model for the surrounding-gate (SG) nMOSFET is developed. The Schrödinger equation is solved analytically. Some of the solutions are verified via results obtained from simulations. It is found that the percentage of the electrons with lighter conductivity mass increases as the silicon body radius decreases, or as the gate voltage reduces, or as the temperature decreases. The centroid of inversion-layer is driven away from the silicon-oxide interface towards the silicon body, therefore the carriers will suffer less scattering from the interface and the electrons effective mobility of the SG nMOSFETs will be enhanced.

Extended-gate field-effect transistor (EG-FET) with molecularly imprinted polymer (MIP) film for selective inosine determination.

PubMed

Iskierko, Zofia; Sosnowska, Marta; Sharma, Piyush Sindhu; Benincori, Tiziana; D'Souza, Francis; Kaminska, Izabela; Fronc, Krzysztof; Noworyta, Krzysztof

2015-12-15

A novel recognition unit of chemical sensor for selective determination of the inosine, renal disfunction biomarker, was devised and prepared. For that purpose, inosine-templated molecularly imprinted polymer (MIP) film was deposited on an extended-gate field-effect transistor (EG-FET) signal transducing unit. The MIP film was prepared by electrochemical polymerization of bis(bithiophene) derivatives bearing cytosine and boronic acid substituents, in the presence of the inosine template and a thiophene cross-linker. After MIP film deposition, the template was removed, and was confirmed by UV-visible spectroscopy. Subsequently, the film composition was characterized by spectroscopic techniques, and its morphology and thickness were determined by AFM. The finally MIP film-coated extended-gate field-effect transistor (EG-FET) was used for signal transduction. This combination is not widely studied in the literature, despite the fact that it allows for facile integration of electrodeposited MIP film with FET transducer. The linear dynamic concentration range of the chemosensor was 0.5-50 μM with inosine detectability of 0.62 μM. The obtained detectability compares well to the levels of the inosine in body fluids which are in the range 0-2.9 µM for patients with diagnosed diabetic nephropathy, gout or hyperuricemia, and can reach 25 µM in certain cases. The imprinting factor for inosine, determined from piezomicrogravimetric experiments with use of the MIP film-coated quartz crystal resonator, was found to be 5.5. Higher selectivity for inosine with respect to common interferents was also achieved with the present molecularly engineered sensing element. The obtained analytical parameters of the devised chemosensor allow for its use for practical sample measurements. Copyright © 2015 Elsevier B.V. All rights reserved.

Enhancing the pH sensitivity by laterally synergic modulation in dual-gate electric-double-layer transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Liu, Ning; Ningbo Institute of Materials Technology and Engineering, Chinese Academy of Sciences, Ningbo 315201; Hui Liu, Yang

2015-02-16

The sensitivity of a standard ion-sensitive field-effect transistor is limited to be 59.2 mV/pH (Nernst limit) at room temperature. Here, a concept based on laterally synergic electric-double-layer (EDL) modulation is proposed in order to overcome the Nernst limit. Indium-zinc-oxide EDL transistors with two laterally coupled gates are fabricated, and the synergic modulation behaviors of the two asymmetric gates are investigated. A high sensitivity of ∼168 mV/pH is realized in the dual-gate operation mode. Laterally synergic modulation in oxide-based EDL transistors is interesting for high-performance bio-chemical sensors.

Dependence of electrical and time stress in organic field effect transistor with low temperature forming gas treated Al2O3 gate dielectrics.

PubMed

Lee, Sunwoo; Chung, Keum Jee; Park, In-Sung; Ahn, Jinho

2009-12-01

We report the characteristics of the organic field effect transistor (OFET) after electrical and time stress. Aluminum oxide (Al2O3) was used as a gate dielectric layer. The surface of the gate oxide layer was treated with hydrogen (H2) and nitrogen (N2) mixed gas to minimize the dangling bond at the interface layer of gate oxide. According to the two stress parameters of electrical and time stress, threshold voltage shift was observed. In particular, the mobility and subthreshold swing of OFET were significantly decreased due to hole carrier localization and degradation of the channel layer between gate oxide and pentacene by electrical stress. Electrical stress is a more critical factor in the degradation of mobility than time stress caused by H2O and O2 in the air.

Antiferromagnetic Spin Wave Field-Effect Transistor

DOE PAGES

Cheng, Ran; Daniels, Matthew W.; Zhu, Jian-Gang; ...

2016-04-06

In a collinear antiferromagnet with easy-axis anisotropy, symmetry dictates that the spin wave modes must be doubly degenerate. Theses two modes, distinguished by their opposite polarization and available only in antiferromagnets, give rise to a novel degree of freedom to encode and process information. We show that the spin wave polarization can be manipulated by an electric field induced Dzyaloshinskii-Moriya interaction and magnetic anisotropy. We propose a prototype spin wave field effect transistor which realizes a gate-tunable magnonic analog of the Faraday effect, and demonstrate its application in THz signal modulation. In conclusion, our findings open up the exciting possibilitymore » of digital data processing utilizing antiferromagnetic spin waves and enable the direct projection of optical computing concepts onto the mesoscopic scale.« less

Printing Semiconductor-Insulator Polymer Bilayers for High-Performance Coplanar Field-Effect Transistors.

PubMed

Bu, Laju; Hu, Mengxing; Lu, Wanlong; Wang, Ziyu; Lu, Guanghao

2018-01-01

Source-semiconductor-drain coplanar transistors with an organic semiconductor layer located within the same plane of source/drain electrodes are attractive for next-generation electronics, because they could be used to reduce material consumption, minimize parasitic leakage current, avoid cross-talk among different devices, and simplify the fabrication process of circuits. Here, a one-step, drop-casting-like printing method to realize a coplanar transistor using a model semiconductor/insulator [poly(3-hexylthiophene) (P3HT)/polystyrene (PS)] blend is developed. By manipulating the solution dewetting dynamics on the metal electrode and SiO 2 dielectric, the solution within the channel region is selectively confined, and thus make the top surface of source/drain electrodes completely free of polymers. Subsequently, during solvent evaporation, vertical phase separation between P3HT and PS leads to a semiconductor-insulator bilayer structure, contributing to an improved transistor performance. Moreover, this coplanar transistor with semiconductor-insulator bilayer structure is an ideal system for injecting charges into the insulator via gate-stress, and the thus-formed PS electret layer acts as a "nonuniform floating gate" to tune the threshold voltage and effective mobility of the transistors. Effective field-effect mobility higher than 1 cm 2 V -1 s -1 with an on/off ratio > 10 7 is realized, and the performances are comparable to those of commercial amorphous silicon transistors. This coplanar transistor simplifies the fabrication process of corresponding circuits. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Monte Carlo simulations of spin transport in a strained nanoscale InGaAs field effect transistor

NASA Astrophysics Data System (ADS)

Thorpe, B.; Kalna, K.; Langbein, F. C.; Schirmer, S.

2017-12-01

Spin-based logic devices could operate at a very high speed with a very low energy consumption and hold significant promise for quantum information processing and metrology. We develop a spintronic device simulator by combining an in-house developed, experimentally verified, ensemble self-consistent Monte Carlo device simulator with spin transport based on a Bloch equation model and a spin-orbit interaction Hamiltonian accounting for Dresselhaus and Rashba couplings. It is employed to simulate a spin field effect transistor operating under externally applied voltages on a gate and a drain. In particular, we simulate electron spin transport in a 25 nm gate length In0.7Ga0.3As metal-oxide-semiconductor field-effect transistor with a CMOS compatible architecture. We observe a non-uniform decay of the net magnetization between the source and the gate and a magnetization recovery effect due to spin refocusing induced by a high electric field between the gate and the drain. We demonstrate a coherent control of the polarization vector of the drain current via the source-drain and gate voltages, and show that the magnetization of the drain current can be increased twofold by the strain induced into the channel.

Experimental Study of the Detection Limit in Dual-Gate Biosensors Using Ultrathin Silicon Transistors

DOE PAGES

Wu, Ting; Alharbi, Abdullah; You, Kai-Dyi; ...

2017-06-21

Dual-gate field-effect biosensors (bioFETs) with asymmetric gate capacitances were shown to surpass the Nernst limit of 59 mV/pH. However, previous studies have conflicting findings on the effect of the capacitive amplification scheme on the sensor detection limit, which is inversely proportional to the signal-to-noise ratio (SNR). In this paper, we present a systematic experimental investigation of the SNR using ultrathin silicon transistors. Our sensors operate at low voltage and feature asymmetric front and back oxide capacitances with asymmetry factors of 1.4 and 2.3. We demonstrate that in the dual-gate configuration, the response of our bioFETs to the pH change increasesmore » proportional to the asymmetry factor and indeed exceeds the Nernst limit. Further, our results reveal that the noise amplitude also increases in proportion to the asymmetry factor. We establish that the commensurate increase of the noise amplitude originates from the intrinsic low-frequency characteristic of the sensor noise, dominated by number fluctuation. Finally, these findings suggest that this capacitive signal amplification scheme does not improve the intrinsic detection limit of the dual-gate biosensors.« less

Experimental Study of the Detection Limit in Dual-Gate Biosensors Using Ultrathin Silicon Transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wu, Ting; Alharbi, Abdullah; You, Kai-Dyi

Dual-gate field-effect biosensors (bioFETs) with asymmetric gate capacitances were shown to surpass the Nernst limit of 59 mV/pH. However, previous studies have conflicting findings on the effect of the capacitive amplification scheme on the sensor detection limit, which is inversely proportional to the signal-to-noise ratio (SNR). In this paper, we present a systematic experimental investigation of the SNR using ultrathin silicon transistors. Our sensors operate at low voltage and feature asymmetric front and back oxide capacitances with asymmetry factors of 1.4 and 2.3. We demonstrate that in the dual-gate configuration, the response of our bioFETs to the pH change increasesmore » proportional to the asymmetry factor and indeed exceeds the Nernst limit. Further, our results reveal that the noise amplitude also increases in proportion to the asymmetry factor. We establish that the commensurate increase of the noise amplitude originates from the intrinsic low-frequency characteristic of the sensor noise, dominated by number fluctuation. Finally, these findings suggest that this capacitive signal amplification scheme does not improve the intrinsic detection limit of the dual-gate biosensors.« less

Experimental Study of the Detection Limit in Dual-Gate Biosensors Using Ultrathin Silicon Transistors.

PubMed

Wu, Ting; Alharbi, Abdullah; You, Kai-Dyi; Kisslinger, Kim; Stach, Eric A; Shahrjerdi, Davood

2017-07-25

Dual-gate field-effect biosensors (bioFETs) with asymmetric gate capacitances were shown to surpass the Nernst limit of 59 mV/pH. However, previous studies have conflicting findings on the effect of the capacitive amplification scheme on the sensor detection limit, which is inversely proportional to the signal-to-noise ratio (SNR). Here, we present a systematic experimental investigation of the SNR using ultrathin silicon transistors. Our sensors operate at low voltage and feature asymmetric front and back oxide capacitances with asymmetry factors of 1.4 and 2.3. We demonstrate that in the dual-gate configuration, the response of our bioFETs to the pH change increases proportional to the asymmetry factor and indeed exceeds the Nernst limit. Further, our results reveal that the noise amplitude also increases in proportion to the asymmetry factor. We establish that the commensurate increase of the noise amplitude originates from the intrinsic low-frequency characteristic of the sensor noise, dominated by number fluctuation. These findings suggest that this capacitive signal amplification scheme does not improve the intrinsic detection limit of the dual-gate biosensors.

Flexible Proton-Gated Oxide Synaptic Transistors on Si Membrane.

PubMed

Zhu, Li Qiang; Wan, Chang Jin; Gao, Ping Qi; Liu, Yang Hui; Xiao, Hui; Ye, Ji Chun; Wan, Qing

2016-08-24

Ion-conducting materials have received considerable attention for their applications in fuel cells, electrochemical devices, and sensors. Here, flexible indium zinc oxide (InZnO) synaptic transistors with multiple presynaptic inputs gated by proton-conducting phosphorosilicate glass-based electrolyte films are fabricated on ultrathin Si membranes. Transient characteristics of the proton gated InZnO synaptic transistors are investigated, indicating stable proton-gating behaviors. Short-term synaptic plasticities are mimicked on the proposed proton-gated synaptic transistors. Furthermore, synaptic integration regulations are mimicked on the proposed synaptic transistor networks. Spiking logic modulations are realized based on the transition between superlinear and sublinear synaptic integration. The multigates coupled flexible proton-gated oxide synaptic transistors may be interesting for neuroinspired platforms with sophisticated spatiotemporal information processing.

Bias temperature instability in tunnel field-effect transistors

NASA Astrophysics Data System (ADS)

Mizubayashi, Wataru; Mori, Takahiro; Fukuda, Koichi; Ishikawa, Yuki; Morita, Yukinori; Migita, Shinji; Ota, Hiroyuki; Liu, Yongxun; O'uchi, Shinichi; Tsukada, Junichi; Yamauchi, Hiromi; Matsukawa, Takashi; Masahara, Meishoku; Endo, Kazuhiko

2017-04-01

We systematically investigated the bias temperature instability (BTI) of tunnel field-effect transistors (TFETs). The positive BTI and negative BTI mechanisms in TFETs are the same as those in metal-oxide-semiconductor FETs (MOSFETs). In TFETs, although traps are generated in high-k gate dielectrics by the bias stress and/or the interface state is degraded at the interfacial layer/channel interface, the threshold voltage (V th) shift due to BTI degradation is caused by the traps and/or the degradation of the interface state locating the band-to-band tunneling (BTBT) region near the source/gate edge. The BTI lifetime in n- and p-type TFETs is improved by applying a drain bias corresponding to the operation conditions.

G4-FETs as Universal and Programmable Logic Gates

NASA Technical Reports Server (NTRS)

Johnson, Travis; Fijany, Amir; Mojarradi, Mohammad; Vatan, Farrokh; Toomarian, Nikzad; Kolawa, Elizabeth; Cristoloveanu, Sorin; Blalock, Benjamin

2007-01-01

An analysis of a patented generic silicon- on-insulator (SOI) electronic device called a G4-FET has revealed that the device could be designed to function as a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer discrete components than are required for conventional transistor-based circuits performing the same logic functions. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G4-FET can also be regarded as a single transistor having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of the SOI substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. With proper choice of the specific dimensions for the gates, channels, and ancillary features of the generic G4-FET, the device could be made to function as a three-input, one-output logic gate. As illustrated by the truth table in the top part of the figure, the behavior of this logic gate would be the inverse (the NOT) of that of a majority gate. In other words, the device would function as a NOT-majority gate. By simply adding an inverter, one could obtain a majority gate. In contrast, to construct a majority gate in conventional complementary metal oxide/semiconductor (CMOS) circuitry, one would need four three-input AND gates and a four-input OR gate, altogether containing 32 transistors.

Double gate graphene nanoribbon field effect transistor with single halo pocket in channel region

NASA Astrophysics Data System (ADS)

Naderi, Ali

2016-01-01

A new structure for graphene nanoribbon field-effect transistors (GNRFETs) is proposed and investigated using quantum simulation with a nonequilibrium Green's function (NEGF) method. Tunneling leakage current and ambipolar conduction are known effects for MOSFET-like GNRFETs. To minimize these issues a novel structure with a simple change of the GNRFETs by using single halo pocket in the intrinsic channel region, "Single Halo GNRFET (SH-GNRFET)", is proposed. An appropriate halo pocket at source side of channel is used to modify potential distribution of the gate region and weaken band to band tunneling (BTBT). In devices with materials like Si in channel region, doping type of halo and source/drain regions are different. But, here, due to the smaller bandgap of graphene, the mentioned doping types should be the same to reduce BTBT. Simulations have shown that in comparison with conventional GNRFET (C-GNRFET), an SH-GNRFET with appropriately halo doping results in a larger ON current (Ion), smaller OFF current (Ioff), a larger ON-OFF current ratio (Ion/Ioff), superior ambipolar characteristics, a reduced power-delay product and lower delay time.

Single ZnO nanowire-PZT optothermal field effect transistors.

PubMed

Hsieh, Chun-Yi; Lu, Meng-Lin; Chen, Ju-Ying; Chen, Yung-Ting; Chen, Yang-Fang; Shih, Wan Y; Shih, Wei-Heng

2012-09-07

A new type of pyroelectric field effect transistor based on a composite consisting of single zinc oxide nanowire and lead zirconate titanate (ZnO NW-PZT) has been developed. Under infrared (IR) laser illumination, the transconductance of the ZnO NW can be modulated by optothermal gating. The drain current can be increased or decreased by IR illumination depending on the polarization orientation of the Pb(Zr(0.3)Ti(0.7))O(3) (PZT) substrate. Furthermore, by combining the photocurrent behavior in the UV range and the optothermal gating effect in the IR range, the wide spectrum of response of current by light offers a variety of opportunities for nanoscale optoelectronic devices.

Modeling of Metal-Ferroelectric-Semiconductor Field Effect Transistors

NASA Technical Reports Server (NTRS)

Duen Ho, Fat; Macleod, Todd C.

1998-01-01

The characteristics for a MFSFET (metal-ferroelectric-semiconductor field effect transistor) is very different than a conventional MOSFET and must be modeled differently. The drain current has a hysteresis shape with respect to the gate voltage. The position along the hysteresis curve is dependent on the last positive or negative polling of the ferroelectric material. The drain current also has a logarithmic decay after the last polling. A model has been developed to describe the MFSFET drain current for both gate voltage on and gate voltage off conditions. This model takes into account the hysteresis nature of the MFSFET and the time dependent decay. The model is based on the shape of the Fermi-Dirac function which has been modified to describe the MFSFET's drain current. This is different from the model proposed by Chen et. al. and that by Wu.

Effects of Energy Relaxation via Quantum Coupling Among Three-Dimensional Motion on the Tunneling Current of Graphene Field-Effect Transistors.

PubMed

Mao, Ling-Feng; Ning, Huansheng; Li, Xijun

2015-12-01

We report theoretical study of the effects of energy relaxation on the tunneling current through the oxide layer of a two-dimensional graphene field-effect transistor. In the channel, when three-dimensional electron thermal motion is considered in the Schrödinger equation, the gate leakage current at a given oxide field largely increases with the channel electric field, electron mobility, and energy relaxation time of electrons. Such an increase can be especially significant when the channel electric field is larger than 1 kV/cm. Numerical calculations show that the relative increment of the tunneling current through the gate oxide will decrease with increasing the thickness of oxide layer when the oxide is a few nanometers thick. This highlights that energy relaxation effect needs to be considered in modeling graphene transistors.

Highly tunable local gate controlled complementary graphene device performing as inverter and voltage controlled resistor.

PubMed

Kim, Wonjae; Riikonen, Juha; Li, Changfeng; Chen, Ya; Lipsanen, Harri

2013-10-04

Using single-layer CVD graphene, a complementary field effect transistor (FET) device is fabricated on the top of separated back-gates. The local back-gate control of the transistors, which operate with low bias at room temperature, enables highly tunable device characteristics due to separate control over electrostatic doping of the channels. Local back-gating allows control of the doping level independently of the supply voltage, which enables device operation with very low VDD. Controllable characteristics also allow the compensation of variation in the unintentional doping typically observed in CVD graphene. Moreover, both p-n and n-p configurations of FETs can be achieved by electrostatic doping using the local back-gate. Therefore, the device operation can also be switched from inverter to voltage controlled resistor, opening new possibilities in using graphene in logic circuitry.

Diamond field effect transistors with a high-dielectric constant Ta2O5 as gate material

NASA Astrophysics Data System (ADS)

Liu, J.-W.; Liao, M.-Y.; Imura, M.; Watanabe, E.; Oosato, H.; Koide, Y.

2014-06-01

A Ta2O5/Al2O3 bilayer gate oxide with a high-dielectric constant (high-k) has been successfully applied to a hydrogenated-diamond (H-diamond) metal-insulator-semiconductor field effect transistor (MISFET). The Ta2O5 layer is prepared by a sputtering-deposition (SD) technique on the Al2O3 buffer layer fabricated by an atomic layer deposition (ALD) technique. The ALD-Al2O3 plays an important role to eliminate plasma damage for the H-diamond surface during SD-Ta2O5 deposition. The dielectric constants of the SD-Ta2O5/ALD-Al2O3 bilayer and single SD-Ta2O5 are as large as 12.7 and 16.5, respectively. The k value of the single SD-Ta2O5 in this study is in good agreement with that of the SD-Ta2O5 on oxygen-terminated diamond. The capacitance-voltage characteristic suggests low interfacial trapped charge density for the SD-Ta2O5/ALD-Al2O3/H-diamond MIS diode. The MISFET with a gate length of 4 µm has a drain current maximum and an extrinsic transconductance of -97.7 mA mm-1 (normalized by gate width) and 31.0 ± 0.1 mS mm-1, respectively. The effective mobility in the H-diamond channel layer is found to be 70.1 ± 0.5 cm2 V-1 s-1.

An Al2O3 Gating Substrate for the Greater Performance of Field Effect Transistors Based on Two-Dimensional Materials

PubMed Central

Zheng, Xiaoming; Wang, Guang; Tan, Yuan; Zhang, Xueao

2017-01-01

We fabricated 70 nm Al2O3 gated field effect transistors based on two-dimensional (2D) materials and characterized their optical and electrical properties. Studies show that the optical contrast of monolayer graphene on an Al2O3/Si substrate is superior to that on a traditional 300 nm SiO2/Si substrate (2.4 times). Significantly, the transconductance of monolayer graphene transistors on the Al2O3/Si substrate shows an approximately 10-fold increase, due to a smaller dielectric thickness and a higher dielectric constant. Furthermore, this substrate is also suitable for other 2D materials, such as WS2, and can enhance the transconductance remarkably by 61.3 times. These results demonstrate a new and ideal substrate for the fabrication of 2D materials-based electronic logic devices. PMID:28937619

Gate insulator effects on the electrical performance of ZnO thin film transistor on a polyethersulphone substrate.

PubMed

Lee, Jae-Kyu; Choi, Duck-Kyun

2012-07-01

Low temperature processing for fabrication of transistor backplane is a cost effective solution while fabrication on a flexible substrate offers a new opportunity in display business. Combination of both merits is evaluated in this investigation. In this study, the ZnO thin film transistor on a flexible Polyethersulphone (PES) substrate is fabricated using RF magnetron sputtering. Since the selection and design of compatible gate insulator is another important issue to improve the electrical properties of ZnO TFT, we have evaluated three gate insulator candidates; SiO2, SiNx and SiO2/SiNx. The SiO2 passivation on both sides of PES substrate prior to the deposition of ZnO layer was effective to enhance the mechanical and thermal stability. Among the fabricated devices, ZnO TFT employing SiNx/SiO2 stacked gate exhibited the best performance. The device parameters of interest are extracted and the on/off current ratio, field effect mobility, threshold voltage and subthreshold swing are 10(7), 22 cm2/Vs, 1.7 V and 0.4 V/decade, respectively.

Negative Photoconductance in Heavily Doped Si Nanowire Field-Effect Transistors.

PubMed

Baek, Eunhye; Rim, Taiuk; Schütt, Julian; Baek, Chang-Ki; Kim, Kihyun; Baraban, Larysa; Cuniberti, Gianaurelio

2017-11-08

We report the first observation of negative photoconductance (NPC) in n- and p-doped Si nanowire field-effect transistors (FETs) and demonstrate the strong influence of doping concentrations on the nonconventional optical switching of the devices. Furthermore, we show that the NPC of Si nanowire FETs is dependent on the wavelength of visible light due to the phonon-assisted excitation to multiple conduction bands with different band gap energies that would be a distinct optoelectronic property of indirect band gap semiconductor. We attribute the main driving force of NPC in Si nanowire FETs to the photogenerated hot electrons trapping by dopants ions and interfacial states. Finally, comparing back- and top-gate modulation, we derive the mechanisms of the transition between negative and positive photoconductance regimes in nanowire devices. The transition is decided by the competition between the light-induced interfacial trapping and the recombination of mobile carriers, which is dependent on the light intensity and the doping concentration.

Top-gate organic depletion and inversion transistors with doped channel and injection contact

NASA Astrophysics Data System (ADS)

Liu, Xuhai; Kasemann, Daniel; Leo, Karl

2015-03-01

Organic field-effect transistors constitute a vibrant research field and open application perspectives in flexible electronics. For a commercial breakthrough, however, significant performance improvements are still needed, e.g., stable and high charge carrier mobility and on-off ratio, tunable threshold voltage, as well as integrability criteria such as n- and p-channel operation and top-gate architecture. Here, we show pentacene-based top-gate organic transistors operated in depletion and inversion regimes, realized by doping source and drain contacts as well as a thin layer of the transistor channel. By varying the doping concentration and the thickness of the doped channel, we control the position of the threshold voltage without degrading on-off ratio or mobility. Capacitance-voltage measurements show that an inversion channel can indeed be formed, e.g., an n-doped channel can be inverted to a p-type inversion channel with highly p-doped contacts. The Cytop polymer dielectric minimizes hysteresis, and the transistors can be biased for prolonged cycles without a shift of threshold voltage, indicating excellent operation stability.

pH sensing characteristics and biosensing application of solution-gated reduced graphene oxide field-effect transistors.

PubMed

Sohn, Il-Yung; Kim, Duck-Jin; Jung, Jin-Heak; Yoon, Ok Ja; Thanh, Tien Nguyen; Quang, Trung Tran; Lee, Nae-Eung

2013-07-15

Solution-gated reduced graphene oxide field-effect transistors (R-GO FETs) were investigated for pH sensing and biochemical sensing applications. A channel of a networked R-GO film formed by self-assembly was incorporated as a sensing layer into a solution-gated FET structure for pH sensing and the detection of acetylcholine (Ach), which is a neurotransmitter in the nerve system, through enzymatic reactions. The fabricated R-GO FET was sensitive to protons (H(+)) with a pH sensitivity of 29 mV/pH in terms of the shift of the charge neutrality point (CNP), which is attributed to changes in the surface potential caused by the interaction of protons with OH surface functional groups present on the R-GO surface. The R-GO FET immobilized with acetylcholinesterase (AchE) was used to detect Ach in the concentration range of 0.1-10mM by sensing protons generated during the enzymatic reactions. The results indicate that R-GO FETs provide the capability to detect protons, demonstrating their applicability as a biosensing device for enzymatic reactions. Copyright © 2013 Elsevier B.V. All rights reserved.

Gate dielectric surface treatments for performance improvement of poly(3-hexylthiophene-2,5-diyl) based organic field-effect transistors

NASA Astrophysics Data System (ADS)

Nawaz, Ali; de, Cristiane, , Col; Cruz-Cruz, Isidro; Kumar, Anshu; Kumar, Anil; Hümmelgen, Ivo A.

2015-08-01

We report on enhanced performance in poly(3-hexylthiophene-2,5-diyl) (P3HT) based organic field effect transistors (OFETs) achieved by improvement in hole transport along the channel near the insulator/semiconductor (I/S) interface. The improvement in hole transport is demonstrated to occur very close to the I/S interface, after treatment of the insulator layer with sodium dodecyl sulfate (SDS). SDS is an anionic surfactant, with negatively charged heads, known for formation of micelles above critical micelle concentration (CMC), which contribute to the passivation of positively charged traps. Investigation of field-effect mobility (μFET) as a function of channel bottleneck thickness in OFETs reveals the favorable gate voltage regime where mobility is the highest. In addition, it shows that the gate dielectric surface treatment not only leads to an increase in mobility in that regime, but also displaces charge transport closer to the interface, hence pointing toward passivation of the charge traps at I/S interface. OFETs with SDS treatment were compared with untreated and vitamin C or hexadecyltrimethylammonium bromide (CTAB) treated OFETs. All the treatments resulted in significant improvements in specific dielectric capacitance, μFET, on/off current ratio and transconductance.

Scaling effects of a graphene field effect transistor for radiation detection

NASA Astrophysics Data System (ADS)

Shollar, Zachary Frank

Radiation detectors based on graphene is a burgeoning research topic within the immense field of graphene research. Although papers continue to parse out their mysteries, the devices remain simplistic and small. New fabrication techniques have allowed for millimeter scale and larger monolayer graphene sheets to be grown with increasingly better quality. It is the goal of this thesis to investigate the scaling effects of millimeter scale graphene for radiation detection purposes. To this end, chemical vapor deposition grown monolayer graphene was purchased and transferred to Si/SiO2 substrates. The devices were patterned into simple rectangular strips varying in size from 3000 x 500 mum, 600 x 100 mum, 300 x 50 mum, and 60 x 11 mum. Four metal contacts were patterned onto each strip for electrical characterization. Two probe resistance measurements were performed on all four sizes, at three different lengths along the graphene. Using the field effect, the graphene resistance response was measured at 0 V back-gate voltage to obtain graphene resistivity on SiO2, which showed an increase in resistivity as the graphene strip size increased. Further, the response was measured for varying back-gate sweep ranges and speeds. This lead to the conclusion that strong p-doping was inherent in the graphene strips, as evidenced by charge neutral points located above +50 V. Strong hysteresis observed in those tests alluded to trapped charge having a major effect on voltage sweeps. Mobility values for the graphene strips were extracted from the back-gate voltage sweeps and fixed gate voltage stabilization curves. Mobility values overall were less than 400 cm2 V-1 s-1, and showed a modest increase in mobility as graphene length increased. Lastly, the largest graphene strip had a light response and radiation response measured. Light response showed a dependence on gate voltage magnitude that favored positive gate voltages, on an n-type Silicon substrate. A saturation effect above +15

The effects of transistor source-to-gate bridging faults in complex CMOS gates

NASA Astrophysics Data System (ADS)

Visweswaran, G. S.; Ali, Akhtar-Uz-Zaman M.; Lala, Parag K.; Hartmann, Carlos R. P.

1991-06-01

A study of the effect of gate-to-source bridging faults in the pull-up section of a complex CMOS gate is presented. The manifestation of these faults depends on the resistance value of the connection causing the bridging. It is shown that such faults manifest themselves either as stuck-at or stuck-open faults and can be detected by tests for stuck-at and stuck-open faults generated for the equivalent logic current. It is observed that for transistor channel lengths larger than 1 microns there exists a range of values of the bridging resistance for which the fault behaves as a pseudo-stuck-open fault.

Double gate impact ionization MOS transistor: Proposal and investigation

NASA Astrophysics Data System (ADS)

Yang, Zhaonian; Zhang, Yue; Yang, Yuan; Yu, Ningmei

2017-02-01

In this paper, a double gate impact ionization MOS (DG-IMOS) transistor with improved performance is proposed and investigated by TCAD simulation. In the proposed design, a second gate is introduced in a conventional impact ionization MOS (IMOS) transistor that lengthens the equivalent channel length and suppresses the band-to-band tunneling. The OFF-state leakage current is reduced by over four orders of magnitude. At the ON-state, the second gate is negatively biased in order to enhance the electric field in the intrinsic region. As a result, the operating voltage does not increase with the increase in the channel length. The simulation result verifies that the proposed DG-IMOS achieves a better switching characteristic than the conventional is achieved. Lastly, the application of the DG-IMOS is discussed theoretically.

Inversion channel diamond metal-oxide-semiconductor field-effect transistor with normally off characteristics.

PubMed

Matsumoto, Tsubasa; Kato, Hiromitsu; Oyama, Kazuhiro; Makino, Toshiharu; Ogura, Masahiko; Takeuchi, Daisuke; Inokuma, Takao; Tokuda, Norio; Yamasaki, Satoshi

2016-08-22

We fabricated inversion channel diamond metal-oxide-semiconductor field-effect transistors (MOSFETs) with normally off characteristics. At present, Si MOSFETs and insulated gate bipolar transistors (IGBTs) with inversion channels are widely used because of their high controllability of electric power and high tolerance. Although a diamond semiconductor is considered to be a material with a strong potential for application in next-generation power devices, diamond MOSFETs with an inversion channel have not yet been reported. We precisely controlled the MOS interface for diamond by wet annealing and fabricated p-channel and planar-type MOSFETs with phosphorus-doped n-type body on diamond (111) substrate. The gate oxide of Al2O3 was deposited onto the n-type diamond body by atomic layer deposition at 300 °C. The drain current was controlled by the negative gate voltage, indicating that an inversion channel with a p-type character was formed at a high-quality n-type diamond body/Al2O3 interface. The maximum drain current density and the field-effect mobility of a diamond MOSFET with a gate electrode length of 5 μm were 1.6 mA/mm and 8.0 cm(2)/Vs, respectively, at room temperature.

Deformable Organic Nanowire Field-Effect Transistors.

PubMed

Lee, Yeongjun; Oh, Jin Young; Kim, Taeho Roy; Gu, Xiaodan; Kim, Yeongin; Wang, Ging-Ji Nathan; Wu, Hung-Chin; Pfattner, Raphael; To, John W F; Katsumata, Toru; Son, Donghee; Kang, Jiheong; Matthews, James R; Niu, Weijun; He, Mingqian; Sinclair, Robert; Cui, Yi; Tok, Jeffery B-H; Lee, Tae-Woo; Bao, Zhenan

2018-02-01

Deformable electronic devices that are impervious to mechanical influence when mounted on surfaces of dynamically changing soft matters have great potential for next-generation implantable bioelectronic devices. Here, deformable field-effect transistors (FETs) composed of single organic nanowires (NWs) as the semiconductor are presented. The NWs are composed of fused thiophene diketopyrrolopyrrole based polymer semiconductor and high-molecular-weight polyethylene oxide as both the molecular binder and deformability enhancer. The obtained transistors show high field-effect mobility >8 cm 2 V -1 s -1 with poly(vinylidenefluoride-co-trifluoroethylene) polymer dielectric and can easily be deformed by applied strains (both 100% tensile and compressive strains). The electrical reliability and mechanical durability of the NWs can be significantly enhanced by forming serpentine-like structures of the NWs. Remarkably, the fully deformable NW FETs withstand 3D volume changes (>1700% and reverting back to original state) of a rubber balloon with constant current output, on the surface of which it is attached. The deformable transistors can robustly operate without noticeable degradation on a mechanically dynamic soft matter surface, e.g., a pulsating balloon (pulse rate: 40 min -1 (0.67 Hz) and 40% volume expansion) that mimics a beating heart, which underscores its potential for future biomedical applications. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Current saturation and voltage gain in bilayer graphene field effect transistors.

PubMed

Szafranek, B N; Fiori, G; Schall, D; Neumaier, D; Kurz, H

2012-03-14

The emergence of graphene with its unique electrical properties has triggered hopes in the electronic devices community regarding its exploitation as a channel material in field effect transistors. Graphene is especially promising for devices working at frequencies in the 100 GHz range. So far, graphene field effect transistors (GFETs) have shown cutoff frequencies up to 300 GHz, while exhibiting poor voltage gains, another important figure of merit for analog high frequency applications. In the present work, we show that the voltage gain of GFETs can be improved significantly by using bilayer graphene, where a band gap is introduced through a vertical electric displacement field. At a displacement field of -1.7 V/nm the bilayer GFETs exhibit an intrinsic voltage gain up to 35, a factor of 6 higher than the voltage gain in corresponding monolayer GFETs. The transconductance, which limits the cutoff frequency of a transistor, is not degraded by the displacement field and is similar in both monolayer and bilayer GFETs. Using numerical simulations based on an atomistic p(z) tight-binding Hamiltonian we demonstrate that this approach can be extended to sub-100 nm gate lengths. © 2012 American Chemical Society

A unified analytical drain current model for Double-Gate Junctionless Field-Effect Transistors including short channel effects

NASA Astrophysics Data System (ADS)

Raksharam; Dutta, Aloke K.

2017-04-01

In this paper, a unified analytical model for the drain current of a symmetric Double-Gate Junctionless Field-Effect Transistor (DG-JLFET) is presented. The operation of the device has been classified into four modes: subthreshold, semi-depleted, accumulation, and hybrid; with the main focus of this work being on the accumulation mode, which has not been dealt with in detail so far in the literature. A physics-based model, using a simplified one-dimensional approach, has been developed for this mode, and it has been successfully integrated with the model for the hybrid mode. It also includes the effect of carrier mobility degradation due to the transverse electric field, which was hitherto missing in the earlier models reported in the literature. The piece-wise models have been unified using suitable interpolation functions. In addition, the model includes two most important short-channel effects pertaining to DG-JLFETs, namely the Drain Induced Barrier Lowering (DIBL) and the Subthreshold Swing (SS) degradation. The model is completely analytical, and is thus computationally highly efficient. The results of our model have shown an excellent match with those obtained from TCAD simulations for both long- and short-channel devices, as well as with the experimental data reported in the literature.

Floating gate transistors as biosensors (Conference Presentation)

NASA Astrophysics Data System (ADS)

Frisbie, C. Daniel

2016-11-01

Electrolyte gated transistors (EGTs) are a sub-class of thin film transistors that are extremely promising for biological sensing applications. These devices employ a solid electrolyte as the gate insulator; the very large capacitance of the electrolyte results in low voltage operation and high transconductance or gain. This talk will describe the fabrication of floating gate EGTs and their use as ricin sensors. The critical performance metrics for EGTs compared with other types of TFTs will also be reviewed.

Junctionless Thin-Film Transistors Gated by an H₃PO₄-Incorporated Chitosan Proton Conductor.

PubMed

Liu, Huixuan; Xun, Damao

2018-04-01

We fabricated an H3PO4-incorporated chitosan proton conductor film that exhibited the electric double layer effect and showed a high specific capacitance of 4.42 μF/cm2. Transparent indium tin oxide thin-film transistors gated by H3PO4-incorporated chitosan films were fabricated by sputtering through a shadow mask. The operating voltage was as low as 1.2 V because of the high specific capacitance of the H3PO4-incorporated chitosan dielectrics. The junctionless transparent indium tin oxide thin film transistors exhibited good performance, including an estimated current on/off ratio and field-effect mobility of 1.2 × 106 and 6.63 cm2V-1s-1, respectively. These low-voltage thin-film electric-double-layer transistors gated by H3PO4-incorporated chitosan are promising for next generation battery-powered "see-through" portable sensors.

Impact of source height on the characteristic of U-shaped channel tunnel field-effect transistor

NASA Astrophysics Data System (ADS)

Yang, Zhaonian; Zhang, Yue; Yang, Yuan; Yu, Ningmei

2017-11-01

Tunnel field-effect transistor (TFET) is very attractive in replacing a MOSFET, particularly for low-power nanoelectronic circuits. The U-shaped channel TFET (U-TFET) was proposed to improve the drain-source current with a reduced footprint. In this work, the impact of the source height (HS) on the characteristic of the U-shaped channel tunnel field-effect transistor (U-TFET) is investigated by using TCAD simulation. It is found that with a fixed gate height (HG) the drain-source current has a negative correlation with HS. This is because when the gate region is deeper than the source region, the electric field near the corner of the tunneling junction can be enhanced and the tunneling rate is increased. When HS becomes very thin, the drain-source current is limited by the source region volume. The U-TFET with an n+ pocket is also studied and the same trend is observed.

Near interface traps in SiO{sub 2}/4H-SiC metal-oxide-semiconductor field effect transistors monitored by temperature dependent gate current transient measurements

DOE Office of Scientific and Technical Information (OSTI.GOV)

Fiorenza, Patrick; La Magna, Antonino; Vivona, Marilena

This letter reports on the impact of gate oxide trapping states on the conduction mechanisms in SiO{sub 2}/4H-SiC metal-oxide-semiconductor field effect transistors (MOSFETs). The phenomena were studied by gate current transient measurements, performed on n-channel MOSFETs operated in “gate-controlled-diode” configuration. The measurements revealed an anomalous non-steady conduction under negative bias (V{sub G} > |20 V|) through the SiO{sub 2}/4H-SiC interface. The phenomenon was explained by the coexistence of a electron variable range hopping and a hole Fowler-Nordheim (FN) tunnelling. A semi-empirical modified FN model with a time-depended electric field is used to estimate the near interface traps in the gate oxide (N{sub trap} ∼ 2 × 10{supmore » 11} cm{sup −2}).« less

Proton Damage Effects on Carbon Nanotube Field-Effect Transistors

DTIC Science & Technology

2014-06-19

PROTON DAMAGE EFFECTS ON CARBON NANOTUBE FIELD-EFFECT TRANSISTORS THESIS Evan R. Kemp, Ctr...United States. AFIT-ENP-T-14-J-39 PROTON DAMAGE EFFECTS ON CARBON NANOTUBE FIELD-EFFECT TRANSISTORS THESIS Presented to...PROTON DAMAGE EFFECTS ON CARBON NANOTUBE FIELD-EFFECT TRANSISTORS Evan R. Kemp, BS Ctr, USAF Approved: // Signed

Ionic liquid versus SiO 2 gated a-IGZO thin film transistors: A direct comparison

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pudasaini, Pushpa Raj; Noh, Joo Hyon; Wong, Anthony T.

Here, ionic liquid gated field effect transistors have been extensively studied due to their low operation voltage, ease of processing and the realization of high electric fields at low bias voltages. Here, we report ionic liquid (IL) gated thin film transistors (TFTs) based on amorphous Indium Gallium Zinc Oxide (a-IGZO) active layers and directly compare the characteristics with a standard SiO 2 gated device. The transport measurements of the top IL gated device revealed the n-channel property of the IGZO thin film with a current ON/OFF ratio ~10 5, a promising field effect mobility of 14.20 cm 2V –1s –1,more » and a threshold voltage of 0.5 V. Comparable measurements on the bottom SiO2 gate insulator revealed a current ON/OFF ratio >108, a field effect mobility of 13.89 cm 2V –1s –1 and a threshold voltage of 2.5 V. Furthermore, temperature-dependent measurements revealed that the ionic liquid electric double layer can be “frozen-in” by cooling below the glass transition temperature with an applied electrical bias. Positive and negative freezing bias locks-in the IGZO TFT “ON” and “OFF” state, respectively, which could lead to new switching and possibly non-volatile memory applications.« less

Ionic liquid versus SiO 2 gated a-IGZO thin film transistors: A direct comparison

DOE PAGES

Pudasaini, Pushpa Raj; Noh, Joo Hyon; Wong, Anthony T.; ...

2015-08-12

Here, ionic liquid gated field effect transistors have been extensively studied due to their low operation voltage, ease of processing and the realization of high electric fields at low bias voltages. Here, we report ionic liquid (IL) gated thin film transistors (TFTs) based on amorphous Indium Gallium Zinc Oxide (a-IGZO) active layers and directly compare the characteristics with a standard SiO 2 gated device. The transport measurements of the top IL gated device revealed the n-channel property of the IGZO thin film with a current ON/OFF ratio ~10 5, a promising field effect mobility of 14.20 cm 2V –1s –1,more » and a threshold voltage of 0.5 V. Comparable measurements on the bottom SiO2 gate insulator revealed a current ON/OFF ratio >108, a field effect mobility of 13.89 cm 2V –1s –1 and a threshold voltage of 2.5 V. Furthermore, temperature-dependent measurements revealed that the ionic liquid electric double layer can be “frozen-in” by cooling below the glass transition temperature with an applied electrical bias. Positive and negative freezing bias locks-in the IGZO TFT “ON” and “OFF” state, respectively, which could lead to new switching and possibly non-volatile memory applications.« less

Modeling of static electrical properties in organic field-effect transistors

NASA Astrophysics Data System (ADS)

Xu, Yong; Minari, Takeo; Tsukagoshi, Kazuhito; Gwoziecki, Romain; Coppard, Romain; Benwadih, Mohamed; Chroboczek, Jan; Balestra, Francis; Ghibaudo, Gerard

2011-07-01

A modeling of organic field-effect transistors' (OFETs') electrical characteristics is presented. This model is based on a one-dimensional (1-D) Poisson's equation solution that solves the potential profile in the organic semiconducting film. Most importantly, it demonstrates that, due to the common open-surface configuration used in organic transistors, the conduction occurs in the film volume below threshold. This is because the potential at the free surface is not fixed to zero but rather rises also with the gate bias. The tail of carrier concentration at the free surface is therefore significantly modulated by the gate bias, which partially explains the gate-voltage dependent contact resistance. At the same time in the so-called subthreshold region, we observe a clear charge trapping from the difference between C-V and I-V measurements; hence a traps study by numerical simulation is also performed. By combining the analytical modeling and the traps analysis, the questions on the C-V and I-V characteristics are answered. Finally, the combined results obtained with traps fit well the experimental data in both pentacene and bis(triisopropylsilylethynyl)-pentacene OFETs.

Modeling of Gate Bias Modulation in Carbon Nanotube Field-Effect-Transistors

NASA Technical Reports Server (NTRS)

Yamada, Toshishige; Biegel, Bryan (Technical Monitor)

2002-01-01

The threshold voltages of a carbon nanotube (CNT) field-effect transistor (FET) are derived and compared with those of the metal oxide-semiconductor (MOS) FETs. The CNT channel is so thin that there is no voltage drop perpendicular to the gate electrode plane, which is the CNT diameter direction, and this makes the CNTFET characteristics quite different from those in MOSFETs. The relation between the voltage and the electrochemical potentials, and the mass action law for electrons and holes are examined in the context of CNTs, and it is shown that the familiar relations are still valid because of the macroscopic number of states available in the CNTs. This is in sharp contrast to the cases of quantum dots. Using these relations, we derive an inversion threshold voltage V(sub Ti) and an accumulation threshold voltage V(sub Ta) as a function of the Fermi level E(sub F) in the channel, where E(sub F) is a measure of channel doping. V(sub Ti) of the CNTFETs has a much stronger dependence than that of MOSFETs, while V(sub Ta)s of both CNTFETs and MOSFETs depend quite weakly on E(sub F) with the same functional form. This means the transition from normally-off mode to normally-on mode is much sharper in CNTFETs as the doping increases, and this property has to be taken into account in circuit design.

Short-Channel Tunneling Field-Effect Transistor with Drain-Overlap and Dual-Metal Gate Structure for Low-Power and High-Speed Operations.

PubMed

Yoon, Young Jun; Eun, Hye Rim; Seo, Jae Hwa; Kang, Hee-Sung; Lee, Seong Min; Lee, Jeongmin; Cho, Seongjae; Tae, Heung-Sik; Lee, Jung-Hee; Kang, In Man

2015-10-01

We have investigated and proposed a highly scaled tunneling field-effect transistor (TFET) based on Ge/GaAs heterojunction with a drain overlap to suppress drain-induced barrier thinning (DIBT) and improve low-power (LP) performance. The highly scaled TFET with a drain overlap achieves lower leakage tunneling current because of the decrease in tunneling events between the source and drain, whereas a typical short-channel TFET suffers from a great deal of tunneling leakage current due to the DIBT at the off-state. However, the drain overlap inevitably increases the gate-to-drain capacitance (Cgd) because of the increase in the overlap capacitance (Cov) and inversion capacitance (Cinv). Thus, in this work, a dual-metal gate structure is additionally applied along with the drain overlap. The current performance and the total gate capacitance (Cgg) of the device with a dual-metal gate can be possibly controlled by adjusting the metal gate workfunction (φgate) and φoverlap-gate in the overlapping regions. As a result, the intrinsic delay time (τ) is greatly reduced by obtaining lower Cgg divided by the on-state current (Ion), i.e., Cgg/Ion. We have successfully demonstrated excellent LP and high-speed performance of a highly scaled TFET by adopting both drain overlap and dual-metal gate with DIBT minimization.

Field-Effect Transistor-Integration with TiO2 Nanoparticles for Sensing of Cardiac Troponin I Biomarker.

PubMed

Arshad, M K Md; Adzhri, R; Fathil, M F M; Gopinath, Subash C B; N M, Nuzaihan M

2018-08-01

The development of electrical biosensor towards device miniaturization in order to achieve better sensitivity with enhanced electrical signal has certain limitations especially complexity in fabrication process and costs. In this paper, an alternative technique with minor modification in the device structure is presented for signal amplification by implementing ambipolar conduction in the biosensor itself. We demonstrated the field-effect transistor (FET)-based biosensor coupled back-gate for attaining a higher sensitivity with the detection of lower target abundance. To utilize the coupled back-gate as a pre-amplifier, silicon-on-insulator wafer with thicknesses of top-silicon and buried oxide (BOX) layers of 70 nm and 145 nm, respectively were desired. Titanium dioxide (TiO2) nanomaterial was deposited using sol-gel method on the channel which acts as a transducer. Surface functionalization on TiO2 thin film allowed an effective immobilization of anti-cardiac troponin I antibody to interact cardiac troponin I (cTnI). Binding events at each step was validated by X-ray photoelectron spectroscopy (XPS) analysis. Further, electrical characterization (Id-Vd) confirms the potentiality of FET-based biosensor to detect cTnI (represents acute myocardial infarction disease) with the concentration ranges from 10 μg/ml down to 1 fg/ml. The sensitivity of 459.2 nA (g/ml)-1 and lower detection limit of 1 fg/ml were achieved at Vbg = -5 V and Vd = 5 V. The designed device demonstrates its ability to detect lower level of cTnI with pre-amplified electrical signal by back-gate biasing.

Statistical variability study of random dopant fluctuation on gate-all-around inversion-mode silicon nanowire field-effect transistors

NASA Astrophysics Data System (ADS)

Yoon, Jun-Sik; Rim, Taiuk; Kim, Jungsik; Kim, Kihyun; Baek, Chang-Ki; Jeong, Yoon-Ha

2015-03-01

Random dopant fluctuation effects of gate-all-around inversion-mode silicon nanowire field-effect transistors (FETs) with different diameters and extension lengths are investigated. The nanowire FETs with smaller diameter and longer extension length reduce average values and variations of subthreshold swing and drain-induced barrier lowering, thus improving short channel immunity. Relative variations of the drain currents increase as the diameter decreases because of decreased current drivability from narrower channel cross-sections. Absolute variations of the drain currents decrease critically as the extension length increases due to decreasing the number of arsenic dopants penetrating into the channel region. To understand variability origins of the drain currents, variations of source/drain series resistance and low-field mobility are investigated. All these two parameters affect the variations of the drain currents concurrently. The nanowire FETs having extension lengths sufficient to prevent dopant penetration into the channel regions and maintaining relatively large cross-sections are suggested to achieve suitable short channel immunity and small variations of the drain currents.

Biologically sensitive field-effect transistors: from ISFETs to NanoFETs

PubMed Central

Pachauri, Vivek

2016-01-01

Biologically sensitive field-effect transistors (BioFETs) are one of the most abundant classes of electronic sensors for biomolecular detection. Most of the time these sensors are realized as classical ion-sensitive field-effect transistors (ISFETs) having non-metallized gate dielectrics facing an electrolyte solution. In ISFETs, a semiconductor material is used as the active transducer element covered by a gate dielectric layer which is electronically sensitive to the (bio-)chemical changes that occur on its surface. This review will provide a brief overview of the history of ISFET biosensors with general operation concepts and sensing mechanisms. We also discuss silicon nanowire-based ISFETs (SiNW FETs) as the modern nanoscale version of classical ISFETs, as well as strategies to functionalize them with biologically sensitive layers. We include in our discussion other ISFET types based on nanomaterials such as carbon nanotubes, metal oxides and so on. The latest examples of highly sensitive label-free detection of deoxyribonucleic acid (DNA) molecules using SiNW FETs and single-cell recordings for drug screening and other applications of ISFETs will be highlighted. Finally, we suggest new device platforms and newly developed, miniaturized read-out tools with multichannel potentiometric and impedimetric measurement capabilities for future biomedical applications. PMID:27365038

Novel WSi/Au T-shaped gate GaAs metal-semiconductor field-effect-transistor fabrication process for super low-noise microwave monolithic integrated circuit amplifiers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Takano, H.; Hosogi, K.; Kato, T.

1995-05-01

A fully ion-implanted self-aligned T-shaped gate Ga As metal-semiconductor field-effect transistor (MESFET) with high frequency and extremely low-noise performance has been successfully fabricated for super low-noise microwave monolithic integrated circuit (MMIC) amplifiers. A subhalf-micrometer gate structure composed of WSi/Ti/Mo/Au is employed to reduce gate resistance effectively. This multilayer gate structure is formed by newly developed dummy SiON self-alignment technology and a photoresist planarization process. At an operating frequency of 12 GHz, a minimum noise figure of 0.87 dB with an associated gain of 10.62 dB has been obtained. Based on the novel FET process, a low-noise single-stage MMIC amplifier withmore » an excellent low-noise figure of 1.2 dB with an associated gain of 8 dB in the 14 GHz band has been realized. This is the lowest noise figure ever reported at this frequency for low-noise MMICs based on ion-implanted self-aligned gate MESFET technology. 14 refs., 9 figs.« less

Flexible bottom-gate graphene transistors on Parylene C substrate and the effect of current annealing

PubMed Central

Kim, Hyungsoo; Bong, Jihye; Mikael, Solomon; Kim, Tong June; Williams, Justin C.; Ma, Zhenqiang

2016-01-01

Flexible graphene transistors built on a biocompatible Parylene C substrate would enable active circuitry to be integrated into flexible implantable biomedical devices. An annealing method to improve the performance of a flexible transistor without damaging the flexible substrate is also desirable. Here, we present a fabrication method of a flexible graphene transistor with a bottom-gate coplanar structure on a Parylene C substrate. Also, a current annealing method and its effect on the device performance have been studied. The localized heat generated by the current annealing method improves the drain current, which is attributed to the decreased contact resistance between graphene and S/D electrodes. A maximum current annealing power in the Parylene C-based graphene transistor has been extracted to provide a guideline for an appropriate current annealing. The fabricated flexible graphene transistor shows a field-effect mobility, maximum transconductance, and a Ion/Ioff ratio of 533.5 cm2/V s, 58.1 μS, and 1.76, respectively. The low temperature process and the current annealing method presented here would be useful to fabricate two-dimensional materials-based flexible electronics. PMID:27795570

Design consideration of δ-doping channels for high-performance n + - GaAs / p + -InGaP/n-GaAs camel-gate field effect transistors

NASA Astrophysics Data System (ADS)

Tsai, Jung-Hui; Chen, Jeng-Shyan; Chu, Yu-Jui

2005-01-01

The influence of δ-doping channels on the performance of n +-GaAs/p +-InGaP/n-GaAs camel-gate field effect transistors is investigated by theoretical analysis and experimental results. The depleted pn junction of the camel gate and the existence of considerable conduction band discontinuity at the InGaP/GaAs heterojunction enhance the potential barrier height and the forward gate voltage. As the concentration-thickness products of the n-GaAs layer and δ-doping layer are fixed, the higher δ-doping device exhibits a higher potential barrier height, a larger drain current, and a broader gate voltage swing, whereas the transconductance is somewhat lower. For a n +=5.5×10 12 cm -2δ-doping device, the experimental result exhibits a maximum transconductance of 240 mS/mm and a gate voltage swing of 3.5 V. Consequently, the studied devices provide a good potential for large signal and linear circuit applications.

Low-voltage organic transistors on plastic comprising high-dielectric constant gate insulators

PubMed

Dimitrakopoulos; Purushothaman; Kymissis; Callegari; Shaw

1999-02-05

The gate bias dependence of the field-effect mobility in pentacene-based insulated gate field-effect transistors (IGFETs) was interpreted on the basis of the interaction of charge carriers with localized trap levels in the band gap. This understanding was used to design and fabricate IGFETs with mobility of more than 0.3 square centimeter per volt per second and current modulation of 10(5), with the use of amorphous metal oxide gate insulators. These values were obtained at operating voltage ranges as low as 5 volts, which are much smaller than previously reported results. An all-room-temperature fabrication process sequence was used, which enabled the demonstration of high-performance organic IGFETs on transparent plastic substrates, at low operating voltages for organic devices.

Polycrystalline silicon ion sensitive field effect transistors

NASA Astrophysics Data System (ADS)

Yan, F.; Estrela, P.; Mo, Y.; Migliorato, P.; Maeda, H.; Inoue, S.; Shimoda, T.

2005-01-01

We report the operation of polycrystalline silicon ion sensitive field effect transistors. These devices can be fabricated on inexpensive disposable substrates such as glass or plastics and are, therefore, promising candidates for low cost single-use intelligent multisensors. In this work we have developed an extended gate structure with a Si3N4 sensing layer. Nearly ideal pH sensitivity (54mV /pH) and stable operation have been achieved. Temperature effects have been characterized. A penicillin sensor has been fabricated by functionalizing the sensing area with penicillinase. The sensitivity to penicillin G is about 10mV/mM, in solutions with concentration lower than the saturation value, which is about 7 mM.

Ferroelectric properties of YMnO3 epitaxial films for ferroelectric-gate field-effect transistors

NASA Astrophysics Data System (ADS)

Ito, Daisuke; Fujimura, Norifumi; Yoshimura, Takeshi; Ito, Taichiro

2003-05-01

Ferroelectric properties of YMnO3 epitaxial films were studied. The ferroelectric properties of epitaxially grown (0001) YMnO3 films on (111)Pt/(0001)sapphire (epi-YMO/Pt) with an excellent crystallinity were compared to (0001)-oriented poly crystalline films on (111)Pt/ZrO2/SiO2/Si. The epi-YMO/Pt had saturated polarization-electric-field (P-E) hysteresis loops, with a remanent polarization (Pr) of 1.7 μC/cm2 and a coercive field (Ec) of 80 kV/cm. The fatigue property showed no degradation up to 1010 measured cycles. These results suggested that the YMnO3 epitaxial films were suitable ferroelectric material for the ferroelectric-gate field-effect transistors. Consequently, epitaxially grown (0001)YMnO3 films on epitaxial Y2O3/Si (epi-YMO/Si) were fabricated. The epi-YMO/Si capacitor had almost equivalent crystallinity compared to epi-YMO/Pt. It was recognized that the epi-YMO/Si capacitor exhibited the ferroelectric type C-V hysteresis loop with the width of the memory window of 4.8 V, which was almost identical to the value of twice coercive voltage of the P-E hysteresis loops of the epi-YMO/Pt. A retention time exceeding 104 s was obtained in the epi-YMO/Si capacitor.

Highly sensitive glucose sensors based on enzyme-modified whole-graphene solution-gated transistors

NASA Astrophysics Data System (ADS)

Zhang, Meng; Liao, Caizhi; Mak, Chun Hin; You, Peng; Mak, Chee Leung; Yan, Feng

2015-02-01

Noninvasive glucose detections are convenient techniques for the diagnosis of diabetes mellitus, which require high performance glucose sensors. However, conventional electrochemical glucose sensors are not sensitive enough for these applications. Here, highly sensitive glucose sensors are successfully realized based on whole-graphene solution-gated transistors with the graphene gate electrodes modified with an enzyme glucose oxidase. The sensitivity of the devices is dramatically improved by co-modifying the graphene gates with Pt nanoparticles due to the enhanced electrocatalytic activity of the electrodes. The sensing mechanism is attributed to the reaction of H2O2 generated by the oxidation of glucose near the gate. The optimized glucose sensors show the detection limits down to 0.5 μM and good selectivity, which are sensitive enough for non-invasive glucose detections in body fluids. The devices show the transconductances two orders of magnitude higher than that of a conventional silicon field effect transistor, which is the main reason for their high sensitivity. Moreover, the devices can be conveniently fabricated with low cost. Therefore, the whole-graphene solution-gated transistors are a high-performance sensing platform for not only glucose detections but also many other types of biosensors that may find practical applications in the near future.

Highly sensitive glucose sensors based on enzyme-modified whole-graphene solution-gated transistors

PubMed Central

Zhang, Meng; Liao, Caizhi; Mak, Chun Hin; You, Peng; Mak, Chee Leung; Yan, Feng

2015-01-01

Noninvasive glucose detections are convenient techniques for the diagnosis of diabetes mellitus, which require high performance glucose sensors. However, conventional electrochemical glucose sensors are not sensitive enough for these applications. Here, highly sensitive glucose sensors are successfully realized based on whole-graphene solution-gated transistors with the graphene gate electrodes modified with an enzyme glucose oxidase. The sensitivity of the devices is dramatically improved by co-modifying the graphene gates with Pt nanoparticles due to the enhanced electrocatalytic activity of the electrodes. The sensing mechanism is attributed to the reaction of H2O2 generated by the oxidation of glucose near the gate. The optimized glucose sensors show the detection limits down to 0.5 μM and good selectivity, which are sensitive enough for non-invasive glucose detections in body fluids. The devices show the transconductances two orders of magnitude higher than that of a conventional silicon field effect transistor, which is the main reason for their high sensitivity. Moreover, the devices can be conveniently fabricated with low cost. Therefore, the whole-graphene solution-gated transistors are a high-performance sensing platform for not only glucose detections but also many other types of biosensors that may find practical applications in the near future. PMID:25655666

High-sensitivity pH sensor using separative extended-gate field-effect transistors with single-walled carbon-nanotube networks

NASA Astrophysics Data System (ADS)

Pyo, Ju-Young; Cho, Won-Ju

2018-04-01

We fabricate high-sensitivity pH sensors using single-walled carbon-nanotube (SWCNT) network thin-film transistors (TFTs). The sensing and transducer parts of the pH sensor are composed of separative extended-sensing gates (ESGs) with SnO2 ion-sensitive membranes and double-gate structure TFTs with thin SWCNT network channels of ∼1 nm and AlO x top-gate insulators formed by the solution-deposition method. To prevent thermal process-induced damages on the SWCNT channel layer due to the post-deposition annealing process and improve the electrical characteristics of the SWCNT-TFTs, microwave irradiation is applied at low temperatures. As a result, a pH sensitivity of 7.6 V/pH, far beyond the Nernst limit, is obtained owing to the capacitive coupling effect between the top- and bottom-gate insulators of the SWCNT-TFTs. Therefore, double-gate structure SWCNT-TFTs with separated ESGs are expected to be highly beneficial for high-sensitivity disposable biosensor applications.

Controllable Hysteresis and Threshold Voltage of Single-Walled Carbon Nano-tube Transistors with Ferroelectric Polymer Top-Gate Insulators

PubMed Central

Sun, Yi-Lin; Xie, Dan; Xu, Jian-Long; Zhang, Cheng; Dai, Rui-Xuan; Li, Xian; Meng, Xiang-Jian; Zhu, Hong-Wei

2016-01-01

Double-gated field effect transistors have been fabricated using the SWCNT networks as channel layer and the organic ferroelectric P(VDF-TrFE) film spin-coated as top gate insulators. Standard photolithography process has been adopted to achieve the patterning of organic P(VDF-TrFE) films and top-gate electrodes, which is compatible with conventional CMOS process technology. An effective way for modulating the threshold voltage in the channel of P(VDF-TrFE) top-gate transistors under polarization has been reported. The introduction of functional P(VDF-TrFE) gate dielectric also provides us an alternative method to suppress the initial hysteresis of SWCNT networks and obtain a controllable ferroelectric hysteresis behavior. Applied bottom gate voltage has been found to be another effective way to highly control the threshold voltage of the networked SWCNTs based FETs by electrostatic doping effect. PMID:26980284

Large current modulation and tunneling magnetoresistance change by a side-gate electric field in a GaMnAs-based vertical spin metal-oxide-semiconductor field-effect transistor.

PubMed

Kanaki, Toshiki; Yamasaki, Hiroki; Koyama, Tomohiro; Chiba, Daichi; Ohya, Shinobu; Tanaka, Masaaki

2018-05-08

A vertical spin metal-oxide-semiconductor field-effect transistor (spin MOSFET) is a promising low-power device for the post scaling era. Here, using a ferromagnetic-semiconductor GaMnAs-based vertical spin MOSFET with a GaAs channel layer, we demonstrate a large drain-source current I DS modulation by a gate-source voltage V GS with a modulation ratio up to 130%, which is the largest value that has ever been reported for vertical spin field-effect transistors thus far. We find that the electric field effect on indirect tunneling via defect states in the GaAs channel layer is responsible for the large I DS modulation. This device shows a tunneling magnetoresistance (TMR) ratio up to ~7%, which is larger than that of the planar-type spin MOSFETs, indicating that I DS can be controlled by the magnetization configuration. Furthermore, we find that the TMR ratio can be modulated by V GS . This result mainly originates from the electric field modulation of the magnetic anisotropy of the GaMnAs ferromagnetic electrodes as well as the potential modulation of the nonmagnetic semiconductor GaAs channel layer. Our findings provide important progress towards high-performance vertical spin MOSFETs.

Origin of low-frequency noise in pentacene field-effect transistors

NASA Astrophysics Data System (ADS)

Xu, Yong; Minari, Takeo; Tsukagoshi, Kazuhito; Chroboczek, Jan; Balestra, Francis; Ghibaudo, Gerard

2011-07-01

Measurements of power spectral density (PSD) of low-frequency noise (LFN) in pentacene field-effect transistors reveal the preponderance of a 1/ f-type PSD behavior with the amplitude varying as the squared transistor gain and increasing as the inverse of the gate surface area. Such features impose an interpretation of LFN by carrier number fluctuations model involving capture/release of charges on traps uniformly distributed over the gate surface. The surface slow trap density extracted by the noise analysis is close to the surface states density deduced independently from static I(V) data, which confirms the validity of the proposed LFN interpretation. Further, we found that the trap densities in bottom-contact (BC) devices were higher than in their top-contact (TC) counterparts, in agreement with observations of a poorer crystal structure of BC devices, in the contact regions in particular. At the highest bias the noise originating from the contact resistance is also shown to be a dominant component in the PSD, and it is well explained by the noise originating from a gate-voltage dependent contact resistance. A gate area scaling was also performed, and the good scaling and the dispersion at the highest bias confirm the validity of the applied carrier number fluctuations model and the predominant contact noise at high current intensities.

Analysis of electric field distribution in GaAs metal-semiconductor field effect transistor with a field-modulating plate

NASA Astrophysics Data System (ADS)

Hori, Yasuko; Kuzuhara, Masaaki; Ando, Yuji; Mizuta, Masashi

2000-04-01

Electric field distribution in the channel of a field effect transistor (FET) with a field-modulating plate (FP) has been theoretically investigated using a two-dimensional ensemble Monte Carlo simulation. This analysis revealed that the introduction of FP is effective in canceling the influence of surface traps under forward bias conditions and in reducing the electric field intensity at the drain side of the gate edge under pinch-off bias conditions. This study also found that a partial overlap of the high-field region under the gate and that at the FP electrode is important for reducing the electric field intensity. The optimized metal-semiconductor FET with FP (FPFET) (LGF˜0.2 μm) exhibited a much lower peak electric field intensity than a conventional metal-semiconductor FET. Based on these numerically calculated results, we have proposed a design procedure to optimize the power FPFET structure with extremely high breakdown voltages while maintaining reasonable gain performance.

Integrating Partial Polarization into a Metal-Ferroelectric-Semiconductor Field Effect Transistor Model

NASA Technical Reports Server (NTRS)

MacLeod, Todd C.; Ho, Fat Duen

1999-01-01

The ferroelectric channel in a Metal-Ferroelectric-Semiconductor Field Effect Transistor (MFSFET) can partially change its polarization when the gate voltage near the polarization threshold voltage. This causes the MFSFET Drain current to change with repeated pulses of the same gate voltage near the polarization threshold voltage. A previously developed model [11, based on the Fermi-Dirac function, assumed that for a given gate voltage and channel polarization, a sin-le Drain current value would be generated. A study has been done to characterize the effects of partial polarization on the Drain current of a MFSFET. These effects have been described mathematically and these equations have been incorporated into a more comprehensive mathematical model of the MFSFET. The model takes into account the hysteresis nature of the MFSFET and the time dependent decay as well as the effects of partial polarization. This model defines the Drain current based on calculating the degree of polarization from previous gate pulses, the present Gate voltage, and the amount of time since the last Gate volta-e pulse.

Sensing properties of separative paper-based extended-gate ion-sensitive field-effect transistor for cost effective pH sensor applications

NASA Astrophysics Data System (ADS)

Cho, Won-Ju; Lim, Cheol-Min

2018-02-01

In this study, we developed a cost-effective ion-sensing field-effect transistor (FET) with an extended gate (EG) fabricated on a separative paper substrate. The pH sensing characteristics of the paper EG was compared with those of other EGs fabricated on silicon, glass, or polyimide substrates. The fabricated paper-based EGFET exhibited excellent sensitivity close to the Nernst response limit as well as to that of the other substrate-based EGFETs. In addition, we found that all EGFETs, regardless of the substrate, have similar non-ideal behavior, i.e., drift phenomenon and hysteresis width. To investigate the degradation and durability of the paper EG after prolonged use, aging-effect tests were carried out in terms of the hysteresis width and sensitivity over a course of 30 days. As a result, the paper EG maintained stable pH sensing characteristics after 30 days. Therefore, we expect that paper EGFETs can provide a cost-effective sensor platform.

Electronic Model of a Ferroelectric Field Effect Transistor

NASA Technical Reports Server (NTRS)

MacLeod, Todd C.; Ho, Fat Duen; Russell, Larry (Technical Monitor)

2001-01-01

A pair of electronic models has been developed of a Ferroelectric Field Effect transistor. These models can be used in standard electrical circuit simulation programs to simulate the main characteristics of the FFET. The models use the Schmitt trigger circuit as a basis for their design. One model uses bipolar junction transistors and one uses MOSFET's. Each model has the main characteristics of the FFET, which are the current hysterisis with different gate voltages and decay of the drain current when the gate voltage is off. The drain current from each model has similar values to an actual FFET that was measured experimentally. T'he input and o Output resistance in the models are also similar to that of the FFET. The models are valid for all frequencies below RF levels. No attempt was made to model the high frequency characteristics of the FFET. Each model can be used to design circuits using FFET's with standard electrical simulation packages. These circuits can be used in designing non-volatile memory circuits and logic circuits and is compatible with all SPICE based circuit analysis programs. The models consist of only standard electrical components, such as BJT's, MOSFET's, diodes, resistors, and capacitors. Each model is compared to the experimental data measured from an actual FFET.

Gas Sensors Based on Semiconducting Nanowire Field-Effect Transistors

PubMed Central

Feng, Ping; Shao, Feng; Shi, Yi; Wan, Qing

2014-01-01

One-dimensional semiconductor nanostructures are unique sensing materials for the fabrication of gas sensors. In this article, gas sensors based on semiconducting nanowire field-effect transistors (FETs) are comprehensively reviewed. Individual nanowires or nanowire network films are usually used as the active detecting channels. In these sensors, a third electrode, which serves as the gate, is used to tune the carrier concentration of the nanowires to realize better sensing performance, including sensitivity, selectivity and response time, etc. The FET parameters can be modulated by the presence of the target gases and their change relate closely to the type and concentration of the gas molecules. In addition, extra controls such as metal decoration, local heating and light irradiation can be combined with the gate electrode to tune the nanowire channel and realize more effective gas sensing. With the help of micro-fabrication techniques, these sensors can be integrated into smart systems. Finally, some challenges for the future investigation and application of nanowire field-effect gas sensors are discussed. PMID:25232915

Dual origin of room temperature sub-terahertz photoresponse in graphene field effect transistors

NASA Astrophysics Data System (ADS)

Bandurin, D. A.; Gayduchenko, I.; Cao, Y.; Moskotin, M.; Principi, A.; Grigorieva, I. V.; Goltsman, G.; Fedorov, G.; Svintsov, D.

2018-04-01

Graphene is considered as a promising platform for detectors of high-frequency radiation up to the terahertz (THz) range due to its superior electron mobility. Previously, it has been shown that graphene field effect transistors (FETs) exhibit room temperature broadband photoresponse to incoming THz radiation, thanks to the thermoelectric and/or plasma wave rectification. Both effects exhibit similar functional dependences on the gate voltage, and therefore, it was difficult to disentangle these contributions in previous studies. In this letter, we report on combined experimental and theoretical studies of sub-THz response in graphene field-effect transistors analyzed at different temperatures. This temperature-dependent study allowed us to reveal the role of the photo-thermoelectric effect, p-n junction rectification, and plasmonic rectification in the sub-THz photoresponse of graphene FETs.

Photolithographically Patterned TiO2 Films for Electrolyte-Gated Transistors.

PubMed

Valitova, Irina; Kumar, Prajwal; Meng, Xiang; Soavi, Francesca; Santato, Clara; Cicoira, Fabio

2016-06-15

Metal oxides constitute a class of materials whose properties cover the entire range from insulators to semiconductors to metals. Most metal oxides are abundant and accessible at moderate cost. Metal oxides are widely investigated as channel materials in transistors, including electrolyte-gated transistors, where the charge carrier density can be modulated by orders of magnitude upon application of relatively low electrical bias (2 V). Electrolyte gating offers the opportunity to envisage new applications in flexible and printed electronics as well as to improve our current understanding of fundamental processes in electronic materials, e.g. insulator/metal transitions. In this work, we employ photolithographically patterned TiO2 films as channels for electrolyte-gated transistors. TiO2 stands out for its biocompatibility and wide use in sensing, electrochromics, photovoltaics and photocatalysis. We fabricated TiO2 electrolyte-gated transistors using an original unconventional parylene-based patterning technique. By using a combination of electrochemical and charge carrier transport measurements we demonstrated that patterning improves the performance of electrolyte-gated TiO2 transistors with respect to their unpatterned counterparts. Patterned electrolyte-gated (EG) TiO2 transistors show threshold voltages of about 0.9 V, ON/OFF ratios as high as 1 × 10(5), and electron mobility above 1 cm(2)/(V s).

Large-current-controllable carbon nanotube field-effect transistor in electrolyte solution

NASA Astrophysics Data System (ADS)

Myodo, Miho; Inaba, Masafumi; Ohara, Kazuyoshi; Kato, Ryogo; Kobayashi, Mikinori; Hirano, Yu; Suzuki, Kazuma; Kawarada, Hiroshi

2015-05-01

Large-current-controllable carbon nanotube field-effect transistors (CNT-FETs) were fabricated with mm-long CNT sheets. The sheets, synthesized by remote-plasma-enhanced CVD, contained both single- and double-walled CNTs. Titanium was deposited on the sheet as source and drain electrodes, and an electrolyte solution was used as a gate electrode (solution gate) to apply a gate voltage to the CNTs through electric double layers formed around the CNTs. The drain current came to be well modulated as electrolyte solution penetrated into the sheets, and one of the solution gate CNT-FETs was able to control a large current of over 2.5 A. In addition, we determined the transconductance parameter per tube and compared it with values for other CNT-FETs. The potential of CNT sheets for applications requiring the control of large current is exhibited in this study.

Computational study of graphene-based vertical field effect transistor

NASA Astrophysics Data System (ADS)

Chen, Wenchao; Rinzler, Andrew; Guo, Jing

2013-03-01

Poisson and drift-diffusion equations are solved in a three-dimensional device structure to simulate graphene-based vertical field effect transistors (GVFETs). Operation mechanisms of the GVFET with and without punched holes in the graphene source contact are presented and compared. The graphene-channel Schottky barrier can be modulated by gate electric field due to graphene's low density of states. For the graphene contact with punched holes, the contact barrier thinning and lowering around punched hole edge allow orders of magnitude higher tunneling current compared to the region away from the punched hole edge, which is responsible for significant performance improvement as already verified by experiments. Small hole size is preferred due to less electrostatic screening from channel inversion layer, which gives large electric field around the punched hole edge, thus, leading to a thinner and lower barrier. Bilayer and trilayer graphenes as the source contact degrade the performance improvement because stronger electrostatic screening leads to smaller contact barrier lowering and thinning. High punched hole area percentage improves current performance by allowing more gate electric field to modulate the graphene-channel barrier. Low effective mass channel material gives better on-off current ratio.

Water-gel for gating graphene transistors.

PubMed

Kim, Beom Joon; Um, Soong Ho; Song, Woo Chul; Kim, Yong Ho; Kang, Moon Sung; Cho, Jeong Ho

2014-05-14

Water, the primary electrolyte in biology, attracts significant interest as an electrolyte-type dielectric material for transistors compatible with biological systems. Unfortunately, the fluidic nature and low ionic conductivity of water prevents its practical usage in such applications. Here, we describe the development of a solid state, megahertz-operating, water-based gate dielectric system for operating graphene transistors. The new electrolyte systems were prepared by dissolving metal-substituted DNA polyelectrolytes into water. The addition of these biocompatible polyelectrolytes induced hydrogelation to provide solid-state integrity to the system. They also enhanced the ionic conductivities of the electrolytes, which in turn led to the quick formation of an electric double layer at the graphene/electrolyte interface that is beneficial for modulating currents in graphene transistors at high frequencies. At the optimized conditions, the Na-DNA water-gel-gated flexible transistors and inverters were operated at frequencies above 1 MHz and 100 kHz, respectively.

Biologically sensitive field-effect transistors: from ISFETs to NanoFETs.

PubMed

Pachauri, Vivek; Ingebrandt, Sven

2016-06-30

Biologically sensitive field-effect transistors (BioFETs) are one of the most abundant classes of electronic sensors for biomolecular detection. Most of the time these sensors are realized as classical ion-sensitive field-effect transistors (ISFETs) having non-metallized gate dielectrics facing an electrolyte solution. In ISFETs, a semiconductor material is used as the active transducer element covered by a gate dielectric layer which is electronically sensitive to the (bio-)chemical changes that occur on its surface. This review will provide a brief overview of the history of ISFET biosensors with general operation concepts and sensing mechanisms. We also discuss silicon nanowire-based ISFETs (SiNW FETs) as the modern nanoscale version of classical ISFETs, as well as strategies to functionalize them with biologically sensitive layers. We include in our discussion other ISFET types based on nanomaterials such as carbon nanotubes, metal oxides and so on. The latest examples of highly sensitive label-free detection of deoxyribonucleic acid (DNA) molecules using SiNW FETs and single-cell recordings for drug screening and other applications of ISFETs will be highlighted. Finally, we suggest new device platforms and newly developed, miniaturized read-out tools with multichannel potentiometric and impedimetric measurement capabilities for future biomedical applications. © 2016 The Author(s). Published by Portland Press Limited on behalf of the Biochemical Society.

Semiconductor to metallic transition in bulk accumulated amorphous indium-gallium-zinc-oxide dual gate thin-film transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chun, Minkyu; Chowdhury, Md Delwar Hossain; Jang, Jin, E-mail: jjang@khu.ac.kr

We investigated the effects of top gate voltage (V{sub TG}) and temperature (in the range of 25 to 70 {sup o}C) on dual-gate (DG) back-channel-etched (BCE) amorphous-indium-gallium-zinc-oxide (a-IGZO) thin film transistors (TFTs) characteristics. The increment of V{sub TG} from -20V to +20V, decreases the threshold voltage (V{sub TH}) from 19.6V to 3.8V and increases the electron density to 8.8 x 10{sup 18}cm{sup −3}. Temperature dependent field-effect mobility in saturation regime, extracted from bottom gate sweep, show a critical dependency on V{sub TG}. At V{sub TG} of 20V, the mobility decreases from 19.1 to 15.4 cm{sup 2}/V ⋅ s with increasingmore » temperature, showing a metallic conduction. On the other hand, at V{sub TG} of - 20V, the mobility increases from 6.4 to 7.5cm{sup 2}/V ⋅ s with increasing temperature. Since the top gate bias controls the position of Fermi level, the temperature dependent mobility shows metallic conduction when the Fermi level is above the conduction band edge, by applying high positive bias to the top gate.« less

High performing solution-coated electrolyte-gated organic field-effect transistors for aqueous media operation.

PubMed

Zhang, Qiaoming; Leonardi, Francesca; Casalini, Stefano; Temiño, Inés; Mas-Torrent, Marta

2016-12-22

Since the first demonstration, the electrolyte-gated organic field-effect transistors (EGOFETs) have immediately gained much attention for the development of cutting-edge technology and they are expected to have a strong impact in the field of (bio-)sensors. However EGOFETs directly expose their active material towards the aqueous media, hence a limited library of organic semiconductors is actually suitable. By using two mostly unexplored strategies in EGOFETs such as blended materials together with a printing technique, we have successfully widened this library. Our benchmarks were 6,13-bis(triisopropylsilylethynyl)pentacene and 2,8-difluoro-5,11-bis(triethylsilylethynyl)anthradithiophene (diF-TES-ADT), which have been firstly blended with polystyrene and secondly deposited by means of the bar-assisted meniscus shearing (BAMS) technique. Our approach yielded thin films (i.e. no thicker than 30 nm) suitable for organic electronics and stable in liquid environment. Up to date, these EGOFETs show unprecedented performances. Furthermore, an extremely harsh environment, like NaCl 1M, has been used in order to test the limit of operability of these electronic devices. Albeit an electrical worsening is observed, our devices can operate under different electrical stresses within the time frame of hours up to a week. In conclusion, our approach turns out to be a powerful tool for the EGOFET manufacturing.

High performing solution-coated electrolyte-gated organic field-effect transistors for aqueous media operation

NASA Astrophysics Data System (ADS)

Zhang, Qiaoming; Leonardi, Francesca; Casalini, Stefano; Temiño, Inés; Mas-Torrent, Marta

2016-12-01

Since the first demonstration, the electrolyte-gated organic field-effect transistors (EGOFETs) have immediately gained much attention for the development of cutting-edge technology and they are expected to have a strong impact in the field of (bio-)sensors. However EGOFETs directly expose their active material towards the aqueous media, hence a limited library of organic semiconductors is actually suitable. By using two mostly unexplored strategies in EGOFETs such as blended materials together with a printing technique, we have successfully widened this library. Our benchmarks were 6,13-bis(triisopropylsilylethynyl)pentacene and 2,8-difluoro-5,11-bis(triethylsilylethynyl)anthradithiophene (diF-TES-ADT), which have been firstly blended with polystyrene and secondly deposited by means of the bar-assisted meniscus shearing (BAMS) technique. Our approach yielded thin films (i.e. no thicker than 30 nm) suitable for organic electronics and stable in liquid environment. Up to date, these EGOFETs show unprecedented performances. Furthermore, an extremely harsh environment, like NaCl 1M, has been used in order to test the limit of operability of these electronic devices. Albeit an electrical worsening is observed, our devices can operate under different electrical stresses within the time frame of hours up to a week. In conclusion, our approach turns out to be a powerful tool for the EGOFET manufacturing.

High performing solution-coated electrolyte-gated organic field-effect transistors for aqueous media operation

PubMed Central

Zhang, Qiaoming; Leonardi, Francesca; Casalini, Stefano; Temiño, Inés; Mas-Torrent, Marta

2016-01-01

Since the first demonstration, the electrolyte-gated organic field-effect transistors (EGOFETs) have immediately gained much attention for the development of cutting-edge technology and they are expected to have a strong impact in the field of (bio-)sensors. However EGOFETs directly expose their active material towards the aqueous media, hence a limited library of organic semiconductors is actually suitable. By using two mostly unexplored strategies in EGOFETs such as blended materials together with a printing technique, we have successfully widened this library. Our benchmarks were 6,13-bis(triisopropylsilylethynyl)pentacene and 2,8-difluoro-5,11-bis(triethylsilylethynyl)anthradithiophene (diF-TES-ADT), which have been firstly blended with polystyrene and secondly deposited by means of the bar-assisted meniscus shearing (BAMS) technique. Our approach yielded thin films (i.e. no thicker than 30 nm) suitable for organic electronics and stable in liquid environment. Up to date, these EGOFETs show unprecedented performances. Furthermore, an extremely harsh environment, like NaCl 1M, has been used in order to test the limit of operability of these electronic devices. Albeit an electrical worsening is observed, our devices can operate under different electrical stresses within the time frame of hours up to a week. In conclusion, our approach turns out to be a powerful tool for the EGOFET manufacturing. PMID:28004824

Multi-Layer SnSe Nanoflake Field-Effect Transistors with Low-Resistance Au Ohmic Contacts

NASA Astrophysics Data System (ADS)

Cho, Sang-Hyeok; Cho, Kwanghee; Park, No-Won; Park, Soonyong; Koh, Jung-Hyuk; Lee, Sang-Kwon

2017-05-01

We report p-type tin monoselenide (SnSe) single crystals, grown in double-sealed quartz ampoules using a modified Bridgman technique at 920 °C. X-ray powder diffraction (XRD) and energy dispersive X-ray spectroscopy (EDX) measurements clearly confirm that the grown SnSe consists of single-crystal SnSe. Electrical transport of multi-layer SnSe nanoflakes, which were prepared by exfoliation from bulk single crystals, was conducted using back-gated field-effect transistor (FET) structures with Au and Ti contacts on SiO2/Si substrates, revealing that multi-layer SnSe nanoflakes exhibit p-type semiconductor characteristics owing to the Sn vacancies on the surfaces of SnSe nanoflakes. In addition, a strong carrier screening effect was observed in 70-90-nm-thick SnSe nanoflake FETs. Furthermore, the effect of the metal contacts to multi-layer SnSe nanoflake-based FETs is also discussed with two different metals, such as Ti/Au and Au contacts.

AlN metal-semiconductor field-effect transistors using Si-ion implantation

NASA Astrophysics Data System (ADS)

Okumura, Hironori; Suihkonen, Sami; Lemettinen, Jori; Uedono, Akira; Zhang, Yuhao; Piedra, Daniel; Palacios, Tomás

2018-04-01

We report on the electrical characterization of Si-ion implanted AlN layers and the first demonstration of metal-semiconductor field-effect transistors (MESFETs) with an ion-implanted AlN channel. The ion-implanted AlN layers with Si dose of 5 × 1014 cm-2 exhibit n-type characteristics after thermal annealing at 1230 °C. The ion-implanted AlN MESFETs provide good drain current saturation and stable pinch-off operation even at 250 °C. The off-state breakdown voltage is 2370 V for drain-to-gate spacing of 25 µm. These results show the great potential of AlN-channel transistors for high-temperature and high-power applications.

Complementary junction heterostructure field-effect transistor

DOEpatents

Baca, Albert G.; Drummond, Timothy J.; Robertson, Perry J.; Zipperian, Thomas E.

1995-01-01

A complimentary pair of compound semiconductor junction heterostructure field-effect transistors and a method for their manufacture are disclosed. The p-channel junction heterostructure field-effect transistor uses a strained layer to split the degeneracy of the valence band for a greatly improved hole mobility and speed. The n-channel device is formed by a compatible process after removing the strained layer. In this manner, both types of transistors may be independently optimized. Ion implantation is used to form the transistor active and isolation regions for both types of complimentary devices. The invention has uses for the development of low power, high-speed digital integrated circuits.

Complementary junction heterostructure field-effect transistor

DOEpatents

Baca, A.G.; Drummond, T.J.; Robertson, P.J.; Zipperian, T.E.

1995-12-26

A complimentary pair of compound semiconductor junction heterostructure field-effect transistors and a method for their manufacture are disclosed. The p-channel junction heterostructure field-effect transistor uses a strained layer to split the degeneracy of the valence band for a greatly improved hole mobility and speed. The n-channel device is formed by a compatible process after removing the strained layer. In this manner, both types of transistors may be independently optimized. Ion implantation is used to form the transistor active and isolation regions for both types of complimentary devices. The invention has uses for the development of low power, high-speed digital integrated circuits. 10 figs.

The fundamental downscaling limit of field effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mamaluy, Denis, E-mail: mamaluy@sandia.gov; Gao, Xujiao

2015-05-11

We predict that within next 15 years a fundamental down-scaling limit for CMOS technology and other Field-Effect Transistors (FETs) will be reached. Specifically, we show that at room temperatures all FETs, irrespective of their channel material, will start experiencing unacceptable level of thermally induced errors around 5-nm gate lengths. These findings were confirmed by performing quantum mechanical transport simulations for a variety of 6-, 5-, and 4-nm gate length Si devices, optimized to satisfy high-performance logic specifications by ITRS. Different channel materials and wafer/channel orientations have also been studied; it is found that altering channel-source-drain materials achieves only insignificant increasemore » in switching energy, which overall cannot sufficiently delay the approaching downscaling limit. Alternative possibilities are discussed to continue the increase of logic element densities for room temperature operation below the said limit.« less

The fundamental downscaling limit of field effect transistors

DOE PAGES

Mamaluy, Denis; Gao, Xujiao

2015-05-12

We predict that within next 15 years a fundamental down-scaling limit for CMOS technology and other Field-Effect Transistors (FETs) will be reached. Specifically, we show that at room temperatures all FETs, irrespective of their channel material, will start experiencing unacceptable level of thermally induced errors around 5-nm gate lengths. These findings were confirmed by performing quantum mechanical transport simulations for a variety of 6-, 5-, and 4-nm gate length Si devices, optimized to satisfy high-performance logic specifications by ITRS. Different channel materials and wafer/channel orientations have also been studied; it is found that altering channel-source-drain materials achieves only insignificant increasemore » in switching energy, which overall cannot sufficiently delay the approaching downscaling limit. Alternative possibilities are discussed to continue the increase of logic element densities for room temperature operation below the said limit.« less

Evaluation of Anisotropic Biaxial Stress Induced Around Trench Gate of Si Power Transistor Using Water-Immersion Raman Spectroscopy

NASA Astrophysics Data System (ADS)

Suzuki, Takahiro; Yokogawa, Ryo; Oasa, Kohei; Nishiwaki, Tatsuya; Hamamoto, Takeshi; Ogura, Atsushi

2018-05-01

The trench gate structure is one of the promising techniques to reduce on-state resistance (R on) for silicon power devices, such as insulated gate bipolar transistors and power metal-oxide-semiconductor field-effect transistors. In addition, it has been reported that stress is induced around the trench gate area, modifying the carrier mobilities. We evaluated the one-dimensional distribution and anisotropic biaxial stress by quasi-line excitation and water-immersion Raman spectroscopy, respectively. The results clearly confirmed anisotropic biaxial stress in state-of-the-art silicon power devices. It is theoretically possible to estimate carrier mobility using piezoresistance coefficients and anisotropic biaxial stress. The electron mobility was increased while the hole mobility was decreased or remained almost unchanged in the silicon (Si) power device. The stress significantly modifies the R on of silicon power transistors. Therefore, their performance can be improved using the stress around the trench gate.

A computational study of a novel graphene nanoribbon field effect transistor

NASA Astrophysics Data System (ADS)

Ghoreishi, Seyed Saleh; Yousefi, Reza

2017-04-01

In this paper, using gate structure engineering and modification of channel dopant profile, we propose a new double gate graphene nanoribbon field effect transistor (DG-GNRFET) mainly to suppress the band-to-band tunneling (BTBT) of carriers. In the new device, the intrinsic part of the channel is replaced by an intrinsic-lightly doped-intrinsic (I -N--I) configuration in a way that only the intrinsic parts are covered by the gate contact. Transport characteristics of the device are investigated theoretically using the nonequilibrium Green’s function (NEGF) formalism. Numerical simulations show that off-current, ambipolar behavior, on/off-current ratio and the switching characteristics such as intrinsic delay and power-delay product are improved. In addition, the new device demonstrates better sub-threshold swing and less drain-induced barrier lowering (DIBL).

Two dimensional analytical model for a reconfigurable field effect transistor

NASA Astrophysics Data System (ADS)

Ranjith, R.; Jayachandran, Remya; Suja, K. J.; Komaragiri, Rama S.

2018-02-01

This paper presents two-dimensional potential and current models for a reconfigurable field effect transistor (RFET). Two potential models which describe subthreshold and above-threshold channel potentials are developed by solving two-dimensional (2D) Poisson's equation. In the first potential model, 2D Poisson's equation is solved by considering constant/zero charge density in the channel region of the device to get the subthreshold potential characteristics. In the second model, accumulation charge density is considered to get above-threshold potential characteristics of the device. The proposed models are applicable for the device having lightly doped or intrinsic channel. While obtaining the mathematical model, whole body area is divided into two regions: gated region and un-gated region. The analytical models are compared with technology computer-aided design (TCAD) simulation results and are in complete agreement for different lengths of the gated regions as well as at various supply voltage levels.

Effect of dielectric layers on device stability of pentacene-based field-effect transistors.

PubMed

Di, Chong-an; Yu, Gui; Liu, Yunqi; Guo, Yunlong; Sun, Xiangnan; Zheng, Jian; Wen, Yugeng; Wang, Ying; Wu, Weiping; Zhu, Daoben

2009-09-07

We report stable organic field-effect transistors (OFETs) based on pentacene. It was found that device stability strongly depends on the dielectric layer. Pentacene thin-film transistors based on the bare or polystyrene-modified SiO(2) gate dielectrics exhibit excellent electrical stabilities. In contrast, the devices with the octadecyltrichlorosilane (OTS)-treated SiO(2) dielectric layer showed the worst stabilities. The effects of the different dielectrics on the device stabilities were investigated. We found that the surface energy of the gate dielectric plays a crucial role in determining the stability of the pentacene thin film, device performance and degradation of electrical properties. Pentacene aggregation, phase transfer and film morphology are also important factors that influence the device stability of pentacene devices. As a result of the surface energy mismatch between the dielectric layer and organic semiconductor, the electronic performance was degraded. Moreover, when pentacene was deposited on the OTS-treated SiO(2) dielectric layer with very low surface energy, pentacene aggregation occurred and resulted in a dramatic decrease of device performance. These results demonstrated that the stable OFETs could be obtained by using pentacene as a semiconductor layer.

The analysis of ion-selective field-effect transistor operation in chemical sensors

NASA Astrophysics Data System (ADS)

Hotra, Zenon; Holyaka, Roman; Hladun, Michael; Humenuk, Iryna

2003-09-01

In this paper we present the research results of influence of substrate potential in ion-selective field-effect transistors (ISFET) on output signal of chemical sensors, e.g. PH-meters. It is shown that the instability of substrate-source p-n junction bias in well-known chemical sensors, which use grounded reference electrode - ISFET gate, affect on sensor characteristics in negative way. The analytical description and research results of 'substrate effect' on ISFET characteristics are considered.

Enhancement of field effect mobility of poly(3-hexylthiophene) thin film transistors by soft-lithographical nanopatterning on the gate-dielectric surface

NASA Astrophysics Data System (ADS)

Park, Jeong-Ho; Kang, Seok-Ju; Park, Jeong-Woo; Lim, Bogyu; Kim, Dong-Yu

2007-11-01

The submicroscaled octadecyltrichlorosilane (OTS) line patterns on gate-dielectric surfaces were introduced into the fabrication of organic field effect transistors (OFETs). These spin-cast regioregular poly(3-hexylthiophene) films on soft-lithographically patterned SiO2 surfaces yielded a higher hole mobility (˜0.072cm2/Vs ) than those of unpatterned (˜0.015cm2/Vs) and untreated (˜5×10-3cm2/Vs) OFETs. The effect of mobility enhancement as a function of the patterned line pitch was investigated in structural and geometric characteristics. The resulting improved mobility is likely attributed to the formation of efficient π-π stacking as a result of guide-assisted, local self-organization-involved molecular interactions between the poly(3-hexylthiophene) polymer and the geometrical OTS patterns.

Atomically engineered epitaxial anatase TiO 2 metal-semiconductor field-effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kim, Brian S. Y.; Minohara, Makoto; Hikita, Yasuyuki

Here, anatase TiO 2 is a promising material for a vast array of electronic, energy, and environmental applications, including photocatalysis, photovoltaics, and sensors. A key requirement for these applications is the ability to modulate its electrical properties without dominant dopant scattering and while maintaining high carrier mobility. Here, we demonstrate the room temperature field-effect modulation of the conducting epitaxial interface between anatase TiO 2 and LaAlO 3 (001), which arises for LaO-terminated LaAlO 3, while the AlO 2-terminated interface is insulating. This approach, together with the metal-semiconductor field-effect transistor geometry, naturally bypasses the gate/channel interface traps, resulting in a highmore » field-effect mobility μ FE of 3.14 cm 2 (V s) –1 approaching 98% of the corresponding Hall mobility μ Hall. Accordingly, the channel conductivity is modulated over 6 orders of magnitude over a gate voltage range of ~4 V.« less

Atomically engineered epitaxial anatase TiO 2 metal-semiconductor field-effect transistors

DOE PAGES

Kim, Brian S. Y.; Minohara, Makoto; Hikita, Yasuyuki; ...

2018-03-26

Here, anatase TiO 2 is a promising material for a vast array of electronic, energy, and environmental applications, including photocatalysis, photovoltaics, and sensors. A key requirement for these applications is the ability to modulate its electrical properties without dominant dopant scattering and while maintaining high carrier mobility. Here, we demonstrate the room temperature field-effect modulation of the conducting epitaxial interface between anatase TiO 2 and LaAlO 3 (001), which arises for LaO-terminated LaAlO 3, while the AlO 2-terminated interface is insulating. This approach, together with the metal-semiconductor field-effect transistor geometry, naturally bypasses the gate/channel interface traps, resulting in a highmore » field-effect mobility μ FE of 3.14 cm 2 (V s) –1 approaching 98% of the corresponding Hall mobility μ Hall. Accordingly, the channel conductivity is modulated over 6 orders of magnitude over a gate voltage range of ~4 V.« less

Atomically engineered epitaxial anatase TiO2 metal-semiconductor field-effect transistors

NASA Astrophysics Data System (ADS)

Kim, Brian S. Y.; Minohara, Makoto; Hikita, Yasuyuki; Bell, Christopher; Hwang, Harold Y.

2018-03-01

Anatase TiO2 is a promising material for a vast array of electronic, energy, and environmental applications, including photocatalysis, photovoltaics, and sensors. A key requirement for these applications is the ability to modulate its electrical properties without dominant dopant scattering and while maintaining high carrier mobility. Here, we demonstrate the room temperature field-effect modulation of the conducting epitaxial interface between anatase TiO2 and LaAlO3 (001), which arises for LaO-terminated LaAlO3, while the AlO2-terminated interface is insulating. This approach, together with the metal-semiconductor field-effect transistor geometry, naturally bypasses the gate/channel interface traps, resulting in a high field-effect mobility μ FE of 3.14 cm2 (V s)-1 approaching 98% of the corresponding Hall mobility μ Hall . Accordingly, the channel conductivity is modulated over 6 orders of magnitude over a gate voltage range of ˜4 V.

Device Physics of Contact Issues for the Overestimation and Underestimation of Carrier Mobility in Field-Effect Transistors

NASA Astrophysics Data System (ADS)

Liu, Chuan; Li, Gongtan; Di Pietro, Riccardo; Huang, Jie; Noh, Yong-Young; Liu, Xuying; Minari, Takeo

2017-09-01

Very high values of carrier mobility have been recently reported in newly developed materials for field-effect transistors (FETs) or thin-film transistors (TFTs). However, there is an increasing concern of whether the values are overestimated. In this paper, we investigate how much contact resistance a FET or TFT can tolerate to allow the conventional current-voltage equations, which is derived for no contact resistance. We contend that mobility in transistors with resistive contact can be underestimated with the presence of the injection barrier, whereas mobility in transistors with gated Schottky contact can be overestimated by more than 10 times. The latter phenomenon occurs even in long-channel devices, and it becomes more severe when using low-k dielectrics. This is because the band bending and injection barrier experience a complicated evolution on account of electrostatic doping in the semiconducting layer; thus, they do not follow a capacitance approximation. When the band bending is weak, the accumulation is as weak as that in the subthreshold regime. Accordingly, the carrier concentration nonlinearly increases with the gate field. This mechanism can occur with or without exhibiting the "kink" feature in the transfer curves, which has been suggested as the signature of overestimation. For precision, carrier mobility should be presented against gate voltage and should be examined by other recommended extraction methods.

Impact of metal gates on remote phonon scattering in titanium nitride/hafnium dioxide n-channel metal-oxide-semiconductor field effect transistors-low temperature electron mobility study

NASA Astrophysics Data System (ADS)

Maitra, Kingsuk; Frank, Martin M.; Narayanan, Vijay; Misra, Veena; Cartier, Eduard A.

2007-12-01

We report low temperature (40-300 K) electron mobility measurements on aggressively scaled [equivalent oxide thickness (EOT)=1 nm] n-channel metal-oxide-semiconductor field effect transistors (nMOSFETs) with HfO2 gate dielectrics and metal gate electrodes (TiN). A comparison is made with conventional nMOSFETs containing HfO2 with polycrystalline Si (poly-Si) gate electrodes. No substantial change in the temperature acceleration factor is observed when poly-Si is replaced with a metal gate, showing that soft optical phonons are not significantly screened by metal gates. A qualitative argument based on an analogy between remote phonon scattering and high-resolution electron energy-loss spectroscopy (HREELS) is provided to explain the underlying physics of the observed phenomenon. It is also shown that soft optical phonon scattering is strongly damped by thin SiO2 interface layers, such that room temperature electron mobility values at EOT=1 nm become competitive with values measured in nMOSFETs with SiON gate dielectrics used in current high performance processors.

Effect of electrode design on crosstalk between neighboring organic field-effect transistors based on one single crystal

NASA Astrophysics Data System (ADS)

Li, Mengjie; Tang, Qingxin; Tong, Yanhong; Zhao, Xiaoli; Zhou, Shujun; Liu, Yichun

2018-03-01

The design of high-integration organic circuits must be such that the interference between neighboring devices is eliminated. Here, rubrene crystals were used to study the effect of the electrode design on crosstalk between neighboring organic field-effect transistors (OFETs). Results show that a decreased source/drain interval and gate electrode width can decrease the diffraction distance of the current, and therefore can weaken the crosstalk. In addition, the inherent low carrier concentration in organic semiconductors can create a high-resistance barrier at the space between gate electrodes of neighboring devices, limiting or even eliminating the crosstalk as a result of the gate electrode width being smaller than the source/drain electrode width.

A scanning probe mounted on a field-effect transistor: Characterization of ion damage in Si.

PubMed

Shin, Kumjae; Lee, Hoontaek; Sung, Min; Lee, Sang Hoon; Shin, Hyunjung; Moon, Wonkyu

2017-10-01

We have examined the capabilities of a Tip-On-Gate of Field-Effect Transistor (ToGoFET) probe for characterization of FIB-induced damage in Si surface. A ToGoFET probe is the SPM probe which the Field Effect Transistor(FET) is embedded at the end of a cantilever and a Pt tip was mounted at the gate of FET. The ToGoFET probe can detect the surface electrical properties by measuring source-drain current directly modulated by the charge on the tip. In this study, a Si specimen whose surface was processed with Ga+ ion beam was prepared. Irradiation and implantation with Ga+ ions induce highly localized modifications to the contact potential. The FET embedded on ToGoFET probe detected the surface electric field profile generated by schottky contact between the Pt tip and the sample surface. Experimentally, it was shown that significant differences of electric field due to the contact potential barrier in differently processed specimens were observed using ToGOFET probe. This result shows the potential that the local contact potential difference can be measured by simple working principle with high sensitivity. Copyright © 2017 Elsevier Ltd. All rights reserved.

Air-gating and chemical-gating in transistors and sensing devices made from hollow TiO2 semiconductor nanotubes

NASA Astrophysics Data System (ADS)

Alivov, Yahya; Funke, Hans; Nagpal, Prashant

2015-07-01

Rapid miniaturization of electronic devices down to the nanoscale, according to Moore’s law, has led to some undesirable effects like high leakage current in transistors, which can offset additional benefits from scaling down. Development of three-dimensional transistors, by spatial extension in the third dimension, has allowed higher contact area with a gate electrode and better control over conductivity in the semiconductor channel. However, these devices do not utilize the large surface area and interfaces for new electronic functionality. Here, we demonstrate air gating and chemical gating in hollow semiconductor nanotube devices and highlight the potential for development of novel transistors that can be modulated using channel bias, gate voltage, chemical composition, and concentration. Using chemical gating, we reversibly altered the conductivity of nanoscaled semiconductor nanotubes (10-500 nm TiO2 nanotubes) by six orders of magnitude, with a tunable rectification factor (ON/OFF ratio) ranging from 1-106. While demonstrated air- and chemical-gating speeds were slow here (˜seconds) due to the mechanical-evacuation rate and size of our chamber, the small nanoscale volume of these hollow semiconductors can enable much higher switching speeds, limited by the rate of adsorption/desorption of molecules at semiconductor interfaces. These chemical-gating effects are completely reversible, additive between different chemical compositions, and can enable semiconductor nanoelectronic devices for ‘chemical transistors’, ‘chemical diodes’, and very high-efficiency sensing applications.

Dual Input AND Gate Fabricated From a Single Channel Poly (3-Hexylthiophene) Thin Film Field Effect Transistor

NASA Technical Reports Server (NTRS)

Pinto, N. J.; Perez, R.; Mueller, C. H.; Theofylaktos, N.; Miranda, F. A.

2006-01-01

A regio-regular poly (3-hexylthiophene) (RRP3HT) thin film transistor having a split-gate architecture has been fabricated on a doped silicon/silicon nitride substrate and characterized. This device demonstrates AND logic functionality. The device functionality was controlled by applying either 0 or -10 V to each of the gate electrodes. When -10 V was simultaneously applied to both gates, the device was conductive (ON), while any other combination of gate voltages rendered the device resistive (OFF). The p-type carrier charge mobility was about 5x10(exp -4) per square centimeter per V-sec. The low mobility is attributed to the sharp contours of the RRP3HT film due to substrate non-planarity. A significant advantage of this architecture is that AND logic devices with multiple inputs can be fabricated using a single RRP3HT channel with multiple gates.

Metal-semiconductor barrier modulation for high photoresponse in transition metal dichalcogenide field effect transistors.

PubMed

Li, Hua-Min; Lee, Dae-Yeong; Choi, Min Sup; Qu, Deshun; Liu, Xiaochi; Ra, Chang-Ho; Yoo, Won Jong

2014-02-10

A gate-controlled metal-semiconductor barrier modulation and its effect on carrier transport were investigated in two-dimensional (2D) transition metal dichalcogenide (TMDC) field effect transistors (FETs). A strong photoresponse was observed in both unipolar MoS2 and ambipolar WSe2 FETs (i) at the high drain voltage due to a high electric field along the channel for separating photo-excited charge carriers and (ii) at the certain gate voltage due to the optimized barriers for the collection of photo-excited charge carriers at metal contacts. The effective barrier height between Ti/Au and TMDCs was estimated by a low temperature measurement. An ohmic contact behavior and drain-induced barrier lowering (DIBL) were clearly observed in MoS2 FET. In contrast, a Schottky-to-ohmic contact transition was observed in WSe2 FET as the gate voltage increases, due to the change of majority carrier transport from holes to electrons. The gate-dependent barrier modulation effectively controls the carrier transport, demonstrating its great potential in 2D TMDCs for electronic and optoelectronic applications.

X-band T/R switch with body-floating multi-gate PDSOI NMOS transistors

NASA Astrophysics Data System (ADS)

Park, Mingyo; Min, Byung-Wook

2018-03-01

This paper presents an X-band transmit/receive switch using multi-gate NMOS transistors in a silicon-on-insulator CMOS process. For low loss and high power handling capability, floating body multi-gate NMOS transistors are adopted instead of conventional stacked NMOS transistors, resulting in 53% reduction of transistor area. Comparing to the stacked NMOS transistors, the multi gate transistor shares the source and drain region between stacked transistors, resulting in reduced chip area and parasitics. The impedance between bodies of gates in multi-gate NMOS transistors is assumed to be very large during design and confirmed after measurement. The measured input 1 dB compression point is 34 dBm. The measured insertion losses of TX and RX modes are respectively 1.7 dB and 2.0 dB at 11 GHz, and the measured isolations of TX and RX modes are >27 dB and >20 dB in X-band, respectively. The chip size is 0.086 mm2 without pads, which is 25% smaller than the T/R switch with stacked transistors.

Drying Temperature Dependence of Sol-gel Spin Coated Bilayer Composite ZnO/TiO2 Thin Films for Extended Gate Field Effect Transistor pH Sensor

NASA Astrophysics Data System (ADS)

Rahman, R. A.; Zulkefle, M. A.; Yusoff, K. A.; Abdullah, W. F. H.; Rusop, M.; Herman, S. H.

2018-03-01

This study presents an investigation on zinc oxide (ZnO) and titanium dioxide (TiO2) bilayer film applied as the sensing membrane for extended-gate field effect transistor (EGFET) for pH sensing application. The influences of the drying temperatures on the pH sensing capability of ZnO/TiO2 were investigated. The sensing performance of the thin films were measured by connecting the thin film to a commercial MOSFET to form the extended gates. By varying the drying temperature, we found that the ZnO/TiO2 thin film dried at 150°C gave the highest sensitivity compared to other drying conditions, with the sensitivity value of 48.80 mV/pH.

Self aligned hysteresis free carbon nanotube field-effect transistors

NASA Astrophysics Data System (ADS)

Shlafman, M.; Tabachnik, T.; Shtempluk, O.; Razin, A.; Kochetkov, V.; Yaish, Y. E.

2016-04-01

Hysteresis phenomenon in the transfer characteristics of carbon nanotube field effect transistor (CNT FET) is being considered as the main obstacle for successful realization of electronic devices based on CNTs. In this study, we prepare four kinds of CNTFETs and explore their hysteretic behavior. Two kinds of devices comprise on-surface CNTs (type I) and suspended CNTs (type II) with thin insulating layer underneath and a single global gate which modulates the CNT conductance. The third and fourth types (types III and IV) consist of suspended CNT over a metallic local gate underneath, where for type IV the local gate was patterned self aligned with the source and drain electrodes. The first two types of devices, i.e., type I and II, exhibit substantial hysteresis which increases with scanning range and sweeping time. Under high vacuum conditions and moderate electric fields ( |E |>4 ×106 V /cm ), the hysteresis for on-surface devices cannot be eliminated, as opposed to suspended devices. Interestingly, type IV devices exhibit no hysteresis at all at ambient conditions, and from the different roles which the global and local gates play for the four types of devices, we could learn about the hysteresis mechanism of this system. We believe that these self aligned hysteresis free FETs will enable the realization of different electronic devices and sensors based on CNTs.

Dependence of Pentacene Crystal Growth on Dielectric Roughness for Fabrication of Flexible Field-Effect Transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yang, H.; Yang, C; Kim, S

2010-01-01

The dependence of pentacene nanostructures on gate dielectric surfaces were investigated for flexible organic field-effect transistor (OFET) applications. Two bilayer types of polymer/aluminum oxide (Al{sub 2}O{sub 3}) gate dielectrics were fabricated on commercial Al foils laminated onto a polymer back plate. Some Al foils were directly used as gate electrodes, and others were smoothly polished by an electrolytic etching. These Al surfaces were then anodized and coated with poly({alpha}-methyl styrene) (PAMS). For PAMS/Al{sub 2}O{sub 3} dielectrics onto etched Al foils, surface roughness up to 1 nm could be reached, although isolated dimples with a lateral diameter of several micrometers weremore » still present. On PAMS/Al{sub 2}O{sub 3} dielectrics (surface roughness >40 nm) containing mechanical grooves of Al foil, average hole mobility ({mu}FET) of 50 nm thick pentacene-FETs under the low operating voltages (|V| < 6 V) was {approx}0.15 cm{sup 2} V{sup -1} s{sup -1}. In contrast, pentacene-FETs employing the etched Al gates exhibited {mu}FET of 0.39 cm{sup 2} V{sup -1} s{sup -1}, which was comparable to that of reference samples with PAMS/Al{sub 2}O{sub 3} dielectrics onto flat sputtered Al gates. Conducting-probe atomic force microscopy and two-dimensional X-ray diffraction of pentacene films with various thicknesses revealed different out-of-plane and in-plane crystal orderings of pentacene, depending on the surface roughness of the gate dielectrics.« less

Atomic-Monolayer MoS2 Band-to-Band Tunneling Field-Effect Transistor.

PubMed

Lan, Yann-Wen; Torres, Carlos M; Tsai, Shin-Hung; Zhu, Xiaodan; Shi, Yumeng; Li, Ming-Yang; Li, Lain-Jong; Yeh, Wen-Kuan; Wang, Kang L

2016-11-01

The experimental observation of band-to-band tunneling in novel tunneling field-effect transistors utilizing a monolayer of MoS 2 as the conducting channel is demonstrated. Our results indicate that the strong gate-coupling efficiency enabled by two-dimensional materials, such as monolayer MoS 2 , results in the direct manifestation of a band-to-band tunneling current and an ambipolar transport. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Investigation of buffer traps in AlGaN/GaN-on-Si devices by thermally stimulated current spectroscopy and back-gating measurement

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yang, Shu; Zhou, Chunhua; Jiang, Qimeng

2014-01-06

Thermally stimulated current (TSC) spectroscopy and high-voltage back-gating measurement are utilized to study GaN buffer traps specific to AlGaN/GaN lateral heterojunction structures grown on a low-resistivity Si substrate. Three dominating deep-level traps in GaN buffer with activation energies of ΔE{sub T1} ∼ 0.54 eV, ΔE{sub T2} ∼ 0.65 eV, and ΔE{sub T3} ∼ 0.75 eV are extracted from TSC spectroscopy in a vertical GaN-on-Si structure. High back-gate bias applied to the Si substrate could influence the drain current in an AlGaN/GaN-on-Si high-electron-mobility transistor in a way that cannot be explained with a simple field-effect model. By correlating the trap states identified in TSC with the back-gating measurement results, itmore » is proposed that the ionization/deionization of both donor and acceptor traps are responsible for the generation of buffer space charges, which impose additional modulation to the 2DEG channel.« less

A carrier-based analytical theory for negative capacitance symmetric double-gate field effect transistors and its simulation verification

NASA Astrophysics Data System (ADS)

Jiang, Chunsheng; Liang, Renrong; Wang, Jing; Xu, Jun

2015-09-01

A carrier-based analytical drain current model for negative capacitance symmetric double-gate field effect transistors (NC-SDG FETs) is proposed by solving the differential equation of the carrier, the Pao-Sah current formulation, and the Landau-Khalatnikov equation. The carrier equation is derived from Poisson’s equation and the Boltzmann distribution law. According to the model, an amplified semiconductor surface potential and a steeper subthreshold slope could be obtained with suitable thicknesses of the ferroelectric film and insulator layer at room temperature. Results predicted by the analytical model agree well with those of the numerical simulation from a 2D simulator without any fitting parameters. The analytical model is valid for all operation regions and captures the transitions between them without any auxiliary variables or functions. This model can be used to explore the operating mechanisms of NC-SDG FETs and to optimize device performance.

Blending effect of 6,13-bis(triisopropylsilylethynyl) pentacene-graphene composite layers for flexible thin film transistors with a polymer gate dielectric.

PubMed

Basu, Sarbani; Adriyanto, Feri; Wang, Yeong-Her

2014-02-28

Solution processible poly(4-vinylphenol) is employed as a transistor dielectric material for low cost processing on flexible substrates at low temperatures. A 6,13-bis (triisopropylsilylethynyl) (TIPS) pentacene-graphene hybrid semiconductor is drop cast to fabricate bottom-gate and bottom-contact field-effect transistor devices on flexible and glass substrates under an ambient air environment. A few layers of graphene flakes increase the area in the conduction channel, and form bridge connections between the crystalline regions of the semiconductor layer which can change the surface morphology of TIPS pentacene films. The TIPS pentacene-graphene hybrid semiconductor-based organic thin film transistors (OTFTs) cross-linked with a poly(4-vinylphenol) gate dielectric exhibit an effective field-effect mobility of 0.076 cm(2) V(-1) s(-1) and a threshold voltage of -0.7 V at V(gs) = -40 V. By contrast, typical TIPS pentacene shows four times lower mobility of 0.019 cm(2) V(-1) s(-1) and a threshold voltage of 5 V. The graphene/TIPS pentacene hybrids presented in this paper can enhance the electrical characteristics of OTFTs due to their high crystallinity, uniform large-grain distribution, and effective reduction of crystal misorientation of the organic semiconductor layer, as confirmed by x-ray diffraction spectroscopy, atomic force microscopy, and optical microscopy studies.

Oxide-based synaptic transistors gated by solution-processed gelatin electrolytes

NASA Astrophysics Data System (ADS)

He, Yinke; Sun, Jia; Qian, Chuan; Kong, Ling-An; Gou, Guangyang; Li, Hongjian

2017-04-01

In human brain, a large number of neurons are connected via synapses. Simulation of the synaptic behaviors using electronic devices is the most important step for neuromorphic systems. In this paper, proton conducting gelatin electrolyte-gated oxide field-effect transistors (FETs) were used for emulating synaptic functions, in which the gate electrode is regarded as pre-synaptic neuron and the channel layer as the post-synaptic neuron. In analogy to the biological synapse, a potential spike can be applied at the gate electrode and trigger ionic motion in the gelatin electrolyte, which in turn generates excitatory post-synaptic current (EPSC) in the channel layer. Basic synaptic behaviors including spike time-dependent EPSC, paired-pulse facilitation (PPF), self-adaptation, and frequency-dependent synaptic transmission were successfully mimicked. Such ionic/electronic hybrid devices are beneficial for synaptic electronics and brain-inspired neuromorphic systems.

Nanocrystal-mediated charge screening effects in nanowire field-effect transistors

NASA Astrophysics Data System (ADS)

Yoon, C. J.; Yeom, D. H.; Jeong, D. Y.; Lee, M. G.; Moon, B. M.; Kim, S. S.; Choi, C. Y.; Koo, S. M.

2009-03-01

ZnO nanowire field-effect transistors having an omega-shaped floating gate (OSFG) have been successfully fabricated by directly coating CdTe nanocrystals (˜6±2.5 nm) at room temperature, and compared to simultaneously prepared control devices without nanocrystals. Herein, we demonstrate that channel punchthrough may occur when the depletion from the OSFG takes place due to the trapped charges in the nanocrystals. Electrical measurements on the OSFG nanowire devices showed static-induction transistorlike behavior in the drain output IDS-VDS characteristics and a hysteresis window as large as ˜3.1 V in the gate transfer IDS-VGS characteristics. This behavior is ascribed to the presence of the CdTe nanocrystals, and is indicative of the trapping and emission of electrons in the nanocrystals. The numerical simulations clearly show qualitatively the same characteristics as the experimental data and confirm the effect, showing that the change in the potential distribution across the channel, induced by both the wrapping-around gate and the drain, affects the transport characteristics of the device. The cross-sectional energy band and potential profile of the OSFG channel corresponding to the "programed (noncharged)" and "erased (charged)" operations for the device are also discussed on the basis of the numerical capacitance-voltage simulations.

Electrospun Polyaniline/Polyethylene Oxide Nanofiber Field Effect Transistor

NASA Technical Reports Server (NTRS)

Pinto, N. J.; Johnson, A. T.; MacDiarmid, A. G.; Mueller, C. H.; Theofylaktos, N.; Robinson, D. C.; Miranda, F. A.

2003-01-01

We report on the observation of field effect transistor (FET) behavior in electrospun camphorsulfonic acid doped polyaniline(PANi)/polyethylene oxide(PE0) nanofibers. Saturation channel currents are observed at surprisingly low source/drain voltages. The hole mobility in the depletion regime is 1.4 x 10(exp -4) sq cm/V s while the 1-D charge density (at zero gate bias) is calculated to be approximately 1 hole per 50 two-ring repeat units of polyaniline, consistent with the rather high channel conductivity (approx. 10(exp -3) S/cm). Reducing or eliminating the PEO content in the fiber is expected to enhance device parameters. Electrospinning is thus proposed as a simple method of fabricating 1-D polymer FET's.

An innovative large scale integration of silicon nanowire-based field effect transistors

NASA Astrophysics Data System (ADS)

Legallais, M.; Nguyen, T. T. T.; Mouis, M.; Salem, B.; Robin, E.; Chenevier, P.; Ternon, C.

2018-05-01

Since the early 2000s, silicon nanowire field effect transistors are emerging as ultrasensitive biosensors while offering label-free, portable and rapid detection. Nevertheless, their large scale production remains an ongoing challenge due to time consuming, complex and costly technology. In order to bypass these issues, we report here on the first integration of silicon nanowire networks, called nanonet, into long channel field effect transistors using standard microelectronic process. A special attention is paid to the silicidation of the contacts which involved a large number of SiNWs. The electrical characteristics of these FETs constituted by randomly oriented silicon nanowires are also studied. Compatible integration on the back-end of CMOS readout and promising electrical performances open new opportunities for sensing applications.

Bias-stress characterization of solution-processed organic field-effect transistor based on highly ordered liquid crystals

NASA Astrophysics Data System (ADS)

Kunii, M.; Iino, H.; Hanna, J.

2017-06-01

Bias-stress effects in solution-processed, 2-decyl-7-phenyl-[1]benzothieno[3,2-b][1]benzothiophene (Ph-BTBT-10) field effect transistors (FETs) are studied under negative and positive direct current bias. The bottom gate, bottom contact polycrystalline Ph-BTBT-10 FET with a hybrid gate dielectric of polystyrene and SiO2 shows high field effect mobility as well as a steep subthreshold slope when fabricated with a highly ordered smectic E liquid crystalline (SmE) film as a precursor. Negative gate bias-stress causes negative threshold voltage shift (ΔVth) for Ph-BTBT-10 FET in ambient air, but ΔVth rapidly decreases as the gate bias decreases and approaches to near zero when the gate bias goes down to 9 V in amplitude. In contrast, positive gate bias-stress causes negligible ΔVth even with a relatively high bias voltage. These results conclude that Ph-BTBT-10 FET has excellent bias-stress stability in ambient air in the range of low to moderate operating voltages.

Fabrication of a Silicon Nanowire on a Bulk Substrate by Use of a Plasma Etching and Total Ionizing Dose Effects on a Gate-All-Around Field-Effect Transistor

NASA Technical Reports Server (NTRS)

Moon, Dong-Il; Han, Jin-Woo; Meyyappan, Meyya

2016-01-01

The gate all around transistor is investigated through experiment. The suspended silicon nanowire for the next generation is fabricated on bulk substrate by plasma etching method. The scallop pattern generated by Bosch process is utilized to form a floating silicon nanowire. By combining anisotropic and istropic silicon etch process, the shape of nanowire is accurately controlled. From the suspended nanowire, the gate all around transistor is demonstrated. As the silicon nanowire is fully surrounded by the gate, the device shows excellent electrostatic characteristics.

Selective Dirac voltage engineering of individual graphene field-effect transistors for digital inverter and frequency multiplier integrations

NASA Astrophysics Data System (ADS)

Sul, Onejae; Kim, Kyumin; Jung, Yungwoo; Choi, Eunsuk; Lee, Seung-Beck

2017-09-01

The ambipolar band structure of graphene presents unique opportunities for novel electronic device applications. A cycle of gate voltage sweep in a conventional graphene transistor produces a frequency-doubled output current. To increase the frequency further, we used various graphene doping control techniques to produce Dirac voltage engineered graphene channels. The various surface treatments and substrate conditions produced differently doped graphene channels that were integrated on a single substrate and multiple Dirac voltages were observed by applying a single gate voltage sweep. We applied the Dirac voltage engineering techniques to graphene field-effect transistors on a single chip for the fabrication of a frequency multiplier and a logic inverter demonstrating analog and digital circuit application possibilities.

Selective Dirac voltage engineering of individual graphene field-effect transistors for digital inverter and frequency multiplier integrations.

PubMed

Sul, Onejae; Kim, Kyumin; Jung, Yungwoo; Choi, Eunsuk; Lee, Seung-Beck

2017-09-15

The ambipolar band structure of graphene presents unique opportunities for novel electronic device applications. A cycle of gate voltage sweep in a conventional graphene transistor produces a frequency-doubled output current. To increase the frequency further, we used various graphene doping control techniques to produce Dirac voltage engineered graphene channels. The various surface treatments and substrate conditions produced differently doped graphene channels that were integrated on a single substrate and multiple Dirac voltages were observed by applying a single gate voltage sweep. We applied the Dirac voltage engineering techniques to graphene field-effect transistors on a single chip for the fabrication of a frequency multiplier and a logic inverter demonstrating analog and digital circuit application possibilities.

InGaP/InGaAs field-effect transistor typed hydrogen sensor

NASA Astrophysics Data System (ADS)

Tsai, Jung-Hui; Liou, Syuan-Hao; Lin, Pao-Sheng; Chen, Yu-Chi

2018-02-01

In this article, the Pd-based mixture comprising silicon dioxide (SiO2) is applied as sensing material for the InGaP/InGaAs field-effect transistor typed hydrogen sensor. After wet selectively etching the SiO2, the mixture is turned into Pd nanoparticles on an interlayer. Experimental results depict that hydrogen atoms trapped inside the mixture could effectively decrease the gate barrier height and increase the drain current due to the improved sensing properties when Pd nanoparticles were formed by wet etching method. The sensitivity of the gate forward current from air (the reference) to 9800 ppm hydrogen/air environment approaches the high value of 1674. Thus, the studied device shows a good potential for hydrogen sensor and integrated circuit applications.

Dynamic Wavelength-Tunable Photodetector Using Subwavelength Graphene Field-Effect Transistors

DOE PAGES

Léonard, François; Spataru, Catalin D.; Goldflam, Michael; ...

2017-04-04

The holy grail of photodetector technology is dynamic wavelength tunability. Because of its atomic thickness and unique properties, graphene opens up new paradigms to realize this concept, but so far this has been elusive experimentally. We employ detailed quantum transport modeling of photocurrent in graphene field-effect transistors (including realistic electromagnetic fields) to show that wavelength tunability is possible by dynamically changing the gate voltage. We also reveal the phenomena that govern the behavior of this type of device and show significant departure from the simple expectations based on vertical transitions. We find strong focusing of the electromagnetic fields at themore » contact edges over the same length scale as the band-bending. Both of these spatially-varying potentials lead to an enhancement of non-vertical optical transitions, which dominate even in the absence of phonon or impurity scattering. Furthermore, we show that the vanishing density of states near the Dirac point leads to contact blocking and a gate-dependent modulation of the photocurrent. Several of the effects discussed here should be applicable to a broad range of one- and two-dimensional materials and devices.« less

Dynamic Wavelength-Tunable Photodetector Using Subwavelength Graphene Field-Effect Transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Léonard, François; Spataru, Catalin D.; Goldflam, Michael

The holy grail of photodetector technology is dynamic wavelength tunability. Because of its atomic thickness and unique properties, graphene opens up new paradigms to realize this concept, but so far this has been elusive experimentally. We employ detailed quantum transport modeling of photocurrent in graphene field-effect transistors (including realistic electromagnetic fields) to show that wavelength tunability is possible by dynamically changing the gate voltage. We also reveal the phenomena that govern the behavior of this type of device and show significant departure from the simple expectations based on vertical transitions. We find strong focusing of the electromagnetic fields at themore » contact edges over the same length scale as the band-bending. Both of these spatially-varying potentials lead to an enhancement of non-vertical optical transitions, which dominate even in the absence of phonon or impurity scattering. Furthermore, we show that the vanishing density of states near the Dirac point leads to contact blocking and a gate-dependent modulation of the photocurrent. Several of the effects discussed here should be applicable to a broad range of one- and two-dimensional materials and devices.« less

Comparison of junctionless and inversion-mode p-type metal-oxide-semiconductor field-effect transistors in presence of hole-phonon interactions

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dib, E., E-mail: elias.dib@for.unipi.it; Carrillo-Nuñez, H.; Cavassilas, N.

Junctionless transistors are being considered as one of the alternatives to conventional metal-oxide field-effect transistors. In this work, it is then presented a simulation study of silicon double-gated p-type junctionless transistors compared with its inversion-mode counterpart. The quantum transport problem is solved within the non-equilibrium Green's function formalism, whereas hole-phonon interactions are tackled by means of the self-consistent Born approximation. Our findings show that junctionless transistors should perform as good as a conventional transistor only for ultra-thin channels, with the disadvantage of requiring higher supply voltages in thicker channel configurations.

Three-terminal graphene single-electron transistor fabricated using feedback-controlled electroburning

DOE Office of Scientific and Technical Information (OSTI.GOV)

Puczkarski, Paweł; Gehring, Pascal, E-mail: pascal.gehring@materials.ox.ac.uk; Lau, Chit S.

2015-09-28

We report room-temperature Coulomb blockade in a single layer graphene three-terminal single-electron transistor fabricated using feedback-controlled electroburning. The small separation between the side gate electrode and the graphene quantum dot results in a gate coupling up to 3 times larger compared to the value found for the back gate electrode. This allows for an effective tuning between the conductive and Coulomb blocked state using a small side gate voltage of about 1 V. The technique can potentially be used in the future to fabricate all-graphene based room temperature single-electron transistors or three terminal single molecule transistors with enhanced gate coupling.

Planarized thick copper gate polycrystalline silicon thin film transistors for ultra-large AMOLED displays

NASA Astrophysics Data System (ADS)

Yun, Seung Jae; Lee, Yong Woo; Son, Se Wan; Byun, Chang Woo; Reddy, A. Mallikarjuna; Joo, Seung Ki

2012-08-01

A planarized thick copper (Cu) gate low temperature polycrystalline silicon (LTPS) thin film transistors (TFTs) is fabricated for ultra-large active-matrix organic light-emitting diode (AMOLED) displays. We introduce a damascene and chemical mechanical polishing process to embed a planarized Cu gate of 500 nm thickness into a trench and Si3N4/SiO2 multilayer gate insulator, to prevent the Cu gate from diffusing into the silicon (Si) layer at 550°C, and metal-induced lateral crystallization (MILC) technology to crystallize the amorphous Si layer. A poly-Si TFT with planarized thick Cu gate exhibits a field effect mobility of 5 cm2/Vs and a threshold voltage of -9 V, and a subthreshold swing (S) of 1.4 V/dec.

Control of Ambipolar Transport in SnO Thin-Film Transistors by Back-Channel Surface Passivation for High Performance Complementary-like Inverters.

PubMed

Luo, Hao; Liang, Lingyan; Cao, Hongtao; Dai, Mingzhi; Lu, Yicheng; Wang, Mei

2015-08-12

For ultrathin semiconductor channels, the surface and interface nature are vital and often dominate the bulk properties to govern the field-effect behaviors. High-performance thin-film transistors (TFTs) rely on the well-defined interface between the channel and gate dielectric, featuring negligible charge trap states and high-speed carrier transport with minimum carrier scattering characters. The passivation process on the back-channel surface of the bottom-gate TFTs is indispensable for suppressing the surface states and blocking the interactions between the semiconductor channel and the surrounding atmosphere. We report a dielectric layer for passivation of the back-channel surface of 20 nm thick tin monoxide (SnO) TFTs to achieve ambipolar operation and complementary metal oxide semiconductor (CMOS) like logic devices. This chemical passivation reduces the subgap states of the ultrathin channel, which offers an opportunity to facilitate the Fermi level shifting upward upon changing the polarity of the gate voltage. With the advent of n-type inversion along with the pristine p-type conduction, it is now possible to realize ambipolar operation using only one channel layer. The CMOS-like logic inverters based on ambipolar SnO TFTs were also demonstrated. Large inverter voltage gains (>100) in combination with wide noise margins are achieved due to high and balanced electron and hole mobilities. The passivation also improves the long-term stability of the devices. The ability to simultaneously achieve field-effect inversion, electrical stability, and logic function in those devices can open up possibilities for the conventional back-channel surface passivation in the CMOS-like electronics.

Atomic layer deposition of insulating nitride interfacial layers for germanium metal oxide semiconductor field effect transistors with high-κ oxide/tungsten nitride gate stacks

NASA Astrophysics Data System (ADS)

Kim, Kyoung H.; Gordon, Roy G.; Ritenour, Andrew; Antoniadis, Dimitri A.

2007-05-01

Atomic layer deposition (ALD) was used to deposit passivating interfacial nitride layers between Ge and high-κ oxides. High-κ oxides on Ge surfaces passivated by ultrathin (1-2nm) ALD Hf3N4 or AlN layers exhibited well-behaved C-V characteristics with an equivalent oxide thickness as low as 0.8nm, no significant flatband voltage shifts, and midgap density of interface states values of 2×1012cm-1eV-1. Functional n-channel and p-channel Ge field effect transistors with nitride interlayer/high-κ oxide/metal gate stacks are demonstrated.

Nonvolatile memory with graphene oxide as a charge storage node in nanowire field-effect transistors

NASA Astrophysics Data System (ADS)

Baek, David J.; Seol, Myeong-Lok; Choi, Sung-Jin; Moon, Dong-Il; Choi, Yang-Kyu

2012-02-01

Through the structural modification of a three-dimensional silicon nanowire field-effect transistor, i.e., a double-gate FinFET, a structural platform was developed which allowed for us to utilize graphene oxide (GO) as a charge trapping layer in a nonvolatile memory device. By creating a nanogap between the gate and the channel, GO was embedded after the complete device fabrication. By applying a proper gate voltage, charge trapping, and de-trapping within the GO was enabled and resulted in large threshold voltage shifts. The employment of GO with FinFET in our work suggests that graphitic materials can potentially play a significant role for future nanoelectronic applications.

Large-Area CVD-Grown Sub-2 V ReS2 Transistors and Logic Gates.

PubMed

Dathbun, Ajjiporn; Kim, Youngchan; Kim, Seongchan; Yoo, Youngjae; Kang, Moon Sung; Lee, Changgu; Cho, Jeong Ho

2017-05-10

We demonstrated the fabrication of large-area ReS 2 transistors and logic gates composed of a chemical vapor deposition (CVD)-grown multilayer ReS 2 semiconductor channel and graphene electrodes. Single-layer graphene was used as the source/drain and coplanar gate electrodes. An ion gel with an ultrahigh capacitance effectively gated the ReS 2 channel at a low voltage, below 2 V, through a coplanar gate. The contact resistance of the ion gel-gated ReS 2 transistors with graphene electrodes decreased dramatically compared with the SiO 2 -devices prepared with Cr electrodes. The resulting transistors exhibited good device performances, including a maximum electron mobility of 0.9 cm 2 /(V s) and an on/off current ratio exceeding 10 4 . NMOS logic devices, such as NOT, NAND, and NOR gates, were assembled using the resulting transistors as a proof of concept demonstration of the applicability of the devices to complex logic circuits. The large-area synthesis of ReS 2 semiconductors and graphene electrodes and their applications in logic devices open up new opportunities for realizing future flexible electronics based on 2D nanomaterials.

Triple-mode single-transistor graphene amplifier and its applications.

PubMed

Yang, Xuebei; Liu, Guanxiong; Balandin, Alexander A; Mohanram, Kartik

2010-10-26

We propose and experimentally demonstrate a triple-mode single-transistor graphene amplifier utilizing a three-terminal back-gated single-layer graphene transistor. The ambipolar nature of electronic transport in graphene transistors leads to increased amplifier functionality as compared to amplifiers built with unipolar semiconductor devices. The ambipolar graphene transistors can be configured as n-type, p-type, or hybrid-type by changing the gate bias. As a result, the single-transistor graphene amplifier can operate in the common-source, common-drain, or frequency multiplication mode, respectively. This in-field controllability of the single-transistor graphene amplifier can be used to realize the modulation necessary for phase shift keying and frequency shift keying, which are widely used in wireless applications. It also offers new opportunities for designing analog circuits with simpler structure and higher integration densities for communications applications.

Glucose Sensing Using Functionalized Amorphous In-Ga-Zn-O Field-Effect Transistors.

PubMed

Du, Xiaosong; Li, Yajuan; Motley, Joshua R; Stickle, William F; Herman, Gregory S

2016-03-01

Recent advances in glucose sensing have focused on the integration of sensors into contact lenses to allow noninvasive continuous glucose monitoring. Current technologies focus primarily on enzyme-based electrochemical sensing which requires multiple nontransparent electrodes to be integrated. Herein, we leverage amorphous indium gallium zinc oxide (IGZO) field-effect transistors (FETs), which have found use in a wide range of display applications and can be made fully transparent. Bottom-gated IGZO-FETs can have significant changes in electrical characteristics when the back-channel is exposed to different environments. We have functionalized the back-channel of IGZO-FETs with aminosilane groups that are cross-linked to glucose oxidase and have demonstrated that these devices have high sensitivity to changes in glucose concentrations. Glucose sensing occurs through the decrease in pH during glucose oxidation, which modulates the positive charge of the aminosilane groups attached to the IGZO surface. The change in charge affects the number of acceptor-like surface states which can deplete electron density in the n-type IGZO semiconductor. Increasing glucose concentrations leads to an increase in acceptor states and a decrease in drain-source conductance due to a positive shift in the turn-on voltage. The functionalized IGZO-FET devices are effective in minimizing detection of interfering compounds including acetaminophen and ascorbic acid. These studies suggest that IGZO FETs can be effective for monitoring glucose concentrations in a variety of environments, including those where fully transparent sensing elements may be of interest.

Band-to-band tunneling field effect transistor for low power logic and memory applications: Design, fabrication and characterization

NASA Astrophysics Data System (ADS)

Mookerjea, Saurabh A.

Over the past decade the microprocessor clock frequency has hit a plateau. The main reason for this has been the inability to follow constant electric field scaling, which requires the transistor supply voltage to be scaled down as the transistor dimensions are reduced. Scaling the supply voltage down reduces the dynamic power quadratically but increases the static leakage power exponentially due to non-scalability of threshold voltage of the transistor, which is required to maintain the same ON state performance. This limitation in supply voltage scaling is directly related to MOSFET's (Metal Oxide Semiconductor Field Effect Transistor) sub-threshold slope (SS) limitation of 60 mV/dec at room temperature. Thus novel device design/materials are required that would allow the transistor to switch with sub-threshold slopes steeper than 60 mV/dec at room temperature, thus facilitating supply voltage scaling. Recently, a new class of devices known as super-steep slope (SS<60 mV/dec) transistors are under intense research for its potential to replace the ubiquitous MOSFET. The focus of this dissertation is on the design, fabrication and characterization of band-to-band tunneling field effect transistor (TFET) which belongs to the family of steep slope transistors. TFET with a gate modulated zener tunnel junction at the source allows sub-kT/q (sub-60 mV/dec at room temperature) sub-threshold slope (SS) device operation over a certain gate bias range near the off-state. This allows TFET to achieve much higher I ON-IOFF ratio over a specified gate voltage swing compared to MOSFETs, thus enabling aggressive supply voltage scaling for low power logic operation without impacting its ON-OFF current ratio. This dissertation presents the operating principle of TFET, the material selection strategy and device design for TFET fabrication. This is followed by a novel 6T SRAM design which circumvents the issue of unidirectional conduction in TFET. The switching behavior of TFET is

Removing the current-limit of vertical organic field effect transistors

NASA Astrophysics Data System (ADS)

Sheleg, Gil; Greenman, Michael; Lussem, Bjorn; Tessler, Nir

2017-11-01

The reported Vertical Organic Field Effect Transistors (VOFETs) show either superior current and switching speeds or well-behaved transistor performance, especially saturation in the output characteristics. Through the study of the relationship between the device architecture or dimensions and the device performance, we find that achieving a saturation regime in the output characteristics requires that the device operates in the injection limited regime. In current structures, the existence of the injection limited regime depends on the source's injection barrier as well as on the buried semiconductor layer thickness. To overcome the injection limit imposed by the necessity of injection barrier, we suggest a new architecture to realize VOFETs. This architecture shows better gate control and is independent of the injection barrier at the source, thus allowing for several A cm-2 for a semiconductor having a mobility value of 0.1 cm2 V-1 s-1.

Transistor Laser Optical NOR Gate for High Speed Optical Logic Processors

DTIC Science & Technology

2017-03-20

proposes an optical bistable latch can be built with two universal photonic NOR gate circuits, which are implemented by the three-port tunneling ... Tunneling Junction Transistor Laser (TJ-TL); Optical NOR Gate. Introduction To fulfill the future national security and intelligence needs in this...two-terminal diode lasers. Three-Port Transistor Laser – an Integration of Quantum-Wells into Heterojunction Bipolar Transistor Different than

Field-effect transistors (2nd revised and enlarged edition)

NASA Astrophysics Data System (ADS)

Bocharov, L. N.

The design, principle of operation, and principal technical characteristics of field-effect transistors produced in the USSR are described. Problems related to the use of field-effect transistors in various radioelectronic devices are examined, and tables of parameters and mean statistical characteristics are presented for the main types of field-effect transistors. Methods for calculating various circuit components are discussed and illustrated by numerical examples.

Attofarad resolution capacitance-voltage measurement of nanometer scale field effect transistors utilizing ambient noise.

PubMed

Gokirmak, Ali; Inaltekin, Hazer; Tiwari, Sandip

2009-08-19

A high resolution capacitance-voltage (C-V) characterization technique, enabling direct measurement of electronic properties at the nanoscale in devices such as nanowire field effect transistors (FETs) through the use of random fluctuations, is described. The minimum noise level required for achieving sub-aF (10(-18) F) resolution, the leveraging of stochastic resonance, and the effect of higher levels of noise are illustrated through simulations. The non-linear DeltaC(gate-source/drain)-V(gate) response of FETs is utilized to determine the inversion layer capacitance (C(inv)) and carrier mobility. The technique is demonstrated by extracting the carrier concentration and effective electron mobility in a nanoscale Si FET with C(inv) = 60 aF.

Organic field-effect transistor with octadecyltrichlorosilane (OTS) self-assembled monolayers on gate oxide: effect of OTS quality

NASA Astrophysics Data System (ADS)

Devynck, M.; Tardy, P.; Wantz, G.; Nicolas, Y.; Hirsch, L.

2011-12-01

The effect of OTS (octadecyltrichlorosilane) Self-Assembled Monolayer (SAM) grafted on SiO2 gate dielectric of pentacene-based OFETs (organic field-effect transistors) is investigated. A significant improvement of the charge mobility (μ), up to 0.74 cm2/V s, is reached thanks to OTS treatment. However, in spite of improved performances, several drawbacks, such as an increase in mobility dispersion, substantial hysteresis in IDS-VG characteristics and high threshold voltages (VT), are observed. Changing solvent and deposition method turns out to have no significant effect on the mobility dispersion. A more accurate approach on the evolution of the mobility and the threshold voltage dispersion with OTS storage time highlights the effect of the OTS solution aging. Even if no difference is evidenced in the surface energy and roughness of the OTS layer, electrical characteristics exhibit considerable deterioration with OTS solution storage time. Using an "aged" OTS solution, opened under air, kept under argon and distilled before use, results in an increase of the IDS-VG hysteresis as well as in VT and in mobility dispersion. In comparison, fresh-OTS-based OFETs present a very low hysteresis, a threshold voltage close to 0 and a much lower mobility dispersion. It is demonstrated that aged OTS solutions contain impurities that are not removed by distillation process, which leads to a less densely packed layer causing interfacial charge traps thus deteriorated performances.

Room Temperature Silicene Field-Effect Transistors

NASA Astrophysics Data System (ADS)

Akinwande, Deji

Silicene, a buckled Si analogue of graphene, holds significant promise for future electronics beyond traditional CMOS. In our predefined experiments via encapsulated delamination with native electrodes approach, silicene devices exhibit an ambipolar charge transport behavior, corroborating theories on Dirac band in Ag-free silicene. Monolayer silicene device has extracted field-effect mobility within the theoretical expectation and ON/OFF ratio greater than monolayer graphene, while multilayer silicene devices show decreased mobility and gate modulation. Air-stability of silicene devices depends on the number of layers of silicene and intrinsic material structure determined by growth temperature. Few or multi-layer silicene devices maintain their ambipolar behavior for days in contrast to minutes time scale for monolayer counterparts under similar conditions. Multilayer silicene grown at different temperatures below 300oC possess different intrinsic structures and yield different electrical property and air-stability. This work suggests a practical prospect to enable more air-stable silicene devices with layer and growth condition control, which can be leveraged for other air-sensitive 2D materials. In addition, we describe quantum and classical transistor device concepts based on silicene and related buckled materials that exploit the 2D topological insulating phenomenon. The transistor device physics offer the potential for ballistic transport that is robust against scattering and can be employed for both charge and spin transport. This work was supported by the ARO.

First-principles simulations of Graphene/Transition-metal-Dichalcogenides/Graphene Field-Effect Transistor

NASA Astrophysics Data System (ADS)

Li, Xiangguo; Wang, Yun-Peng; Zhang, X.-G.; Cheng, Hai-Ping

A prototype field-effect transistor (FET) with fascinating properties can be made by assembling graphene and two-dimensional insulating crystals into three-dimensional stacks with atomic layer precision. Transition metal dichalcogenides (TMDCs) such as WS2, MoS2 are good candidates for the atomically thin barrier between two layers of graphene in the vertical FET due to their sizable bandgaps. We investigate the electronic properties of the Graphene/TMDCs/Graphene sandwich structure using first-principles method. We find that the effective tunnel barrier height of the TMDC layers in contact with the graphene electrodes has a layer dependence and can be modulated by a gate voltage. Consequently a very high ON/OFF ratio can be achieved with appropriate number of TMDC layers and a suitable range of the gate voltage. The spin-orbit coupling in TMDC layers is also layer dependent but unaffected by the gate voltage. These properties can be important in future nanoelectronic device designs. DOE/BES-DE-FG02-02ER45995; NERSC.

Study of fully-depleted Ge double-gate n-type Tunneling Field-Effect Transistors for improvement in on-state current and sub-threshold swing

NASA Astrophysics Data System (ADS)

Liu, Xiangyu; Hu, Huiyong; Wang, Meng; Zhang, Heming; Cui, Shimin; Shu, Bin; Wang, Bin

2018-01-01

In this paper, a fully-depleted (FD) Ge double-gate (DG) n-type Tunneling Field-Effect Transistors (TFET) structure is studied in detail by two-dimensional numerical simulation. The simulation results indicated that the on-state current Ion and on-off ratio of the FD Ge DG-TFET increases about 1 order of magnitude comparing with the Conventional Ge DG-TFET, and Ion=3.95×10-5 A/μm and the below 60 mV/decade subthreshold swing S=26.4 mV/decade are achieved with the length of gate LD=20 nm, the workfuntion of metal gate Φm=0.2 eV and the doping concentration of n+-type-channel ND=1×1018 cm-3. Moreover, the impacts of Φm, ND and LD are investigated. The simulation results indicated that the off-state current Ioff includes the tunneling current at the middle of channel IB the gated-induced drain leakage (GIDL) current IGIDL. With optimized Φm and ND, Ioff is reduced about 2 orders of magnitude to 2.5×10-13 A/μm with LD increasing from 40 nm to 100 nm, and on-off ratio is increased to 1.58×107.

Determination of trap distributions from current characteristics of pentacene field-effect transistors with surface modified gate oxide

NASA Astrophysics Data System (ADS)

Scheinert, Susanne; Pernstich, Kurt P.; Batlogg, Bertram; Paasch, Gernot

2007-11-01

It has been demonstrated [K. P. Pernstich, S. Haas, D. Oberhoff, C. Goldmann, D. J. Gundlach, B. Batlogg, A. N. Rashid, and G. Schitter, J. Appl. Phys. 96, 6431 (2004)] that a controllable shift of the threshold voltage in pentacene thin film transistors is caused by the use of organosilanes with different functional groups forming a self-assembled monolayer (SAM) on the gate oxide. The observed broadening of the subthreshold region indicates that the SAM creates additional trap states. Indeed, it is well known that traps strongly influence the behavior of organic field-effect transistors (OFETs). Therefore, the so-called "amorphous silicon (a-Si) model" has been suggested to be an appropriate model to describe OFETs. The main specifics of this model are transport of carriers above a mobility edge obeying Boltzmann statistics and exponentially distributed tail states and deep trap states. Here, approximate trap distributions are determined by adjusting two-dimensional numerical simulations to the experimental data. It follows from a systematic variation of parameters describing the trap distributions that the existence of both donorlike and acceptorlike trap distributions near the valence band, respectively, and a fixed negative interface charge have to be assumed. For two typical devices with different organosilanes the electrical characteristics can be described well with a donorlike bulk trap distribution, an acceptorlike interface distribution, and/or a fixed negative interface charge. As expected, the density of the fixed or trapped interface charge depends strongly on the surface treatment of the dielectric. There are some limitations in determining the trap distributions caused by either slow time-dependent processes resulting in differences between transfer and output characteristics, or in the uncertainty of the effective mobility.

Memristive device based on a depletion-type SONOS field effect transistor

NASA Astrophysics Data System (ADS)

Himmel, N.; Ziegler, M.; Mähne, H.; Thiem, S.; Winterfeld, H.; Kohlstedt, H.

2017-06-01

State-of-the-art SONOS (silicon-oxide-nitride-oxide-polysilicon) field effect transistors were operated in a memristive switching mode. The circuit design is a variation of the MemFlash concept and the particular properties of depletion type SONOS-transistors were taken into account. The transistor was externally wired with a resistively shunted pn-diode. Experimental current-voltage curves show analog bipolar switching characteristics within a bias voltage range of ±10 V, exhibiting a pronounced asymmetric hysteresis loop. The experimental data are confirmed by SPICE simulations. The underlying memristive mechanism is purely electronic, which eliminates an initial forming step of the as-fabricated cells. This fact, together with reasonable design flexibility, in particular to adjust the maximum R ON/R OFF ratio, makes these cells attractive for neuromorphic applications. The relative large set and reset voltage around ±10 V might be decreased by using thinner gate-oxides. The all-electric operation principle, in combination with an established silicon manufacturing process of SONOS devices at the Semiconductor Foundry X-FAB, promise reliable operation, low parameter spread and high integration density.

Field effect transistors improve buffer amplifier

NASA Technical Reports Server (NTRS)

1967-01-01

Unity gain buffer amplifier with a Field Effect Transistor /FET/ differential input stage responds much faster than bipolar transistors when operated at low current levels. The circuit uses a dual FET in a unity gain buffer amplifier having extremely high input impedance, low bias current requirements, and wide bandwidth.

Design considerations and emerging challenges for nanotube-, nanowire-, and negative capacitor-field effect transistors

NASA Astrophysics Data System (ADS)

Wahab, Md. Abdul

As the era of classical planar metal-oxide-semiconductor field-effect transistors (MOSFETs) comes to an end, the semiconductor industry is beginning to adopt 3D device architectures, such as FinFETs, starting at the 22 nm technology node. Since physical limits such as short channel effect (SCE) and self-heating may dominate, it may be difficult to scale Si FinFET below 10 nm. In this regard, transistors with different materials, geometries, or operating principles may help. For example, gate has excellent electrostatic control over 2D thin film channel with planar geometry, and 1D nanowire (NW) channel with gate-all-around (GAA) geometry to reduce SCE. High carrier mobility of single wall carbon nanotube (SWNT) or III-V channels may reduce VDD to reduce power consumption. Therefore, as channel of transistor, 2D thin film of array SWNTs and 1D III-V multi NWs are promising for sub 10 nm technology nodes. In this thesis, we analyze the potential of these transistors from process, performance, and reliability perspectives. For SWNT FETs, we discuss a set of challenges (such as how to (i) characterize diameter distribution, (ii) remove metallic (m)-SWNTs, and (iii) avoid electrostatic cross-talk among the neighboring SWNTs), and demonstrate solution strategies both theoretically and experimentally. Regarding self-heating in these new class of devices (SWNT FET and GAA NW FET including state-of-the-art FinFET), higher thermal resistance from poor thermal conducting oxides results significant temperature rise, and reduces the IC life-time. For GAA NW FETs, we discuss accurate self-heating evaluation with good spatial, temporal, and thermal resolutions. The introduction of negative capacitor (NC), as gate dielectric stack of transistor, allows sub 60 mV/dec operation to reduce power consumption significantly. Taken together, our work provides a comprehensive perspective regarding the challenges and opportunities of sub 10 nm technology nodes.

Producing smart sensing films by means of organic field effect transistors.

PubMed

Manunza, Ileana; Orgiu, Emanuele; Caboni, Alessandra; Barbaro, Massimo; Bonfiglio, Annalisa

2006-01-01

We have fabricated the first example of totally flexible field effect device for chemical detection based on an organic field effect transistor (OFET) made by pentacene films grown on flexible plastic structures. The ion sensitivity is achieved by employing a thin Mylar foil as gate dielectric. A sensitivity of the device to the pH of the electrolyte solution has been observed A similar structure can be used also for detecting mechanical deformations on flexible surfaces. Thanks to the flexibility of the substrate and the low cost of the employed technology, these devices open the way for the production of flexible chemical and strain gauge sensors that can be employed in a variety of innovative applications such as wearable electronics, e-textiles, new man-machine interfaces.

Ion Sensitive Transparent-Gate Transistor for Visible Cell Sensing.

PubMed

Sakata, Toshiya; Nishimura, Kotaro; Miyazawa, Yuuya; Saito, Akiko; Abe, Hiroyuki; Kajisa, Taira

2017-04-04

In this study, we developed an ion-sensitive transparent-gate transistor (IS-TGT) for visible cell sensing. The gate sensing surface of the IS-TGT is transparent in a solution because a transparent amorphous oxide semiconductor composed of amorphous In-Ga-Zn-oxide (a-IGZO) with a thin SiO 2 film gate that includes an indium tin oxide (ITO) film as the source and drain electrodes is utilized. The pH response of the IS-TGT was found to be about 56 mV/pH, indicating approximately Nernstian response. Moreover, the potential signals of the IS-TGT for sodium and potassium ions, which are usually included in biological environments, were evaluated. The optical and electrical properties of the IS-TGT enable cell functions to be monitored simultaneously with microscopic observation and electrical measurement. A platform based on the IS-TGT can be used as a simple and cost-effective plate-cell-sensing system based on thin-film fabrication technology in the research field of life science.

Bottom-Up Tri-gate Transistors and Submicrosecond Photodetectors from Guided CdS Nanowalls.

PubMed

Xu, Jinyou; Oksenberg, Eitan; Popovitz-Biro, Ronit; Rechav, Katya; Joselevich, Ernesto

2017-11-08

Tri-gate transistors offer better performance than planar transistors by exerting additional gate control over a channel from two lateral sides of semiconductor nanowalls (or "fins"). Here we report the bottom-up assembly of aligned CdS nanowalls by a simultaneous combination of horizontal catalytic vapor-liquid-solid growth and vertical facet-selective noncatalytic vapor-solid growth and their parallel integration into tri-gate transistors and photodetectors at wafer scale (cm 2 ) without postgrowth transfer or alignment steps. These tri-gate transistors act as enhancement-mode transistors with an on/off current ratio on the order of 10 8 , 4 orders of magnitude higher than the best results ever reported for planar enhancement-mode CdS transistors. The response time of the photodetector is reduced to the submicrosecond level, 1 order of magnitude shorter than the best results ever reported for photodetectors made of bottom-up semiconductor nanostructures. Guided semiconductor nanowalls open new opportunities for high-performance 3D nanodevices assembled from the bottom up.

Top-gated chemical vapor deposition grown graphene transistors with current saturation.

PubMed

Bai, Jingwei; Liao, Lei; Zhou, Hailong; Cheng, Rui; Liu, Lixin; Huang, Yu; Duan, Xiangfeng

2011-06-08

Graphene transistors are of considerable interest for radio frequency (rf) applications. In general, transistors with large transconductance and drain current saturation are desirable for rf performance, which is however nontrivial to achieve in graphene transistors. Here we report high-performance top-gated graphene transistors based on chemical vapor deposition (CVD) grown graphene with large transconductance and drain current saturation. The graphene transistors were fabricated with evaporated high dielectric constant material (HfO(2)) as the top-gate dielectrics. Length scaling studies of the transistors with channel length from 5.6 μm to 100 nm show that complete current saturation can be achieved in 5.6 μm devices and the saturation characteristics degrade as the channel length shrinks down to the 100-300 nm regime. The drain current saturation was primarily attributed to drain bias induced shift of the Dirac points. With the selective deposition of HfO(2) gate dielectrics, we have further demonstrated a simple scheme to realize a 300 nm channel length graphene transistors with self-aligned source-drain electrodes to achieve the highest transconductance of 250 μS/μm reported in CVD graphene to date.

High-frequency self-aligned graphene transistors with transferred gate stacks

PubMed Central

Cheng, Rui; Bai, Jingwei; Liao, Lei; Zhou, Hailong; Chen, Yu; Liu, Lixin; Lin, Yung-Chen; Jiang, Shan; Huang, Yu; Duan, Xiangfeng

2012-01-01

Graphene has attracted enormous attention for radio-frequency transistor applications because of its exceptional high carrier mobility, high carrier saturation velocity, and large critical current density. Herein we report a new approach for the scalable fabrication of high-performance graphene transistors with transferred gate stacks. Specifically, arrays of gate stacks are first patterned on a sacrificial substrate, and then transferred onto arbitrary substrates with graphene on top. A self-aligned process, enabled by the unique structure of the transferred gate stacks, is then used to position precisely the source and drain electrodes with minimized access resistance or parasitic capacitance. This process has therefore enabled scalable fabrication of self-aligned graphene transistors with unprecedented performance including a record-high cutoff frequency up to 427 GHz. Our study defines a unique pathway to large-scale fabrication of high-performance graphene transistors, and holds significant potential for future application of graphene-based devices in ultra–high-frequency circuits. PMID:22753503

High-frequency self-aligned graphene transistors with transferred gate stacks.

PubMed

Cheng, Rui; Bai, Jingwei; Liao, Lei; Zhou, Hailong; Chen, Yu; Liu, Lixin; Lin, Yung-Chen; Jiang, Shan; Huang, Yu; Duan, Xiangfeng

2012-07-17

Graphene has attracted enormous attention for radio-frequency transistor applications because of its exceptional high carrier mobility, high carrier saturation velocity, and large critical current density. Herein we report a new approach for the scalable fabrication of high-performance graphene transistors with transferred gate stacks. Specifically, arrays of gate stacks are first patterned on a sacrificial substrate, and then transferred onto arbitrary substrates with graphene on top. A self-aligned process, enabled by the unique structure of the transferred gate stacks, is then used to position precisely the source and drain electrodes with minimized access resistance or parasitic capacitance. This process has therefore enabled scalable fabrication of self-aligned graphene transistors with unprecedented performance including a record-high cutoff frequency up to 427 GHz. Our study defines a unique pathway to large-scale fabrication of high-performance graphene transistors, and holds significant potential for future application of graphene-based devices in ultra-high-frequency circuits.

Improvement in top-gate MoS2 transistor performance due to high quality backside Al2O3 layer

NASA Astrophysics Data System (ADS)

Bolshakov, Pavel; Zhao, Peng; Azcatl, Angelica; Hurley, Paul K.; Wallace, Robert M.; Young, Chadwin D.

2017-07-01

A high quality Al2O3 layer is developed to achieve high performance in top-gate MoS2 transistors. Compared with top-gate MoS2 field effect transistors on a SiO2 layer, the intrinsic mobility and subthreshold slope were greatly improved in high-k backside layer devices. A forming gas anneal is found to enhance device performance due to a reduction in the charge trap density of the backside dielectric. The major improvements in device performance are ascribed to the forming gas anneal and the high-k dielectric screening effect of the backside Al2O3 layer. Top-gate devices built upon these stacks exhibit a near-ideal subthreshold slope of ˜69 mV/dec and a high Y-Function extracted intrinsic carrier mobility (μo) of 145 cm2/V.s, indicating a positive influence on top-gate device performance even without any backside bias.

Quantum ballistic analysis of transition metal dichalcogenides based double gate junctionless field effect transistor and its application in nano-biosensor

NASA Astrophysics Data System (ADS)

Shadman, Abir; Rahman, Ehsanur; Khosru, Quazi D. M.

2017-11-01

To reduce the thermal budget and the short channel effects in state of the art CMOS technology, Junctionless field effect transistor (JLFET) has been proposed in the literature. Numerous experimental, modeling, and simulation based works have been done on this new FET with bulk materials for various geometries until now. On the other hand, the two-dimensional layered material is considered as an alternative to current Si technology because of its ultra-thin body and high mobility. Very recently few simulation based works have been done on monolayer molybdenum disulfide based JLFET mainly to show the advantage of JLFET over conventional FET. However, no comprehensive simulation-based work has been done for double gate JLFET keeping in mind the prominent transition metal dichalcogenides (TMDC) to the authors' best knowledge. In this work, we have studied quantum ballistic drain current-gate voltage characteristics of such FETs within non-equilibrium Green's function (NEGF) framework. Our simulation results reveal that all these TMDC materials are viable options for implementing state of the art Junctionless MOSFET with emphasis on their performance at short gate lengths. Besides evaluating the prospect of TMDC materials in the digital logic application, the performance of Junctionless Double Gate trilayer TMDC heterostructure FET for the label-free electrical detection of biomolecules in dry environment has been investigated for the first time to the authors' best knowledge. The impact of charge neutral biomolecules on the electrical characteristics of the biosensor has been analyzed under dry environment situation. Our study shows that these materials could provide high sensitivity in the sub-threshold region as a channel material in nano-biosensor, a trend demonstrated by silicon on insulator FET sensor in the literature. Thus, going by the trend of replacing silicon with these novel materials in device level, TMDC heterostructure could be a viable alternative to

Nonvolatile gate effect in a ferroelectric-semiconductor quantum well.

PubMed

Stolichnov, Igor; Colla, Enrico; Setter, Nava; Wojciechowski, Tomasz; Janik, Elzbieta; Karczewski, Grzegorz

2006-12-15

Field effect transistors with ferroelectric gates would make ideal rewritable nonvolatile memories were it not for the severe problems in integrating the ferroelectric oxide directly on the semiconductor channel. We propose a powerful way to avoid these problems using a gate material that is ferroelectric and semiconducting simultaneously. First, ferroelectricity in semiconductor (Cd,Zn)Te films is proven and studied using modified piezoforce scanning probe microscopy. Then, a rewritable field effect device is demonstrated by local poling of the (Cd,Zn)Te layer of a (Cd,Zn)Te/CdTe quantum well, provoking a reversible, nonvolatile change in the resistance of the 2D electron gas. The results point to a potential new family of nanoscale one-transistor memories.

Coherent molecular transistor: control through variation of the gate wave function.

PubMed

Ernzerhof, Matthias

2014-03-21

In quantum interference transistors (QUITs), the current through the device is controlled by variation of the gate component of the wave function that interferes with the wave function component joining the source and the sink. Initially, mesoscopic QUITs have been studied and more recently, QUITs at the molecular scale have been proposed and implemented. Typically, in these devices the gate lead is subjected to externally adjustable physical parameters that permit interference control through modifications of the gate wave function. Here, we present an alternative model of a molecular QUIT in which the gate wave function is directly considered as a variable and the transistor operation is discussed in terms of this variable. This implies that we specify the gate current as well as the phase of the gate wave function component and calculate the resulting current through the source-sink channel. Thus, we extend on prior works that focus on the phase of the gate wave function component as a control parameter while having zero or certain discrete values of the current. We address a large class of systems, including finite graphene flakes, and obtain analytic solutions for how the gate wave function controls the transistor.

Polymer-electrolyte-gated nanowire synaptic transistors for neuromorphic applications

NASA Astrophysics Data System (ADS)

Zou, Can; Sun, Jia; Gou, Guangyang; Kong, Ling-An; Qian, Chuan; Dai, Guozhang; Yang, Junliang; Guo, Guang-hua

2017-09-01

Polymer-electrolytes are formed by dissolving a salt in polymer instead of water, the conducting mechanism involves the segmental motion-assisted diffusion of ion in the polymer matrix. Here, we report on the fabrication of tin oxide (SnO2) nanowire synaptic transistors using polymer-electrolyte gating. A thin layer of poly(ethylene oxide) and lithium perchlorate (PEO/LiClO4) was deposited on top of the devices, which was used to boost device performances. A voltage spike applied on the in-plane gate attracts ions toward the polymer-electrolyte/SnO2 nanowire interface and the ions are gradually returned after the pulse is removed, which can induce a dynamic excitatory postsynaptic current in the nanowire channel. The SnO2 synaptic transistors exhibit the behavior of short-term plasticity like the paired-pulse facilitation and self-adaptation, which is related to the electric double-effect regulation. In addition, the synaptic logic functions and the logical function transformation are also discussed. Such single SnO2 nanowire-based synaptic transistors are of great importance for future neuromorphic devices.

Field dependence of interface-trap buildup in polysilicon and metal gate MOS devices

NASA Astrophysics Data System (ADS)

Shaneyfelt, M. R.; Schwank, J. R.; Fleetwood, D. M.; Winokur, P. S.; Hughes, K. L.

1990-12-01

The electric field dependence of radiation-induced oxide- and interface-trap charge (Delta Vot and Delta Vit) generation for polysilicon- and metal-gate MOS transistors is investigated at electric fields (Eox) from -4.2 MV/cm to +4.7 MV/cm. If electron-hole recombination effects are taken into account, the absolute value of Delta Vot and the saturated value of Delta Vit for both polysilicon- and metal-gate transistors are shown to follow an approximate E exp -1/2 field dependence for Eox = 0.4 MV/cm or greater. An E exp -1/2 dependence for the saturated value of Delta Vit was also observed for negative-bias irradiation followed by a constant positive-bias anneal. The E exp -1/2 field dependence observed suggests that the total number of interface traps created in these devices may be determined by hole trapping near the Si/SiO2 interface for positive-bias irradiation or near the gate/SiO2 interface for negative bias irradiation, though H+ drift remains the likely rate-limiting step in the process. Based on these results, a hole-trapping/hydrogen transport model-involving hole trapping and subsequent near-interfacial H+ release, transport, and reaction at the interface-is proposed as a possible explanation of Delta Vit buildup in these polysilicon- and metal-gate transistors.

Temperature dependence of frequency response characteristics in organic field-effect transistors

NASA Astrophysics Data System (ADS)

Lu, Xubing; Minari, Takeo; Liu, Chuan; Kumatani, Akichika; Liu, J.-M.; Tsukagoshi, Kazuhito

2012-04-01

The frequency response characteristics of semiconductor devices play an essential role in the high-speed operation of electronic devices. We investigated the temperature dependence of dynamic characteristics in pentacene-based organic field-effect transistors and metal-insulator-semiconductor capacitors. As the temperature decreased, the capacitance-voltage characteristics showed large frequency dispersion and a negative shift in the flat-band voltage at high frequencies. The cutoff frequency shows Arrhenius-type temperature dependence with different activation energy values for various gate voltages. These phenomena demonstrate the effects of charge trapping on the frequency response characteristics, since decreased mobility prevents a fast charge response for alternating current signals at low temperatures.

Large-signal model of the bilayer graphene field-effect transistor targeting radio-frequency applications: Theory versus experiment

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pasadas, Francisco, E-mail: Francisco.Pasadas@uab.cat; Jiménez, David

2015-12-28

Bilayer graphene is a promising material for radio-frequency transistors because its energy gap might result in a better current saturation than the monolayer graphene. Because the great deal of interest in this technology, especially for flexible radio-frequency applications, gaining control of it requires the formulation of appropriate models for the drain current, charge, and capacitance. In this work, we have developed them for a dual-gated bilayer graphene field-effect transistor. A drift-diffusion mechanism for the carrier transport has been considered coupled with an appropriate field-effect model taking into account the electronic properties of the bilayer graphene. Extrinsic resistances have been includedmore » considering the formation of a Schottky barrier at the metal-bilayer graphene interface. The proposed model has been benchmarked against experimental prototype transistors, discussing the main figures of merit targeting radio-frequency applications.« less

High-performance, low-operating voltage, and solution-processable organic field-effect transistor with silk fibroin as the gate dielectric

DOE Office of Scientific and Technical Information (OSTI.GOV)

Shi, Leilei; Xu, Xinjun, E-mail: xuxj@mater.ustb.edu.cn, E-mail: lidong@mater.ustb.edu.cn; Ma, Mingchao

2014-01-13

We report the use of silk fibroin as the gate dielectric material in solution-processed organic field-effect transistors (OFETs) with poly(3-hexylthiophene) (P3HT) as the semiconducting layer. Such OFETs exhibit a low threshold of −0.77 V and a low-operating voltage (0 to −3 V) compatible with the voltage level commonly-used in current electronic industry. The carrier mobility of such OFETs is as high as 0.21 cm{sup 2} V{sup −1} s{sup −1} in the saturation regime, comparable to the best value of P3HT-based OFETs with dielectric layer that is not solution-processed. The high-performance of this kind of OFET is related with the high contentmore » of β strands in fibroin dielectric which leads to an array of fibers in a highly ordered structure, thus reducing the trapping sites at the semiconductor/dielectric interface.« less

Enhanced performance of solution-processed organic thin-film transistors with a low-temperature-annealed alumina interlayer between the polyimide gate insulator and the semiconductor.

PubMed

Yoon, Jun-Young; Jeong, Sunho; Lee, Sun Sook; Kim, Yun Ho; Ka, Jae-Won; Yi, Mi Hye; Jang, Kwang-Suk

2013-06-12

We studied a low-temperature-annealed sol-gel-derived alumina interlayer between the organic semiconductor and the organic gate insulator for high-performance organic thin-film transistors. The alumina interlayer was deposited on the polyimide gate insulator by a simple spin-coating and 200 °C-annealing process. The leakage current density decreased by the interlayer deposition: at 1 MV/cm, the leakage current densities of the polyimide and the alumina/polyimide gate insulators were 7.64 × 10(-7) and 3.01 × 10(-9) A/cm(2), respectively. For the first time, enhancement of the organic thin-film transistor performance by introduction of an inorganic interlayer between the organic semiconductor and the organic gate insulator was demonstrated: by introducing the interlayer, the field-effect mobility of the solution-processed organic thin-film transistor increased from 0.35 ± 0.15 to 1.35 ± 0.28 cm(2)/V·s. Our results suggest that inorganic interlayer deposition could be a simple and efficient surface treatment of organic gate insulators for enhancing the performance of solution-processed organic thin-film transistors.

Fabrication and analysis of polymer field-effect transistors

NASA Astrophysics Data System (ADS)

Scheinert, S.; Paasch, G.

2004-05-01

Parameters of organic field-effect transistors (OFET) achieved in recent years are promising enough for R & D activities towards a commercial low-cost polymer electronics. In spite of the fast progress, preparations dominated by trial and error are concentrated essentially on higher mobility polymers and shorter channel patterning, and the analysis of measured data is based on oversimplified models. Here ways to professionalize the research on polymer field-effect transistors are discussed exploiting experience accumulated in microelectronics. First of all, designing the devices before fabricating and subsequently analyzing them requires appropriate modelling. Almost independently from the nature of the transport process, the device physics is basically described by the drift-diffusion model, combined with non-degenerate carrier statistics. Therefore, with a modified interpretation of the so-called effective density of states, existing simulation tools can be applied, except for special cases which are discussed. Analytical estimates are helpful already in designing devices, and applied to experimental data they yield input parameters for the numerical simulations. Preparations of OFET's and capacitors with poly(3-ocylthiophene) (P3OT), poly(3-dodecylthiophene) P3HT, Arylamino-poly-(phenylene-vinylene) (PPV), poly(2-methoxy, 5 ethyl (2 hexyloxy) paraphenylenevinylene) MEH-PPV, and pentacene from a soluble precursor are described, with silicon dioxide (SiO2) or poly(4-vinylphenol) (P4VP) as gate insulator, and with rather different channel length. We demonstrate the advantage of combining all steps from design/fabrication to analysis of the experimental data with analytical estimates and numerical simulation. Of special importance is the connection between mobility, transistor channel length, cut-off frequency and operation voltage, which was the starting point for the development of a low-cost fabrication of high-performance submicrometer OFET's by an underetching

Advanced insulated gate bipolar transistor gate drive

DOEpatents

Short, James Evans [Monongahela, PA; West, Shawn Michael [West Mifflin, PA; Fabean, Robert J [Donora, PA

2009-08-04

A gate drive for an insulated gate bipolar transistor (IGBT) includes a control and protection module coupled to a collector terminal of the IGBT, an optical communications module coupled to the control and protection module, a power supply module coupled to the control and protection module and an output power stage module with inputs coupled to the power supply module and the control and protection module, and outputs coupled to a gate terminal and an emitter terminal of the IGBT. The optical communications module is configured to send control signals to the control and protection module. The power supply module is configured to distribute inputted power to the control and protection module. The control and protection module outputs on/off, soft turn-off and/or soft turn-on signals to the output power stage module, which, in turn, supplies a current based on the signal(s) from the control and protection module for charging or discharging an input capacitance of the IGBT.

Negative differential transconductance in silicon quantum well metal-oxide-semiconductor field effect/bipolar hybrid transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Naquin, Clint; Lee, Mark; Edwards, Hal

2014-11-24

Introducing explicit quantum transport into Si transistors in a manner amenable to industrial fabrication has proven challenging. Hybrid field-effect/bipolar Si transistors fabricated on an industrial 45 nm process line are shown to demonstrate explicit quantum transport signatures. These transistors incorporate a lateral ion implantation-defined quantum well (QW) whose potential depth is controlled by a gate voltage (V{sub G}). Quantum transport in the form of negative differential transconductance (NDTC) is observed to temperatures >200 K. The NDTC is tied to a non-monotonic dependence of bipolar current gain on V{sub G} that reduces drain-source current through the QW. These devices establish the feasibility ofmore » exploiting quantum transport to transform the performance horizons of Si devices fabricated in an industrially scalable manner.« less

Tunnel Field-Effect Transistors in 2-D Transition Metal Dichalcogenide Materials

NASA Astrophysics Data System (ADS)

Ilatikhameneh, Hesameddin; Tan, Yaohua; Novakovic, Bozidar; Klimeck, Gerhard; Rahman, Rajib; Appenzeller, Joerg

2015-12-01

In this work, the performance of Tunnel Field-Effect Transistors (TFETs) based on two-dimensional Transition Metal Dichalcogenide (TMD) materials is investigated by atomistic quantum transport simulations. One of the major challenges of TFETs is their low ON-currents. 2D material based TFETs can have tight gate control and high electric fields at the tunnel junction, and can in principle generate high ON-currents along with a sub-threshold swing smaller than 60 mV/dec. Our simulations reveal that high performance TMD TFETs, not only require good gate control, but also rely on the choice of the right channel material with optimum band gap, effective mass and source/drain doping level. Unlike previous works, a full band atomistic tight binding method is used self-consistently with 3D Poisson equation to simulate ballistic quantum transport in these devices. The effect of the choice of TMD material on the performance of the device and its transfer characteristics are discussed. Moreover, the criteria for high ON-currents are explained with a simple analytic model, showing the related fundamental factors. Finally, the subthreshold swing and energy-delay of these TFETs are compared with conventional CMOS devices.

Pinch-off mechanism in double-lateral-gate junctionless transistors fabricated by scanning probe microscope based lithography

PubMed Central

Dehzangi, Arash; Abedini, Alam; Abdullah, Ahmad Makarimi; Saion, Elias; Hutagalung, Sabar D; Hamidon, Mohd N; Hassan, Jumiah

2012-01-01

Summary A double-lateral-gate p-type junctionless transistor is fabricated on a low-doped (1015) silicon-on-insulator wafer by a lithography technique based on scanning probe microscopy and two steps of wet chemical etching. The experimental transfer characteristics are obtained and compared with the numerical characteristics of the device. The simulation results are used to investigate the pinch-off mechanism, from the flat band to the off state. The study is based on the variation of the carrier density and the electric-field components. The device is a pinch-off transistor, which is normally in the on state and is driven into the off state by the application of a positive gate voltage. We demonstrate that the depletion starts from the bottom corner of the channel facing the gates and expands toward the center and top of the channel. Redistribution of the carriers due to the electric field emanating from the gates creates an electric field perpendicular to the current, toward the bottom of the channel, which provides the electrostatic squeezing of the current. PMID:23365794

Effects of HfO2/Al2O3 gate stacks on electrical performance of planar In x Ga1- x As tunneling field-effect transistors

NASA Astrophysics Data System (ADS)

Ahn, Dae-Hwan; Yoon, Sang-Hee; Takenaka, Mitsuru; Takagi, Shinichi

2017-08-01

We study the impact of gate stacks on the electrical characteristics of Zn-diffused source In x Ga1- x As tunneling field-effect transistors (TFETs) with Al2O3 or HfO2/Al2O3 gate insulators. Ta and W gate electrodes are compared in terms of the interface trap density (D it) of InGaAs MOS interfaces. It is found that D it is lower at the W/HfO2/Al2O3 InGaAs MOS interface than at the Ta/HfO2/Al2O3 interface. The In0.53Ga0.47As TFET with a W/HfO2 (2.7 nm)/Al2O3 (0.3 nm) gate stack of 1.4-nm-thick capacitance equivalent thickness (CET) has a steep minimum subthreshold swing (SS) of 57 mV/dec, which is attributed to the thin CET and low D it. Also, the In0.53Ga0.47As (2.6 nm)/In0.67Ga0.33As (3.2 nm)/In0.53Ga0.47As (96.5 nm) quantum-well (QW) TFET supplemented with this 1.4-nm-thick CET gate stack exhibits a steeper minimum SS of 54 mV/dec and a higher on-current (I on) than those of the In0.53Ga0.47As TFET.

Tunnel field-effect transistor charge-trapping memory with steep subthreshold slope and large memory window

NASA Astrophysics Data System (ADS)

Kino, Hisashi; Fukushima, Takafumi; Tanaka, Tetsu

2018-04-01

Charge-trapping memory requires the increase of bit density per cell and a larger memory window for lower-power operation. A tunnel field-effect transistor (TFET) can achieve to increase the bit density per cell owing to its steep subthreshold slope. In addition, a TFET structure has an asymmetric structure, which is promising for achieving a larger memory window. A TFET with the N-type gate shows a higher electric field between the P-type source and the N-type gate edge than the conventional FET structure. This high electric field enables large amounts of charges to be injected into the charge storage layer. In this study, we fabricated silicon-oxide-nitride-oxide-semiconductor (SONOS) memory devices with the TFET structure and observed a steep subthreshold slope and a larger memory window.

Investigation of terbium scandate as an alternative gate dielectric in fully depleted transistors

NASA Astrophysics Data System (ADS)

Roeckerath, M.; Lopes, J. M. J.; Özben, E. Durǧun; Urban, C.; Schubert, J.; Mantl, S.; Jia, Y.; Schlom, D. G.

2010-01-01

Terbium scandate thin films were deposited by e-gun evaporation on (100) silicon substrates. Rutherford backscattering spectrometry and x-ray diffraction studies revealed homogeneous chemical compositions of the films. A dielectric constant of 26 and CV-curves with small hystereses were measured as well as low leakage current densities of <1 nA/cm2. Fully depleted n-type field-effect transistors on thin silicon-on-insulator substrates with terbium scandate gate dielectrics were fabricated with a gate-last process. The devices show inverse subthreshold slopes of 80 mV/dec and a carrier mobility for electrons of 225 cm2/V•s was extracted.

Organic Field Effect Transistors for Large Format Electronics

DTIC Science & Technology

2003-06-19

calculated output characteristics for a p-channel substrate insulator Organic layer Source Drain Gate 6 pentacene OFET with 2µm source to drain spacing...conventional transistors. Figure 3. Calculated output characteristics of a pentacene OFET with image charge induced contact barrier...Cross section view of a part of an OFET in the vicinity of a source or drain contact. local ordering due to surface energy effects. The development of

Enzyme-polyelectrolyte multilayer assemblies on reduced graphene oxide field-effect transistors for biosensing applications.

PubMed

Piccinini, Esteban; Bliem, Christina; Reiner-Rozman, Ciril; Battaglini, Fernando; Azzaroni, Omar; Knoll, Wolfgang

2017-06-15

We present the construction of layer-by-layer (LbL) assemblies of polyethylenimine and urease onto reduced-graphene-oxide based field-effect transistors (rGO FETs) for the detection of urea. This versatile biosensor platform simultaneously exploits the pH dependency of liquid-gated graphene-based transistors and the change in the local pH produced by the catalyzed hydrolysis of urea. The use of an interdigitated microchannel resulted in transistors displaying low noise, high pH sensitivity (20.3µA/pH) and transconductance values up to 800 µS. The modification of rGO FETs with a weak polyelectrolyte improved the pH response because of its transducing properties by electrostatic gating effects. In the presence of urea, the urease-modified rGO FETs showed a shift in the Dirac point due to the change in the local pH close to the graphene surface. Markedly, these devices operated at very low voltages (less than 500mV) and were able to monitor urea in the range of 1-1000µm, with a limit of detection (LOD) down to 1µm, fast response and good long-term stability. The urea-response of the transistors was enhanced by increasing the number of bilayers due to the increment of the enzyme surface coverage onto the channel. Moreover, quantification of the heavy metal Cu 2+ (with a LOD down to 10nM) was performed in aqueous solution by taking advantage of the urease specific inhibition. Copyright © 2016 The Authors. Published by Elsevier B.V. All rights reserved.

In situ monitoring of myenteric neuron activity using acetylcholinesterase-modified AlGaN/GaN solution-gate field-effect transistors.

PubMed

Müntze, Gesche Mareike; Pouokam, Ervice; Steidle, Julia; Schäfer, Wladimir; Sasse, Alexander; Röth, Kai; Diener, Martin; Eickhoff, Martin

2016-03-15

The response characteristics of acetylcholinesterase-modified AlGaN/GaN solution-gate field-effect transistors (AcFETs) are quantitatively analyzed by means of a kinetic model. The characterization shows that the covalent enzyme immobilization process yields reproducible AcFET characteristics with a Michaelis constant KM of (122 ± 4) μM for the immobilized enzyme layer. The increase of KM by a factor of 2.4 during the first four measurement cycles is attributed to partial denaturation of the enzyme. The AcFETs were used to record the release of acetylcholine (ACh) by neuronal tissue cultivated on the gate area upon stimulation by rising the extracellular K(+) concentration. The neuronal tissue constituted of isolated myenteric neurons from four to 12 days old Wistar rats, or sections from the muscularis propria containing the myenteric plexus from adult rats. For both cases the AcFET response was demonstrated to be related to the activity of the immobilized acetylcholinesterase using the reversible acetylcholinesterase blocker donepezil. A concentration response curve of this blocking agent revealed a half maximal inhibitory concentration of 40 nM which is comparable to values measured by complementary in vitro methods. Copyright © 2015 Elsevier B.V. All rights reserved.

Effect of top gate potential on bias-stress for dual gate amorphous indium-gallium-zinc-oxide thin film transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chun, Minkyu; Um, Jae Gwang; Park, Min Sang

We report the abnormal behavior of the threshold voltage (V{sub TH}) shift under positive bias Temperature stress (PBTS) and negative bias temperature stress (NBTS) at top/bottom gate in dual gate amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs). It is found that the PBTS at top gate shows negative transfer shift and NBTS shows positive transfer shift for both top and bottom gate sweep. The shift of bottom/top gate sweep is dominated by top gate bias (V{sub TG}), while bottom gate bias (V{sub BG}) is less effect than V{sub TG}. The X-ray photoelectron spectroscopy (XPS) depth profile provides the evidence of Inmore » metal diffusion to the top SiO{sub 2}/a-IGZO and also the existence of large amount of In{sup +} under positive top gate bias around top interfaces, thus negative transfer shift is observed. On the other hand, the formation of OH{sup −} at top interfaces under the stress of negative top gate bias shows negative transfer shift. The domination of V{sub TG} both on bottom/top gate sweep after PBTS/NBTS is obviously occurred due to thin active layer.« less