Digital microfluidics: Droplet based logic gates

NASA Astrophysics Data System (ADS)

Cheow, Lih Feng; Yobas, Levent; Kwong, Dim-Lee

2007-01-01

The authors present microfluidic logic gates based on two-phase flows at low Reynold's number. The presence and the absence of a dispersed phase liquid (slug) in a continuous phase liquid represent 1 and 0, respectively. The working principle of these devices is based on the change in hydrodynamic resistance for a channel containing droplets. Logical operations including AND, OR, and NOT are demonstrated, and may pave the way for microfludic system automation and computation.

Separating Business Logic from Medical Knowledge in Digital Clinical Workflows Using Business Process Model and Notation and Arden Syntax.

PubMed

de Bruin, Jeroen S; Adlassnig, Klaus-Peter; Leitich, Harald; Rappelsberger, Andrea

2018-01-01

Evidence-based clinical guidelines have a major positive effect on the physician's decision-making process. Computer-executable clinical guidelines allow for automated guideline marshalling during a clinical diagnostic process, thus improving the decision-making process. Implementation of a digital clinical guideline for the prevention of mother-to-child transmission of hepatitis B as a computerized workflow, thereby separating business logic from medical knowledge and decision-making. We used the Business Process Model and Notation language system Activiti for business logic and workflow modeling. Medical decision-making was performed by an Arden-Syntax-based medical rule engine, which is part of the ARDENSUITE software. We succeeded in creating an electronic clinical workflow for the prevention of mother-to-child transmission of hepatitis B, where institution-specific medical decision-making processes could be adapted without modifying the workflow business logic. Separation of business logic and medical decision-making results in more easily reusable electronic clinical workflows.

Digital design using selection operations

NASA Technical Reports Server (NTRS)

Miles, Lowell H. (Inventor); Whitaker, Sterling R. (Inventor); Cameron, Eric G. (Inventor)

2004-01-01

A digital integrated circuit chip is designed by identifying a logical structure to be implemented. This logical structure is represented in terms of a logical operations, at least 5% of which include selection operations. A determination is made of logic cells that correspond to an implementation of these logical operations.

Digital logic circuit based on two component molecular systems of BSA and salen

NASA Astrophysics Data System (ADS)

Hai-Bin, Lin; Feng, Chen; Hong-Xu, Guo

2018-02-01

A new fluorescent molecular probe 1 was designed and constructed by combining bovine serum albumin (BSA) and N,N‧-bis(salicylidene)ethylenediamine (salen). Stimulated by Zn2 +, tris, or EDTAH2Na2, the distance between BSA and salen was regulated, which was accompanied by an obvious change in the fluorescence intensity at 350 or 445 nm based on Förster resonance energy transfer. Moreover, based on the encoding binary digits in these inputs and outputs applying positive logic conventions, a monomolecular circuit integrating one OR, three NOT, and three YES gates, was successfully achieved.

A behavioral-level HDL description of SFQ logic circuits for quantitative performance analysis of large-scale SFQ digital systems

NASA Astrophysics Data System (ADS)

Matsuzaki, F.; Yoshikawa, N.; Tanaka, M.; Fujimaki, A.; Takai, Y.

2003-10-01

Recently many single flux quantum (SFQ) logic circuits containing several thousands of Josephson junctions have been designed successfully by using digital domain simulation based on the hard ware description language (HDL). In the present HDL-based design of SFQ circuits, a structure-level HDL description has been used, where circuits are made up of basic gate cells. However, in order to analyze large-scale SFQ digital systems, such as a microprocessor, more higher-level circuit abstraction is necessary to reduce the circuit simulation time. In this paper we have investigated the way to describe functionality of the large-scale SFQ digital circuits by a behavior-level HDL description. In this method, the functionality and the timing of the circuit block is defined directly by describing their behavior by the HDL. Using this method, we can dramatically reduce the simulation time of large-scale SFQ digital circuits.

Magnon-based logic in a multi-terminal YIG/Pt nanostructure

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ganzhorn, Kathrin, E-mail: kathrin.ganzhorn@wmi.badw.de; Klingler, Stefan; Wimmer, Tobias

2016-07-11

Boolean logic is the foundation of modern digital information processing. Recently, there has been a growing interest in phenomena based on pure spin currents, which allows to move from charge to spin based logic gates. We study a proof-of-principle logic device based on the ferrimagnetic insulator Yttrium Iron Garnet, with Pt strips acting as injectors and detectors for non-equilibrium magnons. We experimentally observe incoherent superposition of magnons generated by different injectors. This allows to implement a fully functional majority gate, enabling multiple logic operations (AND and OR) in one and the same device. Clocking frequencies of the order of severalmore » GHz and straightforward down-scaling make our device promising for applications.« less

Programmable Pulser

NASA Technical Reports Server (NTRS)

Baumann, Eric; Merolla, Anthony

1988-01-01

User controls number of clock pulses to prevent burnout. New digital programmable pulser circuit in three formats; freely running, counted, and single pulse. Operates at frequencies up to 5 MHz, with no special consideration given to layout of components or to terminations. Pulser based on sequential circuit with four states and binary counter with appropriate decoding logic. Number of programmable pulses increased beyond 127 by addition of another counter and decoding logic. For very large pulse counts and/or very high frequencies, use synchronous counters to avoid errors caused by propagation delays. Invaluable tool for initial verification or diagnosis of digital or digitally controlled circuity.

Fundamentals of Digital Logic.

ERIC Educational Resources Information Center

Noell, Monica L.

This course is designed to prepare electronics personnel for further training in digital techniques, presenting need to know information that is basic to any maintenance course on digital equipment. It consists of seven study units: (1) binary arithmetic; (2) boolean algebra; (3) logic gates; (4) logic flip-flops; (5) nonlogic circuits; (6)…

Engineering modular and orthogonal genetic logic gates for robust digital-like synthetic biology.

PubMed

Wang, Baojun; Kitney, Richard I; Joly, Nicolas; Buck, Martin

2011-10-18

Modular and orthogonal genetic logic gates are essential for building robust biologically based digital devices to customize cell signalling in synthetic biology. Here we constructed an orthogonal AND gate in Escherichia coli using a novel hetero-regulation module from Pseudomonas syringae. The device comprises two co-activating genes hrpR and hrpS controlled by separate promoter inputs, and a σ(54)-dependent hrpL promoter driving the output. The hrpL promoter is activated only when both genes are expressed, generating digital-like AND integration behaviour. The AND gate is demonstrated to be modular by applying new regulated promoters to the inputs, and connecting the output to a NOT gate module to produce a combinatorial NAND gate. The circuits were assembled using a parts-based engineering approach of quantitative characterization, modelling, followed by construction and testing. The results show that new genetic logic devices can be engineered predictably from novel native orthogonal biological control elements using quantitatively in-context characterized parts. © 2011 Macmillan Publishers Limited. All rights reserved.

Synthesizing genetic sequential logic circuit with clock pulse generator.

PubMed

Chuang, Chia-Hua; Lin, Chun-Liang

2014-05-28

Rhythmic clock widely occurs in biological systems which controls several aspects of cell physiology. For the different cell types, it is supplied with various rhythmic frequencies. How to synthesize a specific clock signal is a preliminary but a necessary step to further development of a biological computer in the future. This paper presents a genetic sequential logic circuit with a clock pulse generator based on a synthesized genetic oscillator, which generates a consecutive clock signal whose frequency is an inverse integer multiple to that of the genetic oscillator. An analogous electronic waveform-shaping circuit is constructed by a series of genetic buffers to shape logic high/low levels of an oscillation input in a basic sinusoidal cycle and generate a pulse-width-modulated (PWM) output with various duty cycles. By controlling the threshold level of the genetic buffer, a genetic clock pulse signal with its frequency consistent to the genetic oscillator is synthesized. A synchronous genetic counter circuit based on the topology of the digital sequential logic circuit is triggered by the clock pulse to synthesize the clock signal with an inverse multiple frequency to the genetic oscillator. The function acts like a frequency divider in electronic circuits which plays a key role in the sequential logic circuit with specific operational frequency. A cascaded genetic logic circuit generating clock pulse signals is proposed. Based on analogous implement of digital sequential logic circuits, genetic sequential logic circuits can be constructed by the proposed approach to generate various clock signals from an oscillation signal.

Integrated circuits and logic operations based on single-layer MoS2.

PubMed

Radisavljevic, Branimir; Whitwick, Michael Brian; Kis, Andras

2011-12-27

Logic circuits and the ability to amplify electrical signals form the functional backbone of electronics along with the possibility to integrate multiple elements on the same chip. The miniaturization of electronic circuits is expected to reach fundamental limits in the near future. Two-dimensional materials such as single-layer MoS(2) represent the ultimate limit of miniaturization in the vertical dimension, are interesting as building blocks of low-power nanoelectronic devices, and are suitable for integration due to their planar geometry. Because they are less than 1 nm thin, 2D materials in transistors could also lead to reduced short channel effects and result in fabrication of smaller and more power-efficient transistors. Here, we report on the first integrated circuit based on a two-dimensional semiconductor MoS(2). Our integrated circuits are capable of operating as inverters, converting logical "1" into logical "0", with room-temperature voltage gain higher than 1, making them suitable for incorporation into digital circuits. We also show that electrical circuits composed of single-layer MoS(2) transistors are capable of performing the NOR logic operation, the basis from which all logical operations and full digital functionality can be deduced.

Compton suppression and event triggering in a commercial data acquisition system

NASA Astrophysics Data System (ADS)

Tabor, Samuel; Caussyn, D. D.; Tripathi, Vandana; Vonmoss, J.; Liddick, S. N.

2012-10-01

A number of groups are starting to use flash digitizer systems to directly convert the preamplifier signals of high-resolution Ge detectors to a stream of digital data. Some digitizers are also equipped with software constant fraction discriminator algorithms capable of operating on the resulting digital data stream to provide timing information. Because of the dropping cost per channel of these systems, it should now be possible to also connect outputs of the Bismuth Germanate (BGO) scintillators used for Compton suppression to other digitizer inputs so that BGO logic signals can also be available in the same system. This provides the possibility to perform all the Compton suppression and multiplicity trigger logic within the digital system, thus eliminating the need for separate timing filter amplifiers (TFA), constant fraction discriminators (CFD), logic units, and lots of cables. This talk will describe the performance of such a system based on Pixie16 modules from XIA LLC with custom field programmable gate array (FPGA) programming for an array of Compton suppressed single Ge crystal and 4-crystal ``Clover'' detector array along with optional particle detectors. Initial tests of the system have produced results comparable with the current traditional system of individual electronics and peak sensing analog to digital converters. The advantages of the all digital system will be discussed.

Synthetic mixed-signal computation in living cells

PubMed Central

Rubens, Jacob R.; Selvaggio, Gianluca; Lu, Timothy K.

2016-01-01

Living cells implement complex computations on the continuous environmental signals that they encounter. These computations involve both analogue- and digital-like processing of signals to give rise to complex developmental programs, context-dependent behaviours and homeostatic activities. In contrast to natural biological systems, synthetic biological systems have largely focused on either digital or analogue computation separately. Here we integrate analogue and digital computation to implement complex hybrid synthetic genetic programs in living cells. We present a framework for building comparator gene circuits to digitize analogue inputs based on different thresholds. We then demonstrate that comparators can be predictably composed together to build band-pass filters, ternary logic systems and multi-level analogue-to-digital converters. In addition, we interface these analogue-to-digital circuits with other digital gene circuits to enable concentration-dependent logic. We expect that this hybrid computational paradigm will enable new industrial, diagnostic and therapeutic applications with engineered cells. PMID:27255669

Quantum-classical interface based on single flux quantum digital logic

NASA Astrophysics Data System (ADS)

McDermott, R.; Vavilov, M. G.; Plourde, B. L. T.; Wilhelm, F. K.; Liebermann, P. J.; Mukhanov, O. A.; Ohki, T. A.

2018-04-01

We describe an approach to the integrated control and measurement of a large-scale superconducting multiqubit array comprising up to 108 physical qubits using a proximal coprocessor based on the Single Flux Quantum (SFQ) digital logic family. Coherent control is realized by irradiating the qubits directly with classical bitstreams derived from optimal control theory. Qubit measurement is performed by a Josephson photon counter, which provides access to the classical result of projective quantum measurement at the millikelvin stage. We analyze the power budget and physical footprint of the SFQ coprocessor and discuss challenges and opportunities associated with this approach.

Analog-digital simulation of transient-induced logic errors and upset susceptibility of an advanced control system

NASA Technical Reports Server (NTRS)

Carreno, Victor A.; Choi, G.; Iyer, R. K.

1990-01-01

A simulation study is described which predicts the susceptibility of an advanced control system to electrical transients resulting in logic errors, latched errors, error propagation, and digital upset. The system is based on a custom-designed microprocessor and it incorporates fault-tolerant techniques. The system under test and the method to perform the transient injection experiment are described. Results for 2100 transient injections are analyzed and classified according to charge level, type of error, and location of injection.

Digitized synchronous demodulator

NASA Technical Reports Server (NTRS)

Woodhouse, Christopher E. (Inventor)

1990-01-01

A digitized synchronous demodulator is constructed entirely of digital components including timing logic, an accumulator, and means to digitally filter the digital output signal. Indirectly, it accepts, at its input, periodic analog signals which are converted to digital signals by traditional analog-to-digital conversion techniques. Broadly, the input digital signals are summed to one of two registers within an accumulator, based on the phase of the input signal and medicated by timing logic. At the end of a predetermined number of cycles of the inputted periodic signals, the contents of the register that accumulated samples from the negative half cycle is subtracted from the accumulated samples from the positive half cycle. The resulting difference is an accurate measurement of the narrow band amplitude of the periodic input signal during the measurement period. This measurement will not include error sources encountered in prior art synchronous demodulators using analog techniques such as offsets, charge injection errors, temperature drift, switching transients, settling time, analog to digital converter missing code, and linearity errors.

Simulated Laboratory in Digital Logic.

ERIC Educational Resources Information Center

Cleaver, Thomas G.

Design of computer circuits used to be a pencil and paper task followed by laboratory tests, but logic circuit design can now be done in half the time as the engineer accesses a program which simulates the behavior of real digital circuits, and does all the wiring and testing on his computer screen. A simulated laboratory in digital logic has been…

SDLDS--System for Digital Logic Design and Simulation

ERIC Educational Resources Information Center

Stanisavljevic, Z.; Pavlovic, V.; Nikolic, B.; Djordjevic, J.

2013-01-01

This paper presents the basic features of a software system developed to support the teaching of digital logic, as well as the experience of using it in the Digital Logic course taught at the School of Electrical Engineering, University of Belgrade, Serbia. The system has been used for several years, both by students for self-learning and…

A Multi-Discipline, Multi-Genre Digital Library for Research and Education

NASA Technical Reports Server (NTRS)

Nelson, Michael L.; Maly, Kurt; Shen, Stewart N. T.

2004-01-01

We describe NCSTRL+, a unified, canonical digital library for educational and scientific and technical information (STI). NCSTRL+ is based on the Networked Computer Science Technical Report Library (NCSTRL), a World Wide Web (WWW) accessible digital library (DL) that provides access to over 100 university departments and laboratories. NCSTRL+ implements two new technologies: cluster functionality and publishing "buckets". We have extended the Dienst protocol, the protocol underlying NCSTRL, to provide the ability to "cluster" independent collections into a logically centralized digital library based upon subject category classification, type of organization, and genres of material. The concept of "buckets" provides a mechanism for publishing and managing logically linked entities with multiple data formats. The NCSTRL+ prototype DL contains the holdings of NCSTRL and the NASA Technical Report Server (NTRS). The prototype demonstrates the feasibility of publishing into a multi-cluster DL, searching across clusters, and storing and presenting buckets of information.

Demonstration of an optoelectronic interconnect architecture for a parallel modified signed-digit adder and subtracter

NASA Astrophysics Data System (ADS)

Sun, Degui; Wang, Na-Xin; He, Li-Ming; Weng, Zhao-Heng; Wang, Daheng; Chen, Ray T.

1996-06-01

A space-position-logic-encoding scheme is proposed and demonstrated. This encoding scheme not only makes the best use of the convenience of binary logic operation, but is also suitable for the trinary property of modified signed- digit (MSD) numbers. Based on the space-position-logic-encoding scheme, a fully parallel modified signed-digit adder and subtractor is built using optoelectronic switch technologies in conjunction with fiber-multistage 3D optoelectronic interconnects. Thus an effective combination of a parallel algorithm and a parallel architecture is implemented. In addition, the performance of the optoelectronic switches used in this system is experimentally studied and verified. Both the 3-bit experimental model and the experimental results of a parallel addition and a parallel subtraction are provided and discussed. Finally, the speed ratio between the MSD adder and binary adders is discussed and the advantage of the MSD in operating speed is demonstrated.

The effect of prior education on students' competency in digital logic: the case of ultraorthodox Jewish students

NASA Astrophysics Data System (ADS)

Ben-David Kolikant, Yifat; Genut, Sara

2017-10-01

In line with the growing interest in extending the diversity of CS students, we examined the performance of a unique group of students studying an introductory course in Digital logic: ultraorthodox Jewish men, whose previous education was based mostly on studying Talmud and who lacked a conventional high-school education. We used questions from the Digital Logic Concept Inventory . We compared the results to those of religious Jewish men with a conventional high-school education, and to the results reported in the literature. The ultraorthodox group performed better than the other groups in tasks that concerned number representation. No other statistically significant differences were found. Talk-aloud protocols revealed that the ultraorthodox students utilized a viable conceptual understanding in their performance. We can conclude that students' unique, alternative prior education should not be merely viewed as an obstacle to their academic studies, but also as a potential source for strengths.

Synthesizing genetic sequential logic circuit with clock pulse generator

PubMed Central

2014-01-01

Background Rhythmic clock widely occurs in biological systems which controls several aspects of cell physiology. For the different cell types, it is supplied with various rhythmic frequencies. How to synthesize a specific clock signal is a preliminary but a necessary step to further development of a biological computer in the future. Results This paper presents a genetic sequential logic circuit with a clock pulse generator based on a synthesized genetic oscillator, which generates a consecutive clock signal whose frequency is an inverse integer multiple to that of the genetic oscillator. An analogous electronic waveform-shaping circuit is constructed by a series of genetic buffers to shape logic high/low levels of an oscillation input in a basic sinusoidal cycle and generate a pulse-width-modulated (PWM) output with various duty cycles. By controlling the threshold level of the genetic buffer, a genetic clock pulse signal with its frequency consistent to the genetic oscillator is synthesized. A synchronous genetic counter circuit based on the topology of the digital sequential logic circuit is triggered by the clock pulse to synthesize the clock signal with an inverse multiple frequency to the genetic oscillator. The function acts like a frequency divider in electronic circuits which plays a key role in the sequential logic circuit with specific operational frequency. Conclusions A cascaded genetic logic circuit generating clock pulse signals is proposed. Based on analogous implement of digital sequential logic circuits, genetic sequential logic circuits can be constructed by the proposed approach to generate various clock signals from an oscillation signal. PMID:24884665

Nonlinear dynamics based digital logic and circuits.

PubMed

Kia, Behnam; Lindner, John F; Ditto, William L

2015-01-01

We discuss the role and importance of dynamics in the brain and biological neural networks and argue that dynamics is one of the main missing elements in conventional Boolean logic and circuits. We summarize a simple dynamics based computing method, and categorize different techniques that we have introduced to realize logic, functionality, and programmability. We discuss the role and importance of coupled dynamics in networks of biological excitable cells, and then review our simple coupled dynamics based method for computing. In this paper, for the first time, we show how dynamics can be used and programmed to implement computation in any given base, including but not limited to base two.

Superconducting flux flow digital circuits

DOE Office of Scientific and Technical Information (OSTI.GOV)

Martens, J.S.; Zipperian, T.E.; Hietala, V.M.

1993-03-01

The authors have developed a family of digital logic circuits based on superconducting flux flow transistors that show high speed, reasonable signal levels, large fan-out, and large noise margins. The circuits are made from high-temperature superconductors (HTS) and have been shown to operate at over 90 K. NOR gates have been demonstrated with fan-outs of more than 5 and fully loaded switching times less than a fixture-limited 50 ps. Ring-oscillator data suggest inverter delay times of about 40ps when using a 3-[mu]m linewidths. Simple flip-flops have also been demonstrated showing large noise margins, response times of less than 30 ps,more » and static power dissipation on the order of 30 nW. Among other uses, this logic family is appropriate as an interface between logic families such as single flux quantum and conventional semiconductor logic.« less

Digital Holographic Logic

NASA Technical Reports Server (NTRS)

Preston, K., Jr.

1972-01-01

The characteristics of the holographic logic computer are discussed. The holographic operation is reviewed from the Fourier transform viewpoint, and the formation of holograms for use in performing digital logic are described. The operation of the computer with an experiment in which the binary identity function is calculated is discussed along with devices for achieving real-time performance. An application in pattern recognition using neighborhood logic is presented.

VLSI Implementation of Fault Tolerance Multiplier based on Reversible Logic Gate

NASA Astrophysics Data System (ADS)

Ahmad, Nabihah; Hakimi Mokhtar, Ahmad; Othman, Nurmiza binti; Fhong Soon, Chin; Rahman, Ab Al Hadi Ab

2017-08-01

Multiplier is one of the essential component in the digital world such as in digital signal processing, microprocessor, quantum computing and widely used in arithmetic unit. Due to the complexity of the multiplier, tendency of errors are very high. This paper aimed to design a 2×2 bit Fault Tolerance Multiplier based on Reversible logic gate with low power consumption and high performance. This design have been implemented using 90nm Complemetary Metal Oxide Semiconductor (CMOS) technology in Synopsys Electronic Design Automation (EDA) Tools. Implementation of the multiplier architecture is by using the reversible logic gates. The fault tolerance multiplier used the combination of three reversible logic gate which are Double Feynman gate (F2G), New Fault Tolerance (NFT) gate and Islam Gate (IG) with the area of 160μm x 420.3μm (67.25 mm2). This design achieved a low power consumption of 122.85μW and propagation delay of 16.99ns. The fault tolerance multiplier proposed achieved a low power consumption and high performance which suitable for application of modern computing as it has a fault tolerance capabilities.

Fast and robust control of nanopositioning systems: Performance limits enabled by field programmable analog arrays.

PubMed

Baranwal, Mayank; Gorugantu, Ram S; Salapaka, Srinivasa M

2015-08-01

This paper aims at control design and its implementation for robust high-bandwidth precision (nanoscale) positioning systems. Even though modern model-based control theoretic designs for robust broadband high-resolution positioning have enabled orders of magnitude improvement in performance over existing model independent designs, their scope is severely limited by the inefficacies of digital implementation of the control designs. High-order control laws that result from model-based designs typically have to be approximated with reduced-order systems to facilitate digital implementation. Digital systems, even those that have very high sampling frequencies, provide low effective control bandwidth when implementing high-order systems. In this context, field programmable analog arrays (FPAAs) provide a good alternative to the use of digital-logic based processors since they enable very high implementation speeds, moreover with cheaper resources. The superior flexibility of digital systems in terms of the implementable mathematical and logical functions does not give significant edge over FPAAs when implementing linear dynamic control laws. In this paper, we pose the control design objectives for positioning systems in different configurations as optimal control problems and demonstrate significant improvements in performance when the resulting control laws are applied using FPAAs as opposed to their digital counterparts. An improvement of over 200% in positioning bandwidth is achieved over an earlier digital signal processor (DSP) based implementation for the same system and same control design, even when for the DSP-based system, the sampling frequency is about 100 times the desired positioning bandwidth.

Army/NASA small turboshaft engine digital controls research program

NASA Technical Reports Server (NTRS)

Sellers, J. F.; Baez, A. N.

1981-01-01

The emphasis of a program to conduct digital controls research for small turboshaft engines is on engine test evaluation of advanced control logic using a flexible microprocessor based digital control system designed specifically for research on advanced control logic. Control software is stored in programmable memory. New control algorithms may be stored in a floppy disk and loaded directly into memory. This feature facilitates comparative evaluation of different advanced control modes. The central processor in the digital control is an Intel 8086 16 bit microprocessor. Control software is programmed in assembly language. Software checkout is accomplished prior to engine test by connecting the digital control to a real time hybrid computer simulation of the engine. The engine currently installed in the facility has a hydromechanical control modified to allow electrohydraulic fuel metering and VG actuation by the digital control. Simulation results are presented which show that the modern control reduces the transient rotor speed droop caused by unanticipated load changes such as cyclic pitch or wind gust transients.

Scaling up digital circuit computation with DNA strand displacement cascades.

PubMed

Qian, Lulu; Winfree, Erik

2011-06-03

To construct sophisticated biochemical circuits from scratch, one needs to understand how simple the building blocks can be and how robustly such circuits can scale up. Using a simple DNA reaction mechanism based on a reversible strand displacement process, we experimentally demonstrated several digital logic circuits, culminating in a four-bit square-root circuit that comprises 130 DNA strands. These multilayer circuits include thresholding and catalysis within every logical operation to perform digital signal restoration, which enables fast and reliable function in large circuits with roughly constant switching time and linear signal propagation delays. The design naturally incorporates other crucial elements for large-scale circuitry, such as general debugging tools, parallel circuit preparation, and an abstraction hierarchy supported by an automated circuit compiler.

Microfluidic Pneumatic Logic Circuits and Digital Pneumatic Microprocessors for Integrated Microfluidic Systems

PubMed Central

Rhee, Minsoung

2010-01-01

We have developed pneumatic logic circuits and microprocessors built with microfluidic channels and valves in polydimethylsiloxane (PDMS). The pneumatic logic circuits perform various combinational and sequential logic calculations with binary pneumatic signals (atmosphere and vacuum), producing cascadable outputs based on Boolean operations. A complex microprocessor is constructed from combinations of various logic circuits and receives pneumatically encoded serial commands at a single input line. The device then decodes the temporal command sequence by spatial parallelization, computes necessary logic calculations between parallelized command bits, stores command information for signal transportation and maintenance, and finally executes the command for the target devices. Thus, such pneumatic microprocessors will function as a universal on-chip control platform to perform complex parallel operations for large-scale integrated microfluidic devices. To demonstrate the working principles, we have built 2-bit, 3-bit, 4-bit, and 8-bit microprecessors to control various target devices for applications such as four color dye mixing, and multiplexed channel fluidic control. By significantly reducing the need for external controllers, the digital pneumatic microprocessor can be used as a universal on-chip platform to autonomously manipulate microfluids in a high throughput manner. PMID:19823730

NCSTRL+: Adding Multi-Discipline and Multi-Genre Support to the Dienst Protocol Using Clusters and Buckets

NASA Technical Reports Server (NTRS)

Nelson, Michael L.; Maly, Kurt; Shen, Stewart N. T.; Zubair, Mohammad

1998-01-01

We describe NCSTRL+, a unified, canonical digital library for scientific and technical information (STI). NCSTRL+ is based on the Networked Computer Science Technical Report Library (NCSTRL), a World Wide Web (WWW) accessible digital library (DL) that provides access to over 100 university departments and laboratories. NCSTRL+ implements two new technologies: cluster functionality and publishing buckets. We have extended Dienst, the protocol underlying NCSTRL, to provide the ability to cluster independent collections into a logically centralized digital library based upon subject category classification, type of organization, and genres of material. The bucket construct provides a mechanism for publishing and managing logically linked entities with multiple data forms as a single object. The NCSTRL+ prototype DL contains the holdings of NCSTRL and the NASA Technical Report Server (NTRS). The prototype demonstrates the feasibility of publishing into a multi-cluster DL, searching across clusters, and storing and presenting buckets of information.

Reconfigurable fuzzy cell

NASA Technical Reports Server (NTRS)

Salazar, George A. (Inventor)

1993-01-01

This invention relates to a reconfigurable fuzzy cell comprising a digital control programmable gain operation amplifier, an analog-to-digital converter, an electrically erasable PROM, and 8-bit counter and comparator, and supporting logic configured to achieve in real-time fuzzy systems high throughput, grade-of-membership or membership-value conversion of multi-input sensor data. The invention provides a flexible multiplexing-capable configuration, implemented entirely in hardware, for effectuating S-, Z-, and PI-membership functions or combinations thereof, based upon fuzzy logic level-set theory. A membership value table storing 'knowledge data' for each of S-, Z-, and PI-functions is contained within a nonvolatile memory for storing bits of membership and parametric information in a plurality of address spaces. Based upon parametric and control signals, analog sensor data is digitized and converted into grade-of-membership data. In situ learn and recognition modes of operation are also provided.

Procedure for extraction of disparate data from maps into computerized data bases

NASA Technical Reports Server (NTRS)

Junkin, B. G.

1979-01-01

A procedure is presented for extracting disparate sources of data from geographic maps and for the conversion of these data into a suitable format for processing on a computer-oriented information system. Several graphic digitizing considerations are included and related to the NASA Earth Resources Laboratory's Digitizer System. Current operating procedures for the Digitizer System are given in a simplified and logical manner. The report serves as a guide to those organizations interested in converting map-based data by using a comparable map digitizing system.

An iLab for Teaching Advanced Logic Concepts with Hardware Descriptive Languages

ERIC Educational Resources Information Center

Ayodele, Kayode P.; Inyang, Isaac A.; Kehinde, Lawrence O.

2015-01-01

One of the more interesting approaches to teaching advanced logic concepts is the use of online laboratory frameworks to provide student access to remote field-programmable devices. There is as yet, however, no conclusive evidence of the effectiveness of such an approach. This paper presents the Advanced Digital Lab, a remote laboratory based on…

A Simple and Effective Remedial Learning System with a Fuzzy Expert System

ERIC Educational Resources Information Center

Lin, C.-C.; Guo, K.-H.; Lin, Y.-C.

2016-01-01

This study aims at implementing a simple and effective remedial learning system. Based on fuzzy inference, a remedial learning material selection system is proposed for a digital logic course. Two learning concepts of the course have been used in the proposed system: number systems and combinational logic. We conducted an experiment to validate…

Pressure driven digital logic in PDMS based microfluidic devices fabricated by multilayer soft lithography.

PubMed

Devaraju, Naga Sai Gopi K; Unger, Marc A

2012-11-21

Advances in microfluidics now allow an unprecedented level of parallelization and integration of biochemical reactions. However, one challenge still faced by the field has been the complexity and cost of the control hardware: one external pressure signal has been required for each independently actuated set of valves on chip. Using a simple post-modification to the multilayer soft lithography fabrication process, we present a new implementation of digital fluidic logic fully analogous to electronic logic with significant performance advances over the previous implementations. We demonstrate a novel normally closed static gain valve capable of modulating pressure signals in a fashion analogous to an electronic transistor. We utilize these valves to build complex fluidic logic circuits capable of arbitrary control of flows by processing binary input signals (pressure (1) and atmosphere (0)). We demonstrate logic gates and devices including NOT, NAND and NOR gates, bi-stable flip-flops, gated flip-flops (latches), oscillators, self-driven peristaltic pumps, delay flip-flops, and a 12-bit shift register built using static gain valves. This fluidic logic shows cascade-ability, feedback, programmability, bi-stability, and autonomous control capability. This implementation of fluidic logic yields significantly smaller devices, higher clock rates, simple designs, easy fabrication, and integration into MSL microfluidics.

Simultaneous G-Quadruplex DNA Logic.

PubMed

Bader, Antoine; Cockroft, Scott L

2018-04-03

A fundamental principle of digital computer operation is Boolean logic, where inputs and outputs are described by binary integer voltages. Similarly, inputs and outputs may be processed on the molecular level as exemplified by synthetic circuits that exploit the programmability of DNA base-pairing. Unlike modern computers, which execute large numbers of logic gates in parallel, most implementations of molecular logic have been limited to single computing tasks, or sensing applications. This work reports three G-quadruplex-based logic gates that operate simultaneously in a single reaction vessel. The gates respond to unique Boolean DNA inputs by undergoing topological conversion from duplex to G-quadruplex states that were resolved using a thioflavin T dye and gel electrophoresis. The modular, addressable, and label-free approach could be incorporated into DNA-based sensors, or used for resolving and debugging parallel processes in DNA computing applications. © 2018 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim.

Fuzzy Logic-Based Audio Pattern Recognition

NASA Astrophysics Data System (ADS)

Malcangi, M.

2008-11-01

Audio and audio-pattern recognition is becoming one of the most important technologies to automatically control embedded systems. Fuzzy logic may be the most important enabling methodology due to its ability to rapidly and economically model such application. An audio and audio-pattern recognition engine based on fuzzy logic has been developed for use in very low-cost and deeply embedded systems to automate human-to-machine and machine-to-machine interaction. This engine consists of simple digital signal-processing algorithms for feature extraction and normalization, and a set of pattern-recognition rules manually tuned or automatically tuned by a self-learning process.

Reproducible Operating Margins on a 72800-Device Digital Superconducting Chip (Open Access)

DTIC Science & Technology

2015-10-28

superconductor digital logic. Keywords: flux trapping, yield, digital Superconductor digital technology offers fundamental advantages over conventional...trapping in the superconductor films can degrade or preclude correct circuit operation. Scaling superconductor technology is now possible due to recent...advances in circuit design embodied in reciprocal quantum logic (RQL) [2, 3] and recent advances in superconductor integrated circuit fabrication, which

Fundamental physics issues of multilevel logic in developing a parallel processor.

NASA Astrophysics Data System (ADS)

Bandyopadhyay, Anirban; Miki, Kazushi

2007-06-01

In the last century, On and Off physical switches, were equated with two decisions 0 and 1 to express every information in terms of binary digits and physically realize it in terms of switches connected in a circuit. Apart from memory-density increase significantly, more possible choices in particular space enables pattern-logic a reality, and manipulation of pattern would allow controlling logic, generating a new kind of processor. Neumann's computer is based on sequential logic, processing bits one by one. But as pattern-logic is generated on a surface, viewing whole pattern at a time is a truly parallel processing. Following Neumann's and Shannons fundamental thermodynamical approaches we have built compatible model based on series of single molecule based multibit logic systems of 4-12 bits in an UHV-STM. On their monolayer multilevel communication and pattern formation is experimentally verified. Furthermore, the developed intelligent monolayer is trained by Artificial Neural Network. Therefore fundamental weak interactions for the building of truly parallel processor are explored here physically and theoretically.

Digital PCM bit synchronizer and detector

NASA Astrophysics Data System (ADS)

Moghazy, A. E.; Maral, G.; Blanchard, A.

1980-08-01

A theoretical analysis of a digital self-bit synchronizer and detector is presented and supported by the implementation of an experimental model that utilizes standard TTL logic circuits. This synchronizer is based on the generation of spectral line components by nonlinear filtering of the received bit stream, and extracting the line by a digital phase-locked loop (DPLL). The extracted reference signal instructs a digital matched filter (DMF) data detector. This realization features a short acquisition time and an all-digital structure.

Architecture and data processing alternatives for Tse computer. Volume 1: Tse logic design concepts and the development of image processing machine architectures

NASA Technical Reports Server (NTRS)

Rickard, D. A.; Bodenheimer, R. E.

1976-01-01

Digital computer components which perform two dimensional array logic operations (Tse logic) on binary data arrays are described. The properties of Golay transforms which make them useful in image processing are reviewed, and several architectures for Golay transform processors are presented with emphasis on the skeletonizing algorithm. Conventional logic control units developed for the Golay transform processors are described. One is a unique microprogrammable control unit that uses a microprocessor to control the Tse computer. The remaining control units are based on programmable logic arrays. Performance criteria are established and utilized to compare the various Golay transform machines developed. A critique of Tse logic is presented, and recommendations for additional research are included.

Majority logic gate for 3D magnetic computing.

PubMed

Eichwald, Irina; Breitkreutz, Stephan; Ziemys, Grazvydas; Csaba, György; Porod, Wolfgang; Becherer, Markus

2014-08-22

For decades now, microelectronic circuits have been exclusively built from transistors. An alternative way is to use nano-scaled magnets for the realization of digital circuits. This technology, known as nanomagnetic logic (NML), may offer significant improvements in terms of power consumption and integration densities. Further advantages of NML are: non-volatility, radiation hardness, and operation at room temperature. Recent research focuses on the three-dimensional (3D) integration of nanomagnets. Here we show, for the first time, a 3D programmable magnetic logic gate. Its computing operation is based on physically field-interacting nanometer-scaled magnets arranged in a 3D manner. The magnets possess a bistable magnetization state representing the Boolean logic states '0' and '1.' Magneto-optical and magnetic force microscopy measurements prove the correct operation of the gate over many computing cycles. Furthermore, micromagnetic simulations confirm the correct functionality of the gate even for a size in the nanometer-domain. The presented device demonstrates the potential of NML for three-dimensional digital computing, enabling the highest integration densities.

Enhancing Learning Effectiveness in Digital Design Courses through the Use of Programmable Logic Boards

ERIC Educational Resources Information Center

Zhu, Yi; Weng, T.; Cheng, Chung-Kuan

2009-01-01

Incorporating programmable logic devices (PLD) in digital design courses has become increasingly popular. The advantages of using PLDs, such as complex programmable logic devices (CPLDs) and field programmable gate arrays (FPGA), have been discussed before. However, previous studies have focused on the experiences from the point of view of the…

Mutation Testing for Effective Verification of Digital Components of Physical Systems

NASA Astrophysics Data System (ADS)

Kushik, N. G.; Evtushenko, N. V.; Torgaev, S. N.

2015-12-01

Digital components of modern physical systems are often designed applying circuitry solutions based on the field programmable gate array technology (FPGA). Such (embedded) digital components should be carefully tested. In this paper, an approach for the verification of digital physical system components based on mutation testing is proposed. The reference description of the behavior of a digital component in the hardware description language (HDL) is mutated by introducing into it the most probable errors and, unlike mutants in high-level programming languages, the corresponding test case is effectively derived based on a comparison of special scalable representations of the specification and the constructed mutant using various logic synthesis and verification systems.

Eight-Channel Digital Signal Processor and Universal Trigger Module

NASA Astrophysics Data System (ADS)

Skulski, Wojtek; Wolfs, Frank

2003-04-01

A 10-bit, 8-channel, 40 megasamples per second digital signal processor and waveform digitizer DDC-8 (nicknamed Universal Trigger Module) is presented. The digitizer features 8 analog inputs, 1 analog output for a reconstructed analog waveform, 16 NIM logic inputs, 8 NIM logic outputs, and a pool of 16 TTL logic lines which can be individually configured as either inputs or outputs. The first application of this device is to enhance the present trigger electronics for PHOBOS at RHIC. The status of the development and the first results are presented. Possible applications of the new device are discussed. Supported by the NSF grant PHY-0072204.

Method and apparatus for digitally based high speed x-ray spectrometer for direct coupled use with continuous discharge preamplifiers

DOEpatents

Warburton, W.K.

1998-06-30

A high speed, digitally based, signal processing system is disclosed which accepts directly coupled input data from a detector with a continuous discharge type preamplifier and produces a spectral analysis of the x-rays illuminating the detector. The system`s principal elements are an analog signal conditioning section, a combinatorial logic section which implements digital triangular filtering and pileup inspection, and a microprocessor which accepts values captured by the logic section and uses them to compute x-ray energy values. Operating without pole-zero correction, the system achieves high resolution by capturing, in conjunction with each peak value from the digital filter, an associated value of the unfiltered signal, and using this latter signal to correct the former for errors which arise from its local slope terms. This correction greatly reduces both energy resolution degradation and peak centroid shifting in the output spectrum as a function of input count rate. When the noise of this correction is excessive, a modification allows two filtered averages of the signal to be captured and a corrected peak amplitude computed therefrom. 14 figs.

Method and apparatus for digitally based high speed x-ray spectrometer for direct coupled use with continuous discharge preamplifiers

DOEpatents

Warburton, William K.

1998-01-01

A high speed, digitally based, signal processing system which accepts directly coupled input data from a detector with a continuous discharge type preamplifier and produces a spectral analysis of the x-rays illuminating the detector. The system's principal elements are an analog signal conditioning section, a combinatorial logic section which implements digital triangular filtering and pileup inspection, and a microprocessor which accepts values captured by the logic section and uses them to compute x-ray energy values. Operating without pole-zero correction, the system achieves high resolution by capturing, in conjunction with each peak value from the digital filter, an associated value of the unfiltered signal, and using this latter signal to correct the former for errors which arise from its local slope terms. This correction greatly reduces both energy resolution degradation and peak centroid shifting in the output spectrum as a function of input count rate. When the noise of this correction is excessive, a modification allows two filtered averages of the signal to be captured and a corrected peak amplitude computed therefrom.

Biomolecular logic systems: applications to biosensors and bioactuators

NASA Astrophysics Data System (ADS)

Katz, Evgeny

2014-05-01

The paper presents an overview of recent advances in biosensors and bioactuators based on the biocomputing concept. Novel biosensors digitally process multiple biochemical signals through Boolean logic networks of coupled biomolecular reactions and produce output in the form of YES/NO response. Compared to traditional single-analyte sensing devices, biocomputing approach enables a high-fidelity multi-analyte biosensing, particularly beneficial for biomedical applications. Multi-signal digital biosensors thus promise advances in rapid diagnosis and treatment of diseases by processing complex patterns of physiological biomarkers. Specifically, they can provide timely detection and alert to medical emergencies, along with an immediate therapeutic intervention. Application of the biocomputing concept has been successfully demonstrated for systems performing logic analysis of biomarkers corresponding to different injuries, particularly exemplified for liver injury. Wide-ranging applications of multi-analyte digital biosensors in medicine, environmental monitoring and homeland security are anticipated. "Smart" bioactuators, for example for signal-triggered drug release, were designed by interfacing switchable electrodes and biocomputing systems. Integration of novel biosensing and bioactuating systems with the biomolecular information processing systems keeps promise for further scientific advances and numerous practical applications.

Role of biomolecular logic systems in biosensors and bioactuators

NASA Astrophysics Data System (ADS)

Mailloux, Shay; Katz, Evgeny

2014-09-01

An overview of recent advances in biosensors and bioactuators based on biocomputing systems is presented. Biosensors digitally process multiple biochemical signals through Boolean logic networks of coupled biomolecular reactions and produce an output in the form of a YES/NO response. Compared to traditional single-analyte sensing devices, the biocomputing approach enables high-fidelity multianalyte biosensing, which is particularly beneficial for biomedical applications. Multisignal digital biosensors thus promise advances in rapid diagnosis and treatment of diseases by processing complex patterns of physiological biomarkers. Specifically, they can provide timely detection and alert medical personnel of medical emergencies together with immediate therapeutic intervention. Application of the biocomputing concept has been successfully demonstrated for systems performing logic analysis of biomarkers corresponding to different injuries, particularly as exemplified for liver injury. Wide-ranging applications of multianalyte digital biosensors in medicine, environmental monitoring, and homeland security are anticipated. "Smart" bioactuators, for signal-triggered drug release, for example, were designed by interfacing switchable electrodes with biocomputing systems. Integration of biosensing and bioactuating systems with biomolecular information processing systems advances the potential for further scientific innovations and various practical applications.

A DNA Logic Gate Automaton for Detection of Rabies and Other Lyssaviruses.

PubMed

Vijayakumar, Pavithra; Macdonald, Joanne

2017-07-05

Immediate activation of biosensors is not always desirable, particularly if activation is due to non-specific interactions. Here we demonstrate the use of deoxyribozyme-based logic gate networks arranged into visual displays to precisely control activation of biosensors, and demonstrate a prototype molecular automaton able to discriminate between seven different genotypes of Lyssaviruses, including Rabies virus. The device uses novel mixed-base logic gates to enable detection of the large diversity of Lyssavirus sequence populations, while an ANDNOT logic gate prevents non-specific activation across genotypes. The resultant device provides a user-friendly digital-like, but molecule-powered, dot-matrix text output for unequivocal results read-out that is highly relevant for point of care applications. © 2017 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim.

Digital Device Architecture and the Safe Use of Flash Devices in Munitions

NASA Technical Reports Server (NTRS)

Katz, Richard B.; Flowers, David; Bergevin, Keith

2017-01-01

Flash technology is being utilized in fuzed munition applications and, based on the development of digital logic devices in the commercial world, usage of flash technology will increase. Digital devices of interest to designers include flash-based microcontrollers and field programmable gate arrays (FPGAs). Almost a decade ago, a study was undertaken to determine if flash-based microcontrollers could be safely used in fuzes and, if so, how should such devices be applied. The results were documented in the Technical Manual for the Use of Logic Devices in Safety Features. This paper will first review the Technical Manual and discuss the rationale behind the suggested architectures for microcontrollers and a brief review of the concern about data retention in flash cells. An architectural feature in the microcontroller under study will be discussed and its use will show how to screen for weak or failed cells during manufacture, storage, or immediately prior to use. As was done for microcontrollers a decade ago, architectures for a flash-based FPGA will be discussed, showing how it can be safely used in fuzes. Additionally, architectures for using non-volatile (including flash-based) storage will be discussed for SRAM-based FPGAs.

Novel Quaternary Quantum Decoder, Multiplexer and Demultiplexer Circuits

NASA Astrophysics Data System (ADS)

Haghparast, Majid; Monfared, Asma Taheri

2017-05-01

Multiple valued logic is a promising approach to reduce the width of the reversible or quantum circuits, moreover, quaternary logic is considered as being a good choice for future quantum computing technology hence it is very suitable for the encoded realization of binary logic functions through its grouping of 2-bits together into quaternary values. The Quaternary decoder, multiplexer, and demultiplexer are essential units of quaternary digital systems. In this paper, we have initially designed a quantum realization of the quaternary decoder circuit using quaternary 1-qudit gates and quaternary Muthukrishnan-Stroud gates. Then we have presented quantum realization of quaternary multiplexer and demultiplexer circuits using the constructed quaternary decoder circuit and quaternary controlled Feynman gates. The suggested circuits in this paper have a lower quantum cost and hardware complexity than the existing designs that are currently used in quaternary digital systems. All the scales applied in this paper are based on Nanometric area.

Buckets, Clusters and Dienst

NASA Technical Reports Server (NTRS)

Nelson, Michael L.; Maly, Kurt; Shen, Stewart N. T.

1997-01-01

In this paper we describe NCSTRL+, a unified, canonical digital library for scientific and technical information (STI). NCSTRL+ is based on the Networked Computer Science Technical Report Library (NCSTRL), a World Wide Web (WWW) accessible digital library (DL) that provides access to over 80 university departments and laboratories. NCSTRL+ implements two new technologies: cluster functionality and publishing "buckets." We have extended the Dienst protocol, the protocol underlying NCSTRL, to provide the ability to "cluster" independent collections into a logically centralized digital library based upon subject category classification, type of organization, and genres of material. The concept of "buckets" provides a mechanism for publishing and managing logically linked entities with multiple data formats. The NCSTRL+ prototype DL contains the holdings of NCSTRL and the NASA Technical Report Server (NTRS). The prototype demonstrates the feasibility of publishing into a multi-cluster DL, searching across clusters, and storing and presenting buckets of information. We show that the overhead for these additional capabilities is minimal to both the author and the user when compared to the equivalent process within NCSTRL.

Reconfigurable firmware-defined radios synthesized from standard digital logic cells

NASA Astrophysics Data System (ADS)

Faisal, Muhammad; Park, Youngmin; Wentzloff, David D.

2011-06-01

This paper presents recent work on reconfigurable all-digital radio architectures. We leverage the flexibility and scalability of synthesized digital cells to construct reconfigurable radio architectures that consume significantly less power than a software defined radio implementing similar architectures. We present two prototypes of such architectures that can receive and demodulate FM and FRS band signals. Moreover, a radio architecture based on a reconfigurable alldigital phase-locked loop for coherent demodulation is presented.

Two-step digit-set-restricted modified signed-digit addition-subtraction algorithm and its optoelectronic implementation.

PubMed

Qian, F; Li, G; Ruan, H; Jing, H; Liu, L

1999-09-10

A novel, to our knowledge, two-step digit-set-restricted modified signed-digit (MSD) addition-subtraction algorithm is proposed. With the introduction of the reference digits, the operand words are mapped into an intermediate carry word with all digits restricted to the set {1, 0} and an intermediate sum word with all digits restricted to the set {0, 1}, which can be summed to form the final result without carry generation. The operation can be performed in parallel by use of binary logic. An optical system that utilizes an electron-trapping device is suggested for accomplishing the required binary logic operations. By programming of the illumination of data arrays, any complex logic operations of multiple variables can be realized without additional temporal latency of the intermediate results. This technique has a high space-bandwidth product and signal-to-noise ratio. The main structure can be stacked to construct a compact optoelectronic MSD adder-subtracter.

An Optimized Three-Level Design of Decoder Based on Nanoscale Quantum-Dot Cellular Automata

NASA Astrophysics Data System (ADS)

Seyedi, Saeid; Navimipour, Nima Jafari

2018-03-01

Quantum-dot Cellular Automata (QCA) has been potentially considered as a supersede to Complementary Metal-Oxide-Semiconductor (CMOS) because of its inherent advantages. Many QCA-based logic circuits with smaller feature size, improved operating frequency, and lower power consumption than CMOS have been offered. This technology works based on electron relations inside quantum-dots. Due to the importance of designing an optimized decoder in any digital circuit, in this paper, we design, implement and simulate a new 2-to-4 decoder based on QCA with low delay, area, and complexity. The logic functionality of the 2-to-4 decoder is verified using the QCADesigner tool. The results have shown that the proposed QCA-based decoder has high performance in terms of a number of cells, covered area, and time delay. Due to the lower clock pulse frequency, the proposed 2-to-4 decoder is helpful for building QCA-based sequential digital circuits with high performance.

An Undergraduate Design Experience in Digital Logic Design Course of Special Purpose Arithmetic Logic Unit Using Multisim, Ultiboard and Print Circuit Board

ERIC Educational Resources Information Center

Al-Haija, Qasem Abu; Al-Amri, Hasan; Al-Nashri, Mohamed; Al-Muhaisen, Sultan

2013-01-01

Project-Based Curriculum (PBC) is considered one of the most powerful methods in the engineering education where each course or courses-cluster is assigned a design project which considers a series of inter-related concepts that have been shown theoretically for the students. Using this approach, the student will gain the required knowledge in an…

Digital logic circuits in yeast with CRISPR-dCas9 NOR gates

PubMed Central

Gander, Miles W.; Vrana, Justin D.; Voje, William E.; Carothers, James M.; Klavins, Eric

2017-01-01

Natural genetic circuits enable cells to make sophisticated digital decisions. Building equally complex synthetic circuits in eukaryotes remains difficult, however, because commonly used components leak transcriptionally, do not arbitrarily interconnect or do not have digital responses. Here, we designed dCas9-Mxi1-based NOR gates in Saccharomyces cerevisiae that allow arbitrary connectivity and large genetic circuits. Because we used the chromatin remodeller Mxi1, our gates showed minimal leak and digital responses. We built a combinatorial library of NOR gates that directly convert guide RNA (gRNA) inputs into gRNA outputs, enabling the gates to be ‘wired' together. We constructed logic circuits with up to seven gRNAs, including repression cascades with up to seven layers. Modelling predicted the NOR gates have effectively zero transcriptional leak explaining the limited signal degradation in the circuits. Our approach enabled the largest, eukaryotic gene circuits to date and will form the basis for large, synthetic, cellular decision-making systems. PMID:28541304

Characteristics Of Ferroelectric Logic Gates Using a Spice-Based Model

NASA Technical Reports Server (NTRS)

MacLeod, Todd C.; Phillips, Thomas A.; Ho, Fat D.

2005-01-01

A SPICE-based model of an n-channel ferroelectric field effect transistor has been developed based on both theoretical and empirical data. This model was used to generate the I-V characteristic of several logic gates. The use of ferroelectric field effect transistors in memory circuits is being developed by several organizations. The use of FFETs in other circuits, both analog and digital needs to be better understood. The ability of FFETs to have different characteristics depending on the initial polarization can be used to create logic gates. These gates can have properties not available to standard CMOS logic gates, such as memory, reconfigurability and memory. This paper investigates basic properties of FFET logic gates. It models FFET inverter, NAND gate and multi-input NAND gate. The I-V characteristics of the gates are presented as well as transfer characteristics and timing. The model used is a SPICE-based model developed from empirical data from actual Ferroelectric transistors. It simulates all major characteristics of the ferroelectric transistor, including polarization, hysteresis and decay. Contrasts are made of the differences between FFET logic gates and CMOS logic gates. FFET parameters are varied to show the effect on the overall gate. A recodigurable gate is investigated which is not possible with CMOS circuits. The paper concludes that FFETs can be used in logic gates and have several advantages over standard CMOS gates.

Boolean Approaches in Digital Diagnosis

DTIC Science & Technology

1989-12-04

Automation Conference, pages 64-70, 1983. 16. Barry W. Johnson. Design and A nalysis of Fault-Tolerant Digital Systems. Addison- Wesley Publishing...Mitchell. On a new algebra of logic. In C.S. Peirce, edhitor, Studies in Logic. Little, Brown. Boston. 1883. 2:3. Roger S. Pressman . Softwrare Engineering

Building Multi-Discipline, Multi-Format Digital Libraries Using Clusters and Buckets. Degree rewarded by Old Dominion Univ. on Aug. 1997

NASA Technical Reports Server (NTRS)

Nelson, Michael L.

1997-01-01

Our objective was to study the feasibility of extending the Dienst protocol to enable a multi-discipline, multi-format digital library. We implemented two new technologies: cluster functionality and publishing buckets. We have designed a possible implementation of clusters and buckets, and have prototyped some aspects of the resultant digital library. Currently, digital libraries are segregated by the disciplines they serve (computer science, aeronautics, etc.), and by the format of their holdings (reports, software, datasets, etc.). NCSTRL+ is a multi-discipline, multi-format digital library (DL) prototype created to explore the feasibility of the design and implementation issues involved with created a unified, canonical scientific and technical information (STI) DL. NCSTRL+ is based on the Networked Computer Science Technical Report Library (NCSTRL), a World Wide Web (WWW) accessible DL that provides access to over 80 university departments and laboratories. We have extended the Dienst protocol (version 4.1.8), the protocol underlying NCSTRL, to provide the ability to cluster independent collections into a logically centralized DL based upon subject category classification, type of organization, and genre of material. The concept of buckets provides a mechanism for publishing and managing logically linked entities with multiple data formats.

"Glitch Logic" and Applications to Computing and Information Security

NASA Technical Reports Server (NTRS)

Stoica, Adrian; Katkoori, Srinivas

2009-01-01

This paper introduces a new method of information processing in digital systems, and discusses its potential benefits to computing and information security. The new method exploits glitches caused by delays in logic circuits for carrying and processing information. Glitch processing is hidden to conventional logic analyses and undetectable by traditional reverse engineering techniques. It enables the creation of new logic design methods that allow for an additional controllable "glitch logic" processing layer embedded into a conventional synchronous digital circuits as a hidden/covert information flow channel. The combination of synchronous logic with specific glitch logic design acting as an additional computing channel reduces the number of equivalent logic designs resulting from synthesis, thus implicitly reducing the possibility of modification and/or tampering with the design. The hidden information channel produced by the glitch logic can be used: 1) for covert computing/communication, 2) to prevent reverse engineering, tampering, and alteration of design, and 3) to act as a channel for information infiltration/exfiltration and propagation of viruses/spyware/Trojan horses.

Nanoelectromechanical digital logic circuits using curved cantilever switches with amorphous-carbon-coated contacts

NASA Astrophysics Data System (ADS)

Ayala, Christopher L.; Grogg, Daniel; Bazigos, Antonios; Bleiker, Simon J.; Fernandez-Bolaños, Montserrat; Niklaus, Frank; Hagleitner, Christoph

2015-11-01

Nanoelectromechanical (NEM) switches have the potential to complement or replace traditional CMOS transistors in the area of ultra-low-power digital electronics. This paper reports the demonstration of prototype circuits including the first 3-stage ring oscillator built using cell-level digital logic elements based on curved NEM switches. The ring oscillator core occupies an area of 30 μm × 10 μm using 6 NEM switches. Each NEM switch device has a footprint of 5 μm × 3 μm, an air gap of 60 μm and is coated with amorphous carbon (a-C) for reliable operation. The ring oscillator operates at a frequency of 6.7 MHz, and confirms the simulated inverter propagation delay of 25 ns. The successful fabrication and measurement of this demonstrator are key milestones on the way towards an optimized, scaled technology with sub-nanosecond switching times, lower operating voltages and VLSI implementation.

Abstracts of ARI Research Publications, FY 1974 and 1975

DTIC Science & Technology

1979-10-01

may obtain these documents from the National Technical Information Service (NTIS), Department of Commerce, Springfield, Va., 22151. The six- digit AD...Siegel, A. I., Wolf, J. J., & Leahy, W. R. (Applied Psycho- logical Services, Inc.). A digital simulation model of message handling in the Tactical...inherent in the mission of interest, (b) incorporate these 28 into a logic for a digital simulation model, and (c) develop a computer program reflecting

A hybrid nanomemristor/transistor logic circuit capable of self-programming

PubMed Central

Borghetti, Julien; Li, Zhiyong; Straznicky, Joseph; Li, Xuema; Ohlberg, Douglas A. A.; Wu, Wei; Stewart, Duncan R.; Williams, R. Stanley

2009-01-01

Memristor crossbars were fabricated at 40 nm half-pitch, using nanoimprint lithography on the same substrate with Si metal-oxide-semiconductor field effect transistor (MOS FET) arrays to form fully integrated hybrid memory resistor (memristor)/transistor circuits. The digitally configured memristor crossbars were used to perform logic functions, to serve as a routing fabric for interconnecting the FETs and as the target for storing information. As an illustrative demonstration, the compound Boolean logic operation (A AND B) OR (C AND D) was performed with kilohertz frequency inputs, using resistor-based logic in a memristor crossbar with FET inverter/amplifier outputs. By routing the output signal of a logic operation back onto a target memristor inside the array, the crossbar was conditionally configured by setting the state of a nonvolatile switch. Such conditional programming illuminates the way for a variety of self-programmed logic arrays, and for electronic synaptic computing. PMID:19171903

A hybrid nanomemristor/transistor logic circuit capable of self-programming.

PubMed

Borghetti, Julien; Li, Zhiyong; Straznicky, Joseph; Li, Xuema; Ohlberg, Douglas A A; Wu, Wei; Stewart, Duncan R; Williams, R Stanley

2009-02-10

Memristor crossbars were fabricated at 40 nm half-pitch, using nanoimprint lithography on the same substrate with Si metal-oxide-semiconductor field effect transistor (MOS FET) arrays to form fully integrated hybrid memory resistor (memristor)/transistor circuits. The digitally configured memristor crossbars were used to perform logic functions, to serve as a routing fabric for interconnecting the FETs and as the target for storing information. As an illustrative demonstration, the compound Boolean logic operation (A AND B) OR (C AND D) was performed with kilohertz frequency inputs, using resistor-based logic in a memristor crossbar with FET inverter/amplifier outputs. By routing the output signal of a logic operation back onto a target memristor inside the array, the crossbar was conditionally configured by setting the state of a nonvolatile switch. Such conditional programming illuminates the way for a variety of self-programmed logic arrays, and for electronic synaptic computing.

Biosensors with Built-In Biomolecular Logic Gates for Practical Applications

PubMed Central

Lai, Yu-Hsuan; Sun, Sin-Cih; Chuang, Min-Chieh

2014-01-01

Molecular logic gates, designs constructed with biological and chemical molecules, have emerged as an alternative computing approach to silicon-based logic operations. These molecular computers are capable of receiving and integrating multiple stimuli of biochemical significance to generate a definitive output, opening a new research avenue to advanced diagnostics and therapeutics which demand handling of complex factors and precise control. In molecularly gated devices, Boolean logic computations can be activated by specific inputs and accurately processed via bio-recognition, bio-catalysis, and selective chemical reactions. In this review, we survey recent advances of the molecular logic approaches to practical applications of biosensors, including designs constructed with proteins, enzymes, nucleic acids, nanomaterials, and organic compounds, as well as the research avenues for future development of digitally operating “sense and act” schemes that logically process biochemical signals through networked circuits to implement intelligent control systems. PMID:25587423

The Art of Electronics

NASA Astrophysics Data System (ADS)

Horowitz, Paul; Hill, Winfield

2015-04-01

1. Foundations; 2. Bipolar transistors; 3. Field effect transistors; 4. Operational amplifiers; 5. Precision circuits; 6. Filters; 7. Oscillators and timers; 8. Low noise techniques and transimpedance; 9. Power regulation; 10. Digital electronics; 11. Programmable logic devices; 12. Logical interfacing; 13. Digital meets analog; 14. Computers, controllers, and data links; 15. Microcontrollers.

Optical triple-in digital logic using nonlinear optical four-wave mixing

NASA Astrophysics Data System (ADS)

Widjaja, Joewono; Tomita, Yasuo

1995-08-01

A new programmable optical processor is proposed for implementing triple-in combinatorial digital logic that uses four-wave mixing. Binary-coded decimal-to-octal decoding is experimentally demonstrated by use of a photorefractive BaTiO 3 crystal. The result confirms the feasibility of the proposed system.

Modified signed-digit trinary addition using synthetic wavelet filter

NASA Astrophysics Data System (ADS)

Iftekharuddin, K. M.; Razzaque, M. A.

2000-09-01

The modified signed-digit (MSD) number system has been a topic of interest as it allows for parallel carry-free addition of two numbers for digital optical computing. In this paper, harmonic wavelet joint transform (HWJT)-based correlation technique is introduced for optical implementation of MSD trinary adder implementation. The realization of the carry-propagation-free addition of MSD trinary numerals is demonstrated using synthetic HWJT correlator model. It is also shown that the proposed synthetic wavelet filter-based correlator shows high performance in logic processing. Simulation results are presented to validate the performance of the proposed technique.

Light-Gated Memristor with Integrated Logic and Memory Functions.

PubMed

Tan, Hongwei; Liu, Gang; Yang, Huali; Yi, Xiaohui; Pan, Liang; Shang, Jie; Long, Shibing; Liu, Ming; Wu, Yihong; Li, Run-Wei

2017-11-28

Memristive devices are able to store and process information, which offers several key advantages over the transistor-based architectures. However, most of the two-terminal memristive devices have fixed functions once made and cannot be reconfigured for other situations. Here, we propose and demonstrate a memristive device "memlogic" (memory logic) as a nonvolatile switch of logic operations integrated with memory function in a single light-gated memristor. Based on nonvolatile light-modulated memristive switching behavior, a single memlogic cell is able to achieve optical and electrical mixed basic Boolean logic of reconfigurable "AND", "OR", and "NOT" operations. Furthermore, the single memlogic cell is also capable of functioning as an optical adder and digital-to-analog converter. All the memlogic outputs are memristive for in situ data storage due to the nonvolatile resistive switching and persistent photoconductivity effects. Thus, as a memdevice, the memlogic has potential for not only simplifying the programmable logic circuits but also building memristive multifunctional optoelectronics.

Development of an optical parallel logic device and a half-adder circuit for digital optical processing

NASA Technical Reports Server (NTRS)

Athale, R. A.; Lee, S. H.

1978-01-01

The paper describes the fabrication and operation of an optical parallel logic (OPAL) device which performs Boolean algebraic operations on binary images. Several logic operations on two input binary images were demonstrated using an 8 x 8 device with a CdS photoconductor and a twisted nematic liquid crystal. Two such OPAL devices can be interconnected to form a half-adder circuit which is one of the essential components of a CPU in a digital signal processor.

A fuzzy logic sliding mode controlled electronic differential for a direct wheel drive EV

NASA Astrophysics Data System (ADS)

Ozkop, Emre; Altas, Ismail H.; Okumus, H. Ibrahim; Sharaf, Adel M.

2015-11-01

In this study, a direct wheel drive electric vehicle based on an electronic differential system with a fuzzy logic sliding mode controller (FLSMC) is studied. The conventional sliding surface is modified using a fuzzy rule base to obtain fuzzy dynamic sliding surfaces by changing its slopes using the global error and its derivative in a fuzzy logic inference system. The controller is compared with proportional-integral-derivative (PID) and sliding mode controllers (SMCs), which are usually preferred to be used in industry. The proposed controller provides robustness and flexibility to direct wheel drive electric vehicles. The fuzzy logic sliding mode controller, electronic differential system and the overall electrical vehicle mechanism are modelled and digitally simulated by using the Matlab software. Simulation results show that the system with FLSMC has better efficiency and performance compared to those of PID and SMCs.

Design of digital voice storage and playback system

NASA Astrophysics Data System (ADS)

Tang, Chao

2018-03-01

Based on STC89C52 chip, this paper presents a single chip microcomputer minimum system, which is used to realize the logic control of digital speech storage and playback system. Compared with the traditional tape voice recording system, the system has advantages of small size, low power consumption, The effective solution of traditional voice recording system is limited in the use of electronic and information processing.

Motivation for DOC III: 64-bit digital optical computer

NASA Astrophysics Data System (ADS)

Guilfoyle, Peter S.

1991-09-01

This paper suggests a new class of digital logic. OptiComp has focused on a digital optical logic family in order to capitalize on the inherent benefits of optical computing, which include (1) high FAN-IN and FAN-OUT, (2) low power consumption, (3) high noise margin, (4) high algorithmic efficiency using 'smart' interconnects, (5) free space leverage of GIBP (gate interconnect bandwidth product). Other well-known secondary advantages of optical logic include (but are not limited to) zero capacitive loading of signals at a detector, zero cross-talk between signals, zero signal dispersion, minimal clock skew (a few picoseconds or less in an imaging system). The primary focus of this paper is to demonstrate how each of the five advantages can be used to leverage other logic family performance such as GaAs; the secondary attributes will be discussed only in the context of introducing the DOC III architecture.

Motivation for DOC III: 64-bit digital optical computer

NASA Astrophysics Data System (ADS)

Guilfoyle, Peter S.

1991-09-01

The objective of this paper is to motivate a new class of digital logic. OptiComp has focused on a digital optical logic family in order to capitalize on the inherent benefits of optical computing, which include: (1) high FAN-IN and FAN-OUT, (2) low power consumption, (3) high noise margin, (4) high algorithmic efficiency using 'smart' interconnects, (5) free space leverage of GIBP (gate interconnect bandwidth product). Other well-known secondary advantages of optical logic include (but are not limited to): zero capacitive loading of signals at a detector, zero cross-talk between signals, zero signal dispersion, and minimal clock skew (a few picoseconds or less in an imaging system). The primary focus of this paper is on demonstrating how each of the five advantages can be used to leverage other logic family performance such as GaAs; the secondary attributes will be discussed only in the context of introducing the DOC III architecture.

Measurement and Analysis of a Ferroelectric Field-Effect Transistor NAND Gate

NASA Technical Reports Server (NTRS)

Phillips, Thomas A.; MacLeond, Todd C.; Sayyah, Rana; Ho, Fat Duen

2009-01-01

Previous research investigated expanding the use of Ferroelectric Field-Effect Transistors (FFET) to other electronic devices beyond memory circuits. Ferroelectric based transistors possess unique characteris tics that give them interesting and useful properties in digital logic circuits. The NAND gate was chosen for investigation as it is one of the fundamental building blocks of digital electronic circuits. In t his paper, NAND gate circuits were constructed utilizing individual F FETs. N-channel FFETs with positive polarization were used for the standard CMOS NAND gate n-channel transistors and n-channel FFETs with n egative polarization were used for the standard CMOS NAND gate p-chan nel transistors. The voltage transfer curves were obtained for the NA ND gate. Comparisons were made between the actual device data and the previous modeled data. These results are compared to standard MOS logic circuits. The circuits analyzed are not intended to be fully opera tional circuits that would interface with existing logic circuits, bu t as a research tool to look into the possibility of using ferroelectric transistors in future logic circuits. Possible applications for th ese devices are presented, and their potential benefits and drawbacks are discussed.

A low power, area efficient fpga based beamforming technique for 1-D CMUT arrays.

PubMed

Joseph, Bastin; Joseph, Jose; Vanjari, Siva Rama Krishna

2015-08-01

A low power area efficient digital beamformer targeting low frequency (2MHz) 1-D linear Capacitive Micromachined Ultrasonic Transducer (CMUT) array is developed. While designing the beamforming logic, the symmetry of the CMUT array is well exploited to reduce the area and power consumption. The proposed method is verified in Matlab by clocking an Arbitrary Waveform Generator(AWG). The architecture is successfully implemented in Xilinx Spartan 3E FPGA kit to check its functionality. The beamforming logic is implemented for 8, 16, 32, and 64 element CMUTs targeting Application Specific Integrated Circuit (ASIC) platform at Vdd 1.62V for UMC 90nm technology. It is observed that the proposed architecture consumes significantly lesser power and area (1.2895 mW power and 47134.4 μm(2) area for a 64 element digital beamforming circuit) compared to the conventional square root based algorithm.

Advanced reliability modeling of fault-tolerant computer-based systems

NASA Technical Reports Server (NTRS)

Bavuso, S. J.

1982-01-01

Two methodologies for the reliability assessment of fault tolerant digital computer based systems are discussed. The computer-aided reliability estimation 3 (CARE 3) and gate logic software simulation (GLOSS) are assessment technologies that were developed to mitigate a serious weakness in the design and evaluation process of ultrareliable digital systems. The weak link is based on the unavailability of a sufficiently powerful modeling technique for comparing the stochastic attributes of one system against others. Some of the more interesting attributes are reliability, system survival, safety, and mission success.

GMAG Dissertation Award Talk: All Spin Logic -- Multimagnet Networks interacting via Spin currents

NASA Astrophysics Data System (ADS)

Srinivasan, Srikant

2012-02-01

Digital logic circuits have traditionally been based on storing information as charge on capacitors, and the stored information is transferred by controlling the flow of charge. However, electrons carry both charge and spin, the latter being responsible for magnetic phenomena. In the last few decades, there has been a significant improvement in our ability to control spins and their interaction with magnets. All Spin Logic (ASL) represents a new approach to information processing where spins and magnets now mirror the roles of charges and capacitors in conventional logic circuits. In this talk I first present a model [1] that couples non-collinear spin transport with magnet-dynamics to predict the switching behavior of the basic ASL device. This model is based on established physics and is benchmarked against available experimental data that demonstrate spin-torque switching in lateral structures. Next, the model is extended to simulate multi-magnet networks coupled with spin transport channels. The simulations suggest ASL devices have the essential characteristics for building logic circuits. In particular, (1) the example of an ASL ring oscillator [2, 3] is used to provide a clear signature of directed information transfer in cascaded ASL devices without the need for external control circuitry and (2) a simulated NAND [4] gate with fan-out of 2 suggests that ASL can implement universal logic and drive subsequent stages. Finally I will discuss how ASL based circuits could also have potential use in the design of neuromorphic circuits suitable for hybrid analog/digital information processing because of the natural mapping of ASL devices to neurons [4]. [4pt] [1] B. Behin-Aein, A. Sarkar, S. Srinivasan, and S. Datta, ``Switching Energy-Delay of All-Spin Logic devices,'' Appl. Phys. Lett., 98, 123510 (2011).[0pt] [2] S. Srinivasan, A. Sarkar, B. Behin-Aein, and S. Datta, ``All Spin Logic Device with Inbuilt Non-reciprocity,'' IEEE Trans. Magn., 47, 10 (2011).[0pt] [3] S. Srinivasan, A. Sarkar, B. Behin-Aein and S. Datta, ``Unidirectional Information transfer with cascaded All Spin Logic devices: A Ring Oscillator,'' IEEE Device Research Conference (2011).[0pt] [4] A. Sarkar, S. Srinivasan, B. Behin-Aein and S. Datta, ``Multimagnet networks interacting via spin currents'' IEEE International Electron Devices Meeting 2011. (to appear).

Implementing neural nets with programmable logic

NASA Technical Reports Server (NTRS)

Vidal, Jacques J.

1988-01-01

Networks of Boolean programmable logic modules are presented as one purely digital class of artificial neural nets. The approach contrasts with the continuous analog framework usually suggested. Programmable logic networks are capable of handling many neural-net applications. They avoid some of the limitations of threshold logic networks and present distinct opportunities. The network nodes are called dynamically programmable logic modules. They can be implemented with digitally controlled demultiplexers. Each node performs a Boolean function of its inputs which can be dynamically assigned. The overall network is therefore a combinational circuit and its outputs are Boolean global functions of the network's input variables. The approach offers definite advantages for VLSI implementation, namely, a regular architecture with limited connectivity, simplicity of the control machinery, natural modularity, and the support of a mature technology.

FPGA Implementation of Metastability-Based True Random Number Generator

NASA Astrophysics Data System (ADS)

Hata, Hisashi; Ichikawa, Shuichi

True random number generators (TRNGs) are important as a basis for computer security. Though there are some TRNGs composed of analog circuit, the use of digital circuits is desired for the application of TRNGs to logic LSIs. Some of the digital TRNGs utilize jitter in free-running ring oscillators as a source of entropy, which consume large power. Another type of TRNG exploits the metastability of a latch to generate entropy. Although this kind of TRNG has been mostly implemented with full-custom LSI technology, this study presents an implementation based on common FPGA technology. Our TRNG is comprised of logic gates only, and can be integrated in any kind of logic LSI. The RS latch in our TRNG is implemented as a hard-macro to guarantee the quality of randomness by minimizing the signal skew and load imbalance of internal nodes. To improve the quality and throughput, the output of 64-256 latches are XOR'ed. The derived design was verified on a Xilinx Virtex-4 FPGA (XC4VFX20), and passed NIST statistical test suite without post-processing. Our TRNG with 256 latches occupies 580 slices, while achieving 12.5Mbps throughput.

A Compton suppressed detector multiplicity trigger based digital DAQ for gamma-ray spectroscopy

NASA Astrophysics Data System (ADS)

Das, S.; Samanta, S.; Banik, R.; Bhattacharjee, R.; Basu, K.; Raut, R.; Ghugre, S. S.; Sinha, A. K.; Bhattacharya, S.; Imran, S.; Mukherjee, G.; Bhattacharyya, S.; Goswami, A.; Palit, R.; Tan, H.

2018-06-01

The development of a digitizer based pulse processing and data acquisition system for γ-ray spectroscopy with large detector arrays is presented. The system is based on 250 MHz 12-bit digitizers, and is triggered by a user chosen multiplicity of Compton suppressed detectors. The logic for trigger generation is similar to the one practised for analog (NIM/CAMAC) pulse processing electronics, while retaining the fast processing merits of the digitizer system. Codes for reduction of data acquired from the system have also been developed. The system has been tested with offline studies using radioactive sources as well as in the in-beam experiments with an array of Compton suppressed Clover detectors. The results obtained therefrom validate its use in spectroscopic efforts for nuclear structure investigations.

Method and apparatus for combinatorial logic signal processor in a digitally based high speed x-ray spectrometer

DOEpatents

Warburton, William K.; Zhou, Zhiquing

1999-01-01

A high speed, digitally based, signal processing system which accepts a digitized input signal and detects the presence of step-like pulses in the this data stream, extracts filtered estimates of their amplitudes, inspects for pulse pileup, and records input pulse rates and system livetime. The system has two parallel processing channels: a slow channel, which filters the data stream with a long time constant trapezoidal filter for good energy resolution; and a fast channel which filters the data stream with a short time constant trapezoidal filter, detects pulses, inspects for pileups, and captures peak values from the slow channel for good events. The presence of a simple digital interface allows the system to be easily integrated with a digital processor to produce accurate spectra at high count rates and allow all spectrometer functions to be fully automated. Because the method is digitally based, it allows pulses to be binned based on time related values, as well as on their amplitudes, if desired.

Logic circuit detects both present and missing negative pulses in superimposed wave trains

NASA Technical Reports Server (NTRS)

Rice, R. E.

1967-01-01

Pulse divide and determination network provides a logical determination of pulse presence within a data train. The network uses digital logic circuitry to divide positive and negative pulses, to shape the separated pulses, and to determine, by means of coincidence logic, if negative pulses are missing from the pulse train.

Superconducting Digital Multiplexers for Sensor Arrays

NASA Technical Reports Server (NTRS)

Kadin, Alan M.; Brock, Darren K.; Gupta, Deepnarayan

2004-01-01

Arrays of cryogenic microbolometers and other cryogenic detectors are being developed for infrared imaging. If the signal from each sensor is amplified, multiplexed, and digitized using superconducting electronics, then this data can be efficiently read out to ambient temperature with a minimum of noise and thermal load. HYPRES is developing an integrated system based on SQUID amplifiers, a high-resolution analog-to-digital converter (ADC) based on RSFQ (rapid single flux quantum) logic, and a clocked RSFQ multiplexer. The ADC and SQUIDs have already been demonstrated for other projects, so this paper will focus on new results of a digital multiplexer. Several test circuits have been fabricated using Nb Josephson technology and are about to be tested at T = 4.2 K, with a more complete prototype in preparation.

Stochastic p -Bits for Invertible Logic

NASA Astrophysics Data System (ADS)

Camsari, Kerem Yunus; Faria, Rafatul; Sutton, Brian M.; Datta, Supriyo

2017-07-01

Conventional semiconductor-based logic and nanomagnet-based memory devices are built out of stable, deterministic units such as standard metal-oxide semiconductor transistors, or nanomagnets with energy barriers in excess of ≈40 - 60 kT . In this paper, we show that unstable, stochastic units, which we call "p -bits," can be interconnected to create robust correlations that implement precise Boolean functions with impressive accuracy, comparable to standard digital circuits. At the same time, they are invertible, a unique property that is absent in standard digital circuits. When operated in the direct mode, the input is clamped, and the network provides the correct output. In the inverted mode, the output is clamped, and the network fluctuates among all possible inputs that are consistent with that output. First, we present a detailed implementation of an invertible gate to bring out the key role of a single three-terminal transistorlike building block to enable the construction of correlated p -bit networks. The results for this specific, CMOS-assisted nanomagnet-based hardware implementation agree well with those from a universal model for p -bits, showing that p -bits need not be magnet based: any three-terminal tunable random bit generator should be suitable. We present a general algorithm for designing a Boltzmann machine (BM) with a symmetric connection matrix [J ] (Ji j=Jj i) that implements a given truth table with p -bits. The [J ] matrices are relatively sparse with a few unique weights for convenient hardware implementation. We then show how BM full adders can be interconnected in a partially directed manner (Ji j≠Jj i) to implement large logic operations such as 32-bit binary addition. Hundreds of stochastic p -bits get precisely correlated such that the correct answer out of 233 (≈8 ×1 09) possibilities can be extracted by looking at the statistical mode or majority vote of a number of time samples. With perfect directivity (Jj i=0 ) a small number of samples is enough, while for less directed connections more samples are needed, but even in the former case logical invertibility is largely preserved. This combination of digital accuracy and logical invertibility is enabled by the hybrid design that uses bidirectional BM units to construct circuits with partially directed interunit connections. We establish this key result with extensive examples including a 4-bit multiplier which in inverted mode functions as a factorizer.

Implementation of Adaptive Digital Controllers on Programmable Logic Devices

NASA Technical Reports Server (NTRS)

Gwaltney, David A.; King, Kenneth D.; Smith, Keary J.; Monenegro, Justino (Technical Monitor)

2002-01-01

Much has been made of the capabilities of FPGA's (Field Programmable Gate Arrays) in the hardware implementation of fast digital signal processing. Such capability also makes an FPGA a suitable platform for the digital implementation of closed loop controllers. Other researchers have implemented a variety of closed-loop digital controllers on FPGA's. Some of these controllers include the widely used proportional-integral-derivative (PID) controller, state space controllers, neural network and fuzzy logic based controllers. There are myriad advantages to utilizing an FPGA for discrete-time control functions which include the capability for reconfiguration when SRAM-based FPGA's are employed, fast parallel implementation of multiple control loops and implementations that can meet space level radiation tolerance requirements in a compact form-factor. Generally, a software implementation on a DSP (Digital Signal Processor) or microcontroller is used to implement digital controllers. At Marshall Space Flight Center, the Control Electronics Group has been studying adaptive discrete-time control of motor driven actuator systems using digital signal processor (DSP) devices. While small form factor, commercial DSP devices are now available with event capture, data conversion, pulse width modulated (PWM) outputs and communication peripherals, these devices are not currently available in designs and packages which meet space level radiation requirements. In general, very few DSP devices are produced that are designed to meet any level of radiation tolerance or hardness. The goal of this effort is to create a fully digital, flight ready controller design that utilizes an FPGA for implementation of signal conditioning for control feedback signals, generation of commands to the controlled system, and hardware insertion of adaptive control algorithm approaches. An alternative is required for compact implementation of such functionality to withstand the harsh environment encountered on spacecraft. Radiation tolerant FPGA's are a feasible option for reaching this goal.

Efficient G(sup 4)FET-Based Logic Circuits

NASA Technical Reports Server (NTRS)

Vatan, Farrokh

2008-01-01

A total of 81 optimal logic circuits based on four-gate field-effect transistors (G(sup 4)4FETs) have been designed to implement all Boolean functions of up to three variables. The purpose of this development was to lend credence to the expectation that logic circuits based on G(sup 4)FETs could be more efficient (in the sense that they could contain fewer transistors), relative to functionally equivalent logic circuits based on conventional transistors. A G(sup 4)FET a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G(sup 4)FET can also be regarded as a single device having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of a silicon-on-insulator substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. One such option is to design a G(sup 4)FET to function as a three-input NOT-majority gate, which has been shown to be a universal and programmable logic gate. Optimal NOT-majority-gate, G(sup 4)FET-based logic-circuit designs were obtained in a comparative study that also included formulation of functionally equivalent logic circuits based on NOR and NAND gates implemented by use of conventional transistors. In the study, the problem of finding the optimal design for each logic function and each transistor type was solved as an integer-programming optimization problem. Considering all 81 non-equivalent Boolean functions included in the study, it was found that in 63% of the cases, fewer logic gates (and, hence, fewer transistors) would be needed in the G(sup 4)FET-based implementations.

Valleytronics in merging Dirac cones: All-electric-controlled valley filter, valve, and universal reversible logic gate

NASA Astrophysics Data System (ADS)

Ang, Yee Sin; Yang, Shengyuan A.; Zhang, C.; Ma, Zhongshui; Ang, L. K.

2017-12-01

Despite much anticipation of valleytronics as a candidate to replace the aging complementary metal-oxide-semiconductor (CMOS) based information processing, its progress is severely hindered by the lack of practical ways to manipulate valley polarization all electrically in an electrostatic setting. Here, we propose a class of all-electric-controlled valley filter, valve, and logic gate based on the valley-contrasting transport in a merging Dirac cones system. The central mechanism of these devices lies on the pseudospin-assisted quantum tunneling which effectively quenches the transport of one valley when its pseudospin configuration mismatches that of a gate-controlled scattering region. The valley polarization can be abruptly switched into different states and remains stable over semi-infinite gate-voltage windows. Colossal tunneling valley-pseudomagnetoresistance ratio of over 10 000 % can be achieved in a valley-valve setup. We further propose a valleytronic-based logic gate capable of covering all 16 types of two-input Boolean logics. Remarkably, the valley degree of freedom can be harnessed to resurrect logical reversibility in two-input universal Boolean gate. The (2 +1 ) polarization states (two distinct valleys plus a null polarization) reestablish one-to-one input-to-output mapping, a crucial requirement for logical reversibility, and significantly reduce the complexity of reversible circuits. Our results suggest that the synergy of valleytronics and digital logics may provide new paradigms for valleytronic-based information processing and reversible computing.

Using Software Simulators to Enhance the Learning of Digital Logic Design for the Information Technology Students

ERIC Educational Resources Information Center

Alsadoon, Abeer; Prasad, P. W. C.; Beg, Azam

2017-01-01

Making the students understand the theoretical concepts of digital logic design concepts is one of the major issues faced by the academics, therefore the teachers have tried different techniques to link the theoretical information to the practical knowledge. Use of software simulations is a technique for learning and practice that can be applied…

Method and apparatus for digitally based high speed x-ray spectrometer

DOEpatents

Warburton, W.K.; Hubbard, B.

1997-11-04

A high speed, digitally based, signal processing system which accepts input data from a detector-preamplifier and produces a spectral analysis of the x-rays illuminating the detector. The system achieves high throughputs at low cost by dividing the required digital processing steps between a ``hardwired`` processor implemented in combinatorial digital logic, which detects the presence of the x-ray signals in the digitized data stream and extracts filtered estimates of their amplitudes, and a programmable digital signal processing computer, which refines the filtered amplitude estimates and bins them to produce the desired spectral analysis. One set of algorithms allow this hybrid system to match the resolution of analog systems while operating at much higher data rates. A second set of algorithms implemented in the processor allow the system to be self calibrating as well. The same processor also handles the interface to an external control computer. 19 figs.

Method and apparatus for digitally based high speed x-ray spectrometer

DOEpatents

Warburton, William K.; Hubbard, Bradley

1997-01-01

A high speed, digitally based, signal processing system which accepts input data from a detector-preamplifier and produces a spectral analysis of the x-rays illuminating the detector. The system achieves high throughputs at low cost by dividing the required digital processing steps between a "hardwired" processor implemented in combinatorial digital logic, which detects the presence of the x-ray signals in the digitized data stream and extracts filtered estimates of their amplitudes, and a programmable digital signal processing computer, which refines the filtered amplitude estimates and bins them to produce the desired spectral analysis. One set of algorithms allow this hybrid system to match the resolution of analog systems while operating at much higher data rates. A second set of algorithms implemented in the processor allow the system to be self calibrating as well. The same processor also handles the interface to an external control computer.

Community Digital Library Requirements for the Southern California Earthquake Center Community Modeling Environment (SCEC/CME)

NASA Astrophysics Data System (ADS)

Moore, R.; Faerman, M.; Minster, J.; Day, S. M.; Ely, G.

2003-12-01

A community digital library provides support for ingestion, organization, description, preservation, and access of digital entities. The technologies that traditionally provide these capabilities are digital libraries (ingestion, organization, description), persistent archives (preservation) and data grids (access). We present a design for the SCEC community digital library that incorporates aspects of all three systems. Multiple groups have created integrated environments that sustain large-scale scientific data collections. By examining these projects, the following stages of implementation can be identified: \\begin{itemize} Definition of semantic terms to associate with relevant information. This includes definition of uniform content descriptors to describe physical quantities relevant to the scientific discipline, and creation of concept spaces to define how the uniform content descriptors are logically related. Organization of digital entities into logical collections that make it simple to browse and manage related material. Definition of services that are used to access and manipulate material in the collection. Creation of a preservation environment for the long-term management of the collection. Each community is faced with heterogeneity that is introduced when data is distributed across multiple sites, or when multiple sets of collection semantics are used, and or when multiple scientific sub-disciplines are federated. We will present the relevant standards that simplify the implementation of the SCEC community library, the resource requirements for different types of data sets that drive the implementation, and the digital library processes that the SCEC community library will support. The SCEC community library can be viewed as the set of processing steps that are required to build the appropriate SCEC reference data sets (SCEC approved encoding format, SCEC approved descriptive metadata, SCEC approved collection organization, and SCEC managed storage location). Each digital entity that is ingested into the SCEC community library is processed and validated for conformance to SCEC standards. These steps generate provenance, descriptive, administrative, structural, and behavioral metadata. Using data grid technology, the descriptive metadata can be registered onto a logical name space that is controlled and managed by the SCEC digital library. A version of the SCEC community digital library is being implemented in the Storage Resource Broker. The SRB system provides almost all the features enumerated above. The peer-to-peer federation of metadata catalogs is planned for release in September, 2003. The SRB system is in production use in multiple projects, from high-energy physics, to astronomy, to earth systems science, to bio-informatics. The SCEC community library will be based on the definition of standard metadata attributes, the creation of logical collections within the SRB, the creation of access services, and the demonstration of a preservation environment. The use of the SRB for the SCEC digital library will sustain the expected collection size and collection capabilities.

Digital electronic engine control fault detection and accommodation flight evaluation

NASA Technical Reports Server (NTRS)

Baer-Ruedhart, J. L.

1984-01-01

The capabilities and performance of various fault detection and accommodation (FDA) schemes in existing and projected engine control systems were investigated. Flight tests of the digital electronic engine control (DEEC) in an F-15 aircraft show discrepancies between flight results and predictions based on simulation and altitude testing. The FDA methodology and logic in the DEEC system, and the results of the flight failures which occurred to date are described.

Energy-Efficient Wide Datapath Integer Arithmetic Logic Units Using Superconductor Logic

NASA Astrophysics Data System (ADS)

Ayala, Christopher Lawrence

Complementary Metal-Oxide-Semiconductor (CMOS) technology is currently the most widely used integrated circuit technology today. As CMOS approaches the physical limitations of scaling, it is unclear whether or not it can provide long-term support for niche areas such as high-performance computing and telecommunication infrastructure, particularly with the emergence of cloud computing. Alternatively, superconductor technologies based on Josephson junction (JJ) switching elements such as Rapid Single Flux Quantum (RSFQ) logic and especially its new variant, Energy-Efficient Rapid Single Flux Quantum (ERSFQ) logic have the capability to provide an ultra-high-speed, low power platform for digital systems. The objective of this research is to design and evaluate energy-efficient, high-speed 32-bit integer Arithmetic Logic Units (ALUs) implemented using RSFQ and ERSFQ logic as the first steps towards achieving practical Very-Large-Scale-Integration (VLSI) complexity in digital superconductor electronics. First, a tunable VHDL superconductor cell library is created to provide a mechanism to conduct design exploration and evaluation of superconductor digital circuits from the perspectives of functionality, complexity, performance, and energy-efficiency. Second, hybrid wave-pipelining techniques developed earlier for wide datapath RSFQ designs have been used for efficient arithmetic and logic circuit implementations. To develop the core foundation of the ALU, the ripple-carry adder and the Kogge-Stone parallel prefix carry look-ahead adder are studied as representative candidates on opposite ends of the design spectrum. By combining the high-performance features of the Kogge-Stone structure and the low complexity of the ripple-carry adder, a 32-bit asynchronous wave-pipelined hybrid sparse-tree ALU has been designed and evaluated using the VHDL cell library tuned to HYPRES' gate-level characteristics. The designs and techniques from this research have been implemented using RSFQ logic and prototype chips have been fabricated. As a joint work with HYPRES, a 20 GHz 8-bit Kogge-Stone ALU consisting of 7,950 JJs total has been fabricated using a 1.5 μm 4.5 kA/cm2 process and fully demonstrated. An 8-bit sparse-tree ALU (8,832 JJs total) and a 16-bit sparse-tree adder (12,785 JJs total) have also been fabricated using a 1.0 μm 10 kA/cm 2 process and demonstrated under collaboration with Yokohama National University and Nagoya University (Japan).

Compact universal logic gates realized using quantization of current in nanodevices.

PubMed

Zhang, Wancheng; Wu, Nan-Jian; Yang, Fuhua

2007-12-12

This paper proposes novel universal logic gates using the current quantization characteristics of nanodevices. In nanodevices like the electron waveguide (EW) and single-electron (SE) turnstile, the channel current is a staircase quantized function of its control voltage. We use this unique characteristic to compactly realize Boolean functions. First we present the concept of the periodic-threshold threshold logic gate (PTTG), and we build a compact PTTG using EW and SE turnstiles. We show that an arbitrary three-input Boolean function can be realized with a single PTTG, and an arbitrary four-input Boolean function can be realized by using two PTTGs. We then use one PTTG to build a universal programmable two-input logic gate which can be used to realize all two-input Boolean functions. We also build a programmable three-input logic gate by using one PTTG. Compared with linear threshold logic gates, with the PTTG one can build digital circuits more compactly. The proposed PTTGs are promising for future smart nanoscale digital system use.

Engineering integrated digital circuits with allosteric ribozymes for scaling up molecular computation and diagnostics.

PubMed

Penchovsky, Robert

2012-10-19

Here we describe molecular implementations of integrated digital circuits, including a three-input AND logic gate, a two-input multiplexer, and 1-to-2 decoder using allosteric ribozymes. Furthermore, we demonstrate a multiplexer-decoder circuit. The ribozymes are designed to seek-and-destroy specific RNAs with a certain length by a fully computerized procedure. The algorithm can accurately predict one base substitution that alters the ribozyme's logic function. The ability to sense the length of RNA molecules enables single ribozymes to be used as platforms for multiple interactions. These ribozymes can work as integrated circuits with the functionality of up to five logic gates. The ribozyme design is universal since the allosteric and substrate domains can be altered to sense different RNAs. In addition, the ribozymes can specifically cleave RNA molecules with triplet-repeat expansions observed in genetic disorders such as oculopharyngeal muscular dystrophy. Therefore, the designer ribozymes can be employed for scaling up computing and diagnostic networks in the fields of molecular computing and diagnostics and RNA synthetic biology.

Analytical design of a parasitic-loading digital speed controller for a 400-hertz turbine driven alternator

NASA Technical Reports Server (NTRS)

Ingle, B. D.; Ryan, J. P.

1972-01-01

A design for a solid-state parasitic speed controller using digital logic was analyzed. Parasitic speed controllers are used in space power electrical generating systems to control the speed of turbine-driven alternators within specified limits. The analysis included the performance characteristics of the speed controller and the generation of timing functions. The speed controller using digital logic applies step loads to the alternator. The step loads conduct for a full half wave starting at either zero or 180 electrical degrees.

F-15 digital electronic engine control system description

NASA Technical Reports Server (NTRS)

Myers, L. P.

1984-01-01

A digital electronic engine control (DEEC) was developed for use on the F100-PW-100 turbofan engine. This control system has full authority control, capable of moving all the controlled variables over their full ranges. The digital computational electronics and fault detection and accomodation logic maintains safe engine operation. A hydromechanical backup control (BUC) is an integral part of the fuel metering unit and provides gas generator control at a reduced performance level in the event of an electronics failure. The DEEC's features, hardware, and major logic diagrams are described.

Implementation of Adaptive Digital Controllers on Programmable Logic Devices

NASA Technical Reports Server (NTRS)

Gwaltney, David A.; King, Kenneth D.; Smith, Keary J.; Montenegro, Justino (Technical Monitor)

2002-01-01

Much has been made of the capabilities of Field Programmable Gate Arrays (FPGA's) in the hardware implementation of fast digital signal processing functions. Such capability also makes an FPGA a suitable platform for the digital implementation of closed loop controllers. Other researchers have implemented a variety of closed-loop digital controllers on FPGA's. Some of these controllers include the widely used Proportional-Integral-Derivative (PID) controller, state space controllers, neural network and fuzzy logic based controllers. There are myriad advantages to utilizing an FPGA for discrete-time control functions which include the capability for reconfiguration when SRAM- based FPGA's are employed, fast parallel implementation of multiple control loops and implementations that can meet space level radiation tolerance requirements in a compact form-factor. Generally, a software implementation on a Digital Signal Processor (DSP) device or microcontroller is used to implement digital controllers. At Marshall Space Flight Center, the Control Electronics Group has been studying adaptive discrete-time control of motor driven actuator systems using DSP devices. While small form factor, commercial DSP devices are now available with event capture, data conversion, Pulse Width Modulated (PWM) outputs and communication peripherals, these devices are not currently available in designs and packages which meet space level radiation requirements. In general, very few DSP devices are produced that are designed to meet any level of radiation tolerance or hardness. An alternative is required for compact implementation of such functionality to withstand the harsh environment encountered on spacemap. The goal of this effort is to create a fully digital, flight ready controller design that utilizes an FPGA for implementation of signal conditioning for control feedback signals, generation of commands to the controlled system, and hardware insertion of adaptive-control algorithm approaches. Radiation tolerant FPGA's are a feasible option for reaching this goal.

Digital Poetry: A Narrow Relation between Poetics and the Codes of the Computational Logic

NASA Astrophysics Data System (ADS)

Laurentiz, Silvia

The project "Percorrendo Escrituras" (Walking Through Writings Project) has been developed at ECA-USP Fine Arts Department. Summarizing, it intends to study different structures of digital information that share the same universe and are generators of a new aesthetics condition. The aim is to search which are the expressive possibilities of the computer among the algorithm functions and other of its specific properties. It is a practical, theoretical and interdisciplinary project where the study of programming evolutionary language, logic and mathematics take us to poetic experimentations. The focus of this research is the digital poetry, and it comes from poetics of permutation combinations and culminates with dynamic and complex systems, autonomous, multi-user and interactive, through agents generation derivations, filtration and emergent standards. This lecture will present artworks that use some mechanisms introduced by cybernetics and the notion of system in digital poetry that demonstrate the narrow relationship between poetics and the codes of computational logic.

Wide Tuning Capability for Spacecraft Transponders

NASA Technical Reports Server (NTRS)

Lux, James; Mysoor, Narayan; Shah, Biren; Cook, Brian; Smith, Scott

2007-01-01

A document presents additional information on the means of implementing a capability for wide tuning of microwave receiver and transmitter frequencies in the development reported in the immediately preceding article, VCO PLL Frequency Synthesizers for Spacecraft Transponders (NPO- 42909). The reference frequency for a PLL-based frequency synthesizer is derived from a numerically controlled oscillator (NCO) implemented in digital logic, such that almost any reference frequency can be derived from a fixed crystal reference oscillator with microhertz precision. The frequency of the NCO is adjusted to track the received signal, then used to create another NCO frequency used to synthesize the transmitted signal coherent with, and at a specified frequency ratio to, the received signal. The frequencies can be changed, even during operation, through suitable digital programming. The NCOs and the related tracking loops and coherent turnaround logic are implemented in a field-programmable gate array (FPGA). The interface between the analog microwave receiver and transmitter circuits and the FPGA includes analog-to-digital and digital-toanalog converters, the sampling rates of which are chosen to minimize spurious signals and otherwise optimize performance. Several mixers and filters are used to properly route various signals.

A Simple Memristor Model for Circuit Simulations

NASA Astrophysics Data System (ADS)

Fullerton, Farrah-Amoy; Joe, Aaleyah; Gergel-Hackett, Nadine; Department of Chemistry; Physics Team

This work describes the development of a model for the memristor, a novel nanoelectronic technology. The model was designed to replicate the real-world electrical characteristics of previously fabricated memristor devices, but was constructed with basic circuit elements using a free widely available circuit simulator, LT Spice. The modeled memrsistors were then used to construct a circuit that performs material implication. Material implication is a digital logic that can be used to perform all of the same basic functions as traditional CMOS gates, but with fewer nanoelectronic devices. This memristor-based digital logic could enable memristors' use in new paradigms of computer architecture with advantages in size, speed, and power over traditional computing circuits. Additionally, the ability to model the real-world electrical characteristics of memristors in a free circuit simulator using its standard library of elements could enable not only the development of memristor material implication, but also the development of a virtually unlimited array of other memristor-based circuits.

SWARM: A Compact High Resolution Correlator and Wideband VLBI Phased Array Upgrade for SMA

NASA Astrophysics Data System (ADS)

Weintroub, Jonathan

2014-06-01

A new digital back end (DBE) is being commissioned on Mauna Kea. The “SMA Wideband Astronomical ROACH2 Machine”, or SWARM, processes a 4 GHz usable band in single polarization mode and is flexibly reconfigurable for 2 GHz full Stokes dual polarization. The hardware is based on the open source Reconfigurable Open Architecture Computing Hardware 2 (ROACH2) platform from the Collaboration for Astronomy Signal Processing and Electronics Research (CASPER). A 5 GSps quad-core analog-to-digital converter board uses a commercial chip from e2v installed on a CASPER-standard printed circuit board designed by Homin Jiang’s group at ASIAA. Two ADC channels are provided per ROACH2, each sampling a 2.3 GHz Nyquist band generated by a custom wideband block downconverter (BDC). The ROACH2 logic includes 16k-channel Polyphase Filterbank (F-engine) per input followed by a 10 GbE switch based corner-turn which feeds into correlator-accumulator logic (X-engines) co-located with the F-engines. This arrangement makes very effective use of a small amount of digital hardware (just 8 ROACH2s in 1U rack mount enclosures). The primary challenge now is to meet timing at full speed for a large and very complex FPGA bit code. Design of the VLBI phased sum and recorder interface logic is also in process. Our poster will describe the instrument design, with the focus on the particular challenges of ultra wideband signal processing. Early connected commissioning and science verification data will be presented.

Method and apparatus for combinatorial logic signal processor in a digitally based high speed x-ray spectrometer

DOEpatents

Warburton, W.K.

1999-02-16

A high speed, digitally based, signal processing system is disclosed which accepts a digitized input signal and detects the presence of step-like pulses in the this data stream, extracts filtered estimates of their amplitudes, inspects for pulse pileup, and records input pulse rates and system lifetime. The system has two parallel processing channels: a slow channel, which filters the data stream with a long time constant trapezoidal filter for good energy resolution; and a fast channel which filters the data stream with a short time constant trapezoidal filter, detects pulses, inspects for pileups, and captures peak values from the slow channel for good events. The presence of a simple digital interface allows the system to be easily integrated with a digital processor to produce accurate spectra at high count rates and allow all spectrometer functions to be fully automated. Because the method is digitally based, it allows pulses to be binned based on time related values, as well as on their amplitudes, if desired. 31 figs.

A psychometric evaluation of the digital logic concept inventory

NASA Astrophysics Data System (ADS)

Herman, Geoffrey L.; Zilles, Craig; Loui, Michael C.

2014-10-01

Concept inventories hold tremendous promise for promoting the rigorous evaluation of teaching methods that might remedy common student misconceptions and promote deep learning. The measurements from concept inventories can be trusted only if the concept inventories are evaluated both by expert feedback and statistical scrutiny (psychometric evaluation). Classical Test Theory and Item Response Theory provide two psychometric frameworks for evaluating the quality of assessment tools. We discuss how these theories can be applied to assessment tools generally and then apply them to the Digital Logic Concept Inventory (DLCI). We demonstrate that the DLCI is sufficiently reliable for research purposes when used in its entirety and as a post-course assessment of students' conceptual understanding of digital logic. The DLCI can also discriminate between students across a wide range of ability levels, providing the most information about weaker students' ability levels.

Digital MOS integrated circuits

NASA Astrophysics Data System (ADS)

Elmasry, M. I.

MOS in digital circuit design is considered along with aspects of digital VLSI, taking into account a comparison of MOSFET logic circuits, 1-micrometer MOSFET VLSI technology, a generalized guide for MOSFET miniaturization, processing technologies, novel circuit structures for VLSI, and questions of circuit and system design for VLSI. MOS memory cells and circuits are discussed, giving attention to a survey of high-density dynamic RAM cell concepts, one-device cells for dynamic random-access memories, variable resistance polysilicon for high density CMOS Ram, high performance MOS EPROMs using a stacked-gate cell, and the optimization of the latching pulse for dynamic flip-flop sensors. Programmable logic arrays are considered along with digital signal processors, microprocessors, static RAMs, and dynamic RAMs.

Two-dimensional radiant energy array computers and computing devices

NASA Technical Reports Server (NTRS)

Schaefer, D. H.; Strong, J. P., III (Inventor)

1976-01-01

Two dimensional digital computers and computer devices operate in parallel on rectangular arrays of digital radiant energy optical signal elements which are arranged in ordered rows and columns. Logic gate devices receive two input arrays and provide an output array having digital states dependent only on the digital states of the signal elements of the two input arrays at corresponding row and column positions. The logic devices include an array of photoconductors responsive to at least one of the input arrays for either selectively accelerating electrons to a phosphor output surface, applying potentials to an electroluminescent output layer, exciting an array of discrete radiant energy sources, or exciting a liquid crystal to influence crystal transparency or reflectivity.

Logic Gates Made of N-Channel JFETs and Epitaxial Resistors

NASA Technical Reports Server (NTRS)

Krasowski, Michael J.

2008-01-01

Prototype logic gates made of n-channel junction field-effect transistors (JFETs) and epitaxial resistors have been demonstrated, with a view toward eventual implementation of digital logic devices and systems in silicon carbide (SiC) integrated circuits (ICs). This development is intended to exploit the inherent ability of SiC electronic devices to function at temperatures from 300 to somewhat above 500 C and withstand large doses of ionizing radiation. SiC-based digital logic devices and systems could enable operation of sensors and robots in nuclear reactors, in jet engines, near hydrothermal vents, and in other environments that are so hot or radioactive as to cause conventional silicon electronic devices to fail. At present, current needs for digital processing at high temperatures exceed SiC integrated circuit production capabilities, which do not allow for highly integrated circuits. Only single to small number component production of depletion mode n-channel JFETs and epitaxial resistors on a single substrate is possible. As a consequence, the fine matching of components is impossible, resulting in rather large direct-current parameter distributions within a group of transistors typically spanning multiples of 5 to 10. Add to this the lack of p-channel devices to complement the n-channel FETs, the lack of precise dropping diodes, and the lack of enhancement mode devices at these elevated temperatures and the use of conventional direct coupled and buffered direct coupled logic gate design techniques is impossible. The presented logic gate design is tolerant of device parameter distributions and is not hampered by the lack of complementary devices or dropping diodes. In addition to n-channel JFETs, these gates include level-shifting and load resistors (see figure). Instead of relying on precise matching of parameters among individual JFETS, these designs rely on choosing the values of these resistors and of supply potentials so as to make the circuits perform the desired functions throughout the ranges over which the parameters of the JFETs are distributed. The supply rails V(sub dd) and V(sub ss) and the resistors R are chosen as functions of the distribution of direct-current operating parameters of the group of transistors used.

Characterization of radiation effects in 65 nm digital circuits with the DRAD digital radiation test chip

NASA Astrophysics Data System (ADS)

Jara Casas, L. M.; Ceresa, D.; Kulis, S.; Miryala, S.; Christiansen, J.; Francisco, R.; Gnani, D.

2017-02-01

A Digital RADiation (DRAD) test chip has been specifically designed to study the impact of Total Ionizing Dose (TID) (<1 Grad) and Single Event Upset (SEU) on digital logic gates in a 65 nm CMOS technology. Nine different versions of standard cell libraries are studied in this chip, basically differing in the device dimensions, Vt flavor and layout of the device. Each library has eighteen test structures specifically designed to characterize delay degradation and power consumption of the standard cells. For SEU study, a dedicated test structure based on a shift register is designed for each library. TID results up to 500 Mrad are reported.

On the design of high-speed energy-efficient successive-approximation logic for asynchronous SAR ADCs

NASA Astrophysics Data System (ADS)

Yang, Jiaqi; Li, Ting; Yu, Mingyuan; Zhang, Shuangshuang; Lin, Fujiang; He, Lin

2017-08-01

This paper analyzes the power consumption and delay mechanisms of the successive-approximation (SA) logic of a typical asynchronous SAR ADC, and provides strategies to reduce both of them. Following these strategies, a unique direct-pass SA logic is proposed based on a full-swing once-triggered DFF and a self-locking tri-state gate. The unnecessary internal switching power of a typical TSPC DFF, which is commonly used in the SA logic, is avoided. The delay of the ready detector as well as the sequencer is removed from the critical path. A prototype SAR ADC based on the proposed SA logic is fabricated in 130 nm CMOS. It achieves a peak SNDR of 56.3 dB at 1.2 V supply and 65 MS/s sampling rate, and has a total power consumption of 555 μW, while the digital part consumes only 203 μW. Project supported by the National Natural Science Foundation of China (Nos. 61204033, 61331015), the Fundamental Research Funds for the Central Universities (No. WK2100230015), and the Funds of Science and Technology on Analog Integrated Circuit Laboratory (No. 9140C090111150C09041).

Fuzzy logic particle tracking velocimetry

NASA Technical Reports Server (NTRS)

Wernet, Mark P.

1993-01-01

Fuzzy logic has proven to be a simple and robust method for process control. Instead of requiring a complex model of the system, a user defined rule base is used to control the process. In this paper the principles of fuzzy logic control are applied to Particle Tracking Velocimetry (PTV). Two frames of digitally recorded, single exposure particle imagery are used as input. The fuzzy processor uses the local particle displacement information to determine the correct particle tracks. Fuzzy PTV is an improvement over traditional PTV techniques which typically require a sequence (greater than 2) of image frames for accurately tracking particles. The fuzzy processor executes in software on a PC without the use of specialized array or fuzzy logic processors. A pair of sample input images with roughly 300 particle images each, results in more than 200 velocity vectors in under 8 seconds of processing time.

Ideas in Practice (3): A Simulated Laboratory Experience in Digital Design.

ERIC Educational Resources Information Center

Cleaver, Thomas G.

1988-01-01

Gives an example of the use of a simplified logic simulator in a logic design course. Discusses some problems in logic design classes, commercially available software, and software problems. Describes computer-aided engineering (CAE) software. Lists 14 experiments in the simulated laboratory and presents students' evaluation of the course. (YP)

Teaching Discrete and Programmable Logic Design Techniques Using a Single Laboratory Board

ERIC Educational Resources Information Center

Debiec, P.; Byczuk, M.

2011-01-01

Programmable logic devices (PLDs) are used at many universities in introductory digital logic laboratories, where kits containing a single high-capacity PLD replace "standard" sets containing breadboards, wires, and small- or medium-scale integration (SSI/MSI) chips. From the pedagogical point of view, two problems arise in these…

The Effects of Web-Based and Face-to-Face Discussion on Computer Engineering Majors' Performance on the Karnaugh Map

ERIC Educational Resources Information Center

Hung, Yen-Chu

2011-01-01

This study investigates the different effects of web-based and face-to-face discussion on computer engineering majors' performance using the Karnaugh map in digital logic design. Pretest and posttest scores for two treatment groups (web-based discussion and face-to-face discussion) and a control group were compared and subjected to covariance…

Source-Coupled, N-Channel, JFET-Based Digital Logic Gate Structure Using Resistive Level Shifters

NASA Technical Reports Server (NTRS)

Krasowski, Michael J.

2011-01-01

A circuit topography is used to create usable, digital logic gates using N (negatively doped) channel junction field effect transistors (JFETs), load resistors, level shifting resistors, and supply rails whose values are based on the DC parametric distributions of these JFETs. This method has direct application to the current state-of-the-art in high-temperature (300 to 500 C and higher) silicon carbide (SiC) device production, and defines an adaptation to the logic gate described in U.S. Patent 7,688,117 in that, by removing the level shifter from the output of the gate structure described in the patent (and applying it to the input of the same gate), a source-coupled gate topography is created. This structure allows for the construction AND/OR (sum of products) arrays that use far fewer transistors and resistors than the same array as constructed from the gates described in the aforementioned patent. This plays a central role when large multiplexer constructs are necessary; for example, as in the construction of memory. This innovation moves the resistive level shifter from the output of the basic gate structure to the front as if the input is now configured as what would be the output of the preceding gate, wherein the output is the two level shifting resistors. The output of this innovation can now be realized as the lone follower transistor with its source node as the gate output. Additionally, one may leave intact the resistive level shifter on the new gate topography. A source-coupled to direct-coupled logic translator will be the result.

Encoding Schemes For A Digital Optical Multiplier Using The Modified Signed-Digit Number Representation

NASA Astrophysics Data System (ADS)

Lasher, Mark E.; Henderson, Thomas B.; Drake, Barry L.; Bocker, Richard P.

1986-09-01

The modified signed-digit (MSD) number representation offers full parallel, carry-free addition. A MSD adder has been described by the authors. This paper describes how the adder can be used in a tree structure to implement an optical multiply algorithm. Three different optical schemes, involving position, polarization, and intensity encoding, are proposed for realizing the trinary logic system. When configured in the generic multiplier architecture, these schemes yield the combinatorial logic necessary to carry out the multiplication algorithm. The optical systems are essentially three dimensional arrangements composed of modular units. Of course, this modularity is important for design considerations, while the parallelism and noninterfering communication channels of optical systems are important from the standpoint of reduced complexity. The authors have also designed electronic hardware to demonstrate and model the combinatorial logic required to carry out the algorithm. The electronic and proposed optical systems will be compared in terms of complexity and speed.

Improving learning performance with happiness by interactive scenarios.

PubMed

Chuang, Chi-Hung; Chen, Ying-Nong; Tsai, Luo-Wei; Lee, Chun-Chieh; Tsai, Hsin-Chun

2014-01-01

Recently, digital learning has attracted a lot of researchers to improve the problems of learning carelessness, low learning ability, lack of concentration, and difficulties in comprehending the logic of math. In this study, a digital learning system based on Kinect somatosensory system is proposed to make children and teenagers happily learn in the course of the games and improve the learning performance. We propose two interactive geometry and puzzle games. The proposed somatosensory games can make learners feel curious and raise their motivation to find solutions for boring problems via abundant physical expressions and interactive operations. The players are asked to select particular operation by gestures and physical expressions within a certain time. By doing so, the learners can feel the fun of game playing and train their logic ability before they are aware. Experimental results demonstrate that the proposed somatosensory system can effectively improve the students' learning performance.

Implementing finite state machines in a computer-based teaching system

NASA Astrophysics Data System (ADS)

Hacker, Charles H.; Sitte, Renate

1999-09-01

Finite State Machines (FSM) are models for functions commonly implemented in digital circuits such as timers, remote controls, and vending machines. Teaching FSM is core in the curriculum of many university digital electronic or discrete mathematics subjects. Students often have difficulties grasping the theoretical concepts in the design and analysis of FSM. This has prompted the author to develop an MS-WindowsTM compatible software, WinState, that provides a tutorial style teaching aid for understanding the mechanisms of FSM. The animated computer screen is ideal for visually conveying the required design and analysis procedures. WinState complements other software for combinatorial logic previously developed by the author, and enhances the existing teaching package by adding sequential logic circuits. WinState enables the construction of a students own FSM, which can be simulated, to test the design for functionality and possible errors.

Improving Learning Performance with Happiness by Interactive Scenarios

PubMed Central

Chuang, Chi-Hung; Chen, Ying-Nong; Tsai, Luo-Wei; Lee, Chun-Chieh; Tsai, Hsin-Chun

2014-01-01

Recently, digital learning has attracted a lot of researchers to improve the problems of learning carelessness, low learning ability, lack of concentration, and difficulties in comprehending the logic of math. In this study, a digital learning system based on Kinect somatosensory system is proposed to make children and teenagers happily learn in the course of the games and improve the learning performance. We propose two interactive geometry and puzzle games. The proposed somatosensory games can make learners feel curious and raise their motivation to find solutions for boring problems via abundant physical expressions and interactive operations. The players are asked to select particular operation by gestures and physical expressions within a certain time. By doing so, the learners can feel the fun of game playing and train their logic ability before they are aware. Experimental results demonstrate that the proposed somatosensory system can effectively improve the students' learning performance. PMID:24558331

Efficient Multiplexer FPGA Block Structures Based on G4FETs

NASA Technical Reports Server (NTRS)

Vatan, Farrokh; Fijany, Amir

2009-01-01

Generic structures have been conceived for multiplexer blocks to be implemented in field-programmable gate arrays (FPGAs) based on four-gate field-effect transistors (G(sup 4)FETs). This concept is a contribution to the continuing development of digital logic circuits based on G4FETs and serves as a further demonstration that logic circuits based on G(sup 4)FETs could be more efficient (in the sense that they could contain fewer transistors), relative to functionally equivalent logic circuits based on conventional transistors. Results in this line of development at earlier stages were summarized in two previous NASA Tech Briefs articles: "G(sup 4)FETs as Universal and Programmable Logic Gates" (NPO-41698), Vol. 31, No. 7 (July 2007), page 44, and "Efficient G4FET-Based Logic Circuits" (NPO-44407), Vol. 32, No. 1 ( January 2008), page 38 . As described in the first-mentioned previous article, a G4FET can be made to function as a three-input NOT-majority gate, which has been shown to be a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer components than are required for conventional transistor-based circuits performing the same logic functions. The second-mentioned previous article reported results of a comparative study of NOT-majority-gate (G(sup 4)FET)-based logic-circuit designs and equivalent NOR- and NAND-gate-based designs utilizing conventional transistors. [NOT gates (inverters) were also included, as needed, in both the G(sup 4)FET- and the NOR- and NAND-based designs.] In most of the cases studied, fewer logic gates (and, hence, fewer transistors), were required in the G(sup 4)FET-based designs. There are two popular categories of FPGA block structures or architectures: one based on multiplexers, the other based on lookup tables. In standard multiplexer- based architectures, the basic building block is a tree-like configuration of multiplexers, with possibly a few additional logic gates such as ANDs or ORs. Interconnections are realized by means of programmable switches that may connect the input terminals of a block to output terminals of other blocks, may bridge together some of the inputs, or may connect some of the input terminals to signal sources representing constant logical levels 0 or 1. The left part of the figure depicts a four-to-one G(sup 4)FET-based multiplexer tree; the right part of the figure depicts a functionally equivalent four-to-one multiplexer based on conventional transistors. The G(sup 4)FET version would contains 54 transistors; the conventional version contains 70 transistors.

New trends in logic synthesis for both digital designing and data processing

NASA Astrophysics Data System (ADS)

Borowik, Grzegorz; Łuba, Tadeusz; Poźniak, Krzysztof

2016-09-01

FPGA devices are equipped with memory-based structures. These memories act as very large logic cells where the number of inputs equals the number of address lines. At the same time, there is a huge demand in the market of Internet of Things for devices implementing virtual routers, intrusion detection systems, etc.; where such memories are crucial for realizing pattern matching circuits, IP address tables, and other. Unfortunately, existing CAD tools are not well suited to utilize capabilities that such large memory blocks offer due to the lack of appropriate synthesis procedures. This paper presents methods which are useful for memory-based implementations: minimization of the number of input variables and functional decomposition.

Designing learning apparatus to promote twelfth grade students’ understanding of digital technology concept: A preliminary studies

NASA Astrophysics Data System (ADS)

Marlius; Kaniawati, I.; Feranie, S.

2018-05-01

A preliminary learning design using relay to promote twelfth grade student’s understanding of logic gates concept is implemented to see how well it’s to adopted by six high school students, three male students and three female students of twelfth grade. This learning design is considered for next learning of digital technology concept i.e. data digital transmition and analog. This work is a preliminary study to design the learning for large class. So far just a few researches designing learning design related to digital technology with relay. It may due to this concept inserted in Indonesian twelfth grade curriculum recently. This analysis is focus on student difficulties trough video analysis to learn the concept. Based on our analysis, the recommended thing for redesigning learning is: students understand first about symbols and electrical circuits; the Student Worksheet is made in more detail on the assembly steps to the project board; mark with symbols at points in certain places in the circuit for easy assembly; assembly using relays by students is enough until is the NOT’s logic gates and the others that have been assembled so that effective time. The design of learning using relays can make the relay a liaison between the abstract on the digital with the real thing of it, especially in the circuit of symbols and real circuits. Besides it is expected to also enrich the ability of teachers in classroom learning about digital technology.

Parallel database search and prime factorization with magnonic holographic memory devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Khitun, Alexander

In this work, we describe the capabilities of Magnonic Holographic Memory (MHM) for parallel database search and prime factorization. MHM is a type of holographic device, which utilizes spin waves for data transfer and processing. Its operation is based on the correlation between the phases and the amplitudes of the input spin waves and the output inductive voltage. The input of MHM is provided by the phased array of spin wave generating elements allowing the producing of phase patterns of an arbitrary form. The latter makes it possible to code logic states into the phases of propagating waves and exploitmore » wave superposition for parallel data processing. We present the results of numerical modeling illustrating parallel database search and prime factorization. The results of numerical simulations on the database search are in agreement with the available experimental data. The use of classical wave interference may results in a significant speedup over the conventional digital logic circuits in special task data processing (e.g., √n in database search). Potentially, magnonic holographic devices can be implemented as complementary logic units to digital processors. Physical limitations and technological constrains of the spin wave approach are also discussed.« less

Parallel database search and prime factorization with magnonic holographic memory devices

NASA Astrophysics Data System (ADS)

Khitun, Alexander

2015-12-01

In this work, we describe the capabilities of Magnonic Holographic Memory (MHM) for parallel database search and prime factorization. MHM is a type of holographic device, which utilizes spin waves for data transfer and processing. Its operation is based on the correlation between the phases and the amplitudes of the input spin waves and the output inductive voltage. The input of MHM is provided by the phased array of spin wave generating elements allowing the producing of phase patterns of an arbitrary form. The latter makes it possible to code logic states into the phases of propagating waves and exploit wave superposition for parallel data processing. We present the results of numerical modeling illustrating parallel database search and prime factorization. The results of numerical simulations on the database search are in agreement with the available experimental data. The use of classical wave interference may results in a significant speedup over the conventional digital logic circuits in special task data processing (e.g., √n in database search). Potentially, magnonic holographic devices can be implemented as complementary logic units to digital processors. Physical limitations and technological constrains of the spin wave approach are also discussed.

System for adjusting frequency of electrical output pulses derived from an oscillator

DOEpatents

Bartholomew, David B.

2006-11-14

A system for setting and adjusting a frequency of electrical output pulses derived from an oscillator in a network is disclosed. The system comprises an accumulator module configured to receive pulses from an oscillator and to output an accumulated value. An adjustor module is configured to store an adjustor value used to correct local oscillator drift. A digital adder adds values from the accumulator module to values stored in the adjustor module and outputs their sums to the accumulator module, where they are stored. The digital adder also outputs an electrical pulse to a logic module. The logic module is in electrical communication with the adjustor module and the network. The logic module may change the value stored in the adjustor module to compensate for local oscillator drift or change the frequency of output pulses. The logic module may also keep time and calculate drift.

From Prosumer to Prodesigner: Participatory News Consumption

ERIC Educational Resources Information Center

Hernández-Serrano, María-José; Renés-Arellano, Paula; Graham, Gary; Greenhill, Anita

2017-01-01

New democratic participation forms and collaborative productions of diverse audiences have emerged as a result of digital innovations in the online access to and consumption of news. The aim of this paper is to propose a conceptual framework based on the possibilities of Web 2.0. outlining the construction of a "social logic," which…

A Descriptive Study Examining the Impact of Digital Writing Environments on Communication and Mathematical Reasoning for Students with Learning Disabilities

ERIC Educational Resources Information Center

Huscroft-D'Angelo, Jacqueline; Higgins, Kristina N.; Crawford, Lindy L.

2014-01-01

Proficiency in mathematics, including mathematical reasoning skills, requires students to communicate their mathematical thinking. Mathematical reasoning involves making sense of mathematical concepts in a logical way to form conclusions or judgments, and is often underdeveloped in students with learning disabilities. Technology-based environments…

Lyceum: A Multi-Protocol Digital Library Gateway

NASA Technical Reports Server (NTRS)

Maa, Ming-Hokng; Nelson, Michael L.; Esler, Sandra L.

1997-01-01

Lyceum is a prototype scalable query gateway that provides a logically central interface to multi-protocol and physically distributed, digital libraries of scientific and technical information. Lyceum processes queries to multiple syntactically distinct search engines used by various distributed information servers from a single logically central interface without modification of the remote search engines. A working prototype (http://www.larc.nasa.gov/lyceum/) demonstrates the capabilities, potentials, and advantages of this type of meta-search engine by providing access to over 50 servers covering over 20 disciplines.

Airstart performance of a digital electronic engine control system on an F100 engine

NASA Technical Reports Server (NTRS)

Burcham, F. W., Jr.

1984-01-01

The digital electronic engine control (DEEC) system installed on an F100 engine in an F-15 aircraft was tested. The DEEC system incorporates a closed-loop air start feature in which the fuel flow is modulated to achieve the desired rate of compressor acceleration. With this logic the DEEC equipped F100 engine can achieve air starts over a larger envelope. The DEEC air start logic, the test program conducted on the F-15, and its results are described.

The Process, Dialogues, and Attitudes of Vocational Engineering High School Students in a Web Problem-Based Learning (WPBL) System

ERIC Educational Resources Information Center

Tseng, Kuo-Hung; Chang, Chi-Cheng; Lou, Shi-Jer

2012-01-01

This study aims to explore how high school students collaboratively solve problems in a web problem-based learning (WPBL) system in an 8-week digital logic course using discourse analysis. Employing in-depth interviews, this study also investigated the students' attitudes toward the WPBL system. The number of teaching assistants' responses had a…

Degradations to microprocessor-based systems due to environmental stressors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Messman, P. A.; Peilai, Z.; Goodenow, D. A.

Recent studies indicate that EMI/RFI is the most significant environmental Stressor with potential for leading to digital systems degradation and failure. With digital I and C and wireless technology becoming standard in many industrial environments, nuclear power plant operators of current and future plants will or already have implemented these technologies seeking to leverage the economic benefits of such technology. With digital I and C systems' higher susceptibility to EMI/RFI and the increased environmental noise introduced by wireless-based systems, this produces a dangerous combination that could lead to logic errors, equipment damage, and faults in digital I and C. Failuresmore » to these systems, especially to safety-critical systems, could lead to loss of system, which would pose a safety risk and decrease in operational efficiency. In order to better understand system degradations by these means and aid in regulation and guidance, we propose to experimentally study the susceptibility of digital I and C to wireless technology. (authors)« less

Analog Signal Correlating Using an Analog-Based Signal Conditioning Front End

NASA Technical Reports Server (NTRS)

Prokop, Norman; Krasowski, Michael

2013-01-01

This innovation is capable of correlating two analog signals by using an analog-based signal conditioning front end to hard-limit the analog signals through adaptive thresholding into a binary bit stream, then performing the correlation using a Hamming "similarity" calculator function embedded in a one-bit digital correlator (OBDC). By converting the analog signal into a bit stream, the calculation of the correlation function is simplified, and less hardware resources are needed. This binary representation allows the hardware to move from a DSP where instructions are performed serially, into digital logic where calculations can be performed in parallel, greatly speeding up calculations.

Proposal for nanoscale cascaded plasmonic majority gates for non-Boolean computation.

PubMed

Dutta, Sourav; Zografos, Odysseas; Gurunarayanan, Surya; Radu, Iuliana; Soree, Bart; Catthoor, Francky; Naeemi, Azad

2017-12-19

Surface-plasmon-polariton waves propagating at the interface between a metal and a dielectric, hold the key to future high-bandwidth, dense on-chip integrated logic circuits overcoming the diffraction limitation of photonics. While recent advances in plasmonic logic have witnessed the demonstration of basic and universal logic gates, these CMOS oriented digital logic gates cannot fully utilize the expressive power of this novel technology. Here, we aim at unraveling the true potential of plasmonics by exploiting an enhanced native functionality - the majority voter. Contrary to the state-of-the-art plasmonic logic devices, we use the phase of the wave instead of the intensity as the state or computational variable. We propose and demonstrate, via numerical simulations, a comprehensive scheme for building a nanoscale cascadable plasmonic majority logic gate along with a novel referencing scheme that can directly translate the information encoded in the amplitude and phase of the wave into electric field intensity at the output. Our MIM-based 3-input majority gate displays a highly improved overall area of only 0.636 μm 2 for a single-stage compared with previous works on plasmonic logic. The proposed device demonstrates non-Boolean computational capability and can find direct utility in highly parallel real-time signal processing applications like pattern recognition.

Programmable Logic Application Notes

NASA Technical Reports Server (NTRS)

Katz, Richard

2000-01-01

This column will be provided each quarter as a source for reliability, radiation results, NASA capabilities, and other information on programmable logic devices and related applications. This quarter will continue a series of notes concentrating on analysis techniques with this issue's section discussing: Digital Timing Analysis Tools and Techniques. Articles in this issue include: SX and SX-A Series Devices Power Sequencing; JTAG and SXISX-AISX-S Series Devices; Analysis Techniques (i.e., notes on digital timing analysis tools and techniques); Status of the Radiation Hard reconfigurable Field Programmable Gate Array Program, Input Transition Times; Apollo Guidance Computer Logic Study; RT54SX32S Prototype Data Sets; A54SX32A - 0.22 micron/UMC Test Results; Ramtron FM1608 FRAM; and Analysis of VHDL Code and Synthesizer Output.

Digital Ratiometer

NASA Technical Reports Server (NTRS)

Beer, R.

1985-01-01

Small, low-cost comparator with 24-bit-precision yields ratio signal from pair of analog or digital input signals. Arithmetic logic chips (bit-slice) sample two 24-bit analog-to-digital converters approximately once every millisecond and accumulate them in two 24-bit registers. Approach readily modified to arbitrary precision.

Hydraulic logic gates: building a digital water computer

NASA Astrophysics Data System (ADS)

Taberlet, Nicolas; Marsal, Quentin; Ferrand, Jérémy; Plihon, Nicolas

2018-03-01

In this article, we propose an easy-to-build hydraulic machine which serves as a digital binary computer. We first explain how an elementary adder can be built from test tubes and pipes (a cup filled with water representing a 1, and empty cup a 0). Using a siphon and a slow drain, the proposed setup combines AND and XOR logical gates in a single device which can add two binary digits. We then show how these elementary units can be combined to construct a full 4-bit adder. The sequencing of the computation is discussed and a water clock can be incorporated so that the machine can run without any exterior intervention.

Formal Verification of Digital Logic

DTIC Science & Technology

1991-12-01

INVERT circuit was based upon VHDL code provided in the Zycad Reference Manual [32:Ch 10,73]. The other circuits were based upon VHtDL code written...HALFADD.PL /* This file implements a simple half-adder that * /* is built from inverters and 2 input nand gates. * /* It is based upon a Zycad VHDL file...It is based upon a Zycad VHDL file written by * /* Capt Dave Banton, which is attached below the * /* Prolog code . *load..in(primitive). %h get nor2

Practical applications of digital integrated circuits. Part 2: Minimization techniques, code conversion, flip-flops, and asynchronous circuits

NASA Technical Reports Server (NTRS)

1972-01-01

Here, the 7400 line of transistor to transistor logic (TTL) devices is emphasized almost exclusively where hardware is concerned. However, it should be pointed out that the logic theory contained herein applies to all hardware. Binary numbers, simplification of logic circuits, code conversion circuits, basic flip-flop theory, details about series 54/7400, and asynchronous circuits are discussed.

Field Effect Transistor Behavior in Electrospun Polyaniline/Polyethylene Oxide Nanofibers

NASA Technical Reports Server (NTRS)

Miranda, Felix A.; Theofylaktos, Noulle; Robinson, Daryl C.; Mueller, Carl H.; Pinto, Nicholas J.

2004-01-01

Novel translators and logic devices based on nanotechnology concepts are under intense development. The potential for ultra-low power circuitry makes nanotechnology attractive for applications such as digital electronics and sensors. Furthermore, the ability to form devices on flexible substrates expands the range of applications where electronic circuitry can be introduced. For NASA, nonotechndogy offers opportunities for increased onboard data processing and thus autonomous decision-making ability, ad novel sensors that detect and respond to external stimuli with few oversight requirements. The goat of this work is to demonstrate transistor behavior in polyaniline/ polyethylene oxide nanofibers, thus creating a foundation for future logic devices.

Risk-Informed Safety Assurance and Probabilistic Assessment of Mission-Critical Software-Intensive Systems

NASA Technical Reports Server (NTRS)

Guarro, Sergio B.

2010-01-01

This report validates and documents the detailed features and practical application of the framework for software intensive digital systems risk assessment and risk-informed safety assurance presented in the NASA PRA Procedures Guide for Managers and Practitioner. This framework, called herein the "Context-based Software Risk Model" (CSRM), enables the assessment of the contribution of software and software-intensive digital systems to overall system risk, in a manner which is entirely compatible and integrated with the format of a "standard" Probabilistic Risk Assessment (PRA), as currently documented and applied for NASA missions and applications. The CSRM also provides a risk-informed path and criteria for conducting organized and systematic digital system and software testing so that, within this risk-informed paradigm, the achievement of a quantitatively defined level of safety and mission success assurance may be targeted and demonstrated. The framework is based on the concept of context-dependent software risk scenarios and on the modeling of such scenarios via the use of traditional PRA techniques - i.e., event trees and fault trees - in combination with more advanced modeling devices such as the Dynamic Flowgraph Methodology (DFM) or other dynamic logic-modeling representations. The scenarios can be synthesized and quantified in a conditional logic and probabilistic formulation. The application of the CSRM method documented in this report refers to the MiniAERCam system designed and developed by the NASA Johnson Space Center.

Computer-Aided Design Package for Designers of Digital Optical Computers

DTIC Science & Technology

1991-02-01

circuit depth and in circuit breadth. It appears, from initial studies by PhD students Gupta and Majidi using the newly modified tools, that a few irregular...Gupta, which is based on an earlier tool developed by Majidi . The tool allows logic gates to have fan-ins and fan-outs that vary, and allows circuits

A molecular-sized optical logic circuit for digital modulation of a fluorescence signal

NASA Astrophysics Data System (ADS)

Nishimura, Takahiro; Tsuchida, Karin; Ogura, Yusuke; Tanida, Jun

2018-03-01

Fluorescence measurement allows simultaneous detection of multiple molecular species by using spectrally distinct fluorescence probes. However, due to the broad spectra of fluorescence emission, the multiplicity of fluorescence measurement is generally limited. To overcome this limitation, we propose a method to digitally modulate fluorescence output signals with a molecular-sized optical logic circuit by using optical control of fluorescence resonance energy transfer (FRET). The circuit receives a set of optical inputs represented with different light wavelengths, and then it switches high and low fluorescence intensity from a reporting molecule according to the result of the logic operation. By using combinational optical inputs in readout of fluorescence signals, the number of biomolecular species that can be identified is increased. To implement the FRET-based circuits, we designed two types of basic elements, YES and NOT switches. An YES switch produces a high-level output intensity when receiving a designated light wavelength input and a low-level intensity without the light irradiation. A NOT switch operates inversely to the YES switch. In experiments, we investigated the operation of the YES and NOT switches that receive a 532-nm light input and modulate the fluorescence intensity of Alexa Fluor 488. The experimental result demonstrates that the switches can modulate fluorescence signals according to the optical input.

Design Time Optimization for Hardware Watermarking Protection of HDL Designs

PubMed Central

Castillo, E.; Morales, D. P.; García, A.; Parrilla, L.; Todorovich, E.; Meyer-Baese, U.

2015-01-01

HDL-level design offers important advantages for the application of watermarking to IP cores, but its complexity also requires tools automating these watermarking algorithms. A new tool for signature distribution through combinational logic is proposed in this work. IPP@HDL, a previously proposed high-level watermarking technique, has been employed for evaluating the tool. IPP@HDL relies on spreading the bits of a digital signature at the HDL design level using combinational logic included within the original system. The development of this new tool for the signature distribution has not only extended and eased the applicability of this IPP technique, but it has also improved the signature hosting process itself. Three algorithms were studied in order to develop this automated tool. The selection of a cost function determines the best hosting solutions in terms of area and performance penalties on the IP core to protect. An 1D-DWT core and MD5 and SHA1 digital signatures were used in order to illustrate the benefits of the new tool and its optimization related to the extraction logic resources. Among the proposed algorithms, the alternative based on simulated annealing reduces the additional resources while maintaining an acceptable computation time and also saving designer effort and time. PMID:25861681

Development of the automatic test pattern generation for NPP digital electronic circuits using the degree of freedom concept

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kim, D.S.; Seong, P.H.

1995-08-01

In this paper, an improved algorithm for automatic test pattern generation (ATG) for nuclear power plant digital electronic circuits--the combinational type of logic circuits is presented. For accelerating and improving the ATG process for combinational circuits the presented ATG algorithm has the new concept--the degree of freedom (DF). The DF, directly computed from the system descriptions such as types of gates and their interconnections, is the criterion to decide which among several alternate lines` logic values required along each path promises to be the most effective in order to accelerate and improve the ATG process. Based on the DF themore » proposed ATG algorithm is implemented in the automatic fault diagnosis system (AFDS) which incorporates the advanced fault diagnosis method of artificial intelligence technique, it is shown that the AFDS using the ATG algorithm makes Universal Card (UV Card) testing much faster than the present testing practice or by using exhaustive testing sets.« less

Qubits and quantum Hamiltonian computing performances for operating a digital Boolean 1/2-adder

NASA Astrophysics Data System (ADS)

Dridi, Ghassen; Faizy Namarvar, Omid; Joachim, Christian

2018-04-01

Quantum Boolean (1 + 1) digits 1/2-adders are designed with 3 qubits for the quantum computing (Qubits) and 4 quantum states for the quantum Hamiltonian computing (QHC) approaches. Detailed analytical solutions are provided to analyse the time operation of those different 1/2-adder gates. QHC is more robust to noise than Qubits and requires about the same amount of energy for running its 1/2-adder logical operations. QHC is faster in time than Qubits but its logical output measurement takes longer.

Digital transmitter for data bus communications system

NASA Technical Reports Server (NTRS)

Proch, G. E. (Inventor)

1975-01-01

An improved digital transmitter for transmitting serial pulse code modulation (pcm) data at high bit rates over a transmission line is disclosed. When not transmitting, the transmitter features a high output impedance which prevents the transmitter from loading the transmission line. The pcm input is supplied to a logic control circuit which produces two discrete logic level signals which are supplied to an amplifier. The amplifier, which is transformer coupled to the output isolation circuitry, converts the discrete logic level signals to two high current level, ground isolated signals in the secondary windings of the coupling transformer. The latter signals are employed as inputs to the isolation circuitry which includes two series transistor pairs operating into a hybrid transformer functioning to isolate the transmitter circuitry from the transmission line.

VLSI-based video event triggering for image data compression

NASA Astrophysics Data System (ADS)

Williams, Glenn L.

1994-02-01

Long-duration, on-orbit microgravity experiments require a combination of high resolution and high frame rate video data acquisition. The digitized high-rate video stream presents a difficult data storage problem. Data produced at rates of several hundred million bytes per second may require a total mission video data storage requirement exceeding one terabyte. A NASA-designed, VLSI-based, highly parallel digital state machine generates a digital trigger signal at the onset of a video event. High capacity random access memory storage coupled with newly available fuzzy logic devices permits the monitoring of a video image stream for long term (DC-like) or short term (AC-like) changes caused by spatial translation, dilation, appearance, disappearance, or color change in a video object. Pre-trigger and post-trigger storage techniques are then adaptable to archiving only the significant video images.

VLSI-based Video Event Triggering for Image Data Compression

NASA Technical Reports Server (NTRS)

Williams, Glenn L.

1994-01-01

Long-duration, on-orbit microgravity experiments require a combination of high resolution and high frame rate video data acquisition. The digitized high-rate video stream presents a difficult data storage problem. Data produced at rates of several hundred million bytes per second may require a total mission video data storage requirement exceeding one terabyte. A NASA-designed, VLSI-based, highly parallel digital state machine generates a digital trigger signal at the onset of a video event. High capacity random access memory storage coupled with newly available fuzzy logic devices permits the monitoring of a video image stream for long term (DC-like) or short term (AC-like) changes caused by spatial translation, dilation, appearance, disappearance, or color change in a video object. Pre-trigger and post-trigger storage techniques are then adaptable to archiving only the significant video images.

Evolution of Scientific and Technical Information Distribution

NASA Technical Reports Server (NTRS)

Esler, Sandra; Nelson, Michael L.

1998-01-01

World Wide Web (WWW) and related information technologies are transforming the distribution of scientific and technical information (STI). We examine 11 recent, functioning digital libraries focusing on the distribution of STI publications, including journal articles, conference papers, and technical reports. We introduce 4 main categories of digital library projects: based on the architecture (distributed vs. centralized) and the contributor (traditional publisher vs. authoring individual/organization). Many digital library prototypes merely automate existing publishing practices or focus solely on the digitization of the publishing cycle output, not sampling and capturing elements of the input. Still others do not consider for distribution the large body of "gray literature." We address these deficiencies in the current model of STI exchange by suggesting methods for expanding the scope and target of digital libraries by focusing on a greater source of technical publications and using "buckets," an object-oriented construct for grouping logically related information objects, to include holdings other than technical publications.

An enhanced high-speed multi-digit BCD adder using quantum-dot cellular automata

NASA Astrophysics Data System (ADS)

Ajitha, D.; Ramanaiah, K. V.; Sumalatha, V.

2017-02-01

The advent of development of high-performance, low-power digital circuits is achieved by a suitable emerging nanodevice called quantum-dot cellular automata (QCA). Even though many efficient arithmetic circuits were designed using QCA, there is still a challenge to implement high-speed circuits in an optimized manner. Among these circuits, one of the essential structures is a parallel multi-digit decimal adder unit with significant speed which is very attractive for future environments. To achieve high speed, a new correction logic formulation method is proposed for single and multi-digit BCD adder. The proposed enhanced single-digit BCD adder (ESDBA) is 26% faster than the carry flow adder (CFA)-based BCD adder. The multi-digit operations are also performed using the proposed ESDBA, which is cascaded innovatively. The enhanced multi-digit BCD adder (EMDBA) performs two 4-digit and two 8-digit BCD addition 50% faster than the CFA-based BCD adder with the nominal overhead of the area. The EMDBA performs two 4-digit BCD addition 24% faster with 23% decrease in the area, similarly for 8-digit operation the EMDBA achieves 36% increase in speed with 21% less area compared to the existing carry look ahead (CLA)-based BCD adder design. The proposed multi-digit adder produces significantly less delay of (N –1) + 3.5 clock cycles compared to the N* One digit BCD adder delay required by the conventional BCD adder method. It is observed that as per our knowledge this is the first innovative proposal for multi-digit BCD addition using QCA.

Modified-Signed-Digit Optical Computing Using Fan-Out

NASA Technical Reports Server (NTRS)

Liu, Hua-Kuang; Zhou, Shaomin; Yeh, Pochi

1996-01-01

Experimental optical computing system containing optical fan-out elements implements modified signed-digit (MSD) arithmetic and logic. In comparison with previous optical implementations of MSD arithmetic, this one characterized by larger throughput, greater flexibility, and simpler optics.

Flight evaluation of modifications to a digital electronic engine control system in an F-15 airplane

NASA Technical Reports Server (NTRS)

Burcham, F. W., Jr.; Myers, L. P.; Zeller, J. R.

1983-01-01

The third phase of a flight evaluation of a digital electronic engine control system in an F-15 has recently been completed. It was found that digital electronic engine control software logic changes and augmentor hardware improvements resulted in significant improvements in engine operation. For intermediate to maximum power throttle transients, an increase in altitude capability of up to 8000 ft was found, and for idle to maximum transients, an increase of up to 4000 ft was found. A nozzle instability noted in earlier flight testing was investigated on a test engine at NASA Lewis Research Center, a digital electronic engine control software logic change was developed and evaluated, and no instability occurred in the Phase 3 flight evaluation. The backup control airstart modification was evaluated, and gave an improvement of airstart capability by reducing the minimum airspeed for successful airstarts by 50 to 75 knots.

Comparing Online to Face-To-Face Delivery of Undergraduate Digital Circuits Content

ERIC Educational Resources Information Center

LaMeres, Brock J.; Plumb, Carolyn

2014-01-01

This paper presents a comparison of online to traditional face-to-face delivery of undergraduate digital systems material. Two specific components of digital content were compared and evaluated: a sophomore logic circuits course with no laboratory, and a microprocessor laboratory component of a junior-level computer systems course. For each of…

Picoliter DNA Sequencing Chemistry on an Electrowetting-based Digital Microfluidic Platform

PubMed Central

Ferguson Welch, Erin R.; Lin, Yan-You; Madison, Andrew; Fair, R.B.

2011-01-01

The results of investigations into performing DNA sequencing chemistry on a picoliter-scale electrowetting digital microfluidic platform are reported. Pyrosequencing utilizes pyrophosphate produced during nucleotide base addition to initiate a process ending with detection through a chemiluminescence reaction using firefly luciferase. The intensity of light produced during the reaction can be quantified to determine the number of bases added to the DNA strand. The logic-based control and discrete fluid droplets of a digital microfluidic device lend themselves well to the pyrosequencing process. Bead-bound DNA is magnetically held in a single location, and wash or reagent droplets added or split from it to circumvent product dilution. Here we discuss the dispensing, control, and magnetic manipulation of the paramagnetic beads used to hold target DNA. We also demonstrate and characterize the picoliter-scale reaction of luciferase with adenosine triphosphate to represent the detection steps of pyrosequencing and all necessary alterations for working on this scale. PMID:21298802

Rapidly reconfigurable all-optical universal logic gate

DOEpatents

Goddard, Lynford L.; Bond, Tiziana C.; Kallman, Jeffrey S.

2010-09-07

A new reconfigurable cascadable all-optical on-chip device is presented. The gate operates by combining the Vernier effect with a novel effect, the gain-index lever, to help shift the dominant lasing mode from a mode where the laser light is output at one facet to a mode where it is output at the other facet. Since the laser remains above threshold, the speed of the gate for logic operations as well as for reprogramming the function of the gate is primarily limited to the small signal optical modulation speed of the laser, which can be on the order of up to about tens of GHz. The gate can be rapidly and repeatedly reprogrammed to perform any of the basic digital logic operations by using an appropriate analog optical or electrical signal at the gate selection port. Other all-optical functionality includes wavelength conversion, signal duplication, threshold switching, analog to digital conversion, digital to analog conversion, signal routing, and environment sensing. Since each gate can perform different operations, the functionality of such a cascaded circuit grows exponentially.

History Places: A Case Study for Relational Database and Information Retrieval System Design

ERIC Educational Resources Information Center

Hendry, David G.

2007-01-01

This article presents a project-based case study that was developed for students with diverse backgrounds and varied inclinations for engaging technical topics. The project, called History Places, requires that student teams develop a vision for a kind of digital library, propose a conceptual model, and use the model to derive a logical model and…

Amplifying genetic logic gates.

PubMed

Bonnet, Jerome; Yin, Peter; Ortiz, Monica E; Subsoontorn, Pakpoom; Endy, Drew

2013-05-03

Organisms must process information encoded via developmental and environmental signals to survive and reproduce. Researchers have also engineered synthetic genetic logic to realize simpler, independent control of biological processes. We developed a three-terminal device architecture, termed the transcriptor, that uses bacteriophage serine integrases to control the flow of RNA polymerase along DNA. Integrase-mediated inversion or deletion of DNA encoding transcription terminators or a promoter modulates transcription rates. We realized permanent amplifying AND, NAND, OR, XOR, NOR, and XNOR gates actuated across common control signal ranges and sequential logic supporting autonomous cell-cell communication of DNA encoding distinct logic-gate states. The single-layer digital logic architecture developed here enables engineering of amplifying logic gates to control transcription rates within and across diverse organisms.

Programmable Logic Application Notes

NASA Technical Reports Server (NTRS)

Katz, Richard; Day, John H. (Technical Monitor)

2001-01-01

This report will be provided each quarter as a source for reliability, radiation results, NASA capabilities, and other information on programmable logic devices and related applications. This quarter will continue a series of notes concentrating on analysis techniques with this issue's section discussing the use of Root-Sum-Square calculations for digital delays.

Introducing Programmable Logic to Undergraduate Engineering Students in a Digital Electronics Course

ERIC Educational Resources Information Center

Todorovich, E.; Marone, J. A.; Vazquez, M.

2012-01-01

Due to significant technological advances and industry requirements, many universities have introduced programmable logic and hardware description languages into undergraduate engineering curricula. This has led to a number of logistical and didactical challenges, in particular for computer science students. In this paper, the integration of some…

Motivation for DOC III: 64-bit digital optical computer

NASA Astrophysics Data System (ADS)

Guilfoyle, Peter S.

1991-09-01

OptiComp has focused on a digital optical logic family in order to capitalize on the inherent benefits of optical computing, which include (1) high FAN-IN and FAN-OUT, (2) low power consumption, (3) high noise margin, (4) high algorithmic efficiency using 'smart' interconnects, and (5) free-space leverage of gate interconnect bandwidth product. Other well-known secondary advantages of optical logic include zero capacitive loading of signals at a detector, zero cross-talk between signals, zero signal dispersion, and minimal clock skew (a few picoseconds or less in an imaging system). The primary focus of this paper is to demonstrate how each of the five advantages can be used to leverage other logic family performance such as GaAs; the secondary attributes are discussed only in the context of introducing the DOC III architecture.

Benchmarks of a III-V TFET technology platform against the 10-nm CMOS FinFET technology node considering basic arithmetic circuits

NASA Astrophysics Data System (ADS)

Strangio, S.; Palestri, P.; Lanuzza, M.; Esseni, D.; Crupi, F.; Selmi, L.

2017-02-01

In this work, a benchmark for low-power digital applications of a III-V TFET technology platform against a conventional CMOS FinFET technology node is proposed. The analysis focuses on full-adder circuits, which are commonly identified as representative of the digital logic environment. 28T and 24T topologies, implemented in complementary-logic and transmission-gate logic, respectively, are investigated. Transient simulations are performed with a purpose-built test-bench on each single-bit full adder solution. The extracted delays and energy characteristics are post-processed and translated into figures-of-merit for multi-bit ripple-carry-adders. Trends related to the different full-adder implementations (for the same device technology platform) and to the different technology platforms (for the same full-adder topology) are presented and discussed.

Digital Inverter Amine Sensing via Synergistic Responses by n and p Organic Semiconductors.

PubMed

Tremblay, Noah J; Jung, Byung Jun; Breysse, Patrick; Katz, Howard E

2011-11-22

Chemiresistors and sensitive OFETs have been substantially developed as cheap, scalable, and versatile sensing platforms. While new materials are expanding OFET sensing capabilities, the device architectures have changed little. Here we report higher order logic circuits utilizing OFETs sensitive to amine vapors. The circuits depend on the synergistic responses of paired p- and n-channel organic semiconductors, including an unprecedented analyte-induced current increase by the n-channel semiconductor. This represents the first step towards 'intelligent sensors' that utilize analog signal changes in sensitive OFETs to produce direct digital readouts suitable for further logic operations.

Digital Inverter Amine Sensing via Synergistic Responses by n and p Organic Semiconductors

PubMed Central

Tremblay, Noah J.; Jung, Byung Jun; Breysse, Patrick; Katz, Howard E.

2013-01-01

Chemiresistors and sensitive OFETs have been substantially developed as cheap, scalable, and versatile sensing platforms. While new materials are expanding OFET sensing capabilities, the device architectures have changed little. Here we report higher order logic circuits utilizing OFETs sensitive to amine vapors. The circuits depend on the synergistic responses of paired p- and n-channel organic semiconductors, including an unprecedented analyte-induced current increase by the n-channel semiconductor. This represents the first step towards ‘intelligent sensors’ that utilize analog signal changes in sensitive OFETs to produce direct digital readouts suitable for further logic operations. PMID:23754969

Digital Troposcatter Performance Model

DTIC Science & Technology

1983-12-01

Dist Speia DIIBUTON STATEMR AO Approved tot public relemg ** - DistributionUnlimited __________ Communications. Control and Information Systems ...for digital troposcatter communication system design is described. Propagation and modem performance *are modeled. These include Path Loss and RSL...designing digital troposcatter systems . A User’s Manual Report discusses the use of the computer program TROPO. The description of the structure and logical

Pneumatic oscillator circuits for timing and control of integrated microfluidics.

PubMed

Duncan, Philip N; Nguyen, Transon V; Hui, Elliot E

2013-11-05

Frequency references are fundamental to most digital systems, providing the basis for process synchronization, timing of outputs, and waveform synthesis. Recently, there has been growing interest in digital logic systems that are constructed out of microfluidics rather than electronics, as a possible means toward fully integrated laboratory-on-a-chip systems that do not require any external control apparatus. However, the full realization of this goal has not been possible due to the lack of on-chip frequency references, thus requiring timing signals to be provided from off-chip. Although microfluidic oscillators have been demonstrated, there have been no reported efforts to characterize, model, or optimize timing accuracy, which is the fundamental metric of a clock. Here, we report pneumatic ring oscillator circuits built from microfluidic valves and channels. Further, we present a compressible-flow analysis that differs fundamentally from conventional circuit theory, and we show the utility of this physically based model for the optimization of oscillator stability. Finally, we leverage microfluidic clocks to demonstrate circuits for the generation of phase-shifted waveforms, self-driving peristaltic pumps, and frequency division. Thus, pneumatic oscillators can serve as on-chip frequency references for microfluidic digital logic circuits. On-chip clocks and pumps both constitute critical building blocks on the path toward achieving autonomous laboratory-on-a-chip devices.

Binary centrifugal microfluidics enabling novel, digital addressable functions for valving and routing.

PubMed

Wang, Guanghui; Tan, Jie; Tang, Minghui; Zhang, Changbin; Zhang, Dongying; Ji, Wenbin; Chen, Junhao; Ho, Ho-Pui; Zhang, Xuping

2018-03-16

Centrifugal microfluidics or lab-on-a-disc (LOAD) is a promising branch of lab-on-a-chip or microfluidics. Besides effective fluid transportation and inherently available density-based sample separation in centrifugal microfluidics, uniform actuation of flow on the disc makes the platform compact and scalable. However, the natural radially outward centrifugal force in a LOAD system limits its capacity to perform complex fluid manipulation steps. In order to increase the fluid manipulation freedom and integration capacity of the LOAD system, we propose a binary centrifugal microfluidics platform. With the help of Euler force, our platform allows free switching of both left and right states based on a rather simple mechanical structure. The periodical switching of state would provide a "clock" signal for a sequence of droplet binary logic operations. With the binary state platform and the "clock" signal, we can accurately handle the droplet separately in each time step with a maximum main frequency of about 10 S s-1 (switching per second). Apart from droplet manipulations such as droplet generation and metering, we also demonstrate a series of droplet logic operations, such as binary valving, droplet routing and digital addressable droplet storage. Furthermore, complex bioassays such as the Bradford assay and DNA purification assay are demonstrated on a binary platform, which is totally impossible for a traditional LOAD system. Our binary platform largely improves the capability for logic operation on the LOAD platform, and it is a simple and promising approach for microfluidic lab-on-a-disc large-scale integration.

Ultralow-Power Digital Correlator for Microwave Polarimetry

NASA Technical Reports Server (NTRS)

Piepmeier, Jeffrey R.; Hass, K. Joseph

2004-01-01

A recently developed high-speed digital correlator is especially well suited for processing readings of a passive microwave polarimeter. This circuit computes the autocorrelations of, and the cross-correlations among, data in four digital input streams representing samples of in-phase (I) and quadrature (Q) components of two intermediate-frequency (IF) signals, denoted A and B, that are generated in heterodyne reception of two microwave signals. The IF signals arriving at the correlator input terminals have been digitized to three levels (-1,0,1) at a sampling rate up to 500 MHz. Two bits (representing sign and magnitude) are needed to represent the instantaneous datum in each input channel; hence, eight bits are needed to represent the four input signals during any given cycle of the sampling clock. The accumulation (integration) time for the correlation is programmable in increments of 2(exp 8) cycles of the sampling clock, up to a maximum of 2(exp 24) cycles. The basic functionality of the correlator is embodied in 16 correlation slices, each of which contains identical logic circuits and counters (see figure). The first stage of each correlation slice is a logic gate that computes one of the desired correlations (for example, the autocorrelation of the I component of A or the negative of the cross-correlation of the I component of A and the Q component of B). The sampling of the output of the logic gate output is controlled by the sampling-clock signal, and an 8-bit counter increments in every clock cycle when the logic gate generates output. The most significant bit of the 8-bit counter is sampled by a 16-bit counter with a clock signal at 2(exp 8) the frequency of the sampling clock. The 16-bit counter is incremented every time the 8-bit counter rolls over.

Implementation of digital equality comparator circuit on memristive memory crossbar array using material implication logic

NASA Astrophysics Data System (ADS)

Haron, Adib; Mahdzair, Fazren; Luqman, Anas; Osman, Nazmie; Junid, Syed Abdul Mutalib Al

2018-03-01

One of the most significant constraints of Von Neumann architecture is the limited bandwidth between memory and processor. The cost to move data back and forth between memory and processor is considerably higher than the computation in the processor itself. This architecture significantly impacts the Big Data and data-intensive application such as DNA analysis comparison which spend most of the processing time to move data. Recently, the in-memory processing concept was proposed, which is based on the capability to perform the logic operation on the physical memory structure using a crossbar topology and non-volatile resistive-switching memristor technology. This paper proposes a scheme to map digital equality comparator circuit on memristive memory crossbar array. The 2-bit, 4-bit, 8-bit, 16-bit, 32-bit, and 64-bit of equality comparator circuit are mapped on memristive memory crossbar array by using material implication logic in a sequential and parallel method. The simulation results show that, for the 64-bit word size, the parallel mapping exhibits 2.8× better performance in total execution time than sequential mapping but has a trade-off in terms of energy consumption and area utilization. Meanwhile, the total crossbar area can be reduced by 1.2× for sequential mapping and 1.5× for parallel mapping both by using the overlapping technique.

Digital signal conditioning for flight test instrumentation

NASA Technical Reports Server (NTRS)

Bever, Glenn A.

1991-01-01

An introduction to digital measurement processes on aircraft is provided. Flight test instrumentation systems are rapidly evolving from analog-intensive to digital intensive systems, including the use of onboard digital computers. The topics include measurements that are digital in origin, as well as sampling, encoding, transmitting, and storing data. Particular emphasis is placed on modern avionic data bus architectures and what to be aware of when extracting data from them. Examples of data extraction techniques are given. Tradeoffs between digital logic families, trends in digital development, and design testing techniques are discussed. An introduction to digital filtering is also covered.

Room temperature operation of electro-optical bistability in the edge-emitting tunneling-collector transistor laser

NASA Astrophysics Data System (ADS)

Feng, M.; Holonyak, N.; Wang, C. Y.

2017-09-01

Optical bistable devices are fundamental to digital photonics as building blocks of switches, logic gates, and memories in future computer systems. Here, we demonstrate both optical and electrical bistability and capability for switching in a single transistor operated at room temperature. The electro-optical hysteresis is explained by the interaction of electron-hole (e-h) generation and recombination dynamics with the cavity photon modulation in different switching paths. The switch-UP and switch-DOWN threshold voltages are determined by the rate difference of photon generation at the base quantum-well and the photon absorption via intra-cavity photon-assisted tunneling controlled by the collector voltage. Thus, the transistor laser electro-optical bistable switching is programmable with base current and collector voltage, and the basis for high speed optical logic processors.

Biological Signal Processing with a Genetic Toggle Switch

PubMed Central

Hillenbrand, Patrick; Fritz, Georg; Gerland, Ulrich

2013-01-01

Complex gene regulation requires responses that depend not only on the current levels of input signals but also on signals received in the past. In digital electronics, logic circuits with this property are referred to as sequential logic, in contrast to the simpler combinatorial logic without such internal memory. In molecular biology, memory is implemented in various forms such as biochemical modification of proteins or multistable gene circuits, but the design of the regulatory interface, which processes the input signals and the memory content, is often not well understood. Here, we explore design constraints for such regulatory interfaces using coarse-grained nonlinear models and stochastic simulations of detailed biochemical reaction networks. We test different designs for biological analogs of the most versatile memory element in digital electronics, the JK-latch. Our analysis shows that simple protein-protein interactions and protein-DNA binding are sufficient, in principle, to implement genetic circuits with the capabilities of a JK-latch. However, it also exposes fundamental limitations to its reliability, due to the fact that biological signal processing is asynchronous, in contrast to most digital electronics systems that feature a central clock to orchestrate the timing of all operations. We describe a seemingly natural way to improve the reliability by invoking the master-slave concept from digital electronics design. This concept could be useful to interpret the design of natural regulatory circuits, and for the design of synthetic biological systems. PMID:23874595

Simulation of continuously logical base cells (CL BC) with advanced functions for analog-to-digital converters and image processors

NASA Astrophysics Data System (ADS)

Krasilenko, Vladimir G.; Lazarev, Alexander A.; Nikitovich, Diana V.

2017-10-01

The paper considers results of design and modeling of continuously logical base cells (CL BC) based on current mirrors (CM) with functions of preliminary analogue and subsequent analogue-digital processing for creating sensor multichannel analog-to-digital converters (SMC ADCs) and image processors (IP). For such with vector or matrix parallel inputs-outputs IP and SMC ADCs it is needed active basic photosensitive cells with an extended electronic circuit, which are considered in paper. Such basic cells and ADCs based on them have a number of advantages: high speed and reliability, simplicity, small power consumption, high integration level for linear and matrix structures. We show design of the CL BC and ADC of photocurrents and their various possible implementations and its simulations. We consider CL BC for methods of selection and rank preprocessing and linear array of ADCs with conversion to binary codes and Gray codes. In contrast to our previous works here we will dwell more on analogue preprocessing schemes for signals of neighboring cells. Let us show how the introduction of simple nodes based on current mirrors extends the range of functions performed by the image processor. Each channel of the structure consists of several digital-analog cells (DC) on 15-35 CMOS. The amount of DC does not exceed the number of digits of the formed code, and for an iteration type, only one cell of DC, complemented by the device of selection and holding (SHD), is required. One channel of ADC with iteration is based on one DC-(G) and SHD, and it has only 35 CMOS transistors. In such ADCs easily parallel code can be realized and also serial-parallel output code. The circuits and simulation results of their design with OrCAD are shown. The supply voltage of the DC is 1.8÷3.3V, the range of an input photocurrent is 0.1÷24μA, the transformation time is 20÷30nS at 6-8 bit binary or Gray codes. The general power consumption of the ADC with iteration is only 50÷100μW, if the maximum input current is 4μA. Such simple structure of linear array of ADCs with low power consumption and supply voltage 3.3V, and at the same time with good dynamic characteristics (frequency of digitization even for 1.5μm CMOS-technologies is 40÷50 MHz, and can be increased up to 10 times) and accuracy characteristics are show. The SMC ADCs based on CL BC and CM opens new prospects for realization of linear and matrix IP and photo-electronic structures with matrix operands, which are necessary for neural networks, digital optoelectronic processors, neural-fuzzy controllers.

Development of Boolean calculus and its applications. [digital systems design

NASA Technical Reports Server (NTRS)

Tapia, M. A.

1980-01-01

The development of Boolean calculus for its application to developing digital system design methodologies that would reduce system complexity, size, cost, speed, power requirements, etc., is discussed. Synthesis procedures for logic circuits are examined particularly asynchronous circuits using clock triggered flip flops.

DDL:Digital systems design language

NASA Technical Reports Server (NTRS)

Shival, S. G.

1980-01-01

Hardware description languages are valuable tools in such applications as hardware design, system documentation, and logic design training. DDL is convenient medium for inputting design details into hardware-design automation system. It is suitable for describing digital systems at gate, register transfer, and major combinational block level.

Microscale Digital Vacuum Electronic Gates

NASA Technical Reports Server (NTRS)

Manohara, Harish (Inventor); Mojarradi, Mohammed M. (Inventor)

2014-01-01

Systems and methods in accordance with embodiments of the invention implement microscale digital vacuum electronic gates. In one embodiment, a microscale digital vacuum electronic gate includes: a microscale field emitter that can emit electrons and that is a microscale cathode; and a microscale anode; where the microscale field emitter and the microscale anode are disposed within at least a partial vacuum; where the microscale field emitter and the microscale anode are separated by a gap; and where the potential difference between the microscale field emitter and the microscale anode is controllable such that the flow of electrons between the microscale field emitter and the microscale anode is thereby controllable; where when the microscale anode receives a flow of electrons, a first logic state is defined; and where when the microscale anode does not receive a flow of electrons, a second logic state is defined.

The development of a digital logic concept inventory

NASA Astrophysics Data System (ADS)

Herman, Geoffrey Lindsay

Instructors in electrical and computer engineering and in computer science have developed innovative methods to teach digital logic circuits. These methods attempt to increase student learning, satisfaction, and retention. Although there are readily accessible and accepted means for measuring satisfaction and retention, there are no widely accepted means for assessing student learning. Rigorous assessment of learning is elusive because differences in topic coverage, curriculum and course goals, and exam content prevent direct comparison of two teaching methods when using tools such as final exam scores or course grades. Because of these difficulties, computing educators have issued a general call for the adoption of assessment tools to critically evaluate and compare the various teaching methods. Science, Technology, Engineering, and Mathematics (STEM) education researchers commonly measure students' conceptual learning to compare how much different pedagogies improve learning. Conceptual knowledge is often preferred because all engineering courses should teach a fundamental set of concepts even if they emphasize design or analysis to different degrees. Increasing conceptual learning is also important, because students who can organize facts and ideas within a consistent conceptual framework are able to learn new information quickly and can apply what they know in new situations. If instructors can accurately assess their students' conceptual knowledge, they can target instructional interventions to remedy common problems. To properly assess conceptual learning, several researchers have developed concept inventories (CIs) for core subjects in engineering sciences. CIs are multiple-choice assessment tools that evaluate how well a student's conceptual framework matches the accepted conceptual framework of a discipline or common faulty conceptual frameworks. We present how we created and evaluated the digital logic concept inventory (DLCI).We used a Delphi process to identify the important and difficult concepts to include on the DLCI. To discover and describe common student misconceptions, we interviewed students who had completed a digital logic course. Students vocalized their thoughts as they solved digital logic problems. We analyzed the interview data using a qualitative grounded theory approach. We have administered the DLCI at several institutions and have checked the validity, reliability, and bias of the DLCI with classical testing theory procedures. These procedures consisted of follow-up interviews with students, analysis of administration results with statistical procedures, and expert feedback. We discuss these results and present the DLCI's potential for providing a meaningful tool for comparing student learning at different institutions.

Digital circuits for computer applications: A compilation

NASA Technical Reports Server (NTRS)

1972-01-01

The innovations in this updated series of compilations dealing with electronic technology represent a carefully selected collection of digital circuits which have direct application in computer oriented systems. In general, the circuits have been selected as representative items of each section and have been included on their merits of having universal applications in digital computers and digital data processing systems. As such, they should have wide appeal to the professional engineer and scientist who encounter the fundamentals of digital techniques in their daily activities. The circuits are grouped as digital logic circuits, analog to digital converters, and counters and shift registers.

An Introduction to Logic Control Systems for the Behavioral Scientist, Part I, Text.

ERIC Educational Resources Information Center

Larsen, Lawrence A.

This programed instruction course gives a basic introduction to solid state programing equipment. Course objectives include giving the student (1) a working knowledge of the various types of units used in building digital logic control systems and (2) an idea of how they interconnect to perform different functions. The course has no prerequisites…

A m-ary linear feedback shift register with binary logic

NASA Technical Reports Server (NTRS)

Perlman, M. (Inventor)

1973-01-01

A family of m-ary linear feedback shift registers with binary logic is disclosed. Each m-ary linear feedback shift register with binary logic generates a binary representation of a nonbinary recurring sequence, producible with a m-ary linear feedback shift register without binary logic in which m is greater than 2. The state table of a m-ary linear feedback shift register without binary logic, utilizing sum modulo m feedback, is first tubulated for a given initial state. The entries in the state table are coded in binary and the binary entries are used to set the initial states of the stages of a plurality of binary shift registers. A single feedback logic unit is employed which provides a separate feedback binary digit to each binary register as a function of the states of corresponding stages of the binary registers.

Electron lithography STAR design guidelines. Part 2: The design of a STAR for space applications

NASA Technical Reports Server (NTRS)

Trotter, J. D.; Newman, W.

1982-01-01

The STAR design system developed by NASA enables any user with a logic diagram to design a semicustom digital MOS integrated circuit. The system is comprised of a library of standard logic cells and computr programs to place, route, and display designs implemented with cells from the library. Also described is the development of a radiation-hard array designed for the STAR system. The design is based on the CMOS silicon gate technology developed by SANDIA National Laboratories. The design rules used are given as well as the model parameters developed for the basic array element. Library cells of the CMOS metal gate and CMOS silicon gate technologies were simulated using SPICE, and the results are shown and compared.

Evolutions in food marketing, quantifying the impact, and policy implications.

PubMed

Cairns, Georgina

2013-03-01

A case study on interactive digital marketing examined the adequacy of extant policy controls and their underpinning paradigms to constrain the effects of this rapidly emerging practice. Findings were interactive digital marketing is expanding the strategies available to promote products, brands and consumer behaviours. It facilitates relational marketing; the collection of personal data for marketing; integration of the marketing mix, and provides a platform for consumers to engage in the co-creation of marketing communications. The paradigmatic logic of current policies to constrain youth-oriented food marketing does not address the interactive nature of digital marketing. The evidence base on the effects of HFSS marketing and policy interventions is based on conceptualizations of marketing as a force promoting transactions rather than interactions. Digital technologies are generating rich consumer data. Interactive digital technologies increase the complexity of the task of quantifying the impact of marketing. The rapidity of its uptake also increases urgency of need to identify appropriate effects measures. Independent analysis of commercial consumer data (appropriately transformed to protect commercial confidentiality and personal privacy) would provide evidence sources for policy on the impacts of commercial food and beverage marketing and policy controls. Copyright © 2012 Elsevier Ltd. All rights reserved.

A low complexity, low spur digital IF conversion circuit for high-fidelity GNSS signal playback

NASA Astrophysics Data System (ADS)

Su, Fei; Ying, Rendong

2016-01-01

A low complexity high efficiency and low spur digital intermediate frequency (IF) conversion circuit is discussed in the paper. This circuit is key element in high-fidelity GNSS signal playback instrument. We analyze the spur performance of a finite state machine (FSM) based numerically controlled oscillators (NCO), by optimization of the control algorithm, a FSM based NCO with 3 quantization stage can achieves 65dB SFDR in the range of the seventh harmonic. Compare with traditional lookup table based NCO design with the same Spurious Free Dynamic Range (SFDR) performance, the logic resource require to implemented the NCO is reduced to 1/3. The proposed design method can be extended to the IF conversion system with good SFDR in the range of higher harmonic components by increasing the quantization stage.

G4-FETs as Universal and Programmable Logic Gates

NASA Technical Reports Server (NTRS)

Johnson, Travis; Fijany, Amir; Mojarradi, Mohammad; Vatan, Farrokh; Toomarian, Nikzad; Kolawa, Elizabeth; Cristoloveanu, Sorin; Blalock, Benjamin

2007-01-01

An analysis of a patented generic silicon- on-insulator (SOI) electronic device called a G4-FET has revealed that the device could be designed to function as a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer discrete components than are required for conventional transistor-based circuits performing the same logic functions. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G4-FET can also be regarded as a single transistor having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of the SOI substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. With proper choice of the specific dimensions for the gates, channels, and ancillary features of the generic G4-FET, the device could be made to function as a three-input, one-output logic gate. As illustrated by the truth table in the top part of the figure, the behavior of this logic gate would be the inverse (the NOT) of that of a majority gate. In other words, the device would function as a NOT-majority gate. By simply adding an inverter, one could obtain a majority gate. In contrast, to construct a majority gate in conventional complementary metal oxide/semiconductor (CMOS) circuitry, one would need four three-input AND gates and a four-input OR gate, altogether containing 32 transistors.

The Semiautomated Test System: A Tool for Standardized Performance Testing.

ERIC Educational Resources Information Center

Ramsey, H. Rudy

For performance tests to be truly standardized, they must be administered in a way that will minimize variation due to operator intervention and errors. Through such technological developments as low-cost digital computers and digital logic modules, automatic test administration without restriction of test content has become possible. A…

An Undergraduate Experiment in Alarm System Design.

ERIC Educational Resources Information Center

Martini, R. A.; And Others

1988-01-01

Describes an experiment involving data acquisition by a computer, digital signal transmission from the computer to a digital logic circuit and signal interpretation by this circuit. The system is being used at the Illinois Institute of Technology. Discusses the fundamental concepts involved. Demonstrates the alarm experiment as it is used in…

[The improved design of table operating box of digital subtraction angiography device].

PubMed

Qi, Xianying; Zhang, Minghai; Han, Fengtan; Tang, Feng; He, Lemin

2009-12-01

In this paper are analyzed the disadvantages of CGO-3000 digital subtraction angiography table Operating Box. The authors put forward a communication control scheme between single-chip microcomputer(SCM) and programmable logic controller(PLC). The details of hardware and software of communication are given.

Coding Skills as a Success Factor for a Society

ERIC Educational Resources Information Center

Tuomi, Pauliina; Multisilta, Jari Antero; Saarikoski, Petri; Suominen, Jaakko

2018-01-01

Digitalization is one of the most promising ways to increase productivity in the public sector and is needed to reform the economy by creating new innovation related jobs. The implementation of digital services requires problem solving, design skills, logical thinking, an understanding of how computers and networks operate, and programming…

Music, Technology, and an Evolving Curriculum.

ERIC Educational Resources Information Center

Moore, Brian

1992-01-01

Mechanical examples of musical technology, like the Steinway piano, are well known and accepted. Use of computers and electronic technology is the next logical step in developing art of music. MIDI (Musical Instrument Digital Interface) is explained, along with digital devices (such as synthesizers, sequencers, music notation software, multimedia,…

Digital transmitter for data bus communications system

NASA Technical Reports Server (NTRS)

Proch, G. E.

1974-01-01

Digital transmitter designed for Manchester coded signals (and all signals with ac waveforms) generated at a rate of one megabit per second includes efficient output isolation circuit. Transmitter consists of logic control section, amplifier, and output isolation section. Output isolation circuit provides dynamic impedance at terminals as function of amplifier output level.

Optical computing and neural networks; Proceedings of the Meeting, National Chiao Tung Univ., Hsinchu, Taiwan, Dec. 16, 17, 1992

NASA Technical Reports Server (NTRS)

Hsu, Ken-Yuh (Editor); Liu, Hua-Kuang (Editor)

1992-01-01

The present conference discusses optical neural networks, photorefractive nonlinear optics, optical pattern recognition, digital and analog processors, and holography and its applications. Attention is given to bifurcating optical information processing, neural structures in digital halftoning, an exemplar-based optical neural net classifier for color pattern recognition, volume storage in photorefractive disks, and microlaser-based compact optical neuroprocessors. Also treated are the optical implementation of a feature-enhanced optical interpattern-associative neural network model and its optical implementation, an optical pattern binary dual-rail logic gate module, a theoretical analysis for holographic associative memories, joint transform correlators, image addition and subtraction via the Talbot effect, and optical wavelet-matched filters. (No individual items are abstracted in this volume)

Optical computing and neural networks; Proceedings of the Meeting, National Chiao Tung Univ., Hsinchu, Taiwan, Dec. 16, 17, 1992

NASA Astrophysics Data System (ADS)

Hsu, Ken-Yuh; Liu, Hua-Kuang

The present conference discusses optical neural networks, photorefractive nonlinear optics, optical pattern recognition, digital and analog processors, and holography and its applications. Attention is given to bifurcating optical information processing, neural structures in digital halftoning, an exemplar-based optical neural net classifier for color pattern recognition, volume storage in photorefractive disks, and microlaser-based compact optical neuroprocessors. Also treated are the optical implementation of a feature-enhanced optical interpattern-associative neural network model and its optical implementation, an optical pattern binary dual-rail logic gate module, a theoretical analysis for holographic associative memories, joint transform correlators, image addition and subtraction via the Talbot effect, and optical wavelet-matched filters. (No individual items are abstracted in this volume)

The past, present and future of cyber-physical systems: a focus on models.

PubMed

Lee, Edward A

2015-02-26

This paper is about better engineering of cyber-physical systems (CPSs) through better models. Deterministic models have historically proven extremely useful and arguably form the kingpin of the industrial revolution and the digital and information technology revolutions. Key deterministic models that have proven successful include differential equations, synchronous digital logic and single-threaded imperative programs. Cyber-physical systems, however, combine these models in such a way that determinism is not preserved. Two projects show that deterministic CPS models with faithful physical realizations are possible and practical. The first project is PRET, which shows that the timing precision of synchronous digital logic can be practically made available at the software level of abstraction. The second project is Ptides (programming temporally-integrated distributed embedded systems), which shows that deterministic models for distributed cyber-physical systems have practical faithful realizations. These projects are existence proofs that deterministic CPS models are possible and practical.

The Past, Present and Future of Cyber-Physical Systems: A Focus on Models

PubMed Central

Lee, Edward A.

2015-01-01

This paper is about better engineering of cyber-physical systems (CPSs) through better models. Deterministic models have historically proven extremely useful and arguably form the kingpin of the industrial revolution and the digital and information technology revolutions. Key deterministic models that have proven successful include differential equations, synchronous digital logic and single-threaded imperative programs. Cyber-physical systems, however, combine these models in such a way that determinism is not preserved. Two projects show that deterministic CPS models with faithful physical realizations are possible and practical. The first project is PRET, which shows that the timing precision of synchronous digital logic can be practically made available at the software level of abstraction. The second project is Ptides (programming temporally-integrated distributed embedded systems), which shows that deterministic models for distributed cyber-physical systems have practical faithful realizations. These projects are existence proofs that deterministic CPS models are possible and practical. PMID:25730486

Effect of control logic modifications on airstart performance of F100 engine model derivative engines in an F-15 airplane

NASA Technical Reports Server (NTRS)

Crawford, D. B.; Burcham, F. W., Jr.

1984-01-01

A series of airstarts were conducted in an F-15 airplane with two prototype Pratt and Whitney F100 Engine Model Derivative engines equipped with Digital Electronic Engine Control (DEEC) systems. The airstart envelope and the time required for airstarts were defined. Comparisons were made between the original airstart logic, and modified logic which was designed to improve the airstart capability. Spooldown airstarts with the modified logic were more successful at lower altitudes than were those with the original logic. Spooldown airstart times ranged from 33 seconds at 250 knots to 83 seconds at 175 knots. The modified logic improved the airstart time from 31% to 53%, with the most improved times at slower airspeeds. Jet fuel starter (JFS)-assisted airstarts were conducted at 7000 m and airstart times were significantly faster than unassisted airstarts. The effect of altitude on airstart times was small.

Enhanced TCAS 2/CDTI traffic Sensor digital simulation model and program description

NASA Technical Reports Server (NTRS)

Goka, T.

1984-01-01

Digital simulation models of enhanced TCAS 2/CDTI traffic sensors are developed, based on actual or projected operational and performance characteristics. Two enhanced Traffic (or Threat) Alert and Collision Avoidance Systems are considered. A digital simulation program is developed in FORTRAN. The program contains an executive with a semireal time batch processing capability. The simulation program can be interfaced with other modules with a minimum requirement. Both the traffic sensor and CAS logic modules are validated by means of extensive simulation runs. Selected validation cases are discussed in detail, and capabilities and limitations of the actual and simulated systems are noted. The TCAS systems are not specifically intended for Cockpit Display of Traffic Information (CDTI) applications. These systems are sufficiently general to allow implementation of CDTI functions within the real systems' constraints.

Unpredictability and the transmission of numbers

NASA Astrophysics Data System (ADS)

Myers, John M.; Madjid, F. Hadi

2016-03-01

Curiously overlooked in physics is its dependence on the transmission of numbers. For example, the transmission of numerical clock readings is implicit in the concept of a coordinate system. The transmission of numbers and other logical distinctions is often achieved over a computer-mediated communications network in the face of an unpredictable environment. By unpredictable we mean something stronger than the spread of probabilities over given possible outcomes, namely an opening to unforeseeable possibilities. Unpredictability, until now overlooked in theoretical physics, makes the transmission of numbers interesting. Based on recent proofs within quantum theory that provide a theoretical foundation to unpredictability, here we show how regularities in physics rest on a background of channels over which numbers are transmitted. As is known to engineers of digital communications, numerical transmissions depend on coordination reminiscent of the cycle of throwing and catching by players tossing a ball back and forth. In digital communications, the players are computers, and the required coordination involves unpredictably adjusting "live clocks" that step these computers through phases of a cycle. We show how this phasing, which we call logical synchronization, constrains number-carrying networks, and, if a spacetime manifold in invoked, put "stripes" on spacetime. Via its logically synchronized channels, a network of live clocks serves as a reference against which to locate events. Such a network in any case underpins a coordinate frame, and in some cases the direct use of a network can be tailored to investigate an unpredictable environment. Examples include explorations of gravitational variations near Earth.

Programmable single-cell mammalian biocomputers.

PubMed

Ausländer, Simon; Ausländer, David; Müller, Marius; Wieland, Markus; Fussenegger, Martin

2012-07-05

Synthetic biology has advanced the design of standardized control devices that program cellular functions and metabolic activities in living organisms. Rational interconnection of these synthetic switches resulted in increasingly complex designer networks that execute input-triggered genetic instructions with precision, robustness and computational logic reminiscent of electronic circuits. Using trigger-controlled transcription factors, which independently control gene expression, and RNA-binding proteins that inhibit the translation of transcripts harbouring specific RNA target motifs, we have designed a set of synthetic transcription–translation control devices that could be rewired in a plug-and-play manner. Here we show that these combinatorial circuits integrated a two-molecule input and performed digital computations with NOT, AND, NAND and N-IMPLY expression logic in single mammalian cells. Functional interconnection of two N-IMPLY variants resulted in bitwise intracellular XOR operations, and a combinatorial arrangement of three logic gates enabled independent cells to perform programmable half-subtractor and half-adder calculations. Individual mammalian cells capable of executing basic molecular arithmetic functions isolated or coordinated to metabolic activities in a predictable, precise and robust manner may provide new treatment strategies and bio-electronic interfaces in future gene-based and cell-based therapies.

Digital controllers for VTOL aircraft

NASA Technical Reports Server (NTRS)

Stengel, R. F.; Broussard, J. R.; Berry, P. W.

1976-01-01

Using linear-optimal estimation and control techniques, digital-adaptive control laws have been designed for a tandem-rotor helicopter which is equipped for fully automatic flight in terminal area operations. Two distinct discrete-time control laws are designed to interface with velocity-command and attitude-command guidance logic, and each incorporates proportional-integral compensation for non-zero-set-point regulation, as well as reduced-order Kalman filters for sensor blending and noise rejection. Adaptation to flight condition is achieved with a novel gain-scheduling method based on correlation and regression analysis. The linear-optimal design approach is found to be a valuable tool in the development of practical multivariable control laws for vehicles which evidence significant coupling and insufficient natural stability.

The trend of digital control system design for nuclear power plants in Korea

DOE Office of Scientific and Technical Information (OSTI.GOV)

Park, S. H.; Jung, H. Y.; Yang, C. Y.

2006-07-01

Currently there are 20 nuclear power plants (NPPs) in operation, and 6 more units are under construction in Korea. The control systems of those NPPs have also been developed together with the technology advancement. Control systems started with On-Off control using the relay logic, had been evolved into Solid-State logic using TTL ICs, and applied with the micro-processors since the Yonggwang NPP Units 3 and 4 which started its construction in 1989. Multiplexers are also installed at the local plant areas to collect field input and to send output signals while communicating with the controllers located in the system cabinetsmore » near the main control room in order to reduce the field wiring cables. The design of the digital control system technology for the NPPs in Korea has been optimized to maximize the operability as well as the safety through the design, construction, start-up and operation experiences. Both Shin-Kori Units 1 and 2 and Shin-Wolsong Units 1 and 2 NPP projects under construction are being progressed at the same time. Digital Plant Control Systems of these projects have adopted multi-loop controllers, redundant loop configuration, and soft control system for the radwaste system. Programmable Logic Controller (PLC) and Distributed Control System (DCS) are applied with soft control system in Shin-Kori Units 3 and 4. This paper describes the evolvement of control system at the NPPs in Korea and the experience and design improvement through the observation of the latest failure of the digital control system. In addition, design concept and its trend of the digital control system being applied to the NPP in Korea are introduced. (authors)« less

Evolutionary Data Mining Approach to Creating Digital Logic

DTIC Science & Technology

2010-01-01

To deal with this problem a genetic program (GP) based data mining ( DM ) procedure has been invented (Smith 2005). A genetic program is an algorithm...that can operate on the variables. When a GP was used as a DM function in the past to automatically create fuzzy decision trees, the Report...rules represents an approach to the determining the effect of linguistic imprecision, i.e., the inability of experts to provide crisp rules. The

Spacecube: A Family of Reconfigurable Hybrid On-Board Science Data Processors

NASA Technical Reports Server (NTRS)

Flatley, Thomas P.

2015-01-01

SpaceCube is a family of Field Programmable Gate Array (FPGA) based on-board science data processing systems developed at the NASA Goddard Space Flight Center (GSFC). The goal of the SpaceCube program is to provide 10x to 100x improvements in on-board computing power while lowering relative power consumption and cost. SpaceCube is based on the Xilinx Virtex family of FPGAs, which include processor, FPGA logic and digital signal processing (DSP) resources. These processing elements are leveraged to produce a hybrid science data processing platform that accelerates the execution of algorithms by distributing computational functions to the most suitable elements. This approach enables the implementation of complex on-board functions that were previously limited to ground based systems, such as on-board product generation, data reduction, calibration, classification, eventfeature detection, data mining and real-time autonomous operations. The system is fully reconfigurable in flight, including data parameters, software and FPGA logic, through either ground commanding or autonomously in response to detected eventsfeatures in the instrument data stream.

Video rate morphological processor based on a redundant number representation

NASA Astrophysics Data System (ADS)

Kuczborski, Wojciech; Attikiouzel, Yianni; Crebbin, Gregory A.

1992-03-01

This paper presents a video rate morphological processor for automated visual inspection of printed circuit boards, integrated circuit masks, and other complex objects. Inspection algorithms are based on gray-scale mathematical morphology. Hardware complexity of the known methods of real-time implementation of gray-scale morphology--the umbra transform and the threshold decomposition--has prompted us to propose a novel technique which applied an arithmetic system without carrying propagation. After considering several arithmetic systems, a redundant number representation has been selected for implementation. Two options are analyzed here. The first is a pure signed digit number representation (SDNR) with the base of 4. The second option is a combination of the base-2 SDNR (to represent gray levels of images) and the conventional twos complement code (to represent gray levels of structuring elements). Operation principle of the morphological processor is based on the concept of the digit level systolic array. Individual processing units and small memory elements create a pipeline. The memory elements store current image windows (kernels). All operation primitives of processing units apply a unified direction of digit processing: most significant digit first (MSDF). The implementation technology is based on the field programmable gate arrays by Xilinx. This paper justified the rationality of a new approach to logic design, which is the decomposition of Boolean functions instead of Boolean minimization.

Fundamentals of Digital Logic, 7-1. Military Curriculum Materials for Vocational and Technical Education.

ERIC Educational Resources Information Center

Marine Corps, Washington, DC.

Targeted for grades 10 through adult, these military-developed curriculum materials consist of a student lesson book with text readings and review exercises designed to prepare electronic personnel for further training in digital techniques. Covered in the five lessons are binary arithmetic (number systems, decimal systems, the mathematical form…

Evolving Digital Ecological Networks

PubMed Central

Wagner, Aaron P.; Ofria, Charles

2013-01-01

“It is hard to realize that the living world as we know it is just one among many possibilities” [1]. Evolving digital ecological networks are webs of interacting, self-replicating, and evolving computer programs (i.e., digital organisms) that experience the same major ecological interactions as biological organisms (e.g., competition, predation, parasitism, and mutualism). Despite being computational, these programs evolve quickly in an open-ended way, and starting from only one or two ancestral organisms, the formation of ecological networks can be observed in real-time by tracking interactions between the constantly evolving organism phenotypes. These phenotypes may be defined by combinations of logical computations (hereafter tasks) that digital organisms perform and by expressed behaviors that have evolved. The types and outcomes of interactions between phenotypes are determined by task overlap for logic-defined phenotypes and by responses to encounters in the case of behavioral phenotypes. Biologists use these evolving networks to study active and fundamental topics within evolutionary ecology (e.g., the extent to which the architecture of multispecies networks shape coevolutionary outcomes, and the processes involved). PMID:23533370

High-Speed Current dq PI Controller for Vector Controlled PMSM Drive

PubMed Central

Reaz, Mamun Bin Ibne; Rahman, Labonnah Farzana; Chang, Tae Gyu

2014-01-01

High-speed current controller for vector controlled permanent magnet synchronous motor (PMSM) is presented. The controller is developed based on modular design for faster calculation and uses fixed-point proportional-integral (PI) method for improved accuracy. Current dq controller is usually implemented in digital signal processor (DSP) based computer. However, DSP based solutions are reaching their physical limits, which are few microseconds. Besides, digital solutions suffer from high implementation cost. In this research, the overall controller is realizing in field programmable gate array (FPGA). FPGA implementation of the overall controlling algorithm will certainly trim down the execution time significantly to guarantee the steadiness of the motor. Agilent 16821A Logic Analyzer is employed to validate the result of the implemented design in FPGA. Experimental results indicate that the proposed current dq PI controller needs only 50 ns of execution time in 40 MHz clock, which is the lowest computational cycle for the era. PMID:24574913

High performance Si nanowire field-effect-transistors based on a CMOS inverter with tunable threshold voltage.

PubMed

Van, Ngoc Huynh; Lee, Jae-Hyun; Sohn, Jung Inn; Cha, Seung Nam; Whang, Dongmok; Kim, Jong Min; Kang, Dae Joon

2014-05-21

We successfully fabricated nanowire-based complementary metal-oxide semiconductor (NWCMOS) inverter devices by utilizing n- and p-type Si nanowire field-effect-transistors (NWFETs) via a low-temperature fabrication processing technique. We demonstrate that NWCMOS inverter devices can be operated at less than 1 V, a significantly lower voltage than that of typical thin-film based complementary metal-oxide semiconductor (CMOS) inverter devices. This low-voltage operation was accomplished by controlling the threshold voltage of the n-type Si NWFETs through effective management of the nanowire (NW) doping concentration, while realizing high voltage gain (>10) and ultra-low static power dissipation (≤3 pW) for high-performance digital inverter devices. This result offers a viable means of fabricating high-performance, low-operation voltage, and high-density digital logic circuits using a low-temperature fabrication processing technique suitable for next-generation flexible electronics.

Interface For Dual-Channel MIL-STD-1553 Data Bus

NASA Technical Reports Server (NTRS)

Davies, Bryan L.; Heaps, Timothy L.

1992-01-01

Digital electronic subsystem made of commercially available programmable logic arrays and discrete logic devices serves as interface between microprocessor and dual-channel MIL-STD-1553 data bus. Subsystem consumes only 800 mW of power. Provides flexibility in that it is controllable via firmware. Includes only two reading-and-writing ports: one for status and control signals, other for transmission and reception of data.

Hypertext and Multimedia for Functional Enhancement of USARIEM Medical Handbooks and Biomedical Simulation Software.

DTIC Science & Technology

1994-12-01

complex Internet addresses. Hypertext and hypermedia documents have logical and physical structure (Shneiderman, 1993). The logical structure delineates...Rubra, Miliaria Profunda , Anhidrotic Heat Exhaustion, Heat Syncope, Heat Edema, Sunburn, and Heat Tetany. The user may return to the main document...military or scientific organizations via digital communications networks such as the Internet . Access clearance would first be obtained from the USARIEM

The effect of output-input isolation on the scaling and energy consumption of all-spin logic devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hu, Jiaxi; Haratipour, Nazila; Koester, Steven J., E-mail: skoester@umn.edu

All-spin logic (ASL) is a novel approach for digital logic applications wherein spin is used as the state variable instead of charge. One of the challenges in realizing a practical ASL system is the need to ensure non-reciprocity, meaning the information flows from input to output, not vice versa. One approach described previously, is to introduce an asymmetric ground contact, and while this approach was shown to be effective, it remains unclear as to the optimal approach for achieving non-reciprocity in ASL. In this study, we quantitatively analyze techniques to achieve non-reciprocity in ASL devices, and we specifically compare themore » effect of using asymmetric ground position and dipole-coupled output/input isolation. For this analysis, we simulate the switching dynamics of multiple-stage logic devices with FePt and FePd perpendicular magnetic anisotropy materials using a combination of a matrix-based spin circuit model coupled to the Landau–Lifshitz–Gilbert equation. The dipole field is included in this model and can act as both a desirable means of coupling magnets and a source of noise. The dynamic energy consumption has been calculated for these schemes, as a function of input/output magnet separation, and the results show that using a scheme that electrically isolates logic stages produces superior non-reciprocity, thus allowing both improved scaling and reduced energy consumption.« less

Rubbery computing

NASA Astrophysics Data System (ADS)

Wilson, Katherine E.; Henke, E.-F. Markus; Slipher, Geoffrey A.; Anderson, Iain A.

2017-04-01

Electromechanically coupled dielectric elastomer actuators (DEAs) and dielectric elastomer switches (DESs) may form digital logic circuitry made entirely of soft and flexible materials. The expansion in planar area of a DEA exerts force across a DES, which is a soft electrode with strain-dependent resistivity. When compressed, the DES drops steeply in resistance and changes state from non-conducting to conducting. Logic operators may be achieved with different arrangements of interacting DE actuators and switches. We demonstrate combinatorial logic elements, including the fundamental Boolean logic gates, as well as sequential logic elements, including latches and flip-flops. With both data storage and signal processing abilities, the necessary calculating components of a soft computer are available. A noteworthy advantage of a soft computer with mechanosensitive DESs is the potential for responding to environmental strains while locally processing information and generating a reaction, like a muscle reflex.

Computer-aided bone age assessment for ethnically diverse older children using integrated fuzzy logic system

NASA Astrophysics Data System (ADS)

Ma, Kevin; Moin, Paymann; Zhang, Aifeng; Liu, Brent

2010-03-01

Bone Age Assessment (BAA) of children is a clinical procedure frequently performed in pediatric radiology to evaluate the stage of skeletal maturation based on the left hand x-ray radiograph. The current BAA standard in the US is using the Greulich & Pyle (G&P) Hand Atlas, which was developed fifty years ago and was only based on Caucasian population from the Midwest US. To bring the BAA procedure up-to-date with today's population, a Digital Hand Atlas (DHA) consisting of 1400 hand images of normal children of different ethnicities, age, and gender. Based on the DHA and to solve inter- and intra-observer reading discrepancies, an automatic computer-aided bone age assessment system has been developed and tested in clinical environments. The algorithm utilizes features extracted from three regions of interests: phalanges, carpal, and radius. The features are aggregated into a fuzzy logic system, which outputs the calculated bone age. The previous BAA system only uses features from phalanges and carpal, thus BAA result for children over age of 15 is less accurate. In this project, the new radius features are incorporated into the overall BAA system. The bone age results, calculated from the new fuzzy logic system, are compared against radiologists' readings based on G&P atlas, and exhibits an improvement in reading accuracy for older children.

Learning fuzzy logic control system

NASA Technical Reports Server (NTRS)

Lung, Leung Kam

1994-01-01

The performance of the Learning Fuzzy Logic Control System (LFLCS), developed in this thesis, has been evaluated. The Learning Fuzzy Logic Controller (LFLC) learns to control the motor by learning the set of teaching values that are generated by a classical PI controller. It is assumed that the classical PI controller is tuned to minimize the error of a position control system of the D.C. motor. The Learning Fuzzy Logic Controller developed in this thesis is a multi-input single-output network. Training of the Learning Fuzzy Logic Controller is implemented off-line. Upon completion of the training process (using Supervised Learning, and Unsupervised Learning), the LFLC replaces the classical PI controller. In this thesis, a closed loop position control system of a D.C. motor using the LFLC is implemented. The primary focus is on the learning capabilities of the Learning Fuzzy Logic Controller. The learning includes symbolic representation of the Input Linguistic Nodes set and Output Linguistic Notes set. In addition, we investigate the knowledge-based representation for the network. As part of the design process, we implement a digital computer simulation of the LFLCS. The computer simulation program is written in 'C' computer language, and it is implemented in DOS platform. The LFLCS, designed in this thesis, has been developed on a IBM compatible 486-DX2 66 computer. First, the performance of the Learning Fuzzy Logic Controller is evaluated by comparing the angular shaft position of the D.C. motor controlled by a conventional PI controller and that controlled by the LFLC. Second, the symbolic representation of the LFLC and the knowledge-based representation for the network are investigated by observing the parameters of the Fuzzy Logic membership functions and the links at each layer of the LFLC. While there are some limitations of application with this approach, the result of the simulation shows that the LFLC is able to control the angular shaft position of the D.C. motor. Furthermore, the LFLC has better performance in rise time, settling time and steady state error than to the conventional PI controller. This abstract accurately represents the content of the candidate's thesis. I recommend its publication.

DNA-mediated gold nanoparticle signal transducers for combinatorial logic operations and heavy metal ions sensing.

PubMed

Zhang, Yuhuan; Liu, Wei; Zhang, Wentao; Yu, Shaoxuan; Yue, Xiaoyue; Zhu, Wenxin; Zhang, Daohong; Wang, Yanru; Wang, Jianlong

2015-10-15

Herein, the structure of two DNA strands which are complementary except fourteen T-T and C-C mismatches was programmed for the design of the combinatorial logic operation by utilizing the different protective capacities of single chain DNA, part-hybridized DNA and completed-hybridized DNA on unmodified gold nanoparticles. In the presence of either Hg(2+) or Ag(+), the T-Hg(2+)-T or C-Ag(+)-C coordination chemistry could lead to the formation of part-hybridized DNA which keeps gold nanoparticles from clumping after the addition of 40 μL 0.2M NaClO4 solution, but the protection would be screened by 120 μL 0.2M NaClO4 solution. While the coexistence of Hg(2+), Ag(+) caused the formation of completed-hybridized DNA and the protection for gold nanoparticles lost in either 40 μL or 120 μL NaClO4 solutions. Benefiting from sharing of the same inputs of Hg(2+) and Ag(+), OR and AND logic gates were easily integrated into a simple colorimetric combinatorial logic operation in one system, which make it possible to execute logic gates in parallel to mimic arithmetic calculations on a binary digit. Furthermore, two other logic gates including INHIBIT1 and INHIBIT2 were realized to integrated with OR logic gate both for simultaneous qualitative discrimination and quantitative determination of Hg(2+) and Ag(+). Results indicate that the developed logic system based on the different protective capacities of DNA structure on gold nanoparticles provides a new pathway for the design of the combinatorial logic operation in one system and presents a useful strategy for development of advanced sensors, which may have potential applications in multiplex chemical analysis and molecular-scale computer design. Copyright © 2015 Elsevier B.V. All rights reserved.

Turbulence simulation mechanization for Space Shuttle Orbiter dynamics and control studies

NASA Technical Reports Server (NTRS)

Tatom, F. B.; King, R. L.

1977-01-01

The current version of the NASA turbulent simulation model in the form of a digital computer program, TBMOD, is described. The logic of the program is discussed and all inputs and outputs are defined. An alternate method of shear simulation suitable for incorporation into the model is presented. The simulation is based on a von Karman spectrum and the assumption of isotropy. The resulting spectral density functions for the shear model are included.

Single InAs/GaSb nanowire low-power CMOS inverter.

PubMed

Dey, Anil W; Svensson, Johannes; Borg, B Mattias; Ek, Martin; Wernersson, Lars-Erik

2012-11-14

III-V semiconductors have so far predominately been employed for n-type transistors in high-frequency applications. This development is based on the advantageous transport properties and the large variety of heterostructure combinations in the family of III-V semiconductors. In contrast, reports on p-type devices with high hole mobility suitable for complementary metal-oxide-semiconductor (CMOS) circuits for low-power operation are scarce. In addition, the difficulty to integrate both n- and p-type devices on the same substrate without the use of complex buffer layers has hampered the development of III-V based digital logic. Here, inverters fabricated from single n-InAs/p-GaSb heterostructure nanowires are demonstrated in a simple processing scheme. Using undoped segments and aggressively scaled high-κ dielectric, enhancement mode operation suitable for digital logic is obtained for both types of transistors. State-of-the-art on- and off-state characteristics are obtained and the individual long-channel n- and p-type transistors exhibit minimum subthreshold swings of SS = 98 mV/dec and SS = 400 mV/dec, respectively, at V(ds) = 0.5 V. Inverter characteristics display a full signal swing and maximum gain of 10.5 with a small device-to-device variability. Complete inversion is measured at low frequencies although large parasitic capacitances deform the waveform at higher frequencies.

Low power signal processing research at Stanford

NASA Technical Reports Server (NTRS)

Burr, J.; Williamson, P. R.; Peterson, A.

1991-01-01

This paper gives an overview of the research being conducted at Stanford University's Space, Telecommunications, and Radioscience Laboratory in the area of low energy computation. It discusses the work we are doing in large scale digital VLSI neural networks, interleaved processor and pipelined memory architectures, energy estimation and optimization, multichip module packaging, and low voltage digital logic.

The Matter of New Media Making: An Intra-Action Analysis of Adolescents Making a Digital Book Trailer

ERIC Educational Resources Information Center

Ehret, Christian; Hollett, Ty; Jocius, Robin

2016-01-01

Representational logic cannot account for the entanglements of all that matters in making new media: feeling bodies, vibrant matter, feeling bodies and vibrant matter all moving and at different rates. In the currently shifting communicative landscape, where mobile technologies are the primary means for youths' digital production, all this…

Monolithically Integrated Flexible Black Phosphorus Complementary Inverter Circuits.

PubMed

Liu, Yuanda; Ang, Kah-Wee

2017-07-25

Two-dimensional (2D) inverters are a fundamental building block for flexible logic circuits which have previously been realized by heterogeneously wiring transistors with two discrete channel materials. Here, we demonstrate a monolithically integrated complementary inverter made using a homogeneous black phosphorus (BP) nanosheet on flexible substrates. The digital logic inverter circuit is demonstrated via effective threshold voltage tuning within a single BP material, which offers both electron and hole dominated conducting channels with nearly symmetric pinch-off and current saturation. Controllable electron concentration is achieved by accurately modulating the aluminum (Al) donor doping, which realizes BP n-FET with a room-temperature on/off ratio >10 3 . Simultaneously, work function engineering is employed to obtain a low Schottky barrier contact electrode that facilities hole injection, thus enhancing the current density of the BP p-FET by 9.4 times. The flexible inverter circuit shows a clear digital logic voltage inversion operation along with a larger-than-unity direct current voltage gain, while exhibits alternating current dynamic signal switching at a record high frequency up to 100 kHz and remarkable electrical stability upon mechanical bending with a radii as small as 4 mm. Our study demonstrates a practical monolithic integration strategy for achieving functional logic circuits on one material platform, paving the way for future high-density flexible electronic applications.

FPGA-based digital signal processing for the next generation radio astronomy instruments: ultra-pure sideband separation and polarization detection

NASA Astrophysics Data System (ADS)

Alvear, Andrés.; Finger, Ricardo; Fuentes, Roberto; Sapunar, Raúl; Geelen, Tom; Curotto, Franco; Rodríguez, Rafael; Monasterio, David; Reyes, Nicolás.; Mena, Patricio; Bronfman, Leonardo

2016-07-01

Field Programmable Gate Arrays (FPGAs) capacity and Analog to Digital Converters (ADCs) speed have largely increased in the last decade. Nowadays we can find one million or more logic blocks (slices) as well as several thousand arithmetic units (ALUs/DSP) available on a single FPGA chip. We can also commercially procure ADC chips reaching 10 GSPS, with 8 bits resolution or more. This unprecedented power of computing hardware has allowed the digitalization of signal processes traditionally performed by analog components. In radio astronomy, the clearest example has been the development of digital sideband separating receivers which, by replacing the IF hybrid and calibrating the system imbalances, have exhibited a sideband rejection above 40dB; this is 20 to 30dB higher than traditional analog sideband separating (2SB) receivers. In Rodriguez et al.,1 and Finger et al.,2 we have demonstrated very high digital sideband separation at 3mm and 1mm wavelengths, using laboratory setups. We here show the first implementation of such technique with a 3mm receiver integrated into a telescope, where the calibration was performed by quasi-optical injection of the test tone in front of the Cassegrain antenna. We also reported progress in digital polarization synthesis, particularly in the implementation of a calibrated Digital Ortho-Mode Transducer (DOMT) based on the Morgan et al. proof of concept.3 They showed off- line synthesis of polarization with isolation higher than 40dB. We plan to implement a digital polarimeter in a real-time FPGA-based (ROACH-2) platform, to show ultra-pure polarization isolation in a non-stop integrating spectrometer.

Biomolecular filters for improved separation of output signals in enzyme logic systems applied to biomedical analysis.

PubMed

Halámek, Jan; Zhou, Jian; Halámková, Lenka; Bocharova, Vera; Privman, Vladimir; Wang, Joseph; Katz, Evgeny

2011-11-15

Biomolecular logic systems processing biochemical input signals and producing "digital" outputs in the form of YES/NO were developed for analysis of physiological conditions characteristic of liver injury, soft tissue injury, and abdominal trauma. Injury biomarkers were used as input signals for activating the logic systems. Their normal physiological concentrations were defined as logic-0 level, while their pathologically elevated concentrations were defined as logic-1 values. Since the input concentrations applied as logic 0 and 1 values were not sufficiently different, the output signals being at low and high values (0, 1 outputs) were separated with a short gap making their discrimination difficult. Coupled enzymatic reactions functioning as a biomolecular signal processing system with a built-in filter property were developed. The filter process involves a partial back-conversion of the optical-output-signal-yielding product, but only at its low concentrations, thus allowing the proper discrimination between 0 and 1 output values.

Adiabatic quantum-flux-parametron cell library adopting minimalist design

DOE Office of Scientific and Technical Information (OSTI.GOV)

Takeuchi, Naoki, E-mail: takeuchi-naoki-kx@ynu.jp; Yamanashi, Yuki; Yoshikawa, Nobuyuki

We herein build an adiabatic quantum-flux-parametron (AQFP) cell library adopting minimalist design and a symmetric layout. In the proposed minimalist design, every logic cell is designed by arraying four types of building block cells: buffer, NOT, constant, and branch cells. Therefore, minimalist design enables us to effectively build and customize an AQFP cell library. The symmetric layout reduces unwanted parasitic magnetic coupling and ensures a large mutual inductance in an output transformer, which enables very long wiring between logic cells. We design and fabricate several logic circuits using the minimal AQFP cell library so as to test logic cells inmore » the library. Moreover, we experimentally investigate the maximum wiring length between logic cells. Finally, we present an experimental demonstration of an 8-bit carry look-ahead adder designed using the minimal AQFP cell library and demonstrate that the proposed cell library is sufficiently robust to realize large-scale digital circuits.« less

Adiabatic quantum-flux-parametron cell library adopting minimalist design

NASA Astrophysics Data System (ADS)

Takeuchi, Naoki; Yamanashi, Yuki; Yoshikawa, Nobuyuki

2015-05-01

We herein build an adiabatic quantum-flux-parametron (AQFP) cell library adopting minimalist design and a symmetric layout. In the proposed minimalist design, every logic cell is designed by arraying four types of building block cells: buffer, NOT, constant, and branch cells. Therefore, minimalist design enables us to effectively build and customize an AQFP cell library. The symmetric layout reduces unwanted parasitic magnetic coupling and ensures a large mutual inductance in an output transformer, which enables very long wiring between logic cells. We design and fabricate several logic circuits using the minimal AQFP cell library so as to test logic cells in the library. Moreover, we experimentally investigate the maximum wiring length between logic cells. Finally, we present an experimental demonstration of an 8-bit carry look-ahead adder designed using the minimal AQFP cell library and demonstrate that the proposed cell library is sufficiently robust to realize large-scale digital circuits.

A nanocryotron comparator can connect single-flux-quantum circuits to conventional electronics

NASA Astrophysics Data System (ADS)

Zhao, Qing-Yuan; McCaughan, Adam N.; Dane, Andrew E.; Berggren, Karl K.; Ortlepp, Thomas

2017-04-01

Integration with conventional electronics offers a straightforward and economical approach to upgrading existing superconducting technologies, such as scaling up superconducting detectors into large arrays and combining single flux quantum (SFQ) digital circuits with semiconductor logic gates and memories. However, direct output signals from superconducting devices (e.g., Josephson junctions) are usually not compatible with the input requirements of conventional devices (e.g., transistors). Here, we demonstrate the use of a single three-terminal superconducting-nanowire device, called the nanocryotron (nTron), as a digital comparator to combine SFQ circuits with mature semiconductor circuits such as complementary metal oxide semiconductor (CMOS) circuits. Since SFQ circuits can digitize output signals from general superconducting devices and CMOS circuits can interface existing CMOS-compatible electronics, our results demonstrate the feasibility of a general architecture that uses an nTron as an interface to realize a ‘super-hybrid’ system consisting of superconducting detectors, superconducting quantum electronics, CMOS logic gates and memories, and other conventional electronics.

Fault detection and accommodation testing on an F100 engine in an F-15 airplane

NASA Technical Reports Server (NTRS)

Myers, L. P.; Baer-Riedhart, J. L.; Maxwell, M. D.

1985-01-01

The fault detection and accommodation (FDA) methodology for digital engine-control systems may range from simple comparisons of redundant parameters to the more complex and sophisticated observer models of the entire engine system. Evaluations of the various FDA schemes are done using analytical methods, simulation, and limited-altitude-facility testing. Flight testing of the FDA logic has been minimal because of the difficulty of inducing realistic faults in flight. A flight program was conducted to evaluate the fault detection and accommodation capability of a digital electronic engine control in an F-15 aircraft. The objective of the flight program was to induce selected faults and evaluate the resulting actions of the digital engine controller. Comparisons were made between the flight results and predictions. Several anomalies were found in flight and during the ground test. Simulation results showed that the inducement of dual pressure failures was not feasible since the FDA logic was not designed to accommodate these types of failures.

Efficient Phase Unwrapping Architecture for Digital Holographic Microscopy

PubMed Central

Hwang, Wen-Jyi; Cheng, Shih-Chang; Cheng, Chau-Jern

2011-01-01

This paper presents a novel phase unwrapping architecture for accelerating the computational speed of digital holographic microscopy (DHM). A fast Fourier transform (FFT) based phase unwrapping algorithm providing a minimum squared error solution is adopted for hardware implementation because of its simplicity and robustness to noise. The proposed architecture is realized in a pipeline fashion to maximize throughput of the computation. Moreover, the number of hardware multipliers and dividers are minimized to reduce the hardware costs. The proposed architecture is used as a custom user logic in a system on programmable chip (SOPC) for physical performance measurement. Experimental results reveal that the proposed architecture is effective for expediting the computational speed while consuming low hardware resources for designing an embedded DHM system. PMID:22163688

Field Effect Transistor Behavior in Electrospun Polyaniline/Polyethylene Oxide Nanofibers

NASA Technical Reports Server (NTRS)

Miranda, Felix A.; Theofylaktos, Noulie; Mueller, Carl H.; Pinto, Nicholas J.

2004-01-01

Novel transistors and logic devices based on nanotechnology concepts are under intense development. The potential for ultra-low-power circuitry makes nanotechnology attractive for applications such as digital electronics and sensors. For NASA applications, nanotechnology offers tremendous opportunities for increased onboard data processing, and thus autonomous decision-making ability, and novel sensors that detect and respond to environmental stimuli with little oversight requirements. Polyaniline (PANi) is an intriguing material because its electrical conductivity can be changed from insulating to metallic by varying the doping levels and conformations of the polymer chain, and when combined with polyethylene oxide (PEO), can be formed into nanofibers with diameters ranging from approximately 50 to 500 nm (depending on the deposition conditions). The initial goal of this work was to demonstrate transistor behavior in these nanofibers, thus creating a foundation for future logic devices.

Electron lithography STAR design guidelines. Part 1: The STAR user design manual

NASA Technical Reports Server (NTRS)

Trotter, J. D.; Newman, W.

1982-01-01

The STAR system developed by NASA enables any user with a logic diagram to design a semicustom digital MOS integrated circuit. The system is comprised of a library of standard logic cells and computer programs to place, route, and display designs implemented with cells from the library. Library cells of the CMOS metal gate and CMOS silicon gate technologies were simulated using SPICE, and the results are shown and compared.

Reactor protection system with automatic self-testing and diagnostic

DOEpatents

Gaubatz, Donald C.

1996-01-01

A reactor protection system having four divisions, with quad redundant sensors for each scram parameter providing input to four independent microprocessor-based electronic chassis. Each electronic chassis acquires the scram parameter data from its own sensor, digitizes the information, and then transmits the sensor reading to the other three electronic chassis via optical fibers. To increase system availability and reduce false scrams, the reactor protection system employs two levels of voting on a need for reactor scram. The electronic chassis perform software divisional data processing, vote 2/3 with spare based upon information from all four sensors, and send the divisional scram signals to the hardware logic panel, which performs a 2/4 division vote on whether or not to initiate a reactor scram. Each chassis makes a divisional scram decision based on data from all sensors. Automatic detection and discrimination against failed sensors allows the reactor protection system to automatically enter a known state when sensor failures occur. Cross communication of sensor readings allows comparison of four theoretically "identical" values. This permits identification of sensor errors such as drift or malfunction. A diagnostic request for service is issued for errant sensor data. Automated self test and diagnostic monitoring, sensor input through output relay logic, virtually eliminate the need for manual surveillance testing. This provides an ability for each division to cross-check all divisions and to sense failures of the hardware logic.

Reactor protection system with automatic self-testing and diagnostic

DOEpatents

Gaubatz, D.C.

1996-12-17

A reactor protection system is disclosed having four divisions, with quad redundant sensors for each scram parameter providing input to four independent microprocessor-based electronic chassis. Each electronic chassis acquires the scram parameter data from its own sensor, digitizes the information, and then transmits the sensor reading to the other three electronic chassis via optical fibers. To increase system availability and reduce false scrams, the reactor protection system employs two levels of voting on a need for reactor scram. The electronic chassis perform software divisional data processing, vote 2/3 with spare based upon information from all four sensors, and send the divisional scram signals to the hardware logic panel, which performs a 2/4 division vote on whether or not to initiate a reactor scram. Each chassis makes a divisional scram decision based on data from all sensors. Automatic detection and discrimination against failed sensors allows the reactor protection system to automatically enter a known state when sensor failures occur. Cross communication of sensor readings allows comparison of four theoretically ``identical`` values. This permits identification of sensor errors such as drift or malfunction. A diagnostic request for service is issued for errant sensor data. Automated self test and diagnostic monitoring, sensor input through output relay logic, virtually eliminate the need for manual surveillance testing. This provides an ability for each division to cross-check all divisions and to sense failures of the hardware logic. 16 figs.

Solid State pH Sensor Based on Light Emitting Diodes (LED) As Detector Platform

PubMed Central

Lau, King Tong; Shepherd, R.; Diamond, Danny; Diamond, Dermot

2006-01-01

A low-power, high sensitivity, very low-cost light emitting diode (LED)-based device developed for low-cost sensor networks was modified with bromocresol green membrane to work as a solid-state pH sensor. In this approach, a reverse-biased LED functioning as a photodiode is coupled with a second LED configured in conventional emission mode. A simple timer circuit measures how long (in microsecond) it takes for the photocurrent generated on the detector LED to discharge its capacitance from logic 1 (+5 V) to logic 0 (+1.7 V). The entire instrument provides an inherently digital output of light intensity measurements for a few cents. A light dependent resistor (LDR) modified with similar sensor membrane was also used as a comparison method. Both the LED sensor and the LDR sensor responded to various pH buffer solutions in a similar way to obtain sigmoidal curves expected of the dye. The pKa value obtained for the sensors was found to agree with the literature value.

Apollo experience report: Guidance and control systems - Digital autopilot design development

NASA Technical Reports Server (NTRS)

Peters, W. H.; Cox, K. J.

1973-01-01

The development of the Apollo digital autopilots (the primary attitude control systems that were used for all phases of the lunar landing mission) is summarized. This report includes design requirements, design constraints, and design philosophy. The development-process functions and the essential information flow paths are identified. Specific problem areas that existed during the development are included. A discussion is also presented on the benefits inherent in mechanizing attitude-controller logic and dynamic compensation in a digital computer.

A 1 GHz sample rate, 256-channel, 1-bit quantization, CMOS, digital correlator chip

NASA Technical Reports Server (NTRS)

Timoc, C.; Tran, T.; Wongso, J.

1992-01-01

This paper describes the development of a digital correlator chip with the following features: 1 Giga-sample/second; 256 channels; 1-bit quantization; 32-bit counters providing up to 4 seconds integration time at 1 GHz; and very low power dissipation per channel. The improvements in the performance-to-cost ratio of the digital correlator chip are achieved with a combination of systolic architecture, novel pipelined differential logic circuits, and standard 1.0 micron CMOS process.

Germanium-Source Tunnel Field Effect Transistors for Ultra-Low Power Digital Logic

DTIC Science & Technology

2012-05-10

carrier injection via band-to-band tunneling (BTBT) and the absence of thermal (kT) dependence allows for the subthreshold swing to be steeper than... tunneling probability was derived by Kane using time- dependent perturbation theory and Fermi’s Golden Rule [8-9]. This section will instead employ a...be based on tunneling across a reverse- biased p-n junction as shown in Fig. 2.2. In order to obtain a closed form solution of the BTBT

Electro-optic Mach-Zehnder Interferometer based Optical Digital Magnitude Comparator and 1's Complement Calculator

NASA Astrophysics Data System (ADS)

Kumar, Ajay; Raghuwanshi, Sanjeev Kumar

2016-06-01

The optical switching activity is one of the most essential phenomena in the optical domain. The electro-optic effect-based switching phenomena are applicable to generate some effective combinational and sequential logic circuits. The processing of digital computational technique in the optical domain includes some considerable advantages of optical communication technology, e.g. immunity to electro-magnetic interferences, compact size, signal security, parallel computing and larger bandwidth. The paper describes some efficient technique to implement single bit magnitude comparator and 1's complement calculator using the concepts of electro-optic effect. The proposed techniques are simulated on the MATLAB software. However, the suitability of the techniques is verified using the highly reliable Opti-BPM software. It is interesting to analyze the circuits in order to specify some optimized device parameter in order to optimize some performance affecting parameters, e.g. crosstalk, extinction ratio, signal losses through the curved and straight waveguide sections.

Design and Evaluation of a Personal Digital Assistant-based Research Platform for Cochlear Implants

PubMed Central

Ali, Hussnain; Lobo, Arthur P.; Loizou, Philipos C.

2014-01-01

This paper discusses the design, development, features, and clinical evaluation of a personal digital assistant (PDA)-based platform for cochlear implant research. This highly versatile and portable research platform allows researchers to design and perform complex experiments with cochlear implants manufactured by Cochlear Corporation with great ease and flexibility. The research platform includes a portable processor for implementing and evaluating novel speech processing algorithms, a stimulator unit which can be used for electrical stimulation and neurophysio-logic studies with animals, and a recording unit for collecting electroencephalogram/evoked potentials from human subjects. The design of the platform for real time and offline stimulation modes is discussed for electric-only and electric plus acoustic stimulation followed by results from an acute study with implant users for speech intelligibility in quiet and noisy conditions. The results are comparable with users’ clinical processor and very promising for undertaking chronic studies. PMID:23674422

Feed-forward digital phase and amplitude correction system

DOEpatents

Yu, D.U.L.; Conway, P.H.

1994-11-15

Phase and amplitude modifications in repeatable RF pulses at the output of a high power pulsed microwave amplifier are made utilizing a digital feed-forward correction system. A controlled amount of the output power is coupled to a correction system for processing of phase and amplitude information. The correction system comprises circuitry to compare the detected phase and amplitude with the desired phase and amplitude, respectively, and a digitally programmable phase shifter and attenuator and digital logic circuitry to control the phase shifter and attenuator. The phase and amplitude of subsequent are modified by output signals from the correction system. 11 figs.

Feed-forward digital phase and amplitude correction system

DOEpatents

Yu, David U. L.; Conway, Patrick H.

1994-01-01

Phase and amplitude modifications in repeatable RF pulses at the output of a high power pulsed microwave amplifier are made utilizing a digital feed-forward correction system. A controlled amount of the output power is coupled to a correction system for processing of phase and amplitude information. The correction system comprises circuitry to compare the detected phase and amplitude with the desired phase and amplitude, respectively, and a digitally programmable phase shifter and attenuator and digital logic circuitry to control the phase shifter and attenuator. The Phase and amplitude of subsequent are modified by output signals from the correction system.

Hardware synthesis from DDL description. [simulating a digital system for computerized design of large scale integrated circuits

NASA Technical Reports Server (NTRS)

Shiva, S. G.; Shah, A. M.

1980-01-01

The details of digital systems can be conveniently input into the design automation system by means of hardware description language (HDL). The computer aided design and test (CADAT) system at NASA MSFC is used for the LSI design. The digital design language (DDL) was selected as HDL for the CADAT System. DDL translator output can be used for the hardware implementation of the digital design. Problems of selecting the standard cells from the CADAT standard cell library to realize the logic implied by the DDL description of the system are addressed.

Hardware synthesis from DDL. [Digital Design Language for computer aided design and test of LSI

NASA Technical Reports Server (NTRS)

Shah, A. M.; Shiva, S. G.

1981-01-01

The details of the digital systems can be conveniently input into the design automation system by means of Hardware Description Languages (HDL). The Computer Aided Design and Test (CADAT) system at NASA MSFC is used for the LSI design. The Digital Design Language (DDL) has been selected as HDL for the CADAT System. DDL translator output can be used for the hardware implementation of the digital design. This paper addresses problems of selecting the standard cells from the CADAT standard cell library to realize the logic implied by the DDL description of the system.

Design of 4 to 2 line encoder using lithium niobate based Mach Zehnder Interferometers for high speed communication

NASA Astrophysics Data System (ADS)

Pal, Amrindra; Kumar, Santosh; Sharma, Sandeep; Raghuwanshi, Sanjeev K.

2016-04-01

Encoder is a device that allows placing digital information from many inputs to many outputs. Any application of combinational logic circuit can be implemented by using encoder and external gates. In this paper, 4 to 2 line encoder is proposed using electro-optic effect inside lithium-niobate based Mach-Zehnder interferometers (MZIs). The MZI structures have powerful capability to switching an optical input signal to a desired output port. The paper constitutes a mathematical description of the proposed device and thereafter simulation using MATLAB. The study is verified using beam propagation method (BPM).

Design of optical seven-segment decoder using Pockel's effect inside lithium niobate-based waveguide

NASA Astrophysics Data System (ADS)

Pal, Amrindra; Kumar, Santosh; Sharma, Sandeep

2017-01-01

Seven-segment decoder is a device that allows placing digital information from many inputs to many outputs optically, having 11 Mach-Zehnder interferometers (MZIs) for their implementation. The layout of the circuit is implemented to fit the electrical method on an optical logic circuit based on the beam propagation method (BPM). Seven-segment decoder is proposed using electro-optic effect inside lithium niobate-based MZIs. MZI structures are able to switch an optical signal to a desired output port. It consists of a mathematical explanation about the proposed device. The BPM is also used to analyze the study.

Users Guide to Direct Digital Control of Heating, Ventilating, and Air Conditioning Equipment,

DTIC Science & Technology

1985-01-01

cycles, reset, load shedding, chiller optimization , VAV fan synchronization, and optimum start/stop. The prospective buyer of a DDC system should...in Fig- ure 4. Data on setpoints , reset schedules, and event timing, such as that presented in Figure 6, are often even more difficult to find. In con...control logic, setpoint and other data are readily available. Program logic, setpoint and schedule data, and other information stored in a DDC unit

Reasoning About Digital Circuits.

DTIC Science & Technology

1983-07-01

The dissertation will later examine the logic’s formal syntax and semantics in great depth. Below are a few English - language statements and...function have a fixed point. Temporal lolc as a programming langua " Temporal logic can be used directly a a propamuing language . For example, the ...for a separate "sertion language ." For example, the formula S[(I+- );(I + i -- I) (I+2- I) states that if the variable I twice increaes by I in an

High-Speed, High-Resolution Time-to-Digital Conversion

NASA Technical Reports Server (NTRS)

Katz, Richard; Kleyner, Igor; Garcia, Rafael

2013-01-01

This innovation is a series of time-tag pulses from a photomultiplier tube, featuring short time interval between pulses (e.g., 2.5 ns). Using the previous art, dead time between pulses is too long, or too much hardware is required, including a very-high-speed demultiplexer. A faster method is needed. The goal of this work is to provide circuits to time-tag pulses that arrive at a high rate using the hardwired logic in an FPGA - specifically the carry chain - to create what is (in effect) an analog delay line. High-speed pulses travel down the chain in a "wave." For instance, a pulse train has been demonstrated from a 1- GHz source reliably traveling down the carry chain. The size of the carry chain is over 10 ns in the time domain. Thus, multiple pulses will travel down the carry chain in a wave simultaneously. A register clocked by a low-skew clock takes a "snapshot" of the wave. Relatively simple logic can extract the pulses from the snapshot picture by detecting the transitions between logic states. The propagation delay of CMOS (complementary metal oxide semiconductor) logic circuits will differ and/or change as a result of temperature, voltage, age, radiation, and manufacturing variances. The time-to-digital conversion circuits can be calibrated with test signals, or the changes can be nulled by a separate on-die calibration channel, in a closed loop circuit.

The Greenwich Photo-heliographic Results (1874 - 1976): Initial Corrections to the Printed Publications

NASA Astrophysics Data System (ADS)

Erwin, E. H.; Coffey, H. E.; Denig, W. F.; Willis, D. M.; Henwood, R.; Wild, M. N.

2013-11-01

A new sunspot and faculae digital dataset for the interval 1874 - 1955 has been prepared under the auspices of the NOAA National Geophysical Data Center (NGDC). This digital dataset contains measurements of the positions and areas of both sunspots and faculae published initially by the Royal Observatory, Greenwich, and subsequently by the Royal Greenwich Observatory (RGO), under the title Greenwich Photo-heliographic Results ( GPR) , 1874 - 1976. Quality control (QC) procedures based on logical consistency have been used to identify the more obvious errors in the RGO publications. Typical examples of identifiable errors are North versus South errors in specifying heliographic latitude, errors in specifying heliographic (Carrington) longitude, errors in the dates and times, errors in sunspot group numbers, arithmetic errors in the summation process, and the occasional omission of solar ephemerides. Although the number of errors in the RGO publications is remarkably small, an initial table of necessary corrections is provided for the interval 1874 - 1917. Moreover, as noted in the preceding companion papers, the existence of two independently prepared digital datasets, which both contain information on sunspot positions and areas, makes it possible to outline a preliminary strategy for the development of an even more accurate digital dataset. Further work is in progress to generate an extremely reliable sunspot digital dataset, based on the long programme of solar observations supported first by the Royal Observatory, Greenwich, and then by the Royal Greenwich Observatory.

Random noise effects in pulse-mode digital multilayer neural networks.

PubMed

Kim, Y C; Shanblatt, M A

1995-01-01

A pulse-mode digital multilayer neural network (DMNN) based on stochastic computing techniques is implemented with simple logic gates as basic computing elements. The pulse-mode signal representation and the use of simple logic gates for neural operations lead to a massively parallel yet compact and flexible network architecture, well suited for VLSI implementation. Algebraic neural operations are replaced by stochastic processes using pseudorandom pulse sequences. The distributions of the results from the stochastic processes are approximated using the hypergeometric distribution. Synaptic weights and neuron states are represented as probabilities and estimated as average pulse occurrence rates in corresponding pulse sequences. A statistical model of the noise (error) is developed to estimate the relative accuracy associated with stochastic computing in terms of mean and variance. Computational differences are then explained by comparison to deterministic neural computations. DMNN feedforward architectures are modeled in VHDL using character recognition problems as testbeds. Computational accuracy is analyzed, and the results of the statistical model are compared with the actual simulation results. Experiments show that the calculations performed in the DMNN are more accurate than those anticipated when Bernoulli sequences are assumed, as is common in the literature. Furthermore, the statistical model successfully predicts the accuracy of the operations performed in the DMNN.

Development of ADOCS controllers and control laws. Volume 2: Literature review and preliminary analysis

NASA Technical Reports Server (NTRS)

Landis, Kenneth H.; Glusman, Steven I.

1985-01-01

The Advanced Cockpit Controls/Advanced Flight Control System (ACC/AFCS) study was conducted by the Boeing Vertol Company as part of the Army's Advanced Digital/Optical Control System (ADOCS) program. Specifically, the ACC/AFCS investigation was aimed at developing the flight control laws for the ADOCS demonstrator aircraft which will provide satisfactory handling qualities for an attack helicopter mission. The three major elements of design considered are as follows: Pilot's integrated Side-Stick Controller (SSC) -- Number of axes controlled; force/displacement characteristics; ergonomic design. Stability and Control Augmentation System (SCAS)--Digital flight control laws for the various mission phases; SCAS mode switching logic. Pilot's Displays--For night/adverse weather conditions, the dynamics of the superimposed symbology presented to the pilot in a format similar to the Advanced Attack Helicopter (AAH) Pilot Night Vision System (PNVS) for each mission phase as a function of ACAS characteristics; display mode switching logic. Findings from the literature review and the analysis and synthesis of desired control laws are reported in Volume 2. Conclusions drawn from pilot rating data and commentary were used to formulate recommendations for the ADOCS demonstrator flight control system design. The ACC/AFCS simulation data also provide an extensive data base to aid the development of advanced flight control system design for future V/STOL aircraft.

Development of ADOCS controllers and control laws. Volume 1: Executive summary

NASA Technical Reports Server (NTRS)

Landis, Kenneth H.; Glusman, Steven I.

1985-01-01

The Advanced Cockpit Controls/Advanced Flight Control System (ACC/AFCS) study was conducted by the Boeing Vertol Company as part of the Army's Advanced Digital/Optical Control System (ADOCS) program. Specifically, the ACC/AFCS investigation was aimed at developing the flight control laws for the ADOCS demonstrator aircraft that will provide satisfactory handling qualities for an attack helicopter mission. The three major elements of design considered during the study are as follows: Pilot's integrated Side-Stick Controller (SSC) -- Number of axes controlled; force/displacement characteristics; ergonomic design. Stability and Control Augmentation System (SCAS)--Digital flight control laws for the various mission phases; SCAS mode switching logic. Pilot's Displays--For night/adverse weather conditions, the dynamics of the superimposed symbology presented to the pilot in a format similar to the Advanced Attack Helicopter (AAH) Pilot Night Vision System (PNVS) for each mission phase as a function of SCAS characteristics; display mode switching logic. Volume 1 is an Executive Summary of the study. Conclusions drawn from analysis of pilot rating data and commentary were used to formulate recommendations for the ADOCS demonstrator flight control system design. The ACC/AFCS simulation data also provide an extensive data base to aid the development of advanced flight control system design for future V/STOL aircraft.

Riemann-Hypothesis Millennium-Problem(MP) Physics Proof via CATEGORY-SEMANTICS(C-S)/F=C Aristotle SQUARE-of-OPPOSITION(SoO) DEduction-LOGIC DichotomY

NASA Astrophysics Data System (ADS)

Baez, J.; Lapidaryus, M.; Siegel, Edward Carl-Ludwig

2011-03-01

Riemann-hypothesis physics-proof combines: Siegel-Antonoff-Smith[AMS Joint Mtg.(2002)-Abs.973-03-126] digits on-average statistics HIll[Am. J. Math 123, 3, 887(1996)] logarithm-function's (1,0)-fixed-point base=units=scale-invariance proven Newcomb[Am. J. Math. 4, 39(1881)]-Weyl[Goett. Nachr.(1914); Math. Ann. 7, 313(1916)]-Benford[Proc. Am. Phil. Soc. 78, 4, 51(1938)]-law [Kac, Math. of Stat.-Reasoning(1955); Raimi, Sci. Am. 221, 109(1969)] algebraic-inversion to ONLY Bose-Einstein quantum-statistics(BEQS) with digit d = 0 gapFUL Bose-Einstein Condensation(BEC) insight that digits are quanta are bosons were always digits, via Siegel-Baez category-semantics tabular list-format matrix truth-table analytics in Plato-Aristotle classic "square-of-opposition" : FUZZYICS=CATEGORYICS/Category-Semantics, with Goodkind Bose-Einstein condensation(BEC) ABOVE ground-state with/and Rayleigh(cut-limit of "short-cut method";1870)-Polya(1922)-"Anderson"(1958) localization [Doyle and Snell, Random-Walks and Electrical-Networks, MAA(1981)-p.99-100!!!].

Planning an Integrated On-Line Library system (IOLS)

DTIC Science & Technology

1989-03-01

Logical Workflow for Circulation of Library Materials ............. 14 Figure 9. Detail of Circulation of Libary Materials ...................... 15...Operating Honolulu, HI 96826 System (808) 947-4441 DATA RESEARCH ASSOCIATES, Inc. (ATLAS) 9270 Olive Blvd. St. Louis, MO 01775 DIGITAL EQUIPMENT CORP... DIGITAL EQUIPMENT CORP. Stow, MA 01775 (617) 897-7163 EYRING LIBRARY SYSTEMS (CARL) 5280 S. West, Suite E260 Salt Lake City, UT 84107 TANDEM SYSTEMS

Surface-confined assemblies and polymers for molecular logic.

PubMed

de Ruiter, Graham; van der Boom, Milko E

2011-08-16

Stimuli responsive materials are capable of mimicking the operation characteristics of logic gates such as AND, OR, NOR, and even flip-flops. Since the development of molecular sensors and the introduction of the first AND gate in solution by de Silva in 1993, Molecular (Boolean) Logic and Computing (MBLC) has become increasingly popular. In this Account, we present recent research activities that focus on MBLC with electrochromic polymers and metal polypyridyl complexes on a solid support. Metal polypyridyl complexes act as useful sensors to a variety of analytes in solution (i.e., H(2)O, Fe(2+/3+), Cr(6+), NO(+)) and in the gas phase (NO(x) in air). This information transfer, whether the analyte is present, is based on the reversible redox chemistry of the metal complexes, which are stable up to 200 °C in air. The concurrent changes in the optical properties are nondestructive and fast. In such a setup, the input is directly related to the output and, therefore, can be represented by one-input logic gates. These input-output relationships are extendable for mimicking the diverse functions of essential molecular logic gates and circuits within a set of Boolean algebraic operations. Such a molecular approach towards Boolean logic has yielded a series of proof-of-concept devices: logic gates, multiplexers, half-adders, and flip-flop logic circuits. MBLC is a versatile and, potentially, a parallel approach to silicon circuits: assemblies of these molecular gates can perform a wide variety of logic tasks through reconfiguration of their inputs. Although these developments do not require a semiconductor blueprint, similar guidelines such as signal propagation, gate-to-gate communication, propagation delay, and combinatorial and sequential logic will play a critical role in allowing this field to mature. For instance, gate-to-gate communication by chemical wiring of the gates with metal ions as electron carriers results in the integration of stand-alone systems: the output of one gate is used as the input for another gate. Using the same setup, we were able to display both combinatorial and sequential logic. We have demonstrated MBLC by coupling electrochemical inputs with optical readout, which resulted in various logic architectures built on a redox-active, functionalized surface. Electrochemically operated sequential logic systems such as flip-flops, multivalued logic, and multistate memory could enhance computational power without increasing spatial requirements. Applying multivalued digits in data storage could exponentially increase memory capacity. Furthermore, we evaluate the pros and cons of MBLC and identify targets for future research in this Account. © 2011 American Chemical Society

Performance characteristics of a nanoscale double-gate reconfigurable array

NASA Astrophysics Data System (ADS)

Beckett, Paul

2008-12-01

The double gate transistor is a promising device applicable to deep sub-micron design due to its inherent resistance to short-channel effects and superior subthreshold performance. Using both TCAD and SPICE circuit simulation, it is shown that the characteristics of fully depleted dual-gate thin-body Schottky barrier silicon transistors will not only uncouple the conflicting requirements of high performance and low standby power in digital logic, but will also allow the development of a locally-connected reconfigurable computing mesh. The magnitude of the threshold shift effect will scale with device dimensions and will remain compatible with oxide reliability constraints. A field-programmable architecture based on the double gate transistor is described in which the operating point of the circuit is biased via one gate while the other gate is used to form the logic array, such that complex heterogeneous computing functions may be developed from this homogeneous, mesh-connected organization.

WNN 92; Proceedings of the 3rd Workshop on Neural Networks: Academic/Industrial/NASA/Defense, Auburn Univ., AL, Feb. 10-12, 1992 and South Shore Harbour, TX, Nov. 4-6, 1992

NASA Technical Reports Server (NTRS)

Padgett, Mary L. (Editor)

1993-01-01

The present conference discusses such neural networks (NN) related topics as their current development status, NN architectures, NN learning rules, NN optimization methods, NN temporal models, NN control methods, NN pattern recognition systems and applications, biological and biomedical applications of NNs, VLSI design techniques for NNs, NN systems simulation, fuzzy logic, and genetic algorithms. Attention is given to missileborne integrated NNs, adaptive-mixture NNs, implementable learning rules, an NN simulator for travelling salesman problem solutions, similarity-based forecasting, NN control of hypersonic aircraft takeoff, NN control of the Space Shuttle Arm, an adaptive NN robot manipulator controller, a synthetic approach to digital filtering, NNs for speech analysis, adaptive spline networks, an anticipatory fuzzy logic controller, and encoding operations for fuzzy associative memories.

Graphene-based non-Boolean logic circuits

NASA Astrophysics Data System (ADS)

Liu, Guanxiong; Ahsan, Sonia; Khitun, Alexander G.; Lake, Roger K.; Balandin, Alexander A.

2013-10-01

Graphene revealed a number of unique properties beneficial for electronics. However, graphene does not have an energy band-gap, which presents a serious hurdle for its applications in digital logic gates. The efforts to induce a band-gap in graphene via quantum confinement or surface functionalization have not resulted in a breakthrough. Here we show that the negative differential resistance experimentally observed in graphene field-effect transistors of "conventional" design allows for construction of viable non-Boolean computational architectures with the gapless graphene. The negative differential resistance—observed under certain biasing schemes—is an intrinsic property of graphene, resulting from its symmetric band structure. Our atomistic modeling shows that the negative differential resistance appears not only in the drift-diffusion regime but also in the ballistic regime at the nanometer-scale—although the physics changes. The obtained results present a conceptual change in graphene research and indicate an alternative route for graphene's applications in information processing.

Hardness assurance testing and radiation hardening by design techniques for silicon-germanium heterojunction bipolar transistors and digital logic circuits

NASA Astrophysics Data System (ADS)

Sutton, Akil K.

Hydrocarbon exploration, global navigation satellite systems, computed tomography, and aircraft avionics are just a few examples of applications that require system operation at an ambient temperature, pressure, or radiation level outside the range covered by military specifications. The electronics employed in these applications are known as "extreme environment electronics." On account of the increased cost resulting from both process modifications and the use of exotic substrate materials, only a handful of semiconductor foundries have specialized in the production of extreme environment electronics. Protection of these electronic systems in an extreme environment may be attained by encapsulating sensitive circuits in a controlled environment, which provides isolation from the hostile ambient, often at a significant cost and performance penalty. In a significant departure from this traditional approach, system designers have begun to use commercial off-the-shelf technology platforms with built in mitigation techniques for extreme environment applications. Such an approach simultaneously leverages the state of the art in technology performance with significant savings in project cost. Silicon-germanium is one such commercial technology platform that demonstrates potential for deployment into extreme environment applications as a result of its excellent performance at cryogenic temperatures, remarkable tolerance to radiation-induced degradation, and monolithic integration with silicon-based manufacturing. In this dissertation the radiation response of silicon-germanium technology is investigated, and novel transistor-level layout-based techniques are implemented to improve the radiation tolerance of HBT digital logic.

Closed circuit TV system automatically guides welding arc

NASA Technical Reports Server (NTRS)

Stephans, D. L.; Wall, W. A., Jr.

1968-01-01

Closed circuit television /CCTV/ system automatically guides a welding torch to position the welding arc accurately along weld seams. Digital counting and logic techniques incorporated in the control circuitry, ensure performance reliability.

Flip-Flop Digital Modulator

NASA Technical Reports Server (NTRS)

Eno, R. F.

1984-01-01

Clock switched on and off in response to data signal. Flip-flop modulator generates square-wave carrier frequency that is half clock frequency and turns carrier on and off. Final demodulator output logical inverse of data input.

High-performance image processing architecture

NASA Astrophysics Data System (ADS)

Coffield, Patrick C.

1992-04-01

The proposed architecture is a logical design specifically for image processing and other related computations. The design is a hybrid electro-optical concept consisting of three tightly coupled components: a spatial configuration processor (the optical analog portion), a weighting processor (digital), and an accumulation processor (digital). The systolic flow of data and image processing operations are directed by a control buffer and pipelined to each of the three processing components. The image processing operations are defined by an image algebra developed by the University of Florida. The algebra is capable of describing all common image-to-image transformations. The merit of this architectural design is how elegantly it handles the natural decomposition of algebraic functions into spatially distributed, point-wise operations. The effect of this particular decomposition allows convolution type operations to be computed strictly as a function of the number of elements in the template (mask, filter, etc.) instead of the number of picture elements in the image. Thus, a substantial increase in throughput is realized. The logical architecture may take any number of physical forms. While a hybrid electro-optical implementation is of primary interest, the benefits and design issues of an all digital implementation are also discussed. The potential utility of this architectural design lies in its ability to control all the arithmetic and logic operations of the image algebra's generalized matrix product. This is the most powerful fundamental formulation in the algebra, thus allowing a wide range of applications.

NULL Convention Floating Point Multiplier

PubMed Central

Ramachandran, Seshasayanan

2015-01-01

Floating point multiplication is a critical part in high dynamic range and computational intensive digital signal processing applications which require high precision and low power. This paper presents the design of an IEEE 754 single precision floating point multiplier using asynchronous NULL convention logic paradigm. Rounding has not been implemented to suit high precision applications. The novelty of the research is that it is the first ever NULL convention logic multiplier, designed to perform floating point multiplication. The proposed multiplier offers substantial decrease in power consumption when compared with its synchronous version. Performance attributes of the NULL convention logic floating point multiplier, obtained from Xilinx simulation and Cadence, are compared with its equivalent synchronous implementation. PMID:25879069

NULL convention floating point multiplier.

PubMed

Albert, Anitha Juliette; Ramachandran, Seshasayanan

2015-01-01

Floating point multiplication is a critical part in high dynamic range and computational intensive digital signal processing applications which require high precision and low power. This paper presents the design of an IEEE 754 single precision floating point multiplier using asynchronous NULL convention logic paradigm. Rounding has not been implemented to suit high precision applications. The novelty of the research is that it is the first ever NULL convention logic multiplier, designed to perform floating point multiplication. The proposed multiplier offers substantial decrease in power consumption when compared with its synchronous version. Performance attributes of the NULL convention logic floating point multiplier, obtained from Xilinx simulation and Cadence, are compared with its equivalent synchronous implementation.

A bipolar population counter using wave pipelining to achieve 2.5 x normal clock frequency

NASA Technical Reports Server (NTRS)

Wong, Derek C.; De Micheli, Giovanni; Flynn, Michael J.; Huston, Robert E.

1992-01-01

Wave pipelining is a technique for pipelining digital systems that can increase clock frequency in practical circuits without increasing the number of storage elements. In wave pipelining, multiple coherent waves of data are sent through a block of combinational logic by applying new inputs faster than the delay through the logic. The throughput of a 63-b CML population counter was increased from 97 to 250 MHz using wave pipelining. The internal circuit is flowthrough combinational logic. Novel CAD methods have balanced all input-to-output paths to about the same delay. This allows multiple data waves to propagate in sequence when the circuit is clocked faster than its propagation delay.

Complex logic functions implemented with quantum dot bionanophotonic circuits.

PubMed

Claussen, Jonathan C; Hildebrandt, Niko; Susumu, Kimihiro; Ancona, Mario G; Medintz, Igor L

2014-03-26

We combine quantum dots (QDs) with long-lifetime terbium complexes (Tb), a near-IR Alexa Fluor dye (A647), and self-assembling peptides to demonstrate combinatorial and sequential bionanophotonic logic devices that function by time-gated Förster resonance energy transfer (FRET). Upon excitation, the Tb-QD-A647 FRET-complex produces time-dependent photoluminescent signatures from multi-FRET pathways enabled by the capacitor-like behavior of the Tb. The unique photoluminescent signatures are manipulated by ratiometrically varying dye/Tb inputs and collection time. Fluorescent output is converted into Boolean logic states to create complex arithmetic circuits including the half-adder/half-subtractor, 2:1 multiplexer/1:2 demultiplexer, and a 3-digit, 16-combination keypad lock.

Macro Pixel ASIC (MPA): the readout ASIC for the pixel-strip (PS) module of the CMS outer tracker at HL-LHC

NASA Astrophysics Data System (ADS)

Ceresa, D.; Marchioro, A.; Kloukinas, K.; Kaplon, J.; Bialas, W.; Re, V.; Traversi, G.; Gaioni, L.; Ratti, L.

2014-11-01

The CMS tracker at HL-LHC is required to provide prompt information on particles with high transverse momentum to the central Level 1 trigger. For this purpose, the innermost part of the outer tracker is based on a combination of a pixelated sensor with a short strip sensor, the so-called Pixel-Strip module (PS). The readout of these sensors is carried out by distinct ASICs, the Strip Sensor ASIC (SSA), for the strip layer, and the Macro Pixel ASIC (MPA) for the pixel layer. The processing of the data directly on the front-end module represents a design challenge due to the large data volume (30720 pixels and 1920 strips per module) and the limited power budget. This is the reason why several studies have been carried out to find the best compromise between ASICs performance and power consumption. This paper describes the current status of the MPA ASIC development where the logic for generating prompt information on particles with high transverse momentum is implemented. An overview of the readout method is presented with particular attention on the cluster reduction, position encoding and momentum discrimination logic. Concerning the architectural studies, a software test bench capable of reading physics Monte-Carlo generated events has been developed and used to validate the MPA design and to evaluate the MPA performance. The MPA-Light is scheduled to be submitted for fabrication this year and will include the full analog functions and a part of the digital logic of the final version in order to qualify the chosen VLSI technology for the analog front-end, the module assembly and the low voltage digital supply.

Dynamic partial reconfiguration of logic controllers implemented in FPGAs

NASA Astrophysics Data System (ADS)

Bazydło, Grzegorz; Wiśniewski, Remigiusz

2016-09-01

Technological progress in recent years benefits in digital circuits containing millions of logic gates with the capability for reprogramming and reconfiguring. On the one hand it provides the unprecedented computational power, but on the other hand the modelled systems are becoming increasingly complex, hierarchical and concurrent. Therefore, abstract modelling supported by the Computer Aided Design tools becomes a very important task. Even the higher consumption of the basic electronic components seems to be acceptable because chip manufacturing costs tend to fall over the time. The paper presents a modelling approach for logic controllers with the use of Unified Modelling Language (UML). Thanks to the Model Driven Development approach, starting with a UML state machine model, through the construction of an intermediate Hierarchical Concurrent Finite State Machine model, a collection of Verilog files is created. The system description generated in hardware description language can be synthesized and implemented in reconfigurable devices, such as FPGAs. Modular specification of the prototyped controller permits for further dynamic partial reconfiguration of the prototyped system. The idea bases on the exchanging of the functionality of the already implemented controller without stopping of the FPGA device. It means, that a part (for example a single module) of the logic controller is replaced by other version (called context), while the rest of the system is still running. The method is illustrated by a practical example by an exemplary Home Area Network system.

Digi Island: A Serious Game for Teaching and Learning Digital Circuit Optimization

NASA Technical Reports Server (NTRS)

Harper, Michael; Miller, Joseph; Shen, Yuzhong

2011-01-01

Karnaugh maps, also known as K-maps, are a tool used to optimize or simplify digital logic circuits. A K-map is a graphical display of a logic circuit. K-map optimization is essentially the process of finding a minimum number of maximal aggregations of K-map cells. with values of 1 according to a set of rules. The Digi Island is a serious game designed for aiding students to learn K-map optimization. The game takes place on an exotic island (called Digi Island) in the Pacific Ocean . The player is an adventurer to the Digi Island and will transform it into a tourist attraction by developing real estates, such as amusement parks.and hotels. The Digi Island game elegantly converts boring 1s and Os in digital circuits into usable and unusable spaces on a beautiful island and transforms K-map optimization into real estate development, an activity with which many students are familiar and also interested in. This paper discusses the design, development, and some preliminary results of the Digi Island game.

Flight test of a full authority Digital Electronic Engine Control system in an F-15 aircraft

NASA Technical Reports Server (NTRS)

Barrett, W. J.; Rembold, J. P.; Burcham, F. W.; Myers, L.

1981-01-01

The Digital Electronic Engine Control (DEEC) system considered is a relatively low cost digital full authority control system containing selectively redundant components and fault detection logic with capability for accommodating faults to various levels of operational capability. The DEEC digital control system is built around a 16-bit, 1.2 microsecond cycle time, CMOS microprocessor, microcomputer system with approximately 14 K of available memory. Attention is given to the control mode, component bench testing, closed loop bench testing, a failure mode and effects analysis, sea-level engine testing, simulated altitude engine testing, flight testing, the data system, cockpit, and real time display.

Memory device for two-dimensional radiant energy array computers

NASA Technical Reports Server (NTRS)

Schaefer, D. H.; Strong, J. P., III (Inventor)

1977-01-01

A memory device for two dimensional radiant energy array computers was developed, in which the memory device stores digital information in an input array of radiant energy digital signals that are characterized by ordered rows and columns. The memory device contains a radiant energy logic storing device having a pair of input surface locations for receiving a pair of separate radiant energy digital signal arrays and an output surface location adapted to transmit a radiant energy digital signal array. A regenerative feedback device that couples one of the input surface locations to the output surface location in a manner for causing regenerative feedback is also included

The development of an interim generalized gate logic software simulator

NASA Technical Reports Server (NTRS)

Mcgough, J. G.; Nemeroff, S.

1985-01-01

A proof-of-concept computer program called IGGLOSS (Interim Generalized Gate Logic Software Simulator) was developed and is discussed. The simulator engine was designed to perform stochastic estimation of self test coverage (fault-detection latency times) of digital computers or systems. A major attribute of the IGGLOSS is its high-speed simulation: 9.5 x 1,000,000 gates/cpu sec for nonfaulted circuits and 4.4 x 1,000,000 gates/cpu sec for faulted circuits on a VAX 11/780 host computer.

Hardware Implementation of 32-Bit High-Speed Direct Digital Frequency Synthesizer

PubMed Central

Ibrahim, Salah Hasan; Ali, Sawal Hamid Md.; Islam, Md. Shabiul

2014-01-01

The design and implementation of a high-speed direct digital frequency synthesizer are presented. A modified Brent-Kung parallel adder is combined with pipelining technique to improve the speed of the system. A gated clock technique is proposed to reduce the number of registers in the phase accumulator design. The quarter wave symmetry technique is used to store only one quarter of the sine wave. The ROM lookup table (LUT) is partitioned into three 4-bit sub-ROMs based on angular decomposition technique and trigonometric identity. Exploiting the advantages of sine-cosine symmetrical attributes together with XOR logic gates, one sub-ROM block can be removed from the design. These techniques, compressed the ROM into 368 bits. The ROM compressed ratio is 534.2 : 1, with only two adders, two multipliers, and XOR-gates with high frequency resolution of 0.029 Hz. These techniques make the direct digital frequency synthesizer an attractive candidate for wireless communication applications. PMID:24991635

Design Architecture and Initial Results from an FPGA Based Digital Receiver for Multistatic Meteor Measurements

NASA Astrophysics Data System (ADS)

Palo, Scott; Vaudrin, Cody

Defined by a minimal RF front-end followed by an analog-to-digital converter (ADC) and con-trolled by a reconfigurable logic device (FPGA), the digital receiver will replace conventional heterodyning analog receivers currently in use by the COBRA meteor radar. A basic hardware overview touches on the major digital receiver components, theory of operation and data han-dling strategies. We address concerns within the community regarding the implementation of digital receivers in small-scale scientific radars, and outline the numerous benefits with a focus on reconfigurability. From a remote sensing viewpoint, having complete visibility into a band of the EM spectrum allows an experiment designer to focus on parameter estimation rather than hardware limitations. Finally, we show some basic multistatic receiver configurations enabled through GPS time synchronization. Currently, the digital receiver is configured to facilitate range and radial velocity determination of meteors in the MLT region for use with the COBRA meteor radar. Initial measurements from data acquired at Platteville, Colorado and Tierra Del Fuego in Argentina will be presented. We show an improvement in detection rates compared to conventional analog systems. Scientific justification for a digital receiver is clearly made by the presentation of RTI plots created using data acquired from the receiver. These plots reveal an interesting phenomenon concerning vacillating power structures in a select number of meteor trails.

Digital item for digital human memory--television commerce application: family tree albuming system

NASA Astrophysics Data System (ADS)

Song, Jaeil; Lee, Hyejoo; Hong, JinWoo

2004-01-01

Technical advance in creating, storing digital media in daily life enables computers to capture human life and remember it as people do. A critical point with digitizing human life is how to recall bits of experience that are associated by semantic information. This paper proposes a technique for structuring dynamic digital object based on MPEG-21 Digital Item (DI) in order to recall human"s memory and providing interactive TV service on family tree albuming system as one of its applications. DIs are a dynamically reconfigurable, uniquely identified, described by a descriptor language, logical unit for structuring relationship among multiple media resources. Digital Item Processing (DIP) provides the means to interact with DIs to remind context to user, with active properties where objects have executable properties. Each user can adapt DIs" active properties to tailor the behavior of DIs to match his/her own specific needs. DIs" technologies in Intellectual Property Management and Protection (IPMP) can be used for privacy protection. In the interaction between the social space and technological space, the internal dynamics of family life fits well sharing family albuming service via family television. Family albuming service can act as virtual communities builders for family members. As memory is shared between family members, multiple annotations (including active properties on contextual information) will be made with snowballing value.

Comparison of Communication Architectures and Network Topologies for Distributed Propulsion Controls (Preprint)

DTIC Science & Technology

2013-05-01

logic to perform control function computations and are connected to the full authority digital engine control ( FADEC ) via a high-speed data...Digital Engine Control ( FADEC ) via a high speed data communication bus. The short term distributed engine control configu- rations will be core...concen- trator; and high temperature electronics, high speed communication bus between the data concentrator and the control law processor master FADEC

Microcomputer Control of a Hydraulically Actuated Piston.

DTIC Science & Technology

1987-06-01

EhhhohEohEmhhE EhhmhhhohhhhhI M1l *2 112.2 Ll 6 111111.258 MICROCOPY RESOLUfION TEST CHART NATIONAL BUREAUJ nF SIANDARDS 1963 A W* %i r f U V ~ S i V...SYSTE.M............................I( E. I REQUENCY RESPONSE TEST ........................... F. MODEL V.ALIDATION ................................. 2...O RITH M (BA SIC) ................................. 43 APPENDIX D: DIGITAL SYSTEM SIMULATION CODE (DSL) ........... 44 APPENDIX E: DIGITAL LOGIC TEST

Fully digital routing logic for single-photon avalanche diode arrays in highly efficient time-resolved imaging

NASA Astrophysics Data System (ADS)

Cominelli, Alessandro; Acconcia, Giulia; Ghioni, Massimo; Rech, Ivan

2018-03-01

Time-correlated single-photon counting (TCSPC) is a powerful optical technique, which permits recording fast luminous signals with picosecond precision. Unfortunately, given its repetitive nature, TCSPC is recognized as a relatively slow technique, especially when a large time-resolved image has to be recorded. In recent years, there has been a fast trend toward the development of TCPSC imagers. Unfortunately, present systems still suffer from a trade-off between number of channels and performance. Even worse, the overall measurement speed is still limited well below the saturation of the transfer bandwidth toward the external processor. We present a routing algorithm that enables a smart connection between a 32×32 detector array and five shared high-performance converters able to provide an overall conversion rate up to 10 Gbit/s. The proposed solution exploits a fully digital logic circuit distributed in a tree structure to limit the number and length of interconnections, which is a major issue in densely integrated circuits. The behavior of the logic has been validated by means of a field-programmable gate array, while a fully integrated prototype has been designed in 180-nm technology and analyzed by means of postlayout simulations.

Ultrafast all-optical arithmetic logic based on hydrogenated amorphous silicon microring resonators

NASA Astrophysics Data System (ADS)

Gostimirovic, Dusan; Ye, Winnie N.

2016-03-01

For decades, the semiconductor industry has been steadily shrinking transistor sizes to fit more performance into a single silicon-based integrated chip. This technology has become the driving force for advances in education, transportation, and health, among others. However, transistor sizes are quickly approaching their physical limits (channel lengths are now only a few silicon atoms in length), and Moore's law will likely soon be brought to a stand-still despite many unique attempts to keep it going (FinFETs, high-k dielectrics, etc.). This technology must then be pushed further by exploring (almost) entirely new methodologies. Given the explosive growth of optical-based long-haul telecommunications, we look to apply the use of high-speed optics as a substitute to the digital model; where slow, lossy, and noisy metal interconnections act as a major bottleneck to performance. We combine the (nonlinear) optical Kerr effect with a single add-drop microring resonator to perform the fundamental AND-XOR logical operations of a half adder, by all-optical means. This process is also applied to subtraction, higher-order addition, and the realization of an all-optical arithmetic logic unit (ALU). The rings use hydrogenated amorphous silicon as a material with superior nonlinear properties to crystalline silicon, while still maintaining CMOS-compatibility and the many benefits that come with it (low cost, ease of fabrication, etc.). Our method allows for multi-gigabit-per-second data rates while maintaining simplicity and spatial minimalism in design for high-capacity manufacturing potential.

Bio-logic analysis of injury biomarker patterns in human serum samples.

PubMed

Zhou, Jian; Halámek, Jan; Bocharova, Vera; Wang, Joseph; Katz, Evgeny

2011-01-15

Digital biosensor systems analyzing biomarkers characteristic of liver injury (LI), soft tissue injury (STI) and abdominal trauma (ABT) were developed and optimized for their performance in serum solutions spiked with injury biomarkers in order to mimic real medical samples. The systems produced 'Alert'-type optical output signals in the form of "YES-NO" separated by a threshold value. The new approach aims at the reliable detection of injury biomarkers for making autonomous decisions towards timely therapeutic interventions, particularly in conditions when a hospital treatment is not possible. The enzyme-catalyzed reactions performing Boolean AND/NAND logic operations in the presence of different combinations of the injury biomarkers allowed high-fidelity biosensing. Robustness of the systems was confirmed by their operation in serum solutions, representing the first example of chemically performed logic analysis of biological fluids and a step closer towards practical biomedical applications of enzyme-logic bioassays. Copyright © 2010 Elsevier B.V. All rights reserved.

Compact field programmable gate array-based pulse-sequencer and radio-frequency generator for experiments with trapped atoms.

PubMed

Pruttivarasin, Thaned; Katori, Hidetoshi

2015-11-01

We present a compact field-programmable gate array (FPGA) based pulse sequencer and radio-frequency (RF) generator suitable for experiments with cold trapped ions and atoms. The unit is capable of outputting a pulse sequence with at least 32 transistor-transistor logic (TTL) channels with a timing resolution of 40 ns and contains a built-in 100 MHz frequency counter for counting electrical pulses from a photo-multiplier tube. There are 16 independent direct-digital-synthesizers RF sources with fast (rise-time of ∼60 ns) amplitude switching and sub-mHz frequency tuning from 0 to 800 MHz.

Nanoelectronic programmable synapses based on phase change materials for brain-inspired computing.

PubMed

Kuzum, Duygu; Jeyasingh, Rakesh G D; Lee, Byoungil; Wong, H-S Philip

2012-05-09

Brain-inspired computing is an emerging field, which aims to extend the capabilities of information technology beyond digital logic. A compact nanoscale device, emulating biological synapses, is needed as the building block for brain-like computational systems. Here, we report a new nanoscale electronic synapse based on technologically mature phase change materials employed in optical data storage and nonvolatile memory applications. We utilize continuous resistance transitions in phase change materials to mimic the analog nature of biological synapses, enabling the implementation of a synaptic learning rule. We demonstrate different forms of spike-timing-dependent plasticity using the same nanoscale synapse with picojoule level energy consumption.

Compact field programmable gate array-based pulse-sequencer and radio-frequency generator for experiments with trapped atoms

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pruttivarasin, Thaned, E-mail: thaned.pruttivarasin@riken.jp; Katori, Hidetoshi; Innovative Space-Time Project, ERATO, JST, Bunkyo-ku, Tokyo 113-8656

We present a compact field-programmable gate array (FPGA) based pulse sequencer and radio-frequency (RF) generator suitable for experiments with cold trapped ions and atoms. The unit is capable of outputting a pulse sequence with at least 32 transistor-transistor logic (TTL) channels with a timing resolution of 40 ns and contains a built-in 100 MHz frequency counter for counting electrical pulses from a photo-multiplier tube. There are 16 independent direct-digital-synthesizers RF sources with fast (rise-time of ∼60 ns) amplitude switching and sub-mHz frequency tuning from 0 to 800 MHz.

Design and implementation of projects with Xilinx Zynq FPGA: a practical case

NASA Astrophysics Data System (ADS)

Travaglini, R.; D'Antone, I.; Meneghini, S.; Rignanese, L.; Zuffa, M.

The main advantage when using FPGAs with embedded processors is the availability of additional several high-performance resources in the same physical device. Moreover, the FPGA programmability allows for connect custom peripherals. Xilinx have designed a programmable device named Zynq-7000 (simply called Zynq in the following), which integrates programmable logic (identical to the other Xilinx "serie 7" devices) with a System on Chip (SOC) based on two embedded ARM processors. Since both parts are deeply connected, the designers benefit from performance of hardware SOC and flexibility of programmability as well. In this paper a design developed by the Electronic Design Department at the Bologna Division of INFN will be presented as a practical case of project based on Zynq device. It is developed by using a commercial board called ZedBoard hosting a FMC mezzanine with a 12-bit 500 MS/s ADC. The Zynq FPGA on the ZedBoard receives digital outputs from the ADC and send them to the acquisition PC, after proper formatting, through a Gigabit Ethernet link. The major focus of the paper will be about the methodology to develop a Zynq-based design with the Xilinx Vivado software, enlightening how to configure the SOC and connect it with the programmable logic. Firmware design techniques will be presented: in particular both VHDL and IP core based strategies will be discussed. Further, the procedure to develop software for the embedded processor will be presented. Finally, some debugging tools, like the embedded Logic Analyzer, will be shown. Advantages and disadvantages with respect to adopting FPGA without embedded processors will be discussed.

The evolvability of programmable hardware.

PubMed

Raman, Karthik; Wagner, Andreas

2011-02-06

In biological systems, individual phenotypes are typically adopted by multiple genotypes. Examples include protein structure phenotypes, where each structure can be adopted by a myriad individual amino acid sequence genotypes. These genotypes form vast connected 'neutral networks' in genotype space. The size of such neutral networks endows biological systems not only with robustness to genetic change, but also with the ability to evolve a vast number of novel phenotypes that occur near any one neutral network. Whether technological systems can be designed to have similar properties is poorly understood. Here we ask this question for a class of programmable electronic circuits that compute digital logic functions. The functional flexibility of such circuits is important in many applications, including applications of evolutionary principles to circuit design. The functions they compute are at the heart of all digital computation. We explore a vast space of 10(45) logic circuits ('genotypes') and 10(19) logic functions ('phenotypes'). We demonstrate that circuits that compute the same logic function are connected in large neutral networks that span circuit space. Their robustness or fault-tolerance varies very widely. The vicinity of each neutral network contains circuits with a broad range of novel functions. Two circuits computing different functions can usually be converted into one another via few changes in their architecture. These observations show that properties important for the evolvability of biological systems exist in a commercially important class of electronic circuitry. They also point to generic ways to generate fault-tolerant, adaptable and evolvable electronic circuitry.

The evolvability of programmable hardware

PubMed Central

Raman, Karthik; Wagner, Andreas

2011-01-01

In biological systems, individual phenotypes are typically adopted by multiple genotypes. Examples include protein structure phenotypes, where each structure can be adopted by a myriad individual amino acid sequence genotypes. These genotypes form vast connected ‘neutral networks’ in genotype space. The size of such neutral networks endows biological systems not only with robustness to genetic change, but also with the ability to evolve a vast number of novel phenotypes that occur near any one neutral network. Whether technological systems can be designed to have similar properties is poorly understood. Here we ask this question for a class of programmable electronic circuits that compute digital logic functions. The functional flexibility of such circuits is important in many applications, including applications of evolutionary principles to circuit design. The functions they compute are at the heart of all digital computation. We explore a vast space of 1045 logic circuits (‘genotypes’) and 1019 logic functions (‘phenotypes’). We demonstrate that circuits that compute the same logic function are connected in large neutral networks that span circuit space. Their robustness or fault-tolerance varies very widely. The vicinity of each neutral network contains circuits with a broad range of novel functions. Two circuits computing different functions can usually be converted into one another via few changes in their architecture. These observations show that properties important for the evolvability of biological systems exist in a commercially important class of electronic circuitry. They also point to generic ways to generate fault-tolerant, adaptable and evolvable electronic circuitry. PMID:20534598

Biofabricated film with enzymatic and redox-capacitor functionalities to harvest and store electrons.

PubMed

Liba, Benjamin D; Kim, Eunkyoung; Martin, Alexandra N; Liu, Yi; Bentley, William E; Payne, Gregory F

2013-03-01

Exciting opportunities in bioelectronics will be facilitated by materials that can bridge the chemical logic of biology and the digital logic of electronics. Here we report the fabrication of a dual functional hydrogel film that can harvest electrons from its chemical environment and store these electrons by switching the film's redox-state. The hydrogel scaffold was formed by the anodic deposition of the aminopolysaccharide chitosan. Electron-harvesting function was conferred by co-depositing the enzyme glucose dehydrogenase (GDH) with chitosan. GDH catalyzes the transfer of electrons from glucose to the soluble redox-shuttle NADP(+). Electron-storage function was conferred by the redox-active food phenolic chlorogenic acid (CA) that was enzymatically grafted to the chitosan scaffold using tyrosinase. The grafted CA undergoes redox-cycling reactions with NADPH resulting in the net transfer of electrons to the film where they are stored in the reduced state of CA. The individual and dual functionalities of these films were demonstrated experimentally. There are three general conclusions from this proof-of-concept study. First, enzymatically-grafted catecholic moieties confer redox-capacitor function to the chitosan scaffold. Second, biological materials (i.e. chitosan and CA) and mechanisms (i.e. tyrosinase-mediated grafting) allow the reagentless fabrication of functional films that should be environmentally-friendly, safe and potentially even edible. Finally, the film's ability to mediate the transfer of electrons from a biological metabolite to an electrode suggests an approach to bridge the chemical logic of biology with the digital logic of electronics.

Using software simulators to enhance the learning of digital logic design for the information technology students

NASA Astrophysics Data System (ADS)

Alsadoon, Abeer; Prasad, P. W. C.; Beg, Azam

2017-09-01

Making the students understand the theoretical concepts of digital logic design concepts is one of the major issues faced by the academics, therefore the teachers have tried different techniques to link the theoretical information to the practical knowledge. Use of software simulations is a technique for learning and practice that can be applied to many different disciplines. Experimentation of different computer hardware components/integrated circuits with the use of the simulators enhances the student learning. The simulators can be rather simplistic or quite complex. This paper reports our evaluation of different simulators available for use in the higher education institutions. We also provide the experience of incorporating some selected tools in teaching introductory courses in computer systems. We justified the effectiveness of incorporating the simulators into the computer system courses by use of student survey and final grade results.

A description of the thruster attitude control simulation and its application to the HEAO-C study

NASA Technical Reports Server (NTRS)

Brandon, L. B.

1971-01-01

During the design and evaluation of a reaction control system (RCS), it is desirable to have a digital computer program simulating vehicle dynamics, disturbance torques, control torques, and RCS logic. The thruster attitude control simulation (TACS) is just such a computer program. The TACS is a relatively sophisticated digital computer program that includes all the major parameters involved in the attitude control of a vehicle using an RCS for control. It includes the effects of gravity gradient torques and HEAO-C aerodynamic torques so that realistic runs can be made in the areas of fuel consumption and engine actuation rates. Also, the program is general enough that any engine configuration and logic scheme can be implemented in a reasonable amount of time. The results of the application of the TACS in the HEAO-C study are included.

The GANDALF 128-Channel Time-to-Digital Converter

NASA Astrophysics Data System (ADS)

Büchele, M.; Fischer, H.; Herrmann, F.; Königsmann, K.; Schill, C.; Schopferer, S.

The GANDALF 6U-VME64x/VXS module has been designed to cope with a variety of readout tasks in high energy and nuclear physics experiments, in particular the COMPASS experiment at CERN. The exchangeable mezzanine cards allow for an employment of the system in very different applications such as analog-to-digital or time-to-digital conversions, coincidence matrix formation, fast pattern recognition or fast trigger generation. Based on this platform, we present a 128-channel TDC which is implemented in a single Xilinx Virtex-5 FPGA using a shifted clock sampling method. In this concept each input signal is continuously sampled by 16 flip-flops using equidistant phase-shifted clocks. Compared to previous FPGA designs, usually based on delay lines and comprising few TDC channels with resolutions in the order of 10 ps, our design permits the implementation of a large number of TDC channels with a resolution of 64 ps in a single FPGA. Predictable placement of logic components and uniform routing inside the FPGA fabric is a particular challenge of this design. We present measurement results for the time resolution and the nonlinearity of the TDC readout system.

Report from a Multi-Institutional Randomized Clinical Trial Examining Computer-Assisted Problem-Solving Skills Training for English- and Spanish-Speaking Mothers of Children with Newly Diagnosed Cancer

PubMed Central

Sahler, Olle Jane Z.; Sherman, Sandra A.; Fairclough, Diane L.; Butler, Robert W.; Katz, Ernest R.; Dolgin, Michael J.; Varni, James W.; Noll, Robert B.; Phipps, Sean

2009-01-01

Objectives To evaluate the feasibility and efficacy of a handheld personal digital assistant (PDA)-based supplement for maternal Problem-Solving Skills Training (PSST) and to explore Spanish-speaking mothers’ experiences with it. Methods Mothers (n = 197) of children with newly diagnosed cancer were randomized to traditional PSST or PSST + PDA 8-week programs. Participants completed the Social Problem-Solving Inventory-Revised, Beck Depression Inventory-II, Profile of Mood States, and Impact of Event Scale-Revised pre-, post-treatment, and 3 months after completion of the intervention. Mothers also rated optimism, logic, and confidence in the intervention and technology. Results Both groups demonstrated significant positive change over time on all psychosocial measures. No between-group differences emerged. Despite technological “glitches,” mothers expressed moderately high optimism, appreciation for logic, and confidence in both interventions and rated the PDA-based program favorably. Technology appealed to all Spanish-speaking mothers, with younger mothers showing greater proficiency. Conclusions Well-designed, supported technology holds promise for enhancing psychological interventions. PMID:19091804

HYTESS 2: A Hypothetical Turbofan Engine Simplified Simulation with multivariable control and sensor analytical redundancy

NASA Technical Reports Server (NTRS)

Merrill, W. C.

1986-01-01

A hypothetical turbofan engine simplified simulation with a multivariable control and sensor failure detection, isolation, and accommodation logic (HYTESS II) is presented. The digital program, written in FORTRAN, is self-contained, efficient, realistic and easily used. Simulated engine dynamics were developed from linearized operating point models. However, essential nonlinear effects are retained. The simulation is representative of the hypothetical, low bypass ratio turbofan engine with an advanced control and failure detection logic. Included is a description of the engine dynamics, the control algorithm, and the sensor failure detection logic. Details of the simulation including block diagrams, variable descriptions, common block definitions, subroutine descriptions, and input requirements are given. Example simulation results are also presented.

Fundamentals handbook of electrical and computer engineering. Volume 1 Circuits fields and electronics

NASA Astrophysics Data System (ADS)

Chang, S. S. L.

State of the art technology in circuits, fields, and electronics is discussed. The principles and applications of these technologies to industry, digital processing, microwave semiconductors, and computer-aided design are explained. Important concepts and methodologies in mathematics and physics are reviewed, and basic engineering sciences and associated design methods are dealt with, including: circuit theory and the design of magnetic circuits and active filter synthesis; digital signal processing, including FIR and IIR digital filter design; transmission lines, electromagnetic wave propagation and surface acoustic wave devices. Also considered are: electronics technologies, including power electronics, microwave semiconductors, GaAs devices, and magnetic bubble memories; digital circuits and logic design.

All-digital GPS receiver mechanization

NASA Astrophysics Data System (ADS)

Ould, P. C.; van Wechel, R. J.

The paper describes the all-digital baseband correlation processing of GPS signals, which is characterized by (1) a potential for improved antijamming performance, (2) fast acquisition by a digital matched filter, (3) reduction of adjustment, (4) increased system reliability, and (5) provision of a basis for the realization of a high degree of VLSI potential for the development of small economical GPS sets. The basic technical approach consists of a broadband fix-tuned RF converter followed by a digitizer; digital-matched-filter acquisition section; phase- and delay-lock tracking via baseband digital correlation; software acquisition logic and loop filter implementation; and all-digital implementation of the feedback numerical controlled oscillators and code generator. Broadband in-phase and quadrature tracking is performed by an arctangent angle detector followed by a phase-unwrapping algorithm that eliminates false locks induced by sampling and data bit transitions, and yields a wide pull-in frequency range approaching one-fourth of the loop iteration frequency.

The research of laser marking control technology

NASA Astrophysics Data System (ADS)

Zhang, Qiue; Zhang, Rong

2009-08-01

In the area of Laser marking, the general control method is insert control card to computer's mother board, it can not support hot swap, it is difficult to assemble or it. Moreover, the one marking system must to equip one computer. In the system marking, the computer can not to do the other things except to transmit marking digital information. Otherwise it can affect marking precision. Based on traditional control methods existed some problems, introduced marking graphic editing and digital processing by the computer finish, high-speed digital signal processor (DSP) control marking the whole process. The laser marking controller is mainly contain DSP2812, digital memorizer, DAC (digital analog converting) transform unit circuit, USB interface control circuit, man-machine interface circuit, and other logic control circuit. Download the marking information which is processed by computer to U disk, DSP read the information by USB interface on time, then processing it, adopt the DSP inter timer control the marking time sequence, output the scanner control signal by D/A parts. Apply the technology can realize marking offline, thereby reduce the product cost, increase the product efficiency. The system have good effect in actual unit markings, the marking speed is more quickly than PCI control card to 20 percent. It has application value in practicality.

The design of digital-adaptive controllers for VTOL aircraft

NASA Technical Reports Server (NTRS)

Stengel, R. F.; Broussard, J. R.; Berry, P. W.

1976-01-01

Design procedures for VTOL automatic control systems have been developed and are presented. Using linear-optimal estimation and control techniques as a starting point, digital-adaptive control laws have been designed for the VALT Research Aircraft, a tandem-rotor helicopter which is equipped for fully automatic flight in terminal area operations. These control laws are designed to interface with velocity-command and attitude-command guidance logic, which could be used in short-haul VTOL operations. Developments reported here include new algorithms for designing non-zero-set-point digital regulators, design procedures for rate-limited systems, and algorithms for dynamic control trim setting.

Fault detection and accommodation testing on an F100 engine in an F-15 airplane. [digital engine control system

NASA Technical Reports Server (NTRS)

Myers, L. P.; Baer-Riedhart, J. L.; Maxwell, M. D.

1985-01-01

The fault detection and accommodation (FDA) methods that can be used for digital engine control systems are presently subjected to a flight test program in the case of the F-15 fighter's F100 engine electronic controls, inducing selected faults and then evaluating the resulting digital engine control responses. In general, flight test results were found to compare well with both ground tests and predictions. It is noted that the inducement of dual-pressure failures was not feasible, since FDA logic was not designed to accommodate them.

Research on NC motion controller based on SOPC technology

NASA Astrophysics Data System (ADS)

Jiang, Tingbiao; Meng, Biao

2006-11-01

With the rapid development of the digitization and informationization, the application of numerical control technology in the manufacturing industry becomes more and more important. However, the conventional numerical control system usually has some shortcomings such as the poor in system openness, character of real-time, cutability and reconfiguration. In order to solve these problems, this paper investigates the development prospect and advantage of the application in numerical control area with system-on-a-Programmable-Chip (SOPC) technology, and puts forward to a research program approach to the NC controller based on SOPC technology. Utilizing the characteristic of SOPC technology, we integrate high density logic device FPGA, memory SRAM, and embedded processor ARM into a single programmable logic device. We also combine the 32-bit RISC processor with high computing capability of the complicated algorithm with the FPGA device with strong motivable reconfiguration logic control ability. With these steps, we can greatly resolve the defect described in above existing numerical control systems. For the concrete implementation method, we use FPGA chip embedded with ARM hard nuclear processor to construct the control core of the motion controller. We also design the peripheral circuit of the controller according to the requirements of actual control functions, transplant real-time operating system into ARM, design the driver of the peripheral assisted chip, develop the application program to control and configuration of FPGA, design IP core of logic algorithm for various NC motion control to configured it into FPGA. The whole control system uses the concept of modular and structured design to develop hardware and software system. Thus the NC motion controller with the advantage of easily tailoring, highly opening, reconfigurable, and expandable can be implemented.

Development of ADOCS controllers and control laws. Volume 3: Simulation results and recommendations

NASA Technical Reports Server (NTRS)

Landis, Kenneth H.; Glusman, Steven I.

1985-01-01

The Advanced Cockpit Controls/Advanced Flight Control System (ACC/AFCS) study was conducted by the Boeing Vertol Company as part of the Army's Advanced Digital/Optical Control System (ADOCS) program. Specifically, the ACC/AFCS investigation was aimed at developing the flight control laws for the ADOCS demonstator aircraft which will provide satisfactory handling qualities for an attack helicopter mission. The three major elements of design considered are as follows: Pilot's integrated Side-Stick Controller (SSC) -- Number of axes controlled; force/displacement characteristics; ergonomic design. Stability and Control Augmentation System (SCAS)--Digital flight control laws for the various mission phases; SCAS mode switching logic. Pilot's Displays--For night/adverse weather conditions, the dynamics of the superimposed symbology presented to the pilot in a format similar to the Advanced Attack Helicopter (AAH) Pilot Night Vision System (PNVS) for each mission phase is a function of SCAS characteristics; display mode switching logic. Results of the five piloted simulations conducted at the Boeing Vertol and NASA-Ames simulation facilities are presented in Volume 3. Conclusions drawn from analysis of pilot rating data and commentary were used to formulate recommendations for the ADOCS demonstrator flight control system design. The ACC/AFCS simulation data also provide an extensive data base to aid the development of advanced flight control system design for future V/STOL aircraft.

A Subthreshold Digital Library Using a Dynamic-Threshold Metal-Oxide Semiconductor (DTMOS) and Transmission Gate Logic

DTIC Science & Technology

2014-09-01

electrocardiography (ECG), electromyography (EMG), and electroencephalography (EEG) applications that operate using thermoelectrically generated energy...semiconductor ECG electrocardiography EEG electroencephalography EMG electromyography FY15 fiscal year 2015 IC integrated circuit MOSFETs

Pulse stretcher for narrow pulses

NASA Technical Reports Server (NTRS)

Lindsey, R. S., Jr. (Inventor)

1974-01-01

A pulse stretcher for narrow pulses is presented. The stretcher is composed of an analog section for processing each arriving analog pulse and a digital section with logic for providing command signals to the gates and switches in the analog section.

Polynomial-time solution of prime factorization and NP-complete problems with digital memcomputing machines

NASA Astrophysics Data System (ADS)

Traversa, Fabio L.; Di Ventra, Massimiliano

2017-02-01

We introduce a class of digital machines, we name Digital Memcomputing Machines, (DMMs) able to solve a wide range of problems including Non-deterministic Polynomial (NP) ones with polynomial resources (in time, space, and energy). An abstract DMM with this power must satisfy a set of compatible mathematical constraints underlying its practical realization. We prove this by making a connection with the dynamical systems theory. This leads us to a set of physical constraints for poly-resource resolvability. Once the mathematical requirements have been assessed, we propose a practical scheme to solve the above class of problems based on the novel concept of self-organizing logic gates and circuits (SOLCs). These are logic gates and circuits able to accept input signals from any terminal, without distinction between conventional input and output terminals. They can solve boolean problems by self-organizing into their solution. They can be fabricated either with circuit elements with memory (such as memristors) and/or standard MOS technology. Using tools of functional analysis, we prove mathematically the following constraints for the poly-resource resolvability: (i) SOLCs possess a global attractor; (ii) their only equilibrium points are the solutions of the problems to solve; (iii) the system converges exponentially fast to the solutions; (iv) the equilibrium convergence rate scales at most polynomially with input size. We finally provide arguments that periodic orbits and strange attractors cannot coexist with equilibria. As examples, we show how to solve the prime factorization and the search version of the NP-complete subset-sum problem. Since DMMs map integers into integers, they are robust against noise and hence scalable. We finally discuss the implications of the DMM realization through SOLCs to the NP = P question related to constraints of poly-resources resolvability.

Correction And Use Of Jitter In Television Images

NASA Technical Reports Server (NTRS)

Diner, Daniel B.; Fender, Derek H.; Fender, Antony R. H.

1989-01-01

Proposed system stabilizes jittering television image and/or measures jitter to extract information on motions of objects in image. Alternative version, system controls lateral motion on camera to generate stereoscopic views to measure distances to objects. In another version, motion of camera controlled to keep object in view. Heart of system is digital image-data processor called "jitter-miser", which includes frame buffer and logic circuits to correct for jitter in image. Signals from motion sensors on camera sent to logic circuits and processed into corrections for motion along and across line of sight.

Static Characteristics of the Ferroelectric Transistor Inverter

NASA Technical Reports Server (NTRS)

Mitchell, Cody; Laws, crystal; MacLeond, Todd C.; Ho, Fat D.

2010-01-01

The inverter is one of the most fundamental building blocks of digital logic, and it can be used as the foundation for understanding more complex logic gates and circuits. This paper presents the characteristics of an inverter circuit using a ferroelectric field-effect transistor. The voltage transfer characteristics are analyzed with respect to varying parameters such as supply voltage, input voltage, and load resistance. The effects of the ferroelectric layer between the gate and semiconductor are examined, and comparisons are made between the inverters using ferroelectric transistors and those using traditional MOSFETs.

Scalable printed electronics: an organic decoder addressing ferroelectric non-volatile memory.

PubMed

Ng, Tse Nga; Schwartz, David E; Lavery, Leah L; Whiting, Gregory L; Russo, Beverly; Krusor, Brent; Veres, Janos; Bröms, Per; Herlogsson, Lars; Alam, Naveed; Hagel, Olle; Nilsson, Jakob; Karlsson, Christer

2012-01-01

Scalable circuits of organic logic and memory are realized using all-additive printing processes. A 3-bit organic complementary decoder is fabricated and used to read and write non-volatile, rewritable ferroelectric memory. The decoder-memory array is patterned by inkjet and gravure printing on flexible plastics. Simulation models for the organic transistors are developed, enabling circuit designs tolerant of the variations in printed devices. We explain the key design rules in fabrication of complex printed circuits and elucidate the performance requirements of materials and devices for reliable organic digital logic.

NASA Lewis F100 engine testing

NASA Technical Reports Server (NTRS)

Werner, R. A.; Willoh, R. G., Jr.; Abdelwahab, M.

1984-01-01

Two builds of an F100 engine model derivative (EMD) engine were evaluated for improvements in engine components and digital electronic engine control (DEEC) logic. Two DEEC flight logics were verified throughout the flight envelope in support of flight clearance for the F100 engine model derivative program (EMPD). A nozzle instability and a faster augmentor transient capability was investigated in support of the F-15 DEEC flight program. Off schedule coupled system mode fan flutter, DEEC nose-boom pressure correlation, DEEC station six pressure comparison, and a new fan inlet variable vane (CIVV) schedule are identified.

Three-Function Logic Gate Controlled by Analog Voltage

NASA Technical Reports Server (NTRS)

Zebulum, Ricardo; Stoica, Adrian

2006-01-01

The figure is a schematic diagram of a complementary metal oxide/semiconductor (CMOS) electronic circuit that performs one of three different logic functions, depending on the level of an externally applied control voltage, V(sub sel). Specifically, the circuit acts as A NAND gate at V(sub sel) = 0.0 V, A wire (the output equals one of the inputs) at V(sub sel) = 1.0 V, or An AND gate at V(sub sel) = -1.8 V. [The nominal power-supply potential (VDD) and logic "1" potential of this circuit is 1.8 V.] Like other multifunctional circuits described in several prior NASA Tech Briefs articles, this circuit was synthesized following an automated evolutionary approach that is so named because it is modeled partly after the repetitive trial-and-error process of biological evolution. An evolved circuit can be tested by computational simulation and/or tested in real hardware, and the results of the test can provide guidance for refining the design through further iteration. The evolutionary synthesis of electronic circuits can now be implemented by means of a software package Genetic Algorithms for Circuit Synthesis (GACS) that was developed specifically for this purpose. GACS was used to synthesize the present trifunctional circuit. As in the cases of other multifunctional circuits described in several prior NASA Tech Briefs articles, the multiple functionality of this circuit, the use of a single control voltage to select the function, and the automated evolutionary approach to synthesis all contribute synergistically to a combination of features that are potentially advantageous for the further development of robust, multiple-function logic circuits, including, especially, field-programmable gate arrays (FPGAs). These advantages include the following: This circuit contains only 9 transistors about half the number of transistors that would be needed to obtain equivalent NAND/wire/AND functionality by use of components from a standard digital design library. If multifunctional gates like this circuit were used in the place of the configurable logic blocks of present commercial FPGAs, it would be possible to change the functions of the resulting digital systems within shorter times. For example, by changing a single control voltage, one could change the function of thousands of FPGA cells within nanoseconds. In contrast, typically, the reconfiguration in a conventional FPGA by use of bits downloaded from look-up tables via a digital bus takes microseconds.

Brain training for silver gamers: effects of age and game form on effectiveness, efficiency, self-assessment, and gameplay experience.

PubMed

Nacke, Lennart E; Nacke, Anne; Lindley, Craig A

2009-10-01

In recent years, an aging demographic majority in the Western world has come to the attention of the game industry. The recently released "brain-training" games target this population, and research investigating gameplay experience of the elderly using this game form is lacking. This study employs a 2 x 2 mixed factorial design (age group: young and old x game form: paper and Nintendo DS) to investigate effects of age and game form on usability, self-assessment, and gameplay experience in a supervised field study. Effectiveness was evaluated in task completion time, efficiency as error rate, together with self-assessment measures (arousal, pleasure, dominance) and game experience (challenge, flow, competence, tension, positive and negative affect). Results indicate players, regardless of age, are more effective and efficient using pen-and-paper than using a Nintendo DS console. However, the game is more arousing and induces a heightened sense of flow in digital form for gamers of all ages. Logic problem-solving challenges within digital games may be associated with positive feelings for the elderly but with negative feelings for the young. Thus, digital logic-training games may provide positive gameplay experience for an aging Western civilization.

Digital Synchronizer without Metastability

NASA Technical Reports Server (NTRS)

Simle, Robert M.; Cavazos, Jose A.

2009-01-01

A proposed design for a digital synchronizing circuit would eliminate metastability that plagues flip-flop circuits in digital input/output interfaces. This metastability is associated with sampling, by use of flip-flops, of an external signal that is asynchronous with a clock signal that drives the flip-flops: it is a temporary flip-flop failure that can occur when a rising or falling edge of an asynchronous signal occurs during the setup and/or hold time of a flip-flop. The proposed design calls for (1) use of a clock frequency greater than the frequency of the asynchronous signal, (2) use of flip-flop asynchronous preset or clear signals for the asynchronous input, (3) use of a clock asynchronous recovery delay with pulse width discriminator, and (4) tying the data inputs to constant logic levels to obtain (5) two half-rate synchronous partial signals - one for the falling and one for the rising edge. Inasmuch as the flip-flop data inputs would be permanently tied to constant logic levels, setup and hold times would not be violated. The half-rate partial signals would be recombined to construct a signal that would replicate the original asynchronous signal at its original rate but would be synchronous with the clock signal.

Design of transient light signal simulator based on FPGA

NASA Astrophysics Data System (ADS)

Kang, Jing; Chen, Rong-li; Wang, Hong

2014-11-01

A design scheme of transient light signal simulator based on Field Programmable gate Array (FPGA) was proposed in this paper. Based on the characteristics of transient light signals and measured feature points of optical intensity signals, a fitted curve was created in MATLAB. And then the wave data was stored in a programmed memory chip AT29C1024 by using SUPERPRO programmer. The control logic was realized inside one EP3C16 FPGA chip. Data readout, data stream cache and a constant current buck regulator for powering high-brightness LEDs were all controlled by FPGA. A 12-Bit multiplying CMOS digital-to-analog converter (DAC) DAC7545 and an amplifier OPA277 were used to convert digital signals to voltage signals. A voltage-controlled current source constituted by a NPN transistor and an operational amplifier controlled LED array diming to achieve simulation of transient light signal. LM3405A, 1A Constant Current Buck Regulator for Powering LEDs, was used to simulate strong background signal in space. Experimental results showed that the scheme as a transient light signal simulator can satisfy the requests of the design stably.

Short circuit protection for a power distribution system

NASA Technical Reports Server (NTRS)

Owen, J. R., III

1969-01-01

Sensing circuit detects when the output from a matrix is present and when it should be present. The circuit provides short circuit protection for a power distribution system where the selection of the driven load is accomplished by digital logic.

Maximizing Accessibility to Spatially Referenced Digital Data.

ERIC Educational Resources Information Center

Hunt, Li; Joselyn, Mark

1995-01-01

Discusses some widely available spatially referenced datasets, including raster and vector datasets. Strategies for improving accessibility include: acquisition of data in a software-dependent format; reorganization of data into logical geographic units; acquisition of intelligent retrieval software; improving computer hardware; and intelligent…

QCAPUF: QCA-based physically unclonable function as a hardware security primitive

NASA Astrophysics Data System (ADS)

Abutaleb, M. M.

2018-04-01

Physically unclonable functions (PUFs) are increasingly used as innovative security primitives to provide the hardware authentication and identification as well as the secret key generation based on unique and random variations in identically fabricated devices. Security and low power have appeared to become two crucial necessities to modern designs. As an emerging nanoelectronic technology, a quantum-dot cellular automata (QCA) can achieve ultra-low power consumption as well as an extremely small area for implementing digital designs. However, there are various classes of permanent defects that can happen during the manufacture of QCA devices. The recent extensive research has been focused on how to eliminate errors in QCA structures resulting from fabrication variances. By a completely different vision, to turn this disadvantage into an advantage, this paper presents a novel QCA-based PUF (QCAPUF) architecture to exploit the unique physical characteristics of fabricated QCA cells in order to produce different hardware fingerprint instances. This architecture is composed of proposed logic and interconnect blocks that have critical vulnerabilities and perform unexpected logical operations. The behaviour of QCAPUF is thoroughly analysed through physical relations and simulations. Results confirm that the proposed QCAPUF has state of the art PUF characteristics in the QCA technology. This paper will serve as a basis for further research into QCA-based hardware security primitives and applications.

Concordance Rate for the Identification of Distant Entrance Gunshot Wounds of the Back by Experienced Forensic Pathologists Examining Only Images of Autopsies.

PubMed

Heninger, Michael

2016-03-01

The images of 66 gunshot entrance wounds with a defect on the back, a bullet in the body, hemorrhage along the wound track, and logical certainty that it was an entrance wound were collected from the files of a moderately busy medical examiner's office. Participants numbering 22 board-certified forensic pathologists viewed a single digital archival image of each of the 66 entrance wounds randomly mixed with 74 presumptive exit wounds to determine whether they were entrance or exit wounds. The concordance rate for correctly identifying the 66 logically known entrance wounds was 82.8% with a range from 58% to 97%. This pilot study was conducted to provide an evidence-based approach to the interpretation of the direction of gunshot wounds by reviewing pathologists with access only to archival photographs, and it is not a measure of the accuracy to distinguish entrance from exit wounds when given all of the circumstances. © 2016 American Academy of Forensic Sciences.

Multistate Memristive Tantalum Oxide Devices for Ternary Arithmetic

PubMed Central

Kim, Wonjoo; Chattopadhyay, Anupam; Siemon, Anne; Linn, Eike; Waser, Rainer; Rana, Vikas

2016-01-01

Redox-based resistive switching random access memory (ReRAM) offers excellent properties to implement future non-volatile memory arrays. Recently, the capability of two-state ReRAMs to implement Boolean logic functionality gained wide interest. Here, we report on seven-states Tantalum Oxide Devices, which enable the realization of an intrinsic modular arithmetic using a ternary number system. Modular arithmetic, a fundamental system for operating on numbers within the limit of a modulus, is known to mathematicians since the days of Euclid and finds applications in diverse areas ranging from e-commerce to musical notations. We demonstrate that multistate devices not only reduce the storage area consumption drastically, but also enable novel in-memory operations, such as computing using high-radix number systems, which could not be implemented using two-state devices. The use of high radix number system reduces the computational complexity by reducing the number of needed digits. Thus the number of calculation operations in an addition and the number of logic devices can be reduced. PMID:27834352

Automated Software Acceleration in Programmable Logic for an Efficient NFFT Algorithm Implementation: A Case Study.

PubMed

Rodríguez, Manuel; Magdaleno, Eduardo; Pérez, Fernando; García, Cristhian

2017-03-28

Non-equispaced Fast Fourier transform (NFFT) is a very important algorithm in several technological and scientific areas such as synthetic aperture radar, computational photography, medical imaging, telecommunications, seismic analysis and so on. However, its computation complexity is high. In this paper, we describe an efficient NFFT implementation with a hardware coprocessor using an All-Programmable System-on-Chip (APSoC). This is a hybrid device that employs an Advanced RISC Machine (ARM) as Processing System with Programmable Logic for high-performance digital signal processing through parallelism and pipeline techniques. The algorithm has been coded in C language with pragma directives to optimize the architecture of the system. We have used the very novel Software Develop System-on-Chip (SDSoC) evelopment tool that simplifies the interface and partitioning between hardware and software. This provides shorter development cycles and iterative improvements by exploring several architectures of the global system. The computational results shows that hardware acceleration significantly outperformed the software based implementation.

Automated Software Acceleration in Programmable Logic for an Efficient NFFT Algorithm Implementation: A Case Study

PubMed Central

Rodríguez, Manuel; Magdaleno, Eduardo; Pérez, Fernando; García, Cristhian

2017-01-01

Non-equispaced Fast Fourier transform (NFFT) is a very important algorithm in several technological and scientific areas such as synthetic aperture radar, computational photography, medical imaging, telecommunications, seismic analysis and so on. However, its computation complexity is high. In this paper, we describe an efficient NFFT implementation with a hardware coprocessor using an All-Programmable System-on-Chip (APSoC). This is a hybrid device that employs an Advanced RISC Machine (ARM) as Processing System with Programmable Logic for high-performance digital signal processing through parallelism and pipeline techniques. The algorithm has been coded in C language with pragma directives to optimize the architecture of the system. We have used the very novel Software Develop System-on-Chip (SDSoC) evelopment tool that simplifies the interface and partitioning between hardware and software. This provides shorter development cycles and iterative improvements by exploring several architectures of the global system. The computational results shows that hardware acceleration significantly outperformed the software based implementation. PMID:28350358

Multistate Memristive Tantalum Oxide Devices for Ternary Arithmetic.

PubMed

Kim, Wonjoo; Chattopadhyay, Anupam; Siemon, Anne; Linn, Eike; Waser, Rainer; Rana, Vikas

2016-11-11

Redox-based resistive switching random access memory (ReRAM) offers excellent properties to implement future non-volatile memory arrays. Recently, the capability of two-state ReRAMs to implement Boolean logic functionality gained wide interest. Here, we report on seven-states Tantalum Oxide Devices, which enable the realization of an intrinsic modular arithmetic using a ternary number system. Modular arithmetic, a fundamental system for operating on numbers within the limit of a modulus, is known to mathematicians since the days of Euclid and finds applications in diverse areas ranging from e-commerce to musical notations. We demonstrate that multistate devices not only reduce the storage area consumption drastically, but also enable novel in-memory operations, such as computing using high-radix number systems, which could not be implemented using two-state devices. The use of high radix number system reduces the computational complexity by reducing the number of needed digits. Thus the number of calculation operations in an addition and the number of logic devices can be reduced.

Multistate Memristive Tantalum Oxide Devices for Ternary Arithmetic

NASA Astrophysics Data System (ADS)

Kim, Wonjoo; Chattopadhyay, Anupam; Siemon, Anne; Linn, Eike; Waser, Rainer; Rana, Vikas

2016-11-01

Redox-based resistive switching random access memory (ReRAM) offers excellent properties to implement future non-volatile memory arrays. Recently, the capability of two-state ReRAMs to implement Boolean logic functionality gained wide interest. Here, we report on seven-states Tantalum Oxide Devices, which enable the realization of an intrinsic modular arithmetic using a ternary number system. Modular arithmetic, a fundamental system for operating on numbers within the limit of a modulus, is known to mathematicians since the days of Euclid and finds applications in diverse areas ranging from e-commerce to musical notations. We demonstrate that multistate devices not only reduce the storage area consumption drastically, but also enable novel in-memory operations, such as computing using high-radix number systems, which could not be implemented using two-state devices. The use of high radix number system reduces the computational complexity by reducing the number of needed digits. Thus the number of calculation operations in an addition and the number of logic devices can be reduced.

A Web application for the management of clinical workflow in image-guided and adaptive proton therapy for prostate cancer treatments.

PubMed

Yeung, Daniel; Boes, Peter; Ho, Meng Wei; Li, Zuofeng

2015-05-08

Image-guided radiotherapy (IGRT), based on radiopaque markers placed in the prostate gland, was used for proton therapy of prostate patients. Orthogonal X-rays and the IBA Digital Image Positioning System (DIPS) were used for setup correction prior to treatment and were repeated after treatment delivery. Following a rationale for margin estimates similar to that of van Herk,(1) the daily post-treatment DIPS data were analyzed to determine if an adaptive radiotherapy plan was necessary. A Web application using ASP.NET MVC5, Entity Framework, and an SQL database was designed to automate this process. The designed features included state-of-the-art Web technologies, a domain model closely matching the workflow, a database-supporting concurrency and data mining, access to the DIPS database, secured user access and roles management, and graphing and analysis tools. The Model-View-Controller (MVC) paradigm allowed clean domain logic, unit testing, and extensibility. Client-side technologies, such as jQuery, jQuery Plug-ins, and Ajax, were adopted to achieve a rich user environment and fast response. Data models included patients, staff, treatment fields and records, correction vectors, DIPS images, and association logics. Data entry, analysis, workflow logics, and notifications were implemented. The system effectively modeled the clinical workflow and IGRT process.

Toshiba General Hospital PACS for routine in- and outpatient clinics

NASA Astrophysics Data System (ADS)

Toshimitsu, Akihiro; Okazaki, Nobuo; Kura, Hiroyuki; Nishihara, Eitaro; Tsubura, Shinichi

1996-05-01

The Toshiba General Hospital introduced a departmental RIS/PACS (Radiology Information System/Picture Archiving and Communication System) in the radiology department in May, 1993. It has been used routinely since that time. In order to provide efficient means for clinicians to find and read many images, the system has been expanded to the neurosurgery and urology clinics and wards since May, 1995, and five image referring workstations now provide digital images to clinicians. In this paper we discuss an algorithm for image migration, one of the key issues to accomplish the expansion to outpatient clinics successfully, and propose the WYWIWYG (what you want is what you get) image transfer logic. This is the logic used to transfer images that physicians require refer without increasing the traffic between the image server and referring workstations. We accomplish the WYWIWYG logic by prioritizing exams the physicians have not yet viewed and by finding historical exams according to the modality, anatomy, and marking. Clinicians gave us comments from their first use of the system and suggested that the PACS enables clinicians to review images more efficiently compared to a film-based system. Our experience suggests that it is a key to the effective application of PACS in outpatient clinics to incorporate consideration patterns of clinicians on the migration algorithm.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ben-Zvi, I.

Various authors have previously studied the theory and practice of cavity testing, notably an extensive treatment by Powers [1] and Padamsee [2]. The advent of the digital Low Level RF (LLRF) electronics based on Field Programmable Logic Arrays (FPGA) provides various improvements over the rather complex systems used in the past as well as enabling new measurement techniques.In this document we reintroduce a technique that seems to have fallen out of practice in recent times, that is obtaining the coupling constant β through measurements from just one port, the reflected power port, of the directional coupler placed in front ofmore » the cavity.« less

N Channel JFET Based Digital Logic Gate Structure

NASA Technical Reports Server (NTRS)

Krasowski, Michael J (Inventor)

2013-01-01

An apparatus is provided that includes a first field effect transistor with a source tied to zero volts and a drain tied to voltage drain drain (Vdd) through a first resistor. The apparatus also includes a first node configured to tie a second resistor to a third resistor and connect to an input of a gate of the first field effect transistor in order for the first field effect transistor to receive a signal. The apparatus also includes a second field effect transistor configured as a unity gain buffer having a drain tied to Vdd and an uncommitted source.

A distributed fault-tolerant signal processor /FTSP/

NASA Astrophysics Data System (ADS)

Bonneau, R. J.; Evett, R. C.; Young, M. J.

1980-01-01

A digital fault-tolerant signal processor (FTSP), an example of a self-repairing programmable system is analyzed. The design configuration is discussed in terms of fault tolerance, system-level fault detection, isolation and common memory. Special attention is given to the FDIR (fault detection isolation and reconfiguration) logic, noting that the reconfiguration decisions are based on configuration, summary status, end-around tests, and north marker/synchro data. Several mechanisms of fault detection are described which initiate reconfiguration at different levels. It is concluded that the reliability of a signal processor can be significantly enhanced by the use of fault-tolerant techniques.

Statechart-based design controllers for FPGA partial reconfiguration

NASA Astrophysics Data System (ADS)

Łabiak, Grzegorz; Wegrzyn, Marek; Rosado Muñoz, Alfredo

2015-09-01

Statechart diagram and UML technique can be a vital part of early conceptual modeling. At the present time there is no much support in hardware design methodologies for reconfiguration features of reprogrammable devices. Authors try to bridge the gap between imprecise UML model and formal HDL description. The key concept in author's proposal is to describe the behavior of the digital controller by statechart diagrams and to map some parts of the behavior into reprogrammable logic by means of group of states which forms sequential automaton. The whole process is illustrated by the example with experimental results.

The electronics readout and data acquisition system of the KM3NeT neutrino telescope node

DOE Office of Scientific and Technical Information (OSTI.GOV)

Real, Diego; Collaboration: KM3NeT Collaboration

2014-11-18

The KM3NeT neutrino telescope will be composed by tens of thousands of glass spheres, called Digital Optical Module (DOM), each of them containing 31 PMTs of small photocathode area (3'). The readout and data acquisition system of KM3NeT have to collect, treat and send to shore, in an economic way, the enormous amount of data produced by the photomultipliers and at the same time to provide time synchronization between each DOM at the level of 1 ns. It is described in the present article the Central Logic Board, that integrates the Time to Digital Converters and the White Rabbit protocolmore » used for the DOM synchronization in a transparent way, the Power Board used in the DOM, the PMT base to readout the photomultipliers and the respective collecting boards, the so called Octopus Board.« less

A flexible 32-channel time-to-digital converter implemented in a Xilinx Zynq-7000 field programmable gate array

NASA Astrophysics Data System (ADS)

Wang, Yonggang; Kuang, Jie; Liu, Chong; Cao, Qiang; Li, Deng

2017-03-01

A high performance multi-channel time-to-digital converter (TDC) is implemented in a Xilinx Zynq-7000 field programmable gate array (FPGA). It can be flexibly configured as either 32 TDC channels with 9.9 ps time-interval RMS precision, 16 TDC channels with 6.9 ps RMS precision, or 8 TDC channels with 5.8 ps RMS precision. All TDCs have a 380 M Samples/second measurement throughput and a 2.63 ns measurement dead time. The performance consistency and temperature dependence of TDC channels are also evaluated. Because Zynq-7000 FPGA family integrates a feature-rich dual-core ARM based processing system and 28 nm Xilinx programmable logic in a single device, the realization of high performance TDCs on it will make the platform more widely used in time-measuring related applications.

DRS: Derivational Reasoning System

NASA Technical Reports Server (NTRS)

Bose, Bhaskar

1995-01-01

The high reliability requirements for airborne systems requires fault-tolerant architectures to address failures in the presence of physical faults, and the elimination of design flaws during the specification and validation phase of the design cycle. Although much progress has been made in developing methods to address physical faults, design flaws remain a serious problem. Formal methods provides a mathematical basis for removing design flaws from digital systems. DRS (Derivational Reasoning System) is a formal design tool based on advanced research in mathematical modeling and formal synthesis. The system implements a basic design algebra for synthesizing digital circuit descriptions from high level functional specifications. DRS incorporates an executable specification language, a set of correctness preserving transformations, verification interface, and a logic synthesis interface, making it a powerful tool for realizing hardware from abstract specifications. DRS integrates recent advances in transformational reasoning, automated theorem proving and high-level CAD synthesis systems in order to provide enhanced reliability in designs with reduced time and cost.

A Microcomputer Interface for External Circuit Control.

ERIC Educational Resources Information Center

Gorham, D. A.

1983-01-01

Describes an interface designed to meet the requirements of an instrumentation teaching laboratory, particularly to develop computer-controlled digital circuitry while exploiting electrical drive properties of common transistor-transistor logic (TTL) devices, minimizing cost/number of components. Discusses decoding for Pet, switches, lights, and…

Distinguishing between evidence and its explanations in the steering of atomic clocks

NASA Astrophysics Data System (ADS)

Myers, John M.; Hadi Madjid, F.

2014-11-01

Quantum theory reflects within itself a separation of evidence from explanations. This separation leads to a known proof that: (1) no wave function can be determined uniquely by evidence, and (2) any chosen wave function requires a guess reaching beyond logic to things unforeseeable. Chosen wave functions are encoded into computer-mediated feedback essential to atomic clocks, including clocks that step computers through their phases of computation and clocks in space vehicles that supply evidence of signal propagation explained by hypotheses of spacetimes with metric tensor fields. The propagation of logical symbols from one computer to another requires a shared rhythm-like a bucket brigade. Here we show how hypothesized metric tensors, dependent on guesswork, take part in the logical synchronization by which clocks are steered in rate and position toward aiming points that satisfy phase constraints, thereby linking the physics of signal propagation with the sharing of logical symbols among computers. Recognizing the dependence of the phasing of symbol arrivals on guesses about signal propagation transports logical synchronization from the engineering of digital communications to a discipline essential to physics. Within this discipline we begin to explore questions invisible under any concept of time that fails to acknowledge unforeseeable events. In particular, variation of spacetime curvature is shown to limit the bit rate of logical communication.

A simple second-order digital phase-locked loop.

NASA Technical Reports Server (NTRS)

Tegnelia, C. R.

1972-01-01

A simple second-order digital phase-locked loop has been designed for the Viking Orbiter 1975 command system. Excluding analog-to-digital conversion, implementation of the loop requires only an adder/subtractor, two registers, and a correctable counter with control logic. The loop considers only the polarity of phase error and corrects system clocks according to a filtered sequence of this polarity. The loop is insensitive to input gain variation, and therefore offers the advantage of stable performance over long life. Predictable performance is guaranteed by extreme reliability of acquisition, yet in the steady state the loop produces only a slight degradation with respect to analog loop performance.

Characterization of the faulted behavior of digital computers and fault tolerant systems

NASA Technical Reports Server (NTRS)

Bavuso, Salvatore J.; Miner, Paul S.

1989-01-01

A development status evaluation is presented for efforts conducted at NASA-Langley since 1977, toward the characterization of the latent fault in digital fault-tolerant systems. Attention is given to the practical, high speed, generalized gate-level logic system simulator developed, as well as to the validation methodology used for the simulator, on the basis of faultable software and hardware simulations employing a prototype MIL-STD-1750A processor. After validation, latency tests will be performed.

Computer-Aided Design Package for Designers of Digital Optical Computers

DTIC Science & Technology

1993-07-01

Saul Levy, Chun Liew, Masoud Majidi , Donald Smith, and Thomas Stone Final Report for Grant #N00014-90-J-4018 Period Covered: 5/1/90 - 4/30/93 Miles...Logic Arrays," Applied Optics, 27, pp. 1651-1660, (May 1, 1988). [5] Murdocca, M. J., V. Gupta, and M. Majidi , "New Approaches to Digital Optical...Lanzl, F., H.-J. Preuss and G. Wiegelt, eds., Proc. SPIE, vol. 319, Garmisch, Bavaria, pp. 126-127, (1990). Murdocca, M. J., V. Gupta, and M. Majidi

Digital phase-locked loop speed control for a brushless dc motor

NASA Astrophysics Data System (ADS)

Wise, M. G.

1985-06-01

Speed control of d.c. motors by phase-locked loops (PLL) is becoming increasingly popular. Primary interest has been in employing PLL for constant speed control. This thesis investigates the theory and techniques of digital PLL to speed control of a brushless d.c. motor with a variable speed of operation. Addition of logic controlled count enable/disable to a synchronous up/down counter, used as a phase-frequency detector, is shown to improve the performance of previously proposed PLL control schemes.

Augmentor transient capability of an F100 engine equipped with a digital electronic engine control

NASA Technical Reports Server (NTRS)

Burcham, F. W., Jr.; Pai, G. D.

1984-01-01

An F100 augmented turbofan engine equipped with digital electronic engine control (DEEC) system was evaluated. The engine was equipped with a specially modified augmentor to provide improved steady state and transient augmentor capability. The combination of the DEEC and the modified augmentor was evaluated in sea level and altitude facility tests and then in four different flight phases in an F-15 aircraft. The augmentor configuration, logic, and test results are presented.

Digital circuits using universal logic gates

NASA Technical Reports Server (NTRS)

Whitaker, Sterling R. (Inventor); Miles, Lowell H. (Inventor); Cameron, Eric G. (Inventor); Donohoe, Gregory W. (Inventor); Gambles, Jody W. (Inventor)

2004-01-01

According to the invention, a digital circuit design embodied in at least one of a structural netlist, a behavioral netlist, a hardware description language netlist, a full-custom ASIC, a semi-custom ASIC, an IP core, an integrated circuit, a hybrid of chips, one or more masks, a FPGA, and a circuit card assembly is disclosed. The digital circuit design includes first and second sub-circuits. The first sub-circuits comprise a first percentage of the digital circuit design and the second sub-circuits comprise a second percentage of the digital circuit design. Each of the second sub-circuits is substantially comprised of one or more kernel circuits. The kernel circuits are comprised of selection circuits. The second percentage is at least 5%. In various embodiments, the second percentage could be at least 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, or 95%.

Scalable hybrid computation with spikes.

PubMed

Sarpeshkar, Rahul; O'Halloran, Micah

2002-09-01

We outline a hybrid analog-digital scheme for computing with three important features that enable it to scale to systems of large complexity: First, like digital computation, which uses several one-bit precise logical units to collectively compute a precise answer to a computation, the hybrid scheme uses several moderate-precision analog units to collectively compute a precise answer to a computation. Second, frequent discrete signal restoration of the analog information prevents analog noise and offset from degrading the computation. And, third, a state machine enables complex computations to be created using a sequence of elementary computations. A natural choice for implementing this hybrid scheme is one based on spikes because spike-count codes are digital, while spike-time codes are analog. We illustrate how spikes afford easy ways to implement all three components of scalable hybrid computation. First, as an important example of distributed analog computation, we show how spikes can create a distributed modular representation of an analog number by implementing digital carry interactions between spiking analog neurons. Second, we show how signal restoration may be performed by recursive spike-count quantization of spike-time codes. And, third, we use spikes from an analog dynamical system to trigger state transitions in a digital dynamical system, which reconfigures the analog dynamical system using a binary control vector; such feedback interactions between analog and digital dynamical systems create a hybrid state machine (HSM). The HSM extends and expands the concept of a digital finite-state-machine to the hybrid domain. We present experimental data from a two-neuron HSM on a chip that implements error-correcting analog-to-digital conversion with the concurrent use of spike-time and spike-count codes. We also present experimental data from silicon circuits that implement HSM-based pattern recognition using spike-time synchrony. We outline how HSMs may be used to perform learning, vector quantization, spike pattern recognition and generation, and how they may be reconfigured.

Digital microfluidic platform for multiplexing enzyme assays: implications for lysosomal storage disease screening in newborns.

PubMed

Sista, Ramakrishna S; Eckhardt, Allen E; Wang, Tong; Graham, Carrie; Rouse, Jeremy L; Norton, Scott M; Srinivasan, Vijay; Pollack, Michael G; Tolun, Adviye A; Bali, Deeksha; Millington, David S; Pamula, Vamsee K

2011-10-01

Newborn screening for lysosomal storage diseases (LSDs) has been gaining considerable interest owing to the availability of enzyme replacement therapies. We present a digital microfluidic platform to perform rapid, multiplexed enzymatic analysis of acid α-glucosidase (GAA) and acid α-galactosidase to screen for Pompe and Fabry disorders. The results were compared with those obtained using standard fluorometric methods. We performed bench-based, fluorometric enzymatic analysis on 60 deidentified newborn dried blood spots (DBSs), plus 10 Pompe-affected and 11 Fabry-affected samples, at Duke Biochemical Genetics Laboratory using a 3-mm punch for each assay and an incubation time of 20 h. We used a digital microfluidic platform to automate fluorometric enzymatic assays at Advanced Liquid Logic Inc. using extract from a single punch for both assays, with an incubation time of 6 h. Assays were also performed with an incubation time of 1 h. Assay results were generally comparable, although mean enzymatic activity for GAA using microfluidics was approximately 3 times higher than that obtained using bench-based methods, which could be attributed to higher substrate concentration. Clear separation was observed between the normal and affected samples at both 6- and 1-h incubation times using digital microfluidics. A digital microfluidic platform compared favorably with a clinical reference laboratory to perform enzymatic analysis in DBSs for Pompe and Fabry disorders. This platform presents a new technology for a newborn screening laboratory to screen LSDs by fully automating all the liquid-handling operations in an inexpensive system, providing rapid results.

Scalable printed electronics: an organic decoder addressing ferroelectric non-volatile memory

PubMed Central

Ng, Tse Nga; Schwartz, David E.; Lavery, Leah L.; Whiting, Gregory L.; Russo, Beverly; Krusor, Brent; Veres, Janos; Bröms, Per; Herlogsson, Lars; Alam, Naveed; Hagel, Olle; Nilsson, Jakob; Karlsson, Christer

2012-01-01

Scalable circuits of organic logic and memory are realized using all-additive printing processes. A 3-bit organic complementary decoder is fabricated and used to read and write non-volatile, rewritable ferroelectric memory. The decoder-memory array is patterned by inkjet and gravure printing on flexible plastics. Simulation models for the organic transistors are developed, enabling circuit designs tolerant of the variations in printed devices. We explain the key design rules in fabrication of complex printed circuits and elucidate the performance requirements of materials and devices for reliable organic digital logic. PMID:22900143

Reprogrammable field programmable gate array with integrated system for mitigating effects of single event upsets

NASA Technical Reports Server (NTRS)

Ng, Tak-kwong (Inventor); Herath, Jeffrey A. (Inventor)

2010-01-01

An integrated system mitigates the effects of a single event upset (SEU) on a reprogrammable field programmable gate array (RFPGA). The system includes (i) a RFPGA having an internal configuration memory, and (ii) a memory for storing a configuration associated with the RFPGA. Logic circuitry programmed into the RFPGA and coupled to the memory reloads a portion of the configuration from the memory into the RFPGA's internal configuration memory at predetermined times. Additional SEU mitigation can be provided by logic circuitry on the RFPGA that monitors and maintains synchronized operation of the RFPGA's digital clock managers.

Evaluation of an F100 multivariable control using a real-time engine simulation

NASA Technical Reports Server (NTRS)

Szuch, J. R.; Soeder, J. F.; Skira, C.

1977-01-01

The control evaluated has been designed for the F100-PW-100 turbofan engine. The F100 engine represents the current state-of-the-art in aircraft gas turbine technology. The control makes use of a multivariable, linear quadratic regulator. The evaluation procedure employed utilized a real-time hybrid computer simulation of the F100 engine and an implementation of the control logic on the NASA LeRC digital computer/controller. The results of the evaluation indicated that the control logic and its implementation will be capable of controlling the engine throughout its operating range.

Automotive Electronics. Teacher Edition (Revised).

ERIC Educational Resources Information Center

Mackert, Howard C.; Heiserman, Russell L.

This learning module addresses computers and their applications in contemporary automobiles. The text provides students with information on automotive microcomputers and hands-on activities that will help them see how semiconductors and digital logic devices fit into the modern repair facility. The module contains nine instructional units that…

Students' Misconceptions about Medium-Scale Integrated Circuits

ERIC Educational Resources Information Center

Herman, G. L.; Loui, M. C.; Zilles, C.

2011-01-01

To improve instruction in computer engineering and computer science, instructors must better understand how their students learn. Unfortunately, little is known about how students learn the fundamental concepts in computing. To investigate student conceptions and misconceptions about digital logic concepts, the authors conducted a qualitative…

Digital Circuit Analysis Using an 8080 Processor.

ERIC Educational Resources Information Center

Greco, John; Stern, Kenneth

1983-01-01

Presents the essentials of a program written in Intel 8080 assembly language for the steady state analysis of a combinatorial logic gate circuit. Program features and potential modifications are considered. For example, the program could also be extended to include clocked/unclocked sequential circuits. (JN)

Fuzzy Logic Enhanced Digital PIV Processing Software

NASA Technical Reports Server (NTRS)

Wernet, Mark P.

1999-01-01

Digital Particle Image Velocimetry (DPIV) is an instantaneous, planar velocity measurement technique that is ideally suited for studying transient flow phenomena in high speed turbomachinery. DPIV is being actively used at the NASA Glenn Research Center to study both stable and unstable operating conditions in a high speed centrifugal compressor. Commercial PIV systems are readily available which provide near real time feedback of the PIV image data quality. These commercial systems are well designed to facilitate the expedient acquisition of PIV image data. However, as with any general purpose system, these commercial PIV systems do not meet all of the data processing needs required for PIV image data reduction in our compressor research program. An in-house PIV PROCessing (PIVPROC) code has been developed for reducing PIV data. The PIVPROC software incorporates fuzzy logic data validation for maximum information recovery from PIV image data. PIVPROC enables combined cross-correlation/particle tracking wherein the highest possible spatial resolution velocity measurements are obtained.

Performance of the Versatile Array of Neutron Detectors at Low Energy (VANDLE)

DOE PAGES

Peters, W. A.; Ilyushkin, S.; Madurga, M.; ...

2016-08-26

The Versatile Array of Neutron Detectors at Low Energy (VANDLE) is a new, highly efficient plastic-scintillator array constructed for decay and transfer reaction experimental setups that require neutron detection. The versatile and modular design allows for customizable experimental setups including beta-delayed neutron spectroscopy and (d,n) transfer reactions in normal and inverse kinematics. The neutron energy and prompt-photon discrimination is determined through the time of flight technique. Fully digital data acquisition electronics and integrated triggering logic enables some VANDLE modules to achieve an intrinsic efficiency over 70% for 300-keV neutrons, measured through two different methods. A custom Geant4 simulation models aspectsmore » of the detector array and the experimental setups to determine efficiency and detector response. Lastly, a low detection threshold, due to the trigger logic and digitizing data acquisition, allowed us to measure the light-yield response curve from elastically scattered carbon nuclei inside the scintillating plastic from incident neutrons with kinetic energies below 2 MeV.« less

A fast and low-cost genotyping method for hepatitis B virus based on pattern recognition in point-of-care settings

PubMed Central

Qiu, Xianbo; Song, Liuwei; Yang, Shuo; Guo, Meng; Yuan, Quan; Ge, Shengxiang; Min, Xiaoping; Xia, Ningshao

2016-01-01

A fast and low-cost method for HBV genotyping especially for genotypes A, B, C and D was developed and tested. A classifier was used to detect and analyze a one-step immunoassay lateral flow strip functionalized with genotype-specific monoclonal antibodies (mAbs) on multiple capture lines in the form of pattern recognition for point-of-care (POC) diagnostics. The fluorescent signals from the capture lines and the background of the strip were collected via multiple optical channels in parallel. A digital HBV genotyping model, whose inputs are the fluorescent signals and outputs are a group of genotype-specific digital binary codes (0/1), was developed based on the HBV genotyping strategy. Meanwhile, a companion decoding table was established to cover all possible pairing cases between the states of a group of genotype-specific digital binary codes and the HBV genotyping results. A logical analyzing module was constructed to process the detected signals in parallel without program control, and its outputs were used to drive a set of LED indicators, which determine the HBV genotype. Comparing to the nucleic acid analysis to HBV viruses, much faster HBV genotyping with significantly lower cost can be obtained with the developed method. PMID:27306485

Implementation of Adaptive Digital Controllers on Programmable Logic Devices

NASA Technical Reports Server (NTRS)

Gwaltney, David A.; King, Kenneth D.; Smith, Keary J.; Ormsby, John (Technical Monitor)

2002-01-01

Much has been made of the capabilities of FPGA's (Field Programmable Gate Arrays) in the hardware implementation of fast digital signal processing (DSP) functions. Such capability also makes and FPGA a suitable platform for the digital implementation of closed loop controllers. There are myriad advantages to utilizing an FPGA for discrete-time control functions which include the capability for reconfiguration when SRAM- based FPGA's are employed, fast parallel implementation of multiple control loops and implementations that can meet space level radiation tolerance in a compact form-factor. Other researchers have presented the notion that a second order digital filter with proportional-integral-derivative (PID) control functionality can be implemented in an FPGA. At Marshall Space Flight Center, the Control Electronics Group has been studying adaptive discrete-time control of motor driven actuator systems using digital signal processor (DSF) devices. Our goal is to create a fully digital, flight ready controller design that utilizes an FPGA for implementation of signal conditioning for control feedback signals, generation of commands to the controlled system, and hardware insertion of adaptive control algorithm approaches. While small form factor, commercial DSP devices are now available with event capture, data conversion, pulse width modulated outputs and communication peripherals, these devices are not currently available in designs and packages which meet space level radiation requirements. Meeting our goals requires alternative compact implementation of such functionality to withstand the harsh environment encountered on spacecraft. Radiation tolerant FPGA's are a feasible option for reaching these goals.

Intelligent layered nanoflare: ``lab-on-a-nanoparticle'' for multiple DNA logic gate operations and efficient intracellular delivery

NASA Astrophysics Data System (ADS)

Yang, Bin; Zhang, Xiao-Bing; Kang, Li-Ping; Huang, Zhi-Mei; Shen, Guo-Li; Yu, Ru-Qin; Tan, Weihong

2014-07-01

DNA strand displacement cascades have been engineered to construct various fascinating DNA circuits. However, biological applications are limited by the insufficient cellular internalization of naked DNA structures, as well as the separated multicomponent feature. In this work, these problems are addressed by the development of a novel DNA nanodevice, termed intelligent layered nanoflare, which integrates DNA computing at the nanoscale, via the self-assembly of DNA flares on a single gold nanoparticle. As a ``lab-on-a-nanoparticle'', the intelligent layered nanoflare could be engineered to perform a variety of Boolean logic gate operations, including three basic logic gates, one three-input AND gate, and two complex logic operations, in a digital non-leaky way. In addition, the layered nanoflare can serve as a programmable strategy to sequentially tune the size of nanoparticles, as well as a new fingerprint spectrum technique for intelligent multiplex biosensing. More importantly, the nanoflare developed here can also act as a single entity for intracellular DNA logic gate delivery, without the need of commercial transfection agents or other auxiliary carriers. By incorporating DNA circuits on nanoparticles, the presented layered nanoflare will broaden the applications of DNA circuits in biological systems, and facilitate the development of DNA nanotechnology.DNA strand displacement cascades have been engineered to construct various fascinating DNA circuits. However, biological applications are limited by the insufficient cellular internalization of naked DNA structures, as well as the separated multicomponent feature. In this work, these problems are addressed by the development of a novel DNA nanodevice, termed intelligent layered nanoflare, which integrates DNA computing at the nanoscale, via the self-assembly of DNA flares on a single gold nanoparticle. As a ``lab-on-a-nanoparticle'', the intelligent layered nanoflare could be engineered to perform a variety of Boolean logic gate operations, including three basic logic gates, one three-input AND gate, and two complex logic operations, in a digital non-leaky way. In addition, the layered nanoflare can serve as a programmable strategy to sequentially tune the size of nanoparticles, as well as a new fingerprint spectrum technique for intelligent multiplex biosensing. More importantly, the nanoflare developed here can also act as a single entity for intracellular DNA logic gate delivery, without the need of commercial transfection agents or other auxiliary carriers. By incorporating DNA circuits on nanoparticles, the presented layered nanoflare will broaden the applications of DNA circuits in biological systems, and facilitate the development of DNA nanotechnology. Electronic supplementary information (ESI) available: Additional figures (Table S1, Fig. S1-S5). See DOI: 10.1039/c4nr01676a

Studies in optical parallel processing. [All optical and electro-optic approaches

NASA Technical Reports Server (NTRS)

Lee, S. H.

1978-01-01

Threshold and A/D devices for converting a gray scale image into a binary one were investigated for all-optical and opto-electronic approaches to parallel processing. Integrated optical logic circuits (IOC) and optical parallel logic devices (OPA) were studied as an approach to processing optical binary signals. In the IOC logic scheme, a single row of an optical image is coupled into the IOC substrate at a time through an array of optical fibers. Parallel processing is carried out out, on each image element of these rows, in the IOC substrate and the resulting output exits via a second array of optical fibers. The OPAL system for parallel processing which uses a Fabry-Perot interferometer for image thresholding and analog-to-digital conversion, achieves a higher degree of parallel processing than is possible with IOC.

Nanoeletromechanical switch and logic circuits formed therefrom

DOEpatents

Nordquist, Christopher D [Albuquerque, NM; Czaplewski, David A [Albuquerque, NM

2010-05-18

A nanoelectromechanical (NEM) switch is formed on a substrate with a source electrode containing a suspended electrically-conductive beam which is anchored to the substrate at each end. This beam, which can be formed of ruthenium, bows laterally in response to a voltage applied between a pair of gate electrodes and the source electrode to form an electrical connection between the source electrode and a drain electrode located near a midpoint of the beam. Another pair of gate electrodes and another drain electrode can be located on an opposite side of the beam to allow for switching in an opposite direction. The NEM switch can be used to form digital logic circuits including NAND gates, NOR gates, programmable logic gates, and SRAM and DRAM memory cells which can be used in place of conventional CMOS circuits, or in combination therewith.

Implementation Of Fuzzy Automated Brake Controller Using TSK Algorithm

NASA Astrophysics Data System (ADS)

Mittal, Ruchi; Kaur, Magandeep

2010-11-01

In this paper an application of Fuzzy Logic for Automatic Braking system is proposed. Anti-blocking system (ABS) brake controllers pose unique challenges to the designer: a) For optimal performance, the controller must operate at an unstable equilibrium point, b) Depending on road conditions, the maximum braking torque may vary over a wide range, c) The tire slippage measurement signal, crucial for controller performance, is both highly uncertain and noisy. A digital controller design was chosen which combines a fuzzy logic element and a decision logic network. The controller identifies the current road condition and generates a command braking pressure signal Depending upon the speed and distance of train. This paper describes design criteria, and the decision and rule structure of the control system. The simulation results present the system's performance depending upon the varying speed and distance of the train.

Flexible Peripheral Component Interconnect Input/Output Card

NASA Technical Reports Server (NTRS)

Bigelow, Kirk K.; Jerry, Albert L.; Baricio, Alisha G.; Cummings, Jon K.

2010-01-01

The Flexible Peripheral Component Interconnect (PCI) Input/Output (I/O) Card is an innovative circuit board that provides functionality to interface between a variety of devices. It supports user-defined interrupts for interface synchronization, tracks system faults and failures, and includes checksum and parity evaluation of interface data. The card supports up to 16 channels of high-speed, half-duplex, low-voltage digital signaling (LVDS) serial data, and can interface combinations of serial and parallel devices. Placement of a processor within the field programmable gate array (FPGA) controls an embedded application with links to host memory over its PCI bus. The FPGA also provides protocol stacking and quick digital signal processor (DSP) functions to improve host performance. Hardware timers, counters, state machines, and other glue logic support interface communications. The Flexible PCI I/O Card provides an interface for a variety of dissimilar computer systems, featuring direct memory access functionality. The card has the following attributes: 8/16/32-bit, 33-MHz PCI r2.2 compliance, Configurable for universal 3.3V/5V interface slots, PCI interface based on PLX Technology's PCI9056 ASIC, General-use 512K 16 SDRAM memory, General-use 1M 16 Flash memory, FPGA with 3K to 56K logical cells with embedded 27K to 198K bits RAM, I/O interface: 32-channel LVDS differential transceivers configured in eight, 4-bit banks; signaling rates to 200 MHz per channel, Common SCSI-3, 68-pin interface connector.

A Fast Multiple Sampling Method for Low-Noise CMOS Image Sensors With Column-Parallel 12-bit SAR ADCs.

PubMed

Kim, Min-Kyu; Hong, Seong-Kwan; Kwon, Oh-Kyong

2015-12-26

This paper presents a fast multiple sampling method for low-noise CMOS image sensor (CIS) applications with column-parallel successive approximation register analog-to-digital converters (SAR ADCs). The 12-bit SAR ADC using the proposed multiple sampling method decreases the A/D conversion time by repeatedly converting a pixel output to 4-bit after the first 12-bit A/D conversion, reducing noise of the CIS by one over the square root of the number of samplings. The area of the 12-bit SAR ADC is reduced by using a 10-bit capacitor digital-to-analog converter (DAC) with four scaled reference voltages. In addition, a simple up/down counter-based digital processing logic is proposed to perform complex calculations for multiple sampling and digital correlated double sampling. To verify the proposed multiple sampling method, a 256 × 128 pixel array CIS with 12-bit SAR ADCs was fabricated using 0.18 μm CMOS process. The measurement results shows that the proposed multiple sampling method reduces each A/D conversion time from 1.2 μs to 0.45 μs and random noise from 848.3 μV to 270.4 μV, achieving a dynamic range of 68.1 dB and an SNR of 39.2 dB.

Fully Digital Arrays of Silicon Photomultipliers (dSiPM) - a Scalable Alternative to Vacuum Photomultiplier Tubes (PMT)

NASA Astrophysics Data System (ADS)

Haemisch, York; Frach, Thomas; Degenhardt, Carsten; Thon, Andreas

Silicon Photomultipliers (SiPMs) have emerged as promising alternative to fast vacuum photomultiplier tubes (PMT). A fully digital implementation of the Silicon Photomultiplier (dSiPM) has been developed in order to overcome the deficiencies and limitations of the so far only analog SiPMs (aSiPMs). Our sensor is based on arrays of single photon avalanche photodiodes (SPADs) integrated in a standard CMOS process. Photons are detected directly by sensing the voltage at the SPAD anode using a dedicated cell electronics block next to each diode. This block also contains active quenching and recharge circuits as well as a one bit memory for the selective inhibit of detector cells. A balanced trigger network is used to propagate the trigger signal from all cells to the integrated time-to-digital converter. In consequence, photons are detected and counted as digital signals, thus making the sensor less susceptible to temperature variations and electronic noise. The integration with CMOS logic provides the added benefit of low power consumption and possible integration of data post-processing directly in the sensor. In this overview paper, we discuss the sensor architecture together with its characteristics with a focus on scalability and practicability aspects for applications in medical imaging, high energy- and astrophysics.

Translations on Eastern Europe Scientific Affairs, Number 560

DTIC Science & Technology

1977-10-04

Miklos Szilagyi . TAPNEG; prepares digitalized printed wiring diagram control punch tape on an ADMAP-2 graphing machine with reflection on the x axis...FOKAL 16 KE; BME, Dr Zsolt Illyefalvi-Vitez; BME, Dr Miklos Szilagyi . TESTOP-10; the program provides measurement and diagnostics for logic cards

Boolean integral calculus for digital systems

NASA Technical Reports Server (NTRS)

Tucker, J. H.; Tapia, M. A.; Bennett, A. W.

1985-01-01

The concept of Boolean integration is introduced and developed. When the changes in a desired function are specified in terms of changes in its arguments, then ways of 'integrating' (i.e., realizing) the function, if it exists, are presented. Boolean integral calculus has applications in design of logic circuits.

Data system for multiplexed water-current meters

NASA Technical Reports Server (NTRS)

Ramsey, C. R.

1977-01-01

Flow rates at 32 flood plain locations are measured simultaneously by single digital logic unit with high noise immunity. Water flowing through pygmy current meters rotates element that closes electrical contact once every resolution, so flow rate is measured by counting number of closures in time interval.

PLATO--AN AUTOMATED TEACHING DEVICE.

ERIC Educational Resources Information Center

BITZER, D.; AND OTHERS

PLATO (PROGRAMED LOGIC FOR AUTOMATIC TEACHING OPERATION) IS A DEVICE FOR TEACHING A NUMBER OF STUDENTS INDIVIDUALLY BY MEANS OF A SINGLE, CENTRAL PURPOSE, DIGITAL COMPUTER. THE GENERAL ORGANIZATION OF EQUIPMENT CONSISTS OF A KEYSET FOR STUDENT RESPONSES, THE COMPUTER, STORAGE DEVICE (ELECTRIC BLACKBOARD), SLIDE SELECTOR (ELECTRICAL BOOK), AND TV…

A Psychometric Evaluation of the Digital Logic Concept Inventory

ERIC Educational Resources Information Center

Herman, Geoffrey L.; Zilles, Craig; Loui, Michael C.

2014-01-01

Concept inventories hold tremendous promise for promoting the rigorous evaluation of teaching methods that might remedy common student misconceptions and promote deep learning. The measurements from concept inventories can be trusted only if the concept inventories are evaluated both by expert feedback and statistical scrutiny (psychometric…

CEDS Addresses: Rubric Elements

ERIC Educational Resources Information Center

US Department of Education, 2015

2015-01-01

Common Education Data Standards (CEDS) Version 4 introduced a common data vocabulary for defining rubrics in a data system. The CEDS elements support digital representations of both holistic and analytic rubrics. This document shares examples of holistic and analytic project rubrics, available CEDS Connections, and a logical model showing the…

Superconducting flux flow digital circuits

DOEpatents

Hietala, Vincent M.; Martens, Jon S.; Zipperian, Thomas E.

1995-01-01

A NOR/inverter logic gate circuit and a flip flop circuit implemented with superconducting flux flow transistors (SFFTs). Both circuits comprise two SFFTs with feedback lines. They have extremely low power dissipation, very high switching speeds, and the ability to interface between Josephson junction superconductor circuits and conventional microelectronics.

An Amazing Algorithm

ERIC Educational Resources Information Center

Snapp, Robert R.; Neumann, Maureen D.

2015-01-01

The rapid growth of digital technology, including the worldwide adoption of mobile and embedded computers, places new demands on K-grade 12 educators and their students. Young people should have an opportunity to learn the technical knowledge of computer science (e.g., computer programming, mathematical logic, and discrete mathematics) in order to…

Developing measures of fatigue using an alcohol comparison to validate the effects of fatigue on performance.

PubMed

Williamson, A M; Feyer, A M; Mattick, R P; Friswell, R; Finlay-Brown, S

2001-05-01

The effects of 28 h of sleep deprivation were compared with varying doses of alcohol up to 0.1% blood alcohol concentration (BAC) in the same subjects. The study was conducted in the laboratory. Twenty long-haul truck drivers and 19 people not employed as professional drivers acted as subjects. Tests were selected that were likely to be affected by fatigue, including simple reaction time, unstable tracking, dual task, Mackworth clock vigilance test, symbol digit coding, visual search, sequential spatial memory and logical reasoning. While performance effects were seen due to alcohol for all tests, sleep deprivation affected performance on most tests, but had no effect on performance on the visual search and logical reasoning tests. Some tests showed evidence of a circadian rhythm effect on performance, in particular, simple reaction time, dual task, Mackworth clock vigilance, and symbol digit coding, but only for response speed and not response accuracy. Drivers were slower but more accurate than controls on the symbol digit test, suggesting that they took a more conservative approach to performance of this test. This study demonstrated which tests are most sensitive to sleep deprivation and fatigue. The study therefore has established a set of tests that can be used in evaluations of fatigue and fatigue countermeasures.

Design of an FPGA-based electronic flow regulator (EFR) for spacecraft propulsion system

NASA Astrophysics Data System (ADS)

Manikandan, J.; Jayaraman, M.; Jayachandran, M.

2011-02-01

This paper describes a scheme for electronically regulating the flow of propellant to the thruster from a high-pressure storage tank used in spacecraft application. Precise flow delivery of propellant to thrusters ensures propulsion system operation at best efficiency by maximizing the propellant and power utilization for the mission. The proposed field programmable gate array (FPGA) based electronic flow regulator (EFR) is used to ensure precise flow of propellant to the thrusters from a high-pressure storage tank used in spacecraft application. This paper presents hardware and software design of electronic flow regulator and implementation of the regulation logic onto an FPGA.Motivation for proposed FPGA-based electronic flow regulation is on the disadvantages of conventional approach of using analog circuits. Digital flow regulation overcomes the analog equivalent as digital circuits are highly flexible, are not much affected due to noise, accurate performance is repeatable, interface is easier to computers, storing facilities are possible and finally failure rate of digital circuits is less. FPGA has certain advantages over ASIC and microprocessor/micro-controller that motivated us to opt for FPGA-based electronic flow regulator. Also the control algorithm being software, it is well modifiable without changing the hardware. This scheme is simple enough to adopt for a wide range of applications, where the flow is to be regulated for efficient operation.The proposed scheme is based on a space-qualified re-configurable field programmable gate arrays (FPGA) and hybrid micro circuit (HMC). A graphical user interface (GUI) based application software is also developed for debugging, monitoring and controlling the electronic flow regulator from PC COM port.

A bunch to bucket phase detector for the RHIC LLRF upgrade platform

DOE Office of Scientific and Technical Information (OSTI.GOV)

Smith, K.S.; Harvey, M.; Hayes, T.

2011-03-28

As part of the overall development effort for the RHIC LLRF Upgrade Platform [1,2,3], a generic four channel 16 bit Analog-to-Digital Converter (ADC) daughter module was developed to provide high speed, wide dynamic range digitizing and processing of signals from DC to several hundred megahertz. The first operational use of this card was to implement the bunch to bucket phase detector for the RHIC LLRF beam control feedback loops. This paper will describe the design and performance features of this daughter module as a bunch to bucket phase detector, and also provide an overview of its place within the overallmore » LLRF platform architecture as a high performance digitizer and signal processing module suitable to a variety of applications. In modern digital control and signal processing systems, ADCs provide the interface between the analog and digital signal domains. Once digitized, signals are then typically processed using algorithms implemented in field programmable gate array (FPGA) logic, general purpose processors (GPPs), digital signal processors (DSPs) or a combination of these. For the recently developed and commissioned RHIC LLRF Upgrade Platform, we've developed a four channel ADC daughter module based on the Linear Technology LTC2209 16 bit, 160 MSPS ADC and the Xilinx V5FX70T FPGA. The module is designed to be relatively generic in application, and with minimal analog filtering on board, is capable of processing signals from DC to 500 MHz or more. The module's first application was to implement the bunch to bucket phase detector (BTB-PD) for the RHIC LLRF system. The same module also provides DC digitizing of analog processed BPM signals used by the LLRF system for radial feedback.« less

The use of mobile learning application to the fundament of digital electronics course

NASA Astrophysics Data System (ADS)

Rakhmawati, L.; Firdha, A.

2018-01-01

A new trend in e-learning is known as Mobile Learning. Learning through mobile phones have become part of the educative process. Thus, the purposes of this study are to develop a mobile application for the Fundament of Digital Electronics course that consists of number systems operation, logic gates, and Boolean Algebra, and to assess the readiness, perceptions, and effectiveness of students in the use of mobile devices for learning in the classroom. This research uses Research and Development (R&D) method. The design used in this research, by doing treatment in one class and observing by using Android-based mobile application instructional media. The result obtained from this research shows that the test has 80 % validity aspect, 82 % of the user from senior high school students gives a positive response in using the application of mobile learning, and based on the result of post-test, 90, 90% students passed the exam. At last, it can be concluded that the use of the mobile learning application makes the learning process more effective when it is used in the teaching-learning process.

Facilitating Autonomy and Creativity in Second Language Learning through Cyber-Tasks, Hyperlinks and Net-Surfing

ERIC Educational Resources Information Center

Akinwamide, T. K.; Adedara, O. G.

2012-01-01

The digitalization of academic interactions and collaborations in this present technologically conscious world is making collaborations between technology and pedagogy in the teaching and learning processes to display logical and systematic reasoning rather than the usual stereotyped informed decisions. This simply means, pedagogically, learning…

Preservation Health Check: Monitoring Threats to Digital Repository Content

ERIC Educational Resources Information Center

Kool, Wouter; van der Werf, Titia; Lavoie, Brian

2014-01-01

The Preservation Health Check (PHC) project, undertaken as a joint effort by Open Planets Foundation (OPF) and OCLC Research, aims to evaluate the usefulness of the preservation metadata created and maintained by operational repositories for assessing basic preservation properties. The PHC project seeks to develop an implementable logic to support…

Computers in Electrical Engineering Education at Virginia Polytechnic Institute.

ERIC Educational Resources Information Center

Bennett, A. Wayne

1982-01-01

Discusses use of computers in Electrical Engineering (EE) at Virginia Polytechnic Institute. Topics include: departmental background, level of computing power using large scale systems, mini and microcomputers, use of digital logic trainers and analog/hybrid computers, comments on integrating computers into EE curricula, and computer use in…

Highest integration in microelectronics: Development of digital ASICs for PARS3-LR

NASA Astrophysics Data System (ADS)

Scholler, Peter; Vonlutz, Rainer

Essential electronic system components by PARS3-LR, show high requirements in calculation power, power consumption and reliability, by immediately increasing integration thicknesses. These problems are solved by using integrated circuits, developed by LSI LOGIC, that uses the technical and economic advantages of this leading edge technology.

Noncollinear generation of optical spatiotemporal solitons and application to ultrafast digital logic

NASA Astrophysics Data System (ADS)

Liu, Xiang; Beckwitt, Kale; Wise, Frank

2000-05-01

We demonstrate theoretically and experimentally that spatiotemporal solitons can be generated through noncollinear second-harmonic generation. The resulting Y geometry could be used to implement an optical AND gate with ultrafast, high-contrast operation but without sensitivity to the phases of the input pulses.

Superconducting flux flow digital circuits

DOEpatents

Hietala, V.M.; Martens, J.S.; Zipperian, T.E.

1995-02-14

A NOR/inverter logic gate circuit and a flip flop circuit implemented with superconducting flux flow transistors (SFFTs) are disclosed. Both circuits comprise two SFFTs with feedback lines. They have extremely low power dissipation, very high switching speeds, and the ability to interface between Josephson junction superconductor circuits and conventional microelectronics. 8 figs.

Automatic ranging circuit for a digital panel meter

DOEpatents

Mueller, Theodore R.; Ross, Harley H.

1976-01-01

This invention relates to a range changing circuit that operates in conjunction with a digital panel meter of fixed sensitivity. The circuit decodes the output of the panel meter and uses that information to change the gain of an input amplifier to the panel meter in order to insure that the maximum number of significant figures is always displayed in the meter. The circuit monitors five conditions in the meter and responds to any of four combinations of these conditions by means of logic elements to carry out the function of the circuit.

Digital adaptive flight controller development

NASA Technical Reports Server (NTRS)

Kaufman, H.; Alag, G.; Berry, P.; Kotob, S.

1974-01-01

A design study of adaptive control logic suitable for implementation in modern airborne digital flight computers was conducted. Two designs are described for an example aircraft. Each of these designs uses a weighted least squares procedure to identify parameters defining the dynamics of the aircraft. The two designs differ in the way in which control law parameters are determined. One uses the solution of an optimal linear regulator problem to determine these parameters while the other uses a procedure called single stage optimization. Extensive simulation results and analysis leading to the designs are presented.

Simulated fault injection - A methodology to evaluate fault tolerant microprocessor architectures

NASA Technical Reports Server (NTRS)

Choi, Gwan S.; Iyer, Ravishankar K.; Carreno, Victor A.

1990-01-01

A simulation-based fault-injection method for validating fault-tolerant microprocessor architectures is described. The approach uses mixed-mode simulation (electrical/logic analysis), and injects transient errors in run-time to assess the resulting fault impact. As an example, a fault-tolerant architecture which models the digital aspects of a dual-channel real-time jet-engine controller is used. The level of effectiveness of the dual configuration with respect to single and multiple transients is measured. The results indicate 100 percent coverage of single transients. Approximately 12 percent of the multiple transients affect both channels; none result in controller failure since two additional levels of redundancy exist.

An application of different dioids in public key cryptography

DOE Office of Scientific and Technical Information (OSTI.GOV)

Durcheva, Mariana I., E-mail: mdurcheva66@gmail.com

2014-11-18

Dioids provide a natural framework for analyzing a broad class of discrete event dynamical systems such as the design and analysis of bus and railway timetables, scheduling of high-throughput industrial processes, solution of combinatorial optimization problems, the analysis and improvement of flow systems in communication networks. They have appeared in several branches of mathematics such as functional analysis, optimization, stochastic systems and dynamic programming, tropical geometry, fuzzy logic. In this paper we show how to involve dioids in public key cryptography. The main goal is to create key – exchange protocols based on dioids. Additionally the digital signature scheme ismore » presented.« less

An electrically reconfigurable logic gate intrinsically enabled by spin-orbit materials.

PubMed

Kazemi, Mohammad

2017-11-10

The spin degree of freedom in magnetic devices has been discussed widely for computing, since it could significantly reduce energy dissipation, might enable beyond Von Neumann computing, and could have applications in quantum computing. For spin-based computing to become widespread, however, energy efficient logic gates comprising as few devices as possible are required. Considerable recent progress has been reported in this area. However, proposals for spin-based logic either require ancillary charge-based devices and circuits in each individual gate or adopt principals underlying charge-based computing by employing ancillary spin-based devices, which largely negates possible advantages. Here, we show that spin-orbit materials possess an intrinsic basis for the execution of logic operations. We present a spin-orbit logic gate that performs a universal logic operation utilizing the minimum possible number of devices, that is, the essential devices required for representing the logic operands. Also, whereas the previous proposals for spin-based logic require extra devices in each individual gate to provide reconfigurability, the proposed gate is 'electrically' reconfigurable at run-time simply by setting the amplitude of the clock pulse applied to the gate. We demonstrate, analytically and numerically with experimentally benchmarked models, that the gate performs logic operations and simultaneously stores the result, realizing the 'stateful' spin-based logic scalable to ultralow energy dissipation.

Molecular computational elements encode large populations of small objects

NASA Astrophysics Data System (ADS)

Prasanna de Silva, A.; James, Mark R.; McKinney, Bernadine O. F.; Pears, David A.; Weir, Sheenagh M.

2006-10-01

Since the introduction of molecular computation, experimental molecular computational elements have grown to encompass small-scale integration, arithmetic and games, among others. However, the need for a practical application has been pressing. Here we present molecular computational identification (MCID), a demonstration that molecular logic and computation can be applied to a widely relevant issue. Examples of populations that need encoding in the microscopic world are cells in diagnostics or beads in combinatorial chemistry (tags). Taking advantage of the small size (about 1nm) and large `on/off' output ratios of molecular logic gates and using the great variety of logic types, input chemical combinations, switching thresholds and even gate arrays in addition to colours, we produce unique identifiers for members of populations of small polymer beads (about 100μm) used for synthesis of combinatorial libraries. Many millions of distinguishable tags become available. This method should be extensible to far smaller objects, with the only requirement being a `wash and watch' protocol. Our focus on converting molecular science into technology concerning analog sensors, turns to digital logic devices in the present work.

Molecular computational elements encode large populations of small objects.

PubMed

de Silva, A Prasanna; James, Mark R; McKinney, Bernadine O F; Pears, David A; Weir, Sheenagh M

2006-10-01

Since the introduction of molecular computation, experimental molecular computational elements have grown to encompass small-scale integration, arithmetic and games, among others. However, the need for a practical application has been pressing. Here we present molecular computational identification (MCID), a demonstration that molecular logic and computation can be applied to a widely relevant issue. Examples of populations that need encoding in the microscopic world are cells in diagnostics or beads in combinatorial chemistry (tags). Taking advantage of the small size (about 1 nm) and large 'on/off' output ratios of molecular logic gates and using the great variety of logic types, input chemical combinations, switching thresholds and even gate arrays in addition to colours, we produce unique identifiers for members of populations of small polymer beads (about 100 microm) used for synthesis of combinatorial libraries. Many millions of distinguishable tags become available. This method should be extensible to far smaller objects, with the only requirement being a 'wash and watch' protocol. Our focus on converting molecular science into technology concerning analog sensors, turns to digital logic devices in the present work.

An Embedded Reconfigurable Logic Module

NASA Technical Reports Server (NTRS)

Tucker, Jerry H.; Klenke, Robert H.; Shams, Qamar A. (Technical Monitor)

2002-01-01

A Miniature Embedded Reconfigurable Computer and Logic (MERCAL) module has been developed and verified. MERCAL was designed to be a general-purpose, universal module that that can provide significant hardware and software resources to meet the requirements of many of today's complex embedded applications. This is accomplished in the MERCAL module by combining a sub credit card size PC in a DIMM form factor with a XILINX Spartan I1 FPGA. The PC has the ability to download program files to the FPGA to configure it for different hardware functions and to transfer data to and from the FPGA via the PC's ISA bus during run time. The MERCAL module combines, in a compact package, the computational power of a 133 MHz PC with up to 150,000 gate equivalents of digital logic that can be reconfigured by software. The general architecture and functionality of the MERCAL hardware and system software are described.

A Web application for the management of clinical workflow in image‐guided and adaptive proton therapy for prostate cancer treatments

PubMed Central

Boes, Peter; Ho, Meng Wei; Li, Zuofeng

2015-01-01

Image‐guided radiotherapy (IGRT), based on radiopaque markers placed in the prostate gland, was used for proton therapy of prostate patients. Orthogonal X‐rays and the IBA Digital Image Positioning System (DIPS) were used for setup correction prior to treatment and were repeated after treatment delivery. Following a rationale for margin estimates similar to that of van Herk,(1) the daily post‐treatment DIPS data were analyzed to determine if an adaptive radiotherapy plan was necessary. A Web application using ASP.NET MVC5, Entity Framework, and an SQL database was designed to automate this process. The designed features included state‐of‐the‐art Web technologies, a domain model closely matching the workflow, a database‐supporting concurrency and data mining, access to the DIPS database, secured user access and roles management, and graphing and analysis tools. The Model‐View‐Controller (MVC) paradigm allowed clean domain logic, unit testing, and extensibility. Client‐side technologies, such as jQuery, jQuery Plug‐ins, and Ajax, were adopted to achieve a rich user environment and fast response. Data models included patients, staff, treatment fields and records, correction vectors, DIPS images, and association logics. Data entry, analysis, workflow logics, and notifications were implemented. The system effectively modeled the clinical workflow and IGRT process. PACS number: 87 PMID:26103504

Advancing the science of forensic data management

NASA Astrophysics Data System (ADS)

Naughton, Timothy S.

2002-07-01

Many individual elements comprise a typical forensics process. Collecting evidence, analyzing it, and using results to draw conclusions are all mutually distinct endeavors. Different physical locations and personnel are involved, juxtaposed against an acute need for security and data integrity. Using digital technologies and the Internet's ubiquity, these diverse elements can be conjoined using digital data as the common element. This result is a new data management process that can be applied to serve all elements of the community. The first step is recognition of a forensics lifecycle. Evidence gathering, analysis, storage, and use in legal proceedings are actually just distinct parts of a single end-to-end process, and thus, it is hypothesized that a single data system that can also accommodate each constituent phase using common network and security protocols. This paper introduces the idea of web-based Central Data Repository. Its cornerstone is anywhere, anytime Internet upload, viewing, and report distribution. Archives exist indefinitely after being created, and high-strength security and encryption protect data and ensure subsequent case file additions do not violate chain-of-custody or other handling provisions. Several legal precedents have been established for using digital information in courts of law, and in fact, effective prosecution of cyber crimes absolutely relies on its use. An example is a US Department of Agriculture division's use of digital images to back up its inspection process, with pictures and information retained on secure servers to enforce the Perishable Agricultural Commodities Act. Forensics is a cumulative process. Secure, web-based data management solutions, such as the Central Data Repository postulated here, can support each process step. Logically marrying digital technologies with Internet accessibility should help nurture a thought process to explore alternatives that make forensics data accessible to authorized individuals, whenever and wherever they need it.

Boolean logic tree of graphene-based chemical system for molecular computation and intelligent molecular search query.

PubMed

Huang, Wei Tao; Luo, Hong Qun; Li, Nian Bing

2014-05-06

The most serious, and yet unsolved, problem of constructing molecular computing devices consists in connecting all of these molecular events into a usable device. This report demonstrates the use of Boolean logic tree for analyzing the chemical event network based on graphene, organic dye, thrombin aptamer, and Fenton reaction, organizing and connecting these basic chemical events. And this chemical event network can be utilized to implement fluorescent combinatorial logic (including basic logic gates and complex integrated logic circuits) and fuzzy logic computing. On the basis of the Boolean logic tree analysis and logic computing, these basic chemical events can be considered as programmable "words" and chemical interactions as "syntax" logic rules to construct molecular search engine for performing intelligent molecular search query. Our approach is helpful in developing the advanced logic program based on molecules for application in biosensing, nanotechnology, and drug delivery.

GaAs VLSI technology and circuit elements for DSP

NASA Astrophysics Data System (ADS)

Mikkelson, James M.

1990-10-01

Recent progress in digital GaAs circuit performance and complexity is presented to demonstrate the current capabilities of GaAs components. High density GaAs process technology and circuit design techniques are described and critical issues for achieving favorable complexity speed power and cost tradeoffs are reviewed. Some DSP building blocks are described to provide examples of what types of DSP systems could be implemented with present GaAs technology. DIGITAL GaAs CIRCUIT CAPABILITIES In the past few years the capabilities of digital GaAs circuits have dramatically increased to the VLSI level. Major gains in circuit complexity and power-delay products have been achieved by the use of silicon-like process technologies and simple circuit topologies. The very high speed and low power consumption of digital GaAs VLSI circuits have made GaAs a desirable alternative to high performance silicon in hardware intensive high speed system applications. An example of the performance and integration complexity available with GaAs VLSI circuits is the 64x64 crosspoint switch shown in figure 1. This switch which is the most complex GaAs circuit currently available is designed on a 30 gate GaAs gate array. It operates at 200 MHz and dissipates only 8 watts of power. The reasons for increasing the level of integration of GaAs circuits are similar to the reasons for the continued increase of silicon circuit complexity. The market factors driving GaAs VLSI are system design methodology system cost power and reliability. System designers are hesitant or unwilling to go backwards to previous design techniques and lower levels of integration. A more highly integrated system in a lower performance technology can often approach the performance of a system in a higher performance technology at a lower level of integration. Higher levels of integration also lower the system component count which reduces the system cost size and power consumption while improving the system reliability. For large gate count circuits the power per gate must be minimized to prevent reliability and cooling problems. The technical factors which favor increasing GaAs circuit complexity are primarily related to reducing the speed and power penalties incurred when crossing chip boundaries. Because the internal GaAs chip logic levels are not compatible with standard silicon I/O levels input receivers and output drivers are needed to convert levels. These I/O circuits add significant delay to logic paths consume large amounts of power and use an appreciable portion of the die area. The effects of these I/O penalties can be reduced by increasing the ratio of core logic to I/O on a chip. DSP operations which have a large number of logic stages between the input and the output are ideal candidates to take advantage of the performance of GaAs digital circuits. Figure 2 is a schematic representation of the I/O penalties encountered when converting from ECL levels to GaAs

Rule-Based Runtime Verification

NASA Technical Reports Server (NTRS)

Barringer, Howard; Goldberg, Allen; Havelund, Klaus; Sen, Koushik

2003-01-01

We present a rule-based framework for defining and implementing finite trace monitoring logics, including future and past time temporal logic, extended regular expressions, real-time logics, interval logics, forms of quantified temporal logics, and so on. Our logic, EAGLE, is implemented as a Java library and involves novel techniques for rule definition, manipulation and execution. Monitoring is done on a state-by-state basis, without storing the execution trace.

Logic-Based Models for the Analysis of Cell Signaling Networks†

PubMed Central

2010-01-01

Computational models are increasingly used to analyze the operation of complex biochemical networks, including those involved in cell signaling networks. Here we review recent advances in applying logic-based modeling to mammalian cell biology. Logic-based models represent biomolecular networks in a simple and intuitive manner without describing the detailed biochemistry of each interaction. A brief description of several logic-based modeling methods is followed by six case studies that demonstrate biological questions recently addressed using logic-based models and point to potential advances in model formalisms and training procedures that promise to enhance the utility of logic-based methods for studying the relationship between environmental inputs and phenotypic or signaling state outputs of complex signaling networks. PMID:20225868

A motion-constraint logic for moving-base simulators based on variable filter parameters

NASA Technical Reports Server (NTRS)

Miller, G. K., Jr.

1974-01-01

A motion-constraint logic for moving-base simulators has been developed that is a modification to the linear second-order filters generally employed in conventional constraints. In the modified constraint logic, the filter parameters are not constant but vary with the instantaneous motion-base position to increase the constraint as the system approaches the positional limits. With the modified constraint logic, accelerations larger than originally expected are limited while conventional linear filters would result in automatic shutdown of the motion base. In addition, the modified washout logic has frequency-response characteristics that are an improvement over conventional linear filters with braking for low-frequency pilot inputs. During simulated landing approaches of an externally blown flap short take-off and landing (STOL) transport using decoupled longitudinal controls, the pilots were unable to detect much difference between the modified constraint logic and the logic based on linear filters with braking.

Intelligent layered nanoflare: "lab-on-a-nanoparticle" for multiple DNA logic gate operations and efficient intracellular delivery.

PubMed

Yang, Bin; Zhang, Xiao-Bing; Kang, Li-Ping; Huang, Zhi-Mei; Shen, Guo-Li; Yu, Ru-Qin; Tan, Weihong

2014-08-07

DNA strand displacement cascades have been engineered to construct various fascinating DNA circuits. However, biological applications are limited by the insufficient cellular internalization of naked DNA structures, as well as the separated multicomponent feature. In this work, these problems are addressed by the development of a novel DNA nanodevice, termed intelligent layered nanoflare, which integrates DNA computing at the nanoscale, via the self-assembly of DNA flares on a single gold nanoparticle. As a "lab-on-a-nanoparticle", the intelligent layered nanoflare could be engineered to perform a variety of Boolean logic gate operations, including three basic logic gates, one three-input AND gate, and two complex logic operations, in a digital non-leaky way. In addition, the layered nanoflare can serve as a programmable strategy to sequentially tune the size of nanoparticles, as well as a new fingerprint spectrum technique for intelligent multiplex biosensing. More importantly, the nanoflare developed here can also act as a single entity for intracellular DNA logic gate delivery, without the need of commercial transfection agents or other auxiliary carriers. By incorporating DNA circuits on nanoparticles, the presented layered nanoflare will broaden the applications of DNA circuits in biological systems, and facilitate the development of DNA nanotechnology.

Light-effect transistor (LET) with multiple independent gating controls for optical logic gates and optical amplification

NASA Astrophysics Data System (ADS)

Marmon, Jason; Rai, Satish; Wang, Kai; Zhou, Weilie; Zhang, Yong

2016-03-01

Modern electronics are developing electronic-optical integrated circuits, while their electronic backbone, e.g. field-effect transistors (FETs), remains the same. However, further FET down scaling is facing physical and technical challenges. A light-effect transistor (LET) offers electronic-optical hybridization at the component level, which can continue Moore’s law to quantum region without requiring a FET’s fabrication complexity, e.g. physical gate and doping, by employing optical gating and photoconductivity. Multiple independent gates are therefore readily realized to achieve unique functionalities without increasing chip space. Here we report LET device characteristics and novel digital and analog applications, such as optical logic gates and optical amplification. Prototype CdSe-nanowire-based LETs show output and transfer characteristics resembling advanced FETs, e.g. on/off ratios up to ~1.0x106 with a source-drain voltage of ~1.43 V, gate-power of ~260 nW, and subthreshold swing of ~0.3 nW/decade (excluding losses). Our work offers new electronic-optical integration strategies and electronic and optical computing approaches.

Compact FPGA-based beamformer using oversampled 1-bit A/D converters.

PubMed

Tomov, Borislav Gueorguiev; Jensen, Jørgen Arendt

2005-05-01

A compact medical ultrasound beamformer architecture that uses oversampled 1-bit analog-to-digital (A/D) converters is presented. Sparse sample processing is used, as the echo signal for the image lines is reconstructed in 512 equidistant focal points along the line through its in-phase and quadrature components. That information is sufficient for presenting a B-mode image and creating a color flow map. The high sampling rate provides the necessary delay resolution for the focusing. The low channel data width (1-bit) makes it possible to construct a compact beamformer logic. The signal reconstruction is done using finite impulse reponse (FIR) filters, applied on selected bit sequences of the delta-sigma modulator output stream. The approach allows for a multichannel beamformer to fit in a single field programmable gate array (FPGA) device. A 32-channel beamformer is estimated to occupy 50% of the available logic resources in a commercially available mid-range FPGA, and to be able to operate at 129 MHz. Simulation of the architecture at 140 MHz provides images with a dynamic range approaching 60 dB for an excitation frequency of 3 MHz.

A cylindrical SPECT camera with de-centralized readout scheme

NASA Astrophysics Data System (ADS)

Habte, F.; Stenström, P.; Rillbert, A.; Bousselham, A.; Bohm, C.; Larsson, S. A.

2001-09-01

An optimized brain single photon emission computed tomograph (SPECT) camera is being designed at Stockholm University and Karolinska Hospital. The design goal is to achieve high sensitivity, high-count rate and high spatial resolution. The sensitivity is achieved by using a cylindrical crystal, which gives a closed geometry with large solid angles. A de-centralized readout scheme where only a local environment around the light excitation is readout supports high-count rates. The high resolution is achieved by using an optimized crystal configuration. A 12 mm crystal plus 12 mm light guide combination gave an intrinsic spatial resolution better than 3.5 mm (140 keV) in a prototype system. Simulations show that a modified configuration can improve this value. A cylindrical configuration with a rotating collimator significantly simplifies the mechanical design of the gantry. The data acquisition and control system uses early digitization and subsequent digital signal processing to extract timing and amplitude information, and monitors the position of the collimator. The readout system consists of 12 or more modules each based on programmable logic and a digital signal processor. The modules send data to a PC file server-reconstruction engine via a Firewire (IEEE-1394) network.

Can composite digital monitoring biomarkers come of age? A framework for utilization.

PubMed

Kovalchick, Christopher; Sirkar, Rhea; Regele, Oliver B; Kourtis, Lampros C; Schiller, Marie; Wolpert, Howard; Alden, Rhett G; Jones, Graham B; Wright, Justin M

2017-12-01

The application of digital monitoring biomarkers in health, wellness and disease management is reviewed. Harnessing the near limitless capacity of these approaches in the managed healthcare continuum will benefit from a systems-based architecture which presents data quality, quantity, and ease of capture within a decision-making dashboard. A framework was developed which stratifies key components and advances the concept of contextualized biomarkers. The framework codifies how direct, indirect, composite, and contextualized composite data can drive innovation for the application of digital biomarkers in healthcare. The de novo framework implies consideration of physiological, behavioral, and environmental factors in the context of biomarker capture and analysis. Application in disease and wellness is highlighted, and incorporation in clinical feedback loops and closed-loop systems is illustrated. The study of contextualized biomarkers has the potential to offer rich and insightful data for clinical decision making. Moreover, advancement of the field will benefit from innovation at the intersection of medicine, engineering, and science. Technological developments in this dynamic field will thus fuel its logical evolution guided by inputs from patients, physicians, healthcare providers, end-payors, actuarists, medical device manufacturers, and drug companies.

All-optical analog comparator.

PubMed

Li, Pu; Yi, Xiaogang; Liu, Xianglian; Zhao, Dongliang; Zhao, Yongpeng; Wang, Yuncai

2016-08-23

An analog comparator is one of the core units in all-optical analog-to-digital conversion (AO-ADC) systems, which digitizes different amplitude levels into two levels of logical '1' or '0' by comparing with a defined decision threshold. Although various outstanding photonic ADC approaches have been reported, almost all of them necessitate an electrical comparator to carry out this binarization. The use of an electrical comparator is in contradiction to the aim of developing all-optical devices. In this work, we propose a new concept of an all-optical analog comparator and numerically demonstrate an implementation based on a quarter-wavelength-shifted distributed feedback laser diode (QWS DFB-LD) with multiple quantum well (MQW) structures. Our results show that the all-optical comparator is very well suited for true AO-ADCs, enabling the whole digital conversion from an analog optical signal (continuous-time signal or discrete pulse signal) to a binary representation totally in the optical domain. In particular, this all-optical analog comparator possesses a low threshold power (several mW), high extinction ratio (up to 40 dB), fast operation rate (of the order of tens of Gb/s) and a step-like transfer function.

All-optical analog comparator

PubMed Central

Li, Pu; Yi, Xiaogang; Liu, Xianglian; Zhao, Dongliang; Zhao, Yongpeng; Wang, Yuncai

2016-01-01

An analog comparator is one of the core units in all-optical analog-to-digital conversion (AO-ADC) systems, which digitizes different amplitude levels into two levels of logical ‘1’ or ‘0’ by comparing with a defined decision threshold. Although various outstanding photonic ADC approaches have been reported, almost all of them necessitate an electrical comparator to carry out this binarization. The use of an electrical comparator is in contradiction to the aim of developing all-optical devices. In this work, we propose a new concept of an all-optical analog comparator and numerically demonstrate an implementation based on a quarter-wavelength-shifted distributed feedback laser diode (QWS DFB-LD) with multiple quantum well (MQW) structures. Our results show that the all-optical comparator is very well suited for true AO-ADCs, enabling the whole digital conversion from an analog optical signal (continuous-time signal or discrete pulse signal) to a binary representation totally in the optical domain. In particular, this all-optical analog comparator possesses a low threshold power (several mW), high extinction ratio (up to 40 dB), fast operation rate (of the order of tens of Gb/s) and a step-like transfer function. PMID:27550874

All-optical analog comparator

NASA Astrophysics Data System (ADS)

Li, Pu; Yi, Xiaogang; Liu, Xianglian; Zhao, Dongliang; Zhao, Yongpeng; Wang, Yuncai

2016-08-01

An analog comparator is one of the core units in all-optical analog-to-digital conversion (AO-ADC) systems, which digitizes different amplitude levels into two levels of logical ‘1’ or ‘0’ by comparing with a defined decision threshold. Although various outstanding photonic ADC approaches have been reported, almost all of them necessitate an electrical comparator to carry out this binarization. The use of an electrical comparator is in contradiction to the aim of developing all-optical devices. In this work, we propose a new concept of an all-optical analog comparator and numerically demonstrate an implementation based on a quarter-wavelength-shifted distributed feedback laser diode (QWS DFB-LD) with multiple quantum well (MQW) structures. Our results show that the all-optical comparator is very well suited for true AO-ADCs, enabling the whole digital conversion from an analog optical signal (continuous-time signal or discrete pulse signal) to a binary representation totally in the optical domain. In particular, this all-optical analog comparator possesses a low threshold power (several mW), high extinction ratio (up to 40 dB), fast operation rate (of the order of tens of Gb/s) and a step-like transfer function.

Fuzzy logic controller optimization

DOEpatents

Sepe, Jr., Raymond B; Miller, John Michael

2004-03-23

A method is provided for optimizing a rotating induction machine system fuzzy logic controller. The fuzzy logic controller has at least one input and at least one output. Each input accepts a machine system operating parameter. Each output produces at least one machine system control parameter. The fuzzy logic controller generates each output based on at least one input and on fuzzy logic decision parameters. Optimization begins by obtaining a set of data relating each control parameter to at least one operating parameter for each machine operating region. A model is constructed for each machine operating region based on the machine operating region data obtained. The fuzzy logic controller is simulated with at least one created model in a feedback loop from a fuzzy logic output to a fuzzy logic input. Fuzzy logic decision parameters are optimized based on the simulation.

Tyramine Hydrochloride Based Label-Free System for Operating Various DNA Logic Gates and a DNA Caliper for Base Number Measurements.

PubMed

Fan, Daoqing; Zhu, Xiaoqing; Dong, Shaojun; Wang, Erkang

2017-07-05

DNA is believed to be a promising candidate for molecular logic computation, and the fluorogenic/colorimetric substrates of G-quadruplex DNAzyme (G4zyme) are broadly used as label-free output reporters of DNA logic circuits. Herein, for the first time, tyramine-HCl (a fluorogenic substrate of G4zyme) is applied to DNA logic computation and a series of label-free DNA-input logic gates, including elementary AND, OR, and INHIBIT logic gates, as well as a two to one encoder, are constructed. Furthermore, a DNA caliper that can measure the base number of target DNA as low as three bases is also fabricated. This DNA caliper can also perform concatenated AND-AND logic computation to fulfil the requirements of sophisticated logic computing. © 2017 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim.

Assessing Cultural Validity in Standardized Tests in STEM Education

ERIC Educational Resources Information Center

Gassant, Lunes

2013-01-01

This quantitative ex post facto study examined how race and gender, as elements of culture, influence the development of common misconceptions among STEM students. Primary data came from a standardized test: the Digital Logic Concept Inventory (DLCI) developed by Drs. Geoffrey L. Herman, Michael C. Louis, and Craig Zilles from the University of…

Introduction to Digital Logic Systems for Energy Monitoring and Control Systems.

DTIC Science & Technology

1985-05-01

computer were first set down by Charles Babbage in 1830. An additional criteria was proposed by Von Neumann in 1947. These criteria state: (1) An input means...criteria requirements as set down by Babbage and Von Neumann. The computer equipment ("hardware") and internal operating system ("software

ASIC For Complex Fixed-Point Arithmetic

NASA Technical Reports Server (NTRS)

Petilli, Stephen G.; Grimm, Michael J.; Olson, Erlend M.

1995-01-01

Application-specific integrated circuit (ASIC) performs 24-bit, fixed-point arithmetic operations on arrays of complex-valued input data. High-performance, wide-band arithmetic logic unit (ALU) designed for use in computing fast Fourier transforms (FFTs) and for performing ditigal filtering functions. Other applications include general computations involved in analysis of spectra and digital signal processing.

14C autoradiography with an energy-sensitive silicon pixel detector.

PubMed

Esposito, M; Mettivier, G; Russo, P

2011-04-07

The first performance tests are presented of a carbon-14 ((14)C) beta-particle digital autoradiography system with an energy-sensitive hybrid silicon pixel detector based on the Timepix readout circuit. Timepix was developed by the Medipix2 Collaboration and it is similar to the photon-counting Medipix2 circuit, except for an added time-based synchronization logic which allows derivation of energy information from the time-over-threshold signal. This feature permits direct energy measurements in each pixel of the detector array. Timepix is bump-bonded to a 300 µm thick silicon detector with 256 × 256 pixels of 55 µm pitch. Since an energetic beta-particle could release its kinetic energy in more than one detector pixel as it slows down in the semiconductor detector, an off-line image analysis procedure was adopted in which the single-particle cluster of hit pixels is recognized; its total energy is calculated and the position of interaction on the detector surface is attributed to the centre of the charge cluster. Measurements reported are detector sensitivity, (4.11 ± 0.03) × 10(-3) cps mm(-2) kBq(-1) g, background level, (3.59 ± 0.01) × 10(-5) cps mm(-2), and minimum detectable activity, 0.0077 Bq. The spatial resolution is 76.9 µm full-width at half-maximum. These figures are compared with several digital imaging detectors for (14)C beta-particle digital autoradiography.

A self-timed multipurpose delay sensor for Field Programmable Gate Arrays (FPGAs).

PubMed

Osuna, Carlos Gómez; Ituero, Pablo; López-Vallejo, Marisa

2013-12-20

This paper presents a novel self-timed multi-purpose sensor especially conceived for Field Programmable Gate Arrays (FPGAs). The aim of the sensor is to measure performance variations during the life-cycle of the device, such as process variability, critical path timing and temperature variations. The proposed topology, through the use of both combinational and sequential FPGA elements, amplifies the time of a signal traversing a delay chain to produce a pulse whose width is the sensor's measurement. The sensor is fully self-timed, avoiding the need for clock distribution networks and eliminating the limitations imposed by the system clock. One single off- or on-chip time-to-digital converter is able to perform digitization of several sensors in a single operation. These features allow for a simplified approach for designers wanting to intertwine a multi-purpose sensor network with their application logic. Employed as a temperature sensor, it has been measured to have an error of  ±0.67 °C, over the range of 20-100 °C, employing 20 logic elements with a 2-point calibration.

A Self-Timed Multipurpose Delay Sensor for Field Programmable Gate Arrays (FPGAs)

PubMed Central

Osuna, Carlos Gómez; Ituero, Pablo; López-Vallejo, Marisa

2014-01-01

This paper presents a novel self-timed multi-purpose sensor especially conceived for Field Programmable Gate Arrays (FPGAs). The aim of the sensor is to measure performance variations during the life-cycle of the device, such as process variability, critical path timing and temperature variations. The proposed topology, through the use of both combinational and sequential FPGA elements, amplifies the time of a signal traversing a delay chain to produce a pulse whose width is the sensor's measurement. The sensor is fully self-timed, avoiding the need for clock distribution networks and eliminating the limitations imposed by the system clock. One single off- or on-chip time-to-digital converter is able to perform digitization of several sensors in a single operation. These features allow for a simplified approach for designers wanting to intertwine a multi-purpose sensor network with their application logic. Employed as a temperature sensor, it has been measured to have an error of ±0.67 °C, over the range of 20–100 °C, employing 20 logic elements with a 2-point calibration. PMID:24361927

Path programmable logic: A structured design method for digital and/or mixed analog integrated circuits

NASA Technical Reports Server (NTRS)

Taylor, B.

1990-01-01

The design of Integrated Circuits has evolved past the black art practiced by a few semiconductor companies to a world wide community of users. This was basically accomplished by the development of computer aided design tools which were made available to this community. As the tools matured into different components of the design task they were accepted into the community at large. However, the next step in this evolution is being ignored by the large tool vendors hindering the continuation of this process. With system level definition and simulation through the logic specification well understood, why is the physical generation so blatantly ignored. This portion of the development is still treated as an isolated task with information being passed from the designer to the layout function. Some form of result given back but it severely lacks full definition of what has transpired. The level of integration in I.C.'s for tomorrow, whether through new processes or applications will require higher speeds, increased transistor density, and non-digital performance which can only be achieved through attention to the physical implementation.

Neuropsychological correlates of sustained attention in schizophrenia.

PubMed

Chen, E Y; Lam, L C; Chen, R Y; Nguyen, D G; Chan, C K; Wilkins, A J

1997-04-11

We employed a simple and relatively undemanding task of monotone counting for the assessment of sustained attention in schizophrenic patients. The monotone counting task has been validated neuropsychologically and is particularly sensitive to right prefrontal lesions. We compared the performance of schizophrenic patients with age- and education-matched controls. We then explored the extent to which a range of commonly employed neuropsychological tasks in schizophrenia research are related to attentional impairment as measured in this way. Monotone counting performance was found to be correlated with digit span (WAIS-R-HK), information (WAIS-R-HK), comprehension (WAIS-R-HK), logical memory (immediate recall) (Weschler Memory Scale, WMS), and visual reproduction (WMS). Multiple regression analysis also identified visual reproduction, digit span and comprehension as significant predictors of attention performance. In contrast, logical memory (delay recall) (WMS), similarity (WAIS-R-HK), semantic fluency, and Wisconsin Card Sorting Test (perseverative errors) were not correlated with attention. In addition, no significant correlation between sustained attention and symptoms was found. These findings are discussed in the context of a weakly modular cognitive system where attentional impairment may contribute selectively to a range of other cognitive deficits.

Digital logic optimization using selection operators

NASA Technical Reports Server (NTRS)

Whitaker, Sterling R. (Inventor); Miles, Lowell H. (Inventor); Cameron, Eric G. (Inventor); Gambles, Jody W. (Inventor)

2004-01-01

According to the invention, a digital design method for manipulating a digital circuit netlist is disclosed. In one step, a first netlist is loaded. The first netlist is comprised of first basic cells that are comprised of first kernel cells. The first netlist is manipulated to create a second netlist. The second netlist is comprised of second basic cells that are comprised of second kernel cells. A percentage of the first and second kernel cells are selection circuits. There is less chip area consumed in the second basic cells than in the first basic cells. The second netlist is stored. In various embodiments, the percentage could be 2% or more, 5% or more, 10% or more, 20% or more, 30% or more, or 40% or more.

WTEC panel report on European nuclear instrumentation and controls

NASA Technical Reports Server (NTRS)

White, James D.; Lanning, David D.; Beltracchi, Leo; Best, Fred R.; Easter, James R.; Oakes, Lester C.; Sudduth, A. L.

1991-01-01

Control and instrumentation systems might be called the 'brain' and 'senses' of a nuclear power plant. As such they become the key elements in the integrated operation of these plants. Recent developments in digital equipment have allowed a dramatic change in the design of these instrument and control (I&C) systems. New designs are evolving with cathode ray tube (CRT)-based control rooms, more automation, and better logical information for the human operators. As these new advanced systems are developed, various decisions must be made about the degree of automation and the human-to-machine interface. Different stages of the development of control automation and of advanced digital systems can be found in various countries. The purpose of this technology assessment is to make a comparative evaluation of the control and instrumentation systems that are being used for commercial nuclear power plants in Europe and the United States. This study is limited to pressurized water reactors (PWR's). Part of the evaluation includes comparisons with a previous similar study assessing Japanese technology.

Extravehicular mobility unit thermal simulator

NASA Technical Reports Server (NTRS)

Hixon, C. W.; Phillips, M. A.

1973-01-01

The analytical methods, thermal model, and user's instructions for the SIM bay extravehicular mobility unit (EMU) routine are presented. This digital computer program was developed for detailed thermal performance predictions of the crewman performing a command module extravehicular activity during transearth coast. It accounts for conductive, convective, and radiative heat transfer as well as fluid flow and associated flow control components. The program is a derivative of the Apollo lunar surface EMU digital simulator. It has the operational flexibility to accept card or magnetic tape for both the input data and program logic. Output can be tabular and/or plotted and the mission simulation can be stopped and restarted at the discretion of the user. The program was developed for the NASA-JSC Univac 1108 computer system and several of the capabilities represent utilization of unique features of that system. Analytical methods used in the computer routine are based on finite difference approximations to differential heat and mass balance equations which account for temperature or time dependent thermo-physical properties.

A low-noise CMOS pixel direct charge sensor, Topmetal-II-

DOE PAGES

An, Mangmang; Chen, Chufeng; Gao, Chaosong; ...

2015-12-12

In this paper, we report the design and characterization of a CMOS pixel direct charge sensor, Topmetal-II-, fabricated in a standard 0.35 μm CMOS Integrated Circuit process. The sensor utilizes exposed metal patches on top of each pixel to directly collect charge. Each pixel contains a low-noise charge-sensitive preamplifier to establish the analog signal and a discriminator with tunable threshold to generate hits. The analog signal from each pixel is accessible through time-shared multiplexing over the entire array. Hits are read out digitally through a column-based priority logic structure. Tests show that the sensor achieved a <15e - analog noisemore » and a 200e - minimum threshold for digital readout per pixel. The sensor is capable of detecting both electrons and ions drifting in gas. Lastly, these characteristics enable its use as the charge readout device in future Time Projection Chambers without gaseous gain mechanism, which has unique advantages in low background and low rate-density experiments.« less

DOE Office of Scientific and Technical Information (OSTI.GOV)

Agnes, P.; Albuquerque, I. F. M.; Alexander, T.

The DarkSide-50 experiment at the Laboratori Nazionali del Gran Sasso is a search for dark matter using a dual phase time projection chamber with 50 kg of low radioactivity argon as target. Light signals from interactions in the argon are detected by a system of 38 photo-multiplier tubes (PMTs), 19 above and 19 below the TPC volume inside the argon cryostat. We describe the electronics which processes the signals from the photo-multipliers, the trigger system which identifies events of interest, and the data-acquisition system which records the data for further analysis. The electronics include resistive voltage dividers on the PMTs,more » custom pre-amplifiers mounted directly on the PMT voltage dividers in the liquid argon, and custom amplifier/discriminators (at room temperature). After amplification, the PMT signals are digitized in CAEN waveform digitizers, and CAEN logic modules are used to construct the trigger, the data acquisition system for the TPC is based on the Fermilab "artdaq" software. The system has been in operation since early 2014.« less

Video image processor on the Spacelab 2 Solar Optical Universal Polarimeter /SL2 SOUP/

NASA Technical Reports Server (NTRS)

Lindgren, R. W.; Tarbell, T. D.

1981-01-01

The SOUP instrument is designed to obtain diffraction-limited digital images of the sun with high photometric accuracy. The Video Processor originated from the requirement to provide onboard real-time image processing, both to reduce the telemetry rate and to provide meaningful video displays of scientific data to the payload crew. This original concept has evolved into a versatile digital processing system with a multitude of other uses in the SOUP program. The central element in the Video Processor design is a 16-bit central processing unit based on 2900 family bipolar bit-slice devices. All arithmetic, logical and I/O operations are under control of microprograms, stored in programmable read-only memory and initiated by commands from the LSI-11. Several functions of the Video Processor are described, including interface to the High Rate Multiplexer downlink, cosmetic and scientific data processing, scan conversion for crew displays, focus and exposure testing, and use as ground support equipment.

A low-noise CMOS pixel direct charge sensor, Topmetal-II-

DOE Office of Scientific and Technical Information (OSTI.GOV)

An, Mangmang; Chen, Chufeng; Gao, Chaosong

In this paper, we report the design and characterization of a CMOS pixel direct charge sensor, Topmetal-II-, fabricated in a standard 0.35 μm CMOS Integrated Circuit process. The sensor utilizes exposed metal patches on top of each pixel to directly collect charge. Each pixel contains a low-noise charge-sensitive preamplifier to establish the analog signal and a discriminator with tunable threshold to generate hits. The analog signal from each pixel is accessible through time-shared multiplexing over the entire array. Hits are read out digitally through a column-based priority logic structure. Tests show that the sensor achieved a <15e - analog noisemore » and a 200e - minimum threshold for digital readout per pixel. The sensor is capable of detecting both electrons and ions drifting in gas. Lastly, these characteristics enable its use as the charge readout device in future Time Projection Chambers without gaseous gain mechanism, which has unique advantages in low background and low rate-density experiments.« less

Integrated digital inverters based on two-dimensional anisotropic ReS₂ field-effect transistors

DOE PAGES

Liu, Erfu; Fu, Yajun; Wang, Yaojia; ...

2015-05-07

Semiconducting two-dimensional transition metal dichalcogenides are emerging as top candidates for post-silicon electronics. While most of them exhibit isotropic behaviour, lowering the lattice symmetry could induce anisotropic properties, which are both scientifically interesting and potentially useful. Here we present atomically thin rhenium disulfide (ReS₂) flakes with unique distorted 1T structure, which exhibit in-plane anisotropic properties. We fabricated monolayer and few-layer ReS₂ field-effect transistors, which exhibit competitive performance with large current on/off ratios (~10⁷) and low subthreshold swings (100 mV per decade). The observed anisotropic ratio along two principle axes reaches 3.1, which is the highest among all known two-dimensional semiconductingmore » materials. Furthermore, we successfully demonstrated an integrated digital inverter with good performance by utilizing two ReS₂ anisotropic field-effect transistors, suggesting the promising implementation of large-scale two-dimensional logic circuits. Our results underscore the unique properties of two-dimensional semiconducting materials with low crystal symmetry for future electronic applications.« less

Carbon Nanotube-Based Digital Vacuum Electronics and Miniature Instrumentation for Space Exploration

NASA Technical Reports Server (NTRS)

Manohara, H.; Toda, R.; Lin, R. H.; Liao, A.; Mojarradi, M.

2010-01-01

JPL has developed high performance cold cathodes using arrays of carbon nanotube bundles that produce > 15 A/sq cm at applied fields of 5 to 8 V/micron without any beam focusing. They have exhibited robust operation in poor vacuums of 10(exp -6) to 10(exp -4) Torr- a typically achievable range inside hermetically sealed microcavities. Using these CNT cathodes JPL has developed miniature X-ray tubes capable of delivering sufficient photon flux at acceleration voltages of <20kV to perform definitive mineralogy on planetary surfaces; mass ionizers that offer two orders of magnitude power savings, and S/N ratio better by a factor of five over conventional ionizers. JPL has also developed a new class of programmable logic gates using CNT vacuum electronics potentially for Venus in situ missions and defense applications. These digital vacuum electronic devices are inherently high-temperature tolerant and radiation insensitive. Device design, fabrication and DC switching operation at temperatures up to 700 C are presented in this paper.

Nonvolatile “AND,” “OR,” and “NOT” Boolean logic gates based on phase-change memory

DOE Office of Scientific and Technical Information (OSTI.GOV)

Li, Y.; Zhong, Y. P.; Deng, Y. F.

2013-12-21

Electronic devices or circuits that can implement both logic and memory functions are regarded as the building blocks for future massive parallel computing beyond von Neumann architecture. Here we proposed phase-change memory (PCM)-based nonvolatile logic gates capable of AND, OR, and NOT Boolean logic operations verified in SPICE simulations and circuit experiments. The logic operations are parallel computing and results can be stored directly in the states of the logic gates, facilitating the combination of computing and memory in the same circuit. These results are encouraging for ultralow-power and high-speed nonvolatile logic circuit design based on novel memory devices.

Device and method for measuring the coefficient of performance of a heat pump

DOEpatents

Brantley, V.R.; Miller, D.R.

1982-05-18

A method and instrument is provided which allows quick and accurate measurement of the coefficient of performance of an installed electrically powered heat pump including auxiliary resistane heaters. Temperature-sensitive resistors are placed in the return and supply air ducts to measure the temperature increase of the air across the refrigerant and resistive-heating elements of the system. The voltages across the resistors which are directly proportional to the respective duct tempertures are applied to the inputs of a differential amplifier so that its output voltage is proportional to the temperature difference across the unit. A voltage-to-frequency converter connected to the output of the differential amplifier converts the voltage signal to a proportional-frequency signal. A digital watt meter is used to measure the power to the unit and produces a signal having a frequency proportional to the input power. A digital logic circuit ratios the temperature difference signal and the electric power input signal in a unique manner to produce a single number which is the coefficient of performance of the unit over the test interval. The digital logic and an in-situ calibration procedure enables the instrument to make these measurements in such a way that the ratio of heat flow/power input is obtained without computations. No specialized knowledge of thermodynamics or electrons is required to operate the instrument.

Device and method for measuring the coefficient of performance of a heat pump

DOEpatents

Brantley, Vanston R.; Miller, Donald R.

1984-01-01

A method and instrument is provided which allows quick and accurate measurement of the coefficient of performance of an installed electrically powered heat pump including auxiliary resistance heaters. Temperature sensitive resistors are placed in the return and supply air ducts to measure the temperature increase of the air across the refrigerant and resistive heating elements of the system. The voltages across the resistors which are directly proportional to the respective duct temperatures are applied to the inputs of a differential amplifier so that its output voltage is proportional to the temperature difference across the unit. A voltage-to-frequency converter connected to the output of the differential amplifier converts the voltage signal to a proportional frequency signal. A digital watt meter is used to measure the power to the unit and produces a signal having a frequency proportional to the input power. A digital logic circuit ratios the temperature difference signal and the electric power input signal in a unique manner to produce a single number which is the coefficient of performance of the unit over the test interval. The digital logic and an in-situ calibration procedure enables the instrument to make these measurements in such a way that the ratio of heat flow/power input is obtained without computations. No specialized knowledge of thermodynamics or electronics is required to operate the instrument.

A Fast Multiple Sampling Method for Low-Noise CMOS Image Sensors With Column-Parallel 12-bit SAR ADCs

PubMed Central

Kim, Min-Kyu; Hong, Seong-Kwan; Kwon, Oh-Kyong

2015-01-01

This paper presents a fast multiple sampling method for low-noise CMOS image sensor (CIS) applications with column-parallel successive approximation register analog-to-digital converters (SAR ADCs). The 12-bit SAR ADC using the proposed multiple sampling method decreases the A/D conversion time by repeatedly converting a pixel output to 4-bit after the first 12-bit A/D conversion, reducing noise of the CIS by one over the square root of the number of samplings. The area of the 12-bit SAR ADC is reduced by using a 10-bit capacitor digital-to-analog converter (DAC) with four scaled reference voltages. In addition, a simple up/down counter-based digital processing logic is proposed to perform complex calculations for multiple sampling and digital correlated double sampling. To verify the proposed multiple sampling method, a 256 × 128 pixel array CIS with 12-bit SAR ADCs was fabricated using 0.18 μm CMOS process. The measurement results shows that the proposed multiple sampling method reduces each A/D conversion time from 1.2 μs to 0.45 μs and random noise from 848.3 μV to 270.4 μV, achieving a dynamic range of 68.1 dB and an SNR of 39.2 dB. PMID:26712765

Interactive Web-based tutorials for teaching digital electronics

NASA Astrophysics Data System (ADS)

Bailey, Donald G.

2000-10-01

With a wide range of student abilities in a class, it is difficult to effectively teach and stimulate all students. A series of web based tutorials was designed to help weaker students and stretch the stronger students. The tutorials consist of a series of HTML web pages with embedded Java applets. This combination is particularly powerful for providing interactive demonstrations because any textual content may be easily provided within the web page. The applet is able to be a compete working program that dynamically illustrates the concept, or provides a working environment for the student to experiment and work through their solution. The applet is dynamic, and responds to the student through both mouse clicks and keyboard entry. These allow the student to adjust parameters, make selections, and affect the way the program is run or information is displayed. Such interaction allows each applet to provide a mini demonstration or experiment to help the student understand a particular concept or technique. The approach taken is illustrated with a tutorial that dynamically shows the relationships between a truth table, Karnaugh amp, logic circuit and Boolean algebra representations of a logic function, and dramatically illustrates the effect of minimization on the resultant circuit. Use of the tutorial has resulted in significant benefits, particularly with weaker students.

Digital printing

NASA Astrophysics Data System (ADS)

Sobotka, Werner K.

1997-02-01

Digital printing is described as a tool to replace conventional printing machines completely. Still this goal was not reached until now with any of the digital printing technologies to be described in the paper. Productivity and costs are still the main parameters and are not really solved until now. Quality in digital printing is no problem anymore. Definition of digital printing is to transfer digital datas directly on the paper surface. This step can be carried out directly or with the use of an intermediate image carrier. Keywords in digital printing are: computer- to-press; erasable image carrier; image carrier with memory. Digital printing is also the logical development of the new digital area as it is pointed out in Nicholas Negropotes book 'Being Digital' and also the answer to networking and Internet technologies. Creating images text and color in one country and publishing the datas in another country or continent is the main advantage. Printing on demand another big advantage and last but not least personalization the last big advantage. Costs and being able to coop with this new world of prepress technology is the biggest disadvantage. Therefore the very optimistic growth rates for the next few years are really nonexistent. The development of complete new markets is too slow and the replacing of old markets is too small.

Fault-tolerant reactor protection system

DOEpatents

Gaubatz, Donald C.

1997-01-01

A reactor protection system having four divisions, with quad redundant sensors for each scram parameter providing input to four independent microprocessor-based electronic chassis. Each electronic chassis acquires the scram parameter data from its own sensor, digitizes the information, and then transmits the sensor reading to the other three electronic chassis via optical fibers. To increase system availability and reduce false scrams, the reactor protection system employs two levels of voting on a need for reactor scram. The electronic chassis perform software divisional data processing, vote 2/3 with spare based upon information from all four sensors, and send the divisional scram signals to the hardware logic panel, which performs a 2/4 division vote on whether or not to initiate a reactor scram. Each chassis makes a divisional scram decision based on data from all sensors. Each division performs independently of the others (asynchronous operation). All communications between the divisions are asynchronous. Each chassis substitutes its own spare sensor reading in the 2/3 vote if a sensor reading from one of the other chassis is faulty or missing. Therefore the presence of at least two valid sensor readings in excess of a set point is required before terminating the output to the hardware logic of a scram inhibition signal even when one of the four sensors is faulty or when one of the divisions is out of service.

Fault-tolerant reactor protection system

DOEpatents

Gaubatz, D.C.

1997-04-15

A reactor protection system is disclosed having four divisions, with quad redundant sensors for each scram parameter providing input to four independent microprocessor-based electronic chassis. Each electronic chassis acquires the scram parameter data from its own sensor, digitizes the information, and then transmits the sensor reading to the other three electronic chassis via optical fibers. To increase system availability and reduce false scrams, the reactor protection system employs two levels of voting on a need for reactor scram. The electronic chassis perform software divisional data processing, vote 2/3 with spare based upon information from all four sensors, and send the divisional scram signals to the hardware logic panel, which performs a 2/4 division vote on whether or not to initiate a reactor scram. Each chassis makes a divisional scram decision based on data from all sensors. Each division performs independently of the others (asynchronous operation). All communications between the divisions are asynchronous. Each chassis substitutes its own spare sensor reading in the 2/3 vote if a sensor reading from one of the other chassis is faulty or missing. Therefore the presence of at least two valid sensor readings in excess of a set point is required before terminating the output to the hardware logic of a scram inhibition signal even when one of the four sensors is faulty or when one of the divisions is out of service. 16 figs.

Enzyme-based logic gates and circuits-analytical applications and interfacing with electronics.

PubMed

Katz, Evgeny; Poghossian, Arshak; Schöning, Michael J

2017-01-01

The paper is an overview of enzyme-based logic gates and their short circuits, with specific examples of Boolean AND and OR gates, and concatenated logic gates composed of multi-step enzyme-biocatalyzed reactions. Noise formation in the biocatalytic reactions and its decrease by adding a "filter" system, converting convex to sigmoid response function, are discussed. Despite the fact that the enzyme-based logic gates are primarily considered as components of future biomolecular computing systems, their biosensing applications are promising for immediate practical use. Analytical use of the enzyme logic systems in biomedical and forensic applications is discussed and exemplified with the logic analysis of biomarkers of various injuries, e.g., liver injury, and with analysis of biomarkers characteristic of different ethnicity found in blood samples on a crime scene. Interfacing of enzyme logic systems with modified electrodes and semiconductor devices is discussed, giving particular attention to the interfaces functionalized with signal-responsive materials. Future perspectives in the design of the biomolecular logic systems and their applications are discussed in the conclusion. Graphical Abstract Various applications and signal-transduction methods are reviewed for enzyme-based logic systems.

Digital electronic bone growth stimulator

DOEpatents

Kronberg, James W.

1995-01-01

A device for stimulating bone tissue by applying a low level alternating current signal directly to the patient's skin. A crystal oscillator, a binary divider chain and digital logic gates are used to generate the desired waveforms that reproduce the natural electrical characteristics found in bone tissue needed for stimulating bone growth and treating osteoporosis. The device, powered by a battery, contains a switch allowing selection of the correct waveform for bone growth stimulation or osteoporosis treatment so that, when attached to the skin of the patient using standard skin contact electrodes, the correct signal is communicated to the underlying bone structures.

Broadcast satellite service: The international dimension

NASA Technical Reports Server (NTRS)

Samara, Noah

1991-01-01

The dawn of the 1990's has witnessed the birth of a new satellite service - satellite sound broadcasting. This new service is characterized by digital transmission at data rates up to 256 kb/s from satellites in geostationary orbit to small, low-cost, mobile and portable receivers. The satellite sound broadcasting service is a logical step beyond navigation satellite service, such as that provided by the GPS Navstar system. The mass market appeal of satellite sound broadcasting in the area of lightsat technology and low-cost digital radios has greatly facilitated the financing of this type of space service.

Broadcast satellite service: The international dimension

NASA Astrophysics Data System (ADS)

Samara, Noah

1991-09-01

The dawn of the 1990's has witnessed the birth of a new satellite service - satellite sound broadcasting. This new service is characterized by digital transmission at data rates up to 256 kb/s from satellites in geostationary orbit to small, low-cost, mobile and portable receivers. The satellite sound broadcasting service is a logical step beyond navigation satellite service, such as that provided by the GPS Navstar system. The mass market appeal of satellite sound broadcasting in the area of lightsat technology and low-cost digital radios has greatly facilitated the financing of this type of space service.

Low-power triggered data acquisition system and method

NASA Technical Reports Server (NTRS)

Champaigne, Kevin (Inventor); Sumners, Jonathan (Inventor)

2012-01-01

A low-power triggered data acquisition system and method utilizes low-powered circuitry, comparators, and digital logic incorporated into a miniaturized device interfaced with self-generating transducer sensor inputs to detect, identify and assess impact and damage to surfaces and structures wherein, upon the occurrence of a triggering event that produces a signal greater than a set threshold changes the comparator output and causes the system to acquire and store digital data representative of the incoming waveform on at least one triggered channel. The sensors may be disposed in an array to provide triangulation and location of the impact.

A video event trigger for high frame rate, high resolution video technology

NASA Astrophysics Data System (ADS)

Williams, Glenn L.

1991-12-01

When video replaces film the digitized video data accumulates very rapidly, leading to a difficult and costly data storage problem. One solution exists for cases when the video images represent continuously repetitive 'static scenes' containing negligible activity, occasionally interrupted by short events of interest. Minutes or hours of redundant video frames can be ignored, and not stored, until activity begins. A new, highly parallel digital state machine generates a digital trigger signal at the onset of a video event. High capacity random access memory storage coupled with newly available fuzzy logic devices permits the monitoring of a video image stream for long term or short term changes caused by spatial translation, dilation, appearance, disappearance, or color change in a video object. Pretrigger and post-trigger storage techniques are then adaptable for archiving the digital stream from only the significant video images.

A video event trigger for high frame rate, high resolution video technology

NASA Technical Reports Server (NTRS)

Williams, Glenn L.

1991-01-01

When video replaces film the digitized video data accumulates very rapidly, leading to a difficult and costly data storage problem. One solution exists for cases when the video images represent continuously repetitive 'static scenes' containing negligible activity, occasionally interrupted by short events of interest. Minutes or hours of redundant video frames can be ignored, and not stored, until activity begins. A new, highly parallel digital state machine generates a digital trigger signal at the onset of a video event. High capacity random access memory storage coupled with newly available fuzzy logic devices permits the monitoring of a video image stream for long term or short term changes caused by spatial translation, dilation, appearance, disappearance, or color change in a video object. Pretrigger and post-trigger storage techniques are then adaptable for archiving the digital stream from only the significant video images.

Precision digital control systems

NASA Astrophysics Data System (ADS)

Vyskub, V. G.; Rozov, B. S.; Savelev, V. I.

This book is concerned with the characteristics of digital control systems of great accuracy. A classification of such systems is considered along with aspects of stabilization, programmable control applications, digital tracking systems and servomechanisms, and precision systems for the control of a scanning laser beam. Other topics explored are related to systems of proportional control, linear devices and methods for increasing precision, approaches for further decreasing the response time in the case of high-speed operation, possibilities for the implementation of a logical control law, and methods for the study of precision digital control systems. A description is presented of precision automatic control systems which make use of electronic computers, taking into account the existing possibilities for an employment of computers in automatic control systems, approaches and studies required for including a computer in such control systems, and an analysis of the structure of automatic control systems with computers. Attention is also given to functional blocks in the considered systems.

The design of radiation-hardened ICs for space - A compendium of approaches

NASA Technical Reports Server (NTRS)

Kerns, Sherra E.; Shafer, B. D; Rockett, L. R., Jr.; Pridmore, J. S.; Berndt, D. F.

1988-01-01

Several technologies, including bulk and epi CMOS, CMOS/SOI-SOS (silicon-on-insulator-silicon-on-sapphire), CML (current-mode logic), ECL (emitter-coupled logic), analog bipolar (JI, single-poly DI, and SOI) and GaAs E/D (enhancement/depletion) heterojunction MESFET, are discussed. The discussion includes the direct effects of space radiation on microelectronic materials and devices, how these effects are evidenced in circuit and device design parameter variations, the particular effects of most significance to each functional class of circuit, specific techniques for hardening high-speed circuits, design examples for integrated systems, including operational amplifiers and A/D (analog/digital) converters, and the computer simulation of radiation effects on microelectronic ISs.

Design on the x-ray oral digital image display card

NASA Astrophysics Data System (ADS)

Wang, Liping; Gu, Guohua; Chen, Qian

2009-10-01

According to the main characteristics of X-ray imaging, the X-ray display card is successfully designed and debugged using the basic principle of correlated double sampling (CDS) and combined with embedded computer technology. CCD sensor drive circuit and the corresponding procedures have been designed. Filtering and sampling hold circuit have been designed. The data exchange with PC104 bus has been implemented. Using complex programmable logic device as a device to provide gating and timing logic, the functions which counting, reading CPU control instructions, corresponding exposure and controlling sample-and-hold have been completed. According to the image effect and noise analysis, the circuit components have been adjusted. And high-quality images have been obtained.

Learning the Art of Electronics

NASA Astrophysics Data System (ADS)

Hayes, Thomas C.; Horowitz, Paul

2016-03-01

1. DC circuits; 2. RC circuits; 3. Diode circuits; 4. Transistors I; 5. Transistors II; 6. Operational amplifiers I; 7. Operational amplifiers II: nice positive feedback; 8. Operational amplifiers III; 9. Operational amplifiers IV: nasty positive feedback; 10. Operational amplifiers V: PID motor control loop; 11. Voltage regulators; 12. MOSFET switches; 13. Group audio project; 14. Logic gates; 15. Logic compilers, sequential circuits, flip-flops; 16. Counters; 17. Memory: state machines; 18. Analog to digital: phase-locked loop; 19. Microcontrollers and microprocessors I: processor/controller; 20. I/O, first assembly language; 21. Bit operations; 22. Interrupt: ADC and DAC; 23. Moving pointers, serial buses; 24. Dallas Standalone Micro, SiLabs SPI RAM; 25. Toys in the attic; Appendices; Index.

SPECIAL ISSUE ON OPTICAL PROCESSING OF INFORMATION: Method of implementation of optoelectronic multiparametric signal processing systems based on multivalued-logic principles

NASA Astrophysics Data System (ADS)

Arestova, M. L.; Bykovskii, A. Yu

1995-10-01

An architecture is proposed for a specialised optoelectronic multivalued logic processor based on the Allen—Givone algebra. The processor is intended for multiparametric processing of data arriving from a large number of sensors or for tackling spectral analysis tasks. The processor architecture makes it possible to obtain an approximate general estimate of the state of an object being diagnosed on a p-level scale. Optoelectronic systems are proposed for MAXIMUM, MINIMUM, and LITERAL logic gates, based on optical-frequency encoding of logic levels. Corresponding logic gates form a complete set of logic functions in the Allen—Givone algebra.

C code generation from Petri-net-based logic controller specification

NASA Astrophysics Data System (ADS)

Grobelny, Michał; Grobelna, Iwona; Karatkevich, Andrei

2017-08-01

The article focuses on programming of logic controllers. It is important that a programming code of a logic controller is executed flawlessly according to the primary specification. In the presented approach we generate C code for an AVR microcontroller from a rule-based logical model of a control process derived from a control interpreted Petri net. The same logical model is also used for formal verification of the specification by means of the model checking technique. The proposed rule-based logical model and formal rules of transformation ensure that the obtained implementation is consistent with the already verified specification. The approach is validated by practical experiments.

Binary to Octal and Octal to Binary Code Converter Using Mach-Zehnder Interferometer for High Speed Communication

NASA Astrophysics Data System (ADS)

Pal, Amrindra; Kumar, Santosh; Sharma, Sandeep

2017-05-01

Binary to octal and octal to binary code converter is a device that allows placing digital information from many inputs to many outputs. Any application of combinational logic circuit can be implemented by using external gates. In this paper, binary to octal and octal to binary code converter is proposed using electro-optic effect inside lithium-niobate based Mach-Zehnder interferometers (MZIs). The MZI structures have powerful capability to switching an optical input signal to a desired output port. The paper constitutes a mathematical description of the proposed device and thereafter simulation using MATLAB. The study is verified using beam propagation method (BPM).

Superconducting Qubit with Integrated Single Flux Quantum Controller Part I: Theory and Fabrication

NASA Astrophysics Data System (ADS)

Beck, Matthew; Leonard, Edward, Jr.; Thorbeck, Ted; Zhu, Shaojiang; Howington, Caleb; Nelson, Jj; Plourde, Britton; McDermott, Robert

As the size of quantum processors grow, so do the classical control requirements. The single flux quantum (SFQ) Josephson digital logic family offers an attractive route to proximal classical control of multi-qubit processors. Here we describe coherent control of qubits via trains of SFQ pulses. We discuss the fabrication of an SFQ-based pulse generator and a superconducting transmon qubit on a single chip. Sources of excess microwave loss stemming from the complex multilayer fabrication of the SFQ circuit are discussed. We show how to mitigate this loss through judicious choice of process workflow and appropriate use of sacrificial protection layers. Present address: IBM T.J. Watson Research Center.

A case study for a digital seabed database: Bohai Sea engineering geology database

NASA Astrophysics Data System (ADS)

Tianyun, Su; Shikui, Zhai; Baohua, Liu; Ruicai, Liang; Yanpeng, Zheng; Yong, Wang

2006-07-01

This paper discusses the designing plan of ORACLE-based Bohai Sea engineering geology database structure from requisition analysis, conceptual structure analysis, logical structure analysis, physical structure analysis and security designing. In the study, we used the object-oriented Unified Modeling Language (UML) to model the conceptual structure of the database and used the powerful function of data management which the object-oriented and relational database ORACLE provides to organize and manage the storage space and improve its security performance. By this means, the database can provide rapid and highly effective performance in data storage, maintenance and query to satisfy the application requisition of the Bohai Sea Oilfield Paradigm Area Information System.

Ant colony optimisation-direct cover: a hybrid ant colony direct cover technique for multi-level synthesis of multiple-valued logic functions

NASA Astrophysics Data System (ADS)

Abd-El-Barr, Mostafa

2010-12-01

The use of non-binary (multiple-valued) logic in the synthesis of digital systems can lead to savings in chip area. Advances in very large scale integration (VLSI) technology have enabled the successful implementation of multiple-valued logic (MVL) circuits. A number of heuristic algorithms for the synthesis of (near) minimal sum-of products (two-level) realisation of MVL functions have been reported in the literature. The direct cover (DC) technique is one such algorithm. The ant colony optimisation (ACO) algorithm is a meta-heuristic that uses constructive greediness to explore a large solution space in finding (near) optimal solutions. The ACO algorithm mimics the ant's behaviour in the real world in using the shortest path to reach food sources. We have previously introduced an ACO-based heuristic for the synthesis of two-level MVL functions. In this article, we introduce the ACO-DC hybrid technique for the synthesis of multi-level MVL functions. The basic idea is to use an ant to decompose a given MVL function into a number of levels and then synthesise each sub-function using a DC-based technique. The results obtained using the proposed approach are compared to those obtained using existing techniques reported in the literature. A benchmark set consisting of 50,000 randomly generated 2-variable 4-valued functions is used in the comparison. The results obtained using the proposed ACO-DC technique are shown to produce efficient realisation in terms of the average number of gates (as a measure of chip area) needed for the synthesis of a given MVL function.

Website Analysis in an EFL Context: Content Comprehension, Perceptions on Web Usability and Awareness of Reading Strategies

ERIC Educational Resources Information Center

Roy, Debopriyo; Crabbe, Stephen

2015-01-01

Website analysis is an interdisciplinary field of inquiry that focuses on both digital literacy and language competence (Brugger, 2009). Website analysis in an EFL learning context has the potential to facilitate logical thinking and in the process develop functional language proficiency. This study reported on an English language website…

Digital Avionics Information System (DAIS): Training Requirements Analysis Model Users Guide. Final Report.

ERIC Educational Resources Information Center

Czuchry, Andrew J.; And Others

This user's guide describes the functions, logical operations and subroutines, input data requirements, and available outputs of the Training Requirements Analysis Model (TRAMOD), a computerized analytical life cycle cost modeling system for use in the early stages of system design. Operable in a stand-alone mode, TRAMOD can be used for the…

Laser Scanner Tests For Single-Event Upsets

NASA Technical Reports Server (NTRS)

Kim, Quiesup; Soli, George A.; Schwartz, Harvey R.

1992-01-01

Microelectronic advanced laser scanner (MEALS) is opto/electro/mechanical apparatus for nondestructive testing of integrated memory circuits, logic circuits, and other microelectronic devices. Multipurpose diagnostic system used to determine ultrafast time response, leakage, latchup, and electrical overstress. Used to simulate some of effects of heavy ions accelerated to high energies to determine susceptibility of digital device to single-event upsets.

Fast all-optical switch

NASA Technical Reports Server (NTRS)

Shay, Thomas M. (Inventor); Poliakov, Evgeni Y. (Inventor); Hazzard, David A. (Inventor)

2001-01-01

An apparatus and method wherein polarization rotation in alkali vapors or other mediums is used for all-optical switching and digital logic and where the rate of operation is proportional to the amplitude of the pump field. High rates of speed are accomplished by Rabi flopping of the atomic states using a continuously operating monochromatic atomic beam as the pump.

Improving Students' Educational Experience by Harnessing Digital Technology: elgg in the ODL Environment

ERIC Educational Resources Information Center

Tung, Lai Cheng

2013-01-01

Given the rising popularity of both open and distance learning (ODL) and social networking tools, it seems logical to merge and harness these two popular technologies with the goal of improving student educational experience. The integration seems to hold tremendous promise for the open and distance learning mode. To reduce the gap in the…

A Topic Analysis of ISECON Conference Proceedings from 1982 through 2014

ERIC Educational Resources Information Center

Clark, Jon; Athey, Susan; Plotnicki, Jon; Barnes, Jay

2016-01-01

The authors note a distinct shift in topics covered in curricula as well as in conference presentations. This research was undertaken to get a better understanding of what these shifts have been, and determine their magnitude over time. Since ISECON has published its conference proceedings in digital format since 1982, this was a logical source of…

A Systematic Software, Firmware, and Hardware Codesign Methodology for Digital Signal Processing

DTIC Science & Technology

2014-03-01

possible mappings ...................................................60 Table 25. Possible optimal leaf -nodes... size weight and power UAV unmanned aerial vehicle UHF ultra-high frequency UML universal modeling language Verilog verify logic VHDL VHSIC...optimal leaf -nodes to some design patterns for embedded system design. Software and hardware partitioning is a very difficult challenge in the field of

General purpose computer programs for numerically analyzing linear ac electrical and electronic circuits for steady-state conditions

NASA Technical Reports Server (NTRS)

Egebrecht, R. A.; Thorbjornsen, A. R.

1967-01-01

Digital computer programs determine steady-state performance characteristics of active and passive linear circuits. The ac analysis program solves the basic circuit parameters. The compiler program solves these circuit parameters and in addition provides a more versatile program by allowing the user to perform mathematical and logical operations.

Construction of a fuzzy and Boolean logic gates based on DNA.

PubMed

Zadegan, Reza M; Jepsen, Mette D E; Hildebrandt, Lasse L; Birkedal, Victoria; Kjems, Jørgen

2015-04-17

Logic gates are devices that can perform logical operations by transforming a set of inputs into a predictable single detectable output. The hybridization properties, structure, and function of nucleic acids can be used to make DNA-based logic gates. These devices are important modules in molecular computing and biosensing. The ideal logic gate system should provide a wide selection of logical operations, and be integrable in multiple copies into more complex structures. Here we show the successful construction of a small DNA-based logic gate complex that produces fluorescent outputs corresponding to the operation of the six Boolean logic gates AND, NAND, OR, NOR, XOR, and XNOR. The logic gate complex is shown to work also when implemented in a three-dimensional DNA origami box structure, where it controlled the position of the lid in a closed or open position. Implementation of multiple microRNA sensitive DNA locks on one DNA origami box structure enabled fuzzy logical operation that allows biosensing of complex molecular signals. Integrating logic gates with DNA origami systems opens a vast avenue to applications in the fields of nanomedicine for diagnostics and therapeutics. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Digital Learning As Enhanced Learning Processing? Cognitive Evidence for New insight of Smart Learning.

PubMed

Di Giacomo, Dina; Ranieri, Jessica; Lacasa, Pilar

2017-01-01

Large use of technology improved quality of life across aging and favoring the development of digital skills. Digital skills can be considered an enhancing to human cognitive activities. New research trend is about the impact of the technology in the elaboration information processing of the children. We wanted to analyze the influence of technology in early age evaluating the impact on cognition. We investigated the performance of a sample composed of n. 191 children in school age distributed in two groups as users: high digital users and low digital users. We measured the verbal and visuoperceptual cognitive performance of children by n. 8 standardized psychological tests and ad hoc self-report questionnaire. Results have evidenced the influence of digital exposition on cognitive development: the cognitive performance is looked enhanced and better developed: high digital users performed better in naming, semantic, visual memory and logical reasoning tasks. Our finding confirms the data present in literature and suggests the strong impact of the technology using not only in the social, educational and quality of life of the people, but also it outlines the functionality and the effect of the digital exposition in early age; increased cognitive abilities of the children tailor digital skilled generation with enhanced cognitive processing toward to smart learning.

Phase-lock-loop application for fiber optic receiver

NASA Astrophysics Data System (ADS)

Ruggles, Stephen L.; Wills, Robert W.

1991-02-01

Phase-locked loop circuits are frequently employed in communication systems. In recent years, digital phase-locked loop circuits were utilized in optical communications systems. In an optical transceiver system, the digital phase-locked loop circuit is connected to the output of the receiver to extract a clock signal from the received coded data (NRZ, Bi-Phase, or Manchester). The clock signal is then used to reconstruct or recover the original data from the coded data. A theoretical approach to the design of a digital phase-locked loop circuit operation at 1 and 50 MHz is described. Hardware implementation of a breadboard design to function at 1 MHz and a printed-circuit board designed to function at 50 MHz were assembled using emitter coupled logic (ECL) to verify experimentally the theoretical design.

Phase-lock-loop application for fiber optic receiver

NASA Technical Reports Server (NTRS)

Ruggles, Stephen L.; Wills, Robert W.

1991-01-01

Phase-locked loop circuits are frequently employed in communication systems. In recent years, digital phase-locked loop circuits were utilized in optical communications systems. In an optical transceiver system, the digital phase-locked loop circuit is connected to the output of the receiver to extract a clock signal from the received coded data (NRZ, Bi-Phase, or Manchester). The clock signal is then used to reconstruct or recover the original data from the coded data. A theoretical approach to the design of a digital phase-locked loop circuit operation at 1 and 50 MHz is described. Hardware implementation of a breadboard design to function at 1 MHz and a printed-circuit board designed to function at 50 MHz were assembled using emitter coupled logic (ECL) to verify experimentally the theoretical design.

Energy Efficient Digital Logic Using Nanoscale Magnetic Devices

NASA Astrophysics Data System (ADS)

Lambson, Brian James

Increasing demand for information processing in the last 50 years has been largely satisfied by the steadily declining price and improving performance of microelectronic devices. Much of this progress has been made by aggressively scaling the size of semiconductor transistors and metal interconnects that microprocessors are built from. As devices shrink to the size regime in which quantum effects pose significant challenges, new physics may be required in order to continue historical scaling trends. A variety of new devices and physics are currently under investigation throughout the scientific and engineering community to meet these challenges. One of the more drastic proposals on the table is to replace the electronic components of information processors with magnetic components. Magnetic components are already commonplace in computers for their information storage capability. Unlike most electronic devices, magnetic materials can store data in the absence of a power supply. Today's magnetic hard disk drives can routinely hold billions of bits of information and are in widespread commercial use. Their ability to function without a constant power source hints at an intrinsic energy efficiency. The question we investigate in this dissertation is whether or not this advantage can be extended from information storage to the notoriously energy intensive task of information processing. Several proof-of-concept magnetic logic devices were proposed and tested in the past decade. In this dissertation, we build on the prior work by answering fundamental questions about how magnetic devices achieve such high energy efficiency and how they can best function in digital logic applications. The results of this analysis are used to suggest and test improvements to nanomagnetic computing devices. Two of our results are seen as especially important to the field of nanomagnetic computing: (1) we show that it is possible to operate nanomagnetic computers at the fundamental thermodyanimic limits of computation and (2) we develop a nanomagnet with a unique shape that is engineered to significantly improve the reliability of nanomagnetic logic.

Bird's-eye view on noise-based logic.

PubMed

Kish, Laszlo B; Granqvist, Claes G; Horvath, Tamas; Klappenecker, Andreas; Wen, He; Bezrukov, Sergey M

2014-01-01

Noise-based logic is a practically deterministic logic scheme inspired by the randomness of neural spikes and uses a system of uncorrelated stochastic processes and their superposition to represent the logic state. We briefly discuss various questions such as ( i ) What does practical determinism mean? ( ii ) Is noise-based logic a Turing machine? ( iii ) Is there hope to beat (the dreams of) quantum computation by a classical physical noise-based processor, and what are the minimum hardware requirements for that? Finally, ( iv ) we address the problem of random number generators and show that the common belief that quantum number generators are superior to classical (thermal) noise-based generators is nothing but a myth.

Bird's-eye view on noise-based logic

NASA Astrophysics Data System (ADS)

Kish, Laszlo B.; Granqvist, Claes G.; Horvath, Tamas; Klappenecker, Andreas; Wen, He; Bezrukov, Sergey M.

2014-09-01

Noise-based logic is a practically deterministic logic scheme inspired by the randomness of neural spikes and uses a system of uncorrelated stochastic processes and their superposition to represent the logic state. We briefly discuss various questions such as (i) What does practical determinism mean? (ii) Is noise-based logic a Turing machine? (iii) Is there hope to beat (the dreams of) quantum computation by a classical physical noise-based processor, and what are the minimum hardware requirements for that? Finally, (iv) we address the problem of random number generators and show that the common belief that quantum number generators are superior to classical (thermal) noise-based generators is nothing but a myth.

Multi-bit operations in vertical spintronic shift registers

NASA Astrophysics Data System (ADS)

Lavrijsen, Reinoud; Petit, Dorothée C. M. C.; Fernández-Pacheco, Amalio; Lee, JiHyun; Mansell, Mansell; Cowburn, Russell P.

2014-03-01

Spintronic devices have in general demonstrated the feasibility of non-volatile memory storage and simple Boolean logic operations. Modern microprocessors have one further frequently used digital operation: bit-wise operations on multiple bits simultaneously. Such operations are important for binary multiplication and division and in efficient microprocessor architectures such as reduced instruction set computing (RISC). In this paper we show a four-stage vertical serial shift register made from RKKY coupled ultrathin (0.9 nm) perpendicularly magnetised layers into which a 3-bit data word is injected. The entire four stage shift register occupies a total length (thickness) of only 16 nm. We show how under the action of an externally applied magnetic field bits can be shifted together as a word and then manipulated individually, including being brought together to perform logic operations. This is one of the highest level demonstrations of logic operation ever performed on data in the magnetic state and brings closer the possibility of ultrahigh density all-magnetic microprocessors.

Multi-bit operations in vertical spintronic shift registers.

PubMed

Lavrijsen, Reinoud; Petit, Dorothée C M C; Fernández-Pacheco, Amalio; Lee, Jihyun; Mansell, Mansell; Cowburn, Russell P

2014-03-14

Spintronic devices have in general demonstrated the feasibility of non-volatile memory storage and simple Boolean logic operations. Modern microprocessors have one further frequently used digital operation: bit-wise operations on multiple bits simultaneously. Such operations are important for binary multiplication and division and in efficient microprocessor architectures such as reduced instruction set computing (RISC). In this paper we show a four-stage vertical serial shift register made from RKKY coupled ultrathin (0.9 nm) perpendicularly magnetised layers into which a 3-bit data word is injected. The entire four stage shift register occupies a total length (thickness) of only 16 nm. We show how under the action of an externally applied magnetic field bits can be shifted together as a word and then manipulated individually, including being brought together to perform logic operations. This is one of the highest level demonstrations of logic operation ever performed on data in the magnetic state and brings closer the possibility of ultrahigh density all-magnetic microprocessors.

Reprogrammable Logic Gate and Logic Circuit Based on Multistimuli-Responsive Raspberry-like Micromotors.

PubMed

Zhang, Lina; Zhang, Hui; Liu, Mei; Dong, Bin

2016-06-22

In this paper, we report a polymer-based raspberry-like micromotor. Interestingly, the resulting micromotor exhibits multistimuli-responsive motion behavior. Its on-off-on motion can be regulated by the application of stimuli such as H2O2, near-infrared light, NH3, or their combinations. Because of the versatility in motion control, the current micromotor has great potential in the application field of logic gate and logic circuit. With use of different stimuli as the inputs and the micromotor motion as the output, reprogrammable OR and INHIBIT logic gates or logic circuit consisting of OR, NOT, and AND logic gates can be achieved.

On the Importance of Set-Based Meanings for Categories and Connectives in Mathematical Logic

ERIC Educational Resources Information Center

Dawkins, Paul Christian

2017-01-01

Based on data from a series of teaching experiments on standard tools of mathematical logic, this paper characterizes a range of student meanings for mathematical properties and logical connectives. Some observed meanings inhibited students' adoption of logical structure, while others greatly facilitated it. "Reasoning with predicates"…

Functionality and operation of fluoroscopic automatic brightness control/automatic dose rate control logic in modern cardiovascular and interventional angiography systems: A Report of Task Group 125 Radiography/Fluoroscopy Subcommittee, Imaging Physics Committee, Science Council

DOE Office of Scientific and Technical Information (OSTI.GOV)

Rauch, Phillip; Lin, Pei-Jan Paul; Balter, Stephen

2012-05-15

Task Group 125 (TG 125) was charged with investigating the functionality of fluoroscopic automatic dose rate and image quality control logic in modern angiographic systems, paying specific attention to the spectral shaping filters and variations in the selected radiologic imaging parameters. The task group was also charged with describing the operational aspects of the imaging equipment for the purpose of assisting the clinical medical physicist with clinical set-up and performance evaluation. Although there are clear distinctions between the fluoroscopic operation of an angiographic system and its acquisition modes (digital cine, digital angiography, digital subtraction angiography, etc.), the scope of thismore » work was limited to the fluoroscopic operation of the systems studied. The use of spectral shaping filters in cardiovascular and interventional angiography equipment has been shown to reduce patient dose. If the imaging control algorithm were programmed to work in conjunction with the selected spectral filter, and if the generator parameters were optimized for the selected filter, then image quality could also be improved. Although assessment of image quality was not included as part of this report, it was recognized that for fluoroscopic imaging the parameters that influence radiation output, differential absorption, and patient dose are also the same parameters that influence image quality. Therefore, this report will utilize the terminology ''automatic dose rate and image quality'' (ADRIQ) when describing the control logic in modern interventional angiographic systems and, where relevant, will describe the influence of controlled parameters on the subsequent image quality. A total of 22 angiography units were investigated by the task group and of these one each was chosen as representative of the equipment manufactured by GE Healthcare, Philips Medical Systems, Shimadzu Medical USA, and Siemens Medical Systems. All equipment, for which measurement data were included in this report, was manufactured within the three year period from 2006 to 2008. Using polymethylmethacrylate (PMMA) plastic to simulate patient attenuation, each angiographic imaging system was evaluated by recording the following parameters: tube potential in units of kilovolts peak (kVp), tube current in units of milliamperes (mA), pulse width (PW) in units of milliseconds (ms), spectral filtration setting, and patient air kerma rate (PAKR) as a function of the attenuator thickness. Data were graphically plotted to reveal the manner in which the ADRIQ control logic responded to changes in object attenuation. There were similarities in the manner in which the ADRIQ control logic operated that allowed the four chosen devices to be divided into two groups, with two of the systems in each group. There were also unique approaches to the ADRIQ control logic that were associated with some of the systems, and these are described in the report. The evaluation revealed relevant information about the testing procedure and also about the manner in which different manufacturers approach the utilization of spectral filtration, pulsed fluoroscopy, and maximum PAKR limitation. This information should be particularly valuable to the clinical medical physicist charged with acceptance testing and performance evaluation of modern angiographic systems.« less

Functionality and operation of fluoroscopic automatic brightness control/automatic dose rate control logic in modern cardiovascular and interventional angiography systems: a report of Task Group 125 Radiography/Fluoroscopy Subcommittee, Imaging Physics Committee, Science Council.

PubMed

Rauch, Phillip; Lin, Pei-Jan Paul; Balter, Stephen; Fukuda, Atsushi; Goode, Allen; Hartwell, Gary; LaFrance, Terry; Nickoloff, Edward; Shepard, Jeff; Strauss, Keith

2012-05-01

Task Group 125 (TG 125) was charged with investigating the functionality of fluoroscopic automatic dose rate and image quality control logic in modern angiographic systems, paying specific attention to the spectral shaping filters and variations in the selected radiologic imaging parameters. The task group was also charged with describing the operational aspects of the imaging equipment for the purpose of assisting the clinical medical physicist with clinical set-up and performance evaluation. Although there are clear distinctions between the fluoroscopic operation of an angiographic system and its acquisition modes (digital cine, digital angiography, digital subtraction angiography, etc.), the scope of this work was limited to the fluoroscopic operation of the systems studied. The use of spectral shaping filters in cardiovascular and interventional angiography equipment has been shown to reduce patient dose. If the imaging control algorithm were programmed to work in conjunction with the selected spectral filter, and if the generator parameters were optimized for the selected filter, then image quality could also be improved. Although assessment of image quality was not included as part of this report, it was recognized that for fluoroscopic imaging the parameters that influence radiation output, differential absorption, and patient dose are also the same parameters that influence image quality. Therefore, this report will utilize the terminology "automatic dose rate and image quality" (ADRIQ) when describing the control logic in modern interventional angiographic systems and, where relevant, will describe the influence of controlled parameters on the subsequent image quality. A total of 22 angiography units were investigated by the task group and of these one each was chosen as representative of the equipment manufactured by GE Healthcare, Philips Medical Systems, Shimadzu Medical USA, and Siemens Medical Systems. All equipment, for which measurement data were included in this report, was manufactured within the three year period from 2006 to 2008. Using polymethylmethacrylate (PMMA) plastic to simulate patient attenuation, each angiographic imaging system was evaluated by recording the following parameters: tube potential in units of kilovolts peak (kVp), tube current in units of milliamperes (mA), pulse width (PW) in units of milliseconds (ms), spectral filtration setting, and patient air kerma rate (PAKR) as a function of the attenuator thickness. Data were graphically plotted to reveal the manner in which the ADRIQ control logic responded to changes in object attenuation. There were similarities in the manner in which the ADRIQ control logic operated that allowed the four chosen devices to be divided into two groups, with two of the systems in each group. There were also unique approaches to the ADRIQ control logic that were associated with some of the systems, and these are described in the report. The evaluation revealed relevant information about the testing procedure and also about the manner in which different manufacturers approach the utilization of spectral filtration, pulsed fluoroscopy, and maximum PAKR limitation. This information should be particularly valuable to the clinical medical physicist charged with acceptance testing and performance evaluation of modern angiographic systems.

Fuzzy knowledge base construction through belief networks based on Lukasiewicz logic

NASA Technical Reports Server (NTRS)

Lara-Rosano, Felipe

1992-01-01

In this paper, a procedure is proposed to build a fuzzy knowledge base founded on fuzzy belief networks and Lukasiewicz logic. Fuzzy procedures are developed to do the following: to assess the belief values of a consequent, in terms of the belief values of its logical antecedents and the belief value of the corresponding logical function; and to update belief values when new evidence is available.

Visibility enhancement of color images using Type-II fuzzy membership function

NASA Astrophysics Data System (ADS)

Singh, Harmandeep; Khehra, Baljit Singh

2018-04-01

Images taken in poor environmental conditions decrease the visibility and hidden information of digital images. Therefore, image enhancement techniques are necessary for improving the significant details of these images. An extensive review has shown that histogram-based enhancement techniques greatly suffer from over/under enhancement issues. Fuzzy-based enhancement techniques suffer from over/under saturated pixels problems. In this paper, a novel Type-II fuzzy-based image enhancement technique has been proposed for improving the visibility of images. The Type-II fuzzy logic can automatically extract the local atmospheric light and roughly eliminate the atmospheric veil in local detail enhancement. The proposed technique has been evaluated on 10 well-known weather degraded color images and is also compared with four well-known existing image enhancement techniques. The experimental results reveal that the proposed technique outperforms others regarding visible edge ratio, color gradients and number of saturated pixels.

Exploring Carbon Nanotubes for Nanoscale Devices

NASA Technical Reports Server (NTRS)

Han, Jie; Dai; Anantram; Jaffe; Saini, Subhash (Technical Monitor)

1998-01-01

Carbon nanotubes (CNTs) are shown to promise great opportunities in nanoelectronic devices and nanoelectromechanical systems (NEMS) because of their inherent nanoscale sizes, intrinsic electric conductivities, and seamless hexagonal network architectures. I present our collaborative work with Stanford on exploring CNTs for nanodevices in this talk. The electrical property measurements suggest that metallic tubes are quantum wires. Furthermore, two and three terminal CNT junctions have been observed experimentally. We have proposed and studied CNT-based molecular switches and logic devices for future digital electronics. We also have studied CNTs based NEMS inclusing gears, cantilevers, and scanning probe microscopy tips. We investigate both chemistry and physics based aspects of the CNT NEMS. Our results suggest that CNT have ideal stiffness, vibrational frequencies, Q-factors, geometry-dependent electric conductivities, and the highest chemical and mechanical stabilities for the NEMS. The use of CNT SPM tips for nanolithography is presented for demonstration of the advantages of the CNT NEMS.

Fuzzy forecasting based on two-factors second-order fuzzy-trend logical relationship groups and the probabilities of trends of fuzzy logical relationships.

PubMed

Chen, Shyi-Ming; Chen, Shen-Wen

2015-03-01

In this paper, we present a new method for fuzzy forecasting based on two-factors second-order fuzzy-trend logical relationship groups and the probabilities of trends of fuzzy-trend logical relationships. Firstly, the proposed method fuzzifies the historical training data of the main factor and the secondary factor into fuzzy sets, respectively, to form two-factors second-order fuzzy logical relationships. Then, it groups the obtained two-factors second-order fuzzy logical relationships into two-factors second-order fuzzy-trend logical relationship groups. Then, it calculates the probability of the "down-trend," the probability of the "equal-trend" and the probability of the "up-trend" of the two-factors second-order fuzzy-trend logical relationships in each two-factors second-order fuzzy-trend logical relationship group, respectively. Finally, it performs the forecasting based on the probabilities of the down-trend, the equal-trend, and the up-trend of the two-factors second-order fuzzy-trend logical relationships in each two-factors second-order fuzzy-trend logical relationship group. We also apply the proposed method to forecast the Taiwan Stock Exchange Capitalization Weighted Stock Index (TAIEX) and the NTD/USD exchange rates. The experimental results show that the proposed method outperforms the existing methods.

Fuzzy forecasting based on fuzzy-trend logical relationship groups.

PubMed

Chen, Shyi-Ming; Wang, Nai-Yi

2010-10-01

In this paper, we present a new method to predict the Taiwan Stock Exchange Capitalization Weighted Stock Index (TAIEX) based on fuzzy-trend logical relationship groups (FTLRGs). The proposed method divides fuzzy logical relationships into FTLRGs based on the trend of adjacent fuzzy sets appearing in the antecedents of fuzzy logical relationships. First, we apply an automatic clustering algorithm to cluster the historical data into intervals of different lengths. Then, we define fuzzy sets based on these intervals of different lengths. Then, the historical data are fuzzified into fuzzy sets to derive fuzzy logical relationships. Then, we divide the fuzzy logical relationships into FTLRGs for forecasting the TAIEX. Moreover, we also apply the proposed method to forecast the enrollments and the inventory demand, respectively. The experimental results show that the proposed method gets higher average forecasting accuracy rates than the existing methods.

Hardware realization of an SVM algorithm implemented in FPGAs

NASA Astrophysics Data System (ADS)

Wiśniewski, Remigiusz; Bazydło, Grzegorz; Szcześniak, Paweł

2017-08-01

The paper proposes a technique of hardware realization of a space vector modulation (SVM) of state function switching in matrix converter (MC), oriented on the implementation in a single field programmable gate array (FPGA). In MC the SVM method is based on the instantaneous space-vector representation of input currents and output voltages. The traditional computation algorithms usually involve digital signal processors (DSPs) which consumes the large number of power transistors (18 transistors and 18 independent PWM outputs) and "non-standard positions of control pulses" during the switching sequence. Recently, hardware implementations become popular since computed operations may be executed much faster and efficient due to nature of the digital devices (especially concurrency). In the paper, we propose a hardware algorithm of SVM computation. In opposite to the existing techniques, the presented solution applies COordinate Rotation DIgital Computer (CORDIC) method to solve the trigonometric operations. Furthermore, adequate arithmetic modules (that is, sub-devices) used for intermediate calculations, such as code converters or proper sectors selectors (for output voltages and input current) are presented in detail. The proposed technique has been implemented as a design described with the use of Verilog hardware description language. The preliminary results of logic implementation oriented on the Xilinx FPGA (particularly, low-cost device from Artix-7 family from Xilinx was used) are also presented.

An interval logic for higher-level temporal reasoning

NASA Technical Reports Server (NTRS)

Schwartz, R. L.; Melliar-Smith, P. M.; Vogt, F. H.; Plaisted, D. A.

1983-01-01

Prior work explored temporal logics, based on classical modal logics, as a framework for specifying and reasoning about concurrent programs, distributed systems, and communications protocols, and reported on efforts using temporal reasoning primitives to express very high level abstract requirements that a program or system is to satisfy. Based on experience with those primitives, this report describes an Interval Logic that is more suitable for expressing such higher level temporal properties. The report provides a formal semantics for the Interval Logic, and several examples of its use. A description of decision procedures for the logic is also included.

NASA/JPL aircraft SAR operations for 1984 and 1985

NASA Technical Reports Server (NTRS)

Thompson, T. W. (Editor)

1986-01-01

The NASA/JPL aircraft synthetic aperture radar (SAR) was used to conduct major data acquisition expeditions in 1983 through 1985. Substantial improvements to the aircraft SAR were incorporated in 1981 through 1984 resulting in an imaging radar that could simultaneously record all four combinations of linear horizontal and vertical polarization (HH, HV, VH, VV) using computer control of the radar logic, gain setting, and other functions. Data were recorded on high-density digital tapes and processed on a general-purpose computer to produce 10-km square images with 10-m resolution. These digital images yield both the amplitude and phase of the four polarizations. All of the digital images produced so far are archived at the JPL Radar Data Center and are accessible via the Reference Notebook System of that facility. Sites observed in 1984 and 1985 included geological targets in the western United States, as well as agricultural and forestry sites in the Midwest and along the eastern coast. This aircraft radar was destroyed in the CV-990 fire at March Air Force Base on 17 July 1985. It is being rebuilt for flights in l987 and will likely be operated in a mode similar to that described here. The data from 1984 and 1985 as well as those from future expeditions in 1987 and beyond will provide users with a valuable data base for the multifrequency, multipolarization Spaceborne Imaging Radar (SIR-C) scheduled for orbital operations in the early 1990's.

Realisation of all 16 Boolean logic functions in a single magnetoresistance memory cell

NASA Astrophysics Data System (ADS)

Gao, Shuang; Yang, Guang; Cui, Bin; Wang, Shouguo; Zeng, Fei; Song, Cheng; Pan, Feng

2016-06-01

Stateful logic circuits based on next-generation nonvolatile memories, such as magnetoresistance random access memory (MRAM), promise to break the long-standing von Neumann bottleneck in state-of-the-art data processing devices. For the successful commercialisation of stateful logic circuits, a critical step is realizing the best use of a single memory cell to perform logic functions. In this work, we propose a method for implementing all 16 Boolean logic functions in a single MRAM cell, namely a magnetoresistance (MR) unit. Based on our experimental results, we conclude that this method is applicable to any MR unit with a double-hump-like hysteresis loop, especially pseudo-spin-valve magnetic tunnel junctions with a high MR ratio. Moreover, after simply reversing the correspondence between voltage signals and output logic values, this method could also be applicable to any MR unit with a double-pit-like hysteresis loop. These results may provide a helpful solution for the final commercialisation of MRAM-based stateful logic circuits in the near future.Stateful logic circuits based on next-generation nonvolatile memories, such as magnetoresistance random access memory (MRAM), promise to break the long-standing von Neumann bottleneck in state-of-the-art data processing devices. For the successful commercialisation of stateful logic circuits, a critical step is realizing the best use of a single memory cell to perform logic functions. In this work, we propose a method for implementing all 16 Boolean logic functions in a single MRAM cell, namely a magnetoresistance (MR) unit. Based on our experimental results, we conclude that this method is applicable to any MR unit with a double-hump-like hysteresis loop, especially pseudo-spin-valve magnetic tunnel junctions with a high MR ratio. Moreover, after simply reversing the correspondence between voltage signals and output logic values, this method could also be applicable to any MR unit with a double-pit-like hysteresis loop. These results may provide a helpful solution for the final commercialisation of MRAM-based stateful logic circuits in the near future. Electronic supplementary information (ESI) available. See DOI: 10.1039/c6nr03169b

Standard high-reliability integrated circuit logic packaging. [for deep space tracking stations

NASA Technical Reports Server (NTRS)

Slaughter, D. W.

1977-01-01

A family of standard, high-reliability hardware used for packaging digital integrated circuits is described. The design transition from early prototypes to production hardware is covered and future plans are discussed. Interconnections techniques are described as well as connectors and related hardware available at both the microcircuit packaging and main-frame level. General applications information is also provided.

Career Development through Knowledge Management (KM): Be a Chief Information Officer (CIO) for Your Digital Dividend Destiny.

ERIC Educational Resources Information Center

Groff, Warren H.

Career development for the next wave of competent leaders and technically trained workers during e-globalization is one of the most difficult challenges advanced nations face. Career development programs that begin in elementary education and have e-paradigms as a logical choice as the preferred scenario are needed by e-commerce in all its…

Ultra low power CMOS technology

NASA Technical Reports Server (NTRS)

Burr, J.; Peterson, A.

1991-01-01

This paper discusses the motivation, opportunities, and problems associated with implementing digital logic at very low voltages, including the challenge of making use of the available real estate in 3D multichip modules, energy requirements of very large neural networks, energy optimization metrics and their impact on system design, modeling problems, circuit design constraints, possible fabrication process modifications to improve performance, and barriers to practical implementation.

How Gamers Manage Aggression: Situating Skills in Collaborative Computer Games

ERIC Educational Resources Information Center

Bennerstedt, Ulrika; Ivarsson, Jonas; Linderoth, Jonas

2012-01-01

In the discussion on what players learn from digital games, there are two major camps in clear opposition to each other. As one side picks up on negative elements found in games the other side focuses on positive aspects. While the agendas differ, the basic arguments still depart from a shared logic: that engagement in game-related activities…

The mini-O, a digital superhet, or a truly low-cost Omega navigation receiver

NASA Technical Reports Server (NTRS)

Burhans, R. W.

1975-01-01

A quartz tuning fork filter circuit and some unique CMOS clock logic methods provide a very simple OMEGA-VLF receiver with true hyperbolic station pair phase difference outputs. An experimental system was implemented on a single battery-operated circuit board requiring only an external antenna preamplifier, and LOP output recorder. A bench evaluation and preliminary navigation tests indicate the technique is viable and can provide very low-cost OMEGA measurement systems. The method is promising for marine use with small boats in the present form, but might be implemented in conjunction with digital microprocessors for airborne navigation aids.

Introduction to focus issue: intrinsic and designed computation: information processing in dynamical systems--beyond the digital hegemony.

PubMed

Crutchfield, James P; Ditto, William L; Sinha, Sudeshna

2010-09-01

How dynamical systems store and process information is a fundamental question that touches a remarkably wide set of contemporary issues: from the breakdown of Moore's scaling laws--that predicted the inexorable improvement in digital circuitry--to basic philosophical problems of pattern in the natural world. It is a question that also returns one to the earliest days of the foundations of dynamical systems theory, probability theory, mathematical logic, communication theory, and theoretical computer science. We introduce the broad and rather eclectic set of articles in this Focus Issue that highlights a range of current challenges in computing and dynamical systems.

Digital electronic bone growth stimulator

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kronberg, J.W.

1995-05-09

A device is described for stimulating bone tissue by applying a low level alternating current signal directly to the patient`s skin. A crystal oscillator, a binary divider chain and digital logic gates are used to generate the desired waveforms that reproduce the natural electrical characteristics found in bone tissue needed for stimulating bone growth and treating osteoporosis. The device, powered by a battery, contains a switch allowing selection of the correct waveform for bone growth stimulation or osteoporosis treatment so that, when attached to the skin of the patient using standard skin contact electrodes, the correct signal is communicated tomore » the underlying bone structures. 5 figs.« less

Data Grid Management Systems

NASA Technical Reports Server (NTRS)

Moore, Reagan W.; Jagatheesan, Arun; Rajasekar, Arcot; Wan, Michael; Schroeder, Wayne

2004-01-01

The "Grid" is an emerging infrastructure for coordinating access across autonomous organizations to distributed, heterogeneous computation and data resources. Data grids are being built around the world as the next generation data handling systems for sharing, publishing, and preserving data residing on storage systems located in multiple administrative domains. A data grid provides logical namespaces for users, digital entities and storage resources to create persistent identifiers for controlling access, enabling discovery, and managing wide area latencies. This paper introduces data grids and describes data grid use cases. The relevance of data grids to digital libraries and persistent archives is demonstrated, and research issues in data grids and grid dataflow management systems are discussed.

Digital electronic bone growth stimulator

DOEpatents

Kronberg, J.W.

1995-05-09

A device is described for stimulating bone tissue by applying a low level alternating current signal directly to the patient`s skin. A crystal oscillator, a binary divider chain and digital logic gates are used to generate the desired waveforms that reproduce the natural electrical characteristics found in bone tissue needed for stimulating bone growth and treating osteoporosis. The device, powered by a battery, contains a switch allowing selection of the correct waveform for bone growth stimulation or osteoporosis treatment so that, when attached to the skin of the patient using standard skin contact electrodes, the correct signal is communicated to the underlying bone structures. 5 figs.

Three common faults in current practice that influence the validity of data obtained from electronic air pollution instrumentation.

PubMed

Dowd, G; Thomas, R S; Monkman, J L

1975-01-01

Instrumental development is now entering a more logical era, where the former artistic character of electronics is being replaced by cold technology. Because of this, one should be expect more reliability; however, there still exist many weak links in practical application. Digital readout systems and computer processing induce a false sense of security. In reality, it is the sample-measurement relationship that determines an instrument's credibility and not the number of digits on its meter. In describing three faulty practices that greatly influence an instrument's performance, it is hoped that measurement may be more closely related to the sample!

Modern digital flight control system design for VTOL aircraft

NASA Technical Reports Server (NTRS)

Broussard, J. R.; Berry, P. W.; Stengel, R. F.

1979-01-01

Methods for and results from the design and evaluation of a digital flight control system (DFCS) for a CH-47B helicopter are presented. The DFCS employed proportional-integral control logic to provide rapid, precise response to automatic or manual guidance commands while following conventional or spiral-descent approach paths. It contained altitude- and velocity-command modes, and it adapted to varying flight conditions through gain scheduling. Extensive use was made of linear systems analysis techniques. The DFCS was designed, using linear-optimal estimation and control theory, and the effects of gain scheduling are assessed by examination of closed-loop eigenvalues and time responses.