Bidirectional private key exchange using delay-coupled semiconductor lasers.

PubMed

Porte, Xavier; Soriano, Miguel C; Brunner, Daniel; Fischer, Ingo

2016-06-15

We experimentally demonstrate a key exchange cryptosystem based on the phenomenon of identical chaos synchronization. In our protocol, the private key is symmetrically generated by the two communicating partners. It is built up from the synchronized bits occurring between two current-modulated bidirectionally coupled semiconductor lasers with additional self-feedback. We analyze the security of the exchanged key and discuss the amplification of its privacy. We demonstrate private key generation rates up to 11  Mbit/s over a public channel.

Study of bidirectional broadband passive optical network (BPON) using EDFA

NASA Astrophysics Data System (ADS)

Almalaq, Yasser

Optical line terminals (OLTs) and number of optical network units (ONUs) are two main parts of passive optical network (PON). OLT is placed at the central office of the service providers, the ONUs are located near to the end subscribers. When compared with point-to-point design, a PON decreases the number of fiber used and central office components required. Broadband PON (BPON), which is one type of PON, can support high-speed voice, data and video services to subscribers' residential homes and small businesses. In this research, by using erbium doped fiber amplifier (EDFA), the performance of bi-directional BPON is experimented and tested for both downstream and upstream traffic directions. Ethernet PON (E-PON) and gigabit PON (G-PON) are the two other kinds of passive optical network besides BPON. The most beneficial factor of using BPON is it's reduced cost. The cost of the maintenance between the central office and the users' side is suitable because of the use of passive components, such as a splitter in the BPON architecture. In this work, a bidirectional BPON has been analyzed for both downstream and upstream cases by using bit error rate analyzer (BER). BER analyzers test three factors that are the maximum Q factor, minimum bit error rate, and eye height. In other words, parameters such as maximum Q factor, minimum bit error rate, and eye height can be analyzed utilized a BER tester. Passive optical components such as a splitter, optical circulator, and filters have been used in modeling and simulations. A 12th edition Optiwave simulator has been used in order to analyze the bidirectional BPON system. The system has been tested under several conditions such as changing the fiber length, extinction ratio, dispersion, and coding technique. When a long optical fiber above 40km was used, an EDFA was used in order to improve the quality of the signal.

Heterogeneous wireless/wireline optical access networks with the R-EAT as backend component

NASA Astrophysics Data System (ADS)

Hagedorn, Klaus; Gindera, Ralf; Stohr, Andreas; Jager, Dieter

2004-09-01

A heterogeneous wireless/wireline optical transmission link using a reflection type electroabsorption transceiver (R-EAT) is presented. Simultaneous transmission of full-duplex broadband wireless LAN (WLAN) channels and 1Gb/s base band data is experimentally demonstrated. The system link employs sub-carrier multiplexing (SCM) and two optical channels for full duplex transmission of various analog WLAN channels and downlink digital base band data. The developed link architecture is suitable for simultaneous transmission of broadband wireline and wireless signals, it enables the coexistence and interoperability between wireline and wireless access technologies. The developed R-EAT component employed in this wireline/wireless access system, features "single-chip-component" base stations in access networks with star type topology where only a single optical fiber is used for bidirectional optical transmission. The R-EAT can be used within the optical C-band (1530- 1560nm) and is suitable for (D)WDM networks. Bit error rate measurements demonstrate the capabilities of the R-EAT for 1Gb/s base band transmission. The analog performance for WLAN transmission is characterised by a spurious free dynamic range (SFDR) of more than 75dB and 90dB for uplink and downlink transmission, respectively. The link gain for uplink and downlink transmission is -42dB and -37dB, respectively. The demonstrates the analog performances of the R-EAT for being used in wireless access networks such as W-LAN.

Analog Nonvolatile Computer Memory Circuits

NASA Technical Reports Server (NTRS)

MacLeod, Todd

2007-01-01

In nonvolatile random-access memory (RAM) circuits of a proposed type, digital data would be stored in analog form in ferroelectric field-effect transistors (FFETs). This type of memory circuit would offer advantages over prior volatile and nonvolatile types: In a conventional complementary metal oxide/semiconductor static RAM, six transistors must be used to store one bit, and storage is volatile in that data are lost when power is turned off. In a conventional dynamic RAM, three transistors must be used to store one bit, and the stored bit must be refreshed every few milliseconds. In contrast, in a RAM according to the proposal, data would be retained when power was turned off, each memory cell would contain only two FFETs, and the cell could store multiple bits (the exact number of bits depending on the specific design). Conventional flash memory circuits afford nonvolatile storage, but they operate at reading and writing times of the order of thousands of conventional computer memory reading and writing times and, hence, are suitable for use only as off-line storage devices. In addition, flash memories cease to function after limited numbers of writing cycles. The proposed memory circuits would not be subject to either of these limitations. Prior developmental nonvolatile ferroelectric memories are limited to one bit per cell, whereas, as stated above, the proposed memories would not be so limited. The design of a memory circuit according to the proposal must reflect the fact that FFET storage is only partly nonvolatile, in that the signal stored in an FFET decays gradually over time. (Retention times of some advanced FFETs exceed ten years.) Instead of storing a single bit of data as either a positively or negatively saturated state in a ferroelectric device, each memory cell according to the proposal would store two values. The two FFETs in each cell would be denoted the storage FFET and the control FFET. The storage FFET would store an analog signal value, between the positive and negative FFET saturation values. This signal value would represent a numerical value of interest corresponding to multiple bits: for example, if the memory circuit were designed to distinguish among 16 different analog values, then each cell could store 4 bits. Simultaneously with writing the signal value in the storage FFET, a negative saturation signal value would be stored in the control FFET. The decay of this control-FFET signal from the saturation value would serve as a model of the decay, for use in regenerating the numerical value of interest from its decaying analog signal value. The memory circuit would include addressing, reading, and writing circuitry that would have features in common with the corresponding parts of other memory circuits, but would also have several distinctive features. The writing circuitry would include a digital-to-analog converter (DAC); the reading circuitry would include an analog-to-digital converter (ADC). For writing a numerical value of interest in a given cell, that cell would be addressed, the saturation value would be written in the control FFET in that cell, and the non-saturation analog value representing the numerical value of interest would be generated by use of the DAC and stored in the storage FFET in that cell. For reading the numerical value of interest stored in a given cell, the cell would be addressed, the ADC would convert the decaying control and storage analog signal values to digital values, and an associated fast digital processing circuit would regenerate the numerical value from digital values.

A 14-bit 40-MHz analog front end for CCD application

NASA Astrophysics Data System (ADS)

Jingyu, Wang; Zhangming, Zhu; Shubin, Liu

2016-06-01

A 14-bit, 40-MHz analog front end (AFE) for CCD scanners is analyzed and designed. The proposed system incorporates a digitally controlled wideband variable gain amplifier (VGA) with nearly 42 dB gain range, a correlated double sampler (CDS) with programmable gain functionality, a 14-bit analog-to-digital converter and a programmable timing core. To achieve the maximum dynamic range, the VGA proposed here can linearly amplify the input signal in a gain range from -1.08 to 41.06 dB in 6.02 dB step with a constant bandwidth. A novel CDS takes image information out of noise, and further amplifies the signal accurately in a gain range from 0 to 18 dB in 0.035 dB step. A 14-bit ADC is adopted to quantify the analog signal with optimization in power and linearity. An internal timing core can provide flexible timing for CCD arrays, CDS and ADC. The proposed AFE was fabricated in SMIC 0.18 μm CMOS process. The whole circuit occupied an active area of 2.8 × 4.8 mm2 and consumed 360 mW. When the frequency of input signal is 6.069 MHz, and the sampling frequency is 40 MHz, the signal to noise and distortion (SNDR) is 70.3 dB, the effective number of bits is 11.39 bit. Project supported by the National Natural Science Foundation of China (Nos. 61234002, 61322405, 61306044, 61376033), the National High-Tech Program of China (No. 2013AA014103), and the Opening Project of Science and Technology on Reliability Physics and Application Technology of Electronic Component Laboratory (No. ZHD201302).

Bidirectional chaos communication between two outer semiconductor lasers coupled mutually with a central semiconductor laser.

PubMed

Li, Ping; Wu, Jia-Gui; Wu, Zheng-Mao; Lin, Xiao-Dong; Deng, Dao; Liu, Yu-Ran; Xia, Guang-Qiong

2011-11-21

Based on a linear chain composed of a central semiconductor laser and two outer semiconductor lasers, chaos synchronization and bidirectional communication between two outer lasers have been investigated under the case that the central laser and the two outer lasers are coupled mutually, whereas there exists no coupling between the two outer lasers. The simulation results show that high-quality and stable isochronal synchronization between the two outer lasers can be achieved, while the cross-correlation coefficients between the two outer lasers and the central laser are very low under proper operation condition. Based on the high performance chaos synchronization between the two outer lasers, message bidirectional transmissions of bit rates up to 20 Gbit/s can be realized through adopting a novel decoding scheme which is different from that based on chaos pass filtering effect. Furthermore, the security of bidirectional communication is also analyzed. © 2011 Optical Society of America

Bidirectional ultradense WDM for metro networks adopting the beat-frequency-locking method

NASA Astrophysics Data System (ADS)

Kim, Sang-Yuep; Lee, Jae-Hoon; Lee, Jae-Seung

2003-10-01

We present a technique to increase the spectral efficiencies of metro networks by using channel-interleaved bidirectional ultradense wavelength-division multiplexing (WDM) within each customer's optical band. As a demonstration, we transmit 12.5-GHz-spaced 8×10 Gbit/s channels achieving spectral efficiency as high as 0.8 bit/s/Hz with a 25-GHz WDM demultiplexer. The beat-frequency-locking method is used to stabilize the channel frequencies within +/-200 MHz, which is far more accurate than with conventional wavelength lockers.

On Multiple AER Handshaking Channels Over High-Speed Bit-Serial Bidirectional LVDS Links With Flow-Control and Clock-Correction on Commercial FPGAs for Scalable Neuromorphic Systems.

PubMed

Yousefzadeh, Amirreza; Jablonski, Miroslaw; Iakymchuk, Taras; Linares-Barranco, Alejandro; Rosado, Alfredo; Plana, Luis A; Temple, Steve; Serrano-Gotarredona, Teresa; Furber, Steve B; Linares-Barranco, Bernabe

2017-10-01

Address event representation (AER) is a widely employed asynchronous technique for interchanging "neural spikes" between different hardware elements in neuromorphic systems. Each neuron or cell in a chip or a system is assigned an address (or ID), which is typically communicated through a high-speed digital bus, thus time-multiplexing a high number of neural connections. Conventional AER links use parallel physical wires together with a pair of handshaking signals (request and acknowledge). In this paper, we present a fully serial implementation using bidirectional SATA connectors with a pair of low-voltage differential signaling (LVDS) wires for each direction. The proposed implementation can multiplex a number of conventional parallel AER links for each physical LVDS connection. It uses flow control, clock correction, and byte alignment techniques to transmit 32-bit address events reliably over multiplexed serial connections. The setup has been tested using commercial Spartan6 FPGAs attaining a maximum event transmission speed of 75 Meps (Mega events per second) for 32-bit events at a line rate of 3.0 Gbps. Full HDL codes (vhdl/verilog) and example demonstration codes for the SpiNNaker platform will be made available.

Recognition of the optical packet header for two channels utilizing the parallel reservoir computing based on a semiconductor ring laser

NASA Astrophysics Data System (ADS)

Bao, Xiurong; Zhao, Qingchun; Yin, Hongxi; Qin, Jie

2018-05-01

In this paper, an all-optical parallel reservoir computing (RC) system with two channels for the optical packet header recognition is proposed and simulated, which is based on a semiconductor ring laser (SRL) with the characteristic of bidirectional light paths. The parallel optical loops are built through the cross-feedback of the bidirectional light paths where every optical loop can independently recognize each injected optical packet header. Two input signals are mapped and recognized simultaneously by training all-optical parallel reservoir, which is attributed to the nonlinear states in the laser. The recognition of optical packet headers for two channels from 4 bits to 32 bits is implemented through the simulation optimizing system parameters and therefore, the optimal recognition error ratio is 0. Since this structure can combine with the wavelength division multiplexing (WDM) optical packet switching network, the wavelength of each channel of optical packet headers for recognition can be different, and a better recognition result can be obtained.

Practical application of a bidirectional microwave photonic filter: simultaneous transmission of analog TV signals

NASA Astrophysics Data System (ADS)

Correa-Mena, Ana Gabriela; Zaldívar-Huerta, Ignacio E.; Abril García, Jose Humberto; García-Juárez, Alejandro; Vera-Marquina, Alicia

2016-10-01

A practical application of a bidirectional microwave photonic filter (MPF) to transmit simultaneous analog TV signals coded on microwave carriers is experimentally demonstrated. The frequency response of the bidirectional MPF is obtained by the interaction of an externally modulated multimode laser diode emitting at 1.55 μm associated to the free-spectral range of the optical source, the chromatic dispersion parameter of the optical fiber, as well as the length of the optical link. The filtered microwave bandpass window generated around 2 GHz is used as electrical carrier in order to simultaneously transmit TV signals of 67.25 and 61.25 MHz in both directions. The obtained signal-to-noise ratios for the transmitted signals of 67.25 and 61.25 MHz are 37.62 and 44.77 dB, respectively.

Photonic Modulation Using Bi-Directional Diamond Shaped Ring Lasers at 1550 NM

DTIC Science & Technology

2007-04-01

modes for (a) 1% of the relaxation running oscillation frequency and (b) just below free running relaxation oscillation frequency ... List of Tables Table 1. Power requirements needed for a ring laser based flash architecture. Table 2. Achievable bits using 10 mW and

Experimental realization of the analogy of quantum dense coding in classical optics

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yang, Zhenwei; Sun, Yifan; Li, Pengyun

2016-06-15

We report on the experimental realization of the analogy of quantum dense coding in classical optical communication using classical optical correlations. Compared to quantum dense coding that uses pairs of photons entangled in polarization, we find that the proposed design exhibits many advantages. Considering that it is convenient to realize in optical communication, the attainable channel capacity in the experiment for dense coding can reach 2 bits, which is higher than that of the usual quantum coding capacity (1.585 bits). This increased channel capacity has been proven experimentally by transmitting ASCII characters in 12 quaternary digitals instead of the usualmore » 24 bits.« less

Low speed phaselock speed control system. [for brushless dc motor

NASA Technical Reports Server (NTRS)

Fulcher, R. W.; Sudey, J. (Inventor)

1975-01-01

A motor speed control system for an electronically commutated brushless dc motor is provided which includes a phaselock loop with bidirectional torque control for locking the frequency output of a high density encoder, responsive to actual speed conditions, to a reference frequency signal, corresponding to the desired speed. The system includes a phase comparator, which produces an output in accordance with the difference in phase between the reference and encoder frequency signals, and an integrator-digital-to-analog converter unit, which converts the comparator output into an analog error signal voltage. Compensation circuitry, including a biasing means, is provided to convert the analog error signal voltage to a bidirectional error signal voltage which is utilized by an absolute value amplifier, rotational decoder, power amplifier-commutators, and an arrangement of commutation circuitry.

A study on airborne integrated display system and human information processing

NASA Technical Reports Server (NTRS)

Mizumoto, K.; Iwamoto, H.; Shimizu, S.; Kuroda, I.

1983-01-01

The cognitive behavior of pilots was examined in an experiment involving mock ups of an eight display electronic attitude direction indicator for an airborne integrated display. Displays were presented in digital, analog digital, and analog format to experienced pilots. Two tests were run, one involving the speed of memorization in a single exposure and the other comprising two five second exposures spaced 30 sec apart. Errors increased with the speed of memorization. Generally, the analog information was assimilated faster than the digital data, with regard to the response speed. Information processing was quantified as 25 bits for the first five second exposure and 15 bits during the second.

A design method for high performance seismic data acquisition based on oversampling delta-sigma modulation

NASA Astrophysics Data System (ADS)

Gao, Shanghua; Xue, Bing

2017-04-01

The dynamic range of the currently most widely used 24-bit seismic data acquisition devices is 10-20 dB lower than that of broadband seismometers, and this can affect the completeness of seismic waveform recordings under certain conditions. However, this problem is not easy to solve because of the lack of analog to digital converter (ADC) chips with more than 24 bits in the market. So the key difficulties for higher-resolution data acquisition devices lie in achieving more than 24-bit ADC circuit. In the paper, we propose a method in which an adder, an integrator, a digital to analog converter chip, a field-programmable gate array, and an existing low-resolution ADC chip are used to build a third-order 16-bit oversampling delta-sigma modulator. This modulator is equipped with a digital decimation filter, thus forming a complete analog to digital converting circuit. Experimental results show that, within the 0.1-40 Hz frequency range, the circuit board's dynamic range reaches 158.2 dB, its resolution reaches 25.99 dB, and its linearity error is below 2.5 ppm, which is better than what is achieved by the commercial 24-bit ADC chips ADS1281 and CS5371. This demonstrates that the proposed method may alleviate or even solve the amplitude-limitation problem that broadband observation systems so commonly have to face during strong earthquakes.

An integrated interface for peripheral neural system recording and stimulation: system design, electrical tests and in-vivo results.

PubMed

Carboni, Caterina; Bisoni, Lorenzo; Carta, Nicola; Puddu, Roberto; Raspopovic, Stanisa; Navarro, Xavier; Raffo, Luigi; Barbaro, Massimo

2016-04-01

The prototype of an electronic bi-directional interface between the Peripheral Nervous System (PNS) and a neuro-controlled hand prosthesis is presented. The system is composed of 2 integrated circuits: a standard CMOS device for neural recording and a HVCMOS device for neural stimulation. The integrated circuits have been realized in 2 different 0.35μ m CMOS processes available from ams. The complete system incorporates 8 channels each including the analog front-end, the A/D conversion, based on a sigma delta architecture and a programmable stimulation module implemented as a 5-bit current DAC; two voltage boosters supply the output stimulation stage with a programmable voltage scalable up to 17V. Successful in-vivo experiments with rats having a TIME electrode implanted in the sciatic nerve were carried out, showing the capability of recording neural signals in the tens of microvolts, with a global noise of 7μ V r m s , and to selectively elicit the tibial and plantar muscles using different active sites of the electrode.

Correlation Between Analog Noise Measurements and the Expected Bit Error Rate of a Digital Signal Propagating Through Passive Components

NASA Technical Reports Server (NTRS)

Warner, Joseph D.; Theofylaktos, Onoufrios

2012-01-01

A method of determining the bit error rate (BER) of a digital circuit from the measurement of the analog S-parameters of the circuit has been developed. The method is based on the measurement of the noise and the standard deviation of the noise in the S-parameters. Once the standard deviation and the mean of the S-parameters are known, the BER of the circuit can be calculated using the normal Gaussian function.

A Fast Multiple Sampling Method for Low-Noise CMOS Image Sensors With Column-Parallel 12-bit SAR ADCs.

PubMed

Kim, Min-Kyu; Hong, Seong-Kwan; Kwon, Oh-Kyong

2015-12-26

This paper presents a fast multiple sampling method for low-noise CMOS image sensor (CIS) applications with column-parallel successive approximation register analog-to-digital converters (SAR ADCs). The 12-bit SAR ADC using the proposed multiple sampling method decreases the A/D conversion time by repeatedly converting a pixel output to 4-bit after the first 12-bit A/D conversion, reducing noise of the CIS by one over the square root of the number of samplings. The area of the 12-bit SAR ADC is reduced by using a 10-bit capacitor digital-to-analog converter (DAC) with four scaled reference voltages. In addition, a simple up/down counter-based digital processing logic is proposed to perform complex calculations for multiple sampling and digital correlated double sampling. To verify the proposed multiple sampling method, a 256 × 128 pixel array CIS with 12-bit SAR ADCs was fabricated using 0.18 μm CMOS process. The measurement results shows that the proposed multiple sampling method reduces each A/D conversion time from 1.2 μs to 0.45 μs and random noise from 848.3 μV to 270.4 μV, achieving a dynamic range of 68.1 dB and an SNR of 39.2 dB.

Optical-analog-to-digital conversion based on successive-like approximations in octagonal-shape photonic crystal ring resonators

NASA Astrophysics Data System (ADS)

Tavousi, A.; Mansouri-Birjandi, M. A.

2018-02-01

Implementing intensity-dependent Kerr-like nonlinearity in octagonal-shape photonic crystal ring resonators (OSPCRRs), a new class of optical analog-to-digital converters (ADCs) with low power consumption is presented. Due to its size dependent refractive index, Silicon (Si) nanocrystal is used as nonlinear medium in the proposed ADC. Coding system of optical ADC is based on successive-like approximations which requires only one quantization level to represent each single bit, despite of conventional ADCs that require at least two distinct levels for each bit. Each is representing bit of optical ADC is formed by vertically alignment of double rings of OSPCRRs (DR-OSPCRR) and cascading m number of DR-OSPCRR, forms an m bit ADC. Investigating different parameters of DR-OSPCRR such as refractive indices of rings, lattice refractive index, and coupling coefficients of waveguide-to-ring and ring-to-ring, the ADC's threshold power is tuned. Increasing the number of bits of ADC, increases the overall power consumption of ADC. One can arrange to have any number of bits for this ADC, as long as the power levels are treated carefully. Finite difference time domain (FDTD) in-house codes were used to evaluate the ADC's effectiveness.

Serial-to-parallel color-TV converter

NASA Technical Reports Server (NTRS)

Doak, T. W.; Merwin, R. B.; Zuckswert, S. E.; Sepper, W.

1976-01-01

Solid analog-to-digital converter eliminates flicker and problems with time base stability and gain variation in sequential color TV cameras. Device includes 3-bit delta modulator; two-field memory; timing, switching, and sync network; and three 3-bit delta demodulators

A 1000+ channel bionic communication system.

PubMed

Schulman, Joseph H; Mobley, J Phil; Wolfe, James; Stover, Howard; Krag, Adrian

2006-01-01

The wireless electronic nervous system interface known as the functional electrical stimulation-battery powered bion system is being developed at the Alfred Mann Foundation. It contains a real-time propagated wave micro-powered multichannel communication system. This system is designed to send bi-directional messages between an external master controller unit (MCU), and each one of a group of injectable stimulator-sensor battery powered bion implants (BPB). The system is capable of communicating in each direction about 90 times per second using a structure of 850 time slots within a repeating 11 millisecond time window. The system's total Time Division Multiple Access (TDMA) communication capability is about 77,000 two-way communications per second on a single 5 MHz wide radio channel. Each time slot can be used by one BPB, or shared alternately by two or more BPBs. Each bidirectional communication consists of a 15 data bit message sent from the MCU sequentially to each BPB and 10 data bit message sent sequentially from each BPB to the MCU. Redundancy bits are included to provide error detection and correction. This communication system is designed to draw only a few microamps from the 3.6 volt, 3.0 mAHr lithium ion (LiIon) battery contained in each BPB, and the majority of the communications circuitry is contained within a 1.4x5 mm integrated circuit.

Fault-tolerant corrector/detector chip for high-speed data processing

DOEpatents

Andaleon, David D.; Napolitano, Jr., Leonard M.; Redinbo, G. Robert; Shreeve, William O.

1994-01-01

An internally fault-tolerant data error detection and correction integrated circuit device (10) and a method of operating same. The device functions as a bidirectional data buffer between a 32-bit data processor and the remainder of a data processing system and provides a 32-bit datum is provided with a relatively short eight bits of data-protecting parity. The 32-bits of data by eight bits of parity is partitioned into eight 4-bit nibbles and two 4-bit nibbles, respectively. For data flowing towards the processor the data and parity nibbles are checked in parallel and in a single operation employing a dual orthogonal basis technique. The dual orthogonal basis increase the efficiency of the implementation. Any one of ten (eight data, two parity) nibbles are correctable if erroneous, or two different erroneous nibbles are detectable. For data flowing away from the processor the appropriate parity nibble values are calculated and transmitted to the system along with the data. The device regenerates parity values for data flowing in either direction and compares regenerated to generated parity with a totally self-checking equality checker. As such, the device is self-validating and enabled to both detect and indicate an occurrence of an internal failure. A generalization of the device to protect 64-bit data with 16-bit parity to protect against byte-wide errors is also presented.

Fault-tolerant corrector/detector chip for high-speed data processing

DOEpatents

Andaleon, D.D.; Napolitano, L.M. Jr.; Redinbo, G.R.; Shreeve, W.O.

1994-03-01

An internally fault-tolerant data error detection and correction integrated circuit device and a method of operating same is described. The device functions as a bidirectional data buffer between a 32-bit data processor and the remainder of a data processing system and provides a 32-bit datum with a relatively short eight bits of data-protecting parity. The 32-bits of data by eight bits of parity is partitioned into eight 4-bit nibbles and two 4-bit nibbles, respectively. For data flowing towards the processor the data and parity nibbles are checked in parallel and in a single operation employing a dual orthogonal basis technique. The dual orthogonal basis increase the efficiency of the implementation. Any one of ten (eight data, two parity) nibbles are correctable if erroneous, or two different erroneous nibbles are detectable. For data flowing away from the processor the appropriate parity nibble values are calculated and transmitted to the system along with the data. The device regenerates parity values for data flowing in either direction and compares regenerated to generated parity with a totally self-checking equality checker. As such, the device is self-validating and enabled to both detect and indicate an occurrence of an internal failure. A generalization of the device to protect 64-bit data with 16-bit parity to protect against byte-wide errors is also presented. 8 figures.

Design of a Multi-Level/Analog Ferroelectric Memory Device

NASA Technical Reports Server (NTRS)

MacLeod, Todd C.; Phillips, Thomas A.; Ho, Fat D.

2006-01-01

Increasing the memory density and utilizing the dove1 characteristics of ferroelectric devices is important in making ferroelectric memory devices more desirable to the consumer. This paper describes a design that allows multiple levels to be stored in a ferroelectric based memory cell. It can be used to store multiple bits or analog values in a high speed nonvolatile memory. The design utilizes the hysteresis characteristic of ferroelectric transistors to store an analog value in the memory cell. The design also compensates for the decay of the polarization of the ferroelectric material over time. This is done by utilizing a pair of ferroelectric transistors to store the data. One transistor is used as a reference to determine the amount of decay that has occurred since the pair was programmed. The second transistor stores the analog value as a polarization value between zero and saturated. The design allows digital data to be stored as multiple bits in each memory cell. The number of bits per cell that can be stored will vary with the decay rate of the ferroelectric transistors and the repeatability of polarization between transistors. It is predicted that each memory cell may be able to store 8 bits or more. The design is based on data taken from actual ferroelectric transistors. Although the circuit has not been fabricated, a prototype circuit is now under construction. The design of this circuit is different than multi-level FLASH or silicon transistor circuits. The differences between these types of circuits are described in this paper. This memory design will be useful because it allows higher memory density, compensates for the environmental and ferroelectric aging processes, allows analog values to be directly stored in memory, compensates for the thermal and radiation environments associated with space operations, and relies only on existing technologies.

Bidirectional and simultaneous FTTX/Ethernet services using RSOA based remodulation and polarization multiplexing technique

NASA Astrophysics Data System (ADS)

Das, Anindya S.; Patra, Ardhendu S.

2015-08-01

A bidirectional and simultaneous transmission of Ethernet, FTTX services through single optical carrier wavelength employing polarization multiplexing technique in the transmitter end and the user end. 10 Gbps and 2.5 Gbps datarates are transmitted over 50 km single mode fiber employing POLMUX technique at OLT and ONU to provide Ethernet and FTTX services concurrently to the user. Reflective semiconductor optical amplifier is used to reuse and remodulate the downlink signal to uplink transmission. The upstream and the downstream transmission performances are observed by the bit error rate values and the eye diagrams obtained by the BER analyzer.

A Fast Multiple Sampling Method for Low-Noise CMOS Image Sensors With Column-Parallel 12-bit SAR ADCs

PubMed Central

Kim, Min-Kyu; Hong, Seong-Kwan; Kwon, Oh-Kyong

2015-01-01

This paper presents a fast multiple sampling method for low-noise CMOS image sensor (CIS) applications with column-parallel successive approximation register analog-to-digital converters (SAR ADCs). The 12-bit SAR ADC using the proposed multiple sampling method decreases the A/D conversion time by repeatedly converting a pixel output to 4-bit after the first 12-bit A/D conversion, reducing noise of the CIS by one over the square root of the number of samplings. The area of the 12-bit SAR ADC is reduced by using a 10-bit capacitor digital-to-analog converter (DAC) with four scaled reference voltages. In addition, a simple up/down counter-based digital processing logic is proposed to perform complex calculations for multiple sampling and digital correlated double sampling. To verify the proposed multiple sampling method, a 256 × 128 pixel array CIS with 12-bit SAR ADCs was fabricated using 0.18 μm CMOS process. The measurement results shows that the proposed multiple sampling method reduces each A/D conversion time from 1.2 μs to 0.45 μs and random noise from 848.3 μV to 270.4 μV, achieving a dynamic range of 68.1 dB and an SNR of 39.2 dB. PMID:26712765

A sub-microwatt asynchronous level-crossing ADC for biomedical applications.

PubMed

Li, Yongjia; Zhao, Duan; Serdijn, Wouter A

2013-04-01

A continuous-time level-crossing analog-to-digital converter (LC-ADC) for biomedical applications is presented. When compared to uniform-sampling (US) ADCs LC-ADCs generate fewer samples for various sparse biomedical signals. Lower power consumption and reduced design complexity with respect to conventional LC-ADCs are achieved due to: 1) replacing the n-bit digital-to-analog converter (DAC) with a 1-bit DAC; 2) splitting the level-crossing detections; and 3) fixing the comparison window. Designed and implemented in 0.18 μm CMOS technology, the proposed ADC uses a chip area of 220 × 203 μm(2). Operating from a supply voltage of 0.8 V, the ADC consumes 313-582 nW from 5 Hz to 5 kHz and achieves an ENOB up to 7.9 bits.

Experimental results in evolutionary fault-recovery for field programmable analog devices

NASA Technical Reports Server (NTRS)

Zebulum, Ricardo S.; Keymeulen, Didier; Duong, Vu; Guo, Xin; Ferguson, M. I.; Stoica, Adrian

2003-01-01

This paper presents experimental results of fast intrinsic evolutionary design and evolutionary fault recovery of a 4-bit Digital to Analog Converter (DAC) using the JPL stand-alone board-level evolvable system (SABLES).

Highly linear, sensitive analog-to-digital converter

NASA Technical Reports Server (NTRS)

Cox, J.; Finley, W. R.

1969-01-01

Analog-to-digital converter converts 10 volt full scale input signal into 13 bit digital output. Advantages include high sensitivity, linearity, low quantitizing error, high resistance to mechanical shock and vibration loads, and temporary data storage capabilities.

Data recording and playback on video tape--a multi-channel analog interface for a digital audio processor system.

PubMed

Blaettler, M; Bruegger, A; Forster, I C; Lehareinger, Y

1988-03-01

The design of an analog interface to a digital audio signal processor (DASP)-video cassette recorder (VCR) system is described. The complete system represents a low-cost alternative to both FM instrumentation tape recorders and multi-channel chart recorders. The interface or DASP input-output unit described in this paper enables the recording and playback of up to 12 analog channels with a maximum of 12 bit resolution and a bandwidth of 2 kHz per channel. Internal control and timing in the recording component of the interface is performed using ROMs which can be reprogrammed to suit different analog-to-digital converter hardware. Improvement in the bandwidth specifications is possible by connecting channels in parallel. A parallel 16 bit data output port is provided for direct transfer of the digitized data to a computer.

Implementation of high-resolution time-to-digital converter in 8-bit microcontrollers.

PubMed

Bengtsson, Lars E

2012-04-01

This paper will demonstrate how a time-to-digital converter (TDC) with sub-nanosecond resolution can be implemented into an 8-bit microcontroller using so called "direct" methods. This means that a TDC is created using only five bidirectional digital input-output-pins of a microcontroller and a few passive components (two resistors, a capacitor, and a diode). We will demonstrate how a TDC for the range 1-10 μs is implemented with 0.17 ns resolution. This work will also show how to linearize the output by combining look-up tables and interpolation. © 2012 American Institute of Physics

High resolution A/D conversion based on piecewise conversion at lower resolution

DOEpatents

Terwilliger, Steve [Albuquerque, NM

2012-06-05

Piecewise conversion of an analog input signal is performed utilizing a plurality of relatively lower bit resolution A/D conversions. The results of this piecewise conversion are interpreted to achieve a relatively higher bit resolution A/D conversion without sampling frequency penalty.

An Ultra-Low Power Charge Redistribution Successive Approximation Register A/D Converter for Biomedical Applications.

PubMed

Koppa, Santosh; Mohandesi, Manouchehr; John, Eugene

2016-12-01

Power consumption is one of the key design constraints in biomedical devices such as pacemakers that are powered by small non rechargeable batteries over their entire life time. In these systems, Analog to Digital Convertors (ADCs) are used as interface between analog world and digital domain and play a key role. In this paper we present the design of an 8-bit Charge Redistribution Successive Approximation Register (CR-SAR) analog to digital converter in standard TSMC 0.18μm CMOS technology for low power and low data rate devices such as pacemakers. The 8-bit optimized CR-SAR ADC achieves low power of less than 250nW with conversion rate of 1KB/s. This ADC achieves integral nonlinearity (INL) and differential nonlinearity (DNL) less than 0.22 least significant bit (LSB) and less than 0.04 LSB respectively as compared to the standard requirement for the INL and DNL errors to be less than 0.5 LSB. The designed ADC operates at 1V supply voltage converting input ranging from 0V to 250mV.

A Low-cost 4 Bit, 10 Giga-samples-per-second Analog-to-digital Converter Printed Circuit Board Assembly for FPGA-based Backends

NASA Astrophysics Data System (ADS)

Jiang, Homin; Yu, Chen-Yu; Kubo, Derek; Chen, Ming-Tang; Guzzino, Kim

2016-11-01

In this study, a 4 bit, 10 giga-samples-per-second analog-to-digital converter (ADC) printed circuit board assembly (PCBA) was designed, manufactured, and characterized for digitizing radio telescopes. For this purpose, an Adsantec ANST7120A-KMA flash ADC chip was used. Together with the field-programmable gate array platform, developed by the Collaboration for Astronomy Signal Processing and Electronics Research community, the PCBA enables data acquisition with a wide bandwidth and simplifies the intermediate frequency section. In the current version, the PCBA and the chip exhibit an analog bandwidth of 10 GHz (3 dB loss) and 20 GHz, respectively, which facilitates second, third, and even fourth Nyquist sampling. The following average performance parameters were obtained from the first and second Nyquist zones of the three boards: a spurious-free dynamic range of 31.35/30.45 dB, a signal-to-noise and distortion ratio of 22.95/21.83 dB, and an effective number of bits of 3.65/3.43, respectively.

Shuttle bit rate synchronizer. [signal to noise ratios and error analysis

NASA Technical Reports Server (NTRS)

Huey, D. C.; Fultz, G. L.

1974-01-01

A shuttle bit rate synchronizer brassboard unit was designed, fabricated, and tested, which meets or exceeds the contractual specifications. The bit rate synchronizer operates at signal-to-noise ratios (in a bit rate bandwidth) down to -5 dB while exhibiting less than 0.6 dB bit error rate degradation. The mean acquisition time was measured to be less than 2 seconds. The synchronizer is designed around a digital data transition tracking loop whose phase and data detectors are integrate-and-dump filters matched to the Manchester encoded bits specified. It meets the reliability (no adjustments or tweaking) and versatility (multiple bit rates) of the shuttle S-band communication system through an implementation which is all digital after the initial stage of analog AGC and A/D conversion.

Bidirectional fiber-wireless and fiber-IVLLC integrated system based on polarization-orthogonal modulation scheme.

PubMed

Lu, Hai-Han; Li, Chung-Yi; Chen, Hwan-Wei; Ho, Chun-Ming; Cheng, Ming-Te; Huang, Sheng-Jhe; Yang, Zih-Yi; Lin, Xin-Yao

2016-07-25

A bidirectional fiber-wireless and fiber-invisible laser light communication (IVLLC) integrated system that employs polarization-orthogonal modulation scheme for hybrid cable television (CATV)/microwave (MW)/millimeter-wave (MMW)/baseband (BB) signal transmission is proposed and demonstrated. To our knowledge, it is the first one that adopts a polarization-orthogonal modulation scheme in a bidirectional fiber-wireless and fiber-IVLLC integrated system with hybrid CATV/MW/MMW/BB signal. For downlink transmission, carrier-to-noise ratio (CNR), composite second-order (CSO), composite triple-beat (CTB), and bit error rate (BER) perform well over 40-km single-mode fiber (SMF) and 10-m RF/50-m optical wireless transport scenarios. For uplink transmission, good BER performance is obtained over 40-km SMF and 50-m optical wireless transport scenario. Such a bidirectional fiber-wireless and fiber-IVLLC integrated system for hybrid CATV/MW/MMW/BB signal transmission will be an attractive alternative for providing broadband integrated services, including CATV, Internet, and telecommunication services. It is shown to be a prominent one to present the advancements for the convergence of fiber backbone and RF/optical wireless feeder.

Resolution-Adaptive Hybrid MIMO Architectures for Millimeter Wave Communications

NASA Astrophysics Data System (ADS)

Choi, Jinseok; Evans, Brian L.; Gatherer, Alan

2017-12-01

In this paper, we propose a hybrid analog-digital beamforming architecture with resolution-adaptive ADCs for millimeter wave (mmWave) receivers with large antenna arrays. We adopt array response vectors for the analog combiners and derive ADC bit-allocation (BA) solutions in closed form. The BA solutions reveal that the optimal number of ADC bits is logarithmically proportional to the RF chain's signal-to-noise ratio raised to the 1/3 power. Using the solutions, two proposed BA algorithms minimize the mean square quantization error of received analog signals under a total ADC power constraint. Contributions of this paper include 1) ADC bit-allocation algorithms to improve communication performance of a hybrid MIMO receiver, 2) approximation of the capacity with the BA algorithm as a function of channels, and 3) a worst-case analysis of the ergodic rate of the proposed MIMO receiver that quantifies system tradeoffs and serves as the lower bound. Simulation results demonstrate that the BA algorithms outperform a fixed-ADC approach in both spectral and energy efficiency, and validate the capacity and ergodic rate formula. For a power constraint equivalent to that of fixed 4-bit ADCs, the revised BA algorithm makes the quantization error negligible while achieving 22% better energy efficiency. Having negligible quantization error allows existing state-of-the-art digital beamformers to be readily applied to the proposed system.

Long-term potentiation expands information content of hippocampal dentate gyrus synapses.

PubMed

Bromer, Cailey; Bartol, Thomas M; Bowden, Jared B; Hubbard, Dusten D; Hanka, Dakota C; Gonzalez, Paola V; Kuwajima, Masaaki; Mendenhall, John M; Parker, Patrick H; Abraham, Wickliffe C; Sejnowski, Terrence J; Harris, Kristen M

2018-03-06

An approach combining signal detection theory and precise 3D reconstructions from serial section electron microscopy (3DEM) was used to investigate synaptic plasticity and information storage capacity at medial perforant path synapses in adult hippocampal dentate gyrus in vivo. Induction of long-term potentiation (LTP) markedly increased the frequencies of both small and large spines measured 30 minutes later. This bidirectional expansion resulted in heterosynaptic counterbalancing of total synaptic area per unit length of granule cell dendrite. Control hemispheres exhibited 6.5 distinct spine sizes for 2.7 bits of storage capacity while LTP resulted in 12.9 distinct spine sizes (3.7 bits). In contrast, control hippocampal CA1 synapses exhibited 4.7 bits with much greater synaptic precision than either control or potentiated dentate gyrus synapses. Thus, synaptic plasticity altered total capacity, yet hippocampal subregions differed dramatically in their synaptic information storage capacity, reflecting their diverse functions and activation histories.

CMOS-compatible 2-bit optical spectral quantization scheme using a silicon-nanocrystal-based horizontal slot waveguide

PubMed Central

Kang, Zhe; Yuan, Jinhui; Zhang, Xianting; Wu, Qiang; Sang, Xinzhu; Farrell, Gerald; Yu, Chongxiu; Li, Feng; Tam, Hwa Yaw; Wai, P. K. A.

2014-01-01

All-optical analog-to-digital converters based on the third-order nonlinear effects in silicon waveguide are a promising candidate to overcome the limitation of electronic devices and are suitable for photonic integration. In this paper, a 2-bit optical spectral quantization scheme for on-chip all-optical analog-to-digital conversion is proposed. The proposed scheme is realized by filtering the broadened and split spectrum induced by the self-phase modulation effect in a silicon horizontal slot waveguide filled with silicon-nanocrystal. Nonlinear coefficient as high as 8708 W−1/m is obtained because of the tight mode confinement of the horizontal slot waveguide and the high nonlinear refractive index of the silicon-nanocrystal, which provides the enhanced nonlinear interaction and accordingly low power threshold. The results show that a required input peak power level less than 0.4 W can be achieved, along with the 1.98-bit effective-number-of-bit and Gray code output. The proposed scheme can find important applications in on-chip all-optical digital signal processing systems. PMID:25417847

CMOS-compatible 2-bit optical spectral quantization scheme using a silicon-nanocrystal-based horizontal slot waveguide.

PubMed

Kang, Zhe; Yuan, Jinhui; Zhang, Xianting; Wu, Qiang; Sang, Xinzhu; Farrell, Gerald; Yu, Chongxiu; Li, Feng; Tam, Hwa Yaw; Wai, P K A

2014-11-24

All-optical analog-to-digital converters based on the third-order nonlinear effects in silicon waveguide are a promising candidate to overcome the limitation of electronic devices and are suitable for photonic integration. In this paper, a 2-bit optical spectral quantization scheme for on-chip all-optical analog-to-digital conversion is proposed. The proposed scheme is realized by filtering the broadened and split spectrum induced by the self-phase modulation effect in a silicon horizontal slot waveguide filled with silicon-nanocrystal. Nonlinear coefficient as high as 8708 W(-1)/m is obtained because of the tight mode confinement of the horizontal slot waveguide and the high nonlinear refractive index of the silicon-nanocrystal, which provides the enhanced nonlinear interaction and accordingly low power threshold. The results show that a required input peak power level less than 0.4 W can be achieved, along with the 1.98-bit effective-number-of-bit and Gray code output. The proposed scheme can find important applications in on-chip all-optical digital signal processing systems.

Designed cell consortia as fragrance-programmable analog-to-digital converters.

PubMed

Müller, Marius; Ausländer, Simon; Spinnler, Andrea; Ausländer, David; Sikorski, Julian; Folcher, Marc; Fussenegger, Martin

2017-03-01

Synthetic biology advances the rational engineering of mammalian cells to achieve cell-based therapy goals. Synthetic gene networks have nearly reached the complexity of digital electronic circuits and enable single cells to perform programmable arithmetic calculations or to provide dynamic remote control of transgenes through electromagnetic waves. We designed a synthetic multilayered gaseous-fragrance-programmable analog-to-digital converter (ADC) allowing for remote control of digital gene expression with 2-bit AND-, OR- and NOR-gate logic in synchronized cell consortia. The ADC consists of multiple sampling-and-quantization modules sensing analog gaseous fragrance inputs; a gas-to-liquid transducer converting fragrance intensity into diffusible cell-to-cell signaling compounds; a digitization unit with a genetic amplifier circuit to improve the signal-to-noise ratio; and recombinase-based digital expression switches enabling 2-bit processing of logic gates. Synthetic ADCs that can remotely control cellular activities with digital precision may enable the development of novel biosensors and may provide bioelectronic interfaces synchronizing analog metabolic pathways with digital electronics.

A CMOS IC-based multisite measuring system for stimulation and recording in neural preparations in vitro

PubMed Central

Tateno, Takashi; Nishikawa, Jun

2014-01-01

In this report, we describe the system integration of a complementary metal oxide semiconductor (CMOS) integrated circuit (IC) chip, capable of both stimulation and recording of neurons or neural tissues, to investigate electrical signal propagation within cellular networks in vitro. The overall system consisted of three major subunits: a 5.0 × 5.0 mm CMOS IC chip, a reconfigurable logic device (field-programmable gate array, FPGA), and a PC. To test the system, microelectrode arrays (MEAs) were used to extracellularly measure the activity of cultured rat cortical neurons and mouse cortical slices. The MEA had 64 bidirectional (stimulation and recording) electrodes. In addition, the CMOS IC chip was equipped with dedicated analog filters, amplification stages, and a stimulation buffer. Signals from the electrodes were sampled at 15.6 kHz with 16-bit resolution. The measured input-referred circuitry noise was 10.1 μ V root mean square (10 Hz to 100 kHz), which allowed reliable detection of neural signals ranging from several millivolts down to approximately 33 μ Vpp. Experiments were performed involving the stimulation of neurons with several spatiotemporal patterns and the recording of the triggered activity. An advantage over current MEAs, as demonstrated by our experiments, includes the ability to stimulate (voltage stimulation, 5-bit resolution) spatiotemporal patterns in arbitrary subsets of electrodes. Furthermore, the fast stimulation reset mechanism allowed us to record neuronal signals from a stimulating electrode around 3 ms after stimulation. We demonstrate that the system can be directly applied to, for example, auditory neural prostheses in conjunction with an acoustic sensor and a sound processing system. PMID:25346683

A CMOS IC-based multisite measuring system for stimulation and recording in neural preparations in vitro.

PubMed

Tateno, Takashi; Nishikawa, Jun

2014-01-01

In this report, we describe the system integration of a complementary metal oxide semiconductor (CMOS) integrated circuit (IC) chip, capable of both stimulation and recording of neurons or neural tissues, to investigate electrical signal propagation within cellular networks in vitro. The overall system consisted of three major subunits: a 5.0 × 5.0 mm CMOS IC chip, a reconfigurable logic device (field-programmable gate array, FPGA), and a PC. To test the system, microelectrode arrays (MEAs) were used to extracellularly measure the activity of cultured rat cortical neurons and mouse cortical slices. The MEA had 64 bidirectional (stimulation and recording) electrodes. In addition, the CMOS IC chip was equipped with dedicated analog filters, amplification stages, and a stimulation buffer. Signals from the electrodes were sampled at 15.6 kHz with 16-bit resolution. The measured input-referred circuitry noise was 10.1 μ V root mean square (10 Hz to 100 kHz), which allowed reliable detection of neural signals ranging from several millivolts down to approximately 33 μ Vpp. Experiments were performed involving the stimulation of neurons with several spatiotemporal patterns and the recording of the triggered activity. An advantage over current MEAs, as demonstrated by our experiments, includes the ability to stimulate (voltage stimulation, 5-bit resolution) spatiotemporal patterns in arbitrary subsets of electrodes. Furthermore, the fast stimulation reset mechanism allowed us to record neuronal signals from a stimulating electrode around 3 ms after stimulation. We demonstrate that the system can be directly applied to, for example, auditory neural prostheses in conjunction with an acoustic sensor and a sound processing system.

On Processing Hexagonally Sampled Images

DTIC Science & Technology

2011-07-01

Mersereau’s HDFT: Mersereau encountered an “insurmountable difficulty” when attempting to develop a fast algorithm to compute the hexagonal DFT...WNR GND 1-bit output CS1 . ------. (input for analog) j(-- -: I (analog out) ADC ,. __ I I I I l ______ l Power to Firefly C1 ~2 TT

4 channels x 10-Gbps optoelectronic transceiver based on silicon optical bench technology

NASA Astrophysics Data System (ADS)

Chen, Chin T.; Hsiao, Hsu L.; Chang, Chia. C.; Shen, Po K.; Lu, Guan F.; Lee, Yun C.; Chang, Shou F.; Lin, Yo S.; Wu, Mount L.

2012-01-01

In this paper, a bi-directional 4-channel x 10-Gbps optoelectronic transceiver based on this silicon optical bench (SiOB) technology is developed. A bi-directional optical sub-assembly (BOSA), fiber ribbon assembly, PCB with high frequency trace design, transmitter driver, and receiver TIA IC are included in this transceiver. The BOSA and PCB also have some specific design for conventional chip-on-board (COB) process. In eye diagram measurement, the transmitter can pass 10-G Ethernet eye mask with 25% margin at room temperature; Bit-error-rate (BER) performance from the transmitter to receiver via 10-meter fiber can achieve 10-12 order, which confirm the transceiver's ability of 10-Gbps data transmission per a channel.

Performance Enhancement of Bidirectional TWDM-PON by Rayleigh Backscattering Mitigation

NASA Astrophysics Data System (ADS)

Elewah, Ibrahim A.; Wadie, Martina N.; Aly, Moustafa H.

2018-01-01

A bidirectional time wavelength division multiplexing-passive optical network (TWDM-PON) with a centralized light source (CLS) is designed and evaluated. TWDM-PON is the promising solution for PON future expansion and migration. The most important issue that limits optical fiber transmission length is the interferometric noise caused by Rayleigh backscattering (RB). In this study, we demonstrate a TWDM-PON architecture with subcarrier at the remote node (RN) to mitigate the RB effect. A successful transmission with 8 optical channels is achieved using wavelength division multiplexing (WDM). Each optical channel is splitted into 8 time slots to achieve TWDM. The proposed scheme is operated over 20 km bidirectional single mode fiber (SMF). The proposed system has the advantage of expanding the downstream (DS) capacity to be 160 Gb/s (8 channels×20 Gb/s) and 20 Gb/s (8 channels×2.5 Gb/s) for the upstream (US) transmission capacity. This is accomplished by a remarkable bit error rate (BER) and low complexity.

Charge integration successive approximation analog-to-digital converter for focal plane applications using a single amplifier

NASA Technical Reports Server (NTRS)

Zhou, Zhimin (Inventor); Pain, Bedabrata (Inventor)

1999-01-01

An analog-to-digital converter for on-chip focal-plane image sensor applications. The analog-to-digital converter utilizes a single charge integrating amplifier in a charge balancing architecture to implement successive approximation analog-to-digital conversion. This design requires minimal chip area and has high speed and low power dissipation for operation in the 2-10 bit range. The invention is particularly well suited to CMOS on-chip applications requiring many analog-to-digital converters, such as column-parallel focal-plane architectures.

Optical digital to analog conversion performance analysis for indoor set-up conditions

NASA Astrophysics Data System (ADS)

Dobesch, Aleš; Alves, Luis Nero; Wilfert, Otakar; Ribeiro, Carlos Gaspar

2017-10-01

In visible light communication (VLC) the optical digital to analog conversion (ODAC) approach was proposed as a suitable driving technique able to overcome light-emitting diode's (LED) non-linear characteristic. This concept is analogous to an electrical digital-to-analog converter (EDAC). In other words, digital bits are binary weighted to represent an analog signal. The method supports elementary on-off based modulations able to exploit the essence of LED's non-linear characteristic allowing simultaneous lighting and communication. In the ODAC concept the reconstruction error does not simply rely upon the converter bit depth as in case of EDAC. It rather depends on communication system set-up and geometrical relation between emitter and receiver as well. The paper describes simulation results presenting the ODAC's error performance taking into account: the optical channel, the LED's half power angle (HPA) and the receiver field of view (FOV). The set-up under consideration examines indoor conditions for a square room with 4 m length and 3 m height, operating with one dominant wavelength (blue) and having walls with a reflection coefficient of 0.8. The achieved results reveal that reconstruction error increases for higher data rates as a result of interference due to multipath propagation.

Design of integrated all optical digital to analog converter (DAC) using 2D photonic crystals

NASA Astrophysics Data System (ADS)

Moniem, Tamer A.; El-Din, Eman S.

2017-11-01

A novel design of all optical 3 bit digital to analog (DAC) converter will be presented in this paper based on 2 Dimension photonic crystals (PhC). The proposed structure is based on the photonic crystal ring resonators (PCRR) with combining the nonlinear Kerr effect on the PCRR. The total size of the proposed optical 3 bit DAC is equal to 44 μm × 37 μm of 2D square lattice photonic crystals of silicon rods with refractive index equal to 3.4. The finite different time domain (FDTD) and Plane Wave Expansion (PWE) methods are used to back the overall operation of the proposed optical DAC.

Data Capture Technique for High Speed Signaling

DOEpatents

Barrett, Wayne Melvin; Chen, Dong; Coteus, Paul William; Gara, Alan Gene; Jackson, Rory; Kopcsay, Gerard Vincent; Nathanson, Ben Jesse; Vranas, Paylos Michael; Takken, Todd E.

2008-08-26

A data capture technique for high speed signaling to allow for optimal sampling of an asynchronous data stream. This technique allows for extremely high data rates and does not require that a clock be sent with the data as is done in source synchronous systems. The present invention also provides a hardware mechanism for automatically adjusting transmission delays for optimal two-bit simultaneous bi-directional (SiBiDi) signaling.

Fast bi-directional prediction selection in H.264/MPEG-4 AVC temporal scalable video coding.

PubMed

Lin, Hung-Chih; Hang, Hsueh-Ming; Peng, Wen-Hsiao

2011-12-01

In this paper, we propose a fast algorithm that efficiently selects the temporal prediction type for the dyadic hierarchical-B prediction structure in the H.264/MPEG-4 temporal scalable video coding (SVC). We make use of the strong correlations in prediction type inheritance to eliminate the superfluous computations for the bi-directional (BI) prediction in the finer partitions, 16×8/8×16/8×8 , by referring to the best temporal prediction type of 16 × 16. In addition, we carefully examine the relationship in motion bit-rate costs and distortions between the BI and the uni-directional temporal prediction types. As a result, we construct a set of adaptive thresholds to remove the unnecessary BI calculations. Moreover, for the block partitions smaller than 8 × 8, either the forward prediction (FW) or the backward prediction (BW) is skipped based upon the information of their 8 × 8 partitions. Hence, the proposed schemes can efficiently reduce the extensive computational burden in calculating the BI prediction. As compared to the JSVM 9.11 software, our method saves the encoding time from 48% to 67% for a large variety of test videos over a wide range of coding bit-rates and has only a minor coding performance loss. © 2011 IEEE

A Bidirectional Neural Interface IC with Chopper Stabilized BioADC Array and Charge Balanced Stimulator

PubMed Central

Greenwald, Elliot; So, Ernest; Wang, Qihong; Mollazadeh, Mohsen; Maier, Christoph; Etienne-Cummings, Ralph; Cauwenberghs, Gert; Thakor, Nitish

2016-01-01

We present a bidirectional neural interface with a 4-channel biopotential analog-to-digital converter (bioADC) and a 4-channel current-mode stimulator in 180nm CMOS. The bioADC directly transduces microvolt biopotentials into a digital representation without a voltage-amplification stage. Each bioADC channel comprises a continuous-time first-order ΔΣ modulator with a chopper-stabilized OTA input and current feedback, followed by a second-order comb-filter decimator with programmable oversampling ratio. Each stimulator channel contains two independent digital-to-analog converters for anodic and cathodic current generation. A shared calibration circuit matches the amplitude of the anodic and cathodic currents for charge balancing. Powered from a 1.5V supply, the analog and digital circuits in each recording channel draw on average 1.54 μA and 2.13 μA of supply current, respectively. The bioADCs achieve an SNR of 58 dB and a SFDR of >70 dB, for better than 9-b ENOB. Intracranial EEG recordings from an anesthetized rat are shown and compared to simultaneous recordings from a commercial reference system to validate performance in-vivo. Additionally, we demonstrate bidirectional operation by recording cardiac modulation induced through vagus nerve stimulation, and closed-loop control of cardiac rhythm. The micropower operation, direct digital readout, and integration of electrical stimulation circuits make this interface ideally suited for closed-loop neuromodulation applications. PMID:27845676

Performance Measurement of a Multi-Level/Analog Ferroelectric Memory Device Design

NASA Technical Reports Server (NTRS)

MacLeod, Todd C.; Phillips, Thomas A.; Ho, Fat D.

2007-01-01

Increasing the memory density and utilizing the unique characteristics of ferroelectric devices is important in making ferroelectric memory devices more desirable to the consumer. This paper describes the characterization of a design that allows multiple levels to be stored in a ferroelectric based memory cell. It can be used to store multiple bits or analog values in a high speed nonvolatile memory. The design utilizes the hysteresis characteristic of ferroelectric transistors to store an analog value in the memory cell. The design also compensates for the decay of the polarization of the ferroelectric material over time. This is done by utilizing a pair of ferroelectric transistors to store the data. One transistor is used a reference to determinethe amount of decay that has occurred since the pair was programmed. The second transistor stores the analog value as a polarization value between zero and saturated. The design allows digital data to be stored as multiple bits in each memory cell. The number of bits per cell that can be stored will vary with the decay rate of the ferroelectric transistors and the repeatability of polarization between transistors. This paper presents measurements of an actual prototype memory cell. This prototype is not a complete implementation of a device, but instead, a prototype of the storage and retrieval portion of an actual device. The performance of this prototype is presented with the projected performance of the overall device. This memory design will be useful because it allows higher memory density, compensates for the environmental and ferroelectric aging processes, allows analog values to be directly stored in memory, compensates for the thermal and radiation environments associated with space operations, and relies only on existing technologies.

Universal ripper miner

DOEpatents

Morrell, Roger J.; Larson, David A.

1991-01-01

A universal ripper miner used to cut, collect and transfer material from an underground mine working face includes a cutter head that is vertically movable in an arcuate cutting cycle by means of drive members, such as hydraulically actuated pistons. The cutter head may support a circular cutter bit having a circular cutting edge that may be indexed to incrementally expose a fresh cutting edge. An automatic indexing system is disclosed wherein indexing occurs by means of a worm gear and indexing lever mechanism. The invention also contemplates a bi-directional bit holder enabling cutting to occur in both the upstroke and the downstroke cutting cycle. Another feature of the invention discloses multiple bits arranged in an in-line, radially staggered pattern, or a side-by-side pattern to increase the mining capacity in each cutting cycle. An on-board resharpening system is also disclosed for resharpening the cutting edge at the end of cutting stroke position. The aforementioned improvement features may be used either singly, or in any proposed combination with each other.

Analysis of the influence of backscattered optical power over bidirectional PON links

NASA Astrophysics Data System (ADS)

Martínez, J. J.; Garcés, I.; López, A.; Villafranca, A.; Losada, M. A.

2010-05-01

Our aim is to describe the behavior of non-linear scattering effects that arise in standard single mode fiber (SMF), specifically scattering effects that propagate optical power in the reverse direction of the source signal such as Rayleigh Scattering (RS) and Brillouin Scattering (BS). For this purpose, the effects of backscattering phenomena over a bidirectional data transmission in a passive optical network (PON) scheme have been assessed. The impact of these high optical power components over reception at the optical line terminal (OLT) side has been determined when both links use the same wavelength. Bit Error Rate (BER) measurements have been performed with different transmission rates, using several techniques to mitigate the influence of backscattering over the received signal and considering cases with filtered and unfiltered BS.

Visible and near-infrared reflectance spectroscopy of planetary analog materials. Experimental facility at Laboratoire de Planetologie de Grenoble.

NASA Astrophysics Data System (ADS)

Pommerol, A.; Brissaud, O.; Schmitt, B.; Quirico, E.; Doute, S.

2007-08-01

We have developed an original experimental facility designed to measure the bidirectional reflectance spectra of planetary analog materials. These measurements are helpful to interpret the observations of the spectrometers on board space probes in orbit around various Solar System bodies. The central part of the facility is the LPG spectrogonio- radiometer (Brissaud et al., 2004). This instrument provides measurements of samples BRDF (Bidirectional Reflectance Distribution Function) with high photometric and spectrometric accuracy in the spectral range of visible and near-infrared (0.3 - 4.8 microns). Measurements can be made at any value of incidence and emergence angle up to 80°. Azimuth angle is allowed to vary between 0 and 180°. The instrument was recently installed in a cold room allowing ambient temperatures as low as -20°C. This makes possible the measurements on different kinds of water ice samples (slab ice, frost, snow...) and mixtures of minerals and water ice with unprecedented accuracy. We also have designed and built a simulation chamber to measure spectra of samples (water ice and/or minerals) under an atmosphere with perfectly controlled temperature, pressure and composition. The main objective of this last improvement is the study of water exchange between planetary regolith analogs and atmosphere (adsorption/ desorption, condensation/sublimation). Experimental results will mainly apply to Martian water cycle and hydrated mineralogy. This simulation chamber also provides an efficient way to obtain bidirectional reflectance spectra of dry materials (removal of adsorbed water) with implications for planetary bodies without atmospheric or surface water (Titan, asteroids...). The reflectance spectroscopy facility is part of a large panel of instruments and techniques available at Laboratoire de Planetologie de Grenoble that provide complementary measurements on the same samples: infrared transmission spectroscopy of thin ice films, thick liquid and solid samples and samples diluted in KBr pellets, infrared imaging microscope, numerical modeling of bidirectional reflectance spectra using laboratory-measured optical constants. We will present different examples of experimental results obtained on the reflectance spectroscopy facility: - Effects of particle size, mixtures between samples with different albedo and measurement geometries on the water-of-hydration near-infrared absorption signatures with implications for the Martian regolith water content. - BRDF of regolith analogs and natural snow. - Hydration and dehydration of planetary analogs. - Spectra of different kinds of mixtures between water ice and minerals. We will briefly discuss the planetary implications of each of these measurements and detail the future investigations that will be undertaken on our experimental facility.

RF digital-to-analog converter

DOEpatents

Conway, P.H.; Yu, D.U.L.

1995-02-28

A digital-to-analog converter is disclosed for producing an RF output signal proportional to a digital input word of N bits from an RF reference input, N being an integer greater or equal to 2. The converter comprises a plurality of power splitters, power combiners and a plurality of mixers or RF switches connected in a predetermined configuration. 18 figs.

Method and apparatus for communicating computer data from one point to another over a communications medium

DOEpatents

Arneson, Michael R [Chippewa Falls, WI; Bowman, Terrance L [Sumner, WA; Cornett, Frank N [Chippewa Falls, WI; DeRyckere, John F [Eau Claire, WI; Hillert, Brian T [Chippewa Falls, WI; Jenkins, Philip N [Eau Claire, WI; Ma, Nan [Chippewa Falls, WI; Placek, Joseph M [Chippewa Falls, WI; Ruesch, Rodney [Eau Claire, WI; Thorson, Gregory M [Altoona, WI

2007-07-24

The present invention is directed toward a communications channel comprising a link level protocol, a driver, a receiver, and a canceller/equalizer. The link level protocol provides logic for DC-free signal encoding and recovery as well as supporting many features including CRC error detection and message resend to accommodate infrequent bit errors across the medium. The canceller/equalizer provides equalization for destabilized data signals and also provides simultaneous bi-directional data transfer. The receiver provides bit deskewing by removing synchronization error, or skewing, between data signals. The driver provides impedance controlling by monitoring the characteristics of the communications medium, like voltage or temperature, and providing a matching output impedance in the signal driver so that fewer distortions occur while the data travels across the communications medium.

A digital-type fluxgate magnetometer using a sigma-delta digital-to-analog converter for a sounding rocket experiment

NASA Astrophysics Data System (ADS)

Iguchi, Kyosuke; Matsuoka, Ayako

2014-07-01

One of the design challenges for future magnetospheric satellite missions is optimizing the mass, size, and power consumption of the instruments to meet the mission requirements. We have developed a digital-type fluxgate (DFG) magnetometer that is anticipated to have significantly less mass and volume than the conventional analog-type. Hitherto, the lack of a space-grade digital-to-analog converter (DAC) with good accuracy has prevented the development of a high-performance DFG. To solve this problem, we developed a high-resolution DAC using parts whose performance was equivalent to existing space-grade parts. The developed DAC consists of a 1-bit second-order sigma-delta modulator and a fourth-order analog low-pass filter. We tested the performance of the DAC experimentally and found that it had better than 17-bits resolution in 80% of the measurement range, and the linearity error was 2-13.3 of the measurement range. We built a DFG flight model (in which this DAC was embedded) for a sounding rocket experiment as an interim step in the development of a future satellite mission. The noise of this DFG was 0.79 nTrms at 0.1-10 Hz, which corresponds to a roughly 17-bit resolution. The results show that the sigma-delta DAC and the DFG had a performance that is consistent with our optimized design, and the noise was as expected from the noise simulation. Finally, we have confirmed that the DFG worked successfully during the flight of the sounding rocket.

Bi-directional magnetic domain wall shift register

NASA Astrophysics Data System (ADS)

Read, D. E.; O'Brien, L.; Zeng, H. T.; Lewis, E. R.; Petit, D.; Cowburn, R. P.

2010-03-01

Data storage devices based on magnetic domain walls (DWs) propagating through ferromagnetic nanowires have attracted a great deal of attention in recent years [1,2]. Here we experimentally demonstrate a shift register based on an open-ended chain of ferromagnetic NOT gates. When used in combination with a globally applied magnetic field such devices can support bi-directional data flow [3]. We have demonstrated data writing, propagation, and readout in individually addressable NiFe nanowires 90 nm wide and 10 nm thick. Up to eight data bits are electrically input to the device, stored for extended periods without power supplied to the device, and then output using either a first in first out or a last in first out mode of operation. Compared to traditional electronic transistor-based circuits, the inherent bi-directionality afforded by these DW logic gates offers a range of devices that are reversible and not limited to only one mode of operation. [1] S. S. Parkin, US Patent 6,834,005 (2004) [2] D. A. Allwod, et al., Science 309 (5741), 1688 (2005) [3] L. O'Brien, et al. accepted for publication in APL (2009)

Automatic Single Event Effects Sensitivity Analysis of a 13-Bit Successive Approximation ADC

NASA Astrophysics Data System (ADS)

Márquez, F.; Muñoz, F.; Palomo, F. R.; Sanz, L.; López-Morillo, E.; Aguirre, M. A.; Jiménez, A.

2015-08-01

This paper presents Analog Fault Tolerant University of Seville Debugging System (AFTU), a tool to evaluate the Single-Event Effect (SEE) sensitivity of analog/mixed signal microelectronic circuits at transistor level. As analog cells can behave in an unpredictable way when critical areas interact with the particle hitting, there is a need for designers to have a software tool that allows an automatic and exhaustive analysis of Single-Event Effects influence. AFTU takes the test-bench SPECTRE design, emulates radiation conditions and automatically evaluates vulnerabilities using user-defined heuristics. To illustrate the utility of the tool, the SEE sensitivity of a 13-bits Successive Approximation Analog-to-Digital Converter (ADC) has been analysed. This circuit was selected not only because it was designed for space applications, but also due to the fact that a manual SEE sensitivity analysis would be too time-consuming. After a user-defined test campaign, it was detected that some voltage transients were propagated to a node where a parasitic diode was activated, affecting the offset cancelation, and therefore the whole resolution of the ADC. A simple modification of the scheme solved the problem, as it was verified with another automatic SEE sensitivity analysis.

a Real-Time Computer Music Synthesis System

NASA Astrophysics Data System (ADS)

Lent, Keith Henry

A real time sound synthesis system has been developed at the Computer Music Center of The University of Texas at Austin. This system consists of several stand alone processors that were constructed jointly with White Instruments in Austin. These processors can be programmed as general purpose computers, but are provided with a number of specialized interfaces including: MIDI, 8 bit parallel, high speed serial, 2 channels analog input (18 bit A/Ds, 48kHz sample rate), and 4 channels analog output (18 bit D/As). In addition, a basic music synthesis language (Music56000) has been written in assembly code. On top of this, a symbolic compiler (PatchWork) has been developed to enable algorithms which run in these processors to be created graphically. And finally, a number of efficient time domain numerical models have been developed to enable the construction, simulation, control, and synthesis of many musical acoustics systems in real time on these processors. Specifically, assembly language models for cylindrical and conical horn sections, dissipative losses, tone holes, bells, and a number of linear and nonlinear boundary conditions have been developed.

Successive approximation-like 4-bit full-optical analog-to-digital converter based on Kerr-like nonlinear photonic crystal ring resonators

NASA Astrophysics Data System (ADS)

Tavousi, Alireza; Mansouri-Birjandi, Mohammad Ali; Saffari, Mehdi

2016-09-01

Implementing of photonic sampling and quantizing analog-to-digital converters (ADCs) enable us to extract a single binary word from optical signals without need for extra electronic assisting parts. This would enormously increase the sampling and quantizing time as well as decreasing the consumed power. To this end, based on the concept of successive approximation method, a 4-bit full-optical ADC that operates using the intensity-dependent Kerr-like nonlinearity in a two dimensional photonic crystal (2DPhC) platform is proposed. The Silicon (Si) nanocrystal is chosen because of the suitable nonlinear material characteristic. An optical limiter is used for the clamping and quantization of each successive levels that represent the ADC bits. In the proposal, an energy efficient optical ADC circuit is implemented by controlling the system parameters such as ring-to-waveguide coupling coefficients, the ring's nonlinear refractive index, and the ring's length. The performance of the ADC structure is verified by the simulation using finite difference time domain (FDTD) method.

Design and performance of a custom ASIC digitizer for wire chamber readout in 65 nm CMOS technology

NASA Astrophysics Data System (ADS)

Lee, M. J.; Brown, D. N.; Chang, J. K.; Ding, D.; Gnani, D.; Grace, C. R.; Jones, J. A.; Kolomensky, Y. G.; von der Lippe, H.; Mcvittie, P. J.; Stettler, M. W.; Walder, J.-P.

2015-06-01

We present the design and performance of a prototype ASIC digitizer for integrated wire chamber readout, implemented in 65 nm commercial CMOS technology. Each channel of the 4-channel prototype is composed of two 16-bit Time-to-Digital Converters (TDCs), one 8-bit Analog-to-Digital Converter (ADC), a front-end preamplifier and shaper, plus digital and analog buffers that support a variety of digitization chains. The prototype has a multiplexed digital backend that executes a state machine, distributes control and timing signals, and buffers data for serial output. Laboratory bench tests measure the absolute TDC resolution between 74 ps and 480 ps, growing with the absolute delay, and a relative time resolution of 19 ps. Resolution outliers due to cross-talk between clock signals and supply or reference voltages are seen. After calibration, the ADC displays good linearity and noise performance, with an effective number of bits of 6.9. Under normal operating conditions the circuit consumes 32 mW per channel. Potential design improvements to address the resolution drift and tails are discussed.

Equipment for the Transient Capture of Chaotic Microwave Signals

DTIC Science & Technology

2017-09-14

estimated to average 1 hour per response, including the time for reviewing instructions, searching existing data sources, gathering and maintaining the... times are needed and over-sampling by a factor of 8 is required so that the effective number of bits can be increased from the actual bit resolution... time acquisition of transient signals with analog bandwidths up to 70 GHz for one channel, and 30 GHz for two channels.. Training Opportunities

Minimal-post-processing 320-Gbps true random bit generation using physical white chaos.

PubMed

Wang, Anbang; Wang, Longsheng; Li, Pu; Wang, Yuncai

2017-02-20

Chaotic external-cavity semiconductor laser (ECL) is a promising entropy source for generation of high-speed physical random bits or digital keys. The rate and randomness is unfortunately limited by laser relaxation oscillation and external-cavity resonance, and is usually improved by complicated post processing. Here, we propose using a physical broadband white chaos generated by optical heterodyning of two ECLs as entropy source to construct high-speed random bit generation (RBG) with minimal post processing. The optical heterodyne chaos not only has a white spectrum without signature of relaxation oscillation and external-cavity resonance but also has a symmetric amplitude distribution. Thus, after quantization with a multi-bit analog-digital-convertor (ADC), random bits can be obtained by extracting several least significant bits (LSBs) without any other processing. In experiments, a white chaos with a 3-dB bandwidth of 16.7 GHz is generated. Its entropy rate is estimated as 16 Gbps by single-bit quantization which means a spectrum efficiency of 96%. With quantization using an 8-bit ADC, 320-Gbps physical RBG is achieved by directly extracting 4 LSBs at 80-GHz sampling rate.

Photometric study of cometary analogs in the LOSSy laboratory at the University of Bern

NASA Astrophysics Data System (ADS)

Pommerol, A.; Thomas, N.; Jost, B.; Poch, O.

2014-07-01

We have set up the LOSSy laboratory (Laboratory for Outflow Studies of Sublimating Materials) to study the spectro-photometric properties of various analogs of planetary-object surfaces, with a special emphasis on icy samples and their evolution under simulated space conditions. This laboratory is currently equipped with two facilities: the PHIRE-2 radio-goniometer, designed to measure the bidirectional visible reflectance of samples under a wide range of geometries and the SCITEAS simulation chamber, designed to follow the evolution of icy samples subliming under low temperature and low pressure conditions by means of VIS-NIR hyperspectral imaging. We will report on the characterization of cometary analogs using both facilities. We produce these analogs by mixing in various proportions fine-grained ice, mineral and organic matter. Various preparation protocols have been defined to produce different textures of sample. Using the PHIRE-2 radio-goniometer, we are building a catalog of bidirectional reflectance data for various cometary analogs, varying by steps the different parameters susceptible to affect the reflectance phase function. In particular, we have recently upgraded the instrument to be able to characterize in detail the opposition effect by allowing measurements of the reflectance at very low phase angle. This laboratory dataset is intended to be used for the analysis of the data acquired by the OSIRIS imager onboard Rosetta. Using the SCITEAS simulation chamber, we have followed for 30 hours the evolution of a cometary analog placed under secondary vacuum (<10^{-6} mbar) and maintained at low temperature (170-200 K) for more than 30 hours. We analyzed the temporal evolution of the morphology and the photometry of the surface of the sample to identify which processes affect the surfaces of cometary nuclei during sublimation and how they affect their visible and near-infrared surface properties.

Long-distance multi-channel bidirectional chaos communication based on synchronized VCSELs subject to chaotic signal injection

NASA Astrophysics Data System (ADS)

Xie, Yi-Yuan; Li, Jia-Chao; He, Chao; Zhang, Zhen-Dong; Song, Ting-Ting; Xu, Chang-Jun; Wang, Gui-Jin

2016-10-01

A novel long-distance multi-channel bidirectional chaos communication system over multiple paths based on two synchronized 1550 nm vertical-cavity surface-emitting lasers (VCSELs) is proposed and studied theoretically. These two responding VCSELs (R-VCSELs) can output similar chaotic signals served as chaotic carrier in two linear polarization (LP) modes with identical signal injection from a driving VCSEL (D-VCSEL), which is subject to optical feedback and optical injection, simultaneously. Through the numerical simulations, high quality chaos synchronization between the two R-VCSELs can be obtained. Besides, the effects of varied qualities of chaos synchronization on communication performances in 20 km single mode fiber (SMF) channels are investigated by regulating different internal parameters mismatch after adopting chaos masking (CMS) technique. With the decrease of the maximum cross correlation coefficient (Max-C) between the two R-VCSELs, the bit error rate (BER) of decoded message increase. Meanwhile, the BER can still be less than 10-9 when the Max-C degrades to 0.982. Based on high quality synchronization, when the dispersion compensating fiber (DCF) links are introduced, 4n messages of 10 Gbit/s can transmit in 180 km SMF channels over n coupling paths, bidirectionally and simultaneously. Thorough tests are carried out with detailed analysis, demonstrating long-distance, multi-channel, bidirectional chaos communication based on VCSELs with chaotic signal injection.

Enabling high grayscale resolution displays and accurate response time measurements on conventional computers.

PubMed

Li, Xiangrui; Lu, Zhong-Lin

2012-02-29

Display systems based on conventional computer graphics cards are capable of generating images with 8-bit gray level resolution. However, most experiments in vision research require displays with more than 12 bits of luminance resolution. Several solutions are available. Bit++ (1) and DataPixx (2) use the Digital Visual Interface (DVI) output from graphics cards and high resolution (14 or 16-bit) digital-to-analog converters to drive analog display devices. The VideoSwitcher (3) described here combines analog video signals from the red and blue channels of graphics cards with different weights using a passive resister network (4) and an active circuit to deliver identical video signals to the three channels of color monitors. The method provides an inexpensive way to enable high-resolution monochromatic displays using conventional graphics cards and analog monitors. It can also provide trigger signals that can be used to mark stimulus onsets, making it easy to synchronize visual displays with physiological recordings or response time measurements. Although computer keyboards and mice are frequently used in measuring response times (RT), the accuracy of these measurements is quite low. The RTbox is a specialized hardware and software solution for accurate RT measurements. Connected to the host computer through a USB connection, the driver of the RTbox is compatible with all conventional operating systems. It uses a microprocessor and high-resolution clock to record the identities and timing of button events, which are buffered until the host computer retrieves them. The recorded button events are not affected by potential timing uncertainties or biases associated with data transmission and processing in the host computer. The asynchronous storage greatly simplifies the design of user programs. Several methods are available to synchronize the clocks of the RTbox and the host computer. The RTbox can also receive external triggers and be used to measure RT with respect to external events. Both VideoSwitcher and RTbox are available for users to purchase. The relevant information and many demonstration programs can be found at http://lobes.usc.edu/.

High-speed, bi-directional dual-core fiber transmission system for high-density, short-reach optical interconnects

NASA Astrophysics Data System (ADS)

Geng, Ying; Li, Shenping; Li, Ming-Jun; Sutton, Clifford G.; McCollum, Robert L.; McClure, Randy L.; Koklyushkin, Alexander V.; Matthews, Karen I.; Luther, James P.; Butler, Douglas L.

2015-03-01

A complete single mode dual-core fiber system for short-reach optical interconnects is fabricated and tested for high-speed data transmission. It includes dual-core fibers capable of bi-directional data transmission, dual-core simplex LC connectors, and fan-outs. The transmission system offers simplified bi-directional traffic engineering with integrated bidirectional transceivers and compact system design, utilizing simplex dual-core LC connectors that use half the space while increasing the bandwidth density by a factor of two. The fiber has two cores that are compatible with single mode fiber and conforms to the industry standard outer diameter of 125 μm. This reduces operational complexity by reducing the size and number of fibers, cables and connectors. Measured OTDR loss for both cores was 0.34 dB/km at 1310 nm and 0.19 dB/km at 1550 nm. Crosstalk for a piece of 5.8 km long dual-core fiber was measured to be below -75 dB at 1310 nm, and below -40 dB at 1550 nm. Both free-space optics fan-outs and tapered-fiber-coupler based MCF fan-outs were evaluated for the transmission system. Error-free and penalty-free 25 Gb/s bi-directional transmission performance was demonstrated for three different fiber lengths, 200 m, 2 km and 10 km, using the complete all-fiber-based system including connectors and fan-outs. This single mode, dual-core fiber transmission system adds complementary value to systems where additional increases in bandwidth density can come from wavelength division multiplexing and multiple bits per symbol.

Method and Apparatus for Improving the Resolution of Digitally Sampled Analog Data

NASA Technical Reports Server (NTRS)

Liaghati, Amir L. (Inventor)

2017-01-01

A system and method is described for converting an analog signal into a digital signal. The gain and offset of an ADC is dynamically adjusted so that the N-bits of input data are assigned to a narrower channel instead of the entire input range of the ADC. This provides greater resolution in the range of interest without generating longer digital data strings.

Symmetric reconfigurable capacity assignment in a bidirectional DWDM access network.

PubMed

Ortega, Beatriz; Mora, José; Puerto, Gustavo; Capmany, José

2007-12-10

This paper presents a novel architecture for DWDM bidirectional access networks providing symmetric dynamic capacity allocation for both downlink and uplink signals. A foldback arrayed waveguide grating incorporating an optical switch enables the experimental demonstration of flexible assignment of multiservice capacity. Different analog and digital services, such as CATV, 10 GHz-tone, 155Mb/s PRBS and UMTS signals have been transmitted in order to successfully test the system performance under different scenarios of total capacity distribution from the Central Station to different Base Stations with two reconfigurable extra channels for each down and upstream direction.

Full-duplex bidirectional data transmission link using twisted lights multiplexing over 1.1-km orbital angular momentum fiber

PubMed Central

Chen, Shi; Liu, Jun; Zhao, Yifan; Zhu, Long; Wang, Andong; Li, Shuhui; Du, Jing; Du, Cheng; Mo, Qi; Wang, Jian

2016-01-01

We present a full-duplex bidirectional data transmission link using twisted lights multiplexing over 1.1-km orbital angular momentum (OAM) fiber. OAM+1 and OAM−1 modes carrying 20-Gbit/s quadrature phase-shift keying (QPSK) signals are employed in the downlink and uplink transmission experiments. The observed mode crosstalks are less than −15.2 dB, and the full-duplex crosstalks are less than −12.7 dB. The measured full-duplex optical signal-to-noise ratio (OSNR) penalties at a bit-error rate (BER) of 2 × 10−3 are ~2.4 dB in the downlink transmission and ~2.3 dB in the uplink transmission. The obtained results show favorable full-duplex twisted lights multiplexing data transmission performance in a km-scale OAM fiber link. PMID:27901082

Performance comparison between 8 and 14 bit-depth imaging in polarization-sensitive swept-source optical coherence tomography

NASA Astrophysics Data System (ADS)

Lu, Zenghai; Kasaragoda, Deepa K.; Matcher, Stephen J.

2011-03-01

We compare true 8 and 14 bit-depth imaging of SS-OCT and polarization-sensitive SS-OCT (PS-SS-OCT) at 1.3μm wavelength by using two hardware-synchronized high-speed data acquisition (DAQ) boards. The two DAQ boards read exactly the same imaging data for comparison. The measured system sensitivity at 8-bit depth is comparable to that for 14-bit acquisition when using the more sensitive of the available full analog input voltage ranges of the ADC. Ex-vivo structural and birefringence images of an equine tendon sample indicate no significant differences between images acquired by the two DAQ boards suggesting that 8-bit DAQ boards can be employed to increase imaging speeds and reduce storage in clinical SS-OCT/PS-SS-OCT systems. We also compare the resulting image quality when the image data sampled with the 14-bit DAQ from human finger skin is artificially bit-reduced during post-processing. However, in agreement with the results reported previously, we also observe that in our system that real-world 8-bit image shows more artifacts than the image acquired by numerically truncating to 8-bits from the raw 14-bit image data, especially in low intensity image area. This is due to the higher noise floor and reduced dynamic range of the 8-bit DAQ. One possible disadvantage is a reduced imaging dynamic range which can manifest itself as an increase in image artefacts due to strong Fresnel reflection.

Design of a Low-Light-Level Image Sensor with On-Chip Sigma-Delta Analog-to- Digital Conversion

NASA Technical Reports Server (NTRS)

Mendis, Sunetra K.; Pain, Bedabrata; Nixon, Robert H.; Fossum, Eric R.

1993-01-01

The design and projected performance of a low-light-level active-pixel-sensor (APS) chip with semi-parallel analog-to-digital (A/D) conversion is presented. The individual elements have been fabricated and tested using MOSIS* 2 micrometer CMOS technology, although the integrated system has not yet been fabricated. The imager consists of a 128 x 128 array of active pixels at a 50 micrometer pitch. Each column of pixels shares a 10-bit A/D converter based on first-order oversampled sigma-delta (Sigma-Delta) modulation. The 10-bit outputs of each converter are multiplexed and read out through a single set of outputs. A semi-parallel architecture is chosen to achieve 30 frames/second operation even at low light levels. The sensor is designed for less than 12 e^- rms noise performance.

Controlled Bidirectional Quantum Secure Direct Communication

PubMed Central

Chou, Yao-Hsin; Lin, Yu-Ting; Zeng, Guo-Jyun; Lin, Fang-Jhu; Chen, Chi-Yuan

2014-01-01

We propose a novel protocol for controlled bidirectional quantum secure communication based on a nonlocal swap gate scheme. Our proposed protocol would be applied to a system in which a controller (supervisor/Charlie) controls the bidirectional communication with quantum information or secret messages between legitimate users (Alice and Bob). In this system, the legitimate users must obtain permission from the controller in order to exchange their respective quantum information or secret messages simultaneously; the controller is unable to obtain any quantum information or secret messages from the decoding process. Moreover, the presence of the controller also avoids the problem of one legitimate user receiving the quantum information or secret message before the other, and then refusing to help the other user decode the quantum information or secret message. Our proposed protocol is aimed at protecting against external and participant attacks on such a system, and the cost of transmitting quantum bits using our protocol is less than that achieved in other studies. Based on the nonlocal swap gate scheme, the legitimate users exchange their quantum information or secret messages without transmission in a public channel, thus protecting against eavesdroppers stealing the secret messages. PMID:25006596

A 4 μW/Ch analog front-end module with moderate inversion and power-scalable sampling operation for 3-D neural microsystems.

PubMed

Al-Ashmouny, Khaled M; Chang, Sun-Il; Yoon, Euisik

2012-10-01

We report an analog front-end prototype designed in 0.25 μm CMOS process for hybrid integration into 3-D neural recording microsystems. For scaling towards massive parallel neural recording, the prototype has investigated some critical circuit challenges in power, area, interface, and modularity. We achieved extremely low power consumption of 4 μW/channel, optimized energy efficiency using moderate inversion in low-noise amplifiers (K of 5.98 × 10⁸ or NEF of 2.9), and minimized asynchronous interface (only 2 per 16 channels) for command and data capturing. We also implemented adaptable operations including programmable-gain amplification, power-scalable sampling (up to 50 kS/s/channel), wide configuration range (9-bit) for programmable gain and bandwidth, and 5-bit site selection capability (selecting 16 out of 128 sites). The implemented front-end module has achieved a reduction in noise-energy-area product by a factor of 5-25 times as compared to the state-of-the-art analog front-end approaches reported to date.

Learning by Reading for Robust Reasoning in Intelligent Agents

DTIC Science & Technology

2018-04-24

SUPPLEMENTARY NOTES 14. ABSTRACT Our hypotheses are that analogical processing plays multiple roles in enabling machines to learn by reading, and that...systems). Our overall hypotheses are that analogical processing plays multiple roles in learning by reading, and that qualitative representations provide...from reading this text? Narrative function can be seen as a kind of communication act, but the idea goes a bit beyond that. Communication acts are

The initial characterization of a revised 10-Gsps analog-to-digital converter board for radio telescopes

NASA Astrophysics Data System (ADS)

Jiango, Homin; Liuo, Howard; Guzzino, Kim

2016-07-01

In this study, the design of a 4 bit, 10-gigasamples-per-second analog-to-digital converter (ADC) printed circuit board assembly (PCBA) was revised, manufactured, and tested. It is used for digitizing radio telescopes. An Adsantec ANST7120-KMA flash ADC chip was used, as in the original design. Associated with the field-programmable gate array platform developed by the Collaboration for Astronomy Signal Processing and Electronics Research community, the developed PCBA provides data acquisition systems with a wider bandwidth and simplifies the intermediate frequency section. The current version of the PCBA exhibits an analog bandwidth of up to 10 GHz (3 dB loss), and the chip exhibits an analog bandwidth of up to 18 GHz. This facilitates second and third Nyquist sampling. The following worstcase performance parameters were obtained from the revised PCBA at over 5 GHz: spurious-free dynamic range of 12 dB, signal-to-noise and distortion ratio of 2 dB, and effective number of bits of 0.7. The design bugs in the ADC chip caused the poor performance. The vendor created a new batch run and confirmed that the ADC chips of the new batch will meet the specifications addressed in its data sheet.

A low power, low noise Programmable Analog Front End (PAFE) for biopotential measurements.

PubMed

Adimulam, Mahesh Kumar; Divya, A; Tejaswi, K; Srinivas, M B

2017-07-01

A low power Programmable Analog Front End (PAFE) for biopotential measurements is presented in this paper. The PAFE circuit processes electrocardiogram (ECG), electromyography (EMG) and electroencephalogram (EEG) signals with higher accuracy. It consists mainly of improved transconductance programmable gain instrumentational amplifier (PGIA), programmable high pass filter (PHPF), and second order low pass filter (SLPF). A 15-bit programmable 5-stage successive approximation analog-to-digital converter (SAR-ADC) is implemented for improving the performance, whose power consumption is reduced due to multiple stages and by OTA/Comparator sharing technique between the stages. The power consumption is further reduced by operating the analog portion of PAFE on 0.5V supply voltage and digital portion on 0.3V supply voltage generated internally through a voltage regulator. The proposed low power PAFE has been fabricated in 180nm standard CMOS process. The performance parameters of PAFE in 15-bit mode are found to be, gain of 31-70 dB, input referred noise of 1.15 μVrms, CMRR of 110 dB, PSRR of 104 dB, and signal-to-noise distortion ratio (SNDR) of 83.5dB. The power consumption of the design is 1.1 μW @ 0.5 V supply voltage and it occupies a core silicon area of 1.2 mm 2 .

Bi-directional Reflectance of Icy Surface Analogs: A Dual Approach

NASA Astrophysics Data System (ADS)

Quinones, Juan Manuel; Vides, Christina; Nelson, Robert M.; Boryta, Mark; Mannat, Ken s.

2018-01-01

Bi-directional reflectance measurements of analogs for planetary regolith have provided insight into the surface properties of planetary satellites and small bodies. Because Aluminum Oxide (Al2O3) and water ice share a similar hexagonal crystalline structure, the former has been used in laboratory experiments to simulate the regolith of both icy and dusty planetary bodies. By measuring various sizes of well sorted size fractions of Al2O3, the reflectance phase curve and porosity of a planetary regolith can be determined. We have designed an experiment to test the laboratory measurements produced by Nelson et al. (2000). Additionally, we made reflectance measurements for other alkali-halide compounds that could be used for applications beyond astronomy and planetary science.In order to provide an independent check on the Nelson et al. data, we designed an instrument with a different configuration. While both instruments take bidirectional reflectance measurements, our instrument, the Rigid Photometric Goniometer (RPG), is fixed at a phase angle of 5° and detects the scattered light with a photomultiplier tube (PMT). The PMT current is then measured with an electrometer. Following the example of Nelson et al., we measured the bidirectional reflectance of Al2O3 particulate size fractions between 0.1

Optical analog-to-digital converter

DOEpatents

Vawter, G Allen [Corrales, NM; Raring, James [Goleta, CA; Skogen, Erik J [Albuquerque, NM

2009-07-21

An optical analog-to-digital converter (ADC) is disclosed which converts an input optical analog signal to an output optical digital signal at a sampling rate defined by a sampling optical signal. Each bit of the digital representation is separately determined using an optical waveguide interferometer and an optical thresholding element. The interferometer uses the optical analog signal and the sampling optical signal to generate a sinusoidally-varying output signal using cross-phase-modulation (XPM) or a photocurrent generated from the optical analog signal. The sinusoidally-varying output signal is then digitized by the thresholding element, which includes a saturable absorber or at least one semiconductor optical amplifier, to form the optical digital signal which can be output either in parallel or serially.

Enabling technology for future gigabit-symmetric FTTH: coherent OCDMA over WDM-PON

NASA Astrophysics Data System (ADS)

Kitayama, Ken-ichi; Wang, Xu; Wada, Naoya

2006-09-01

For the future broadband Fiber-To-The-Home (FTTH) services, it will be revealed to be a myth that the low bit-rate uplink may be deployed, while only the downlink has to be high bit-rate. Current FTTH system forces the customers a stressful access in the uplink due to its MAC based on TDMA under always-on service provisionings. Without an abundant bandwidth of uplink available, peer-to-peer applications such as exchanging gigabyte files of uncompressed 1.2 Gbps high-definition (HD) TV class or even 6Gbps super-high-definition (SHD)class digital movies as well as teleconferencing and bi-directional medical applications such as tele-diagnosis and -surgery won't become widewpread. With a narrowband uplink, even non peer-to-peer customers will be put in a disadvantageous position by being forced to share the limited bandwidth with a limited number of bandwidth-hungry users.

High speed and adaptable error correction for megabit/s rate quantum key distribution.

PubMed

Dixon, A R; Sato, H

2014-12-02

Quantum Key Distribution is moving from its theoretical foundation of unconditional security to rapidly approaching real world installations. A significant part of this move is the orders of magnitude increases in the rate at which secure key bits are distributed. However, these advances have mostly been confined to the physical hardware stage of QKD, with software post-processing often being unable to support the high raw bit rates. In a complete implementation this leads to a bottleneck limiting the final secure key rate of the system unnecessarily. Here we report details of equally high rate error correction which is further adaptable to maximise the secure key rate under a range of different operating conditions. The error correction is implemented both in CPU and GPU using a bi-directional LDPC approach and can provide 90-94% of the ideal secure key rate over all fibre distances from 0-80 km.

High speed and adaptable error correction for megabit/s rate quantum key distribution

PubMed Central

Dixon, A. R.; Sato, H.

2014-01-01

Quantum Key Distribution is moving from its theoretical foundation of unconditional security to rapidly approaching real world installations. A significant part of this move is the orders of magnitude increases in the rate at which secure key bits are distributed. However, these advances have mostly been confined to the physical hardware stage of QKD, with software post-processing often being unable to support the high raw bit rates. In a complete implementation this leads to a bottleneck limiting the final secure key rate of the system unnecessarily. Here we report details of equally high rate error correction which is further adaptable to maximise the secure key rate under a range of different operating conditions. The error correction is implemented both in CPU and GPU using a bi-directional LDPC approach and can provide 90–94% of the ideal secure key rate over all fibre distances from 0–80 km. PMID:25450416

The Design of a Single-Bit CMOS Image Sensor for Iris Recognition Applications

PubMed Central

Park, Keunyeol; Song, Minkyu

2018-01-01

This paper presents a single-bit CMOS image sensor (CIS) that uses a data processing technique with an edge detection block for simple iris segmentation. In order to recognize the iris image, the image sensor conventionally captures high-resolution image data in digital code, extracts the iris data, and then compares it with a reference image through a recognition algorithm. However, in this case, the frame rate decreases by the time required for digital signal conversion of multi-bit digital data through the analog-to-digital converter (ADC) in the CIS. In order to reduce the overall processing time as well as the power consumption, we propose a data processing technique with an exclusive OR (XOR) logic gate to obtain single-bit and edge detection image data instead of multi-bit image data through the ADC. In addition, we propose a logarithmic counter to efficiently measure single-bit image data that can be applied to the iris recognition algorithm. The effective area of the proposed single-bit image sensor (174 × 144 pixel) is 2.84 mm2 with a 0.18 μm 1-poly 4-metal CMOS image sensor process. The power consumption of the proposed single-bit CIS is 2.8 mW with a 3.3 V of supply voltage and 520 frame/s of the maximum frame rates. The error rate of the ADC is 0.24 least significant bit (LSB) on an 8-bit ADC basis at a 50 MHz sampling frequency. PMID:29495273

The Design of a Single-Bit CMOS Image Sensor for Iris Recognition Applications.

PubMed

Park, Keunyeol; Song, Minkyu; Kim, Soo Youn

2018-02-24

This paper presents a single-bit CMOS image sensor (CIS) that uses a data processing technique with an edge detection block for simple iris segmentation. In order to recognize the iris image, the image sensor conventionally captures high-resolution image data in digital code, extracts the iris data, and then compares it with a reference image through a recognition algorithm. However, in this case, the frame rate decreases by the time required for digital signal conversion of multi-bit digital data through the analog-to-digital converter (ADC) in the CIS. In order to reduce the overall processing time as well as the power consumption, we propose a data processing technique with an exclusive OR (XOR) logic gate to obtain single-bit and edge detection image data instead of multi-bit image data through the ADC. In addition, we propose a logarithmic counter to efficiently measure single-bit image data that can be applied to the iris recognition algorithm. The effective area of the proposed single-bit image sensor (174 × 144 pixel) is 2.84 mm² with a 0.18 μm 1-poly 4-metal CMOS image sensor process. The power consumption of the proposed single-bit CIS is 2.8 mW with a 3.3 V of supply voltage and 520 frame/s of the maximum frame rates. The error rate of the ADC is 0.24 least significant bit (LSB) on an 8-bit ADC basis at a 50 MHz sampling frequency.

Optical transmission modules for multi-channel superconducting quantum interference device readouts.

PubMed

Kim, Jin-Mok; Kwon, Hyukchan; Yu, Kwon-kyu; Lee, Yong-Ho; Kim, Kiwoong

2013-12-01

We developed an optical transmission module consisting of 16-channel analog-to-digital converter (ADC), digital-noise filter, and one-line serial transmitter, which transferred Superconducting Quantum Interference Device (SQUID) readout data to a computer by a single optical cable. A 16-channel ADC sent out SQUID readouts data with 32-bit serial data of 8-bit channel and 24-bit voltage data at a sample rate of 1.5 kSample/s. A digital-noise filter suppressed digital noises generated by digital clocks to obtain SQUID modulation as large as possible. One-line serial transmitter reformed 32-bit serial data to the modulated data that contained data and clock, and sent them through a single optical cable. When the optical transmission modules were applied to 152-channel SQUID magnetoencephalography system, this system maintained a field noise level of 3 fT/√Hz @ 100 Hz.

Modular error embedding

DOEpatents

Sandford, II, Maxwell T.; Handel, Theodore G.; Ettinger, J. Mark

1999-01-01

A method of embedding auxiliary information into the digital representation of host data containing noise in the low-order bits. The method applies to digital data representing analog signals, for example digital images. The method reduces the error introduced by other methods that replace the low-order bits with auxiliary information. By a substantially reverse process, the embedded auxiliary data can be retrieved easily by an authorized user through use of a digital key. The modular error embedding method includes a process to permute the order in which the host data values are processed. The method doubles the amount of auxiliary information that can be added to host data values, in comparison with bit-replacement methods for high bit-rate coding. The invention preserves human perception of the meaning and content of the host data, permitting the addition of auxiliary data in the amount of 50% or greater of the original host data.

Analogy between gambling and measurement-based work extraction

NASA Astrophysics Data System (ADS)

Vinkler, Dror A.; Permuter, Haim H.; Merhav, Neri

2016-04-01

In information theory, one area of interest is gambling, where mutual information characterizes the maximal gain in wealth growth rate due to knowledge of side information; the betting strategy that achieves this maximum is named the Kelly strategy. In the field of physics, it was recently shown that mutual information can characterize the maximal amount of work that can be extracted from a single heat bath using measurement-based control protocols, i.e. using ‘information engines’. However, to the best of our knowledge, no relation between gambling and information engines has been presented before. In this paper, we briefly review the two concepts and then demonstrate an analogy between gambling, where bits are converted into wealth, and information engines, where bits representing measurements are converted into energy. From this analogy follows an extension of gambling to the continuous-valued case, which is shown to be useful for investments in currency exchange rates or in the stock market using options. Moreover, the analogy enables us to use well-known methods and results from one field to solve problems in the other. We present three such cases: maximum work extraction when the probability distributions governing the system and measurements are unknown, work extraction when some energy is lost in each cycle, e.g. due to friction, and an analysis of systems with memory. In all three cases, the analogy enables us to use known results in order to obtain new ones.

14 CFR 1215.105 - Delivery of user data.

Code of Federal Regulations, 2010 CFR

2010-01-01

... SATELLITE SYSTEM (TDRSS) Use and Reimbursement Policy for Non-U.S. Government Users § 1215.105 Delivery of... determined by NASA in the form of one or more digital or analog bit streams synchronized to associated clock...

Reconfigurable fuzzy cell

NASA Technical Reports Server (NTRS)

Salazar, George A. (Inventor)

1993-01-01

This invention relates to a reconfigurable fuzzy cell comprising a digital control programmable gain operation amplifier, an analog-to-digital converter, an electrically erasable PROM, and 8-bit counter and comparator, and supporting logic configured to achieve in real-time fuzzy systems high throughput, grade-of-membership or membership-value conversion of multi-input sensor data. The invention provides a flexible multiplexing-capable configuration, implemented entirely in hardware, for effectuating S-, Z-, and PI-membership functions or combinations thereof, based upon fuzzy logic level-set theory. A membership value table storing 'knowledge data' for each of S-, Z-, and PI-functions is contained within a nonvolatile memory for storing bits of membership and parametric information in a plurality of address spaces. Based upon parametric and control signals, analog sensor data is digitized and converted into grade-of-membership data. In situ learn and recognition modes of operation are also provided.

Fast, Deep-Record-Length, Fiber-Coupled Photodiode Imaging Array for Plasma Diagnostics

NASA Astrophysics Data System (ADS)

Brockington, Samuel; Case, Andrew; Witherspoon, F. Douglas

2015-11-01

HyperV Technologies has been developing an imaging diagnostic comprised of an array of fast, low-cost, long-record-length, fiber-optically-coupled photodiode channels to investigate plasma dynamics and other fast, bright events. By coupling an imaging fiber bundle to a bank of amplified photodiode channels, imagers and streak imagers can be constructed. By interfacing analog photodiode systems directly to commercial analog-to-digital converters and modern memory chips, a scalable solution for 100 to 1000 pixel systems with 14 bit resolution and record-lengths of 128k frames has been developed. HyperV is applying these techniques to construct a prototype 1000 Pixel framing camera with up to 100 Msamples/sec rate and 10 to 14 bit depth. Preliminary experimental results as well as future plans will be discussed. Work supported by USDOE Phase 2 SBIR Grant DE-SC0009492.

Fast, Deep-Record-Length, Fiber-Coupled Photodiode Imaging Array for Plasma Diagnostics

NASA Astrophysics Data System (ADS)

Brockington, Samuel; Case, Andrew; Witherspoon, F. Douglas

2014-10-01

HyperV Technologies has been developing an imaging diagnostic comprised of an array of fast, low-cost, long-record-length, fiber-optically-coupled photodiode channels to investigate plasma dynamics and other fast, bright events. By coupling an imaging fiber bundle to a bank of amplified photodiode channels, imagers and streak imagers of 100 to 1000 pixels can be constructed. By interfacing analog photodiode systems directly to commercial analog-to-digital converters and modern memory chips, a prototype 100 pixel array with an extremely deep record length (128 k points at 20 Msamples/s) and 10 bit pixel resolution has already been achieved. HyperV now seeks to extend these techniques to construct a prototype 1000 Pixel framing camera with up to 100 Msamples/sec rate and 10 to 12 bit depth. Preliminary experimental results as well as Phase 2 plans will be discussed. Work supported by USDOE Phase 2 SBIR Grant DE-SC0009492.

Image display device in digital TV

DOEpatents

Choi, Seung Jong [Seoul, KR

2006-07-18

Disclosed is an image display device in a digital TV that is capable of carrying out the conversion into various kinds of resolution by using single bit map data in the digital TV. The image display device includes: a data processing part for executing bit map conversion, compression, restoration and format-conversion for text data; a memory for storing the bit map data obtained according to the bit map conversion and compression in the data processing part and image data inputted from an arbitrary receiving part, the receiving part receiving one of digital image data and analog image data; an image outputting part for reading the image data from the memory; and a display processing part for mixing the image data read from the image outputting part and the bit map data converted in format from the a data processing part. Therefore, the image display device according to the present invention can convert text data in such a manner as to correspond with various resolution, carry out the compression for bit map data, thereby reducing the memory space, and support text data of an HTML format, thereby providing the image with the text data of various shapes.

Stochastic p -Bits for Invertible Logic

NASA Astrophysics Data System (ADS)

Camsari, Kerem Yunus; Faria, Rafatul; Sutton, Brian M.; Datta, Supriyo

2017-07-01

Conventional semiconductor-based logic and nanomagnet-based memory devices are built out of stable, deterministic units such as standard metal-oxide semiconductor transistors, or nanomagnets with energy barriers in excess of ≈40 - 60 kT . In this paper, we show that unstable, stochastic units, which we call "p -bits," can be interconnected to create robust correlations that implement precise Boolean functions with impressive accuracy, comparable to standard digital circuits. At the same time, they are invertible, a unique property that is absent in standard digital circuits. When operated in the direct mode, the input is clamped, and the network provides the correct output. In the inverted mode, the output is clamped, and the network fluctuates among all possible inputs that are consistent with that output. First, we present a detailed implementation of an invertible gate to bring out the key role of a single three-terminal transistorlike building block to enable the construction of correlated p -bit networks. The results for this specific, CMOS-assisted nanomagnet-based hardware implementation agree well with those from a universal model for p -bits, showing that p -bits need not be magnet based: any three-terminal tunable random bit generator should be suitable. We present a general algorithm for designing a Boltzmann machine (BM) with a symmetric connection matrix [J ] (Ji j=Jj i) that implements a given truth table with p -bits. The [J ] matrices are relatively sparse with a few unique weights for convenient hardware implementation. We then show how BM full adders can be interconnected in a partially directed manner (Ji j≠Jj i) to implement large logic operations such as 32-bit binary addition. Hundreds of stochastic p -bits get precisely correlated such that the correct answer out of 233 (≈8 ×1 09) possibilities can be extracted by looking at the statistical mode or majority vote of a number of time samples. With perfect directivity (Jj i=0 ) a small number of samples is enough, while for less directed connections more samples are needed, but even in the former case logical invertibility is largely preserved. This combination of digital accuracy and logical invertibility is enabled by the hybrid design that uses bidirectional BM units to construct circuits with partially directed interunit connections. We establish this key result with extensive examples including a 4-bit multiplier which in inverted mode functions as a factorizer.

A 12-bit high-speed column-parallel two-step single-slope analog-to-digital converter (ADC) for CMOS image sensors.

PubMed

Lyu, Tao; Yao, Suying; Nie, Kaiming; Xu, Jiangtao

2014-11-17

A 12-bit high-speed column-parallel two-step single-slope (SS) analog-to-digital converter (ADC) for CMOS image sensors is proposed. The proposed ADC employs a single ramp voltage and multiple reference voltages, and the conversion is divided into coarse phase and fine phase to improve the conversion rate. An error calibration scheme is proposed to correct errors caused by offsets among the reference voltages. The digital-to-analog converter (DAC) used for the ramp generator is based on the split-capacitor array with an attenuation capacitor. Analysis of the DAC's linearity performance versus capacitor mismatch and parasitic capacitance is presented. A prototype 1024 × 32 Time Delay Integration (TDI) CMOS image sensor with the proposed ADC architecture has been fabricated in a standard 0.18 μm CMOS process. The proposed ADC has average power consumption of 128 μW and a conventional rate 6 times higher than the conventional SS ADC. A high-quality image, captured at the line rate of 15.5 k lines/s, shows that the proposed ADC is suitable for high-speed CMOS image sensors.

Novel method of finding extreme edges in a convex set of N-dimension vectors

NASA Astrophysics Data System (ADS)

Hu, Chia-Lun J.

2001-11-01

As we published in the last few years, for a binary neural network pattern recognition system to learn a given mapping {Um mapped to Vm, m=1 to M} where um is an N- dimension analog (pattern) vector, Vm is a P-bit binary (classification) vector, the if-and-only-if (IFF) condition that this network can learn this mapping is that each i-set in {Ymi, m=1 to M} (where Ymithere existsVmiUm and Vmi=+1 or -1, is the i-th bit of VR-m).)(i=1 to P and there are P sets included here.) Is POSITIVELY, LINEARLY, INDEPENDENT or PLI. We have shown that this PLI condition is MORE GENERAL than the convexity condition applied to a set of N-vectors. In the design of old learning machines, we know that if a set of N-dimension analog vectors form a convex set, and if the machine can learn the boundary vectors (or extreme edges) of this set, then it can definitely learn the inside vectors contained in this POLYHEDRON CONE. This paper reports a new method and new algorithm to find the boundary vectors of a convex set of ND analog vectors.

Analog/digital pH meter system I.C.

NASA Technical Reports Server (NTRS)

Vincent, Paul; Park, Jea

1992-01-01

The project utilizes design automation software tools to design, simulate, and fabricate a pH meter integrated circuit (IC) system including a successive approximation type seven-bit analog to digital converter circuits using a 1.25 micron N-Well CMOS MOSIS process. The input voltage ranges from 0.5 to 1.0 V derived from a special type pH sensor, and the output is a three-digit decimal number display of pH with one decimal point.

Bidirectional fiber-IVLLC and fiber-wireless convergence system with two orthogonally polarized optical sidebands.

PubMed

Lu, Hai-Han; Wu, Hsiao-Wen; Li, Chung-Yi; Ho, Chun-Ming; Yang, Zih-Yi; Cheng, Ming-Te; Lu, Chang-Kai

2017-05-01

A bidirectional fiber-invisible laser light communication (IVLLC) and fiber-wireless convergence system with two orthogonally polarized optical sidebands for hybrid cable television (CATV)/millimeter-wave (MMW)/baseband (BB) signal transmission is proposed and experimentally demonstrated. Two optical sidebands generated by a 60-GHz MMW signal are orthogonally polarized and separated into different polarizations. These orthogonally polarized optical sidebands are delivered over a 40-km single-mode fiber (SMF) transport to effectually reduce the fiber dispersion induced by a 40-km SMF transmission and the distortion caused by the parallel polarized optical sidebands. To the best of our knowledge, this work is the first to adopt two orthogonally polarized optical sidebands in a bidirectional fiber-IVLLC and fiber-wireless convergence system to reduce fiber dispersion and distortion effectually. Good carrier-to-noise ratio, composite second order, composite triple beat, and bit error rate (BER) are achieved for downlink transmission at a 40-km SMF operation and a 100-m free-space optical (FSO) link/3-m RF wireless transmission. For up-link transmission, good BER performance is acquired over a 40-km SMF transport and a 100-m FSO link. The approach presented in this work signifies the advancements in the convergence of SMF-based backbone and optical/RF wireless-based feeder.

Computers in the General Physics Laboratory.

ERIC Educational Resources Information Center

Preston, Daryl W.; Good, R. H.

1996-01-01

Provides ideas and outcomes for nine computer laboratory experiments using a commercial eight-bit analog to digital (ADC) interface. Experiments cover statistics; rotation; harmonic motion; voltage, current, and resistance; ADC conversions; temperature measurement; single slit diffraction; and radioactive decay. Includes necessary schematics. (MVL)

Resonant Tunneling Analog-To-Digital Converter

NASA Technical Reports Server (NTRS)

Broekaert, T. P. E.; Seabaugh, A. C.; Hellums, J.; Taddiken, A.; Tang, H.; Teng, J.; vanderWagt, J. P. A.

1995-01-01

As sampling rates continue to increase, current analog-to-digital converter (ADC) device technologies will soon reach a practical resolution limit. This limit will most profoundly effect satellite and military systems used, for example, for electronic countermeasures, electronic and signal intelligence, and phased array radar. New device and circuit concepts will be essential for continued progress. We describe a novel, folded architecture ADC which could enable a technological discontinuity in ADC performance. The converter technology is based on the integration of multiple resonant tunneling diodes (RTD) and hetero-junction transistors on an indium phosphide substrate. The RTD consists of a layered semiconductor hetero-structure AlAs/InGaAs/AlAs(2/4/2 nm) clad on either side by heavily doped InGaAs contact layers. Compact quantizers based around the RTD offer a reduction in the number of components and a reduction in the input capacitance Because the component count and capacitance scale with the number of bits N, rather than by 2 (exp n) as in the flash ADC, speed can be significantly increased, A 4-bit 2-GSps quantizer circuit is under development to evaluate the performance potential. Circuit designs for ADC conversion with a resolution of 6-bits at 25GSps may be enabled by the resonant tunneling approach.

Coherent ultra dense wavelength division multiplexing passive optical networks

NASA Astrophysics Data System (ADS)

Shahpari, Ali; Ferreira, Ricardo; Ribeiro, Vitor; Sousa, Artur; Ziaie, Somayeh; Tavares, Ana; Vujicic, Zoran; Guiomar, Fernando P.; Reis, Jacklyn D.; Pinto, Armando N.; Teixeira, António

2015-12-01

In this paper, we firstly review the progress in ultra-dense wavelength division multiplexing passive optical network (UDWDM-PON), by making use of the key attributes of this technology in the context of optical access and metro networks. Besides the inherit properties of coherent technology, we explore different modulation formats and pulse shaping. The performance is experimentally demonstrated through a 12 × 10 Gb/s bidirectional UDWDM-PON over hybrid 80 km standard single mode fiber (SSMF) and optical wireless link. High density, 6.25 GHz grid, Nyquist shaped 16-ary quadrature amplitude modulation (16QAM) and digital frequency shifting are some of the properties exploited together in the tests. Also, bidirectional transmission in fiber, relevant in the context, is analyzed in terms of nonlinear and back-reflection effects on receiver sensitivity. In addition, as a basis for the discussion on market readiness, we experimentally demonstrate real-time detection of a Nyquist-shaped quaternary phase-shift keying (QPSK) signal using simple 8-bit digital signal processing (DSP) on a field-programmable gate array (FPGA).

Next-generation bidirectional Triple-play services using RSOA based WDM Radio on Free-Space Optics PON

NASA Astrophysics Data System (ADS)

Mandal, Gour Chandra; Mukherjee, Rahul; Das, Binoy; Patra, Ardhendu Sekhar

2018-03-01

An innovative low cost reflective semiconductor amplifier (RSOA) based bidirectional Triple-play services (TPS) using wavelength division multiplexed radio on free-space-optics passive optical network (WDM-RoFSO-PON) is proposed and experimentally demonstrated to transmit data, voice and video services simultaneously. In this paper, the TPS (10 Gb/s data/voice and 1.49 Gb/s HDTV signal) are successfully transmitted over a 500 m free-space link in downstream and RSOA is utilized at the receiving site to broadcast 1.25 Gb/s data/voice signal over same free-space link in upstream by reusing the carrier, that makes the system cost-effective. High receiver sensitivity and signal-to-noise ratio (SNR), low bit-error-rate (BER) and low error vector magnitude (EVM), and excellent eye-diagrams in our proposed network build the system more reliable and stable with acceptable performance. Therefore, proposed WDM-RoFSO-PON could be the viable solution for future ubiquitous multiservice wireless network in the scenario of TPS.

Miniaturized module for the wireless transmission of measurements with Bluetooth.

PubMed

Roth, H; Schwaibold, M; Moor, C; Schöchlin, J; Bolz, A

2002-01-01

The wiring of patients for obtaining medical measurements has many disadvantages. In order to limit these, a miniaturized module was developed which digitalizes analog signals and sends the signal wirelessly to the receiver using Bluetooth. Bluetooth is especially suitable for this application because distances of up to 10 m are possible with low power consumption and robust transmission with encryption. The module consists of a Bluetooth chip, which is initialized in such a way by a microcontroller that connections from other bluetooth receivers can be accepted. The signals are then transmitted to the distant end. The maximum bit rate of the 23 mm x 30 mm module is 73.5 kBit/s. At 4.7 kBit/s, the current consumption is 12 mA.

Lessons Learned in the Specification, Purchase, Validation and Final Installation Process of a Replacement PCM Bit Synchronizer

NASA Technical Reports Server (NTRS)

Price, Richard N.

2007-01-01

This paper intends to describe the lessons learned while specifying validating and installing a bit sync to replace the 30 year old Aydin Model 335a PCM bit sync used in the Space Shuttle Launch Control Center. The engineer had to analyze the original requirements and specifications and then create new requirements documentation that more correctly described our needs. One issue to consider was the removal of unnecessary requirements such as various data formats when only one format is used. The conversion to a system that no longer has an assortment of analog rotary switches required retraining of the operators. Finally, post-procurement corrections for undisclosed user requirements and missed design requirements required close contact with a manufacturer who was willing to accommodate the changes.

Eight-Channel Digital Signal Processor and Universal Trigger Module

NASA Astrophysics Data System (ADS)

Skulski, Wojtek; Wolfs, Frank

2003-04-01

A 10-bit, 8-channel, 40 megasamples per second digital signal processor and waveform digitizer DDC-8 (nicknamed Universal Trigger Module) is presented. The digitizer features 8 analog inputs, 1 analog output for a reconstructed analog waveform, 16 NIM logic inputs, 8 NIM logic outputs, and a pool of 16 TTL logic lines which can be individually configured as either inputs or outputs. The first application of this device is to enhance the present trigger electronics for PHOBOS at RHIC. The status of the development and the first results are presented. Possible applications of the new device are discussed. Supported by the NSF grant PHY-0072204.

Simple Multiplexing Hand-Held Control Unit

NASA Technical Reports Server (NTRS)

Hannaford, Blake

1989-01-01

Multiplexer consists of series of resistors, each shunted by single-pole, single-throw switch. User operates switches by pressing buttons or squeezing triggers. Prototype includes three switches operated successfully in over 200 hours of system operations. Number of switches accommodated determined by signal-to-noise ratio of current source, noise induced in control unit and cable, and number of bits in output of analog-to-digital converter. Because many computer-contolled robots have extra analog-to-digital channels, such multiplexer added at little extra cost.

SEMICONDUCTOR INTEGRATED CIRCUITS A 10-bit 200-kS/s SAR ADC IP core for a touch screen SoC

NASA Astrophysics Data System (ADS)

Xingyuan, Tong; Yintang, Yang; Zhangming, Zhu; Wenfang, Sheng

2010-10-01

Based on a 5 MSBs (most-significant-bits)-plus-5 LSBs (least-significant-bits) C-R hybrid D/A conversion and low-offset pseudo-differential comparison approach, with capacitor array axially symmetric layout topology and resistor string low gradient mismatch placement method, an 8-channel 10-bit 200-kS/s SAR ADC (successive-approximation-register analog-to-digital converter) IP core for a touch screen SoC (system-on-chip) is implemented in a 0.18 μm 1P5M CMOS logic process. Design considerations for the touch screen SAR ADC are included. With a 1.8 V power supply, the DNL (differential non-linearity) and INL (integral non-linearity) of this converter are measured to be about 0.32 LSB and 0.81 LSB respectively. With an input frequency of 91 kHz at 200-kS/s sampling rate, the spurious-free dynamic range and effective-number-of-bits are measured to be 63.2 dB and 9.15 bits respectively, and the power is about 136 μW. This converter occupies an area of about 0.08 mm2. The design results show that it is very suitable for touch screen SoC applications.

Cost-effective bidirectional digitized radio-over-fiber systems employing sigma delta modulation

NASA Astrophysics Data System (ADS)

Lee, Kyung Woon; Jung, HyunDo; Park, Jung Ho

2016-11-01

We propose a cost effective digitized radio-over-fiber (D-RoF) system employing a sigma delta modulation (SDM) and a bidirectional transmission technique using phase modulated downlink and intensity modulated uplink. SDM is transparent to different radio access technologies and modulation formats, and more suitable for a downlink of wireless system because a digital to analog converter (DAC) can be avoided at the base station (BS). Also, Central station and BS share the same light source by using a phase modulation for the downlink and an intensity modulation for the uplink transmission. Avoiding DACs and light sources have advantages in terms of cost reduction, power consumption, and compatibility with conventional wireless network structure. We have designed a cost effective bidirectional D-RoF system using a low pass SDM and measured the downlink and uplink transmission performance in terms of error vector magnitude, signal spectra, and constellations, which are based on the 10MHz LTE 64-QAM standard.

Multiplexed Oversampling Digitizer in 65 nm CMOS for Column-Parallel CCD Readout

DOE Office of Scientific and Technical Information (OSTI.GOV)

Grace, Carl; Walder, Jean-Pierre; von der Lippe, Henrik

2012-04-10

A digitizer designed to read out column-parallel charge-coupled devices (CCDs) used for high-speed X-ray imaging is presented. The digitizer is included as part of the High-Speed Image Preprocessor with Oversampling (HIPPO) integrated circuit. The digitizer module comprises a multiplexed, oversampling, 12-bit, 80 MS/s pipelined Analog-to-Digital Converter (ADC) and a bank of four fast-settling sample-and-hold amplifiers to instrument four analog channels. The ADC multiplexes and oversamples to reduce its area to allow integration that is pitch-matched to the columns of the CCD. Novel design techniques are used to enable oversampling and multiplexing with a reduced power penalty. The ADC exhibits 188more » ?V-rms noise which is less than 1 LSB at a 12-bit level. The prototype is implemented in a commercially available 65 nm CMOS process. The digitizer will lead to a proof-of-principle 2D 10 Gigapixel/s X-ray detector.« less

Testing of the Prototype Mars Drill and Sample Acquisition System in the Mars Analog Site of the Antarctica's Dry Valleys

NASA Astrophysics Data System (ADS)

Zacny, K.; Paulsen, G.; McKay, C.; Glass, B. J.; Marinova, M.; Davila, A. F.; Pollard, W. H.; Jackson, A.

2011-12-01

We report on the testing of the one meter class prototype Mars drill and cuttings sampling system, called the IceBreaker in the Dry Valleys of Antarctica. The drill consists of a rotary-percussive drill head, a sampling auger with a bit at the end having an integrated temperature sensor, a Z-stage for advancing the auger into the ground, and a sampling station for moving the augered ice shavings or soil cuttings into a sample cup. In November/December of 2010, the IceBreaker drill was tested in the Uni-versity Valley (within the Beacon Valley region of the Antarctic Dry Valleys). University Valley is a good analog to the Northern Polar Regions of Mars because a layer of dry soil lies on top of either ice-cemeted ground or massive ice (depending on the location within the valley). That is exactly what the 2007 Phoenix mission discovered on Mars. The drill demonstrated drilling in ice-cemented ground and in massive ice at the 1-1-100-100 level; that is the drill reached 1 meter in 1 hour with 100 Watts of power and 100 Newton Weight on Bit. This corresponds to an average energy of 100 Whr. At the same time, the bit temperature measured by the bit thermocouple did not exceed more than 10 °C above the formation temperature. The temperature also never exceeded freezing, which minimizes chances of getting stuck and also of altering the materials that are being sampled and analyzed. The samples in the forms of cuttings were acquired every 10 cm intervals into sterile bags. These tests have shown that drilling on Mars, in ice cemented ground with limited power, energy and Weight on Bit, and collecting samples in discrete depth intervals is possible within the given mass, power, and energy levels of a Phoenix-size lander and within the duration of a Phoenix-like mission.

Digital plus analog output encoder

NASA Technical Reports Server (NTRS)

Hafle, R. S. (Inventor)

1976-01-01

The disclosed encoder is adapted to produce both digital and analog output signals corresponding to the angular position of a rotary shaft, or the position of any other movable member. The digital signals comprise a series of binary signals constituting a multidigit code word which defines the angular position of the shaft with a degree of resolution which depends upon the number of digits in the code word. The basic binary signals are produced by photocells actuated by a series of binary tracks on a code disc or member. The analog signals are in the form of a series of ramp signals which are related in length to the least significant bit of the digital code word. The analog signals are derived from sine and cosine tracks on the code disc.

An Open Hardware seismic data recorder - a solid basis for citizen science

NASA Astrophysics Data System (ADS)

Mertl, Stefan

2015-04-01

"Ruwai" is a 24-Bit Open Hardware seismic data recorder. It is built up of four stackable printed circuit boards fitting the Arduino Mega 2560 microcontroller prototyping platform. An interface to the BeagleBone Black single-board computer enables extensive data storage, -processing and networking capabilities. The four printed circuit boards provide a uBlox Lea-6T GPS module and real-time clock (GPS Timing shield), an Texas Instruments ADS1274 24-Bit analog to digital converter (ADC main shield), an analog input section with a Texas Instruments PGA281 programmable gain amplifier and an analog anti-aliasing filter (ADC analog interface pga) and the power conditioning based on 9-36V DC input (power supply shield). The Arduino Mega 2560 is used for controlling the hardware components, timestamping sampled data using the GPS timing information and transmitting the data to the BeagleBone Black single-board computer. The BeagleBone Black provides local data storage, wireless mesh networking using the optimized link state routing daemon and differential GNSS positioning using the RTKLIB software. The complete hardware and software is published under free software - or open hardware licenses and only free software (e.g. KiCad) was used for the development to facilitate the reusability of the design and increases the sustainability of the project. "Ruwai" was developed within the framework of the "Community Environmental Observation Network (CEON)" (http://www.mertl-research.at/ceon/) which was supported by the Internet Foundation Austria (IPA) within the NetIdee 2013 call.

Topological solitons as addressable phase bits in a driven laser

NASA Astrophysics Data System (ADS)

Garbin, Bruno; Javaloyes, Julien; Tissoni, Giovanna; Barland, Stéphane

2015-01-01

Optical localized states are usually defined as self-localized bistable packets of light, which exist as independently controllable optical intensity pulses either in the longitudinal or transverse dimension of nonlinear optical systems. Here we demonstrate experimentally and analytically the existence of longitudinal localized states that exist fundamentally in the phase of laser light. These robust and versatile phase bits can be individually nucleated and canceled in an injection-locked semiconductor laser operated in a neuron-like excitable regime and submitted to delayed feedback. The demonstration of their control opens the way to their use as phase information units in next-generation coherent communication systems. We analyse our observations in terms of a generic model, which confirms the topological nature of the phase bits and discloses their formal but profound analogy with Sine-Gordon solitons.

55-mW, 1.2-V, 12-bit, 100-MSPS Pipeline ADCs for Wireless Receivers

NASA Astrophysics Data System (ADS)

Ito, Tomohiko; Kurose, Daisuke; Ueno, Takeshi; Yamaji, Takafumi; Itakura, Tetsuro

For wireless receivers, low-power 1.2-V 12-bit 100-MSPS pipeline ADCs are fabricated in 90-nm CMOS technology. To achieve low-power dissipation at 1.2V without the degradation of SNR, the configuration of 2.5bit/stage is employed with an I/Q amplifier sharing technique. Furthermore, single-stage pseudo-differential amplifiers are used in a Sample-and-Hold (S/H) circuit and a 1st Multiplying Digital-to-Analog Converter (MDAC). The pseudo-differential amplifier with two-gain-stage transimpedance gain-boosting amplifiers realizes high DC gain of more than 90dB with low power. The measured SNR of the 100-MSPS ADC is 66.7dB at 1.2-V supply. Under that condition, each ADC dissipates only 55mW.

High-performance dual-speed CCD camera system for scientific imaging

NASA Astrophysics Data System (ADS)

Simpson, Raymond W.

1996-03-01

Traditionally, scientific camera systems were partitioned with a `camera head' containing the CCD and its support circuitry and a camera controller, which provided analog to digital conversion, timing, control, computer interfacing, and power. A new, unitized high performance scientific CCD camera with dual speed readout at 1 X 106 or 5 X 106 pixels per second, 12 bit digital gray scale, high performance thermoelectric cooling, and built in composite video output is described. This camera provides all digital, analog, and cooling functions in a single compact unit. The new system incorporates the A/C converter, timing, control and computer interfacing in the camera, with the power supply remaining a separate remote unit. A 100 Mbyte/second serial link transfers data over copper or fiber media to a variety of host computers, including Sun, SGI, SCSI, PCI, EISA, and Apple Macintosh. Having all the digital and analog functions in the camera made it possible to modify this system for the Woods Hole Oceanographic Institution for use on a remote controlled submersible vehicle. The oceanographic version achieves 16 bit dynamic range at 1.5 X 105 pixels/second, can be operated at depths of 3 kilometers, and transfers data to the surface via a real time fiber optic link.

A cryogenic DAC operating down to 4.2 K

NASA Astrophysics Data System (ADS)

Rahman, M. T.; Lehmann, T.

2016-04-01

This paper presents a 10 bit CMOS current steering digital to analog converter (DAC) that operates from room temperature to as low as 4.2 K. It works as the core part of a cryogenic Silicon quantum computer controller circuit producing rapid control gate voltage pulses for quantum bits (qubits) initialization. An improved analog calibration method with a unique unit current cell design is included in the D/A converter structure to overcome the extended cryogenic nonlinear and mismatch effects. The DAC retains its 10 bit linear monotonic behavior over the wide temperature range and it drives a 50 Ω load to 516 mV with a full scale rise time of 10 ns. The differential non-linearity (DNL) of the converter is 0.35LSB while its average power consumption is 32.18 mW from a 3 V power supply. The complete converter is fabricated using a commercial 0.5 μm 1 poly 3 metal Silicon on Sapphire (SOS) CMOS process. He briefly worked as a Lecturer in the Stamford University Bangladesh prior to starting his Ph.D. in 2012 in the School of Electrical Engineering and Telecommunications, UNSW. His Ph.D. research is focused on cryogenic electronics for Quantum Computer Interface. His main research interests are in designing data converters for ultra-low temperature electronics and biomedical applications. He spent two years as a Research Fellow at the University of Edinburgh, U.K., where he worked with biologically inspired artificial neural systems. From 1997 to 2000, he was an Assistant Professor in electronics at the Technical University of Denmark, working with low-power low-noise low-voltage analog and mixed analog-digital integrated circuits. From 2001 to 2003 he was Principal Engineer with Cochlear Ltd., Australia, where he was involved in the design of the world's first fully implantable cochlear implant. Today he is Associate Professor in microelectronics at the University of New South Wales, Australia. He has authored over 100 journal papers, conference papers, book chapters and patents in microelectronic circuit design for a range of applications. His main research interests are in solid-state circuits and systems (analog and digital), biomedical microelectronics, ultra-low temperature electronics, nanometre CMOS, and green electronics.

Sleep stage classification with low complexity and low bit rate.

PubMed

Virkkala, Jussi; Värri, Alpo; Hasan, Joel; Himanen, Sari-Leena; Müller, Kiti

2009-01-01

Standard sleep stage classification is based on visual analysis of central (usually also frontal and occipital) EEG, two-channel EOG, and submental EMG signals. The process is complex, using multiple electrodes, and is usually based on relatively high (200-500 Hz) sampling rates. Also at least 12 bit analog to digital conversion is recommended (with 16 bit storage) resulting in total bit rate of at least 12.8 kbit/s. This is not a problem for in-house laboratory sleep studies, but in the case of online wireless self-applicable ambulatory sleep studies, lower complexity and lower bit rates are preferred. In this study we further developed earlier single channel facial EMG/EOG/EEG-based automatic sleep stage classification. An algorithm with a simple decision tree separated 30 s epochs into wakefulness, SREM, S1/S2 and SWS using 18-45 Hz beta power and 0.5-6 Hz amplitude. Improvements included low complexity recursive digital filtering. We also evaluated the effects of a reduced sampling rate, reduced number of quantization steps and reduced dynamic range on the sleep data of 132 training and 131 testing subjects. With the studied algorithm, it was possible to reduce the sampling rate to 50 Hz (having a low pass filter at 90 Hz), and the dynamic range to 244 microV, with an 8 bit resolution resulting in a bit rate of 0.4 kbit/s. Facial electrodes and a low bit rate enables the use of smaller devices for sleep stage classification in home environments.

Method and apparatus for analog signal conditioner for high speed, digital x-ray spectrometer

DOEpatents

Warburton, William K.; Hubbard, Bradley

1999-01-01

A signal processing system which accepts input from an x-ray detector-preamplifier and produces a signal of reduced dynamic range for subsequent analog-to-digital conversion. The system conditions the input signal to reduce the number of bits required in the analog-to-digital converter by removing that part of the input signal which varies only slowly in time and retaining the amplitude of the pulses which carry information about the x-rays absorbed by the detector. The parameters controlling the signal conditioner's operation can be readily supplied in digital form, allowing it to be integrated into a feedback loop as part of a larger digital x-ray spectroscopy system.

The interplay of conflict and analogy in multidisciplinary teams.

PubMed

Paletz, Susannah B F; Schunn, Christian D; Kim, Kevin H

2013-01-01

Creative teamwork in multidisciplinary teams is a topic of interest to cognitive psychologists on the one hand, and to both social and organizational psychologists on the other. However, the interconnections between cognitive and social layers have been rarely explored. Drawing on mental models and dissonance theories, the current study takes a central variable studied by cognitive psychologists-analogy-and examines its relationship to a central variable examined by social psychologists-conflict. In an observational, field study, over 11h of audio-video data from conversations of the Mars Exploration Rover scientists were coded for different types of analogy and micro-conflicts that reveal the character of underlying psychological mechanisms. Two different types of time-lagged logistic models applied to these data revealed asymmetric patterns of associations between analogy and conflict. Within-domain analogies, but not within-discipline or outside-discipline analogies, preceded science and work process conflicts, suggesting that in multidisciplinary teams, representational gaps in very close domains will be more likely to spark conflict. But analogies also occurred in reaction to conflict: Process and negative conflicts, but not task conflicts, preceded within-discipline analogies, but not to within-domain or outside-discipline analogies. This study demonstrates ways in which cognition can be bidirectionally tied to social processes and discourse. Copyright © 2012 Elsevier B.V. All rights reserved.

47 CFR 101.75 - Involuntary relocation procedures.

Code of Federal Regulations, 2010 CFR

2010-10-01

... engineering, equipment, site and FCC fees, as well as any legitimate and prudent transaction expenses incurred... reliability of their system. For digital data systems, reliability is measured by the percent of time the bit error rate (BER) exceeds a desired value, and for analog or digital voice transmissions, it is measured...

47 CFR 101.91 - Involuntary relocation procedures.

Code of Federal Regulations, 2010 CFR

2010-10-01

... engineering, equipment, site and FCC fees, as well as any legitimate and prudent transaction expenses incurred..., reliability is measured by the percent of time the bit error rate (BER) exceeds a desired value, and for analog or digital voice transmissions, it is measured by the percent of time that audio signal quality...

Personal Fabrication Systems: From Bits to Atoms

ERIC Educational Resources Information Center

Bull, Glen; Garofalo, Joe

2009-01-01

Media--text, images, audio, and video--underwent a transformation from analog to digital formats during the transition from the 20th to the 21st century. Digital media can easily be replicated, downloaded, revised, edited, and reposted, and the implications of this are affecting education, government, entertainment, culture, and society. The…

A 9-Bit 50 MSPS Quadrature Parallel Pipeline ADC for Communication Receiver Application

NASA Astrophysics Data System (ADS)

Roy, Sounak; Banerjee, Swapna

2018-03-01

This paper presents the design and implementation of a pipeline Analog-to-Digital Converter (ADC) for superheterodyne receiver application. Several enhancement techniques have been applied in implementing the ADC, in order to relax the target specifications of its building blocks. The concepts of time interleaving and double sampling have been used simultaneously to enhance the sampling speed and to reduce the number of amplifiers used in the ADC. Removal of a front end sample-and-hold amplifier is possible by employing dynamic comparators with switched capacitor based comparison of input signal and reference voltage. Each module of the ADC comprises two 2.5-bit stages followed by two 1.5-bit stages and a 3-bit flash stage. Four such pipeline ADC modules are time interleaved using two pairs of non-overlapping clock signals. These two pairs of clock signals are in phase quadrature with each other. Hence the term quadrature parallel pipeline ADC has been used. These configurations ensure that the entire ADC contains only eight operational-trans-conductance amplifiers. The ADC is implemented in a 0.18-μm CMOS process and supply voltage of 1.8 V. The proto-type is tested at sampling frequencies of 50 and 75 MSPS producing an Effective Number of Bits (ENOB) of 6.86- and 6.11-bits respectively. At peak sampling speed, the core ADC consumes only 65 mW of power.

A 9-Bit 50 MSPS Quadrature Parallel Pipeline ADC for Communication Receiver Application

NASA Astrophysics Data System (ADS)

Roy, Sounak; Banerjee, Swapna

2018-06-01

This paper presents the design and implementation of a pipeline Analog-to-Digital Converter (ADC) for superheterodyne receiver application. Several enhancement techniques have been applied in implementing the ADC, in order to relax the target specifications of its building blocks. The concepts of time interleaving and double sampling have been used simultaneously to enhance the sampling speed and to reduce the number of amplifiers used in the ADC. Removal of a front end sample-and-hold amplifier is possible by employing dynamic comparators with switched capacitor based comparison of input signal and reference voltage. Each module of the ADC comprises two 2.5-bit stages followed by two 1.5-bit stages and a 3-bit flash stage. Four such pipeline ADC modules are time interleaved using two pairs of non-overlapping clock signals. These two pairs of clock signals are in phase quadrature with each other. Hence the term quadrature parallel pipeline ADC has been used. These configurations ensure that the entire ADC contains only eight operational-trans-conductance amplifiers. The ADC is implemented in a 0.18-μm CMOS process and supply voltage of 1.8 V. The proto-type is tested at sampling frequencies of 50 and 75 MSPS producing an Effective Number of Bits (ENOB) of 6.86- and 6.11-bits respectively. At peak sampling speed, the core ADC consumes only 65 mW of power.

Enhanced intercarrier interference mitigation based on encoded bit-sequence distribution inside optical superchannels

NASA Astrophysics Data System (ADS)

Torres, Jhon James Granada; Soto, Ana María Cárdenas; González, Neil Guerrero

2016-10-01

In the context of gridless optical multicarrier systems, we propose a method for intercarrier interference (ICI) mitigation which allows bit error correction in scenarios of nonspectral flatness between the subcarriers composing the multicarrier system and sub-Nyquist carrier spacing. We propose a hybrid ICI mitigation technique which exploits the advantages of signal equalization at both levels: the physical level for any digital and analog pulse shaping, and the bit-data level and its ability to incorporate advanced correcting codes. The concatenation of these two complementary techniques consists of a nondata-aided equalizer applied to each optical subcarrier, and a hard-decision forward error correction applied to the sequence of bits distributed along the optical subcarriers regardless of prior subchannel quality assessment as performed in orthogonal frequency-division multiplexing modulations for the implementation of the bit-loading technique. The impact of the ICI is systematically evaluated in terms of bit-error-rate as a function of the carrier frequency spacing and the roll-off factor of the digital pulse-shaping filter for a simulated 3×32-Gbaud single-polarization quadrature phase shift keying Nyquist-wavelength division multiplexing system. After the ICI mitigation, a back-to-back error-free decoding was obtained for sub-Nyquist carrier spacings of 28.5 and 30 GHz and roll-off values of 0.1 and 0.4, respectively.

The Random Telegraph Signal Behavior of Intermittently Stuck Bits in SDRAMs

NASA Astrophysics Data System (ADS)

Chugg, Andrew Michael; Burnell, Andrew J.; Duncan, Peter H.; Parker, Sarah; Ward, Jonathan J.

2009-12-01

This paper reports behavior analogous to the Random Telegraph Signal (RTS) seen in the leakage currents from radiation induced hot pixels in Charge Coupled Devices (CCDs), but in the context of stuck bits in Synchronous Dynamic Random Access Memories (SDRAMs). Our analysis suggests that pseudo-random sticking and unsticking of the SDRAM bits is due to thermally induced fluctuations in leakage current through displacement damage complexes in depletion regions that were created by high-energy neutron and proton interactions. It is shown that the number of observed stuck bits increases exponentially with temperature, due to the general increase in the leakage currents through the damage centers with temperature. Nevertheless, some stuck bits are seen to pseudo-randomly stick and unstick in the context of a continuously rising trend of temperature, thus demonstrating that their damage centers can exist in multiple widely spaced, discrete levels of leakage current, which is highly consistent with RTS. This implies that these intermittently stuck bits (ISBs) are a displacement damage phenomenon and are unrelated to microdose issues, which is confirmed by the observation that they also occur in unbiased irradiation. Finally, we note that observed variations in the periodicity of the sticking and unsticking behavior on several timescales is most readily explained by multiple leakage current pathways through displacement damage complexes spontaneously and independently opening and closing under the influence of thermal vibrations.

Time of flight system on a chip

NASA Technical Reports Server (NTRS)

Paschalidis, Nicholas P. (Inventor)

2006-01-01

A CMOS time-of-flight TOF system-on-a-chip SoC for precise time interval measurement with low power consumption and high counting rate has been developed. The analog and digital TOF chip may include two Constant Fraction Discriminators CFDs and a Time-to-Digital Converter TDC. The CFDs can interface to start and stop anodes through two preamplifiers and perform signal processing for time walk compensation (110). The TDC digitizes the time difference with reference to an off-chip precise external clock (114). One TOF output is an 11-bit digital word and a valid event trigger output indicating a valid event on the 11-bit output bus (116).

Experimental Primer on the Trapped Ion Quantum Computer

DTIC Science & Technology

1998-01-01

analogously), then exposing this ion to a traveling- wave electric field E�r� � E0 cos �k rÿ wLt � j� with frequency wL, phase j, and wavevector k, results...eih�a�a y��ij � Sjÿ eÿih�a�a y�ÿij� �4� in a frame rotating at wL, where terms oscillating faster than W j �Wj wz; w0� have been neglected. Here, h...of the single bit rotation gate and the two-bit controlled-NOT gate [34]. For brevity, we concentrate on these two gates and how they can be

NbN A/D Conversion of IR Focal Plane Sensor Signal at 10 K

NASA Technical Reports Server (NTRS)

Eaton, L.; Durand, D.; Sandell, R.; Spargo, J.; Krabach, T.

1994-01-01

We are implementing a 12 bit SFQ counting ADC with parallel-to-serial readout using our established 10 K NbN capability. This circuit provides a key element of the analog signal processor (ASP) used in large infrared focal plane arrays. The circuit processes the signal data stream from a Si:As BIB detector array. A 10 mega samples per second (MSPS) pixel data stream flows from the chip at a 120 megabit bit rate in a format that is compatible with other superconductive time dependent processor (TDP) circuits being developed. We will discuss our planned ASP demonstration, the circuit design, and test results.

Hardware description ADSP-21020 40-bit floating point DSP as designed in a remotely controlled digital CW Doppler radar

NASA Astrophysics Data System (ADS)

Morrison, R. E.; Robinson, S. H.

A continuous wave Doppler radar system has been designed which is portable, easily deployed, and remotely controlled. The heart of this system is a DSP/control board using Analog Devices ADSP-21020 40-bit floating point digital signal processor (DSP) microprocessor. Two 18-bit audio A/D converters provide digital input to the DSP/controller board for near real time target detection. Program memory for the DSP is dual ported with an Intel 87C51 microcontroller allowing DSP code to be up-loaded or down-loaded from a central controlling computer. The 87C51 provides overall system control for the remote radar and includes a time-of-day/day-of-year real time clock, system identification (ID) switches, and input/output (I/O) expansion by an Intel 82C55 I/O expander.

A high SFDR 6-bit 20-MS/s SAR ADC based on time-domain comparator

NASA Astrophysics Data System (ADS)

Xue, Han; Hua, Fan; Qi, Wei; Huazhong, Yang

2013-08-01

This paper presents a 6-bit 20-MS/s high spurious-free dynamic range (SFDR) and low power successive approximation register analog to digital converter (SAR ADC) for the radio-frequency (RF) transceiver front-end, especially for wireless sensor network (WSN) applications. This ADC adopts the modified common-centroid symmetry layout and the successive approximation register reset circuit to improve the linearity and dynamic range. Prototyped in a 0.18-μm 1P6M CMOS technology, the ADC performs a peak SFDR of 55.32 dB and effective number of bits (ENOB) of 5.1 bit for 10 MS/s. At the sample rate of 20 MS/s and the Nyquist input frequency, the 47.39-dB SFDR and 4.6-ENOB are achieved. The differential nonlinearity (DNL) is less than 0.83 LSB and the integral nonlinearity (INL) is less than 0.82 LSB. The experimental results indicate that this SAR ADC consumes a total of 522 μW power and occupies 0.98 mm2.

Compact FPGA-based beamformer using oversampled 1-bit A/D converters.

PubMed

Tomov, Borislav Gueorguiev; Jensen, Jørgen Arendt

2005-05-01

A compact medical ultrasound beamformer architecture that uses oversampled 1-bit analog-to-digital (A/D) converters is presented. Sparse sample processing is used, as the echo signal for the image lines is reconstructed in 512 equidistant focal points along the line through its in-phase and quadrature components. That information is sufficient for presenting a B-mode image and creating a color flow map. The high sampling rate provides the necessary delay resolution for the focusing. The low channel data width (1-bit) makes it possible to construct a compact beamformer logic. The signal reconstruction is done using finite impulse reponse (FIR) filters, applied on selected bit sequences of the delta-sigma modulator output stream. The approach allows for a multichannel beamformer to fit in a single field programmable gate array (FPGA) device. A 32-channel beamformer is estimated to occupy 50% of the available logic resources in a commercially available mid-range FPGA, and to be able to operate at 129 MHz. Simulation of the architecture at 140 MHz provides images with a dynamic range approaching 60 dB for an excitation frequency of 3 MHz.

Method and apparatus for analog signal conditioner for high speed, digital x-ray spectrometer

DOEpatents

Warburton, W.K.; Hubbard, B.

1999-02-09

A signal processing system which accepts input from an x-ray detector-preamplifier and produces a signal of reduced dynamic range for subsequent analog-to-digital conversion is disclosed. The system conditions the input signal to reduce the number of bits required in the analog-to-digital converter by removing that part of the input signal which varies only slowly in time and retaining the amplitude of the pulses which carry information about the x-rays absorbed by the detector. The parameters controlling the signal conditioner`s operation can be readily supplied in digital form, allowing it to be integrated into a feedback loop as part of a larger digital x-ray spectroscopy system. 13 figs.

A wideband-PCM recorder for the Space Shuttle orbiter

NASA Technical Reports Server (NTRS)

Petit, R. D.

1976-01-01

The Shuttle wideband-PCM recorder accomplishes recording on up to 14 data tracks with analog or digital data inputs. FM multiplexed analog frequencies of up to 2 MHz and digital rates of 1 Mb/s are accommodated at a tape speed of 120 in/s. Recording time in analog mode varies between 4 min for 2 MHz data to 80 min for 100 kHz data. The total digital data storage is 3.44 x 10 to the 9th bits with recording times from 1 hour for 1 Mb/s to 19 hours for 50 Kb/s data in the serial track switching mode. A versatile command decoder and control interface are used for eight primary modes of operation.

Controlling a Four-Quadrant Brushless Three-Phase dc Motor

NASA Technical Reports Server (NTRS)

Nola, F. J.

1986-01-01

Control circuit commutates windings of brushless, three-phase, permanent-magnet motor operating from power supply. With single analog command voltage, controller makes motor accelerate, drive steadily, or brake regeneratively, in clockwise or counterclockwise direction. Controller well suited for use with energy-storage flywheels, actuators for aircraft-control surfaces, cranes, industrial robots, and other electromechanical systems requiring bidirectional control or sudden stopping and reversal.

Interface Provides Standard-Bus Communication

NASA Technical Reports Server (NTRS)

Culliton, William G.

1995-01-01

Microprocessor-controlled interface (IEEE-488/LVABI) incorporates service-request and direct-memory-access features. Is circuit card enabling digital communication between system called "laser auto-covariance buffer interface" (LVABI) and compatible personal computer via general-purpose interface bus (GPIB) conforming to Institute for Electrical and Electronics Engineers (IEEE) Standard 488. Interface serves as second interface enabling first interface to exploit advantages of GPIB, via utility software written specifically for GPIB. Advantages include compatibility with multitasking and support of communication among multiple computers. Basic concept also applied in designing interfaces for circuits other than LVABI for unidirectional or bidirectional handling of parallel data up to 16 bits wide.

RF digital-to-analog converter

DOEpatents

Conway, Patrick H.; Yu, David U. L.

1995-01-01

A digital-to analogue converter for producing an RF output signal proportional to a digital input word of N bits from an RF reference input, N being an integer greater or equal to 2. The converter comprises a plurality of power splitters, power combiners and a plurality of mixers or RF switches connected in a predetermined configuration.

47 CFR 27.1252 - Involuntary Relocation Procedures.

Code of Federal Regulations, 2010 CFR

2010-10-01

... costs, including all engineering, equipment, site and FCC fees, as well as any legitimate and prudent... measured by the percent of time the bit error rate (BER) exceeds a desired value, and for analog or digital video transmissions, it is measured by whether the end-to-end transmission delay is within the required...

Ocean Basin Impact of Ambient Noise on Marine Mammal Detectability, Distribution, and Acoustic Communication - YIP

DTIC Science & Technology

2011-09-30

when applying the 4 passive sonar equation. The integration of acoustic time series from different ocean basins will provide a synoptic...Penn State ARL Hydrophone Analog signal (V) Preamplifiers & 24-bit AiD 1-100 HzBP filter Signal Flow for a Single Hydrophone Digital signal

A compact, multichannel, and low noise arbitrary waveform generator

DOE Office of Scientific and Technical Information (OSTI.GOV)

Govorkov, S.; Ivanov, B. I.; Novosibirsk State Technical University, K.Marx-Ave. 20, Novosibirsk 630092

2014-05-15

A new type of high functionality, fast, compact, and easy programmable arbitrary waveform generator for low noise physical measurements is presented. The generator provides 7 fast differential waveform channels with a maximum bandwidth up to 200 MHz frequency. There are 6 fast pulse generators on the generator board with 78 ps time resolution in both duration and delay, 3 of them with amplitude control. The arbitrary waveform generator is additionally equipped with two auxiliary slow 16 bit analog-to-digital converters and four 16 bit digital-to-analog converters for low frequency applications. Electromagnetic shields are introduced to the power supply, digital, and analogmore » compartments and with a proper filter design perform more than 110 dB digital noise isolation to the output signals. All the output channels of the board have 50 Ω SubMiniature version A termination. The generator board is suitable for use as a part of a high sensitive physical equipment, e.g., fast read out and manipulation of nuclear magnetic resonance or superconducting quantum systems and any other application, which requires electromagnetic interference free fast pulse and arbitrary waveform generation.« less

Experimental demonstration of the optical multi-mesh hypercube: scaleable interconnection network for multiprocessors and multicomputers.

PubMed

Louri, A; Furlonge, S; Neocleous, C

1996-12-10

A prototype of a novel topology for scaleable optical interconnection networks called the optical multi-mesh hypercube (OMMH) is experimentally demonstrated to as high as a 150-Mbit/s data rate (2(7) - 1 nonreturn-to-zero pseudo-random data pattern) at a bit error rate of 10(-13)/link by the use of commercially available devices. OMMH is a scaleable network [Appl. Opt. 33, 7558 (1994); J. Lightwave Technol. 12, 704 (1994)] architecture that combines the positive features of the hypercube (small diameter, connectivity, symmetry, simple routing, and fault tolerance) and the mesh (constant node degree and size scaleability). The optical implementation method is divided into two levels: high-density local connections for the hypercube modules, and high-bit-rate, low-density, long connections for the mesh links connecting the hypercube modules. Free-space imaging systems utilizing vertical-cavity surface-emitting laser (VCSEL) arrays, lenslet arrays, space-invariant holographic techniques, and photodiode arrays are demonstrated for the local connections. Optobus fiber interconnects from Motorola are used for the long-distance connections. The OMMH was optimized to operate at the data rate of Motorola's Optobus (10-bit-wide, VCSEL-based bidirectional data interconnects at 150 Mbits/s). Difficulties encountered included the varying fan-out efficiencies of the different orders of the hologram, misalignment sensitivity of the free-space links, low power (1 mW) of the individual VCSEL's, and noise.

A low-noise low-power EEG acquisition node for scalable brain-machine interfaces

NASA Astrophysics Data System (ADS)

Sullivan, Thomas J.; Deiss, Stephen R.; Cauwenberghs, Gert; Jung, Tzyy-Ping

2007-05-01

Electroencephalograph (EEG) recording systems offer a versatile, noninvasive window on the brain's spatio-temporal activity for many neuroscience and clinical applications. Our research aims at improving the spatial resolution and mobility of EEG recording by reducing the form factor, power drain and signal fanout of the EEG acquisition node in a scalable sensor array architecture. We present such a node integrated onto a dimesized circuit board that contains a sensor's complete signal processing front-end, including amplifier, filters, and analog-to-digital conversion. A daisy-chain configuration between boards with bit-serial output reduces the wiring needed. The circuit's low power consumption of 423 μW supports EEG systems with hundreds of electrodes to operate from small batteries for many hours. Coupling between the bit-serial output and the highly sensitive analog input due to dense integration of analog and digital functions on the circuit board results in a deterministic noise component in the output, larger than the intrinsic sensor and circuit noise. With software correction of this noise contribution, the system achieves an input-referred noise of 0.277 μVrms in the signal band of 1 to 100 Hz, comparable to the best medical-grade systems in use. A chain of seven nodes using EEG dry electrodes created in micro-electrical-mechanical system (MEMS) technology is demonstrated in a real-world setting.

Extension of analog network coding in wireless information exchange

NASA Astrophysics Data System (ADS)

Chen, Cheng; Huang, Jiaqing

2012-01-01

Ever since the concept of analog network coding(ANC) was put forward by S.Katti, much attention has been focused on how to utilize analog network coding to take advantage of wireless interference, which used to be considered generally harmful, to improve throughput performance. Previously, only the case of two nodes that need to exchange information has been fully discussed while the issue of extending analog network coding to more than three nodes remains undeveloped. In this paper, we propose a practical transmission scheme to extend analog network coding to more than two nodes that need to exchange information among themselves. We start with the case of three nodes that need to exchange information and demonstrate that through utilizing our algorithm, the throughput can achieve 33% and 20% increase compared with that of traditional transmission scheduling and digital network coding, respectively. Then, we generalize the algorithm so that it can fit for occasions with any number of nodes. We also discuss some technical issues and throughput analysis as well as the bit error rate.

Quantization noise in digital speech. M.S. Thesis- Houston Univ.

NASA Technical Reports Server (NTRS)

Schmidt, O. L.

1972-01-01

The amount of quantization noise generated in a digital-to-analog converter is dependent on the number of bits or quantization levels used to digitize the analog signal in the analog-to-digital converter. The minimum number of quantization levels and the minimum sample rate were derived for a digital voice channel. A sample rate of 6000 samples per second and lowpass filters with a 3 db cutoff of 2400 Hz are required for 100 percent sentence intelligibility. Consonant sounds are the first speech components to be degraded by quantization noise. A compression amplifier can be used to increase the weighting of the consonant sound amplitudes in the analog-to-digital converter. An expansion network must be installed at the output of the digital-to-analog converter to restore the original weighting of the consonant sounds. This technique results in 100 percent sentence intelligibility for a sample rate of 5000 samples per second, eight quantization levels, and lowpass filters with a 3 db cutoff of 2000 Hz.

Micromechanical torsional digital-to-analog converter for open-loop angular positioning applications

NASA Astrophysics Data System (ADS)

Zhou, Guangya; Tay, Francis E. H.; Chau, Fook Siong; Zhao, Yi; Logeeswaran, VJ

2004-05-01

This paper reports a novel micromechanical torsional digital-to-analog converter (MTDAC), operated in open-loop with digitally controlled precise multi-level tilt angles. The MTDAC mechanism presented is analogous to that of an electrical binary-weighted-input digital-to-analog converter (DAC). It consists of a rigid tunable platform, an array of torsional microactuators, each operating in a two-state (on/off) mode, and a set of connection beams with binary-weighted torsional stiffnesses that connect the actuators to the platform. The feasibility of the proposed MTDAC mechanism was verified numerically by finite element simulations and experimentally with a commercial optical phase-shifting interferometric system. A prototype 2-bit MTDAC was implemented using the poly-MUMPS process achieving a full-scale output tilt angle of 1.92° with a rotation step of 0.64°. This mechanism can be configured for many promising applications, particularly in beam steering-based OXC switches.

Processing and Prolonged 500 C Testing of 4H-SiC JFET Integrated Circuits with Two Levels of Metal Interconnect

NASA Technical Reports Server (NTRS)

Spry, David J.; Neudeck, Philip G.; Chen, Liangyu; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.; Krasowski, Michael J.; Prokop, Norman F.

2015-01-01

Complex integrated circuit (IC) chips rely on more than one level of interconnect metallization for routing of electrical power and signals. This work reports the processing and testing of 4H-SiC junction field effect transistor (JFET) prototype ICs with two levels of metal interconnect capable of prolonged operation at 500 C. Packaged functional circuits including 3-and 11-stage ring oscillators, a 4-bit digital to analog converter, and a 4-bit address decoder and random access memory cell have been demonstrated at 500 C. A 3-stage oscillator functioned for over 3000 hours at 500 C in air ambient.

Reversion of the P-glycoprotein-mediated multidrug resistance of cancer cells by FK-506 derivatives.

PubMed

Jachez, B; Boesch, D; Grassberger, M A; Loor, F

1993-04-01

FK-506 is a resistance-modulating agent (RMA) for tumor cells whose multidrug resistance (MDR) involves a P-glycoprotein (Pgp)-mediated anti-cancer drug efflux. The family of FK-506 relatives and derivatives includes analogs which display a whole range of chemosensitizing strengths, from no detectable RMA activity to a complete reversion of the MDR phenotype. Similarly, FK-506 analogs display a whole range of immunosuppressive activities, including inactive ones. FK-506 was compared for RMA activity with 11 FK-506 analogs which were at least 20-fold less active than FK-506 for the inhibition of the bi-directional mixed lymphocyte reaction displayed the whole range of RMA activity. One such strong RMA derivative of FK-506 (SDZ 280-629) was further shown able to restore completely daunomycin retention by highly resistant MDR P388 tumor cells.

Enhancing Observability of Signal Composition and Error Signatures During Dynamic SEE Analog to Digital Device Testing

NASA Technical Reports Server (NTRS)

Berg, M.; Buchner, S.; Kim, H.; Friendlich, M.; Perez, C.; Phan, A.; Seidleck, C.; LaBel, K.; Kruckmeyer, K.

2010-01-01

A novel approach to dynamic SEE ADC testing is presented. The benefits of this test scheme versus prior implemented techniques include the ability to observe ADC SEE errors that are in the form of phase shifts, single bit upsets, bursts of disrupted signal composition, and device clock loss.

A Low Power Digital Accumulation Technique for Digital-Domain CMOS TDI Image Sensor.

PubMed

Yu, Changwei; Nie, Kaiming; Xu, Jiangtao; Gao, Jing

2016-09-23

In this paper, an accumulation technique suitable for digital domain CMOS time delay integration (TDI) image sensors is proposed to reduce power consumption without degrading the rate of imaging. In terms of the slight variations of quantization codes among different pixel exposures towards the same object, the pixel array is divided into two groups: one is for coarse quantization of high bits only, and the other one is for fine quantization of low bits. Then, the complete quantization codes are composed of both results from the coarse-and-fine quantization. The equivalent operation comparably reduces the total required bit numbers of the quantization. In the 0.18 µm CMOS process, two versions of 16-stage digital domain CMOS TDI image sensor chains based on a 10-bit successive approximate register (SAR) analog-to-digital converter (ADC), with and without the proposed technique, are designed. The simulation results show that the average power consumption of slices of the two versions are 6 . 47 × 10 - 8 J/line and 7 . 4 × 10 - 8 J/line, respectively. Meanwhile, the linearity of the two versions are 99.74% and 99.99%, respectively.

45 Gb/s low complexity optical front-end for soft-decision LDPC decoders.

PubMed

Sakib, Meer Nazmus; Moayedi, Monireh; Gross, Warren J; Liboiron-Ladouceur, Odile

2012-07-30

In this paper a low complexity and energy efficient 45 Gb/s soft-decision optical front-end to be used with soft-decision low-density parity-check (LDPC) decoders is demonstrated. The results show that the optical front-end exhibits a net coding gain of 7.06 and 9.62 dB for post forward error correction bit error rate of 10(-7) and 10(-12) for long block length LDPC(32768,26803) code. The performance over a hard decision front-end is 1.9 dB for this code. It is shown that the soft-decision circuit can also be used as a 2-bit flash type analog-to-digital converter (ADC), in conjunction with equalization schemes. At bit rate of 15 Gb/s using RS(255,239), LDPC(672,336), (672, 504), (672, 588), and (1440, 1344) used with a 6-tap finite impulse response (FIR) equalizer will result in optical power savings of 3, 5, 7, 9.5 and 10.5 dB, respectively. The 2-bit flash ADC consumes only 2.71 W at 32 GSamples/s. At 45 GSamples/s the power consumption is estimated to be 4.95 W.

A bunch to bucket phase detector for the RHIC LLRF upgrade platform

DOE Office of Scientific and Technical Information (OSTI.GOV)

Smith, K.S.; Harvey, M.; Hayes, T.

2011-03-28

As part of the overall development effort for the RHIC LLRF Upgrade Platform [1,2,3], a generic four channel 16 bit Analog-to-Digital Converter (ADC) daughter module was developed to provide high speed, wide dynamic range digitizing and processing of signals from DC to several hundred megahertz. The first operational use of this card was to implement the bunch to bucket phase detector for the RHIC LLRF beam control feedback loops. This paper will describe the design and performance features of this daughter module as a bunch to bucket phase detector, and also provide an overview of its place within the overallmore » LLRF platform architecture as a high performance digitizer and signal processing module suitable to a variety of applications. In modern digital control and signal processing systems, ADCs provide the interface between the analog and digital signal domains. Once digitized, signals are then typically processed using algorithms implemented in field programmable gate array (FPGA) logic, general purpose processors (GPPs), digital signal processors (DSPs) or a combination of these. For the recently developed and commissioned RHIC LLRF Upgrade Platform, we've developed a four channel ADC daughter module based on the Linear Technology LTC2209 16 bit, 160 MSPS ADC and the Xilinx V5FX70T FPGA. The module is designed to be relatively generic in application, and with minimal analog filtering on board, is capable of processing signals from DC to 500 MHz or more. The module's first application was to implement the bunch to bucket phase detector (BTB-PD) for the RHIC LLRF system. The same module also provides DC digitizing of analog processed BPM signals used by the LLRF system for radial feedback.« less

High density, multi-range analog output Versa Module Europa board for control system applications

DOE Office of Scientific and Technical Information (OSTI.GOV)

Singh, Kundan, E-mail: kundan@iuac.res.in; Das, Ajit Lal

2014-01-15

A new VMEDAC64, 12-bit 64 channel digital-to-analog converter, a Versa Module Europa (VME) module, features 64 analog voltage outputs with user selectable multiple ranges, has been developed for control system applications at Inter University Accelerator Centre. The FPGA (Field Programmable Gate Array) is the module's core, i.e., it implements the DAC control logic and complexity of VMEbus slave interface logic. The VMEbus slave interface and DAC control logic are completely designed and implemented on a single FPGA chip to achieve high density of 64 channels in a single width VME module and will reduce the module count in the controlmore » system applications, and hence will reduce the power consumption and cost of overall system. One of our early design goals was to develop the VME interface such that it can be easily integrated with the peripheral devices and satisfy the timing specifications of VME standard. The modular design of this module reduces the amount of time required to develop other custom modules for control system. The VME slave interface is written as a single component inside FPGA which will be used as a basic building block for any VMEbus interface project. The module offers multiple output voltage ranges depending upon the requirement. The output voltage range can be reduced or expanded by writing range selection bits in the control register. The module has programmable refresh rate and by default hold capacitors in the sample and hold circuit for each channel are charged periodically every 7.040 ms (i.e., update frequency 284 Hz). Each channel has software controlled output switch which disconnects analog output from the field. The modularity in the firmware design on FPGA makes the debugging very easy. On-board DC/DC converters are incorporated for isolated power supply for the analog section of the board.« less

Stereoselective virtual screening of the ZINC database using atom pair 3D-fingerprints.

PubMed

Awale, Mahendra; Jin, Xian; Reymond, Jean-Louis

2015-01-01

Tools to explore large compound databases in search for analogs of query molecules provide a strategically important support in drug discovery to help identify available analogs of any given reference or hit compound by ligand based virtual screening (LBVS). We recently showed that large databases can be formatted for very fast searching with various 2D-fingerprints using the city-block distance as similarity measure, in particular a 2D-atom pair fingerprint (APfp) and the related category extended atom pair fingerprint (Xfp) which efficiently encode molecular shape and pharmacophores, but do not perceive stereochemistry. Here we investigated related 3D-atom pair fingerprints to enable rapid stereoselective searches in the ZINC database (23.2 million 3D structures). Molecular fingerprints counting atom pairs at increasing through-space distance intervals were designed using either all atoms (16-bit 3DAPfp) or different atom categories (80-bit 3DXfp). These 3D-fingerprints retrieved molecular shape and pharmacophore analogs (defined by OpenEye ROCS scoring functions) of 110,000 compounds from the Cambridge Structural Database with equal or better accuracy than the 2D-fingerprints APfp and Xfp, and showed comparable performance in recovering actives from decoys in the DUD database. LBVS by 3DXfp or 3DAPfp similarity was stereoselective and gave very different analogs when starting from different diastereomers of the same chiral drug. Results were also different from LBVS with the parent 2D-fingerprints Xfp or APfp. 3D- and 2D-fingerprints also gave very different results in LBVS of folded molecules where through-space distances between atom pairs are much shorter than topological distances. 3DAPfp and 3DXfp are suitable for stereoselective searches for shape and pharmacophore analogs of query molecules in large databases. Web-browsers for searching ZINC by 3DAPfp and 3DXfp similarity are accessible at www.gdb.unibe.ch and should provide useful assistance to drug discovery projects. Graphical abstractAtom pair fingerprints based on through-space distances (3DAPfp) provide better shape encoding than atom pair fingerprints based on topological distances (APfp) as measured by the recovery of ROCS shape analogs by fp similarity.

Fast Low-Cost Multiple Sensor Readout System

DOEpatents

Carter-Lewis, David; Krennich, Frank; Le Bohec, Stephane; Petry, Dirk; Sleege, Gary

2004-04-06

A low resolution data acquisition system is presented. The data acquisition system has a plurality of readout modules serially connected to a controller. Each readout module has a FPGA in communication with analog to digital (A/D) converters, which are connected to sensors. The A/D converter has eight bit or lower resolution. The FPGA detects when a command is addressed to it and commands the A/D converters to convert analog sensor data into digital data. The digital data is sent on a high speed serial communication bus to the controller. A graphical display is used in one embodiment to indicate if a sensor reading is outside of a predetermined range.

Hardware/Software Issues for Video Guidance Systems: The Coreco Frame Grabber

NASA Technical Reports Server (NTRS)

Bales, John W.

1996-01-01

The F64 frame grabber is a high performance video image acquisition and processing board utilizing the TMS320C40 and TMS34020 processors. The hardware is designed for the ISA 16 bit bus and supports multiple digital or analog cameras. It has an acquisition rate of 40 million pixels per second, with a variable sampling frequency of 510 kHz to MO MHz. The board has a 4MB frame buffer memory expandable to 32 MB, and has a simultaneous acquisition and processing capability. It supports both VGA and RGB displays, and accepts all analog and digital video input standards.

Biwavelength transceiver module for parallel simultaneous bidirectional optical interconnections

NASA Astrophysics Data System (ADS)

Nguyen, Nga T. H.; Ukaegbu, Ikechi A.; Sangirov, Jamshid; Cho, Mu-Hee; Lee, Tae-Woo; Park, Hyo-Hoon

2013-12-01

The design of a biwavelength transceiver (TRx) module for parallel simultaneous bidirectional optical interconnects is described. The TRx module has been implemented using two different wavelengths, 850 and 1060 nm, to send and receive signals simultaneously through a common optical interface while optimizing cost and performance. Filtering mirrors are formed in the optical fibers which are embedded on a V-grooved silicon substrate for reflecting and filtering optical signals from/to vertical-cavity surface-emitting laser (VCSEL)/photodiode (PD). The VCSEL and PD are flip-chip bonded on individual silicon optical benches, which are attached on the silicon substrate for optical signal coupling from the VCSEL to fiber and from fiber to the PD. A high-speed and low-loss ceramic printed circuit board, which has a compact size of 0.033 cc, has been designed to carry transmitter and receiver chips for easy packaging of the TRx module. Applied for quad small form-factor pluggable applications at 40-Gbps operation, the four-channel biwavelength TRx module showed clear eye diagrams with a bit error rate (BER) of 10-12 at input powers of -5 and -5.8 dBm for 1060 and 850 nm operation modes, respectively.

4 channel × 10 Gb/s bidirectional optical subassembly using silicon optical bench with precise passive optical alignment.

PubMed

Kang, Eun Kyu; Lee, Yong Woo; Ravindran, Sooraj; Lee, Jun Ki; Choi, Hee Ju; Ju, Gun Wu; Min, Jung Wook; Song, Young Min; Sohn, Ik-Bu; Lee, Yong Tak

2016-05-16

We demonstrate an advanced structure for optical interconnect consisting of 4 channel × 10 Gb/s bidirectional optical subassembly (BOSA) formed using silicon optical bench (SiOB) with tapered fiber guiding holes (TFGHs) for precise and passive optical alignment of vertical-cavity surface-emitting laser (VCSEL)-to-multi mode fiber (MMF) and MMF-to-photodiode (PD). The co-planar waveguide (CPW) transmission line (Tline) was formed on the backside of silicon substrate to reduce the insertion loss of electrical data signal. The 4 channel VCSEL and PD array are attached at the end of CPW Tline using a flip-chip bonder and solder pad. The 12-channel ribbon fiber is simply inserted into the TFGHs of SiOB and is passively aligned to the VCSEL and PD in which no additional coupling optics are required. The fabricated BOSA shows high coupling efficiency and good performance with the clearly open eye patterns and a very low bit error rate of less than 10^-12 order at a data rate of 10 Gb/s with a PRBS pattern of 2³¹-1.

Method and apparatus for spur-reduced digital sinusoid synthesis

NASA Technical Reports Server (NTRS)

Zimmerman, George A. (Inventor); Flanagan, Michael J. (Inventor)

1995-01-01

A technique for reducing the spurious signal content in digital sinusoid synthesis is presented. Spur reduction is accomplished through dithering both amplitude and phase values prior to word-length reduction. The analytical approach developed for analog quantization is used to produce new bounds on spur performance in these dithered systems. Amplitude dithering allows output word-length reduction without introducing additional spurs. Effects of periodic dither similar to that produced by a pseudo-noise (PN) generator are analyzed. This phase dithering method provides a spur reduction of 6(M + 1) dB per phase bit when the dither consists of M uniform variates. While the spur reduction is at the expense of an increase in system noise, the noise power can be made white, making the power spectral density small. This technique permits the use of a smaller number of phase bits addressing sinusoid look-up tables, resulting in an exponential decrease in system complexity. Amplitude dithering allows the use of less complicated multipliers and narrower data paths in purely digital applications, as well as the use of coarse-resolution, highly-linear digital-to-analog converters (DAC's) to obtain spur performance limited by the DAC linearity rather than its resolution.

A fast combination calibration of foreground and background for pipelined ADCs

NASA Astrophysics Data System (ADS)

Kexu, Sun; Lenian, He

2012-06-01

This paper describes a fast digital calibration scheme for pipelined analog-to-digital converters (ADCs). The proposed method corrects the nonlinearity caused by finite opamp gain and capacitor mismatch in multiplying digital-to-analog converters (MDACs). The considered calibration technique takes the advantages of both foreground and background calibration schemes. In this combination calibration algorithm, a novel parallel background calibration with signal-shifted correlation is proposed, and its calibration cycle is very short. The details of this technique are described in the example of a 14-bit 100 Msample/s pipelined ADC. The high convergence speed of this background calibration is achieved by three means. First, a modified 1.5-bit stage is proposed in order to allow the injection of a large pseudo-random dithering without missing code. Second, before correlating the signal, it is shifted according to the input signal so that the correlation error converges quickly. Finally, the front pipeline stages are calibrated simultaneously rather than stage by stage to reduce the calibration tracking constants. Simulation results confirm that the combination calibration has a fast startup process and a short background calibration cycle of 2 × 221 conversions.

An ultra low-power front-end IC for wearable health monitoring system.

PubMed

Yu-Pin Hsu; Zemin Liu; Hella, Mona M

2016-08-01

This paper presents a low-power front-end IC for wearable health monitoring systems. The IC, designed in a standard 0.13μm CMOS technology, fully integrates a low-noise analog front-end (AFE) to process the weak bio-signals, followed by an analog-to-digital converter (ADC) to digitize the extracted signals. An AC-coupled driving buffer, that interfaces between the AFE and the ADC is introduced to scale down the power supply of the ADC. The power consumption decreases by 50% compared to the case without power supply scaling. The AFE passes signals from 0.5Hz to 280Hz and from 0.7Hz to 160Hz with a simulated input referred noise of 1.6μVrms and achieves a maximum gain of 35dB/41dB respectively, with a noise-efficiency factor (NEF) of the AFE is 1. The 8-bit ADC achieves a simulated 7.96-bit resolution at 10KS/s sampling rate under 0.5V supply voltage. The overall system consumes only 0.86μW at dual supply voltages of 1V (AFE) and 0.5 V (ADC).

Design of a universal two-layered neural network derived from the PLI theory

NASA Astrophysics Data System (ADS)

Hu, Chia-Lun J.

2004-05-01

The if-and-only-if (IFF) condition that a set of M analog-to-digital vector-mapping relations can be learned by a one-layered-feed-forward neural network (OLNN) is that all the input analog vectors dichotomized by the i-th output bit must be positively, linearly independent, or PLI. If they are not PLI, then the OLNN just cannot learn no matter what learning rules is employed because the solution of the connection matrix does not exist mathematically. However, in this case, one can still design a parallel-cascaded, two-layered, perceptron (PCTLP) to acheive this general mapping goal. The design principle of this "universal" neural network is derived from the major mathematical properties of the PLI theory - changing the output bits of the dependent relations existing among the dichotomized input vectors to make the PLD relations PLI. Then with a vector concatenation technique, the required mapping can still be learned by this PCTLP system with very high efficiency. This paper will report in detail the mathematical derivation of the general design principle and the design procedures of the PCTLP neural network system. It then will be verified in general by a practical numerical example.

Processing and Prolonged 500 C Testing of 4H-SiC JFET Integrated Circuits with Two Levels of Metal Interconnect

NASA Technical Reports Server (NTRS)

Spry, David J.; Neudeck, Philip G.; Chen, Liangyu; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.; Krasowski, Michael J.; Prokop, Norman F.

2015-01-01

Complex integrated circuit (IC) chips rely on more than one level of interconnect metallization for routing of electrical power and signals. This work reports the processing and testing of 4H-SiC junction field effect transistor (JFET) prototype IC's with two levels of metal interconnect capable of prolonged operation at 500 C. Packaged functional circuits including 3- and 11-stage ring oscillators, a 4-bit digital to analog converter, and a 4-bit address decoder and random access memory cell have been demonstrated at 500 C. A 3-stage oscillator functioned for over 3000 hours at 500 C in air ambient. Improved reproducibility remains to be accomplished.

Adaptive 84.44-190 Mbit/s phosphor-LED wireless communication utilizing no blue filter at practical transmission distance.

PubMed

Yeh, C H; Chow, C W; Chen, H Y; Chen, J; Liu, Y L

2014-04-21

We propose and experimentally demonstrate a white-light phosphor-LED visible light communication (VLC) system with an adaptive 84.44 to 190 Mbit/s 16 quadrature-amplitude-modulation (QAM) orthogonal-frequency-division-multiplexing (OFDM) signal utilizing bit-loading method. Here, the optimal analogy pre-equalization design is performed at LED transmitter (Tx) side and no blue filter is used at the Rx side. Hence, the ~1 MHz modulation bandwidth of phosphor-LED could be extended to 30 MHz. In addition, the measured bit error rates (BERs) of < 3.8 × 10(-3) [forward error correction (FEC) threshold] at different measured data rates can be achieved at practical transmission distances of 0.75 to 2 m.

Design and implementation of a wireless (Bluetooth) four channel bio-instrumentation amplifier and digital data acquisition device with user-selectable gain, frequency, and driven reference.

PubMed

Cosmanescu, Alin; Miller, Benjamin; Magno, Terence; Ahmed, Assad; Kremenic, Ian

2006-01-01

A portable, multi-purpose Bio-instrumentation Amplifier and Data AcQuisition device (BADAQ) capable of measuring and transmitting EMG and EKG signals wirelessly via Bluetooth is designed and implemented. Common topologies for instrumentation amplifiers and filters are used and realized with commercially available, low-voltage, high precision operational amplifiers. An 8-bit PIC microcontroller performs 10-bit analog-to-digital conversion of the amplified and filtered signals and controls a Bluetooth transceiver capable of wirelessly transmitting the data to any Bluetooth enabled device. Electrical isolation between patient/subject, circuitry, and ancillary equipment is achieved by optocoupling components. The design focuses on simplicity, portability, and affordability.

Bidirectional reflectance distribution function effects in ladar-based reflection tomography.

PubMed

Jin, Xuemin; Levine, Robert Y

2009-07-20

Light reflection from a surface is described by the bidirectional reflectance distribution function (BRDF). In this paper, BRDF effects in reflection tomography are studied using modeled range-resolved reflection from well-characterized geometrical surfaces. It is demonstrated that BRDF effects can cause a darkening at the interior boundary of the reconstructed surface analogous to the well-known beam hardening artifact in x-ray transmission computed tomography (CT). This artifact arises from reduced reflection at glancing incidence angles to the surface. It is shown that a purely Lambertian surface without shadowed components is perfectly reconstructed from range-resolved measurements. This result is relevant to newly fabricated carbon nanotube materials. Shadowing is shown to cause crossed streak artifacts similar to limited-angle effects in CT reconstruction. In tomographic reconstruction, these effects can overwhelm highly diffuse components in proximity to specularly reflecting elements. Diffuse components can be recovered by specialized processing, such as reducing glints via thresholded measurements.

A low-power bidirectional telemetry device with a near-field charging feature for a cardiac microstimulator.

PubMed

Shuenn-Yuh Lee; Chih-Jen Cheng; Ming-Chun Liang

2011-08-01

In this paper, wireless telemetry using the near-field coupling technique with round-wire coils for an implanted cardiac microstimulator is presented. The proposed system possesses an external powering amplifier and an internal bidirectional microstimulator. The energy of the microstimulator is provided by a rectifier that can efficiently charge a rechargeable device. A fully integrated regulator and a charge pump circuit are included to generate a stable, low-voltage, and high-potential supply voltage, respectively. A miniature digital processor includes a phase-shift-keying (PSK) demodulator to decode the transmission data and a self-protective system controller to operate the entire system. To acquire the cardiac signal, a low-voltage and low-power monitoring analog front end (MAFE) performs immediate threshold detection and data conversion. In addition, the pacing circuit, which consists of a pulse generator (PG) and its digital-to-analog (D/A) controller, is responsible for stimulating heart tissue. The chip was fabricated by Taiwan Semiconductor Manufacturing Company (TSMC) with 0.35-μm complementary metal-oxide semiconductor technology to perform the monitoring and pacing functions with inductively powered communication. Using a model with lead and heart tissue on measurement, a -5-V pulse at a stimulating frequency of 60 beats per minute (bpm) is delivered while only consuming 31.5 μW of power.

Critical issues regarding SEU in avionics

DOE Office of Scientific and Technical Information (OSTI.GOV)

Normand, E.; McNulty, P.J.

1993-01-01

The energetic neutrons in the atmosphere cause microelectronics in avionic system to malfunction through a mechanism called single-event upsets (SEUs), and single-event latchup is a potential threat. Data from military and experimental flights as well as laboratory testing indicate that typical non-radiation-hardened 64K and 256K static random access memories (SRAMs) can experience a significant SEU rate at aircraft altitudes. Microelectronics in avionics systems have been demonstrated to be susceptible to SEU. Of all device types, RAMs are the most sensitive because they have the largest number of bits on a chip (e.g., an SRAM may have from 64K to 1Mmore » bits, a microprocessor 3K to 10K bits, and a logic device like an analog-to-digital converter, 12 bits). Avionics designers will need to take this susceptibility into account in current and future designs. A number of techniques are available for dealing with SEU: EDAC, redundancy, use of SEU-hard parts, reset and/or watchdog timer capability, etc. Specifications should be developed to guide avionics vendors in the analysis, prevention, and verification of neutron-induced SEU. Areas for additional research include better definition of the atmospheric neutrons and protons, development of better calculational models (e.g., those used for protons[sup 11]), and better characterization of neutron-induced latchup.« less

"MEJ" Covers from the First 100 Years: Designing to Unite a Profession

ERIC Educational Resources Information Center

Freer, Patrick K.

2014-01-01

Each of the covers designed for the 638 issues of "Music Educators Journal" and her predecessors conveys a bit of our history. These covers are analogous to single frames from a motion picture in that they each tell a piece of the story about how NAfME grew as an association and how we developed as a profession. But many of the…

Real-time display of flow-pressure-volume loops.

PubMed

Morozoff, P E; Evans, R W

1992-01-01

Graphic display of respiratory waveforms can be valuable for monitoring the progress of ventilated patients. A system has been developed that can display flow-pressure-volume loops as derived from a patient's respiratory circuit in real time. It can also display, store, print, and retrieve ventilatory waveforms. Five loops can be displayed at once: current, previous, reference, "ideal," and previously saved. Two components, the data-display device (DDD) and the data-collection device (DCD), comprise the system. An IBM 286/386 computer with a graphics card (VGA) and bidirectional parallel port is used for the DDD; an eight-bit microprocessor card and an A/D convertor card make up the DCD. A real-time multitasking operating system was written to control the DDD, while the DCD operates from in-line assembly code. The DCD samples the pressure and flow sensors at 100 Hz and looks for a complete flow waveform pattern based on flow slope. These waveforms are then passed to the DDD via the mutual parallel port. Within the DDD a process integrates the flow to create a volume signal and performs a multilinear regression on the pressure, flow, and volume data to calculate the elastance, resistance, pressure offset, and coefficient of determination. Elastance, resistance, and offset are used to calculate Pr and Pc where: Pr[k] = P[k]-offset-(elastance.V[k]) and Pc[k] = P[k]-offset-(resistance.F[k]). Volume vs. Pc and flow vs. Pr can be displayed in real time. Patient data from previous clinical tests were loaded into the device to verify the software calculations. An analog waveform generator was used to simulate flow and pressure waveforms that validated the system.(ABSTRACT TRUNCATED AT 250 WORDS)

Multi-GHz Synchronous Waveform Acquisition With Real-Time Pattern-Matching Trigger Generation

NASA Astrophysics Data System (ADS)

Kleinfelder, Stuart A.; Chiang, Shiuh-hua Wood; Huang, Wei

2013-10-01

A transient waveform capture and digitization circuit with continuous synchronous 2-GHz sampling capability and real-time programmable windowed trigger generation has been fabricated and tested. Designed in 0.25 μm CMOS, the digitizer contains a circular array of 128 sample and hold circuits for continuous sample acquisition, and attains 2-GHz sample speeds with over 800-MHz analog bandwidth. Sample clock generation is synchronous, combining a phase-locked loop for high-speed clock generation and a high-speed fully-differential shift register for distributing clocks to all 128 sample circuits. Using two comparators per sample, the sampled voltage levels are compared against two reference levels, a high threshold and a low threshold, that are set via per-comparator digital to analog converters (DACs). The 256 per-comparator 5-bit DACs compensate for comparator offsets and allow for fine reference level adjustment. The comparator results are matched in 8-sample-wide windows against up to 72 programmable patterns in real time using an on-chip programmable logic array. Each 8-sample trigger window is equivalent to 4 ns of acquisition, overlapped sample by sample in a circular fashion through the entire 128-sample array. The 72 pattern-matching trigger criteria can be programmed to be any combination of High-above the high threshold, Low-below the low threshold, Middle-between the two thresholds, or “Don't Care”-any state is accepted. A trigger pattern of “HLHLHLHL,” for example, watches for a waveform that is oscillating at about 1 GHz given the 2-GHz sample rate. A trigger is flagged in under 20 ns if there is a match, after which sampling is stopped, and on-chip digitization can proceed via 128 parallel 10-bit converters, or off-chip conversion can proceed via an analog readout. The chip exceeds 11 bits of dynamic range, nets over 800-MHz -3-dB bandwidth in a realistic system, and jitter in the PLL-based sampling clock has been measured to be about 1 part per million, RMS.

A Wearable Healthcare System With a 13.7 μA Noise Tolerant ECG Processor.

PubMed

Izumi, Shintaro; Yamashita, Ken; Nakano, Masanao; Kawaguchi, Hiroshi; Kimura, Hiromitsu; Marumoto, Kyoji; Fuchikami, Takaaki; Fujimori, Yoshikazu; Nakajima, Hiroshi; Shiga, Toshikazu; Yoshimoto, Masahiko

2015-10-01

To prevent lifestyle diseases, wearable bio-signal monitoring systems for daily life monitoring have attracted attention. Wearable systems have strict size and weight constraints, which impose significant limitations of the battery capacity and the signal-to-noise ratio of bio-signals. This report describes an electrocardiograph (ECG) processor for use with a wearable healthcare system. It comprises an analog front end, a 12-bit ADC, a robust Instantaneous Heart Rate (IHR) monitor, a 32-bit Cortex-M0 core, and 64 Kbyte Ferroelectric Random Access Memory (FeRAM). The IHR monitor uses a short-term autocorrelation (STAC) algorithm to improve the heart-rate detection accuracy despite its use in noisy conditions. The ECG processor chip consumes 13.7 μA for heart rate logging application.

Charge pump-based MOSFET-only 1.5-bit pipelined ADC stage in digital CMOS technology

NASA Astrophysics Data System (ADS)

Singh, Anil; Agarwal, Alpana

2016-10-01

A simple low-power and low-area metal-oxide-semiconductor field-effect transistor-only fully differential 1.5-bit pipelined analog-to-digital converter stage is proposed and designed in Taiwan Semiconductor Manufacturing Company 0.18 μm-technology using BSIM3v3 parameters with supply voltage of 1.8 V in inexpensive digital complementary metal-oxide semiconductor (CMOS) technology. It is based on charge pump technique to achieve the desired voltage gain of 2, independent of capacitor mismatch and avoiding the need of power hungry operational amplifier-based architecture to reduce the power, Si area and cost. Various capacitances are implemented by metal-oxide semiconductor capacitors, offering compatibility with cheaper digital CMOS process in order to reduce the much required manufacturing cost.

Demonstration of hybrid orbital angular momentum multiplexing and time-division multiplexing passive optical network.

PubMed

Wang, Andong; Zhu, Long; Liu, Jun; Du, Cheng; Mo, Qi; Wang, Jian

2015-11-16

Mode-division multiplexing passive optical network (MDM-PON) is a promising scheme for next-generation access networks to further increase fiber transmission capacity. In this paper, we demonstrate the proof-of-concept experiment of hybrid mode-division multiplexing (MDM) and time-division multiplexing (TDM) PON architecture by exploiting orbital angular momentum (OAM) modes. Bidirectional transmissions with 2.5-Gbaud 4-level pulse amplitude modulation (PAM-4) downstream and 2-Gbaud on-off keying (OOK) upstream are demonstrated in the experiment. The observed optical signal-to-noise ratio (OSNR) penalties for downstream and upstream transmissions at a bit-error rate (BER) of 2 × 10(-3) are less than 2.0 dB and 3.0 dB, respectively.

Secure chaotic transmission of electrocardiography signals with acousto-optic modulation under profiled beam propagation.

PubMed

Almehmadi, Fares S; Chatterjee, Monish R

2015-01-10

Electrocardiography (ECG) signals are used for both medical purposes and identifying individuals. It is often necessary to encrypt this highly sensitive information before it is transmitted over any channel. A closed-loop acousto-optic hybrid device acting as a chaotic modulator is applied to ECG signals to achieve this encryption. Recently improved modeling of this approach using profiled optical beams has shown it to be very sensitive to key parameters that characterize the encryption and decryption process, exhibiting its potential for secure transmission of analog and digital signals. Here the encryption and decryption is demonstrated for ECG signals, both analog and digital versions, illustrating strong encryption without significant distortion. Performance analysis pertinent to both analog and digital transmission of the ECG waveform is also carried out using output signal-to-noise, signal-to-distortion, and bit-error-rate measures relative to the key parameters and presence of channel noise in the system.

QPPM receiver for free-space laser communications

NASA Technical Reports Server (NTRS)

Budinger, J. M.; Mohamed, J. H.; Nagy, L. A.; Lizanich, P. J.; Mortensen, D. J.

1994-01-01

A prototype receiver developed at NASA Lewis Research Center for direct detection and demodulation of quaternary pulse position modulated (QPPM) optical carriers is described. The receiver enables dual-channel communications at 325-Megabits per second (Mbps) per channel. The optical components of the prototype receiver are briefly described. The electronic components, comprising the analog signal conditioning, slot clock recovery, matched filter and maximum likelihood data recovery circuits are described in more detail. A novel digital symbol clock recovery technique is presented as an alternative to conventional analog methods. Simulated link degradations including noise and pointing-error induced amplitude variations are applied. The bit-error-rate performance of the electronic portion of the prototype receiver under varying optical signal-to-noise power ratios is found to be within 1.5-dB of theory. Implementation of the receiver as a hybrid of analog and digital application specific integrated circuits is planned.

Generation of optical OFDM signals using 21.4 GS/s real time digital signal processing.

PubMed

Benlachtar, Yannis; Watts, Philip M; Bouziane, Rachid; Milder, Peter; Rangaraj, Deepak; Cartolano, Anthony; Koutsoyannis, Robert; Hoe, James C; Püschel, Markus; Glick, Madeleine; Killey, Robert I

2009-09-28

We demonstrate a field programmable gate array (FPGA) based optical orthogonal frequency division multiplexing (OFDM) transmitter implementing real time digital signal processing at a sample rate of 21.4 GS/s. The QPSK-OFDM signal is generated using an 8 bit, 128 point inverse fast Fourier transform (IFFT) core, performing one transform per clock cycle at a clock speed of 167.2 MHz and can be deployed with either a direct-detection or a coherent receiver. The hardware design and the main digital signal processing functions are described, and we show that the main performance limitation is due to the low (4-bit) resolution of the digital-to-analog converter (DAC) and the 8-bit resolution of the IFFT core used. We analyze the back-to-back performance of the transmitter generating an 8.36 Gb/s optical single sideband (SSB) OFDM signal using digital up-conversion, suitable for direct-detection. Additionally, we use the device to transmit 8.36 Gb/s SSB OFDM signals over 200 km of uncompensated standard single mode fiber achieving an overall BER<10(-3).

Digital phased array beamforming using single-bit delta-sigma conversion with non-uniform oversampling.

PubMed

Kozak, M; Karaman, M

2001-07-01

Digital beamforming based on oversampled delta-sigma (delta sigma) analog-to-digital (A/D) conversion can reduce the overall cost, size, and power consumption of phased array front-end processing. The signal resampling involved in dynamic delta sigma beamforming, however, disrupts synchronization between the modulators and demodulator, causing significant degradation in the signal-to-noise ratio. As a solution to this, we have explored a new digital beamforming approach based on non-uniform oversampling delta sigma A/D conversion. Using this approach, the echo signals received by the transducer array are sampled at time instants determined by the beamforming timing and then digitized by single-bit delta sigma A/D conversion prior to the coherent beam summation. The timing information involves a non-uniform sampling scheme employing different clocks at each array channel. The delta sigma coded beamsums obtained by adding the delayed 1-bit coded RF echo signals are then processed through a decimation filter to produce final beamforming outputs. The performance and validity of the proposed beamforming approach are assessed by means of emulations using experimental raw RF data.

Development of the Low-cost Analog-to-Digital Converter (for nuclear physics experiments) with PC sound card

NASA Astrophysics Data System (ADS)

Sugihara, Kenkoh

2009-10-01

A low-cost ADC (Analogue-to-Digital Converter) with shaping embedded for undergraduate physics laboratory is developed using a home made circuit and a PC sound card. Even though an ADC is needed as an essential part of an experimental set up, commercially available ones are very expensive and are scarce for undergraduate laboratory experiments. The system that is developed from the present work is designed for a gamma-ray spectroscopy laboratory with NaI(Tl) counters, but not limited. For this purpose, the system performance is set to sampling rate of 1-kHz with 10-bit resolution using a typical PC sound card with 41-kHz or higher sampling rate and 16-bit resolution ADC with an addition of a shaping circuit. Details of the system and the status of development will be presented. Ping circuit and PC soundcard as typical PC sound card has 41.1kHz or heiger sampling rate and 16bit resolution ADCs. In the conference details of the system and the status of development will be presented.

Direct-phase and amplitude digitalization based on free-space interferometry

NASA Astrophysics Data System (ADS)

Kleiner, Vladimir; Rudnitsky, Arkady; Zalevsky, Zeev

2017-12-01

A novel ADC configuration that can be characterized as a photonic-domain flash analog-to-digital convertor operating based upon free-space interferometry is proposed and analysed. The structure can be used as the front-end of a coherent receiver as well as for other applications. Two configurations are considered: the first, ‘direct free-space interference’, allows simultaneous measuring of the optical phase and amplitude; the second, ‘extraction of the ac component of interference by means of pixel-by-pixel balanced photodetection’, allows only phase digitization but with significantly higher sensitivity. For both proposed configurations, we present Monte Carlo estimations of the performance limitations, due to optical noise and photo-current noise, at sampling rates of 60 giga-samples per second. In terms of bit resolution, we simulated multiple cases with growing complexity of up to 4 bits for the amplitude and up to 6 bits for the phase. The simulations show that the digitization errors in the optical domain can be reduced to levels close to the quantization noise limits. Preliminary experimental results validate the fundamentals of the proposed idea.

Cepstral domain modification of audio signals for data embedding: preliminary results

NASA Astrophysics Data System (ADS)

Gopalan, Kaliappan

2004-06-01

A method of embedding data in an audio signal using cepstral domain modification is described. Based on successful embedding in the spectral points of perceptually masked regions in each frame of speech, first the technique was extended to embedding in the log spectral domain. This extension resulted at approximately 62 bits /s of embedding with less than 2 percent of bit error rate (BER) for a clean cover speech (from the TIMIT database), and about 2.5 percent for a noisy speech (from an air traffic controller database), when all frames - including silence and transition between voiced and unvoiced segments - were used. Bit error rate increased significantly when the log spectrum in the vicinity of a formant was modified. In the next procedure, embedding by altering the mean cepstral values of two ranges of indices was studied. Tests on both a noisy utterance and a clean utterance indicated barely noticeable perceptual change in speech quality when lower range of cepstral indices - corresponding to vocal tract region - was modified in accordance with data. With an embedding capacity of approximately 62 bits/s - using one bit per each frame regardless of frame energy or type of speech - initial results showed a BER of less than 1.5 percent for a payload capacity of 208 embedded bits using the clean cover speech. BER of less than 1.3 percent resulted for the noisy host with a capacity was 316 bits. When the cepstrum was modified in the region of excitation, BER increased to over 10 percent. With quantization causing no significant problem, the technique warrants further studies with different cepstral ranges and sizes. Pitch-synchronous cepstrum modification, for example, may be more robust to attacks. In addition, cepstrum modification in regions of speech that are perceptually masked - analogous to embedding in frequency masked regions - may yield imperceptible stego audio with low BER.

Standardization of End-to-End Performance of Digital Video Teleconferencing/Video Telephony Systems

DTIC Science & Technology

1991-12-01

SYSTEM 3-1 end-to-end video transmission system including both firmly specified and peripheral flexible functions. The format converter changes either...which manifests itself in both subjective evaluations and objective tests. The relative importance of performance parameters is likely to change with...conventional analog performance parameters to be largely independent of bit rate, and only slightly changed between different codec models. The

Data compression/error correction digital test system. Appendix 2: Theory of operation

NASA Technical Reports Server (NTRS)

1972-01-01

An overall block diagram of the DC/EC digital system test is shown. The system is divided into two major units: the transmitter and the receiver. In operation, the transmitter and receiver are connected only by a real or simulated transmission link. The system inputs consist of: (1) standard format TV video, (2) two channels of analog voice, and (3) one serial PCM bit stream.

Non-Invasive Monitoring of Intra-Abdominal Bleeding Rate Using Electrical Impedance Tomography

DTIC Science & Technology

2009-09-01

labeled ‘Measurement Index’, represents each of the 40 transimpedance measurements. The measurement index variable corresponds to the 40 measurements...system are amplified , and digitized by a 14-bit ADC (AD9240, Analog Devices). Waveforms are then sampled synchronous with the source, at 32 samples per...voltage changes (decreases in transimpedance ) during this phase were in measurements between the two outermost electrodes. We believe the apparent

Pneumatically Modulated Liquid Delivery System for Nebulizers

DTIC Science & Technology

2011-12-02

VII. Acknowledgements 18 APPENDIX A: Complete Parts List 19 APPENDIX B: Source code for the Arduino Uno microcontroller (CD) 23 1 I...implemented. The Arduino Uno is a well-established hobbyist microcontroller, focused on ease-of-use and teaching non-computer programmers about embedded...circuits. The Arduino Uno uses an Atmega328 microcontroller with thirteen digital TTL control lines, six 10-bit resolution 0-5 V analog inputs, TTL

An integrated system for multichannel neuronal recording with spike/LFP separation, integrated A/D conversion and threshold detection.

PubMed

Perelman, Yevgeny; Ginosar, Ran

2007-01-01

A mixed-signal front-end processor for multichannel neuronal recording is described. It receives 12 differential-input channels of implanted recording electrodes. A programmable cutoff High Pass Filter (HPF) blocks dc and low-frequency input drift at about 1 Hz. The signals are band-split at about 200 Hz to low-frequency Local Field Potential (LFP) and high-frequency spike data (SPK), which is band limited by a programmable-cutoff LPF, in a range of 8-13 kHz. Amplifier offsets are compensated by 5-bit calibration digital-to-analog converters (DACs). The SPK and LFP channels provide variable amplification rates of up to 5000 and 500, respectively. The analog signals are converted into 10-bit digital form, and streamed out over a serial digital bus at up to 8 Mbps. A threshold filter suppresses inactive portions of the signal and emits only spike segments of programmable length. A prototype has been fabricated on a 0.35-microm CMOS process and tested successfully, demonstrating a 3-microV noise level. Special interface system incorporating an embedded CPU core in a programmable logic device accompanied by real-time software has been developed to allow connectivity to a computer host.

Photonic ADC: overcoming the bottleneck of electronic jitter.

PubMed

Khilo, Anatol; Spector, Steven J; Grein, Matthew E; Nejadmalayeri, Amir H; Holzwarth, Charles W; Sander, Michelle Y; Dahlem, Marcus S; Peng, Michael Y; Geis, Michael W; DiLello, Nicole A; Yoon, Jung U; Motamedi, Ali; Orcutt, Jason S; Wang, Jade P; Sorace-Agaskar, Cheryl M; Popović, Miloš A; Sun, Jie; Zhou, Gui-Rong; Byun, Hyunil; Chen, Jian; Hoyt, Judy L; Smith, Henry I; Ram, Rajeev J; Perrott, Michael; Lyszczarz, Theodore M; Ippen, Erich P; Kärtner, Franz X

2012-02-13

Accurate conversion of wideband multi-GHz analog signals into the digital domain has long been a target of analog-to-digital converter (ADC) developers, driven by applications in radar systems, software radio, medical imaging, and communication systems. Aperture jitter has been a major bottleneck on the way towards higher speeds and better accuracy. Photonic ADCs, which perform sampling using ultra-stable optical pulse trains generated by mode-locked lasers, have been investigated for many years as a promising approach to overcome the jitter problem and bring ADC performance to new levels. This work demonstrates that the photonic approach can deliver on its promise by digitizing a 41 GHz signal with 7.0 effective bits using a photonic ADC built from discrete components. This accuracy corresponds to a timing jitter of 15 fs - a 4-5 times improvement over the performance of the best electronic ADCs which exist today. On the way towards an integrated photonic ADC, a silicon photonic chip with core photonic components was fabricated and used to digitize a 10 GHz signal with 3.5 effective bits. In these experiments, two wavelength channels were implemented, providing the overall sampling rate of 2.1 GSa/s. To show that photonic ADCs with larger channel counts are possible, a dual 20-channel silicon filter bank has been demonstrated.

Fully Integrated Passive UHF RFID Tag for Hash-Based Mutual Authentication Protocol.

PubMed

Mikami, Shugo; Watanabe, Dai; Li, Yang; Sakiyama, Kazuo

2015-01-01

Passive radio-frequency identification (RFID) tag has been used in many applications. While the RFID market is expected to grow, concerns about security and privacy of the RFID tag should be overcome for the future use. To overcome these issues, privacy-preserving authentication protocols based on cryptographic algorithms have been designed. However, to the best of our knowledge, evaluation of the whole tag, which includes an antenna, an analog front end, and a digital processing block, that runs authentication protocols has not been studied. In this paper, we present an implementation and evaluation of a fully integrated passive UHF RFID tag that runs a privacy-preserving mutual authentication protocol based on a hash function. We design a single chip including the analog front end and the digital processing block. We select a lightweight hash function supporting 80-bit security strength and a standard hash function supporting 128-bit security strength. We show that when the lightweight hash function is used, the tag completes the protocol with a reader-tag distance of 10 cm. Similarly, when the standard hash function is used, the tag completes the protocol with the distance of 8.5 cm. We discuss the impact of the peak power consumption of the tag on the distance of the tag due to the hash function.

Integrated High Resolution Digital Color Light Sensor in 130 nm CMOS Technology.

PubMed

Strle, Drago; Nahtigal, Uroš; Batistell, Graciele; Zhang, Vincent Chi; Ofner, Erwin; Fant, Andrea; Sturm, Johannes

2015-07-22

This article presents a color light detection system integrated in 130 nm CMOS technology. The sensors and corresponding electronics detect light in a CIE XYZ color luminosity space using on-chip integrated sensors without any additional process steps, high-resolution analog-to-digital converter, and dedicated DSP algorithm. The sensor consists of a set of laterally arranged integrated photodiodes that are partly covered by metal, where color separation between the photodiodes is achieved by lateral carrier diffusion together with wavelength-dependent absorption. A high resolution, hybrid, ∑∆ ADC converts each photo diode's current into a 22-bit digital result, canceling the dark current of the photo diodes. The digital results are further processed by the DSP, which calculates normalized XYZ or RGB color and intensity parameters using linear transformations of the three photo diode responses by multiplication of the data with a transformation matrix, where the coefficients are extracted by training in combination with a pseudo-inverse operation and the least-mean square approximation. The sensor system detects the color light parameters with 22-bit accuracy, consumes less than 60 μA on average at 10 readings per second, and occupies approx. 0.8 mm(2) of silicon area (including three photodiodes and the analog part of the ADC). The DSP is currently implemented on FPGA.

A 30 Gb/s full-duplex bi-directional transmission optical wireless-over fiber integration system at W-band.

PubMed

Tang, Chanjuan; Yu, Jianjun; Li, Xinying; Chi, Nan; Xiao, Jiangnan; Tian, Yumin; Zhang, Junwen

2014-01-13

We propose and experimentally demonstrate a full-duplex bi-directional transmission optical wireless-over fiber integration system at W-band (75-100 GHz) with the speed up to 15 Gb/s for both 95.4 GHz link and 88.6 GHz link for the first time. The generation of millimeter-wave (mm-wave) wireless signal is based on the photonic technique by heterodyne mixing of an optical quadrature-phase-shift-keying (QPSK) signal with a free-running light at different wavelength. After 20 km fiber transmission, up to 30 Gb/s mm-wave signal is delivered over 2 m wireless link, and then converted to the optical signal for another 20 km fiber transmission. At the wireless receiver, coherent detection and advanced digital signal processing (DSP) are introduced to improve receiver sensitivity and system performance. With the OSNR of 15 dB, the bit error ratios (BERs) for 10 Gb/s signal transmission at 95.4 GHz and 88.6 GHz are below the forward-error-correction (FEC) threshold of 3.8 × 10(-3) whether post filter is used or not, while the BER for 15 Gb/s QPSK signal employing post filter in the link of 95.4 GHz is 2.9 × 10(-3).

Design of a network for concurrent message passing systems

NASA Astrophysics Data System (ADS)

Song, Paul Y.

1988-08-01

We describe the design of the network design frame (NDF), a self-timed routing chip for a message-passing concurrent computer. The NDF uses a partitioned data path, low-voltage output drivers, and a distributed token-passing arbiter to provide a bandwidth of 450 Mbits/sec into the network. Wormhole routing and bidirectional virtual channels are used to provide low latency communications, less than 2us latency to deliver a 216 bit message across the diameter of a 1K node mess-connected machine. To support concurrent software systems, the NDF provides two logical networks, one for user messages and one for system messages. The two networks share the same set of physical wires. To facilitate the development of network nodes, the NDF is a design frame. The NDF circuitry is integrated into the pad frame of a chip leaving the center of the chip uncommitted. We define an analytic framework in which to study the effects of network size, network buffering capacity, bidirectional channels, and traffic on this class of networks. The response of the network to various combinations of these parameters are obtained through extensive simulation of the network model. Through simulation, we are able to observe the macro behavior of the network as opposed to the micro behavior of the NDF routing controller.

Robustness of spiking Deep Belief Networks to noise and reduced bit precision of neuro-inspired hardware platforms.

PubMed

Stromatias, Evangelos; Neil, Daniel; Pfeiffer, Michael; Galluppi, Francesco; Furber, Steve B; Liu, Shih-Chii

2015-01-01

Increasingly large deep learning architectures, such as Deep Belief Networks (DBNs) are the focus of current machine learning research and achieve state-of-the-art results in different domains. However, both training and execution of large-scale Deep Networks require vast computing resources, leading to high power requirements and communication overheads. The on-going work on design and construction of spike-based hardware platforms offers an alternative for running deep neural networks with significantly lower power consumption, but has to overcome hardware limitations in terms of noise and limited weight precision, as well as noise inherent in the sensor signal. This article investigates how such hardware constraints impact the performance of spiking neural network implementations of DBNs. In particular, the influence of limited bit precision during execution and training, and the impact of silicon mismatch in the synaptic weight parameters of custom hybrid VLSI implementations is studied. Furthermore, the network performance of spiking DBNs is characterized with regard to noise in the spiking input signal. Our results demonstrate that spiking DBNs can tolerate very low levels of hardware bit precision down to almost two bits, and show that their performance can be improved by at least 30% through an adapted training mechanism that takes the bit precision of the target platform into account. Spiking DBNs thus present an important use-case for large-scale hybrid analog-digital or digital neuromorphic platforms such as SpiNNaker, which can execute large but precision-constrained deep networks in real time.

Robustness of spiking Deep Belief Networks to noise and reduced bit precision of neuro-inspired hardware platforms

PubMed Central

Stromatias, Evangelos; Neil, Daniel; Pfeiffer, Michael; Galluppi, Francesco; Furber, Steve B.; Liu, Shih-Chii

2015-01-01

Increasingly large deep learning architectures, such as Deep Belief Networks (DBNs) are the focus of current machine learning research and achieve state-of-the-art results in different domains. However, both training and execution of large-scale Deep Networks require vast computing resources, leading to high power requirements and communication overheads. The on-going work on design and construction of spike-based hardware platforms offers an alternative for running deep neural networks with significantly lower power consumption, but has to overcome hardware limitations in terms of noise and limited weight precision, as well as noise inherent in the sensor signal. This article investigates how such hardware constraints impact the performance of spiking neural network implementations of DBNs. In particular, the influence of limited bit precision during execution and training, and the impact of silicon mismatch in the synaptic weight parameters of custom hybrid VLSI implementations is studied. Furthermore, the network performance of spiking DBNs is characterized with regard to noise in the spiking input signal. Our results demonstrate that spiking DBNs can tolerate very low levels of hardware bit precision down to almost two bits, and show that their performance can be improved by at least 30% through an adapted training mechanism that takes the bit precision of the target platform into account. Spiking DBNs thus present an important use-case for large-scale hybrid analog-digital or digital neuromorphic platforms such as SpiNNaker, which can execute large but precision-constrained deep networks in real time. PMID:26217169

Low-voltage analog front-end processor design for ISFET-based sensor and H+ sensing applications

NASA Astrophysics Data System (ADS)

Chung, Wen-Yaw; Yang, Chung-Huang; Peng, Kang-Chu; Yeh, M. H.

2003-04-01

This paper presents a modular-based low-voltage analog-front-end processor design in a 0.5mm double-poly double-metal CMOS technology for Ion Sensitive Field Effect Transistor (ISFET)-based sensor and H+ sensing applications. To meet the potentiometric response of the ISFET that is proportional to various H+ concentrations, the constant-voltage and constant current (CVCS) testing configuration has been used. Low-voltage design skills such as bulk-driven input pair, folded-cascode amplifier, bootstrap switch control circuits have been designed and integrated for 1.5V supply and nearly rail-to-rail analog to digital signal processing. Core modules consist of an 8-bit two-step analog-digital converter and bulk-driven pre-amplifiers have been developed in this research. The experimental results show that the proposed circuitry has an acceptable linearity to 0.1 pH-H+ sensing conversions with the buffer solution in the range of pH2 to pH12. The processor has a potential usage in battery-operated and portable healthcare devices and environmental monitoring applications.

Design and implementation of a reconfigurable mixed-signal SoC based on field programmable analog arrays

NASA Astrophysics Data System (ADS)

Liu, Lintao; Gao, Yuhan; Deng, Jun

2017-11-01

This work presents a reconfigurable mixed-signal system-on-chip (SoC), which integrates switched-capacitor-based field programmable analog arrays (FPAA), analog-to-digital converter (ADC), digital-to-analog converter, digital down converter , digital up converter, 32-bit reduced instruction-set computer central processing unit (CPU) and other digital IPs on a single chip with 0.18 μm CMOS technology. The FPAA intellectual property could be reconfigured as different function circuits, such as gain amplifier, divider, sine generator, and so on. This single-chip integrated mixed-signal system is a complete modern signal processing system, occupying a die area of 7 × 8 mm 2 and consuming 719 mW with a clock frequency of 150 MHz for CPU and 200 MHz for ADC/DAC. This SoC chip can help customers to shorten design cycles, save board area, reduce the system power consumption and depress the system integration risk, which would afford a big prospect of application for wireless communication. Project supported by the National High Technology and Development Program of China (No. 2012AA012303).

Progress In Optical Memory Technology

NASA Astrophysics Data System (ADS)

Tsunoda, Yoshito

1987-01-01

More than 20 years have passed since the concept of optical memory was first proposed in 1966. Since then considerable progress has been made in this area together with the creation of completely new markets of optical memory in consumer and computer application areas. The first generation of optical memory was mainly developed with holographic recording technology in late 1960s and early 1970s. Considerable number of developments have been done in both analog and digital memory applications. Unfortunately, these technologies did not meet a chance to be a commercial product. The second generation of optical memory started at the beginning of 1970s with bit by bit recording technology. Read-only type optical memories such as video disks and compact audio disks have extensively investigated. Since laser diodes were first applied to optical video disk read out in 1976, there have been extensive developments of laser diode pick-ups for optical disk memory systems. The third generation of optical memory started in 1978 with bit by bit read/write technology using laser diodes. Developments of recording materials including both write-once and erasable have been actively pursued at several research institutes. These technologies are mainly focused on the optical memory systems for computer application. Such practical applications of optical memory technology has resulted in the creation of such new products as compact audio disks and computer file memories.

Binary CMOS image sensor with a gate/body-tied MOSFET-type photodetector for high-speed operation

NASA Astrophysics Data System (ADS)

Choi, Byoung-Soo; Jo, Sung-Hyun; Bae, Myunghan; Kim, Sang-Hwan; Shin, Jang-Kyoo

2016-05-01

In this paper, a binary complementary metal oxide semiconductor (CMOS) image sensor with a gate/body-tied (GBT) metal oxide semiconductor field effect transistor (MOSFET)-type photodetector is presented. The sensitivity of the GBT MOSFET-type photodetector, which was fabricated using the standard CMOS 0.35-μm process, is higher than the sensitivity of the p-n junction photodiode, because the output signal of the photodetector is amplified by the MOSFET. A binary image sensor becomes more efficient when using this photodetector. Lower power consumptions and higher speeds of operation are possible, compared to the conventional image sensors using multi-bit analog to digital converters (ADCs). The frame rate of the proposed image sensor is over 2000 frames per second, which is higher than those of the conventional CMOS image sensors. The output signal of an active pixel sensor is applied to a comparator and compared with a reference level. The 1-bit output data of the binary process is determined by this level. To obtain a video signal, the 1-bit output data is stored in the memory and is read out by horizontal scanning. The proposed chip is composed of a GBT pixel array (144 × 100), binary-process circuit, vertical scanner, horizontal scanner, and readout circuit. The operation mode can be selected from between binary mode and multi-bit mode.

Second quantization in bit-string physics

NASA Technical Reports Server (NTRS)

Noyes, H. Pierre

1993-01-01

Using a new fundamental theory based on bit-strings, a finite and discrete version of the solutions of the free one particle Dirac equation as segmented trajectories with steps of length h/mc along the forward and backward light cones executed at velocity +/- c are derived. Interpreting the statistical fluctuations which cause the bends in these segmented trajectories as emission and absorption of radiation, these solutions are analogous to a fermion propagator in a second quantized theory. This allows us to interpret the mass parameter in the step length as the physical mass of the free particle. The radiation in interaction with it has the usual harmonic oscillator structure of a second quantized theory. How these free particle masses can be generated gravitationally using the combinatorial hierarchy sequence (3,10,137,2(sup 127) + 136), and some of the predictive consequences are sketched.

A reconfigurable medically cohesive biomedical front-end with ΣΔ ADC in 0.18µm CMOS.

PubMed

Jha, Pankaj; Patra, Pravanjan; Naik, Jairaj; Acharya, Amit; Rajalakshmi, P; Singh, Shiv Govind; Dutta, Ashudeb

2015-08-01

This paper presents a generic programmable analog front-end (AFE) for acquisition and digitization of various biopotential signals. This includes a lead-off detection circuit, an ultra-low current capacitively coupled signal conditioning stage with programmable gain and bandwidth, a new mixed signal automatic gain control (AGC) mechanism and a medically cohesive reconfigurable ΣΔ ADC. The full system is designed in UMC 0.18μm CMOS. The AFE achieves an overall linearity of more 10 bits with 0.47μW power consumption. The ADC provides 2(nd) order noise-shaping while using single integrator and an ENOB of ~11 bits with 5μW power consumption. The system was successfully verified for various ECG signals from PTB database. This system is intended for portable batteryless u-Healthcare devices.

Science beyond fiction. A revolution of knowledge transfer in research, education, and practice is on the horizon.

PubMed

Ammann, Alexander

2016-01-01

"Digitality" (as opposed to "digitalization"--the conversion from the analog domain to the digital domain) will open up a whole new world that does not originate from the analog world. Contemporary research in the field of neural concepts and neuromorphic computing systems will lead to convergences between the world of digitality and the world of neuronality, giving the theme "Knowledge and Culture" a new meaning. The simulation of virtual multidimensional and contextual spaces will transform the transfer of knowledge from a uni- and bidirectional process into an interactive experience. We will learn to learn in a ubiquitous computing environment and will abandon conventional curriculum organization principles. The adaptation of individualized ontologies will result in the emergence of a new world of knowledge in which knowledge evolves from a cultural heritage into a commodity.

A linearly controlled direct-current power source for high-current inductive loads in a magnetic suspension wind tunnel

NASA Technical Reports Server (NTRS)

Tripp, John S.; Daniels, Taumi S.

1990-01-01

The NASA Langley 6 inch magnetic suspension and balance system (MSBS) requires an independently controlled bidirectional DC power source for each of six positioning electromagnets. These electromagnets provide five-degree-of-freedom control over a suspended aerodynamic test model. Existing power equipment, which employs resistance coupled thyratron controlled rectifiers as well as AC to DC motor generator converters, is obsolete, inefficient, and unreliable. A replacement six phase bidirectional controlled bridge rectifier is proposed, which employs power MOSFET switches sequenced by hybrid analog/digital circuits. Full load efficiency is 80 percent compared to 25 percent for the resistance coupled thyratron system. Current feedback provides high control linearity, adjustable current limiting, and current overload protection. A quenching circuit suppresses inductive voltage impulses. It is shown that 20 kHz interference from positioning magnet power into MSBS electromagnetic model position sensors results predominantly from capacitively coupled electric fields. Hence, proper shielding and grounding techniques are necessary. Inductively coupled magnetic interference is negligible.

A solid-state controllable power supply for a magnetic suspension wind tunnel

NASA Technical Reports Server (NTRS)

Daniels, Taumi S.; Tripp, John S.

1991-01-01

The NASA Langley 6-inch Magnetic Suspension and Balance System (6-in. MSBS) requires an independently controlled bidirectional dc power source for each of six positioning electromagnets. These electromagnets provide five-degree-of-freedom control over a suspended aerodynamic test model. Existing power equipment, which employs resistance-coupled thyratron-controlled rectifiers as well as ac to dc motor-generator converters, is obsolete, inefficient, and unreliable. A replacement six-phase bidirectional controlled bridge rectifier is proposed, which employs power MOSFET switches sequenced by hybrid analog/digital circuits. Full-load efficiency is 80 percent compared with 25 percent for the resistance-coupled thyratron system. Current feedback provides high control linearity, adjustable current limiting, and current overload protection. A quenching circuit suppresses inductive voltage impulses. It is shown that 20-kHz interference from positioning magnet power into MSBS electromagnetic model position sensors results predominantly from capacitively coupled electric fields. Hence, proper shielding and grounding techniques are necessary. Inductively coupled magnetic interference is negligible.

Five Bit, Five Gigasample TED Analog-to-Digital Converter Development.

DTIC Science & Technology

1981-06-01

pliers. TRW uses two sources at present: materials grown by Horizontal I Bridgman technique from Crystal Specialties, and Czochralski from MRI. The...the circuit modelling and circuit design tasks. A number of design iterations were required to arrive at a satisfactory design. In or-der to riake...made by modeling the TELD as a voltage-controlled current generator with a built-in time delay between impressed voltage and output current. Based on

Interpretation of spectrophotometric surface properties of comet 67P/Churyumov-Gerasimenko by laboratory simulations of cometary analogs

NASA Astrophysics Data System (ADS)

Jost, Bernhard; Pommerol, Antoine; Poch, Olivier; Carrasco, Nathalie; Szopa, Cyril; Thomas, Nicolas

2015-11-01

The OSIRIS imaging system [1] onboard European Space Agency’s Rosetta mission has been orbiting the comet 67P/Churyumov-Gerasimenko (67P) since August 2014. It provides an enormous quantity of high resolution images of the nucleus in the visible spectral range. 67P revealed an unexpected diversity of complex surface structures and spectral properties have also been measured [2].To better interpret this data, a profound knowledge of laboratory analogs of cometary surfaces is essential. For this reason we have set up the LOSSy laboratory (Laboratory for Outflow Studies of Sublimating Materials) to study the spectrophotometric properties of ice-bearing cometary nucleus analogs. The main focus lies on the characterization of the surface evolution under simulated space conditions. The laboratory is equipped with two facilities: the PHIRE-2 radio-goniometer [3], designed to measure the bidirectional visible reflectance of samples under a wide range of geometries and the SCITEAS simulation chamber [4], designed to study the evolution of icy samples subliming under low pressure/temperature conditions by hyperspectral imaging in the VIS-NIR range. Different microscopes complement the two facilities.We present laboratory data of different types of fine grained ice particles mixed with non-volatile components (complex organic matter and minerals). As the ice sublimes, a deposition lag of non-volatile constituents is built-up on top of the ice, possibly mimic a cometary surface. The bidirectional reflectance of the samples have been characterized before and after the sublimation process.A comparison of our laboratory findings with recent OSIRIS data [5] will be presented.[1] Keller, H. U., et al., 2007, Space Sci. Rev., 128, 26[2] Thomas, N. , 2015, Science, 347, Issue 6220, aaa0440[3] Jost, B., submitted, Icarus[4] Pommerol, A., et al., 2015. Planet Space Sci 109:106-122.[5] Fornasier, S., et al., in press. Icarus, arXiv:1505.06888

A Bidirectional Brain-Machine Interface Featuring a Neuromorphic Hardware Decoder.

PubMed

Boi, Fabio; Moraitis, Timoleon; De Feo, Vito; Diotalevi, Francesco; Bartolozzi, Chiara; Indiveri, Giacomo; Vato, Alessandro

2016-01-01

Bidirectional brain-machine interfaces (BMIs) establish a two-way direct communication link between the brain and the external world. A decoder translates recorded neural activity into motor commands and an encoder delivers sensory information collected from the environment directly to the brain creating a closed-loop system. These two modules are typically integrated in bulky external devices. However, the clinical support of patients with severe motor and sensory deficits requires compact, low-power, and fully implantable systems that can decode neural signals to control external devices. As a first step toward this goal, we developed a modular bidirectional BMI setup that uses a compact neuromorphic processor as a decoder. On this chip we implemented a network of spiking neurons built using its ultra-low-power mixed-signal analog/digital circuits. On-chip on-line spike-timing-dependent plasticity synapse circuits enabled the network to learn to decode neural signals recorded from the brain into motor outputs controlling the movements of an external device. The modularity of the BMI allowed us to tune the individual components of the setup without modifying the whole system. In this paper, we present the features of this modular BMI and describe how we configured the network of spiking neuron circuits to implement the decoder and to coordinate it with the encoder in an experimental BMI paradigm that connects bidirectionally the brain of an anesthetized rat with an external object. We show that the chip learned the decoding task correctly, allowing the interfaced brain to control the object's trajectories robustly. Based on our demonstration, we propose that neuromorphic technology is mature enough for the development of BMI modules that are sufficiently low-power and compact, while being highly computationally powerful and adaptive.

A Bidirectional Brain-Machine Interface Featuring a Neuromorphic Hardware Decoder

PubMed Central

Boi, Fabio; Moraitis, Timoleon; De Feo, Vito; Diotalevi, Francesco; Bartolozzi, Chiara; Indiveri, Giacomo; Vato, Alessandro

2016-01-01

Bidirectional brain-machine interfaces (BMIs) establish a two-way direct communication link between the brain and the external world. A decoder translates recorded neural activity into motor commands and an encoder delivers sensory information collected from the environment directly to the brain creating a closed-loop system. These two modules are typically integrated in bulky external devices. However, the clinical support of patients with severe motor and sensory deficits requires compact, low-power, and fully implantable systems that can decode neural signals to control external devices. As a first step toward this goal, we developed a modular bidirectional BMI setup that uses a compact neuromorphic processor as a decoder. On this chip we implemented a network of spiking neurons built using its ultra-low-power mixed-signal analog/digital circuits. On-chip on-line spike-timing-dependent plasticity synapse circuits enabled the network to learn to decode neural signals recorded from the brain into motor outputs controlling the movements of an external device. The modularity of the BMI allowed us to tune the individual components of the setup without modifying the whole system. In this paper, we present the features of this modular BMI and describe how we configured the network of spiking neuron circuits to implement the decoder and to coordinate it with the encoder in an experimental BMI paradigm that connects bidirectionally the brain of an anesthetized rat with an external object. We show that the chip learned the decoding task correctly, allowing the interfaced brain to control the object's trajectories robustly. Based on our demonstration, we propose that neuromorphic technology is mature enough for the development of BMI modules that are sufficiently low-power and compact, while being highly computationally powerful and adaptive. PMID:28018162

Optical modulator system

NASA Technical Reports Server (NTRS)

Brand, J.

1972-01-01

The fabrication, test, and delivery of an optical modulator system which will operate with a mode-locked Nd:YAG laser indicating at either 1.06 or 0.53 micrometers is discussed. The delivered hardware operates at data rates up to 400 Mbps and includes a 0.53 micrometer electrooptic modulator, a 1.06 micrometer electrooptic modulator with power supply and signal processing electronics with power supply. The modulators contain solid state drivers which accept digital signals with MECL logic levels, temperature controllers to maintain a stable thermal environment for the modulator crystals, and automatic electronic compensation to maximize the extinction ratio. The modulators use two lithium tantalate crystals cascaded in a double pass configuration. The signal processing electronics include encoding electronics which are capable of digitizing analog signals between the limit of + or - 0.75 volts at a maximum rate of 80 megasamples per second with 5 bit resolution. The digital samples are serialized and made available as a 400 Mbps serial NRZ data source for the modulators. A pseudorandom (PN) generator is also included in the signal processing electronics. This data source generates PN sequences with lengths between 31 bits and 32,767 bits in a serial NRZ format at rates up to 400 Mbps.

A microcontroller-based telemetry system for sympathetic nerve activity and ECG measurement.

PubMed

Harada, E; Yonezawa, Y; Caldwell, W M; Hahn, A W

1999-01-01

A telemetry system employing a low power 8-bit microcontroller has been developed for chronic unanesthetized small animal studies. The two-channel system is designed for use with animals in shielded cages. Analog signals from implantable ECG and nerve electrodes are converted to an 8-bit serial digital format. This is accomplished by individual 8 bit A/D converters included in the microcontroller, which also has serial I/O port. The converted serial binary code is applied directly to an antenna wire. Therefore, the system does not need to employ a separate transmitter, such as in FM or infrared optical telemeters. The system is used in a shielded animal cage to reduce interference from external radio signals and 60 Hz power line fields. The code is received by a high input impedance amplifier in the cage and is then demodulated. The telemeter is powered by a small 3 V lithium battery, which provides 100 hours of continuous operation. The circuit is constructed on two 25 x 25 mm. printed circuit boards and encapsulated in epoxy, yielding a total volume of 6.25 cc. The weight is 15 g.

An 8-PSK TDMA uplink modulation and coding system

NASA Technical Reports Server (NTRS)

Ames, S. A.

1992-01-01

The combination of 8-phase shift keying (8PSK) modulation and greater than 2 bits/sec/Hz drove the design of the Nyquist filter to one specified to have a rolloff factor of 0.2. This filter when built and tested was found to produce too much intersymbol interference and was abandoned for a design with a rolloff factor of 0.4. The preamble is limited to 100 bit periods of the uncoded bit period of 5 ns for a maximum preamble length of 500 ns or 40 8PSK symbol times at 12.5 ns per symbol. For 8PSK modulation, the required maximum degradation of 1 dB in -20 dB cochannel interference (CCI) drove the requirement for forward error correction coding. In this contract, the funding was not sufficient to develop the proposed codec so the codec was limited to a paper design during the preliminary design phase. The mechanization of the demodulator is digital, starting from the output of the analog to digital converters which quantize the outputs of the quadrature phase detectors. This approach is amenable to an application specific integrated circuit (ASIC) replacement in the next phase of development.

Spectrally efficient digitized radio-over-fiber system with k-means clustering-based multidimensional quantization.

PubMed

Zhang, Lu; Pang, Xiaodan; Ozolins, Oskars; Udalcovs, Aleksejs; Popov, Sergei; Xiao, Shilin; Hu, Weisheng; Chen, Jiajia

2018-04-01

We propose a spectrally efficient digitized radio-over-fiber (D-RoF) system by grouping highly correlated neighboring samples of the analog signals into multidimensional vectors, where the k-means clustering algorithm is adopted for adaptive quantization. A 30  Gbit/s D-RoF system is experimentally demonstrated to validate the proposed scheme, reporting a carrier aggregation of up to 40 100 MHz orthogonal frequency division multiplexing (OFDM) channels with quadrate amplitude modulation (QAM) order of 4 and an aggregation of 10 100 MHz OFDM channels with a QAM order of 16384. The equivalent common public radio interface rates from 37 to 150  Gbit/s are supported. Besides, the error vector magnitude (EVM) of 8% is achieved with the number of quantization bits of 4, and the EVM can be further reduced to 1% by increasing the number of quantization bits to 7. Compared with conventional pulse coding modulation-based D-RoF systems, the proposed D-RoF system improves the signal-to-noise-ratio up to ∼9  dB and greatly reduces the EVM, given the same number of quantization bits.

CALORIC: A readout chip for high granularity calorimeter

DOE Office of Scientific and Technical Information (OSTI.GOV)

Royer, L.; Bonnard, J.; Manen, S.

2011-07-01

A very-front-end electronics has been developed to fulfil requirements for the next generation of electromagnetic calorimeters. The compactness of this kind of detector and its large number of channels (up to several millions) impose a drastic limitation of the power consumption and a high level of integration. The electronic channel proposed is first of all composed of a low-noise Charge Sensitive Amplifier (CSA) able to amplify the charge delivered by a silicon diode up to 10 pC. Next, a two-gain shaping, based on a Gated Integration (G.I.), is implemented to cover the 15 bits dynamic range required: a high gainmore » shaper processes signals from 4 fC (charge corresponding to the MIP) up to 1 pC, and a low gain filter handles charges up to 10 pC. The G.I. performs also the analog memorization of the signal until it is digitalized. Hence, the analog-to-digital conversion is carried out through a low-power 12-bit cyclic ADC. If the signal overloads the high-gain channel dynamic range, a comparator selects the low-gain channel instead. Moreover, an auto-trigger channel has been implemented in order to select and store a valid event over the noise. The timing sequence of the channel is managed by a digital IP. It controls the G.I. switches, generates all needed clocks, drives the ADC and delivers the final result over 12 bits. The whole readout channel is power controlled, which permits to reduce the consumption according to the duty cycle of the beam collider. Simulations have been performed with Spectre simulator on the prototype chip designed with the 0.35 {mu}m CMOS technology from Austriamicrosystems. Results show a non-linearity better than 0.1% for the high-gain channel, and a non-linearity limited to 1% for the low-gain channel. The Equivalent Noise Charge referred to the input of the channel is evaluated to 0.4 fC complying with the MIP/10 limit. With the timing sequence of the International Linear Collider, which presents a duty cycle of 1%, the power consumption of the complete channel is limited to 43 {mu}W thanks to the power pulsing. The total area of the channel is 1.2 mm{sup 2} with an analog memory depth of 16. (authors)« less

Neuromorphic crossbar circuit with nanoscale filamentary-switching binary memristors for speech recognition.

PubMed

Truong, Son Ngoc; Ham, Seok-Jin; Min, Kyeong-Sik

2014-01-01

In this paper, a neuromorphic crossbar circuit with binary memristors is proposed for speech recognition. The binary memristors which are based on filamentary-switching mechanism can be found more popularly and are easy to be fabricated than analog memristors that are rare in materials and need a more complicated fabrication process. Thus, we develop a neuromorphic crossbar circuit using filamentary-switching binary memristors not using interface-switching analog memristors. The proposed binary memristor crossbar can recognize five vowels with 4-bit 64 input channels. The proposed crossbar is tested by 2,500 speech samples and verified to be able to recognize 89.2% of the tested samples. From the statistical simulation, the recognition rate of the binary memristor crossbar is estimated to be degraded very little from 89.2% to 80%, though the percentage variation in memristance is increased very much from 0% to 15%. In contrast, the analog memristor crossbar loses its recognition rate significantly from 96% to 9% for the same percentage variation in memristance.

Novel active signal compression in low-noise analog readout at future X-ray FEL facilities

NASA Astrophysics Data System (ADS)

Manghisoni, M.; Comotti, D.; Gaioni, L.; Lodola, L.; Ratti, L.; Re, V.; Traversi, G.; Vacchi, C.

2015-04-01

This work presents the design of a low-noise front-end implementing a novel active signal compression technique. This feature can be exploited in the design of analog readout channels for application to the next generation free electron laser (FEL) experiments. The readout architecture includes the low-noise charge sensitive amplifier (CSA) with dynamic signal compression, a time variant shaper used to process the signal at the preamplifier output and a 10-bit successive approximation register (SAR) analog-to-digital converter (ADC). The channel will be operated in such a way to cope with the high frame rate (exceeding 1 MHz) foreseen for future XFEL machines. The choice of a 65 nm CMOS technology has been made in order to include all the building blocks in the target pixel pitch of 100 μm. This work has been carried out in the frame of the PixFEL Project funded by the Istituto Nazionale di Fisica Nucleare (INFN), Italy.

The IRM fluxgate magnetometer

NASA Technical Reports Server (NTRS)

Luehr, H.; Kloecker, N.; Oelschlaegel, W.; Haeusler, B.; Acuna, M.

1985-01-01

This report describes the three-axis fluxgate magnetometer instrument on board the AMPTE IRM spacecraft. Important features of the instrument are its wide dynamic range (0.1-60,000 nT), a high resolution (16-bit analog to digital conversion) and the capability to operate automatically or via telecommand in two gain states. In addition, the wave activity is monitored in all three components up to 50 Hz. Inflight checkout proved the nominal functioning of the instrument in all modes.

Fully Integrated Passive UHF RFID Tag for Hash-Based Mutual Authentication Protocol

PubMed Central

Mikami, Shugo; Watanabe, Dai; Li, Yang; Sakiyama, Kazuo

2015-01-01

Passive radio-frequency identification (RFID) tag has been used in many applications. While the RFID market is expected to grow, concerns about security and privacy of the RFID tag should be overcome for the future use. To overcome these issues, privacy-preserving authentication protocols based on cryptographic algorithms have been designed. However, to the best of our knowledge, evaluation of the whole tag, which includes an antenna, an analog front end, and a digital processing block, that runs authentication protocols has not been studied. In this paper, we present an implementation and evaluation of a fully integrated passive UHF RFID tag that runs a privacy-preserving mutual authentication protocol based on a hash function. We design a single chip including the analog front end and the digital processing block. We select a lightweight hash function supporting 80-bit security strength and a standard hash function supporting 128-bit security strength. We show that when the lightweight hash function is used, the tag completes the protocol with a reader-tag distance of 10 cm. Similarly, when the standard hash function is used, the tag completes the protocol with the distance of 8.5 cm. We discuss the impact of the peak power consumption of the tag on the distance of the tag due to the hash function. PMID:26491714

Integrated High Resolution Digital Color Light Sensor in 130 nm CMOS Technology

PubMed Central

Strle, Drago; Nahtigal, Uroš; Batistell, Graciele; Zhang, Vincent Chi; Ofner, Erwin; Fant, Andrea; Sturm, Johannes

2015-01-01

This article presents a color light detection system integrated in 130 nm CMOS technology. The sensors and corresponding electronics detect light in a CIE XYZ color luminosity space using on-chip integrated sensors without any additional process steps, high-resolution analog-to-digital converter, and dedicated DSP algorithm. The sensor consists of a set of laterally arranged integrated photodiodes that are partly covered by metal, where color separation between the photodiodes is achieved by lateral carrier diffusion together with wavelength-dependent absorption. A high resolution, hybrid, ∑∆ ADC converts each photo diode’s current into a 22-bit digital result, canceling the dark current of the photo diodes. The digital results are further processed by the DSP, which calculates normalized XYZ or RGB color and intensity parameters using linear transformations of the three photo diode responses by multiplication of the data with a transformation matrix, where the coefficients are extracted by training in combination with a pseudo-inverse operation and the least-mean square approximation. The sensor system detects the color light parameters with 22-bit accuracy, consumes less than 60 μA on average at 10 readings per second, and occupies approx. 0.8 mm2 of silicon area (including three photodiodes and the analog part of the ADC). The DSP is currently implemented on FPGA. PMID:26205275

High-frame-rate infrared and visible cameras for test range instrumentation

NASA Astrophysics Data System (ADS)

Ambrose, Joseph G.; King, B.; Tower, John R.; Hughes, Gary W.; Levine, Peter A.; Villani, Thomas S.; Esposito, Benjamin J.; Davis, Timothy J.; O'Mara, K.; Sjursen, W.; McCaffrey, Nathaniel J.; Pantuso, Francis P.

1995-09-01

Field deployable, high frame rate camera systems have been developed to support the test and evaluation activities at the White Sands Missile Range. The infrared cameras employ a 640 by 480 format PtSi focal plane array (FPA). The visible cameras employ a 1024 by 1024 format backside illuminated CCD. The monolithic, MOS architecture of the PtSi FPA supports commandable frame rate, frame size, and integration time. The infrared cameras provide 3 - 5 micron thermal imaging in selectable modes from 30 Hz frame rate, 640 by 480 frame size, 33 ms integration time to 300 Hz frame rate, 133 by 142 frame size, 1 ms integration time. The infrared cameras employ a 500 mm, f/1.7 lens. Video outputs are 12-bit digital video and RS170 analog video with histogram-based contrast enhancement. The 1024 by 1024 format CCD has a 32-port, split-frame transfer architecture. The visible cameras exploit this architecture to provide selectable modes from 30 Hz frame rate, 1024 by 1024 frame size, 32 ms integration time to 300 Hz frame rate, 1024 by 1024 frame size (with 2:1 vertical binning), 0.5 ms integration time. The visible cameras employ a 500 mm, f/4 lens, with integration time controlled by an electro-optical shutter. Video outputs are RS170 analog video (512 by 480 pixels), and 12-bit digital video.

A SAR-ADC using unit bridge capacitor and with calibration for the front-end electronics of PET imaging

NASA Astrophysics Data System (ADS)

Liu, Wei; Wei, Tingcun; Li, Bo; Yang, Lifeng; Xue, Feifei; Hu, Yongcai

2016-05-01

This paper presents a 12-bit 1 MS/s successive approximation register-analog to digital converter (SAR-ADC) for the 32-channel front-end electronics of CZT-based PET imaging system. To reduce the capacitance mismatch, instead of the fractional capacitor, the unit capacitor is used as the bridge capacitor in the split-capacitor digital to analog converter (DAC) circuit. In addition, in order to eliminate the periodical DNL errors of -1 LSB which often exists in the SAR-ADC using the charge-redistributed DAC, a calibration algorithm is proposed and verified by the experiments. The proposed 12-bit 1 MS/s SAR-ADC is designed and implemented using a 0.35 μm CMOS technology, it occupies only an active area of 986×956 μm2. The measurement results show that, at the power supply of 3.3/5.0 V and the sampling rate of 1 MS/s, the ADC with calibration has a signal-to-noise-and-distortion ratio (SINAD) of 67.98 dB, the power dissipation of 5 mW, and a figure of merit (FOM) of 2.44 pJ/conv.-step. This ADC is with the features of high accuracy, low power and small layout area, it is especially suitable to the one-chip integration of the front-end readout electronics.

A Fully Integrated Sensor SoC with Digital Calibration Hardware and Wireless Transceiver at 2.4 GHz

PubMed Central

Kim, Dong-Sun; Jang, Sung-Joon; Hwang, Tae-Ho

2013-01-01

A single-chip sensor system-on-a-chip (SoC) that implements radio for 2.4 GHz, complete digital baseband physical layer (PHY), 10-bit sigma-delta analog-to-digital converter and dedicated sensor calibration hardware for industrial sensing systems has been proposed and integrated in a 0.18-μm CMOS technology. The transceiver's building block includes a low-noise amplifier, mixer, channel filter, receiver signal-strength indicator, frequency synthesizer, voltage-controlled oscillator, and power amplifier. In addition, the digital building block consists of offset quadrature phase-shift keying (OQPSK) modulation, demodulation, carrier frequency offset compensation, auto-gain control, digital MAC function, sensor calibration hardware and embedded 8-bit microcontroller. The digital MAC function supports cyclic redundancy check (CRC), inter-symbol timing check, MAC frame control, and automatic retransmission. The embedded sensor signal processing block consists of calibration coefficient calculator, sensing data calibration mapper and sigma-delta analog-to-digital converter with digital decimation filter. The sensitivity of the overall receiver and the error vector magnitude (EVM) of the overall transmitter are −99 dBm and 18.14%, respectively. The proposed calibration scheme has a reduction of errors by about 45.4% compared with the improved progressive polynomial calibration (PPC) method and the maximum current consumption of the SoC is 16 mA. PMID:23698271

SALT, a dedicated readout chip for high precision tracking silicon strip detectors at the LHCb Upgrade

NASA Astrophysics Data System (ADS)

Bugiel, Sz.; Dasgupta, R.; Firlej, M.; Fiutowski, T.; Idzik, M.; Kuczynska, M.; Moron, J.; Swientek, K.; Szumlak, T.

2016-02-01

The Upstream Tracker (UT) silicon strip detector, one of the central parts of the tracker system of the modernised LHCb experiment, will use a new 128-channel readout ASIC called SALT. It will extract and digitise analogue signals from the UT sensors, perform digital signal processing and transmit a serial output data. The SALT is being designed in CMOS 130 nm process and uses a novel architecture comprising of analog front-end and fast (40 MSps) ultra-low power (<0.5 mW) 6-bit ADC in each channel. The prototype ASICs of important functional blocks, like analogue front-end, 6-bit SAR ADC, PLL, and DLL, were designed, fabricated and tested. A prototype of an 8-channel version of the SALT chip, comprising all important functionalities was also designed and fabricated. The architecture and design of the SALT, together with the selected preliminary tests results, are presented.

Design, Simulation and Characteristics Research of the Interface Circuit based on nano-polysilicon thin films pressure sensor

NASA Astrophysics Data System (ADS)

Zhao, Xiaosong; Zhao, Xiaofeng; Yin, Liang

2018-03-01

This paper presents a interface circuit for nano-polysilicon thin films pressure sensor. The interface circuit includes consist of instrument amplifier and Analog-to-Digital converter (ADC). The instrumentation amplifier with a high common mode rejection ratio (CMRR) is implemented by three stages current feedback structure. At the same time, in order to satisfy the high precision requirements of pressure sensor measure system, the 1/f noise corner of 26.5 mHz can be achieved through chopping technology at a noise density of 38.2 nV/sqrt(Hz).Ripple introduced by chopping technology adopt continuous ripple reduce circuit (RRL), which achieves the output ripple level is lower than noise. The ADC achieves 16 bits significant digit by adopting sigma-delta modulator with fourth-order single-bit structure and digital decimation filter, and finally achieves high precision integrated pressure sensor interface circuit.

A Three-Step Resolution-Reconfigurable Hazardous Multi-Gas Sensor Interface for Wireless Air-Quality Monitoring Applications.

PubMed

Choi, Subin; Park, Kyeonghwan; Lee, Seungwook; Lim, Yeongjin; Oh, Byungjoo; Chae, Hee Young; Park, Chan Sam; Shin, Heugjoo; Kim, Jae Joon

2018-03-02

This paper presents a resolution-reconfigurable wide-range resistive sensor readout interface for wireless multi-gas monitoring applications that displays results on a smartphone. Three types of sensing resolutions were selected to minimize processing power consumption, and a dual-mode front-end structure was proposed to support the detection of a variety of hazardous gases with wide range of characteristic resistance. The readout integrated circuit (ROIC) was fabricated in a 0.18 μm CMOS process to provide three reconfigurable data conversions that correspond to a low-power resistance-to-digital converter (RDC), a 12-bit successive approximation register (SAR) analog-to-digital converter (ADC), and a 16-bit delta-sigma modulator. For functional feasibility, a wireless sensor system prototype that included in-house microelectromechanical (MEMS) sensing devices and commercial device products was manufactured and experimentally verified to detect a variety of hazardous gases.

A 0.18 micrometer CMOS Thermopile Readout ASIC Immune to 50 MRAD Total Ionizing Dose (SI) and Single Event Latchup to 174MeV-cm(exp 2)/mg

NASA Technical Reports Server (NTRS)

Quilligan, Gerard T.; Aslam, Shahid; Lakew, Brook; DuMonthier, Jeffery J.; Katz, Richard B.; Kleyner, Igor

2014-01-01

Radiation hardened by design (RHBD) techniques allow commercial CMOS circuits to operate in high total ionizing dose and particle fluence environments. Our radiation hard multi-channel digitizer (MCD) ASIC (Figure 1) is a versatile analog system on a chip (SoC) fabricated in 180nm CMOS. It provides 18 chopper stabilized amplifier channels, a 16- bit sigma-delta analog-digital converter (SDADC) and an on-chip controller. The MCD was evaluated at Goddard Space Flight Center and Texas A&M University's radiation effects facilities and found to be immune to single event latchup (SEL) and total ionizing dose (TID) at 174 MeV-cm(exp 2)/mg and 50 Mrad (Si) respectively.

Ultra-fast analog-to-digital converter based on a nonlinear triplexer and an optical coder with a photonic crystal structure.

PubMed

Mehdizadeh, Farhad; Soroosh, Mohammad; Alipour-Banaei, Hamed; Farshidi, Ebrahim

2017-03-01

In this paper, we propose what we believe is a novel all-optical analog-to-digital converter (ADC) based on photonic crystals. The proposed structure is composed of a nonlinear triplexer and an optical coder. The nonlinear triplexer is for creating discrete levels in the continuous optical input signal, and the optical coder is for generating a 2-bit standard binary code out of the discrete levels coming from the nonlinear triplexer. Controlling the resonant mode of the resonant rings through optical intensity is the main objective and working mechanism of the proposed structure. The maximum delay time obtained for the proposed structure was about 5 ps and the total footprint is about 1520  μm².

Performance Analysis for Channel Estimation With 1-Bit ADC and Unknown Quantization Threshold

NASA Astrophysics Data System (ADS)

Stein, Manuel S.; Bar, Shahar; Nossek, Josef A.; Tabrikian, Joseph

2018-05-01

In this work, the problem of signal parameter estimation from measurements acquired by a low-complexity analog-to-digital converter (ADC) with $1$-bit output resolution and an unknown quantization threshold is considered. Single-comparator ADCs are energy-efficient and can be operated at ultra-high sampling rates. For analysis of such systems, a fixed and known quantization threshold is usually assumed. In the symmetric case, i.e., zero hard-limiting offset, it is known that in the low signal-to-noise ratio (SNR) regime the signal processing performance degrades moderately by ${2}/{\\pi}$ ($-1.96$ dB) when comparing to an ideal $\\infty$-bit converter. Due to hardware imperfections, low-complexity $1$-bit ADCs will in practice exhibit an unknown threshold different from zero. Therefore, we study the accuracy which can be obtained with receive data processed by a hard-limiter with unknown quantization level by using asymptotically optimal channel estimation algorithms. To characterize the estimation performance of these nonlinear algorithms, we employ analytic error expressions for different setups while modeling the offset as a nuisance parameter. In the low SNR regime, we establish the necessary condition for a vanishing loss due to missing offset knowledge at the receiver. As an application, we consider the estimation of single-input single-output wireless channels with inter-symbol interference and validate our analysis by comparing the analytic and experimental performance of the studied estimation algorithms. Finally, we comment on the extension to multiple-input multiple-output channel models.

Scalable hybrid computation with spikes.

PubMed

Sarpeshkar, Rahul; O'Halloran, Micah

2002-09-01

We outline a hybrid analog-digital scheme for computing with three important features that enable it to scale to systems of large complexity: First, like digital computation, which uses several one-bit precise logical units to collectively compute a precise answer to a computation, the hybrid scheme uses several moderate-precision analog units to collectively compute a precise answer to a computation. Second, frequent discrete signal restoration of the analog information prevents analog noise and offset from degrading the computation. And, third, a state machine enables complex computations to be created using a sequence of elementary computations. A natural choice for implementing this hybrid scheme is one based on spikes because spike-count codes are digital, while spike-time codes are analog. We illustrate how spikes afford easy ways to implement all three components of scalable hybrid computation. First, as an important example of distributed analog computation, we show how spikes can create a distributed modular representation of an analog number by implementing digital carry interactions between spiking analog neurons. Second, we show how signal restoration may be performed by recursive spike-count quantization of spike-time codes. And, third, we use spikes from an analog dynamical system to trigger state transitions in a digital dynamical system, which reconfigures the analog dynamical system using a binary control vector; such feedback interactions between analog and digital dynamical systems create a hybrid state machine (HSM). The HSM extends and expands the concept of a digital finite-state-machine to the hybrid domain. We present experimental data from a two-neuron HSM on a chip that implements error-correcting analog-to-digital conversion with the concurrent use of spike-time and spike-count codes. We also present experimental data from silicon circuits that implement HSM-based pattern recognition using spike-time synchrony. We outline how HSMs may be used to perform learning, vector quantization, spike pattern recognition and generation, and how they may be reconfigured.

Scaling vectors of attoJoule per bit modulators

NASA Astrophysics Data System (ADS)

Sorger, Volker J.; Amin, Rubab; Khurgin, Jacob B.; Ma, Zhizhen; Dalir, Hamed; Khan, Sikandar

2018-01-01

Electro-optic modulation performs the conversion between the electrical and optical domain with applications in data communication for optical interconnects, but also for novel optical computing algorithms such as providing nonlinearity at the output stage of optical perceptrons in neuromorphic analog optical computing. While resembling an optical transistor, the weak light-matter-interaction makes modulators 105 times larger compared to their electronic counterparts. Since the clock frequency for photonics on-chip has a power-overhead sweet-spot around tens of GHz, ultrafast modulation may only be required in long-distance communication, not for short on-chip links. Hence, the search is open for power-efficient on-chip modulators beyond the solutions offered by foundries to date. Here, we show scaling vectors towards atto-Joule per bit efficient modulators on-chip as well as some experimental demonstrations of novel plasmonic modulators with sub-fJ/bit efficiencies. Our parametric study of placing different actively modulated materials into plasmonic versus photonic optical modes shows that 2D materials overcompensate their miniscule modal overlap by their unity-high index change. Furthermore, we reveal that the metal used in plasmonic-based modulators not only serves as an electrical contact, but also enables low electrical series resistances leading to near-ideal capacitors. We then discuss the first experimental demonstration of a photon-plasmon-hybrid graphene-based electro-absorption modulator on silicon. The device shows a sub-1 V steep switching enabled by near-ideal electrostatics delivering a high 0.05 dB V-1 μm-1 performance requiring only 110 aJ/bit. Improving on this demonstration, we discuss a plasmonic slot-based graphene modulator design, where the polarization of the plasmonic mode aligns with graphene’s in-plane dimension; where a push-pull dual-gating scheme enables 2 dB V-1 μm-1 efficient modulation allowing the device to be just 770 nm short for 3 dB small signal modulation. Lastly, comparing the switching energy of transistors to modulators shows that modulators based on emerging materials and plasmonic-silicon hybrid integration perform on-par relative to their electronic counter parts. This in turn allows for a device-enabled two orders-of-magnitude improvement of electrical-optical co-integrated network-on-chips over electronic-only architectures. The latter opens technological opportunities in cognitive computing, dynamic data-driven applications systems, and optical analog computer engines including neuromorphic photonic computing.

Microdensitometer errors: Their effect on photometric data reduction

NASA Technical Reports Server (NTRS)

Bozyan, E. P.; Opal, C. B.

1984-01-01

The performance of densitometers used for photometric data reduction of high dynamic range electrographic plate material is analyzed. Densitometer repeatability is tested by comparing two scans of one plate. Internal densitometer errors are examined by constructing histograms of digitized densities and finding inoperative bits and differential nonlinearity in the analog to digital converter. Such problems appear common to the four densitometers used in this investigation and introduce systematic algorithm dependent errors in the results. Strategies to improve densitometer performance are suggested.

Preliminary design and implementation of the baseline digital baseband architecture for advanced deep space transponders

NASA Technical Reports Server (NTRS)

Nguyen, T. M.; Yeh, H.-G.

1993-01-01

The baseline design and implementation of the digital baseband architecture for advanced deep space transponders is investigated and identified. Trade studies on the selection of the number of bits for the analog-to-digital converter (ADC) and optimum sampling schemes are presented. In addition, the proposed optimum sampling scheme is analyzed in detail. Descriptions of possible implementations for the digital baseband (or digital front end) and digital phase-locked loop (DPLL) for carrier tracking are also described.

Wing Dike of Hardened Lava in New Mexico

NASA Image and Video Library

2017-01-25

This photograph from northwestern New Mexico shows a ridge roughly 30 feet about 10 meters tall that formed from lava filling an underground fracture then resisting erosion better than the material around it did. The dike extends from a volcanic peak (out of view here) called Shiprock in English and Tsé Bit'a'í, meaning "rock with wings," in the Navajo language. It offers an Earth analog for some larger hardened-lava walls on Mars http://photojournal.jpl.nasa.gov/catalog/PIA21266

A Compressed Sensing Based Ultra-Wideband Communication System

DTIC Science & Technology

2009-06-01

principle, most of the processing at the receiver can be moved to the transmitter—where energy consumption and computation are sufficient for many advanced...extended to continuous time signals. We use ∗ to denote the convolution process in a linear time-invariant (LTI) system. Assume that there is an analog...Filter Channel Low Rate A/D Processing Sparse Bit Sequence UWB Pulse Generator α̂ Waves)(RadioGHz 5 MHz125 θ Ψ Φ y θ̂ 1 ˆ arg min s.t. yθ

Performance of a flight qualified, thermoelectrically temperature controlled QCM sensor with power supply, thermal controller and signal processor

NASA Technical Reports Server (NTRS)

Wallace, D. A.

1980-01-01

A thermoelectrically temperature controlled quartz crystal microbalance (QCM) system was developed for the measurement of ion thrustor generated mercury contamination on spacecraft. Meaningful flux rate measurements dictated an accurately held sensing crystal temperature despite spacecraft surface temperature variations from -35 C to +60 C over the flight temperature range. An electronic control unit was developed with magentic amplifier transformer secondary power supply, thermal control electronics, crystal temperature analog conditioning and a multiplexed 16 bit frequency encoder.

Pulse Code Modulation (PCM) encoder handbook for Aydin Vector MMP-900 series system

NASA Technical Reports Server (NTRS)

Raphael, David

1995-01-01

This handbook explicates the hardware and software properties of a time division multiplex system. This system is used to sample analog and digital data. The data is then merged with frame synchronization information to produce a serial pulse coded modulation (PCM) bit stream. Information in this handbook is required by users to design congruous interface and attest effective utilization of this encoder system. Aydin Vector provides all of the components for these systems to Goddard Space Flight Center/Wallops Flight Facility.

A memory-mapped output interface: Omega navigation output data from the JOLT (TM) microcomputer

NASA Technical Reports Server (NTRS)

Lilley, R. W.

1976-01-01

A hardware interface which allows both digital and analog data output from the JOLT microcomputer is described in the context of a software-based Omega Navigation receiver. The interface hardware described is designed for output of six (or eight with simple extensions) bits of binary output in response to a memory store command from the microcomputer. The interface was produced in breadboard form and is operational as an evaluation aid for the software Omega receiver.

Signal chain for the Airborne Visible/Infrared Imaging Spectrometer (AVIRIS)

NASA Technical Reports Server (NTRS)

Bunn, James S., Jr.

1988-01-01

The AVIRIS instrument has a separate dedicated analog signal processing chain for each of its four spectrometers. The signal chains amplify low-level focal-plane line array signals (5 to 10 mV full-scale span) in the presence of larger multiplexing signals (approx 150 mV) providing the data handling system a ten-bit digital word (for each spectrometer) each 1.3 microns. This signal chain provides automatic correction for the line array dark signal nonuniformity (which can approach the full-scale signal span).

Signal chain for the Airborne Visible/Infrared Imaging Spectrometer (AVIRIS)

NASA Technical Reports Server (NTRS)

Bunn, James S., Jr.

1987-01-01

The AVIRIS instrument has a separate dedicated analog signal processing chain for each of its four spectrometers. The signal chains amplify low-level focal-plane line array signals (5 to 10 mV full-scale span) in the presence of larger multiplexing signals (approx 150 mV) providing the data handling system a ten-bit digital word (for each spectrometer) each 1.3 microns. This signal chain provides automatic correction for the line array dark signal nonuniformity (which can approach the full-scale signal span).

Design of 90×8 ROIC with pixel level digital TDI implementation for scanning type LWIR FPAs

NASA Astrophysics Data System (ADS)

Ceylan, Omer; Kayahan, Huseyin; Yazici, Melik; Gurbuz, Yasar

2013-06-01

Design of a 90×8 CMOS readout integrated circuit (ROIC) based on pixel level digital time delay integration (TDI) for scanning type LWIR focal plane arrays (FPAs) is presented. TDI is implemented on 8 pixels which improves the SNR of the system with a factor of √8. Oversampling rate of 3 improves the spatial resolution of the system. TDI operation is realized with a novel under-pixel analog-to-digital converter, which improves the noise performance of ROIC with a lower quantization noise. Since analog signal is converted to digital domain in-pixel, non-uniformities and inaccuracies due to analog signal routing over large chip area is eliminated. Contributions of each pixel for proper TDI operation are added in summation counters, no op-amps are used for summation, hence power consumption of ROIC is lower than its analog counterparts. Due to lack of multiple capacitors or summation amplifiers, ROIC occupies smaller chip area compared to its analog counterparts. ROIC is also superior to its digital counterparts due to novel digital TDI implementation in terms of power consumption, noise and chip area. ROIC supports bi-directional scan, multiple gain settings, bypass operation, automatic gain adjustment, pixel select/deselect, and is programmable through serial or parallel interface. Input referred noise of ROIC is less than 750 rms electrons, while power consumption is less than 20mW. ROIC is designed to perform both in room and cryogenic temperatures.

A Spacecraft Housekeeping System-on-Chip in a Radiation Hardened Structured ASIC

NASA Technical Reports Server (NTRS)

Suarez, George; DuMonthier, Jeffrey J.; Sheikh, Salman S.; Powell, Wesley A.; King, Robyn L.

2012-01-01

Housekeeping systems are essential to health monitoring of spacecraft and instruments. Typically, sensors are distributed across various sub-systems and data is collected using components such as analog-to-digital converters, analog multiplexers and amplifiers. In most cases programmable devices are used to implement the data acquisition control and storage, and the interface to higher level systems. Such discrete implementations require additional size, weight, power and interconnect complexity versus an integrated circuit solution, as well as the qualification of multiple parts. Although commercial devices are readily available, they are not suitable for space applications due the radiation tolerance and qualification requirements. The Housekeeping System-o n-A-Chip (HKSOC) is a low power, radiation hardened integrated solution suitable for spacecraft and instrument control and data collection. A prototype has been designed and includes a wide variety of functions including a 16-channel analog front-end for driving and reading sensors, analog-to-digital and digital-to-analog converters, on-chip temperature sensor, power supply current sense circuits, general purpose comparators and amplifiers, a 32-bit processor, digital I/O, pulse-width modulation (PWM) generators, timers and I2C master and slave serial interfaces. In addition, the device can operate in a bypass mode where the processor is disabled and external logic is used to control the analog and mixed signal functions. The device is suitable for stand-alone or distributed systems where multiple chips can be deployed across different sub-systems as intelligent nodes with computing and processing capabilities.

Initial Results from the Bloomsburg University Goniometer Laboratory

NASA Technical Reports Server (NTRS)

Shepard, M. K.

2002-01-01

The Bloomsburg University Goniometer Laboratory (B.U.G. Lab) consists of three systems for studying the photometric properties of samples. The primary system is an automated goniometer capable of measuring the entire bi-directional reflectance distribution function (BRDF) of samples. Secondary systems include a reflectance spectrometer and digital video camera with macro zoom lens for characterizing and documenting other physical properties of measured samples. Works completed or in progress include the characterization of the BRDF of calibration surfaces for the 2003 Mars Exploration Rovers (MER03), Martian analog soils including JSC-Mars-1, and tests of photometric models.

On-chip integratable all-optical quantizer using strong cross-phase modulation in a silicon-organic hybrid slot waveguide

PubMed Central

Kang, Zhe; Yuan, Jinhui; Zhang, Xianting; Sang, Xinzhu; Wang, Kuiru; Wu, Qiang; Yan, Binbin; Li, Feng; Zhou, Xian; Zhong, Kangping; Zhou, Guiyao; Yu, Chongxiu; Farrell, Gerald; Lu, Chao; Yaw Tam, Hwa; Wai, P. K. A.

2016-01-01

High performance all-optical quantizer based on silicon waveguide is believed to have significant applications in photonic integratable optical communication links, optical interconnection networks, and real-time signal processing systems. In this paper, we propose an integratable all-optical quantizer for on-chip and low power consumption all-optical analog-to-digital converters. The quantization is realized by the strong cross-phase modulation and interference in a silicon-organic hybrid (SOH) slot waveguide based Mach-Zehnder interferometer. By carefully designing the dimension of the SOH waveguide, large nonlinear coefficients up to 16,000 and 18,069 W−1/m for the pump and probe signals can be obtained respectively, along with a low pulse walk-off parameter of 66.7 fs/mm, and all-normal dispersion in the wavelength regime considered. Simulation results show that the phase shift of the probe signal can reach 8π at a low pump pulse peak power of 206 mW and propagation length of 5 mm such that a 4-bit all-optical quantizer can be realized. The corresponding signal-to-noise ratio is 23.42 dB and effective number of bit is 3.89-bit. PMID:26777054

The feasibility of inflight measurement of lightning strike parameters

NASA Technical Reports Server (NTRS)

Crouch, K. E.; Plumer, J. A.

1978-01-01

The appearance of nonmetallic structural materials and microelectronics in aircraft design has resulted in a need for better knowledge of hazardous environments such as lightning and the effects these environments have on the aircraft. This feasibility study was performed to determine the lightning parameters in the greatest need of clarification and the performance requirements of equipment necessary to sense and record these parameters on an instrumented flight research aircraft. It was found that electric field rate of change, lightning currents, and induced voltages in aircraft wiring are the parameters of greatest importance. Flat-plate electric field sensors and resistive current shunts are proposed for electric field and current sensors, to provide direct measurements of these parameters. Six bit analog-to-digital signal conversion at a 5 nanosecond sampling rate, short-term storage of 85000 bits and long term storage of 5 x 10 to the 7th power bits of electric field, current and induced voltage data on the airplane are proposed, with readout and further analysis to be accomplished on the ground. A NASA F-106B was found to be suitable for use as the research aircraft because it has a minimum number of possible lightning attachment points, space for the necessary instrumentation, and appears to meet operational requirements. Safety considerations are also presented.

Low-Actuation Voltage MEMS Digital-to-Analog Converter with Parylene Spring Structures.

PubMed

Ma, Cheng-Wen; Lee, Fu-Wei; Liao, Hsin-Hung; Kuo, Wen-Cheng; Yang, Yao-Joe

2015-08-28

We propose an electrostatically-actuated microelectromechanical digital-to-analog converter (M-DAC) device with low actuation voltage. The spring structures of the silicon-based M-DAC device were monolithically fabricated using parylene-C. Because the Young's modulus of parylene-C is considerably lower than that of silicon, the electrostatic microactuators in the proposed device require much lower actuation voltages. The actuation voltage of the proposed M-DAC device is approximately 6 V, which is less than one half of the actuation voltages of a previously reported M-DAC equipped with electrostatic microactuators. The measured total displacement of the proposed three-bit M-DAC is nearly 504 nm, and the motion step is approximately 72 nm. Furthermore, we demonstrated that the M-DAC can be employed as a mirror platform with discrete displacement output for a noncontact surface profiling system.

A system-level view of optimizing high-channel-count wireless biosignal telemetry.

PubMed

Chandler, Rodney J; Gibson, Sarah; Karkare, Vaibhav; Farshchi, Shahin; Marković, Dejan; Judy, Jack W

2009-01-01

In this paper we perform a system-level analysis of a wireless biosignal telemetry system. We perform an analysis of each major system component (e.g., analog front end, analog-to-digital converter, digital signal processor, and wireless link), in which we consider physical, algorithmic, and design limitations. Since there are a wide range applications for wireless biosignal telemetry systems, each with their own unique set of requirements for key parameters (e.g., channel count, power dissipation, noise level, number of bits, etc.), our analysis is equally broad. The net result is a set of plots, in which the power dissipation for each component and as the system as a whole, are plotted as a function of the number of channels for different architectural strategies. These results are also compared to existing implementations of complete wireless biosignal telemetry systems.

Oscillatory motor network activity during rest and movement: an fNIRS study

PubMed Central

Bajaj, Sahil; Drake, Daniel; Butler, Andrew J.; Dhamala, Mukesh

2014-01-01

Coherent network oscillations (<0.1 Hz) linking distributed brain regions are commonly observed in the brain during both rest and task conditions. What oscillatory network exists and how network oscillations change in connectivity strength, frequency and direction when going from rest to explicit task are topics of recent inquiry. Here, we study network oscillations within the sensorimotor regions of able-bodied individuals using hemodynamic activity as measured by functional near-infrared spectroscopy (fNIRS). Using spectral interdependency methods, we examined how the supplementary motor area (SMA), the left premotor cortex (LPMC) and the left primary motor cortex (LM1) are bound as a network during extended resting state (RS) and between-tasks resting state (btRS), and how the activity of the network changes as participants execute left, right, and bilateral hand (LH, RH, and BH) finger movements. We found: (i) power, coherence and Granger causality (GC) spectra had significant peaks within the frequency band (0.01–0.04 Hz) during RS whereas the peaks shifted to a bit higher frequency range (0.04–0.08 Hz) during btRS and finger movement tasks, (ii) there was significant bidirectional connectivity between all the nodes during RS and unidirectional connectivity from the LM1 to SMA and LM1 to LPMC during btRS, and (iii) the connections from SMA to LM1 and from LPMC to LM1 were significantly modulated in LH, RH, and BH finger movements relative to btRS. The unidirectional connectivity from SMA to LM1 just before the actual task changed to the bidirectional connectivity during LH and BH finger movement. The uni-directionality could be associated with movement suppression and the bi-directionality with preparation, sensorimotor update and controlled execution. These results underscore that fNIRS is an effective tool for monitoring spectral signatures of brain activity, which may serve as an important precursor before monitoring the recovery progress following brain injury. PMID:24550793

Design and characterization of a 12-bit 10MS/s 10mW pipelined SAR ADC for CZT-based hard X-ray imager

NASA Astrophysics Data System (ADS)

Xue, F.; Gao, W.; Duan, Y.; Zheng, R.; Hu, Y.

2018-02-01

This paper presents a 12-bit pipelined successive approximation register (SAR) ADC for CZT-based hard X-ray Imager. The proposed ADC is comprised of a first-stage 6-bit SAR-based Multiplying Digital Analog Converter (MDAC) and a second-stage 8-bit SAR ADC. A novel MDAC architecture using Vcm-based Switching method is employed to maximize the energy efficiency and improve the linearity of the ADC. Moreover, the unit-capacitor array instead of the binary-weighted capacitor array is adopted to improve the conversion speed and linearity of the ADC in the first-stage MDAC. In addition, a new layout design method for the binary-weighted capacitor array is proposed to reduce the capacitor mismatches and make the routing become easier and less-time-consuming. Finally, several radiation-hardened-by-design technologies are adopted in the layout design against space radiation effects. The prototype chip was fabricated in 0.18 μm mixed-signal 1.8V/3.3V process and operated at 1.8 V supply. The chip occupies a core area of only 0.58 mm2. The proposed pipelined SAR ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 66.7 dB and a peak spurious-free dynamic range (SFDR) of 78.6 dB at 10 MS/s sampling rate and consumes 10 mW. The figure of merit (FOM) of the proposed ADC is 0.56 pJ/conversion-step.

Physical layer one-time-pad data encryption through synchronized semiconductor laser networks

NASA Astrophysics Data System (ADS)

Argyris, Apostolos; Pikasis, Evangelos; Syvridis, Dimitris

2016-02-01

Semiconductor lasers (SL) have been proven to be a key device in the generation of ultrafast true random bit streams. Their potential to emit chaotic signals under conditions with desirable statistics, establish them as a low cost solution to cover various needs, from large volume key generation to real-time encrypted communications. Usually, only undemanding post-processing is needed to convert the acquired analog timeseries to digital sequences that pass all established tests of randomness. A novel architecture that can generate and exploit these true random sequences is through a fiber network in which the nodes are semiconductor lasers that are coupled and synchronized to central hub laser. In this work we show experimentally that laser nodes in such a star network topology can synchronize with each other through complex broadband signals that are the seed to true random bit sequences (TRBS) generated at several Gb/s. The potential for each node to access real-time generated and synchronized with the rest of the nodes random bit streams, through the fiber optic network, allows to implement an one-time-pad encryption protocol that mixes the synchronized true random bit sequence with real data at Gb/s rates. Forward-error correction methods are used to reduce the errors in the TRBS and the final error rate at the data decoding level. An appropriate selection in the sampling methodology and properties, as well as in the physical properties of the chaotic seed signal through which network locks in synchronization, allows an error free performance.

An actively mode-locked fiber laser for sampling in a wide-bandwidth opto-electronic analog-to-digital converter

NASA Astrophysics Data System (ADS)

Powers, John P.; Pace, Phillip E.

2008-02-01

We have designed, built and tested an actively mode-locked fiber laser, operating at 1550 nm, for use as the sampling waveform in an opto-electronic analog-to-digital converter (ADC). Analysis shows that, in order to digitize a 10-GHz signal to 10 bits of resolution, the sampling pulsewidth must be less than 2.44 ps, the RMS timing jitter must be below 31.0 fs, and the RMS amplitude jitter must be below 0.195%. Fiber lasers have proven to have the capability to narrowly exceed these operating requirements. The fiber laser is a "sigma" laser consisting of Er-doped gain medium, dispersion-compensating fiber, nonlinear fiber, a Faraday rotation mirror, polarization-maintaining fiber and components, and diode pump lasers. The active mode-locking is achieved by a Mach-Zehnder interferometer modulator, driven by a frequency synthesizer operating at the desired sampling rate. A piezo-electric element is used in a feedback control loop to stabilize the output PRF against environmental changes. Measurements of the laser output revealed the maximum nominal PRF to be 16 GHz, the nominal pulsewidth to be 7.2 ps, and the nominal RNS timing jitter to be 386 fs. Incorporating this laser into a sampling ADC would allow us to sample a 805-MHz bandwidth signal to a resolution of 10 bits as limited by timing jitter. Techniques to reduce the timing-jitter bottleneck are discussed.

VHDL Implementation of Sigma-Delta Analog To Digital Converter

NASA Astrophysics Data System (ADS)

Chavan, R. N.; Chougule, D. G.

2010-11-01

Sigma-Delta modulation techniques provide a range of opportunities in a signal processing system for both increasing performance and data path optimization along the silicon area axis in the design space. One of the most challenging tasks in Analog to Digital Converter (ADC) design is to adapt the circuitry to ever new CMOS process technology. For digital circuits the number of gates per square mm app. doubles per chip generation. Integration of analog parts in newer deep submicron technologies is much more tough and additionally complicated because the usable voltage ranges are decreasing with every new integration step. This paper shows an approach which only uses 2 resistors and 1 capacitor which are located outside a pure digital chip. So all integration advantages of pure digital chips are preserved, there is no design effort for a new chip generation and the ADC also can be used for FPGAs. Resolutions of up to 16 bit are achievable. Sample rates in the 1 MHz region are feasible so that the approach is also useful for ADCs for xDSL technologies.

A 32-channel front-end ASIC for GEM detectors used in beam monitoring applications

NASA Astrophysics Data System (ADS)

Ciciriello, F.; Altieri, P. R.; Corsi, F.; De Robertis, G.; Felici, G.; Loddo, F.; Lorusso, L.; Marzocca, C.; Matarrese, G.; Ranieri, A.; Stamerra, A.

2017-11-01

A multichannel, mixed-signal, front-end ASIC for GEM detectors, intended for beam monitoring in hadron therapy applications, has been designed and prototyped in a standard 0.35 μm CMOS technology. The analog channels are based on the classic CSA + shaper processing chain, followed by a peak detector which can work as an analog memory, to simplifiy the analog-to-digital conversion of the peak voltage of the output pulse, proportional to the energy of the detected event. The available hardware resources include an 8-bit A/D converter and a standard-cell digital part, which manages the read-out procedure, in sparse or serial mode. The ASIC is self-triggered and transfers energy and address data to the external DAQ via a fast 100 MHz LVDS link. Preliminary characterization results show that the non-linearity error is limited to 5% for a maximum input charge of about 70 fC, the measured ENC is about 1400e- and the time jitter of the trigger signal generated in response to an injected charge of 60 fC is close to 200 ps.

Memristor-Based Analog Computation and Neural Network Classification with a Dot Product Engine.

PubMed

Hu, Miao; Graves, Catherine E; Li, Can; Li, Yunning; Ge, Ning; Montgomery, Eric; Davila, Noraica; Jiang, Hao; Williams, R Stanley; Yang, J Joshua; Xia, Qiangfei; Strachan, John Paul

2018-03-01

Using memristor crossbar arrays to accelerate computations is a promising approach to efficiently implement algorithms in deep neural networks. Early demonstrations, however, are limited to simulations or small-scale problems primarily due to materials and device challenges that limit the size of the memristor crossbar arrays that can be reliably programmed to stable and analog values, which is the focus of the current work. High-precision analog tuning and control of memristor cells across a 128 × 64 array is demonstrated, and the resulting vector matrix multiplication (VMM) computing precision is evaluated. Single-layer neural network inference is performed in these arrays, and the performance compared to a digital approach is assessed. Memristor computing system used here reaches a VMM accuracy equivalent of 6 bits, and an 89.9% recognition accuracy is achieved for the 10k MNIST handwritten digit test set. Forecasts show that with integrated (on chip) and scaled memristors, a computational efficiency greater than 100 trillion operations per second per Watt is possible. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

A wideband dual-antenna receiver for wireless recording from animals behaving in large arenas.

PubMed

Lee, Seung Bae; Yin, Ming; Manns, Joseph R; Ghovanloo, Maysam

2013-07-01

A low-noise wideband receiver (Rx) is presented for a multichannel wireless implantable neural recording (WINeR) system that utilizes time-division multiplexing of pulse width modulated (PWM) samples. The WINeR-6 Rx consists of four parts: 1) RF front end; 2) signal conditioning; 3) analog output (AO); and 4) field-programmable gate array (FPGA) back end. The RF front end receives RF-modulated neural signals in the 403-490 MHz band with a wide bandwidth of 18 MHz. The frequency-shift keying (FSK) PWM demodulator in the FPGA is a time-to-digital converter with 304 ps resolution, which converts the analog pulse width information to 16-bit digital samples. Automated frequency tracking has been implemented in the Rx to lock onto the free-running voltage-controlled oscillator in the transmitter (Tx). Two antennas and two parallel RF paths are used to increase the wireless coverage area. BCI-2000 graphical user interface has been adopted and modified to acquire, visualize, and record the recovered neural signals in real time. The AO module picks three demultiplexed channels and converts them into analog signals for direct observation on an oscilloscope. One of these signals is further amplified to generate an audio output, offering users the ability to listen to ongoing neural activity. Bench-top testing of the Rx performance with a 32-channel WINeR-6 Tx showed that the input referred noise of the entire system at a Tx-Rx distance of 1.5 m was 4.58 μV rms with 8-bit resolution at 640 kSps. In an in vivo experiment, location-specific receptive fields of hippocampal place cells were mapped during a behavioral experiment in which a rat completed 40 laps in a large circular track. Results were compared against those acquired from the same animal and the same set of electrodes by a commercial hardwired recording system to validate the wirelessly recorded signals.

A compact 16-module camera using 64-pixel CsI(Tl)/Si p-i-n photodiode imaging modules

NASA Astrophysics Data System (ADS)

Choong, W.-S.; Gruber, G. J.; Moses, W. W.; Derenzo, S. E.; Holland, S. E.; Pedrali-Noy, M.; Krieger, B.; Mandelli, E.; Meddeler, G.; Wang, N. W.; Witt, E. K.

2002-10-01

We present a compact, configurable scintillation camera employing a maximum of 16 individual 64-pixel imaging modules resulting in a 1024-pixel camera covering an area of 9.6 cm/spl times/9.6 cm. The 64-pixel imaging module consists of optically isolated 3 mm/spl times/3 mm/spl times/5 mm CsI(Tl) crystals coupled to a custom array of Si p-i-n photodiodes read out by a custom integrated circuit (IC). Each imaging module plugs into a readout motherboard that controls the modules and interfaces with a data acquisition card inside a computer. For a given event, the motherboard employs a custom winner-take-all IC to identify the module with the largest analog output and to enable the output address bits of the corresponding module's readout IC. These address bits identify the "winner" pixel within the "winner" module. The peak of the largest analog signal is found and held using a peak detect circuit, after which it is acquired by an analog-to-digital converter on the data acquisition card. The camera is currently operated with four imaging modules in order to characterize its performance. At room temperature, the camera demonstrates an average energy resolution of 13.4% full-width at half-maximum (FWHM) for the 140-keV emissions of /sup 99m/Tc. The system spatial resolution is measured using a capillary tube with an inner diameter of 0.7 mm and located 10 cm from the face of the collimator. Images of the line source in air exhibit average system spatial resolutions of 8.7- and 11.2-mm FWHM when using an all-purpose and high-sensitivity parallel hexagonal holes collimator, respectively. These values do not change significantly when an acrylic scattering block is placed between the line source and the camera.

A Wideband Dual-Antenna Receiver for Wireless Recording From Animals Behaving in Large Arenas

PubMed Central

Lee, Seung Bae; Yin, Ming; Manns, Joseph R.

2014-01-01

A low-noise wideband receiver (Rx) is presented for a multichannel wireless implantable neural recording (WINeR) system that utilizes time-division multiplexing of pulse width modulated (PWM) samples. The WINeR-6 Rx consists of four parts: 1) RF front end; 2) signal conditioning; 3) analog output (AO); and 4) field-programmable gate array (FPGA) back end. The RF front end receives RF-modulated neural signals in the 403–490 MHz band with a wide bandwidth of 18 MHz. The frequency-shift keying (FSK) PWM demodulator in the FPGA is a time-to-digital converter with 304 ps resolution, which converts the analog pulse width information to 16-bit digital samples. Automated frequency tracking has been implemented in the Rx to lock onto the free-running voltage-controlled oscillator in the transmitter (Tx). Two antennas and two parallel RF paths are used to increase the wireless coverage area. BCI-2000 graphical user interface has been adopted and modified to acquire, visualize, and record the recovered neural signals in real time. The AO module picks three demultiplexed channels and converts them into analog signals for direct observation on an oscilloscope. One of these signals is further amplified to generate an audio output, offering users the ability to listen to ongoing neural activity. Bench-top testing of the Rx performance with a 32-channel WINeR-6 Tx showed that the input referred noise of the entire system at a Tx–Rx distance of 1.5 m was 4.58 μVrms with 8-bit resolution at 640 kSps. In an in vivo experiment, location-specific receptive fields of hippocampal place cells were mapped during a behavioral experiment in which a rat completed 40 laps in a large circular track. Results were compared against those acquired from the same animal and the same set of electrodes by a commercial hardwired recording system to validate the wirelessly recorded signals. PMID:23428612

Intelligent Articulated Robot

NASA Astrophysics Data System (ADS)

Nyein, Aung Kyaw; Thu, Theint Theint

2008-10-01

In this paper, an articulated type of industrial used robot is discussed. The robot is mainly intended to be used in pick and place operation. It will sense the object at the specified place and move it to a desired location. A peripheral interface controller (PIC16F84A) is used as the main controller of the robot. Infrared LED and IR receiver unit for object detection and 4-bit bidirectional universal shift registers (74LS194) and high current and high voltage Darlington transistors arrays (ULN2003) for driving the arms' motors are used in this robot. The amount of rotation for each arm is regulated by the limit switches. The operation of the robot is very simple but it has the ability of to overcome resetting position after power failure. It can continue its work from the last position before the power is failed without needing to come back to home position.

High-efficient full-duplex WDM-RoF system with sub-central station

NASA Astrophysics Data System (ADS)

Liu, Anliang; Yin, Hongxi; Wu, Bin

2018-05-01

With an additional sub-central station (S-CS), a high-efficient full-duplex radio-over-fiber (RoF) system compatible with the wavelength-division-multiplexing technology is proposed and experimentally demonstrated in this paper. To improve the dispersion tolerance of the RoF system, the baseband data format for the downlink and an all-optical down-conversion approach for the uplink are employed. In addition, this RoF system can not only make full use of the fiber link resources but also realize the upstream transmission without any local light sources at remote base stations (BSs). A 10-GHz RoF experimental system with a 1.25-Gb/s rate bidirectional transmission is established based on the S-CS structure. The feasibility and reliability of this RoF system are verified through eye diagrams and bit error rate (BER) curves experimentally obtained.

Chip-to-Chip Half Duplex Spiking Data Communication over Power Supply Rails

NASA Astrophysics Data System (ADS)

Hashida, Takushi; Nagata, Makoto

Chip-to-chip serial data communication is superposed on power supply over common Vdd/Vss connections through chip, package, and board traces. A power line transceiver demonstrates half duplex spiking communication at more than 100Mbps. A pair of transceivers consumes 1.35mA from 3.3V, at 130Mbps. On-chip power line LC low pass filter attenuates pseudo-differential communication spikes by 30dB, purifying power supply current for internal circuits. Bi-directional spiking communication was successfully examined in a 90-nm CMOS prototype setup of on-chip waveform capturing. A micro controller forwards clock pulses to and receives data streams from a comparator based waveform capturer formed on a different chip, through a single pair of power and ground traces. The bit error rate is small enough not to degrade waveform acquisition capability, maintaining the spurious free dynamic range of higher than 50dB.

Bandwidth efficient bidirectional 5 Gb/s overlapped-SCM WDM PON with electronic equalization and forward-error correction.

PubMed

Buset, Jonathan M; El-Sahn, Ziad A; Plant, David V

2012-06-18

We demonstrate an improved overlapped-subcarrier multiplexed (O-SCM) WDM PON architecture transmitting over a single feeder using cost sensitive intensity modulation/direct detection transceivers, data re-modulation and simple electronics. Incorporating electronic equalization and Reed-Solomon forward-error correction codes helps to overcome the bandwidth limitation of a remotely seeded reflective semiconductor optical amplifier (RSOA)-based ONU transmitter. The O-SCM architecture yields greater spectral efficiency and higher bit rates than many other SCM techniques while maintaining resilience to upstream impairments. We demonstrate full-duplex 5 Gb/s transmission over 20 km and analyze BER performance as a function of transmitted and received power. The architecture provides flexibility to network operators by relaxing common design constraints and enabling full-duplex operation at BER ∼ 10(-10) over a wide range of OLT launch powers from 3.5 to 8 dBm.

A WDM-PON with DPSK modulated downstream and OOK modulated upstream signals based on symmetric 10 Gbit/s wavelength reused bidirectional reflective SOA

NASA Astrophysics Data System (ADS)

El-Nahal, Fady I.

2017-01-01

We investigate a wavelength-division-multiplexing passive optical network (WDM-PON) with centralized lightwave and direct detection. The system is demonstrated for symmetric 10 Gbit/s differential phase-shift keying (DPSK) downstream signals and on-off keying (OOK) upstream signals, respectively. A wavelength reused scheme is employed to carry the upstream data by using a reflective semiconductor optical amplifier (RSOA) as an intensity modulator at the optical network unit (ONU). The constant-intensity property of the DPSK modulation format can keep high extinction ratio ( ER) of downstream signal and reduce the crosstalk to the upstream signal. The bit error rate ( BER) performance of our scheme shows that the proposed 10 Gbit/s symmetric WDM-PON can achieve error free transmission over 25-km-long fiber transmission with low power penalty.

Transfer Entropy and Transient Limits of Computation

PubMed Central

Prokopenko, Mikhail; Lizier, Joseph T.

2014-01-01

Transfer entropy is a recently introduced information-theoretic measure quantifying directed statistical coherence between spatiotemporal processes, and is widely used in diverse fields ranging from finance to neuroscience. However, its relationships to fundamental limits of computation, such as Landauer's limit, remain unknown. Here we show that in order to increase transfer entropy (predictability) by one bit, heat flow must match or exceed Landauer's limit. Importantly, we generalise Landauer's limit to bi-directional information dynamics for non-equilibrium processes, revealing that the limit applies to prediction, in addition to retrodiction (information erasure). Furthermore, the results are related to negentropy, and to Bremermann's limit and the Bekenstein bound, producing, perhaps surprisingly, lower bounds on the computational deceleration and information loss incurred during an increase in predictability about the process. The identified relationships set new computational limits in terms of fundamental physical quantities, and establish transfer entropy as a central measure connecting information theory, thermodynamics and theory of computation. PMID:24953547

Fast collimated neutron flux measurement using stilbene scintillator and flashy analog-to-digital converter in JT-60U

NASA Astrophysics Data System (ADS)

Ishikawa, M.; Itoga, T.; Okuji, T.; Nakhostin, M.; Shinohara, K.; Hayashi, T.; Sukegawa, A.; Baba, M.; Nishitani, T.

2006-10-01

A line-integrated neutron emission profile is routinely measured using the radial neutron collimator system in JT-60U tokamak. Stilbene neuron detectors (SNDs), which combine a stilbene organic crystal scintillation detector (SD) with an analog neutron-gamma pulse shape discrimination (PSD) circuit, have been used to measure collimated neutron flux. Although the SND has many advantages as a neutron detector, the maximum count rate is limited up to ˜1×105counts/s due to the analog PSD circuit. To overcome this issue, a digital signal processing system (DSPS) using a flash analog-to-digital converter (Acqiris DC252, 8GHz, 10bits) has been developed at Cyclotron and Radioisotope Center in Tohoku University. In this system anode signals from photomultiplier of the SD are directory stored and digitized. Then, the PSD between neutrons and gamma rays is performed using software. The DSPS has been installed in the vertical neutron collimator system in JT-60U and applied to deuterium experiments. It is confirmed that the PSD is sufficiently performed and collimated neutron flux is successfully measured with count rate up to ˜5×105counts/s without the effect of pileup of detected pulses. The performance of the DSPS as a neutron detector, which supersedes the SND, is demonstrated.

Design specification of an acousto-optic spectrum analyzer that could be used as an auxiliary receiver for CANEWS

NASA Astrophysics Data System (ADS)

Studenny, John; Johnstone, Eric

1991-01-01

The acousto-optic spectrum analyzer has undergone a theoretical design review and a basic parameter tradeoff analysis has been performed. The main conclusion is that for the given scenario of a 55 dB dynamic range and for a one-second temporal resolution, a 3.9 MHz resolution is a reasonable compromise with respect to current technology. Additional configurations are suggested. Noise testing of the signal detection processor algorithm was conducted. Additive white Gaussian noise was introduced to pure data. As expected, the tradeoff was between algorithm sensitivity and false alarms. No additional algorithm improvements could be made. The algorithm was observed to be robust, provided that the noise floor was set at a proper level. The digitization scheme was mainly driven by hardware constraints. To implement an analog to digital conversion scheme that linearly covers a 55 dB dynamic range would require a minimum of 17 bits. The general consensus was that 17 bits would be untenable for very large scale integration.

Low Temperature Testing of a Radiation Hardened CMOS 8-Bit Flash Analog-to-Digital (A/D) Converter

NASA Technical Reports Server (NTRS)

Gerber, Scott S.; Hammond, Ahmad; Elbuluk, Malik E.; Patterson, Richard L.; Overton, Eric; Ghaffarian, Reza; Ramesham, Rajeshuni; Agarwal, Shri G.

2001-01-01

Power processing electronic systems, data acquiring probes, and signal conditioning circuits are required to operate reliably under harsh environments in many of NASA:s missions. The environment of the space mission as well as the operational requirements of some of the electronic systems, such as infrared-based satellite or telescopic observation stations where cryogenics are involved, dictate the utilization of electronics that can operate efficiently and reliably at low temperatures. In this work, radiation-hard CMOS 8-bit flash A/D converters were characterized in terms of voltage conversion and offset in the temperature range of +25 to -190 C. Static and dynamic supply currents, ladder resistance, and gain and offset errors were also obtained in the temperature range of +125 to -190 C. The effect of thermal cycling on these properties for a total of ten cycles between +80 and - 150 C was also determined. The experimental procedure along with the data obtained are reported and discussed in this paper.

A single-chip event sequencer and related microcontroller instrumentation for atomic physics research.

PubMed

Eyler, E E

2011-01-01

A 16-bit digital event sequencer with 50 ns resolution and 50 ns trigger jitter is implemented by using an internal 32-bit timer on a dsPIC30F4013 microcontroller, controlled by an easily modified program written in standard C. It can accommodate hundreds of output events, and adjacent events can be spaced as closely as 1.5 μs. The microcontroller has robust 5 V inputs and outputs, allowing a direct interface to common laboratory equipment and other electronics. A USB computer interface and a pair of analog ramp outputs can be added with just two additional chips. An optional display/keypad unit allows direct interaction with the sequencer without requiring an external computer. Minor additions also allow simple realizations of other complex instruments, including a precision high-voltage ramp generator for driving spectrum analyzers or piezoelectric positioners, and a low-cost proportional integral differential controller and lock-in amplifier for laser frequency stabilization with about 100 kHz bandwidth.

High-speed phosphor-LED wireless communication system utilizing no blue filter

NASA Astrophysics Data System (ADS)

Yeh, C. H.; Chow, C. W.; Chen, H. Y.; Chen, J.; Liu, Y. L.; Wu, Y. F.

2014-09-01

In this paper, we propose and investigate an adaptively 84.44 to 190 Mb/s phosphor-LED visible light communication (VLC) system at a practical transmission distance. Here, we utilize the orthogonal-frequency-division-multiplexing quadrature-amplitude-modulation (OFDM-QAM) modulation with power/bit-loading algorithm in proposed VLC system. In the experiment, the optimal analogy pre-equalization design is also performed at LED-Tx side and no blue filter is used at the Rx side for extending the modulation bandwidth from 1 MHz to 30 MHz. In addition, the corresponding free space transmission lengths are between 75 cm and 2 m under various data rates of proposed VLC. And the measured bit error rates (BERs) of < 3.8×10-3 [forward error correction (FEC) limit] at different transmission lengths and measured data rates can be also obtained. Finally, we believe that our proposed scheme could be another alternative VLC implementation in practical distance, supporting < 100 Mb/s, using commercially available LED and PD (without optical blue filtering) and compact size.

A Radiation Hardened by Design CMOS ASIC for Thermopile Readouts

NASA Technical Reports Server (NTRS)

Quilligan, G.; Aslam, S.; DuMonthier, J.

2012-01-01

A radiation hardened by design (RHBD) mixed-signal application specific integrated circuit (ASIC) has been designed for a thermopile readout for operation in the harsh Jovian orbital environment. The multi-channel digitizer (MCD) ASIC includes 18 low noise amplifier channels which have tunable gain/filtering coefficients, a 16-bit sigma-delta analog-digital converter (SDADC) and an on-chip controller. The 18 channels, SDADC and controller were designed to operate with immunity to single event latchup (SEL) and to at least 10 Mrad total ionizing dose (TID). The ASIC also contains a radiation tolerant 16-bit 20 MHz Nyquist ADC for general purpose instrumentation digitizer needs. The ASIC is currently undergoing fabrication in a commercial 180 nm CMOS process. Although this ASIC was designed specifically for the harsh radiation environment of the NASA led JEO mission it is suitable for integration into instrumentation payloads 011 the ESA JUICE mission where the radiation hardness requirements are slightly less stringent.

Cam-driven monochromator for QEXAFS

NASA Astrophysics Data System (ADS)

Caliebe, W. A.; So, I.; Lenhard, A.; Siddons, D. P.

2006-11-01

We have developed a cam-drive for quickly tuning the energy of an X-ray monochromator through an X-ray absorption edge for quick extended X-ray absorption spectroscopy (QEXAFS). The data are collected using a 4-channel, 12-bit multiplexed VME analog to digital converter and a VME angle encoder. The VME crate controller runs a real-time operating system. This system is capable of collecting 2 EXAFS-scans in 1 s with an energy stability of better than 1 eV. Additional improvements to increase the speed and the energy stability are under way.

Design and Implementation of Readout Circuit with Threshold Voltage Compensation on Glass Substrate for Touch Panel Applications

NASA Astrophysics Data System (ADS)

Lin, Yu-Ta; Ker, Ming-Dou; Wang, Tzu-Ming

2011-03-01

A new on-panel readout circuit with threshold voltage compensation for capacitive sensor in low temperature polycrystalline silicon (poly-Si) thin-film transistor (LTPS-TFT) process has been proposed. In order to compensate the threshold voltage variation from LTPS process variation, the proposed readout circuit applies a novel compensation approach with switch capacitor technique. In addition, a 4-bit analog-to-digital converter (ADC) is added to identify different sensed capacitor values and further enhances the overall resolution of touch panel.

Pulse Code Modulation (PCM) encoder handbook for Aydin Vector MMP-600 series system

NASA Technical Reports Server (NTRS)

Currier, S. F.; Powell, W. R.

1986-01-01

The hardware and software characteristics of a time division multiplex system are described. The system is used to sample analog and digital data. The data is merged with synchronization information to produce a serial pulse coded modulation (PCM) bit stream. Information presented herein is required by users to design compatible interfaces and assure effective utilization of this encoder system. GSFC/Wallops Flight Facility has flown approximately 50 of these systems through 1984 on sounding rockets with no inflight failures. Aydin Vector manufactures all of the components for these systems.

Using experience with bidirectional HL7-ACR-NEMA interfaces between the federal government HIS/RIS and commercial PACS to plan for DICOM

NASA Astrophysics Data System (ADS)

Kuzmak, Peter M.; Norton, Gary S.; Dayhoff, Ruth E.

1995-05-01

The Department of Veterans Affairs has developed a bidirectional HL7 - ACR-NEMA V 2.0 interface for connecting existing federal government hospital/radiology information systems (HIS/RIS) to commercial picture archive and communication systems (PACS). The interface has been in use since October 1993 at the Baltimore VAMC between the VA's HIS/RIS (DHCP) and a commercial PACS, and handles both text and image transfer. The text-only portion of the interface has been ported to work with a second vendor's PACS, and to work with the Department of Defense HIS/RIS (CHCS). Currently the interface is in production at two VA and three DoD sites. The common benefit experienced at all these sites is that passing patient, order, and report information directly from the HIS/RIS to the PACS greatly improves the flow of work in the Radiology Department. Image transfer to the DHCP Imaging System at the Baltimore VAMC demonstrated the advantage of providing `reference quality' (1K X 1K X 8-bit) radiology images to treating clinicians throughout the hospital. Experience has shown that the gateway must handle transactions between the HIS/RIS and the PACS quickly in order to keep up with the volume, and must provide an audit trail for system diagnostic purposes. Work is underway to construct a HL7 - DICOM gateway built upon the operational experience gathered from the existing interface.

A double-panel active segmented partition module using decoupled analog feedback controllers: numerical model.

PubMed

Sagers, Jason D; Leishman, Timothy W; Blotter, Jonathan D

2009-06-01

Low-frequency sound transmission has long plagued the sound isolation performance of lightweight partitions. Over the past 2 decades, researchers have investigated actively controlled structures to prevent sound transmission from a source space into a receiving space. An approach using active segmented partitions (ASPs) seeks to improve low-frequency sound isolation capabilities. An ASP is a partition which has been mechanically and acoustically segmented into a number of small individually controlled modules. This paper provides a theoretical and numerical development of a single ASP module configuration, wherein each panel of the double-panel structure is independently actuated and controlled by an analog feedback controller. A numerical model is developed to estimate frequency response functions for the purpose of controller design, to understand the effects of acoustic coupling between the panels, to predict the transmission loss of the module in both passive and active states, and to demonstrate that the proposed ASP module will produce bidirectional sound isolation.

Fast Offset Laser Phase-Locking System

NASA Technical Reports Server (NTRS)

Shaddock, Daniel; Ware, Brent

2008-01-01

Figure 1 shows a simplified block diagram of an improved optoelectronic system for locking the phase of one laser to that of another laser with an adjustable offset frequency specified by the user. In comparison with prior systems, this system exhibits higher performance (including higher stability) and is much easier to use. The system is based on a field-programmable gate array (FPGA) and operates almost entirely digitally; hence, it is easily adaptable to many different systems. The system achieves phase stability of less than a microcycle. It was developed to satisfy the phase-stability requirement for a planned spaceborne gravitational-wave-detecting heterodyne laser interferometer (LISA). The system has potential terrestrial utility in communications, lidar, and other applications. The present system includes a fast phasemeter that is a companion to the microcycle-accurate one described in High-Accuracy, High-Dynamic-Range Phase-Measurement System (NPO-41927), NASA Tech Briefs, Vol. 31, No. 6 (June 2007), page 22. In the present system (as in the previously reported one), beams from the two lasers (here denoted the master and slave lasers) interfere on a photodiode. The heterodyne photodiode output is digitized and fed to the fast phasemeter, which produces suitably conditioned, low-latency analog control signals which lock the phase of the slave laser to that of the master laser. These control signals are used to drive a thermal and a piezoelectric transducer that adjust the frequency and phase of the slave-laser output. The output of the photodiode is a heterodyne signal at the difference between the frequencies of the two lasers. (The difference is currently required to be less than 20 MHz due to the Nyquist limit of the current sampling rate. We foresee few problems in doubling this limit using current equipment.) Within the phasemeter, the photodiode-output signal is digitized to 15 bits at a sampling frequency of 40 MHz by use of the same analog-to-digital converter (ADC) as that of the previously reported phasemeter. The ADC output is passed to the FPGA, wherein the signal is demodulated using a digitally generated oscillator signal at the offset locking frequency specified by the user. The demodulated signal is low-pass filtered, decimated to a sample rate of 1 MHz, then filtered again. The decimated and filtered signal is converted to an analog output by a 1 MHz, 16-bit digital-to-analog converters. After a simple low-pass filter, these analog signals drive the thermal and piezoelectric transducers of the laser.

A digitalized silicon microgyroscope based on embedded FPGA.

PubMed

Xia, Dunzhu; Yu, Cheng; Wang, Yuliang

2012-09-27

This paper presents a novel digital miniaturization method for a prototype silicon micro-gyroscope (SMG) with the symmetrical and decoupled structure. The schematic blocks of the overall system consist of high precision analog front-end interface, high-speed 18-bit analog to digital convertor, a high-performance core Field Programmable Gate Array (FPGA) chip and other peripherals such as high-speed serial ports for transmitting data. In drive mode, the closed-loop drive circuit are implemented by automatic gain control (AGC) loop and software phase-locked loop (SPLL) based on the Coordinated Rotation Digital Computer (CORDIC) algorithm. Meanwhile, the sense demodulation module based on varying step least mean square demodulation (LMSD) are addressed in detail. All kinds of algorithms are simulated by Simulink and DSPbuilder tools, which is in good agreement with the theoretical design. The experimental results have fully demonstrated the stability and flexibility of the system.

A Digitalized Silicon Microgyroscope Based on Embedded FPGA

PubMed Central

Xia, Dunzhu; Yu, Cheng; Wang, Yuliang

2012-01-01

This paper presents a novel digital miniaturization method for a prototype silicon micro-gyroscope (SMG) with the symmetrical and decoupled structure. The schematic blocks of the overall system consist of high precision analog front-end interface, high-speed 18-bit analog to digital convertor, a high-performance core Field Programmable Gate Array (FPGA) chip and other peripherals such as high-speed serial ports for transmitting data. In drive mode, the closed-loop drive circuit are implemented by automatic gain control (AGC) loop and software phase-locked loop (SPLL) based on the Coordinated Rotation Digital Computer (CORDIC) algorithm. Meanwhile, the sense demodulation module based on varying step least mean square demodulation (LMSD) are addressed in detail. All kinds of algorithms are simulated by Simulink and DSPbuilder tools, which is in good agreement with the theoretical design. The experimental results have fully demonstrated the stability and flexibility of the system. PMID:23201990

Low-Actuation Voltage MEMS Digital-to-Analog Converter with Parylene Spring Structures

PubMed Central

Ma, Cheng-Wen; Lee, Fu-Wei; Liao, Hsin-Hung; Kuo, Wen-Cheng; Yang, Yao-Joe

2015-01-01

We propose an electrostatically-actuated microelectromechanical digital-to-analog converter (M-DAC) device with low actuation voltage. The spring structures of the silicon-based M-DAC device were monolithically fabricated using parylene-C. Because the Young’s modulus of parylene-C is considerably lower than that of silicon, the electrostatic microactuators in the proposed device require much lower actuation voltages. The actuation voltage of the proposed M-DAC device is approximately 6 V, which is less than one half of the actuation voltages of a previously reported M-DAC equipped with electrostatic microactuators. The measured total displacement of the proposed three-bit M-DAC is nearly 504 nm, and the motion step is approximately 72 nm. Furthermore, we demonstrated that the M-DAC can be employed as a mirror platform with discrete displacement output for a noncontact surface profiling system. PMID:26343682

Analog-to-digital conversion to accommodate the dynamics of live music in hearing instruments.

PubMed

Hockley, Neil S; Bahlmann, Frauke; Fulton, Bernadette

2012-09-01

Hearing instrument design focuses on the amplification of speech to reduce the negative effects of hearing loss. Many amateur and professional musicians, along with music enthusiasts, also require their hearing instruments to perform well when listening to the frequent, high amplitude peaks of live music. One limitation, in most current digital hearing instruments with 16-bit analog-to-digital (A/D) converters, is that the compressor before the A/D conversion is limited to 95 dB (SPL) or less at the input. This is more than adequate for the dynamic range of speech; however, this does not accommodate the amplitude peaks present in live music. The hearing instrument input compression system can be adjusted to accommodate for the amplitudes present in music that would otherwise be compressed before the A/D converter in the hearing instrument. The methodology behind this technological approach will be presented along with measurements to demonstrate its effectiveness.

A 10MHz Fiber-Coupled Photodiode Imaging Array for Plasma Diagnostics

NASA Astrophysics Data System (ADS)

Brockington, Samuel; Case, Andrew; Witherspoon, F. Douglas

2013-10-01

HyperV Technologies has been developing an imaging diagnostic comprised of arrays of fast, low-cost, long-record-length, fiber-optically-coupled photodiode channels to investigate plasma dynamics and other fast, bright events. By coupling an imaging fiber bundle to a bank of amplified photodiode channels, imagers and streak imagers of 100 to 10,000 pixels can be constructed. By interfacing analog photodiode systems directly to commercial analog to digital convertors and modern memory chips, a prototype pixel with an extremely deep record length (128 k points at 40 Msamples/s) has been achieved for a 10 bit resolution system with signal bandwidths of at least 10 MHz. Progress on a prototype 100 Pixel streak camera employing this technique is discussed along with preliminary experimental results and plans for a 10,000 pixel imager. Work supported by USDOE Phase 1 SBIR Grant DE-SC0009492.

Coherent detection and digital signal processing for fiber optic communications

NASA Astrophysics Data System (ADS)

Ip, Ezra

The drive towards higher spectral efficiency in optical fiber systems has generated renewed interest in coherent detection. We review different detection methods, including noncoherent, differentially coherent, and coherent detection, as well as hybrid detection methods. We compare the modulation methods that are enabled and their respective performances in a linear regime. An important system parameter is the number of degrees of freedom (DOF) utilized in transmission. Polarization-multiplexed quadrature-amplitude modulation maximizes spectral efficiency and power efficiency as it uses all four available DOF contained in the two field quadratures in the two polarizations. Dual-polarization homodyne or heterodyne downconversion are linear processes that can fully recover the received signal field in these four DOF. When downconverted signals are sampled at the Nyquist rate, compensation of transmission impairments can be performed using digital signal processing (DSP). Software based receivers benefit from the robustness of DSP, flexibility in design, and ease of adaptation to time-varying channels. Linear impairments, including chromatic dispersion (CD) and polarization-mode dispersion (PMD), can be compensated quasi-exactly using finite impulse response filters. In practical systems, sampling the received signal at 3/2 times the symbol rate is sufficient to enable an arbitrary amount of CD and PMD to be compensated for a sufficiently long equalizer whose tap length scales linearly with transmission distance. Depending on the transmitted constellation and the target bit error rate, the analog-to-digital converter (ADC) should have around 5 to 6 bits of resolution. Digital coherent receivers are naturally suited for the implementation of feedforward carrier recovery, which has superior linewidth tolerance than phase-locked loops, and does not suffer from feedback delay constraints. Differential bit encoding can be used to prevent catastrophic receiver failure due to cycle slips. In systems where nonlinear effects are concentrated mostly at fiber locations with small accumulated dispersion, nonlinear phase de-rotation is a low-complexity algorithm that can partially mitigate nonlinear effects. For systems with arbitrary dispersion maps, however, backpropagation is the only universal technique that can jointly compensate dispersion and fiber nonlinearity. Backpropagation requires solving the nonlinear Schrodinger equation at the receiver, and has high computational cost. Backpropagation is most effective when dispersion compensation fibers are removed, and when signal processing is performed at three times oversampling. Backpropagation can improve system performance and increase transmission distance. With anticipated advances in analog-to-digital converters and integrated circuit technology, DSP-based coherent receivers at bit rates up to 100 Gb/s should become practical in the near future.

The fenestrated Kawashima operation for single ventricle with interrupted inferior vena cava.

PubMed

Hannan, Robert L; Rossi, Anthony F; Nykanen, David G; Lopez, Leo; Alonso, Francisco; White, Jeffrey A; Burke, Redmond P

2003-01-01

An 8-month-old boy with double outlet right ventricle with hypoplastic left ventricle, heterotaxy, left atrial isomerism, bilateral superior vena cavae without bridging vein, and interruption of the inferior vena cava with azygous continuation to the left superior cava underwent a bilateral bidirectional cavopulmonary anastomosis. A calibrated 3-mm connection between the right pulmonary artery and the common atrium was constructed with the proximal right superior vena cava to allow right to left shunting, analogous to a fenestration in a Fontan operation. We hypothesize that in small young patients undergoing the Kawashima operation a fenestration may improve postoperative hemodynamics.

Noncontact Measurement Of Shaft Speed, Torque, And Power

NASA Technical Reports Server (NTRS)

Madzsar, George C.

1993-01-01

Noncontact fiber-optic sensor and associated electronic equipment measure twist and speed of rotation of shaft. Measurements determine torque and power. Response of sensor remains linear even at cryogenic temperatures. Reflective strips on rotating shaft reflect two series of light pulses back into optical system. Bidirectional coupler in each of two optical fiber paths separates reflected light from incident light, sending it to photodiode for output to analog-to-digital converter and computer. Sensor requires no slip rings or telemetry to transfer signals from shaft. Well suited for providing data on performances of turbopumps for such cryogenic fluids as liquid oxygen and liquid hydrogen.

Capacitor-Chain Successive-Approximation ADC

NASA Technical Reports Server (NTRS)

Cunningham, Thomas

2003-01-01

A proposed successive-approximation analog-to-digital converter (ADC) would contain a capacitively terminated chain of identical capacitor cells. Like a conventional successive-approximation ADC containing a bank of binary-scaled capacitors, the proposed ADC would store an input voltage on a sample-and-hold capacitor and would digitize the stored input voltage by finding the closest match between this voltage and a capacitively generated sum of binary fractions of a reference voltage (Vref). However, the proposed capacitor-chain ADC would offer two major advantages over a conventional binary-scaled-capacitor ADC: (1) In a conventional ADC that digitizes to n bits, the largest capacitor (representing the most significant bit) must have 2(exp n-1) times as much capacitance, and hence, approximately 2(exp n-1) times as much area as does the smallest capacitor (representing the least significant bit), so that the total capacitor area must be 2(exp n) times that of the smallest capacitor. In the proposed capacitor-chain ADC, there would be three capacitors per cell, each approximately equal to the smallest capacitor in the conventional ADC, and there would be one cell per bit. Therefore, the total capacitor area would be only about 3(exp n) times that of the smallest capacitor. The net result would be that the proposed ADC could be considerably smaller than the conventional ADC. (2) Because of edge effects, parasitic capacitances, and manufacturing tolerances, it is difficult to make capacitor banks in which the values of capacitance are scaled by powers of 2 to the required precision. In contrast, because all the capacitors in the proposed ADC would be identical, the problem of precise binary scaling would not arise.

Dry and noncontact EEG sensors for mobile brain-computer interfaces.

PubMed

Chi, Yu Mike; Wang, Yu-Te; Wang, Yijun; Maier, Christoph; Jung, Tzyy-Ping; Cauwenberghs, Gert

2012-03-01

Dry and noncontact electroencephalographic (EEG) electrodes, which do not require gel or even direct scalp coupling, have been considered as an enabler of practical, real-world, brain-computer interface (BCI) platforms. This study compares wet electrodes to dry and through hair, noncontact electrodes within a steady state visual evoked potential (SSVEP) BCI paradigm. The construction of a dry contact electrode, featuring fingered contact posts and active buffering circuitry is presented. Additionally, the development of a new, noncontact, capacitive electrode that utilizes a custom integrated, high-impedance analog front-end is introduced. Offline tests on 10 subjects characterize the signal quality from the different electrodes and demonstrate that acquisition of small amplitude, SSVEP signals is possible, even through hair using the new integrated noncontact sensor. Online BCI experiments demonstrate that the information transfer rate (ITR) with the dry electrodes is comparable to that of wet electrodes, completely without the need for gel or other conductive media. In addition, data from the noncontact electrode, operating on the top of hair, show a maximum ITR in excess of 19 bits/min at 100% accuracy (versus 29.2 bits/min for wet electrodes and 34.4 bits/min for dry electrodes), a level that has never been demonstrated before. The results of these experiments show that both dry and noncontact electrodes, with further development, may become a viable tool for both future mobile BCI and general EEG applications.

Demonstration of the CDMA-mode CAOS smart camera.

PubMed

Riza, Nabeel A; Mazhar, Mohsin A

2017-12-11

Demonstrated is the code division multiple access (CDMA)-mode coded access optical sensor (CAOS) smart camera suited for bright target scenarios. Deploying a silicon CMOS sensor and a silicon point detector within a digital micro-mirror device (DMD)-based spatially isolating hybrid camera design, this smart imager first engages the DMD starring mode with a controlled factor of 200 high optical attenuation of the scene irradiance to provide a classic unsaturated CMOS sensor-based image for target intelligence gathering. Next, this CMOS sensor provided image data is used to acquire a focused zone more robust un-attenuated true target image using the time-modulated CDMA-mode of the CAOS camera. Using four different bright light test target scenes, successfully demonstrated is a proof-of-concept visible band CAOS smart camera operating in the CDMA-mode using up-to 4096 bits length Walsh design CAOS pixel codes with a maximum 10 KHz code bit rate giving a 0.4096 seconds CAOS frame acquisition time. A 16-bit analog-to-digital converter (ADC) with time domain correlation digital signal processing (DSP) generates the CDMA-mode images with a 3600 CAOS pixel count and a best spatial resolution of one micro-mirror square pixel size of 13.68 μm side. The CDMA-mode of the CAOS smart camera is suited for applications where robust high dynamic range (DR) imaging is needed for un-attenuated un-spoiled bright light spectrally diverse targets.

High Rate Digital Demodulator ASIC

NASA Technical Reports Server (NTRS)

Ghuman, Parminder; Sheikh, Salman; Koubek, Steve; Hoy, Scott; Gray, Andrew

1998-01-01

The architecture of High Rate (600 Mega-bits per second) Digital Demodulator (HRDD) ASIC capable of demodulating BPSK and QPSK modulated data is presented in this paper. The advantages of all-digital processing include increased flexibility and reliability with reduced reproduction costs. Conventional serial digital processing would require high processing rates necessitating a hardware implementation in other than CMOS technology such as Gallium Arsenide (GaAs) which has high cost and power requirements. It is more desirable to use CMOS technology with its lower power requirements and higher gate density. However, digital demodulation of high data rates in CMOS requires parallel algorithms to process the sampled data at a rate lower than the data rate. The parallel processing algorithms described here were developed jointly by NASA's Goddard Space Flight Center (GSFC) and the Jet Propulsion Laboratory (JPL). The resulting all-digital receiver has the capability to demodulate BPSK, QPSK, OQPSK, and DQPSK at data rates in excess of 300 Mega-bits per second (Mbps) per channel. This paper will provide an overview of the parallel architecture and features of the HRDR ASIC. In addition, this paper will provide an over-view of the implementation of the hardware architectures used to create flexibility over conventional high rate analog or hybrid receivers. This flexibility includes a wide range of data rates, modulation schemes, and operating environments. In conclusion it will be shown how this high rate digital demodulator can be used with an off-the-shelf A/D and a flexible analog front end, both of which are numerically computer controlled, to produce a very flexible, low cost high rate digital receiver.

Noise-Enhanced Measurement of Weak Doublet Spectra with a Fourier-Transform Spectrometer and a 1-Bit Analog-to-Digital Converter.

PubMed

Lim, M; Saloma, C

2001-04-10

We demonstrate an efficient noise dithering procedure for measuring the power spectrum of a weak spectral doublet with a Fourier-transform spectrometer in which the subthreshold interferogram is measured by a 1-bit analog-to-digital converter without oversampling. In the absence of noise, no information is obtained regarding the doublet spectrum because the modulation term s(x) of its interferogram is below the instrumental detection limit B, i.e., |s(x)| < B, for all path difference x values. Extensive numerical experiments are carried out concerning the recovery of the doublet power spectrum that is represented by s(x) = (s(0)/2)exp(-pi(2)x(2)/beta)[cos(2pif(1)x) + cos(2pif(2)x)], where s(0) is a constant, beta is the linewidth factor, and ?f? = (f(1) + f(2))/2. Different values of ?f?, s(0), and beta are considered to evaluate thoroughly the accuracy of the procedure to determine the unknown values of f(1) and f(2), the spectral linewidth, and the peak values of the spectral profiles. Our experiments show that, even for short observation times, the resonant frequencies of s(x) could be located with high accuracy over a wide range of ?f? and beta values. Signal-to-noise ratios as high as 50 are also gained for the recovered power spectra. The performance of the procedure is also analyzed with respect to another method that recovers the amplitude values of s(x) directly.

Digital receiver study and implementation

NASA Technical Reports Server (NTRS)

Fogle, D. A.; Lee, G. M.; Massey, J. C.

1972-01-01

Computer software was developed which makes it possible to use any general purpose computer with A/D conversion capability as a PSK receiver for low data rate telemetry processing. Carrier tracking, bit synchronization, and matched filter detection are all performed digitally. To aid in the implementation of optimum computer processors, a study of general digital processing techniques was performed which emphasized various techniques for digitizing general analog systems. In particular, the phase-locked loop was extensively analyzed as a typical non-linear communication element. Bayesian estimation techniques for PSK demodulation were studied. A hardware implementation of the digital Costas loop was developed.

Design and Analysis of Reconfigurable Analog System

DTIC Science & Technology

2011-02-01

the number of the bits of the sub-ADC, the range of V is smaller than the full-scale input range by a factor of -L. If it is desired that Vin and Vst ...Transistor M1, M9, and M8 are off. Transistor M3 turns on which turns on transistor M7. As a result Vst is connected to V2. Since V2 was charged to Vdd when...Vutb), it disconnects the other output voltage ( Vst ) from the lower transistors (M2). A regenerative action helps both V0st and Vtb to reach their final

Sensor Authentication: Embedded Processor Code

DOE Office of Scientific and Technical Information (OSTI.GOV)

Svoboda, John

2012-09-25

Described is the c code running on the embedded Microchip 32bit PIC32MX575F256H located on the INL developed noise analysis circuit board. The code performs the following functions: Controls the noise analysis circuit board preamplifier voltage gains of 1, 10, 100, 000 Initializes the analog to digital conversion hardware, input channel selection, Fast Fourier Transform (FFT) function, USB communications interface, and internal memory allocations Initiates high resolution 4096 point 200 kHz data acquisition Computes complex 2048 point FFT and FFT magnitude. Services Host command set Transfers raw data to Host Transfers FFT result to host Communication error checking

Negative base encoding in optical linear algebra processors

NASA Technical Reports Server (NTRS)

Perlee, C.; Casasent, D.

1986-01-01

In the digital multiplication by analog convolution algorithm, the bits of two encoded numbers are convolved to form the product of the two numbers in mixed binary representation; this output can be easily converted to binary. Attention is presently given to negative base encoding, treating base -2 initially, and then showing that the negative base system can be readily extended to any radix. In general, negative base encoding in optical linear algebra processors represents a more efficient technique than either sign magnitude or 2's complement encoding, when the additions of digitally encoded products are performed in parallel.

Mosad and Stream Vision For A Telerobotic, Flying Camera System

NASA Technical Reports Server (NTRS)

Mandl, William

2002-01-01

Two full custom camera systems using the Multiplexed OverSample Analog to Digital (MOSAD) conversion technology for visible light sensing were built and demonstrated. They include a photo gate sensor and a photo diode sensor. The system includes the camera assembly, driver interface assembly, a frame stabler board with integrated decimeter and Windows 2000 compatible software for real time image display. An array size of 320X240 with 16 micron pixel pitch was developed for compatibility with 0.3 inch CCTV optics. With 1.2 micron technology, a 73% fill factor was achieved. Noise measurements indicated 9 to 11 bits operating with 13.7 bits best case. Power measured under 10 milliwatts at 400 samples per second. Nonuniformity variation was below noise floor. Pictures were taken with different cameras during the characterization study to demonstrate the operable range. The successful conclusion of this program demonstrates the utility of the MOSAD for NASA missions, providing superior performance over CMOS and lower cost and power consumption over CCD. The MOSAD approach also provides a path to radiation hardening for space based applications.

Fully integrated low-noise readout circuit with automatic offset cancellation loop for capacitive microsensors.

PubMed

Song, Haryong; Park, Yunjong; Kim, Hyungseup; Cho, Dong-Il Dan; Ko, Hyoungho

2015-10-14

Capacitive sensing schemes are widely used for various microsensors; however, such microsensors suffer from severe parasitic capacitance problems. This paper presents a fully integrated low-noise readout circuit with automatic offset cancellation loop (AOCL) for capacitive microsensors. The output offsets of the capacitive sensing chain due to the parasitic capacitances and process variations are automatically removed using AOCL. The AOCL generates electrically equivalent offset capacitance and enables charge-domain fine calibration using a 10-bit R-2R digital-to-analog converter, charge-transfer switches, and a charge-storing capacitor. The AOCL cancels the unwanted offset by binary-search algorithm based on 10-bit successive approximation register (SAR) logic. The chip is implemented using 0.18 μm complementary metal-oxide-semiconductor (CMOS) process with an active area of 1.76 mm². The power consumption is 220 μW with 3.3 V supply. The input parasitic capacitances within the range of -250 fF to 250 fF can be cancelled out automatically, and the required calibration time is lower than 10 ms.

Fully Integrated Low-Noise Readout Circuit with Automatic Offset Cancellation Loop for Capacitive Microsensors

PubMed Central

Song, Haryong; Park, Yunjong; Kim, Hyungseup; Cho, Dong-il Dan; Ko, Hyoungho

2015-01-01

Capacitive sensing schemes are widely used for various microsensors; however, such microsensors suffer from severe parasitic capacitance problems. This paper presents a fully integrated low-noise readout circuit with automatic offset cancellation loop (AOCL) for capacitive microsensors. The output offsets of the capacitive sensing chain due to the parasitic capacitances and process variations are automatically removed using AOCL. The AOCL generates electrically equivalent offset capacitance and enables charge-domain fine calibration using a 10-bit R-2R digital-to-analog converter, charge-transfer switches, and a charge-storing capacitor. The AOCL cancels the unwanted offset by binary-search algorithm based on 10-bit successive approximation register (SAR) logic. The chip is implemented using 0.18 μm complementary metal-oxide-semiconductor (CMOS) process with an active area of 1.76 mm2. The power consumption is 220 μW with 3.3 V supply. The input parasitic capacitances within the range of −250 fF to 250 fF can be cancelled out automatically, and the required calibration time is lower than 10 ms. PMID:26473877

Remote Semi-State Preparation as SuperDense Quantum Teleportation

NASA Astrophysics Data System (ADS)

Bernstein, Herbert J.

2011-03-01

Recent advances in experimental technique make SuperDense Teleportation (SDT) possible. The effect uses remote state preparation to send more state-specifying parameters per bit than ordinary quantum teleportation (QT) can transmit. SDT uses a maximal entanglement to teleport the relative phases of an {n}-dimensional equimodular state. This means that one can send only {n}-1 of the total (2 n - 2) parameters -- comprising the relative phases and amplitudes -- of a general state. Nevertheless, for {n} >= 3 , SDT sends more of these state-specifying parameters than QT for a given number of classical bits. In the limit of large {n} the ratio is 2 to 1, hence the nomenclature Bennett suggested, SDT, by analogy with Super Dense Coding. Alice's measurements and Bob's transformations are simpler than in QT. The roles of Charles the state chooser, and Diana who deploys it, are different than in QT. I briefly review possible experimental realizations, including two that are under consideration at the present time by an experimental group leading in higher-dimension entanglement work. Supported in part by NSF grants PHY97-22614 & 07-58149 & KITP, UCSB, including an ITP Scholar-ship.

ATCA digital controller hardware for vertical stabilization of plasmas in tokamaks

DOE Office of Scientific and Technical Information (OSTI.GOV)

Batista, A. J. N.; Sousa, J.; Varandas, C. A. F.

2006-10-15

The efficient vertical stabilization (VS) of plasmas in tokamaks requires a fast reaction of the VS controller, for example, after detection of edge localized modes (ELM). For controlling the effects of very large ELMs a new digital control hardware, based on the Advanced Telecommunications Computing Architecture trade mark sign (ATCA), is being developed aiming to reduce the VS digital control loop cycle (down to an optimal value of 10 {mu}s) and improve the algorithm performance. The system has 1 ATCA trade mark sign processor module and up to 12 ATCA trade mark sign control modules, each one with 32 analogmore » input channels (12 bit resolution), 4 analog output channels (12 bit resolution), and 8 digital input/output channels. The Aurora trade mark sign and PCI Express trade mark sign communication protocols will be used for data transport, between modules, with expected latencies below 2 {mu}s. Control algorithms are implemented on a ix86 based processor with 6 Gflops and on field programmable gate arrays with 80 GMACS, interconnected by serial gigabit links in a full mesh topology.« less

Room temperature 1040fps, 1 megapixel photon-counting image sensor with 1.1um pixel pitch

NASA Astrophysics Data System (ADS)

Masoodian, S.; Ma, J.; Starkey, D.; Wang, T. J.; Yamashita, Y.; Fossum, E. R.

2017-05-01

A 1Mjot single-bit quanta image sensor (QIS) implemented in a stacked backside-illuminated (BSI) process is presented. This is the first work to report a megapixel photon-counting CMOS-type image sensor to the best of our knowledge. A QIS with 1.1μm pitch tapered-pump-gate jots is implemented with cluster-parallel readout, where each cluster of jots is associated with its own dedicated readout electronics stacked under the cluster. Power dissipation is reduced with this cluster readout because of the reduced column bus parasitic capacitance, which is important for the development of 1Gjot arrays. The QIS functions at 1040fps with binary readout and dissipates only 17.6mW, including I/O pads. The readout signal chain uses a fully differential charge-transfer amplifier (CTA) gain stage before a 1b-ADC to achieve an energy/bit FOM of 16.1pJ/b and 6.9pJ/b for the whole sensor and gain stage+ADC, respectively. Analog outputs with on-chip gain are implemented for pixel characterization purposes.

Nonlinearity-aware 200  Gbit/s DMT transmission for C-band short-reach optical interconnects with a single packaged electro-absorption modulated laser.

PubMed

Zhang, Lu; Hong, Xuezhi; Pang, Xiaodan; Ozolins, Oskars; Udalcovs, Aleksejs; Schatz, Richard; Guo, Changjian; Zhang, Junwei; Nordwall, Fredrik; Engenhardt, Klaus M; Westergren, Urban; Popov, Sergei; Jacobsen, Gunnar; Xiao, Shilin; Hu, Weisheng; Chen, Jiajia

2018-01-15

We experimentally demonstrate the transmission of a 200 Gbit/s discrete multitone (DMT) at the soft forward error correction limit in an intensity-modulation direct-detection system with a single C-band packaged distributed feedback laser and traveling-wave electro absorption modulator (DFB-TWEAM), digital-to-analog converter and photodiode. The bit-power loaded DMT signal is transmitted over 1.6 km standard single-mode fiber with a net rate of 166.7 Gbit/s, achieving an effective electrical spectrum efficiency of 4.93 bit/s/Hz. Meanwhile, net rates of 174.2 Gbit/s and 179.5 Gbit/s are also demonstrated over 0.8 km SSMF and in an optical back-to-back case, respectively. The feature of the packaged DFB-TWEAM is presented. The nonlinearity-aware digital signal processing algorithm for channel equalization is mathematically described, which improves the signal-to-noise ratio up to 3.5 dB.

Probe-controlled soliton frequency shift in the regime of optical event horizon.

PubMed

Gu, Jie; Guo, Hairun; Wang, Shaofei; Zeng, Xianglong

2015-08-24

In optical analogy of the event horizon, temporal pulse collision and mutual interactions are mainly between an intense solitary wave (soliton) and a dispersive probe wave. In such a regime, here we numerically investigate the probe-controlled soliton frequency shift as well as the soliton self-compression. In particular, in the dispersion landscape with multiple zero dispersion wavelengths, bi-directional soliton spectral tunneling effects is possible. Moreover, we propose a mid-infrared soliton self-compression to the generation of few-cycle ultrashort pulses, in a bulk of quadratic nonlinear crystals in contrast to optical fibers or cubic nonlinear media, which could contribute to the community with a simple and flexible method to experimental implementations.

New Ground-based Spectral Observations of Mercury and Comparison with the Moon

NASA Technical Reports Server (NTRS)

Blewett, D. T.; Warell, J.

2003-01-01

Spectroscopic observations (400-670 nm) of Mercury were made at La Palma with the Nordic Optical Telescope (NOT) in June and July of 2002. Extensive observations of solar analog standard stars and validation spectra of 7 Iris and a variety of locations on the Moon were also collected. The 2002 Mercury data were also combined with previous observations (520-970 nm) from the Swedish Solar Vacuum Telescope (SVST). A spectrum (400-970 nm) calibrated to standard bidirectional geometry (alpha=i=30deg, e=0deg) was constructed based on the spectral slopes from 2002. The combined spectrum permits analysis with the Lucey lunar abundance relations for FeO and TiO2.

A novel wavelength reused bidirectional RoF-WDM-PON architecture to mitigate reflection and Rayleigh backscattered noise in multi-Gb/s m-QAM OFDM SSB upstream and downstream transmission over a single fiber

NASA Astrophysics Data System (ADS)

Patel, Dhananjay; Dalal, U. D.

2017-05-01

A novel m-QAM Orthogonal Frequency Division Multiplexing (OFDM) Single Sideband (SSB) architecture is proposed for centralized light source (CLS) bidirectional Radio over Fiber (RoF) - Wavelength Division Multiplexing (WDM) - Passive Optical Network (PON). In bidirectional transmission with carrier reuse over the single fiber, the Rayleigh Backscattering (RB) noise and reflection (RE) interferences from optical components can seriously deteriorate the transmission performance of the fiber optic systems. These interferometric noises can be mitigated by utilizing the optical modulation schemes at the Optical Line Terminal (OLT) and Optical Network Unit (ONU) such that the spectral overlap between the optical data spectrum and the RB and RE noise is minimum. A mathematical model is developed for the proposed architecture to accurately measure the performance of the transmission system and also to analyze the effect of interferometric noise caused by the RB and RE. The model takes into the account the different modulation schemes employed at the OLT and the ONU using a Mach Zehnder Modulator (MZM), the optical launch power and the bit-rates of the downstream and upstream signals, the gain of the amplifiers at the OLT and the ONU, the RB-RE noise, chromatic dispersion of the single mode fiber and optical filter responses. In addition, the model analyzes all the components of the RB-RE noise such as carrier RB, signal RB, carrier RE and signal RE, thus providing the complete representation of all the physical phenomena involved. An optical m-QAM OFDM SSB signal acts as a test signal to validate the model which provides excellent agreement with simulation results. The SSB modulation technique using the MZM at the OLT and the ONU differs in the data transmission technique that takes place through the first-order higher and the lower optical sideband respectively. This spectral gap between the downstream and upstream signals reduces the effect of Rayleigh backscattering and discrete reflections.

High-definition video display based on the FPGA and THS8200

NASA Astrophysics Data System (ADS)

Qian, Jia; Sui, Xiubao

2014-11-01

This paper presents a high-definition video display solution based on the FPGA and THS8200. THS8200 is a video decoder chip launched by TI company, this chip has three 10-bit DAC channels which can capture video data in both 4:2:2 and 4:4:4 formats, and its data synchronization can be either through the dedicated synchronization signals HSYNC and VSYNC, or extracted from the embedded video stream synchronization information SAV / EAV code. In this paper, we will utilize the address and control signals generated by FPGA to access to the data-storage array, and then the FPGA generates the corresponding digital video signals YCbCr. These signals combined with the synchronization signals HSYNC and VSYNC that are also generated by the FPGA act as the input signals of THS8200. In order to meet the bandwidth requirements of the high-definition TV, we adopt video input in the 4:2:2 format over 2×10-bit interface. THS8200 is needed to be controlled by FPGA with I2C bus to set the internal registers, and as a result, it can generate the synchronous signal that is satisfied with the standard SMPTE and transfer the digital video signals YCbCr into analog video signals YPbPr. Hence, the composite analog output signals YPbPr are consist of image data signal and synchronous signal which are superimposed together inside the chip THS8200. The experimental research indicates that the method presented in this paper is a viable solution for high-definition video display, which conforms to the input requirements of the new high-definition display devices.

Deep Cryogenic Low Power 24 Bits Analog to Digital Converter with Active Reverse Cryostat

NASA Astrophysics Data System (ADS)

Turqueti, Marcos; Prestemon, Soren; Albright, Robert

LBNL is developing an innovative data acquisition module for superconductive magnets where the front-end electronics and digitizer resides inside the cryostat. This electronic package allows conventional electronic technologies such as enhanced metal-oxide-semiconductor to work inside cryostats at temperatures as low as 4.2 K. This is achieved by careful management of heat inside the module that keeps the electronic envelop at approximately 85 K. This approach avoids all the difficulties that arise from changes in carrier mobility that occur in semiconductors at deep cryogenic temperatures. There are several advantages in utilizing this system. A significant reduction in electrical noise from signals captured inside the cryostat occurs due to the low temperature that the electronics is immersed in, reducing the thermal noise. The shorter distance that signals are transmitted before digitalization reduces pickup and cross-talk between channels. This improved performance in signal-to-noise rate by itself is a significant advantage. Another important advantage is the simplification of the feedthrough interface on the cryostat head. Data coming out of the cryostat is digital and serial, dramatically reducing the number of lines going through the cryostat feedthrough interface. It is important to notice that all lines coming out of the cryostat are digital and low voltage, reducing the possibility of electric breakdown inside the cryostat. This paper will explain in details the architecture and inner workings of this data acquisition system. It will also provide the performance of the analog to digital converter when the system is immersed in liquid helium, and in liquid nitrogen. Parameters such as power dissipation, integral non-linearity, effective number of bits, signal-to-noise and distortion, will be presented for both temperatures.

A high-efficiency real-time digital signal averager for time-of-flight mass spectrometry.

PubMed

Wang, Yinan; Xu, Hui; Li, Qingjiang; Li, Nan; Huang, Zhengxu; Zhou, Zhen; Liu, Husheng; Sun, Zhaolin; Xu, Xin; Yu, Hongqi; Liu, Haijun; Li, David D-U; Wang, Xi; Dong, Xiuzhen; Gao, Wei

2013-05-30

Analog-to-digital converter (ADC)-based acquisition systems are widely applied in time-of-flight mass spectrometers (TOFMS) due to their ability to record the signal intensity of all ions within the same pulse. However, the acquisition system raises the requirement for data throughput, along with increasing the conversion rate and resolution of the ADC. It is therefore of considerable interest to develop a high-performance real-time acquisition system, which can relieve the limitation of data throughput. We present in this work a high-efficiency real-time digital signal averager, consisting of a signal conditioner, a data conversion module and a signal processing module. Two optimization strategies are implemented using field programmable gate arrays (FPGAs) to enhance the efficiency of the real-time processing. A pipeline procedure is used to reduce the time consumption of the accumulation strategy. To realize continuous data transfer, a high-efficiency transmission strategy is developed, based on a ping-pong procedure. The digital signal averager features good responsiveness, analog bandwidth and dynamic performance. The optimal effective number of bits reaches 6.7 bits. For a 32 µs record length, the averager can realize 100% efficiency with an extraction frequency below 31.23 kHz by modifying the number of accumulation steps. In unit time, the averager yields superior signal-to-noise ratio (SNR) compared with data accumulation in a computer. The digital signal averager is combined with a vacuum ultraviolet single-photon ionization time-of-flight mass spectrometer (VUV-SPI-TOFMS). The efficiency of the real-time processing is tested by analyzing the volatile organic compounds (VOCs) from ordinary printed materials. In these experiments, 22 kinds of compounds are detected, and the dynamic range exceeds 3 orders of magnitude. Copyright © 2013 John Wiley & Sons, Ltd.

Deep Cryogenic Low Power 24 Bits Analog to Digital Converter with Active Reverse Cryostat

DOE PAGES

Turqueti, Marcos; Prestemon, Soren; Albright, Robert

2015-07-15

LBNL is developing an innovative data acquisition module for superconductive magnets where the front-end electronics and digitizer resides inside the cryostat. This electronic package allows conventional electronic technologies such as enhanced metal–oxide–semiconductor to work inside cryostats at temperatures as low as 4.2 K. This is achieved by careful management of heat inside the module that keeps the electronic envelop at approximately 85 K. This approach avoids all the difficulties that arise from changes in carrier mobility that occur in semiconductors at deep cryogenic temperatures. There are several advantages in utilizing this system. A significant reduction in electrical noise from signalsmore » captured inside the cryostat occurs due to the low temperature that the electronics is immersed in, reducing the thermal noise. The shorter distance that signals are transmitted before digitalization reduces pickup and cross-talk between channels. This improved performance in signal-to-noise rate by itself is a significant advantage. Another important advantage is the simplification of the feedthrough interface on the cryostat head. Data coming out of the cryostat is digital and serial, dramatically reducing the number of lines going through the cryostat feedthrough interface. It is important to notice that all lines coming out of the cryostat are digital and low voltage, reducing the possibility of electric breakdown inside the cryostat. This paper will explain in details the architecture and inner workings of this data acquisition system. It will also provide the performance of the analog to digital converter when the system is immersed in liquid helium, and in liquid nitrogen. Parameters such as power dissipation, integral non-linearity, effective number of bits, signal-to-noise and distortion, will be presented for both temperatures.« less

Design of a CMOS readout circuit on ultra-thin flexible silicon chip for printed strain gauges

NASA Astrophysics Data System (ADS)

Elsobky, Mourad; Mahsereci, Yigit; Keck, Jürgen; Richter, Harald; Burghartz, Joachim N.

2017-09-01

Flexible electronics represents an emerging technology with features enabling several new applications such as wearable electronics and bendable displays. Precise and high-performance sensors readout chips are crucial for high quality flexible electronic products. In this work, the design of a CMOS readout circuit for an array of printed strain gauges is presented. The ultra-thin readout chip and the printed sensors are combined on a thin Benzocyclobutene/Polyimide (BCB/PI) substrate to form a Hybrid System-in-Foil (HySiF), which is used as an electronic skin for robotic applications. Each strain gauge utilizes a Wheatstone bridge circuit, where four Aerosol Jet® printed meander-shaped resistors form a full-bridge topology. The readout chip amplifies the output voltage difference (about 5 mV full-scale swing) of the strain gauge. One challenge during the sensor interface circuit design is to compensate for the relatively large dc offset (about 30 mV at 1 mA) in the bridge output voltage so that the amplified signal span matches the input range of an analog-to-digital converter (ADC). The circuit design uses the 0. 5 µm mixed-signal GATEFORESTTM technology. In order to achieve the mechanical flexibility, the chip fabrication is based on either back thinned wafers or the ChipFilmTM technology, which enables the manufacturing of silicon chips with a thickness of about 20 µm. The implemented readout chip uses a supply of 5 V and includes a 5-bit digital-to-analog converter (DAC), a differential difference amplifier (DDA), and a 10-bit successive approximation register (SAR) ADC. The circuit is simulated across process, supply and temperature corners and the simulation results indicate excellent performance in terms of circuit stability and linearity.

Performance Comparison of 112-Gb/s DMT, Nyquist PAM4, and Partial-Response PAM4 for Future 5G Ethernet-Based Fronthaul Architecture

NASA Astrophysics Data System (ADS)

Eiselt, Nicklas; Muench, Daniel; Dochhan, Annika; Griesser, Helmut; Eiselt, Michael; Olmos, Juan Jose Vegas; Monroy, Idelfonso Tafur; Elbers, Joerg-Peter

2018-05-01

For a future 5G Ethernet-based fronthaul architecture, 100G trunk lines of a transmission distance up to 10 km standard single mode fiber (SSMF) in combination with cheap grey optics to daisy chain cell site network interfaces are a promising cost- and power-efficient solution. For such a scenario, different intensity modulation and direct detect (IMDD) Formats at a data rate of 112 Gb/s, namely Nyquist four-level pulse amplitude modulation (PAM4), discrete multi-tone Transmission (DMT) and partial-response (PR) PAM4 are experimentally investigated, using a low-cost electro-absorption modulated laser (EML), a 25G driver and current state-of-the-art high Speed 84 GS/s CMOS digital-to-analog converter (DAC) and analog-to-digital converter (ADC) test chips. Each modulation Format is optimized independently for the desired scenario and their digital signal processing (DSP) requirements are investigated. The performance of Nyquist PAM4 and PR PAM4 depend very much on the efficiency of pre- and post-equalization. We show the necessity for at least 11 FFE-taps for pre-emphasis and up to 41 FFE coefficients at the receiver side. In addition, PR PAM4 requires an MLSE with four states to decode the signal back to a PAM4 signal. On the contrary, bit- and power-loading (BL, PL) is crucial for DMT and an FFT length of at least 512 is necessary. With optimized parameters, all Modulation formats result in a very similar performances, demonstrating a transmission distance of up to 10 km over SSMF with bit error rates (BERs) below a FEC threshold of 4.4E-3, allowing error free transmission.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hart, Darren M.

Sandia National Laboratories has tested and evaluated Geotech Smart24 data acquisition system with active Fortezza crypto card data signing and authentication. The test results included in this report were in response to static and tonal-dynamic input signals. Most test methodologies used were based on IEEE Standards 1057 for Digitizing Waveform Recorders and 1241 for Analog to Digital Converters; others were designed by Sandia specifically for infrasound application evaluation and for supplementary criteria not addressed in the IEEE standards. The objective of this work was to evaluate the overall technical performance of the Geotech Smart24 digitizer with a Fortezza PCMCIA cryptomore » card actively implementing the signing of data packets. The results of this evaluation were compared to relevant specifications provided within manufacturer's documentation notes. The tests performed were chosen to demonstrate different performance aspects of the digitizer under test. The performance aspects tested include determining noise floor, least significant bit (LSB), dynamic range, cross-talk, relative channel-to-channel timing, time-tag accuracy, analog bandwidth and calibrator performance.« less

Noise reduction and control in mode-locked semiconductor diode lasers for use in next-generation all-optical analog-to-digital converters

NASA Astrophysics Data System (ADS)

DePriest, Christopher M.; Abeles, Joseph H.; Braun, Alan; Delfyett, Peter J., Jr.

2000-07-01

External-cavity, actively-modelocked semiconductor diode lasers (SDLs) have proven to be attractive candidates for forming the backbone of next-generation analog-to-digital converters (ADCs), which are currently being developed to sample signals at repetition rates exceeding several GHz with up to 12 bits of digital resolution. Modelocked SDLs are capable of producing waveform-sampling pulse trains with very low temporal jitter (phase noise) and very small fluctuations in pulse height (amplitude noise)--two basic conditions that must be met in order for high-speed ADCs to achieve projected design goals. Single-wavelength modelocked operation (at nominal repetition frequencies of 400 MHz) has produced pulse trains with very low amplitude noise (approximately 0.08%), and the implementation of a phase- locked-loop has been effective in reducing the system's low- frequency phase noise (RMS timing jitter for offset frequencies between 10 Hz and 10 kHz has been reduced from 240 fs to 27 fs).

Analog-to-Digital Conversion to Accommodate the Dynamics of Live Music in Hearing Instruments

PubMed Central

Bahlmann, Frauke; Fulton, Bernadette

2012-01-01

Hearing instrument design focuses on the amplification of speech to reduce the negative effects of hearing loss. Many amateur and professional musicians, along with music enthusiasts, also require their hearing instruments to perform well when listening to the frequent, high amplitude peaks of live music. One limitation, in most current digital hearing instruments with 16-bit analog-to-digital (A/D) converters, is that the compressor before the A/D conversion is limited to 95 dB (SPL) or less at the input. This is more than adequate for the dynamic range of speech; however, this does not accommodate the amplitude peaks present in live music. The hearing instrument input compression system can be adjusted to accommodate for the amplitudes present in music that would otherwise be compressed before the A/D converter in the hearing instrument. The methodology behind this technological approach will be presented along with measurements to demonstrate its effectiveness. PMID:23258618

An integrated multichannel neural recording analog front-end ASIC with area-efficient driven right leg circuit.

PubMed

Tao Tang; Wang Ling Goh; Lei Yao; Jia Hao Cheong; Yuan Gao

2017-07-01

This paper describes an integrated multichannel neural recording analog front end (AFE) with a novel area-efficient driven right leg (DRL) circuit to improve the system common mode rejection ratio (CMRR). The proposed AFE consists of an AC-coupled low-noise programmable-gain amplifier, an area-efficient DRL block and a 10-bit SAR ADC. Compared to conventional DRL circuit, the proposed capacitor-less DRL design achieves 90% chip area reduction with enhanced CMRR performance, making it ideal for multichannel biomedical recording applications. The AFE circuit has been designed in a standard 0.18-μm CMOS process. Post-layout simulation results show that the AFE provides two gain settings of 54dB/60dB while consuming 1 μA per channel under a supply voltage of 1 V. The input-referred noise of the AFE integrated from 1 Hz to 10k Hz is only 4 μVrms and the CMRR is 110 dB.

Analog front-end design of the STS/MUCH-XYTER2—full size prototype ASIC for the CBM experiment

NASA Astrophysics Data System (ADS)

Kleczek, Rafal

2017-01-01

The design of the analog front-end of the STS/MUCH-XYTER2 ASIC, a full-size prototype chip for the Silicon Tracking System (STS, based on double-sided silicon strip sensors) and Muon Chamber (MUCH, based on gas sensors) detectors is presented. The ASIC contains 128 charge processing channels, each built of a charge sensitive amplifier, a polarity selection circuit and two pulse shaping amplifiers forming two parallel signal paths. The first path is used for timing measurement with a fast discriminator. The second path allows low-noise amplitude measurement with a 5-bit continuous-time flash ADC. Different operating conditions and constraints posed by two target detectors' applications require front-end electronics flexibility to meet extended system-wise requirements. The presented circuit implements switchable shaper peaking time, gain switching and trimming, input amplifier pulsed reset circuit, fail-safe measures. The power consumption is scalable (for the STS and the MUCH modes), but limited to 10 mW/channel.

Digital signal processing the Tevatron BPM signals

DOE Office of Scientific and Technical Information (OSTI.GOV)

Cancelo, G.; James, E.; Wolbers, S.

2005-05-01

The Beam Position Monitor (TeV BPM) readout system at Fermilab's Tevatron has been updated and is currently being commissioned. The new BPMs use new analog and digital hardware to achieve better beam position measurement resolution. The new system reads signals from both ends of the existing directional stripline pickups to provide simultaneous proton and antiproton measurements. The signals provided by the two ends of the BPM pickups are processed by analog band-pass filters and sampled by 14-bit ADCs at 74.3MHz. A crucial part of this work has been the design of digital filters that process the signal. This paper describesmore » the digital processing and estimation techniques used to optimize the beam position measurement. The BPM electronics must operate in narrow-band and wide-band modes to enable measurements of closed-orbit and turn-by-turn positions. The filtering and timing conditions of the signals are tuned accordingly for the operational modes. The analysis and the optimized result for each mode are presented.« less

A CMOS Imager with Focal Plane Compression using Predictive Coding

NASA Technical Reports Server (NTRS)

Leon-Salas, Walter D.; Balkir, Sina; Sayood, Khalid; Schemm, Nathan; Hoffman, Michael W.

2007-01-01

This paper presents a CMOS image sensor with focal-plane compression. The design has a column-level architecture and it is based on predictive coding techniques for image decorrelation. The prediction operations are performed in the analog domain to avoid quantization noise and to decrease the area complexity of the circuit, The prediction residuals are quantized and encoded by a joint quantizer/coder circuit. To save area resources, the joint quantizerlcoder circuit exploits common circuitry between a single-slope analog-to-digital converter (ADC) and a Golomb-Rice entropy coder. This combination of ADC and encoder allows the integration of the entropy coder at the column level. A prototype chip was fabricated in a 0.35 pm CMOS process. The output of the chip is a compressed bit stream. The test chip occupies a silicon area of 2.60 mm x 5.96 mm which includes an 80 X 44 APS array. Tests of the fabricated chip demonstrate the validity of the design.

Neutron/ γ-ray digital pulse shape discrimination with organic scintillators

NASA Astrophysics Data System (ADS)

Kaschuck, Y.; Esposito, B.

2005-10-01

Neutrons and γ-rays produce light pulses with different shapes when interacting with organic scintillators. This property is commonly used to distinguish between neutrons (n) and γ-rays ( γ) in mixed n/ γ fields as those encountered in radiation physics experiments. Although analog electronic pulse shape discrimination (PSD) modules have been successfully used for many years, they do not allow data reprocessing and are limited in count rate capability (typically up to 200 kHz). The performance of a n/ γ digital pulse shape discrimination (DPSD) system by means of a commercial 12-bit 200 MSamples/s transient recorder card is investigated here. Three organic scintillators have been studied: stilbene, NE213 and anthracene. The charge comparison method has been used to obtain simultaneous n/ γ discrimination and pulse height analysis. The importance of DPSD for high-intensity radiation field measurements and its advantages with respect to analog PSD are discussed. Based on post-experiment simulations with acquired data, the requirements for fast digitizers to provide DPSD with organic scintillators are also analyzed.

Bidirectional optical subassembly-shaped 20-Gbit/s compact single-mode four-channel wavelength-division multiplexing optical modules for optical multimedia interfaces

NASA Astrophysics Data System (ADS)

Lim, Kwon-Seob; Yu, Hong-Yeon; Park, Hyoung-Jun; Kang, Hyun Seo; Jang, Jae-Hyung

2016-06-01

Low-cost single-mode four-channel optical transmitter and receiver modules using the wavelength-division multiplexing (WDM) method have been developed for long-reach fiber optic applications. The single-mode four-channel WDM optical transmitter and receiver modules consist of two dual-wavelength optical transmitter and receiver submodules, respectively. The integration of two channels in a glass-sealed transistor outline-can package is an effective way to reduce cost and size and to extend the number of channels. The clear eye diagrams with more than about 6 dB of the extinction ratio and the minimum receiver sensitivity of lower than -16 dBm at a bit error rate of 10-12 have been obtained for the transmitter and receiver modules, respectively, at 5 Gbps/channel. The 4K ultrahigh definition contents have been transmitted over a 1-km-long single-mode fiber using a pair of proposed four-channel transmitter optical subassembly and receiver optical subassembly.

Simultaneous DPSK demodulation and chirp management using delay interferometer in symmetric 40-Gb/s capability TWDM-PON system.

PubMed

Bi, Meihua; Xiao, Shilin; He, Hao; Yi, Lilin; Li, Zhengxuan; Li, Jun; Yang, Xuelin; Hu, Weisheng

2013-07-15

We propose a symmetric 40-Gb/s aggregate rate time and wavelength division multiplexed passive optical network (TWDM-PON) system with the capability of simultaneous downstream differential phase shift keying (DPSK) signal demodulation and upstream signal chirp management based on delay interferometer (DI). With the bi-pass characteristic of DI, we experimentally demonstrate the bidirectional transmission of signals at 10-Gb/s per wavelength, and achieve negligible power penalties after 50-km single mode fiber (SMF). For the uplink transmission with DI, a ~11-dB optical power budget improvement at a bit error ratio of 1e-3 is obtained and the extinction ratio (ER) of signal is also improved from 3.4 dB to 13.75 dB. Owing to this high ER, the upstream burst-mode transmitting is successfully presented in term of time-division multiplexing. Moreover, in our experiment, a ~38-dB power budget is obtained to support 256 users with 50-km SMF transmission.

Upgrade of an optical network unit in a 40 Gb/s time and wavelength-division multiplexed passive optical network using an upstream tunable colorless laser

NASA Astrophysics Data System (ADS)

Bindhaiq, Salem; Supa'at, Abu Sahmah M.; Zulkifli, Nadiatulhuda; Shaddad, Redhwan Q.; Mataria, Abdallah

2014-07-01

A high data transmission rate is the main requirement for next-generation telecommunication networks. A design for a 40 Gb/s time and wavelength-division multiplexed passive optical network (TWDM-PON) for next-generation passive optical network stage 2 is presented. The use of a modulated grating Y-branch (MG-Y) laser is proposed as an upstream tunable colorless laser source to upgrade the optical network unit. The electronically tuned MG-Y externally modulated laser with a 10 Gb/s modulation rate is applied to a TWDM-PON and presented across a 3.2-nm tuning range. The performance of the proposed laser is analyzed in terms of bit error rate, eye diagram, and optical signal-to-noise ratio. The proposed TWDM-PON achieved an aggregated data rate of 40 Gb/s along 40 km of bidirectional fiber at a 1:128 splitting ratio without amplification and dispersion compensation.

A small step in VLC systems - a big step in Li-Fi implementation

NASA Astrophysics Data System (ADS)

Rîurean, S. M.; Nagy, A. A.; Leba, M.; Ionica, A. C.

2018-01-01

Light is part of our sustainable environmental life so, using it would be the handiest and cheapest way for wireless communication. Since ever, light has been used to send messages in different ways and now, due to the high technological improvements, bits through light, at high speed on multiple paths, allow humans to communicate. Using the lighting system both for illumination and communication represents lately one of the worldwide main research issues with several implementations with real benefits. This paper presents a viable VLC system, that proves its sustainability for sending by light information not only few millimetres but meters away. This system has multiple potential applications in different areas where other communication systems are bottlenecked, too expensive, unavailable or even forbidden. Since a Li-Fi fully developed system requires bidirectional, multiple access communication, there are still some challenges towards a functional Li-Fi wireless network. Although important steps have been made, Li-Fi is still under experimental stage.

Experimental multiplexing of quantum key distribution with classical optical communication

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Liu-Jun; Chen, Luo-Kan; Ju, Lei

2015-02-23

We demonstrate the realization of quantum key distribution (QKD) when combined with classical optical communication, and synchronous signals within a single optical fiber. In the experiment, the classical communication sources use Fabry-Pérot (FP) lasers, which are implemented extensively in optical access networks. To perform QKD, multistage band-stop filtering techniques are developed, and a wavelength-division multiplexing scheme is designed for the multi-longitudinal-mode FP lasers. We have managed to maintain sufficient isolation among the quantum channel, the synchronous channel and the classical channels to guarantee good QKD performance. Finally, the quantum bit error rate remains below a level of 2% across themore » entire practical application range. The proposed multiplexing scheme can ensure low classical light loss, and enables QKD over fiber lengths of up to 45 km simultaneously when the fibers are populated with bidirectional FP laser communications. Our demonstration paves the way for application of QKD to current optical access networks, where FP lasers are widely used by the end users.« less

Designing of a small wearable conformal phased array antenna for wireless communications

NASA Astrophysics Data System (ADS)

Roy, Sayan

In this thesis, a unique design of a self-adapting conformal phased-array antenna system for wireless communications is presented. The antenna system is comprised of one microstrip antenna array and a sensor circuit. A 1x4 printed microstrip patch antenna array was designed on a flexible substrate with a resonant frequency of 2.47 GHz. However, the performance of the antenna starts to degrade as the curvature of the surface of the substrate changes. To recover the performance of the system, a flexible sensor circuitry was designed. This sensor circuitry uses analog phase shifters, a flexible resistor and operational-amplifier circuitry to compensate the phase of each array element of the antenna. The proposed analytical method for phase compensation has been first verified by designing an RF test platform consisting of a microstrip antenna array, commercially available analog phase shifters, analog voltage attenuators, 4-port power dividers and amplifiers. The platform can be operated through a LabVIEW GUI interface using a 12-bit digital-to-analog converter. This test board was used to design and calibrate the sensor circuitry by observing the behavior of the antenna array system on surfaces with different curvatures. In particular, this phased array antenna system was designed to be used on the surface of a spacesuit or any other flexible prototype. This work was supported in part by the Defense Miroelectronics Activity (DMEA), NASA ND EPSCoR and DARPA/MTO.

MEMS analog light processing: an enabling technology for adaptive optical phase control

NASA Astrophysics Data System (ADS)

Gehner, Andreas; Wildenhain, Michael; Neumann, Hannes; Knobbe, Jens; Komenda, Ondrej

2006-01-01

Various applications in modern optics are demanding for Spatial Light Modulators (SLM) with a true analog light processing capability, e.g. the generation of arbitrary analog phase patterns for an adaptive optical phase control. For that purpose the Fraunhofer IPMS has developed a high-resolution MEMS Micro Mirror Array (MMA) with an integrated active-matrix CMOS address circuitry. The device provides 240 x 200 piston-type mirror elements with 40 μm pixel size, where each of them can be addressed and deflected independently at an 8bit height resolution with a vertical analog deflection range of up to 400 nm suitable for a 2pi phase modulation in the visible. Full user programmability and control is provided by a newly developed comfortable driver software for Windows XP based PCs supporting both a Graphical User Interface (GUI) for stand-alone operation with pre-defined data patterns as well as an open ActiveX programming interface for a direct data feed-through within a closed-loop environment. High-speed data communication is established by an IEEE1394a FireWire interface together with an electronic driving board performing the actual MMA programming and control at a maximum frame rate of up to 500 Hz. Successful application demonstrations have been given in eye aberration correction, coupling efficiency optimization into a monomode fiber, ultra-short laser pulse modulation and diffractive beam shaping. Besides a presentation of the basic device concept the paper will give an overview of the obtained results from these applications.

Laser doppler blood flow imaging using a CMOS imaging sensor with on-chip signal processing.

PubMed

He, Diwei; Nguyen, Hoang C; Hayes-Gill, Barrie R; Zhu, Yiqun; Crowe, John A; Gill, Cally; Clough, Geraldine F; Morgan, Stephen P

2013-09-18

The first fully integrated 2D CMOS imaging sensor with on-chip signal processing for applications in laser Doppler blood flow (LDBF) imaging has been designed and tested. To obtain a space efficient design over 64 × 64 pixels means that standard processing electronics used off-chip cannot be implemented. Therefore the analog signal processing at each pixel is a tailored design for LDBF signals with balanced optimization for signal-to-noise ratio and silicon area. This custom made sensor offers key advantages over conventional sensors, viz. the analog signal processing at the pixel level carries out signal normalization; the AC amplification in combination with an anti-aliasing filter allows analog-to-digital conversion with a low number of bits; low resource implementation of the digital processor enables on-chip processing and the data bottleneck that exists between the detector and processing electronics has been overcome. The sensor demonstrates good agreement with simulation at each design stage. The measured optical performance of the sensor is demonstrated using modulated light signals and in vivo blood flow experiments. Images showing blood flow changes with arterial occlusion and an inflammatory response to a histamine skin-prick demonstrate that the sensor array is capable of detecting blood flow signals from tissue.

Design and status of the RF-digitizer integrated circuit

NASA Technical Reports Server (NTRS)

Rayhrer, B.; Lam, B.; Young, L. E.; Srinivasan, J. M.; Thomas, J. B.

1991-01-01

An integrated circuit currently under development samples a bandpass-limited signal at a radio frequency in quadrature and then performs a simple sum-and-dump operation in order to filter and lower the rate of the samples. Downconversion to baseband is carried out by the sampling step itself through the aliasing effect of an appropriately selected subharmonic sampling frequency. Two complete RF digitizer circuits with these functions will be implemented with analog and digital elements on one GaAs substrate. An input signal, with a carrier frequency as high as 8 GHz, can be sampled at a rate as high as 600 Msamples/sec for each quadrature component. The initial version of the chip will sign-sample (1-bit) the input RF signal. The chip will contain a synthesizer to generate a sample frequency that is a selectable integer multiple of an input reference frequency. In addition to the usual advantages of compactness and reliability associated with integrated circuits, the single chip will replace several steps required by standard analog downconversion. Furthermore, when a very high initial sample rate is selected, the presampling analog filters can be given very large bandwidths, thereby greatly reducing phase and delay instabilities typically introduced by such filters, as well as phase and delay variation due to Doppler changes.

Improved performance of analog and digital acousto-optic modulation with feedback under profiled beam propagation for secure communication using chaos

NASA Astrophysics Data System (ADS)

Almehmadi, Fares S.; Chatterjee, Monish R.

2014-12-01

Using intensity feedback, the closed-loop behavior of an acousto-optic hybrid device under profiled beam propagation has been recently shown to exhibit wider chaotic bands potentially leading to an increase in both the dynamic range and sensitivity to key parameters that characterize the encryption. In this work, a detailed examination is carried out vis-à-vis the robustness of the encryption/decryption process relative to parameter mismatch for both analog and pulse code modulation signals, and bit error rate (BER) curves are used to examine the impact of additive white noise. The simulations with profiled input beams are shown to produce a stronger encryption key (i.e., much lower parametric tolerance thresholds) relative to simulations with uniform plane wave input beams. In each case, it is shown that the tolerance for key parameters drops by factors ranging from 10 to 20 times below those for uniform plane wave propagation. Results are shown to be at consistently lower tolerances for secure transmission of analog and digital signals using parameter tolerance measures, as well as BER performance measures for digital signals. These results hold out the promise for considerably greater information transmission security for such a system.

Low-power low-noise mixed-mode VLSI ASIC for infinite dynamic range imaging applications

NASA Astrophysics Data System (ADS)

Turchetta, Renato; Hu, Y.; Zinzius, Y.; Colledani, C.; Loge, A.

1998-11-01

Solid state solutions for imaging are mainly represented by CCDs and, more recently, by CMOS imagers. Both devices are based on the integration of the total charge generated by the impinging radiation, with no processing of the single photon information. The dynamic range of these devices is intrinsically limited by the finite value of noise. Here we present the design of an architecture which allows efficient, in-pixel, noise reduction to a practically zero level, thus allowing infinite dynamic range imaging. A detailed calculation of the dynamic range is worked out, showing that noise is efficiently suppressed. This architecture is based on the concept of single-photon counting. In each pixel, we integrate both the front-end, low-noise, low-power analog part and the digital part. The former consists of a charge preamplifier, an active filter for optimal noise bandwidth reduction, a buffer and a threshold comparator, and the latter is simply a counter, which can be programmed to act as a normal shift register for the readout of the counters' contents. Two different ASIC's based on this concept have been designed for different applications. The first one has been optimized for silicon edge-on microstrips detectors, used in a digital mammography R and D project. It is a 32-channel circuit, with a 16-bit binary static counter.It has been optimized for a relatively large detector capacitance of 5 pF. Noise has been measured to be equal to 100 + 7*Cd (pF) electron rms with the digital part, showing no degradation of the noise performances with respect to the design values. The power consumption is 3.8mW/channel for a peaking time of about 1 microsecond(s) . The second circuit is a prototype for pixel imaging. The total active area is about (250 micrometers )**2. The main differences of the electronic architecture with respect to the first prototype are: i) different optimization of the analog front-end part for low-capacitance detectors, ii) in- pixel 4-bit comparator-offset compensation, iii) 15-bit pseudo-random counter. The power consumption is 255 (mu) W/channel for a peaking time of 300 ns and an equivalent noise charge of 185 + 97*Cd electrons rms. Simulation and experimental result as well as imaging results will be presented.

Design and Test of a 65nm CMOS Front-End with Zero Dead Time for Next Generation Pixel Detectors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gaioni, L.; Braga, D.; Christian, D.

This work is concerned with the experimental characterization of a synchronous analog processor with zero dead time developed in a 65 nm CMOS technology, conceived for pixel detectors at the HL-LHC experiment upgrades. It includes a low noise, fast charge sensitive amplifier with detector leakage compensation circuit, and a compact, single ended comparator able to correctly process hits belonging to two consecutive bunch crossing periods. A 2-bit Flash ADC is exploited for digital conversion immediately after the preamplifier. A description of the circuits integrated in the front-end processor and the initial characterization results are provided

Design of a digital voice data compression technique for orbiter voice channels

NASA Technical Reports Server (NTRS)

1975-01-01

Candidate techniques were investigated for digital voice compression to a transmission rate of 8 kbps. Good voice quality, speaker recognition, and robustness in the presence of error bursts were considered. The technique of delayed-decision adaptive predictive coding is described and compared with conventional adaptive predictive coding. Results include a set of experimental simulations recorded on analog tape. The two FM broadcast segments produced show the delayed-decision technique to be virtually undegraded or minimally degraded at .001 and .01 Viterbi decoder bit error rates. Preliminary estimates of the hardware complexity of this technique indicate potential for implementation in space shuttle orbiters.

Wideband pulse amplifiers for the NECTAr chip

NASA Astrophysics Data System (ADS)

Sanuy, A.; Delagnes, E.; Gascon, D.; Sieiro, X.; Bolmont, J.; Corona, P.; Feinstein, F.; Glicenstein, J.-F.; Naumann, C. L.; Nayman, P.; Ribó, M.; Tavernet, J.-P.; Toussenel, F.; Vincent, P.; Vorobiov, S.

2012-12-01

The NECTAr collaboration's FE option for the camera of the CTA is a 16 bits and 1-3 GS/s sampling chip based on analog memories including most of the readout functions. This works describes the input amplifiers of the NECTAr ASIC. A fully differential wideband amplifier, with voltage gain up to 20 V/V and a BW of 400 MHz. As it is impossible to design a fully differential OpAmp with an 8 GHz GBW product in a 0.35 CMOS technology, an alternative implementation based on HF linearized transconductors is explored. The output buffer is a class AB miller operational amplifier, with special non-linear current boost.

Beam test results of the BTeV silicon pixel detector

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gabriele Chiodini et al.

2000-09-28

The authors have described the results of the BTeV silicon pixel detector beam test. The pixel detectors under test used samples of the first two generations of Fermilab pixel readout chips, FPIX0 and FPIX1, (indium bump-bonded to ATLAS sensor prototypes). The spatial resolution achieved using analog charge information is excellent for a large range of track inclination. The resolution is still very good using only 2-bit charge information. A relatively small dependence of the resolution on bias voltage is observed. The resolution is observed to depend dramatically on the discriminator threshold, and it deteriorates rapidly for threshold above 4000e{sup {minus}}.

High speed fault tolerant secure communication for muon chamber using FPGA based GBTx emulator

NASA Astrophysics Data System (ADS)

Sau, Suman; Mandal, Swagata; Saini, Jogender; Chakrabarti, Amlan; Chattopadhyay, Subhasis

2015-12-01

The Compressed Baryonic Matter (CBM) experiment is a part of the Facility for Antiproton and Ion Research (FAIR) in Darmstadt at the GSI. The CBM experiment will investigate the highly compressed nuclear matter using nucleus-nucleus collisions. This experiment will examine lieavy-ion collisions in fixed target geometry and will be able to measure hadrons, electrons and muons. CBM requires precise time synchronization, compact hardware, radiation tolerance, self-triggered front-end electronics, efficient data aggregation schemes and capability to handle high data rate (up to several TB/s). As a part of the implementation of read out chain of Muon Cliamber(MUCH) [1] in India, we have tried to implement FPGA based emulator of GBTx in India. GBTx is a radiation tolerant ASIC that can be used to implement multipurpose high speed bidirectional optical links for high-energy physics (HEP) experiments and is developed by CERN. GBTx will be used in highly irradiated area and more prone to be affected by multi bit error. To mitigate this effect instead of single bit error correcting RS code we have used two bit error correcting (15, 7) BCH code. It will increase the redundancy which in turn increases the reliability of the coded data. So the coded data will be less prone to be affected by noise due to radiation. The data will go from detector to PC through multiple nodes through the communication channel. The computing resources are connected to a network which can be accessed by authorized person to prevent unauthorized data access which might happen by compromising the network security. Thus data encryption is essential. In order to make the data communication secure, advanced encryption standard [2] (AES - a symmetric key cryptography) and RSA [3], [4] (asymmetric key cryptography) are used after the channel coding. We have implemented GBTx emulator on two Xilinx Kintex-7 boards (KC705). One will act as transmitter and other will act as receiver and they are connected through optical fiber through small form-factor pluggable (SFP) port. We have tested the setup in the runtime environment using Xilinx Cliipscope Pro Analyzer. We also measure the resource utilization, throughput., power optimization of implemented design.

A pulsated weak-resonant-cavity laser diode with transient wavelength scanning and tracking for injection-locked RZ transmission.

PubMed

Lin, Gong-Ru; Chi, Yu-Chieh; Liao, Yu-Sheng; Kuo, Hao-Chung; Liao, Zhi-Wang; Wang, Hai-Lin; Lin, Gong-Cheng

2012-06-18

By spectrally slicing a single longitudinal-mode from a master weak-resonant-cavity Fabry-Perot laser diode with transient wavelength scanning and tracking functions, the broadened self-injection-locking of a slave weak-resonant-cavity Fabry-Perot laser diode is demonstrated to achieve bi-directional transmission in a 200-GHz array-waveguide-grating channelized dense-wavelength-division-multiplexing passive optical network system. Both the down- and up-stream slave weak-resonant-cavity Fabry-Perot laser diodes are non-return-to-zero modulated below threshold and coherently injection-locked to deliver the pulsed carrier for 25-km bi-directional 2.5 Gbits/s return-to-zero transmission. The master weak-resonant-cavity Fabry-Perot laser diode is gain-switched at near threshold condition and delivers an optical coherent pulse-train with its mode linewidth broadened from 0.2 to 0.8 nm by transient wavelength scanning, which facilitates the broadband injection-locking of the slave weak-resonant-cavity Fabry-Perot laser diodes with a threshold current reducing by 10 mA. Such a transient wavelength scanning induced spectral broadening greatly releases the limitation on wavelength injection-locking range required for the slave weak-resonant-cavity Fabry-Perot laser diode. The theoretical modeling and numerical simulation on the wavelength scanning and tracking effects of the master and slave weak-resonant-cavity Fabry-Perot laser diodes are performed. The receiving power sensitivity for back-to-back transmission at bit-error-rate <10(-10) is -25.6 dBm, and the power penalty added after 25-km transmission is less than 2 dB for all 16 channels.

A CMOS frontend chip for implantable neural recording with wide voltage supply range

NASA Astrophysics Data System (ADS)

Jialin, Liu; Xu, Zhang; Xiaohui, Hu; Yatao, Guo; Peng, Li; Ming, Liu; Bin, Li; Hongda, Chen

2015-10-01

A design for a CMOS frontend integrated circuit (chip) for neural signal acquisition working at wide voltage supply range is presented in this paper. The chip consists of a preamplifier, a serial instrumental amplifier (IA) and a cyclic analog-to-digital converter (CADC). The capacitive-coupled and capacitive-feedback topology combined with MOS-bipolar pseudo-resistor element is adopted in the preamplifier to create a -3 dB upper cut-off frequency less than 1 Hz without using a ponderous discrete device. A dual-amplifier instrumental amplifier is used to provide a low output impedance interface for ADC as well as to boost the gain. The preamplifier and the serial instrumental amplifier together provide a midband gain of 45.8 dB and have an input-referred noise of 6.7 μVrms integrated from 1 Hz to 5 kHz. The ADC digitizes the amplified signal at 12-bits precision with a highest sampling rate of 130 kS/s. The measured effective number of bits (ENOB) of the ADC is 8.7 bits. The entire circuit draws 165 to 216 μA current from the supply voltage varied from 1.34 to 3.3 V. The prototype chip is fabricated in the 0.18-μm CMOS process and occupies an area of 1.23 mm2 (including pads). In-vitro recording was successfully carried out by the proposed frontend chip. Project supported by the National Natural Science Foundation of China (Nos. 61474107, 61372060, 61335010, 61275200, 61178051) and the Key Program of the Chinese Academy of Sciences (No. KJZD-EW-L11-01).

An Intelligent Sensor Array Distributed System for Vibration Analysis and Acoustic Noise Characterization of a Linear Switched Reluctance Actuator

PubMed Central

Salvado, José; Espírito-Santo, António; Calado, Maria

2012-01-01

This paper proposes a distributed system for analysis and monitoring (DSAM) of vibrations and acoustic noise, which consists of an array of intelligent modules, sensor modules, communication bus and a host PC acting as data center. The main advantages of the DSAM are its modularity, scalability, and flexibility for use of different type of sensors/transducers, with analog or digital outputs, and for signals of different nature. Its final cost is also significantly lower than other available commercial solutions. The system is reconfigurable, can operate either with synchronous or asynchronous modes, with programmable sampling frequencies, 8-bit or 12-bit resolution and a memory buffer of 15 kbyte. It allows real-time data-acquisition for signals of different nature, in applications that require a large number of sensors, thus it is suited for monitoring of vibrations in Linear Switched Reluctance Actuators (LSRAs). The acquired data allows the full characterization of the LSRA in terms of its response to vibrations of structural origins, and the vibrations and acoustic noise emitted under normal operation. The DSAM can also be used for electrical machine condition monitoring, machine fault diagnosis, structural characterization and monitoring, among other applications. PMID:22969364

A simple encoding method for Sigma-Delta ADC based biopotential acquisition systems.

PubMed

Guerrero, Federico N; Spinelli, Enrique M

2017-10-01

Sigma Delta analogue-to-digital converters allow acquiring the full dynamic range of biomedical signals at the electrodes, resulting in less complex hardware and increased measurement robustness. However, the increased data size per sample (typically 24 bits) demands the transmission of extremely large volumes of data across the isolation barrier, thus increasing power consumption on the patient side. This problem is accentuated when a large number of channels is used as in current 128-256 electrodes biopotential acquisition systems, that usually opt for an optic fibre link to the computer. An analogous problem occurs for simpler low-power acquisition platforms that transmit data through a wireless link to a computing platform. In this paper, a low-complexity encoding method is presented to decrease sample data size without losses, while preserving the full DC-coupled signal. The method achieved a 2.3 average compression ratio evaluated over an ECG and EMG signal bank acquired with equipment based on Sigma-Delta converters. It demands a very low processing load: a C language implementation is presented that resulted in an 110 clock cycles average execution on an 8-bit microcontroller.

Low frequency noise elimination technique for 24-bit Σ-Δ data acquisition systems.

PubMed

Qu, Shao-Bo; Robert, Olivier; Lognonné, Philippe; Zhou, Ze-Bing; Yang, Shan-Qing

2015-03-01

Low frequency 1/f noise is one of the key limiting factors of high precision measurement instruments. In this paper, digital correlated double sampling is implemented to reduce the offset and low frequency 1/f noise of a data acquisition system with 24-bit sigma delta (Σ-Δ) analog to digital converter (ADC). The input voltage is modulated by cross-coupled switches, which are synchronized to the sampling clock, and converted into digital signal by ADC. By using a proper switch frequency, the unwanted parasitic signal frequencies generated by the switches are avoided. The noise elimination processing is made through the principle of digital correlated double sampling, which is equivalent to a time shifted subtraction for the sampled voltage. The low frequency 1/f noise spectrum density of the data acquisition system is reduced to be flat down to the measurement frequency lower limit, which is about 0.0001 Hz in this paper. The noise spectrum density is eliminated by more than 60 dB at 0.0001 Hz, with a residual noise floor of (9 ± 2) nV/Hz(1/2) which is limited by the intrinsic white noise floor of the ADC above its corner frequency.

A 10 GS/s time-interleaved ADC in 0.25 micrometer CMOS technology

NASA Astrophysics Data System (ADS)

Aytar, Oktay; Tangel, Ali; Afacan, Engin

2017-11-01

This paper presents design and simulation of a 4-bit 10 GS/s time interleaved ADC in 0.25 micrometer CMOS technology. The designed TI-ADC has 4 channels including 4-bit flash ADC in each channel, in which area and power efficiency are targeted. Therefore, basic standard cell logic gates are preferred. Meanwhile, the aspect ratios in the gate designs are kept as small as possible considering the speed performance. In the literature, design details of the timing control circuits have not been provided, whereas the proposed timing control process is comprehensively explained and design details of the proposed timing control process are clearly presented in this study. The proposed circuits producing consecutive pulses for timing control of the input S/H switches (ie the analog demultiplexer front-end circuitry) and the very fast digital multiplexer unit at the output are the main contributions of this study. The simulation results include +0.26/-0.22 LSB of DNL and +0.01/-0.44 LSB of INL, layout area of 0.27 mm2, and power consumption of 270 mW. The provided power consumption, DNL and INL measures are observed at 100 MHz input with 10 GS/s sampling rate.

On phaser-based processing of impulse radio UWB over fiber systems employing SOA

NASA Astrophysics Data System (ADS)

Taki, H.; Azou, S.; Hamie, A.; Al Housseini, A.; Alaeddine, A.; Sharaiha, A.

2017-07-01

In this study, we adopt a phaser-based processing to enhance the performance of impulse radio over fiber system utilizing SOA. The amplifier has been placed at a distance in the optical link, so as to extend the coverage area of proposed transceiver. Operating in the linear or saturation region for SOA, adds ASE noise or strong nonlinearities acting on the propagated pulses, respectively. Both lead to a degradation in the power efficiency and bit error rate performance. By applying up and down analog chirping technique, we have reduced the ASE power and nonlinearity simultaneously. Based on the 5th Gaussian pulse and Abraha's combination of doublets, a significant improvement has been achieved at extremely low and high input powers entering the amplifier (<-15 dBm and 0 dBm), recording a very good bit error rate performance and power efficiency. Better signal quality was observed after photo-detector, due to the fact that waveforms with lower frequency components are less affected by SOA nonlinearity. Our scheme has proved to be effective for 1 Gbps OOK and 0.5 Gbps PPM transmissions, while reaching a distance of 160 km in the optical fiber.

KLauS: an ASIC for silicon photomultiplier readout and its application in a setup for production testing of scintillating tiles

NASA Astrophysics Data System (ADS)

Briggl, K.; Dorn, M.; Hagdorn, R.; Harion, T.; Schultz-Coulon, H. C.; Shen, W.

2014-02-01

KLauS is an ASIC produced in the AMS 0.35 μm SiGe process to read out the charge signals from silicon photomultipliers. Developed as an analog front-end for future calorimeters with high granularity as pursued by the AHCAL concept in the CALICE collaboration, the ASIC is designed to measure the charge signal of the sensors in a large dynamic range and with low electronic noise contributions. In order to tune the operation voltage of each sensor individually, an 8-bit DAC to tune the voltage at the input terminal within a range of 2V is implemented. Using an integrated fast comparator with low jitter, the time information can be measured with sub-nanosecond resolution. The low power consumption of the ASIC can be further decreased using power gating techniques. Future versions of KLauS are under development and will incorporate an ADC with a resolution of up to 12-bits and blocks for digital data transmission. The chip is used in a setup for mass testing and characterization of scintillator tiles for the AHCAL test beam program.

Impact of ADC parameters on linear optical sampling systems

NASA Astrophysics Data System (ADS)

Nguyen, Trung-Hien; Gay, Mathilde; Gomez-Agis, Fausto; Lobo, Sébastien; Sentieys, Olivier; Simon, Jean-Claude; Peucheret, Christophe; Bramerie, Laurent

2017-11-01

Linear optical sampling (LOS), based on the coherent photodetection of an optical signal under test with a low repetition-rate signal originating from a pulsed local oscillator (LO), enables the characterization of the temporal electric field of optical sources. Thanks to this technique, low-speed photodetectors and analog-to-digital converters (ADCs) can be integrated in the LOS system providing a cost-effective tool for characterizing high-speed signals. However, the impact of photodetector and ADC parameters on such LOS systems has not been explored in detail so far. These parameters, including the integration time of the track-and-hold function, the effective number of bits (ENOB) of the ADC, as well as the combined limited bandwidth of the photodetector and ADC are experimentally and numerically investigated in a LOS system for the first time. More specifically, by reconstructing 10-Gbit/s non-return-to-zero on-off keying (NRZ-OOK) and 10-Gbaud NRZ-quadrature phase-shift-keying (QPSK) signals, it is shown that a short integration time provides a better recovered signal fidelity. Furthermore, an ENOB of 6 bits and an ADC bandwidth normalized to the sampling rate of 2.8 are found to be sufficient in order to reliably monitor the considered signals.

In vitro blood-brain barrier permeability predictions for GABAA receptor modulating piperine analogs.

PubMed

Eigenmann, Daniela Elisabeth; Dürig, Carmen; Jähne, Evelyn Andrea; Smieško, Martin; Culot, Maxime; Gosselet, Fabien; Cecchelli, Romeo; Helms, Hans Christian Cederberg; Brodin, Birger; Wimmer, Laurin; Mihovilovic, Marko D; Hamburger, Matthias; Oufir, Mouhssin

2016-06-01

The alkaloid piperine from black pepper (Piper nigrum L.) and several synthetic piperine analogs were recently identified as positive allosteric modulators of γ-aminobutyric acid type A (GABAA) receptors. In order to reach their target sites of action, these compounds need to enter the brain by crossing the blood-brain barrier (BBB). We here evaluated piperine and five selected analogs (SCT-66, SCT-64, SCT-29, LAU397, and LAU399) regarding their BBB permeability. Data were obtained in three in vitro BBB models, namely a recently established human model with immortalized hBMEC cells, a human brain-like endothelial cells (BLEC) model, and a primary animal (bovine endothelial/rat astrocytes co-culture) model. For each compound, quantitative UHPLC-MS/MS methods in the range of 5.00-500ng/mL in the corresponding matrix were developed, and permeability coefficients in the three BBB models were determined. In vitro predictions from the two human BBB models were in good agreement, while permeability data from the animal model differed to some extent, possibly due to protein binding of the screened compounds. In all three BBB models, piperine and SCT-64 displayed the highest BBB permeation potential. This was corroborated by data from in silico prediction. For the other piperine analogs (SCT-66, SCT-29, LAU397, and LAU399), BBB permeability was low to moderate in the two human BBB models, and moderate to high in the animal BBB model. Efflux ratios (ER) calculated from bidirectional permeability experiments indicated that the compounds were likely not substrates of active efflux transporters. Copyright © 2016 Elsevier B.V. All rights reserved.

A Multi-Resolution Mode CMOS Image Sensor with a Novel Two-Step Single-Slope ADC for Intelligent Surveillance Systems.

PubMed

Kim, Daehyeok; Song, Minkyu; Choe, Byeongseong; Kim, Soo Youn

2017-06-25

In this paper, we present a multi-resolution mode CMOS image sensor (CIS) for intelligent surveillance system (ISS) applications. A low column fixed-pattern noise (CFPN) comparator is proposed in 8-bit two-step single-slope analog-to-digital converter (TSSS ADC) for the CIS that supports normal, 1/2, 1/4, 1/8, 1/16, 1/32, and 1/64 mode of pixel resolution. We show that the scaled-resolution images enable CIS to reduce total power consumption while images hold steady without events. A prototype sensor of 176 × 144 pixels has been fabricated with a 0.18 μm 1-poly 4-metal CMOS process. The area of 4-shared 4T-active pixel sensor (APS) is 4.4 μm × 4.4 μm and the total chip size is 2.35 mm × 2.35 mm. The maximum power consumption is 10 mW (with full resolution) with supply voltages of 3.3 V (analog) and 1.8 V (digital) and 14 frame/s of frame rates.

An experimental adaptive radar MTI filter

NASA Astrophysics Data System (ADS)

Gong, Y. H.; Cooling, J. E.

The theoretical and practical features of a self-adaptive filter designed to remove clutter noise from a radar signal are described. The hardware employs an 8-bit microprocessor/fast hardware multiplier combination along with analog-digital and digital-analog interfaces. The software here is implemented in assembler language. It is assumed that there is little overlap between the signal and the noise spectra and that the noise power is much greater than that of the signal. It is noted that one of the most important factors to be considered when designing digital filters is the quantization noise. This works to degrade the steady state performance from that of the ideal (infinite word length) filter. The principal limitation of the filter described here is its low sampling rate (1.72 kHz), due mainly to the time spent on the multiplication routines. The methods discussed here, however, are general and can be applied to both traditional and more complex radar MTI systems, provided that the filter sampling frequency is increased. Dedicated VLSI signal processors are seen as holding considerable promise.

Prototype data terminal-multiplexer/demultiplexer

NASA Technical Reports Server (NTRS)

Leck, D. E.; Goodwin, J. E.

1972-01-01

The design and operation of a quad redundant data terminal and a multiplexer/demultiplexer (MDU) is described. The most unique feature is the design of the quad redundant data terminal. This is one of the few designs where the unit is fail/op, fail/op, fail/safe. Laboratory tests confirm that the unit will operate satisfactorily with the failure of three out of four channels. Although the design utilizes state-of-the-art technology, the waveform error checks, the voting techniques, and the parity bit checks are believed to be used in unique configurations. Correct word selection routines are also novel. The MDU design, while not redundant, utilizes, the latest state-of-the-art advantages of light coupler and interested amplifiers. Much of the technology employed was an evolution of prior NASA contracts related to the Addressable Time Division Data System. A good example of the earlier technology development was the development of a low level analog multiplexer, a high level analog multiplexer, and a digital multiplexer. A list of all drawings is included for reference and all schematic, block and timing diagrams are incorporated.

Evaluation of commercial ADC radiation tolerance for accelerator experiments

DOE PAGES

Chen, K.; Chen, H.; Kierstead, J.; ...

2015-08-17

Electronic components used in high energy physics experiments are subjected to a radiation background composed of high energy hadrons, mesons and photons. These particles can induce permanent and transient effects that affect the normal device operation. Ionizing dose and displacement damage can cause chronic damage which disable the device permanently. Transient effects or single event effects are in general recoverable with time intervals that depend on the nature of the failure. The magnitude of these effects is technology dependent with feature size being one of the key parameters. Analog to digital converters are components that are frequently used in detectormore » front end electronics, generally placed as close as possible to the sensing elements to maximize signal fidelity. We report on radiation effects tests conducted on 17 commercially available analog to digital converters and extensive single event effect measurements on specific twelve and fourteen bit ADCs that presented high tolerance to ionizing dose. We discuss mitigation strategies for single event effects (SEE) for their use in the large hadron collider environment.« less

High speed analog-to-digital conversion with silicon photonics

NASA Astrophysics Data System (ADS)

Holzwarth, C. W.; Amatya, R.; Araghchini, M.; Birge, J.; Byun, H.; Chen, J.; Dahlem, M.; DiLello, N. A.; Gan, F.; Hoyt, J. L.; Ippen, E. P.; Kärtner, F. X.; Khilo, A.; Kim, J.; Kim, M.; Motamedi, A.; Orcutt, J. S.; Park, M.; Perrott, M.; Popovic, M. A.; Ram, R. J.; Smith, H. I.; Zhou, G. R.; Spector, S. J.; Lyszczarz, T. M.; Geis, M. W.; Lennon, D. M.; Yoon, J. U.; Grein, M. E.; Schulein, R. T.; Frolov, S.; Hanjani, A.; Shmulovich, J.

2009-02-01

Sampling rates of high-performance electronic analog-to-digital converters (ADC) are fundamentally limited by the timing jitter of the electronic clock. This limit is overcome in photonic ADC's by taking advantage of the ultra-low timing jitter of femtosecond lasers. We have developed designs and strategies for a photonic ADC that is capable of 40 GSa/s at a resolution of 8 bits. This system requires a femtosecond laser with a repetition rate of 2 GHz and timing jitter less than 20 fs. In addition to a femtosecond laser this system calls for the integration of a number of photonic components including: a broadband modulator, optical filter banks, and photodetectors. Using silicon-on-insulator (SOI) as the platform we have fabricated these individual components. The silicon optical modulator is based on a Mach-Zehnder interferometer architecture and achieves a VπL of 2 Vcm. The filter banks comprise 40 second-order microring-resonator filters with a channel spacing of 80 GHz. For the photodetectors we are exploring ion-bombarded silicon waveguide detectors and germanium films epitaxially grown on silicon utilizing a process that minimizes the defect density.

Locality of Area Coverage on Digital Acoustic Communication in Air using Differential Phase Shift Keying

NASA Astrophysics Data System (ADS)

Mizutani, Keiichi; Ebihara, Tadashi; Wakatsuki, Naoto; Mizutani, Koichi

2009-07-01

We experimentally evaluate the locality of digital acoustic communication in air. Digital acoustic communication in air is suitable for a small cell system, because acoustic waves have a short propagation distance in air. In this study, optimal cell size is experimentally evaluated. Each base station (BS) transmits different commands. In our experiment, differential phase shift keying (DPSK), especially binary DPSK (DBPSK), is adopted as a modulation and demodulation scheme. The evaluated system consists of a personal computer (PC), a digital-to-analog converter (DAC), an analog-to-digital converter (ADC), a loud speaker (SP), a microphone (MIC), and transceiver software. All experiments are performed in an anechoic room. The cell size of the transmitter can be limited under low signal-to-noise ratio (SNR) condition. If another transmitter works, cell size is limited by the effect of the interference from that transmitter. The cell size-to-distance ratio of transmitter A to transmitter B is 37.5%, if cell edge bit-error-rate (BER) is taken as 10-3.

Method of recording bioelectrical signals using a capacitive coupling

NASA Astrophysics Data System (ADS)

Simon, V. A.; Gerasimov, V. A.; Kostrin, D. K.; Selivanov, L. M.; Uhov, A. A.

2017-11-01

In this article a technique for the bioelectrical signals acquisition by means of the capacitive sensors is described. A feedback loop for the ultra-high impedance biasing of the input instrumentation amplifier, which provides receiving of the electrical cardiac signal (ECS) through a capacitive coupling, is proposed. The mains 50/60 Hz noise is suppressed by a narrow-band stop filter with an independent notch frequency and quality factor tuning. Filter output is attached to a ΣΔ analog-to-digital converter (ADC), which acquires the filtered signal with a 24-bit resolution. Signal processing board is connected through universal serial bus interface to a personal computer, where ECS in a digital form is recorded and processed.

Simple Model of Mating Preference and Extinction Risk

NASA Astrophysics Data System (ADS)

PȨKALSKI, Andrzej

We present a simple model of a population of individuals characterized by their genetic structure in the form of a double string of bits and the phenotype following from it. The population is living in an unchanging habitat preferring a certain type of phenotype (optimum). Individuals are unisex, however a pair is necessary for breeding. An individual rejects a mate if the latter's phenotype contains too many bad, i.e. different from the optimum, genes in the same places as the individual's. We show that such strategy, analogous to disassortative mating based on the major histocompatibility complex, avoiding inbreeding and incest, could be beneficial for the population and could reduce considerably the extinction risk, especially in small populations.

The new ATLAS/LUCID detector

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bruschi, Marco

The new ATLAS luminosity monitor has many innovative aspects implemented. Its photomultipliers tubes are used as detector elements by using the Cherenkov light produced by charged particles above threshold crossing the quartz windows. The analog shaping of the readout chain has been improved, in order to cope with the 25 ns bunch spacing of the LHC machine. The main readout card is a quite general processing unit based on 12 bit - 500 MS/s Flash ADC and on FPGAs, delivering the processed data to 1.3 Gb/s optical links. The article will describe all these aspects and will outline future perspectivesmore » of the card for next generation high energy physics experiments. (authors)« less

SNR characteristics of 850-nm OEIC receiver with a silicon avalanche photodetector.

PubMed

Youn, Jin-Sung; Lee, Myung-Jae; Park, Kang-Yeob; Rücker, Holger; Choi, Woo-Young

2014-01-13

We investigate signal-to-noise ratio (SNR) characteristics of an 850-nm optoelectronic integrated circuit (OEIC) receiver fabricated with standard 0.25-µm SiGe bipolar complementary metal-oxide-semiconductor (BiCMOS) technology. The OEIC receiver is composed of a Si avalanche photodetector (APD) and BiCMOS analog circuits including a transimpedance amplifier with DC-balanced buffer, a tunable equalizer, a limiting amplifier, and an output buffer with 50-Ω loads. We measure APD SNR characteristics dependence on the reverse bias voltage as well as BiCMOS circuit noise characteristics. From these, we determine the SNR characteristics of the entire OEIC receiver, and finally, the results are verified with bit-error rate measurement.

The application of digital signal processing techniques to a teleoperator radar system

NASA Technical Reports Server (NTRS)

Pujol, A.

1982-01-01

A digital signal processing system was studied for the determination of the spectral frequency distribution of echo signals from a teleoperator radar system. The system consisted of a sample and hold circuit, an analog to digital converter, a digital filter, and a Fast Fourier Transform. The system is interfaced to a 16 bit microprocessor. The microprocessor is programmed to control the complete digital signal processing. The digital filtering and Fast Fourier Transform functions are implemented by a S2815 digital filter/utility peripheral chip and a S2814A Fast Fourier Transform chip. The S2815 initially simulates a low-pass Butterworth filter with later expansion to complete filter circuit (bandpass and highpass) synthesizing.

Learning the Art of Electronics

NASA Astrophysics Data System (ADS)

Hayes, Thomas C.; Horowitz, Paul

2016-03-01

1. DC circuits; 2. RC circuits; 3. Diode circuits; 4. Transistors I; 5. Transistors II; 6. Operational amplifiers I; 7. Operational amplifiers II: nice positive feedback; 8. Operational amplifiers III; 9. Operational amplifiers IV: nasty positive feedback; 10. Operational amplifiers V: PID motor control loop; 11. Voltage regulators; 12. MOSFET switches; 13. Group audio project; 14. Logic gates; 15. Logic compilers, sequential circuits, flip-flops; 16. Counters; 17. Memory: state machines; 18. Analog to digital: phase-locked loop; 19. Microcontrollers and microprocessors I: processor/controller; 20. I/O, first assembly language; 21. Bit operations; 22. Interrupt: ADC and DAC; 23. Moving pointers, serial buses; 24. Dallas Standalone Micro, SiLabs SPI RAM; 25. Toys in the attic; Appendices; Index.

Social conflicts elicit an N400-like component.

PubMed

Huang, Yi; Kendrick, Keith M; Yu, Rongjun

2014-12-01

When people have different opinions, they often adjust their own attitude to match that of others, known as social conformity. How social conflicts trigger subsequent conformity remains unclear. One possibility is that a conflict with the group opinion is perceived as a violation of social information, analogous to using wrong grammar, and activates conflict monitoring and adjustment mechanisms. Using event related potential (ERP) recording combined with a face attractiveness judgment task, we investigated the neural encoding of social conflicts. We found that social conflicts elicit an N400-like negative deflection, being more negative for conflict with group opinions than no-conflict condition. The social conflict related signals also have a bi-directional profile similar to reward prediction error signals: it was more negative for under-estimation (i.e. one׳s own ratings were smaller than group ratings) than over-estimation, and the larger the differences between ratings, the larger the N400 amplitude. The N400 effects were significantly diminished in the non-social condition. We conclude that social conflicts are encoded in a bidirectional fashion in the N400-like component, similar to the pattern of reward-based prediction error signals. Our findings also suggest that the N400, a well-established ERP component encoding semantic violation, might be involved in social conflict processing and social learning. Copyright © 2014 Elsevier Ltd. All rights reserved.

The Effects of Increasing Ocular Surface Stimulation on Blinking and Sensation

PubMed Central

Wu, Ziwei; Begley, Carolyn G.; Situ, Ping; Simpson, Trefford

2014-01-01

Purpose. The purpose of this study was to determine how increasing ocular surface stimulation affected blinking and sensation, while controlling task concentration. Methods. Ten healthy subjects concentrated on a task while a custom pneumatic device generated air flow toward the central cornea. Six flow rates (FRs) were randomly presented three times each and subjects used visual analog scales to record their sensory responses. The interblink interval (IBI) and the FR were recorded simultaneously and the IBI, sensory response, and corresponding FR were determined for each trial. The FR associated with a statistically significant decrease in IBI, the blink increase threshold (BIT), was calculated for each subject. Results. Both the mean and SD of IBI were decreased with increasing stimulation, from 5.69 ± 3.96 seconds at baseline to 1.02 ± 0.37 seconds at maximum stimulation. The average BIT was 129 ± 20 mL/min flow rate with an IBI of 2.33 ± 1.10 seconds (permutation test, P < 0.001). After log transformation, there was a significant linear function between increasing FR and decreasing IBI within each subject (Pearson's r ≤ −0.859, P < 0.05). The IBI was highly correlated with wateriness, discomfort, and cooling ratings (Pearson's r ≤ −0.606, P < 0.001). Conclusions. There was a dose-response–like relationship between increased surface stimulation and blinking in healthy subjects, presumably for protection of the ocular surface. The blink response was highly correlated with ocular surface sensation, which is not surprising given their common origins. The BIT, a novel metric, may provide an additional end point for studies on dry eye or other conditions. PMID:24557346

The architecture design of a 2mW 18-bit high speed weight voltage type DAC based on dual weight resistance chain

NASA Astrophysics Data System (ADS)

Qixing, Chen; Qiyu, Luo

2013-03-01

At present, the architecture of a digital-to-analog converter (DAC) in essence is based on the weight current, and the average value of its D/A signal current increases in geometric series according to its digital signal bits increase, which is 2n-1 times of its least weight current. But for a dual weight resistance chain type DAC, by using the weight voltage manner to D/A conversion, the D/A signal current is fixed to chain current Icha; it is only 1/2n-1 order of magnitude of the average signal current value of the weight current type DAC. Its principle is: n pairs dual weight resistances form a resistance chain, which ensures the constancy of the chain current; if digital signals control the total weight resistance from the output point to the zero potential point, that could directly control the total weight voltage of the output point, so that the digital signals directly turn into a sum of the weight voltage signals; thus the following goals are realized: (1) the total current is less than 200 μA (2) the total power consumption is less than 2 mW; (3) an 18-bit conversion can be realized by adopting a multi-grade structure; (4) the chip area is one order of magnitude smaller than the subsection current-steering type DAC; (5) the error depends only on the error of the unit resistance, so it is smaller than the error of the subsection current-steering type DAC; (6) the conversion time is only one action time of switch on or off, so its speed is not lower than the present DAC.

Design challenges of EO polymer based leaky waveguide deflector for 40 Gs/s all-optical analog-to-digital converters

NASA Astrophysics Data System (ADS)

Hadjloum, Massinissa; El Gibari, Mohammed; Li, Hongwu; Daryoush, Afshin S.

2016-08-01

Design challenges and performance optimization of an all-optical analog-to-digital converter (AOADC) is presented here. The paper addresses both microwave and optical design of a leaky waveguide optical deflector using electro-optic (E-O) polymer. The optical deflector converts magnitude variation of the applied RF voltage into variation of deflection angle out of a leaky waveguide optical beam using the linear E-O effect (Pockels effect) as part of the E-O polymer based optical waveguide. This variation of deflection angle as result of the applied RF signal is then quantized using optical windows followed by an array of high-speed photodetectors. We optimized the leakage coefficient of the leaky waveguide and its physical length to achieve the best trade-off between bandwidth and the deflected optical beam resolution, by improving the phase velocity matching between lightwave and microwave on one hand and using pre-emphasis technique to compensate for the RF signal attenuation on the other hand. In addition, for ease of access from both optical and RF perspective, a via-hole less broad bandwidth transition is designed between coplanar pads and coupled microstrip (CPW-CMS) driving electrodes. With the best reported E-O coefficient of 350 pm/V, the designed E-O deflector should allow an AOADC operating over 44 giga-samples-per-seconds with an estimated effective resolution of 6.5 bits on RF signals with Nyquist bandwidth of 22 GHz. The overall DC power consumption of all components used in this AOADC is of order of 4 W and is dominated by power consumption in the power amplifier to generate a 20 V RF voltage in 50 Ohm system. A higher sampling rate can be achieved at similar bits of resolution by interleaving a number of this elementary AOADC at the expense of a higher power consumption.

Stroboscope Controller for Imaging Helicopter Rotors

NASA Technical Reports Server (NTRS)

Jensen, Scott; Marmie, John; Mai, Nghia

2004-01-01

A versatile electronic timing-and-control unit, denoted a rotorcraft strobe controller, has been developed for use in controlling stroboscopes, lasers, video cameras, and other instruments for capturing still images of rotating machine parts especially helicopter rotors. This unit is designed to be compatible with a variety of sources of input shaftangle or timing signals and to be capable of generating a variety of output signals suitable for triggering instruments characterized by different input-signal specifications. It is also designed to be flexible and reconfigurable in that it can be modified and updated through changes in its control software, without need to change its hardware. Figure 1 is a block diagram of the rotorcraft strobe controller. The control processor is a high-density complementary metal oxide semiconductor, singlechip 8-bit microcontroller. It is connected to a 32K x 8 nonvolatile static random-access memory (RAM) module. Also connected to the control processor is a 32K 8 electrically programmable read-only-memory (EPROM) module, which is used to store the control software. Digital logic support circuitry is implemented in a field-programmable gate array (FPGA). A 240 x 128-dot, 40- character 16-line liquid-crystal display (LCD) module serves as a graphical user interface; the user provides input through a 16-key keypad mounted next to the LCD. A 12-bit digital-to-analog converter (DAC) generates a 0-to-10-V ramp output signal used as part of a rotor-blade monitoring system, while the control processor generates all the appropriate strobing signals. Optocouplers are used to isolate all input and output digital signals, and optoisolators are used to isolate all analog signals. The unit is designed to fit inside a 19-in. (.48-cm) rack-mount enclosure. Electronic components are mounted on a custom printed-circuit board (see Figure 2). Two power-conversion modules on the printedcircuit board convert AC power to +5 VDC and 15 VDC, respectively.

Laser pulse bidirectional reflectance from CALIPSO mission

NASA Astrophysics Data System (ADS)

Lu, Xiaomei; Hu, Yongxiang; Yang, Yuekui; Vaughan, Mark; Liu, Zhaoyan; Rodier, Sharon; Hunt, William; Powell, Kathy; Lucker, Patricia; Trepte, Charles

2018-06-01

This paper presents an innovative retrieval method that translates the CALIOP land surface laser pulse returns into the surface bidirectional reflectance. To better analyze the surface returns, the CALIOP receiver impulse response and the downlinked samples' distribution at 30 m vertical resolution are discussed. The saturated laser pulse magnitudes from snow and ice surfaces are recovered based on information extracted from the tail end of the surface signal. The retrieved snow surface bidirectional reflectance is compared with reflectance from both CALIOP cloud-covered regions and MODIS BRDF-albedo model parameters. In addition to the surface bidirectional reflectance, the column top-of-atmosphere bidirectional reflectances are calculated from the CALIOP lidar background data and compared with the bidirectional reflectances derived from WFC radiance measurements. The retrieved CALIOP surface bidirectional reflectance and column top-of-atmosphere bidirectional reflectance results provide unique information to complement existing MODIS standard data products and are expected to have valuable applications for modelers.

Optically-synchronized encoder and multiplexer scheme for interleaved photonics analog-to-digital conversion

NASA Astrophysics Data System (ADS)

Villa, Carlos; Kumavor, Patrick; Donkor, Eric

2008-04-01

Photonics Analog-to-Digital Converters (ADCs) utilize a train of optical pulses to sample an electrical input waveform applied to an electrooptic modulator or a reverse biased photodiode. In the former, the resulting train of amplitude-modulated optical pulses is detected (converter to electrical) and quantized using a conversional electronics ADC- as at present there are no practical, cost-effective optical quantizers available with performance that rival electronic quantizers. In the latter, the electrical samples are directly quantized by the electronics ADC. In both cases however, the sampling rate is limited by the speed with which the electronics ADC can quantize the electrical samples. One way to increase the sampling rate by a factor N is by using the time-interleaved technique which consists of a parallel array of N electrical ADC converters, which have the same sampling rate but different sampling phase. Each operating at a quantization rate of fs/N where fs is the aggregated sampling rate. In a system with no real-time operation, the N channels digital outputs are stored in memory, and then aggregated (multiplexed) to obtain the digital representation of the analog input waveform. Alternatively, for real-time operation systems the reduction of storing time in the multiplexing process is desired to improve the time response of the ADC. The complete elimination of memories come expenses of concurrent timing and synchronization in the aggregation of the digital signal that became critical for a good digital representation of the analog signal waveform. In this paper we propose and demonstrate a novel optically synchronized encoder and multiplexer scheme for interleaved photonics ADCs that utilize the N optical signals used to sample different phases of an analog input signal to synchronize the multiplexing of the resulting N digital output channels in a single digital output port. As a proof of concept, four 320 Megasamples/sec 12-bit of resolution digital signals were multiplexed to form an aggregated 1.28 Gigasamples/sec single digital output signal.

A reconfigurable cryogenic platform for the classical control of quantum processors

NASA Astrophysics Data System (ADS)

Homulle, Harald; Visser, Stefan; Patra, Bishnu; Ferrari, Giorgio; Prati, Enrico; Sebastiano, Fabio; Charbon, Edoardo

2017-04-01

The implementation of a classical control infrastructure for large-scale quantum computers is challenging due to the need for integration and processing time, which is constrained by coherence time. We propose a cryogenic reconfigurable platform as the heart of the control infrastructure implementing the digital error-correction control loop. The platform is implemented on a field-programmable gate array (FPGA) that supports the functionality required by several qubit technologies and that can operate close to the physical qubits over a temperature range from 4 K to 300 K. This work focuses on the extensive characterization of the electronic platform over this temperature range. All major FPGA building blocks (such as look-up tables (LUTs), carry chains (CARRY4), mixed-mode clock manager (MMCM), phase-locked loop (PLL), block random access memory, and IDELAY2 (programmable delay element)) operate correctly and the logic speed is very stable. The logic speed of LUTs and CARRY4 changes less then 5%, whereas the jitter of MMCM and PLL clock managers is reduced by 20%. The stability is finally demonstrated by operating an integrated 1.2 GSa/s analog-to-digital converter (ADC) with a relatively stable performance over temperature. The ADCs effective number of bits drops from 6 to 4.5 bits when operating at 15 K.

A reconfigurable cryogenic platform for the classical control of quantum processors.

PubMed

Homulle, Harald; Visser, Stefan; Patra, Bishnu; Ferrari, Giorgio; Prati, Enrico; Sebastiano, Fabio; Charbon, Edoardo

2017-04-01

The implementation of a classical control infrastructure for large-scale quantum computers is challenging due to the need for integration and processing time, which is constrained by coherence time. We propose a cryogenic reconfigurable platform as the heart of the control infrastructure implementing the digital error-correction control loop. The platform is implemented on a field-programmable gate array (FPGA) that supports the functionality required by several qubit technologies and that can operate close to the physical qubits over a temperature range from 4 K to 300 K. This work focuses on the extensive characterization of the electronic platform over this temperature range. All major FPGA building blocks (such as look-up tables (LUTs), carry chains (CARRY4), mixed-mode clock manager (MMCM), phase-locked loop (PLL), block random access memory, and IDELAY2 (programmable delay element)) operate correctly and the logic speed is very stable. The logic speed of LUTs and CARRY4 changes less then 5%, whereas the jitter of MMCM and PLL clock managers is reduced by 20%. The stability is finally demonstrated by operating an integrated 1.2 GSa/s analog-to-digital converter (ADC) with a relatively stable performance over temperature. The ADCs effective number of bits drops from 6 to 4.5 bits when operating at 15 K.

SEMICONDUCTOR INTEGRATED CIRCUITS: A high performance 90 nm CMOS SAR ADC with hybrid architecture

NASA Astrophysics Data System (ADS)

Xingyuan, Tong; Jianming, Chen; Zhangming, Zhu; Yintang, Yang

2010-01-01

A 10-bit 2.5 MS/s SAR A/D converter is presented. In the circuit design, an R-C hybrid architecture D/A converter, pseudo-differential comparison architecture and low power voltage level shifters are utilized. Design challenges and considerations are also discussed. In the layout design, each unit resistor is sided by dummies for good matching performance, and the capacitors are routed with a common-central symmetry method to reduce the nonlin-earity error. This proposed converter is implemented based on 90 nm CMOS logic process. With a 3.3 V analog supply and a 1.0 V digital supply, the differential and integral nonlinearity are measured to be less than 0.36 LSB and 0.69 LSB respectively. With an input frequency of 1.2 MHz at 2.5 MS/s sampling rate, the SFDR and ENOB are measured to be 72.86 dB and 9.43 bits respectively, and the power dissipation is measured to be 6.62 mW including the output drivers. This SAR A/D converter occupies an area of 238 × 214 μm2. The design results of this converter show that it is suitable for multi-supply embedded SoC applications.

A customizable system for real-time image processing using the Blackfin DSProcessor and the MicroC/OS-II real-time kernel

NASA Astrophysics Data System (ADS)

Coffey, Stephen; Connell, Joseph

2005-06-01

This paper presents a development platform for real-time image processing based on the ADSP-BF533 Blackfin processor and the MicroC/OS-II real-time operating system (RTOS). MicroC/OS-II is a completely portable, ROMable, pre-emptive, real-time kernel. The Blackfin Digital Signal Processors (DSPs), incorporating the Analog Devices/Intel Micro Signal Architecture (MSA), are a broad family of 16-bit fixed-point products with a dual Multiply Accumulate (MAC) core. In addition, they have a rich instruction set with variable instruction length and both DSP and MCU functionality thus making them ideal for media based applications. Using the MicroC/OS-II for task scheduling and management, the proposed system can capture and process raw RGB data from any standard 8-bit greyscale image sensor in soft real-time and then display the processed result using a simple PC graphical user interface (GUI). Additionally, the GUI allows configuration of the image capture rate and the system and core DSP clock rates thereby allowing connectivity to a selection of image sensors and memory devices. The GUI also allows selection from a set of image processing algorithms based in the embedded operating system.

Bidirectional Pressure-Regulator System

NASA Technical Reports Server (NTRS)

Burke, Kenneth; Miller, John R.

2008-01-01

A bidirectional pressure-regulator system has been devised for use in a regenerative fuel cell system. The bidirectional pressure-regulator acts as a back-pressure regulator as gas flows through the bidirectional pressure-regulator in one direction. Later, the flow of gas goes through the regulator in the opposite direction and the bidirectional pressure-regulator operates as a pressure- reducing pressure regulator. In the regenerative fuel cell system, there are two such bidirectional regulators, one for the hydrogen gas and another for the oxygen gas. The flow of gases goes from the regenerative fuel cell system to the gas storage tanks when energy is being stored, and reverses direction, flowing from the storage tanks to the regenerative fuel cell system when the stored energy is being withdrawn from the regenerative fuel cell system. Having a single bidirectional regulator replaces two unidirectional regulators, plumbing, and multiple valves needed to reverse the flow direction. The term "bidirectional" refers to both the bidirectional nature of the gas flows and capability of each pressure regulator to control the pressure on either its upstream or downstream side, regardless of the direction of flow.

Programmable synaptic devices for electronic neural nets

NASA Technical Reports Server (NTRS)

Moopenn, A.; Thakoor, A. P.

1990-01-01

The architecture, design, and operational characteristics of custom VLSI and thin film synaptic devices are described. The devices include CMOS-based synaptic chips containing 1024 reprogrammable synapses with a 6-bit dynamic range, and nonvolatile, write-once, binary synaptic arrays based on memory switching in hydrogenated amorphous silicon films. Their suitability for embodiment of fully parallel and analog neural hardware is discussed. Specifically, a neural network solution to an assignment problem of combinatorial global optimization, implemented in fully parallel hardware using the synaptic chips, is described. The network's ability to provide optimal and near optimal solutions over a time scale of few neuron time constants has been demonstrated and suggests a speedup improvement of several orders of magnitude over conventional search methods.

Coherent Oscillations inside a Quantum Manifold Stabilized by Dissipation

NASA Astrophysics Data System (ADS)

Touzard, S.; Grimm, A.; Leghtas, Z.; Mundhada, S. O.; Reinhold, P.; Axline, C.; Reagor, M.; Chou, K.; Blumoff, J.; Sliwa, K. M.; Shankar, S.; Frunzio, L.; Schoelkopf, R. J.; Mirrahimi, M.; Devoret, M. H.

2018-04-01

Manipulating the state of a logical quantum bit (qubit) usually comes at the expense of exposing it to decoherence. Fault-tolerant quantum computing tackles this problem by manipulating quantum information within a stable manifold of a larger Hilbert space, whose symmetries restrict the number of independent errors. The remaining errors do not affect the quantum computation and are correctable after the fact. Here we implement the autonomous stabilization of an encoding manifold spanned by Schrödinger cat states in a superconducting cavity. We show Zeno-driven coherent oscillations between these states analogous to the Rabi rotation of a qubit protected against phase flips. Such gates are compatible with quantum error correction and hence are crucial for fault-tolerant logical qubits.

Scientists must listen to be heard

NASA Astrophysics Data System (ADS)

Lefkoff, Jeff

My experience as an AGU Congressional Fellow began in earnest when I was told “Legislation is a bit like sausage—Once you find out how it's really made, you feel completely different about it.” Being a vegetarian, I knew then that I was in for an interesting year.The sausage analogy was cited during a 2-week orientation to Capitol Hill that was planned by the American Association for the Advancement of Science (AAAS). I was one of 25 AAAS Congressional Science Fellows, each sponsored by different scientific society. Though our backgrounds varied widely, two shared feelings quickly brought us together: an interest in the interface between science and policy and a desire to steer our career paths toward that interface.

Thomson Scattering Diagnostic Data Acquisition Systems for Modern Fusion Systems

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ivanenko, S.V.; Khilchenko, A.D.; Ovchar, V.K.

2015-07-01

Uniquely designed complex data acquisition system for Thomson scattering diagnostic was developed. It allows recording short duration (3-5 ns) scattered pulses with 2 GHz sampling rate and 10-bit total resolution in oscilloscope mode. The system consists up to 48 photo detector modules with 0- 200 MHz bandwidth, 1-48 simultaneously sampling ADC modules and synchronization subsystem. The photo detector modules are based on avalanche photodiodes (APD) and ultra-low noise trans-impedance amplifiers. ADC modules include fast analog to digital converters and digital units based on the FPGA (Field- Programmable Gate Array) for data processing and storage. The synchronization subsystem is used tomore » form triggering pulses and to organize the simultaneously mode of ADC modules operation. (authors)« less

Temporal steering and security of quantum key distribution with mutually unbiased bases against individual attacks

NASA Astrophysics Data System (ADS)

Bartkiewicz, Karol; Černoch, Antonín; Lemr, Karel; Miranowicz, Adam; Nori, Franco

2016-06-01

Temporal steering, which is a temporal analog of Einstein-Podolsky-Rosen steering, refers to temporal quantum correlations between the initial and final state of a quantum system. Our analysis of temporal steering inequalities in relation to the average quantum bit error rates reveals the interplay between temporal steering and quantum cloning, which guarantees the security of quantum key distribution based on mutually unbiased bases against individual attacks. The key distributions analyzed here include the Bennett-Brassard 1984 protocol and the six-state 1998 protocol by Bruss. Moreover, we define a temporal steerable weight, which enables us to identify a kind of monogamy of temporal correlation that is essential to quantum cryptography and useful for analyzing various scenarios of quantum causality.

Electronic still camera

NASA Astrophysics Data System (ADS)

Holland, S. Douglas

1992-09-01

A handheld, programmable, digital camera is disclosed that supports a variety of sensors and has program control over the system components to provide versatility. The camera uses a high performance design which produces near film quality images from an electronic system. The optical system of the camera incorporates a conventional camera body that was slightly modified, thus permitting the use of conventional camera accessories, such as telephoto lenses, wide-angle lenses, auto-focusing circuitry, auto-exposure circuitry, flash units, and the like. An image sensor, such as a charge coupled device ('CCD') collects the photons that pass through the camera aperture when the shutter is opened, and produces an analog electrical signal indicative of the image. The analog image signal is read out of the CCD and is processed by preamplifier circuitry, a correlated double sampler, and a sample and hold circuit before it is converted to a digital signal. The analog-to-digital converter has an accuracy of eight bits to insure accuracy during the conversion. Two types of data ports are included for two different data transfer needs. One data port comprises a general purpose industrial standard port and the other a high speed/high performance application specific port. The system uses removable hard disks as its permanent storage media. The hard disk receives the digital image signal from the memory buffer and correlates the image signal with other sensed parameters, such as longitudinal or other information. When the storage capacity of the hard disk has been filled, the disk can be replaced with a new disk.

Electronic Still Camera

NASA Technical Reports Server (NTRS)

Holland, S. Douglas (Inventor)

1992-01-01

A handheld, programmable, digital camera is disclosed that supports a variety of sensors and has program control over the system components to provide versatility. The camera uses a high performance design which produces near film quality images from an electronic system. The optical system of the camera incorporates a conventional camera body that was slightly modified, thus permitting the use of conventional camera accessories, such as telephoto lenses, wide-angle lenses, auto-focusing circuitry, auto-exposure circuitry, flash units, and the like. An image sensor, such as a charge coupled device ('CCD') collects the photons that pass through the camera aperture when the shutter is opened, and produces an analog electrical signal indicative of the image. The analog image signal is read out of the CCD and is processed by preamplifier circuitry, a correlated double sampler, and a sample and hold circuit before it is converted to a digital signal. The analog-to-digital converter has an accuracy of eight bits to insure accuracy during the conversion. Two types of data ports are included for two different data transfer needs. One data port comprises a general purpose industrial standard port and the other a high speed/high performance application specific port. The system uses removable hard disks as its permanent storage media. The hard disk receives the digital image signal from the memory buffer and correlates the image signal with other sensed parameters, such as longitudinal or other information. When the storage capacity of the hard disk has been filled, the disk can be replaced with a new disk.

A Wireless FSCV Monitoring IC With Analog Background Subtraction and UWB Telemetry.

PubMed

Dorta-Quiñones, Carlos I; Wang, Xiao Y; Dokania, Rajeev K; Gailey, Alycia; Lindau, Manfred; Apsel, Alyssa B

2016-04-01

A 30-μW wireless fast-scan cyclic voltammetry monitoring integrated circuit for ultra-wideband (UWB) transmission of dopamine release events in freely-behaving small animals is presented. On-chip integration of analog background subtraction and UWB telemetry yields a 32-fold increase in resolution versus standard Nyquist-rate conversion alone, near a four-fold decrease in the volume of uplink data versus single-bit, third-order, delta-sigma modulation, and more than a 20-fold reduction in transmit power versus narrowband transmission for low data rates. The 1.5- mm(2) chip, which was fabricated in 65-nm CMOS technology, consists of a low-noise potentiostat frontend, a two-step analog-to-digital converter (ADC), and an impulse-radio UWB transmitter (TX). The duty-cycled frontend and ADC/UWB-TX blocks draw 4 μA and 15 μA from 3-V and 1.2-V supplies, respectively. The chip achieves an input-referred current noise of 92 pA(rms) and an input current range of ±430 nA at a conversion rate of 10 kHz. The packaged device operates from a 3-V coin-cell battery, measures 4.7 × 1.9 cm(2), weighs 4.3 g (including the battery and antenna), and can be carried by small animals. The system was validated by wirelessly recording flow-injection of dopamine with concentrations in the range of 250 nM to 1 μM with a carbon-fiber microelectrode (CFM) using 300-V/s FSCV.

A Wireless FSCV Monitoring IC with Analog Background Subtraction and UWB Telemetry

PubMed Central

Dorta-Quiñones, Carlos I.; Wang, Xiao Y.; Dokania, Rajeev K.; Gailey, Alycia; Lindau, Manfred; Apsel, Alyssa B.

2015-01-01

A 30-μW wireless fast-scan cyclic voltammetry monitoring integrated circuit for ultra-wideband (UWB) transmission of dopamine release events in freely-behaving small animals is presented. On-chip integration of analog background subtraction and UWB telemetry yields a 32-fold increase in resolution versus standard Nyquist-rate conversion alone, near a four-fold decrease in the volume of uplink data versus single-bit, third-order, delta-sigma modulation, and more than a 20-fold reduction in transmit power versus narrowband transmission for low data rates. The 1.5-mm2 chip, which was fabricated in 65-nm CMOS technology, consists of a low-noise potentiostat frontend, a two-step analog-to-digital converter (ADC), and an impulse-radio UWB transmitter (TX). The duty-cycled frontend and ADC/UWB-TX blocks draw 4 μA and 15 μA from 3-V and 1.2-V supplies, respectively. The chip achieves an input-referred current noise of 92 pArms and an input current range of ±430 nA at a conversion rate of 10 kHz. The packaged device operates from a 3-V coin-cell battery, measures 4.7 × 1.9 cm2, weighs 4.3 g (including the battery and antenna), and can be carried by small animals. The system was validated by wirelessly recording flow-injection of dopamine with concentrations in the range of 250 nM to 1 μM with a carbon-fiber microelectrode (CFM) using 300-V/s FSCV. PMID:26057983

Frequency domain near-infrared multiwavelength imager design using high-speed, direct analog-to-digital conversion

NASA Astrophysics Data System (ADS)

Zimmermann, Bernhard B.; Fang, Qianqian; Boas, David A.; Carp, Stefan A.

2016-01-01

Frequency domain near-infrared spectroscopy (FD-NIRS) has proven to be a reliable method for quantification of tissue absolute optical properties. We present a full-sampling direct analog-to-digital conversion FD-NIR imager. While we developed this instrument with a focus on high-speed optical breast tomographic imaging, the proposed design is suitable for a wide-range of biophotonic applications where fast, accurate quantification of absolute optical properties is needed. Simultaneous dual wavelength operation at 685 and 830 nm is achieved by concurrent 67.5 and 75 MHz frequency modulation of each laser source, respectively, followed by digitization using a high-speed (180 MS/s) 16-bit A/D converter and hybrid FPGA-assisted demodulation. The instrument supports 25 source locations and features 20 concurrently operating detectors. The noise floor of the instrument was measured at <1.4 pW/√Hz, and a dynamic range of 115+ dB, corresponding to nearly six orders of magnitude, has been demonstrated. Titration experiments consisting of 200 different absorption and scattering values were conducted to demonstrate accurate optical property quantification over the entire range of physiologically expected values.

Frequency domain near-infrared multiwavelength imager design using high-speed, direct analog-to-digital conversion

PubMed Central

Zimmermann, Bernhard B.; Fang, Qianqian; Boas, David A.; Carp, Stefan A.

2016-01-01

Abstract. Frequency domain near-infrared spectroscopy (FD-NIRS) has proven to be a reliable method for quantification of tissue absolute optical properties. We present a full-sampling direct analog-to-digital conversion FD-NIR imager. While we developed this instrument with a focus on high-speed optical breast tomographic imaging, the proposed design is suitable for a wide-range of biophotonic applications where fast, accurate quantification of absolute optical properties is needed. Simultaneous dual wavelength operation at 685 and 830 nm is achieved by concurrent 67.5 and 75 MHz frequency modulation of each laser source, respectively, followed by digitization using a high-speed (180  MS/s) 16-bit A/D converter and hybrid FPGA-assisted demodulation. The instrument supports 25 source locations and features 20 concurrently operating detectors. The noise floor of the instrument was measured at <1.4  pW/√Hz, and a dynamic range of 115+ dB, corresponding to nearly six orders of magnitude, has been demonstrated. Titration experiments consisting of 200 different absorption and scattering values were conducted to demonstrate accurate optical property quantification over the entire range of physiologically expected values. PMID:26813081

A configurable and low-power mixed signal SoC for portable ECG monitoring applications.

PubMed

Kim, Hyejung; Kim, Sunyoung; Van Helleputte, Nick; Artes, Antonio; Konijnenburg, Mario; Huisken, Jos; Van Hoof, Chris; Yazicioglu, Refet Firat

2014-04-01

This paper describes a mixed-signal ECG System-on-Chip (SoC) that is capable of implementing configurable functionality with low-power consumption for portable ECG monitoring applications. A low-voltage and high performance analog front-end extracts 3-channel ECG signals and single channel electrode-tissue-impedance (ETI) measurement with high signal quality. This can be used to evaluate the quality of the ECG measurement and to filter motion artifacts. A custom digital signal processor consisting of 4-way SIMD processor provides the configurability and advanced functionality like motion artifact removal and R peak detection. A built-in 12-bit analog-to-digital converter (ADC) is capable of adaptive sampling achieving a compression ratio of up to 7, and loop buffer integration reduces the power consumption for on-chip memory access. The SoC is implemented in 0.18 μm CMOS process and consumes 32 μ W from a 1.2 V while heart beat detection application is running, and integrated in a wireless ECG monitoring system with Bluetooth protocol. Thanks to the ECG SoC, the overall system power consumption can be reduced significantly.

Evaluation of the Geotech SMART24BH 20Vpp/5Vpp data acquisition system with active fortezza crypto card data signing and authentication.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Rembold, Randy Kai; Hart, Darren M.

Sandia National Laboratories has tested and evaluated Geotech SMART24BH borehole data acquisition system with active Fortezza crypto card data signing and authentication. The test results included in this report were in response to static and tonal-dynamic input signals. Most test methodologies used were based on IEEE Standards 1057 for Digitizing Waveform Recorders and 1241 for Analog to Digital Converters; others were designed by Sandia specifically for infrasound application evaluation and for supplementary criteria not addressed in the IEEE standards. The objective of this work was to evaluate the overall technical performance of two Geotech SMART24BH digitizers with a Fortezza PCMCIAmore » crypto card actively implementing the signing of data packets. The results of this evaluation were compared to relevant specifications provided within manufacturer's documentation notes. The tests performed were chosen to demonstrate different performance aspects of the digitizer under test. The performance aspects tested include determining noise floor, least significant bit (LSB), dynamic range, cross-talk, relative channel-to-channel timing, time-tag accuracy/statistics/drift, analog bandwidth.« less

Digital Plasma Control System for Alcator C-Mod

NASA Astrophysics Data System (ADS)

Ferrara, M.; Wolfe, S.; Stillerman, J.; Fredian, T.; Hutchinson, I.

2004-11-01

A digital plasma control system (DPCS) has been designed to replace the present C-Mod system, which is based on hybrid analog-digital computer. The initial implementation of DPCS comprises two 64 channel, 16 bit, low-latency cPCI digitizers, each with 16 analog outputs, controlled by a rack-mounted single-processor Linux server, which also serves as the compute engine. A prototype system employing three older 32 channel digitizers was tested during the 2003-04 campaign. The hybrid's linear PID feedback system was emulated by IDL code executing a synchronous loop, using the same target waveforms and control parameters. Reliable real-time operation was accomplished under a standard Linux OS (RH9) by locking memory and disabling interrupts during the plasma pulse. The DPCS-computed outputs agreed to within a few percent with those produced by the hybrid system, except for discrepancies due to offsets and non-ideal behavior of the hybrid circuitry. The system operated reliably, with no sample loss, at more than twice the 10kHz design specification, providing extra time for implementing more advanced control algorithms. The code is fault-tolerant and produces consistent output waveforms even with 10% sample loss.

Focal plane subsystem design and performance for atmospheric chemistry from geostationary orbit tropospheric emissions monitoring of pollution

NASA Astrophysics Data System (ADS)

Gilmore, A. S.; Philbrick, R. H.; Funderburg, J.

2017-09-01

Remote sensing of pollutants are enabled from a satellite in a geostationary orbit containing an imaging spectrometer encompassing the wavelength ranges of 290 - 490 nm and 540 - 740 nm. As the first of NASA's Earth Venture Instrument Program, the Tropospheric Emissions: Monitoring of Pollution (TEMPO) program will utilize this instrument to measure hourly air quality over a large portion of North America. The focal plane subsystem (FPS) contains two custom designed and critically aligned full frame transfer charge coupled devices (active area: 1028 x 2048, 18 μm) within a focal plane array package designed for radiation tolerance and space charging rejection. In addition, the FPS contains custom distributed focal plane electronics that provide all necessary clocks and biases to the sensors, receives all analog data from the sensors and performs 14 bit analog to digital conversion for upstream processing. Finally, the FPS encompasses custom low noise cables connecting the focal plane array and associated electronics. This paper discusses the design and performance of this novel focal plane subsystem with particular emphasis on the optical performance achieved including alignment, quantum efficiency, and modulation transfer function.

Characterization of Sphinx1 ASIC X-ray detector using photon counting and charge integration

NASA Astrophysics Data System (ADS)

Habib, A.; Arques, M.; Moro, J.-L.; Accensi, M.; Stanchina, S.; Dupont, B.; Rohr, P.; Sicard, G.; Tchagaspanian, M.; Verger, L.

2018-01-01

Sphinx1 is a novel pixel architecture adapted for X-ray imaging, it detects radiation by photon counting and charge integration. In photon counting mode, each photon is compensated by one or more counter-charges typically consisting of 100 electrons (e-) each. The number of counter-charges required gives a measure of the incoming photon energy, thus allowing spectrometric detection. Pixels can also detect radiation by integrating the charges deposited by all incoming photons during one image frame and converting this analog value into a digital response with a 100 electrons least significant bit (LSB), based on the counter-charge concept. A proof of concept test chip measuring 5 mm × 5 mm, with 200 μm × 200 μm pixels has been produced and characterized. This paper provides details on the architecture and the counter-charge design; it also describes the two modes of operation: photon counting and charge integration. The first performance measurements for this test chip are presented. Noise was found to be ~80 e-rms in photon counting mode with a power consumption of only 0.9 μW/pixel for the static analog part and 0.3 μW/pixel for the static digital part.

Investigating the Binary Offset Effect in the STIS CCD

NASA Astrophysics Data System (ADS)

Debes, John H.; Lockwood, Sean A.

2018-05-01

Recently, Boone et al., (2018) presented the "Binary Offset Effect" for the SNIFS instrument, which uses a CCD detector. The source of this uncertainty is related to the analog-to-digital readout process, which converts the analog electronic signal of the detector into a digital number as represented by binary bits. The Binary Offset Effect is due to cross-talk between the digital conversion process for a source or driver pixel and pixels read out after the driver. In the course of Boone et al.'s experimentation with this effect they identified a similar effect with the STIS CCD. The STIS team has independently investigated the Binary Offset Effect for a range of bias images currently used for scientific observations, broadly confirming that the effect exists. However, our preliminary investigation suggests that the impact is smaller than reported in Boone et al. (2018) for biases taken with Amplifier=D and GAIN=1, and a lesser effect exists for Amplifier=D and GAIN=4. There is a hint that the effect is time variable for the detector. We broadly assess the potential impact of this effect and make recommendations both for users and future directions of investigation.

32-Bit-Wide Memory Tolerates Failures

NASA Technical Reports Server (NTRS)

Buskirk, Glenn A.

1990-01-01

Electronic memory system of 32-bit words corrects bit errors caused by some common type of failures - even failure of entire 4-bit-wide random-access-memory (RAM) chip. Detects failure of two such chips, so user warned that ouput of memory may contain errors. Includes eight 4-bit-wide DRAM's configured so each bit of each DRAM assigned to different one of four parallel 8-bit words. Each DRAM contributes only 1 bit to each 8-bit word.

Effect of PDC bit design and confining pressure on bit-balling tendencies while drilling shale using water base mud

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hariharan, P.R.; Azar, J.J.

1996-09-01

A good majority of all oilwell drilling occurs in shale and other clay-bearing rocks. In the light of relatively fewer studies conducted, the problem of bit-balling in PDC bits while drilling shale has been addressed with the primary intention of attempting to quantify the degree of balling, as well as to investigate the influence of bit design and confining pressures. A series of full-scale laboratory drilling tests under simulated down hole conditions were conducted utilizing seven different PDC bits in Catoosa shale. Test results have indicated that the non-dimensional parameter R{sub d} [(bit torque).(weight-on-bit)/(bit diameter)] is a good indicator ofmore » the degree of bit-balling and that it correlated well with Specific-Energy. Furthermore, test results have shown bit-profile and bit-hydraulic design to be key parameters of bit design that dictate the tendency of balling in shales under a given set of operating conditions. A bladed bit was noticed to ball less compared to a ribbed or open-faced bit. Likewise, related to bit profile, test results have indicated that the parabolic profile has a lesser tendency to ball compared to round and flat profiles. The tendency of PDC bits to ball was noticed to increase with increasing confining pressures for the set of drilling conditions used.« less

Frequency-agile wireless sensor networks

NASA Astrophysics Data System (ADS)

Arms, Steven W.; Townsend, Christopher P.; Churchill, David L.; Hamel, Michael J.; Galbreath, Jacob H.; Mundell, Steven W.

2004-07-01

Our goal was to demonstrate a wireless communications system capable of simultaneous, high speed data communications from a variety of sensors. We have previously reported on the design and application of 2 KHz data logging transceiver nodes, however, only one node may stream data at a time, since all nodes on the network use the same communications frequency. To overcome these limitations, second generation data logging transceivers were developed with software programmable radio frequency (RF) communications. Each node contains on-board memory (2 Mbytes), sensor excitation, instrumentation amplifiers with programmable gains & offsets, multiplexer, 16 bit A/D converter, microcontroller, and frequency agile, bi-directional, frequency shift keyed (FSK) RF serial data link. These systems are capable of continuous data transmission from 26 distinct nodes (902-928 MHz band, 75 kbaud). The system was demonstrated in a compelling structural monitoring application. The National Parks Service requested a means for continual monitoring and recording of sensor data from the Liberty Bell during a move to a new location (Philadelphia, October 2003). Three distinct, frequency agile, wireless sensing nodes were used to detect visible crack shear/opening micromotions, triaxial accelerations, and hairline crack tip strains. The wireless sensors proved to be useful in protecting the Liberty Bell.

Wireless neural recording with single low-power integrated circuit.

PubMed

Harrison, Reid R; Kier, Ryan J; Chestek, Cynthia A; Gilja, Vikash; Nuyujukian, Paul; Ryu, Stephen; Greger, Bradley; Solzbacher, Florian; Shenoy, Krishna V

2009-08-01

We present benchtop and in vivo experimental results from an integrated circuit designed for wireless implantable neural recording applications. The chip, which was fabricated in a commercially available 0.6- mum 2P3M BiCMOS process, contains 100 amplifiers, a 10-bit analog-to-digital converter (ADC), 100 threshold-based spike detectors, and a 902-928 MHz frequency-shift-keying (FSK) transmitter. Neural signals from a selected amplifier are sampled by the ADC at 15.7 kSps and telemetered over the FSK wireless data link. Power, clock, and command signals are sent to the chip wirelessly over a 2.765-MHz inductive (coil-to-coil) link. The chip is capable of operating with only two off-chip components: a power/command receiving coil and a 100-nF capacitor.

Advanced Atmospheric Water Vapor DIAL Detection System

NASA Technical Reports Server (NTRS)

Refaat, Tamer F.; Elsayed-Ali, Hani E.; DeYoung, Russell J. (Technical Monitor)

2000-01-01

Measurement of atmospheric water vapor is very important for understanding the Earth's climate and water cycle. The remote sensing Differential Absorption Lidar (DIAL) technique is a powerful method to perform such measurement from aircraft and space. This thesis describes a new advanced detection system, which incorporates major improvements regarding sensitivity and size. These improvements include a low noise advanced avalanche photodiode detector, a custom analog circuit, a 14-bit digitizer, a microcontroller for on board averaging and finally a fast computer interface. This thesis describes the design and validation of this new water vapor DIAL detection system which was integrated onto a small Printed Circuit Board (PCB) with minimal weight and power consumption. Comparing its measurements to an existing DIAL system for aerosol and water vapor profiling validated the detection system.

Development of land based radar polarimeter processor system

NASA Technical Reports Server (NTRS)

Kronke, C. W.; Blanchard, A. J.

1983-01-01

The processing subsystem of a land based radar polarimeter was designed and constructed. This subsystem is labeled the remote data acquisition and distribution system (RDADS). The radar polarimeter, an experimental remote sensor, incorporates the RDADS to control all operations of the sensor. The RDADS uses industrial standard components including an 8-bit microprocessor based single board computer, analog input/output boards, a dynamic random access memory board, and power supplis. A high-speed digital electronics board was specially designed and constructed to control range-gating for the radar. A complete system of software programs was developed to operate the RDADS. The software uses a powerful real time, multi-tasking, executive package as an operating system. The hardware and software used in the RDADS are detailed. Future system improvements are recommended.

A Compton suppressed detector multiplicity trigger based digital DAQ for gamma-ray spectroscopy

NASA Astrophysics Data System (ADS)

Das, S.; Samanta, S.; Banik, R.; Bhattacharjee, R.; Basu, K.; Raut, R.; Ghugre, S. S.; Sinha, A. K.; Bhattacharya, S.; Imran, S.; Mukherjee, G.; Bhattacharyya, S.; Goswami, A.; Palit, R.; Tan, H.

2018-06-01

The development of a digitizer based pulse processing and data acquisition system for γ-ray spectroscopy with large detector arrays is presented. The system is based on 250 MHz 12-bit digitizers, and is triggered by a user chosen multiplicity of Compton suppressed detectors. The logic for trigger generation is similar to the one practised for analog (NIM/CAMAC) pulse processing electronics, while retaining the fast processing merits of the digitizer system. Codes for reduction of data acquired from the system have also been developed. The system has been tested with offline studies using radioactive sources as well as in the in-beam experiments with an array of Compton suppressed Clover detectors. The results obtained therefrom validate its use in spectroscopic efforts for nuclear structure investigations.

Proper nozzle location, bit profile, and cutter arrangement affect PDC-bit performance significantly

DOE Office of Scientific and Technical Information (OSTI.GOV)

Garcia-Gavito, D.; Azar, J.J.

1994-09-01

During the past 20 years, the drilling industry has looked to new technology to halt the exponentially increasing costs of drilling oil, gas, and geothermal wells. This technology includes bit design innovations to improve overall drilling performance and reduce drilling costs. These innovations include development of drag bits that use PDC cutters, also called PDC bits, to drill long, continuous intervals of soft to medium-hard formations more economically than conventional three-cone roller-cone bits. The cost advantage is the result of higher rates of penetration (ROP's) and longer bit life obtained with the PDC bits. An experimental study comparing the effectsmore » of polycrystalline-diamond-compact (PDC)-bit design features on the dynamic pressure distribution at the bit/rock interface was conducted on a full-scale drilling rig. Results showed that nozzle location, bit profile, and cutter arrangement are significant factors in PDC-bit performance.« less

Acquisition and Retaining Granular Samples via a Rotating Coring Bit

NASA Technical Reports Server (NTRS)

Bar-Cohen, Yoseph; Badescu, Mircea; Sherrit, Stewart

2013-01-01

This device takes advantage of the centrifugal forces that are generated when a coring bit is rotated, and a granular sample is entered into the bit while it is spinning, making it adhere to the internal wall of the bit, where it compacts itself into the wall of the bit. The bit can be specially designed to increase the effectiveness of regolith capturing while turning and penetrating the subsurface. The bit teeth can be oriented such that they direct the regolith toward the bit axis during the rotation of the bit. The bit can be designed with an internal flute that directs the regolith upward inside the bit. The use of both the teeth and flute can be implemented in the same bit. The bit can also be designed with an internal spiral into which the various particles wedge. In another implementation, the bit can be designed to collect regolith primarily from a specific depth. For that implementation, the bit can be designed such that when turning one way, the teeth guide the regolith outward of the bit and when turning in the opposite direction, the teeth will guide the regolith inward into the bit internal section. This mechanism can be implemented with or without an internal flute. The device is based on the use of a spinning coring bit (hollow interior) as a means of retaining granular sample, and the acquisition is done by inserting the bit into the subsurface of a regolith, soil, or powder. To demonstrate the concept, a commercial drill and a coring bit were used. The bit was turned and inserted into the soil that was contained in a bucket. While spinning the bit (at speeds of 600 to 700 RPM), the drill was lifted and the soil was retained inside the bit. To prove this point, the drill was turned horizontally, and the acquired soil was still inside the bit. The basic theory behind the process of retaining unconsolidated mass that can be acquired by the centrifugal forces of the bit is determined by noting that in order to stay inside the interior of the bit, the frictional force must be greater than the weight of the sample. The bit can be designed with an internal sleeve to serve as a container for granular samples. This tube-shaped component can be extracted upon completion of the sampling, and the bottom can be capped by placing the bit onto a corklike component. Then, upon removal of the internal tube, the top section can be sealed. The novel features of this device are: center dot A mechanism of acquiring and retaining granular samples using a coring bit without a closed door. center dot An acquisition bit that has internal structure such as a waffle pattern for compartmentalizing or helical internal flute to propel the sample inside the bit and help in acquiring and retaining granular samples. center dot A bit with an internal spiral into which the various particles wedge. center dot A design that provides a method of testing frictional properties of the granular samples and potentially segregating particles based on size and density. A controlled acceleration or deceleration may be used to drop the least-frictional particles or to eventually shear the unconsolidated material near the bit center.

Preliminary Results from a Model-Driven Architecture Methodology for Development of an Event-Driven Space Communications Service Concept

NASA Technical Reports Server (NTRS)

Roberts, Christopher J.; Morgenstern, Robert M.; Israel, David J.; Borky, John M.; Bradley, Thomas H.

2017-01-01

NASA's next generation space communications network will involve dynamic and autonomous services analogous to services provided by current terrestrial wireless networks. This architecture concept, known as the Space Mobile Network (SMN), is enabled by several technologies now in development. A pillar of the SMN architecture is the establishment and utilization of a continuous bidirectional control plane space link channel and a new User Initiated Service (UIS) protocol to enable more dynamic and autonomous mission operations concepts, reduced user space communications planning burden, and more efficient and effective provider network resource utilization. This paper provides preliminary results from the application of model driven architecture methodology to develop UIS. Such an approach is necessary to ensure systematic investigation of several open questions concerning the efficiency, robustness, interoperability, scalability and security of the control plane space link and UIS protocol.

Bidirectional Teleportation Protocol in Quantum Wireless Multi-hop Network

NASA Astrophysics Data System (ADS)

Cai, Rui; Yu, Xu-Tao; Zhang, Zai-Chen

2018-06-01

We propose a bidirectional quantum teleportation protocol based on a composite GHZ-Bell state. In this protocol, the composite GHZ-Bell state channel is transformed into two-Bell state channel through gate operations and single qubit measurements. The channel transformation will lead to different kinds of quantum channel states, so a method is proposed to help determine the unitary matrices effectively under different quantum channels. Furthermore, we discuss the bidirectional teleportation protocol in the quantum wireless multi-hop network. This paper is aimed to provide a bidirectional teleportation protocol and study the bidirectional multi-hop teleportation in the quantum wireless communication network.

Bidirectional Teleportation Protocol in Quantum Wireless Multi-hop Network

NASA Astrophysics Data System (ADS)

Cai, Rui; Yu, Xu-Tao; Zhang, Zai-Chen

2018-02-01

We propose a bidirectional quantum teleportation protocol based on a composite GHZ-Bell state. In this protocol, the composite GHZ-Bell state channel is transformed into two-Bell state channel through gate operations and single qubit measurements. The channel transformation will lead to different kinds of quantum channel states, so a method is proposed to help determine the unitary matrices effectively under different quantum channels. Furthermore, we discuss the bidirectional teleportation protocol in the quantum wireless multi-hop network. This paper is aimed to provide a bidirectional teleportation protocol and study the bidirectional multi-hop teleportation in the quantum wireless communication network.

A 25μm pitch LWIR focal plane array with pixel-level 15-bit ADC providing high well capacity and targeting 2mK NETD

NASA Astrophysics Data System (ADS)

Guellec, Fabrice; Peizerat, Arnaud; Tchagaspanian, Michael; de Borniol, Eric; Bisotto, Sylvette; Mollard, Laurent; Castelein, Pierre; Zanatta, Jean-Paul; Maillart, Patrick; Zecri, Michel; Peyrard, Jean-Christophe

2010-04-01

CEA Leti has recently developed a new readout IC (ROIC) with pixel-level ADC for cooled infrared focal plane arrays (FPAs). It operates at 50Hz frame rate in a snapshot Integrate-While-Read (IWR) mode. It targets applications that provide a large amount of integrated charge thanks to a long integration time. The pixel-level analog-to-digital conversion is based on charge packets counting. This technique offers a large well capacity that paves the way for a breakthrough in NETD performances. The 15 bits ADC resolution preserves the excellent detector SNR at full well (3Ge-). These characteristics are essential for LWIR FPAs as broad intra-scene dynamic range imaging requires high sensitivity. The ROIC, featuring a 320x256 array with 25μm pixel pitch, has been designed in a standard 0.18μm CMOS technology. The main design challenges for this digital pixel array (SNR, power consumption and layout density) are discussed. The IC has been hybridized to a LWIR detector fabricated using our in-house HgCdTe process. The first electro-optical test results of the detector dewar assembly are presented. They validate both the pixel-level ADC concept and its circuit implementation. Finally, the benefit of this LWIR FPA in terms of NETD performance is demonstrated.

Dissipative production of a maximally entangled steady state of two quantum bits.

PubMed

Lin, Y; Gaebler, J P; Reiter, F; Tan, T R; Bowler, R; Sørensen, A S; Leibfried, D; Wineland, D J

2013-12-19

Entangled states are a key resource in fundamental quantum physics, quantum cryptography and quantum computation. Introduction of controlled unitary processes--quantum gates--to a quantum system has so far been the most widely used method to create entanglement deterministically. These processes require high-fidelity state preparation and minimization of the decoherence that inevitably arises from coupling between the system and the environment, and imperfect control of the system parameters. Here we combine unitary processes with engineered dissipation to deterministically produce and stabilize an approximate Bell state of two trapped-ion quantum bits (qubits), independent of their initial states. Compared with previous studies that involved dissipative entanglement of atomic ensembles or the application of sequences of multiple time-dependent gates to trapped ions, we implement our combined process using trapped-ion qubits in a continuous time-independent fashion (analogous to optical pumping of atomic states). By continuously driving the system towards the steady state, entanglement is stabilized even in the presence of experimental noise and decoherence. Our demonstration of an entangled steady state of two qubits represents a step towards dissipative state engineering, dissipative quantum computation and dissipative phase transitions. Following this approach, engineered coupling to the environment may be applied to a broad range of experimental systems to achieve desired quantum dynamics or steady states. Indeed, concurrently with this work, an entangled steady state of two superconducting qubits was demonstrated using dissipation.

A Robust 96.6-dB-SNDR 50-kHz-Bandwidth Switched-Capacitor Delta-Sigma Modulator for IR Imagers in Space Instrumentation †

PubMed Central

Dei, Michele; Sutula, Stepan; Cisneros, Jose; Pun, Ernesto; Jansen, Richard Jan Engel; Terés, Lluís; Serra-Graells, Francisco

2017-01-01

Infrared imaging technology, used both to study deep-space bodies’ radiation and environmental changes on Earth, experienced constant improvements in the last few years, pushing data converter designers to face new challenges in terms of speed, power consumption and robustness against extremely harsh operating conditions. This paper presents a 96.6-dB-SNDR (Signal-to-Noise-plus-Distortion Ratio) 50-kHz-bandwidth fourth-order single-bit switched-capacitor delta-sigma modulator for ADC operating at 1.8 V and consuming 7.9 mW fit for space instrumentation. The circuit features novel Class-AB single-stage switched variable-mirror amplifiers (SVMAs) enabling low-power operation, as well as low sensitivity to both process and temperature deviations for the whole modulator. The physical implementation resulted in a 1.8-mm2 chip integrated in a standard 0.18-μm 1-poly-6-metal (1P6M) CMOS technology, and it reaches a 164.6-dB Schreier figure of merit from experimental SNDR measurements without making use of any clock bootstrapping, analog calibration, nor digital compensation technique. When coupled to a 2048×2048 IR imager, the current design allows more than 50 frames per minute with a resolution of 16 effective number of bits (ENOB) while consuming less than 300 mW. PMID:28574466

Wireless recording systems: from noninvasive EEG-NIRS to invasive EEG devices.

PubMed

Sawan, Mohamad; Salam, Muhammad T; Le Lan, Jérôme; Kassab, Amal; Gelinas, Sébastien; Vannasing, Phetsamone; Lesage, Frédéric; Lassonde, Maryse; Nguyen, Dang K

2013-04-01

In this paper, we present the design and implementation of a wireless wearable electronic system dedicated to remote data recording for brain monitoring. The reported wireless recording system is used for a) simultaneous near-infrared spectrometry (NIRS) and scalp electro-encephalography (EEG) for noninvasive monitoring and b) intracerebral EEG (icEEG) for invasive monitoring. Bluetooth and dual radio links were introduced for these recordings. The Bluetooth-based device was embedded in a noninvasive multichannel EEG-NIRS system for easy portability and long-term monitoring. On the other hand, the 32-channel implantable recording device offers 24-bit resolution, tunable features, and a sampling frequency up to 2 kHz per channel. The analog front-end preamplifier presents low input-referred noise of 5 μ VRMS and a signal-to-noise ratio of 112 dB. The communication link is implemented using a dual-band radio frequency transceiver offering a half-duplex 800 kb/s data rate, 16.5 mW power consumption and less than 10(-10) post-correction Bit-Error Rate (BER). The designed system can be accessed and controlled by a computer with a user-friendly graphical interface. The proposed wireless implantable recording device was tested in vitro using real icEEG signals from two patients with refractory epilepsy. The wirelessly recorded signals were compared to the original signals recorded using wired-connection, and measured normalized root-mean square deviation was under 2%.

All-digital pulse-expansion-based CMOS digital-to-time converter.

PubMed

Chen, Chun-Chi; Chu, Che-Hsun

2017-02-01

This paper presents a new all-digital CMOS digital-to-time converter (DTC) based on pulse expansion. Pulse expansion is achieved using an all-digital pulse-mixing scheme that can effectively improve the timing resolution and enable the DTC to be concise. Without requiring the Vernier principle or a costly digital-to-analog converter, the DTC comprises a pulse generator for generating a pulse, a pulse-expanding circuit (PEC) for programming timing generation, and a time subtractor for removing the time width of the pulse. The PEC comprises only a delay chain composed of proposed pulse-expanding units and a multiplexer. For accuracy enhancement, a pulse neutralization technique is presented to eliminate undesirable pulse variation. A 4-bit converter was fabricated in a 0.35-μm Taiwan Semiconductor Manufacturing Company CMOS process and had a small area of nearly 0.045 mm 2 . Six chips were tested, all of which exhibited an improved resolution (approximately 16 ps) and low integral nonlinearity (less than ±0.4 least significant bit). The power consumption was 0.2 mW when the sample rate was 1M samples/s and the voltage supply was 3.3 V. The proposed DTC not only has favorable cost and power but also achieves an acceptable resolution without requiring an advanced CMOS process. This study is the first to use pulse expansion in digital-to-time conversion.

All-digital pulse-expansion-based CMOS digital-to-time converter

NASA Astrophysics Data System (ADS)

Chen, Chun-Chi; Chu, Che-Hsun

2017-02-01

This paper presents a new all-digital CMOS digital-to-time converter (DTC) based on pulse expansion. Pulse expansion is achieved using an all-digital pulse-mixing scheme that can effectively improve the timing resolution and enable the DTC to be concise. Without requiring the Vernier principle or a costly digital-to-analog converter, the DTC comprises a pulse generator for generating a pulse, a pulse-expanding circuit (PEC) for programming timing generation, and a time subtractor for removing the time width of the pulse. The PEC comprises only a delay chain composed of proposed pulse-expanding units and a multiplexer. For accuracy enhancement, a pulse neutralization technique is presented to eliminate undesirable pulse variation. A 4-bit converter was fabricated in a 0.35-μ m Taiwan Semiconductor Manufacturing Company CMOS process and had a small area of nearly 0.045 mm2. Six chips were tested, all of which exhibited an improved resolution (approximately 16 ps) and low integral nonlinearity (less than ±0.4 least significant bit). The power consumption was 0.2 mW when the sample rate was 1M samples/s and the voltage supply was 3.3 V. The proposed DTC not only has favorable cost and power but also achieves an acceptable resolution without requiring an advanced CMOS process. This study is the first to use pulse expansion in digital-to-time conversion.

Small-area low-power heart condition monitoring system using dual-mode SAR-ADC for low-cost wearable healthcare systems.

PubMed

Shin, Young-San; Wee, Jae-Kyung; Song, Inchae; Lee, Seongsoo

2015-01-01

Heart rate monitoring is useful to detect many cardiovascular diseases. It can be implemented in a small device with low power consumption, and it can exploit low-cost piezoelectric pressure sensors to measure heart rate. However, it is also desirable to transmit heartbeat waveform for emergency treatment, which significantly increases transmission power. In this paper, a low-cost wireless heart condition monitoring SoC is proposed. It can monitor and transmit both heart rate and heartbeat waveform, but the hardware is extremely simplified to achieve in a small package. By slight modification of successive-approximation analog-digital converter, it can count heart rate and read out heartbeat waveform with the same hardware. In the normal mode, only an 8-bit heart rate is transmitted for power reduction. If the heart rate is out of a given range, it goes to the emergency mode and a 10-bit heartbeat waveform is transmitted for fast treatment. The fabricated chip size is 1.1 mm2 in 0.11 μ m CMOS technology, including the radio-frequency transmitter. The measured power consumption is 161.8 μ W in normal mode and 507.3 μ W in emergency mode, respectively. The proposed SoC achieves low-cost, small area, and low-power. It is useful as part of a disposable healthcare system.

Acquisition de donnees a haute resolution et faible latence dediee aux capteurs avioniques de position

NASA Astrophysics Data System (ADS)

Koubaa, Zied

The communication network and the detection mechanisms are two critical systems in a plane. Their performance has a direct impact on aircrafts. This is of particular interest for avionics designers, who have increasingly invested more and more in the development of these elements. As a part of a project in this domain, we introduce the design and the development of a smart interface for position sensors dedicated to flights (Smart Sensor Interface - SSI). This interface will serve to connect sensors of different technologies (electromagnetic, optical and MEMS) to the new communication network, AFDX. The role of this interface is to generate an appropriate excitation signal for certain types of sensors (R/LVDT), and to treat, demodulate, and digitize their output signals. The proposed interface is thus composed of a Signal Acquisition Path (SAP) and an Excitation Signal Generation (ESG). By adopting the Integrated Modular Avionics architecture (IMA), we can minimize the size of the classic interface, reduce its energy consumption and improve its reliability and its performance. The focus of our design is particularly on the Data Acquisition Path (DAP). An Architecture characterized by a high resolution (14 bits) and a low latency (1.2 ms) of this module is introduced and developed in this prestigious work. This architecture was developed after a wellconducted study of existing solutions found in literature work and a detailed analysis of the problems arise in the design and implementation of this system (DAP). The conversion of the sensor signal into a digital signal is the most important step in acquiring data, as it sets the resolution of the acquired information and generates the majority of its latency. This module can also affect the reliability and stability of the system. Among different models and architectures, the Delta-Sigma analog-to-digital converter (ADC) is preferred for this application (for better resolution). This converter is formed by an analog circuit (modulator) followed by digital filters. The complexity of the implementation, the processing delay and the output resolution are all susceptible to change depending on the architecture of these filters. Thus, the main problem while designing such a system arises in the opposing evolution of the resolution and latency parameters; the improvement or evolution of one, results in the destruction of the other. Therefore, our work aims to provide one or more method to optimize the latency caused by the CAN while maintaining the same resolution of the desired data (14 bits). This optimization takes into account the objective of integrating the DAP in modules of small size and low power consumption. This proposed solution was implemented in order to validate the design of the conception of the interface. We are also interested to achieve the proposed solution and validate our design. The obtained results will be evaluated after following the manufacturing strategy. The data acquisition unit is made up of two electronic components. The first component is an integrated circuit, which uses CMOS 0.13mum IBM technology and contains the analog part of CAN (SigmaDelta modulator). The second component is a Virtex-6 FPGA, which allows one to acquire the necessary digital processing required for the acquisition and conversion of the sensor signal. In the final version of the interface, our analog portion will be integrated with the analog portion of GSE in the same chip. The integrated digital logic in the (FPGA) role will thus provide digital data to the ESG module in order to generate the excitation signal.

Generalized model of a bidirectional DC-DC converter

NASA Astrophysics Data System (ADS)

Hinov, Nikolay; Arnaudov, Dimitar; Penev, Dimitar

2017-12-01

The following paperwork presents models of bidirectional converters. A classic bidirectional converter and a new bidirectional circuit based on a ZCS resonant converter are investigated and compared. The developed models of these converters allow comparison between their characteristics showing their advantages and disadvantages. The models allow precise models of energy storage elements to be implemented as well, which is useful for examination of energy storage systems.

A Concurrent Smalltalk Compiler for the Message-Driven Processor

DTIC Science & Technology

1988-05-01

apj with bits from low-bit (inclusive) to high-bit (exclusive) set. ;;;Low-bit defaults to zero. (defmacro brange (high-bit &optional low-bit) (list...n2) (null (cddr num))) (aetg bits (b+ bits (if (>- nl n2) ( brange (1+ nl) n2) ( brange (1+ n2) ni)))) (error "Bad bmap range: -S" flu.)))) (t (error...vlocs) flat ((vlive (b- finst-vllv* mast) *I.( brange firat-context-slot-nun))) (next (inst-next last))) (if (bempty vlive) (delete-module module inat

Effects of plastic bits on the condition and behaviour of captive-reared pheasants.

PubMed

Butler, D A; Davis, C

2010-03-27

Between 2005 and 2007, data were collected from game farms across England and Wales to examine the effects of the use of bits on the physiological condition and behaviour of pheasants. On each site, two pheasant pens kept in the same conditions were randomly allocated to either use bits or not. The behaviour and physiological conditions of pheasants in each treatment pen were assessed on the day of bitting and weekly thereafter until release. Detailed records of feed usage, medications and mortality were also kept. Bits halved the number of acts of bird-on-bird pecking, but they doubled the incidence of headshaking and scratching. Bits caused nostril inflammation and bill deformities in some birds, particularly after seven weeks of age. In all weeks after bitting, feather condition was poorer in non-bitted pheasants than in those fitted with bits. Less than 3 per cent of bitted birds had damaged skin, but in the non-bitted pens this figure increased over time to 23 per cent four weeks later. Feed use and mortality did not differ between bitted and non-bitted birds.

New PDC bit design reduces vibrational problems

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mensa-Wilmot, G.; Alexander, W.L.

1995-05-22

A new polycrystalline diamond compact (PDC) bit design combines cutter layout, load balancing, unsymmetrical blades and gauge pads, and spiraled blades to reduce problematic vibrations without limiting drilling efficiency. Stabilization improves drilling efficiency and also improves dull characteristics for PDC bits. Some PDC bit designs mitigate one vibrational mode (such as bit whirl) through drilling parameter manipulation yet cause or excite another vibrational mode (such as slip-stick). An alternative vibration-reducing concept which places no limitations on the operational environment of a PDC bit has been developed to ensure optimization of the bit`s available mechanical energy. The paper discusses bit stabilization,more » vibration reduction, vibration prevention, cutter arrangement, load balancing, blade layout, spiraled blades, and bit design.« less

How many pixels does it take to make a good 4"×6" print? Pixel count wars revisited

NASA Astrophysics Data System (ADS)

Kriss, Michael A.

2011-01-01

In the early 1980's the future of conventional silver-halide photographic systems was of great concern due to the potential introduction of electronic imaging systems then typified by the Sony Mavica analog electronic camera. The focus was on the quality of film-based systems as expressed in the number of equivalent number pixels and bits-per-pixel, and how many pixels would be required to create an equivalent quality image from a digital camera. It was found that 35-mm frames, for ISO 100 color negative film, contained equivalent pixels of 12 microns for a total of 18 million pixels per frame (6 million pixels per layer) with about 6 bits of information per pixel; the introduction of new emulsion technology, tabular AgX grains, increased the value to 8 bit per pixel. Higher ISO speed films had larger equivalent pixels, fewer pixels per frame, but retained the 8 bits per pixel. Further work found that a high quality 3.5" x 5.25" print could be obtained from a three layer system containing 1300 x 1950 pixels per layer or about 7.6 million pixels in all. In short, it became clear that when a digital camera contained about 6 million pixels (in a single layer using a color filter array and appropriate image processing) that digital systems would challenge and replace conventional film-based system for the consumer market. By 2005 this became the reality. Since 2005 there has been a "pixel war" raging amongst digital camera makers. The question arises about just how many pixels are required and are all pixels equal? This paper will provide a practical look at how many pixels are needed for a good print based on the form factor of the sensor (sensor size) and the effective optical modulation transfer function (optical spread function) of the camera lens. Is it better to have 16 million, 5.7-micron pixels or 6 million 7.8-micron pixels? How does intrinsic (no electronic boost) ISO speed and exposure latitude vary with pixel size? A systematic review of these issues will be provided within the context of image quality and ISO speed models developed over the last 15 years.

Critique of a Hughes shuttle Ku-band data sampler/bit synchronizer

NASA Technical Reports Server (NTRS)

Holmes, J. K.

1980-01-01

An alternative bit synchronizer proposed for shuttle was analyzed in a noise-free environment by considering the basic operation of the loop via timing diagrams and by linearizing the bit synchronizer as an equivalent, continuous, phased-lock loop (PLL). The loop is composed of a high-frequency phase-frequency detector which is capable of detecting both phase and frequency errors and is used to track the clock, and a bit transition detector which attempts to track the transitions of the data bits. It was determined that the basic approach was a good design which, with proper implementation of the accumulator, up/down counter and logic should provide accurate mid-bit sampling with symmetric bits. However, when bit asymmetry occurs, the bit synchronizer can lock up with a large timing error, yet be quasi-stable (timing will not change unless the clock and bit sequence drift). This will result in incorrectly detecting some bits.

Development of a dedicated readout ASIC for TPC based X-ray polarimeter

NASA Astrophysics Data System (ADS)

Zhang, Hongyan; Deng, Zhi; Li, Hong; Liu, Yinong; Feng, Hua

2016-07-01

X-ray polarimetry with time projection chambers was firstly proposed by JK Black in 2007 and has been greatly developed since then. It measured two dimensional photoelectron tracks with one dimensional strip and the other dimension was estimated by the drift time from the signal waveforms. A readout ASIC, APV25, originally developed for CMS silicon trackers was used and has shown some limitations such as waveform sampling depth. A dedicated ASIC was developed for TPC based X-ray polarimeters in this paper. It integrated 32 channel circuits and each channel consisted of an analog front-end and a waveform sampler based on switched capacitor array. The analog front-end has a charge sensitive preamplifier with a gain of 25 mV/fC, a CR-RC shaper with a peaking time of 25 ns, a baseline holder and a discriminator for self-triggering. The SCA has a buffer latency of 3.2 μs with 64 cells operating at 20 MSPS. The ASIC was fabricated in a 0.18 μm CMOS process. The equivalent noise charge (ENC) of the analog front-end was measured to be 274.8 e+34.6 e/pF. The effective resolution of the SCA was 8.8 bits at sampling rate up to 50 MSPS. The total power consumption was 2.8 mW per channel. The ASIC was also tested with real TPC detectors and two dimensional photoelectron tracks have been successfully acquired. More tests and analysis on the sensitivity to the polarimetry are undergoing and will be presented in this paper.

GLAST Burst Monitor Signal Processing System

NASA Astrophysics Data System (ADS)

Bhat, P. Narayana; Briggs, Michael; Connaughton, Valerie; Diehl, Roland; Fishman, Gerald; Greiner, Jochen; Kippen, R. Marc; von Kienlin, Andreas; Kouveliotou, Chryssa; Lichti, Giselher; Meegan, Charles; Paciesas, William; Persyn, Steven; Preece, Robert; Steinle, Helmut; Wilson-Hodge, Colleen

2007-07-01

The onboard Data Processing Unit (DPU), designed and built by Southwest Research Institute, performs the high-speed data acquisition for GBM. The analog signals from each of the 14 detectors are digitized by high-speed multichannel analog data acquisition architecture. The streaming digital values resulting from a periodic (period of 104.2 ns) sampling of the analog signal by the individual ADCs are fed to a Field-Programmable Gate Array (FPGA). Real-time Digital Signal Processing (DSP) algorithms within the FPGA implement functions like filtering, thresholding, time delay and pulse height measurement. The spectral data with a 12-bit resolution are formatted according to the commandable look-up-table (LUT) and then sent to the High-Speed Science-Date Bus (HSSDB, speed=1.5 MB/s) to be telemetered to ground. The DSP offers a novel feature of a commandable & constant event deadtime. The ADC non-linearities have been calibrated so that the spectral data can be corrected during analysis. The best temporal resolution is 2 μs for the pre-burst & post-trigger time-tagged events (TTE) data. The time resolution of the binned data types is commandable from 64 msec to 1.024 s for the CTIME data (8 channel spectral resolution) and 1.024 to 32.768 s for the CSPEC data (128 channel spectral resolution). The pulse pile-up effects have been studied by Monte Carlo simulations. For a typical GRB, the possible shift in the Epeak value at high-count rates (~100 kHz) is ~1% while the change in the single power-law index could be up to 5%.

Advanced technology satellite demodulator development

NASA Technical Reports Server (NTRS)

Ames, Stephen A.

1989-01-01

Ford Aerospace has developed a proof-of-concept satellite 8 phase shift keying (PSK) modulation and coding system operating in the Time Division Multiple Access (TDMA) mode at a data range of 200 Mbps using rate 5/6 forward error correction coding. The 80 Msps 8 PSK modem was developed in a mostly digital form and is amenable to an ASIC realization in the next phase of development. The codec was developed as a paper design only. The power efficiency goal was to be within 2 dB of theoretical at a bit error rate (BER) of 5x10(exp 7) while the measured implementation loss was 4.5 dB. The bandwidth efficiency goal was 2 bits/sec/Hz while the realized bandwidth efficiency was 1.8 bits/sec/Hz. The burst format used a preamble of only 40 8 PSK symbol times including 32 symbols of all zeros and an eight symbol unique word. The modem and associated special test equipment (STE) were fabricated mostly on a specially designed stitch-weld board although a few of the highest rate circuits were built on printed circuit cards. All the digital circuits were ECL to support the clock rates of from 80 MHz to 360 MHz. The transmitter and receiver matched filters were square-root Nyquist bandpass filters realized at the 3.37 GHz i.f. The modem operated as a coherent system although no analog phase locked (PLL) loop was employed. Within the budgetary constraints of the program, the approach to the demodulator has been proven and is eligible to proceed to the next phase of development of a satellite demodulator engineering model. This would entail the development of an ASIC version of the digital portion of the demodulator, and MMIC version of the quadrature detector, and SAW Nyquist filters to realize the bandwidth efficiency.

Universal sensor interface module (USIM)

NASA Astrophysics Data System (ADS)

King, Don; Torres, A.; Wynn, John

1999-01-01

A universal sensor interface model (USIM) is being developed by the Raytheon-TI Systems Company for use with fields of unattended distributed sensors. In its production configuration, the USIM will be a multichip module consisting of a set of common modules. The common module USIM set consists of (1) a sensor adapter interface (SAI) module, (2) digital signal processor (DSP) and associated memory module, and (3) a RF transceiver model. The multispectral sensor interface is designed around a low-power A/D converted, whose input/output interface consists of: -8 buffered, sampled inputs from various devices including environmental, acoustic seismic and magnetic sensors. The eight sensor inputs are each high-impedance, low- capacitance, differential amplifiers. The inputs are ideally suited for interface with discrete or MEMS sensors, since the differential input will allow direct connection with high-impedance bridge sensors and capacitance voltage sources. Each amplifier is connected to a 22-bit (Delta) (Sigma) A/D converter to enable simultaneous samples. The low power (Delta) (Sigma) converter provides 22-bit resolution at sample frequencies up to 142 hertz (used for magnetic sensors) and 16-bit resolution at frequencies up to 1168 hertz (used for acoustic and seismic sensors). The video interface module is based around the TMS320C5410 DSP. It can provide sensor array addressing, video data input, data calibration and correction. The processor module is based upon a MPC555. It will be used for mode control, synchronization of complex sensors, sensor signal processing, array processing, target classification and tracking. Many functions of the A/D, DSP and transceiver can be powered down by using variable clock speeds under software command or chip power switches. They can be returned to intermediate or full operation by DSP command. Power management may be based on the USIM's internal timer, command from the USIM transceiver, or by sleep mode processing management. The low power detection mode is implemented by monitoring any of the sensor analog outputs at lower sample rates for detection over a software controllable threshold.

Application of Field System-FS9 and a PC to Antenna Control Unit interface in Radio Astronomy in Peru

NASA Astrophysics Data System (ADS)

Vidal, E. V. S.; Ishitsuka, J. I. I.; Koyama, K. Y.

2006-08-01

We are in the process to transform a 32m antenna in Peru, used for telecommunications, into a Radio Telescope to perform Radio Astronomy in Peru. The 32m antenna of Peru constructed by NEC was used for telecommunications with communications satellites at 6 GHz for transmission, and 4 GHz for reception. In collaboration of National Institute of Information and Communications Technology (NICT) Japan, and National Observatory of Japan we developed an Antenna Control System for the 32m antenna in Peru. It is based on the Field System FS9, software released by NASA for VLBI station, and an interface to link PC within FS9 software (PC-FS9) and Antenna Control Unit (ACU) of the 32 meters antenna. The PC-FS9 controls the antenna, commands are translated by interface into control signals compatibles with the ACU using: an I/O digital card with two 20bits ports to read azimuth and elevation angles, one 16bits port for reading status of ACU, one 24bits port to send pulses to start or stop operations of antenna, two channels are analogic outputs to drive the azimuth and elevation motors of the antenna, a LCD display to show the status of interface and error messages, and one serial port for communications with PC-FS9,. The first experiment of the control system was made with 11m parabolic antenna of Kashima Space Research Center (NICT), where we tested the right working of the routines implemented for de FS9 software, and simulations was made with looped data between output and input of the interface, both test were done successfully. With this scientific instrument we will be able to contribute with researching of astrophysics. We expect to into a near future to work at 6.7GHz to study Methanol masers, and higher frequencies with some improvements of the surface of the dish.

Bit-1 is an essential regulator of myogenic differentiation

PubMed Central

Griffiths, Genevieve S.; Doe, Jinger; Jijiwa, Mayumi; Van Ry, Pam; Cruz, Vivian; de la Vega, Michelle; Ramos, Joe W.; Burkin, Dean J.; Matter, Michelle L.

2015-01-01

Muscle differentiation requires a complex signaling cascade that leads to the production of multinucleated myofibers. Genes regulating the intrinsic mitochondrial apoptotic pathway also function in controlling cell differentiation. How such signaling pathways are regulated during differentiation is not fully understood. Bit-1 (also known as PTRH2) mutations in humans cause infantile-onset multisystem disease with muscle weakness. We demonstrate here that Bit-1 controls skeletal myogenesis through a caspase-mediated signaling pathway. Bit-1-null mice exhibit a myopathy with hypotrophic myofibers. Bit-1-null myoblasts prematurely express muscle-specific proteins. Similarly, knockdown of Bit-1 expression in C2C12 myoblasts promotes early differentiation, whereas overexpression delays differentiation. In wild-type mice, Bit-1 levels increase during differentiation. Bit-1-null myoblasts exhibited increased levels of caspase 9 and caspase 3 without increased apoptosis. Bit-1 re-expression partially rescued differentiation. In Bit-1-null muscle, Bcl-2 levels are reduced, suggesting that Bcl-2-mediated inhibition of caspase 9 and caspase 3 is decreased. Bcl-2 re-expression rescued Bit-1-mediated early differentiation in Bit-1-null myoblasts and C2C12 cells with knockdown of Bit-1 expression. These results support an unanticipated yet essential role for Bit-1 in controlling myogenesis through regulation of Bcl-2. PMID:25770104

Implementation of integrated circuit and design of SAR ADC for fully implantable hearing aids.

PubMed

Kim, Jong Hoon; Lee, Jyung Hyun; Cho, Jin-Ho

2017-07-20

The hearing impaired population has been increasing; many people suffer from hearing problems. To deal with this difficulty, various types of hearing aids are being rapidly developed. In particular, fully implantable hearing aids are being actively studied to improve the performance of existing hearing aids and to reduce the stigma of hearing loss patients. It has to be of small size and low-power consumption for easy implantation and long-term use. The objective of the study was to implement a small size and low-power consumption successive approximation register analog-to-digital converter (SAR ADC) for fully implantable hearing aids. The ADC was selected as the SAR ADC because its analog circuit components are less required by the feedback circuit of the SAR ADC than the sigma-delta ADC which is conventionally used in hearing aids, and it has advantages in the area and power consumption. So, the circuit of SAR ADC is designed considering the speech region of humans because the objective is to deliver the speech signals of humans to hearing loss patients. If the switch of sample and hold works in the on/off positions, the charge injection and clock feedthrough are produced by a parasitic capacitor. These problems affect the linearity of the hold voltage, and as a result, an error of the bit conversion is generated. In order to solve the problem, a CMOS switch that consists of NMOS and PMOS was used, and it reduces the charge injection because the charge carriers in the NMOS and PMOS have inversed polarity. So, 16 bit conversion is performed before the occurrence of the Least Significant Bit (LSB) error. In order to minimize the offset voltage and power consumption of the designed comparator, we designed a preamplifier with current mirror. Therefore, the power consumption was reduced by the power control switch used in the comparator. The layout of the designed SAR ADC was performed by Virtuoso Layout Editor (Cadence, USA). In the layout result, the size of the designed SAR ADC occupied 124.9 μm × 152.1 μm. The circuit verification was performed by layout versus schematic (LVS) and design rule check (DRC) which are provided by Calibre (Mentor Graphics, USA), and it was confirmed that there was no error. The designed SAR ADC was implemented in SMIC 180 nm CMOS technology. The operation of the manufactured SAR ADC was confirmed by using an oscilloscope. The SAR ADC output was measured using a distortion meter (HM 8027), when applying pure tone sounds of 94 dB SPL at 500, 800, and 1600 Hz regions. As a result, the THD performance of the proposed chip was satisfied with the ANSI. s3. 22. 2003 standard. We proposed a low-power 16-bit 32 kHz SAR ADC for fully implantable hearing aids. The manufactured SAR ADC based on this design was confirmed to have advantages in power consumption and size through the comparison with the conventional ADC. Therefore, the manufactured SAR ADC is expected to be used in the implantable medical device field and speech signal processing field, which require small size and low power consumption.

Micromachined Silicon Stimulating Probes with CMOS Circuitry for Use in the Central Nervous System

NASA Astrophysics Data System (ADS)

Tanghe, Steven John

1992-01-01

Electrical stimulation in the central nervous system is a valuable technique for studying neural systems and is a key element in the development of prostheses for deafness and other disorders. This thesis presents a family of multielectrode probe structures, fulfilling the need for chronic multipoint stimulation tools essential for interfacing to the highly complex neural networks in the brain. These probes are batch-fabricated on silicon wafers, employing photoengraving techniques to precisely control the electrode site and array geometries and to allow the integration of on-chip CMOS circuitry for signal multiplexing and stimulus current generation. Silicon micromachining is used to define the probe shapes, which have typical shank dimensions of 3 mm in length by 100 mu m in width by 15 μm in thickness. Each shank supports up to eight planar iridium oxide electrode sites capable of delivering charge densities in excess of 3 mC/cm^2 during current pulse stimulation. Three active probe circuits have been designed with varied complexity and capability. All three can deliver biphasic stimulus currents through 16 sites using only 5 external leads, and they are all compatible with the same external control system. The most complex design interprets site addresses and stimulus current amplitudes from 16-bit words shifted into the probe at 4 MHz. Sixteen on-chip, biphasic, 8-bit digital-to-analog converters deliver analog stimulus currents in the range of +/- 254 muA to any combination of electrode sites. These DACs exhibit full-scale internal linearity to better than +/-1/2 LSB and can be calibrated by varying the positive power supply voltage. The entire probe circuit dissipates only 80 muW from +/-5 V supplies when not delivering stimulus currents, it includes several safety features, and is testable from the input pads. Test results from the fabricated circuits indicate that they all function properly at clocking frequencies as high as 10 MHz, meeting or exceeding all design specifications. Probe structures without circuitry have been used for stimulation experiments in guinea pigs yielding excellent results.

A Type of Non-cable Self-Posioning Seismograph Served For SinoProbe Project In China

NASA Astrophysics Data System (ADS)

Yang, H.; Lin, J.; Chen, Z.; Zhang, L.; Huaizhu, Z.; Zheng, F.; Seismic Instrument Design Team

2011-12-01

A type of cableless self-positioning telemetry seismograph designed for deep exploration is introduced in this article. The seismograph adopts 24-bit ADC and the analog circuits are designed carefully to attain a low noise level of 300nV RMS. It also uses 24-bit DAC and FPGA circuits to perform self-test including noise level, trace crosstalk, CMRR, harmonic distortion, geophone resitor testing, pulse testing, gain calibration and etc. As the testing result shows, the analog acquisition performances are similar to the most popular seismograph 428XL system from Sercel. However, the seismograph has a different structure with 428XL. It gets rid of cables and stores seismic data in mass non-volatile memory, and meanwhile it employs GPS combined with Compass global navigation satellite system to implement synchronous data aquisiton and self-positioning. In addition, the seismograph has a built-in WiFi module and can communicate with a cental server in Ad-hoc mode or AP mode depending on the distance between the seismograph and the central server. The working status and seismic data quality can be monitored through the WiFi network and some seismic data can be transmitted back on demand. When the distance between adjacent seismographs exceed 500 metres, the Compass global navigation satellite system which supports global communication can be used to send necessary data. At last, dynamic power management is emplyed and the system working voltage and frequency will be changed as the system runs into different status, and also all circuit modules can be switched off when not needed. Because of all the benefits listed above, the seismograph can be used in a variety of ways as needed, such as seismic network, deep seismic reflection exploration, wide-angle seismic reflection and refraction exploration, ore zone seismic exploration and etc. To sum up, the cable-less self-positioning seismograph employs mass non-volatile storage technology, global navigation satellite sytem, WiFi modules and dynamic power management technology to attain a flexible data acquisition system suitable for most of the seismic deep exploration in SinoProbe launched in China.

Research of built-in self test technology on cable-free self-positioning seismograph

NASA Astrophysics Data System (ADS)

Huaizhu, Z.; Lin, J.; Chen, Z.; Zhang, L.; Yang, H.; Zheng, F.

2011-12-01

Cable-free self-positioning seismograph is the key instrument and equipment required for deep seismic exploration in China. In order to measure the performance of seismic data acquisition systems whether meet exploration requirements , to ensure the accuracy of seismic data, and to ensure equipment reliability and stability, a built-in self test solution of the cable-free self-positioning seismic recorder is provided. Within a 24-bits Σ-Δ DAC, the seismograph can produce sine, step, pulse and other high-precision analog test signal, with dynamic range of 120dB or more, through the FPGA to control the analog multiplexer switching the input signal acquisition channels, and start the 24-bit Σ-Δ ADC in the instrument internal simultaneously to acquisition the test signal data, carries on the fast Fournier transformation by instrument internal CPU, to achieve the instrument of analysis and calculation of performance indicators, including: the equivalent noise and drift, common mode rejection ratio (CMRR), crosstalk, harmonic distortion, dynamic range, channel response consistency, detector impulse response , etc. A lot of testing experiments about the various parameters were performed and studied currently. By setting different sampling rate (1Hz, 5Hz, ..., 4kHz), each of the measurement system noise level was measured, and the maximum noise is about 0.5μV; the crosstalk between channels was tested using the 31.25Hz sine wave, the result is more than-120dB with sampling rate of 1kHz; the harmonic distortion was measured by adding the high-precision sine wave signals of different frequencies, such as 500Hz, 250 Hz, 125 Hz, 62.5 Hz, 31.25 Hz, 15.625 Hz, 7.812 Hz, 3.90625Hz, etc. the calculated results is in-118dB or more. The experimental results show that, the parameters of the cable-free self-positioning of the seismic recorder meet the technical requirements for the deep exploration, compared to the corresponding parameters with the 428XL seismograph of the French Sercel company, the instrument in performance has reached the advanced level of overseas equipment.

A portable battery powered microfluidic impedance cytometer with smartphone readout: towards personal health monitoring.

PubMed

Talukder, Niloy; Furniturewalla, Abbas; Le, Tuan; Chan, Matthew; Hirday, Shreyas; Cao, Xinnan; Xie, Pengfei; Lin, Zhongtian; Gholizadeh, Azam; Orbine, Steve; Javanmard, Mehdi

2017-06-01

We present a portable system for personalized blood cell counting consisting of a microfluidic impedance cytometer and portable analog readout electronics, feeding into an analog-to-digital converter (ADC), and being transmitted via Bluetooth to a user-accessible mobile application. We fabricated a microfluidic impedance cytometer with a novel portable analog readout. The novel design of the analog readout, which consists of a lock-in-amplifier followed by a high-pass filter stage for subtraction of drift and DC offset, and a post-subtraction high gain stage, enables detection of particles and cells as small as 1 μm in diameter, despite using a low-end 8-bit ADC. The lock-in-amplifier and the ADC were set up to receive and transmit data from a Bluetooth module. In order to initiate the system, as well as to transmit all of the data, a user friendly mobile application was developed, and a proof-of-concept trial was run on a blood sample. Applications such as personalized health monitoring require robust device operation and resilience to clogging. It is desirable to avoid using channels comparable in size to the particles being detected thus requiring high levels of sensitivity. Despite using low-end off-the-shelf hardware, our sensing platform was capable of detecting changes in impedance as small as 0.032%, allowing detection of 3 μm diameter particles in a 300 μm wide channel. The sensitivity of our system is comparable to that of a high-end bench-top impedance spectrometer when tested using the same sensors. The novel analog design allowed for an instrument with a footprint of less than 80 cm 2 . The aim of this work is to demonstrate the potential of using microfluidic impedance spectroscopy for low cost health monitoring. We demonstrated the utility of the platform technology towards cell counting, however, our platform is broadly applicable to assaying wide panels of biomarkers including proteins, nucleic acids, and various cell types.

A Statistical Theory of Bidirectionality

NASA Technical Reports Server (NTRS)

DeLoach, Richard; Ulbrich, Norbert

2013-01-01

Original concepts related to the quantification and assessment of bidirectionality in strain-gage balances were introduced by Ulbrich in 2012. These concepts are extended here in three ways: 1) the metric originally proposed by Ulbrich is normalized, 2) a categorical variable is introduced in the regression analysis to account for load polarity, and 3) the uncertainty in both normalized and non-normalized bidirectionality metrics is quantified. These extensions are applied to four representative balances to assess the bidirectionality characteristics of each. The paper is tutorial in nature, featuring reviews of certain elements of regression and formal inference. Principal findings are that bidirectionality appears to be a common characteristic of most balance outputs and that unless it is taken into account, it is likely to consume the entire error budget of a typical balance calibration experiment. Data volume and correlation among calibration loads are shown to have a significant impact on the precision with which bidirectionality metrics can be assessed.

Improved Iris Recognition through Fusion of Hamming Distance and Fragile Bit Distance.

PubMed

Hollingsworth, Karen P; Bowyer, Kevin W; Flynn, Patrick J

2011-12-01

The most common iris biometric algorithm represents the texture of an iris using a binary iris code. Not all bits in an iris code are equally consistent. A bit is deemed fragile if its value changes across iris codes created from different images of the same iris. Previous research has shown that iris recognition performance can be improved by masking these fragile bits. Rather than ignoring fragile bits completely, we consider what beneficial information can be obtained from the fragile bits. We find that the locations of fragile bits tend to be consistent across different iris codes of the same eye. We present a metric, called the fragile bit distance, which quantitatively measures the coincidence of the fragile bit patterns in two iris codes. We find that score fusion of fragile bit distance and Hamming distance works better for recognition than Hamming distance alone. To our knowledge, this is the first and only work to use the coincidence of fragile bit locations to improve the accuracy of matches.

BIT BY BIT: A Game Simulating Natural Language Processing in Computers

ERIC Educational Resources Information Center

Kato, Taichi; Arakawa, Chuichi

2008-01-01

BIT BY BIT is an encryption game that is designed to improve students' understanding of natural language processing in computers. Participants encode clear words into binary code using an encryption key and exchange them in the game. BIT BY BIT enables participants who do not understand the concept of binary numbers to perform the process of…

Bit selection using field drilling data and mathematical investigation

NASA Astrophysics Data System (ADS)

Momeni, M. S.; Ridha, S.; Hosseini, S. J.; Meyghani, B.; Emamian, S. S.

2018-03-01

A drilling process will not be complete without the usage of a drill bit. Therefore, bit selection is considered to be an important task in drilling optimization process. To select a bit is considered as an important issue in planning and designing a well. This is simply because the cost of drilling bit in total cost is quite high. Thus, to perform this task, aback propagation ANN Model is developed. This is done by training the model using several wells and it is done by the usage of drilling bit records from offset wells. In this project, two models are developed by the usage of the ANN. One is to find predicted IADC bit code and one is to find Predicted ROP. Stage 1 was to find the IADC bit code by using all the given filed data. The output is the Targeted IADC bit code. Stage 2 was to find the Predicted ROP values using the gained IADC bit code in Stage 1. Next is Stage 3 where the Predicted ROP value is used back again in the data set to gain Predicted IADC bit code value. The output is the Predicted IADC bit code. Thus, at the end, there are two models that give the Predicted ROP values and Predicted IADC bit code values.

Investigation of PDC bit failure base on stick-slip vibration analysis of drilling string system plus drill bit

NASA Astrophysics Data System (ADS)

Huang, Zhiqiang; Xie, Dou; Xie, Bing; Zhang, Wenlin; Zhang, Fuxiao; He, Lei

2018-03-01

The undesired stick-slip vibration is the main source of PDC bit failure, such as tooth fracture and tooth loss. So, the study of PDC bit failure base on stick-slip vibration analysis is crucial to prolonging the service life of PDC bit and improving ROP (rate of penetration). For this purpose, a piecewise-smooth torsional model with 4-DOF (degree of freedom) of drilling string system plus PDC bit is proposed to simulate non-impact drilling. In this model, both the friction and cutting behaviors of PDC bit are innovatively introduced. The results reveal that PDC bit is easier to fail than other drilling tools due to the severer stick-slip vibration. Moreover, reducing WOB (weight on bit) and improving driving torque can effectively mitigate the stick-slip vibration of PDC bit. Therefore, PDC bit failure can be alleviated by optimizing drilling parameters. In addition, a new 4-DOF torsional model is established to simulate torsional impact drilling and the effect of torsional impact on PDC bit's stick-slip vibration is analyzed by use of an engineering example. It can be concluded that torsional impact can mitigate stick-slip vibration, prolonging the service life of PDC bit and improving drilling efficiency, which is consistent with the field experiment results.

An Over 90 dB Intra-Scene Single-Exposure Dynamic Range CMOS Image Sensor Using a 3.0 μm Triple-Gain Pixel Fabricated in a Standard BSI Process.

PubMed

Takayanagi, Isao; Yoshimura, Norio; Mori, Kazuya; Matsuo, Shinichiro; Tanaka, Shunsuke; Abe, Hirofumi; Yasuda, Naoto; Ishikawa, Kenichiro; Okura, Shunsuke; Ohsawa, Shinji; Otaka, Toshinori

2018-01-12

To respond to the high demand for high dynamic range imaging suitable for moving objects with few artifacts, we have developed a single-exposure dynamic range image sensor by introducing a triple-gain pixel and a low noise dual-gain readout circuit. The developed 3 μm pixel is capable of having three conversion gains. Introducing a new split-pinned photodiode structure, linear full well reaches 40 ke - . Readout noise under the highest pixel gain condition is 1 e - with a low noise readout circuit. Merging two signals, one with high pixel gain and high analog gain, and the other with low pixel gain and low analog gain, a single exposure dynamic rage (SEHDR) signal is obtained. Using this technology, a 1/2.7", 2M-pixel CMOS image sensor has been developed and characterized. The image sensor also employs an on-chip linearization function, yielding a 16-bit linear signal at 60 fps, and an intra-scene dynamic range of higher than 90 dB was successfully demonstrated. This SEHDR approach inherently mitigates the artifacts from moving objects or time-varying light sources that can appear in the multiple exposure high dynamic range (MEHDR) approach.

Pressure driven digital logic in PDMS based microfluidic devices fabricated by multilayer soft lithography.

PubMed

Devaraju, Naga Sai Gopi K; Unger, Marc A

2012-11-21

Advances in microfluidics now allow an unprecedented level of parallelization and integration of biochemical reactions. However, one challenge still faced by the field has been the complexity and cost of the control hardware: one external pressure signal has been required for each independently actuated set of valves on chip. Using a simple post-modification to the multilayer soft lithography fabrication process, we present a new implementation of digital fluidic logic fully analogous to electronic logic with significant performance advances over the previous implementations. We demonstrate a novel normally closed static gain valve capable of modulating pressure signals in a fashion analogous to an electronic transistor. We utilize these valves to build complex fluidic logic circuits capable of arbitrary control of flows by processing binary input signals (pressure (1) and atmosphere (0)). We demonstrate logic gates and devices including NOT, NAND and NOR gates, bi-stable flip-flops, gated flip-flops (latches), oscillators, self-driven peristaltic pumps, delay flip-flops, and a 12-bit shift register built using static gain valves. This fluidic logic shows cascade-ability, feedback, programmability, bi-stability, and autonomous control capability. This implementation of fluidic logic yields significantly smaller devices, higher clock rates, simple designs, easy fabrication, and integration into MSL microfluidics.

World's Cheapest Readout Electronics for Kinetic Inductance Detector by Using RedPitaya

NASA Astrophysics Data System (ADS)

Tomita, N.; Jeong, H.; Choi, J.; Ishitsuka, H.; Mima, S.; Nagasaki, T.; Oguri, S.; Tajima, O.

2016-07-01

The kinetic inductance detector (KID) is a cutting-edge superconducting detector. The number of KID developers is growing. Most of them have switched from their previous study to superconducting technologies. Therefore, infrastructures for the fabrication of KIDs and cooling systems for their tests have already been established. However, readout electronics have to be newly prepared. Neither a commercial system nor low-cost standard electronics are available despite various attempts to create a standard one. We suggest the use of RedPitaya as readout electronics for the initial step of KID development, which is low cost (≈ 400 USD) and easy to set up. The RedPitaya consists of an all-programmable FPGA-CPU module and a dual-channel 14 bit DAC (ADC) to generate (measure) fast analog signals with 125 MSpS. Each port can be synchronized in-phase or quadrature-phase, and functions for generating and sampling analog signal are prepared. It is straightforward to construct vector network analyzer-like logic by using a combination of these default functions. Up-conversion and down-conversion of its frequency range are also possible by using commercial equipment, i.e., mixers, couplers, and a local oscillator. We implemented direct down-conversion logic on the RedPitaya, and successfully demonstrated KID signal measurements.

Frequency position modulation using multi-spectral projections

NASA Astrophysics Data System (ADS)

Goodman, Joel; Bertoncini, Crystal; Moore, Michael; Nousain, Bryan; Cowart, Gregory

2012-10-01

In this paper we present an approach to harness multi-spectral projections (MSPs) to carefully shape and locate tones in the spectrum, enabling a new and robust modulation in which a signal's discrete frequency support is used to represent symbols. This method, called Frequency Position Modulation (FPM), is an innovative extension to MT-FSK and OFDM and can be non-uniformly spread over many GHz of instantaneous bandwidth (IBW), resulting in a communications system that is difficult to intercept and jam. The FPM symbols are recovered using adaptive projections that in part employ an analog polynomial nonlinearity paired with an analog-to-digital converter (ADC) sampling at a rate at that is only a fraction of the IBW of the signal. MSPs also facilitate using commercial of-the-shelf (COTS) ADCs with uniform-sampling, standing in sharp contrast to random linear projections by random sampling, which requires a full Nyquist rate sample-and-hold. Our novel communication system concept provides an order of magnitude improvement in processing gain over conventional LPI/LPD communications (e.g., FH- or DS-CDMA) and facilitates the ability to operate in interference laden environments where conventional compressed sensing receivers would fail. We quantitatively analyze the bit error rate (BER) and processing gain (PG) for a maximum likelihood based FPM demodulator and demonstrate its performance in interference laden conditions.

Design of handwriting drawing board based on common copper clad laminate

NASA Astrophysics Data System (ADS)

Wang, Hongyuan; Gao, Wenzhi; Wang, Yuan

2015-02-01

Handwriting drawing board is not only a subject which can be used to write and draw, but also a method to measure and process weak signals. This design adopts 8051 single chip microprocessor as the main controller. It applies a constant-current source[1][2] to copper plate and collects the voltage value according to the resistance divider effect. Then it amplifies the signal with low-noise and high-precision amplifier[3] AD620 which is placed in the low impedance and anti-interference pen. It converts analog signal to digital signal by an 11-channel, 12-bit A/D converter TLC2543. Adoption of average filtering algorithm can effectively improve the measuring accuracy, reduce the error and make the collected voltage signal more stable. The accurate position can be detected by scanning the horizontal and vertical ordinates with the analog switch via the internal bridge of module L298 which can change the direction of X-Y axis signal scan. DM12864 is used as man-machine interface and this hominization design is convenient for man-machine communication. This collecting system has high accuracy, high stability and strong anti-interference capability. It's easy to control and has very large development space in the future.

An Over 90 dB Intra-Scene Single-Exposure Dynamic Range CMOS Image Sensor Using a 3.0 μm Triple-Gain Pixel Fabricated in a Standard BSI Process †

PubMed Central

Takayanagi, Isao; Yoshimura, Norio; Mori, Kazuya; Matsuo, Shinichiro; Tanaka, Shunsuke; Abe, Hirofumi; Yasuda, Naoto; Ishikawa, Kenichiro; Okura, Shunsuke; Ohsawa, Shinji; Otaka, Toshinori

2018-01-01

To respond to the high demand for high dynamic range imaging suitable for moving objects with few artifacts, we have developed a single-exposure dynamic range image sensor by introducing a triple-gain pixel and a low noise dual-gain readout circuit. The developed 3 μm pixel is capable of having three conversion gains. Introducing a new split-pinned photodiode structure, linear full well reaches 40 ke−. Readout noise under the highest pixel gain condition is 1 e− with a low noise readout circuit. Merging two signals, one with high pixel gain and high analog gain, and the other with low pixel gain and low analog gain, a single exposure dynamic rage (SEHDR) signal is obtained. Using this technology, a 1/2.7”, 2M-pixel CMOS image sensor has been developed and characterized. The image sensor also employs an on-chip linearization function, yielding a 16-bit linear signal at 60 fps, and an intra-scene dynamic range of higher than 90 dB was successfully demonstrated. This SEHDR approach inherently mitigates the artifacts from moving objects or time-varying light sources that can appear in the multiple exposure high dynamic range (MEHDR) approach. PMID:29329210

Development of monolithic pixel detector with SOI technology for the ILC vertex detector

NASA Astrophysics Data System (ADS)

Yamada, M.; Ono, S.; Tsuboyama, T.; Arai, Y.; Haba, J.; Ikegami, Y.; Kurachi, I.; Togawa, M.; Mori, T.; Aoyagi, W.; Endo, S.; Hara, K.; Honda, S.; Sekigawa, D.

2018-01-01

We have been developing a monolithic pixel sensor for the International Linear Collider (ILC) vertex detector with the 0.2 μm FD-SOI CMOS process by LAPIS Semiconductor Co., Ltd. We aim to achieve a 3 μm single-point resolution required for the ILC with a 20×20 μm2 pixel. Beam bunch crossing at the ILC occurs every 554 ns in 1-msec-long bunch trains with an interval of 200 ms. Each pixel must record the charge and time stamp of a hit to identify a collision bunch for event reconstruction. Necessary functions include the amplifier, comparator, shift register, analog memory and time stamp implementation in each pixel, and column ADC and Zero-suppression logic on the chip. We tested the first prototype sensor, SOFIST ver.1, with a 120 GeV proton beam at the Fermilab Test Beam Facility in January 2017. SOFIST ver.1 has a charge sensitive amplifier and two analog memories in each pixel, and an 8-bit Wilkinson-type ADC is implemented for each column on the chip. We measured the residual of the hit position to the reconstructed track. The standard deviation of the residual distribution fitted by a Gaussian is better than 3 μm.

Design of a Multi-Channel Front-End Readout ASIC With Low Noise and Large Dynamic Input Range for APD-Based PET Imaging

NASA Astrophysics Data System (ADS)

Fang, X. C.; Hu-Guo, Ch.; Ollivier-Henry, N.; Brasse, D.; Hu, Y.

2010-06-01

This paper represents the design of a low-noise, wide band multi-channel readout integrated circuit (IC) used as front end readout electronics of avalanche photo diodes (APD) dedicated to a small animal positron emission tomography (PET) system. The first ten-channel prototype chip (APD-Chip) of the analog parts has been designed and fabricated in a 0.35 μm CMOS process. Every channel of the APD_Chip includes a charge-sensitive preamplifier (CSA), a CR-(RC)2 shaper, and an analog buffer. In a channel, the CSA reads charge signals (10 bits dynamic range) from an APD array having 10 pF of capacitance per pixel. A linearized degenerated differential pair which ensures high linearity in all dynamical range is used as the high feedback resistor for preventing pile up of signals. The designed CSA has the capability of compensating automatically up to 200 nA leakage current from the detector. The CR-(RC)2 shaper filters and shapes the output signal of the CSA. An equivalent input noise charge obtained from test is 275 e -+ 10 e-/pF. In this paper the prototype is presented for both its theoretical analysis and its test results.

Enhanced robustness of evolving open systems by the bidirectionality of interactions between elements.

PubMed

Ogushi, Fumiko; Kertész, János; Kaski, Kimmo; Shimada, Takashi

2017-08-01

Living organisms, ecosystems, and social systems are examples of complex systems in which robustness against inclusion of new elements is an essential feature. A recently proposed simple model has revealed a general mechanism by which such systems can become robust against inclusion of elements with totally random interactions when the elements have a moderate number of links. The interaction is, however, in many systems often intrinsically bidirectional like for mutual symbiosis and competition in ecology. This study reports the strong reinforcement effect of the bidirectionality of the interactions on the robustness of evolving systems. We show that the system with purely bidirectional interactions can grow with twofold average degree, in comparison with the purely unidirectional system. This drastic shift of the transition point comes from the reinforcement of each node, not from a change in structure of the emergent system. For systems with partially bidirectional interactions we find that the regime of the growing phase gets expanded. In the dense interaction regime, there exists an optimum proportion of bidirectional interactions for the growth rate at around 1/3. In the sparsely connected systems, small but finite fraction of bidirectional links can change the system's behaviour from non-growing to growing.

Boring apparatus capable of boring straight holes

DOE Office of Scientific and Technical Information (OSTI.GOV)

Peterson, C.R.

The invention relates to a rock boring assembly for producing a straight hole for use in a drill string above a pilot boring bit of predetermined diameter smaller than the desired final hole size. The boring assembly comprises a small conical boring bit and a larger conical boring, the conical boring bits mounted on lower and upper ends of an enlongated spacer, respectively, and the major effective cutting diameters of each of the conical boring bits being at least 10% greater than the minor effective cutting diameter of the respective bit. The spacer has a cross-section resistant bending and spacesmore » the conical boring bits apart a distance at least 5 times the major cutting diameter of the small conical boring bit, thereby spacing the pivot points provided by the two conical boring bits to limit bodily angular deflection of the assembly and providing a substantial moment arm to resist lateral forces applied to the assembly by the pilot bit and drill string. The spacing between the conical bits is less than about 20 times the major cutting diameter of the lower conical boring bit to enable the spacer to act as a bend-resistant beam to resist angular deflection of the axis of either of the conical boring bits relative to the other when it receives uneven lateral force due to non-uniformity of cutting conditions about the circumference of the bit. Advantageously the boring bits also are self-advancing and feature skewed rollers. 7 claims.« less

Riemannian and Lorentzian flow-cut theorems

NASA Astrophysics Data System (ADS)

Headrick, Matthew; Hubeny, Veronika E.

2018-05-01

We prove several geometric theorems using tools from the theory of convex optimization. In the Riemannian setting, we prove the max flow-min cut (MFMC) theorem for boundary regions, applied recently to develop a ‘bit-thread’ interpretation of holographic entanglement entropies. We also prove various properties of the max flow and min cut, including respective nesting properties. In the Lorentzian setting, we prove the analogous MFMC theorem, which states that the volume of a maximal slice equals the flux of a minimal flow, where a flow is defined as a divergenceless timelike vector field with norm at least 1. This theorem includes as a special case a continuum version of Dilworth’s theorem from the theory of partially ordered sets. We include a brief review of the necessary tools from the theory of convex optimization, in particular Lagrangian duality and convex relaxation.

Combining multiple decisions: applications to bioinformatics

NASA Astrophysics Data System (ADS)

Yukinawa, N.; Takenouchi, T.; Oba, S.; Ishii, S.

2008-01-01

Multi-class classification is one of the fundamental tasks in bioinformatics and typically arises in cancer diagnosis studies by gene expression profiling. This article reviews two recent approaches to multi-class classification by combining multiple binary classifiers, which are formulated based on a unified framework of error-correcting output coding (ECOC). The first approach is to construct a multi-class classifier in which each binary classifier to be aggregated has a weight value to be optimally tuned based on the observed data. In the second approach, misclassification of each binary classifier is formulated as a bit inversion error with a probabilistic model by making an analogy to the context of information transmission theory. Experimental studies using various real-world datasets including cancer classification problems reveal that both of the new methods are superior or comparable to other multi-class classification methods.

Wireless Neural Recording With Single Low-Power Integrated Circuit

PubMed Central

Harrison, Reid R.; Kier, Ryan J.; Chestek, Cynthia A.; Gilja, Vikash; Nuyujukian, Paul; Ryu, Stephen; Greger, Bradley; Solzbacher, Florian; Shenoy, Krishna V.

2010-01-01

We present benchtop and in vivo experimental results from an integrated circuit designed for wireless implantable neural recording applications. The chip, which was fabricated in a commercially available 0.6-μm 2P3M BiCMOS process, contains 100 amplifiers, a 10-bit analog-to-digital converter (ADC), 100 threshold-based spike detectors, and a 902–928 MHz frequency-shift-keying (FSK) transmitter. Neural signals from a selected amplifier are sampled by the ADC at 15.7 kSps and telemetered over the FSK wireless data link. Power, clock, and command signals are sent to the chip wirelessly over a 2.765-MHz inductive (coil-to-coil) link. The chip is capable of operating with only two off-chip components: a power/command receiving coil and a 100-nF capacitor. PMID:19497825

MAROC, a generic photomultiplier readout chip

NASA Astrophysics Data System (ADS)

Blin, S.; Barrillon, P.; de La Taille, C.

2010-12-01

The MAROC ASICs family is dedicated to the readout of 64-channel Multi Anode PMT and similar detectors. Its main roles are to correct the gain spread of MAPMT channels thanks to an individual variable gain preamplifier and to discriminate the input signals (from 50fC i.e 1/3 photo-electron) in order to produce 64 trigger outputs. A multiplexed analog charge output is also available with a dynamic range around 10 pe ( ~ 1.6 pC) and a 12 bit Wilkinson ADC is embedded. Three versions of this chip have been submitted. MAROC 2 is the production version for the ATLAS luminometer and MAROC3 is a version with lower dissipation and significant improvements concerning the charge (30 pe: ~ 5 pC) and trigger (discrimination from 10fC). This third version showed very good characteristics that are presented here.

Digital data-acquisition system for measuring the free decay of acoustical standing waves in a resonant tube

NASA Technical Reports Server (NTRS)

Meredith, R. W.; Zuckerwar, A. J.

1984-01-01

A low-cost digital system based on an 8-bit Apple II microcomputer has been designed to provide on-line control, data acquisition, and evaluation of sound absorption measurements in gases. The measurements are conducted in a resonant tube, in which an acoustical standing wave is excited, the excitation removed, and the sound absorption evaluated from the free decay envelope. The free decay is initiated from the computer keyboard after the standing wave is established, and the microphone response signal is the source of the analog signal for the A/D converter. The acquisition software is written in ASSEMBLY language and the evaluation software in BASIC. This paper describes the acoustical measurement, hardware, software, and system performance and presents measurements of sound absorption in air as an example.

Processors for wavelet analysis and synthesis: NIFS and TI-C80 MVP

NASA Astrophysics Data System (ADS)

Brooks, Geoffrey W.

1996-03-01

Two processors are considered for image quadrature mirror filtering (QMF). The neuromorphic infrared focal-plane sensor (NIFS) is an existing prototype analog processor offering high speed spatio-temporal Gaussian filtering, which could be used for the QMF low- pass function, and difference of Gaussian filtering, which could be used for the QMF high- pass function. Although not designed specifically for wavelet analysis, the biologically- inspired system accomplishes the most computationally intensive part of QMF processing. The Texas Instruments (TI) TMS320C80 Multimedia Video Processor (MVP) is a 32-bit RISC master processor with four advanced digital signal processors (DSPs) on a single chip. Algorithm partitioning, memory management and other issues are considered for optimal performance. This paper presents these considerations with simulated results leading to processor implementation of high-speed QMF analysis and synthesis.

Programmable high-output-impedance, large-voltage compliance, microstimulator for low-voltage biomedical applications.

PubMed

Farahmand, Sina; Maghami, Mohammad Hossein; Sodagar, Amir M

2012-01-01

This paper reports on the design of a programmable, high output impedance, large voltage compliance microstimulator for low-voltage biomedical applications. A 6-bit binary-weighted digital to analog converter (DAC) is used to generate biphasic stimulus current pulses. A compact current mirror with large output voltage compliance and high output resistance conveys the current pulses to the target tissue. Designed and simulated in a standard 0.18µm CMOS process, the microstimulator circuit is capable of delivering a maximum stimulation current of 160µA to a 10-kΩ resistive load. Operated at a 1.8-V supply voltage, the output stage exhibits a voltage compliance of 1.69V and output resistance of 160MΩ at full scale stimulus current. Layout of the core microelectrode circuit measures 25.5µm×31.5µm.

A readout system for X-ray powder crystallography

NASA Astrophysics Data System (ADS)

Loukas, D.; Haralabidis, N.; Pavlidis, A.; Karvelas, E.; Psycharis ^a, K. Misiakos, V.; Mousa, J.; Dre, Ch.

2000-06-01

A system for capturing and processing data, from radiation detectors, in the field of X-ray crystallography has been developed. The system includes a custom-made mixed analog-digital 16-channel VLSI circuit in 50 μm pitch. Each channel comprises a charge amplifier, a shaper, a comparator and a 21-bit counter. The circuit can be scaled in a daisy chain configuration. Data acquisition is performed with a custom made PCI card while the control software is developed with Visual C++ under the MS Windows NT environment. Performance of a fully operational system, in terms of electronic noise, statistical variations and data capture speed is presented. The noise level permits counting of X-rays down to 8 keV while the counting capability is in excess of 200 kHz. The system is intended for X-ray crystallography with silicon detectors.

Construction of a fast, inexpensive rapid-scanning diode-array detector and spectrometer.

PubMed

Carter, T P; Baek, H K; Bonninghausen, L; Morris, R J; van Wart, H E

1990-10-01

A 512-element diode-array spectroscopic detection system capable of acquiring multiple spectra at a rate of 5 ms per spectrum with an effective scan rate of 102.9 kHz has been constructed. Spectra with fewer diode elements can also be acquired at scan rates up to 128 kHz. The detector utilizes a Hamamatsu silicon photodiode-array sensor that is interfaced to Hamamatsu driver/amplifier and clock generator boards and a DRA laboratories 12-bit 160-kHz analog-to-digital converter. These are standard, commercially available devices which cost approximately $3500. The system is interfaced to and controlled by an IBM XT microcomputer. Detailed descriptions of the home-built detector housing and control/interface circuitry are presented and its application to the study of the reaction of horseradish peroxidase with hydrogen peroxide is demonstrated.

The Thomson scattering system at Wendelstein 7-X

NASA Astrophysics Data System (ADS)

Pasch, E.; Beurskens, M. N. A.; Bozhenkov, S. A.; Fuchert, G.; Knauer, J.; Wolf, R. C.

2016-11-01

This paper describes the design of the Thomson scattering system at the Wendelstein 7-X stellarator. For the first operation campaign we installed a 10 spatial channel system to cover a radial half profile of the plasma cross section. The start-up system is based on one Nd:YAG laser with 10 Hz repetition frequency, one observation optics, five fiber bundles with one delay line each, and five interference filter polychromators with five spectral channels and silicon avalanche diodes as detectors. High dynamic range analog to digital converters with 14 bit, 1 GS/s are used to digitize the signals. The spectral calibration of the system was done using a pulsed super continuum laser together with a monochromator. For density calibration we used Raman scattering in nitrogen gas. Peaked temperature profiles and flat density profiles are observed in helium and hydrogen discharges.

A digitally implemented communications experiment utilizing the Hermes (CTS) satellite

NASA Technical Reports Server (NTRS)

Jackson, H. D.; Fiala, J. L.

1977-01-01

The Hermes (CTS) experiment program made possible a significant effort directed toward new developments which will reduce the costs associated with the distribution of satellite services. Advanced satellite transponder technology and small inexpensive earth terminals were demonstrated as part of the Hermes program. Another system element that holds promise for reduced transmission cost is associated with the communication link implementation. An experiment is described which uses CTS to demonstrate digital link implementation and its advantages over conventional analog systems. A Digitally Implemented Communications experiment which demonstrates the flexibility and efficiency of digital transmission of television video and audio, telephone voice and high-bit-rate data is also described. Presentation of the experiment concept which concentrates on the evaluation of full-duplex digital television in the teleconferencing environment is followed by a description of unique equipment that was developed.

Fail-safe bidirectional valve driver

NASA Technical Reports Server (NTRS)

Fujimoto, H.

1974-01-01

Cross-coupled diodes are added to commonly used bidirectional valve driver circuit to protect circuit and power supply. Circuit may be used in systems requiring fail-safe bidirectional valve operation, particularly in chemical- and petroleum-processing control systems and computer-controlled hydraulic or pneumatic systems.

Bit-Grooming: Shave Your Bits with Razor-sharp Precision

NASA Astrophysics Data System (ADS)

Zender, C. S.; Silver, J.

2017-12-01

Lossless compression can reduce climate data storage by 30-40%. Further reduction requires lossy compression that also reduces precision. Fortunately, geoscientific models and measurements generate false precision (scientifically meaningless data bits) that can be eliminated without sacrificing scientifically meaningful data. We introduce Bit Grooming, a lossy compression algorithm that removes the bloat due to false-precision, those bits and bytes beyond the meaningful precision of the data.Bit Grooming is statistically unbiased, applies to all floating point numbers, and is easy to use. Bit-Grooming reduces geoscience data storage requirements by 40-80%. We compared Bit Grooming to competitors Linear Packing, Layer Packing, and GRIB2/JPEG2000. The other compression methods have the edge in terms of compression, but Bit Grooming is the most accurate and certainly the most usable and portable.Bit Grooming provides flexible and well-balanced solutions to the trade-offs among compression, accuracy, and usability required by lossy compression. Geoscientists could reduce their long term storage costs, and show leadership in the elimination of false precision, by adopting Bit Grooming.

A Compression Algorithm for Field Programmable Gate Arrays in the Space Environment

DTIC Science & Technology

2011-12-01

Bit 1 ,Bit 0P  . (V.3) Equation (V.3) is implemented with a string of XOR gates and Bit Basher blocks, as shown in Figure 31. As discussed in...5], the string of Bit Basher blocks are used to separate each 35-bit value into 35 one-bit values, and the string of XOR gates is used to

Drag bit construction

DOEpatents

Hood, M.

1986-02-11

A mounting movable with respect to an adjacent hard face has a projecting drag bit adapted to engage the hard face. The drag bit is disposed for movement relative to the mounting by encounter of the drag bit with the hard face. That relative movement regulates a valve in a water passageway, preferably extending through the drag bit, to play a stream of water in the area of contact of the drag bit and the hard face and to prevent such water play when the drag bit is out of contact with the hard face. 4 figs.

Drag bit construction

DOEpatents

Hood, Michael

1986-01-01

A mounting movable with respect to an adjacent hard face has a projecting drag bit adapted to engage the hard face. The drag bit is disposed for movement relative to the mounting by encounter of the drag bit with the hard face. That relative movement regulates a valve in a water passageway, preferably extending through the drag bit, to play a stream of water in the area of contact of the drag bit and the hard face and to prevent such water play when the drag bit is out of contact with the hard face.

An Asymptotically-Optimal Sampling-Based Algorithm for Bi-directional Motion Planning

PubMed Central

Starek, Joseph A.; Gomez, Javier V.; Schmerling, Edward; Janson, Lucas; Moreno, Luis; Pavone, Marco

2015-01-01

Bi-directional search is a widely used strategy to increase the success and convergence rates of sampling-based motion planning algorithms. Yet, few results are available that merge both bi-directional search and asymptotic optimality into existing optimal planners, such as PRM*, RRT*, and FMT*. The objective of this paper is to fill this gap. Specifically, this paper presents a bi-directional, sampling-based, asymptotically-optimal algorithm named Bi-directional FMT* (BFMT*) that extends the Fast Marching Tree (FMT*) algorithm to bidirectional search while preserving its key properties, chiefly lazy search and asymptotic optimality through convergence in probability. BFMT* performs a two-source, lazy dynamic programming recursion over a set of randomly-drawn samples, correspondingly generating two search trees: one in cost-to-come space from the initial configuration and another in cost-to-go space from the goal configuration. Numerical experiments illustrate the advantages of BFMT* over its unidirectional counterpart, as well as a number of other state-of-the-art planners. PMID:27004130

Bidirectional Associations between Parenting Practices and Conduct Problems in Boys from Childhood to Adolescence: The Moderating Effect of Age and African-American Ethnicity

PubMed Central

Fite, Paula J.; Burke, Jeffrey D.

2010-01-01

This study examined the bidirectional relationship between parent and teacher reported conduct problems in youth and parenting practices using a longitudinal sample of boys assessed from 6 to 16 years of age. Analyses tested whether these bidirectional associations changed across development and whether the nature of these associations varied across African-American and Caucasian families. Overall, the results supported a bidirectional relationship between conduct problems and all parenting practices examined from childhood to adolescence. The influence of conduct problems on changes in parenting behaviors was as strong as the influence of parenting behaviors on changes in conduct problems across development. Changes in the bidirectional relationship across development were found in some, but not all, models. While corporal punishment was more strongly related to changes in teacher-reported conduct problems for African-American boys compared to Caucasian boys, more similarities than differences were found between the ethnic groups in terms of the bidirectional associations examined. PMID:17899362

PDC-bit performance under simulated borehole conditions

DOE Office of Scientific and Technical Information (OSTI.GOV)

Anderson, E.E.; Azar, J.J.

1993-09-01

Laboratory drilling tests were used to investigate the effects of pressure on polycrystalline-diamond-compact (PDC) drill-bit performance. Catoosa shale core samples were drilled with PDC and roller-cone bits at up to 1,750-psi confining pressure. All tests were conducted in a controlled environment with a full-scale laboratory drilling system. Test results indicate, that under similar operating conditions, increases in confining pressure reduce PDC-bit performance as much as or more than conventional-rock-bit performance. Specific energy calculations indicate that a combination of rock strength, chip hold-down, and bit balling may have reduced performance. Quantifying the degree to which pressure reduces PDC-bit performance will helpmore » researchers interpret test results and improve bit designs and will help drilling engineers run PDC bits more effectively in the field.« less

Smart built-in test

NASA Technical Reports Server (NTRS)

Richards, Dale W.

1990-01-01

The work which built-in test (BIT) is asked to perform in today's electronic systems increases with every insertion of new technology or introduction of tighter performance criteria. Yet the basic purpose remains unchanged -- to determine with high confidence the operational capability of that equipment. Achievement of this level of BIT performance requires the management and assimilation of a large amount of data, both realtime and historical. Smart BIT has taken advantage of advanced techniques from the field of artificial intelligence (AI) in order to meet these demands. The Smart BIT approach enhances traditional functional BIT by utilizing AI techniques to incorporate environmental stress data, temporal BIT information and maintenance data, and realtime BIT reports into an integrated test methodology for increased BIT effectiveness and confidence levels. Future research in this area will incorporate onboard fault-logging of BIT output, stress data and Smart BIT decision criteria in support of a singular, integrated and complete test and maintenance capability. The state of this research is described along with a discussion of directions for future development.

Smart built-in test

NASA Astrophysics Data System (ADS)

Richards, Dale W.

1990-03-01

The work which built-in test (BIT) is asked to perform in today's electronic systems increases with every insertion of new technology or introduction of tighter performance criteria. Yet the basic purpose remains unchanged -- to determine with high confidence the operational capability of that equipment. Achievement of this level of BIT performance requires the management and assimilation of a large amount of data, both realtime and historical. Smart BIT has taken advantage of advanced techniques from the field of artificial intelligence (AI) in order to meet these demands. The Smart BIT approach enhances traditional functional BIT by utilizing AI techniques to incorporate environmental stress data, temporal BIT information and maintenance data, and realtime BIT reports into an integrated test methodology for increased BIT effectiveness and confidence levels. Future research in this area will incorporate onboard fault-logging of BIT output, stress data and Smart BIT decision criteria in support of a singular, integrated and complete test and maintenance capability. The state of this research is described along with a discussion of directions for future development.

Hey! A Flea Bit Me!

MedlinePlus

... Staying Safe Videos for Educators Search English Español Hey! A Flea Bit Me! KidsHealth / For Kids / Hey! A Flea Bit Me! Print en español ¡Ay! ¡ ... 30% DEET. More on this topic for: Kids Hey! A Gnat Bit Me! Hey! A Bedbug Bit ...

Hey! A Louse Bit Me!

MedlinePlus

... Staying Safe Videos for Educators Search English Español Hey! A Louse Bit Me! KidsHealth / For Kids / Hey! A Louse Bit Me! Print en español ¡Ay! ¡ ... topic for: Kids Lice Aren't So Nice Hey! A Gnat Bit Me! Hey! A Flea Bit ...

PDC bits: What`s needed to meet tomorrow`s challenge

DOE Office of Scientific and Technical Information (OSTI.GOV)

Warren, T.M.; Sinor, L.A.

1994-12-31

When polycrystalline diamond compact (PDC) bits were introduced in the mid-1970s they showed tantalizingly high penetration rates in laboratory drilling tests. Single cutter tests indicated that they had the potential to drill very hard rocks. Unfortunately, 20 years later we`re still striving to reach the potential that these bits seem to have. Many problems have been overcome, and PDC bits have offered capabilities not possible with roller cone bits. PDC bits provide the most economical bit choice in many areas, but their limited durability has hampered their application in many other areas.

Global evaluation of ammonia bidirectional exchange and livestock diurnal variation schemes

EPA Science Inventory

Bidirectional air–surface exchange of ammonia (NH3) has been neglected in many air quality models. In this study, we implement the bidirectional exchange of NH3 in the GEOS-Chem global chemical transport model. We also introduce an updated diurnal variability scheme for NH3...

Computer-Communications Networks and Teletraffic.

ERIC Educational Resources Information Center

Switzer, I.

Bi-directional cable TV (CATV) systems that are being installed today may not be well suited for computer communications. Older CATV systems are being modified to bi-directional transmission and most new systems are being built with bi-directional capability included. The extreme bandwidth requirement for carrying 20 or more TV channels on a…

Evolution of bidirectional sex change and gonochorism in fishes of the gobiid genera Trimma, Priolepis, and Trimmatom.

PubMed

Sunobe, Tomoki; Sado, Tetsuya; Hagiwara, Kiyoshi; Manabe, Hisaya; Suzuki, Toshiyuki; Kobayashi, Yasuhisa; Sakurai, Makoto; Dewa, Shin-Ichi; Matsuoka, Midori; Shinomiya, Akihiko; Fukuda, Kazuya; Miya, Masaki

2017-04-01

Size-advantage and low-density models have been used to explain how mating systems favor hermaphroditism or gonochorism. However, these models do not indicate historical transitions in sexuality. Here, we investigate the evolution of bidirectional sex change and gonochorism by phylogenetic analysis using the mitochondrial gene of the gobiids Trimma (31 species), Priolepis (eight species), and Trimmatom (two species). Trimma and Priolepis formed a clade within the sister group Trimmatom. Gonadal histology and rearing experiments revealed that Trimma marinae, Trimma nasa, and Trimmatom spp. were gonochoric, whereas all other Trimma and Priolepis spp. were bidirectional sex changers or inferred ones. A maximum-likelihood reconstruction analysis demonstrated that the common ancestor of the three genera was gonochoristic. Bidirectional sex change probably evolved from gonochorism in a common ancestor of Trimma and Priolepis. As the gonads of bidirectional sex changers simultaneously contain mature ovarian and immature testicular components or vice versa, individuals are always potentially capable of functioning as females or males, respectively. Monogamy under low-density conditions may have been the ecological condition for the evolution of bidirectional sex change in a common ancestor. As T. marinae and T. nasa are a monophyletic group, gonochorism should have evolved from bidirectional sex change in a common ancestor.

Evolution of bidirectional sex change and gonochorism in fishes of the gobiid genera Trimma, Priolepis, and Trimmatom

NASA Astrophysics Data System (ADS)

Sunobe, Tomoki; Sado, Tetsuya; Hagiwara, Kiyoshi; Manabe, Hisaya; Suzuki, Toshiyuki; Kobayashi, Yasuhisa; Sakurai, Makoto; Dewa, Shin-ichi; Matsuoka, Midori; Shinomiya, Akihiko; Fukuda, Kazuya; Miya, Masaki

2017-04-01

Size-advantage and low-density models have been used to explain how mating systems favor hermaphroditism or gonochorism. However, these models do not indicate historical transitions in sexuality. Here, we investigate the evolution of bidirectional sex change and gonochorism by phylogenetic analysis using the mitochondrial gene of the gobiids Trimma (31 species), Priolepis (eight species), and Trimmatom (two species). Trimma and Priolepis formed a clade within the sister group Trimmatom. Gonadal histology and rearing experiments revealed that Trimma marinae, Trimma nasa, and Trimmatom spp. were gonochoric, whereas all other Trimma and Priolepis spp. were bidirectional sex changers or inferred ones. A maximum-likelihood reconstruction analysis demonstrated that the common ancestor of the three genera was gonochoristic. Bidirectional sex change probably evolved from gonochorism in a common ancestor of Trimma and Priolepis. As the gonads of bidirectional sex changers simultaneously contain mature ovarian and immature testicular components or vice versa, individuals are always potentially capable of functioning as females or males, respectively. Monogamy under low-density conditions may have been the ecological condition for the evolution of bidirectional sex change in a common ancestor. As T. marinae and T. nasa are a monophyletic group, gonochorism should have evolved from bidirectional sex change in a common ancestor.

A multi-channel low-power system-on-chip for single-unit recording and narrowband wireless transmission of neural signal.

PubMed

Bonfanti, A; Ceravolo, M; Zambra, G; Gusmeroli, R; Spinelli, A S; Lacaita, A L; Angotzi, G N; Baranauskas, G; Fadiga, L

2010-01-01

This paper reports a multi-channel neural recording system-on-chip (SoC) with digital data compression and wireless telemetry. The circuit consists of a 16 amplifiers, an analog time division multiplexer, an 8-bit SAR AD converter, a digital signal processor (DSP) and a wireless narrowband 400-MHz binary FSK transmitter. Even though only 16 amplifiers are present in our current die version, the whole system is designed to work with 64 channels demonstrating the feasibility of a digital processing and narrowband wireless transmission of 64 neural recording channels. A digital data compression, based on the detection of action potentials and storage of correspondent waveforms, allows the use of a 1.25-Mbit/s binary FSK wireless transmission. This moderate bit-rate and a low frequency deviation, Manchester-coded modulation are crucial for exploiting a narrowband wireless link and an efficient embeddable antenna. The chip is realized in a 0.35- εm CMOS process with a power consumption of 105 εW per channel (269 εW per channel with an extended transmission range of 4 m) and an area of 3.1 × 2.7 mm(2). The transmitted signal is captured by a digital TV tuner and demodulated by a wideband phase-locked loop (PLL), and then sent to a PC via an FPGA module. The system has been tested for electrical specifications and its functionality verified in in-vivo neural recording experiments.

Design techniques for a stable operation of cryogenic field-programmable gate arrays.

PubMed

Homulle, Harald; Visser, Stefan; Patra, Bishnu; Charbon, Edoardo

2018-01-01

In this paper, we show how a deep-submicron field-programmable gate array (FPGA) can be operated more stably at extremely low temperatures through special firmware design techniques. Stability at low temperatures is limited through long power supply wires and reduced performance of various printed circuit board components commonly employed at room temperature. Extensive characterization of these components shows that the majority of decoupling capacitor types and voltage regulators are not well behaved at cryogenic temperatures, asking for an ad hoc solution to stabilize the FPGA supply voltage, especially for sensitive applications. Therefore, we have designed a firmware that enforces a constant power consumption, so as to stabilize the supply voltage in the interior of the FPGA. The FPGA is powered with a supply at several meters distance, causing significant resistive voltage drop and thus fluctuations on the local supply voltage. To achieve the stabilization, the variation in digital logic speed, which directly corresponds to changes in supply voltage, is constantly measured and corrected for through a tunable oscillator farm, implemented on the FPGA. The impact of the stabilization technique is demonstrated together with a reconfigurable analog-to-digital converter (ADC), completely implemented in the FPGA fabric and operating at 15 K. The ADC performance can be improved by at most 1.5 bits (effective number of bits) thanks to the more stable supply voltage. The method is versatile and robust, enabling seamless porting to other FPGA families and configurations.

Design techniques for a stable operation of cryogenic field-programmable gate arrays

NASA Astrophysics Data System (ADS)

Homulle, Harald; Visser, Stefan; Patra, Bishnu; Charbon, Edoardo

2018-01-01

In this paper, we show how a deep-submicron field-programmable gate array (FPGA) can be operated more stably at extremely low temperatures through special firmware design techniques. Stability at low temperatures is limited through long power supply wires and reduced performance of various printed circuit board components commonly employed at room temperature. Extensive characterization of these components shows that the majority of decoupling capacitor types and voltage regulators are not well behaved at cryogenic temperatures, asking for an ad hoc solution to stabilize the FPGA supply voltage, especially for sensitive applications. Therefore, we have designed a firmware that enforces a constant power consumption, so as to stabilize the supply voltage in the interior of the FPGA. The FPGA is powered with a supply at several meters distance, causing significant resistive voltage drop and thus fluctuations on the local supply voltage. To achieve the stabilization, the variation in digital logic speed, which directly corresponds to changes in supply voltage, is constantly measured and corrected for through a tunable oscillator farm, implemented on the FPGA. The impact of the stabilization technique is demonstrated together with a reconfigurable analog-to-digital converter (ADC), completely implemented in the FPGA fabric and operating at 15 K. The ADC performance can be improved by at most 1.5 bits (effective number of bits) thanks to the more stable supply voltage. The method is versatile and robust, enabling seamless porting to other FPGA families and configurations.

["A Little Bit of Switzerland, a Little Bit of Kosovo". Swiss Immigrants from Former Yugoslavia with Type 2 Diabetes. A Qualitative Study' in Analogy to Grounded Theory].

PubMed

Wenger, A; Mischke, C

2015-10-01

Type 2 diabetes is on the increase among the Swiss immigrants. The cultural background of patients presents new linguistic and sociocultural barriers and gains in importance for health care. In order to develop patient-centred care, it is necessary to focus on different sociocultural aspects in everyday life and experiences of immigrants from the former republics of Yugoslavia with diabetes who have rarely been studied in Switzerland. Based on these insights the needs for counselling can be identified and nursing interventions can be designed accordingly. Using the Grounded Theory approach, 5 interviews were analysed according to the Corbin and Strauss coding paradigm. The central phenomenon found is the experience to live in 2 different cultures. The complexity arises from the tension living in 2 cultural backgrounds at the same time. It turns out that in the country of origin the immigrants adjust their disease management. The changing daily rhythm and the more traditional role model affect aspects of their disease management such as diet and/or drug therapy. The different strategies impact the person's roles, emotions, their everyday lives and their families. It provides an insight into the perspective of Swiss immigrants from the former republics of Yugoslavia suffering from diabetes. Many questions are still unanswered and further research will be required. © Georg Thieme Verlag KG Stuttgart · New York.

A 16-Channel CMOS Chopper-Stabilized Analog Front-End ECoG Acquisition Circuit for a Closed-Loop Epileptic Seizure Control System.

PubMed

Wu, Chung-Yu; Cheng, Cheng-Hsiang; Chen, Zhi-Xin

2018-06-01

In this paper, a 16-channel analog front-end (AFE) electrocorticography signal acquisition circuit for a closed-loop seizure control system is presented. It is composed of 16 input protection circuits, 16 auto-reset chopper-stabilized capacitive-coupled instrumentation amplifiers (AR-CSCCIA) with bandpass filters, 16 programmable transconductance gain amplifiers, a multiplexer, a transimpedance amplifier, and a 128-kS/s 10-bit delta-modulated successive-approximation-register analog-to-digital converter (SAR ADC). In closed-loop seizure control system applications, the stimulator shares the same electrode with the AFE amplifier for effective suppression of epileptic seizures. To prevent from overstress in MOS devices caused by high stimulation voltage, an input protection circuit with a high-voltage-tolerant switch is proposed for the AFE amplifier. Moreover, low input-referred noise is achieved by using the chopper modulation technique in the AR-CSCCIA. To reduce the undesired effects of chopper modulation, an improved offset reduction loop is proposed to reduce the output offset generated by input chopper mismatches. The digital ripple reduction loop is also used to reduce the chopper ripple. The fabricated AFE amplifier has 49.1-/59.4-/67.9-dB programmable gain and 2.02-μVrms input referred noise in a bandwidth of 0.59-117 Hz. The measured power consumption of the AFE amplifier is 3.26 μW per channel, and the noise efficiency factor is 3.36. The in vivo animal test has been successfully performed to verify the functions. It is shown that the proposed AFE acquisition circuit is suitable for implantable closed-loop seizure control systems.

FPGA-based digital signal processing for the next generation radio astronomy instruments: ultra-pure sideband separation and polarization detection

NASA Astrophysics Data System (ADS)

Alvear, Andrés.; Finger, Ricardo; Fuentes, Roberto; Sapunar, Raúl; Geelen, Tom; Curotto, Franco; Rodríguez, Rafael; Monasterio, David; Reyes, Nicolás.; Mena, Patricio; Bronfman, Leonardo

2016-07-01

Field Programmable Gate Arrays (FPGAs) capacity and Analog to Digital Converters (ADCs) speed have largely increased in the last decade. Nowadays we can find one million or more logic blocks (slices) as well as several thousand arithmetic units (ALUs/DSP) available on a single FPGA chip. We can also commercially procure ADC chips reaching 10 GSPS, with 8 bits resolution or more. This unprecedented power of computing hardware has allowed the digitalization of signal processes traditionally performed by analog components. In radio astronomy, the clearest example has been the development of digital sideband separating receivers which, by replacing the IF hybrid and calibrating the system imbalances, have exhibited a sideband rejection above 40dB; this is 20 to 30dB higher than traditional analog sideband separating (2SB) receivers. In Rodriguez et al.,1 and Finger et al.,2 we have demonstrated very high digital sideband separation at 3mm and 1mm wavelengths, using laboratory setups. We here show the first implementation of such technique with a 3mm receiver integrated into a telescope, where the calibration was performed by quasi-optical injection of the test tone in front of the Cassegrain antenna. We also reported progress in digital polarization synthesis, particularly in the implementation of a calibrated Digital Ortho-Mode Transducer (DOMT) based on the Morgan et al. proof of concept.3 They showed off- line synthesis of polarization with isolation higher than 40dB. We plan to implement a digital polarimeter in a real-time FPGA-based (ROACH-2) platform, to show ultra-pure polarization isolation in a non-stop integrating spectrometer.

GLAST Burst Monitor Signal Processing System

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bhat, P. Narayana; Briggs, Michael; Connaughton, Valerie

The onboard Data Processing Unit (DPU), designed and built by Southwest Research Institute, performs the high-speed data acquisition for GBM. The analog signals from each of the 14 detectors are digitized by high-speed multichannel analog data acquisition architecture. The streaming digital values resulting from a periodic (period of 104.2 ns) sampling of the analog signal by the individual ADCs are fed to a Field-Programmable Gate Array (FPGA). Real-time Digital Signal Processing (DSP) algorithms within the FPGA implement functions like filtering, thresholding, time delay and pulse height measurement. The spectral data with a 12-bit resolution are formatted according to the commandablemore » look-up-table (LUT) and then sent to the High-Speed Science-Date Bus (HSSDB, speed=1.5 MB/s) to be telemetered to ground. The DSP offers a novel feature of a commandable and constant event deadtime. The ADC non-linearities have been calibrated so that the spectral data can be corrected during analysis. The best temporal resolution is 2 {mu}s for the pre-burst and post-trigger time-tagged events (TTE) data. The time resolution of the binned data types is commandable from 64 msec to 1.024 s for the CTIME data (8 channel spectral resolution) and 1.024 to 32.768 s for the CSPEC data (128 channel spectral resolution). The pulse pile-up effects have been studied by Monte Carlo simulations. For a typical GRB, the possible shift in the Epeak value at high-count rates ({approx}100 kHz) is {approx}1% while the change in the single power-law index could be up to 5%.« less

High bit depth infrared image compression via low bit depth codecs

NASA Astrophysics Data System (ADS)

Belyaev, Evgeny; Mantel, Claire; Forchhammer, Søren

2017-08-01

Future infrared remote sensing systems, such as monitoring of the Earth's environment by satellites, infrastructure inspection by unmanned airborne vehicles etc., will require 16 bit depth infrared images to be compressed and stored or transmitted for further analysis. Such systems are equipped with low power embedded platforms where image or video data is compressed by a hardware block called the video processing unit (VPU). However, in many cases using two 8-bit VPUs can provide advantages compared with using higher bit depth image compression directly. We propose to compress 16 bit depth images via 8 bit depth codecs in the following way. First, an input 16 bit depth image is mapped into 8 bit depth images, e.g., the first image contains only the most significant bytes (MSB image) and the second one contains only the least significant bytes (LSB image). Then each image is compressed by an image or video codec with 8 bits per pixel input format. We analyze how the compression parameters for both MSB and LSB images should be chosen to provide the maximum objective quality for a given compression ratio. Finally, we apply the proposed infrared image compression method utilizing JPEG and H.264/AVC codecs, which are usually available in efficient implementations, and compare their rate-distortion performance with JPEG2000, JPEG-XT and H.265/HEVC codecs supporting direct compression of infrared images in 16 bit depth format. A preliminary result shows that two 8 bit H.264/AVC codecs can achieve similar result as 16 bit HEVC codec.

Performance test of different 3.5 mm drill bits and consequences for orthopaedic surgery.

PubMed

Clement, Hans; Zopf, Christoph; Brandner, Markus; Tesch, Norbert P; Vallant, Rudolf; Puchwein, Paul

2015-12-01

Drilling of bones in orthopaedic and trauma surgery is a common procedure. There are yet no recommendations about which drill bits/coating should be preferred and when to change a used drill bit. In preliminary studies typical "drilling patterns" of surgeons concerning used spindle speed and feeding force were recorded. Different feeding forces were tested and abrasion was analysed using magnification and a scanning electron microscope (SEM). Acquired data were used for programming a friction stir welding machine (FSWM). Four drill bits (a default AISI 440A, a HSS, an AISI 440B and a Zirconium-oxide drill bit) were analysed for abrasive wear after 20/40/60 machine-guided and hand-driven drilled holes. Additionally different drill coatings [diamond-like carbon/grafitic (DLC), titanium nitride/carbide (Ti-N)] were tested. The mean applied feeding force by surgeons was 45 ± 15.6 Newton (N). HSS bits were still usable after 51 drill holes. Both coated AISI 440A bits showed considerable breakouts of the main cutting edge after 20 hand-driven drilled holes. The coated HSS bit showed very low abrasive wear. The non-coated AISI 440B bit had a similar durability to the HSS bits. The ZrO2 dental drill bit excelled its competitors (no considerable abrasive wear at >100 holes). If the default AISI 440A drill bit cannot be checked by 20-30× magnification after surgery, it should be replaced after 20 hand-driven drilled holes. Low price coated HSS bits could be a powerful alternative.

Bit-1 Mediates Integrin-dependent Cell Survival through Activation of the NFκB Pathway*

PubMed Central

Griffiths, Genevieve S.; Grundl, Melanie; Leychenko, Anna; Reiter, Silke; Young-Robbins, Shirley S.; Sulzmaier, Florian J.; Caliva, Maisel J.; Ramos, Joe W.; Matter, Michelle L.

2011-01-01

Loss of properly regulated cell death and cell survival pathways can contribute to the development of cancer and cancer metastasis. Cell survival signals are modulated by many different receptors, including integrins. Bit-1 is an effector of anoikis (cell death due to loss of attachment) in suspended cells. The anoikis function of Bit-1 can be counteracted by integrin-mediated cell attachment. Here, we explored integrin regulation of Bit-1 in adherent cells. We show that knockdown of endogenous Bit-1 in adherent cells decreased cell survival and re-expression of Bit-1 abrogated this effect. Furthermore, reduction of Bit-1 promoted both staurosporine and serum-deprivation induced apoptosis. Indeed knockdown of Bit-1 in these cells led to increased apoptosis as determined by caspase-3 activation and positive TUNEL staining. Bit-1 expression protected cells from apoptosis by increasing phospho-IκB levels and subsequently bcl-2 gene transcription. Protection from apoptosis under serum-free conditions correlated with bcl-2 transcription and Bcl-2 protein expression. Finally, Bit-1-mediated regulation of bcl-2 was dependent on focal adhesion kinase, PI3K, and AKT. Thus, we have elucidated an integrin-controlled pathway in which Bit-1 is, in part, responsible for the survival effects of cell-ECM interactions. PMID:21383007

Bit Grooming: statistically accurate precision-preserving quantization with compression, evaluated in the netCDF Operators (NCO, v4.4.8+)

NASA Astrophysics Data System (ADS)

Zender, Charles S.

2016-09-01

Geoscientific models and measurements generate false precision (scientifically meaningless data bits) that wastes storage space. False precision can mislead (by implying noise is signal) and be scientifically pointless, especially for measurements. By contrast, lossy compression can be both economical (save space) and heuristic (clarify data limitations) without compromising the scientific integrity of data. Data quantization can thus be appropriate regardless of whether space limitations are a concern. We introduce, implement, and characterize a new lossy compression scheme suitable for IEEE floating-point data. Our new Bit Grooming algorithm alternately shaves (to zero) and sets (to one) the least significant bits of consecutive values to preserve a desired precision. This is a symmetric, two-sided variant of an algorithm sometimes called Bit Shaving that quantizes values solely by zeroing bits. Our variation eliminates the artificial low bias produced by always zeroing bits, and makes Bit Grooming more suitable for arrays and multi-dimensional fields whose mean statistics are important. Bit Grooming relies on standard lossless compression to achieve the actual reduction in storage space, so we tested Bit Grooming by applying the DEFLATE compression algorithm to bit-groomed and full-precision climate data stored in netCDF3, netCDF4, HDF4, and HDF5 formats. Bit Grooming reduces the storage space required by initially uncompressed and compressed climate data by 25-80 and 5-65 %, respectively, for single-precision values (the most common case for climate data) quantized to retain 1-5 decimal digits of precision. The potential reduction is greater for double-precision datasets. When used aggressively (i.e., preserving only 1-2 digits), Bit Grooming produces storage reductions comparable to other quantization techniques such as Linear Packing. Unlike Linear Packing, whose guaranteed precision rapidly degrades within the relatively narrow dynamic range of values that it can compress, Bit Grooming guarantees the specified precision throughout the full floating-point range. Data quantization by Bit Grooming is irreversible (i.e., lossy) yet transparent, meaning that no extra processing is required by data users/readers. Hence Bit Grooming can easily reduce data storage volume without sacrificing scientific precision or imposing extra burdens on users.

Bidirectional Longitudinal Relations between Father-Child Relationships and Chinese Children's Social Competence during Early Childhood

ERIC Educational Resources Information Center

Zhang, Xiao

2013-01-01

Using a two-year and three-wave cross-lagged design with a sample of 118 Chinese preschoolers, the present study examined bidirectional longitudinal relations between father-child relationships and children's social competence. The results of structural equation modeling showed bidirectional effects between father-child conflict and social…

Numerical Modelling of a Bidirectional Long Ring Raman Fiber Laser Dynamics

NASA Astrophysics Data System (ADS)

Sukhanov, S. V.; Melnikov, L. A.; Mazhirina, Yu A.

2017-11-01

The numerical model for the simulation of the dynamics of a bidirectional long ring Raman fiber laser is proposed. The model is based on the transport equations and Courant-Isaacson-Rees method. Different regimes of a bidirectional long ring Raman fiber laser and long time-domain realizations are investigated.

Analytical investigation of bidirectional ductile diaphragms in multi-span bridges

NASA Astrophysics Data System (ADS)

Wei, Xiaone; Bruneau, Michel

2018-04-01

In the AASHTO Guide Specifications for Seismic Bridge Design Provisions, ductile diaphragms are identified as Permissible Earthquake-Resisting Elements (EREs), designed to help resist seismic loads applied in the transverse direction of bridges. When adding longitudinal ductile diaphragms, a bidirectional ductile diaphragm system is created that can address seismic excitations acting along both the bridge's longitudinal and transverse axes. This paper investigates bidirectional ductile diaphragms with Buckling Restrained Braces (BRBs) in straight multi-span bridge with simply supported floating spans. The flexibility of the substructures in the transverse and longitudinal direction of the bridge is considered. Design procedures for the bidirectional ductile diaphragms are first proposed. An analytical model of the example bridge with bidirectional ductile diaphragms, designed based on the proposed methodology, is then built in SAP2000. Pushover and nonlinear time history analyses are performed on the bridge model, and corresponding results are presented. The effect of changing the longitudinal stiffness of the bidirectional ductile diaphragms in the end spans connecting to the abutment is also investigated, in order to better understand the impact on the bridge's dynamic performance.

Causes of wear of PDC bits and ways of improving their wear resistance

NASA Astrophysics Data System (ADS)

Timonin, VV; Smolentsev, AS; Shakhtorin, I. O.; Polushin, NI; Laptev, AI; Kushkhabiev, AS

2017-02-01

The scope of the paper encompasses basic factors that influence PDC bit efficiency. Feasible ways of eliminating the negatives are illustrated. The wash fluid flow in a standard bit is modeled, the resultant pattern of the bit washing is analyzed, and the recommendations are made on modification of the PDC bit design.

Graph-theoretic quantum system modelling for neuronal microtubules as hierarchical clustered quantum Hopfield networks

NASA Astrophysics Data System (ADS)

Srivastava, D. P.; Sahni, V.; Satsangi, P. S.

2014-08-01

Graph-theoretic quantum system modelling (GTQSM) is facilitated by considering the fundamental unit of quantum computation and information, viz. a quantum bit or qubit as a basic building block. Unit directional vectors "ket 0" and "ket 1" constitute two distinct fundamental quantum across variable orthonormal basis vectors, for the Hilbert space, specifying the direction of propagation of information, or computation data, while complementary fundamental quantum through, or flow rate, variables specify probability parameters, or amplitudes, as surrogates for scalar quantum information measure (von Neumann entropy). This paper applies GTQSM in continuum of protein heterodimer tubulin molecules of self-assembling polymers, viz. microtubules in the brain as a holistic system of interacting components representing hierarchical clustered quantum Hopfield network, hQHN, of networks. The quantum input/output ports of the constituent elemental interaction components, or processes, of tunnelling interactions and Coulombic bidirectional interactions are in cascade and parallel interconnections with each other, while the classical output ports of all elemental components are interconnected in parallel to accumulate micro-energy functions generated in the system as Hamiltonian, or Lyapunov, energy function. The paper presents an insight, otherwise difficult to gain, for the complex system of systems represented by clustered quantum Hopfield network, hQHN, through the application of GTQSM construct.

Enhanced noise tolerance for 10 Gb/s Bi-directional cross-wavelength reuse colorless WDM-PON by using spectrally shaped OFDM signals

NASA Astrophysics Data System (ADS)

Choudhury, Pallab K.

2018-05-01

Spectrally shaped orthogonal frequency division multiplexing (OFDM) signal for symmetric 10 Gb/s cross-wavelength reuse reflective semiconductor optical amplifier (RSOA) based colorless wavelength division multiplexed passive optical network (WDM-PON) is proposed and further analyzed to support broadband services of next generation high speed optical access networks. The generated OFDM signal has subcarriers in separate frequency ranges for downstream and upstream, such that the re-modulation noise can be effectively minimized in upstream data receiver. Moreover, the cross wavelength reuse approach improves the tolerance against Rayleigh backscattering noise due to the propagation of different wavelengths in the same feeder fiber. The proposed WDM-PON is successfully demonstrated for 25 km fiber with 16-QAM (quadrature amplitude modulation) OFDM signal having bandwidth of 2.5 GHz for 10 Gb/s operation and subcarrier frequencies in 3-5.5 GHz and DC-2.5 GHz for downstream (DS) and upstream (US) transmission respectively. The result shows that the proposed scheme maintains a good bit error rate (BER) performance below the forward error correction (FEC) limit of 3.8 × 10-3 at acceptable receiver sensitivity and provides a high resilience against re-modulation and Rayleigh backscattering noises as well as chromatic dispersion.

Analysis of bidirectional pattern synchrony of concentration-secretion pairs: implementation in the human testicular and adrenal axes.

PubMed

Liu, Peter Y; Pincus, Steven M; Keenan, Daniel M; Roelfsema, Ferdinand; Veldhuis, Johannes D

2005-02-01

The hypothalamo-pituitary-testicular and hypothalamo-pituitary-adrenal axes are prototypical coupled neuroendocrine systems. In the present study, we contrasted in vivo linkages within and between these two axes using methods without linearity assumptions. We examined 11 young (21-31 yr) and 8 older (62-74 yr) men who underwent frequent (every 2.5 min) blood sampling overnight for paired measurement of LH and testosterone and 35 adults (17 women and 18 men; 26-77 yr old) who underwent adrenocorticotropic hormone (ACTH) and cortisol measurements every 10 min for 24 h. To mirror physiological interactions, hormone secretion was first deconvolved from serial concentrations with a waveform-independent biexponential elimination model. Feedforward synchrony, feedback synchrony, and the difference in feedforward-feedback synchrony were quantified by the cross-approximate entropy (X-ApEn) statistic. These were applied in a forward (LH concentration template, examining pattern recurrence in testosterone secretion), reverse (testosterone concentration template, examining pattern recurrence in LH secretion), and differential (forward minus reverse) manner, respectively. Analogous concentration-secretion X-ApEn estimates were calculated from ACTH-cortisol pairs. X-ApEn, a scale- and model-independent measure of pattern reproducibility, disclosed 1) greater testosterone-LH feedback coordination than LH-testosterone feedforward synchrony in healthy men and significant and symmetric erosion of both feedforward and feedback linkages with aging; 2) more synchronous ACTH concentration-dependent feedforward than feedback drive of cortisol secretion, independent of gender and age; and 3) enhanced detection of bidirectional physiological regulation by in vivo pairwise concentration-secretion compared with concentration-concentration analyses. The linking of relevant biological input to output signals and vice versa should be useful in the dissection of the reciprocal control of neuroendocrine systems or even in the analysis of other nonendocrine networks.

A miniature bidirectional telemetry system for in-vivo gastric slow wave recordings

PubMed Central

Farajidavar, Aydin; O’Grady, Gregory; Rao, Smitha M.N.; Cheng, Leo K; Abell, Thomas; Chiao, J.-C.

2012-01-01

Stomach contractions are initiated and coordinated by an underlying electrical activity (slow waves), and electrical dysrhythmias accompany motility diseases. Electrical recordings taken directly from the stomach provide the most valuable data, but face technical constraints. Serosal or mucosal electrodes have cables that traverse the abdominal wall, or a natural orifice, causing discomfort and possible infection, and restricting mobility. These problems motivated the development of a wireless system. The bidirectional telemetric system constitutes a front-end transponder, a back-end receiver and a graphical user interface. The front-end module conditions the analog signals, then digitizes and loads the data into a radio for transmission. Data receipt at the back-end is acknowledged via a transceiver function. The system was validated in a bench-top study, then validated in-vivo using serosal electrodes connected simultaneously to a commercial wired system. The front-end module was 35×35×27 mm3 and weighed 20 g. Bench-top tests demonstrated reliable communication within a distance range of 30 m, power consumption of 13.5 mW, and 124-hour operation when utilizing a 560-mAh, 3-V battery. In-vivo, slow wave frequencies were recorded identically with the wireless and wired reference systems (2.4 cycles/min), automated activation time detection was modestly better for the wireless system (5% vs 14% false positive rate), and signal amplitudes were modestly higher via the wireless system (462 vs 386 μV; p<0.001). This telemetric system for slow wave acquisition is reliable, power efficient, readily portable and potentially implantable. The device will enable chronic monitoring and evaluation of slow wave patterns in animals and patients. PMID:22635054

Image processing on the image with pixel noise bits removed

NASA Astrophysics Data System (ADS)

Chuang, Keh-Shih; Wu, Christine

1992-06-01

Our previous studies used statistical methods to assess the noise level in digital images of various radiological modalities. We separated the pixel data into signal bits and noise bits and demonstrated visually that the removal of the noise bits does not affect the image quality. In this paper we apply image enhancement techniques on noise-bits-removed images and demonstrate that the removal of noise bits has no effect on the image property. The image processing techniques used are gray-level look up table transformation, Sobel edge detector, and 3-D surface display. Preliminary results show no noticeable difference between original image and noise bits removed image using look up table operation and Sobel edge enhancement. There is a slight enhancement of the slicing artifact in the 3-D surface display of the noise bits removed image.