Satisfying STEM Education Using the Arduino Microprocessor in C Programming

NASA Astrophysics Data System (ADS)

Hoffer, Brandyn M.

There exists a need to promote better Science Technology Engineering and Math (STEM) education at the high school level. To satisfy this need a series of hands-on laboratory assignments were created to be accompanied by 2 educational trainers that contain various electronic components. This project provides an interdisciplinary, hands-on approach to teaching C programming that meets several standards defined by the Tennessee Board of Education. Together the trainers and lab assignments also introduce key concepts in math and science while allowing students hands-on experience with various electronic components. This will allow students to mimic real world applications of using the C programming language while exposing them to technology not currently introduced in many high school classrooms. The developed project is targeted at high school students performing at or above the junior level and uses the Arduino Mega open-source Microprocessor and software as the primary control unit.

A Study of a Standard BIT Circuit.

DTIC Science & Technology

1977-02-01

IENDED BIT APPROACHES FOR QED MODULES AND APPLICATION OF THE ANALYTIC MEASURES 36 4.1 Built-In-Test for Memory Class Modules 37 4.1.1 Random Access...Implementation 68 4.1.5.5 Criti cal Parameters 68 4.1.5.6 QED Module Test Equipment Requirements 68 4.1.6 Application of Analytic Measures to the...Microprocessor BIT Techniques.. 121 4.2.9 Application of Analytic Measures to the Recommended BIT App roaches 125 4.2.10 Process Class BIT by Partial

Loran-C digital word generator for use with a KIM-1 microprocessor system

NASA Technical Reports Server (NTRS)

Nickum, J. D.

1977-01-01

The problem of translating the time of occurrence of received Loran-C pulses into a time, referenced to a particular period of occurrence is addressed and applied to the design of a digital word generator for a Loran-C sensor processor package. The digital information from this word generator is processed in a KIM-1 microprocessor system which is based on the MOS 6502 CPU. This final system will consist of a complete time difference sensor processor for determining position information using Loran-C charts. The system consists of the KIM-1 microprocessor module, a 4K RAM memory board, a user interface, and the Loran-C word generator.

Evaluation of function, performance, and preference as transfemoral amputees transition from mechanical to microprocessor control of the prosthetic knee.

PubMed

Hafner, Brian J; Willingham, Laura L; Buell, Noelle C; Allyn, Katheryn J; Smith, Douglas G

2007-02-01

To evaluate differences in function, performance, and preference between mechanical and microprocessor prosthetic knee control technologies. A-B-A-B reversal design. Home, community, and laboratory environments. Twenty-one unilateral, transfemoral amputees. Mechanical control prosthetic knee versus microprocessor control prosthetic knee (Otto Bock C-Leg). Stair rating, hill rating and time, obstacle course time, divided attention task accuracy and time, Amputee Mobility Predictor score, step activity, Prosthesis Evaluation Questionnaire score, Medical Outcomes Study 36-Item Short-Form Health Survey score, self-reported frequency of stumbles and falls, and self-reported concentration required for ambulation. Stair descent score, hill descent time, and hill sound-side step length showed significant (P<.01) improvement with the C-Leg. Users reported a significant (P<.05) decrease in frequency of stumbles and falls, frustration with falling, and difficulty in multitasking while using the microprocessor knee. Subject satisfaction with the C-Leg was significantly (P<.001) greater than the mechanical control prosthesis. The study population showed improved performance when negotiating stairs and hills, reduced frequency of stumbling and falling, and a preference for the microprocessor control C-Leg as compared with the mechanical control prosthetic knee.

SEU induced errors observed in microprocessor systems

DOE Office of Scientific and Technical Information (OSTI.GOV)

Asenek, V.; Underwood, C.; Oldfield, M.

In this paper, the authors present software tools for predicting the rate and nature of observable SEU induced errors in microprocessor systems. These tools are built around a commercial microprocessor simulator and are used to analyze real satellite application systems. Results obtained from simulating the nature of SEU induced errors are shown to correlate with ground-based radiation test data.

Neutron beam irradiation study of workload dependence of SER in a microprocessor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Michalak, Sarah E; Graves, Todd L; Hong, Ted

It is known that workloads are an important factor in soft error rates (SER), but it is proving difficult to find differentiating workloads for microprocessors. We have performed neutron beam irradiation studies of a commercial microprocessor under a wide variety of workload conditions from idle, performing no operations, to very busy workloads resembling real HPC, graphics, and business applications. There is evidence that the mean times to first indication of failure, MTFIF defined in Section II, may be different for some of the applications.

Fiber optic, Fabry-Perot high temperature sensor

NASA Technical Reports Server (NTRS)

James, K.; Quick, B.

1984-01-01

A digital, fiber optic temperature sensor using a variable Fabry-Perot cavity as the sensor element was analyzed, designed, fabricated, and tested. The fiber transmitted cavity reflection spectra is dispersed then converted from an optical signal to electrical information by a charged coupled device (CCD). A microprocessor-based color demodulation system converts the wavelength information to temperature. This general sensor concept not only utilizes an all-optical means of parameter sensing and transmitting, but also exploits microprocessor technology for automated control, calibration, and enhanced performance. The complete temperature sensor system was evaluated in the laboratory. Results show that the Fabry-Perot temperature sensor has good resolution (0.5% of full seale), high accuracy, and potential high temperature ( 1000 C) applications.

Microprocessor Controlled Isometric Contractions of Cat Gastrocnemius Muscle.

DTIC Science & Technology

1981-12-01

A-A15 504 AIR FORCE INST OF TECH WRIGHT-PATTERSON AFS OH 5CHOO--ETC F/6 6/2 MICROPROCESSOR CONTROLLED ISOMETRIC CONTRACTIONS OF CAT GASTROC-ETC(U) D...CONTROLLED ISOMETRIC CONTRACTIONS OF CAT GASTROCNEMIUS MUSCLE THESIS Presented to the Faculty of the School of Engineering of the Air Force Institute of...1981 Appzoved for public release; distribution unlimited. AFIT/GE/EE/81D-4O \\ MICROPROCESSOR CONTROLLED ISOMETRIC COMUtCTIONS OF CAT GASTfOCNEMIUS i

Distributed asynchronous microprocessor architectures in fault tolerant integrated flight systems

NASA Technical Reports Server (NTRS)

Dunn, W. R.

1983-01-01

The paper discusses the implementation of fault tolerant digital flight control and navigation systems for rotorcraft application. It is shown that in implementing fault tolerance at the systems level using advanced LSI/VLSI technology, aircraft physical layout and flight systems requirements tend to define a system architecture of distributed, asynchronous microprocessors in which fault tolerance can be achieved locally through hardware redundancy and/or globally through application of analytical redundancy. The effects of asynchronism on the execution of dynamic flight software is discussed. It is shown that if the asynchronous microprocessors have knowledge of time, these errors can be significantly reduced through appropiate modifications of the flight software. Finally, the papear extends previous work to show that through the combined use of time referencing and stable flight algorithms, individual microprocessors can be configured to autonomously tolerate intermittent faults.

Report on the formal specification and partial verification of the VIPER microprocessor

NASA Technical Reports Server (NTRS)

Brock, Bishop; Hunt, Warren A., Jr.

1991-01-01

The formal specification and partial verification of the VIPER microprocessor is reviewed. The VIPER microprocessor was designed by RSRE, Malvern, England, for safety critical computing applications (e.g., aircraft, reactor control, medical instruments, armaments). The VIPER was carefully specified and partially verified in an attempt to provide a microprocessor with completely predictable operating characteristics. The specification of VIPER is divided into several levels of abstraction, from a gate-level description up to an instruction execution model. Although the consistency between certain levels was demonstrated with mechanically-assisted mathematical proof, the formal verification of VIPER was never completed.

Safety and walking ability of KAFO users with the C-Brace® Orthotronic Mobility System, a new microprocessor stance and swing control orthosis

PubMed Central

Pröbsting, Eva; Kannenberg, Andreas; Zacharias, Britta

2016-01-01

Background: There are clear indications for benefits of stance control orthoses compared to locked knee ankle foot orthoses. However, stance control orthoses still have limited function compared with a sound human leg. Objectives: The aim of this study was to evaluate the potential benefits of a microprocessor stance and swing control orthosis compared to stance control orthoses and locked knee ankle foot orthoses in activities of daily living. Study design: Survey of lower limb orthosis users before and after fitting of a microprocessor stance and swing control orthosis. Methods: Thirteen patients with various lower limb pareses completed a baseline survey for their current orthotic device (locked knee ankle foot orthosis or stance control orthosis) and a follow-up for the microprocessor stance and swing control orthosis with the Orthosis Evaluation Questionnaire, a new self-reported outcome measure devised by modifying the Prosthesis Evaluation Questionnaire for use in lower limb orthotics and the Activities of Daily Living Questionnaire. Results: The Orthosis Evaluation Questionnaire results demonstrated significant improvements by microprocessor stance and swing control orthosis use in the total score and the domains of ambulation (p = .001), paretic limb health (p = .04), sounds (p = .02), and well-being (p = .01). Activities of Daily Living Questionnaire results showed significant improvements with the microprocessor stance and swing control orthosis with regard to perceived safety and difficulty of activities of daily living. Conclusion: The microprocessor stance and swing control orthosis may facilitate an easier, more physiological, and safer execution of many activities of daily living compared to traditional leg orthosis technologies. Clinical relevance This study compared patient-reported outcomes of a microprocessor stance and swing control orthosis (C-Brace) to those with traditional knee ankle foot orthosis and stance control orthosis devices. The C-Brace offers new functions including controlled knee flexion during weight bearing and dynamic swing control, resulting in significant improvements in perceived orthotic mobility and safety. PMID:27151648

Safety and walking ability of KAFO users with the C-Brace® Orthotronic Mobility System, a new microprocessor stance and swing control orthosis.

PubMed

Pröbsting, Eva; Kannenberg, Andreas; Zacharias, Britta

2017-02-01

There are clear indications for benefits of stance control orthoses compared to locked knee ankle foot orthoses. However, stance control orthoses still have limited function compared with a sound human leg. The aim of this study was to evaluate the potential benefits of a microprocessor stance and swing control orthosis compared to stance control orthoses and locked knee ankle foot orthoses in activities of daily living. Survey of lower limb orthosis users before and after fitting of a microprocessor stance and swing control orthosis. Thirteen patients with various lower limb pareses completed a baseline survey for their current orthotic device (locked knee ankle foot orthosis or stance control orthosis) and a follow-up for the microprocessor stance and swing control orthosis with the Orthosis Evaluation Questionnaire, a new self-reported outcome measure devised by modifying the Prosthesis Evaluation Questionnaire for use in lower limb orthotics and the Activities of Daily Living Questionnaire. The Orthosis Evaluation Questionnaire results demonstrated significant improvements by microprocessor stance and swing control orthosis use in the total score and the domains of ambulation ( p = .001), paretic limb health ( p = .04), sounds ( p = .02), and well-being ( p = .01). Activities of Daily Living Questionnaire results showed significant improvements with the microprocessor stance and swing control orthosis with regard to perceived safety and difficulty of activities of daily living. The microprocessor stance and swing control orthosis may facilitate an easier, more physiological, and safer execution of many activities of daily living compared to traditional leg orthosis technologies. Clinical relevance This study compared patient-reported outcomes of a microprocessor stance and swing control orthosis (C-Brace) to those with traditional knee ankle foot orthosis and stance control orthosis devices. The C-Brace offers new functions including controlled knee flexion during weight bearing and dynamic swing control, resulting in significant improvements in perceived orthotic mobility and safety.

Microprocessor Simulation: A Training Technique.

ERIC Educational Resources Information Center

Oscarson, David J.

1982-01-01

Describes the design and application of a microprocessor simulation using BASIC for formal training of technicians and managers and as a management tool. Illustrates the utility of the modular approach for the instruction and practice of decision-making techniques. (SK)

Concept report: Microprocessor control of electrical power system

NASA Technical Reports Server (NTRS)

Perry, E.

1977-01-01

An electrical power system which uses a microprocessor for systems control and monitoring is described. The microprocessor controlled system permits real time modification of system parameters for optimizing a system configuration, especially in the event of an anomaly. By reducing the components count, the assembling and testing of the unit is simplified, and reliability is increased. A resuable modular power conversion system capable of satisfying a large percentage of space applications requirements is examined along with the programmable power processor. The PC global controller which handles systems control and external communication is analyzed, and a software description is given. A systems application summary is also included.

Microprocessor, Setx, Xrn2, and Rrp6 co-operate to induce premature termination of transcription by RNAPII.

PubMed

Wagschal, Alexandre; Rousset, Emilie; Basavarajaiah, Poornima; Contreras, Xavier; Harwig, Alex; Laurent-Chabalier, Sabine; Nakamura, Mirai; Chen, Xin; Zhang, Ke; Meziane, Oussama; Boyer, Frédéric; Parrinello, Hugues; Berkhout, Ben; Terzian, Christophe; Benkirane, Monsef; Kiernan, Rosemary

2012-09-14

Transcription elongation is increasingly recognized as an important mechanism of gene regulation. Here, we show that microprocessor controls gene expression in an RNAi-independent manner. Microprocessor orchestrates the recruitment of termination factors Setx and Xrn2, and the 3'-5' exoribonuclease, Rrp6, to initiate RNAPII pausing and premature termination at the HIV-1 promoter through cleavage of the stem-loop RNA, TAR. Rrp6 further processes the cleavage product, which generates a small RNA that is required to mediate potent transcriptional repression and chromatin remodeling at the HIV-1 promoter. Using chromatin immunoprecipitation coupled to high-throughput sequencing (ChIP-seq), we identified cellular gene targets whose transcription is modulated by microprocessor. Our study reveals RNAPII pausing and premature termination mediated by the co-operative activity of ribonucleases, Drosha/Dgcr8, Xrn2, and Rrp6, as a regulatory mechanism of RNAPII-dependent transcription elongation. Copyright © 2012 Elsevier Inc. All rights reserved.

A Microprocessor-Based Real-Time Simulator of a Turbofan Engine

DTIC Science & Technology

1988-01-01

NASA AVSCOM Technical Memorandum 100889 Technical Report 88-C-011 Lfl A Microprocessor-Based Real-Time Simulator of a Turbofan Engine CD I Jonathan S...Accession For NTIS GRA&I A MICROPROCESSOR-BASED REAL-TIME SIMULATOR DTIC TABUnannounced OF A TURBOFAN ENGINE Justifiaation, Jonathan S. Litt Propulsion...the F100 engine without augmentation (without afterburning). HYTESS is a simplified simulation written in FORTRAN of a generalized turbofan engine . To

Instruction-Level Characterization of Scientific Computing Applications Using Hardware Performance Counters

DOE Office of Scientific and Technical Information (OSTI.GOV)

Luo, Y.; Cameron, K.W.

1998-11-24

Workload characterization has been proven an essential tool to architecture design and performance evaluation in both scientific and commercial computing areas. Traditional workload characterization techniques include FLOPS rate, cache miss ratios, CPI (cycles per instruction or IPC, instructions per cycle) etc. With the complexity of sophisticated modern superscalar microprocessors, these traditional characterization techniques are not powerful enough to pinpoint the performance bottleneck of an application on a specific microprocessor. They are also incapable of immediately demonstrating the potential performance benefit of any architectural or functional improvement in a new processor design. To solve these problems, many people rely on simulators,more » which have substantial constraints especially on large-scale scientific computing applications. This paper presents a new technique of characterizing applications at the instruction level using hardware performance counters. It has the advantage of collecting instruction-level characteristics in a few runs virtually without overhead or slowdown. A variety of instruction counts can be utilized to calculate some average abstract workload parameters corresponding to microprocessor pipelines or functional units. Based on the microprocessor architectural constraints and these calculated abstract parameters, the architectural performance bottleneck for a specific application can be estimated. In particular, the analysis results can provide some insight to the problem that only a small percentage of processor peak performance can be achieved even for many very cache-friendly codes. Meanwhile, the bottleneck estimation can provide suggestions about viable architectural/functional improvement for certain workloads. Eventually, these abstract parameters can lead to the creation of an analytical microprocessor pipeline model and memory hierarchy model.« less

COED Transactions, Vol. IX, No. 6, June 1977. An Introductory Course in Microprocessors and Microcomputers.

ERIC Educational Resources Information Center

Marcovitz, Alan B., Ed.

This paper describes an introductory course in microprocessors and microcomputers implemented at Grossmont College. The current state-of-the-art in the microprocessor field is discussed, with special emphasis on the 8-bit MOS single-chip processors which are the most commonly used devices. Objectives and guidelines for the course are presented,…

Applications of Microcomputers in the Teaching of Physics 6502 Software.

ERIC Educational Resources Information Center

Marsh, David P.

1980-01-01

Described is a variety of uses of the microcomputer when coupled with software available for systems using 6502 microprocessors. Included are several computer programs which exhibit some of the possibilities for programing the 6502 microprocessors. (DS)

Microprocessor dynamics and interactions at endogenous imprinted C19MC microRNA genes.

PubMed

Bellemer, Clément; Bortolin-Cavaillé, Marie-Line; Schmidt, Ute; Jensen, Stig Mølgaard Rask; Kjems, Jørgen; Bertrand, Edouard; Cavaillé, Jérôme

2012-06-01

Nuclear primary microRNA (pri-miRNA) processing catalyzed by the DGCR8-Drosha (Microprocessor) complex is highly regulated. Little is known, however, about how microRNA biogenesis is spatially organized within the mammalian nucleus. Here, we image for the first time, in living cells and at the level of a single microRNA cluster, the intranuclear distribution of untagged, endogenously-expressed pri-miRNAs generated at the human imprinted chromosome 19 microRNA cluster (C19MC), from the environment of transcription sites to single molecules of fully released DGCR8-bound pri-miRNAs dispersed throughout the nucleoplasm. We report that a large fraction of Microprocessor concentrates onto unspliced C19MC pri-miRNA deposited in close proximity to their genes. Our live-cell imaging studies provide direct visual evidence that DGCR8 and Drosha are targeted post-transcriptionally to C19MC pri-miRNAs as a preformed complex but dissociate separately. These dynamics support the view that, upon pri-miRNA loading and most probably concomitantly with Drosha-mediated cleavages, Microprocessor undergoes conformational changes that trigger the release of Drosha while DGCR8 remains stably bound to pri-miRNA.

The development of a microprocessor-controlled linearly-actuated valve assembly

NASA Technical Reports Server (NTRS)

Wall, R. H.

1984-01-01

The development of a proportional fluid control valve assembly is presented. This electromechanical system is needed for space applications to replace the current proportional flow controllers. The flow is controlled by a microprocessor system that monitors the control parameters of upstream pressure and requested volumetric flow rate. The microprocessor achieves the proper valve stem displacement by means of a digital linear actuator. A linear displacement sensor is used to measure the valve stem position. This displacement is monitored by the microprocessor system as a feedback signal to close the control loop. With an upstream pressure between 15 and 47 psig, the developed system operates between 779 standard CU cm/sec (SCCS) and 1543 SCCS.

PDSparc: A Drop-in Replacement for LEON3 Written Using Synopsys Processor Designer

DTIC Science & Technology

2015-08-18

Written Using  Synopsys Processor Designer1  David Whelihan, Ph.D. and Kate Thurmer  MIT Lincoln Laboratory, Lexington, MA, USA    ABSTRACT  Microprocessors ...internet-enabled appliances has opened a significant new niche: the Application Specific Standard Product (ASSP) microprocessor . These processors... microprocessor is a small part of a working system and requires peripherals such as DRAM controllers and communication sub-systems to properly carry out its

RS-600 programmable controller: Solar heating and cooling

NASA Technical Reports Server (NTRS)

1978-01-01

Three identical microprocessor control subsystems were developed which can be used in heating, heating and cooling, and/or hot water systems for single family, multifamily, or commercial applications. The controller incorporates a low cost, highly reliable (all solid state) microprocessor which can be easily reprogrammed.

Innovative architectures for dense multi-microprocessor computers

NASA Technical Reports Server (NTRS)

Larson, Robert E.

1989-01-01

The purpose is to summarize a Phase 1 SBIR project performed for the NASA/Langley Computational Structural Mechanics Group. The project was performed from February to August 1987. The main objectives of the project were to: (1) expand upon previous research into the application of chordal ring architectures to the general problem of designing multi-microcomputer architectures, (2) attempt to identify a family of chordal rings such that each chordal ring can be simply expanded to produce the next member of the family, (3) perform a preliminary, high-level design of an expandable multi-microprocessor computer based upon chordal rings, (4) analyze the potential use of chordal ring based multi-microprocessors for sparse matrix problems and other applications arising in computational structural mechanics.

A microarchitecture for resource-limited superscalar microprocessors

NASA Astrophysics Data System (ADS)

Basso, Todd David

1999-11-01

Microelectronic components in space and satellite systems must be resistant to total dose radiation, single-even upset, and latchup in order to accomplish their missions. The demand for inexpensive, high-volume, radiation hardened (rad-hard) integrated circuits (ICs) is expected to increase dramatically as the communication market continues to expand. Motorola's Complementary Gallium Arsenide (CGaAsTM) technology offers superior radiation tolerance compared to traditional CMOS processes, while being more economical than dedicated rad-hard CMOS processes. The goals of this dissertation are to optimize a superscalar microarchitecture suitable for CGaAsTM microprocessors, develop circuit techniques for such applications, and evaluate the potential of CGaAsTM for the development of digital VLSI circuits. Motorola's 0.5 mum CGaAsTM process is summarized and circuit techniques applicable to digital CGaAsTM are developed. Direct coupled FET, complementary, and domino logic circuits are compared based on speed, power, area, and noise margins. These circuit techniques are employed in the design of a 600 MHz PowerPCTM arithmetic logic unit. The dissertation emphasizes CGaASTM-specific design considerations, specifically, low integration level. A baseline superscalar microarchitecture is defined and SPEC95 integer benchmark simulations are used to evaluate the applicability of advanced architectural features to microprocessors having low integration levels. The performance simulations center around the optimization of a simple superscalar core, small-scale branch prediction, instruction prefetching, and an off-chip primary data cache. The simulation results are used to develop a superscalar microarchitecture capable of outperforming a comparable sequential pipeline, while using only 500,000 transistors. The architecture, running at 200 MHz, is capable of achieving an estimated 153 MIPS, translating to a 27% performance increase over a comparable traditional pipelined microprocessor. The proposed microarchitecture is process independent and can be applied to low-cost, or transistor-limited applications. The proposed microarchitecture is implemented in the design of a 0.35 mum CMOS microprocessor, and the design of a 0.5 mum CGaAsTM micro-processor. The two technologies and designs are compared to ascertain the state of CGaAsTM for digital VLSI applications.

Application Specific Chemical Information Microprocessor (ASCI mu P)

DTIC Science & Technology

1999-09-30

lithography created channels in polydimethylsiloxane polymer. 1C. Optical micrograph of 100 um line widths using soft lithography Progress has also been made...also collaborated with Dr. Jose Almirall at Florida International University and have accomplished the HPLC method development of explosives detection...analytical materials. We have established the base for LIF electrophoretic chip analysis and similarly for the electrochemcial detection. We have learned the

Teacher Training for High Technology. Final Report.

ERIC Educational Resources Information Center

Goettmann, Thomas L.

The objective of this project was to develop computer literacy and a working knowledge of microprocessor applications and digital circuits for teachers in selected vocational subject areas. Twenty-four vocational trade and industry teachers completed 16 hours of training in microprocessor skills for computerized instruction and curriculum update.…

Safety of Vital Control and Communication Systems in Guided Ground Transportation : Analysis of Railroad Signaling System Microprocessor Interlocking

DOT National Transportation Integrated Search

1993-05-01

This study has been conducted with the goal of gaining an insight into the issues of maintaining vital signal systems implemented with microprocessor chips and of making field changes to the application of such systems. To relate these abstract topic...

High-Speed Integrated Circuits for Military Applications.

DTIC Science & Technology

1979-11-01

1.5 pm circuits at the present time. " Market economics do not justify these circuits in the time frame of the VHSI program." See also Ref. 9. 7 per...on microprocessors currently in production, but the huge commercial market that is thought to exist for these devices when they can at last be...Subsection I, below). The single-chip microprocessor dominates the commercial market and those military applications for which their through- put is

The formal verification of generic interpreters

NASA Technical Reports Server (NTRS)

Windley, P.; Levitt, K.; Cohen, G. C.

1991-01-01

The task assignment 3 of the design and validation of digital flight control systems suitable for fly-by-wire applications is studied. Task 3 is associated with formal verification of embedded systems. In particular, results are presented that provide a methodological approach to microprocessor verification. A hierarchical decomposition strategy for specifying microprocessors is also presented. A theory of generic interpreters is presented that can be used to model microprocessor behavior. The generic interpreter theory abstracts away the details of instruction functionality, leaving a general model of what an interpreter does.

46 CFR 62.25-25 - Programable systems and devices.

Code of Federal Regulations, 2013 CFR

2013-10-01

...-25 Shipping COAST GUARD, DEPARTMENT OF HOMELAND SECURITY (CONTINUED) MARINE ENGINEERING VITAL SYSTEM... range of the equipment. (b) Operating programs for microprocessor-based or computer-based vital control... power resumption. (c) If a microprocessor-based or computer-based system serves both vital and non-vital...

46 CFR 62.25-25 - Programable systems and devices.

Code of Federal Regulations, 2010 CFR

2010-10-01

...-25 Shipping COAST GUARD, DEPARTMENT OF HOMELAND SECURITY (CONTINUED) MARINE ENGINEERING VITAL SYSTEM... range of the equipment. (b) Operating programs for microprocessor-based or computer-based vital control... power resumption. (c) If a microprocessor-based or computer-based system serves both vital and non-vital...

46 CFR 62.25-25 - Programable systems and devices.

Code of Federal Regulations, 2012 CFR

2012-10-01

...-25 Shipping COAST GUARD, DEPARTMENT OF HOMELAND SECURITY (CONTINUED) MARINE ENGINEERING VITAL SYSTEM... range of the equipment. (b) Operating programs for microprocessor-based or computer-based vital control... power resumption. (c) If a microprocessor-based or computer-based system serves both vital and non-vital...

46 CFR 62.25-25 - Programable systems and devices.

Code of Federal Regulations, 2011 CFR

2011-10-01

...-25 Shipping COAST GUARD, DEPARTMENT OF HOMELAND SECURITY (CONTINUED) MARINE ENGINEERING VITAL SYSTEM... range of the equipment. (b) Operating programs for microprocessor-based or computer-based vital control... power resumption. (c) If a microprocessor-based or computer-based system serves both vital and non-vital...

NSC 800, 8-bit CMOS microprocessor

NASA Technical Reports Server (NTRS)

Suszko, S. F.

1984-01-01

The NSC 800 is an 8-bit CMOS microprocessor manufactured by National Semiconductor Corp., Santa Clara, California. The 8-bit microprocessor chip with 40-pad pin-terminals has eight address buffers (A8-A15), eight data address -- I/O buffers (AD(sub 0)-AD(sub 7)), six interrupt controls and sixteen timing controls with a chip clock generator and an 8-bit dynamic RAM refresh circuit. The 22 internal registers have the capability of addressing 64K bytes of memory and 256 I/O devices. The chip is fabricated on N-type (100) silicon using self-aligned polysilicon gates and local oxidation process technology. The chip interconnect consists of four levels: Aluminum, Polysi 2, Polysi 1, and P(+) and N(+) diffusions. The four levels, except for contact interface, are isolated by interlevel oxide. The chip is packaged in a 40-pin dual-in-line (DIP), side brazed, hermetically sealed, ceramic package with a metal lid. The operating voltage for the device is 5 V. It is available in three operating temperature ranges: 0 to +70 C, -40 to +85 C, and -55 to +125 C. Two devices were submitted for product evaluation by F. Stott, MTS, JPL Microprocessor Specialist. The devices were pencil-marked and photographed for identification.

Special purpose parallel computer architecture for real-time control and simulation in robotic applications

NASA Technical Reports Server (NTRS)

Fijany, Amir (Inventor); Bejczy, Antal K. (Inventor)

1993-01-01

This is a real-time robotic controller and simulator which is a MIMD-SIMD parallel architecture for interfacing with an external host computer and providing a high degree of parallelism in computations for robotic control and simulation. It includes a host processor for receiving instructions from the external host computer and for transmitting answers to the external host computer. There are a plurality of SIMD microprocessors, each SIMD processor being a SIMD parallel processor capable of exploiting fine grain parallelism and further being able to operate asynchronously to form a MIMD architecture. Each SIMD processor comprises a SIMD architecture capable of performing two matrix-vector operations in parallel while fully exploiting parallelism in each operation. There is a system bus connecting the host processor to the plurality of SIMD microprocessors and a common clock providing a continuous sequence of clock pulses. There is also a ring structure interconnecting the plurality of SIMD microprocessors and connected to the clock for providing the clock pulses to the SIMD microprocessors and for providing a path for the flow of data and instructions between the SIMD microprocessors. The host processor includes logic for controlling the RRCS by interpreting instructions sent by the external host computer, decomposing the instructions into a series of computations to be performed by the SIMD microprocessors, using the system bus to distribute associated data among the SIMD microprocessors, and initiating activity of the SIMD microprocessors to perform the computations on the data by procedure call.

An Ill-Structured PBL-Based Microprocessor Course without Formal Laboratory

ERIC Educational Resources Information Center

Kim, Jungkuk

2012-01-01

This paper introduces a problem-based learning (PBL) microprocessor application course designed according to the following strategies: 1) hands-on training without having a formal laboratory, and 2) intense student-centered cooperative learning through an ill-structured problem. PBL was adopted as the core educational technique of the course to…

G-cueing microcontroller (a microprocessor application in simulators)

NASA Technical Reports Server (NTRS)

Horattas, C. G.

1980-01-01

A g cueing microcontroller is described which consists of a tandem pair of microprocessors, dedicated to the task of simulating pilot sensed cues caused by gravity effects. This task includes execution of a g cueing model which drives actuators that alter the configuration of the pilot's seat. The g cueing microcontroller receives acceleration commands from the aerodynamics model in the main computer and creates the stimuli that produce physical acceleration effects of the aircraft seat on the pilots anatomy. One of the two microprocessors is a fixed instruction processor that performs all control and interface functions. The other, a specially designed bipolar bit slice microprocessor, is a microprogrammable processor dedicated to all arithmetic operations. The two processors communicate with each other by a shared memory. The g cueing microcontroller contains its own dedicated I/O conversion modules for interface with the seat actuators and controls, and a DMA controller for interfacing with the simulation computer. Any application which can be microcoded within the available memory, the available real time and the available I/O channels, could be implemented in the same controller.

A microprocessor application to a strapdown laser gyro navigator

NASA Technical Reports Server (NTRS)

Giardina, C.; Luxford, E.

1980-01-01

The replacement of analog circuit control loops for laser gyros (path length control, cross axis temperature compensation loops, dither servo and current regulators) with digital filters residing in microcomputers is addressed. In addition to the control loops, a discussion is given on applying the microprocessor hardware to compensation for coning and skulling motion where simple algorithms are processed at high speeds to compensate component output data (digital pulses) for linear and angular vibration motions. Highlights are given on the methodology and system approaches used in replacing differential equations describing the analog system in terms of the mechanized difference equations of the microprocessor. Standard one for one frequency domain techniques are employed in replacing analog transfer functions by their transform counterparts. Direct digital design techniques are also discussed along with their associated benefits. Time and memory loading analyses are also summarized, as well as signal and microprocessor architecture. Trade offs in algorithm, mechanization, time/memory loading, accuracy, and microprocessor architecture are also given.

Establishment of cells to monitor Microprocessor through fusion genes of microRNA and GFP

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tsutsui, Motomu; Hasegawa, Hitoki; Adachi, Koichi

Microprocessor, the complex of Drosha and DGCR8, promotes the processing of primary microRNA to precursor microRNA, which is a crucial step for microRNA maturation. So far, no convenient assay systems have been developed for observing this step in vivo. Here we report the establishment of highly sensitive cellular systems where we can visually monitor the function of Microprocessor. During a series of screening of transfectants with fusion genes of the EGFP cDNA and primary microRNA genes, we have obtained certain cell lines where introduction of siRNA against DGCR8 or Drosha strikingly augments GFP signals. In contrast, these cells have notmore » responded to Dicer siRNA; thus they have a unique character that GFP signals should be negatively and specifically correlated to the action of Microprocessor among biogenesis of microRNA. These cell lines can be useful tools for real-time analysis of Microprocessor action in vivo and identifying its novel modulators.« less

Flexible Architecture for FPGAs in Embedded Systems

NASA Technical Reports Server (NTRS)

Clark, Duane I.; Lim, Chester N.

2012-01-01

Commonly, field-programmable gate arrays (FPGAs) being developed in cPCI embedded systems include the bus interface in the FPGA. This complicates the development because the interface is complicated and requires a lot of development time and FPGA resources. In addition, flight qualification requires a substantial amount of time be devoted to just this interface. Another complication of putting the cPCI interface into the FPGA being developed is that configuration information loaded into the device by the cPCI microprocessor is lost when a new bit file is loaded, requiring cumbersome operations to return the system to an operational state. Finally, SRAM-based FPGAs are typically programmed via specialized cables and software, with programming files being loaded either directly into the FPGA, or into PROM devices. This can be cumbersome when doing FPGA development in an embedded environment, and does not have an easy path to flight. Currently, FPGAs used in space applications are usually programmed via multiple space-qualified PROM devices that are physically large and require extra circuitry (typically including a separate one-time programmable FPGA) to enable them to be used for this application. This technology adds a cPCI interface device with a simple, flexible, high-performance backend interface supporting multiple backend FPGAs. It includes a mechanism for programming the FPGAs directly via the microprocessor in the embedded system, eliminating specialized hardware, software, and PROM devices and their associated circuitry. It has a direct path to flight, and no extra hardware and minimal software are required to support reprogramming in flight. The device added is currently a small FPGA, but an advantage of this technology is that the design of the device does not change, regardless of the application in which it is being used. This means that it needs to be qualified for flight only once, and is suitable for one-time programmable devices or an application specific integrated circuit (ASIC). An application programming interface (API) further reduces the development time needed to use the interface device in a system.

A Multi-Media CAI Terminal Based upon a Microprocessor with Applications for the Handicapped.

ERIC Educational Resources Information Center

Brebner, Ann; Hallworth, H. J.

The design of the CAI interface described is based on the microprocessor in order to meet three basic requirements for providing appropriate instruction to the developmentally handicapped: (1) portability, so that CAI can be taken into the customary learning environment; (2) reliability; and (3) flexibility, to permit use of new input and output…

Implementation of the DAST ARW II control laws using an 8086 microprocessor and an 8087 floating-point coprocessor. [drones for aeroelasticity research

NASA Technical Reports Server (NTRS)

Kelly, G. L.; Berthold, G.; Abbott, L.

1982-01-01

A 5 MHZ single-board microprocessor system which incorporates an 8086 CPU and an 8087 Numeric Data Processor is used to implement the control laws for the NASA Drones for Aerodynamic and Structural Testing, Aeroelastic Research Wing II. The control laws program was executed in 7.02 msec, with initialization consuming 2.65 msec and the control law loop 4.38 msec. The software emulator execution times for these two tasks were 36.67 and 61.18, respectively, for a total of 97.68 msec. The space, weight and cost reductions achieved in the present, aircraft control application of this combination of a 16-bit microprocessor with an 80-bit floating point coprocessor may be obtainable in other real time control applications.

A functional comparison of conventional knee-ankle-foot orthoses and a microprocessor-controlled leg orthosis system based on biomechanical parameters.

PubMed

Schmalz, Thomas; Pröbsting, Eva; Auberger, Roland; Siewert, Gordon

2016-04-01

The microprocessor-controlled leg orthosis C-Brace enables patients with paretic or paralysed lower limb muscles to use dampened knee flexion under weight-bearing and speed-adapted control of the swing phase. The objective of the present study was to investigate the new technical functions of the C-Brace orthosis, based on biomechanical parameters. The study enrolled six patients. The C-Brace orthosis is compared with conventional leg orthoses (four stance control orthoses, two locked knee-ankle-foot orthoses) using biomechanical parameters of level walking, descending ramps and descending stairs. Ground reaction forces, joint moments and kinematic parameters were measured for level walking as well as ascending and descending ramps and stairs. With the C-Brace, a nearly natural stance phase knee flexion was measured during level walking (mean value 11° ± 5.6°). The maximum swing phase knee flexion angle of the C-Brace approached the normal value of 65° more closely than the stance control orthoses (66° ± 8.5° vs 74° ± 6.4°). No significant differences in the joint moments were found between the C-Brace and stance control orthosis conditions. In contrast to the conventional orthoses, all patients were able to ambulate ramps and stairs using a step-over-step technique with C-Brace (flexion angle 64.6° ± 8.2° and 70.5° ± 12.4°). The results show that the functions of the C-Brace for situation-dependent knee flexion under weight bearing have been used by patients with a high level of confidence. The functional benefits of the C-Brace in comparison with the conventional orthotic mechanisms could be demonstrated most clearly for descending ramps and stairs. The C-Brace orthosis is able to combine improved orthotic function with sustained orthotic safety. © The International Society for Prosthetics and Orthotics 2014.

Application of Fault-Tolerant Computing For Spacecraft Using Commercial-Off-The-Shelf Microprocessors

DTIC Science & Technology

2000-06-01

real - time operating system and design of a human-computer interface (HCI) for a triple modular redundant (TMR) fault-tolerant microprocessor for use in space-based applications. Once disadvantage of using COTS hardware components is their susceptibility to the radiation effects present in the space environment. and specifically, radiation-induced single-event upsets (SEUs). In the event of an SEU, a fault-tolerant system can mitigate the effects of the upset and continue to process from the last known correct system state. The TMR basic hardware

Stability of nano-fluids and their use for thermal management of a microprocessor: an experimental and numerical study

NASA Astrophysics Data System (ADS)

Shoukat, Ahmad Adnan; Shaban, Muhammad; Israr, Asif; Shah, Owaisur Rahman; Khan, Muhammad Zubair; Anwar, Muhammad

2018-03-01

We investigate the heat transfer effect of different types of Nano-fluids on the pin fin heat sinks used in computer's microprocessor. Nano-particles of Aluminum oxide have been used with volumetric concentrations of 0.002% and Silver oxide with volumetric concentrations of 0.001% in the base fluid of deionized water. We have also used Aluminum oxide with ethylene glycol at volumetric concentrations of 0.002%. We report the cooling rates of Nano-fluids for pin-fin heat to cool the microprocessor and compare these with the cooling rate of pure water. We use a microprocessor heat generator in this investigation. The base temperature is obtained using surface heater of power 130 W. The main purpose of this work is to minimize the base temperature, and increase the heat transfer rate of the water block and radiator. The temperature of the heat sink is maintained at 110 °C which is nearly equal to the observed computer microprocessor temperature. We also provide the base temperature at different Reynolds's number using the above mention Nano-fluids with different volumetric concentrations.

Low cost Czochralski crystal growing technology. Near implementation of the flat plate photovoltaic cost reduction of the low cost solar array project

NASA Technical Reports Server (NTRS)

Roberts, E. G.

1980-01-01

Equipment developed for the manufacture of over 100 kg of silicon ingot from one crucible by rechanging from another crucible is described. Attempts were made to eliminate the cost of raising the furnace temperature to 250 C above the melting point of silicon by using an RF coil to melt polycrystalline silicon rod as a means of rechanging the crucible. Microprocessor control of the straight growth process was developed and domonstrated for both 4 inch and 6 inch diameter. Both meltdown and melt stabilization processes were achieved using operator prompting through the microprocessor. The use of the RF work coil in poly rod melting as a heat sink in the accelerated growth process was unsuccessful. The total design concept for fabrication and interfacing of the total cold crucible system was completed.

Impact of a stance phase microprocessor-controlled knee prosthesis on level walking in lower functioning individuals with a transfemoral amputation.

PubMed

Eberly, Valerie J; Mulroy, Sara J; Gronley, JoAnne K; Perry, Jacquelin; Yule, William J; Burnfield, Judith M

2014-12-01

For individuals with transfemoral amputation, walking with a prosthesis presents challenges to stability and increases the demand on the hip of the prosthetic limb. Increasing age or comorbidities magnify these challenges. Computerized prosthetic knee joints improve stability and efficiency of gait, but are seldom prescribed for less physically capable walkers who may benefit from them. To compare level walking function while wearing a microprocessor-controlled knee (C-Leg Compact) prosthesis to a traditionally prescribed non-microprocessor-controlled knee prosthesis for Medicare Functional Classification Level K-2 walkers. Crossover. Stride characteristics, kinematics, kinetics, and electromyographic activity were recorded in 10 participants while walking with non-microprocessor-controlled knee and Compact prostheses. Walking with the Compact produced significant increase in velocity, cadence, stride length, single-limb support, and heel-rise timing compared to walking with the non-microprocessor-controlled knee prosthesis. Hip and thigh extension during late stance improved bilaterally. Ankle dorsiflexion, knee extension, and hip flexion moments of the prosthetic limb were significantly improved. Improvements in walking function and stability on the prosthetic limb were demonstrated by the K-2 level walkers when using the C-Leg Compact prosthesis. Understanding the impact of new prosthetic designs on gait mechanics is essential to improve prescription guidelines for deconditioned or older persons with transfemoral amputation. Prosthetic designs that improve stability for safety and walking function have the potential to improve community participation and quality of life. © The International Society for Prosthetics and Orthotics 2013.

Single-Event Upset and Scaling Trends in New Generation of the Commercial SOI PowerPC Microprocessors

NASA Technical Reports Server (NTRS)

Irom, Farokh; Farmanesh, Farhad; Kouba, Coy K.

2006-01-01

SEU from heavy-ions is measured for SOI PowerPC microprocessors. Results for 0.13 micron PowerPC with 1.1V core voltages increases over 1.3V versions. This suggests that improvement in SEU for scaled devices may be reversed. In recent years there has been interest in the possible use of unhardened commercial microprocessors in space because of their superior performance compared to hardened processors. However, unhardened devices are susceptible to upset from radiation space. More information is needed on how they respond to radiation before they can be used in space. Only a limited number of advanced microprocessors have been subjected to radiation tests, which are designed with lower clock frequencies and higher internal core voltage voltages than recent devices [1-6]. However the trend for commercial Silicon-on-insulator (SOI) microprocessors is to reduce feature size and internal core voltage and increase the clock frequency. Commercial microprocessors with the PowerPC architecture are now available that use partially depleted SOI processes with feature size of 90 nm and internal core voltage as low as 1.0 V and clock frequency in the GHz range. Previously, we reported SEU measurements for SOI commercial PowerPCs with feature size of 0.18 and 0.13 m [7, 8]. The results showed an order of magnitude reduction in saturated cross section compared to CMOS bulk counterparts. This paper examines SEUs in advanced commercial SOI microprocessors, focusing on SEU sensitivity of D-Cache and hangs with feature size and internal core voltage. Results are presented for the Motorola SOI processor with feature sizes of 0.13 microns and internal core voltages of 1.3 and 1.1 V. These results are compared with results for the Motorola SOI processors with feature size of 0.18 microns and internal core voltage of 1.6 and 1.3 V.

The Shock and Vibration Digest. Volume 18, Number 9

DTIC Science & Technology

1986-09-01

microprocessors. ods for mobility measurements, methods for Modeling and computation of transient rotor analyzing mobility data, mathematical modeling...behavior and nonlinear fluid-film bearing from mobility data, and applications of modal behavior will be described. Sessions will be test results will be...Zoned Viscoelastic Analysis of the Response of Dams to Earth- soil, quakesR. Abascal, J. Dominguez V. Lotfi , N6 445 • . , .-e ’SJ. PP %-’ , Ph.D. Thesis

Experience with custom processors in space flight applications

NASA Technical Reports Server (NTRS)

Fraeman, M. E.; Hayes, J. R.; Lohr, D. A.; Ballard, B. W.; Williams, R. L.; Henshaw, R. M.

1991-01-01

The Applied Physics Laboratory (APL) has developed a magnetometer instrument for a swedish satellite named Freja with launch scheduled for August 1992 on a Chinese Long March rocket. The magnetometer controller utilized a custom microprocessor designed at APL with the Genesil silicon compiler. The processor evolved from our experience with an older bit-slice design and two prior single chip efforts. The architecture of our microprocessor greatly lowered software development costs because it was optimized to provide an interactive and extensible programming environment hosted by the target hardware. Radiation tolerance of the microprocessor was also tested and was adequate for Freja's mission -- 20 kRad(Si) total dose and very infrequent latch-up and single event upset events.

Microprocessor Control Design for a Low-Head Crossflow Turbine.

DTIC Science & Technology

1985-03-01

Controllers For a Typical 10 KW Hydroturbine ............ 1-5 I-1 Ely’s Crossflow Turbine . ........ 11-2 11-2 Basic Turbine * * 0 * 0 11-5 11-3 Turbine...the systems. For example, a 25 kilowatt hydroturbine built and installed by Bell Hydroelectric would cost approximately $20,000 in 1978 (6:49). The...O Manual Controller S2 E- Microprocessor Controller 1 2 3 4 5 6 7 8 YEARS Fig. 1-2 Comparative Costs of Controllers For a Typical 10 KW Hydroturbine

Microfluidic Pneumatic Logic Circuits and Digital Pneumatic Microprocessors for Integrated Microfluidic Systems

PubMed Central

Rhee, Minsoung

2010-01-01

We have developed pneumatic logic circuits and microprocessors built with microfluidic channels and valves in polydimethylsiloxane (PDMS). The pneumatic logic circuits perform various combinational and sequential logic calculations with binary pneumatic signals (atmosphere and vacuum), producing cascadable outputs based on Boolean operations. A complex microprocessor is constructed from combinations of various logic circuits and receives pneumatically encoded serial commands at a single input line. The device then decodes the temporal command sequence by spatial parallelization, computes necessary logic calculations between parallelized command bits, stores command information for signal transportation and maintenance, and finally executes the command for the target devices. Thus, such pneumatic microprocessors will function as a universal on-chip control platform to perform complex parallel operations for large-scale integrated microfluidic devices. To demonstrate the working principles, we have built 2-bit, 3-bit, 4-bit, and 8-bit microprecessors to control various target devices for applications such as four color dye mixing, and multiplexed channel fluidic control. By significantly reducing the need for external controllers, the digital pneumatic microprocessor can be used as a universal on-chip platform to autonomously manipulate microfluids in a high throughput manner. PMID:19823730

Report on phase 1 of the Microprocessor Seminar. [and associated large scale integration

NASA Technical Reports Server (NTRS)

1977-01-01

Proceedings of a seminar on microprocessors and associated large scale integrated (LSI) circuits are presented. The potential for commonality of device requirements, candidate processes and mechanisms for qualifying candidate LSI technologies for high reliability applications, and specifications for testing and testability were among the topics discussed. Various programs and tentative plans of the participating organizations in the development of high reliability LSI circuits are given.

Simplified microprocessor design for VLSI control applications

NASA Technical Reports Server (NTRS)

Cameron, K.

1991-01-01

A design technique for microprocessors combining the simplicity of reduced instruction set computers (RISC's) with the richer instruction sets of complex instruction set computers (CISC's) is presented. They utilize the pipelined instruction decode and datapaths common to RISC's. Instruction invariant data processing sequences which transparently support complex addressing modes permit the formulation of simple control circuitry. Compact implementations are possible since neither complicated controllers nor large register sets are required.

Evolution of a standard microprocessor-based space computer

NASA Technical Reports Server (NTRS)

Fernandez, M.

1980-01-01

An existing in inventory computer hardware/software package (B-1 RFS/ECM) was repackaged and applied to multiple missile/space programs. Concurrent with the application efforts, low risk modifications were made to the computer from program to program to take advantage of newer, advanced technology and to meet increasingly more demanding requirements (computational and memory capabilities, longer life, and fault tolerant autonomy). It is concluded that microprocessors hold promise in a number of critical areas for future space computer applications. However, the benefits of the DoD VHSIC Program are required and the old proliferation problem must be revised.

Microprocessor Recruitment to Elongating RNA Polymerase II Is Required for Differential Expression of MicroRNAs.

PubMed

Church, Victoria A; Pressman, Sigal; Isaji, Mamiko; Truscott, Mary; Cizmecioglu, Nihal Terzi; Buratowski, Stephen; Frolov, Maxim V; Carthew, Richard W

2017-09-26

The cellular abundance of mature microRNAs (miRNAs) is dictated by the efficiency of nuclear processing of primary miRNA transcripts (pri-miRNAs) into pre-miRNA intermediates. The Microprocessor complex of Drosha and DGCR8 carries this out, but it has been unclear what controls Microprocessor's differential processing of various pri-miRNAs. Here, we show that Drosophila DGCR8 (Pasha) directly associates with the C-terminal domain of the RNA polymerase II elongation complex when it is phosphorylated by the Cdk9 kinase (pTEFb). When association is blocked by loss of Cdk9 activity, a global change in pri-miRNA processing is detected. Processing of pri-miRNAs with a UGU sequence motif in their apical junction domain increases, while processing of pri-miRNAs lacking this motif decreases. Therefore, phosphorylation of RNA polymerase II recruits Microprocessor for co-transcriptional processing of non-UGU pri-miRNAs that would otherwise be poorly processed. In contrast, UGU-positive pri-miRNAs are robustly processed by Microprocessor independent of RNA polymerase association. Copyright © 2017 The Author(s). Published by Elsevier Inc. All rights reserved.

Designs and performance of three new microprocessor-controlled knee joints.

PubMed

Thiele, Julius; Schöllig, Christina; Bellmann, Malte; Kraft, Marc

2018-02-09

A crossover design study with a small group of subjects was used to evaluate the performance of three microprocessor-controlled exoprosthetic knee joints (MPKs): C-Leg 4, Plié 3 and Rheo Knee 3. Given that the mechanical designs and control algorithms of the joints determine the user outcome, the influence of these inherent differences on the functional characteristics was investigated in this study. The knee joints were evaluated during level-ground walking at different velocities in a motion analysis laboratory. Additionally, technical analyses using patents, technical documentations and X-ray computed tomography (CT) for each knee joint were performed. The technical analyses showed that only C-Leg 4 and Rheo Knee 3 allow microprocessor-controlled adaptation of the joint resistances for different gait velocities. Furthermore, Plié 3 is not able to provide stance extension damping. The biomechanical results showed that only if a knee joint adapts flexion and extension resistances by the microprocessor all known advantages of MPKs can become apparent. But not all users may benefit from the examined functions: e.g. a good accommodation to fast walking speeds or comfortable stance phase flexion. Hence, a detailed comparison of user demands and performance of the designated knee joint is mandatory to ensure a maximum in user outcome.

Microprocessor-controlled Nd:YAG laser for hyperthermia induction in the RIF-1 tumor.

PubMed

Waldow, S M; Russell, G E; Wallner, P E

1992-01-01

Near-infrared radiation from a Nd:YAG laser at 1,064 nm was used interstitially or superficially to induce hyperthermia in RIF-1 tumors in C3H male mice. A single 600-microns quartz fiber with a 0.5-cm cylindrical diffusor or a weakly diverging microlens at its distal end was used to deliver laser energy to tumors in the hind leg (mean volume = 100 mm3). Two thermocouples were inserted into each tumor. One thermocouple controlled a microprocessor-driven hyperthermia program (maximum output of 3.5 Watts) to maintain the desired temperature. Tumors were exposed to various temperature-time combinations (42-45 degrees C/30 min). Our initial results indicated that excellent temperature control to within 0.2 degrees C of the desired temperature at the feedback thermocouple was achievable during both superficial and interstitial heat treatments. Temperatures at the second thermocouple, however, were found to be lower by as much as 2.3 degrees C (using the cylindrical diffusor) or higher by up to 4.6 degrees C (using the microlens) when compared to the feedback thermocouple temperature. Several correlations were seen between total dose, tumor growth delay, percent skin necrosis, and temperature at the second thermocouple after several superficial and interstitial treatments. Statistically significant improvements in tumor growth delay (at 42 and 45 degrees C) and increased percent skin necrosis at all temperatures were observed after superficial versus interstitial treatment.

Personal Computers.

ERIC Educational Resources Information Center

Toong, Hoo-min D.; Gupta, Amar

1982-01-01

Describes the hardware, software, applications, and current proliferation of personal computers (microcomputers). Includes discussions of microprocessors, memory, output (including printers), application programs, the microcomputer industry, and major microcomputer manufacturers (Apple, Radio Shack, Commodore, and IBM). (JN)

A microprocessor-based multichannel subsensory stochastic resonance electrical stimulator.

PubMed

Chang, Gwo-Ching

2013-01-01

Stochastic resonance electrical stimulation is a novel intervention which provides potential benefits for improving postural control ability in the elderly, those with diabetic neuropathy, and stroke patients. In this paper, a microprocessor-based subsensory white noise electrical stimulator for the applications of stochastic resonance stimulation is developed. The proposed stimulator provides four independent programmable stimulation channels with constant-current output, possesses linear voltage-to-current relationship, and has two types of stimulation modes, pulse amplitude and width modulation.

Proceedings of the Technical Forum (3rd) on the F-16 MIL-STD-1750A Microprocessor and the F-16 MIL-STD-1589B Compiler Held at Wright-Patterson AFB, OH on May 5-6, 1982. Volume 2. Specifications,

DTIC Science & Technology

1982-05-06

access 99 6.3.2 Input/output interrupt code 99 register (IOIC) 6.3.2.1 Read input/output interrupt 100 code, level 1 (OAOOOH) 6.3.2.2 Read input...output interrupt 100 code, level 2 (OA001H) 6.3.3 Console input/output 100 6.3.3.1 Clear console (4001H) 100 6.3.3.2 Console output (4000H) 100 6.3.3.3...Console input (COOOH) 100 6.3.3.4 Read console status (C0O01H) 100 6.3.4 Memory fault status register (MFSR) 100 6.3.4.1 Read memory fault register

Variable frequency microprocessor clock generator

DOE Office of Scientific and Technical Information (OSTI.GOV)

Branson, C.N.

A microprocessor-based system is described comprising: a digital central microprocessor provided with a clock input and having a rate of operation determined by the frequency of a clock signal input thereto; memory means operably coupled to the central microprocessor for storing programs respectively including a plurality of instructions and addressable by the central microprocessor; peripheral device operably connected to the central microprocessor, the first peripheral device being addressable by the central microprocessor for control thereby; a system clock generator for generating a digital reference clock signal having a reference frequency rate; and frequency rate reduction circuit means connected between themore » clock generator and the clock input of the central microprocessor for selectively dividing the reference clock signal to generate a microprocessor clock signal as an input to the central microprocessor for clocking the central microprocessor.« less

Concept for a power system controller for large space electrical power systems

NASA Technical Reports Server (NTRS)

Lollar, L. F.; Lanier, J. R., Jr.; Graves, J. R.

1981-01-01

The development of technology for a fail-operatonal power system controller (PSC) utilizing microprocessor technology for managing the distribution and power processor subsystems of a large multi-kW space electrical power system is discussed. The specific functions which must be performed by the PSC, the best microprocessor available to do the job, and the feasibility, cost savings, and applications of a PSC were determined. A limited function breadboard version of a PSC was developed to demonstrate the concept and potential cost savings.

Self-Checking Pairs Of Microprocessors

NASA Technical Reports Server (NTRS)

Smith, Brian S.

1995-01-01

Method of imparting fault tolerance to computer system provides for immediate detection of faults at microprocessor level. Shadow microprocessor provides nominal duplicate outputs to verify functioning of main microprocessor. When output signal on any pin of one microprocessor differs from that on corresponding pin of other microprocessor, comparator puts out alarm signal.

Commercial CMOS image sensors as X-ray imagers and particle beam monitors

NASA Astrophysics Data System (ADS)

Castoldi, A.; Guazzoni, C.; Maffessanti, S.; Montemurro, G. V.; Carraresi, L.

2015-01-01

CMOS image sensors are widely used in several applications such as mobile handsets webcams and digital cameras among others. Furthermore they are available across a wide range of resolutions with excellent spectral and chromatic responses. In order to fulfill the need of cheap systems as beam monitors and high resolution image sensors for scientific applications we exploited the possibility of using commercial CMOS image sensors as X-rays and proton detectors. Two different sensors have been mounted and tested. An Aptina MT9v034, featuring 752 × 480 pixels, 6μm × 6μm pixel size has been mounted and successfully tested as bi-dimensional beam profile monitor, able to take pictures of the incoming proton bunches at the DeFEL beamline (1-6 MeV pulsed proton beam) of the LaBeC of INFN in Florence. The naked sensor is able to successfully detect the interactions of the single protons. The sensor point-spread-function (PSF) has been qualified with 1MeV protons and is equal to one pixel (6 mm) r.m.s. in both directions. A second sensor MT9M032, featuring 1472 × 1096 pixels, 2.2 × 2.2 μm pixel size has been mounted on a dedicated board as high-resolution imager to be used in X-ray imaging experiments with table-top generators. In order to ease and simplify the data transfer and the image acquisition the system is controlled by a dedicated micro-processor board (DM3730 1GHz SoC ARM Cortex-A8) on which a modified LINUX kernel has been implemented. The paper presents the architecture of the sensor systems and the results of the experimental measurements.

Implementation of Segment Management for a Secure Archival Storage System.

DTIC Science & Technology

1980-09-01

microprocessor operating systems from which the subset, SASS, was later derived (6]. In their work, two of the primary motivations were to provide a system...facility provided by segmentation. The ju~stification Is based on a design decision motivated by another goal of SASS -- reduction of bus contention among...1- I ’ E-4 P4 2-4 E-:t 1 P- W E-E-4&r,3- ’-4 :/I 64 t Ln i.. E-.’f2) V) : / x W~ E.4 E- $=I~ P4 X * U C - ~-4 :Pz=r- -C4 PS4 &2- I-.4 14~ PC: co E E

System for simultaneously loading program to master computer memory devices and corresponding slave computer memory devices

NASA Technical Reports Server (NTRS)

Hall, William A. (Inventor)

1993-01-01

A bus programmable slave module card for use in a computer control system is disclosed which comprises a master computer and one or more slave computer modules interfacing by means of a bus. Each slave module includes its own microprocessor, memory, and control program for acting as a single loop controller. The slave card includes a plurality of memory means (S1, S2...) corresponding to a like plurality of memory devices (C1, C2...) in the master computer, for each slave memory means its own communication lines connectable through the bus with memory communication lines of an associated memory device in the master computer, and a one-way electronic door which is switchable to either a closed condition or a one-way open condition. With the door closed, communication lines between master computer memory (C1, C2...) and slave memory (S1, S2...) are blocked. In the one-way open condition invention, the memory communication lines or each slave memory means (S1, S2...) connect with the memory communication lines of its associated memory device (C1, C2...) in the master computer, and the memory devices (C1, C2...) of the master computer and slave card are electrically parallel such that information seen by the master's memory is also seen by the slave's memory. The slave card is also connectable to a switch for electronically removing the slave microprocessor from the system. With the master computer and the slave card in programming mode relationship, and the slave microprocessor electronically removed from the system, loading a program in the memory devices (C1, C2...) of the master accomplishes a parallel loading into the memory devices (S1, S2...) of the slave.

A methodology based on reduced complexity algorithm for system applications using microprocessors

NASA Technical Reports Server (NTRS)

Yan, T. Y.; Yao, K.

1988-01-01

The paper considers a methodology on the analysis and design of a minimum mean-square error criterion linear system incorporating a tapped delay line (TDL) where all the full-precision multiplications in the TDL are constrained to be powers of two. A linear equalizer based on the dispersive and additive noise channel is presented. This microprocessor implementation with optimized power of two TDL coefficients achieves a system performance comparable to the optimum linear equalization with full-precision multiplications for an input data rate of 300 baud.

Microprocessor implementation of an FFT for ionospheric VLF observations

NASA Technical Reports Server (NTRS)

Elvidge, J.; Kintner, P.; Holzworth, R.

1984-01-01

A fast Fourier transform algorithm is implemented on a CMOS microprocessor for application to very low-frequency electric fields (less than 10 kHz) sensed on high-altitude scientific balloons. Two FFT's are calculated simultaneously by associating them with conjugate symmetric and conjugate antisymmetric results. One goal of the system was to detect spectral signatures associated with fast time variations present in natural signals such as whistlers and chorus. Although a full evaluation of the system was not possible for operational reasons, a measure of the system's success has been defined and evaluated.

Proceedings of the Annual Precise Time and Time Interval (PTTI) Applications and Planning Meeting (22nd) Held in Vienna, Virginia on 4-6 Dec 1990

DTIC Science & Technology

1991-05-01

the problem of the frequency drift is still open. In- this context, the cavity pulling has drawn a lot of attention. Today, to our knowledge, 4...term maser frequency drift associated with the cavity pulling is a well known subject due to the high level of -precision obtainable in principle by...microprocessors. The frequency pulling due to microwave AM = =1:transitions (Ramsey pulling ) has been analyzed and shown to be important. Status of

EFFECTS OF THE GENIUM MICROPROCESSOR KNEE SYSTEM ON KNEE MOMENT SYMMETRY DURING HILL WALKING.

PubMed

Highsmith, M Jason; Klenow, Tyler D; Kahle, Jason T; Wernke, Matthew M; Carey, Stephanie L; Miro, Rebecca M; Lura, Derek J

2016-09-01

Use of the Genium microprocessor knee (MPK) system reportedly improves knee kinematics during walking and other functional tasks compared to other MPK systems. This improved kinematic pattern was observed when walking on different hill conditions and at different speeds. Given the improved kinematics associated with hill walking while using the Genium, a similar improvement in the symmetry of knee kinetics is also feasible. The purpose of this study was to determine if Genium MPK use would reduce the degree of asymmetry (DoA) of peak stance knee flexion moment compared to the C-Leg MPK in transfemoral amputation (TFA) patients. This study used a randomized experimental crossover of TFA patients using Genium and C-Leg MPKs ( n = 20). Biomechanical gait analysis by 3D motion tracking with floor mounted force plates of TFA patients ambulating at different speeds on 5° ramps was completed. Knee moment DoA was significantly different between MPK conditions in the slow and fast uphill as well as the slow and self-selected downhill conditions. In a sample of high-functioning TFA patients, Genium knee system accommodation and use improved knee moment symmetry in slow speed walking up and down a five degree ramp compared with C-Leg. Additionally, the Genium improved knee moment symmetry when walking downhill at comfortable speed. These results likely have application in other patients who could benefit from more consistent knee function, such as older patients and others who have slower walking speeds.

A survey of the state of the art and focused research in range systems, task 2

NASA Technical Reports Server (NTRS)

Yao, K.

1986-01-01

Many communication, control, and information processing subsystems are modeled by linear systems incorporating tapped delay lines (TDL). Such optimized subsystems result in full precision multiplications in the TDL. In order to reduce complexity and cost in a microprocessor implementation, these multiplications can be replaced by single-shift instructions which are equivalent to powers of two multiplications. Since, in general, the obvious operation of rounding the infinite precision TDL coefficients to the nearest powers of two usually yield quite poor system performance, the optimum powers of two coefficient solution was considered. Detailed explanations on the use of branch-and-bound algorithms for finding the optimum powers of two solutions are given. Specific demonstration of this methodology to the design of a linear data equalizer and its implementation in assembly language on a 8080 microprocessor with a 12 bit A/D converter are reported. This simple microprocessor implementation with optimized TDL coefficients achieves a system performance comparable to the optimum linear equalization with full precision multiplications for an input data rate of 300 baud. The philosophy demonstrated in this implementation is dully applicable to many other microprocessor controlled information processing systems.

Advanced information processing system for advanced launch system: Hardware technology survey and projections

NASA Technical Reports Server (NTRS)

Cole, Richard

1991-01-01

The major goals of this effort are as follows: (1) to examine technology insertion options to optimize Advanced Information Processing System (AIPS) performance in the Advanced Launch System (ALS) environment; (2) to examine the AIPS concepts to ensure that valuable new technologies are not excluded from the AIPS/ALS implementations; (3) to examine advanced microprocessors applicable to AIPS/ALS, (4) to examine radiation hardening technologies applicable to AIPS/ALS; (5) to reach conclusions on AIPS hardware building blocks implementation technologies; and (6) reach conclusions on appropriate architectural improvements. The hardware building blocks are the Fault-Tolerant Processor, the Input/Output Sequencers (IOS), and the Intercomputer Interface Sequencers (ICIS).

Noiseless coding for the magnetometer

NASA Technical Reports Server (NTRS)

Rice, Robert F.; Lee, Jun-Ji

1987-01-01

Future unmanned space missions will continue to seek a full understanding of magnetic fields throughout the solar system. Severely constrained data rates during certain portions of these missions could limit the possible science return. This publication investigates the application of universal noiseless coding techniques to more efficiently represent magnetometer data without any loss in data integrity. Performance results indicated that compression factors of 2:1 to 6:1 can be expected. Feasibility for general deep space application was demonstrated by implementing a microprocessor breadboard coder/decoder using the Intel 8086 processor. The Comet Rendezvous Asteroid Flyby mission will incorporate these techniques in a buffer feedback, rate-controlled configuration. The characteristics of this system are discussed.

Proceedings: DISE Workshop on Microprocessors and Education (Fort Collins, Colorado, August 16-18, 1976).

ERIC Educational Resources Information Center

Pittsburgh Univ., PA. Dept. of Electrical Engineering.

Papers presented during four sessions of a workshop, which addressed the role of microprocessors in education, are included in this publication. The issues covered involved seven areas: (1) views of the microelectronics industry; (2) microprocessor architecture; (3) microprocessor chip design; (4) microprocessor software; (5) the impact of…

Proceedings of the Ship Control Systems Symposium (9th) Held in Bethesda, Maryland on 10-14 September 1990. Theme: Automation in Surface Ship Control Systems, Today’s Applications and Future Trends. Volume 1

DTIC Science & Technology

1990-09-14

transmission of detected variations through sound lines of communication to centrally located standard Navy computers . These computers would be programmed to...have been programmed in C language. The program runs under the operating system ,OS9 on a VME-bus computer with a 68000 microprocessor. A number of full...present practice of"add-on" supervisory controls during ship design and construction,and "fix-it" R&D programs implemented after the ship isoperational

Analysis of the Intel 386 and i486 microprocessors for the Space Station Freedom Data Management System

NASA Technical Reports Server (NTRS)

Liu, Yuan-Kwei

1991-01-01

The feasibility is analyzed of upgrading the Intel 386 microprocessor, which has been proposed as the baseline processor for the Space Station Freedom (SSF) Data Management System (DMS), to the more advanced i486 microprocessors. The items compared between the two processors include the instruction set architecture, power consumption, the MIL-STD-883C Class S (Space) qualification schedule, and performance. The advantages of the i486 over the 386 are (1) lower power consumption; and (2) higher floating point performance. The i486 on-chip cache does not have parity check or error detection and correction circuitry. The i486 with on-chip cache disabled, however, has lower integer performance than the 386 without cache, which is the current DMS design choice. Adding cache to the 386/386 DX memory hierachy appears to be the most beneficial change to the current DMS design at this time.

Analysis of the Intel 386 and i486 microprocessors for the Space Station Freedom Data Management System

NASA Technical Reports Server (NTRS)

Liu, Yuan-Kwei

1991-01-01

The feasibility is analyzed of upgrading the Intel 386 microprocessor, which has been proposed as the baseline processor for the Space Station Freedom (SSF) Data Management System (DMS), to the more advanced i486 microprocessors. The items compared between the two processors include the instruction set architecture, power consumption, the MIL-STD-883C Class S (Space) qualification schedule, and performance. The advantages of the i486 over the 386 are (1) lower power consumption; and (2) higher floating point performance. The i486 on-chip cache does not have parity check or error detection and correction circuitry. The i486 with on-chip cache disabled, however, has lower integer performance than the 386 without cache, which is the current DMS design choice. Adding cache to the 386/387 DX memory hierarchy appears to be the most beneficial change to the current DMS design at this time.

Synchronous clock stopper for microprocessor

NASA Technical Reports Server (NTRS)

Kitchin, David A. (Inventor)

1985-01-01

A synchronous clock stopper circuit for inhibiting clock pulses to a microprocessor in response to a stop request signal, and for reinstating the clock pulses in response to a start request signal thereby to conserve power consumption of the microprocessor when used in an environment of limited power. The stopping and starting of the microprocessor is synchronized, by a phase tracker, with the occurrences of a predetermined phase in the instruction cycle of the microprocessor in which the I/O data and address lines of the microprocessor are of high impedance so that a shared memory connected to the I/O lines may be accessed by other peripheral devices. The starting and stopping occur when the microprocessor initiates and completes, respectively, an instruction, as well as before and after transferring data with a memory. Also, the phase tracker transmits phase information signals over a bus to other peripheral devices which signals identify the current operational phase of the microprocessor.

Cumulative Timers for Microprocessors

NASA Technical Reports Server (NTRS)

Battle, John O.

2007-01-01

It has been proposed to equip future microprocessors with electronic cumulative timers, for essentially the same reasons for which land vehicles are equipped with odometers (total-distance-traveled meters) and aircraft are equipped with Hobbs meters (total-engine-operating time meters). Heretofore, there has been no way to determine the amount of use to which a microprocessor (or a product containing a microprocessor) has been subjected. The proposed timers would count all microprocessor clock cycles and could only be read by means of microprocessor instructions but, like odometers and Hobbs meters, could never be reset to zero without physically damaging the chip.

Feasibility study of microprocessor systems suitable for use in developing a real-time for the 4.75 GHz scatterometer

NASA Technical Reports Server (NTRS)

1977-01-01

A class of signal processors suitable for the reduction of radar scatterometer data in real time was developed. The systems were applied to the reduction of single polarized 13.3 GHz scatterometer data and provided a real time output of radar scattering coefficient as a function of incident angle. It was proposed that a system for processing of C band radar data be constructed to support scatterometer system currently under development. The establishment of a feasible design approach to the development of this processor system utilizing microprocessor technology was emphasized.

Stand-alone development system using a KIM-1 microcomputer module

NASA Technical Reports Server (NTRS)

Nickum, J. D.

1978-01-01

A small microprocessor-based system designed to: contain all or most of the interface hardware, designed to be easy to access and modify the hardware, to be capable of being strapped to the seat of a small general aviation aircraft, and to be independent of the aircraft power system is described. The system is used to develop a low cost Loran C sensor processor, but is designed such that the Loran interface boards may be removed and other hardware interfaces inserted into the same connectors. This flexibility is achieved through memory-mapping techniques into the microprocessor.

Comparison between the C-leg microprocessor-controlled prosthetic knee and non-microprocessor control prosthetic knees: a preliminary study of energy expenditure, obstacle course performance, and quality of life survey.

PubMed

Seymour, Ron; Engbretson, Brenda; Kott, Karen; Ordway, Nathaniel; Brooks, Gary; Crannell, Jessica; Hickernell, Elise; Wheeler, Katie

2007-03-01

This study investigated energy expenditure and obstacle course negotiation between the C-leg and various non-microprocessor control (NMC) prosthetic knees and compared a quality of life survey (SF-36v2) of use of the C-leg to national norms. Thirteen subjects with unilateral limb loss (12 with trans-femoral and one with a knee disarticulation amputation) participated in the study. The mean age was 46 years, range 30-75. Energy expenditure using both the NMC and C-leg prostheses was measured at self-selected typical and fast walking paces on a motorized treadmill. Subjects were also asked to walk through a standardized walking obstacle course carrying a 4.5 kg (10 lb) basket and with hands free. Finally, the SF-36v2 was completed for subjects while using the C-leg. Statistically significant differences were found in oxygen consumption between prostheses at both typical and fast paces with the C-leg showing decreased values. Use of the C-leg resulted in a statistically significant decrease in the number of steps and time to complete the obstacle course. Scores on a quality of life index for subjects using the C-leg were above the mean for norms for limitation in the use of an arm or leg, equal to the mean for the general United States population for the physical component score and were above this mean for the mental component score. Based on oxygen consumption and obstacle course findings, the C-leg when compared to the NMC prostheses may provide increased functional mobility and ease of performance in the home and community environment. Questionnaire results suggest a minimal quality of life impairment when using a C-leg for this cohort of individuals with amputation.

An Innovative Method of Teaching Electronic System Design with PSoC

ERIC Educational Resources Information Center

Ye, Zhaohui; Hua, Chengying

2012-01-01

Programmable system-on-chip (PSoC), which provides a microprocessor and programmable analog and digital peripheral functions in a single chip, is very convenient for mixed-signal electronic system design. This paper presents the experience of teaching contemporary mixed-signal electronic system design with PSoC in the Department of Automation,…

Microprocessors: Laboratory Simulation of Industrial Control Applications.

ERIC Educational Resources Information Center

Gedeon, David V.

1981-01-01

Describes a course to make technical managers more aware of computer technology and how data loggers, programmable controllers, and larger computer systems interact in a hierarchical configuration of manufacturing process control. (SK)

A case study for the real-time experimental evaluation of the VIPER microprocessor

NASA Astrophysics Data System (ADS)

Carreno, Victor A.; Angellatta, Rob K.

1991-09-01

An experiment to evaluate the applicability of the Verifiable Integrated Processor for Enhanced Reliability (VIPER) microprocessor to real time control is described. The VIPER microprocessor was invented by the Royal Signals and Radar Establishment (RSRE), U.K., and is an example of the use of formal mathematical methods for developing electronic digital systems with a high degree of assurance on the system design and implementation correctness. The experiment consisted of selecting a control law, writing the control law algorithm for the VIPER processor, and providing real time, dynamic inputs into the processor and monitoring the outputs. The control law selected and coded for the VIPER processor was the yaw damper function of an automatic landing program for a 737 aircraft. The mechanisms for interfacing the VIPER Single Board Computer to the VAX host are described. Results include run time experiences, performance evaluation, and comparison of VIPER and FORTRAN yaw damper algorithm output for accuracy estimation.

A case study for the real-time experimental evaluation of the VIPER microprocessor

NASA Technical Reports Server (NTRS)

Carreno, Victor A.; Angellatta, Rob K.

1991-01-01

An experiment to evaluate the applicability of the Verifiable Integrated Processor for Enhanced Reliability (VIPER) microprocessor to real time control is described. The VIPER microprocessor was invented by the Royal Signals and Radar Establishment (RSRE), U.K., and is an example of the use of formal mathematical methods for developing electronic digital systems with a high degree of assurance on the system design and implementation correctness. The experiment consisted of selecting a control law, writing the control law algorithm for the VIPER processor, and providing real time, dynamic inputs into the processor and monitoring the outputs. The control law selected and coded for the VIPER processor was the yaw damper function of an automatic landing program for a 737 aircraft. The mechanisms for interfacing the VIPER Single Board Computer to the VAX host are described. Results include run time experiences, performance evaluation, and comparison of VIPER and FORTRAN yaw damper algorithm output for accuracy estimation.

A Performance Evaluation of the Cray X1 for Scientific Applications

NASA Technical Reports Server (NTRS)

Oliker, Leonid; Biswas, Rupak; Borrill, Julian; Canning, Andrew; Carter, Jonathan; Djomehri, M. Jahed; Shan, Hongzhang; Skinner, David

2004-01-01

The last decade has witnessed a rapid proliferation of superscalar cache-based microprocessors to build high-end capability and cost effectiveness. However, the recent development of massively parallel vector systems is having a significant effect on the supercomputing landscape. In this paper, we compare the performance of the recently released Cray X1 vector system with that of the cacheless NEC SX-6 vector machine, and the superscalar cache-based IBM Power3 and Power4 architectures for scientific applications. Overall results demonstrate that the X1 is quite promising, but performance improvements are expected as the hardware, systems software, and numerical libraries mature. Code reengineering to effectively utilize the complex architecture may also lead to significant efficiency enhancements.

Microprocessor utilization in search and rescue missions

NASA Technical Reports Server (NTRS)

Schwartz, M.

1977-01-01

The feasibility of performing the same task in real time using microprocessor technology was determined. The least square algorithm was implemented on an Intel 8080 microprocessor. Results indicated that a microprocessor could easily match the IBM implementation in accuracy and be performed inside the time limitations set.

Microprocessors in U.S. Electrical Engineering Departments, 1974-1975.

ERIC Educational Resources Information Center

Sloan, M. E.

Drawn from a survey of engineering departments known to be teaching microprocessor courses, this paper shows that the adoption of microprocessors by Electrical Engineering Departments has been rapid compared with their adoption of minicomputers. The types of courses that are being taught can be categorized as: surveys of microprocessors, intensive…

76 FR 39895 - In the Matter of Certain Microprocessors, Components Thereof, and Products Containing Same...

Federal Register 2010, 2011, 2012, 2013, 2014

2011-07-07

... INTERNATIONAL TRADE COMMISSION [Inv. No. 337-TA-781] In the Matter of Certain Microprocessors... importation of certain microprocessors, components thereof, and products containing same by reason of... microprocessors, components thereof, and products containing same that infringe one or more of claims 11-16, 41...

Debris measure subsystem of the nanosatellite IRECIN

NASA Astrophysics Data System (ADS)

Ferrante, M.; di Ciolo, L.; Ortenzi, A.; Petrozzi, M.; del Re, V.

2003-09-01

The on board resources, needed to perform the mission tasks, are very limited in nano-satellites. This paper proposes an Electronic real-time system that acquires space debris measures. It uses a piezo-electric sensor. The described device is a subsystem on board of the IRECIN nanosatellite composed mainly by a r.i.s.c. microprocessor, an electronic part that interfaces to the debris sensor in order to provide a low noise electrical and suitable range to ADC 12 bit converter, and finally a memory in order to store the data. The microprocessor handles the Debris Measure System measuring the impacts number, their intensity and storing their waves form. This subsystem is able to communicate with the other IRECIN subsystems through I2C Bus and principally with the "Main Microprocessor" subsystem allowing the data download directly to the Ground Station. Moreover this subsystem lets free the "Main Microprocessor Board" from the management and charge of debris data. All electronic components are SMD technology in order to reduce weight and size. The realized Electronic board are completely developed, realized and tested at the Vitrociset S.P.A. under control of Research and Development Group. The proposed system is implemented on the IRECIN, a modular nanosatellite weighting less than 1.5 kg, constituted by sixteen external sides with surface-mounted solar cells and three internal Al plates, kept together by four steel bars. Lithium-ions batteries are added for eclipse operations. Attitude is determined by two three-axis magnetometers and the solar panels data. Control is provided by an active magnetic control system. The spacecraft will be spin-stabilized with the spin-axis normal to the orbit. debris and micrometeoroids mass and velocity.

The Large Angle Spectroscopic Coronagraph (LASCO): Visible light coronal imaging and spectroscopy

NASA Technical Reports Server (NTRS)

Brueckner, Guenter E.; Howard, Russell A.; Koomen, Martin J.; Korendyke, C.; Michels, D. J.; Socker, D. G.; Lamy, Philippe; Llebaria, Antoine; Maucherat, J.; Schwenn, Rainer

1992-01-01

The Large Angle Spectroscopic Coronagraph (LASCO) is a triple coronagraph being jointly developed for the Solar and Heliospheric Observatory (SOHO) mission. LASCO comprises three nested coronagraphs (C1, C2, and C3) that image the solar corona for 1.1 to 30 solar radii (C1: 1.1 to 3 solar radii, C2: 1.5 to 6 solar radii, and C3: 3 to 30.0 solar radii). The inner coronagraph (C1) is a newly developed mirror version of the classic Lyot coronagraph without an external occultor, while the middle coronagraph (C2) and the outer coronagraph (C3) are externally occulted instruments. High resolution coronal spectroscopy from 1.1 to 3 R solar radii can be performed by using a Fabry-Perot interferometer, which is part of C1. High volume memories and a high speed microprocessor enable extensive onboard image processing. Image compression by factors of 10 to 20 will result in the transmission of 10 to 20 full images per hour.

A thin-film microprocessor with inkjet print-programmable memory

NASA Astrophysics Data System (ADS)

Myny, Kris; Smout, Steve; Rockelé, Maarten; Bhoolokam, Ajay; Ke, Tung Huei; Steudel, Soeren; Cobb, Brian; Gulati, Aashini; Rodriguez, Francisco Gonzalez; Obata, Koji; Marinkovic, Marko; Pham, Duy-Vu; Hoppe, Arne; Gelinck, Gerwin H.; Genoe, Jan; Dehaene, Wim; Heremans, Paul

2014-12-01

The Internet of Things is driving extensive efforts to develop intelligent everyday objects. This requires seamless integration of relatively simple electronics, for example through `stick-on' electronics labels. We believe the future evolution of this technology will be governed by Wright's Law, which was first proposed in 1936 and states that the cost of a product decreases with cumulative production. This implies that a generic electronic device that can be tailored for application-specific requirements during downstream integration would be a cornerstone in the development of the Internet of Things. We present an 8-bit thin-film microprocessor with a write-once, read-many (WORM) instruction generator that can be programmed after manufacture via inkjet printing. The processor combines organic p-type and soluble oxide n-type thin-film transistors in a new flavor of the familiar complementary transistor technology with the potential to be manufactured on a very thin polyimide film, enabling low-cost flexible electronics. It operates at 6.5 V and reaches clock frequencies up to 2.1 kHz. An instruction set of 16 code lines, each line providing a 9 bit instruction, is defined by means of inkjet printing of conductive silver inks.

Development of a microprocessor controller for stand-alone photovoltaic power systems

NASA Technical Reports Server (NTRS)

Millner, A. R.; Kaufman, D. L.

1984-01-01

A controller for stand-alone photovoltaic systems has been developed using a low power CMOS microprocessor. It performs battery state of charge estimation, array control, load management, instrumentation, automatic testing, and communications functions. Array control options are sequential subarray switching and maximum power control. A calculator keypad and LCD display provides manual control, fault diagnosis and digital multimeter functions. An RS-232 port provides data logging or remote control capability. A prototype 5 kW unit has been built and tested successfully. The controller is expected to be useful in village photovoltaic power systems, large solar water pumping installations, and other battery management applications.

LLL 8080 BASIC-II interpreter user's manual

DOE Office of Scientific and Technical Information (OSTI.GOV)

McGoldrick, P.R.; Dickinson, J.; Allison, T.G.

1978-04-03

Scientists are finding increased applications for microprocessors as process controllers in their experiments. However, while microprocessors are small and inexpensive, they are difficult to program in machine or assembly language. A high-level language is needed to enable scientists to develop their own microcomputer programs for their experiments on location. Recognizing this need, LLL contracted to have such a language developed. This report describes the resulting LLL BASIC interpreter, which opeates with LLL's 8080-based MCS-8 microcomputer system. All numerical operations are done using Advanced Micro Device's Am9511 arithmetic processor chip or optionally by using a software simulation of that chip. 1more » figure.« less

The biological microprocessor, or how to build a computer with biological parts

PubMed Central

Moe-Behrens, Gerd HG

2013-01-01

Systemics, a revolutionary paradigm shift in scientific thinking, with applications in systems biology, and synthetic biology, have led to the idea of using silicon computers and their engineering principles as a blueprint for the engineering of a similar machine made from biological parts. Here we describe these building blocks and how they can be assembled to a general purpose computer system, a biological microprocessor. Such a system consists of biological parts building an input / output device, an arithmetic logic unit, a control unit, memory, and wires (busses) to interconnect these components. A biocomputer can be used to monitor and control a biological system. PMID:24688733

Fast computational scheme of image compression for 32-bit microprocessors

NASA Technical Reports Server (NTRS)

Kasperovich, Leonid

1994-01-01

This paper presents a new computational scheme of image compression based on the discrete cosine transform (DCT), underlying JPEG and MPEG International Standards. The algorithm for the 2-d DCT computation uses integer operations (register shifts and additions / subtractions only); its computational complexity is about 8 additions per image pixel. As a meaningful example of an on-board image compression application we consider the software implementation of the algorithm for the Mars Rover (Marsokhod, in Russian) imaging system being developed as a part of Mars-96 International Space Project. It's shown that fast software solution for 32-bit microprocessors may compete with the DCT-based image compression hardware.

Differences in knee flexion between the Genium and C-Leg microprocessor knees while walking on level ground and ramps.

PubMed

Lura, Derek J; Wernke, Matthew M; Carey, Stephanie L; Kahle, Jason T; Miro, Rebecca M; Highsmith, M Jason

2015-02-01

Microprocessor knees have improved the gait and functional abilities of persons with transfemoral amputation. The Genium prosthetic knee offers an advanced sensor and control system designed to decrease impairment by: allowing greater stance phase flexion, easing transitions between gait phases, and compensating for changes in terrain. The aim of this study was to determine differences between the knee flexion angle of persons using the Genium knee, the C-Leg knee, and non-amputee controls; and to evaluate the impact the prostheses on gait and level of impairment of the user. This study used a randomized experimental crossover of persons with transfemoral amputation using the Genium and C-Leg microprocessor knees (n=25), with an observational sample of non-amputee controls (n=5). Gait analysis by 3D motion tracking of subjects ambulating at different speeds on level ground and on 5° and 10° ramps was completed. Use of the Genium resulted in a significant increase in peak knee flexion for swing (5°, p<0.01, d=0.34) and stance (2°, p<0.01, d=0.19) phases relative to C-Leg use. There was a high degree of variability between subjects, and significant differences still remain between the Genium group and the control group's knee flexion angles for most speeds and slopes. The Genium knee generally increases flexion in swing and stance, potentially decreasing the level of impairment for persons with transfemoral amputation. This study demonstrates functional differences between the C-Leg and Genium knees to help prosthetists determine if the Genium will provide functional benefits to individual patients. Copyright © 2014 Elsevier Ltd. All rights reserved.

Autoregulatory mechanisms controlling the Microprocessor.

PubMed

Triboulet, Robinson; Gregory, Richard I

2010-01-01

The Microprocessor, comprising the ribonuclease Drosha and its essential cofactor, the double-stranded RNA-binding protein, DGCR8, is essential for the first step of the miRNA biogenesis pathway. It specifically cleaves double-stranded RNA within stem-loop structures of primary miRNA transcripts (pri-miRNAs) to generate precursor (pre-miRNA) intermediates. Pre-miRNAs are subsequently processed by Dicer to their mature 22 nt form. Thus, Microprocessor is essential for miRNA maturation, and pri-miRNA cleavage by this complex defines one end of the mature miRNA. Moreover, it is emerging that dysregulation of the Microprocessor is associated with various human diseases. It is therefore important to understand the mechanisms by which the expression of the subunits of the Microprocessor is regulated. Recent findings have uncovered a post-transcriptional mechanism that maintains the integrity of the Microprocessor. These studies revealed that the Microprocessor is involved in the processing of the messenger RNA (mRNA) that encodes DGCR8. This regulatory feedback loop, along with the reported role played by DGCR8 in the stabilization of Drosha protein, is part ofa newly identified regulatory mechanism controlling Microprocessor activity.

Enhancement of a prosthetic knee with a microprocessor-controlled gait phase switch reduces falls and improves balance confidence and gait speed in community ambulators with unilateral transfemoral amputation.

PubMed

Fuenzalida Squella, Sara Agueda; Kannenberg, Andreas; Brandão Benetti, Ângelo

2018-04-01

Despite the evidence for improved safety and function of microprocessor stance and swing-controlled prosthetic knees, non-microprocessor-controlled prosthetic knees are still standard of care for persons with transfemoral amputations in most countries. Limited feature microprocessor-control enhancement of such knees could stand to significantly improve patient outcomes. To evaluate gait speed, balance, and fall reduction benefits of the new 3E80 default stance hydraulic knee compared to standard non-microprocessor-controlled prosthetic knees. Comparative within-subject clinical study. A total of 13 young, high-functioning community ambulators with a transfemoral amputation underwent assessment of performance-based (e.g. 2-min walk test, timed ramp/stair tests) and self-reported (e.g. falls, Activities-Specific Balance Confidence scale, Prosthesis Evaluation Questionnaire question #1, Satisfaction with the Prosthesis) outcome measures for their non-microprocessor-controlled prosthetic knees and again after 8 weeks of accommodation to the 3E80 microprocessor-enhanced knee. Self-reported falls significantly declined 77% ( p = .04), Activities-Specific Balance Confidence scores improved 12 points ( p = .005), 2-min walk test walking distance increased 20 m on level ( p = .01) and uneven ( p = .045) terrain, and patient satisfaction significantly improved ( p < .01) when using the 3E80 knee. Slope and stair ambulation performance did not differ between knee conditions. The 3E80 knee reduced self-reported fall incidents and improved balance confidence. Walking performance on both level and uneven terrains also improved compared to non-microprocessor-controlled prosthetic knees. Subjects' satisfaction was significantly higher than with their previous non-microprocessor-controlled prosthetic knees. The 3E80 may be considered a prosthetic option for improving gait performance, balance confidence, and safety in highly active amputees. Clinical relevance This study compared performance-based and self-reported outcome measures when using non-microprocessor and a new microprocessor-enhanced, default stance rotary hydraulic knee. The results inform rehabilitation professionals about the functional benefits of a limited-feature, microprocessor-enhanced hydraulic prosthetic knee over standard non-microprocessor-controlled prosthetic knees.

Microprocessor-controlled iontophoretic drug delivery of 5-fluorouracil: pharmacodynamic and pharmacokinetic study.

PubMed

Chandrashekar, N S; Shobha Rani, R H

2007-01-01

The purpose of this study was to fabricate monolithic 5-fluorouracil (5-FU) transdermal patch with microprocessor- controlled iontophoretic delivery, to evaluate the pharmacodynamic effects on Dalton's lymphoma ascites (DLA) induced in Balb/c mice, and to study pharmacokinetics in rabbits. The transdermal patches were prepared by solvent casting method; a reprogrammable microprocessor was developed and connected to the patches. DLA cells were injected to the hind limb of Balb/c mice (10 animals/group). In the first group of mice 5-FU was administered i.v. (12 mg/kg). In the second group of mice, transdermal patches (20 mg/patch/animal) were installed and kept for 10 consecutive days, while the third (control) group was kept without any treatment. The tumor diameter was measured every 5th day for 30 days, and the animal survival time and death pattern were studied. The electric current density protocol of 0.5 mA/cm(2) for 30 min was used in the pharmacokinetic study in rabbits. There was a significant reduction in tumor volume in the animals treated with monolithic matrix 5-FU transdermal patch compared to untreated controls and i.v. therapy. Tumor volume of the control animals was 5.8 cm(3) on the 30th day, while in 5-FU with transdermal patch delivery animals it was only 0.23 cm(3) (p <0.05). DLA cells tumor-bearing mice treated with 5-FU with transdermal patch had significantly increased lifespan (ILS). Control animals survived only 21+/-1 days after the tumor inoculation, while i.v. 5-FU and 5-FU patches animals survived 24+/-2.7 days and 39.5+/-1.87 days with ILS of 25.58% and 88.09%, respectively (p <0.01). There was significant sustained release of 5-FU through microprocessor-controlled patches and half-life was significantly higher (p <0.05) compared to the i.v. route. Cytotoxic concentration of 5-FU can be achieved through the transdermal drug delivery and effective therapeutic drug concentration can be maintained up to 24 h, with less toxicity. A new generation of transdermal drug delivery systems based on microprocessor-controlled iontophoresis is in the late stages of development and promises to enhance the treatment of local and systemic medical conditions. The incorporation of microprocessor into these systems has been an important advancement to ensure safe and efficient administration of a wide variety of drugs.

Bus-Programmable Slave Card

NASA Technical Reports Server (NTRS)

Hall, William A.

1990-01-01

Slave microprocessors in multimicroprocessor computing system contains modified circuit cards programmed via bus connecting master processor with slave microprocessors. Enables interactive, microprocessor-based, single-loop control. Confers ability to load and run program from master/slave bus, without need for microprocessor development station. Tristate buffers latch all data and information on status. Slave central processing unit never connected directly to bus.

Accelerating a MPEG-4 video decoder through custom software/hardware co-design

NASA Astrophysics Data System (ADS)

Díaz, Jorge L.; Barreto, Dacil; García, Luz; Marrero, Gustavo; Carballo, Pedro P.; Núñez, Antonio

2007-05-01

In this paper we present a novel methodology to accelerate an MPEG-4 video decoder using software/hardware co-design for wireless DAB/DMB networks. Software support includes the services provided by the embedded kernel μC/OS-II, and the application tasks mapped to software. Hardware support includes several custom co-processors and a communication architecture with bridges to the main system bus and with a dual port SRAM. Synchronization among tasks is achieved at two levels, by a hardware protocol and by kernel level scheduling services. Our reference application is an MPEG-4 video decoder composed of several software functions and written using a special C++ library named CASSE. Profiling and space exploration techniques were used previously over the Advanced Simple Profile (ASP) MPEG-4 decoder to determinate the best HW/SW partition developed here. This research is part of the ARTEMI project and its main goal is the establishment of methodologies for the design of real-time complex digital systems using Programmable Logic Devices with embedded microprocessors as target technology and the design of multimedia systems for broadcasting networks as reference application.

A Fourier transform with speed improvements for microprocessor applications

NASA Technical Reports Server (NTRS)

Lokerson, D. C.; Rochelle, R.

1980-01-01

A fast Fourier transform algorithm for the RCA 1802microprocessor was developed for spacecraft instrument applications. The computations were tailored for the restrictions an eight bit machine imposes. The algorithm incorporates some aspects of Walsh function sequency to improve operational speed. This method uses a register to add a value proportional to the period of the band being processed before each computation is to be considered. If the result overflows into the DF register, the data sample is used in computation; otherwise computation is skipped. This operation is repeated for each of the 64 data samples. This technique is used for both sine and cosine portions of the computation. The processing uses eight bit data, but because of the many computations that can increase the size of the coefficient, floating point form is used. A method to reduce the alias problem in the lower bands is also described.

Microprocessor control of a wind turbine generator

NASA Technical Reports Server (NTRS)

Gnecco, A. J.; Whitehead, G. T.

1978-01-01

A microprocessor based system was used to control the unattended operation of a wind turbine generator. The turbine and its microcomputer system are fully described with special emphasis on the wide variety of tasks performed by the microprocessor for the safe and efficient operation of the turbine. The flexibility, cost and reliability of the microprocessor were major factors in its selection.

Autoregulatory mechanisms controlling the microprocessor.

PubMed

Triboulet, Robinson; Gregory, Richard I

2011-01-01

The Microprocessor, comprising the ribonuclease Drosha and its essential cofactor, the double-stranded RNA-binding protein, DGCR8, is essential for the first step of the miRNA biogenesis pathway. It specifically cleaves double-stranded RNA within stem-loop structures of primary miRNA transcripts (pri-miRNAs) to generate precursor (pre-miRNA) intermediates. Pre-miRNAs are subsequently processed by Dicer to their mature ∼22 nt form. Thus, Microprocessor is essential for miRNA maturation, and pri-miRNA cleavage by this complex defines one end of the mature miRNA. Moreover, it is emerging that dysregulation of the Microprocessor is associated with various human diseases. It is therefore important to understand the mechanisms by which the expression of the subunits of the Microprocessor is regulated. Recent findings have uncovered a post-transcriptional mechanism that maintains the integrity of the Microprocessor. These studies revealed that the Microprocessor is involved in the processing of the messenger RNA (mRNA) that encodes DGCR8. This regulatory feedback loop, along with the reported role played by DGCR8 in the stabilization of Drosha protein, is part of a newly identified regulatory mechanism controlling Microprocessor activity.

VxWorks 6.9 for LEON

NASA Astrophysics Data System (ADS)

Cederman, Daniel; Hellstrom, Daniel

2016-08-01

The VxWorks operating system together with the Cobham Grislier LEON architectural port provides an efficient platform for the development of software for space applications. It supports both uni-and multiprocessor mode (SMP or AMP) and comes with an integrated development environment with several debugging and analysis tools. The LEON architectural port from Cobham Grislier supports LEON2/3/4 systems and includes drivers for all standard on-chip peripherals, as well as support for RASTA boards. In this paper we will highlight some the many features of VxWorks and the LEON architectural port. The latest version of the architectural port now supports VxWorks 6.9 (the previous version was for VxWorks 6.7) and has the support for the GR740, the commercially available quad-core LEON system, designed as the European Space Agency's Next Generation Microprocessor (NGMP).

Post-transcriptional control of DGCR8 expression by the Microprocessor.

PubMed

Triboulet, Robinson; Chang, Hao-Ming; Lapierre, Robert J; Gregory, Richard I

2009-06-01

The Microprocessor, comprising the RNase III Drosha and the double-stranded RNA binding protein DGCR8, is essential for microRNA (miRNA) biogenesis. In the miRNA processing pathway certain hairpin structures within primary miRNA (pri-miRNA) transcripts are specifically cleaved by the Microprocessor to release approximately 60-70-nucleotide precursor miRNA (pre-miRNA) intermediates. Although both Drosha and DGCR8 are required for Microprocessor activity, the mechanisms regulating the expression of these proteins are unknown. Here we report that the Microprocessor negatively regulates DGCR8 expression. Using in vitro reconstitution and in vivo studies, we demonstrate that a hairpin, localized in the 5' untranslated region (5'UTR) of DGCR8 mRNA, is cleaved by the Microprocessor. Accordingly, knockdown of Drosha leads to an increase in DGCR8 mRNA and protein levels in cells. Furthermore, we found that the DGCR8 5'UTR confers Microprocessor-dependent repression of a luciferase reporter gene in vivo. Our results uncover a novel feedback loop that regulates DGCR8 levels.

Microprocessors in Schools?

ERIC Educational Resources Information Center

Cuthbert, L. G.

1981-01-01

Examines reasons for including microprocessors in school curricula. Indicates that practical work with microprocessors is not easy and discusses problems associated with using and constructing these control and processing devices of microcomputers. (SK)

A Performance Evaluation of the Cray X1 for Scientific Applications

NASA Technical Reports Server (NTRS)

Oliker, Leonid; Biswas, Rupak; Borrill, Julian; Canning, Andrew; Carter, Jonathan; Djomehri, M. Jahed; Shan, Hongzhang; Skinner, David

2003-01-01

The last decade has witnessed a rapid proliferation of superscalar cache-based microprocessors to build high-end capability and capacity computers because of their generality, scalability, and cost effectiveness. However, the recent development of massively parallel vector systems is having a significant effect on the supercomputing landscape. In this paper, we compare the performance of the recently-released Cray X1 vector system with that of the cacheless NEC SX-6 vector machine, and the superscalar cache-based IBM Power3 and Power4 architectures for scientific applications. Overall results demonstrate that the X1 is quite promising, but performance improvements are expected as the hardware, systems software, and numerical libraries mature. Code reengineering to effectively utilize the complex architecture may also lead to significant efficiency enhancements.

A Microprocessor Project for Non-Electrical Engineering Students.

ERIC Educational Resources Information Center

Swingler, D. N.

1981-01-01

Offers rationale for and a description of a microprocessor-based control system project for mechanical engineering students. Includes reasons for selecting a Texas Instruments TM990/189 microprocessor system. (SK)

Microprocessor prosthetic knees.

PubMed

Berry, Dale

2006-02-01

This article traces the development of microprocessor prosthetic knees from early research in the 1970s to the present. Read about how microprocessor knees work, functional options, patient selection, and the future of this prosthetic.

15 CFR 744.17 - Restrictions on certain exports and reexports of general purpose microprocessors for “military...

Code of Federal Regulations, 2013 CFR

2013-01-01

... reexports of general purpose microprocessors for âmilitary end-usesâ and to âmilitary end-users.â 744.17... microprocessors for “military end-uses” and to “military end-users.” (a) General prohibition. In addition to the... reexport commodities described in ECCN 3A991.a.1 on the CCL (“microprocessor microcircuits”, “microcomputer...

15 CFR 744.17 - Restrictions on certain exports and reexports of general purpose microprocessors for “military...

Code of Federal Regulations, 2010 CFR

2010-01-01

... reexports of general purpose microprocessors for âmilitary end-usesâ and to âmilitary end-users.â 744.17... microprocessors for “military end-uses” and to “military end-users.” (a) General prohibition. In addition to the... reexport commodities described in ECCN 3A991.a.1 on the CCL (“microprocessor microcircuits”, “microcomputer...

15 CFR 744.17 - Restrictions on certain exports and reexports of general purpose microprocessors for ‘military...

Code of Federal Regulations, 2014 CFR

2014-01-01

... reexports of general purpose microprocessors for âmilitary end usesâ and to âmilitary end usersâ. 744.17... microprocessors for ‘military end uses’ and to ‘military end users’. (a) General prohibition. In addition to the... reexport commodities described in ECCN 3A991.a.1 on the CCL (“microprocessor microcircuits”, “microcomputer...

15 CFR 744.17 - Restrictions on certain exports and reexports of general purpose microprocessors for “military...

Code of Federal Regulations, 2012 CFR

2012-01-01

... reexports of general purpose microprocessors for âmilitary end-usesâ and to âmilitary end-users.â 744.17... microprocessors for “military end-uses” and to “military end-users.” (a) General prohibition. In addition to the... reexport commodities described in ECCN 3A991.a.1 on the CCL (“microprocessor microcircuits”, “microcomputer...

15 CFR 744.17 - Restrictions on certain exports and reexports of general purpose microprocessors for “military...

Code of Federal Regulations, 2011 CFR

2011-01-01

... reexports of general purpose microprocessors for âmilitary end-usesâ and to âmilitary end-users.â 744.17... microprocessors for “military end-uses” and to “military end-users.” (a) General prohibition. In addition to the... reexport commodities described in ECCN 3A991.a.1 on the CCL (“microprocessor microcircuits”, “microcomputer...

Operation of commercially-based microcomputer technology in a space radiation environment

NASA Astrophysics Data System (ADS)

Yelverton, J. N.

This paper focuses on detection and recovery techniques that should enable the reliable operation of commercially-based microprocessor technology in the harsh radiation environment of space and at high altitudes. This approach is especially significant in light of the current shift in emphasis (due to cost) from space hardened Class-S parts qualification to a more direct use of commercial parts. The method should offset some of the concern that the newer high density state-of-the-art RISC and CISC microprocessors can be used in future space applications. Also, commercial aviation, should benefit, since radiation induced transients are a new issue arising from the increased quantities of microcomputers used in aircraft avionics.

The application of digital signal processing techniques to a teleoperator radar system

NASA Technical Reports Server (NTRS)

Pujol, A.

1982-01-01

A digital signal processing system was studied for the determination of the spectral frequency distribution of echo signals from a teleoperator radar system. The system consisted of a sample and hold circuit, an analog to digital converter, a digital filter, and a Fast Fourier Transform. The system is interfaced to a 16 bit microprocessor. The microprocessor is programmed to control the complete digital signal processing. The digital filtering and Fast Fourier Transform functions are implemented by a S2815 digital filter/utility peripheral chip and a S2814A Fast Fourier Transform chip. The S2815 initially simulates a low-pass Butterworth filter with later expansion to complete filter circuit (bandpass and highpass) synthesizing.

A microprocessor based anti-aliasing filter for a PCM system

NASA Technical Reports Server (NTRS)

Morrow, D. C.; Sandlin, D. R.

1984-01-01

Described is the design and evaluation of a microprocessor based digital filter. The filter was made to investigate the feasibility of a digital replacement for the analog pre-sampling filters used in telemetry systems at the NASA Ames-Dryden Flight Research Facility (DFRF). The digital filter will utilize an Intel 2920 Analog Signal Processor (ASP) chip. Testing includes measurements of: (1) the filter frequency response and, (2) the filter signal resolution. The evaluation of the digital filter was made on the basis of circuit size, projected environmental stability and filter resolution. The 2920 based digital filter was found to meet or exceed the pre-sampling filter specifications for limited signal resolution applications.

Application of digital control to a magnetic model suspension and balance model

NASA Technical Reports Server (NTRS)

Luh, P. B.; Covert, E. E.; Whitaker, H. P.; Haldeman, C. W.

1978-01-01

The feasibility of using a digital computer for performing the automatic control functions for a magnetic suspension and balance system (MSBS) for use with wind tunnel models was investigated. Modeling was done using both a prototype MSBS and a one dimensional magnetic balance. A microcomputer using the Intel 8080 microprocessor is described and results are given using this microprocessor to control the one dimensional balance. Hybrid simulations for one degree of freedom of the MSBS were also performed and are reported. It is concluded that use of a digital computer to control the MSBS is eminently feasible and should extend both the accuracy and utility of the system.

A system for applying rapid warming or cooling stimuli to cells during patch clamp recording or ion imaging.

PubMed

Reid, G; Amuzescu, B; Zech, E; Flonta, M L

2001-10-15

We describe a system for superfusing small groups of cells at a precisely controlled and rapidly adjustable local temperature. Before being applied to the cell or cells under study, solutions are heated or cooled in a chamber of small volume ( approximately 150 microl) and large surface area, sandwiched between four small Peltier elements. The current through the Peltier elements is controlled by a microprocessor using a PID (proportional-integral-derivative) feedback algorithm. The chamber can be heated to at least 60 degrees C and cooled to 0 degrees C, changing its temperature at a maximum rate of about 7 degrees C per second; temperature ramps can be followed under feedback control at up to 4 degrees C per second. Temperature commands can be applied from the digital-to-analogue converter of any laboratory interface or generated digitally by the microprocessor. The peak-to-peak noise contributed by the system does not exceed that contributed by a patch pipette, holder and headstage, making it suitable for single channel as well as whole cell recordings.

Transcription of the Workshop on General Aviation Advanced Avionics Systems

NASA Technical Reports Server (NTRS)

Tashker, M. (Editor)

1975-01-01

Papers are presented dealing with the design of reliable, low cost, advanced avionics systems applicable to general aviation in the 1980's and beyond. Sensors, displays, integrated circuits, microprocessors, and minicomputers are among the topics discussed.

Digital interface of electronic transformers based on embedded system

NASA Astrophysics Data System (ADS)

Shang, Qiufeng; Qi, Yincheng

2008-10-01

Benefited from digital interface of electronic transformers, information sharing and system integration in substation can be realized. An embedded system-based digital output scheme of electronic transformers is proposed. The digital interface is designed with S3C44B0X 32bit RISC microprocessor as the hardware platform. The μCLinux operation system (OS) is transplanted on ARM7 (S3C44B0X). Applying Ethernet technology as the communication mode in the substation automation system is a new trend. The network interface chip RTL8019AS is adopted. Data transmission is realized through the in-line TCP/IP protocol of uClinux embedded OS. The application result and character analysis show that the design can meet the real-time and reliability requirements of IEC60044-7/8 electronic voltage/current instrument transformer standards.

IEEE 1451.2 based Smart sensor system using ADuc847

NASA Astrophysics Data System (ADS)

Sreejithlal, A.; Ajith, Jose

IEEE 1451 standard defines a standard interface for connecting transducers to microprocessor based data acquisition systems, instrumentation systems, control and field networks. Smart transducer interface module (STIM) acts as a unit which provides signal conditioning, digitization and data packet generation functions to the transducers connected to it. This paper describes the implementation of a microcontroller based smart transducer interface module based on IEEE 1451.2 standard. The module, implemented using ADuc847 microcontroller has 2 transducer channels and is programmed using Embedded C language. The Sensor system consists of a Network Controlled Application Processor (NCAP) module which controls the Smart transducer interface module (STIM) over an IEEE1451.2-RS232 bus. The NCAP module is implemented as a software module in C# language. The hardware details, control principles involved and the software implementation for the STIM are described in detail.

JPRS Report, Science & Technology, China, High-Performance Computer Systems

DTIC Science & Technology

1992-10-28

microprocessor array The microprocessor array in the AP85 system is com- posed of 16 completely identical array element micro - processors . Each array element...microprocessors and capable of host machine reading and writing. The memory capacity of the array element micro - processors as a whole can be expanded...transmission functions to carry out data transmission from array element micro - processor to array element microprocessor, from array element

External Verification of SCADA System Embedded Controller Firmware

DTIC Science & Technology

2012-03-01

microprocessor and read-only memory (ROM) or flash memory for storing firmware and control logic [5],[8]. A PLC typically has three software levels as shown in...implementing different firmware. Because PLCs are in effect a microprocessor device, an analysis of the current research on embedded devices is important...Electronics Engineers (IEEE) published a 15 best practices guide for firmware control on microprocessors [44]. IEEE suggests that microprocessors

OS friendly microprocessor architecture: Hardware level computer security

NASA Astrophysics Data System (ADS)

Jungwirth, Patrick; La Fratta, Patrick

2016-05-01

We present an introduction to the patented OS Friendly Microprocessor Architecture (OSFA) and hardware level computer security. Conventional microprocessors have not tried to balance hardware performance and OS performance at the same time. Conventional microprocessors have depended on the Operating System for computer security and information assurance. The goal of the OS Friendly Architecture is to provide a high performance and secure microprocessor and OS system. We are interested in cyber security, information technology (IT), and SCADA control professionals reviewing the hardware level security features. The OS Friendly Architecture is a switched set of cache memory banks in a pipeline configuration. For light-weight threads, the memory pipeline configuration provides near instantaneous context switching times. The pipelining and parallelism provided by the cache memory pipeline provides for background cache read and write operations while the microprocessor's execution pipeline is running instructions. The cache bank selection controllers provide arbitration to prevent the memory pipeline and microprocessor's execution pipeline from accessing the same cache bank at the same time. This separation allows the cache memory pages to transfer to and from level 1 (L1) caching while the microprocessor pipeline is executing instructions. Computer security operations are implemented in hardware. By extending Unix file permissions bits to each cache memory bank and memory address, the OSFA provides hardware level computer security.

Microprocessor-based interface for oceanography

NASA Technical Reports Server (NTRS)

Hansen, G. R.

1979-01-01

Ocean floor imaging system incorporates five identical microprocessor-based interface units each assigned to specific sonar instrument to simplify system. Central control module based on same microprocessor eliminates need for custom tailoring hardware interfaces for each instrument.

Comparative biomechanical analysis of current microprocessor-controlled prosthetic knee joints.

PubMed

Bellmann, Malte; Schmalz, Thomas; Blumentritt, Siegmar

2010-04-01

To investigate and identify functional differences of 4 microprocessor-controlled prosthetic knee joints (C-Leg, Hybrid Knee [also called Energy Knee], Rheo Knee, Adaptive 2). Tested situations were walking on level ground, on stairs and ramps; additionally, the fall prevention potentials for each design were examined. The measuring technology used included an optoelectronic camera system combined with 2 forceplates as well as a mobile spiroergometric system. The study was conducted in a gait laboratory. Subjects with unilateral transfemoral amputations (N=9; mobility grade, 3-4; age, 22-49y) were tested. Participants were fitted and tested with 4 different microprocessor-controlled knee joints. Static prosthetic alignment, time distance parameters, kinematic and kinetic data and metabolic energy consumption. Compared with the Hybrid Knee and the Adaptive 2, the C-Leg offers clear advantages in the provision of adequate swing phase flexion resistances and terminal extension damping during level walking at various speeds, especially at higher walking speeds. The Rheo Knee provides sufficient terminal extension; however, swing phase flexion resistances seem to be too low. The values for metabolic energy consumption show only slight differences during level walking. The joint resistances generated for descending stairs and ramps relieve the contralateral side to varying degrees. When walking on stairs, safety-relevant technical differences between the investigated joint types can be observed. Designs with adequate internal resistances offer stability advantages when the foot is positioned on the step. Stumble recovery tests reveal that the different knee joint designs vary in their effectiveness in preventing the patient from falling. The patient benefits provided by the investigated electronic prosthetic knee joints differ considerably. The C-Leg appears to offer the amputee greater functional and safety-related advantages than the other tested knee joints. Reduced loading of the contralateral side has been demonstrated during ramp and stair descent. Metabolic energy consumption does not vary significantly between the tested knees. Hence, this parameter seems not to be a suitable criterion for assessing microprocessor-controlled knee components. Copyright 2010 American Congress of Rehabilitation Medicine. Published by Elsevier Inc. All rights reserved.

Microprocessor controlled movement of liquid gastric content using sequential neural electrical stimulation

PubMed Central

Mintchev, M; Sanmiguel, C; Otto, S; Bowes, K

1998-01-01

Background—Gastric electrical stimulation has been attempted for several years with little success. 
Aims—To determine whether movement of liquid gastric content could be achieved using microprocessor controlled sequential electrical stimulation. 
Methods—Eight anaesthetised dogs underwent laparotomy and implantation of four sets of bipolar stainless steel wire electrodes. Each set consisted of two to six electrodes (10×0.25 mm, 3 cm apart) implanted circumferentially. The stomach was filled with water and the process of gastric emptying was monitored. Artificial contractions were produced using microprocessor controlled phase locked bipolar four second trains of 50 Hz, 14 V (peak to peak) rectangular voltage. In four of the dogs four force transducers were implanted close to each circumferential electrode set. In one gastroparetic patient the effect of direct electrical stimulation was determined at laparotomy. 
Results—Using the above stimulating parameters circumferential gastric contractions were produced which were artificially propagated distally by phase locking the stimulating voltage. Averaged stimulated gastric emptying times were significantly shorter than spontaneus emptying times (t1/2 6.7 (3.0) versus 25.3 (12.9) minutes, p<0.01). Gastric electrical stimulation of the gastroparetic patient at operation produced circumferential contractions. 
Conclusions—Microprocessor controlled electrical stimulation produced artificial peristalsis and notably accelerated the movement of liquid gastric content. 

 Keywords: gastric electrical stimulation; gastric motility PMID:9824339

Single event effect testing of the Intel 80386 family and the 80486 microprocessor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Moran, A.; LaBel, K.; Gates, M.

The authors present single event effect test results for the Intel 80386 microprocessor, the 80387 coprocessor, the 82380 peripheral device, and on the 80486 microprocessor. Both single event upset and latchup conditions were monitored.

Microprocessors and the Curriculum.

ERIC Educational Resources Information Center

Pasahow, Edward J.

1981-01-01

Presents three approaches to teaching the use of a microprocessor: (1) a "generic" device on paper; (2) a "conglomeration" device, surveying a number of real products; and (3) the "how" course which covers a small number of actual but related microprocessors. (CT)

Software resilience and the effectiveness of software mitigation in microcontrollers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Quinn, Heather; Baker, Zachary; Fairbanks, Tom

Commercially available microprocessors could be useful to the space community for noncritical computations. There are many possible components that are smaller, lower-power, and less expensive than traditional radiation-hardened microprocessors. Many commercial microprocessors have issues with single-event effects (SEEs), such as single-event upsets (SEUs) and single-event transients (SETs), that can cause the microprocessor to calculate an incorrect result or crash. In this paper we present the Trikaya technique for masking SEUs and SETs through software mitigation techniques. Furthermore, test results show that this technique can be very effective at masking errors, making it possible to fly these microprocessors for a varietymore » of missions.« less

Software resilience and the effectiveness of software mitigation in microcontrollers

DOE PAGES

Quinn, Heather; Baker, Zachary; Fairbanks, Tom; ...

2015-12-01

Commercially available microprocessors could be useful to the space community for noncritical computations. There are many possible components that are smaller, lower-power, and less expensive than traditional radiation-hardened microprocessors. Many commercial microprocessors have issues with single-event effects (SEEs), such as single-event upsets (SEUs) and single-event transients (SETs), that can cause the microprocessor to calculate an incorrect result or crash. In this paper we present the Trikaya technique for masking SEUs and SETs through software mitigation techniques. Furthermore, test results show that this technique can be very effective at masking errors, making it possible to fly these microprocessors for a varietymore » of missions.« less

Microprocessors in Systems Engineering at the U.S. Naval Academy.

ERIC Educational Resources Information Center

Mitchell, Eugene E., Ed.; Lowe, W. M., Ed.

1982-01-01

Describes the introduction of microprocessors into the Weapons and Systems Engineering Department at the U.S. Naval Academy, including planning decisions, implementation, procedures, uses of microprocessors in the department, and impact on the Systems Engineering major and curriculum. (SK)

Aircraft interrogation and display system: A ground support equipment for digital flight systems

NASA Technical Reports Server (NTRS)

Glover, R. D.

1982-01-01

A microprocessor-based general purpose ground support equipment for electronic systems was developed. The hardware and software are designed to permit diverse applications in support of aircraft flight systems and simulation facilities. The implementation of the hardware, the structure of the software, describes the application of the system to an ongoing research aircraft project are described.

Microprocessor controlled compliance monitor for eye drop medication.

PubMed

Hermann, M M; Diestelhorst, M

2006-07-01

The effectiveness of a self administered eye drop medication can only be assessed if the compliance is known. The authors studied the specificity and sensitivity of a new microprocessor controlled monitoring device. The monitoring system was conducted by an 8 bit microcontroller for data acquisition and storage with sensors measuring applied pressure to the bottle, temperature, and vertical position. 10 devices were mounted under commercial 10 ml eye drops. Test subjects had to note down each application manually. A total of 15 applications each within 3 days was intended. Manual reports confirmed 15 applications for each of the 10 bottles. The monitoring devices detected a total of 149 events; one was missed; comprising a sensitivity of 99%. Two devices registered three applications, which did not appear in the manual protocols, indicating a specificity of about 98%. Refrigerated bottles were correctly identified. The battery lifetime exceeded 60 days. The new monitoring device demonstrated a high reliability of the collected compliance data. The important, yet often unknown, influence of compliance in patient care and clinical trials shall be illuminated by the new device. This may lead to a better adapted patient care. Studies will profit from a higher credibility and results will be less influenced by non-compliance.

Practical application to composite materials of a portable digital ultrasound device controlled by a microprocessor

NASA Astrophysics Data System (ADS)

Castel, J. G.; Husarek, V.

1987-06-01

The usefulness of a portable microprocessor-controlled ultrasound device for the periodic assessment of aircraft parts made of composite materials is shown. The performance of the device is demonstrated with the examples of a metallic honeycomb with a carbon-fiber skin, a phenolic honeycomb with a carbon skin, and a phenolic honeycomb with a Kevlar skin. Also considered are assessments of homogeneous carbon-fiber parts, including the study of artificial defects consisting of 1-2 mm diameter holes, and the assessment of the behavior of a carbon-titanium interface with separated zones. Advantages of the device include ease of adjustment, automated evaluation of the depth of defects, and the nearly-absolute reproducibility of adjustments.

Automated Liquid-Level Control of a Nutrient Reservoir for a Hydroponic System

NASA Technical Reports Server (NTRS)

Smith, Boris; Asumadu, Johnson A.; Dogan, Numan S.

1997-01-01

A microprocessor-based system for control of the liquid level of a nutrient reservoir for a plant hydroponic growing system has been developed. The system uses an ultrasonic transducer to sense the liquid level or height. A National Instruments' Multifunction Analog and Digital Input/Output PC Kit includes NI-DAQ DOS/Windows driver software for an IBM 486 personal computer. A Labview Full Development system for Windows is the graphical programming system being used. The system allows liquid level control to within 0.1 cm for all levels tried between 8 and 36 cm in the hydroponic system application. The detailed algorithms have been developed and a fully automated microprocessor based nutrient replenishment system has been described for this hydroponic system.

Application of low-noise CID imagers in scientific instrumentation cameras

NASA Astrophysics Data System (ADS)

Carbone, Joseph; Hutton, J.; Arnold, Frank S.; Zarnowski, Jeffrey J.; Vangorden, Steven; Pilon, Michael J.; Wadsworth, Mark V.

1991-07-01

CIDTEC has developed a PC-based instrumentation camera incorporating a preamplifier per row CID imager and a microprocessor/LCA camera controller. The camera takes advantage of CID X-Y addressability to randomly read individual pixels and potentially overlapping pixel subsets in true nondestructive (NDRO) as well as destructive readout modes. Using an oxy- nitride fabricated CID and the NDRO readout technique, pixel full well and noise levels of approximately 1*10(superscript 6) and 40 electrons, respectively, were measured. Data taken from test structures indicates noise levels (which appear to be 1/f limited) can be reduced by a factor of two by eliminating the nitride under the preamplifier gate. Due to software programmability, versatile readout capabilities, wide dynamic range, and extended UV/IR capability, this camera appears to be ideally suited for use in spectroscopy and other scientific applications.

75 FR 2591 - Petition for Waiver of Compliance

Federal Register 2010, 2011, 2012, 2013, 2014

2010-01-15

... on vital microprocessor-based systems. CSXT proposes to verify and test signal locking systems controlled by microprocessor-based equipment by use of alternative procedures every 4 years after initial... vital microprocessor-based systems. These systems utilize programmed logic equations in lieu of relays...

Redundant Asynchronous Microprocessor System

NASA Technical Reports Server (NTRS)

Meyer, G.; Johnston, J. O.; Dunn, W. R.

1985-01-01

Fault-tolerant computer structure called RAMPS (for redundant asynchronous microprocessor system) has simplicity of static redundancy but offers intermittent-fault handling ability of complex, dynamically redundant systems. New structure useful wherever several microprocessors are employed for control - in aircraft, industrial processes, robotics, and automatic machining, for example.

Module comprising IC memory stack dedicated to and structurally combined with an IC microprocessor chip

NASA Technical Reports Server (NTRS)

Carson, John C. (Inventor); Indin, Ronald J. (Inventor); Shanken, Stuart N. (Inventor)

1994-01-01

A computer module is disclosed in which a stack of glued together IC memory chips is structurally integrated with a microprocessor chip. The memory provided by the stack is dedicated to the microprocessor chip. The microprocessor and its memory stack may be connected either by glue and/or by solder bumps. The solder bumps can perform three functions--electrical interconnection, mechanical connection, and heat transfer. The electrical connections in some versions are provided by wire bonding.

High-speed microprocessor characterization. Final report/project accomplishments summary, CRADA Number KCP-94-1004

DOE Office of Scientific and Technical Information (OSTI.GOV)

Brown, L.W.

The objective of the project was to characterize and document the critical operating parameters of an 0.8-micron, 350-MHz, 32-bit microprocessor prototype. The roles of FM and T and the participant company were: FM and T -- evaluation performance of the prototype 32-bit microprocessor using the IDS5000 and Tektronix S3260 Integrated Circuit Test System; Corda -- design and build the prototype microprocessor. This project was terminated with nearly all of the planned activities unaddressed.

76 FR 61476 - Petition for Waiver of Compliance

Federal Register 2010, 2011, 2012, 2013, 2014

2011-10-04

... locking; and 236.109, Time releases, timing relays and timing devices; on vital microprocessor-based... microprocessor-based locking systems. These tests, at this interval, would replace the tests currently required... listed in Exhibit B. 2. All future purchases of microprocessor-controlled interlocking locations. 3...

Future Applications of Electronic Technology to Education.

ERIC Educational Resources Information Center

Lewis, Arthur J.; And Others

Developments in electronic technology that have improved and linked together telecommunication and computers are discussed, as well as their use in instruction, implications of this use, and associated issues. The first section briefly describes the following developments: microcomputers and microprocessors, bubble memory, lasers, holography,…

Identifying, Quantifying, Extracting and Enhancing Implicit Parallelism

ERIC Educational Resources Information Center

Agarwal, Mayank

2009-01-01

The shift of the microprocessor industry towards multicore architectures has placed a huge burden on the programmers by requiring explicit parallelization for performance. Implicit Parallelization is an alternative that could ease the burden on programmers by parallelizing applications "under the covers" while maintaining sequential semantics…

Neural network application to comprehensive engine diagnostics

NASA Technical Reports Server (NTRS)

Marko, Kenneth A.

1994-01-01

We have previously reported on the use of neural networks for detection and identification of faults in complex microprocessor controlled powertrain systems. The data analyzed in those studies consisted of the full spectrum of signals passing between the engine and the real-time microprocessor controller. The specific task of the classification system was to classify system operation as nominal or abnormal and to identify the fault present. The primary concern in earlier work was the identification of faults, in sensors or actuators in the powertrain system as it was exercised over its full operating range. The use of data from a variety of sources, each contributing some potentially useful information to the classification task, is commonly referred to as sensor fusion and typifies the type of problems successfully addressed using neural networks. In this work we explore the application of neural networks to a different diagnostic problem, the diagnosis of faults in newly manufactured engines and the utility of neural networks for process control.

Microprocessor control and networking for the amps breadboard

NASA Technical Reports Server (NTRS)

Floyd, Stephen A.

1987-01-01

Future space missions will require more sophisticated power systems, implying higher costs and more extensive crew and ground support involvement. To decrease this human involvement, as well as to protect and most efficiently utilize this important resource, NASA has undertaken major efforts to promote progress in the design and development of autonomously managed power systems. Two areas being actively pursued are autonomous power system (APS) breadboards and knowledge-based expert system (KBES) applications. The former are viewed as a requirement for the timely development of the latter. Not only will they serve as final testbeds for the various KBES applications, but will play a major role in the knowledge engineering phase of their development. The current power system breadboard designs are of a distributed microprocessor nature. The distributed nature, plus the need to connect various external computer capabilities (i.e., conventional host computers and symbolic processors), places major emphasis on effective networking. The communications and networking technologies for the first power system breadboard/test facility are described.

The Stand-Alone Microprocessor System: A Valuable Tool in College Admissions and Recruitment.

ERIC Educational Resources Information Center

Garrett, Larry Neal

1983-01-01

The stand-alone microprocessor is seen as one innovative tool that can be used both in the organizational management of decline and in meeting specific organizational needs such as those of the admissions director and staff. The term "microprocessor" is defined. (MLW)

78 FR 3449 - Certain Microprocessors, Components Thereof, and Products Containing Same; Request for Statements...

Federal Register 2010, 2011, 2012, 2013, 2014

2013-01-16

... INTERNATIONAL TRADE COMMISSION [Investigation No. 337-TA-781] Certain Microprocessors, Components Thereof, and Products Containing Same; Request for Statements on the Public Interest AGENCY: U.S... a limited exclusion order as to subject Intel microprocessors, but that implementation be delayed...

Direct medical costs of accidental falls for adults with transfemoral amputations.

PubMed

Mundell, Benjamin; Maradit Kremers, Hilal; Visscher, Sue; Hoppe, Kurtis; Kaufman, Kenton

2017-12-01

Active individuals with transfemoral amputations are provided a microprocessor-controlled knee with the belief that the prosthesis reduces their risk of falling. However, these prostheses are expensive and the cost-effectiveness is unknown with regard to falls in the transfemoral amputation population. The direct medical costs of falls in adults with transfemoral amputations need to be determined in order to assess the incremental costs and benefits of microprocessor-controlled prosthetic knees. We describe the direct medical costs of falls in adults with a transfemoral amputation. This is a retrospective, population-based, cohort study of adults who underwent transfemoral amputations between 2000 and 2014. A Bayesian structural time series approach was used to estimate cost differences between fallers and non-fallers. The mean 6-month direct medical costs of falls for six hospitalized adults with transfemoral amputations was US$25,652 (US$10,468, US$38,872). The mean costs for the 10 adults admitted to the emergency department was US$18,091 (US$-7,820, US$57,368). Falls are expensive in adults with transfemoral amputations. The 6-month costs of falls resulting in hospitalization are similar to those reported in the elderly population who are also at an increased risk of falling. Clinical relevance Estimates of fall costs in adults with transfemoral amputations can provide policy makers with additional insight when determining whether or not to cover a prescription for microprocessor-controlled prosthetic knees.

Gallium-arsenide process evaluation based on a RISC microprocessor example

NASA Astrophysics Data System (ADS)

Brown, Richard B.; Upton, Michael; Chandna, Ajay; Huff, Thomas R.; Mudge, Trevor N.; Oettel, Richard E.

1993-10-01

This work evaluates the features of a gallium-arsenide E/D MESFET process in which a 32-b RISC microprocessor was implemented. The design methodology and architecture of this prototype CPU are described. The performance sensitivity of the microprocessor and other large circuit blocks to different process parameters is analyzed, and recommendations for future process features, circuit approaches, and layout styles are made. These recommendations are reflected in the design of a second microprocessor using a more advanced process that achieves much higher density and performance.

Integrally regulated solar array demonstration using an Intel 8080 microprocessor

NASA Technical Reports Server (NTRS)

Petrik, E. J.

1977-01-01

A concept for regulating the voltage of a solar array by using a microprocessor to effect discrete voltage changes was demonstrated. Eight shorting switches were employed to regulate a simulated array at set-point voltages between 10,000 and 15,000 volts. The demonstration showed that the microprocessor easily regulated the solar array output voltage independently of whether or not the switched cell groups were binary sized in voltage. In addition, the microprocessor provided logic memory capability to perform additional tasks such as locating and insolating a faulty switch.

Single-Event Upset and Scaling Trends in New Generation of the Commercial SOI PowerPC Microprocessors

NASA Technical Reports Server (NTRS)

Irom, Farokh; Farmanesh, Farhad; Kouba, Coy K.

2006-01-01

Single-event upset effects from heavy ions are measured for Motorola silicon-on-insulator (SOI) microprocessor with 90 nm feature sizes. The results are compared with previous results for SOI microprocessors with feature sizes of 130 and 180 nm. The cross section of the 90 nm SOI processors is smaller than results for 130 and 180 nm counterparts, but the threshold is about the same. The scaling of the cross section with reduction of feature size and core voltage for SOI microprocessors is discussed.

An assembler for the MOS Technology 6502 microprocessor as implemented in jolt (TM) and KIM-1 (TM)

NASA Technical Reports Server (NTRS)

Lilley, R. W.

1976-01-01

Design of low-cost, microcomputer-based navigation receivers, and the assembler are described. The development of computer software for microprocessors is materially aided by the assembler program using mnemonic variable names. The flexibility of the environment provided by the IBM's Virtual Machine Facility and the Conversational Monitor System, make possible the convenient assembler access. The implementation of the assembler for the microprocessor chip serves a part of the present need and forms a model for support of other microprocessors.

Genomic analysis suggests that mRNA destabilization by the microprocessor is specialized for the auto-regulation of Dgcr8.

PubMed

Shenoy, Archana; Blelloch, Robert

2009-09-11

The Microprocessor, containing the RNA binding protein Dgcr8 and RNase III enzyme Drosha, is responsible for processing primary microRNAs to precursor microRNAs. The Microprocessor regulates its own levels by cleaving hairpins in the 5'UTR and coding region of the Dgcr8 mRNA, thereby destabilizing the mature transcript. To determine whether the Microprocessor has a broader role in directly regulating other coding mRNA levels, we integrated results from expression profiling and ultra high-throughput deep sequencing of small RNAs. Expression analysis of mRNAs in wild-type, Dgcr8 knockout, and Dicer knockout mouse embryonic stem (ES) cells uncovered mRNAs that were specifically upregulated in the Dgcr8 null background. A number of these transcripts had evolutionarily conserved predicted hairpin targets for the Microprocessor. However, analysis of deep sequencing data of 18 to 200nt small RNAs in mouse ES, HeLa, and HepG2 indicates that exonic sequence reads that map in a pattern consistent with Microprocessor activity are unique to Dgcr8. We conclude that the Microprocessor's role in directly destabilizing coding mRNAs is likely specifically targeted to Dgcr8 itself, suggesting a specialized cellular mechanism for gene auto-regulation.

Fiber Laser methane sensor with the function of self-diagnose

NASA Astrophysics Data System (ADS)

Li, Yan-fang; Wei, Yu-bin; Shang, Ying; Wang, Chang; Liu, Tong-yu

2012-02-01

Using the technology of tunable diode laser absorption spectroscopy and the technology of micro-electronics, a fiber laser methane sensor based on the microprocessor C8051F410 is given. In this paper, we use the DFB Laser as the light source of the sensor. By tuning temperature and driver current of the DFB laser, we can scan the laser over the methane absorption line, Based on the Beer-Lambert law, through detect the variation of the light power before and after the absorption we realize the methane detection. It makes the real-time and online detection of methane concentration to be true, and it has the advantages just as high accuracy, immunity to other gases , long calibration cycle and so on. The sensor has the function of adaptive gain and self-diagnose. By introducing digital potentiometers, the gain of the photoelectric conversion operational amplifier can be controlled by the microprocessor according to the light power. When the gain and the conversion voltage achieve the set value, then we can consider the sensor in a fault status, and then the software will alarm us to check the status of the probe. So we improved the dependence and the stability of the measured results. At last we give some analysis on the sensor according the field application and according the present working, we have a look of our next work in the distance.

An electronic flow control system for a variable-rate tree sprayer

USDA-ARS?s Scientific Manuscript database

Precise modulation of nozzle flow rates is a critical measure to achieve variable-rate spray applications. An electronic flow rate control system accommodating with microprocessors and pulse width modulation (PWM) controlled solenoid valves was designed to manipulate the output of spray nozzles inde...

Development of digital flow control system for multi-channel variable-rate sprayers

USDA-ARS?s Scientific Manuscript database

Precision modulation of nozzle flow rates is a critical step for variable-rate spray applications in orchards and ornamental nurseries. An automatic flow rate control system activated with microprocessors and pulse width modulation (PWM) controlled solenoid valves was developed to control flow rates...

Commercial Parts Radiation Testing

DTIC Science & Technology

2015-01-13

New Mexico’s COSMIAC Center performed radiation testing on a series of operational amplifiers, microcontrollers and microprocessor. The...commercial microcontroller and microprocessor equipment. The team would develop a list of the most promising commercial parts that might be utilized to...parts will include microprocessors, microcontrollers and memory modules. In addition, Field Programmable Gate Arrays (FPGAs) will also be chosen

Microprocessors: An Understandable Guide for the Classroom Teacher.

ERIC Educational Resources Information Center

Okinaka, Russell T.

A microprocessor constitutes the heart and soul of a personal computer. Indeed, the quality of a personal computer is determined largely by the type of microprocessor that is included within its circuitry. Since the microcomputer revolution began in the late 1970s, these special chips have gone through a series of improvements and modifications.…

Cellular functions of the microprocessor.

PubMed

Macias, Sara; Cordiner, Ross A; Cáceres, Javier F

2013-08-01

The microprocessor is a complex comprising the RNase III enzyme Drosha and the double-stranded RNA-binding protein DGCR8 (DiGeorge syndrome critical region 8 gene) that catalyses the nuclear step of miRNA (microRNA) biogenesis. DGCR8 recognizes the RNA substrate, whereas Drosha functions as an endonuclease. Recent global analyses of microprocessor and Dicer proteins have suggested novel functions for these components independent of their role in miRNA biogenesis. A HITS-CLIP (high-throughput sequencing of RNA isolated by cross-linking immunoprecipitation) experiment designed to identify novel substrates of the microprocessor revealed that this complex binds and regulates a large variety of cellular RNAs. The microprocessor-mediated cleavage of several classes of RNAs not only regulates transcript levels, but also modulates alternative splicing events, independently of miRNA function. Importantly, DGCR8 can also associate with other nucleases, suggesting the existence of alternative DGCR8 complexes that may regulate the fate of a subset of cellular RNAs. The aim of the present review is to provide an overview of the diverse functional roles of the microprocessor.

Microprocessor design for GaAs technology

NASA Astrophysics Data System (ADS)

Milutinovic, Veljko M.

Recent advances in the design of GaAs microprocessor chips are examined in chapters contributed by leading experts; the work is intended as reading material for a graduate engineering course or as a practical R&D reference. Topics addressed include the methodology used for the architecture, organization, and design of GaAs processors; GaAs device physics and circuit design; design concepts for microprocessor-based GaAs systems; a 32-bit GaAs microprocessor; a 32-bit processor implemented in GaAs JFET; and a direct coupled-FET-logic E/D-MESFET experimental RISC machine. Drawings, micrographs, and extensive circuit diagrams are provided.

Development of a real-time chemical injection system for air-assisted variable-rate sprayers

USDA-ARS?s Scientific Manuscript database

A chemical injection system is an effective method to minimize chemical waste and reduce the environmental pollution in pesticide spray applications. A microprocessor controlled injection system implementing a ceramic piston metering pump was developed to accurately dispense chemicals to be mixed wi...

Network Interface Specification for the T1 Microprocessor

DTIC Science & Technology

1994-05-01

features data transfer directly to/from processor registers, hardware dispatch directly to Active Message handlers (along with limited context...Implementation Choices 9 3.1 Overview .................................... 9 3.2 Context ..................................... 10 3.3 Data Transfer...details of the data transfer functional units, interconnect structure, and network operation. Application Layer Communication Model Communication

77 FR 35107 - Petition for Waiver of Compliance

Federal Register 2010, 2011, 2012, 2013, 2014

2012-06-12

... devices. CSX requests relief from 49 CFR 236.109 as it applies to variable timers within the program logic... program logic of the operating software. However, CSX notes that some microprocessor-based equipment have.../check sum/universal control number of the existing location specific application logic to the previously...

A programmable transformer coupled converter for high-power space applications

NASA Technical Reports Server (NTRS)

Kapustka, R. E.; Bush, J. R., Jr.; Graves, J. R.; Lanier, J. R., Jr.

1986-01-01

A programmable transformer coupled converter (PTCC) is being developed by NASA/Marshall Space Flight Center for application in future large space power systems. The PTCC uses an internal microprocessor to control the output characteristics of its three Cuk integrated magnetics type power stages which have a combined capability of 5.4 kW (30 V at 180 A). Details of design trade-offs and test results are presented.

Microprogrammable Integrated Data Acquisition System-Fatigue Life Data Application

DTIC Science & Technology

1976-03-01

Lt. James W. Sturges, successfully applied the Midas general system [Sturges, 1975] to the fatigue life data monitoring problem and proved its...life data problem . The Midas FLD system computer program generates the required signals in the proper sequence for effectively sampling the 8-channel...Integrated Data Acquisition System- Fatigue Life Data Application" ( Midas FLD) is a microprocessor based data acquisition system. It incorporates a Pro-Log

Microprocessor-Controlled Laser Balancing System

NASA Technical Reports Server (NTRS)

Demuth, R. S.

1985-01-01

Material removed by laser action as part tested for balance. Directed by microprocessor, laser fires appropriate amount of pulses in correct locations to remove necessary amount of material. Operator and microprocessor software interact through video screen and keypad; no programing skills or unprompted system-control decisions required. System provides complete and accurate balancing in single load-and-spinup cycle.

Microprocessor controlled compliance monitor for eye drop medication

PubMed Central

Hermann, M M; Diestelhorst, M

2006-01-01

Background/aims The effectiveness of a self administered eye drop medication can only be assessed if the compliance is known. The authors studied the specificity and sensitivity of a new microprocessor controlled monitoring device. Methods The monitoring system was conducted by an 8 bit microcontroller for data acquisition and storage with sensors measuring applied pressure to the bottle, temperature, and vertical position. 10 devices were mounted under commercial 10 ml eye drops. Test subjects had to note down each application manually. A total of 15 applications each within 3 days was intended. Results Manual reports confirmed 15 applications for each of the 10 bottles. The monitoring devices detected a total of 149 events; one was missed; comprising a sensitivity of 99%. Two devices registered three applications, which did not appear in the manual protocols, indicating a specificity of about 98%. Refrigerated bottles were correctly identified. The battery lifetime exceeded 60 days. Conclusion The new monitoring device demonstrated a high reliability of the collected compliance data. The important, yet often unknown, influence of compliance in patient care and clinical trials shall be illuminated by the new device. This may lead to a better adapted patient care. Studies will profit from a higher credibility and results will be less influenced by non‐compliance. PMID:16540488

The Microprocessor controls the activity of mammalian retrotransposons

PubMed Central

Heras, Sara R.; Macias, Sara; Plass, Mireya; Fernandez, Noemí; Cano, David; Eyras, Eduardo; Garcia-Perez, José L.; Cáceres, Javier F.

2013-01-01

More than half of the human genome is made of Transposable Elements. Their ongoing mobilization is a driving force in genetic diversity; however, little is known about how the host regulates their activity. Here, we show that the Microprocessor (Drosha-DGCR8), which is required for microRNA biogenesis, also recognizes and binds RNAs derived from human LINE-1 (Long INterspersed Element 1), Alu and SVA retrotransposons. Expression analyses demonstrate that cells lacking a functional Microprocessor accumulate LINE-1 mRNA and encoded proteins. Furthermore, we show that structured regions of the LINE-1 mRNA can be cleaved in vitro by Drosha. Additionally, we used a cell culture-based assay to show that the Microprocessor negatively regulates LINE-1 and Alu retrotransposition in vivo. Altogether, these data reveal a new role for the Microprocessor as a post-transcriptional repressor of mammalian retrotransposons acting as a defender of human genome integrity. PMID:23995758

The Microprocessor controls the activity of mammalian retrotransposons.

PubMed

Heras, Sara R; Macias, Sara; Plass, Mireya; Fernandez, Noemí; Cano, David; Eyras, Eduardo; Garcia-Perez, José L; Cáceres, Javier F

2013-10-01

More than half of the human genome is made of transposable elements whose ongoing mobilization is a driving force in genetic diversity; however, little is known about how the host regulates their activity. Here, we show that the Microprocessor (Drosha-DGCR8), which is required for microRNA biogenesis, also recognizes and binds RNAs derived from human long interspersed element 1 (LINE-1), Alu and SVA retrotransposons. Expression analyses demonstrate that cells lacking a functional Microprocessor accumulate LINE-1 mRNA and encoded proteins. Furthermore, we show that structured regions of the LINE-1 mRNA can be cleaved in vitro by Drosha. Additionally, we used a cell culture-based assay to show that the Microprocessor negatively regulates LINE-1 and Alu retrotransposition in vivo. Altogether, these data reveal a new role for the Microprocessor as a post-transcriptional repressor of mammalian retrotransposons and a defender of human genome integrity.

Impact of stance phase microprocessor-controlled knee prosthesis on ramp negotiation and community walking function in K2 level transfemoral amputees.

PubMed

Burnfield, Judith M; Eberly, Valerie J; Gronely, Joanne K; Perry, Jacquelin; Yule, William Jared; Mulroy, Sara J

2012-03-01

Microprocessor controlled prosthetic knees (MPK) offer opportunities for improved walking stability and function, but some devices' swing phase features may exceed needs of users with invariable cadence. One MPK offers computerized control of only stance (C-Leg Compact). To assess Medicare Functional Classification Level K2 walkers' ramp negotiation performance, function and balance while using a non-MPK (NMPK) compared to the C-Leg Compact. Crossover. Gait while ascending and descending a ramp (stride characteristics, kinematics, electromyography) and function were assessed in participant's existing NMPK and again in the C-Leg Compact following accommodation. Ramp ascent and descent were markedly faster in the C-Leg Compact compared to the NMPK (p ≤ 0.006), owing to increases in stride length (p ≤ 0.020) and cadence (p ≤ 0.020). Residual limb peak knee flexion and ankle dorsiflexion were significantly greater (12.9° and 4.9° more, respectively) during single limb support while using the C-Leg Compact to descend ramps. Electromyography (mean, peak) did not differ significantly between prosthesis. Function improved in the C-Leg Compact as evidenced by a significantly faster Timed Up and Go and higher functional questionnaire scores. Transfemoral K2 walkers exhibited significantly improved function and balance while using the stance-phase only MPK compared to their traditional NMPK.

Application of microprocessors in an upper atmosphere instrument package

NASA Technical Reports Server (NTRS)

Lim, T. S.; Ehrman, C. H.; Allison, S.

1981-01-01

A servo-driven magnetometer table measuring offset from magnetic north has been developed by NASA to calculate payload azimuth required to point at a celestial target. Used as an aid to the study of gamma-ray phenomena, the high-altitude balloon-borne instrument determines a geocentric reference system, and calculates a set of pointing directions with respect to the system. Principal components include the magnetometer, stepping motor, microcomputer, and gray code shaft encoder. The single-chip microcomputer is used to control the orientation of the system, and consists of a central processing unit, program memory, data memory and input/output ports. Principal advantages include a low power requirement, consuming 6 watts, as compared to 30 watts consumed by the previous system.

A technique for incorporating the NASA spacelab payload dedicated experiment processor software into the simulation system for the payload crew training complex

NASA Technical Reports Server (NTRS)

Bremmer, D. A.

1986-01-01

The feasibility of some off-the-shelf microprocessors and state-of-art software is assessed (1) as a development system for the principle investigator (pi) in the design of the experiment model, (2) as an example of available technology application for future PI's experiments, (3) as a system capable of being interactive in the PCTC's simulation of the dedicated experiment processor (DEP), preferably by bringing the PI's DEP software directly into the simulation model, (4) as a system having bus compatibility with host VAX simulation computers, (5) as a system readily interfaced with mock-up panels and information displays, and (6) as a functional system for post mission data analysis.

Embedded C Programming: A Practical Course Introducing Programmable Microprocessors

ERIC Educational Resources Information Center

Laverty, David M.; Milliken, Jonny; Milford, Matthew; Cregan, Michael

2012-01-01

This paper presents a new laboratory-based module for embedded systems teaching, which addresses the current lack of consideration for the link between hardware development, software implementation, course content and student evaluation in a laboratory environment. The course introduces second year undergraduate students to the interface between…

Microprocessor-based single particle calibration of scintillation counter

NASA Technical Reports Server (NTRS)

Mazumdar, G. K. D.; Pathak, K. M.

1985-01-01

A microprocessor-base set-up is fabricated and tested for the single particle calibration of the plastic scintillator. The single particle response of the scintillator is digitized by an A/D converter, and a 8085 A based microprocessor stores the pulse heights. The digitized information is printed. Facilities for CRT display and cassette storing and recalling are also made available.

Microprocessor Based Real-Time Monitoring of Multiple ECG Signals

PubMed Central

Nasipuri, M.; Basu, D.K.; Dattagupta, R.; Kundu, M.; Banerjee, S.

1987-01-01

A microprocessor based system capable of realtime monitoring of multiple ECG signals has been described. The system consists of a number of microprocessors connected in a hierarchical fashion and capable of working concurrently on ECG data collected from different channels. The system can monitor different arrhythmic abnormalities for at least 36 patients even for a heart rate of 500 beats/min.

Integrated strain array for cellular mechanobiology studies

NASA Astrophysics Data System (ADS)

Simmons, C. S.; Sim, J. Y.; Baechtold, P.; Gonzalez, A.; Chung, C.; Borghi, N.; Pruitt, B. L.

2011-05-01

We have developed an integrated strain array for cell culture enabling high-throughput mechano-transduction studies. Biocompatible cell culture chambers were integrated with an acrylic pneumatic compartment and microprocessor-based control system. Each element of the array consists of a deformable membrane supported by a cylindrical pillar within a well. For user-prescribed waveforms, the annular region of the deformable membrane is pulled into the well around the pillar under vacuum, causing the pillar-supported region with cultured cells to be stretched biaxially. The optically clear device and pillar-based mechanism of operation enables imaging on standard laboratory microscopes. Straightforward fabrication utilizes off-the-shelf components, soft lithography techniques in polydimethylsiloxane and laser ablation of acrylic sheets. Proof of compatibility with basic biological assays and standard imaging equipment were accomplished by straining C2C12 skeletal myoblasts on the device for 6 h. At higher strains, cells and actin stress fibers realign with a circumferential preference.

1988 IEEE Aerospace Applications Conference, Park City, UT, Feb. 7-12, 1988, Digest

NASA Astrophysics Data System (ADS)

The conference presents papers on microwave applications, data and signal processing applications, related aerospace applications, and advanced microelectronic products for the aerospace industry. Topics include a high-performance antenna measurement system, microwave power beaming from earth to space, the digital enhancement of microwave component performance, and a GaAs vector processor based on parallel RISC microprocessors. Consideration is also given to unique techniques for reliable SBNR architectures, a linear analysis subsystem for CSSL-IV, and a structured singular value approach to missile autopilot analysis.

Technology transfer of military space microprocessor developments

NASA Astrophysics Data System (ADS)

Gorden, C.; King, D.; Byington, L.; Lanza, D.

1999-01-01

Over the past 13 years the Air Force Research Laboratory (AFRL) has led the development of microprocessors and computers for USAF space and strategic missile applications. As a result of these Air Force development programs, advanced computer technology is available for use by civil and commercial space customers as well. The Generic VHSIC Spaceborne Computer (GVSC) program began in 1985 at AFRL to fulfill a deficiency in the availability of space-qualified data and control processors. GVSC developed a radiation hardened multi-chip version of the 16-bit, Mil-Std 1750A microprocessor. The follow-on to GVSC, the Advanced Spaceborne Computer Module (ASCM) program, was initiated by AFRL to establish two industrial sources for complete, radiation-hardened 16-bit and 32-bit computers and microelectronic components. Development of the Control Processor Module (CPM), the first of two ASCM contract phases, concluded in 1994 with the availability of two sources for space-qualified, 16-bit Mil-Std-1750A computers, cards, multi-chip modules, and integrated circuits. The second phase of the program, the Advanced Technology Insertion Module (ATIM), was completed in December 1997. ATIM developed two single board computers based on 32-bit reduced instruction set computer (RISC) processors. GVSC, CPM, and ATIM technologies are flying or baselined into the majority of today's DoD, NASA, and commercial satellite systems.

Scaling theory for information networks.

PubMed

Moses, Melanie E; Forrest, Stephanie; Davis, Alan L; Lodder, Mike A; Brown, James H

2008-12-06

Networks distribute energy, materials and information to the components of a variety of natural and human-engineered systems, including organisms, brains, the Internet and microprocessors. Distribution networks enable the integrated and coordinated functioning of these systems, and they also constrain their design. The similar hierarchical branching networks observed in organisms and microprocessors are striking, given that the structure of organisms has evolved via natural selection, while microprocessors are designed by engineers. Metabolic scaling theory (MST) shows that the rate at which networks deliver energy to an organism is proportional to its mass raised to the 3/4 power. We show that computational systems are also characterized by nonlinear network scaling and use MST principles to characterize how information networks scale, focusing on how MST predicts properties of clock distribution networks in microprocessors. The MST equations are modified to account for variation in the size and density of transistors and terminal wires in microprocessors. Based on the scaling of the clock distribution network, we predict a set of trade-offs and performance properties that scale with chip size and the number of transistors. However, there are systematic deviations between power requirements on microprocessors and predictions derived directly from MST. These deviations are addressed by augmenting the model to account for decentralized flow in some microprocessor networks (e.g. in logic networks). More generally, we hypothesize a set of constraints between the size, power and performance of networked information systems including transistors on chips, hosts on the Internet and neurons in the brain.

Extreme Temperature Operation of a 10 MHz Silicon Oscillator Type STCL1100

NASA Technical Reports Server (NTRS)

Patterson, Richard L.; Hammoud, Ahmad

2008-01-01

The performance of STMicroelectronics 10 MHz silicon oscillator was evaluated under exposure to extreme temperatures. The oscillator was characterized in terms of its output frequency stability, output signal rise and fall times, duty cycle, and supply current. The effects of thermal cycling and re-start capability at extreme low and high temperatures were also investigated. The silicon oscillator chip operated well with good stability in its output frequency over the temperature region of -50 C to +130 C, a range that by far exceeded its recommended specified boundaries of -20 C to +85 C. In addition, this chip, which is a low-cost oscillator designed for use in applications where great accuracy is not required, continued to function at cryogenic temperatures as low as - 195 C but at the expense of drop in its output frequency. The STCL1100 silicon oscillator was also able to re-start at both -195 C and +130 C, and it exhibited no change in performance due to the thermal cycling. In addition, no physical damage was observed in the packaging material due to extreme temperature exposure and thermal cycling. Therefore, it can be concluded that this device could potentially be used in space exploration missions under extreme temperature conditions in microprocessor and other applications where tight clock accuracy is not critical. In addition to the aforementioned screening evaluation, additional testing, however, is required to fully establish the reliability of these devices and to determine their suitability for long-term use.

Reliability Testing on the CTI-Cryogenic 1 Watt Integral Cooler (HD- 1033C/UA)

DTIC Science & Technology

1989-09-01

SUBJECT TERMS (Continue on reverse if necessary and identify by block numbe) FIELD GROUP SUB- GROUP Cryocooler, Stirling Cycle, Cryogenics 19, ABSTRCT...the Army. C2NVEO also maintains configuration management control of the forward-looking infrared (FLIR) Common Module coolers used in thermal imagers... controlled high/low temperature chamber. * A microprocessor which was programmed to automatically cycle the temperature in the chamber in accordance

Nuclear Science Symposium, 23rd, Scintillation and Semiconductor Counter Symposium, 15th, and Nuclear Power Systems Symposium, 8th, New Orleans, La., October 20-22, 1976, Proceedings

NASA Technical Reports Server (NTRS)

Wagner, L. J.

1977-01-01

The volume includes papers on semiconductor radiation detectors of various types, components of radiation detection and dosimetric systems, digital and microprocessor equipment in nuclear industry and science, and a wide variety of applications of nuclear radiation detectors. Semiconductor detectors of X-rays, gamma radiation, heavy ions, neutrons, and other nuclear particles, plastic scintillator arrays, drift chambers, spark wire chambers, and radiation dosimeter systems are reported on. Digital and analog conversion systems, digital data and control systems, microprocessors, and their uses in scientific research and nuclear power plants are discussed. Large-area imaging and biomedical nucleonic instrumentation, nuclear power plant safeguards, reactor instrumentation, nuclear power plant instrumentation, space instrumentation, and environmental instrumentation are dealt with. Individual items are announced in this issue.

Implementation of kernels on the Maestro processor

NASA Astrophysics Data System (ADS)

Suh, Jinwoo; Kang, D. I. D.; Crago, S. P.

Currently, most microprocessors use multiple cores to increase performance while limiting power usage. Some processors use not just a few cores, but tens of cores or even 100 cores. One such many-core microprocessor is the Maestro processor, which is based on Tilera's TILE64 processor. The Maestro chip is a 49-core, general-purpose, radiation-hardened processor designed for space applications. The Maestro processor, unlike the TILE64, has a floating point unit (FPU) in each core for improved floating point performance. The Maestro processor runs at 342 MHz clock frequency. On the Maestro processor, we implemented several widely used kernels: matrix multiplication, vector add, FIR filter, and FFT. We measured and analyzed the performance of these kernels. The achieved performance was up to 5.7 GFLOPS, and the speedup compared to single tile was up to 49 using 49 tiles.

Comparison of different microprocessor controlled knee joints on the energy consumption during walking in trans-femoral amputees: intelligent knee prosthesis (IP) versus C-leg.

PubMed

Chin, Takaaki; Machida, Katsuhiro; Sawamura, Seishi; Shiba, Ryouichi; Oyabu, Hiroko; Nagakura, Yuji; Takase, Izumi; Nakagawa, Akio

2006-04-01

The purpose of this study was to investigate the characteristic differences between the IP and C-Leg by making a comparative study of energy consumption and walking speeds in trans-femoral amputees. The subjects consisted of four persons with traumatic trans-femoral amputations aged 17 - 33 years who had been using the IP and were active in society. Fourteen able-bodied persons served as controls. First the energy consumption at walking speeds of 30, 50, 70, and 90 m/min was measured when using the IP. Then the knee joint was switched to the C-Leg. The same energy consumption measurement was taken once the subjects were accustomed to using the C-Leg. The most metabolically efficient walking speed was also determined. At a walking speed of 30 m/min using the IP and C-Leg, the oxygen rate (ml/kg/ min) was, on average, 42.5% and 33.3% higher (P< 0.05) than for the able-bodied group. At 50 m/min, the equivalent figures were 56.6% and 49.5% (P< 0.05), while at 70 m/min the figures were 57.8% and 51.2% (P<0.05), and at 90m/min the figures were 61.9% and 55.2% (P<0.05%). Comparing the oxygen rates for the subjects using the IP and C-Leg at walking speeds of 30 m/min and 90 m/min it was found that subjects who used C-Leg walked somewhat more efficiently than those who used IP. However, there was no significant difference between the two types at each walking speed. It was also determined that the most energy-efficient walking speed for subjects using the IP and C-Leg was the same as for the controls. Although the subjects in this study walked with comparable speed and efficiency whether they used the IP or C-Leg, the subjects' energy consumption while walking with the IP and C-Leg at normal speeds were much lower than previously reported. This study suggested that the microprocessor controlled knee joints appeared to be valid alternative for improving walking performance of trans-femoral amputees.

Atomic layer deposition (ALD): A versatile technique for plasmonics and nanobiotechnology.

PubMed

Im, Hyungsoon; Wittenberg, Nathan J; Lindquist, Nathan C; Oh, Sang-Hyun

2012-02-28

While atomic layer deposition (ALD) has been used for many years as an industrial manufacturing method for microprocessors and displays, this versatile technique is finding increased use in the emerging fields of plasmonics and nanobiotechnology. In particular, ALD coatings can modify metallic surfaces to tune their optical and plasmonic properties, to protect them against unwanted oxidation and contamination, or to create biocompatible surfaces. Furthermore, ALD is unique among thin-film deposition techniques in its ability to meet the processing demands for engineering nanoplasmonic devices, offering conformal deposition of dense and ultra-thin films on high-aspect-ratio nanostructures at temperatures below 100 °C. In this review, we present key features of ALD and describe how it could benefit future applications in plasmonics, nanosciences, and biotechnology.

A Signal Processing Algorithm Based on Multiple Microprocessors for an Underwater Acoustic Imaging System.

DTIC Science & Technology

1980-12-01

identified by the 49 4 UJ 4 4JJ 4A ww U- *i 0 tao Cv4- 50-0 trace) indicated that the bus usage was 7.9% of the loop’s execution time. The number of...1S Wc 0 4 wW 1 C, .- L 3 WQ - is = IViu4 W" L - &’aoI c O: W " Cn -- I C I0 " L =l- *. at C mW C 4 isq - is Ca W WCC .. .- C.- a .of C-( i I X0"e , Lw

ADA and multi-microprocessor real-time simulation

NASA Technical Reports Server (NTRS)

Feyock, S.; Collins, W. R.

1983-01-01

The selection of a high-order programming language for a real-time distributed network simulation is described. The additional problem of implementing a language on a possibly changing network is addressed. The recently designed language ADA (trademarked by DoD) was chosen since it provides the best model of the underlying application to be simulated.

AGARD Flight Test Instrumentation Series. Volume 18. Microprocessor Applications in Airborne Flight Test Instrumentation

DTIC Science & Technology

1987-02-01

flowcharting . 3. ProEram Codin in HLL. This stage consists of transcribing the previously designed program into R an t at can be translated into the machine...specified conditios 7. Documentation. Program documentation is necessary for user information, for maintenance, and for future applications. Flowcharts ...particular CP U. Asynchronous. Operating without reference to an overall timing source. BASIC. Beginners ’ All-purpose Symbolic Instruction Code; a widely

Smart motor technology

NASA Technical Reports Server (NTRS)

Packard, D.; Schmitt, D.

1984-01-01

Current spacecraft design relies upon microprocessor control; however, motors usually require extensive additional electronic circuitry to interface with these microprocessor controls. An improved control technique that allows a smart brushless motor to connect directly to a microprocessor control system is described. An actuator with smart motors receives a spacecraft command directly and responds in a closed loop control mode. In fact, two or more smart motors can be controlled for synchronous operation.

Microprocessor Realization of a Linear Predictive Vocoder. Appendix C. LPCM Detail Drawings and Layouts

DTIC Science & Technology

1977-02-07

CHG12 1 Dr.%VC 8 DB ILA8 DC1II 29 FTLE: FDS TAPIRWLST Al 1/19/77 16:1~2 H.I.T. LINCOLN LAB3ORATORY 1 DB116 DB16 D11G12 1 DI)V8 DD V,"R DWl 1 DBV16 DBV...5 CD27 CA27 CDC.6 CAC6 "F23 CD25 CA25 CD%.4 CAt4 IN ,7 F2’ C!ൠ CA24 CDV3 CA.^ ELI 11 CI)22 CA23 CP,2 CA,2 1D1.. CA22 CDI CA. 1 "FH𔃼 CD39 CA38 CD17...FC17 FE22 ,26 FC19 UE24 1 ’P27 FC19 F21 1 IP 29 FA V7 EF21 1 !p33* FA10 FF12" I %P32 FG𔄀 EE1 1 IP3 FG ’i^7 EF15 1 ’P 34 FGF12 Ffl2 1 1115FG ’ 1 F12

Cell cycle-dependent regulation of Aurora kinase B mRNA by the Microprocessor complex.

PubMed

Jung, Eunsun; Seong, Youngmo; Seo, Jae Hong; Kwon, Young-Soo; Song, Hoseok

2014-03-28

Aurora kinase B regulates the segregation of chromosomes and the spindle checkpoint during mitosis. In this study, we showed that the Microprocessor complex, which is responsible for the processing of the primary transcripts during the generation of microRNAs, destabilizes the mRNA of Aurora kinase B in human cells. The Microprocessor-mediated cleavage kept Aurora kinase B at a low level and prevented premature entrance into mitosis. The cleavage was reduced during mitosis leading to the accumulation of Aurora kinase B mRNA and protein. In addition to Aurora kinase B mRNA, the processing of other primary transcripts of miRNAs were also decreased during mitosis. We found that the cleavage was dependent on an RNA helicase, DDX5, and the association of DDX5 and DDX17 with the Microprocessor was reduced during mitosis. Thus, we propose a novel mechanism by which the Microprocessor complex regulates stability of Aurora kinase B mRNA and cell cycle progression. Copyright © 2014 Elsevier Inc. All rights reserved.

Gait and balance of transfemoral amputees using passive mechanical and microprocessor-controlled prosthetic knees.

PubMed

Kaufman, K R; Levine, J A; Brey, R H; Iverson, B K; McCrady, S K; Padgett, D J; Joyner, M J

2007-10-01

Microprocessor-controlled knee joints appeared on the market a decade ago. These joints are more sophisticated and more expensive than mechanical ones. The literature is contradictory regarding changes in gait and balance when using these sophisticated devices. This study employed a crossover design to assess the comparative performance of a passive mechanical knee prosthesis compared to a microprocessor-controlled knee joint in 15 subjects with an above-knee amputation. Objective measurements of gait and balance were obtained. Subjects demonstrated significantly improved gait characteristics after receiving the microprocessor-controlled prosthetic knee joint (p<0.01). Improvements in gait were a transition from a hyperextended knee to a flexed knee during loading response which resulted in a change from an internal knee flexor moment to a knee extensor moment. The participants' balance also improved (p<0.01). All conditions of the Sensory Organization Test (SOT) demonstrated improvements in equilibrium score. The composite score also increased. Transfemoral amputees using a microprocessor-controlled knee have significant improvements in gait and balance.

Functional Anatomy of the Human Microprocessor.

PubMed

Nguyen, Tuan Anh; Jo, Myung Hyun; Choi, Yeon-Gil; Park, Joha; Kwon, S Chul; Hohng, Sungchul; Kim, V Narry; Woo, Jae-Sung

2015-06-04

MicroRNA (miRNA) maturation is initiated by Microprocessor composed of RNase III DROSHA and its cofactor DGCR8, whose fidelity is critical for generation of functional miRNAs. To understand how Microprocessor recognizes pri-miRNAs, we here reconstitute human Microprocessor with purified recombinant proteins. We find that Microprocessor is an ∼364 kDa heterotrimeric complex of one DROSHA and two DGCR8 molecules. Together with a 23-amino acid peptide from DGCR8, DROSHA constitutes a minimal functional core. DROSHA serves as a "ruler" by measuring 11 bp from the basal ssRNA-dsRNA junction. DGCR8 interacts with the stem and apical elements through its dsRNA-binding domains and RNA-binding heme domain, respectively, allowing efficient and accurate processing. DROSHA and DGCR8, respectively, recognize the basal UG and apical UGU motifs, which ensure proper orientation of the complex. These findings clarify controversies over the action mechanism of DROSHA and allow us to build a general model for pri-miRNA processing. Copyright © 2015 Elsevier Inc. All rights reserved.

Data and results of a laboratory investigation of microprocessor upset caused by simulated lightning-induced analog transients

NASA Technical Reports Server (NTRS)

Belcastro, C. M.

1984-01-01

A methodology was developed a assess the upset susceptibility/reliability of a computer system onboard an aircraft flying through a lightning environment. Upset error modes in a general purpose microprocessor were studied. The upset tests involved the random input of analog transients which model lightning induced signals onto interface lines of an 8080 based microcomputer from which upset error data was recorded. The program code on the microprocessor during tests is designed to exercise all of the machine cycles and memory addressing techniques implemented in the 8080 central processing unit. A statistical analysis is presented in which possible correlations are established between the probability of upset occurrence and transient signal inputs during specific processing states and operations. A stochastic upset susceptibility model for the 8080 microprocessor is presented. The susceptibility of this microprocessor to upset, once analog transients have entered the system, is determined analytically by calculating the state probabilities of the stochastic model.

A Report of Bethune-Cookman College NASA JOVE Projects

NASA Technical Reports Server (NTRS)

Agba, Lawrence C.; David, Sunil K.; Rao, Narsing G.; Rahmani, Munir A.

1997-01-01

This document is the final report for the Joint Venture (JOVE) in Space Sciences, and describes the tasks, performed with the support of the contract. These tasks include work in: (1) interfacing microprocessor systems to high performance parallel interface chips, SCSI drive and memory, needed for the implementation of a Space Optical Data Recorder; (2) designing a digital interface architecture for a microprocessor controlled sensors monitoring unit for a NASA Jitter Attenuation and Dynamics Experiment (JADE) project; (3) developing an enhanced back-propagation training algorithm; (4) studying the effect of simulated spaceflight on Aortic Contractility; (5) developing a course in astronomy; and (6) improving internet access by running cables, and installing hubs in various places on the campus; and (7) researching the characteristics of Nd:YALO laser resonator.

Design and Demonstration of a 30 GHz 16-bit Superconductor RSFQ Microprocessor

DTIC Science & Technology

2015-03-10

for Public Release; Distribution Unlimited Final Report: Design and Demonstration of a 30 GHz 16-bit Superconductor RSFQ Microprocessor The views...P.O. Box 12211 Research Triangle Park, NC 27709-2211 Superconductor technology, RSFQ, RQL, processor design, arithmetic units, high-performance...Demonstration of a 30 GHz 16-bit Superconductor RSFQ Microprocessor Report Title The major objective of the project was to design and demonstrate operation

Pain and efficacy rating of a microprocessor-controlled metered injection system for local anaesthesia in minor hand surgery.

PubMed

Nimigan, André S; Gan, Bing Siang

2011-01-01

Purpose. Little attention has been given to syringe design and local anaesthetic administration methods. A microprocessor-controlled anaesthetic delivery device has become available that may minimize discomfort during injection. The purpose of this study was to document the pain experience associated with the use of this system and to compare it with use of a conventional syringe. Methods. A prospective, randomized clinical trial was designed. 40 patients undergoing carpal tunnel release were block randomized according to sex into a two groups: a traditional syringe group and a microprocessor-controlled device group. The primary outcome measure was surgical pain and local anaesthetic administration pain. Secondary outcomes included volume of anaesthetic used and injection time. Results. Analysis showed that equivalent anaesthesia was achieved in the microprocessor-controlled group despite using a significantly lower volume of local anaesthetic (P = .0002). This same group, however, has significantly longer injection times (P < .0001). Pain during the injection process or during surgery was not different between the two groups. Conclusions. This RCT comparing traditional and microprocessor controlled methods of administering local anaesthetic showed similar levels of discomfort in both groups. While the microprocessor-controlled group used less volume, the total time for the administration was significantly greater.

Energy expenditure and activity of transfemoral amputees using mechanical and microprocessor-controlled prosthetic knees.

PubMed

Kaufman, Kenton R; Levine, James A; Brey, Robert H; McCrady, Shelly K; Padgett, Denny J; Joyner, Michael J

2008-07-01

To quantify the energy efficiency of locomotion and free-living physical activity energy expenditure of transfemoral amputees using a mechanical and microprocessor-controlled prosthetic knee. Repeated-measures design to evaluate comparative functional outcomes. Exercise physiology laboratory and community free-living environment. Subjects (N=15; 12 men, 3 women; age, 42+/-9 y; range, 26-57 y) with transfemoral amputation. Research participants were long-term users of a mechanical prosthesis (20+/-10 y as an amputee; range, 3-36 y). They were fitted with a microprocessor-controlled knee prosthesis and allowed to acclimate (mean time, 18+/-8 wk) before being retested. Objective measurements of energy efficiency and total daily energy expenditure were obtained. The Prosthetic Evaluation Questionnaire was used to gather subjective feedback from the participants. Subjects demonstrated significantly increased physical activity-related energy expenditure levels in the participant's free-living environment (P=.04) after wearing the microprocessor-controlled prosthetic knee joint. There was no significant difference in the energy efficiency of walking (P=.34). When using the microprocessor-controlled knee, the subjects expressed increased satisfaction in their daily lives (P=.02). People ambulating with a microprocessor-controlled knee significantly increased their physical activity during daily life, outside the laboratory setting, and expressed an increased quality of life.

Functional added value of microprocessor-controlled knee joints in daily life performance of Medicare Functional Classification Level-2 amputees.

PubMed

Theeven, Patrick; Hemmen, Bea; Rings, Frans; Meys, Guido; Brink, Peter; Smeets, Rob; Seelen, Henk

2011-10-01

To assess the effects of using a microprocessor-controlled prosthetic knee joint on the functional performance of activities of daily living in persons with an above-knee leg amputation. To assess the effects of using a microprocessor-controlled prosthetic knee joint on the functional performance of activities of daily living in persons with an above-knee leg amputation. Randomised cross-over trial. Forty-one persons with unilateral above-knee or knee disarticulation limb loss, classified as Medicare Functional Classification Level-2 (MFCL-2). Participants were measured in 3 conditions, i.e. using a mechanically controlled knee joint and two types of microprocessor-controlled prosthetic knee joints. Functional performance level was assessed using a test in which participants performed 17 simulated activities of daily living (Assessment of Daily Activity Performance in Transfemoral amputees test). Performance time was measured and self-perceived level of difficulty was scored on a visual analogue scale for each activity. High levels of within-group variability in functional performance obscured detection of any effects of using a microprocessor-controlled prosthetic knee joint. Data analysis after stratification of the participants into 3 subgroups, i.e. participants with a "low", "intermediate" and "high" functional mobility level, showed that the two higher functional subgroups performed significantly faster using microprocessor-controlled prosthetic knee joints. MFCL-2 amputees constitute a heterogeneous patient group with large variation in functional performance levels. A substantial part of this group seems to benefit from using a microprocessor-controlled prosthetic knee joint when performing activities of daily living.

Interfacing Optical Document Scanners: Principles and Practical Considerations.

ERIC Educational Resources Information Center

Krus, David J.; Kodimer, Dennis

1987-01-01

Handlers for interfacing the ScanTron and 2700 Optical Mark Readers with the IBM AT/XT/PC and Tandy 2000/1000/3000 iAPX 88/186/286 based computers were described. Differences between programing an RS232C serial port using BIOS interrupts and directly addressing the Motorola 8550 ART microprocessor were discussed. (Author/LMO)

Regulation of Plant Microprocessor Function in Shaping microRNA Landscape.

PubMed

Dolata, Jakub; Taube, Michał; Bajczyk, Mateusz; Jarmolowski, Artur; Szweykowska-Kulinska, Zofia; Bielewicz, Dawid

2018-01-01

MicroRNAs are small molecules (∼21 nucleotides long) that are key regulators of gene expression. They originate from long stem-loop RNAs as a product of cleavage by a protein complex called Microprocessor. The core components of the plant Microprocessor are the RNase type III enzyme Dicer-Like 1 (DCL1), the zinc finger protein Serrate (SE), and the double-stranded RNA binding protein Hyponastic Leaves 1 (HYL1). Microprocessor assembly and its processing of microRNA precursors have been reported to occur in discrete nuclear bodies called Dicing bodies. The accessibility of and modifications to Microprocessor components affect microRNA levels and may have dramatic consequences in plant development. Currently, numerous lines of evidence indicate that plant Microprocessor activity is tightly regulated. The cellular localization of HYL1 is dependent on a specific KETCH1 importin, and the E3 ubiquitin ligase COP1 indirectly protects HYL1 from degradation in a light-dependent manner. Furthermore, proper localization of HYL1 in Dicing bodies is regulated by MOS2. On the other hand, the Dicing body localization of DCL1 is regulated by NOT2b, which also interacts with SE in the nucleus. Post-translational modifications are substantial factors that contribute to protein functional diversity and provide a fine-tuning system for the regulation of protein activity. The phosphorylation status of HYL1 is crucial for its activity/stability and is a result of the interplay between kinases (MPK3 and SnRK2) and phosphatases (CPL1 and PP4). Additionally, MPK3 and SnRK2 are known to phosphorylate SE. Several other proteins (e.g., TGH, CDF2, SIC, and RCF3) that interact with Microprocessor have been found to influence its RNA-binding and processing activities. In this minireview, recent findings on the various modes of Microprocessor activity regulation are discussed.

Regulation of Plant Microprocessor Function in Shaping microRNA Landscape

PubMed Central

Dolata, Jakub; Taube, Michał; Bajczyk, Mateusz; Jarmolowski, Artur; Szweykowska-Kulinska, Zofia; Bielewicz, Dawid

2018-01-01

MicroRNAs are small molecules (∼21 nucleotides long) that are key regulators of gene expression. They originate from long stem–loop RNAs as a product of cleavage by a protein complex called Microprocessor. The core components of the plant Microprocessor are the RNase type III enzyme Dicer-Like 1 (DCL1), the zinc finger protein Serrate (SE), and the double-stranded RNA binding protein Hyponastic Leaves 1 (HYL1). Microprocessor assembly and its processing of microRNA precursors have been reported to occur in discrete nuclear bodies called Dicing bodies. The accessibility of and modifications to Microprocessor components affect microRNA levels and may have dramatic consequences in plant development. Currently, numerous lines of evidence indicate that plant Microprocessor activity is tightly regulated. The cellular localization of HYL1 is dependent on a specific KETCH1 importin, and the E3 ubiquitin ligase COP1 indirectly protects HYL1 from degradation in a light-dependent manner. Furthermore, proper localization of HYL1 in Dicing bodies is regulated by MOS2. On the other hand, the Dicing body localization of DCL1 is regulated by NOT2b, which also interacts with SE in the nucleus. Post-translational modifications are substantial factors that contribute to protein functional diversity and provide a fine-tuning system for the regulation of protein activity. The phosphorylation status of HYL1 is crucial for its activity/stability and is a result of the interplay between kinases (MPK3 and SnRK2) and phosphatases (CPL1 and PP4). Additionally, MPK3 and SnRK2 are known to phosphorylate SE. Several other proteins (e.g., TGH, CDF2, SIC, and RCF3) that interact with Microprocessor have been found to influence its RNA-binding and processing activities. In this minireview, recent findings on the various modes of Microprocessor activity regulation are discussed. PMID:29922322

The application of charge-coupled device processors in automatic-control systems

NASA Technical Reports Server (NTRS)

Mcvey, E. S.; Parrish, E. A., Jr.

1977-01-01

The application of charge-coupled device (CCD) processors to automatic-control systems is suggested. CCD processors are a new form of semiconductor component with the unique ability to process sampled signals on an analog basis. Specific implementations of controllers are suggested for linear time-invariant, time-varying, and nonlinear systems. Typical processing time should be only a few microseconds. This form of technology may become competitive with microprocessors and minicomputers in addition to supplementing them.

Integrated Chemical Fuel Microprocessor for Power Generation in MEMS Applications

DTIC Science & Technology

2005-07-01

unreacted fuels (ammonia and hydrocarbon) and carbon monoxide that could otherwise adversely affect hydrogen Proton Exchange Membrane ( PEM ) fuel cell ...High hydrogen purity is required in a variety of processes, from the microelectronics industry to PEM fuel cells . For portable-power applications, it...Geff Ffuel Heat Load Complexity Li-Ion Batteries 330 140 1.2 W Low Carnot Engines *7,878 13,750 10% 50% 395 690 10 W Low Fuel Cells : PEM /Hydride #2,382

Dynamically Reconfigurable Systolic Array Accelorators

NASA Technical Reports Server (NTRS)

Dasu, Aravind (Inventor); Barnes, Robert C. (Inventor)

2014-01-01

A polymorphic systolic array framework that works in conjunction with an embedded microprocessor on an FPGA, that allows for dynamic and complimentary scaling of acceleration levels of two algorithms active concurrently on the FPGA. Use is made of systolic arrays and hardware-software co-design to obtain an efficient multi-application acceleration system. The flexible and simple framework allows hosting of a broader range of algorithms and extendable to more complex applications in the area of aerospace embedded systems.

Expression levels of the microRNA maturing microprocessor complex component DGCR8 and the RNA-induced silencing complex (RISC) components argonaute-1, argonaute-2, PACT, TARBP1, and TARBP2 in epithelial skin cancer.

PubMed

Sand, Michael; Skrygan, Marina; Georgas, Dimitrios; Arenz, Christoph; Gambichler, Thilo; Sand, Daniel; Altmeyer, Peter; Bechara, Falk G

2012-11-01

The microprocessor complex mediates intranuclear biogenesis of precursor microRNAs from the primary microRNA transcript. Extranuclear, mature microRNAs are incorporated into the RNA-induced silencing complex (RISC) before interaction with complementary target mRNA leads to transcriptional repression or cleavage. In this study, we investigated the expression profiles of the microprocessor complex subunit DiGeorge syndrome critical region gene 8 (DGCR8) and the RISC components argonaute-1 (AGO1), argonaute-2 (AGO2), as well as double-stranded RNA-binding proteins PACT, TARBP1, and TARBP2 in epithelial skin cancer and its premalignant stage. Patients with premalignant actinic keratoses (AK, n = 6), basal cell carcinomas (BCC, n = 15), and squamous cell carcinomas (SCC, n = 7) were included in the study. Punch biopsies were harvested from the center of the tumors (lesional), from healthy skin sites (intraindividual controls), and from healthy skin sites in a healthy control group (n = 16; interindividual control). The DGCR8, AGO1, AGO2, PACT, TARBP1, and TARBP2 mRNA expression levels were detected by quantitative real-time reverse transcriptase polymerase chain reaction. The DGCR8, AGO1, AGO2, PACT, and TARBP1 expression levels were significantly higher in the AK, BCC, and SCC groups than the healthy controls (P < 0.05). There was no significant difference in the TARBP2 expression levels between groups (P > 0.05). This study indicates that major components of the miRNA pathway, such as the microprocessor complex and RISC, are dysregulated in epithelial skin cancer. Copyright © 2011 Wiley Periodicals, Inc.

Safety and function of a prototype microprocessor-controlled knee prosthesis for low active transfemoral amputees switching from a mechanic knee prosthesis: a pilot study.

PubMed

Hasenoehrl, Timothy; Schmalz, Thomas; Windhager, Reinhard; Domayer, Stephan; Dana, Sara; Ambrozy, Clemens; Palma, Stefano; Crevenna, Richard

2018-02-01

Aim of this pilot study was to assess safety and functioning of a microprocessor-controlled knee prosthesis (MPK) after a short familiarization time and no structured physical therapy. Five elderly, low-active transfemoral amputees who were fitted with a standard non-microprocessor controlled knee prosthesis (NMPK) performed a baseline measurement consisting of a 3 D gait analysis, functional tests and questionnaires. The first follow-up consisted of the same test procedure and was performed with the MPK after 4 to 6 weeks of familiarization. After being refitted to their standard NMPK again, the subjects undertook the second follow-up which consisted of solely questionnaires 4 weeks later. Questionnaires and functional tests showed an increase in the perception of safety. Moreover, gait analysis revealed more physiologic knee and hip extension/flexion patterns when using the MPK. Our results showed that although the Genium with Cenior-Leg ruleset-MPK (GCL-MPK) might help to improve several safety-related outcomes as well as gait biomechanics the functional potential of the GCL-MPK may have been limited without specific training and a sufficient acclimation period. Implications for Rehabilitation Elderly transfemoral amputees are often limited in their activity by safety issues as well as insufficient functioning regarding the non microprocessor-controlled knee prostheses (NMPK), thing that could be eliminated with the use of suitable microprocessor-controlled prostheses (MPK). The safety and functioning of a prototype MPK (GCL-MPK) specifically designed for the needs of older and low-active transfemoral amputees was assessed in this pilot study. The GCL-MPK showed indicators of increased safety and more natural walking patterns in older and low-active transfemoral amputees in comparison to the standard NMPK already after a short acclimatisation time and no structured physical therapy. Regarding functional performance it seems as if providing older and low-active transfemoral amputees with the GCL-MPK alone without prescribing structured prosthesis training might be insufficient to achieve improvements over the standard NMPKs.

The Effect of a Microprocessor Prosthetic Foot on Function and Quality of Life in Transtibial Amputees Who Are Limited Community Ambulators

DTIC Science & Technology

2017-09-01

parallel, randomized, controlled clinical trial designed to determine if a microprocessor controlled prosthetic foot (MPF), with greater range of...clinical trial designed to determine if a microprocessor controlled prosthetic foot (MPF), with greater range of motion and active power, will...Department of the Army position, policy or decision unless so designated by other documentation. CONTRACTING ORGANIZATION: University of Tennessee

Formal proof of the AVM-1 microprocessor using the concept of generic interpreters

NASA Technical Reports Server (NTRS)

Windley, P.; Levitt, K.; Cohen, G. C.

1991-01-01

A microprocessor designated AVM-1 was designed to demonstrate the use of generic interpreters in verifying hierarchically decomposed microprocessor specifications. This report is intended to document the high-order language (HOL) code verifying AVM-1. The organization of the proof is discussed and some technical details concerning the execution of the proof scripts in HOL are presented. The proof scripts used to verify AVM-1 are also presented.

The design of a microprocessor-based data logger

USGS Publications Warehouse

Leap, K.J.; Dedini, L.A.

1982-01-01

The design of a microprocessor-based data logger, which collects and digitizes analog voltage signals from a continuous-measuring instrumentation system and transmits serial data to a magnetic tape recorder, is discussed. The data logger was assembled from commercially-available components and can be user-programmed for greater flexibility. A description of the data logger hardware and software designs, general operating instructions, the microprocessor program listing, and electrical schematic diagrams are presented.

Hardware-Enabled Security Through On-Chip Reconfigurable Fabric

DTIC Science & Technology

2016-02-05

SECURITY CLASSIFICATION OF: The goal of this project was to enable hardware-based security techniques on future microprocessors in a way that they... microprocessors in a way that they can be added and updated after fabrication, similar to software, while maintaining the efficiency and the security of...Progress The goal of this project was to enable hardware-based security techniques on future microprocessors in a way that they can be added and

Automated mixed traffic transit vehicle microprocessor controller

NASA Technical Reports Server (NTRS)

Marks, R. A.; Cassell, P.; Johnston, A. R.

1981-01-01

An improved Automated Mixed Traffic Vehicle (AMTV) speed control system employing a microprocessor and transistor chopper motor current controller is described and its performance is presented in terms of velocity versus time curves. The on board computer hardware and software systems are described as is the software development system. All of the programming used in this controller was implemented using FORTRAN. This microprocessor controller made possible a number of safety features and improved the comfort associated with starting and shopping. In addition, most of the vehicle's performance characteristics can be altered by simple program parameter changes. A failure analysis of the microprocessor controller was generated and the results are included. Flow diagrams for the speed control algorithms and complete FORTRAN code listings are also included.

Mold heating and cooling microprocessor conversion. Final report

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hoffman, D.P.

Conversion of the microprocessors and software for the Mold Heating and Cooling (MHAC) pump package control systems was initiated to allow required system enhancements and provide data communications capabilities with the Plastics Information and Control System (PICS). The existing microprocessor-based control systems for the pump packages use an Intel 8088-based microprocessor board with a maximum of 64 Kbytes of program memory. The requirements for the system conversion were developed, and hardware has been selected to allow maximum reuse of existing hardware and software while providing the required additional capabilities and capacity. The new hardware will incorporate an Intel 80286-based microprocessormore » board with an 80287 math coprocessor, the system includes additional memory, I/O, and RS232 communication ports.« less

Technological trends in automobiles.

PubMed

Horton, E J; Compton, W D

1984-08-10

Current technological trends in the automotive industry reflect many diverse disciplines. Electronics and microprocessors, new engine transmission concepts, composite and ceramic materials, and computer-aided design and manufacture will combine to make possible the creation of advanced automobiles offering outstanding quality, fuel economy, and performance. A projected "average" vehicle of the 1990's is described to illustrate the application of these new concepts.

A Particulate Matter

NASA Technical Reports Server (NTRS)

1999-01-01

Technical Applications Unlimited, through a contract with Kennedy Space Center, developed the an activity sensor, called the TAU- N100A, which includes a microprocessor-controlled module that detects a particular on a sensor surface and converts this information into digital data. Its original purpose for development was to detect the accumulation of potentially damaging dust and fibers on sensitive payload components.

Rad-hard computer elements for space applications

NASA Technical Reports Server (NTRS)

Krishnan, G. S.; Longerot, Carl D.; Treece, R. Keith

1993-01-01

Space Hardened CMOS computer elements emulating a commercial microcontroller and microprocessor family have been designed, fabricated, qualified, and delivered for a variety of space programs including NASA's multiple launch International Solar-Terrestrial Physics (ISTP) program, Mars Observer, and government and commercial communication satellites. Design techniques and radiation performance of the 1.25 micron feature size products are described.

On-board landmark navigation and attitude reference parallel processor system

NASA Technical Reports Server (NTRS)

Gilbert, L. E.; Mahajan, D. T.

1978-01-01

An approach to autonomous navigation and attitude reference for earth observing spacecraft is described along with the landmark identification technique based on a sequential similarity detection algorithm (SSDA). Laboratory experiments undertaken to determine if better than one pixel accuracy in registration can be achieved consistent with onboard processor timing and capacity constraints are included. The SSDA is implemented using a multi-microprocessor system including synchronization logic and chip library. The data is processed in parallel stages, effectively reducing the time to match the small known image within a larger image as seen by the onboard image system. Shared memory is incorporated in the system to help communicate intermediate results among microprocessors. The functions include finding mean values and summation of absolute differences over the image search area. The hardware is a low power, compact unit suitable to onboard application with the flexibility to provide for different parameters depending upon the environment.

Electron lithography STAR design guidelines. Part 3: The mosaic transistor array applied to custom microprocessors. Part 4: Stores logic arrays, SLAs implemented with clocked CMOS

NASA Technical Reports Server (NTRS)

Trotter, J. D.

1982-01-01

The Mosaic Transistor Array is an extension of the STAR system developed by NASA which has dedicated field cells designed to be specifically used in semicustom microprocessor applications. The Sandia radiation hard bulk CMOS process is utilized in order to satisfy the requirements of space flights. A design philosophy is developed which utilizes the strengths and recognizes the weaknesses of the Sandia process. A style of circuitry is developed which incorporates the low power and high drive capability of CMOS. In addition the density achieved is better than that for classic CMOS, although not as good as for NMOS. The basic logic functions for a data path are designed with compatible interface to the STAR grid system. In this manner either random logic or PLA type structures can be utilized for the control logic.

Data and results of a laboratory investigation of microprocessor upset caused by simulated lightning-induced analog transients

NASA Technical Reports Server (NTRS)

Belcastro, C. M.

1984-01-01

Advanced composite aircraft designs include fault-tolerant computer-based digital control systems with thigh reliability requirements for adverse as well as optimum operating environments. Since aircraft penetrate intense electromagnetic fields during thunderstorms, onboard computer systems maya be subjected to field-induced transient voltages and currents resulting in functional error modes which are collectively referred to as digital system upset. A methodology was developed for assessing the upset susceptibility of a computer system onboard an aircraft flying through a lightning environment. Upset error modes in a general-purpose microprocessor were studied via tests which involved the random input of analog transients which model lightning-induced signals onto interface lines of an 8080-based microcomputer from which upset error data were recorded. The application of Markov modeling to upset susceptibility estimation is discussed and a stochastic model development.

A real time, FEM based optimal control algorithm and its implementation using parallel processing hardware (transistors) in a microprocessor environment

NASA Technical Reports Server (NTRS)

Patten, William Neff

1989-01-01

There is an evident need to discover a means of establishing reliable, implementable controls for systems that are plagued by nonlinear and, or uncertain, model dynamics. The development of a generic controller design tool for tough-to-control systems is reported. The method utilizes a moving grid, time infinite element based solution of the necessary conditions that describe an optimal controller for a system. The technique produces a discrete feedback controller. Real time laboratory experiments are now being conducted to demonstrate the viability of the method. The algorithm that results is being implemented in a microprocessor environment. Critical computational tasks are accomplished using a low cost, on-board, multiprocessor (INMOS T800 Transputers) and parallel processing. Progress to date validates the methodology presented. Applications of the technique to the control of highly flexible robotic appendages are suggested.

Using a Cray Y-MP as an array processor for a RISC Workstation

NASA Technical Reports Server (NTRS)

Lamaster, Hugh; Rogallo, Sarah J.

1992-01-01

As microprocessors increase in power, the economics of centralized computing has changed dramatically. At the beginning of the 1980's, mainframes and super computers were often considered to be cost-effective machines for scalar computing. Today, microprocessor-based RISC (reduced-instruction-set computer) systems have displaced many uses of mainframes and supercomputers. Supercomputers are still cost competitive when processing jobs that require both large memory size and high memory bandwidth. One such application is array processing. Certain numerical operations are appropriate to use in a Remote Procedure Call (RPC)-based environment. Matrix multiplication is an example of an operation that can have a sufficient number of arithmetic operations to amortize the cost of an RPC call. An experiment which demonstrates that matrix multiplication can be executed remotely on a large system to speed the execution over that experienced on a workstation is described.

76 FR 323 - Information Systems Technical Advisory Committee; Notice of Partially Closed Meeting

Federal Register 2010, 2011, 2012, 2013, 2014

2011-01-04

...), Building 33, Cloud Room, 53560 Hull Street, San Diego, California 92152. The Committee advises the Office... and Relation to Category 3 5. Godson Microprocessor Project 6. Autonomous Vehicle Project 7. Cloud Computing, Technology and Security Issues Thursday, January 27 Closed Session 8. Discussion of matters...

49 CFR 661.7 - Waivers.

Code of Federal Regulations, 2013 CFR

2013-10-01

... requirements applies to microprocessors, computers, microcomputers, or software, or other such devices, which... a product or device which merely contains a microprocessor or microcomputer and is not used solely...

49 CFR 661.7 - Waivers.

Code of Federal Regulations, 2012 CFR

2012-10-01

... requirements applies to microprocessors, computers, microcomputers, or software, or other such devices, which... a product or device which merely contains a microprocessor or microcomputer and is not used solely...

49 CFR 661.7 - Waivers.

Code of Federal Regulations, 2011 CFR

2011-10-01

... requirements applies to microprocessors, computers, microcomputers, or software, or other such devices, which... a product or device which merely contains a microprocessor or microcomputer and is not used solely...

49 CFR 661.7 - Waivers.

Code of Federal Regulations, 2010 CFR

2010-10-01

... requirements applies to microprocessors, computers, microcomputers, or software, or other such devices, which... a product or device which merely contains a microprocessor or microcomputer and is not used solely...

49 CFR 661.7 - Waivers.

Code of Federal Regulations, 2014 CFR

2014-10-01

... requirements applies to microprocessors, computers, microcomputers, or software, or other such devices, which... a product or device which merely contains a microprocessor or microcomputer and is not used solely...

The comparison of transfemoral amputees using mechanical and microprocessor- controlled prosthetic knee under different walking speeds: A randomized cross-over trial.

PubMed

Cao, Wujing; Yu, Hongliu; Zhao, Weiliang; Meng, Qiaoling; Chen, Wenming

2018-04-20

The microprocessor-controlled prosthetic knees have been introduced to transfemoral amputees due to advances in biomedical engineering. A body of scientific literature has shown that the microprocessor-controlled prosthetic knees improve the gait and functional abilities of persons with transfemoral amputation. The aim of this study was to propose a new microprocessor-controlled prosthetic knee (MPK) and compare it with non-microprocessor-controlled prosthetic knees (NMPKs) under different walking speeds. The microprocessor-controlled prosthetic knee (i-KNEE) with hydraulic damper was developed. The comfortable self-selected walking speeds of 12 subjects with i-KNEE and NMPK were obtained. The maximum swing flexion knee angle and gait symmetry were compared in i-KNEE and NMPK condition. The comfortable self-selected walking speeds of some subjects were higher with i-KNEE while some were not. There was no significant difference in comfortable self-selected walking speed between the i-KNEE and the NMPK condition (P= 0.138). The peak prosthetic knee flexion during swing in the i-KNEE condition was between sixty and seventy degree under any walking speed. In the NMPK condition, the maximum swing flexion knee angle changed significantly. And it increased with walking speed. There is no significant difference in knee kinematic symmetry when the subjects wear the i-KNEE or NMPK. The results of this study indicated that the new microprocessor-controlled prosthetic knee was suitable for transfemoral amputees. The maximum swing flexion knee angle under different walking speeds showed different properties in the NMPK and i-KNEE condition. The i-KNEE was more adaptive to speed changes. There was little difference of comfortable self-selected walking speed between i-KNEE and NMPK condition.

Microprocessor based implementation of attitude and shape control of large space structures

NASA Technical Reports Server (NTRS)

Reddy, A. S. S. R.

1984-01-01

The feasibility of off the shelf eight bit and 16 bit microprocessors to implement linear state variable feedback control laws and assessing the real time response to spacecraft dynamics is studied. The complexity of the dynamic model is described along with the appropriate software. An experimental setup of a beam, microprocessor system for implementing the control laws and the needed generalized software to implement any state variable feedback control system is included.

Global identification of target recognition and cleavage by the Microprocessor in human ES cells

PubMed Central

Seong, Youngmo; Lim, Do-Hwan; Kim, Augustine; Seo, Jae Hong; Lee, Young Sik; Song, Hoseok; Kwon, Young-Soo

2014-01-01

The Microprocessor plays an essential role in canonical miRNA biogenesis by facilitating cleavage of stem-loop structures in primary transcripts to yield pre-miRNAs. Although miRNA biogenesis has been extensively studied through biochemical and molecular genetic approaches, it has yet to be addressed to what extent the current miRNA biogenesis models hold true in intact cells. To address the issues of in vivo recognition and cleavage by the Microprocessor, we investigate RNAs that are associated with DGCR8 and Drosha by using immunoprecipitation coupled with next-generation sequencing. Here, we present global protein–RNA interactions with unprecedented sensitivity and specificity. Our data indicate that precursors of canonical miRNAs and miRNA-like hairpins are the major substrates of the Microprocessor. As a result of specific enrichment of nascent cleavage products, we are able to pinpoint the Microprocessor-mediated cleavage sites per se at single-nucleotide resolution. Unexpectedly, a 2-nt 3′ overhang invariably exists at the ends of cleaved bases instead of nascent pre-miRNAs. Besides canonical miRNA precursors, we find that two novel miRNA-like structures embedded in mRNAs are cleaved to yield pre-miRNA-like hairpins, uncoupled from miRNA maturation. Our data provide a framework for in vivo Microprocessor-mediated cleavage and a foundation for experimental and computational studies on miRNA biogenesis in living cells. PMID:25326327

Energy Expenditure and Activity of Transfemoral Amputees Using Mechanical and Microprocessor-Controlled Prosthetic Knees

PubMed Central

Kaufman, Kenton R.; Levine, James A.; Brey, Robert H.; McCrady, Shelly K.; Padgett, Denny J.; Joyner, Michael J.

2009-01-01

Objective To quantify the energy efficiency of locomotion and free-living physical activity energy expenditure of transfemoral amputees using a mechanical and microprocessor-controlled prosthetic knee. Design Repeated-measures design to evaluate comparative functional outcomes. Setting Exercise physiology laboratory and community free-living environment. Participants Subjects (N=15; 12 men, 3 women; age, 42±9y; range, 26 –57y) with transfemoral amputation. Intervention Research participants were long-term users of a mechanical prosthesis (20±10y as an amputee; range, 3–36y). They were fitted with a microprocessor-controlled knee prosthesis and allowed to acclimate (mean time, 18±8wk) before being retested. Main Outcome Measures Objective measurements of energy efficiency and total daily energy expenditure were obtained. The Prosthetic Evaluation Questionnaire was used to gather subjective feedback from the participants. Results Subjects demonstrated significantly increased physical activity–related energy expenditure levels in the participant’s free-living environment (P=.04) after wearing the microprocessor-controlled prosthetic knee joint. There was no significant difference in the energy efficiency of walking (P=.34). When using the microprocessor-controlled knee, the subjects expressed increased satisfaction in their daily lives (P=.02). Conclusions People ambulating with a microprocessor-controlled knee significantly increased their physical activity during daily life, outside the laboratory setting, and expressed an increased quality of life. PMID:18586142

Robust Duplication with Comparison Methods in Microcontrollers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Quinn, Heather Marie; Baker, Zachary Kent; Fairbanks, Thomas D.

Commercial microprocessors could be useful computational platforms in space systems, as long as the risk is bound. Many spacecraft are computationally constrained because all of the computation is done on a single radiation-hardened microprocessor. It is possible that a commercial microprocessor could be used for configuration, monitoring and background tasks that are not mission critical. Most commercial microprocessors are affected by radiation, including single-event effects (SEEs) that could be destructive to the component or corrupt the data. Part screening can help designers avoid components with destructive failure modes, and mitigation can suppress data corruption. We have been experimenting with amore » method for masking radiation-induced faults through the software executing on the microprocessor. While triple-modular redundancy (TMR) techniques are very effective at masking faults in software, the increased amount of execution time to complete the computation is not desirable. Here in this article we present a technique for combining duplication with compare (DWC) with TMR that decreases observable errors by as much as 145 times with only a 2.35 time decrease in performance.« less

Robust Duplication with Comparison Methods in Microcontrollers

DOE PAGES

Quinn, Heather Marie; Baker, Zachary Kent; Fairbanks, Thomas D.; ...

2016-01-01

Commercial microprocessors could be useful computational platforms in space systems, as long as the risk is bound. Many spacecraft are computationally constrained because all of the computation is done on a single radiation-hardened microprocessor. It is possible that a commercial microprocessor could be used for configuration, monitoring and background tasks that are not mission critical. Most commercial microprocessors are affected by radiation, including single-event effects (SEEs) that could be destructive to the component or corrupt the data. Part screening can help designers avoid components with destructive failure modes, and mitigation can suppress data corruption. We have been experimenting with amore » method for masking radiation-induced faults through the software executing on the microprocessor. While triple-modular redundancy (TMR) techniques are very effective at masking faults in software, the increased amount of execution time to complete the computation is not desirable. Here in this article we present a technique for combining duplication with compare (DWC) with TMR that decreases observable errors by as much as 145 times with only a 2.35 time decrease in performance.« less

Full autonomous microline trace robot

NASA Astrophysics Data System (ADS)

Yi, Deer; Lu, Si; Yan, Yingbai; Jin, Guofan

2000-10-01

Optoelectric inspection may find applications in robotic system. In micro robotic system, smaller optoelectric inspection system is preferred. However, as miniaturizing the size of the robot, the number of the optoelectric detector becomes lack. And lack of the information makes the micro robot difficult to acquire its status. In our lab, a micro line trace robot has been designed, which autonomous acts based on its optoelectric detection. It has been programmed to follow a black line printed on the white colored ground. Besides the optoelectric inspection, logical algorithm in the microprocessor is also important. In this paper, we propose a simply logical algorithm to realize robot's intelligence. The robot's intelligence is based on a AT89C2051 microcontroller which controls its movement. The technical details of the micro robot are as follow: dimension: 30mm*25mm*35*mm; velocity: 60mm/s.

49 CFR 229.27 - Annual tests.

Code of Federal Regulations, 2011 CFR

2011-10-01

... DMU locomotive or an MU locomotive, equipped with a microprocessor-based event recorder that includes...) A microprocessor-based event recorder with a self-monitoring feature equipped to verify that all...

Microprocessor utilization in search and rescue missions

NASA Technical Reports Server (NTRS)

Schwartz, M.; Bashkow, T.

1978-01-01

The position of an emergency transmitter may be determined by measuring the Doppler shift of the distress signal as received by an orbiting satellite. This requires the computation of an initial estimate and refinement of this estimate through an iterative, nonlinear, least squares estimation. A version of the algorithm was implemented and tested by locating a transmitter on the premises and obtaining observations from a satellite. The computer used was an IBM 360/95. The position was determined within the desired 10 km radius accuracy. The feasibility of performing the same task in real time using microprocessor technology, was determined. The least squares algorithm was implemented on an Intel 8080 microprocessor. The results indicate that a microprocessor can easily match the IBM implementation in accuracy and be performed inside the time limitations set.

[The development of an intelligent four-channel aggregometer].

PubMed

Guan, X; Wang, M

1998-07-01

The paper introduces the hardware and software design of the instrument. We use 89C52 single-chip computer as the microprocessor to control the amplifier, AD and DA conversion chip to realize the sampling, data process, printout and supervision. The final result is printed out in form of data and aggregation curve from PP40 plotter.

77 FR 30048 - Petition for Waiver of Compliance

Federal Register 2010, 2011, 2012, 2013, 2014

2012-05-21

... locking; and 236.381, Traffic locking on vital microprocessor-based systems. MNCW proposes to verify and test signal locking systems controlled by microprocessor-based equipment by use of alternative...

Anti-Hassle Chip

NASA Technical Reports Server (NTRS)

1998-01-01

With assistance from NASA's Ames Research Center, the iTV Corporation has developed a full custom microprocessor that enables access to the Internet through a $49 device. The microprocessor is supported with a compliment of design tools for customization and adaptation as either a licensable core or as a complete microprocessor. Other uses include cell phones, DVD (digital versatile disk) players, cable modems, video conferencing equipment, digital cameras, wireless LANs (Local Area Network) and WANs (Wide Area Network). iTV continues to design new, low-cost consumer products.

Frequency Dependence of Single-event Upset in Advanced Commerical PowerPC Microprocessors

NASA Technical Reports Server (NTRS)

Irom, Frokh; Farmanesh, Farhad F.; Swift, Gary M.; Johnston, Allen H.

2004-01-01

This paper examines single-event upsets in advanced commercial SOI microprocessors in a dynamic mode, studying SEU sensitivity of General Purpose Registers (GPRs) with clock frequency. Results are presented for SOI processors with feature sizes of 0.18 microns and two different core voltages. Single-event upset from heavy ions is measured for advanced commercial microprocessors in a dynamic mode with clock frequency up to 1GHz. Frequency and core voltage dependence of single-event upsets in registers is discussed.

Orbit determination software development for microprocessor based systems: Evaluation and recommendations

NASA Technical Reports Server (NTRS)

Shenitz, C. M.; Mcgarry, F. E.; Tasaki, K. K.

1980-01-01

A guide is presented for National Aeronautics and Space Administration management personnel who stand to benefit from the lessons learned in developing microprocessor-based flight dynamics software systems. The essential functional characteristics of microprocessors are presented. The relevant areas of system support software are examined, as are the distinguishing characteristics of flight dynamics software. Design examples are provided to illustrate the major points presented, and actual development experience obtained in this area is provided as evidence to support the conclusions reached.

49 CFR 229.23 - Periodic inspection: general.

Code of Federal Regulations, 2012 CFR

2012-10-01

... locomotive. (b) For each locomotive equipped with advanced microprocessor-based on-board electronic condition... April 2, or July 3 if it's a locomotive equipped with advanced microprocessor-based on-board electronic...

49 CFR 229.23 - Periodic inspection: general.

Code of Federal Regulations, 2013 CFR

2013-10-01

... locomotive. (b) For each locomotive equipped with advanced microprocessor-based on-board electronic condition... April 2, or July 3 if it's a locomotive equipped with advanced microprocessor-based on-board electronic...

49 CFR 229.23 - Periodic inspection: general.

Code of Federal Regulations, 2014 CFR

2014-10-01

... locomotive. (b) For each locomotive equipped with advanced microprocessor-based on-board electronic condition... April 2, or July 3 if it's a locomotive equipped with advanced microprocessor-based on-board electronic...

Lasers in automobile production

NASA Astrophysics Data System (ADS)

Pizzi, P.

There is a trend in mechanical equipment to replace complicated mechanical components with electronics, especially microprocessors, laser technology represents an important new tool. The effects of laser technology can be seen in production systems concerned with cutting, welding, heat treatment, and the alloying of mechanical components. Applications in the automobile industry today are not very widespread and are concerned essentially with welding and cutting.

Approximate Linear Regulator and Kalman Filter

DTIC Science & Technology

1980-09-01

of Equivalent Dominant Poles and Zeros Using Industrial Specifications," IEEE Trans. on Industrial Electronics and Control Instrumentation, Vol. IECI...true. In recent years, the rapid development of powerful minicomputers and microprocessors makes the industrial applications of optimal control...1976, pp. 677-687. [21] Y. Takahashi, M. Tomizuka and D. I. Auslander, Simple discrete control of industrial processes, Trans. on ASME J. of Dynamic

Advances in 7xx-nm fiber-coupled modules with application to Tm fiber laser pumping and DPAL (Conference Presentation)

NASA Astrophysics Data System (ADS)

Patterson, Steven G.; Guiney, Tina; Stapleton, Dean; Braker, Joseph; Alegria, Kim; Irwin, David A.; Ebert, Christopher

2017-02-01

DILAS has leveraged its industry-leading work in manufacturing low SWaP fiber-coupled modules extending the wavelength range to 793nm for Tm fiber laser pumping. Ideal for medical, industrial and military applications, modules spanning from single emitter-based 9W to TBar-based 200W of 793nm pump power will be discussed. The highlight is a lightweight module capable of <200W of 793nm pump power out of a package weighing < 400 grams. In addition, other modules spanning from single emitter-based 9W to TBar-based 200W of 793nm pump power will be presented. In addition, advances in DPAL modules, emitting at the technologically important wavelengths near 766nm and 780nm, will be detailed. Highlights include a fully microprocessor controlled fiber-coupled module that produces greater than 400W from a 600 micron core fiber and a line width of only 56.3pm. The micro-processor permits the automated center wavelength and line width tuning of the output over a range of output powers while retaining excellent line center and line width stability over time.

Multilevel Summation of Electrostatic Potentials Using Graphics Processing Units*

PubMed Central

Hardy, David J.; Stone, John E.; Schulten, Klaus

2009-01-01

Physical and engineering practicalities involved in microprocessor design have resulted in flat performance growth for traditional single-core microprocessors. The urgent need for continuing increases in the performance of scientific applications requires the use of many-core processors and accelerators such as graphics processing units (GPUs). This paper discusses GPU acceleration of the multilevel summation method for computing electrostatic potentials and forces for a system of charged atoms, which is a problem of paramount importance in biomolecular modeling applications. We present and test a new GPU algorithm for the long-range part of the potentials that computes a cutoff pair potential between lattice points, essentially convolving a fixed 3-D lattice of “weights” over all sub-cubes of a much larger lattice. The implementation exploits the different memory subsystems provided on the GPU to stream optimally sized data sets through the multiprocessors. We demonstrate for the full multilevel summation calculation speedups of up to 26 using a single GPU and 46 using multiple GPUs, enabling the computation of a high-resolution map of the electrostatic potential for a system of 1.5 million atoms in under 12 seconds. PMID:20161132

A Microprocessor Development System for the Intel 8748 Microcomputer.

DTIC Science & Technology

1979-12-01

their ready availability, it was decided to build the system on a 4 x 6 Vector plugboard with a 44 pin connect- or and which was predrilled for wirewrap...8748, additional sockets were provided in a 4 socket mother board. These sockets accept the standard 44 pin Vector plugboard . It is recommended that

The Promise of Technology. Proceedings of the Annual Conference on Rehabilitation Engineering (6th, San Diego, California, June 12-16, 1983). Volume 3.

ERIC Educational Resources Information Center

Bowman, Bruce R., Ed.

These proceedings contain abstracts of 164 papers in the area of interdisciplinary rehabilitation research, focusing on the theme of "The Promise of Technology." The abstracts are organized into the following sections: "Home and Worksite Modification,""Computers and Microprocessor Systems,""Neuromuscular…

Benchmark tests on the digital equipment corporation Alpha AXP 21164-based AlphaServer 8400, including a comparison of optimized vector and superscalar processing

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wasserman, H.J.

1996-02-01

The second generation of the Digital Equipment Corp. (DEC) DECchip Alpha AXP microprocessor is referred to as the 21164. From the viewpoint of numerically-intensive computing, the primary difference between it and its predecessor, the 21064, is that the 21164 has twice the multiply/add throughput per clock period (CP), a maximum of two floating point operations (FLOPS) per CP vs. one for 21064. The AlphaServer 8400 is a shared-memory multiprocessor server system that can accommodate up to 12 CPUs and up to 14 GB of memory. In this report we will compare single processor performance of the 8400 system with thatmore » of the International Business Machines Corp. (IBM) RISC System/6000 POWER-2 microprocessor running at 66 MHz, the Silicon Graphics, Inc. (SGI) MIPS R8000 microprocessor running at 75 MHz, and the Cray Research, Inc. CRAY J90. The performance comparison is based on a set of Fortran benchmark codes that represent a portion of the Los Alamos National Laboratory supercomputer workload. The advantage of using these codes, is that the codes also span a wide range of computational characteristics, such as vectorizability, problem size, and memory access pattern. The primary disadvantage of using them is that detailed, quantitative analysis of performance behavior of all codes on all machines is difficult. One important addition to the benchmark set appears for the first time in this report. Whereas the older version was written for a vector processor, the newer version is more optimized for microprocessor architectures. Therefore, we have for the first time, an opportunity to measure performance on a single application using implementations that expose the respective strengths of vector and superscalar architecture. All results in this report are from single processors. A subsequent article will explore shared-memory multiprocessing performance of the 8400 system.« less

Development and testing of the Rho Sigma Incorporated microprocessor control subsystem

NASA Technical Reports Server (NTRS)

Hankins, J. D.

1979-01-01

Product development and performance tests of three programmable microprocessor controllers for use with solar heating and cooling systems are presented. The products were developed to be marketable for public use.

A Micro-Processor Based System as a Teaching Tool.

ERIC Educational Resources Information Center

Spero, Samuel W.

1979-01-01

Two instructional strategies incorporating a microprocessor-based computer system are described. These are the use of the system to drive a television monitor, and the system's use in generating problem sets. (MP)

40 CFR Appendix F to Part 60 - Quality Assurance Procedures

Code of Federal Regulations, 2012 CFR

2012-07-01

... automatically adjust the data to the corrected calibration values (e.g., microprocessor control) must be... calibration values (e.g., microprocessor control), you must program your PM CEMS to record the unadjusted...

Global identification of target recognition and cleavage by the Microprocessor in human ES cells.

PubMed

Seong, Youngmo; Lim, Do-Hwan; Kim, Augustine; Seo, Jae Hong; Lee, Young Sik; Song, Hoseok; Kwon, Young-Soo

2014-11-10

The Microprocessor plays an essential role in canonical miRNA biogenesis by facilitating cleavage of stem-loop structures in primary transcripts to yield pre-miRNAs. Although miRNA biogenesis has been extensively studied through biochemical and molecular genetic approaches, it has yet to be addressed to what extent the current miRNA biogenesis models hold true in intact cells. To address the issues of in vivo recognition and cleavage by the Microprocessor, we investigate RNAs that are associated with DGCR8 and Drosha by using immunoprecipitation coupled with next-generation sequencing. Here, we present global protein-RNA interactions with unprecedented sensitivity and specificity. Our data indicate that precursors of canonical miRNAs and miRNA-like hairpins are the major substrates of the Microprocessor. As a result of specific enrichment of nascent cleavage products, we are able to pinpoint the Microprocessor-mediated cleavage sites per se at single-nucleotide resolution. Unexpectedly, a 2-nt 3' overhang invariably exists at the ends of cleaved bases instead of nascent pre-miRNAs. Besides canonical miRNA precursors, we find that two novel miRNA-like structures embedded in mRNAs are cleaved to yield pre-miRNA-like hairpins, uncoupled from miRNA maturation. Our data provide a framework for in vivo Microprocessor-mediated cleavage and a foundation for experimental and computational studies on miRNA biogenesis in living cells. © The Author(s) 2014. Published by Oxford University Press on behalf of Nucleic Acids Research.

77 FR 22384 - Petition To Modify an Exemption of a Previously Approved Antitheft Device; Porsche

Federal Register 2010, 2011, 2012, 2013, 2014

2012-04-13

... passive, microprocessor-based device which includes a starter interrupt function, transponder key and a.... Porsche stated that the antitheft system consists of two major subsystems: a microprocessor-based...

47 CFR 15.32 - Test procedures for CPU boards and computer power supplies.

Code of Federal Regulations, 2011 CFR

2011-10-01

... result in a complete personal computer system. If the oscillator and the microprocessor circuits are... microprocessor circuits are contained on separate circuit boards, both boards, typical of the combination that...

47 CFR 15.32 - Test procedures for CPU boards and computer power supplies.

Code of Federal Regulations, 2013 CFR

2013-10-01

... result in a complete personal computer system. If the oscillator and the microprocessor circuits are... microprocessor circuits are contained on separate circuit boards, both boards, typical of the combination that...

47 CFR 15.32 - Test procedures for CPU boards and computer power supplies.

Code of Federal Regulations, 2014 CFR

2014-10-01

... result in a complete personal computer system. If the oscillator and the microprocessor circuits are... microprocessor circuits are contained on separate circuit boards, both boards, typical of the combination that...

47 CFR 15.32 - Test procedures for CPU boards and computer power supplies.

Code of Federal Regulations, 2012 CFR

2012-10-01

... result in a complete personal computer system. If the oscillator and the microprocessor circuits are... microprocessor circuits are contained on separate circuit boards, both boards, typical of the combination that...

75 FR 22174 - Petition To Modify an Exemption of a Previously Approved Antitheft Device; Porsche

Federal Register 2010, 2011, 2012, 2013, 2014

2010-04-27

... passive antitheft device installed on the Porsche Panamera includes a microprocessor-based immobilizer... modified antitheft system will now consist of a microprocessor based immobilizer system which prevents...

47 CFR 15.32 - Test procedures for CPU boards and computer power supplies.

Code of Federal Regulations, 2010 CFR

2010-10-01

... result in a complete personal computer system. If the oscillator and the microprocessor circuits are... microprocessor circuits are contained on separate circuit boards, both boards, typical of the combination that...

Sensium: an ultra-low-power wireless body sensor network platform: design & application challenges.

PubMed

Wong, A W; McDonagh, D; Omeni, O; Nunn, C; Hernandez-Silveira, M; Burdett, A J

2009-01-01

In this paper we present a system-on-chip for wireless body sensor networks, which integrates a transceiver, hardware MAC protocol, microprocessor, IO peripherals, memories, ADC and custom sensor interfaces. Addressing the challenges in the design, this paper will continue to discuss the issues in the applications of this technology to body worn monitoring for real-time measurement of ECG, heart rate, physical activity, respiration and/or skin temperature. Two application challenges are described; the real-time measurement of energy expenditure using the LifePebble, and; the development issues surrounding the 'Digital Patch'.

Microprocessors: the engines of the digital age

PubMed Central

2017-01-01

The microprocessor—a computer central processing unit integrated onto a single microchip—has come to dominate computing across all of its scales from the tiniest consumer appliance to the largest supercomputer. This dominance has taken decades to achieve, but an irresistible logic made the ultimate outcome inevitable. The objectives of this Perspective paper are to offer a brief history of the development of the microprocessor and to answer questions such as: where did the microprocessor come from, where is it now, and where might it go in the future? PMID:28413353

Evaluation of the performance of microprocessor-based colorimeter

PubMed Central

Randhawa, S. S.; Gupta, R. C.; Bhandari, A. K.; Malhotra, P. S.

1992-01-01

Colorimetric estimations have an important role in quantitative studies. An inexpensive and portable microprocessor-based colorimeter developed by the authors is described in this paper. The colorimeter uses a light emitting diode as the light source; a pinphotodiode as the detector and an 8085A microprocessor. Blood urea, glucose, total protein, albumin and bilirubin from patient blood samples were analysed with the instrument and results obtained were compared with assays of the same blood using a Spectronic 21. A good correlation was found between the results from the two instruments. PMID:18924952

Evaluation of the performance of microprocessor-based colorimeter.

PubMed

Randhawa, S S; Gupta, R C; Bhandari, A K; Malhotra, P S

1992-01-01

Colorimetric estimations have an important role in quantitative studies. An inexpensive and portable microprocessor-based colorimeter developed by the authors is described in this paper. The colorimeter uses a light emitting diode as the light source; a pinphotodiode as the detector and an 8085A microprocessor. Blood urea, glucose, total protein, albumin and bilirubin from patient blood samples were analysed with the instrument and results obtained were compared with assays of the same blood using a Spectronic 21. A good correlation was found between the results from the two instruments.

Advanced microprocessor based power protection system using artificial neural network techniques

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chen, Z.; Kalam, A.; Zayegh, A.

This paper describes an intelligent embedded microprocessor based system for fault classification in power system protection system using advanced 32-bit microprocessor technology. The paper demonstrates the development of protective relay to provide overcurrent protection schemes for fault detection. It also describes a method for power fault classification in three-phase system based on the use of neural network technology. The proposed design is implemented and tested on a single line three phase power system in power laboratory. Both the hardware and software development are described in detail.

Tandem accelerators in Romania: Multi-tools for science, education and technology

NASA Astrophysics Data System (ADS)

Burducea, I.; GhiÅ£ǎ, D. G.; Sava, T. B.; Straticiuc, M.

2017-06-01

An educated selection of the main beam parameters - particle type, velocity and intensity, can result in a cutting-edge scalpel to remove tumors, sanitize sewage, act as a nuclear forensics detective, date an artefact, clean up air, improve a microprocessor, transmute nuclear waste, detect a counterfeit or even look into the stars. Nowadays more than particle accelerators operate worldwide in medicine, industry and basic research. For example the proton therapy market is expected to attain 1 billion US per year in 2019 with almost 330 proton therapy rooms, while the annual market for the ion implantation industry already reached 1.5 G in revenue [1,2]. A brief history of the Tandem Accelerators Complex at IFIN-HH [3] emphasizing on their applications and the physics behind the scenes, is also presented [4-6].

A MICROPROCESSOR ASCII CHARACTER BUFFERING SYSTEM

EPA Science Inventory

A microprocessor buffering system (MBS) was developed at the Environmental Monitoring and Support Laboratory -Cincinnati (EMSL-CI) to provide an efficient transfer for serial ASCII information between intelligent instrument systema and a Data General NOVA laboratory automation co...

MICROPROCESSOR CONTROL OF ROTOGRAVURE AIRFLOWS

EPA Science Inventory

The report discusses the technical and economic viability of using micro-processor-based control technology to collect volatile organic compound (VOC) emissions from a paper coating operation. The microprocessor-based control system monitors and controls both the airflow rate and...

78 FR 53500 - Petition for Exemption From the Federal Motor Vehicle Theft Prevention Standard; Chrysler

Federal Register 2010, 2011, 2012, 2013, 2014

2013-08-29

...) transceiver and a microprocessor and it initiates the ignition process by communicating with the BCM through SKIS. The microprocessor-based SKIS hardware and software also use electronic messages to communicate...

Pupillometry, a bioengineering overview

NASA Technical Reports Server (NTRS)

Myers, G.; Anchetta, J.; Hannaford, B.; Peng, P.; Sherman, K.; Stark, L.; Sun, F.; Usui, S.

1981-01-01

The pupillary control system is examined using a microprocessor based integrative pupillometer. The real time software functions of the microprocessor include: data collection, stimulus generation and area to diameter conversion. Results of an analysis of linear and nonlinear phenomena are presented.

Microprocessor mediates transcriptional termination of long noncoding RNA transcripts hosting microRNAs.

PubMed

Dhir, Ashish; Dhir, Somdutta; Proudfoot, Nick J; Jopling, Catherine L

2015-04-01

MicroRNAs (miRNAs) play a major part in the post-transcriptional regulation of gene expression. Mammalian miRNA biogenesis begins with cotranscriptional cleavage of RNA polymerase II (Pol II) transcripts by the Microprocessor complex. Although most miRNAs are located within introns of protein-coding transcripts, a substantial minority of miRNAs originate from long noncoding (lnc) RNAs, for which transcript processing is largely uncharacterized. We show, by detailed characterization of liver-specific lnc-pri-miR-122 and genome-wide analysis in human cell lines, that most lncRNA transcripts containing miRNAs (lnc-pri-miRNAs) do not use the canonical cleavage-and-polyadenylation pathway but instead use Microprocessor cleavage to terminate transcription. Microprocessor inactivation leads to extensive transcriptional readthrough of lnc-pri-miRNA and transcriptional interference with downstream genes. Consequently we define a new RNase III-mediated, polyadenylation-independent mechanism of Pol II transcription termination in mammalian cells.

Microprocessor mediates transcriptional termination in long noncoding microRNA genes

PubMed Central

Dhir, Ashish; Dhir, Somdutta; Proudfoot, Nick J.; Jopling, Catherine L.

2015-01-01

MicroRNA (miRNA) play a major role in the post-transcriptional regulation of gene expression. Mammalian miRNA biogenesis begins with co-transcriptional cleavage of RNA polymerase II (Pol II) transcripts by the Microprocessor complex. While most miRNA are located within introns of protein coding genes, a substantial minority of miRNA originate from long non coding (lnc) RNA where transcript processing is largely uncharacterized. We show, by detailed characterization of liver-specific lnc-pri-miR-122 and genome-wide analysis in human cell lines, that most lnc-pri-miRNA do not use the canonical cleavage and polyadenylation (CPA) pathway, but instead use Microprocessor cleavage to terminate transcription. This Microprocessor inactivation leads to extensive transcriptional readthrough of lnc-pri-miRNA and transcriptional interference with downstream genes. Consequently we define a novel RNase III-mediated, polyadenylation-independent mechanism of Pol II transcription termination in mammalian cells. PMID:25730776

Development of 3-Year Roadmap to Transform the Discipline of Systems Engineering

DTIC Science & Technology

2010-03-31

quickly humans could physically construct them. Indeed, magnetic core memory was entirely constructed by human hands until it was superseded by...For their mainframe computers, IBM develops the applications, operating system, computer hardware and microprocessors (off the shelf standard memory ...processor developers work on potential computational and memory pipelines to support the required performance capabilities and use the available transistors

Installation package for integrated programmable electronic controller and hydronic subsystem - solar heating and cooling

NASA Technical Reports Server (NTRS)

1978-01-01

A description is given of the Installation, Operation, and Maintenance Manual and information on the power panel and programmable microprocessor, a hydronic solar pump system and a hydronic heating hot water pumping system. These systems are integrated into various configurations for usages in solar energy management, control and monitoring, lighting control, data logging and other solar related applications.

Alternating phase-shifted mask for logic gate levels, design, and mask manufacturing

NASA Astrophysics Data System (ADS)

Liebmann, Lars W.; Graur, Ioana C.; Leipold, William C.; Oberschmidt, James M.; O'Grady, David S.; Regaill, Denis

1999-07-01

While the benefits of alternating phase shifted masks in improving lithographic process windows at increased resolution are well known throughout the lithography community, broad implementation of this potentially powerful technique has been slow due to the inherent complexity of the layout design and mask manufacturing process. This paper will review a project undertaken at IBM's Semiconductor Research and Development Center and Mask Manufacturing and Development facility to understand the technical and logistical issues associated with the application of alternating phase shifted mask technology to the gate level of a full microprocessor chip. The work presented here depicts an important milestone toward integration of alternating phase shifted masks into the manufacturing process by demonstrating an automated design solution and yielding a functional alternating phase shifted mask. The design conversion of the microprocessor gate level to a conjugate twin shifter alternating phase shift layout was accomplished with IBM's internal design system that automatically scaled the design, added required phase regions, and resolved phase conflicts. The subsequent fabrication of a nearly defect free phase shifted mask, as verified by SEM based die to die inspection, highlights the maturity of the alternating phase shifted mask manufacturing process in IBM's internal mask facility. Well defined and recognized challenges in mask inspection and repair remain and the layout of alternating phase shifted masks present a design and data preparation overhead, but the data presented here demonstrate the feasibility of designing and building manufacturing quality alternating phase shifted masks for the gate level of a microprocessor.

OS Friendly Microprocessor Architecture

DTIC Science & Technology

2017-04-01

fact or fiction. Austin ( TX ): The Virtualization Practice; [accessed 2012 July 26]. http://www.virtualization practice.com/type-0-hypervisor-fact......needed. Do not return it to the originator. ARL-SR-0370 ● APR 2017 US Army Research Laboratory OS Friendly Microprocessor

Single-event upset in advanced commercial power PC microprocessors

NASA Technical Reports Server (NTRS)

Irom, F.; Farmanesh, F.; Swift, G. M.; Johnston, A. H.

2003-01-01

Single-event upset from heavy ions in measured for advanced commercial microprocessors, comparing upset sensitivity in registers and d-cache for several generations of devices. Multiple-bit upsets and asymmetry in registers upset cross sections are also discussed.

Intelligent lightening system of urban and rural road traffic based on pyroelectric infrared detector

NASA Astrophysics Data System (ADS)

Miao, Man-Xiang

2007-12-01

By using the photo-voltage characteristics of pyroelectric infrared detector to fulfill signal acquisition, the detecting signal is processed with the core of a single chip microprocessor AT89C51. AT89C51 controls the CAN bus controller SJA1000/transceiver 82C250 to structure CAN bus communication system to transmit data through serial interface MAX232 connected with PC. The intelligent lightening system of urban and rural road traffic was carried out. In this paper, its construction and part's methods of hardware and software design were introduced in detail.

AC resistance measuring instrument

DOEpatents

Hof, P.J.

1983-10-04

An auto-ranging AC resistance measuring instrument for remote measurement of the resistance of an electrical device or circuit connected to the instrument includes a signal generator which generates an AC excitation signal for application to a load, including the device and the transmission line, a monitoring circuit which provides a digitally encoded signal representing the voltage across the load, and a microprocessor which operates under program control to provide an auto-ranging function by which range resistance is connected in circuit with the load to limit the load voltage to an acceptable range for the instrument, and an auto-compensating function by which compensating capacitance is connected in shunt with the range resistance to compensate for the effects of line capacitance. After the auto-ranging and auto-compensation functions are complete, the microprocessor calculates the resistance of the load from the selected range resistance, the excitation signal, and the load voltage signal, and displays of the measured resistance on a digital display of the instrument. 8 figs.

AC Resistance measuring instrument

DOEpatents

Hof, Peter J.

1983-01-01

An auto-ranging AC resistance measuring instrument for remote measurement of the resistance of an electrical device or circuit connected to the instrument includes a signal generator which generates an AC excitation signal for application to a load, including the device and the transmission line, a monitoring circuit which provides a digitally encoded signal representing the voltage across the load, and a microprocessor which operates under program control to provide an auto-ranging function by which range resistance is connected in circuit with the load to limit the load voltage to an acceptable range for the instrument, and an auto-compensating function by which compensating capacitance is connected in shunt with the range resistance to compensate for the effects of line capacitance. After the auto-ranging and auto-compensation functions are complete, the microprocessor calculates the resistance of the load from the selected range resistance, the excitation signal, and the load voltage signal, and displays of the measured resistance on a digital display of the instrument.

Equipment upgrades for the Pu-238 program

DOE Office of Scientific and Technical Information (OSTI.GOV)

Congdon, J.W.; Stephens, W.D.; Marra, J.E.

1990-02-14

Much of the equipment and instrumentation in the Pu-238 production facilities is more than 15 years old. Significant improvements have been made in the available instrumentation, in particular, due to the application of microprocessors and lasers. The Actinide Technology Section of SRL has selected and is in the process of evaluating several state-of-the-art instruments which have potential applications in the Pu-238 program. The ease of operation and the accuracy of the instruments have been improved and, in most cases, the cost of the instruments have decreased. 5 refs.

Versatile, low-cost, computer-controlled, sample positioning system for vacuum applications

NASA Technical Reports Server (NTRS)

Vargas-Aburto, Carlos; Liff, Dale R.

1991-01-01

A versatile, low-cost, easy to implement, microprocessor-based motorized positioning system (MPS) suitable for accurate sample manipulation in a Second Ion Mass Spectrometry (SIMS) system, and for other ultra-high vacuum (UHV) applications was designed and built at NASA LeRC. The system can be operated manually or under computer control. In the latter case, local, as well as remote operation is possible via the IEEE-488 bus. The position of the sample can be controlled in three linear orthogonal and one angular coordinates.

15 CFR Supplement No. 1 to Part 744 - Military End-Use Examples for § 744.17

Code of Federal Regulations, 2012 CFR

2012-01-01

... part) of general-purpose microprocessors classified as ECCN 3A991.a.1 includes employing such microprocessors in the “use”, “development”, “production”, or deployment of: (1) Cruise missiles; (2) Electronic...

15 CFR Supplement No. 1 to Part 744 - Military End-Use Examples for § 744.17

Code of Federal Regulations, 2010 CFR

2010-01-01

... part) of general-purpose microprocessors classified as ECCN 3A991.a.1 includes employing such microprocessors in the “use”, “development”, “production”, or deployment of: (1) Cruise missiles; (2) Electronic...

15 CFR Supplement No. 1 to Part 744 - Military End-Use Examples for § 744.17

Code of Federal Regulations, 2013 CFR

2013-01-01

... part) of general-purpose microprocessors classified as ECCN 3A991.a.1 includes employing such microprocessors in the “use”, “development”, “production”, or deployment of: (1) Cruise missiles; (2) Electronic...

15 CFR Supplement No. 1 to Part 744 - Military End-Use Examples for § 744.17

Code of Federal Regulations, 2011 CFR

2011-01-01

... part) of general-purpose microprocessors classified as ECCN 3A991.a.1 includes employing such microprocessors in the “use”, “development”, “production”, or deployment of: (1) Cruise missiles; (2) Electronic...

Improved Training Program for Fall Prevention of Warfighters with Lower Extremity Trauma

DTIC Science & Technology

2016-10-01

productive, active civilian life. The training program utilizes a microprocessor -controlled treadmill designed to deliver task- specific training...National Military Medical Center (WRNMMC), and Mayo. The fall prevention training program utilizes a microprocessor -controlled treadmill to deliver

15 CFR Supplement No. 1 to Part 744 - Military End-Use Examples for § 744.17

Code of Federal Regulations, 2014 CFR

2014-01-01

... part) of general-purpose microprocessors classified as ECCN 3A991.a.1 includes employing such microprocessors in the “use”, “development”, “production”, or deployment of: (1) Cruise missiles; (2) Electronic...

Briefing: Microprocessors.

ERIC Educational Resources Information Center

Standing, Roy A.

1982-01-01

Reviews the basic concepts and technology behind the functions computers perform, describes the miniaturization of computer components, discusses the development of the microprocessor and the microcomputer, and makes projections concerning the future of the microcomputer market. Information is provided on the features, costs, and manufacturers of…

Single-event upset in highly scaled commercial silicon-on-insulator PowerPc microprocessors

NASA Technical Reports Server (NTRS)

Irom, Farokh; Farmanesh, Farhad H.

2004-01-01

Single event upset effects from heavy ions are measured for Motorola and IBM silicon-on-insulator (SOI) microprocessors with different feature sizes, and core voltages. The results are compared with results for similar devices with build substrates. The cross sections of the SOI processors are lower than their bulk counterparts, but the threshold is about the same, even though the charge collections depth is more than an order of magnitude smaller in the SOI devices. The scaling of the cross section with reduction of feature size and core voltage dependence for SOI microprocessors discussed.

Development of the self-learning machine for creating models of microprocessor of single-phase earth fault protection devices in networks with isolated neutral voltage above 1000 V

NASA Astrophysics Data System (ADS)

Utegulov, B. B.; Utegulov, A. B.; Meiramova, S.

2018-02-01

The paper proposes the development of a self-learning machine for creating models of microprocessor-based single-phase ground fault protection devices in networks with an isolated neutral voltage higher than 1000 V. Development of a self-learning machine for creating models of microprocessor-based single-phase earth fault protection devices in networks with an isolated neutral voltage higher than 1000 V. allows to effectively implement mathematical models of automatic change of protection settings. Single-phase earth fault protection devices.

Could a neuroscientist understand a microprocessor?

DOE PAGES

Jonas, Eric; Kording, Konrad Paul; Diedrichsen, Jorn

2017-01-12

There is a popular belief in neuroscience that we are primarily data limited, and that producing large, multimodal, and complex datasets will, with the help of advanced data analysis algorithms, lead to fundamental insights into the way the brain processes information. These datasets do not yet exist, and if they did we would have no way of evaluating whether or not the algorithmically-generated insights were sufficient or even correct. To address this, here we take a classical microprocessor as a model organism, and use our ability to perform arbitrary experiments on it to see if popular data analysis methods frommore » neuroscience can elucidate the way it processes information. Microprocessors are among those artificial information processing systems that are both complex and that we understand at all levels, from the overall logical flow, via logical gates, to the dynamics of transistors. We show that the approaches reveal interesting structure in the data but do not meaningfully describe the hierarchy of information processing in the microprocessor. This suggests current analytic approaches in neuroscience may fall short of producing meaningful understanding of neural systems, regardless of the amount of data. Furthermore, we argue for scientists using complex non-linear dynamical systems with known ground truth, such as the microprocessor as a validation platform for time-series and structure discovery methods.« less

Could a Neuroscientist Understand a Microprocessor?

PubMed Central

Kording, Konrad Paul

2017-01-01

There is a popular belief in neuroscience that we are primarily data limited, and that producing large, multimodal, and complex datasets will, with the help of advanced data analysis algorithms, lead to fundamental insights into the way the brain processes information. These datasets do not yet exist, and if they did we would have no way of evaluating whether or not the algorithmically-generated insights were sufficient or even correct. To address this, here we take a classical microprocessor as a model organism, and use our ability to perform arbitrary experiments on it to see if popular data analysis methods from neuroscience can elucidate the way it processes information. Microprocessors are among those artificial information processing systems that are both complex and that we understand at all levels, from the overall logical flow, via logical gates, to the dynamics of transistors. We show that the approaches reveal interesting structure in the data but do not meaningfully describe the hierarchy of information processing in the microprocessor. This suggests current analytic approaches in neuroscience may fall short of producing meaningful understanding of neural systems, regardless of the amount of data. Additionally, we argue for scientists using complex non-linear dynamical systems with known ground truth, such as the microprocessor as a validation platform for time-series and structure discovery methods. PMID:28081141

Could a Neuroscientist Understand a Microprocessor?

PubMed

Jonas, Eric; Kording, Konrad Paul

2017-01-01

There is a popular belief in neuroscience that we are primarily data limited, and that producing large, multimodal, and complex datasets will, with the help of advanced data analysis algorithms, lead to fundamental insights into the way the brain processes information. These datasets do not yet exist, and if they did we would have no way of evaluating whether or not the algorithmically-generated insights were sufficient or even correct. To address this, here we take a classical microprocessor as a model organism, and use our ability to perform arbitrary experiments on it to see if popular data analysis methods from neuroscience can elucidate the way it processes information. Microprocessors are among those artificial information processing systems that are both complex and that we understand at all levels, from the overall logical flow, via logical gates, to the dynamics of transistors. We show that the approaches reveal interesting structure in the data but do not meaningfully describe the hierarchy of information processing in the microprocessor. This suggests current analytic approaches in neuroscience may fall short of producing meaningful understanding of neural systems, regardless of the amount of data. Additionally, we argue for scientists using complex non-linear dynamical systems with known ground truth, such as the microprocessor as a validation platform for time-series and structure discovery methods.

Could a neuroscientist understand a microprocessor?

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jonas, Eric; Kording, Konrad Paul; Diedrichsen, Jorn

There is a popular belief in neuroscience that we are primarily data limited, and that producing large, multimodal, and complex datasets will, with the help of advanced data analysis algorithms, lead to fundamental insights into the way the brain processes information. These datasets do not yet exist, and if they did we would have no way of evaluating whether or not the algorithmically-generated insights were sufficient or even correct. To address this, here we take a classical microprocessor as a model organism, and use our ability to perform arbitrary experiments on it to see if popular data analysis methods frommore » neuroscience can elucidate the way it processes information. Microprocessors are among those artificial information processing systems that are both complex and that we understand at all levels, from the overall logical flow, via logical gates, to the dynamics of transistors. We show that the approaches reveal interesting structure in the data but do not meaningfully describe the hierarchy of information processing in the microprocessor. This suggests current analytic approaches in neuroscience may fall short of producing meaningful understanding of neural systems, regardless of the amount of data. Furthermore, we argue for scientists using complex non-linear dynamical systems with known ground truth, such as the microprocessor as a validation platform for time-series and structure discovery methods.« less

Educational Implications of Microelectronics and Microprocessors.

ERIC Educational Resources Information Center

Harris, N. D. C., Ed.

This conference report explores microelectronic technology, its effect on educational methods and objectives, and its implications for educator responsibilities. Two main areas were considered: the significance of the likely impact of the large scale introduction of microprocessors and microelectronics on commercial and industrial processes, the…

Variable-thermoinsulation garments with a microprocessor temperature controller.

PubMed

Kurczewska, Agnieszka; Leánikowski, Jacek

2008-01-01

This paper presents the concept of active variable thermoinsulation clothing for users working in low temperatures. Those garments contain heating inserts regulated by a microprocessor temperature controller. This paper also presents the results of tests carried out on the newly designed garments.

Gait termination on a declined surface in trans-femoral amputees: Impact of using microprocessor-controlled limb system.

PubMed

Abdulhasan, Zahraa M; Scally, Andy J; Buckley, John G

2018-05-30

Walking down ramps is a demanding task for transfemoral-amputees and terminating gait on ramps is even more challenging because of the requirement to maintain a stable limb so that it can do the necessary negative mechanical work on the centre-of-mass in order to arrest (dissipate) forward/downward velocity. We determined how the use of a microprocessor-controlled limb system (simultaneous control over hydraulic resistances at ankle and knee) affected the negative mechanical work done by each limb when transfemoral-amputees terminated gait during ramp descent. Eight transfemoral-amputees completed planned gait terminations (stopping on prosthesis) on a 5-degree ramp from slow and customary walking speeds, with the limb's microprocessor active or inactive. When active the limb operated in its 'ramp-descent' mode and when inactive the knee and ankle devices functioned at constant default levels. Negative limb work, determined as the integral of the negative mechanical (external) limb power during the braking phase, was compared across speeds and microprocessor conditions. Negative work done by each limb increased with speed (p < 0.001), and on the prosthetic limb it was greater when the microprocessor was active compared to inactive (p = 0.004). There was no change in work done across microprocessor conditions on the intact limb (p = 0.35). Greater involvement of the prosthetic limb when the limb system was active indicates its ramp-descent mode effectively altered the hydraulic resistances at the ankle and knee. Findings highlight participants became more assured using their prosthetic limb to arrest centre-of-mass velocity. Copyright © 2018 Elsevier Ltd. All rights reserved.

The quality of life analysis of knee prosthesis with complete microprocessor control in trans-femoral amputees.

PubMed

Saglam, Yavuz; Gulenc, Baris; Birisik, Fevzi; Ersen, Ali; Yilmaz Yalcinkaya, Ebru; Yazicioglu, Onder

2017-12-01

The aim of this study was to analyze the patient demographics, etiology of limb loss as well as reporting SF-36 scores for microprocessor prosthesis users in Turkish population. We reviewed 72 patients (61 male and 11 female; mean age: 37.7 ± 10.7) with uni-lateral, above knee amputation and a history of regular and microprocessor prosthesis use. All patients were called back for a last follow-up and they were asked to fill a self-administered general health status questionnaire (SF-36). According to the SF-36 results; physical component score (PCS) score was 46 ± 7.3 and mental components summary (MCS) score was 46.5 ± 9.1. These scores have statistical similarity with Turkish healthy controls, except SF (social functioning) sub-dimension. PCS score for women microprocessor users were significantly lower than men (43.3 vs. 48.7, p = 0.03), but MCS scores were similar in between genders (46 vs. 48.2, p = 0.13). Conventional prostheses usage time was positively correlated with physical function (PF) scores (r = 0.322, p = 0.010). Microprocessor prosthesis usage time was negatively correlated with role limitations due to emotional problem (RE) scores (r = -0,313, p = 0.009). The quality of life surveys were showed that the loss of an extremity have higher physical and psychological impact on women's physical scores. Overall, SF-36 results were similar in microprocessor using amputee's and Turkish normal controls. Level IV, therapeutic study. Copyright © 2017 Turkish Association of Orthopaedics and Traumatology. Production and hosting by Elsevier B.V. All rights reserved.

Virtual Instrument Simulator for CERES

NASA Technical Reports Server (NTRS)

Chapman, John J.

1997-01-01

A benchtop virtual instrument simulator for CERES (Clouds and the Earth's Radiant Energy System) has been built at NASA, Langley Research Center in Hampton, VA. The CERES instruments will fly on several earth orbiting platforms notably NASDA's Tropical Rainfall Measurement Mission (TRMM) and NASA's Earth Observing System (EOS) satellites. CERES measures top of the atmosphere radiative fluxes using microprocessor controlled scanning radiometers. The CERES Virtual Instrument Simulator consists of electronic circuitry identical to the flight unit's twin microprocessors and telemetry interface to the supporting spacecraft electronics and two personal computers (PC) connected to the I/O ports that control azimuth and elevation gimbals. Software consists of the unmodified TRW developed Flight Code and Ground Support Software which serves as the instrument monitor and NASA/TRW developed engineering models of the scanners. The CERES Instrument Simulator will serve as a testbed for testing of custom instrument commands intended to solve in-flight anomalies of the instruments which could arise during the CERES mission. One of the supporting computers supports the telemetry display which monitors the simulator microprocessors during the development and testing of custom instrument commands. The CERES engineering development software models have been modified to provide a virtual instrument running on a second supporting computer linked in real time to the instrument flight microprocessor control ports. The CERES Instrument Simulator will be used to verify memory uploads by the CERES Flight Operations TEAM at NASA. Plots of the virtual scanner models match the actual instrument scan plots. A high speed logic analyzer has been used to track the performance of the flight microprocessor. The concept of using an identical but non-flight qualified microprocessor and electronics ensemble linked to a virtual instrument with identical system software affords a relatively inexpensive simulation system capable of high fidelity.

Description and Applications for an Automated Inertial Azimuth Measuring System,

DTIC Science & Technology

specialized field environment. The present system consists of two integrated inertial sensors , an angle transfer system, a tiltmeter array and a...optical path. Highly sensitive tiltmeters are used to measure and correct for errors due to base motions of the inertial sensors . Data handling and...microprocessor. The inertial sensors use gimbal-mounted rate gyrocompasses to indicate the azimuths of two transfer mirrors with respect to true North. The

1989 IEEE Aerospace Applications Conference, Breckenridge, CO, Feb. 12-17, 1989, Conference Digest

NASA Astrophysics Data System (ADS)

Recent advances in electronic devices for aerospace applications are discussed in reviews and reports. Topics addressed include large-aperture mm-wave antennas, a cross-array radiometer for spacecraft applications, a technique for computing the propagation characteristics of optical fibers, an analog light-wave system for improving microwave-telemetry data communication, and a ground demonstration of an orbital-debris radar. Consideration is given to a verifiable autonomous satellite control system, Inmarsat second-generation satellites for mobile communication, automated tools for data-base design and criteria for their selection, and a desk-top simulation work station based on the DSP96002 microprocessor chip.

What does voice-processing technology support today?

PubMed Central

Nakatsu, R; Suzuki, Y

1995-01-01

This paper describes the state of the art in applications of voice-processing technologies. In the first part, technologies concerning the implementation of speech recognition and synthesis algorithms are described. Hardware technologies such as microprocessors and DSPs (digital signal processors) are discussed. Software development environment, which is a key technology in developing applications software, ranging from DSP software to support software also is described. In the second part, the state of the art of algorithms from the standpoint of applications is discussed. Several issues concerning evaluation of speech recognition/synthesis algorithms are covered, as well as issues concerning the robustness of algorithms in adverse conditions. Images Fig. 3 PMID:7479720

Immediate effects of a new microprocessor-controlled prosthetic knee joint: a comparative biomechanical evaluation.

PubMed

Bellmann, Malte; Schmalz, Thomas; Ludwigs, Eva; Blumentritt, Siegmar

2012-03-01

To investigate the immediate biomechanical effects after transition to a new microprocessor-controlled prosthetic knee joint. Intervention cross-over study with repeated measures. Only prosthetic knee joints were changed. Motion analysis laboratory. Men (N=11; mean age ± SD, 36.7±10.2y; Medicare functional classification level, 3-4) with unilateral transfemoral amputation. Two microprocessor-controlled prosthetic knee joints: C-Leg and a new prosthetic knee joint, Genium. Static prosthetic alignment, time-distance parameters, kinematic and kinetic parameters, and center of pressure. After a half-day training and an additional half-day accommodation, improved biomechanical outcomes were demonstrated by the Genium: lower ground reaction forces at weight acceptance during level walking at various velocities, increased swing phase flexion angles during walking on a ramp, and level walking with small steps. Maximum knee flexion angle during swing phase at various velocities was nearly equal for Genium. Step-over-step stair ascent with the Genium knee was more physiologic as demonstrated by a more equal load distribution between the prosthetic and contralateral sides and a more natural gait pattern. When descending stairs and ramps, knee flexion moments with the Genium tended to increase. During quiet stance on a decline, subjects using Genium accepted higher loading of the prosthetic side knee joint, thus reducing same side hip joint loading as well as postural sway. In comparision to the C-Leg, the Genium demonstrated immediate biomechanical advantages during various daily ambulatory activities, which may lead to an increase in range and diversity of activity of people with above-knee amputations. Results showed that use of the Genium facilitated more natural gait biomechanics and load distribution throughout the affected and sound musculoskeletal structure. This was observed during quiet stance on a decline, walking on level ground, and walking up and down ramps and stairs. Copyright © 2012 American Congress of Rehabilitation Medicine. Published by Elsevier Inc. All rights reserved.

Proceedings of the 1981 Army Numerical Analysis and Computers Conference, held U. S. Army Missile Command, Redstone Arsenal, Alabama, 26-27 February 1981

DTIC Science & Technology

1981-08-01

loaded Loading done Time= 1295 msec. SQRT(3) %I + 1 SQRT(3) %I - 1 SQRT(3) %I f 1 (D13) TX = 1---------+-1** x = C-l---+-------, x = - 1, x...thnrl its competitors. As is to be expected, the table makes cJc ;lr the benefits of subincrement ing for nny approximation. For example, usiny the...Acquisition Systems ( DACS ) and a Data Analysis System (DAN), The DACs will be microprocessor-based recording devices with software-control

Rapidly quantifying the relative distention of a human bladder

NASA Technical Reports Server (NTRS)

Companion, John A. (Inventor); Heyman, Joseph S. (Inventor); Mineo, Beth A. (Inventor); Cavalier, Albert R. (Inventor); Blalock, Travis N. (Inventor)

1991-01-01

A device and method was developed to rapidly quantify the relative distention of the bladder of a human subject. An ultrasonic transducer is positioned on the human subject near the bladder. A microprocessor controlled pulser excites the transducer by sending an acoustic wave into the human subject. This wave interacts with the bladder walls and is reflected back to the ultrasonic transducer where it is received, amplified, and processed by the receiver. The resulting signal is digitized by an analog to digital converter, controlled by the microprocessor again, and is stored in data memory. The software in the microprocessor determines the relative distention of the bladder as a function of the propagated ultrasonic energy. Based on programmed scientific measurements and the human subject's past history as contained in program memory, the microprocessor sends out a signal to turn on any or all of the available alarms. The alarm system includes and audible alarm, the visible alarm, the tactile alarm, and the remote wireless alarm.

Development of the transtibial prosthesis controlled pneumatically and electrically by microcomputer system.

PubMed

Shimada, Youichi; Terayama, Yukio

2006-01-01

This report represents the development of the prototype transtibial prosthesis to assist a smooth and comfortable walking for an unilateral amputee. This prosthesis is composed of two air cylinders, solenoid valves, portable and small air tank for compressed air storage, a multiple sensor system and a microprocessor. Two air cylinders are located around the rods to act as antagonistic and agonistic muscles. The system causes flexion and extension of the foot plate jointed at the ankle with compressed air, injected -or discharged via a solenoid or electromagnetic valves. The valves or solenoids are controlled with a microprocessor (Microchip Technology Inc., PIC16F876), the microprocessor generates control signals to the interface circuits for valve opening and closing consistent with the foot position during the walking phase. The control patterns generated in the microprocessor are modified with feedback from the touch sensor, ankle joint angle sensor and the two dimensional acceleration sensor. The primary walking pattern for an individual amputee should be developed through the gait analysis with video.

Developing prescribing guidelines for microprocessor-controlled prosthetic knees in the South East England.

PubMed

Sedki, Imad; Fisher, Keren

2015-06-01

Microprocessor-controlled prosthetic knees have gained increasing popularity over the last decade. Research supports their provision to address specific problems or to achieve certain rehabilitation goals. However, there are yet no agreed protocols or prescribing criteria to assist clinicians in the identification and appropriate selection of suitable users. The aim is to reach professionals' agreement on specific prescribing guidelines for microprocessor-controlled prosthetic knees. The study involved multidisciplinary teams from the Inter Regional Prosthetic Audit Group, representing nine Prosthetic Rehabilitation Centres in the South East England region. We used the Delphi technique with a total of three rounds to reach professionals' agreement. The prescribing guidelines were agreed and will be reviewed and updated depending on new research evidence and technical advances. This project is highly useful for professionals in a clinic setting to aid in appropriate patient selection and to justify the cost of prescribing microprocessor-controlled prosthetic knees. © The International Society for Prosthetics and Orthotics 2014.

Formal verification of an avionics microprocessor

NASA Technical Reports Server (NTRS)

Srivas, Mandayam, K.; Miller, Steven P.

1995-01-01

Formal specification combined with mechanical verification is a promising approach for achieving the extremely high levels of assurance required of safety-critical digital systems. However, many questions remain regarding their use in practice: Can these techniques scale up to industrial systems, where are they likely to be useful, and how should industry go about incorporating them into practice? This report discusses a project undertaken to answer some of these questions, the formal verification of the AAMPS microprocessor. This project consisted of formally specifying in the PVS language a rockwell proprietary microprocessor at both the instruction-set and register-transfer levels and using the PVS theorem prover to show that the microcode correctly implemented the instruction-level specification for a representative subset of instructions. Notable aspects of this project include the use of a formal specification language by practicing hardware and software engineers, the integration of traditional inspections with formal specifications, and the use of a mechanical theorem prover to verify a portion of a commercial, pipelined microprocessor that was not explicitly designed for formal verification.

Inhibition of Microprocessor Function during the Activation of the Type I Interferon Response.

PubMed

Witteveldt, Jeroen; Ivens, Alasdair; Macias, Sara

2018-06-12

Type I interferons (IFNs) are central components of the antiviral response. Most cell types respond to viral infections by secreting IFNs, but the mechanisms that regulate correct expression of these cytokines are not completely understood. Here, we show that activation of the type I IFN response regulates the expression of miRNAs in a post-transcriptional manner. Activation of IFN expression alters the binding of the Microprocessor complex to pri-miRNAs, reducing its processing rate and thus leading to decreased levels of a subset of mature miRNAs in an IRF3-dependent manner. The rescue of Microprocessor function during the antiviral response downregulates the levels of IFN-β and IFN-stimulated genes. All these findings support a model by which the inhibition of Microprocessor activity is an essential step to induce a robust type I IFN response in mammalian cells. Copyright © 2018 The Author(s). Published by Elsevier Inc. All rights reserved.

Gait asymmetry of transfemoral amputees using mechanical and microprocessor-controlled prosthetic knees.

PubMed

Kaufman, Kenton R; Frittoli, Serena; Frigo, Carlo A

2012-06-01

Amputees walk with an asymmetrical gait, which may lead to future musculoskeletal degenerative changes. The purpose of this study was to compare the gait asymmetry of active transfemoral amputees while using a passive mechanical knee joint or a microprocessor-controlled knee joint. Objective 3D gait measurements were obtained in 15 subjects (12 men and 3 women; age 42, range 26-57). Research participants were longtime users of a mechanical prosthesis (mean 20 years, range 3-36 years). Joint symmetry was calculated using a novel method that includes the entire waveform throughout the gait cycle. There was no significant difference in hip, knee and ankle kinematics symmetry when using the different knee prostheses. In contrast, the results demonstrated a significant improvement in lower extremity joint kinetics symmetry when using the microprocessor-controlled knee. Use of the microprocessor-controlled knee joint resulted in improved gait symmetry. These improvements may lead to a reduction in the degenerative musculoskeletal changes often experienced by amputees. Copyright © 2011 Elsevier Ltd. All rights reserved.

A Feasibility Study for Advanced Technology Integration for General Aviation.

DTIC Science & Technology

1980-05-01

154 4.5.9.4 Stratified Charge Reciprocating Engine ..... .. 155 4.5.9.5 Advanced Diesel Engine . ... 158 4.5.9.6 Liquid Cooling ... ........ 159... diesel , rotary combustion engine, advanced reciprocating engine concepts. (7) Powerplant control - integrated controls, microprocessor- based controls...Research Center Topics. (1) GATE (2) Positive displacement engines (a) Advanced reciprocating engines. (b) Alternative engine systems Diesel engines

Study of limitations and attributes of microprocessor testing techniques

NASA Technical Reports Server (NTRS)

Mccaskill, R.; Sohl, W. E.

1977-01-01

All microprocessor units have a similar architecture from which a basic test philosophy can be adopted and used to develop an approach to test each module separately in order to verify the functionality of each module within the device using the input/output pins of the device and its instruction set; test for destructive interaction between functional modules; and verify all timing, status information, and interrupt operations of the device. Block and test flow diagrams are given for the 8080, 8008, 2901, 6800, and 1802 microprocessors. Manufacturers are listed and problems encountered in testing the modules are discussed. Test equipment and methods are described.

Automated quantitative muscle biopsy analysis system

NASA Technical Reports Server (NTRS)

Castleman, Kenneth R. (Inventor)

1980-01-01

An automated system to aid the diagnosis of neuromuscular diseases by producing fiber size histograms utilizing histochemically stained muscle biopsy tissue. Televised images of the microscopic fibers are processed electronically by a multi-microprocessor computer, which isolates, measures, and classifies the fibers and displays the fiber size distribution. The architecture of the multi-microprocessor computer, which is iterated to any required degree of complexity, features a series of individual microprocessors P.sub.n each receiving data from a shared memory M.sub.n-1 and outputing processed data to a separate shared memory M.sub.n+1 under control of a program stored in dedicated memory M.sub.n.

Design of a microprocessor-based Control, Interface and Monitoring (CIM unit for turbine engine controls research

NASA Technical Reports Server (NTRS)

Delaat, J. C.; Soeder, J. F.

1983-01-01

High speed minicomputers were used in the past to implement advanced digital control algorithms for turbine engines. These minicomputers are typically large and expensive. It is desirable for a number of reasons to use microprocessor-based systems for future controls research. They are relatively compact, inexpensive, and are representative of the hardware that would be used for actual engine-mounted controls. The Control, Interface, and Monitoring Unit (CIM) contains a microprocessor-based controls computer, necessary interface hardware and a system to monitor while it is running an engine. It is presently being used to evaluate an advanced turbofan engine control algorithm.

Design description of a microprocessor based Engine Monitoring and Control unit (EMAC) for small turboshaft

NASA Technical Reports Server (NTRS)

Baez, A. N.

1985-01-01

Research programs have demonstrated that digital electronic controls are more suitable for advanced aircraft/rotorcraft turbine engine systems than hydromechanical controls. Commercially available microprocessors are believed to have the speed and computational capability required for implementing advanced digital control algorithms. Thus, it is desirable to demonstrate that off-the-shelf microprocessors are indeed capable of performing real time control of advanced gas turbine engines. The engine monitoring and control (EMAC) unit was designed and fabricated specifically to meet the requirements of an advanced gas turbine engine control system. The EMAC unit is fully operational in the Army/NASA small turboshaft engine digital research program.

Extended performance electric propulsion power processor design study. Volume 2: Technical summary

NASA Technical Reports Server (NTRS)

Biess, J. J.; Inouye, L. Y.; Schoenfeld, A. D.

1977-01-01

Electric propulsion power processor technology has processed during the past decade to the point that it is considered ready for application. Several power processor design concepts were evaluated and compared. Emphasis was placed on a 30 cm ion thruster power processor with a beam power rating supply of 2.2KW to 10KW for the main propulsion power stage. Extension in power processor performance were defined and were designed in sufficient detail to determine efficiency, component weight, part count, reliability and thermal control. A detail design was performed on a microprocessor as the thyristor power processor controller. A reliability analysis was performed to evaluate the effect of the control electronics redesign. Preliminary electrical design, mechanical design and thermal analysis were performed on a 6KW power transformer for the beam supply. Bi-Mod mechanical, structural and thermal control configurations were evaluated for the power processor and preliminary estimates of mechanical weight were determined.

Work and Programmable Automation.

ERIC Educational Resources Information Center

DeVore, Paul W.

A new industrial era based on electronics and the microprocessor has arrived, an era that is being called intelligent automation. Intelligent automation, in the form of robots, replaces workers, and the new products, using microelectronic devices, require significantly less labor to produce than the goods they replace. The microprocessor thus…

Small Private Key PKS on an Embedded Microprocessor

PubMed Central

Seo, Hwajeong; Kim, Jihyun; Choi, Jongseok; Park, Taehwan; Liu, Zhe; Kim, Howon

2014-01-01

Multivariate quadratic ( ) cryptography requires the use of long public and private keys to ensure a sufficient security level, but this is not favorable to embedded systems, which have limited system resources. Recently, various approaches to cryptography using reduced public keys have been studied. As a result of this, at CHES2011 (Cryptographic Hardware and Embedded Systems, 2011), a small public key scheme, was proposed, and its feasible implementation on an embedded microprocessor was reported at CHES2012. However, the implementation of a small private key scheme was not reported. For efficient implementation, random number generators can contribute to reduce the key size, but the cost of using a random number generator is much more complex than computing on modern microprocessors. Therefore, no feasible results have been reported on embedded microprocessors. In this paper, we propose a feasible implementation on embedded microprocessors for a small private key scheme using a pseudo-random number generator and hash function based on a block-cipher exploiting a hardware Advanced Encryption Standard (AES) accelerator. To speed up the performance, we apply various implementation methods, including parallel computation, on-the-fly computation, optimized logarithm representation, vinegar monomials and assembly programming. The proposed method reduces the private key size by about 99.9% and boosts signature generation and verification by 5.78% and 12.19% than previous results in CHES2012. PMID:24651722

Use of electronic microprocessor-based instrumentation by the U.S. geological survey for hydrologic data collection

USGS Publications Warehouse

Shope, William G.; ,

1991-01-01

The U.S. Geological Survey is acquiring a new generation of field computers and communications software to support hydrologic data-collection at field locations. The new computer hardware and software mark the beginning of the Survey's transition from the use of electromechanical devices and paper tapes to electronic microprocessor-based instrumentation. Software is being developed for these microprocessors to facilitate the collection, conversion, and entry of data into the Survey's National Water Information System. The new automated data-collection process features several microprocessor-controlled sensors connected to a serial digital multidrop line operated by an electronic data recorder. Data are acquired from the sensors in response to instructions programmed into the data recorder by the user through small portable lap-top or hand-held computers. The portable computers, called personal field computers, also are used to extract data from the electronic recorders for transport by courier to the office computers. The Survey's alternative to manual or courier retrieval is the use of microprocessor-based remote telemetry stations. Plans have been developed to enhance the Survey's use of the Geostationary Operational Environmental Satellite telemetry by replacing the present network of direct-readout ground stations with less expensive units. Plans also provide for computer software that will support other forms of telemetry such as telephone or land-based radio.

Small private key MQPKS on an embedded microprocessor.

PubMed

Seo, Hwajeong; Kim, Jihyun; Choi, Jongseok; Park, Taehwan; Liu, Zhe; Kim, Howon

2014-03-19

Multivariate quadratic (MQ) cryptography requires the use of long public and private keys to ensure a sufficient security level, but this is not favorable to embedded systems, which have limited system resources. Recently, various approaches to MQ cryptography using reduced public keys have been studied. As a result of this, at CHES2011 (Cryptographic Hardware and Embedded Systems, 2011), a small public key MQ scheme, was proposed, and its feasible implementation on an embedded microprocessor was reported at CHES2012. However, the implementation of a small private key MQ scheme was not reported. For efficient implementation, random number generators can contribute to reduce the key size, but the cost of using a random number generator is much more complex than computing MQ on modern microprocessors. Therefore, no feasible results have been reported on embedded microprocessors. In this paper, we propose a feasible implementation on embedded microprocessors for a small private key MQ scheme using a pseudo-random number generator and hash function based on a block-cipher exploiting a hardware Advanced Encryption Standard (AES) accelerator. To speed up the performance, we apply various implementation methods, including parallel computation, on-the-fly computation, optimized logarithm representation, vinegar monomials and assembly programming. The proposed method reduces the private key size by about 99.9% and boosts signature generation and verification by 5.78% and 12.19% than previous results in CHES2012.

Mobility and satisfaction with a microprocessor-controlled knee in moderately active amputees: A multi-centric randomized crossover trial.

PubMed

Lansade, Céline; Vicaut, Eric; Paysant, Jean; Ménager, Doménico; Cristina, Marie-Christine; Braatz, Frank; Domayer, Stephan; Pérennou, Dominic; Chiesa, Gérard

2018-05-14

Microprocessor-controlled knees are generally prescribed and reimbursed for active amputees. Recent studies suggested that this technology could be useful for amputees with moderate activity level. We compared the efficiency of a microprocessor-controlled knee (MPK, Kenevo, Otto Bock) and non-MPKs (NMPKs) in these indications. A multi-centric randomized crossover trial was conducted in 16 hospitals from 3 European countries. Participants were randomized to an MPK-NMPK sequence, testing the MPK for 3 months and the NMPK for 1 month, or to an NMPK-MPK sequence, testing the NMPK for 1 month and the MPK for 3 months. Dynamic balance, the main criteria, was assessed with the Timed-Up and Go test (TUG), functional mobility with the Locomotor Capability Index (LCI-5), quality of life with the Medical Outcomes Study Short Form 36 v2 (SF-36v2) and satisfaction with the Quebec User Evaluation of Satisfaction with Assistive Technology 2.0. The occurrence of falls was monitored during the last month of trial. Analysis was by intent-to-treat and per-protocol (PP). We recruited 35 individuals with transfemoral amputation or knee disarticulation (27 males; mean age 65.6years [SD 10.1]). On PP analysis, dynamic balance and functional mobility were improved with the MPK, as shown by a reduced median TUG time (from 21.4s [Q1-Q3 19.3-26.6] to 17.9s [15.4-22.7], P=0.001) and higher mean global LCI-5 (from 40.4 [SD 7.6] to 42.8 [6.2], P=0.02). Median global satisfaction score increased (from 3.9 [Q1-Q3 3.8-4.4] to 4.7 [4.1-4.9], P=0.001) and quality of life was improved for the mental component summary of the SF-36v2 (median score from 53.3 [Q1-Q3 47.8-60.7] to 60.2 [51.6-62.6], P=0.03) and physical component summary but not significantly (mean score from 44.1 [SD 6.3] to 46.3 [7.0], P=0.08). Monitoring of adverse events including falls revealed no differences between both assessed devices. This study enhances the level of evidence to argue equal opportunity for all individuals with transfemoral amputation or knee disarticulation, regardless of their mobility grade, to be provided with appropriate prostheses. Copyright © 2018. Published by Elsevier Masson SAS.

Microprocessor-based long term cardiorespirography. II. Status evaluation in term and premature newborns.

PubMed

Hörnchen, H; Betz, R; Kotlarek, F; Roebruck, P

1983-01-01

In 1965 URBACH et al. and RUDOLPH et al. [35, 39] described a loss of heart rate variability in severely ill neonates. In this study we investigated the correlation between instantaneous heart rate patterns and status diagnosis. We used a microprocessor-based cardiorespirography system. Seventy five newborn infants (51 prematures and 24 term neonates) were studied for about 12 hours each. Twenty nine patients had a second record after the first investigation. Parameters were: Type of frequency and oscillation, long time variability (LTV), short time variability (STV) and the newly introduced P-value (maximal difference between two successive R-peaks in five minutes). We found clear differences between the study groups. With increasing severity of illness mean values ("group mean values") of long time variability, short time variability and P-value decreased. Fixed heart rate became predominant. The most pronounced loss of heart rate variability was seen in infants with severe intracranial bleeding, thus offering a tentative diagnosis. For statistical analysis long time variability and the silent oscillation type have been proved as best parameters for this diagnosis. Severely decreased heart rate variations also have been seen in infants with acute renal failure--possibly because of brain edema--, after application of muscle relaxants, repeated doses of sedatives, and after prolonged anesthesia. Otherwise, the heart rate variability was probably dependent on age and gestational age in prematures and newborn infants without intracranial bleeding. It is possible to use microprocessor-based long time cardiorespirography as a simple screening method for the diagnosis of neonatal intracerebral bleeding. In future experiences transcutaneous measurements of oxygen tension should be included.

Walking-Beam Solar-Cell Conveyor

NASA Technical Reports Server (NTRS)

Feder, H.; Frasch, W.

1982-01-01

Microprocessor-controlled walking-beam conveyor moves cells between work stations in automated assembly line. Conveyor has arm at each work station. In unison arms pick up all solar cells and advance them one station; then beam retracks to be in position for next step. Microprocessor sets beam stroke, speed, and position.

High Stability Metal-Protein Interactions Evaluated by Microcalorimetry

DTIC Science & Technology

2016-04-29

microprocessor -controlled internal vacuum pump runs for a 90 second period, then it evaluates the vacuum pressure attained, and if that value meets spec...and the other with the software. There is a place in the wash module program where the ITC’s microprocessor - controlled internal vacuum pump runs for

An Interdisciplinary Microprocessor Project.

ERIC Educational Resources Information Center

Wilcox, Alan D.; And Others

1985-01-01

Describes an unusual project in which third-year computer science students designed and built a four-bit multiplier circuit and then combines it with software to complete a full 16-bit multiplication. The multiplier was built using TTL components, interfaced with a Z-80 microprocessor system, and programed in assembly language. (JN)

Maxi CAI with a Micro.

ERIC Educational Resources Information Center

Gerhold, George; And Others

This paper describes an effective microprocessor-based CAI system which has been repeatedly tested by a large number of students and edited accordingly. Tasks not suitable for microprocessor based systems (authoring, testing, and debugging) were handled on larger multi-terminal systems. This approach requires that the CAI language used on the…

Advanced Electricity. Microprocessors and Robotics. Curriculum Development. Bulletin 1803.

ERIC Educational Resources Information Center

Southeastern Louisiana Univ., Hammond.

This model instructional unit was developed to aid industrial arts/technology education teachers in Louisiana to teach a course on microprocessors and robotics in grades 11 and 12. It provides guidance on model performance objectives, current technology content, sources, and supplemental materials. Following a course description, rationale, and…

Fast Initialization of Bubble-Memory Systems

NASA Technical Reports Server (NTRS)

Looney, K. T.; Nichols, C. D.; Hayes, P. J.

1986-01-01

Improved scheme several orders of magnitude faster than normal initialization scheme. State-of-the-art commercial bubble-memory device used. Hardware interface designed connects controlling microprocessor to bubblememory circuitry. System software written to exercise various functions of bubble-memory system in comparison made between normal and fast techniques. Future implementations of approach utilize E2PROM (electrically-erasable programable read-only memory) to provide greater system flexibility. Fastinitialization technique applicable to all bubble-memory devices.

A Methodology for Formal Hardware Verification, with Application to Microprocessors.

DTIC Science & Technology

1993-08-29

concurrent programming lan- guages. Proceedings of the NATO Advanced Study Institute on Logics and Models of Concurrent Systems ( Colle - sur - Loup , France, 8-19...restricted class of formu- las . Bose and Fisher [26] developed a symbolic model checker based on a Cosmos switch-level model. Their modeling approach...verification using SDVS-the method and a case study. 17th Anuual Microprogramming Workshop (New Orleans, LA , 30 October-2 November 1984). Published as

To catch a comet: Technical overview of CAN DO G-324

NASA Technical Reports Server (NTRS)

Obrien, T. J. (Editor)

1986-01-01

The primary objective of the C. E. Williams Middle School Get Away Special CAN DO is the photographing of Comet Halley. The project will involve middle school students, grades 6 through 8, in the study and interpretation of astronomical photographs and techniques. G-324 is contained in a 5 cubic foot GAS Canister with an opening door and pyrex window for photography. It will be pressurized with one atmosphere of dry nitrogen. Three 35mm still cameras with 250 exposure film backs and different focal length lenses will be fired by a combination of automatic timer and an active comet detector. A lightweight 35mm movie camera will shoot single exposures at about 1/2 minute intervals to give an overlapping skymap of the mission. The fifth camera is a solid state television camera specially constructed for detection of the comet by microprocessor.

A microprocessor-based cardiotachometer

NASA Technical Reports Server (NTRS)

Donaldson, J. A.; Crosier, W. G.

1979-01-01

The development of a highly accurate and reliable cardiotachometer for measuring the heart rate of test subjects is discussed. It measures heart rate over the range of 30 to 250 beats/minute and gives instantaneous (beat to beat) updates on the system output so that occasional noise artifacts or ectopic beats could be more easily identified except that occasional missed beats caused by switching ECG leads should not cause a change in the output. The cardiotachometer uses an improved analog filter and R-wave detector and an Intel 8080A microprocessor to handle all of the logic and arithmetic necessary. By using the microprocessor, future hardware modifications could easily be made if functional changes were needed.

Implementation of the Sun Position Calculation in the PDC-1 Control Microprocessor

NASA Technical Reports Server (NTRS)

Stallkamp, J. A.

1984-01-01

The several computational approaches to providing the local azimuth and elevation angles of the Sun as a function of local time and then the utilization of the most appropriate method in the PDC-1 microprocessor are presented. The full algorithm, the FORTRAN form, is felt to be very useful in any kind or size of computer. It was used in the PDC-1 unit to generate efficient code for the microprocessor with its floating point arithmetic chip. The balance of the presentation consists of a brief discussion of the tracking requirements for PPDC-1, the planetary motion equations from the first to the final version, and the local azimuth-elevation geometry.

Instrumentation and control of harmonic oscillators via a single-board microprocessor-FPGA device.

PubMed

Picone, Rico A R; Davis, Solomon; Devine, Cameron; Garbini, Joseph L; Sidles, John A

2017-04-01

We report the development of an instrumentation and control system instantiated on a microprocessor-field programmable gate array (FPGA) device for a harmonic oscillator comprising a portion of a magnetic resonance force microscope. The specific advantages of the system are that it minimizes computation, increases maintainability, and reduces the technical barrier required to enter the experimental field of magnetic resonance force microscopy. Heterodyne digital control and measurement yields computational advantages. A single microprocessor-FPGA device improves system maintainability by using a single programming language. The system presented requires significantly less technical expertise to instantiate than the instrumentation of previous systems, yet integrity of performance is retained and demonstrated with experimental data.

Instrumentation and control of harmonic oscillators via a single-board microprocessor-FPGA device

NASA Astrophysics Data System (ADS)

Picone, Rico A. R.; Davis, Solomon; Devine, Cameron; Garbini, Joseph L.; Sidles, John A.

2017-04-01

We report the development of an instrumentation and control system instantiated on a microprocessor-field programmable gate array (FPGA) device for a harmonic oscillator comprising a portion of a magnetic resonance force microscope. The specific advantages of the system are that it minimizes computation, increases maintainability, and reduces the technical barrier required to enter the experimental field of magnetic resonance force microscopy. Heterodyne digital control and measurement yields computational advantages. A single microprocessor-FPGA device improves system maintainability by using a single programming language. The system presented requires significantly less technical expertise to instantiate than the instrumentation of previous systems, yet integrity of performance is retained and demonstrated with experimental data.

Distributed Microprocessor Automation Network for Synthesizing Radiotracers Used in Positron Emission Tomography [PET

DOE R&D Accomplishments Database

Russell, J. A. G.; Alexoff, D. L.; Wolf, A. P.

1984-09-01

This presentation describes an evolving distributed microprocessor network for automating the routine production synthesis of radiotracers used in Positron Emission Tomography. We first present a brief overview of the PET method for measuring biological function, and then outline the general procedure for producing a radiotracer. The paper identifies several reasons for our automating the syntheses of these compounds. There is a description of the distributed microprocessor network architecture chosen and the rationale for that choice. Finally, we speculate about how this network may be exploited to extend the power of the PET method from the large university or National Laboratory to the biomedical research and clinical community at large. (DT)

Computer Architecture's Changing Role in Rebooting Computing

DOE Office of Scientific and Technical Information (OSTI.GOV)

DeBenedictis, Erik P.

In this paper, Windows 95 started the Wintel era, in which Microsoft Windows running on Intel x86 microprocessors dominated the computer industry and changed the world. Retaining the x86 instruction set across many generations let users buy new and more capable microprocessors without having to buy software to work with new architectures.

Dynamic characterization and microprocessor control of the NASA/UVA proof mass actuator

NASA Technical Reports Server (NTRS)

Zimmerman, D. C.; Inman, D. J.; Horner, G. C.

1984-01-01

The self-contained electromagnetic-reaction-type force-actuator system developed by NASA/UVA for the verification of spacecraft-structure vibration-control laws is characterized and demonstrated. The device is controlled by a dedicated microprocessor and has dynamic characteristics determined by Fourier analysis. Test data on a cantilevered beam are shown.

Microprocessor-Based Neural-Pulse-Wave Analyzer

NASA Technical Reports Server (NTRS)

Kojima, G. K.; Bracchi, F.

1983-01-01

Microprocessor-based system analyzes amplitudes and rise times of neural waveforms. Displaying histograms of measured parameters helps researchers determine how many nerves contribute to signal and specify waveform characteristics of each. Results are improved noise rejection, full or partial separation of overlapping peaks, and isolation and identification of related peaks in different histograms. 2

The Use of Opto-Electronics in Viscometry.

ERIC Educational Resources Information Center

Mazza, R. J.; Washbourn, D. H.

1982-01-01

Describes a semi-automatic viscometer which incorporates a microprocessor system and uses optoelectronics to detect flow of liquid through the capillary, flow time being displayed on a timer with accuracy of 0.01 second. The system could be made fully automatic with an additional microprocessor circuit and inclusion of a pump. (Author/JN)

Coed Transactions, Vol. XI, No. 1, January 1979. Microprocessor Course Development Equipment Selection.

ERIC Educational Resources Information Center

Mitchell, Eugene E., Ed.; Leventhal, Lance A.

Many devices and systems related to microprocessors are available on the marketplace. The author suggests that criteria for selecting and designing workstations and development systems are necessary. Seventeen important factors of designing workstations and six desirable features of a development system are presented. The kinds of places in which…

Microprocessor Design Using Hardware Description Language

ERIC Educational Resources Information Center

Mita, Rosario; Palumbo, Gaetano

2008-01-01

The following paper has been conceived to deal with the contents of some lectures aimed at enhancing courses on digital electronic, microelectronic or VLSI systems. Those lectures show how to use a hardware description language (HDL), such as the VHDL, to specify, design and verify a custom microprocessor. The general goal of this work is to teach…

The Effects of Microprocessors on Industry, Society and Employment: A Meeting of the Frontier Group on Strategies for Change in a Technological Society (Bath, England, March 13, 1979).

ERIC Educational Resources Information Center

Harris, N. D. C.

Discussed are the multiple impacts of microelectronics on society. Included are discussions of the problem of predicting effects, difficulty of exploiting new technology, manpower consequences, and needs within the United Kingdom relating to microprocessors. (RE)

DSS 13 microprocessor antenna controller

NASA Technical Reports Server (NTRS)

Gosline, R. M.

1988-01-01

A microprocessor-based antenna monitor and control system with multiple CPUs are described. The system was developed as part of the unattended station project for DSS 13 and was enhanced for use by the SETI project. The operational features, hardware, and software designs are described, and a discussion is provided of the major problems encountered.

Computer Architecture's Changing Role in Rebooting Computing

DOE PAGES

DeBenedictis, Erik P.

2017-04-26

In this paper, Windows 95 started the Wintel era, in which Microsoft Windows running on Intel x86 microprocessors dominated the computer industry and changed the world. Retaining the x86 instruction set across many generations let users buy new and more capable microprocessors without having to buy software to work with new architectures.

An FPGA computing demo core for space charge simulation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wu, Jinyuan; Huang, Yifei; /Fermilab

2009-01-01

In accelerator physics, space charge simulation requires large amount of computing power. In a particle system, each calculation requires time/resource consuming operations such as multiplications, divisions, and square roots. Because of the flexibility of field programmable gate arrays (FPGAs), we implemented this task with efficient use of the available computing resources and completely eliminated non-calculating operations that are indispensable in regular micro-processors (e.g. instruction fetch, instruction decoding, etc.). We designed and tested a 16-bit demo core for computing Coulomb's force in an Altera Cyclone II FPGA device. To save resources, the inverse square-root cube operation in our design is computedmore » using a memory look-up table addressed with nine to ten most significant non-zero bits. At 200 MHz internal clock, our demo core reaches a throughput of 200 M pairs/s/core, faster than a typical 2 GHz micro-processor by about a factor of 10. Temperature and power consumption of FPGAs were also lower than those of micro-processors. Fast and convenient, FPGAs can serve as alternatives to time-consuming micro-processors for space charge simulation.« less

Microprocessor activity controls differential miRNA biogenesis In Vivo.

PubMed

Conrad, Thomas; Marsico, Annalisa; Gehre, Maja; Orom, Ulf Andersson

2014-10-23

In miRNA biogenesis, pri-miRNA transcripts are converted into pre-miRNA hairpins. The in vivo properties of this process remain enigmatic. Here, we determine in vivo transcriptome-wide pri-miRNA processing using next-generation sequencing of chromatin-associated pri-miRNAs. We identify a distinctive Microprocessor signature in the transcriptome profile from which efficiency of the endogenous processing event can be accurately quantified. This analysis reveals differential susceptibility to Microprocessor cleavage as a key regulatory step in miRNA biogenesis. Processing is highly variable among pri-miRNAs and a better predictor of miRNA abundance than primary transcription itself. Processing is also largely stable across three cell lines, suggesting a major contribution of sequence determinants. On the basis of differential processing efficiencies, we define functionality for short sequence features adjacent to the pre-miRNA hairpin. In conclusion, we identify Microprocessor as the main hub for diversified miRNA output and suggest a role for uncoupling miRNA biogenesis from host gene expression. Copyright © 2014 The Authors. Published by Elsevier Inc. All rights reserved.

Microprocessor depends on hemin to recognize the apical loop of primary microRNA

PubMed Central

Park, Joha; Dang, Thi Lieu; Choi, Yeon-Gil; Kim, V Narry

2018-01-01

Abstract Microprocessor, which consists of a ribonuclease III DROSHA and its cofactor DGCR8, initiates microRNA (miRNA) maturation by cleaving primary miRNA transcripts (pri-miRNAs). We recently demonstrated that the DGCR8 dimer recognizes the apical elements of pri-miRNAs, including the UGU motif, to accurately locate and orient Microprocessor on pri-miRNAs. However, the mechanism underlying the selective RNA binding remains unknown. In this study, we find that hemin, a ferric ion-containing porphyrin, enhances the specific interaction between the apical UGU motif and the DGCR8 dimer, allowing Microprocessor to achieve high efficiency and fidelity of pri-miRNA processing in vitro. Furthermore, by generating a DGCR8 mutant cell line and carrying out rescue experiments, we discover that hemin preferentially stimulates the expression of miRNAs possessing the UGU motif, thereby conferring differential regulation of miRNA maturation. Our findings reveal the molecular action mechanism of hemin in pri-miRNA processing and establish a novel function of hemin in inducing specific RNA-protein interaction. PMID:29750274

Microprocessor depends on hemin to recognize the apical loop of primary microRNA.

PubMed

Nguyen, Tuan Anh; Park, Joha; Dang, Thi Lieu; Choi, Yeon-Gil; Kim, V Narry

2018-06-20

Microprocessor, which consists of a ribonuclease III DROSHA and its cofactor DGCR8, initiates microRNA (miRNA) maturation by cleaving primary miRNA transcripts (pri-miRNAs). We recently demonstrated that the DGCR8 dimer recognizes the apical elements of pri-miRNAs, including the UGU motif, to accurately locate and orient Microprocessor on pri-miRNAs. However, the mechanism underlying the selective RNA binding remains unknown. In this study, we find that hemin, a ferric ion-containing porphyrin, enhances the specific interaction between the apical UGU motif and the DGCR8 dimer, allowing Microprocessor to achieve high efficiency and fidelity of pri-miRNA processing in vitro. Furthermore, by generating a DGCR8 mutant cell line and carrying out rescue experiments, we discover that hemin preferentially stimulates the expression of miRNAs possessing the UGU motif, thereby conferring differential regulation of miRNA maturation. Our findings reveal the molecular action mechanism of hemin in pri-miRNA processing and establish a novel function of hemin in inducing specific RNA-protein interaction.

Turbo Pascal Implementation of a Distributed Processing Network of MS-DOS Microcomputers Connected in a Master-Slave Configuration

DTIC Science & Technology

1989-12-01

Interrupt Procedures ....... 29 13. Support for a Larger Memory Model ................ 29 C. IMPLEMENTATION ........................................ 29...describe the programmer’s model of the hardware utilized in the microcomputers and interrupt driven serial communication considerations. Chapter III...Central Processor Unit The programming model of Table 2.1 is common to the Intel 8088, 8086 and 80x86 series of microprocessors used in the IBM PC/AT

Radome Positioner for the RFSS (Radio Frequency Simulation System).

DTIC Science & Technology

1978-02-27

its associated circuits contained on the Motorola M68MM01A-I micro- module (See Drawing 64). This board contains the 6800 microprocessor. Ik bytes of...D 00 1~ 0 41 + C.) ) -44 208 g. Small encoder diameter achieved by using integrated circuit modules . h. Stainless steel case. U...to the 30 integrated circuits which actually comprise the heart of the-microcomputer. This dramatic reduction in parts count re- sults in a similar

Proceedings of the Technical Forum (3rd) on the F-16 MIL-STD-1750A Microprocessor and the F-16 MIL-STD-1589B Compiler Held at Wright-Patterson AFB, OH on May 5-6, 1982. Volume 1. Papers,

DTIC Science & Technology

1982-05-06

BUS MKS Fucioa Diagram ~ALAOAR *RSAU TT E E 0E U D*iQ MKSXQ16 Microinstruction Word 1 ~ ~5 .6 a7 . 6 1 1,I 1,. 151li "" SP*D ACCA CONTROL JASNTJ EX...result CALLSF 4F FA Call with ID in register GETSID 4F F9 Get re-time ID of function Data Forwarding FWD 4F F6 Forward integer DFWD 4F F5 Forward

Autonomous vehicle navigation utilizing fuzzy controls concepts for a next generation wheelchair.

PubMed

Hansen, J D; Barrett, S F; Wright, C H G; Wilcox, M

2008-01-01

Three different positioning techniques were investigated to create an autonomous vehicle that could accurately navigate towards a goal: Global Positioning System (GPS), compass dead reckoning, and Ackerman steering. Each technique utilized a fuzzy logic controller that maneuvered a four-wheel car towards a target. The reliability and the accuracy of the navigation methods were investigated by modeling the algorithms in software and implementing them in hardware. To implement the techniques in hardware, positioning sensors were interfaced to a remote control car and a microprocessor. The microprocessor utilized the sensor measurements to orient the car with respect to the target. Next, a fuzzy logic control algorithm adjusted the front wheel steering angle to minimize the difference between the heading and bearing. After minimizing the heading error, the car maintained a straight steering angle along its path to the final destination. The results of this research can be used to develop applications that require precise navigation. The design techniques can also be implemented on alternate platforms such as a wheelchair to assist with autonomous navigation.

369 TFlop/s molecular dynamics simulations on the Roadrunner general-purpose heterogeneous supercomputer

DOE Office of Scientific and Technical Information (OSTI.GOV)

Swaminarayan, Sriram; Germann, Timothy C; Kadau, Kai

2008-01-01

The authors present timing and performance numbers for a short-range parallel molecular dynamics (MD) code, SPaSM, that has been rewritten for the heterogeneous Roadrunner supercomputer. Each Roadrunner compute node consists of two AMD Opteron dual-core microprocessors and four PowerXCell 8i enhanced Cell microprocessors, so that there are four MPI ranks per node, each with one Opteron and one Cell. The interatomic forces are computed on the Cells (each with one PPU and eight SPU cores), while the Opterons are used to direct inter-rank communication and perform I/O-heavy periodic analysis, visualization, and checkpointing tasks. The performance measured for our initial implementationmore » of a standard Lennard-Jones pair potential benchmark reached a peak of 369 Tflop/s double-precision floating-point performance on the full Roadrunner system (27.7% of peak), corresponding to 124 MFlop/Watt/s at a price of approximately 3.69 MFlops/dollar. They demonstrate an initial target application, the jetting and ejection of material from a shocked surface.« less

DOE Office of Scientific and Technical Information (OSTI.GOV)

Underwood, Keith D; Ulmer, Craig D.; Thompson, David

Field programmable gate arrays (FPGAs) have been used as alternative computational de-vices for over a decade; however, they have not been used for traditional scientific com-puting due to their perceived lack of floating-point performance. In recent years, there hasbeen a surge of interest in alternatives to traditional microprocessors for high performancecomputing. Sandia National Labs began two projects to determine whether FPGAs wouldbe a suitable alternative to microprocessors for high performance scientific computing and,if so, how they should be integrated into the system. We present results that indicate thatFPGAs could have a significant impact on future systems. FPGAs have thepotentialtohave ordermore » of magnitude levels of performance wins on several key algorithms; however,there are serious questions as to whether the system integration challenge can be met. Fur-thermore, there remain challenges in FPGA programming and system level reliability whenusing FPGA devices.4 AcknowledgmentArun Rodrigues provided valuable support and assistance in the use of the Structural Sim-ulation Toolkit within an FPGA context. Curtis Janssen and Steve Plimpton provided valu-able insights into the workings of two Sandia applications (MPQC and LAMMPS, respec-tively).5« less

High-performance computing for airborne applications

DOE Office of Scientific and Technical Information (OSTI.GOV)

Quinn, Heather M; Manuzzato, Andrea; Fairbanks, Tom

2010-06-28

Recently, there has been attempts to move common satellite tasks to unmanned aerial vehicles (UAVs). UAVs are significantly cheaper to buy than satellites and easier to deploy on an as-needed basis. The more benign radiation environment also allows for an aggressive adoption of state-of-the-art commercial computational devices, which increases the amount of data that can be collected. There are a number of commercial computing devices currently available that are well-suited to high-performance computing. These devices range from specialized computational devices, such as field-programmable gate arrays (FPGAs) and digital signal processors (DSPs), to traditional computing platforms, such as microprocessors. Even thoughmore » the radiation environment is relatively benign, these devices could be susceptible to single-event effects. In this paper, we will present radiation data for high-performance computing devices in a accelerated neutron environment. These devices include a multi-core digital signal processor, two field-programmable gate arrays, and a microprocessor. From these results, we found that all of these devices are suitable for many airplane environments without reliability problems.« less

United States Air Force Research Initiation Program. 1984 Research Reports. Volume 1.

DTIC Science & Technology

1986-05-01

storage , several 8" floppy disk drives were substituteu; to gain the equivalent speed, an 8088 microprocessor faster than the Intel version and a 2-wegabyte... RAil .. cnory and ram-drive software were substituted. 2. Not included above is one item which was listed in the RISE proposal budget (the Z-204...FUSOIONCAL/JM. 280 REM C4IHEAT CAPACITYiCAL/GM-K. 2,90 C=0.46 00’ REM E1=ACTIVATION ENERGYiCAL /MOL. 3 2’ REM R-GAS CONSTANTiCAL/MOL-K. F!’ = 1. 9 B37 .* 3

Variable-Speed Instrumented Centrifuges

NASA Technical Reports Server (NTRS)

Chapman, David K.; Brown, Allan H.

1991-01-01

Report describes conceptual pair of centrifuges, speed of which varied to produce range of artificial gravities in zero-gravity environment. Image and data recording and controlled temperature and gravity provided for 12 experiments. Microprocessor-controlled centrifuges include video cameras to record stop-motion images of experiments. Potential applications include studies of effect of gravity on growth and on production of hormones in corn seedlings, experiments with magnetic flotation to separate cells, and electrophoresis to separate large fragments of deoxyribonucleic acid.

Supercritical water oxidation of products of human metabolism

NASA Technical Reports Server (NTRS)

Tester, Jefferson W.; Orge A. achelling, Richard K. ADTHOMASSON; Orge A. achelling, Richard K. ADTHOMASSON

1986-01-01

Although the efficient destruction of organic material was demonstrated in the supercritical water oxidation process, the reaction kinetics and mechanisms are unknown. The kinetics and mechanisms of carbon monoxide and ammonia oxidation in and reaction with supercritical water were studied experimentally. Experimental oxidation of urine and feces in a microprocessor controlled system was performed. A minaturized supercritical water oxidation process for space applications was design, including preliminary mass and energy balances, power, space and weight requirements.

Automatic Control and Data Acquisition System for Combustion Laboratory Applications.

DTIC Science & Technology

1982-10-01

O VPI Access~.ion FCr- 1473 2 UNCLASSIFIED Approved for public release; distribution unlimited JAutomatic Control and Data Acquisition System for...unit. The CPU/ROK board includes a 16 bit microprocessor chip which decodes and executes all in- structions, and controls all data transfers. The 12K...in the limited memory space of 32K of the HP-85 33 ACQDTA’ 1) Controls DevicesCRAIN ,2) Acquires Photodiods Output$ 3) Stores Data o Disc 1

Distributed Micro-Processor Applications to Guidance and Control Systems.

DTIC Science & Technology

1982-07-01

nanoseconds compared with 22 milliseconds for the older type of NMOS non-volatile RAM. This non-volatile RAM is estimated to hold its memory for 100 years...illustrated in figure 1.4.3.3 and compared with the traditional permalog chevron bubble structure. The contiguous element bubble structure is being developed ...M for its 8086 based Digital Advanced Avionics System (DAAS) developed for NASA Ames, but rejected it as being unsuitable. Ada is the new DoD

Electronic Dipstick

NASA Technical Reports Server (NTRS)

1991-01-01

Lake-Tronic's Negative Thermistor Coefficients (NTC) prevent engine nozzles in the Space Shuttle Orbiter from swinging from side to side changing the thrust line. This technology has been adapted to an Electronik Dipstick, used to automatically monitor automotive fluid levels. NTC's are placed at predetermined levels in the dipstick and heated. Contact with fluids dissipates the heat creating a resistance change, which is analyzed by a microprocessor. Installation is simple, and additional applications are under consideration. This product is no longer manufactured.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gebis, Joseph; Oliker, Leonid; Shalf, John

The disparity between microprocessor clock frequencies and memory latency is a primary reason why many demanding applications run well below peak achievable performance. Software controlled scratchpad memories, such as the Cell local store, attempt to ameliorate this discrepancy by enabling precise control over memory movement; however, scratchpad technology confronts the programmer and compiler with an unfamiliar and difficult programming model. In this work, we present the Virtual Vector Architecture (ViVA), which combines the memory semantics of vector computers with a software-controlled scratchpad memory in order to provide a more effective and practical approach to latency hiding. ViVA requires minimal changesmore » to the core design and could thus be easily integrated with conventional processor cores. To validate our approach, we implemented ViVA on the Mambo cycle-accurate full system simulator, which was carefully calibrated to match the performance on our underlying PowerPC Apple G5 architecture. Results show that ViVA is able to deliver significant performance benefits over scalar techniques for a variety of memory access patterns as well as two important memory-bound compact kernels, corner turn and sparse matrix-vector multiplication -- achieving 2x-13x improvement compared the scalar version. Overall, our preliminary ViVA exploration points to a promising approach for improving application performance on leading microprocessors with minimal design and complexity costs, in a power efficient manner.« less

Microprocessor controlled advanced battery management systems

NASA Technical Reports Server (NTRS)

Payne, W. T.

1978-01-01

The advanced battery management system described uses the capabilities of an on-board microprocessor to: (1) monitor the state of the battery on a cell by cell basis; (2) compute the state of charge of each cell; (3) protect each cell from reversal; (4) prevent overcharge on each individual cell; and (5) control dual rate reconditioning to zero volts per cell.

Nonanalytic function generation routines for 16-bit microprocessors

NASA Technical Reports Server (NTRS)

Soeder, J. F.; Shaufl, M.

1980-01-01

Interpolation techniques for three types (univariate, bivariate, and map) of nonanalytic functions are described. These interpolation techniques are then implemented in scaled fraction arithmetic on a representative 16 bit microprocessor. A FORTRAN program is described that facilitates the scaling, documentation, and organization of data for use by these routines. Listings of all these programs are included in an appendix.

Microcprocessing Computer Technician, Digital and Microprocessor Technician Program. Post-Graduate 5th Year.

ERIC Educational Resources Information Center

Carangelo, Pasquale R.; Janeczek, Anthony J.

Materials are provided for a two-semester digital and microprocessor technician postgraduate program. Prerequisites stated for the program include a background in DC and AC theory, solid state devices, basic circuit fundamentals, and basic math. A chronology of major topics and a listing of course objectives appear first. Theory outlines for each…

The Minerva Multi-Microprocessor.

DTIC Science & Technology

A multiprocessor system is described which is an experiment in low cost, extensible, multiprocessor architectures. Global issues such as inclusion of a central bus, design of the bus arbiter, and methods of interrupt handling are considered. The system initially includes two processor types, based on microprocessors, and these are discussed. Methods for reducing processor demand for the central bus are described.

Failure analysis on false call probe pins of microprocessor test equipment

NASA Astrophysics Data System (ADS)

Tang, L. W.; Ong, N. R.; Mohamad, I. S. B.; Alcain, J. B.; Retnasamy, V.

2017-09-01

A study has been conducted to investigate failure analysis on probe pins of test modules for microprocessor. The `health condition' of the probe pin is determined by the resistance value. A test module of 5V power supplied from Arduino UNO with "Four-wire Ohm measurement" method is implemented in this study to measure the resistance of the probe pins of a microprocessor. The probe pins from a scrapped computer motherboard is used as the test sample in this study. The functionality of the test module was validated with the pre-measurement experiment via VEE Pro software. Lastly, the experimental work have demonstrated that the implemented test module have the capability to identify the probe pin's `health condition' based on the measured resistance value.

A microcomputer-based position updating system for general aviation utilizing Loran-C

NASA Technical Reports Server (NTRS)

Fischer, J. P.

1982-01-01

Modern digital electronic technology is used to produce a device to convert LORAN C to useful pilot information using a simple software algebra and low cost microprocessor devices. Results indicate that the processor based LORAN C navigator has an accuracy of 1.0 nm or less over an area typically covered by a triad of Loran C stations and can execute a position update in less than 0.2 seconds. The system was tested in 30 hours of flight and proved that it can give reliable and accurate navigation information. Methods of converting time differences to position, design considerations for the microcomputer system, and the system for coordinate conversion are discussed. Testing with predetermined points and possible fixes for errors are also considered.

Efficient system interrupt concept design at the microprogramming level

DOE Office of Scientific and Technical Information (OSTI.GOV)

Fakharzadeh, M.M.

1989-01-01

Over the past decade the demand for high speed super microcomputers has been tremendously increased. To satisfy this demand many high speed 32-bit microcomputers have been designed. However, the currently available 32-bit systems do not provide an adequate solution to many highly demanding problems such as in multitasking, and in interrupt driven applications, which both require context switching. Systems for these purposes usually incorporate sophisticated software. In order to be efficient, a high end microprocessor based system must satisfy stringent software demands. Although these microprocessors use the latest technology in the fabrication design and run at a very high speed,more » they still suffer from insufficient hardware support for such applications. All too often, this lack also is the premier cause of execution inefficiency. In this dissertation a micro-programmable control unit and operation unit is considered in an advanced design. An automaton controller is designed for high speed micro-level interrupt handling. Different stack models are designed for the single task and multitasking environment. The stacks are used for storage of various components of the processor during the interrupt calls, procedure calls, and task switching. A universal (as an example seven port) register file is designed for high speed parameter passing, and intertask communication in the multitasking environment. In addition, the register file provides a direct path between ALU and the peripheral data which is important in real-time control applications. The overall system is a highly parallel architecture, with no pipeline and internal cache memory, which allows the designer to be able to predict the processor's behavior during the critical times.« less

Radiation Evaluation of the AM2901A Microprocessor.

DTIC Science & Technology

1980-08-01

Fitz , Jr. ATTN: DRDAR-LCA-PD 4 cy ATTN: TITL U.S. Army Communications R&D Command Field Command ATTN: D. Huewe Defense Nuclear Agency ATTN: FCPR U.S...Stahl ATTN: Technical Library ATTN: T. Flanagan Mission Research Corp, Santa Barbara Johns Hopkins University, Laurel ATTN: C. Longmire Applied...Bernardino Sperry Rand Corp, Phoenix ATTN: F. Fay ATTN: D. Schow ATTN: M. Gorman ATTN: P. Kitter Sperry Univac, St. Paul ATTN: J. Inda TRW Systems and

uSOP: A Microprocessor-Based Service-Oriented Platform for Control and Monitoring

NASA Astrophysics Data System (ADS)

Aloisio, Alberto; Ameli, Fabrizio; Anastasio, Antonio; Branchini, Paolo; Di Capua, Francesco; Giordano, Raffaele; Izzo, Vincenzo; Tortone, Gennaro

2017-06-01

uSOP is a general purpose single-board computer designed for deep embedded applications in control and monitoring of detectors, sensors, and complex laboratory equipment. In this paper, we present and discuss the main aspects of the hardware and software designs and the expandable peripheral architecture built around serial busses. We show the tests done with state-of-the-art ΔΣ 24-b ADC acquisition modules, in order to assess the achievable noise floor in a typical application. Eventually, we report on the deployment of uSOP in the monitoring system framework of the Belle2 experiment, presently under construction at the KEK Laboratory (Tsukuba, Japan).

Developing stereo image based robot control system

DOE Office of Scientific and Technical Information (OSTI.GOV)

Suprijadi,; Pambudi, I. R.; Woran, M.

Application of image processing is developed in various field and purposes. In the last decade, image based system increase rapidly with the increasing of hardware and microprocessor performance. Many fields of science and technology were used this methods especially in medicine and instrumentation. New technique on stereovision to give a 3-dimension image or movie is very interesting, but not many applications in control system. Stereo image has pixel disparity information that is not existed in single image. In this research, we proposed a new method in wheel robot control system using stereovision. The result shows robot automatically moves based onmore » stereovision captures.« less

The Use of a Microprocessor-Controlled, Video Output Atomic Absorption Spectrometer as an Educational Tool in a Two-Year Technical Curriculum.

ERIC Educational Resources Information Center

Kerfoot, Henry B.

Based on instructional experiences at Charles County Community College, Maryland, this report examines the pedagogical advantage of teaching atomic absorption (AA) spectroscopy with an AA spectrophotometer that is equipped with a microprocessor and video output mechanism. The report first discusses the growing importance of AA spectroscopy in…

[An integral chip for the multiphase pulse-duration modulation used for voltage changer in biomedical microprocessor systems].

PubMed

Balashov, A M; Selishchev, S V

2004-01-01

An integral chip (IC) was designed for controlling the step-down pulse voltage converter, which is based on the multiphase pulse-duration modulation, for use in biomedical microprocessor systems. The CMOS technology was an optimal basis for the IC designing. An additional feedback circuit diminishes the output voltage dispersion at dynamically changing loads.

Hardware Fault Simulator for Microprocessors

NASA Technical Reports Server (NTRS)

Hess, L. M.; Timoc, C. C.

1983-01-01

Breadboarded circuit is faster and more thorough than software simulator. Elementary fault simulator for AND gate uses three gates and shaft register to simulate stuck-at-one or stuck-at-zero conditions at inputs and output. Experimental results showed hardware fault simulator for microprocessor gave faster results than software simulator, by two orders of magnitude, with one test being applied every 4 microseconds.

Microprocessor control of photovoltaic systems

NASA Technical Reports Server (NTRS)

Millner, A. R.; Kaufman, D. L.

1984-01-01

The present low power CMOS microprocessor controller for photovoltaic power systems possesses three programs, which are respectively intended for (1) conventional battery-charging systems with state-of-charge estimation and sequential shedding of subarrays and loads, (2) maximum power-controlled battery-charging systems, and (3) variable speed dc motor drives. Attention is presently given to the development of this terrestrial equipment for spacecraft use.

Analysis of inadvertent microprocessor lag time on eddy covariance results

Treesearch

Karl Zeller; Gary Zimmerman; Ted Hehn; Evgeny Donev; Diane Denny; Jeff Welker

2001-01-01

Researchers using the eddy covariance approach to measuring trace gas fluxes are often hoping to measure carbon dioxide and energy fluxes for ecosystem intercomparisons. This paper demonstrates a systematic microprocessor- caused lag of 20.1 to 20.2 s in a commercial sonic anemometer-analog-to-digital datapacker system operated at 10 Hz. The result of the inadvertent...

A real-time implementation of an advanced sensor failure detection, isolation, and accommodation algorithm

NASA Technical Reports Server (NTRS)

Delaat, J. C.; Merrill, W. C.

1983-01-01

A sensor failure detection, isolation, and accommodation algorithm was developed which incorporates analytic sensor redundancy through software. This algorithm was implemented in a high level language on a microprocessor based controls computer. Parallel processing and state-of-the-art 16-bit microprocessors are used along with efficient programming practices to achieve real-time operation.

Mark IVA microprocessor support

NASA Technical Reports Server (NTRS)

Burford, A. L.

1982-01-01

The requirements and plans for the maintenance support of microprocessor-based controllers in the Deep Space Network Mark IVA System are discussed. Additional new interfaces and 16-bit processors have introduced problems not present in the Mark III System. The need for continuous training of maintenance personnel to maintain a level of expertise consistent with the sophistication of the required tools is also emphasized.

European Science Notes Information Bulletin Reports on Current European and Middle Eastern Science

DTIC Science & Technology

1992-01-01

evclopment in the Abbey-Polymer Processing and Properties ................... 524 J, Magill Corrosion and Protection Centre at the University of...34* Software Engineering and microprocessors and communication chips. The Information Processing Systems recently announced T9000 microprocessor will...computational fluid dynamics, struc- In addition to general and special-purpose tural mechanics, partial differential equations, processing , Europe has a

Transient Heat Conduction Simulation around Microprocessor Die

NASA Astrophysics Data System (ADS)

Nishi, Koji

This paper explains about fundamental formula of calculating power consumption of CMOS (Complementary Metal-Oxide-Semiconductor) devices and its voltage and temperature dependency, then introduces equation for estimating power consumption of the microprocessor for notebook PC (Personal Computer). The equation is applied to heat conduction simulation with simplified thermal model and evaluates in sub-millisecond time step calculation. In addition, the microprocessor has two major heat conduction paths; one is from the top of the silicon die via thermal solution and the other is from package substrate and pins via PGA (Pin Grid Array) socket. Even though the dominant factor of heat conduction is the former path, the latter path - from package substrate and pins - plays an important role in transient heat conduction behavior. Therefore, this paper tries to focus the path from package substrate and pins, and to investigate more accurate method of estimating heat conduction paths of the microprocessor. Also, cooling performance expression of heatsink fan is one of key points to assure result with practical accuracy, while finer expression requires more computation resources which results in longer computation time. Then, this paper discusses the expression to minimize computation workload with a practical accuracy of the result.

Deformability in the cleavage site of primary microRNA is not sensed by the double-stranded RNA binding domains in the microprocessor component DGCR8.

PubMed

Quarles, Kaycee A; Chadalavada, Durga; Showalter, Scott A

2015-06-01

The prevalence of double-stranded RNA (dsRNA) in eukaryotic cells has only recently been appreciated. Of interest here, RNA silencing begins with dsRNA substrates that are bound by the dsRNA-binding domains (dsRBDs) of their processing proteins. Specifically, processing of microRNA (miRNA) in the nucleus minimally requires the enzyme Drosha and its dsRBD-containing cofactor protein, DGCR8. The smallest recombinant construct of DGCR8 that is sufficient for in vitro dsRNA binding, referred to as DGCR8-Core, consists of its two dsRBDs and a C-terminal tail. As dsRBDs rarely recognize the nucleotide sequence of dsRNA, it is reasonable to hypothesize that DGCR8 function is dependent on the recognition of specific structural features in the miRNA precursor. Previously, we demonstrated that noncanonical structural elements that promote RNA flexibility within the stem of miRNA precursors are necessary for efficient in vitro cleavage by reconstituted Microprocessor complexes. Here, we combine gel shift assays with in vitro processing assays to demonstrate that neither the N-terminal dsRBD of DGCR8 in isolation nor the DGCR8-Core construct is sensitive to the presence of noncanonical structural elements within the stem of miRNA precursors, or to single-stranded segments flanking the stem. Extending DGCR8-Core to include an N-terminal heme-binding region does not change our conclusions. Thus, our data suggest that although the DGCR8-Core region is necessary for dsRNA binding and recruitment to the Microprocessor, it is not sufficient to establish the previously observed connection between RNA flexibility and processing efficiency. © 2015 Wiley Periodicals, Inc.

CAMAC: A Unique Application with a Pocket Terminal.

DTIC Science & Technology

1982-09-16

POCKET TERMINAL S. PERFORMING ORG. REPORT NUMSIER I. AUTWOR(o) S. CONTRACT OR GRANT NUMU41’e() A.D. Elmond S. PERFORMING ORGANIZATION NAME AND ADORIESS 10...port of any CAMAC crate. In addition to being a maintenance device, the HHTT is a " smart " device that can control operations in a CAMAC crate. The...system LSI 11/23 microprocessor through an Asynchronous Serial Port (ASP) interface module. This ASP interface consists of: 1) Crystal Clock 2) MIK -Bus

Miniature penetrator (MinPen) acceleration recorder development test

DOE Office of Scientific and Technical Information (OSTI.GOV)

Franco, R.J.; Platzbecker, M.R.

1998-08-01

The Telemetry Technology Development Department at Sandia National Laboratories actively develops and tests acceleration recorders for penetrating weapons. This new acceleration recorder (MinPen) utilizes a microprocessor-based architecture for operational flexibility while maintaining electronics and packaging techniques developed over years of penetrator testing. MinPen has been demonstrated to function in shock environments up to 20,000 Gs. The MinPen instrumentation development has resulted in a rugged, versatile, miniature acceleration recorder and is a valuable tool for penetrator testing in a wide range of applications.

Microcomputer programming skills

NASA Technical Reports Server (NTRS)

Barth, C. W.

1979-01-01

Some differences in skill and techniques required for conversion from programmer to microprogrammer are discussed. The primary things with which the programmer should work are hardware architecture, hardware/software trade off, and interfacing. The biggest differences, however, will stem from the differences in applications than from differences in machine size. The change to real-time programming is the most important of these differences, particularly on dedicated microprocessors. Another primary change is programming with a more computer-naive user in mind, and dealing with his limitations and expectations.

Photonic Integrated Circuits

NASA Technical Reports Server (NTRS)

Krainak, Michael; Merritt, Scott

2016-01-01

Integrated photonics generally is the integration of multiple lithographically defined photonic and electronic components and devices (e.g. lasers, detectors, waveguides passive structures, modulators, electronic control and optical interconnects) on a single platform with nanometer-scale feature sizes. The development of photonic integrated circuits permits size, weight, power and cost reductions for spacecraft microprocessors, optical communication, processor buses, advanced data processing, and integrated optic science instrument optical systems, subsystems and components. This is particularly critical for small spacecraft platforms. We will give an overview of some NASA applications for integrated photonics.

Intercommunications in Real Time, Redundant, Distributed Computer System

NASA Technical Reports Server (NTRS)

Zanger, H.

1980-01-01

An investigation into the applicability of fiber optic communication techniques to real time avionic control systems, in particular the total automatic flight control system used for the VSTOL aircraft is presented. The system consists of spatially distributed microprocessors. The overall control function is partitioned to yield a unidirectional data flow between the processing elements (PE). System reliability is enhanced by the use of triple redundancy. Some general overall system specifications are listed here to provide the necessary background for the requirements of the communications system.

ONR Workshop on Magnetohydrodynamic Submarine Propulsion (2nd), Held in San Diego, California on November 16-17, 1989

DTIC Science & Technology

1990-07-01

electrohtic dissociation of the electrode mate- pedo applications seem to be still somewhat rial, and to provide a good gas evolution wlhich out of the...rod cathode. A unique feature of this preliminary experiment was the use of a prototype gated, intensified video camera. This camera is based on a...microprocessor controlled microchannel plate intensifier tube. The intensifier tube image is focused on a standard CCD video camera so that the object

Integrating Software Modules For Robot Control

NASA Technical Reports Server (NTRS)

Volpe, Richard A.; Khosla, Pradeep; Stewart, David B.

1993-01-01

Reconfigurable, sensor-based control system uses state variables in systematic integration of reusable control modules. Designed for open-architecture hardware including many general-purpose microprocessors, each having own local memory plus access to global shared memory. Implemented in software as extension of Chimera II real-time operating system. Provides transparent computing mechanism for intertask communication between control modules and generic process-module architecture for multiprocessor realtime computation. Used to control robot arm. Proves useful in variety of other control and robotic applications.

Manned maneuvering unit technology survey

NASA Technical Reports Server (NTRS)

Cook, G. V. O. (Editor)

1975-01-01

The preliminary design of the manned maneuvering unit (MMU) for the shuttle is investigated, and the current state of the art in certain technology areas that may find application on the operational EVA shuttle MMU is examined. Three broad areas of technology, namely: (1) mechanical energy storage - i.e., the practicality of utilizing the energy storage capability of either a reaction wheel or a control moment gyro, (2) numerical and alphanumerical displays, and (3) recent electronics developments such as microprocessors and integrated injection logic, were covered.

A PWM transistor inverter for an ac electric vehicle drive

NASA Technical Reports Server (NTRS)

Slicker, J. M.

1981-01-01

A prototype system consisting of closely integrated motor, inverter, and transaxle has been built in order to demonstrate the feasibility of a three-phase ac transistorized inverter for electric vehicle applications. The microprocessor-controlled inverter employs monolithic power transistors to drive an oil-cooled, three-phase induction traction motor at a peak output power of 30 kW from a 144 V battery pack. Transistor safe switching requirements are discussed, and a circuit is presented for recovering trapped snubber inductor energy at transistor turn-off.

Real-time fetal ECG system design using embedded microprocessors

NASA Astrophysics Data System (ADS)

Meyer-Baese, Uwe; Muddu, Harikrishna; Schinhaerl, Sebastian; Kumm, Martin; Zipf, Peter

2016-05-01

The emphasis of this project lies in the development and evaluation of new robust and high fidelity fetal electrocardiogram (FECG) systems to determine the fetal heart rate (FHR). Recently several powerful algorithms have been suggested to improve the FECG fidelity. Until now it is unknown if these algorithms allow a real-time processing, can be used in mobile systems (low power), and which algorithm produces the best error rate for a given system configuration. In this work we have developed high performance, low power microprocessor-based biomedical systems that allow a fair comparison of proposed, state-of-the-art FECG algorithms. We will evaluate different soft-core microprocessors and compare these solutions to other commercial off-the-shelf (COTS) hardcore solutions in terms of price, size, power, and speed.

A microprocessor-based position control system for a telescope secondary mirror

NASA Technical Reports Server (NTRS)

Lorell, K. R.; Barrows, W. F.; Clappier, R. R.; Lee, G. K.

1983-01-01

The pointing requirements for the Shuttle IR Telescope Facility (SIRTF), which consists of an 0.85-m cryogenically cooled IR telescope, call for an image stability of 0.25 arcsec. Attention is presently given to a microprocessor-based position control system developed for the control of the SIRTF secondary mirror, employing a special control law (to minimize energy dissipation), a precision capacitive position sensor, and a specially designed power amplifier/actuator combination. The microprocessor generates the command angular position and rate waveforms in order to maintain a 90 percent dwell time/10 percent transition time ratio independently of chop frequency or amplitude. Performance and test results of a prototype system designed for use with a demonstration model of the SIRTF focal plane fine guidance sensor are presented.

A Decade of Neural Networks: Practical Applications and Prospects

NASA Technical Reports Server (NTRS)

Kemeny, Sabrina E.

1994-01-01

The Jet Propulsion Laboratory Neural Network Workshop, sponsored by NASA and DOD, brings together sponsoring agencies, active researchers, and the user community to formulate a vision for the next decade of neural network research and application prospects. While the speed and computing power of microprocessors continue to grow at an ever-increasing pace, the demand to intelligently and adaptively deal with the complex, fuzzy, and often ill-defined world around us remains to a large extent unaddressed. Powerful, highly parallel computing paradigms such as neural networks promise to have a major impact in addressing these needs. Papers in the workshop proceedings highlight benefits of neural networks in real-world applications compared to conventional computing techniques. Topics include fault diagnosis, pattern recognition, and multiparameter optimization.

Formal design specification of a Processor Interface Unit

NASA Technical Reports Server (NTRS)

Fura, David A.; Windley, Phillip J.; Cohen, Gerald C.

1992-01-01

This report describes work to formally specify the requirements and design of a processor interface unit (PIU), a single-chip subsystem providing memory-interface bus-interface, and additional support services for a commercial microprocessor within a fault-tolerant computer system. This system, the Fault-Tolerant Embedded Processor (FTEP), is targeted towards applications in avionics and space requiring extremely high levels of mission reliability, extended maintenance-free operation, or both. The need for high-quality design assurance in such applications is an undisputed fact, given the disastrous consequences that even a single design flaw can produce. Thus, the further development and application of formal methods to fault-tolerant systems is of critical importance as these systems see increasing use in modern society.

Application of fuzzy logic to the control of wind tunnel settling chamber temperature

NASA Technical Reports Server (NTRS)

Gwaltney, David A.; Humphreys, Gregory L.

1994-01-01

The application of Fuzzy Logic Controllers (FLC's) to the control of nonlinear processes, typically controlled by a human operator, is a topic of much study. Recent application of a microprocessor-based FLC to the control of temperature processes in several wind tunnels has proven to be very successful. The control of temperature processes in the wind tunnels requires the ability to monitor temperature feedback from several points and to accommodate varying operating conditions in the wind tunnels. The FLC has an intuitive and easily configurable structure which incorporates the flexibility required to have such an ability. The design and implementation of the FLC is presented along with process data from the wind tunnels under automatic control.

A Flight Investigation of Digital Control Using Microprocessor Technology.

DTIC Science & Technology

1979-06-01

software development system (Fig. 3-4) allow programs to be entered and tested efficiently. The ground chasis 3-7 pF MIRO -DFCS HOUSING I ANALOG...6E/V .125 06 La/V Lca/V/10 .200 07 L /V 100 LV/V .200 V 08 Step Gust .100 Scaling 10 D-VT V.073 11 Da-g Da.g/10o .060 12 g g/100 . 322 13 Vscale 1003x

Electronics Industry Study Report: Semiconductors and Defense Electronics

DTIC Science & Technology

2003-01-01

Access Memory (DRAM) chips and microprocessors. Samsung , Micron, Hynix, and Infineon control almost three-fourths of the DRAM market,8 while Intel alone...Country 2001 Sales ($B) 2002 Sales ($B) % Change % 2002 Mkt 1 1 Intel U.S. 23.7 24.0 1% 16.9% 2 3 Samsung Semiconductor S. Korea 6.3...located in four major regions: the United States, Europe, Japan, and the Asia-Pacific region (includes South Korea, China, Singapore, Malaysia , Taiwan

Comparison of mobility and user satisfaction between a microprocessor knee and a standard prosthetic knee: a summary of seven single-subject trials.

PubMed

Howard, Charla L; Wallace, Chris; Perry, Bonnie; Stokic, Dobrivoje S

2018-03-01

Insufficient evidence of the benefits provided by costlier microprocessor knees (MPKs) over nonmicroprocessor knees (NMPKs) often causes concern when considering MPK prescription. Thus, more studies are needed to demonstrate differences between MPKs and NMPKs and define sensitive outcomes to guide MPK prescription. The aim of this study was to evaluate the impact of switching from NMPK to MPK on measures of mobility and preference. Seven long-term NMPK users (all men, ages 50-84, 3-64 years postamputation) participated in this study, which use a single-subject design (ABA or BAB; A=NMPK, B=MPK). Mobility was assessed with the Amputee Mobility Predictor, Berg Balance Scale (BBS), L-Test, 6-Min Walk Test (6MWT) with Physiological Cost Index, and self-selected normal and very fast gait speeds. The preference between NMPK and MPK was evaluated by the Prosthesis Evaluation Questionnaire (PEQ) and the visual analog scale. Mobility improved with the MPK in six of seven participants, which was most often captured with BBS (median: +6 points) and 6MWT (median: +63 m). These improvements typically exceeded minimal clinically important difference or minimal detectable change thresholds. Most participants scored the MPK higher on the PEQ (median: +20 points) and six of seven expressed a global preference toward MPK. In the BAB group, the Amputee Mobility Predictor and BBS correlated with perception of change on several PEQ domains (Ρ≥0.59). In conclusion, MPKs may provide better outcomes and user satisfaction, particularly in those with lower mobility function. BBS and 6MWT were found to be the most sensitive measures to capture changes in mobility while using MPK for several weeks.

Microprocessor in controlled transdermal drug delivery of anti-cancer drugs.

PubMed

Chandrashekar, N S; Shobha Rani, R H

2009-12-01

Microprocessor controlled transdermal delivery of anticancer drugs 5-Fluorouracil (5-FU) and 6-Mercaptopurine (6-MP) was developed and in vitro evaluation was done. Drugs were loaded based on the pharmacokinetics parameters. In vitro diffusion studies were carried at different current density (0.0, 0.1, 0.22, 0.50 mA/cm2). The patches were evaluated for the drug content, thickness, weight, folding endurance, flatness, thumb tack test and adhesive properties all were well with in the specification of transdermal patches with elegant and transparent in appearance. In vitro permeation studies through human cadaver skin showed, passive delivery (0.0 mA/cm2) of 6-MP was low. As the current density was progressively increased, the flux also increased. the flux also increased with 0.1 mA/cm2 for 15-20 min, but it was less than desired flux, 0.2 mA/cm2 for 30 min showed better flux than 0.1 mA/cm2 current, but lag time was more than 4 h, 0.5 mA/cm2 current for more than 1 h, flux was >159 microg/cm2 h which was desired flux for 6-MP. 5-FU flux reached the minimum effective concentration (MEC) of 54 microg/cm2 h with 0.5 mA/cm2 current for 30-45 min, drug concentration were within the therapeutic window in post-current phase. We concluded from Ohm's Law that as the resistance decreases, current increases. Skin resistance decrease with increase in time and current, increase in the drug permeation. Interestingly, for all investigated current densities, as soon as the current was switched off, 5-FU and 6-MP flux decreased fairly, but the controlled drug delivery can be achieved by switching the current for required period of time.

A Microprocessor-Controlled Data Acquisition System for the Federal Scientific Model UA-500-1 Ubiquitous Spectrum Analyzer

DTIC Science & Technology

1976-09-01

Model AN/ UGC -59A teletype and paper-tape punch console. This unit is connected with the Intellec 8 computer and punching operations are controlled by...order to use this program, the microprocessor would have to be one of the many types on the market that make use of the INTEL 8008-1 CPD chip. The use

Design of a Distributed Microprocessor Sensor System

DTIC Science & Technology

1990-04-01

implemented through these methods, multiversion software and recovery the use of multiple identical software tasks running on blocks, are intended to... Multiversion software for real-time systems tolerant microprocessor that uses three processing is discussed by Shepherd32, Hitt33, Avizienis’, and...tasks and the there are no data available to determine the cost third is used for noncritical tasks. If a discrepancy effectiveness of multiversion

A microprocessor-based system for continuous monitoring of radiation levels around the CERN PS and PSB accelerators

NASA Astrophysics Data System (ADS)

Agoritsas, V.; Beck, F.; Benincasa, G. P.; Bovigny, J. P.

1986-06-01

This paper describes a new beam loss monitor system which has been installed in the PS and PSB machines, replacing an earlier system. The new system is controlled by a microprocessor which can operate independently of the accelerator control system, though setting up and central display are usually done remotely, using the standard control system facilities.

Microprocessor controlled transdermal drug delivery.

PubMed

Subramony, J Anand; Sharma, Ashutosh; Phipps, J B

2006-07-06

Transdermal drug delivery via iontophoresis is reviewed with special focus on the delivery of lidocaine for local anesthesia and fentanyl for patient controlled acute therapy such as postoperative pain. The role of the microprocessor controller in achieving dosimetry, alternating/reverse polarity, pre-programmed, and sensor-based delivery is highlighted. Unique features such as the use of tactile signaling, telemetry control, and pulsatile waveforms in iontophoretic drug delivery are described briefly.

A central microprocessor controlled electrical storage heating system

NASA Astrophysics Data System (ADS)

Horstmann, H.

1980-12-01

The use of a microprocessor to control the reloading of electrical storage heaters not only during the night, but whenever the electrical grid is cycled down, was tested. The test setup, used to control a total of about 10 MW installed storage heating in 96 dwellings, is described. It is demonstrated that additional consumers can be connected to the system without demand for more power stations.

The Single Event Effect Characteristics of the 486-DX4 Microprocessor

NASA Technical Reports Server (NTRS)

Kouba, Coy; Choi, Gwan

1996-01-01

This research describes the development of an experimental radiation testing environment to investigate the single event effect (SEE) susceptibility of the 486-DX4 microprocessor. SEE effects are caused by radiation particles that disrupt the logic state of an operating semiconductor, and include single event upsets (SEU) and single event latchup (SEL). The relevance of this work can be applied directly to digital devices that are used in spaceflight computer systems. The 486-DX4 is a powerful commercial microprocessor that is currently under consideration for use in several spaceflight systems. As part of its selection process, it must be rigorously tested to determine its overall reliability in the space environment, including its radiation susceptibility. The goal of this research is to experimentally test and characterize the single event effects of the 486-DX4 microprocessor using a cyclotron facility as the fault-injection source. The test philosophy is to focus on the "operational susceptibility," by executing real software and monitoring for errors while the device is under irradiation. This research encompasses both experimental and analytical techniques, and yields a characterization of the 486-DX4's behavior for different operating modes. Additionally, the test methodology can accommodate a wide range of digital devices, such as microprocessors, microcontrollers, ASICS, and memory modules, for future testing. The goals were achieved by testing with three heavy-ion species to provide different linear energy transfer rates, and a total of six microprocessor parts were tested from two different vendors. A consistent set of error modes were identified that indicate the manner in which the errors were detected in the processor. The upset cross-section curves were calculated for each error mode, and the SEU threshold and saturation levels were identified for each processor. Results show a distinct difference in the upset rate for different configurations of the on-chip cache, as well as proving that one vendor is superior to the other in terms of latchup susceptibility. Results from this testing were also used to provide a mean-time-between-failure estimate of the 486-DX4 operating in the radiation environment for the International Space Station.

Design considerations for a LORAN-C timing receiver in a hostile signal to noise environment

NASA Technical Reports Server (NTRS)

Porter, J. W.; Bowell, J. R.; Price, G. E.

1981-01-01

The environment in which a LORAN-C Timing Receiver may function effectively depends to a large extent on the techniques utilized to insure that interfering signals within the pass band of the unit are neutralized. The baseline performance manually operated timing receivers is discussed and the basic design considerations and necessary parameters for an automatic unit utilizing today's technology are established. Actual performance data is presented comparing the results obtained from a present generation timing receiver against a new generation microprocessor controlled automatic acquisition receiver. The achievements possible in a wide range of signal to noise situations are demonstrated.

A micro-computer-based system to compute magnetic variation

NASA Technical Reports Server (NTRS)

Kaul, Rajan

1987-01-01

A mathematical model of magnetic variation in the continental United States was implemented in the Ohio University Loran-C receiver. The model is based on a least squares fit of a polynomial function. The implementation on the microprocessor based Loran-C receiver is possible with the help of a math chip which performs 32 bit floating point mathematical operations. A Peripheral Interface Adapter is used to communicate between the 6502 based microcomputer and the 9511 math chip. The implementation provides magnetic variation data to the pilot as a function of latitude and longitude. The model and the real time implementation in the receiver are described.

American power conference: Proceedings

DOE Office of Scientific and Technical Information (OSTI.GOV)

Not Available

1994-01-01

The first volume of this conference contains papers on the following topics: (1) Controls, monitoring, and expert systems (Harnessing microprocessor revolution for a more competitive power industry; Plant control--Upgrades; Neural network applications); (2) Diversification and globalization (Electric utility diversification/globalization--Panel; Private power in developing countries); (3) Environment and clean air (Clean Air compliance costs; Site selection for power stations and related facilities; Electric utility trace substance emissions; Solid waste disposal and commercial use; Precipitators/fabric filters; and Effect of flow modifications on fisheries and water quality); (4) Generation--Fuel options equipment (Alternate fuels; Advances in fuel cells for electric power applications; Secondary containmentmore » and seismic requirements for petrochemical facilities; Clean coal technology demonstration; Advanced energy systems; Hydropower); (5) Nuclear operations options (Radioactive waste management and disposal; Off normal conditions; Advanced light water reactors--15 years after TMI; Structural dynamic analyses for nuclear power plants); (6) Retrofit, betterment, repowering maintenance (Project management; Improving competitiveness through process re-engineering; Central stations; Water and wastewater treatment); (7) System planning, operation demand maintenance (Transmission system access; Stability; Systems planning); (8) Transmission and distribution (Transformers; Relaying for system protection; Managing EMF effects); and (9) Education (Power engineering). 155 papers have been processed separately for inclusion on the data base.« less

Architecture design of the multi-functional wavelet-based ECG microprocessor for realtime detection of abnormal cardiac events.

PubMed

Cheng, Li-Fang; Chen, Tung-Chien; Chen, Liang-Gee

2012-01-01

Most of the abnormal cardiac events such as myocardial ischemia, acute myocardial infarction (AMI) and fatal arrhythmia can be diagnosed through continuous electrocardiogram (ECG) analysis. According to recent clinical research, early detection and alarming of such cardiac events can reduce the time delay to the hospital, and the clinical outcomes of these individuals can be greatly improved. Therefore, it would be helpful if there is a long-term ECG monitoring system with the ability to identify abnormal cardiac events and provide realtime warning for the users. The combination of the wireless body area sensor network (BASN) and the on-sensor ECG processor is a possible solution for this application. In this paper, we aim to design and implement a digital signal processor that is suitable for continuous ECG monitoring and alarming based on the continuous wavelet transform (CWT) through the proposed architectures--using both programmable RISC processor and application specific integrated circuits (ASIC) for performance optimization. According to the implementation results, the power consumption of the proposed processor integrated with an ASIC for CWT computation is only 79.4 mW. Compared with the single-RISC processor, about 91.6% of the power reduction is achieved.

A rocket-borne microprocessor-based experiment for investigation of energetic particles in the D and E regions

NASA Technical Reports Server (NTRS)

Braswell, F. M.

1981-01-01

An energetic experiment using the Z80 family of microcomputer components is described. Data collected from the experiment allowed fast and efficient postprocessing, yielding both energy-spectrum and pitch-angle distribution of energetic particles in the D and E regions. Advanced microprocessor system architecture and software concepts were used in the design to cope with the large amount of data being processed. This required the Z80 system to operate at over 80% of its total capacity. The microprocessor system was included in the payloads of three rockets launched during the Energy Budget Campaign at ESRANGE, Kiruna, Sweden in November 1980. Based on preliminary examination of the data, the performance of the experiment was satisfactory and good data were obtained on the energy spectrum and pitch-angle distribution of the particles.

Control methodologies for large space structures

NASA Technical Reports Server (NTRS)

Mcree, G. J.; Altonji, E.

1984-01-01

The objectives of this research were to develop techniques of controlling a dc-motor driven flywheel which would apply torque to the structure to which it was mounted. The motor control system was to be implemented using a microprocessor based controller. The purpose of the torque applied by this system was to dampen oscillations of the structure to which it was mounted. Before the work was terminated due to the unavailability of equipment, a system was developed and partially tested which would provide tight control of the flywheel velocity when it received a velocity command in the form of a voltage. The procedure followed in this development was to first model the motor and flywheel system on an analog computer. Prior to the time the microprocessor development system was available, an analog control loop was replaced by the microprocessor and the system was partially tested.

A rocket-borne pulse-height analyzer for energetic particle measurements

NASA Technical Reports Server (NTRS)

Leung, W.; Smith, L. G.; Voss, H. D.

1979-01-01

The pulse-height analyzer basically resembles a time-sharing multiplexing data-acquisition system which acquires analog data (from energetic particle spectrometers) and converts them into digital code. The PHA simultaneously acquires pulse-height information from the analog signals of the four input channels and sequentially multiplexes the digitized data to a microprocessor. The PHA together with the microprocessor form an on-board real-time data-manipulation system. The system processes data obtained during the rocket flight and reduces the amount of data to be sent back to the ground station. Consequently the data-reduction process for the rocket experiments is speeded up. By using a time-sharing technique, the throughput rate of the microprocessor is increased. Moreover, data from several particle spectrometers are manipulated to share one information channel; consequently, the TM capacity is increased.

A programmable heater control circuit for spacecraft

NASA Technical Reports Server (NTRS)

Nguyen, D. D.; Owen, J. W.; Smith, D. A.; Lewter, W. J.

1994-01-01

Spacecraft thermal control is accomplished for many components through use of multilayer insulation systems, electrical heaters, and radiator systems. The heaters are commanded to maintain component temperatures within design specifications. The programmable heater control circuit (PHCC) was designed to obtain an effective and efficient means of spacecraft thermal control. The hybrid circuit provides use of control instrumentation as temperature data, available to the spacecraft central data system, reprogramming capability of the local microprocessor during the spacecraft's mission, and the elimination of significant spacecraft wiring. The hybrid integrated circuit has a temperature sensing and conditioning circuit, a microprocessor, and a heater power and control circuit. The device is miniature and housed in a volume which allows physical integration with the component to be controlled. Applications might include alternate battery-powered logic-circuit configurations. A prototype unit with appropriate physical and functional interfaces was procured for testing. The physical functionality and the feasibility of fabrication of the hybrid integrated circuit were successfully verified. The remaining work to develop a flight-qualified device includes fabrication and testing of a Mil-certified part. An option for completing the PHCC flight qualification testing is to enter into a joint venture with industry.

GPS/MEMS IMU/Microprocessor Board for Navigation

NASA Technical Reports Server (NTRS)

Gender, Thomas K.; Chow, James; Ott, William E.

2009-01-01

A miniaturized instrumentation package comprising a (1) Global Positioning System (GPS) receiver, (2) an inertial measurement unit (IMU) consisting largely of surface-micromachined sensors of the microelectromechanical systems (MEMS) type, and (3) a microprocessor, all residing on a single circuit board, is part of the navigation system of a compact robotic spacecraft intended to be released from a larger spacecraft [e.g., the International Space Station (ISS)] for exterior visual inspection of the larger spacecraft. Variants of the package may also be useful in terrestrial collision-detection and -avoidance applications. The navigation solution obtained by integrating the IMU outputs is fed back to a correlator in the GPS receiver to aid in tracking GPS signals. The raw GPS and IMU data are blended in a Kalman filter to obtain an optimal navigation solution, which can be supplemented by range and velocity data obtained by use of (l) a stereoscopic pair of electronic cameras aboard the robotic spacecraft and/or (2) a laser dynamic range imager aboard the ISS. The novelty of the package lies mostly in those aspects of the design of the MEMS IMU that pertain to controlling mechanical resonances and stabilizing scale factors and biases.

Update on radiation-hardened microcomputers for robotics and teleoperated systems

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sias, F.R. Jr.; Tulenko, J.S.

1993-12-31

Since many programs sponsored by the Department of Defense are being canceled, it is important to select carefully radiation-hardened microprocessors for projects that will mature (or will require continued support) several years in the future. At the present time there are seven candidate 32-bit processors that should be considered for long-range planning for high-performance radiation-hardened computer systems. For Department of Energy applications it is also important to consider efforts at standardization that require the use of the VxWorks operating system and hardware based on the VMEbus. Of the seven processors, one has been delivered and is operating and other systemsmore » are scheduled to be delivered late in 1993 or early in 1994. At the present time the Honeywell-developed RH32, the Harris RH-3000 and the Harris RHC-3000 are leading contenders for meeting DOE requirements for a radiation-hardened advanced 32-bit microprocessor. These are all either compatible with or are derivatives of the MIPS R3000 Reduced Instruction Set Computer. It is anticipated that as few as two of the seven radiation-hardened processors will be supported by the space program in the long run.« less

Importance of balanced architectures in the design of high-performance imaging systems

NASA Astrophysics Data System (ADS)

Sgro, Joseph A.; Stanton, Paul C.

1999-03-01

Imaging systems employed in demanding military and industrial applications, such as automatic target recognition and computer vision, typically require real-time high-performance computing resources. While high- performances computing systems have traditionally relied on proprietary architectures and custom components, recent advances in high performance general-purpose microprocessor technology have produced an abundance of low cost components suitable for use in high-performance computing systems. A common pitfall in the design of high performance imaging system, particularly systems employing scalable multiprocessor architectures, is the failure to balance computational and memory bandwidth. The performance of standard cluster designs, for example, in which several processors share a common memory bus, is typically constrained by memory bandwidth. The symptom characteristic of this problem is failure to the performance of the system to scale as more processors are added. The problem becomes exacerbated if I/O and memory functions share the same bus. The recent introduction of microprocessors with large internal caches and high performance external memory interfaces makes it practical to design high performance imaging system with balanced computational and memory bandwidth. Real word examples of such designs will be presented, along with a discussion of adapting algorithm design to best utilize available memory bandwidth.

European Scientific Notes. Volume 35, Number 12,

DTIC Science & Technology

1981-12-31

been redesigned to work A. Osorio, which was organized some 3 with the Intel 8085 microprocessor, it years ago and contains about half of the has the...operational set. attempt to derive a set of invariants MOISE is based on the Intel 8085A upon which virtually speaker-invariant microprocessor, and...FACILITY software interface; a Research Signal Processor (RSP) using reduced computational It has been IBM International’s complexity algorithms for

Radiation Test Results for Common CubeSat Microcontrollers and Microprocessors

NASA Technical Reports Server (NTRS)

Guertin, Steven M.; Amrbar, Mehran; Vartanian, Sergeh

2015-01-01

SEL, SEU, and TID results are presented for microcontrollers and microprocessors of interest for small satellite systems such as the TI MSP430F1611, MSP430F1612 and MSP430FR5739, Microchip PIC24F256GA110 and dsPIC33FJ256GP710, Atmel AT91SAM9G20, and Intel Atom E620T, and the Qualcomm Snapdragon APQ8064.

FEDS - An experiment with a microprocessor-based orbit determination system using TDRS data

NASA Technical Reports Server (NTRS)

Shank, D.; Pajerski, R.

1986-01-01

An experiment in microprocessor-based onboard orbit determination has been conducted at NASA's Goddard Space Flight Center. The experiment collected forward-link observation data in real time from a prototype transponder and performed orbit estimation on a typical low-earth scientific satellite. This paper discusses the hardware and organizational configurations of the experiment, the structure of the onboard software, the mathematical models, and the experiment results.

Industry Study, Electronics Industry, Spring 2009

DTIC Science & Technology

2009-01-01

Toshiba, Samsung , and NEC.7 The microprocessor is a central processing unit containing hundreds of millions of transistors and logic to perform...business with an 11.7% market share followed closely by Samsung with a 10.3% market share.40 Intel is the leader in the production of microprocessors...while Samsung is the leading memory chip producer. Other US chip manufacturers include Texas Instruments (TI), Advanced Micro Devices (AMD), Micron

Microprocessor-based cardiotachometer

NASA Technical Reports Server (NTRS)

Crosier, W. G.; Donaldson, J. A.

1981-01-01

Instrument operates reliably even with stress-test electrocardiogram (ECG) signals subject to noise, baseline wandering, and amplitude change. It records heart rate from preamplified, single-lead ECG input signal and produces digital and analog heart-rate outputs which are fed elsewhere. Analog hardware processes ECG input signal, producing 10-ms pulse for each heartbeat. Microprocessor analyzes resulting pulse train, identifying irregular heartbeats and maintaining stable output during lead switching. Easily modified computer program provides analysis.

Optical detector calibrator system

NASA Technical Reports Server (NTRS)

Strobel, James P. (Inventor); Moerk, John S. (Inventor); Youngquist, Robert C. (Inventor)

1996-01-01

An optical detector calibrator system simulates a source of optical radiation to which a detector to be calibrated is responsive. A light source selected to emit radiation in a range of wavelengths corresponding to the spectral signature of the source is disposed within a housing containing a microprocessor for controlling the light source and other system elements. An adjustable iris and a multiple aperture filter wheel are provided for controlling the intensity of radiation emitted from the housing by the light source to adjust the simulated distance between the light source and the detector to be calibrated. The geared iris has an aperture whose size is adjustable by means of a first stepper motor controlled by the microprocessor. The multiple aperture filter wheel contains neutral density filters of different attenuation levels which are selectively positioned in the path of the emitted radiation by a second stepper motor that is also controlled by the microprocessor. An operator can select a number of detector tests including range, maximum and minimum sensitivity, and basic functionality. During the range test, the geared iris and filter wheel are repeatedly adjusted by the microprocessor as necessary to simulate an incrementally increasing simulated source distance. A light source calibration subsystem is incorporated in the system which insures that the intensity of the light source is maintained at a constant level over time.

Low-power circuits design for the wireless force measurement system of the total knee arthroplasty.

PubMed

Chen, Hong; Liu, Ming; Wan, Weiyi; Jia, Chen; Zhang, Chun; Wang, Zihua

2010-01-01

This paper proposes a novel wireless force measurement system for the Total Knee Arthroplasty (TKA) to improve the ligament balancing procedure during TKA. The force measurement system is comprised of a Wireless Force Measurement Spacer (WFMS) and the display part. They communicate with each other by the Radio Frequency (RF) signal. The WFMS is designed to measure the force between the WFMS and the femoral component of the artificial implants and to transmit the force data wirelessly by a low power transceiver. The display part demonstrates the force data in 3D images in real time. The WFMS composes of a sensors array, a Universal Transducer Interfaces (UTIs) array, a low-power sub-threshold microprocessor and a transceiver. The sub-threshold 8-bit microprocessor is taped out with 0.18 microm CMOS technology. The testing results of the microprocessor show that the leakage power of 46nW and the dynamic power of 385nW@165kHz are achieved with the operating voltage of 350 mV. The test results of the system are given and the errors of the system are analyzed. The results verified the reliability of the system. The future work is to design the microprocessor and a lower power transceiver within a single chip.

Association of a peptoid ligand with the apical loop of pri-miR-21 inhibits cleavage by Drosha

PubMed Central

Diaz, Jason P.; Chirayil, Rachel; Chirayil, Sara; Tom, Martin; Head, Katie J.; Luebke, Kevin J.

2014-01-01

We have found a small molecule that specifically inhibits cleavage of a precursor to the oncogenic miRNA, miR-21, by the microprocessor complex of Drosha and DGCR8. We identified novel ligands for the apical loop of this precursor from a screen of 14,024 N-substituted oligoglycines (peptoids) in a microarray format. Eight distinct compounds with specific affinity were obtained, three having affinities for the targeted loop in the low micromolar range and greater than 15-fold discrimination against a closely related hairpin. One of these compounds completely inhibits microprocessor cleavage of a miR-21 primary transcript at concentrations at which cleavage of another miRNA primary transcript, pri-miR-16, is little affected. The apical loop of pri-miR-21, placed in the context of pri-miR-16, is sufficient for inhibition of microprocessor cleavage by the peptoid. This compound also inhibits cleavage of pri-miR-21 containing the pri-miR-16 apical loop, suggesting an additional site of association within pri-miR-21. The reported peptoid is the first example of a small molecule that inhibits microprocessor cleavage by binding to the apical loop of a pri-miRNA. PMID:24497550

Vehicle safety telemetry for automated highways

NASA Technical Reports Server (NTRS)

Hansen, G. R.

1977-01-01

The emphasis in current, automatic vehicle testing and diagnosis is primarily centered on the proper operation of the engine. Lateral and longitudinal guidance technologies, including speed control and headway sensing for collision avoidance, are reviewed. The principal guidance technique remains the buried wire. Speed control and headway sensing, even though they show the same basic elements in braking and fuel systems, are proceeding independently. The applications of on-board electronic and microprocessor techniques were investigated; each application (emission control, spark advance, or anti-slip braking) is being treated as an independent problem is proposed. A unified bus system of distributed processors for accomplishing the various functions and testing required for vehicles equipped to use automated highways.

Dynamically Reconfigurable Systolic Array Accelerator

NASA Technical Reports Server (NTRS)

Dasu, Aravind; Barnes, Robert

2012-01-01

A polymorphic systolic array framework has been developed that works in conjunction with an embedded microprocessor on a field-programmable gate array (FPGA), which allows for dynamic and complimentary scaling of acceleration levels of two algorithms active concurrently on the FPGA. Use is made of systolic arrays and a hardware-software co-design to obtain an efficient multi-application acceleration system. The flexible and simple framework allows hosting of a broader range of algorithms, and is extendable to more complex applications in the area of aerospace embedded systems. FPGA chips can be responsive to realtime demands for changing applications needs, but only if the electronic fabric can respond fast enough. This systolic array framework allows for rapid partial and dynamic reconfiguration of the chip in response to the real-time needs of scalability, and adaptability of executables.

An Economic Analysis of Two Groundwater Allocation Programs for the Salinas Valley

DTIC Science & Technology

1994-06-01

monitoring system would establish a definable and 17Each individual well would have a frequency generator, analog/ digital converter, microprocessor with...RTU). The cost for purchasing and installing the frequency generator is estimated to be $1,100. The RTU consists of an analog/ digital converter and a...programmable microprocessor that can accept up to eight inputs and one output. The unit can transmit and receive digital data via LAN network or

Programmable data collection platform study

NASA Technical Reports Server (NTRS)

1976-01-01

The results of a feasibility study incorporating microprocessors in data collection platforms in described. An introduction to microcomputer hardware and software concepts is provided. The influence of microprocessor technology on the design of programmable data collection platform hardware is discussed. A standard modular PDCP design capable of meeting the design goals is proposed, and the process of developing PDCP programs is examined. A description of design and construction of the UT PDCP development system is given.

Hardware math for the 6502 microprocessor

NASA Technical Reports Server (NTRS)

Kissel, R.; Currie, J.

1985-01-01

A floating-point arithmetic unit is described which is being used in the Ground Facility of Large Space Structures Control Verification (GF/LSSCV). The experiment uses two complete inertial measurement units and a set of three gimbal torquers in a closed loop to control the structural vibrations in a flexible test article (beam). A 6502 (8-bit) microprocessor controls four AMD 9511A floating-point arithmetic units to do all the computation in 20 milliseconds.

Design and Development of a Multiprogramming Operating System for Sixteen Bit Microprocessors.

DTIC Science & Technology

1981-12-01

with the technical details of how services are programmed or produced, except perhaps when they fail to meet user requirements. Users are interested in...locations and loading decks. As the expense *and speed of computers increased, executive programs were created to allow several users to sequence...single user operating system as a companion to the 8080 microprocessor. CP/M (Control Program for Microcomputers) was a single user operating system that

Power Converters Maximize Outputs Of Solar Cell Strings

NASA Technical Reports Server (NTRS)

Frederick, Martin E.; Jermakian, Joel B.

1993-01-01

Microprocessor-controlled dc-to-dc power converters devised to maximize power transferred from solar photovoltaic strings to storage batteries and other electrical loads. Converters help in utilizing large solar photovoltaic arrays most effectively with respect to cost, size, and weight. Main points of invention are: single controller used to control and optimize any number of "dumb" tracker units and strings independently; power maximized out of converters; and controller in system is microprocessor.

Achieving High Performance on the i860 Microprocessor

NASA Technical Reports Server (NTRS)

Lee, King; Kutler, Paul (Technical Monitor)

1998-01-01

The i860 is a high performance microprocessor used in the Intel Touchstone project. This paper proposes a paradigm for programming the i860 that is modelled on the vector instructions of the Cray computers. Fortran callable assembler subroutines were written that mimic the concurrent vector instructions of the Cray. Cache takes the place of vector registers. Using this paradigm we have achieved twice the performance of compiled code on a traditional solve.

Low-level processing for real-time image analysis

NASA Technical Reports Server (NTRS)

Eskenazi, R.; Wilf, J. M.

1979-01-01

A system that detects object outlines in television images in real time is described. A high-speed pipeline processor transforms the raw image into an edge map and a microprocessor, which is integrated into the system, clusters the edges, and represents them as chain codes. Image statistics, useful for higher level tasks such as pattern recognition, are computed by the microprocessor. Peak intensity and peak gradient values are extracted within a programmable window and are used for iris and focus control. The algorithms implemented in hardware and the pipeline processor architecture are described. The strategy for partitioning functions in the pipeline was chosen to make the implementation modular. The microprocessor interface allows flexible and adaptive control of the feature extraction process. The software algorithms for clustering edge segments, creating chain codes, and computing image statistics are also discussed. A strategy for real time image analysis that uses this system is given.

A programmable controller based on CAN field bus embedded microprocessor and FPGA

NASA Astrophysics Data System (ADS)

Cai, Qizhong; Guo, Yifeng; Chen, Wenhei; Wang, Mingtao

2008-10-01

One kind of new programmable controller(PLC) is introduced in this paper. The advanced embedded microprocessor and Field-Programmable Gate Array (FPGA) device are applied in the PLC system. The PLC system structure was presented in this paper. It includes 32 bits Advanced RISC Machines (ARM) embedded microprocessor as control core, FPGA as control arithmetic coprocessor and CAN bus as data communication criteria protocol connected the host controller and its various extension modules. It is detailed given that the circuits and working principle, IiO interface circuit between ARM and FPGA and interface circuit between ARM and FPGA coprocessor. Furthermore the interface circuit diagrams between various modules are written. In addition, it is introduced that ladder chart program how to control the transfer info of control arithmetic part in FPGA coprocessor. The PLC, through nearly two months of operation to meet the design of the basic requirements.

A microprocessor based on a two-dimensional semiconductor.

PubMed

Wachter, Stefan; Polyushkin, Dmitry K; Bethge, Ole; Mueller, Thomas

2017-04-11

The advent of microcomputers in the 1970s has dramatically changed our society. Since then, microprocessors have been made almost exclusively from silicon, but the ever-increasing demand for higher integration density and speed, lower power consumption and better integrability with everyday goods has prompted the search for alternatives. Germanium and III-V compound semiconductors are being considered promising candidates for future high-performance processor generations and chips based on thin-film plastic technology or carbon nanotubes could allow for embedding electronic intelligence into arbitrary objects for the Internet-of-Things. Here, we present a 1-bit implementation of a microprocessor using a two-dimensional semiconductor-molybdenum disulfide. The device can execute user-defined programs stored in an external memory, perform logical operations and communicate with its periphery. Our 1-bit design is readily scalable to multi-bit data. The device consists of 115 transistors and constitutes the most complex circuitry so far made from a two-dimensional material.

A microprocessor based on a two-dimensional semiconductor

NASA Astrophysics Data System (ADS)

Wachter, Stefan; Polyushkin, Dmitry K.; Bethge, Ole; Mueller, Thomas

2017-04-01

The advent of microcomputers in the 1970s has dramatically changed our society. Since then, microprocessors have been made almost exclusively from silicon, but the ever-increasing demand for higher integration density and speed, lower power consumption and better integrability with everyday goods has prompted the search for alternatives. Germanium and III-V compound semiconductors are being considered promising candidates for future high-performance processor generations and chips based on thin-film plastic technology or carbon nanotubes could allow for embedding electronic intelligence into arbitrary objects for the Internet-of-Things. Here, we present a 1-bit implementation of a microprocessor using a two-dimensional semiconductor--molybdenum disulfide. The device can execute user-defined programs stored in an external memory, perform logical operations and communicate with its periphery. Our 1-bit design is readily scalable to multi-bit data. The device consists of 115 transistors and constitutes the most complex circuitry so far made from a two-dimensional material.

Alternative splicing of a viral mirtron differentially affects the expression of other microRNAs from its cluster and of the host transcript

PubMed Central

Rasschaert, Perrine; Dambrine, Ginette; Rasschaert, Denis; Laurent, Sylvie

2016-01-01

ABSTRACT Interplay between alternative splicing and the Microprocessor may have differential effects on the expression of intronic miRNAs organized into clusters. We used a viral model — the LAT long non-coding RNA (LAT lncRNA) of Marek's disease oncogenic herpesvirus (MDV-1), which has the mdv1-miR-M8-M6-M7-M10 cluster embedded in its first intron — to assess the impact of splicing modifications on the biogenesis of each of the miRNAs from the cluster. Drosha silencing and alternative splicing of an extended exon 2 of the LAT lncRNA from a newly identified 3′ splice site (SS) at the end of the second miRNA of the cluster showed that mdv1-miR-M6 was a 5′-tailed mirtron. We have thus identified the first 5′-tailed mirtron within a cluster of miRNAs for which alternative splicing is directly associated with differential expression of the other miRNAs of the cluster, with an increase in intronic mdv1-miR-M8 expression and a decrease in expression of the exonic mdv1-miR-M7, and indirectly associated with regulation of the host transcript. According to the alternative 3SS used for the host intron splicing, the mdv1-miR-M6 is processed as a mirtron by the spliceosome, dispatching the other miRNAs of the cluster into intron and exon, or as a canonical miRNA by the Microprocessor complex. The viral mdv1-miR-M6 mirtron is the first mirtron described that can also follow the canonical pathway. PMID:27715458

Prototype microprocessor controller. [for STDN antennas

NASA Technical Reports Server (NTRS)

Zarur, J.; Kraeuter, R.

1980-01-01

A microcomputer controller for STDN antennas was developed. The microcomputer technology reduces the system's physical size by the implementation in firmware of functions. The reduction in the number of components increases system reliability and similar benefit is derived when a graphic video display is substituted for several control and indicator panels. A substantial reduction in the number of cables, connectors, and mechanical switches is achieved. The microcomputer based system is programmed to perform calibration and diagnostics, to update the satellite orbital vector, and to communicate with other network systems. The design is applicable to antennas and lasers.

Device for detecting imminent failure of high-dielectric stress capacitors. [Patent application

DOEpatents

McDuff, G.G.

1980-11-05

A device is described for detecting imminent failure of a high-dielectric stress capacitor utilizing circuitry for detecting pulse width variations and pulse magnitude variations. Inexpensive microprocessor circuitry is utilized to make numerical calculations of digital data supplied by detection circuitry for comparison of pulse width data and magnitude data to determine if preselected ranges have been exceeded, thereby indicating imminent failure of a capacitor. Detection circuitry may be incorporated in transmission lines, pulse power circuitry, including laser pulse circuitry or any circuitry where capacitors or capacitor banks are utilized.

The development of an airborne information management system for flight test

NASA Technical Reports Server (NTRS)

Bever, Glenn A.

1992-01-01

An airborne information management system is being developed at the NASA Dryden Flight Research Facility. This system will improve the state of the art in management data acquisition on-board research aircraft. The design centers around highly distributable, high-speed microprocessors that allow data compression, digital filtering, and real-time analysis. This paper describes the areas of applicability, approach to developing the system, potential for trouble areas, and reasons for this development activity. System architecture (including the salient points of what makes it unique), design philosophy, and tradeoff issues are also discussed.

High speed quantitative digital microscopy

NASA Technical Reports Server (NTRS)

Castleman, K. R.; Price, K. H.; Eskenazi, R.; Ovadya, M. M.; Navon, M. A.

1984-01-01

Modern digital image processing hardware makes possible quantitative analysis of microscope images at high speed. This paper describes an application to automatic screening for cervical cancer. The system uses twelve MC6809 microprocessors arranged in a pipeline multiprocessor configuration. Each processor executes one part of the algorithm on each cell image as it passes through the pipeline. Each processor communicates with its upstream and downstream neighbors via shared two-port memory. Thus no time is devoted to input-output operations as such. This configuration is expected to be at least ten times faster than previous systems.

Multitasking in a data acquisition system

DOE Office of Scientific and Technical Information (OSTI.GOV)

Larsen, J.E.

1980-01-01

Microprocessors and microcomputers have been employed widely in data acquisition applications due to low cost and the ease of adapting the microcomputer to changing or altered requirements. Multitasking offers ways of getting more performance from a microcomputer and also a means of designing a system which by its nature is easily changed to meet new requirements. The term multitasking is used to include definitions of multitasking and multiprogramming: multitasking-performing various related functions of the same job, e.g. data acquisition and data logging (recording); multiprogramming-performing possibly unrelated jobs concurrently.

Multitasking OS manages a team of processors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ripps, D.L.

1983-07-21

MTOS-68k is a real-time multitasking operating system designed for the popular MC68000 microprocessors. It aproaches task coordination and synchronization in a fashion that matches uniquely the structural simplicity and regularity of the 68000 instruction set. Since in many 68000 applications the speed and power of one CPU are not enough, MTOS-68k has been designed to support multiple processors, as well as multiple tasks. Typically, the devices are tightly coupled single-board computers, that is they share a backplane and parts of global memory.

Noiseless coding for the Gamma Ray spectrometer

NASA Technical Reports Server (NTRS)

Rice, R.; Lee, J. J.

1985-01-01

The payload of several future unmanned space missions will include a sophisticated gamma ray spectrometer. Severely constrained data rates during certain portions of these missions could limit the possible science return from this instrument. This report investigates the application of universal noiseless coding techniques to represent gamma ray spectrometer data more efficiently without any loss in data integrity. Performance results demonstrate compression factors from 2.5:1 to 20:1 in comparison to a standard representation. Feasibility was also demonstrated by implementing a microprocessor breadboard coder/decoder using an Intel 8086 processor.

Retroreflector field tracker. [noncontact optical position sensor for space application

NASA Technical Reports Server (NTRS)

Wargocki, F. E.; Ray, A. J.; Hall, G. E.

1984-01-01

An electrooptical position-measuring instrument, the Retroreflector Field Tracker or RFT, is described. It is part of the Dynamic Augmentation Experiment - a part of the payload of Space Shuttle flight 41-D in Summer 1984. The tracker measures and outputs the position of 23 reflective targets placed on a 32-m solar array to provide data for determination of the dynamics of the lightweight structure. The sensor uses a 256 x 256 pixel CID detector; the processor electronics include three Z-80 microprocessors. A pulsed laser diode illuminator is used.

Wearable sweat detector device design for health monitoring and clinical diagnosis

NASA Astrophysics Data System (ADS)

Wu, Qiuchen; Zhang, Xiaodong; Tian, Bihao; Zhang, Hongyan; Yu, Yang; Wang, Ming

2017-06-01

Miniaturized sensor is necessary part for wearable detector for biomedical applications. Wearable detector device is indispensable for online health care. This paper presents a concept of an wearable digital health monitoring device design for sweat analysis. The flexible sensor is developed to quantify the amount of hydrogen ions in sweat and skin temperature in real time. The detection system includes pH sensor, temperature sensor, signal processing module, power source, microprocessor, display module and so on. The sweat monitoring device is designed for sport monitoring or clinical diagnosis.

Nuclear Science Symposium, 4th, and Nuclear Power Systems Symposium, 9th, San Francisco, Calif., October 19-21, 1977, Proceedings

NASA Technical Reports Server (NTRS)

1978-01-01

Consideration is given to the following types of high energy physics instrumentation: drift chambers, multiwire proportional chambers, calorimeters, optical detectors, ionization and scintillation detectors, solid state detectors, and electronic and digital subsystems. Attention is also paid to reactor instrumentation, nuclear medicine instrumentation, data acquisition systems for nuclear instrumentation, microprocessor applications in nuclear science, environmental instrumentation, control and instrumentation of nuclear power generating stations, and radiation monitoring. Papers are also presented on instrumentation for the High Energy Astronomy Observatory.

U. S. GEOLOGICAL SURVEY LAND REMOTE SENSING ACTIVITIES.

USGS Publications Warehouse

Frederick, Doyle G.

1983-01-01

USGS uses all types of remotely sensed data, in combination with other sources of data, to support geologic analyses, hydrologic assessments, land cover mapping, image mapping, and applications research. Survey scientists use all types of remotely sensed data with ground verifications and digital topographic and cartographic data. A considerable amount of research is being done by Survey scientists on developing automated geographic information systems that can handle a wide variety of digital data. The Survey is also investigating the use of microprocessor computer systems for accessing, displaying, and analyzing digital data.

Thermoelectric Devices Cool, Power Electronics

NASA Technical Reports Server (NTRS)

2009-01-01

Nextreme Thermal Solutions Inc., based in Research Triangle Park, North Carolina, licensed thermoelectric technology from NASA s Jet Propulsion Laboratory. This has allowed the company to develop cutting edge, thin-film thermoelectric coolers that effective remove heat generated by increasingly powerful and tightly packed microchip components. These solid-state coolers are ideal solutions for applications like microprocessors, laser diodes, LEDs, and even potentially for cooling the human body. Nextreme s NASA technology has also enabled the invention of thermoelectric generators capable of powering technologies like medical implants and wireless sensor networks.

XMOS XC-2 Development Board for Mechanical Control and Data Collection

NASA Technical Reports Server (NTRS)

Jarnot, Robert F.; Bowden, William J.

2011-01-01

The scanning microwave limb sounder (SMLS) will use technological improvements in low-noise mixers to provide precise data on the Earth s atmospheric composition with high spatial resolution. This project focuses on the design and implementation of a realtime control system needed for airborne engineering tests of the SMLS. The system must coordinate the actuation of optical components using four motors with encoder readback, while collecting synchronized telemetric data from a GPS receiver and 3-axis gyrometric system. A graphical user interface for testing the control system was also designed using Python. Although the system could have been implemented with an FPGA(fieldprogrammable gate array)-based setup, a processor development kit manufactured by XMOS was chosen. The XMOS architecture allows parallel execution of multiple tasks on separate threads, making it ideal for this application. It is easily programmed using XC (a subset of C). The necessary communication interfaces were implemented in software, including Ethernet, with significant cost and time reduction compared to an FPGA-based approach. A simple approach to control the chopper, calibration mirror, and gimbal for the airborne SMLS was needed. The XMOS board allows for multiple threads and real-time data acquisition. The XC-2 development kit is an attractive choice for synchronized, real-time, event-driven applications. The XMOS is based on the transputer microprocessor architecture developed for parallel computing, which is being revamped in this new platform. The XMOS device has multiple cores capable of running parallel applications on separate threads. The threads communicate with each other via user-defined channels capable of transmitting data within the device. XMOS provides a C-based development environment using XC, which eliminates the need for custom tool kits associated with FPGA programming. The XC-2 has four cores and necessary hardware for Ethernet I/O.

Diode-pumped DUV cw all-solid-state laser to replace argon ion lasers

NASA Astrophysics Data System (ADS)

Zanger, Ekhard; Liu, B.; Gries, Wolfgang

2000-04-01

The slim series DELTATRAINTM-worldwide the first integrated cw diode-pumped all-solid-state DUV laser at 266 nm with a compact, slim design-has been developed. The slim design minimizes the DUV DPSSL footprint and thus greatly facilitates the replacement of commonly used gas ion lasers, including these with intra-cavity frequency doubling, in numerous industrial and scientific applications. Such a replacement will result in an operation cost reduction by several thousands US$DLR each year for one unit. Owing to its unique geometry-invariant frequency doubling cavity- based on the LAS patent-pending DeltaConcept architecture- this DUV laser provides excellent beam-pointing stability of <2 (mu) rad/ degree(s)C and power stability of <2%. The newest design of the cavity block has adopted a cemented resonator with each component positioned precisely inside a compact monolithic metal block. The automatic and precise crystal shifter ensures long operation lifetime of > 5000 hours of whole 266 nm laser. The microprocessor controlled power supply provides an automatic control of the whole 266 nm laser, making this DUV laser a hands-off system which can meet tough requirements posed by numerous industrial and scientific applications. It will replace the commonplace ion laser as the future DUV laser of choice.

A micro-computer based system to compute magnetic variation

NASA Technical Reports Server (NTRS)

Kaul, R.

1984-01-01

A mathematical model of magnetic variation in the continental United States (COT48) was implemented in the Ohio University LORAN C receiver. The model is based on a least squares fit of a polynomial function. The implementation on the microprocessor based LORAN C receiver is possible with the help of a math chip, Am9511 which performs 32 bit floating point mathematical operations. A Peripheral Interface Adapter (M6520) is used to communicate between the 6502 based micro-computer and the 9511 math chip. The implementation provides magnetic variation data to the pilot as a function of latitude and longitude. The model and the real time implementation in the receiver are described.

Human operator tracking performance with a vibrotactile display

NASA Technical Reports Server (NTRS)

Inbar, Gideon F.

1991-01-01

Vibrotactile displays have been designed and used as a sensory aid for the blind. In the present work the same 6 x 24 'Optacon' type vibrotactile display (VTD) was used to characterize human operator (HO) tracking performance in pursuit and compensatory tasks. The VTD was connected via a microprocessor to a one-dimensional joy stick manipulator. Various display schemes were tested on the VDT, and were also compared to visual tracking performance using a specially constructed photo diode matrix display comparable to the VTD.

A Low Cost Navigation Microprocessor System.

DTIC Science & Technology

1977-03-01

a., 77843. uaed to iteratively update hi ~~~~~~~~~ -~~~- .:S~~~~~~~~~~~~~ . .— a — ~~~~~~~~~. - ~~~~ - . .- . — --- •5 n- -pr~~~ I~~~ ‘77 PIC ~~DU...the altitude above the reference ellipsoid (Ian — feature is implemented as step (6) below . nude —longitude—altitude coordinate system). Since cal

Flutter Generator Control and Force Computer.

DTIC Science & Technology

1985-07-01

exciter module 2. Mechanical load 3. Rectifier and triac 4. Overall system 5. Velocity control 6. Microprocessor 7. Operation in 1 ’g’ environment 8...amplifier Output voltage from the rectifier/ triac circuit (figure 3) is a function of the conduction angle of each triac . In a 400 Hz 3-phase system...3IIGCICI FIRING CIRCUIT FIRING CIRCUIT TO MOTOR Figure 3. Rectifier and triac _____ -=low AEL-0242-TNI Figure 4 DEMAND(V V49 -9 APIFE M O T OR

Use of a Microprocessor to Implement an ADCCP Protocol (Federal Std-1003) Operating in the Unbalanced Normal Mode.

DTIC Science & Technology

1980-05-01

andcoptrpormigfrteublne nra ls fpoeue nacrac with Federal Standard 1003 fTelecommunications: Synchronous Bit Oriented Data Link Control Procedures...and the higher level user. The solution to the producer/consumer problem involves the use of PASS and SICHAL primitives and event variables or... semaphores . The event variables have been defined for the LS-microprocessor interface as part of I-1 the internal registers that are included in the F6856

The special radiation-hardened processors for new highly informative experiments in space

NASA Astrophysics Data System (ADS)

Serdin, O. V.; Antonov, A. A.; Dubrovsky, A. G.; Novogilov, E. A.; Zuev, A. L.

2017-01-01

The article provides a detailed description of the series of special radiation-hardened microprocessor developed by SRISA for use in space technology. The microprocessors have 32-bit and 64-bit KOMDIV architecture with embedded SpaceWire, RapidIO, Ethernet and MIL-STD-1553B interfaces. These devices are used in space telescope GAMMA-400 data acquisition system, and may also be applied to other experiments in space (such as observatory “Millimetron” etc.).

DSS 13 Microprocessor Antenna Controller

NASA Technical Reports Server (NTRS)

Gosline, R. M.

1984-01-01

A microprocessor based antenna controller system developed as part of the unattended station project for DSS 13 is described. Both the hardware and software top level designs are presented and the major problems encounted are discussed. Developments useful to related projects include a JPL standard 15 line interface using a single board computer, a general purpose parser, a fast floating point to ASCII conversion technique, and experience gained in using off board floating point processors with the 8080 CPU.

Test report for single event effects of the 80386DX microprocessor

NASA Technical Reports Server (NTRS)

Watson, R. Kevin; Schwartz, Harvey R.; Nichols, Donald K.

1993-01-01

The Jet Propulsion Laboratory Section 514 Single Event Effects (SEE) Testing and Analysis Group has performed a series of SEE tests of certain strategic registers of Intel's 80386DX CHMOS 4 microprocessor. Following a summary of the test techniques and hardware used to gather the data, we present the SEE heavy ion and proton test results. We also describe the registers tested, along with a system impact analysis should these registers experience a single event upset.

Missile Manufacturing Technology Conference Held at Hilton Head Island, South Carolina on 22-26 September 1975. Panel Presentations: Guidance

DTIC Science & Technology

1975-01-01

Instead of the current three. Some de - tail on each component follows. II. POTENTIAL MANUFACTURING TECHNOLOGY PROJECTS Gyro Because of the...ranges of environment. With Imbedded microprocessors. It Is possible that parameters, once de - fined, can be placed within the microprocessor memory...Project cost: $53,000 Estimated duration of the project Is nine months. Benefits: Benefits to be de :ved from this project are a reduction

Use of a Microprocessor to Implement an ADCCP Protocol (Federal Standard 1003).

DTIC Science & Technology

1980-07-01

results of other studies, to evaluate the operational and economic impact of incorporating various options in Federal Standard 1003. The effort...the LSI interface and the microprocessor; the LSI chip deposits bytes in its buffer as the producer, and the MPU reads this data as the consumer...on the interface between the MPU and the LSI protocol chip. This requires two main processes to be running at the same time--transmit and receive. The

Method and apparatus for determining position using global positioning satellites

NASA Technical Reports Server (NTRS)

Ward, John (Inventor); Ward, William S. (Inventor)

1998-01-01

A global positioning satellite receiver having an antenna for receiving a L1 signal from a satellite. The L1 signal is processed by a preamplifier stage including a band pass filter and a low noise amplifier and output as a radio frequency (RF) signal. A mixer receives and de-spreads the RF signal in response to a pseudo-random noise code, i.e., Gold code, generated by an internal pseudo-random noise code generator. A microprocessor enters a code tracking loop, such that during the code tracking loop, it addresses the pseudo-random code generator to cause the pseudo-random code generator to sequentially output pseudo-random codes corresponding to satellite codes used to spread the L1 signal, until correlation occurs. When an output of the mixer is indicative of the occurrence of correlation between the RF signal and the generated pseudo-random codes, the microprocessor enters an operational state which slows the receiver code sequence to stay locked with the satellite code sequence. The output of the mixer is provided to a detector which, in turn, controls certain routines of the microprocessor. The microprocessor will output pseudo range information according to an interrupt routine in response detection of correlation. The pseudo range information is to be telemetered to a ground station which determines the position of the global positioning satellite receiver.

TDP-43 regulates the microprocessor complex activity during in vitro neuronal differentiation.

PubMed

Di Carlo, Valerio; Grossi, Elena; Laneve, Pietro; Morlando, Mariangela; Dini Modigliani, Stefano; Ballarino, Monica; Bozzoni, Irene; Caffarelli, Elisa

2013-12-01

TDP-43 (TAR DNA-binding protein 43) is an RNA-binding protein implicated in RNA metabolism at several levels. Even if ubiquitously expressed, it is considered as a neuronal activity-responsive factor and a major signature for neurological pathologies, making the comprehension of its activity in the nervous system a very challenging issue. TDP-43 has also been described as an accessory component of the Drosha-DGCR8 (DiGeorge syndrome critical region gene 8) microprocessor complex, which is crucially involved in basal and tissue-specific RNA processing events. In the present study, we exploited in vitro neuronal differentiation systems to investigate the TDP-43 demand for the microprocessor function, focusing on both its canonical microRNA biosynthetic activity and its alternative role as a post-transcriptional regulator of gene expression. Our findings reveal a novel role for TDP-43 as an essential factor that controls the stability of Drosha protein during neuronal differentiation, thus globally affecting the production of microRNAs. We also demonstrate that TDP-43 is required for the Drosha-mediated regulation of Neurogenin 2, a master gene orchestrating neurogenesis, whereas post-transcriptional control of Dgcr8, another Drosha target, resulted to be TDP-43-independent. These results implicate a previously uncovered contribution of TDP-43 in regulating the abundance and the substrate specificity of the microprocessor complex and provide new insights into TDP-43 as a key player in neuronal differentiation.

A lightweight security scheme for wireless body area networks: design, energy evaluation and proposed microprocessor design.

PubMed

Selimis, Georgios; Huang, Li; Massé, Fabien; Tsekoura, Ioanna; Ashouei, Maryam; Catthoor, Francky; Huisken, Jos; Stuyt, Jan; Dolmans, Guido; Penders, Julien; De Groot, Harmke

2011-10-01

In order for wireless body area networks to meet widespread adoption, a number of security implications must be explored to promote and maintain fundamental medical ethical principles and social expectations. As a result, integration of security functionality to sensor nodes is required. Integrating security functionality to a wireless sensor node increases the size of the stored software program in program memory, the required time that the sensor's microprocessor needs to process the data and the wireless network traffic which is exchanged among sensors. This security overhead has dominant impact on the energy dissipation which is strongly related to the lifetime of the sensor, a critical aspect in wireless sensor network (WSN) technology. Strict definition of the security functionality, complete hardware model (microprocessor and radio), WBAN topology and the structure of the medium access control (MAC) frame are required for an accurate estimation of the energy that security introduces into the WBAN. In this work, we define a lightweight security scheme for WBAN, we estimate the additional energy consumption that the security scheme introduces to WBAN based on commercial available off-the-shelf hardware components (microprocessor and radio), the network topology and the MAC frame. Furthermore, we propose a new microcontroller design in order to reduce the energy consumption of the system. Experimental results and comparisons with other works are given.

Legacy Code Modernization

NASA Technical Reports Server (NTRS)

Hribar, Michelle R.; Frumkin, Michael; Jin, Haoqiang; Waheed, Abdul; Yan, Jerry; Saini, Subhash (Technical Monitor)

1998-01-01

Over the past decade, high performance computing has evolved rapidly; systems based on commodity microprocessors have been introduced in quick succession from at least seven vendors/families. Porting codes to every new architecture is a difficult problem; in particular, here at NASA, there are many large CFD applications that are very costly to port to new machines by hand. The LCM ("Legacy Code Modernization") Project is the development of an integrated parallelization environment (IPE) which performs the automated mapping of legacy CFD (Fortran) applications to state-of-the-art high performance computers. While most projects to port codes focus on the parallelization of the code, we consider porting to be an iterative process consisting of several steps: 1) code cleanup, 2) serial optimization,3) parallelization, 4) performance monitoring and visualization, 5) intelligent tools for automated tuning using performance prediction and 6) machine specific optimization. The approach for building this parallelization environment is to build the components for each of the steps simultaneously and then integrate them together. The demonstration will exhibit our latest research in building this environment: 1. Parallelizing tools and compiler evaluation. 2. Code cleanup and serial optimization using automated scripts 3. Development of a code generator for performance prediction 4. Automated partitioning 5. Automated insertion of directives. These demonstrations will exhibit the effectiveness of an automated approach for all the steps involved with porting and tuning a legacy code application for a new architecture.

Designing a Virtual-Memory Implementation Using the Motorola MC68010 16- Bit Microprocessor with Multi-Processor Capability Interfaced to the VMEbus

DTIC Science & Technology

1990-06-01

RAM and ROM output enable signals. Figure C.7 shows the logic for the interrupt priority level (IPLO* through IPL2 *) and the interrupt acknowledge...IACK681* signal is sent to the DUART when a level one interrupt acknowledge is output by the CPU. The logic for the IACK681* and the IPLO* through IPL2 ...signals are actually implemented with an EPLD. Listing D.4 in Appendix D presents the Abel description of the IACK681* and IPLO* through IPL2

Modular System Control Development Model (MSCDM). Design Specification.

DTIC Science & Technology

1979-08-01

with power supply and ¶ can be used independently of the loop. The PDU can be used as a general purpose processor. The loop is contained in a separate...inputs to nodes 22 (VSQC), 23 (DSQC ) , and 26 (BWBSA) will be generated by a LSI—ll microprocessor used as a simulated input generator (SIG). The SIG...who c o b m n u n i — cate tau lt - s to the FIAC module. F~IAC generates even t reports to the OCRI and DBMS. The PDP1I/40 in loop 2 generates

Modern Methods of Analysis for Control of Continuous Nitroguanidine Process

DTIC Science & Technology

1981-05-01

S 0.0804 0.008 0.018 Ca(N0 3)2 18.60 1.86 3.076 H 20 12.30 1.23 2000. CaNCN 2.20 ~ 0 .Ia - 0 0 5bc, d C 1.80 0.18 0.215 Guanidine Nitrate 16.70 1.67...not constitute official endorsement or approval of such commercial firms, products, or services by the United States Government. UNCLASSTFT D SECURITY...Dedicated microprocessors Guanidine nitrate Polarography Ultraviolet absorption spectroscopy Ion chromatography 20. AVTAI T RAcreunae amrevr ae * it nmems I

Enhanced boiling in microchannels due to recirculation induced by repeated saw-toothed cross-sectional geometry

NASA Astrophysics Data System (ADS)

Gao, Le; Bhavnani, Sushil H.

2017-10-01

A saw-toothed shaped microchannel heat sink is investigated for enhancing flow boiling heat transfer. Tests are conducted at mass fluxes of 444-1776 kg/m2 s and an inlet subcooling of 15 °C. The effects of channel geometry on boiling curves, flow patterns, pressure drops, and heat transfer coefficient are discussed in this letter. It is found that heat transfer performance is enhanced by up to 50% especially at heat flux levels associated with the current generation of microprocessors.