A fast and simple bonding method for low cost microfluidic chip fabrication

NASA Astrophysics Data System (ADS)

Yin, Zhifu; Zou, Helin

2018-01-01

With the development of the microstructure fabrication technique, microfluidic chips are widely used in biological and medical researchers. Future advances in their commercial applications depend on the mass bonding of microfluidic chip. In this study we are presenting a simple, low cost and fast way of bonding microfluidic chips at room temperature. The influence of the bonding pressure on the deformation of the microchannel and adhesive tape was analyzed by numerical simulation. By this method, the microfluidic chip can be fully sealed at low temperature and pressure without using any equipment. The dye water and gas leakage test indicated that the microfluidic chip can be bonded without leakage or block and its bonding strength can up to 0.84 MPa.

Backside contacted field effect transistor array for extracellular signal recording.

PubMed

Ingebrandt, S; Yeung, C K; Staab, W; Zetterer, T; Offenhäusser, A

2003-04-01

A new approach to the design of field-effect transistor (FET) sensors and the use of these FETs in detecting extracellular electrophysiological recordings is reported. Backside contacts were engineered by deep reactive ion etching and a gas phase boron doping process of the holes using planar diffusion sources. The metal contacts were designed to fit on top of the bonding pads of a standard industrial 22-pin DIL (dual inline) chip carrier. To minimise contact resistance, the metal backside contacts of the chips were electroless plated with gold. The chips were mounted on top of the bonding pads using a standard flip-chip process and a fineplacer unit previously described. Rat embryonic myocytes were cultured on these new devices (effective growth area 6 x 6 mm(2)) in order to confirm their validity in electrophysiological recording. Copyright 2003 Elsevier Science B.V.

Two-Step Plasma Process for Cleaning Indium Bonding Bumps

NASA Technical Reports Server (NTRS)

Greer, Harold F.; Vasquez, Richard P.; Jones, Todd J.; Hoenk, Michael E.; Dickie, Matthew R.; Nikzad, Shouleh

2009-01-01

A two-step plasma process has been developed as a means of removing surface oxide layers from indium bumps used in flip-chip hybridization (bump bonding) of integrated circuits. The two-step plasma process makes it possible to remove surface indium oxide, without incurring the adverse effects of the acid etching process.

Vertical integration of array-type miniature interferometers at wafer level by using multistack anodic bonding

NASA Astrophysics Data System (ADS)

Wang, Wei-Shan; Wiemer, Maik; Froemel, Joerg; Enderlein, Tom; Gessner, Thomas; Lullin, Justine; Bargiel, Sylwester; Passilly, Nicolas; Albero, Jorge; Gorecki, Christophe

2016-04-01

In this work, vertical integration of miniaturized array-type Mirau interferometers at wafer level by using multi-stack anodic bonding is presented. Mirau interferometer is suitable for MEMS metrology and for medical imaging according to its vertical-, lateral- resolutions and working distances. Miniaturized Mirau interferometer can be a promising candidate as a key component of an optical coherence tomography (OCT) system. The miniaturized array-type interferometer consists of a microlens doublet, a Si-based MEMS Z scanner, a spacer for focus-adjustment and a beam splitter. Therefore, bonding technologies which are suitable for heterogeneous substrates are of high interest and necessary for the integration of MEMS/MOEMS devices. Multi-stack anodic bonding, which meets the optical and mechanical requirements of the MOEMS device, is adopted to integrate the array-type interferometers. First, the spacer and the beam splitter are bonded, followed by bonding of the MEMS Z scanner. In the meanwhile, two microlenses, which are composed of Si and glass wafers, are anodically bonded to form a microlens doublet. Then, the microlens doublet is aligned and bonded with the scanner/spacer/beam splitter stack. The bonded array-type interferometer is a 7- wafer stack and the thickness is approximately 5mm. To separate such a thick wafer stack with various substrates, 2-step laser cutting is used to dice the bonded stack into Mirau chips. To simplify fabrication process of each component, electrical connections are created at the last step by mounting a Mirau chip onto a flip chip PCB instead of through wafer vias. Stability of Au/Ti films on the MEMS Z scanner after anodic bonding, laser cutting and flip chip bonding are discussed as well.

Progress on TSV technology for Medipix3RX chip

NASA Astrophysics Data System (ADS)

Sarajlić, M.; Pennicard, D.; Smoljanin, S.; Fritzsch, T.; Zoschke, K.; Graafsma, H.

2017-12-01

The progress of Through Silicon Via (TSV) technology for Medipix3RX chip done at DESY is presented here. The goal of this development is to replace the wire bonds in X-ray detectors with TSVs, in order to reduce the dead area between detectors. We obtained the first working chips assembled together with Si based sensors for X-ray detection. The 3D integration technology, including TSV, Re-distribution layer deposition, bump bonding to the Si sensor and bump bonding to the carrier PCB, was done by Fraunhofer Institute IZM in Berlin. After assembly, the module was successfully tested by recording background radiation and making X-ray images of small objects. The active area of the Medipix3RX chip is 14.1 mm×14.1 mm or 256×256 pixels. During TSV processing, the Medipix3RX chip was thinned from 775 μm original thickness, to 130 μm. The diameter of the vias is 40 μm, and the pitch between the vias is 120 μm. A liner filling approach was used to contact the TSV with the RDL on the backside of the Medipix3RX readout chip.

Design and process development of a photonic crystal polymer biosensor for point-of-care diagnostics

NASA Astrophysics Data System (ADS)

Dortu, F.; Egger, H.; Kolari, K.; Haatainen, T.; Furjes, P.; Fekete, Z.; Bernier, D.; Sharp, G.; Lahiri, B.; Kurunczi, S.; Sanchez, J.-C.; Turck, N.; Petrik, P.; Patko, D.; Horvath, R.; Eiden, S.; Aalto, T.; Watts, S.; Johnson, N. P.; De La Rue, R. M.; Giannone, D.

2011-07-01

In this work, we report advances in the fabrication and anticipated performance of a polymer biosensor photonic chip developed in the European Union project P3SENS (FP7-ICT4-248304). Due to the low cost requirements of point-ofcare applications, the photonic chip is fabricated from nanocomposite polymeric materials, using highly scalable nanoimprint- lithography (NIL). A suitable microfluidic structure transporting the analyte solutions to the sensor area is also fabricated in polymer and adequately bonded to the photonic chip. We first discuss the design and the simulated performance of a high-Q resonant cavity photonic crystal sensor made of a high refractive index polyimide core waveguide on a low index polymer cladding. We then report the advances in doped and undoped polymer thin film processing and characterization for fabricating the photonic sensor chip. Finally the development of the microfluidic chip is presented in details, including the characterisation of the fluidic behaviour, the technological and material aspects of the 3D polymer structuring and the stable adhesion strategies for bonding the fluidic and the photonic chips, with regards to the constraints imposed by the bioreceptors supposedly already present on the sensors.

Characterizations of Rapid Sintered Nanosilver Joint for Attaching Power Chips

PubMed Central

Feng, Shuang-Tao; Mei, Yun-Hui; Chen, Gang; Li, Xin; Lu, Guo-Quan

2016-01-01

Sintering of nanosilver paste has been extensively studied as a lead-free die-attach solution for bonding semiconductor power chips, such as the power insulated gated bipolar transistor (IGBT). However, for the traditional method of bonding IGBT chips, an external pressure of a few MPa is reported necessary for the sintering time of ~1 h. In order to shorten the processing duration time, we developed a rapid way to sinter nanosilver paste for bonding IGBT chips in less than 5 min using pulsed current. In this way, we firstly dried as-printed paste at about 100 °C to get rid of many volatile solvents because they may result in defects or voids during the out-gassing from the paste. Then, the pre-dried paste was further heated by pulse current ranging from 1.2 kA to 2.4 kA for several seconds. The whole procedure was less than 3 min and did not require any gas protection. We could obtain robust sintered joint with shear strength of 30–35 MPa for bonding 1200-V, 25-A IGBT and superior thermal properties. Static and dynamic electrical performance of the as-bonded IGBT assemblies was also characterized to verify the feasibility of this rapid sintering method. The results indicate that the electrical performance is comparable or even partially better than that of commercial IGBT modules. The microstructure evolution of the rapid sintered joints was also studied by scanning electron microscopy (SEM). This work may benefit the wide usage of nanosilver paste for rapid bonding IGBT chips in the future. PMID:28773686

Characterizations of Rapid Sintered Nanosilver Joint for Attaching Power Chips.

PubMed

Feng, Shuang-Tao; Mei, Yun-Hui; Chen, Gang; Li, Xin; Lu, Guo-Quan

2016-07-12

Sintering of nanosilver paste has been extensively studied as a lead-free die-attach solution for bonding semiconductor power chips, such as the power insulated gated bipolar transistor (IGBT). However, for the traditional method of bonding IGBT chips, an external pressure of a few MPa is reported necessary for the sintering time of ~1 h. In order to shorten the processing duration time, we developed a rapid way to sinter nanosilver paste for bonding IGBT chips in less than 5 min using pulsed current. In this way, we firstly dried as-printed paste at about 100 °C to get rid of many volatile solvents because they may result in defects or voids during the out-gassing from the paste. Then, the pre-dried paste was further heated by pulse current ranging from 1.2 kA to 2.4 kA for several seconds. The whole procedure was less than 3 min and did not require any gas protection. We could obtain robust sintered joint with shear strength of 30-35 MPa for bonding 1200-V, 25-A IGBT and superior thermal properties. Static and dynamic electrical performance of the as-bonded IGBT assemblies was also characterized to verify the feasibility of this rapid sintering method. The results indicate that the electrical performance is comparable or even partially better than that of commercial IGBT modules. The microstructure evolution of the rapid sintered joints was also studied by scanning electron microscopy (SEM). This work may benefit the wide usage of nanosilver paste for rapid bonding IGBT chips in the future.

1.65 mm diameter forward-viewing confocal endomicroscopic catheter using a flip-chip bonded electrothermal MEMS fiber scanner.

PubMed

Seo, Yeong-Hyeon; Hwang, Kyungmin; Jeong, Ki-Hun

2018-02-19

We report a 1.65 mm diameter forward-viewing confocal endomicroscopic catheter using a flip-chip bonded electrothermal MEMS fiber scanner. Lissajous scanning was implemented by the electrothermal MEMS fiber scanner. The Lissajous scanned MEMS fiber scanner was precisely fabricated to facilitate flip-chip connection, and bonded with a printed circuit board. The scanner was successfully combined with a fiber-based confocal imaging system. A two-dimensional reflectance image of the metal pattern 'OPTICS' was successfully obtained with the scanner. The flip-chip bonded scanner minimizes electrical packaging dimensions. The inner diameter of the flip-chip bonded MEMS fiber scanner is 1.3 mm. The flip-chip bonded MEMS fiber scanner is fully packaged with a 1.65 mm diameter housing tube, 1 mm diameter GRIN lens, and a single mode optical fiber. The packaged confocal endomicroscopic catheter can provide a new breakthrough for diverse in-vivo endomicroscopic applications.

Bi-level microelectronic device package with an integral window

DOEpatents

Peterson, Kenneth A.; Watson, Robert D.

2004-01-06

A package with an integral window for housing a microelectronic device. The integral window is bonded directly to the package without having a separate layer of adhesive material disposed in-between the window and the package. The device can be a semiconductor chip, CCD chip, CMOS chip, VCSEL chip, laser diode, MEMS device, or IMEMS device. The multilayered package can be formed of a LTCC or HTCC cofired ceramic material, with the integral window being simultaneously joined to the package during LTCC or HTCC processing. The microelectronic device can be flip-chip bonded so that the light-sensitive side is optically accessible through the window. The package has at least two levels of circuits for making electrical interconnections to a pair of microelectronic devices. The result is a compact, low-profile package having an integral window that is hermetically sealed to the package prior to mounting and interconnecting the microelectronic device(s).

Fabrication of Quench Condensed Thin Films Using an Integrated MEMS Fab on a Chip

NASA Astrophysics Data System (ADS)

Lally, Richard; Reeves, Jeremy; Stark, Thomas; Barrett, Lawrence; Bishop, David

Atomic calligraphy is a microelectromechanical systems (MEMS)-based dynamic stencil nanolithography technique. Integrating MEMS devices into a bonded stacked array of three die provides a unique platform for conducting quench condensed thin film mesoscopic experiments. The atomic calligraphy Fab on a Chip process incorporates metal film sources, electrostatic comb driven stencil plate, mass sensor, temperature sensor, and target surface into one multi-die assembly. Three separate die are created using the PolyMUMPs process and are flip-chip bonded together. A die containing joule heated sources must be prepared with metal for evaporation prior to assembly. A backside etch of the middle/central die exposes the moveable stencil plate allowing the flux to pass through the stencil from the source die to the target die. The chip assembly is mounted in a cryogenic system at ultra-high vacuum for depositing extremely thin films down to single layers of atoms across targeted electrodes. Experiments such as the effect of thin film alloys or added impurities on their superconductivity can be measured in situ with this process.

Wafer-to-wafer bonding of nonplanarized MEMS surfaces using solder

NASA Astrophysics Data System (ADS)

Sparks, D.; Queen, G.; Weston, R.; Woodward, G.; Putty, M.; Jordan, L.; Zarabadi, S.; Jayakar, K.

2001-11-01

The fabrication and reliability of a solder wafer-to-wafer bonding process is discussed. Using a solder reflow process allows vacuum packaging to be accomplished with unplanarized complementary metal-oxide semiconductor (CMOS) surface topography. This capability enables standard CMOS processes, and integrated microelectromechanical systems devices to be packaged at the chip-level. Alloy variations give this process the ability to bond at lower temperatures than most alternatives. Factors affecting hermeticity, shorts, Q values, shifting cavity pressure, wafer saw cleanliness and corrosion resistance will be covered.

A review on solder reflow and flux application for flip chip

NASA Astrophysics Data System (ADS)

Suppiah, Sarveshvaran; Ong, Nestor Rubio; Sauli, Zaliman; Sarukunaselan, Karunavani; Alcain, Jesselyn Barro; Visvanathan, Susthitha Menon; Retnasamy, Vithyacharan

2017-09-01

This paper encompassed of the evolution and key findings, critical technical challenges, solutions and bonding equipment of solder reflow in flip chip bonding. Upon scrutinizing researches done by others, it can be deduced that peak temperature, time above liquidus, soak temperature, soak time, cooling rate and reflow environment played a vital role in achieving the desired bonding profile. In addition, flux is also needed with the purpose of removing oxides/contaminations on bump surface as well as to promote wetting of solder balls. Electromigration and warpage are the two main challenges faced by solder reflow process which can be overcome by the advancement in under bump metallization (UBM) and substrate technology. The review is ended with a brief description of the current equipment used in solder reflow process.

Fabrication of a microfluidic chip by UV bonding at room temperature for integration of temperature-sensitive layers

NASA Astrophysics Data System (ADS)

Schlautmann, S.; Besselink, G. A. J.; Radhakrishna Prabhu, G.; Schasfoort, R. B. M.

2003-07-01

A method for the bonding of a microfluidic device at room temperature is presented. The wafer with the fluidic structures was bonded to a sensor wafer with gold pads by means of adhesive bonding, utilizing an UV-curable glue layer. To avoid filling the fluidic channels with the glue, a stamping process was developed which allows the selective application of a thin glue layer. In this way a microfluidic glass chip was fabricated that could be used for performing surface plasmon resonance measurements without signs of leakage. The advantage of this method is the possibility of integration of organic layers as well as other temperature-sensitive layers into a microfluidic glass device.

Self-Patterning of Silica/Epoxy Nanocomposite Underfill by Tailored Hydrophilic-Superhydrophobic Surfaces for 3D Integrated Circuit (IC) Stacking.

PubMed

Tuan, Chia-Chi; James, Nathan Pataki; Lin, Ziyin; Chen, Yun; Liu, Yan; Moon, Kyoung-Sik; Li, Zhuo; Wong, C P

2017-03-15

As microelectronics are trending toward smaller packages and integrated circuit (IC) stacks nowadays, underfill, the polymer composite filled in between the IC chip and the substrate, becomes increasingly important for interconnection reliability. However, traditional underfills cannot meet the requirements for low-profile and fine pitch in high density IC stacking packages. Post-applied underfills have difficulties in flowing into the small gaps between the chip and the substrate, while pre-applied underfills face filler entrapment at bond pads. In this report, we present a self-patterning underfilling technology that uses selective wetting of underfill on Cu bond pads and Si 3 N 4 passivation via surface energy engineering. This novel process, fully compatible with the conventional underfilling process, eliminates the issue of filler entrapment in typical pre-applied underfilling process, enabling high density and fine pitch IC die bonding.

Route to one-step microstructure mold fabrication for PDMS microfluidic chip

NASA Astrophysics Data System (ADS)

Lv, Xiaoqing; Geng, Zhaoxin; Fan, Zhiyuan; Wang, Shicai; Su, Yue; Fang, Weihao; Pei, Weihua; Chen, Hongda

2018-04-01

The microstructure mold fabrication for PDMS microfluidic chip remains complex and time-consuming process requiring special equipment and protocols: photolithography and etching. Thus, a rapid and cost-effective method is highly needed. Comparing with the traditional microfluidic chip fabricating process based on the micro-electromechanical system (MEMS), this method is simple and easy to implement, and the whole fabrication process only requires 1-2 h. Different size of microstructure from 100 to 1000 μm was fabricated, and used to culture four kinds of breast cancer cell lines. Cell viability and morphology was assessed when they were cultured in the micro straight channels, micro square holes and the bonding PDMS-glass microfluidic chip. The experimental results indicate that the microfluidic chip is good and meet the experimental requirements. This method can greatly reduce the process time and cost of the microfluidic chip, and provide a simple and effective way for the structure design and in the field of biological microfabrications and microfluidic chips.

Microchannel cooling of face down bonded chips

DOEpatents

Bernhardt, A.F.

1993-06-08

Microchannel cooling is applied to flip-chip bonded integrated circuits, in a manner which maintains the advantages of flip-chip bonds, while overcoming the difficulties encountered in cooling the chips. The technique is suited to either multi chip integrated circuit boards in a plane, or to stacks of circuit boards in a three dimensional interconnect structure. Integrated circuit chips are mounted on a circuit board using flip-chip or control collapse bonds. A microchannel structure is essentially permanently coupled with the back of the chip. A coolant delivery manifold delivers coolant to the microchannel structure, and a seal consisting of a compressible elastomer is provided between the coolant delivery manifold and the microchannel structure. The integrated circuit chip and microchannel structure are connected together to form a replaceable integrated circuit module which can be easily decoupled from the coolant delivery manifold and the circuit board. The coolant supply manifolds may be disposed between the circuit boards in a stack and coupled to supplies of coolant through a side of the stack.

3D integrated superconducting qubits

NASA Astrophysics Data System (ADS)

Rosenberg, D.; Kim, D.; Das, R.; Yost, D.; Gustavsson, S.; Hover, D.; Krantz, P.; Melville, A.; Racz, L.; Samach, G. O.; Weber, S. J.; Yan, F.; Yoder, J. L.; Kerman, A. J.; Oliver, W. D.

2017-10-01

As the field of quantum computing advances from the few-qubit stage to larger-scale processors, qubit addressability and extensibility will necessitate the use of 3D integration and packaging. While 3D integration is well-developed for commercial electronics, relatively little work has been performed to determine its compatibility with high-coherence solid-state qubits. Of particular concern, qubit coherence times can be suppressed by the requisite processing steps and close proximity of another chip. In this work, we use a flip-chip process to bond a chip with superconducting flux qubits to another chip containing structures for qubit readout and control. We demonstrate that high qubit coherence (T1, T2,echo > 20 μs) is maintained in a flip-chip geometry in the presence of galvanic, capacitive, and inductive coupling between the chips.

Decapsulation Method for Flip Chips with Ceramics in Microelectronic Packaging

NASA Astrophysics Data System (ADS)

Shih, T. I.; Duh, J. G.

2008-06-01

The decapsulation of flip chips bonded to ceramic substrates is a challenging task in the packaging industry owing to the vulnerability of the chip surface during the process. In conventional methods, such as manual grinding and polishing, the solder bumps are easily damaged during the removal of underfill, and the thin chip may even be crushed due to mechanical stress. An efficient and reliable decapsulation method consisting of thermal and chemical processes was developed in this study. The surface quality of chips after solder removal is satisfactory for the existing solder rework procedure as well as for die-level failure analysis. The innovative processes included heat-sink and ceramic substrate removal, solder bump separation, and solder residue cleaning from the chip surface. In the last stage, particular temperatures were selected for the removal of eutectic Pb-Sn, high-lead, and lead-free solders considering their respective melting points.

Photodiodes integration on a suspended ridge structure VOA using 2-step flip-chip bonding method

NASA Astrophysics Data System (ADS)

Kim, Seon Hoon; Kim, Tae Un; Ki, Hyun Chul; Kim, Doo Gun; Kim, Hwe Jong; Lim, Jung Woon; Lee, Dong Yeol; Park, Chul Hee

2015-01-01

In this works, we have demonstrated a VOA integrated with mPDs, based on silica-on-silicon PLC and flip-chip bonding technologies. The suspended ridge structure was applied to reduce the power consumption. It achieves the attenuation of 30dB in open loop operation with the power consumption of below 30W. We have applied two-step flipchip bonding method using passive alignment to perform high density multi-chip integration on a VOA with eutectic AuSn solder bumps. The average bonding strength of the two-step flip-chip bonding method was about 90gf.

Multigigabit optical transceivers for high-data rate military applications

NASA Astrophysics Data System (ADS)

Catanzaro, Brian E.; Kuznia, Charlie

2012-01-01

Avionics has experienced an ever increasing demand for processing power and communication bandwidth. Currently deployed avionics systems require gigabit communication using opto-electronic transceivers connected with parallel optical fiber. Ultra Communications has developed a series of transceiver solutions combining ASIC technology with flip-chip bonding and advanced opto-mechanical molded optics. Ultra Communications custom high speed ASIC chips are developed using an SoS (silicon on sapphire) process. These circuits are flip chip bonded with sources (VCSEL arrays) and detectors (PIN diodes) to create an Opto-Electronic Integrated Circuit (OEIC). These have been combined with micro-optics assemblies to create transceivers with interfaces to standard fiber array (MT) cabling technology. We present an overview of the demands for transceivers in military applications and how new generation transceivers leverage both previous generation military optical transceivers as well as commercial high performance computing optical transceivers.

Sealed symmetric multilayered microelectronic device package with integral windows

DOEpatents

Peterson, Kenneth A.; Watson, Robert D.

2002-01-01

A sealed symmetric multilayered package with integral windows for housing one or more microelectronic devices. The devices can be a semiconductor chip, a CCD chip, a CMOS chip, a VCSEL chip, a laser diode, a MEMS device, or a IMEMS device. The multilayered package can be formed of a low-temperature cofired ceramic (LTCC) or high-temperature cofired ceramic (HTCC) multilayer processes with the windows being simultaneously joined (e.g. cofired) to the package body during LTCC or HTCC processing. The microelectronic devices can be flip-chip bonded and oriented so that the light-sensitive sides are optically accessible through the windows. The result is a compact, low-profile, sealed symmetric package, having integral windows that can be hermetically-sealed.

Microchannel cooling of face down bonded chips

DOEpatents

Bernhardt, Anthony F.

1993-01-01

Microchannel cooling is applied to flip-chip bonded integrated circuits, in a manner which maintains the advantages of flip-chip bonds, while overcoming the difficulties encountered in cooling the chips. The technique is suited to either multichip integrated circuit boards in a plane, or to stacks of circuit boards in a three dimensional interconnect structure. Integrated circuit chips are mounted on a circuit board using flip-chip or control collapse bonds. A microchannel structure is essentially permanently coupled with the back of the chip. A coolant delivery manifold delivers coolant to the microchannel structure, and a seal consisting of a compressible elastomer is provided between the coolant delivery manifold and the microchannel structure. The integrated circuit chip and microchannel structure are connected together to form a replaceable integrated circuit module which can be easily decoupled from the coolant delivery manifold and the circuit board. The coolant supply manifolds may be disposed between the circuit boards in a stack and coupled to supplies of coolant through a side of the stack.

Three dimensional, multi-chip module

DOEpatents

Bernhardt, A.F.; Petersen, R.W.

1993-08-31

A plurality of multi-chip modules are stacked and bonded around the perimeter by sold-bump bonds to adjacent modules on, for instance, three sides of the perimeter. The fourth side can be used for coolant distribution, for more interconnect structures, or other features, depending on particular design considerations of the chip set. The multi-chip modules comprise a circuit board, having a planarized interconnect structure formed on a first major surface, and integrated circuit chips bonded to the planarized interconnect surface. Around the periphery of each circuit board, long, narrow dummy chips'' are bonded to the finished circuit board to form a perimeter wall. The wall is higher than any of the chips on the circuit board, so that the flat back surface of the board above will only touch the perimeter wall. Module-to-module interconnect is laser-patterned on the sides of the boards and over the perimeter wall in the same way and at the same time that chip to board interconnect may be laser-patterned.

Three dimensional, multi-chip module

DOEpatents

Bernhardt, Anthony F.; Petersen, Robert W.

1993-01-01

A plurality of multi-chip modules are stacked and bonded around the perimeter by sold-bump bonds to adjacent modules on, for instance, three sides of the perimeter. The fourth side can be used for coolant distribution, for more interconnect structures, or other features, depending on particular design considerations of the chip set. The multi-chip modules comprise a circuit board, having a planarized interconnect structure formed on a first major surface, and integrated circuit chips bonded to the planarized interconnect surface. Around the periphery of each circuit board, long, narrow "dummy chips" are bonded to the finished circuit board to form a perimeter wall. The wall is higher than any of the chips on the circuit board, so that the flat back surface of the board above will only touch the perimeter wall. Module-to-module interconnect is laser-patterned o the sides of the boards and over the perimeter wall in the same way and at the same time that chip to board interconnect may be laser-patterned.

Chip-to-chip interconnects based on 3D stacking of optoelectrical dies on Si

NASA Astrophysics Data System (ADS)

Duan, P.; Raz, O.; Smalbrugge, B. E.; Duis, J.; Dorren, H. J. S.

2012-01-01

We demonstrate a new approach to increase the optical interconnection bandwidth density by stacking the opto-electrical dies directly on the CMOS driver. The suggested implementation is aiming to provide a wafer scale process which will make the use of wire bonding redundant and will allow for impedance matched metallic wiring between the electronic driving circuit and its opto-electronic counter part. We suggest the use of a thick photoresist ramp between CMOS driver and opto-electrical dies surface as the bridge for supporting co-plannar waveguides (CPW) electrically plated with lithographic accuracy. In this way all three dimensions of the interconnecting metal layer, width, length and thickness can be completely controlled. In this 1st demonstration all processing is done on commercially available devices and products, and is compatible with CMOS processing technology. To test the applicability of CPW instead of wire bonds for interconnecting the CMOS circuit and opto-electronic chips, we have made test samples and tested their performance at speeds up to 10 Gbps. In this demonstration, a silicon substrate was used on which we evaporated gold co-planar waveguides (CPW) to mimic a wire on the driver. An optical link consisting of a VCSEL chip and a photodiode chip has been assembled and fully characterized using optical coupling into and out of a multimode fiber (MMF). A 10 Gb/s 27-1 NRZ PRBS signal transmitted from one chip to another chip was detected error free. A 4 dB receiver sensitivity penalty is measured for the integrated device compared to a commercial link.

Laser-induced forward transfer for flip-chip packaging of single dies.

PubMed

Kaur, Kamal S; Van Steenberge, Geert

2015-03-20

Flip-chip (FC) packaging is a key technology for realizing high performance, ultra-miniaturized and high-density circuits in the micro-electronics industry. In this technique the chip and/or the substrate is bumped and the two are bonded via these conductive bumps. Many bumping techniques have been developed and intensively investigated since the introduction of the FC technology in 1960(1) such as stencil printing, stud bumping, evaporation and electroless/electroplating2. Despite the progress that these methods have made they all suffer from one or more than one drawbacks that need to be addressed such as cost, complex processing steps, high processing temperatures, manufacturing time and most importantly the lack of flexibility. In this paper, we demonstrate a simple and cost-effective laser-based bump forming technique known as Laser-induced Forward Transfer (LIFT)3. Using the LIFT technique a wide range of bump materials can be printed in a single-step with great flexibility, high speed and accuracy at RT. In addition, LIFT enables the bumping and bonding down to chip-scale, which is critical for fabricating ultra-miniature circuitry.

Flip-chip fabrication of integrated micromirror arrays using a novel latching off-chip hinge mechanism

NASA Astrophysics Data System (ADS)

Michalicek, M. Adrian; Bright, Victor M.

2001-10-01

This paper presents the design, fabrication, modeling, and testing of various arrays of cantilever micromirror devices integrated atop CMOS control electronics. The upper layers of the arrays are prefabricated in the MUMPs process and then flip-chip transferred to CMOS receiving modules using a novel latching off-chip hinge mechanism. This mechanism allows the micromirror arrays to be released, rotated off the edge of the host module and then bonded to the receiving module using a standard probe station. The hinge mechanism supports the arrays by tethers that are severed to free the arrays once bonded. The resulting devices are inherently planarized since the bottom of the first releasable MUMPs layer becomes the surface of the integrated mirror. The working devices are formed by mirror surfaces bonded to address electrodes fabricated above static memory cells on the CMOS module. These arrays demonstrate highly desirable features such as compatible address potentials, less than 2 nm of RMS roughness, approximately 1 micrometers of lateral position accuracy and the unique ability to metallize reflective surfaces without masking. Ultimately, the off-chip hinge mechanism enables very low-cost, simple, reliable, repeatable and accurate assembly of advanced MEMS and integrated microsystems without specialized equipment or complex procedures.

Design, processing and testing of LSI arrays, hybrid microelectronics task

NASA Technical Reports Server (NTRS)

Himmel, R. P.; Stuhlbarg, S. M.; Ravetti, R. G.; Zulueta, P. J.; Rothrock, C. W.

1979-01-01

Mathematical cost models previously developed for hybrid microelectronic subsystems were refined and expanded. Rework terms related to substrate fabrication, nonrecurring developmental and manufacturing operations, and prototype production are included. Sample computer programs were written to demonstrate hybrid microelectric applications of these cost models. Computer programs were generated to calculate and analyze values for the total microelectronics costs. Large scale integrated (LST) chips utilizing tape chip carrier technology were studied. The feasibility of interconnecting arrays of LSU chips utilizing tape chip carrier and semiautomatic wire bonding technology was demonstrated.

The fabrication of a double-layer atom chip with through silicon vias for an ultra-high-vacuum cell

NASA Astrophysics Data System (ADS)

Chuang, Ho-Chiao; Lin, Yun-Siang; Lin, Yu-Hsin; Huang, Chi-Sheng

2014-04-01

This study presents a double-layer atom chip that provides users with increased diversity in the design of the wire patterns and flexibility in the design of the magnetic field. It is more convenient for use in atomic physics experiments. A negative photoresist, SU-8, was used as the insulating layer between the upper and bottom copper wires. The electrical measurement results show that the upper and bottom wires with a width of 100 µm can sustain a 6 A current without burnout. Another focus of this study is the double-layer atom chips integrated with the through silicon via (TSV) technique, and anodically bonded to a Pyrex glass cell, which makes it a desired vacuum chamber for atomic physics experiments. Thus, the bonded glass cell not only significantly reduces the overall size of the ultra-high-vacuum (UHV) chamber but also conducts the high current from the backside to the front side of the atom chip via the TSV under UHV (9.5 × 10-10 Torr). The TSVs with a diameter of 70 µm were etched through by the inductively coupled plasma ion etching and filled by the bottom-up copper electroplating method. During the anodic bonding process, the electroplated copper wires and TSVs on atom chips also need to pass the examination of the required bonding temperature of 250 °C, under an applied voltage of 1000 V. Finally, the UHV test of the double-layer atom chips with TSVs at room temperature can be reached at 9.5 × 10-10 Torr, thus satisfying the requirements of atomic physics experiments under an UHV environment.

Silicon ball grid array chip carrier

DOEpatents

Palmer, David W.; Gassman, Richard A.; Chu, Dahwey

2000-01-01

A ball-grid-array integrated circuit (IC) chip carrier formed from a silicon substrate is disclosed. The silicon ball-grid-array chip carrier is of particular use with ICs having peripheral bond pads which can be reconfigured to a ball-grid-array. The use of a semiconductor substrate such as silicon for forming the ball-grid-array chip carrier allows the chip carrier to be fabricated on an IC process line with, at least in part, standard IC processes. Additionally, the silicon chip carrier can include components such as transistors, resistors, capacitors, inductors and sensors to form a "smart" chip carrier which can provide added functionality and testability to one or more ICs mounted on the chip carrier. Types of functionality that can be provided on the "smart" chip carrier include boundary-scan cells, built-in test structures, signal conditioning circuitry, power conditioning circuitry, and a reconfiguration capability. The "smart" chip carrier can also be used to form specialized or application-specific ICs (ASICs) from conventional ICs. Types of sensors that can be included on the silicon ball-grid-array chip carrier include temperature sensors, pressure sensors, stress sensors, inertia or acceleration sensors, and/or chemical sensors. These sensors can be fabricated by IC processes and can include microelectromechanical (MEM) devices.

Low-temperature bonding process for the fabrication of hybrid glass-membrane organ-on-a-chip devices

NASA Astrophysics Data System (ADS)

Pocock, Kyall J.; Gao, Xiaofang; Wang, Chenxi; Priest, Craig; Prestidge, Clive A.; Mawatari, Kazuma; Kitamori, Takehiko; Thierry, Benjamin

2016-10-01

The integration of microfluidics with living biological systems has paved the way to the exciting concept of "organs-on-a-chip," which aims at the development of advanced in vitro models that replicate the key features of human organs. Glass-based devices have long been utilized in the field of microfluidics but the integration of alternative functional elements within multilayered glass microdevices, such as polymeric membranes, remains a challenge. To this end, we have extended a previously reported approach for the low-temperature bonding of glass devices that enables the integration of a functional polycarbonate porous membrane. The process was initially developed and optimized on specialty low-temperature bonding equipment (μTAS2001, Bondtech, Japan) and subsequently adapted to more widely accessible hot embosser units (EVG520HE Hot Embosser, EVG, Austria). The key aspect of this method is the use of low temperatures compatible with polymeric membranes. Compared to borosilicate glass bonding (650°C) and quartz/fused silica bonding (1050°C) processes, this method maintains the integrity and functionality of the membrane (Tg 150°C for polycarbonate). Leak tests performed showed no damage or loss of integrity of the membrane for up to 150 h, indicating sufficient bond strength for long-term cell culture. A feasibility study confirmed the growth of dense and functional monolayers of Caco-2 cells within 5 days.

Rapid bonding of Pyrex glass microchips.

PubMed

Akiyama, Yoshitake; Morishima, Keisuke; Kogi, Atsuna; Kikutani, Yoshikuni; Tokeshi, Manabu; Kitamori, Takehiko

2007-03-01

A newly developed vacuum hot press system has been specially designed for the thermal bonding of glass substrates in the fabrication process of Pyrex glass microchemical chips. This system includes a vacuum chamber equipped with a high-pressure piston cylinder and carbon plate heaters. A temperature of up to 900 degrees C and a force of as much as 9800 N could be applied to the substrates in a vacuum atmosphere. The Pyrex substrates bonded with this system under different temperatures, pressures, and heating times were evaluated by tensile strength tests, by measurements of thickness, and by observations of the cross-sectional shapes of the microchannels. The optimal bonding conditions of the Pyrex glass substrates were 570 degrees C for 10 min under 4.7 N/mm(2) of applied pressure. Whereas more than 16 h is required for thermal bonding with a conventional furnace, the new system could complete the whole bonding processes within just 79 min, including heating and cooling periods. Such improvements should considerably enhance the production rate of Pyrex glass microchemical chips. Whereas flat and dust-free surfaces are required for conventional thermal bonding, especially without long and repeated heating periods, our hot press system could press a fine dust into glass substrates so that even the areas around the dust were bonded. Using this capability, we were able to successfully integrate Pt/Ti thin film electrodes into a Pyrex glass microchip.

Bonding prediction in friction stir consolidation of aluminum alloys: A preliminary study

NASA Astrophysics Data System (ADS)

Baffari, Dario; Reynolds, Anthony P.; Li, Xiao; Fratini, Livan

2018-05-01

Friction Stir Consolidation (FSC) is a solid-state process that results in consolidation of metal powders or chips producing solid billet through severe plastic deformation and the solid-state bonding phenomena. This process can be used both for primary production and for metal scrap recycling. During the FSC process, a rotating die is plunged into a hollow chamber containing the finely divided, unconsolidated material to be processed. In this paper, a FEM numerical model for the prediction of the quality of the consolidated billet is presented. In particular, a dedicated bonding criterion that takes into account the peculiar process mechanics of this innovative technology is proposed.

Development and Status of Cu Ball/Wedge Bonding in 2012

NASA Astrophysics Data System (ADS)

Schneider-Ramelow, Martin; Geißler, Ute; Schmitz, Stefan; Grübl, Wolfgang; Schuch, Bernhard

2013-03-01

Starting in the 1980s and continuing right into the last decade, a great deal of research has been published on Cu ball/wedge (Cu B/W) wire bonding. Despite this, the technology has not been established in industrial manufacturing to any meaningful extent. Only spikes in the price of Au, improvements in equipment and techniques, and better understanding of the Cu wire-bonding process have seen Cu B/W bonding become more widespread—initially primarily for consumer goods manufacturing. Cu wire bonding is now expected to soon be used for at least 20% of all ball/wedge-bonded components, and its utilization in more sophisticated applications is around the corner. In light of this progress, the present paper comprehensively reviews the existing literature on this topic and discusses wire-bonding materials, equipment, and tools in the ongoing development of Cu B/W bonding technology. Key bonding techniques, such as flame-off, how to prevent damage to the chip (cratering), and bond formation on various common chip and substrate finishes are also described. Furthermore, apart from discussing quality assessment of Cu wire bonds in the initial state, the paper also provides an overview of Cu bonding reliability, in particular regarding Cu balls on Al metalization at high temperatures and in humidity (including under the influence of halide ions).

Advanced processing of CdTe pixel radiation detectors

NASA Astrophysics Data System (ADS)

Gädda, A.; Winkler, A.; Ott, J.; Härkönen, J.; Karadzhinova-Ferrer, A.; Koponen, P.; Luukka, P.; Tikkanen, J.; Vähänen, S.

2017-12-01

We report a fabrication process of pixel detectors made of bulk cadmium telluride (CdTe) crystals. Prior to processing, the quality and defect density in CdTe material was characterized by infrared (IR) spectroscopy. The semiconductor detector and Flip-Chip (FC) interconnection processing was carried out in the clean room premises of Micronova Nanofabrication Centre in Espoo, Finland. The chip scale processes consist of the aluminum oxide (Al2O3) low temperature thermal Atomic Layer Deposition (ALD), titanium tungsten (TiW) metal sputtering depositions and an electroless Nickel growth. CdTe crystals with the size of 10×10×0.5 mm3 were patterned with several photo-lithography techniques. In this study, gold (Au) was chosen as the material for the wettable Under Bump Metalization (UBM) pads. Indium (In) based solder bumps were grown on PSI46dig read out chips (ROC) having 4160 pixels within an area of 1 cm2. CdTe sensor and ROC were hybridized using a low temperature flip-chip (FC) interconnection technique. The In-Au cold weld bonding connections were successfully connecting both elements. After the processing the detector packages were wire bonded into associated read out electronics. The pixel detectors were tested at the premises of Finnish Radiation Safety Authority (STUK). During the measurement campaign, the modules were tested by exposure to a 137Cs source of 1.5 TBq for 8 minutes. We detected at the room temperature a photopeak at 662 keV with about 2 % energy resolution.

Development of n+-in-p planar pixel quadsensor flip-chipped with FE-I4 readout ASICs

NASA Astrophysics Data System (ADS)

Unno, Y.; Kamada, S.; Yamamura, K.; Yamamoto, H.; Hanagaki, K.; Hori, R.; Ikegami, Y.; Nakamura, K.; Takubo, Y.; Takashima, R.; Tojo, J.; Kono, T.; Nagai, R.; Saito, S.; Sugibayashi, K.; Hirose, M.; Jinnouchi, O.; Sato, S.; Sawai, H.; Hara, K.; Sato, Kz.; Sato, Kj.; Iwabuchi, S.; Suzuki, J.

2017-01-01

We have developed flip-chip modules applicable to the pixel detector for the HL-LHC. New radiation-tolerant n+-in-p planar pixel sensors of a size of four FE-I4 application-specific integrated circuits (ASICs) are laid out in a 6-in wafer. Variation in readout connection for the pixels at the boundary of ASICs is implemented in the design of quadsensors. Bump bonding technology is developed for four ASICs onto one quadsensor. Both sensors and ASICs are thinned to 150 μm before bump bonding, and are held flat with vacuum chucks. Using lead-free SnAg solder bumps, we encounter deficiency with large areas of disconnected bumps after thermal stress treatment, including irradiation. Surface oxidation of the solder bumps is identified as a critical source of this deficiency after bump bonding trials, using SnAg bumps with solder flux, indium bumps, and SnAg bumps with a newly-introduced hydrogen-reflow process. With hydrogen-reflow, we establish flux-less bump bonding technology with SnAg bumps, appropriate for mass production of the flip-chip modules with thin sensors and thin ASICs.

High-performance genetic analysis on microfabricated capillary array electrophoresis plastic chips fabricated by injection molding.

PubMed

Dang, Fuquan; Tabata, Osamu; Kurokawa, Masaya; Ewis, Ashraf A; Zhang, Lihua; Yamaoka, Yoshihisa; Shinohara, Shouji; Shinohara, Yasuo; Ishikawa, Mitsuru; Baba, Yoshinobu

2005-04-01

We have developed a novel technique for mass production of microfabricated capillary array electrophoresis (mu-CAE) plastic chips for high-speed, high-throughput genetic analysis. The mu-CAE chips, containing 10 individual separation channels of 50-microm width, 50-microm depth, and a 100-microm lane-to-lane spacing at the detection region and a sacrificial channel network, were fabricated on a poly(methyl methacrylate) substrate by injection molding and then bonded manually using a pressure-sensitive sealing tape within several seconds at room temperature. The conditions for injection molding and bonding were carefully characterized to yield mu-CAE chips with well-defined channel and injection structures. A CCD camera equipped with an image intensifier was used to monitor simultaneously the separation in a 10-channel array with laser-induced fluorescence detection. High-performance electrophoretic separations of phiX174 HaeIII DNA restriction fragments and PCR products related to the human beta-globin gene and SP-B gene (the surfactant protein B) have been demonstrated on mu-CAE plastic chips using a methylcellulose sieving matrix in individual channels. The current work demonstrated greatly simplified the fabrication process as well as a detection scheme for mu-CAE chips and will bring the low-cost mass production and application of mu-CAE plastic chips for genetic analysis.

Integrated circuit package with lead structure and method of preparing the same

NASA Technical Reports Server (NTRS)

Kennedy, B. W. (Inventor)

1973-01-01

A beam-lead integrated circuit package assembly including a beam-lead integrated circuit chip, a lead frame array bonded to projecting fingers of the chip, a rubber potting compound disposed around the chip, and an encapsulating molded plastic is described. The lead frame array is prepared by photographically printing a lead pattern on a base metal sheet, selectively etching to remove metal between leads, and plating with gold. Joining of the chip to the lead frame array is carried out by thermocompression bonding of mating goldplated surfaces. A small amount of silicone rubber is then applied to cover the chip and bonded joints, and the package is encapsulated with epoxy resin, applied by molding.

Fluxless Bonding Processes Using Silver-Indium System for High Temperature Electronics and Silver Flip-Chip Interconnect Technology

NASA Astrophysics Data System (ADS)

Wu, Yuan-Yun

In this dissertation, fluxless silver (Ag)-indium (In) binary system bonding and Ag solid-state bonding are used between different bonded pairs which have large thermal expansion coefficient (CTE) mismatch and flip-chip interconnect bonding application. In contrast to the conventional soldering process, fluxless bonding technique eliminates contamination and reliability problems caused by flux to fabricate high quality joints. There are two section are reported. In the first section, the reactions of Ag-In binary system are presented. In the second section, the high melting temperature, thermal and electrical conductivity joint materials bonding by either Ag-In binary system bonding or solid-state bonding processes for different bonded pairs and flip-chip application are designed, developed, and reported. Our group have studied Ag-In system for several years and developed the bonding processes successfully. However, the detailed reactions of Ag and In were seldom studied. To design a proper bonding structure, it is necessary to understand the reaction between Ag and In. The systematic experiments were performed to investigate these reactions. A 40 um Ag layer was electroplated on copper (Cu) substrates, followed by indium layers of 1, 3, 5, 10, and 15 um, respectively. The samples were annealed at 180 °C in 0.1 torr vacuum. For samples with In thickness less than 5 mum, the joint compositions are Ag2In only (1 um) or AgIn2, Ag2In, and Ag solid solution (Ag) after annealing. No indium is identified. For 10 and 15 um thick In samples, In covers almost over the entire sample surface after annealing. Later, an Ag layer was annealed at 450 °C for 3 hours to grow Ag grains, followed by plating 10 um In and annealing at 180 °C. By annealing Ag before plating In, more In is kept in the structure during annealing at 180 °C. Based on above results, for those designs with In thinner than 5 um, the Ag layer needs to be annealed, prior to In plating in order to make a successful bonding. In this section, we further studied the Ag-In bonding and solid-state bonding for different bonded pairs and flip-chip application. For the silicon (Si) and aluminum (Al) pair, Al has been used as the material for interconnect pads on the ICs. However, its high CTE (23 x 10-6/°C) and non-solderable property limit its applications in electronic products. To overcome these problems, a fluxless Ag-In bonding was developed. Al was deposited Cr/Cu layer on the surface by E-beam evaporator to make it solderable. 15 um of Ag and 8 um of In were sequentially plated on the Al substrates and 15 um of Ag was on Si chips with Cr/Au coating layer. The bonding was performed at 180 °C in 0.1 torr vacuum. The joint consists of Ag/(Ag)/Ag2In/(Ag)/Ag. The joint can achieve a solidus temperature of beyond 600 °C. From shear test results, the shear strengths far exceed the requirement in MIL-STD-883H. Al is not considered as a favorable substrate material because it is not solderable and has a high CTE. The new method presented in this thesis seems to have surmounted these two challenges. Since Ag2In is weak inside the joint in Ag-In system, an annealed process was used to convert the joints into Ag solid solution (Ag) to increase the joint strength and ductility. Two copper (Cu) substrates were bonded at 180 °C without flux. Bonding samples were annealed at 200 °C for 1,000 hours (first design) and at 250 °C for 350 hours (second design), respectively. Scanning electron microscope with energy dispersive X-ray (EDX) analysis results indicate that the joint of the first design is an alloy of mostly (Ag) with micron-size Ag2In and Ag3In regions, and that of second design has converted to a single (Ag) phase. Shear test results show that the breaking forces far exceed the requirement in MIL-STD-883H. The joint solidus temperatures are 600 °C and 800 °C for the first and second designs, respectively. The research results have shown that high-strength and high temperature joints can be manufactured using fluxless low temperature processes with the Ag-In system and are valuable in developing high temperature package. (Abstract shortened by UMI.).

Advanced Liquid-Free, Piezoresistive, SOI-Based Pressure Sensors for Measurements in Harsh Environments.

PubMed

Ngo, Ha-Duong; Mukhopadhyay, Biswaijit; Ehrmann, Oswin; Lang, Klaus-Dieter

2015-08-18

In this paper we present and discuss two innovative liquid-free SOI sensors for pressure measurements in harsh environments. The sensors are capable of measuring pressures at high temperatures. In both concepts media separation is realized using a steel membrane. The two concepts represent two different strategies for packaging of devices for use in harsh environments and at high temperatures. The first one is a "one-sensor-one-packaging_technology" concept. The second one uses a standard flip-chip bonding technique. The first sensor is a "floating-concept", capable of measuring pressures at temperatures up to 400 °C (constant load) with an accuracy of 0.25% Full Scale Output (FSO). A push rod (mounted onto the steel membrane) transfers the applied pressure directly to the center-boss membrane of the SOI-chip, which is placed on a ceramic carrier. The chip membrane is realized by Deep Reactive Ion Etching (DRIE or Bosch Process). A novel propertied chip housing employing a sliding sensor chip that is fixed during packaging by mechanical preloading via the push rod is used, thereby avoiding chip movement, and ensuring optimal push rod load transmission. The second sensor can be used up to 350 °C. The SOI chips consists of a beam with an integrated centre-boss with was realized using KOH structuring and DRIE. The SOI chip is not "floating" but bonded by using flip-chip technology. The fabricated SOI sensor chip has a bridge resistance of 3250 Ω. The realized sensor chip has a sensitivity of 18 mV/µm measured using a bridge current of 1 mA.

Attachment method for stacked integrated circuit (IC) chips

DOEpatents

Bernhardt, Anthony F.; Malba, Vincent

1999-01-01

An attachment method for stacked integrated circuit (IC) chips. The method involves connecting stacked chips, such as DRAM memory chips, to each other and/or to a circuit board. Pads on the individual chips are rerouted to form pads on the side of the chip, after which the chips are stacked on top of each other whereby desired interconnections to other chips or a circuit board can be accomplished via the side-located pads. The pads on the side of a chip are connected to metal lines on a flexible plastic tape (flex) by anisotropically conductive adhesive (ACA). Metal lines on the flex are likewise connected to other pads on chips and/or to pads on a circuit board. In the case of a stack of DRAM chips, pads to corresponding address lines on the various chips may be connected to the same metal line on the flex to form an address bus. This method has the advantage of reducing the number of connections required to be made to the circuit board due to bussing; the flex can accommodate dimensional variation in the alignment of chips in the stack; bonding of the ACA is accomplished at low temperature and is otherwise simpler and less expensive than solder bonding; chips can be bonded to the ACA all at once if the sides of the chips are substantially coplanar, as in the case for stacks of identical chips, such as DRAM.

Effect of oxalic acid pretreatment of wood chips on manufacturing medium-density fiberboard

Treesearch

Xianjun Li; Zhiyong Cai; Eric Horn; Jerrold E. Winandy

2011-01-01

The main objective of this study was to evaluate the effect of oxalic acid (OA) wood chips pretreatment prior to refining, which is done to reduce energy used during the refining process. Selected mechanical and physical performances of medium-density fiberboard (MDF) – internal bonding (IB), modulus of elasticity (MOE), modulus of rupture (MOR), water absorption (WA)...

Effect of Slice Error of Glass on Zero Offset of Capacitive Accelerometer

NASA Astrophysics Data System (ADS)

Hao, R.; Yu, H. J.; Zhou, W.; Peng, B.; Guo, J.

2018-03-01

Packaging process had been studied on capacitance accelerometer. The silicon-glass bonding process had been adopted on sensor chip and glass, and sensor chip and glass was adhered on ceramic substrate, the three-layer structure was curved due to the thermal mismatch, the slice error of glass lead to asymmetrical curve of sensor chip. Thus, the sensitive mass of accelerometer deviated along the sensitive direction, which was caused in zero offset drift. It was meaningful to confirm the influence of slice error of glass, the simulation results showed that the zero output drift was 12.3×10-3 m/s2 when the deviation was 40μm.

Super-Lattice Light Emitting Diodes (SLEDS) on GaAs

DTIC Science & Technology

2016-03-31

Super-Lattice Light Emitting Diodes (SLEDS) on GaAs Kassem Nabha1, Russel Ricker2, Rodney McGee1, Nick Waite1, John Prineas2, Sydney Provence2...infrared light emitting diodes (LEDs). Typically, the LED arrays are mated with CMOS read-in integrated circuit (RIIC) chips using flip-chip bonding. In...circuit (RIIC) chips using flip-chip bonding. This established technology is called Hybrid-super-lattice light emitting diodes (Hybrid- SLEDS). In

Attachment method for stacked integrated circuit (IC) chips

DOEpatents

Bernhardt, A.F.; Malba, V.

1999-08-03

An attachment method for stacked integrated circuit (IC) chips is disclosed. The method involves connecting stacked chips, such as DRAM memory chips, to each other and/or to a circuit board. Pads on the individual chips are rerouted to form pads on the side of the chip, after which the chips are stacked on top of each other whereby desired interconnections to other chips or a circuit board can be accomplished via the side-located pads. The pads on the side of a chip are connected to metal lines on a flexible plastic tape (flex) by anisotropically conductive adhesive (ACA). Metal lines on the flex are likewise connected to other pads on chips and/or to pads on a circuit board. In the case of a stack of DRAM chips, pads to corresponding address lines on the various chips may be connected to the same metal line on the flex to form an address bus. This method has the advantage of reducing the number of connections required to be made to the circuit board due to bussing; the flex can accommodate dimensional variation in the alignment of chips in the stack; bonding of the ACA is accomplished at low temperature and is otherwise simpler and less expensive than solder bonding; chips can be bonded to the ACA all at once if the sides of the chips are substantially coplanar, as in the case for stacks of identical chips, such as DRAM. 12 figs.

Low-temperature bonded glass-membrane microfluidic device for in vitro organ-on-a-chip cell culture models

NASA Astrophysics Data System (ADS)

Pocock, Kyall J.; Gao, Xiaofang; Wang, Chenxi; Priest, Craig; Prestidge, Clive A.; Mawatari, Kazuma; Kitamori, Takehiko; Thierry, Benjamin

2015-12-01

The integration of microfluidics with living biological systems has paved the way to the exciting concept of "organson- a-chip", which aims at the development of advanced in vitro models that replicate the key features of human organs. Glass based devices have long been utilised in the field of microfluidics but the integration of alternative functional elements within multi-layered glass microdevices, such as polymeric membranes, remains a challenge. To this end, we have extended a previously reported approach for the low-temperature bonding of glass devices that enables the integration of a functional polycarbonate porous membrane. The process was initially developed and optimised on specialty low-temperature bonding equipment (μTAS2001, Bondtech, Japan) and subsequently adapted to more widely accessible hot embosser units (EVG520HE Hot Embosser, EVG, Austria). The key aspect of this method is the use of low temperatures compatible with polymeric membranes. Compared to borosilicate glass bonding (650 °C) and quartz/fused silica bonding (1050 °C) processes, this method maintains the integrity and functionality of the membrane (Tg 150 °C for polycarbonate). Leak tests performed showed no damage or loss of integrity of the membrane for up to 150 hours, indicating sufficient bond strength for long term cell culture. A feasibility study confirmed the growth of dense and functional monolayers of Caco-2 cells within 5 days.

A novel miniaturized PCR multi-reactor array fabricated using flip-chip bonding techniques

NASA Astrophysics Data System (ADS)

Zou, Zhi-Qing; Chen, Xiang; Jin, Qing-Hui; Yang, Meng-Su; Zhao, Jian-Long

2005-08-01

This paper describes a novel miniaturized multi-chamber array capable of high throughput polymerase chain reaction (PCR). The structure of the proposed device is verified by using finite element analysis (FEA) to optimize the thermal performance, and then implemented on a glass-silicon substrate using a standard MEMS process and post-processing. Thermal analysis simulation and verification of each reactor cell is equipped with integrated Pt temperature sensors and heaters at the bottom of the reaction chamber for real-time accurate temperature sensing and control. The micro-chambers are thermally separated from each other, and can be controlled independently. The multi-chip array was packaged on a printed circuit board (PCB) substrate using a conductive polymer flip-chip bonding technique, which enables effective heat dissipation and suppresses thermal crosstalk between the chambers. The designed system has successfully demonstrated a temperature fluctuation of ±0.5 °C during thermal multiplexing of up to 2 × 2 chambers, a full speed of 30 min for 30 cycle PCR, as well as the capability of controlling each chamber digitally and independently.

3D Stacked Memory Final Report CRADA No. TC-0494-93

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bernhardt, A.; Beene, G.

TI and LLNL demonstrated: (1) a process for the fabrication of 3-D memory using stacked DRAM chips, and (2) a fast prototyping process for 3-D stacks and MCMs. The metallization to route the chip pads to the sides of the die was carried out in a single high-speed masking step. The mask was not the usual physical one in glass and chrome, but was simply a computer file used to control the laser patterning process. Changes in either chip or customer circuit-board pad layout were easily and inexpensively accommodated, so that prototyping was a natural consequence of the laser patterningmore » process. As in the current TI process, a dielectric layer was added to the wafer, and vias to the chip I/0 pads were formed. All of the steps in Texas Instruments earlier process that were required to gold bump the pads were eliminated, significantly reducing fabrication cost and complexity. Pads were created on the sides of ·the die, which became pads on the side of the stack. In order to extend the process to accommodate non-memory devices with substantially greater I/0 than is required for DRAMs, pads were patterned on two sides of the memory stacks as a proof of principle. Stacking and bonding were done using modifications of the current TI process. After stacking and bonding, the pads on the sides of the dice were connected by application of a polyimide insulator film with laser ablation of the polyimide to form contacts to the pads. Then metallization was accomplished in the same manner as on the individual die.« less

Advanced Liquid-Free, Piezoresistive, SOI-Based Pressure Sensors for Measurements in Harsh Environments

PubMed Central

Ngo, Ha-Duong; Mukhopadhyay, Biswaijit; Ehrmann, Oswin; Lang, Klaus-Dieter

2015-01-01

In this paper we present and discuss two innovative liquid-free SOI sensors for pressure measurements in harsh environments. The sensors are capable of measuring pressures at high temperatures. In both concepts media separation is realized using a steel membrane. The two concepts represent two different strategies for packaging of devices for use in harsh environments and at high temperatures. The first one is a “one-sensor-one-packaging_technology” concept. The second one uses a standard flip-chip bonding technique. The first sensor is a “floating-concept”, capable of measuring pressures at temperatures up to 400 °C (constant load) with an accuracy of 0.25% Full Scale Output (FSO). A push rod (mounted onto the steel membrane) transfers the applied pressure directly to the center-boss membrane of the SOI-chip, which is placed on a ceramic carrier. The chip membrane is realized by Deep Reactive Ion Etching (DRIE or Bosch Process). A novel propertied chip housing employing a sliding sensor chip that is fixed during packaging by mechanical preloading via the push rod is used, thereby avoiding chip movement, and ensuring optimal push rod load transmission. The second sensor can be used up to 350 °C. The SOI chips consists of a beam with an integrated centre-boss with was realized using KOH structuring and DRIE. The SOI chip is not “floating” but bonded by using flip-chip technology. The fabricated SOI sensor chip has a bridge resistance of 3250 Ω. The realized sensor chip has a sensitivity of 18 mV/µm measured using a bridge current of 1 mA. PMID:26295235

Wafer Scale Integration of CMOS Chips for Biomedical Applications via Self-Aligned Masking.

PubMed

Uddin, Ashfaque; Milaninia, Kaveh; Chen, Chin-Hsuan; Theogarajan, Luke

2011-12-01

This paper presents a novel technique for the integration of small CMOS chips into a large area substrate. A key component of the technique is the CMOS chip based self-aligned masking. This allows for the fabrication of sockets in wafers that are at most 5 µm larger than the chip on each side. The chip and the large area substrate are bonded onto a carrier such that the top surfaces of the two components are flush. The unique features of this technique enable the integration of macroscale components, such as leads and microfluidics. Furthermore, the integration process allows for MEMS micromachining after CMOS die-wafer integration. To demonstrate the capabilities of the proposed technology, a low-power integrated potentiostat chip for biosensing implemented in the AMI 0.5 µm CMOS technology is integrated in a silicon substrate. The horizontal gap and the vertical displacement between the chip and the large area substrate measured after the integration were 4 µm and 0.5 µm, respectively. A number of 104 interconnects are patterned with high-precision alignment. Electrical measurements have shown that the functionality of the chip is not affected by the integration process.

Multilayered Microelectronic Device Package With An Integral Window

DOEpatents

Peterson, Kenneth A.; Watson, Robert D.

2004-10-26

A microelectronic package with an integral window mounted in a recessed lip for housing a microelectronic device. The device can be a semiconductor chip, a CCD chip, a CMOS chip, a VCSEL chip, a laser diode, a MEMS device, or a IMEMS device. The package can be formed of a low temperature co-fired ceramic (LTCC) or high temperature cofired ceramic (HTCC) multilayered material, with the integral window being simultaneously joined (e.g. co-fired) to the package body during LTCC or HTCC processing. The microelectronic device can be flip-chip bonded and oriented so that a light-sensitive side is optically accessible through the window. The result is a compact, low profile package, having an integral window mounted in a recessed lip, that can be hermetically sealed.

Capacitor bonding techniques and reliability. [thermal cycling tests

NASA Technical Reports Server (NTRS)

Kinser, D. L.; Graff, S. M.; Allen, R. V.; Caruso, S. V.

1974-01-01

The effect of thermal cycling on the mechanical failure of bonded ceramic chip capacitors mounted on alumina substrates is studied. It is shown that differential thermal expansion is responsible for the cumulative effects which lead to delayed failure of the capacitors. Harder or higher melting solders are found to be less susceptible to thermal cycling effects, although they are more likely to fail during initial processing operations.

A simple and low-cost chip bonding solution for high pressure, high temperature and biological applications.

PubMed

Serra, M; Pereiro, I; Yamada, A; Viovy, J-L; Descroix, S; Ferraro, D

2017-02-14

The sealing of microfluidic devices remains a complex and time-consuming process requiring specific equipment and protocols: a universal method is thus highly desirable. We propose here the use of a commercially available sealing tape as a robust, versatile, reversible solution, compatible with cell and molecular biology protocols, and requiring only the application of manually achievable pressures. The performance of the seal was tested with regards to the most commonly used chip materials. For most materials, the bonding resisted 5 bars at room temperature and 1 bar at 95 °C. This method should find numerous uses, ranging from fast prototyping in the laboratory to implementation in low technology environments or industrial production.

Flexure mechanism-based parallelism measurements for chip-on-glass bonding

NASA Astrophysics Data System (ADS)

Jung, Seung Won; Yun, Won Soo; Jin, Songwan; Kim, Bo Sun; Jeong, Young Hun

2011-08-01

Recently, liquid crystal displays (LCDs) have played vital roles in a variety of electronic devices such as televisions, cellular phones, and desktop/laptop monitors because of their enhanced volume, performance, and functionality. However, there is still a need for thinner LCD panels due to the trend of miniaturization in electronic applications. Thus, chip-on-glass (COG) bonding has become one of the most important aspects in the LCD panel manufacturing process. In this study, a novel sensor was developed to measure the parallelism between the tooltip planes of the bonding head and the backup of the COG main bonder, which has previously been estimated by prescale pressure films in industry. The sensor developed in this study is based on a flexure mechanism, and it can measure the total pressing force and the inclination angles in two directions that satisfy the quantitative definition of parallelism. To improve the measurement accuracy, the sensor was calibrated based on the estimation of the total pressing force and the inclination angles using the least-squares method. To verify the accuracy of the sensor, the estimation results for parallelism were compared with those from prescale pressure film measurements. In addition, the influence of parallelism on the bonding quality was experimentally demonstrated. The sensor was successfully applied to the measurement of parallelism in the COG-bonding process with an accuracy of more than three times that of the conventional method using prescale pressure films.

Characterization of Calcite Mineral Precipitation Process by EICP in Porous Media

NASA Astrophysics Data System (ADS)

Kim, D.; Mahabadi, N.; Hall, C.; Jang, J.; van Paassen, L. A.

2017-12-01

One of the most prevalent ground improvement techniques is injection of synthetic materials, such as cement grout or silicates into the pore space to create cementing bonds between soil particles. Besides these traditional ground improvement methods, several biological processes have been developed to improve soil properties. Enzyme induced carbonate precipitation (EICP) is a biological process in which urea hydrolyzes into ammonia and inorganic carbon, and promotes carbonate mineral precipitation. Different morphologies and patterns of calcite mineral precipitation, such as particle surface coating, pore filling, and soil particles bonding, have been observed in the previous studies. Most of the researches have detected precipitated minerals after the completion of the treatment using SEM (Scanning Electron Microscope) imaging and XRD (X-ray Diffractometer) structural analysis. In this research, an EICP reaction medium is injected into a microfluidic chip to observe the entire process of carbonate precipitation through several cycles of EICP treatment in the porous medium. Once the process of mineral precipitation is completed, water is injected into the microfluidic chip with different flow rates to evaluate the stability of carbonates during fluid flow injection.

Evaluation of advanced microelectronic fluxless solder-bump contacts for hybrid microcircuits

NASA Technical Reports Server (NTRS)

Mandal, R. P.

1976-01-01

Technology for interconnecting monolithic integrated circuit chips with other components is investigated. The advantages and disadvantages of the current flip-chip approach as compared to other interconnection methods are outlined. A fluxless solder-bump contact technology is evaluated. Multiple solder-bump contacts were formed on silicon integrated circuit chips. The solder-bumps, comprised of a rigid nickel under layer and a compliant solder overlayer, were electroformed onto gold device pads with the aid of thick dry film photomasks. Different solder alloys and the use of conductive epoxy for bonding were explored. Fluxless solder-bump bond quality and reliability were evaluated by measuring the effects of centrifuge, thermal cycling, and high temperature storage on bond visual characteristics, bond electrical continuity, and bond shear tests. The applicability and suitability of this technology for hybrid microelectronic packaging is discussed.

A short review on thermosonic flip chip bonding

NASA Astrophysics Data System (ADS)

Suppiah, Sarveshvaran; Ong, Nestor Rubio; Sauli, Zaliman; Sarukunaselan, Karunavani; Alcain, Jesselyn Barro; Shahimin, Mukhzeer Mohamad; Retnasamy, Vithyacharan

2017-09-01

This review is to study the evolution and key findings, critical technical challenges, solutions and bonding equipment of thermosonic flip chip bonding. Based on the review done, it was found that ultrasonic power, bonding time and force are the three main critical parameters need to be optimized in order to achieve sound and reliable bonding between the die and substrate. A close monitoring of the ultrasonic power helped to prevent over bonding phenomena on flexible substrate. Gold stud bumping is commonly used in thermosonic bonding compared to solder due to its better reliability obtained in the LED and optoelectronic packages. The review comprised short details on the available thermosonic bonding equipment in the semiconductor industry as well.

Physics of self-aligned assembly at room temperature

NASA Astrophysics Data System (ADS)

Dubey, V.; Beyne, E.; Derakhshandeh, J.; De Wolf, I.

2018-01-01

Self-aligned assembly, making use of capillary forces, is considered as an alternative to active alignment during thermo-compression bonding of Si chips in the 3D heterogeneous integration process. Various process parameters affect the alignment accuracy of the chip over the patterned binding site on a substrate/carrier wafer. This paper discusses the chip motion due to wetting and capillary force using a transient coupled physics model for the two regimes (that is, wetting regime and damped oscillatory regime) in the temporal domain. Using the transient model, the effect of the volume of the liquid and the placement accuracy of the chip on the alignment force is studied. The capillary time (that is, the time it takes for the chip to reach its mean position) for the chip is directly proportional to the placement offset and inversely proportional to the viscosity. The time constant of the harmonic oscillations is directly proportional to the gap between the chips due to the volume of the fluid. The predicted behavior from transient simulations is next experimentally validated and it is confirmed that the liquid volume and the initial placement affect the final alignment accuracy of the top chip on the bottom substrate. With statistical experimental data, we demonstrate an alignment accuracy reaching <1 μm.

Chip packaging technique

NASA Technical Reports Server (NTRS)

Jayaraj, Kumaraswamy (Inventor); Noll, Thomas E. (Inventor); Lockwood, Harry F. (Inventor)

2001-01-01

A hermetically sealed package for at least one semiconductor chip is provided which is formed of a substrate having electrical interconnects thereon to which the semiconductor chips are selectively bonded, and a lid which preferably functions as a heat sink, with a hermetic seal being formed around the chips between the substrate and the heat sink. The substrate is either formed of or includes a layer of a thermoplastic material having low moisture permeability which material is preferably a liquid crystal polymer (LCP) and is a multiaxially oriented LCP material for preferred embodiments. Where the lid is a heat sink, the heat sink is formed of a material having high thermal conductivity and preferably a coefficient of thermal expansion which substantially matches that of the chip. A hermetic bond is formed between the side of each chip opposite that connected to the substrate and the heat sink. The thermal bond between the substrate and the lid/heat sink may be a pinched seal or may be provided, for example by an LCP frame which is hermetically bonded or sealed on one side to the substrate and on the other side to the lid/heat sink. The chips may operate in the RF or microwave bands with suitable interconnects on the substrate and the chips may also include optical components with optical fibers being sealed into the substrate and aligned with corresponding optical components to transmit light in at least one direction. A plurality of packages may be physically and electrically connected together in a stack to form a 3D array.

Effect of ultrasonic capillary dynamics on the mechanics of thermosonic ball bonding.

PubMed

Huang, Yan; Shah, Aashish; Mayer, Michael; Zhou, Norman Y; Persic, John

2010-01-01

Microelectronic wire bonding is an essential step in today's microchip production. It is used to weld (bond) microwires to metallized pads of integrated circuits using ultrasound with hundreds of thousands of vibration cycles. Thermosonic ball bonding is the most popular variant of the wire bonding process and frequently investigated using finite element (FE) models that simplify the ultrasonic dynamics of the process with static or quasistatic boundary conditions. In this study, the ultrasonic dynamics of the bonding tool (capillary), made from Al(2)O(3), is included in a FE model. For more accuracy of the FE model, the main material parameters are measured. The density of the capillary was measured to be rho(cap) = 3552 +/- 100 kg/m(3). The elastic modulus of the capillary, E(cap) = 389 +/- 11 GPa, is found by comparing an auxiliary FE model of the free vibrating capillary with measured values. A capillary "nodding effect" is identified and found to be essential when describing the ultrasonic vibration shape. A main FE model builds on these results and adds bonded ball, pad, chip, and die attach components. There is excellent agreement between the main model and the ultrasonic force measured at the interface on a test chip with stress microsensors. Bonded ball and underpad stress results are reported. When adjusted to the same ultrasonic force, a simplified model without ultrasonic dynamics and with an infinitely stiff capillary tip is substantially off target by -40% for the maximum underpad stress. The compliance of the capillary causes a substantial inclination effect at the bonding interface between wire and pad. This oscillating inclination effect massively influences the stress fields under the pad and is studied in more detail. For more accurate results, it is therefore recommended to include ultrasonic dynamics of the bonding tool in mechanical FE models of wire bonding.

Assembly of opto-electronic module with improved heat sink

DOEpatents

Chan, Benson; Fortier, Paul Francis; Freitag, Ladd William; Galli, Gary T.; Guindon, Francois; Johnson, Glen Walden; Letourneau, Martial; Sherman, John H.; Tetreault, Real

2004-11-23

A heat sink for a transceiver optoelectronic module including dual direct heat paths and a structure which encloses a number of chips having a central web which electrically isolates transmitter and receiver chips from each other. A retainer for an optical coupler having a port into which epoxy is poured. An overmolded base for an optoelectronic module having epoxy flow controller members built thereon. Assembly methods for an optoelectronic module including gap setting and variation of a TAB bonding process.

Hybrid integration of VCSELs onto a silicon photonic platform for biosensing application

NASA Astrophysics Data System (ADS)

Lu, Huihui; Lee, Jun Su; Zhao, Yan; Cardile, Paolo; Daly, Aidan; Carroll, Lee; O'Brien, Peter

2017-02-01

This paper presents a technology of hybrid integration vertical cavity surface emitting lasers (VCSELs) directly on silicon photonics chip. By controlling the reflow of the solder balls used for electrical and mechanical bonding, the VCSELs were bonded at 10 degree to achieve the optimum angle-of-incidence to the planar grating coupler through vision based flip-chip techniques. The 1 dB discrepancy between optical loss values of flip-chip passive assembly and active alignment confirmed that the general purpose of the flip-chip design concept is achieved. This hybrid approach of integrating a miniaturized light source on chip opens the possibly of highly compact sensor system, which enable future portable and wearable diagnostics devices.

Warpage Characteristics and Process Development of Through Silicon Via-Less Interconnection Technology.

PubMed

Shen, Wen-Wei; Lin, Yu-Min; Wu, Sheng-Tsai; Lee, Chia-Hsin; Huang, Shin-Yi; Chang, Hsiang-Hung; Chang, Tao-Chih; Chen, Kuan-Neng

2018-08-01

In this study, through silicon via (TSV)-less interconnection using the fan-out wafer-level-packaging (FO-WLP) technology and a novel redistribution layer (RDL)-first wafer level packaging are investigated. Since warpage of molded wafer is a critical issue and needs to be optimized for process integration, the evaluation of the warpage issue on a 12-inch wafer using finite element analysis (FEA) at various parameters is presented. Related parameters include geometric dimension (such as chip size, chip number, chip thickness, and mold thickness), materials' selection and structure optimization. The effect of glass carriers with various coefficients of thermal expansion (CTE) is also discussed. Chips are bonded onto a 12-inch reconstituted wafer, which includes 2 RDL layers, 3 passivation layers, and micro bumps, followed by using epoxy molding compound process. Furthermore, an optical surface inspector is adopted to measure the surface profile and the results are compared with the results from simulation. In order to examine the quality of the TSV-less interconnection structure, electrical measurement is conducted and the respective results are presented.

Knudsen pump produced via silicon deep RIE, thermal oxidation, and anodic bonding processes for on-chip vacuum pumping

NASA Astrophysics Data System (ADS)

Van Toan, Nguyen; Inomata, Naoki; Trung, Nguyen Huu; Ono, Takahito

2018-05-01

This work describes the fabrication and evaluation of the Knudsen pump for on-chip vacuum pumping that works based on the principle of a thermal transpiration. Three AFM (atomic force microscope) cantilevers are integrated into small chambers with a size of 5 mm  ×  3 mm  ×  0.4 mm for the pump’s evaluation. Knudsen pump is fabricated using deep RIE (reactive ion etching), wet thermal oxidation and anodic bonding processes. The fabricated device is evaluated by monitoring the quality (Q) factor of the integrated cantilevers. The Q factor of the cantilever is increased from 300 -1150 in cases without and with a temperature difference approximately 25 °C between the top (the hot side at 40 °C) and bottom (the cold side at 15 °C) sides of the fabricated device, respectively. The evacuated chamber pressure of around 10 kPa is estimated from the Q factor of the integrated cantilevers.

High reliability bond program using small diameter aluminum wire

NASA Technical Reports Server (NTRS)

Macha, M.; Thiel, R. A.

1975-01-01

The program was undertaken to characterize the performance of small diameter aluminum wire ultrasonically bonded to conductors commonly encountered in hybrid assemblies, and to recommend guidelines for improving this performance. Wire, 25.4, 38.1 and 50.8 um (1, 1.5 and 2 mil), was used with bonding metallization consisting of thick film gold, thin film gold and aluminum as well as conventional aluminum pads on semiconductor chips. The chief tool for evaluating the performance was the double bond pull test in conjunction with a 72 hour - 150 C heat soak and -65 C to +150 C thermal cycling. In practice the thermal cycling was found to have relatively little effect compared to the heat soak. Pull strength will decrease after heat soak as a result of annealing of the aluminum wire; when bonded to thick film gold, the pull strength decreased by about 50% (weakening of the bond interface was the major cause of the reduction). Bonds to thin film gold lost about 30 - 40% of their initial pull strenth; weakening of the wire itself at the bond heel was the predominant cause. Bonds to aluminum substrate metallization lost only about 22%. Bonds between thick and thin film gold substrate metallization and semiconductor chips substantiated the previous conclusions but also showed that in about 20 to 25% of the cases, bond interface failure occurred at the semiconductor chip.

Reliable bonding using indium-based solders

NASA Astrophysics Data System (ADS)

Cheong, Jongpil; Goyal, Abhijat; Tadigadapa, Srinivas; Rahn, Christopher

2004-01-01

Low temperature bonding techniques with high bond strengths and reliability are required for the fabrication and packaging of MEMS devices. Indium and indium-tin based bonding processes are explored for the fabrication of a flextensional MEMS actuator, which requires the integration of lead zirconate titanate (PZT) substrate with a silicon micromachined structure at low temperatures. The developed technique can be used either for wafer or chip level bonding. The lithographic steps used for the patterning and delineation of the seed layer limit the resolution of this technique. Using this technique, reliable bonds were achieved at a temperature of 200°C. The bonds yielded an average tensile strength of 5.41 MPa and 7.38 MPa for samples using indium and indium-tin alloy solders as the intermediate bonding layers respectively. The bonds (with line width of 100 microns) showed hermetic sealing capability of better than 10-11 mbar-l/s when tested using a commercial helium leak tester.

Reliable bonding using indium-based solders

NASA Astrophysics Data System (ADS)

Cheong, Jongpil; Goyal, Abhijat; Tadigadapa, Srinivas; Rahn, Christopher

2003-12-01

Low temperature bonding techniques with high bond strengths and reliability are required for the fabrication and packaging of MEMS devices. Indium and indium-tin based bonding processes are explored for the fabrication of a flextensional MEMS actuator, which requires the integration of lead zirconate titanate (PZT) substrate with a silicon micromachined structure at low temperatures. The developed technique can be used either for wafer or chip level bonding. The lithographic steps used for the patterning and delineation of the seed layer limit the resolution of this technique. Using this technique, reliable bonds were achieved at a temperature of 200°C. The bonds yielded an average tensile strength of 5.41 MPa and 7.38 MPa for samples using indium and indium-tin alloy solders as the intermediate bonding layers respectively. The bonds (with line width of 100 microns) showed hermetic sealing capability of better than 10-11 mbar-l/s when tested using a commercial helium leak tester.

Quantum Devices Bonded Beneath a Superconducting Shield: Part 2

NASA Astrophysics Data System (ADS)

McRae, Corey Rae; Abdallah, Adel; Bejanin, Jeremy; Earnest, Carolyn; McConkey, Thomas; Pagel, Zachary; Mariantoni, Matteo

The next-generation quantum computer will rely on physical quantum bits (qubits) organized into arrays to form error-robust logical qubits. In the superconducting quantum circuit implementation, this architecture will require the use of larger and larger chip sizes. In order for on-chip superconducting quantum computers to be scalable, various issues found in large chips must be addressed, including the suppression of box modes (due to the sample holder) and the suppression of slot modes (due to fractured ground planes). By bonding a metallized shield layer over a superconducting circuit using thin-film indium as a bonding agent, we have demonstrated proof of concept of an extensible circuit architecture that holds the key to the suppression of spurious modes. Microwave characterization of shielded transmission lines and measurement of superconducting resonators were compared to identical unshielded devices. The elimination of box modes was investigated, as well as bond characteristics including bond homogeneity and the presence of a superconducting connection.

Microelectronic device package with an integral window

DOEpatents

Peterson, Kenneth A.; Watson, Robert D.

2002-01-01

An apparatus for packaging of microelectronic devices, including an integral window. The microelectronic device can be a semiconductor chip, a CCD chip, a CMOS chip, a VCSEL chip, a laser diode, a MEMS device, or a IMEMS device. The package can include a cofired ceramic frame or body. The package can have an internal stepped structure made of one or more plates, with apertures, which are patterned with metallized conductive circuit traces. The microelectronic device can be flip-chip bonded on the plate to these traces, and oriented so that the light-sensitive side is optically accessible through the window. A cover lid can be attached to the opposite side of the package. The result is a compact, low-profile package, having an integral window that can be hermetically-sealed. The package body can be formed by low-temperature cofired ceramic (LTCC) or high-temperature cofired ceramic (HTCC) multilayer processes with the window being simultaneously joined (e.g. cofired) to the package body during LTCC or HTCC processing. Multiple chips can be located within a single package. The cover lid can include a window. The apparatus is particularly suited for packaging of MEMS devices, since the number of handling steps is greatly reduced, thereby reducing the potential for contamination.

Ultrasonic friction power during Al wire wedge-wedge bonding

NASA Astrophysics Data System (ADS)

Shah, A.; Gaul, H.; Schneider-Ramelow, M.; Reichl, H.; Mayer, M.; Zhou, Y.

2009-07-01

Al wire bonding, also called ultrasonic wedge-wedge bonding, is a microwelding process used extensively in the microelectronics industry for interconnections to integrated circuits. The bonding wire used is a 25μm diameter AlSi1 wire. A friction power model is used to derive the ultrasonic friction power during Al wire bonding. Auxiliary measurements include the current delivered to the ultrasonic transducer, the vibration amplitude of the bonding tool tip in free air, and the ultrasonic force acting on the bonding pad during the bond process. The ultrasonic force measurement is like a signature of the bond as it allows for a detailed insight into mechanisms during various phases of the process. It is measured using piezoresistive force microsensors integrated close to the Al bonding pad (Al-Al process) on a custom made test chip. A clear break-off in the force signal is observed, which is followed by a relatively constant force for a short duration. A large second harmonic content is observed, describing a nonsymmetric deviation of the signal wave form from the sinusoidal shape. This deviation might be due to the reduced geometrical symmetry of the wedge tool. For bonds made with typical process parameters, several characteristic values used in the friction power model are determined. The ultrasonic compliance of the bonding system is 2.66μm/N. A typical maximum value of the relative interfacial amplitude of ultrasonic friction is at least 222nm. The maximum interfacial friction power is at least 11.5mW, which is only about 4.8% of the total electrical power delivered to the ultrasonic generator.

Ultra-thin silicon (UTSi) on insulator CMOS transceiver and time-division multiplexed switch chips for smart pixel integration

NASA Astrophysics Data System (ADS)

Zhang, Liping; Sawchuk, Alexander A.

2001-12-01

We describe the design, fabrication and functionality of two different 0.5 micron CMOS optoelectronic integrated circuit (OEIC) chips based on the Peregrine Semiconductor Ultra-Thin Silicon on insulator technology. The Peregrine UTSi silicon- on-sapphire (SOS) technology is a member of the silicon-on- insulator (SOI) family. The low-loss synthetic sapphire substrate is optically transparent and has good thermal conductivity and coefficient of thermal expansion properties, which meet the requirements for flip-chip bonding of VCSELs and other optoelectronic input-output components. One chip contains transceiver and network components, including four channel high-speed CMOS transceiver modules, pseudo-random bit stream (PRBS) generators, a voltage controlled oscillator (VCO) and other test circuits. The transceiver chips can operate in both self-testing mode and networking mode. An on- chip clock and true-single-phase-clock (TSPC) D-flip-flop have been designed to generate a PRBS at over 2.5 Gb/s for the high-speed transceiver arrays to operate in self-testing mode. In the networking mode, an even number of transceiver chips forms a ring network through free-space or fiber ribbon interconnections. The second chip contains four channel optical time-division multiplex (TDM) switches, optical transceiver arrays, an active pixel detector and additional test devices. The eventual applications of these chips will require monolithic OEICs with integrated optical input and output. After fabrication and testing, the CMOS transceiver array dies will be packaged with 850 nm vertical cavity surface emitting lasers (VCSELs), and metal-semiconductor- metal (MSM) or GaAs p-i-n detector die arrays to achieve high- speed optical interconnections. The hybrid technique could be either wire bonding or flip-chip bonding of the CMOS SOS smart-pixel arrays with arrays of VCSELs and photodetectors onto an optoelectronic chip carrier as a multi-chip module (MCM).

Microfabricated Electrical Connector for Atomic Force Microscopy Probes with Integrated Sensor/Actuator

NASA Astrophysics Data System (ADS)

Akiyama, Terunobu; Staufer, Urs; Rooij, Nico F. de

2002-06-01

A microfabricated, electrical connector is proposed for facilitating the mounting of atomic force microscopy (AFM) probes, which have an integrated sensor and/or actuator. Only a base chip, which acts as a socket, is permanently fixed onto a printed circuit board and electronically connected by standard wire bonding. The AFM chip, the “plug”, is flipped onto the base chip and pressed from the backside by a spring. Electrical contact with the eventual stress sensors, capacitive or piezoelectric sensor/actuators, is provided by contact bumps. These bumps of about 8 μm height are placed onto the base chip. They touch the pads on the AFM chip that were originally foreseen to be for wire bonding and thus provide the electrical contact. This connector schema was successfully used to register AFM images with piezoresistive cantilevers.

Method to Improve Indium Bump Bonding via Indium Oxide Removal Using a Multi-Step Plasma Process

NASA Technical Reports Server (NTRS)

Dickie, Matthew R. (Inventor); Nikzad, Shouleh (Inventor); Greer, H. Frank (Inventor); Jones, Todd J. (Inventor); Vasquez, Richard P. (Inventor); Hoenk, Michael E. (Inventor)

2012-01-01

A process for removing indium oxide from indium bumps in a flip-chip structure to reduce contact resistance, by a multi-step plasma treatment. A first plasma treatment of the indium bumps with an argon, methane and hydrogen plasma reduces indium oxide, and a second plasma treatment with an argon and hydrogen plasma removes residual organics. The multi-step plasma process for removing indium oxide from the indium bumps is more effective in reducing the oxide, and yet does not require the use of halogens, does not change the bump morphology, does not attack the bond pad material or under-bump metallization layers, and creates no new mechanisms for open circuits.

Chip-scale integrated optical interconnects: a key enabler for future high-performance computing

NASA Astrophysics Data System (ADS)

Haney, Michael; Nair, Rohit; Gu, Tian

2012-01-01

High Performance Computing (HPC) systems are putting ever-increasing demands on the throughput efficiency of their interconnection fabrics. In this paper, the limits of conventional metal trace-based inter-chip interconnect fabrics are examined in the context of state-of-the-art HPC systems, which currently operate near the 1 GFLOPS/W level. The analysis suggests that conventional metal trace interconnects will limit performance to approximately 6 GFLOPS/W in larger HPC systems that require many computer chips to be interconnected in parallel processing architectures. As the HPC communications bottlenecks push closer to the processing chips, integrated Optical Interconnect (OI) technology may provide the ultra-high bandwidths needed at the inter- and intra-chip levels. With inter-chip photonic link energies projected to be less than 1 pJ/bit, integrated OI is projected to enable HPC architecture scaling to the 50 GFLOPS/W level and beyond - providing a path to Peta-FLOPS-level HPC within a single rack, and potentially even Exa-FLOPSlevel HPC for large systems. A new hybrid integrated chip-scale OI approach is described and evaluated. The concept integrates a high-density polymer waveguide fabric directly on top of a multiple quantum well (MQW) modulator array that is area-bonded to the Silicon computing chip. Grayscale lithography is used to fabricate 5 μm x 5 μm polymer waveguides and associated novel small-footprint total internal reflection-based vertical input/output couplers directly onto a layer containing an array of GaAs MQW devices configured to be either absorption modulators or photodetectors. An external continuous wave optical "power supply" is coupled into the waveguide links. Contrast ratios were measured using a test rider chip in place of a Silicon processing chip. The results suggest that sub-pJ/b chip-scale communication is achievable with this concept. When integrated into high-density integrated optical interconnect fabrics, it could provide a seamless interconnect fabric spanning the intra-

Microstructural Evolution of Ni-Sn Transient Liquid Phase Sintering Bond during High-Temperature Aging

NASA Astrophysics Data System (ADS)

Feng, Hongliang; Huang, Jihua; Peng, Xianwen; Lv, Zhiwei; Wang, Yue; Yang, Jian; Chen, Shuhai; Zhao, Xingke

2018-05-01

For high-temperature-resistant packaging of new generation power chip, a chip packaging simulation structure of Ni/Ni-Sn/Ni was bonded by a transient liquid-phase sintering process. High-temperature aging experiments were carried out to investigate joint heat stability. The microstructural evolution and mechanism during aging, and mechanical properties after aging were analyzed. The results show that the 30Ni-70Sn bonding layer as-bonded at 340°C for 240 min is mainly composed of Ni3Sn4 and residual Ni particles. When aged at 350°C, because of the difficulty of nucleation for Ni3Sn and quite slow growth of Ni3Sn2, the bonding layer is stable and the strength of that doesn't change obviously with aging time. When aging temperature increased to 500°C, however, the residual Ni particles were gradually dissolved and the bonding layer formed a stable structure with dominated Ni3Sn2 after 36 h. Meanwhile, due to the volume shrinkage (4.43%) from Ni3Sn2 formation, a number of voids were formed. The shear strength shows an increase, resulting from Ni3Sn2 formation, but then it decreases slightly caused by voids. After aging at 500°C for 100 h, shear strength is still maintained at 29.6 MPa. In addition, the mechanism of void formation was analyzed and microstructural evolution model was also established.

Effect of Silver Flakes in Silver Paste on the Joining Process and Properties of Sandwich Power Modules (IGBTs Chip/Silver Paste/Bare Cu)

NASA Astrophysics Data System (ADS)

Zhao, Su-Yan; Li, Xin; Mei, Yun-Hui; Lu, Guo-Quan

2016-11-01

In this study, a silver paste has been introduced for attaching chips onto bare Cu substrates (without coating) without applying pressure. Small nano-thickness Ag flakes, measuring 1 μm-5 μm length, were embedded uniformly in Ag nanoparticles for improving the density of the material. The presence of silver flakes in the silver paste affected the joining process and its microstructure. Microstructure characterization revealed that densification of the silver layer was affected by the presence of silver flakes as the flakes coarsened and formed reactive in situ nanoparticles, which facilitated the sintering between the flakes and the incorporated nanoparticles. Coarsening of silver flakes depended on the sintering temperature, time, and the atmosphere, which affected the decomposition and burning out of organics presented on the surface of the flakes. A high-density silver layer was obtained due to the presence of compact silver flakes. With an increase in the microstructure density, a higher bonding strength and a lower thermal impedance of the sintered joints were achieved. On performing pressureless sintering at 270°C for 30 min under 99.99% N2 or 4% H2/N2, the bonding strength and thermal impedance for 11 × 11 mm2 chips were excellent, measuring approximately 21.9 MPa and 0.077°C/W, respectively.

CE chips fabricated by injection molding and polyethylene/thermoplastic elastomer film packaging methods.

PubMed

Huang, Fu-Chun; Chen, Yih-Far; Lee, Gwo-Bin

2007-04-01

This study presents a new packaging method using a polyethylene/thermoplastic elastomer (PE/TPE) film to seal an injection-molded CE chip made of either poly(methyl methacrylate) (PMMA) or polycarbonate (PC) materials. The packaging is performed at atmospheric pressure and at room temperature, which is a fast, easy, and reliable bonding method to form a sealed CE chip for chemical analysis and biomedical applications. The fabrication of PMMA and PC microfluidic channels is accomplished by using an injection-molding process, which could be mass-produced for commercial applications. In addition to microfluidic CE channels, 3-D reservoirs for storing biosamples, and CE buffers are also formed during this injection-molding process. With this approach, a commercial CE chip can be of low cost and disposable. Finally, the functionality of the mass-produced CE chip is demonstrated through its successful separation of phiX174 DNA/HaeIII markers. Experimental data show that the S/N for the CE chips using the PE/TPE film has a value of 5.34, when utilizing DNA markers with a concentration of 2 ng/microL and a CE buffer of 2% hydroxypropyl-methylcellulose (HPMC) in Tris-borate-EDTA (TBE) with 1% YO-PRO-1 fluorescent dye. Thus, the detection limit of the developed chips is improved. Lastly, the developed CE chips are used for the separation and detection of PCR products. A mixture of an amplified antibiotic gene for Streptococcus pneumoniae and phiX174 DNA/HaeIII markers was successfully separated and detected by using the proposed CE chips. Experimental data show that these DNA samples were separated within 2 min. The study proposed a promising method for the development of mass-produced CE chips.

Aluminum-Scandium: A Material for Semiconductor Packaging

NASA Astrophysics Data System (ADS)

Geissler, Ute; Thomas, Sven; Schneider-Ramelow, Martin; Mukhopadhyay, Biswajit; Lang, Klaus-Dieter

2016-10-01

A well-known aluminum-scandium (Al-Sc) alloy, already used in lightweight sports equipment, is about to be established for use in electronic packaging. One application for Al-Sc alloy is manufacture of bonding wires. The special feature of the alloy is its ability to harden by precipitation. The new bonding wires with electrical conductivity similar to pure Al wires can be processed on common wire bonders for aluminum wedge/wedge (w/w) bonding. The wires exhibit very fine-grained microstructure. Small Al3Sc particles are the main reason for its high strength and prevent recrystallization and grain growth at higher temperatures (>150°C). After the wire-bonding process, the interface is well closed. Reliability investigations by active power cycling demonstrated considerably improved lifetime compared with pure Al heavy wires. Furthermore, the Al-Sc alloy was sputter-deposited onto silicon wafer to test it as chip metallization in copper (Cu) ball/wedge bonding technology. After deposition, the layers exhibited fine-grained columnar structure and small coherent Al3Sc particles with dimensions of a few nanometers. These particles inhibit softening processes such as Al splashing in fine wire bonding processes and increase the thickness of remnant Al under the copper balls to 85% of the initial thickness.

Characterization of the Photon Counting CHASE Jr., Chip Built in a 40-nm CMOS Process With a Charge Sharing Correction Algorithm Using a Collimated X-Ray Beam

DOE Office of Scientific and Technical Information (OSTI.GOV)

Krzyżanowska, A.; Deptuch, G. W.; Maj, P.

This paper presents the detailed characterization of a single photon counting chip, named CHASE Jr., built in a CMOS 40-nm process, operating with synchrotron radiation. The chip utilizes an on-chip implementation of the C8P1 algorithm. The algorithm eliminates the charge sharing related uncertainties, namely, the dependence of the number of registered photons on the discriminator’s threshold, set for monochromatic irradiation, and errors in the assignment of an event to a certain pixel. The article presents a short description of the algorithm as well as the architecture of the CHASE Jr., chip. The analog and digital functionalities, allowing for proper operationmore » of the C8P1 algorithm are described, namely, an offset correction for two discriminators independently, two-stage gain correction, and different operation modes of the digital blocks. The results of tests of the C8P1 operation are presented for the chip bump bonded to a silicon sensor and exposed to the 3.5- μm -wide pencil beam of 8-keV photons of synchrotron radiation. It was studied how sensitive the algorithm performance is to the chip settings, as well as the uniformity of parameters of the analog front-end blocks. Presented results prove that the C8P1 algorithm enables counting all photons hitting the detector in between readout channels and retrieving the actual photon energy.« less

Investigation of ball bond integrity for 0.8 mil (20 microns) diameter gold bonding wire on low k die in wire bonding technology

NASA Astrophysics Data System (ADS)

Kudtarkar, Santosh Anil

Microelectronics technology has been undergoing continuous scaling to accommodate customer driven demand for smaller, faster and cheaper products. This demand has been satisfied by using novel materials, design techniques and processes. This results in challenges for the chip connection technology and also the package technology. The focus of this research endeavor was restricted to wire bond interconnect technology using gold bonding wires. Wire bond technology is often regarded as a simple first level interconnection technique. In reality, however, this is a complex process that requires a thorough understanding of the interactions between the design, material and process variables, and their impact on the reliability of the bond formed during this process. This research endeavor primarily focused on low diameter, 0.8 mil thick (20 mum) diameter gold bonding wire. Within the scope of this research, the integrity of the ball bond formed by 1.0 mil (25 mum) and 0.8 mil (20 mum) diameter wires was compared. This was followed by the evaluation of bonds formed on bond pads having doped SiO2 (low k) as underlying structures. In addition, the effect of varying the percentage of the wire dopant, palladium and bonding process parameters (bonding force, bond time, ultrasonic energy) for 0.8 mil (20 mum) bonding wire was also evaluated. Finally, a degradation empirical model was developed to understand the decrease in the wire strength. This research effort helped to develop a fundamental understanding of the various factors affecting the reliability of a ball bond from a design (low diameter bonding wire), material (low k and bonding wire dopants), and process (wire bonding process parameters) perspective for a first level interconnection technique, namely wire bonding. The significance of this research endeavor was the systematic investigation of the ball bonds formed using 0.8 mil (20 microm) gold bonding wire within the wire bonding arena. This research addressed low k structures on 90 nm silicon technology, bonding wires with different percentage of doping element (palladium), and different levels of bonding process parameters. An empirical model to understand the high temperature effects for bonds formed using the low diameter wire was also developed.

Advanced Flip Chips in Extreme Temperature Environments

NASA Technical Reports Server (NTRS)

Ramesham, Rajeshuni

2010-01-01

The use of underfill materials is necessary with flip-chip interconnect technology to redistribute stresses due to mismatching coefficients of thermal expansion (CTEs) between dissimilar materials in the overall assembly. Underfills are formulated using organic polymers and possibly inorganic filler materials. There are a few ways to apply the underfills with flip-chip technology. Traditional capillary-flow underfill materials now possess high flow speed and reduced time to cure, but they still require additional processing steps beyond the typical surface-mount technology (SMT) assembly process. Studies were conducted using underfills in a temperature range of -190 to 85 C, which resulted in an increase of reliability by one to two orders of magnitude. Thermal shock of the flip-chip test articles was designed to induce failures at the interconnect sites (-40 to 100 C). The study on the reliability of flip chips using underfills in the extreme temperature region is of significant value for space applications. This technology is considered as an enabling technology for future space missions. Flip-chip interconnect technology is an advanced electrical interconnection approach where the silicon die or chip is electrically connected, face down, to the substrate by reflowing solder bumps on area-array metallized terminals on the die to matching footprints of solder-wettable pads on the chosen substrate. This advanced flip-chip interconnect technology will significantly improve the performance of high-speed systems, productivity enhancement over manual wire bonding, self-alignment during die joining, low lead inductances, and reduced need for attachment of precious metals. The use of commercially developed no-flow fluxing underfills provides a means of reducing the processing steps employed in the traditional capillary flow methods to enhance SMT compatibility. Reliability of flip chips may be significantly increased by matching/tailoring the CTEs of the substrate material and the silicon die or chip, and also the underfill materials. Advanced packaging interconnects technology such as flip-chip interconnect test boards have been subjected to various extreme temperature ranges that cover military specifications and extreme Mars and asteroid environments. The eventual goal of each process step and the entire process is to produce components with 100 percent interconnect and satisfy the reliability requirements. Underfill materials, in general, may possibly meet demanding end use requirements such as low warpage, low stress, fine pitch, high reliability, and high adhesion.

Shrink film patterning by craft cutter: complete plastic chips with high resolution/high-aspect ratio channel.

PubMed

Taylor, Douglas; Dyer, David; Lew, Valerie; Khine, Michelle

2010-09-21

This paper presents a rapid, ultra-low-cost approach to fabricate microfluidic devices using a polyolefin shrink film and a digital craft cutter. The shrinking process (with a 95% reduction in area) results in relatively uniform and consistent microfluidic channels with smooth surfaces, vertical sidewalls, and high aspect ratio channels with lateral resolutions well beyond the tool used to cut them. The thermal bonding of the layers results in strongly bonded devices. Complex microfluidic designs are easily designed on the fly and protein assays are also readily integrated into the device. Full device characterization including channel consistency, optical properties, and bonding strength are assessed in this technical note.

A one-step strategy for ultra-fast and low-cost mass production of plastic membrane microfluidic chips.

PubMed

Hu, Chong; Lin, Sheng; Li, Wanbo; Sun, Han; Chen, Yangfan; Chan, Chiu-Wing; Leung, Chung-Hang; Ma, Dik-Lung; Wu, Hongkai; Ren, Kangning

2016-10-05

An ultra-fast, extremely cost-effective, and environmentally friendly method was developed for fabricating flexible microfluidic chips with plastic membranes. With this method, we could fabricate plastic microfluidic chips rapidly (within 12 seconds per piece) at an extremely low cost (less than $0.02 per piece). We used a heated perfluoropolymer perfluoroalkoxy (often called Teflon PFA) solid stamp to press a pile of two pieces of plastic membranes, low density polyethylene (LDPE) and polyethylene terephthalate (PET) coated with an ethylene-vinyl acetate copolymer (EVA). During the short period of contact with the heated PFA stamp, the pressed area of the membranes permanently bonded, while the LDPE membrane spontaneously rose up at the area not pressed, forming microchannels automatically. These two regions were clearly distinguishable even at the micrometer scale so we were able to fabricate microchannels with widths down to 50 microns. This method combines the two steps in the conventional strategy for microchannel fabrication, generating microchannels and sealing channels, into a single step. The production is a green process without using any solvent or generating any waste. Also, the chips showed good resistance against the absorption of Rhodamine 6G, oligonucleotides, and green fluorescent protein (GFP). We demonstrated some typical microfluidic manipulations with the flexible plastic membrane chips, including droplet formation, on-chip capillary electrophoresis, and peristaltic pumping for quantitative injection of samples and reagents. In addition, we demonstrated convenient on-chip detection of lead ions in water samples by a peristaltic-pumping design, as an example of the application of the plastic membrane chips in a resource-limited environment. Due to the high speed and low cost of the fabrication process, this single-step method will facilitate the mass production of microfluidic chips and commercialization of microfluidic technologies.

Discrete component bonding and thick film materials study. [of capacitor chips bonded with solders and conductive epoxies

NASA Technical Reports Server (NTRS)

Kinser, D. L.

1976-01-01

The bonding reliability of discrete capacitor chips bonded with solders and conductive epoxies was examined along with the thick film resistor materials consisting of iron oxide phosphate and vanadium oxide phosphates. It was concluded from the bonding reliability studies that none of the wide range of types of solders examined is capable of resisting failure during thermal cycling while the conductive epoxy gives substantially lower failure rates. The thick film resistor studies proved the feasibility of iron oxide phosphate resistor systems although some environmental sensitivity problems remain. One of these resistor compositions has inadvertently proven to be a candidate for thermistor applications because of the excellent control achieved upon the temperature coefficient of resistance. One new and potentially damaging phenomenon observed was the degradation of thick film conductors during the course of thermal cycling.

A strategy for design and fabrication of low cost microchannel for future reproductivity of bio/chemical lab-on-chip application

NASA Astrophysics Data System (ADS)

Humayun, Q.; Hashim, U.; Ruzaidi, C. M.; Noriman, N. Z.

2017-03-01

The fabrication and characterization of sensitive and selective fluids delivery system for the application of nano laboratory on a single chip is a challenging task till to date. This paper is one of the initial attempt to resolve this challenging task by using a simple, cost effective and reproductive technique for pattering a microchannel structures on SU-8 resist. The objective of the research is to design, fabricate and characterize polydimethylsiloxane (PDMS) microchannel. The proposed device mask was designed initially by using AutoCAD software and then the designed was transferred to transparency sheet and to commercial chrome mask for better photo masking process. The standard photolithography process coupled with wet chemical etching process was used for the fabrication of proposed microchannel. This is a low cost fabrication technique for the formation of microchannel structure at resist. The fabrication process start from microchannel formation and then the structure was transformed to PDMS substrate, the microchannel structure was cured from mold and then the cured mold was bonded with the glass substrate by plasma oxidation bonding process. The surface morphology was characterized by high power microscope (HPM) and the structure was characterized by Hawk 3 D surface nanoprofiler. The next part of the research will be focus onto device testing and validation by using real biological samples by the implementation of a simple manual injection technique.

Feasibility study of silicon nitride protection of plastic encapsulated semiconductors

NASA Technical Reports Server (NTRS)

Peters, J. W.; Hall, T. C.; Erickson, J. J.; Gebhart, F. L.

1979-01-01

The application of low temperature silicon nitride protective layers on wire bonded integrated circuits mounted on lead frame assemblies is reported. An evaluation of the mechanical and electrical compatibility of both plasma nitride and photochemical silicon nitride (photonitride) passivations (parallel evaluations) of integrated circuits which were then encapsulated in plastic is described. Photonitride passivation is compatible with all wire bonded lead frame assemblies, with or without initial chip passivation. Plasma nitride passivation of lead frame assemblies is possible only if the chip is passivated before lead frame assembly. The survival rate after the environmental test sequence of devices with a coating of plasma nitride on the chip and a coating of either plasma nitride or photonitride over the assembled device is significantly greater than that of devices assembled with no nitride protective coating over either chip or lead frame.

Flexible packaging of solid-state integrated circuit chips with elastomeric microfluidics

PubMed Central

Zhang, Bowei; Dong, Quan; Korman, Can E.; Li, Zhenyu; Zaghloul, Mona E.

2013-01-01

A flexible technology is proposed to integrate smart electronics and microfluidics all embedded in an elastomer package. The microfluidic channels are used to deliver both liquid samples and liquid metals to the integrated circuits (ICs). The liquid metals are used to realize electrical interconnects to the IC chip. This avoids the traditional IC packaging challenges, such as wire-bonding and flip-chip bonding, which are not compatible with current microfluidic technologies. As a demonstration we integrated a CMOS magnetic sensor chip and associate microfluidic channels on a polydimethylsiloxane (PDMS) substrate that allows precise delivery of small liquid samples to the sensor. Furthermore, the packaged system is fully functional under bending curvature radius of one centimetre and uniaxial strain of 15%. The flexible integration of solid-state ICs with microfluidics enables compact flexible electronic and lab-on-a-chip systems, which hold great potential for wearable health monitoring, point-of-care diagnostics and environmental sensing among many other applications.

Test systems of the STS-XYTER2 ASIC: from wafer-level to in-system verification

NASA Astrophysics Data System (ADS)

Kasinski, Krzysztof; Zubrzycka, Weronika

2016-09-01

The STS/MUCH-XYTER2 ASIC is a full-size prototype chip for the Silicon Tracking System (STS) and Muon Chamber (MUCH) detectors in the new fixed-target experiment Compressed Baryonic Matter (CBM) at FAIR-center, Darmstadt, Germany. The STS assembly includes more than 14000 ASICs. The complicated, time-consuming, multi-step assembly process of the detector building blocks and tight quality assurance requirements impose several intermediate testing to be performed for verifying crucial assembly steps (e.g. custom microcable tab-bonding before wire-bonding to the PCB) and - if necessary - identifying channels or modules for rework. The chip supports the multi-level testing with different probing / contact methods (wafer probe-card, pogo-probes, in-system tests). A huge number of ASICs to be tested restricts the number and kind of tests possible to be performed within a reasonable time. The proposed architectures of test stand equipment and a brief summary of methodologies are presented in this paper.

A Microsystem Based on Porous Silicon-Glass Anodic Bonding for Gas and Liquid Optical Sensing

PubMed Central

De Stefano, Luca; Malecki, Krzysztof; Della Corte, Francesco G.; Moretti, Luigi; Rea, Ilaria; Rotiroti, Lucia; Rendina, Ivo

2006-01-01

We have recently presented an integrated silicon-glass opto-chemical sensor for lab-on-chip applications, based on porous silicon and anodic bonding technologies. In this work, we have optically characterized the sensor response on exposure to vapors of several organic compounds by means of reflectivity measurements. The interaction between the porous silicon, which acts as transducer layer, and the organic vapors fluxed into the glass sealed microchamber, is preserved by the fabrication process, resulting in optical path increase, due to the capillary condensation of the vapors into the pores. Using the Bruggemann theory, we have calculated the filled pores volume for each substance. The sensor dynamic has been described by time-resolved measurements: due to the analysis chamber miniaturization, the response time is only of 2 s. All these results have been compared with data acquired on the same PSi structure before the anodic bonding process.

Platform technologies for hybrid optoelectronic integration and packaging

NASA Astrophysics Data System (ADS)

Datta, Madhumita

In order to bring fiber-optics closer to individual home and business services, the optical network components have to be inexpensive and reliable. Integration and packaging of optoelectronic devices holds the key to high-volume low-cost component manufacturing. The goal of this dissertation is to propose, study, and demonstrate various ways to integrate optoelectronic devices on a packaging platform to implement cost-effective, functional optical modules. Two types of hybrid integration techniques have been proposed: flip-chip solder bump bonding for high-density two-dimensional array packaging of surface-emitting devices, and solder preform bonding for fiber-coupled edge-emitting semiconductor devices. For flip-chip solder bump bonding, we developed a simple, inexpensive remetallization process called "electroless plating", which converts the aluminum bond pads of foundry-made complementary metal oxide semiconductor (CMOS) chips into solder-bondable and wire-bondable gold surfaces. We have applied for a patent on this remetallization technique. For fiber-pigtailed edge-emitting laser modules, we have studied the coupling characteristics of different types of lensed single-mode fibers including semispherically lensed fiber, cylindrically lensed fiber and conically lensed fiber. We have experimentally demonstrated 66% coupling efficiency with semispherically lensed fiber and 50% efficiency with conically lensed fibers. We have proposed and designed a packaging platform on which lensed fibers can be actively aligned to a laser and solder-attached reliably to the platform so that the alignment is retained. We have designed thin-film nichrome heaters on fused quartz platforms as local heat source to facilitate on-board solder alignment and attachment of fiber. The thermal performance of the heaters was simulated using finite element analysis tool ANSYS prior to fabrication. Using the heater's reworkability advantage, we have estimated the shift of the fiber due to solder shrinkage and introduced a pre-correction in the alignment process to restore optimum coupling efficiency close to 50% with conically lensed fibers. We have applied for a patent on this unique active alignment method through the University of Maryland's Technology Commercialization Office. Although we have mostly concentrated on active alignment platforms, we have proposed the idea of combining the passive alignment advantages of silicon optical benches to the on-board heater-assisted active alignment technique. This passive-active alignment process has the potential of cost-effective array packaging of edge-emitting devices.

High performance low cost interconnections for flip chip attachment with electrically conductive adhesive. Final report

DOE Office of Scientific and Technical Information (OSTI.GOV)

NONE

1998-05-01

This final report is a compilation of final reports from each of the groups participating in the program. The main three groups involved in this effort are the Thomas J. Watson Research Center of IBM Corporation in Yorktown Heights, New York, Assembly Process Design of IBM Corporation in Endicott, New York, and SMT Laboratory of Universal Instruments Corporation in Binghamton, New York. The group at the research center focused on the conductive adhesive materials development and characterization. The group in process development focused on processing of the Polymer-Metal-Solvent Paste (PMSP) to form conductive adhesive bumps, formation of the Polymer-Metal Compositemore » (PMC) on semiconductor devices and study of the bonding process to circuitized organic carriers, and the long term durability and reliability of joints formed using the process. The group at Universal Instruments focused on development of an equipment set and bonding parameters for the equipment to produce bond assembly tooling. Reports of each of these individual groups are presented here reviewing their technical efforts and achievements.« less

AIN-Based Packaging for SiC High-Temperature Electronics

NASA Technical Reports Server (NTRS)

Savrun, Ender

2004-01-01

Packaging made primarily of aluminum nitride has been developed to enclose silicon carbide-based integrated circuits (ICs), including circuits containing SiC-based power diodes, that are capable of operation under conditions more severe than can be withstood by silicon-based integrated circuits. A major objective of this development was to enable packaged SiC electronic circuits to operate continuously at temperatures up to 500 C. AlN-packaged SiC electronic circuits have commercial potential for incorporation into high-power electronic equipment and into sensors that must withstand high temperatures and/or high pressures in diverse applications that include exploration in outer space, well logging, and monitoring of nuclear power systems. This packaging embodies concepts drawn from flip-chip packaging of silicon-based integrated circuits. One or more SiC-based circuit chips are mounted on an aluminum nitride package substrate or sandwiched between two such substrates. Intimate electrical connections between metal conductors on the chip(s) and the metal conductors on external circuits are made by direct bonding to interconnections on the package substrate(s) and/or by use of holes through the package substrate(s). This approach eliminates the need for wire bonds, which have been the most vulnerable links in conventional electronic circuitry in hostile environments. Moreover, the elimination of wire bonds makes it possible to pack chips more densely than was previously possible.

Significance of wood extractives for wood bonding.

PubMed

Roffael, Edmone

2016-02-01

Wood contains primary extractives, which are present in all woods, and secondary extractives, which are confined in certain wood species. Extractives in wood play a major role in wood-bonding processes, as they can contribute to or determine the bonding relevant properties of wood such as acidity and wettability. Therefore, extractives play an immanent role in bonding of wood chips and wood fibres with common synthetic adhesives such as urea-formaldehyde-resins (UF-resins) and phenol-formaldehyde-resins (PF-resins). Extractives of high acidity accelerate the curing of acid curing UF-resins and decelerate bonding with alkaline hardening PF-resins. Water-soluble extractives like free sugars are detrimental for bonding of wood with cement. Polyphenolic extractives (tannins) can be used as a binder in the wood-based industry. Additionally, extractives in wood can react with formaldehyde and reduce the formaldehyde emission of wood-based panels. Moreover, some wood extractives are volatile organic compounds (VOC) and insofar also relevant to the emission of VOC from wood and wood-based panels.

Pressure activated diaphragm bonder

DOEpatents

Evans, L.B.; Malba, V.

1997-05-27

A device is available for bonding one component to another, particularly for bonding electronic components of integrated circuits, such as chips, to a substrate. The bonder device in one embodiment includes a bottom metal block having a machined opening wherein a substrate is located, a template having machined openings which match solder patterns on the substrate, a thin diaphragm placed over the template after the chips have been positioned in the openings therein, and a top metal block positioned over the diaphragm and secured to the bottom block, with the diaphragm retained therebetween. The top block includes a countersink portion which extends over at least the area of the template and an opening through which a high pressure inert gas is supplied to exert uniform pressure distribution over the diaphragm to keep the chips in place during soldering. A heating means is provided to melt the solder patterns on the substrate and thereby solder the chips thereto. 4 figs.

Pressure activated diaphragm bonder

DOEpatents

Evans, Leland B.; Malba, Vincent

1997-01-01

A device is available for bonding one component to another, particularly for bonding electronic components of integrated circuits, such as chips, to a substrate. The bonder device in one embodiment includes a bottom metal block having a machined opening wherein a substrate is located, a template having machined openings which match solder patterns on the substrate, a thin diaphragm placed over the template after the chips have been positioned in the openings therein, and a top metal block positioned over the diaphragm and secured to the bottom block, with the diaphragm retained therebetween. The top block includes a countersink portion which extends over at least the area of the template and an opening through which a high pressure inert gas is supplied to exert uniform pressure distribution over the diaphragm to keep the chips in place during soldering. A heating means is provided to melt the solder patterns on the substrate and thereby solder the chips thereto.

Creating Sub-50 Nm Nanofluidic Junctions in PDMS Microfluidic Chip via Self-Assembly Process of Colloidal Particles

PubMed Central

Wei, Xi; Syed, Abeer; Mao, Pan; Han, Jongyoon; Song, Yong-Ak

2016-01-01

Polydimethylsiloxane (PDMS) is the prevailing building material to make microfluidic devices due to its ease of molding and bonding as well as its transparency. Due to the softness of the PDMS material, however, it is challenging to use PDMS for building nanochannels. The channels tend to collapse easily during plasma bonding. In this paper, we present an evaporation-driven self-assembly method of silica colloidal nanoparticles to create nanofluidic junctions with sub-50 nm pores between two microchannels. The pore size as well as the surface charge of the nanofluidic junction is tunable simply by changing the colloidal silica bead size and surface functionalization outside of the assembled microfluidic device in a vial before the self-assembly process. Using the self-assembly of nanoparticles with a bead size of 300 nm, 500 nm, and 900 nm, it was possible to fabricate a porous membrane with a pore size of ~45 nm, ~75 nm and ~135 nm, respectively. Under electrical potential, this nanoporous membrane initiated ion concentration polarization (ICP) acting as a cation-selective membrane to concentrate DNA by ~1,700 times within 15 min. This non-lithographic nanofabrication process opens up a new opportunity to build a tunable nanofluidic junction for the study of nanoscale transport processes of ions and molecules inside a PDMS microfluidic chip. PMID:27023724

Hybrid UV Imager Containing Face-Up AlGaN/GaN Photodiodes

NASA Technical Reports Server (NTRS)

Zheng, Xinyu; Pain, Bedabrata

2005-01-01

A proposed hybrid ultraviolet (UV) image sensor would comprise a planar membrane array of face-up AlGaN/GaN photodiodes integrated with a complementary metal oxide/semiconductor (CMOS) readout-circuit chip. Each pixel in the hybrid image sensor would contain a UV photodiode on the AlGaN/GaN membrane, metal oxide/semiconductor field-effect transistor (MOSFET) readout circuitry on the CMOS chip underneath the photodiode, and a metal via connection between the photodiode and the readout circuitry (see figure). The proposed sensor design would offer all the advantages of comparable prior CMOS active-pixel sensors and AlGaN UV detectors while overcoming some of the limitations of prior (AlGaN/sapphire)/CMOS hybrid image sensors that have been designed and fabricated according to the methodology of flip-chip integration. AlGaN is a nearly ideal UV-detector material because its bandgap is wide and adjustable and it offers the potential to attain extremely low dark current. Integration of AlGaN with CMOS is necessary because at present there are no practical means of realizing readout circuitry in the AlGaN/GaN material system, whereas the means of realizing readout circuitry in CMOS are well established. In one variant of the flip-chip approach to integration, an AlGaN chip on a sapphire substrate is inverted (flipped) and then bump-bonded to a CMOS readout circuit chip; this variant results in poor quantum efficiency. In another variant of the flip-chip approach, an AlGaN chip on a crystalline AlN substrate would be bonded to a CMOS readout circuit chip; this variant is expected to result in narrow spectral response, which would be undesirable in many applications. Two other major disadvantages of flip-chip integration are large pixel size (a consequence of the need to devote sufficient area to each bump bond) and severe restriction on the photodetector structure. The membrane array of AlGaN/GaN photodiodes and the CMOS readout circuit for the proposed image sensor would be fabricated separately.

Packaged integrated opto-fluidic solution for harmful fluid analysis

NASA Astrophysics Data System (ADS)

Allenet, T.; Bucci, D.; Geoffray, F.; Canto, F.; Couston, L.; Jardinier, E.; Broquin, J.-E.

2016-02-01

Advances in nuclear fuel reprocessing have led to a surging need for novel chemical analysis tools. In this paper, we present a packaged lab-on-chip approach with co-integration of optical and micro-fluidic functions on a glass substrate as a solution. A chip was built and packaged to obtain light/fluid interaction in order for the entire device to make spectral measurements using the photo spectroscopy absorption principle. The interaction between the analyte solution and light takes place at the boundary between a waveguide and a fluid micro-channel thanks to the evanescent part of the waveguide's guided mode that propagates into the fluid. The waveguide was obtained via ion exchange on a glass wafer. The input and the output of the waveguides were pigtailed with standard single mode optical fibers. The micro-scale fluid channel was elaborated with a lithography procedure and hydrofluoric acid wet etching resulting in a 150+/-8 μm deep channel. The channel was designed with fluidic accesses, in order for the chip to be compatible with commercial fluidic interfaces/chip mounts. This allows for analyte fluid in external capillaries to be pumped into the device through micro-pipes, hence resulting in a fully packaged chip. In order to produce this co-integrated structure, two substrates were bonded. A study of direct glass wafer-to-wafer molecular bonding was carried-out to improve detector sturdiness and durability and put forward a bonding protocol with a bonding surface energy of γ>2.0 J.m-2. Detector viability was shown by obtaining optical mode measurements and detecting traces of 1.2 M neodymium (Nd) solute in 12+/-1 μL of 0.01 M and pH 2 nitric acid (HNO3) solvent by obtaining an absorption peak specific to neodymium at 795 nm.

27 CFR 19.318 - Addition of caramel to rum or brandy and addition of oak chips to spirits.

Code of Federal Regulations, 2010 CFR

2010-04-01

... or brandy and addition of oak chips to spirits. 19.318 Section 19.318 Alcohol, Tobacco Products and... PLANTS Production § 19.318 Addition of caramel to rum or brandy and addition of oak chips to spirits. Caramel possessing no material sweetening properties may be added to rum or brandy on bonded premises...

Multilayer based lab-on-a-chip-systems for substance testing

NASA Astrophysics Data System (ADS)

Sonntag, Frank; Grünzner, Stefan; Schmieder, Florian; Busek, Mathias; Klotzbach, Udo; Franke, Volker

2015-03-01

An integrated technology chain for laser-microstructuring and bonding of polymer foils for fast, flexible and low-cost manufacturing of multilayer lab-on-a-chip devices especially for complex cell and tissue culture applications, which provides pulsatile fluid flow within physiological ranges at low media-to-cells ratio, was developed and established. Initially the microfluidic system is constructively divided into individual layers which are formed by separate foils or plates. Based on the functional boundary conditions and the necessary properties of each layer the corresponding foils and plates are chosen. In the third step the foils and plates are laser microstructured and functionalized from both sides. In the fourth and last manufacturing step the multiple plates and foils are joined using thermal diffusion bonding. Membranes for pneumatically driven valves and micropumps where bonded via chemical surface modification. Based on the established lab-on-a-chip platform for perfused cell-based assays, a multilayer microfluidic system with two parallel connected cell culture chambers was successfully implemented.

Fabrication of Cantilever-Bump Type Si Probe Card

NASA Astrophysics Data System (ADS)

Park, Jeong-Yong; Lee, Dong-Seok; Kim, Dong-Kwon; Lee, Jong-Hyun

2000-12-01

Probe card is most important part in the test system which selects the good or bad chip of integrated circuit (IC) chips. Silicon vertical probe card is able to test multiple semiconductor chips simultaneously. We presented cantilever-bump type vertical probe card. It was fabricated by dry etching using RIE(reactive ion etching) technique and porous silicon micromachining using silicon direct bonded (SDB) wafer. Cantilevers and bumps were fabricated by isotropic etching using RIE@. 3-dimensional structures were formed by porous silicon micromachining technique using SDB wafer. Contact resistance of fabricated probe card was less than 2 Ω and its life time was more than 200,000 turns. The process used in this work is very simple and reproducible, which has good controllability in the tip dimension and spacing. It is expected that the fabricated probe card can reduce testing time, can promote productivity and enables burn-in test.

A monolithic glass chip for active single-cell sorting based on mechanical phenotyping.

PubMed

Faigle, Christoph; Lautenschläger, Franziska; Whyte, Graeme; Homewood, Philip; Martín-Badosa, Estela; Guck, Jochen

2015-03-07

The mechanical properties of biological cells have long been considered as inherent markers of biological function and disease. However, the screening and active sorting of heterogeneous populations based on serial single-cell mechanical measurements has not been demonstrated. Here we present a novel monolithic glass chip for combined fluorescence detection and mechanical phenotyping using an optical stretcher. A new design and manufacturing process, involving the bonding of two asymmetrically etched glass plates, combines exact optical fiber alignment, low laser damage threshold and high imaging quality with the possibility of several microfluidic inlet and outlet channels. We show the utility of such a custom-built optical stretcher glass chip by measuring and sorting single cells in a heterogeneous population based on their different mechanical properties and verify sorting accuracy by simultaneous fluorescence detection. This offers new possibilities of exact characterization and sorting of small populations based on rheological properties for biological and biomedical applications.

Ultra-compact 32 × 32 strictly-non-blocking Si-wire optical switch with fan-out LGA interposer.

PubMed

Tanizawa, Ken; Suzuki, Keijiro; Toyama, Munehiro; Ohtsuka, Minoru; Yokoyama, Nobuyuki; Matsumaro, Kazuyuki; Seki, Miyoshi; Koshino, Keiji; Sugaya, Toshio; Suda, Satoshi; Cong, Guangwei; Kimura, Toshio; Ikeda, Kazuhiro; Namiki, Shu; Kawashima, Hitoshi

2015-06-29

We demonstrate a 32 × 32 path-independent-insertion-loss optical path switch that integrates 1024 thermooptic Mach-Zehnder switches and 961 intersections on a small, 11 × 25 mm2 die. The switch is fabricated on a 300-mm-diameter silicon-on-insulator wafer by a complementary metal-oxide semiconductor-compatible process with advanced ArF immersion lithography. For reliable electrical packaging, the switch chip is flip-chip bonded to a ceramic interposer that arranges the electrodes in a 0.5-mm pitch land grid array. The on-chip loss is measured to be 15.8 ± 1.0 dB, and successful switching is demonstrated for digital-coherent 43-Gb/s QPSK signals. The total crosstalk of the switch is estimated to be less than -20 dB at the center wavelength of 1545 nm. The bandwidth narrowing caused by dimensional errors that arise during fabrication is discussed.

Contamination control in hybrid microelectronic modules. Part 2: Selection and evaluation of coating materials

NASA Technical Reports Server (NTRS)

Himmel, R. P.

1975-01-01

The selection, test, and evaluation of organic coating materials for contamination control in hybrid circuits is reported. The coatings were evaluated to determine their suitability for use as a conformal coating over the hybrid microcircuit (including chips and wire bonds) inside a hermetically sealed package. Evaluations included ease of coating application and repair and effect on thin film and thick film resistors, beam leads, wire bonds, transistor chips, and capacitor chips. The coatings were also tested for such properties as insulation resistance, voltage breakdown strength, and capability of immobilizing loose particles inside the packages. The selected coatings were found to be electrically, mechanically, and chemically compatible with all components and materials normally used in hybrid microcircuits.

Improvement of modulation bandwidth in electroabsorption-modulated laser by utilizing the resonance property in bonding wire.

PubMed

Kwon, Oh Kee; Han, Young Tak; Baek, Yong Soon; Chung, Yun C

2012-05-21

We present and demonstrate a simple and cost-effective technique for improving the modulation bandwidth of electroabsorption-modulated laser (EML). This technique utilizes the RF resonance caused by the EML chip (i.e., junction capacitance) and bonding wire (i.e, wire inductance). We analyze the effects of the lengths of the bonding wires on the frequency responses of EML by using an equivalent circuit model. To verify this analysis, we package a lumped EML chip on the sub-mount and measure its frequency responses. The results show that, by using the proposed technique, we can increase the modulation bandwidth of EML from ~16 GHz to ~28 GHz.

Hot embossing and thermal bonding of poly(methyl methacrylate) microfluidic chips using positive temperature coefficient ceramic heater.

PubMed

Wang, Xia; Zhang, Luyan; Chen, Gang

2011-11-01

As a self-regulating heating device, positive temperature coefficient ceramic heater was employed for hot embossing and thermal bonding of poly(methyl methacrylate) microfluidic chip because it supplied constant-temperature heating without electrical control circuits. To emboss a channel plate, a piece of poly(methyl methacrylate) plate was sandwiched between a template and a microscopic glass slide on a positive temperature coefficient ceramic heater. All the assembled components were pressed between two elastic press heads of a spring-driven press while a voltage was applied to the heater for 10 min. Subsequently, the embossed poly(methyl methacrylate) plate bearing negative relief of channel networks was bonded with a piece of poly(methyl methacrylate) cover sheet to obtain a complete microchip using a positive temperature coefficient ceramic heater and a spring-driven press. High quality microfluidic chips fabricated by using the novel embossing/bonding device were successfully applied in the electrophoretic separation of three cations. Positive temperature coefficient ceramic heater indicates great promise for the low-cost production of poly(methyl methacrylate) microchips and should find wide applications in the fabrication of other thermoplastic polymer microfluidic devices.

Adaptive Optoelectronic Eyes: Hybrid Sensor/Processor Architectures

DTIC Science & Technology

2006-11-13

corresponding calculated data. The width of the mirror stopband is proportional to the refractive index difference between the high and low index materials ...Silicon VLSI Neuron Unit Arrays 56 Development of a Single-Sided Flip-Chip Bonding Process 65 Development of High Refractive Index Diffractive Optical ...Elements (DOEs) 68 Development of High-Performance Antireflection Coatings for High Refractive Index DOEs 69 Design and Fabrication of Low Threshold

Edge chipping and flexural resistance of monolithic ceramics☆

PubMed Central

Zhang, Yu; Lee, James J.-W.; Srikanth, Ramanathan; Lawn, Brian R.

2014-01-01

Objective Test the hypothesis that monolithic ceramics can be developed with combined esthetics and superior fracture resistance to circumvent processing and performance drawbacks of traditional all-ceramic crowns and fixed-dental-prostheses consisting of a hard and strong core with an esthetic porcelain veneer. Specifically, to demonstrate that monolithic prostheses can be produced with a much reduced susceptibility to fracture. Methods Protocols were applied for quantifying resistance to chipping as well as resistance to flexural failure in two classes of dental ceramic, microstructurally-modified zirconias and lithium disilicate glass–ceramics. A sharp indenter was used to induce chips near the edges of flat-layer specimens, and the results compared with predictions from a critical load equation. The critical loads required to produce cementation surface failure in monolithic specimens bonded to dentin were computed from established flexural strength relations and the predictions validated with experimental data. Results Monolithic zirconias have superior chipping and flexural fracture resistance relative to their veneered counterparts. While they have superior esthetics, glass–ceramics exhibit lower strength but higher chip fracture resistance relative to porcelain-veneered zirconias. Significance The study suggests a promising future for new and improved monolithic ceramic restorations, with combined durability and acceptable esthetics. PMID:24139756

Module comprising IC memory stack dedicated to and structurally combined with an IC microprocessor chip

NASA Technical Reports Server (NTRS)

Carson, John C. (Inventor); Indin, Ronald J. (Inventor); Shanken, Stuart N. (Inventor)

1994-01-01

A computer module is disclosed in which a stack of glued together IC memory chips is structurally integrated with a microprocessor chip. The memory provided by the stack is dedicated to the microprocessor chip. The microprocessor and its memory stack may be connected either by glue and/or by solder bumps. The solder bumps can perform three functions--electrical interconnection, mechanical connection, and heat transfer. The electrical connections in some versions are provided by wire bonding.

Sparsely-Bonded CMOS Hybrid Imager

NASA Technical Reports Server (NTRS)

Sun, Chao (Inventor); Jones, Todd J. (Inventor); Nikzad, Shouleh (Inventor); Newton, Kenneth W. (Inventor); Cunningham, Thomas J. (Inventor); Hancock, Bruce R. (Inventor); Dickie, Matthew R. (Inventor); Hoenk, Michael E. (Inventor); Wrigley, Christopher J. (Inventor); Pain, Bedabrata (Inventor)

2015-01-01

A method and device for imaging or detecting electromagnetic radiation is provided. A device structure includes a first chip interconnected with a second chip. The first chip includes a detector array, wherein the detector array comprises a plurality of light sensors and one or more transistors. The second chip includes a Read Out Integrated Circuit (ROIC) that reads out, via the transistors, a signal produced by the light sensors. A number of interconnects between the ROIC and the detector array can be less than one per light sensor or pixel.

Modular integration of electronics and microfluidic systems using flexible printed circuit boards.

PubMed

Wu, Amy; Wang, Lisen; Jensen, Erik; Mathies, Richard; Boser, Bernhard

2010-02-21

Microfluidic systems offer an attractive alternative to conventional wet chemical methods with benefits including reduced sample and reagent volumes, shorter reaction times, high-throughput, automation, and low cost. However, most present microfluidic systems rely on external means to analyze reaction products. This substantially adds to the size, complexity, and cost of the overall system. Electronic detection based on sub-millimetre size integrated circuits (ICs) has been demonstrated for a wide range of targets including nucleic and amino acids, but deployment of this technology to date has been limited due to the lack of a flexible process to integrate these chips within microfluidic devices. This paper presents a modular and inexpensive process to integrate ICs with microfluidic systems based on standard printed circuit board (PCB) technology to assemble the independently designed microfluidic and electronic components. The integrated system can accommodate multiple chips of different sizes bonded to glass or PDMS microfluidic systems. Since IC chips and flex PCB manufacturing and assembly are industry standards with low cost, the integrated system is economical for both laboratory and point-of-care settings.

Submillimeter-Wave Amplifier Module with Integrated Waveguide Transitions

NASA Technical Reports Server (NTRS)

Samoska, Lorene; Chattopadhyay, Goutam; Pukala, David; Gaier, Todd; Soria, Mary; ManFung, King; Deal, William; Mei, Gerry; Radisic, Vesna; Lai, Richard

2009-01-01

To increase the usefulness of monolithic millimeter-wave integrated circuit (MMIC) components at submillimeter-wave frequencies, a chip has been designed that incorporates two integrated, radial E-plane probes with an MMIC amplifier in between, thus creating a fully integrated waveguide module. The integrated amplifier chip has been fabricated in 35-nm gate length InP high-electron-mobility-transistor (HEMT) technology. The radial probes were mated to grounded coplanar waveguide input and output lines in the internal amplifier. The total length of the internal HEMT amplifier is 550 m, while the total integrated chip length is 1,085 m. The chip thickness is 50 m with the chip width being 320 m. The internal MMIC amplifier is biased through wire-bond connections to the gates and drains of the chip. The chip has 3 stages, employing 35-nm gate length transistors in each stage. Wire bonds from the DC drain and gate pads are connected to off-chip shunt 51-pF capacitors, and additional off-chip capacitors and resistors are added to the gate and drain bias lines for low-frequency stability of the amplifier. Additionally, bond wires to the grounded coplanar waveguide pads at the RF input and output of the internal amplifier are added to ensure good ground connections to the waveguide package. The S-parameters of the module, not corrected for input or output waveguide loss, are measured at the waveguide flange edges. The amplifier module has over 10 dB of gain from 290 to 330 GHz, with a peak gain of over 14 dB at 307 GHz. The WR2.2 waveguide cutoff is again observed at 268 GHz. The module is biased at a drain current of 27 mA, a drain voltage of 1.24 V, and a gate voltage of +0.21 V. Return loss of the module is very good between 5 to 25 dB. This result illustrates the usefulness of the integrated radial probe transition, and the wide (over 10-percent) bandwidth that one can expect for amplifier modules with integrated radial probes in the submillimeter-regime (>300 GHz).

A PDMS membrane microvalve with one-dimensional line valve seat for robust microfluidics

NASA Astrophysics Data System (ADS)

Park, Chin-Sung; Hwang, Kyu-Youn; Jung, Wonjong; Namkoong, Kak; Chung, Wonseok; Kim, Joon-Ho; Huh, Nam

2014-02-01

We have developed a monolithic polydimethylsiloxane (PDMS) membrane microvalve with an isotropically etched valve seat for robust microfluidics. In order to avoid bonding or sticking of the PDMS membrane to the valve seat during the bonding process, the valve seat was wet-etched to be a one-dimensional line instead of a plane. The simple wet-etching technique allowed for the fabrication of an anti-bonding architecture in a scalable manner, and it intrinsically prevented contact between the PDMS membrane and valve seat when no external force was applied (i.e., normally open). This approach enables the permanent device assembly so that the microfluidic chip can be operable in a wide range of fluid pressures (e.g., over 200 kPa) without any leakage and sticking problems.

Microfluidic "thin chips" for chemical separations.

PubMed

Gaspar, Attila; Salgado, Marisol; Stevens, Schetema; Gomez, Frank A

2010-08-01

This paper describes the design, development and application of microfluidic "thin chips" fabricated from PDMS. Thin chips consist of multiple layers of PDMS chemically bonded onto each other. Unlike thicker PDMS chips that suffer from lack of sensitivity due to PDMS absorption in the VIS and UV range, the thinness of these chips allows for the detection of chromophoric species within the microchannel via an external fiber optics detection system. C18-modified reversed-phase silica particles are packed into the microchannel using a temporary taper created by a magnetic valve and separations using both pressure- and electrochromatographic-driven methods are detailed.

Grinding damage assessment on four high-strength ceramics.

PubMed

Canneto, Jean-Jacques; Cattani-Lorente, Maria; Durual, Stéphane; Wiskott, Anselm H W; Scherrer, Susanne S

2016-02-01

The purpose of this study was to assess surface and subsurface damage on 4 CAD-CAM high-strength ceramics after grinding with diamond disks of 75 μm, 54 μm and 18 μm and to estimate strength losses based on damage crack sizes. The materials tested were: 3Y-TZP (Lava), dense Al2O3 (In-Ceram AL), alumina glass-infiltrated (In-Ceram ALUMINA) and alumina-zirconia glass-infiltrated (In-Ceram ZIRCONIA). Rectangular specimens with 2 mirror polished orthogonal sides were bonded pairwise together prior to degrading the top polished surface with diamond disks of either 75 μm, 54 μm or 18 μm. The induced chip damage was evaluated on the bonded interface using SEM for chip depth measurements. Fracture mechanics were used to estimate fracture stresses based on average and maximum chip depths considering these as critical flaws subjected to tension and to calculate possible losses in strength compared to manufacturer's data. 3Y-TZP was hardly affected by grinding chip damage viewed on the bonded interface. Average chip depths were of 12.7±5.2 μm when grinding with 75 μm diamond inducing an estimated loss of 12% in strength compared to manufacturer's reported flexural strength values of 1100 MPa. Dense alumina showed elongated chip cracks and was suffering damage of an average chip depth of 48.2±16.3 μm after 75 μm grinding, representing an estimated loss in strength of 49%. Grinding with 54 μm was creating chips of 32.2±9.1 μm in average, representing a loss in strength of 23%. Alumina glass-infiltrated ceramic was exposed to chipping after 75 μm (mean chip size=62.4±19.3 μm) and 54 μm grinding (mean chip size=42.8±16.6 μm), with respectively 38% and 25% estimated loss in strength. Alumina-zirconia glass-infiltrated ceramic was mainly affected by 75 μm grinding damage with a chip average size of 56.8±15.1 μm, representing an estimated loss in strength of 34%. All four ceramics were not exposed to critical chipping at 18 μm diamond grinding. Reshaping a ceramic framework post sintering should be avoided with final diamond grits of 75 μm as a general rule. For alumina and the glass-infiltrated alumina, using a 54 μm diamond still induces chip damage which may affect strength. Removal of such damage from a reshaped framework is mandatory by using sequentially finer diamonds prior to the application of veneering ceramics especially in critical areas such as margins, connectors and inner surfaces. Copyright © 2015 Academy of Dental Materials. Published by Elsevier Ltd. All rights reserved.

Fluxless flip-chip bonding using a lead-free solder bumping technique

NASA Astrophysics Data System (ADS)

Hansen, K.; Kousar, S.; Pitzl, D.; Arab, S.

2017-09-01

With the LHC exceeding the nominal instantaneous luminosity, the current barrel pixel detector (BPIX) of the CMS experiment at CERN will reach its performance limits and undergo significant radiation damage. In order to improve detector performance in high luminosity conditions, the entire BPIX is replaced with an upgraded version containing an additional detection layer. Half of the modules comprising this additional layer are produced at DESY using fluxless and lead-free bumping and bonding techniques. Sequential solder-jetting technique is utilized to wet 40-μm SAC305 solder spheres on the silicon-sensor pads with electroless Ni, Pd and immersion Au (ENEPIG) under-bump metallization (UBM). The bumped sensors are flip-chip assembled with readout chips (ROCs) and then reflowed using a flux-less bonding facility. The challenges for jetting low solder volume have been analyzed and will be presented in this paper. An average speed of 3.4 balls per second is obtained to jet about 67 thousand solder balls on a single chip. On average, 7 modules have been produced per week. The bump-bond quality is evaluated in terms of electrical and mechanical properties. The peak-bump resistance is about 17.5 mΩ. The cross-section study revealed different types of intermetallic compounds (IMC) as a result of interfacial reactions between UBM and solder material. The effect of crystalline phases on the mechanical properties of the joint is discussed. The mean shear strength per bump after the final module reflow is about 16 cN. The results and sources of yield loss of module production are reported. The achieved yield is 95%.

Optimization of Indium Bump Morphology for Improved Flip Chip Devices

NASA Technical Reports Server (NTRS)

Jones, Todd J.; Nikzad, Shouleh; Cunningham, Thomas J.; Blazejewski, Edward; Dickie, Matthew R.; Hoenk, Michael E.; Greer, Harold F.

2011-01-01

Flip-chip hybridization, also known as bump bonding, is a packaging technique for microelectronic devices that directly connects an active element or detector to a substrate readout face-to-face, eliminating the need for wire bonding. In order to make conductive links between the two parts, a solder material is used between the bond pads on each side. Solder bumps, composed of indium metal, are typically deposited by thermal evaporation onto the active regions of the device and substrate. While indium bump technology has been a part of the electronic interconnect process field for many years and has been extensively employed in the infrared imager industry, obtaining a reliable, high-yield process for high-density patterns of bumps can be quite difficult. Under the right conditions, a moderate hydrogen plasma exposure can raise the temperature of the indium bump to the point where it can flow. This flow can result in a desirable shape where indium will efficiently wet the metal contact pad to provide good electrical contact to the underlying readout or imager circuit. However, it is extremely important to carefully control this process as the intensity of the hydrogen plasma treatment dramatically affects the indium bump morphology. To ensure the fine-tuning of this reflow process, it is necessary to have realtime feedback on the status of the bumps. With an appropriately placed viewport in a plasma chamber, one can image a small field (a square of approximately 5 millimeters on each side) of the bumps (10-20 microns in size) during the hydrogen plasma reflow process. By monitoring the shape of the bumps in real time using a video camera mounted to a telescoping 12 magnifying zoom lens and associated optical elements, an engineer can precisely determine when the reflow of the bumps has occurred, and can shut off the plasma before evaporation or de-wetting takes place.

A simple method of fabricating mask-free microfluidic devices for biological analysis

PubMed Central

Yi, Xin; Kodzius, Rimantas; Gong, Xiuqing; Xiao, Kang; Wen, Weijia

2010-01-01

We report a simple, low-cost, rapid, and mask-free method to fabricate two-dimensional (2D) and three-dimensional (3D) microfluidic chip for biological analysis researches. In this fabrication process, a laser system is used to cut through paper to form intricate patterns and differently configured channels for specific purposes. Bonded with cyanoacrylate-based resin, the prepared paper sheet is sandwiched between glass slides (hydrophilic) or polymer-based plates (hydrophobic) to obtain a multilayer structure. In order to examine the chip’s biocompatibility and applicability, protein concentration was measured while DNA capillary electrophoresis was carried out, and both of them show positive results. With the utilization of direct laser cutting and one-step gas-sacrificing techniques, the whole fabrication processes for complicated 2D and 3D microfluidic devices are shorten into several minutes which make it a good alternative of poly(dimethylsiloxane) microfluidic chips used in biological analysis researches. PMID:20890452

A 16 x 16-pixel retinal-prosthesis vision chip with in-pixel digital image processing in a frequency domain by use of a pulse-frequency-modulation photosensor

NASA Astrophysics Data System (ADS)

Kagawa, Keiichiro; Furumiya, Tetsuo; Ng, David C.; Uehara, Akihiro; Ohta, Jun; Nunoshita, Masahiro

2004-06-01

We are exploring the application of pulse-frequency-modulation (PFM) photosensor to retinal prosthesis for the blind because behavior of PFM photosensors is similar to retinal ganglion cells, from which visual data are transmitted from the retina toward the brain. We have developed retinal-prosthesis vision chips that reshape the output pulses of the PFM photosensor to biphasic current pulses suitable for electric stimulation of retinal cells. In this paper, we introduce image-processing functions to the pixel circuits. We have designed a 16x16-pixel retinal-prosthesis vision chip with several kinds of in-pixel digital image processing such as edge enhancement, edge detection, and low-pass filtering. This chip is a prototype demonstrator of the retinal prosthesis vision chip applicable to in-vitro experiments. By utilizing the feature of PFM photosensor, we propose a new scheme to implement the above image processing in a frequency domain by digital circuitry. Intensity of incident light is converted to a 1-bit data stream by a PFM photosensor, and then image processing is executed by a 1-bit image processor based on joint and annihilation of pulses. The retinal prosthesis vision chip is composed of four blocks: a pixels array block, a row-parallel stimulation current amplifiers array block, a decoder block, and a base current generators block. All blocks except PFM photosensors and stimulation current amplifiers are embodied as digital circuitry. This fact contributes to robustness against noises and fluctuation of power lines. With our vision chip, we can control photosensitivity and intensity and durations of stimulus biphasic currents, which are necessary for retinal prosthesis vision chip. The designed dynamic range is more than 100 dB. The amplitude of the stimulus current is given by a base current, which is common for all pixels, multiplied by a value in an amplitude memory of pixel. Base currents of the negative and positive pulses are common for the all pixels, and they are set in a linear manner. Otherwise, the value in the amplitude memory of the pixel is presented in an exponential manner to cover the wide range. The stimulus currents are put out column by column by scanning. The pixel size is 240um x 240um. Each pixel has a bonding pad on which stimulus electrode is to be formed. We will show the experimental results of the test chip.

DINS Final Report.

DTIC Science & Technology

1979-10-19

A optical input from a laser ggw system . The photodetector assembly shall consist of two chips: (1) photodiode chip and (2) preamplifier chip. The...181 4.1 Transienit Gamm ------ - 182 4.2 Therm~al Noise ------------------- 186 2 1 System F’unatioma Diagram -B 2 Bonding...5 2u.0 ed IG o Hl MM The desJign reurnents of the DIM~ Pbto detector System are - The system sball 1eev a 300 nhnowatt, (Min.) 63282 signal from a

Flip-chip integration of tilted VCSELs onto a silicon photonic integrated circuit.

PubMed

Lu, Huihui; Lee, Jun Su; Zhao, Yan; Scarcella, Carmelo; Cardile, Paolo; Daly, Aidan; Ortsiefer, Markus; Carroll, Lee; O'Brien, Peter

2016-07-25

In this article we describe a cost-effective approach for hybrid laser integration, in which vertical cavity surface emitting lasers (VCSELs) are passively-aligned and flip-chip bonded to a Si photonic integrated circuit (PIC), with a tilt-angle optimized for optical-insertion into standard grating-couplers. A tilt-angle of 10° is achieved by controlling the reflow of the solder ball deposition used for the electrical-contacting and mechanical-bonding of the VCSEL to the PIC. After flip-chip integration, the VCSEL-to-PIC insertion loss is -11.8 dB, indicating an excess coupling penalty of -5.9 dB, compared to Fibre-to-PIC coupling. Finite difference time domain simulations indicate that the penalty arises from the relatively poor match between the VCSEL mode and the grating-coupler.

MEMS Incandescent Light Source

NASA Technical Reports Server (NTRS)

Tuma, Margaret; King, Kevin; Kim, Lynn; Hansler, Richard; Jones, Eric; George, Thomas

2001-01-01

A MEMS-based, low-power, incandescent light source is being developed. This light source is fabricated using three bonded chips. The bottom chip consists of a reflector on Silicon, the middle chip contains a Tungsten filament bonded to silicon and the top layer is a transparent window. A 25-micrometer-thick spiral filament is fabricated in Tungsten using lithography and wet-etching. A proof-of-concept device has been fabricated and tested in a vacuum chamber. Results indicate that the filament is electrically heated to approximately 2650 K. The power required to drive the proof-of-concept spiral filament to incandescence is 1.25 W. The emitted optical power is expected to be approximately 1.0 W with the spectral peak at 1.1 microns. The micromachining techniques used to fabricate this light source can be applied to other MEMS devices.

High Efficiency Coupling of Optical Fibres with SU8 Micro-droplet Using Laser Welding Process

NASA Astrophysics Data System (ADS)

Yardi, Seema; Gupta, Ankur; Sundriyal, Poonam; Bhatt, Geeta; Kant, Rishi; Boolchandani, D.; Bhattacharya, Shantanu

2016-09-01

Apart from micro- structure fabrication, ablation, lithography etc., lasers find a lot of utility in various areas like precision joining, device fabrication, local heat delivery for surface texturing and local change of microstructure fabrication of standalone optical micro-devices (like microspheres, micro-prisms, micro-scale ring resonators, optical switches etc). There is a wide utility of such systems in chemical/ biochemical diagnostics and also communications where the standalone optical devices exist at a commercial scale but chip based devices with printed optics are necessary due to coupling issues between printed structures and external optics. This paper demonstrates a novel fabrication strategy used to join standalone optical fibres to microchip based printed optics using a simple SU8 drop. The fabrication process is deployed for fiber to fiber optical coupling and coupling between fiber and printed SU-8 waveguides. A CO2 laser is used to locally heat the coupling made up of SU8 material. Optimization of various dimensional parameters using design of experiments (DOE) on the bonded assembly has been performed as a function of laser power, speed, cycle control, spot size so on so forth. Exclusive optical [RF] modelling has been performed to estimate the transmissibility of the optical fibers bonded to each other on a surface with SU8. Our studies indicate the formation of a Whispering gallery mode (WGM) across the micro-droplet leading to high transmissibility of the signal. Through this work we have thus been able to develop a method of fabrication for optical coupling of standalone fibers or coupling of on-chip optics with off-chip illumination/detection.

Multilayered microelectronic device package with an integral window

DOEpatents

Peterson, Kenneth A.; Watson, Robert D.

2003-01-01

An apparatus for packaging of microelectronic devices is disclosed, wherein the package includes an integral window. The microelectronic device can be a semiconductor chip, a CCD chip, a CMOS chip, a VCSEL chip, a laser diode, a MEMS device, or a IMEMS device. The package can comprise, for example, a cofired ceramic frame or body. The package has an internal stepped structure made of a plurality of plates, with apertures, which are patterned with metallized conductive circuit traces. The microelectronic device can be flip-chip bonded on the plate to these traces, and oriented so that the light-sensitive side is optically accessible through the window. A cover lid can be attached to the opposite side of the package. The result is a compact, low-profile package, having an integral window that can be hermetically-sealed. The package body can be formed by low-temperature cofired ceramic (LTCC) or high-temperature cofired ceramic (HTCC) multilayer processes with the window being simultaneously joined (e.g. cofired) to the package body during LTCC or HTCC processing. Multiple chips can be located within a single package, according to some embodiments. The cover lid can include a window. The apparatus is particularly suited for packaging of MEMS devices, since the number of handling steps is greatly reduced, thereby reducing the potential for contamination. The integral window can further include a lens for optically transforming light passing through the window. The package can include an array of binary optic lenslets made integral with the window. The package can include an electrically-switched optical modulator, such as a lithium niobate window attached to the package, for providing a very fast electrically-operated shutter.

Flip-chip assembly and reliability using gold/tin solder bumps

NASA Astrophysics Data System (ADS)

Oppermann, Hermann; Hutter, Matthias; Klein, Matthias; Reichl, Herbert

2004-09-01

Au/Sn solder bumps are commonly used for flip chip assembly of optoelectronic and RF devices. They allow a fluxless assembly which is required to avoid contamination at optical interfaces. Flip chip assembly experiments were carried out using as plated Au/Sn bumps without prior bump reflow. An RF and reliability test vehicles comprise a GaAs chip which was flip chip soldered on a silicon substrate. Temperature cycling tests with and without underfiller were performed and the results are presented. The different failure modes for underfilled and non-underfilled samples were discussed and compared. Additional reliability tests were performed with flip chip bonding by gold thermocompression for comparison. The test results and the failure modes are discussed in detail.

On-demand acoustic droplet splitting and steering in a disposable microfluidic chip.

PubMed

Park, Jinsoo; Jung, Jin Ho; Park, Kwangseok; Destgeer, Ghulam; Ahmed, Husnain; Ahmad, Raheel; Sung, Hyung Jin

2018-01-30

On-chip droplet splitting is one of the fundamental droplet-based microfluidic unit operations to control droplet volume after production and increase operational capability, flexibility, and throughput. Various droplet splitting methods have been proposed, and among them the acoustic droplet splitting method is promising because of its label-free operation without any physical or thermal damage to droplets. Previous acoustic droplet splitting methods faced several limitations: first, they employed a cross-type acoustofluidic device that precluded multichannel droplet splitting; second, they required irreversible bonding between a piezoelectric substrate and a microfluidic chip, such that the fluidic chip was not replaceable. Here, we present a parallel-type acoustofluidic device with a disposable microfluidic chip to address the limitations of previous acoustic droplet splitting devices. In the proposed device, an acoustic field is applied in the direction opposite to the flow direction to achieve multichannel droplet splitting and steering. A disposable polydimethylsiloxane microfluidic chip is employed in the developed device, thereby removing the need for permanent bonding and improving the flexibility of the droplet microfluidic device. We experimentally demonstrated on-demand acoustic droplet bi-splitting and steering with precise control over the droplet splitting ratio, and we investigated the underlying physical mechanisms of droplet splitting and steering based on Laplace pressure and ray acoustics analyses, respectively. We also demonstrated droplet tri-splitting to prove the feasibility of multichannel droplet splitting. The proposed on-demand acoustic droplet splitting device enables on-chip droplet volume control in various droplet-based microfluidic applications.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Fahim, Farah; Deptuch, Grzegorz; Shenai, Alpana

The Vertically Integrated Photon Imaging Chip - Large, (VIPIC-L), is a large area, small pixel (65μm), 3D integrated, photon counting ASIC with zero-suppressed or full frame dead-time-less data readout. It features data throughput of 14.4 Gbps per chip with a full frame readout speed of 56kframes/s in the imaging mode. VIPIC-L contain 192 x 192 pixel array and the total size of the chip is 1.248cm x 1.248cm with only a 5μm periphery. It contains about 120M transistors. A 1.3M pixel camera module will be developed by arranging a 6 x 6 array of 3D VIPIC-L’s bonded to a largemore » area silicon sensor on the analog side and to a readout board on the digital side. The readout board hosts a bank of FPGA’s, one per VIPIC-L to allow processing of up to 0.7 Tbps of raw data produced by the camera.« less

Stacked Fresnel Zone Plates for High Energy X-rays

NASA Astrophysics Data System (ADS)

Snigireva, Irina; Snigirev, Anatoly; Vaughan, Gavin; Di Michiel, Marco; Kohn, Viktor; Yunkin, Vyacheslav; Grigoriev, Maxim

2007-01-01

A stacking technique was developed in order to increase focusing efficiency of Fresnel zone plates (FZP) at high energies. Two identical Si chips each of which containing 9 FZPs were used for stacking. Alignment of the chips was achieved by on-line observation of the moiré pattern. The formation of moiré patterns was studied theoretically and experimentally at different experimental conditions. To provide the desired stability Si-chips were bonded together with slow solidification speed epoxy glue. A technique of angular alignment in order to compensate a linear displacement in the process of gluing was proposed. Two sets of stacked FZPs were experimentally tested to focus 15 and 50 keV x rays. The gain in the efficiency by factor 2.5 was demonstrated at 15 keV. The focal spot of 1.8 μm vertically and 14 μm horizontally with 35% efficiency was measured at 50 keV. Forecast for the stacking of nanofocusing FZPs was discussed.

Hard X-ray focusing by stacked Fresnel zone plates

NASA Astrophysics Data System (ADS)

Snigireva, Irina; Snigirev, Anatoly; Kohn, Viktor; Yunkin, Vyacheslav; Grigoriev, Maxim; Kuznetsov, Serguei; Vaughan, Gavin; Di Michiel, Marco

2007-09-01

Stacking technique was developed in order to increase focusing efficiency of Fresnel zone plates at high energies. Two identical Si chips each of which containing Fresnel zone plates were used for stacking. Alignment of the chips was achieved by on-line observation of the moiré pattern from the two zone plates. The formation of moiré patterns was studied theoretically and experimentally at different experimental conditions. To provide the desired stability Si-chips with zone plates were bonded together with slow solidification speed epoxy glue. Technique of angular alignment in order to compensate a linear displacement in the process of gluing was proposed. Two sets of stacked FZPs were produced and experimentally tested to focus 15 and 50 keV X-rays. Gain in the efficiency by factor 2.5 was demonstrated at 15 keV. Focal spot of 1.8 μm vertically and 14 μm horizontally with 35% efficiency was measured at 50 keV. Forecast for the stacking of nanofocusing Fresnel zone plates was discussed.

Novel First-Level Interconnect Techniques for Flip Chip on MEMS Devices

PubMed Central

Sutanto, Jemmy; Anand, Sindhu; Patel, Chetan; Muthuswamy, Jit

2013-01-01

Flip-chip packaging is desirable for microelectro-mechanical systems (MEMS) devices because it reduces the overall package size and allows scaling up the number of MEMS chips through 3-D stacks. In this report, we demonstrate three novel techniques to create first-level interconnect (FLI) on MEMS: 1) Dip and attach technology for Ag epoxy; 2) Dispense technology for solder paste; 3) Dispense, pull, and attach technology (DPAT) for solder paste. The above techniques required no additional microfabrication steps, produced no visible surface contamination on the MEMS active structures, and generated high-aspect-ratio interconnects. The developed FLIs were successfully tested on MEMS moveable microelectrodes microfabricated by SUMMiTVTM process producing no apparent detrimental effect due to outgassing. The bumping processes were successfully applied on Al-deposited bond pads of 100 μm × 100 μm with an average bump height of 101.3 μm for Ag and 184.8 μm for solder (63Sn, 37Pb). DPAT for solder paste produced bumps with the aspect ratio of 1.8 or more. The average shear strengths of Ag and solder bumps were 78 MPa and 689 kPa, respectively. The electrical test on Ag bumps at 794 A/cm2 demonstrated reliable electrical interconnects with negligible resistance. These scalable FLI technologies are potentially useful for MEMS flip-chip packaging and 3-D stacking. PMID:24504168

Atom Chips on Direct Bonded Copper Substrates (Postprint)

DTIC Science & Technology

2012-01-19

joining of a thin sheet of pure copper to a ceramic substrate14 and is commonly used in power electronics due to its high current handling and heat...Squires et al. Rev. Sci. Instrum. 82, 023101 (2011) FIG. 1. A scanning electron micrograph of the top view of test chip A. the photolithographically...the etching pro- cesses and masking methods were quantified using a scanning electron microscope. Two test chips (A and B) are presented below and are

Design considerations for FET-gated power transistors

NASA Technical Reports Server (NTRS)

Chen, D. Y.; Chin, S. A.

1983-01-01

An FET-bipolar combinational power transistor configuration (tested up to 300 V, 20 A at 100 kHz) is described. The critical parameters for integrating the chips in hybrid form are examined, and an effort to optimize the overall characteristics of the configuration is discussed. Chip considerations are examined with respect to the voltage and current rating of individual chips, the FET surge capability, the choice of triple diffused transistor or epitaxial transistor for the bipolar element, the current tailing effect, and the implementation of the bipolar transistor and an FET as single chip or separate chips. Package considerations are discussed with respect to package material and geometry, surge current capability of bipolar base terminal bonding, and power losses distribution.

Development and applications of 3-dimensional integration nanotechnologies.

PubMed

Kim, Areum; Choi, Eunmi; Son, Hyungbin; Pyo, Sung Gyu

2014-02-01

Unlike conventional two-dimensional (2D) planar structures, signal or power is supplied through through-silicon via (TSV) in three-dimensional (3D) integration technology to replace wires for binding the chip/wafer. TSVs have becomes an essential technology, as they satisfy Moore's law. This 3D integration technology enables system and sensor functions at a nanoscale via the implementation of a highly integrated nano-semiconductor as well as the fabrication of a single chip with multiple functions. Thus, this technology is considered to be a new area of development for the systemization of the nano-bio area. In this review paper, the basic technology required for such 3D integration is described and methods to measure the bonding strength in order to measure the void occurring during bonding are introduced. Currently, CMOS image sensors and memory chips associated with nanotechnology are being realized on the basis of 3D integration technology. In this paper, we intend to describe the applications of high-performance nano-biosensor technology currently under development and the direction of development of a high performance lab-on-a-chip (LOC).

Laser vibrometry characterisation of a microfluidic lab-on-a-chip device: a preliminary investigation

NASA Astrophysics Data System (ADS)

Fury, C.; Gélat, P. N.; Jones, P. H.; Memoli, G.

2014-04-01

Since their original inception as ultrasound contrast agents, potential applications of microbubbles have evolved to encompass molecular imaging and targeted drug delivery. As these areas develop, so does the need to understand the mechanisms behind the interaction of microbubbles both with biological tissue and with other microbubbles. There is therefore a metrological requirement to develop a controlled environment in which to study these processes. Presented here is the design and characterisation of such a system, which consists of a microfluidic chip, specifically developed for manipulating microbubbles using both optical and acoustic trapping. A laser vibrometer is used to observe the coupling of acoustic energy into the chip from a piezoelectric transducer bonded to the surface. Measurement of the velocity of surface waves on the chip is investigated as a potential method for inferring the nature of the acoustic fields excited within the liquid medium of the device. Comparison of measured surface wavelengths with wave types suggests the observation of anti-symmetric Lamb or Love-Kirchhoff waves. Further visual confirmation of the acoustic fields through bubble aggregation highlights differences between the model and experimental results in predicting the position of acoustic pressure nodes in relation to excitation frequency.

Development of Equivalent Material Properties of Microbump for Simulating Chip Stacking Packaging

PubMed Central

Lee, Chang-Chun; Tzeng, Tzai-Liang; Huang, Pei-Chen

2015-01-01

A three-dimensional integrated circuit (3D-IC) structure with a significant scale mismatch causes difficulty in analytic model construction. This paper proposes a simulation technique to introduce an equivalent material composed of microbumps and their surrounding wafer level underfill (WLUF). The mechanical properties of this equivalent material, including Young’s modulus (E), Poisson’s ratio, shear modulus, and coefficient of thermal expansion (CTE), are directly obtained by applying either a tensile load or a constant displacement, and by increasing the temperature during simulations, respectively. Analytic results indicate that at least eight microbumps at the outermost region of the chip stacking structure need to be considered as an accurate stress/strain contour in the concerned region. In addition, a factorial experimental design with analysis of variance is proposed to optimize chip stacking structure reliability with four factors: chip thickness, substrate thickness, CTE, and E-value. Analytic results show that the most significant factor is CTE of WLUF. This factor affects microbump reliability and structural warpage under a temperature cycling load and high-temperature bonding process. WLUF with low CTE and high E-value are recommended to enhance the assembly reliability of the 3D-IC architecture. PMID:28793495

Flexible Chip Scale Package and Interconnect for Implantable MEMS Movable Microelectrodes for the Brain

PubMed Central

Jackson, Nathan; Muthuswamy, Jit

2009-01-01

We report here a novel approach called MEMS microflex interconnect (MMFI) technology for packaging a new generation of Bio-MEMS devices that involve movable microelectrodes implanted in brain tissue. MMFI addresses the need for (i) operating space for movable parts and (ii) flexible interconnects for mechanical isolation. We fabricated a thin polyimide substrate with embedded bond-pads, vias, and conducting traces for the interconnect with a backside dry etch, so that the flexible substrate can act as a thin-film cap for the MEMS package. A double gold stud bump rivet bonding mechanism was used to form electrical connections to the chip and also to provide a spacing of approximately 15–20 µm for the movable parts. The MMFI approach achieved a chip scale package (CSP) that is lightweight, biocompatible, having flexible interconnects, without an underfill. Reliability tests demonstrated minimal increases of 0.35 mΩ, 0.23 mΩ and 0.15 mΩ in mean contact resistances under high humidity, thermal cycling, and thermal shock conditions respectively. High temperature tests resulted in an increase in resistance of > 90 mΩ when aluminum bond pads were used, but an increase of ~ 4.2 mΩ with gold bond pads. The mean-time-to-failure (MTTF) was estimated to be at least one year under physiological conditions. We conclude that MMFI technology is a feasible and reliable approach for packaging and interconnecting Bio-MEMS devices. PMID:20160981

Method of fabricating a microelectronic device package with an integral window

DOEpatents

Peterson, Kenneth A.; Watson, Robert D.

2003-01-01

A method of fabricating a microelectronic device package with an integral window for providing optical access through an aperture in the package. The package is made of a multilayered insulating material, e.g., a low-temperature cofired ceramic (LTCC) or high-temperature cofired ceramic (HTCC). The window is inserted in-between personalized layers of ceramic green tape during stackup and registration. Then, during baking and firing, the integral window is simultaneously bonded to the sintered ceramic layers of the densified package. Next, the microelectronic device is flip-chip bonded to cofired thick-film metallized traces on the package, where the light-sensitive side is optically accessible through the window. Finally, a cover lid is attached to the opposite side of the package. The result is a compact, low-profile package, flip-chip bonded, hermetically-sealed package having an integral window.

Silicon Hard-Stop Mesas for 3D Integration of Superconducting Qubits

NASA Astrophysics Data System (ADS)

Kim, David; Rosenberg, Danna; Osadchy, Brenda; Calusine, Greg; Das, Rabindra; Melville, Alexander; Yoder, Jonilyn; Yost, Donna-Ruth; Racz, Livia; Oliver, William

As quantum computing with superconducting qubits advances past the few-qubit stage, implementing 3D packaging/integration to route readout/control lines will become increasingly important. One approach is to bond chips that perform different functions using indium bump bonds. Because indium is malleable, however, achieving the desired spacing and tilt between two chips can be challenging. We present an approach based on etching several microns into the silicon substrate to produce hard stop silicon posts. Since this process involves etching into a pristine substrate, it is essential to evaluate its impact on qubit performance. We report the etched surface's effect on the resonator quality factor and qubit coherence time, as well as the improvement in planarity and tilt. This research was funded in part by the Office of the Director of National Intelligence (ODNI), Intelligence Advanced Research Projects Activity (IARPA) and by the Assistant Secretary of Defense for Research & Engineering under Air Force Contract No. FA8721-05-C-0002. The views and conclusions contained herein are those of the authors and should not be interpreted as necessarily representing the official policies or endorsements, either expressed or implied, of ODNI, IARPA, or the US Government.

Particleboard made from remediated CCA-treated wood : evaluation of panel properties

Treesearch

Carol A. Clausen; S. Nami Kartal; James Muehl

2001-01-01

CCA-treated southern yellow pine (SYP) chips were remediated utilizing acid extraction alone, and using acid extraction followed by bioleaching with the metal-tolerant bacterium Bacillus licheniformis CC01. bCleanedc chips were used to make particleboard (PB) with 10 percent urea-formaldehyde (UF) resin, and the PB samples were evaluated for internal bond (IB), modulus...

Rapid prototyping of versatile atom chips for atom interferometry applications.

NASA Astrophysics Data System (ADS)

Kasch, Brian; Squires, Matthew; Olson, Spencer; Kroese, Bethany; Imhof, Eric; Kohn, Rudolph; Stuhl, Benjamin; Schramm, Stacy; Stickney, James

2016-05-01

We present recent advances in the manipulation of ultracold atoms with ex-vacuo atom chips (i.e. atom chips that are not inside to the UHV chamber). Details will be presented of an experimental system that allows direct bonded copper (DBC) atom chips to be removed and replaced in minutes, requiring minimal re-optimization of parameters. This system has been used to create Bose-Einstein condensates, as well as magnetic waveguides with precisely tunable axial parameters, allowing double wells, pure harmonic confinement, and modified harmonic traps. We investigate the effects of higher order magnetic field contributions to the waveguide, and the implications for confined atom interferometry.

Design, fabrication and actuation of a MEMS-based image stabilizer for photographic cell phone applications

NASA Astrophysics Data System (ADS)

Chiou, Jin-Chern; Hung, Chen-Chun; Lin, Chun-Ying

2010-07-01

This work presents a MEMS-based image stabilizer applied for anti-shaking function in photographic cell phones. The proposed stabilizer is designed as a two-axis decoupling XY stage 1.4 × 1.4 × 0.1 mm3 in size, and adequately strong to suspend an image sensor for anti-shaking photographic function. This stabilizer is fabricated by complex fabrication processes, including inductively coupled plasma (ICP) processes and flip-chip bonding technique. Based on the special designs of a hollow handle layer and a corresponding wire-bonding assisted holder, electrical signals of the suspended image sensor can be successfully sent out with 32 signal springs without incurring damage during wire-bonding packaging. The longest calculated traveling distance of the stabilizer is 25 µm which is sufficient to resolve the anti-shaking problem in a three-megapixel image sensor. Accordingly, the applied voltage for the 25 µm moving distance is 38 V. Moreover, the resonant frequency of the actuating device with the image sensor is 1.123 kHz.

Thin hybrid pixel assembly with backside compensation layer on ROIC

NASA Astrophysics Data System (ADS)

Bates, R.; Buttar, C.; McMullen, T.; Cunningham, L.; Ashby, J.; Doherty, F.; Gray, C.; Pares, G.; Vignoud, L.; Kholti, B.; Vahanen, S.

2017-01-01

The entire ATLAS inner tracking system will be replaced for operation at the HL-LHC . This will include a significantly larger pixel detector of approximately 15 m2. For this project, it is critical to reduce the mass of the hybrid pixel modules and this requires thinning both the sensor and readout chips to about 150 micrometres each. The thinning of the silicon chips leads to low bump yield for SnAg bumps due to bad co-planarity of the two chips at the solder reflow stage creating dead zones within the pixel array. In the case of the ATLAS FEI4 pixel readout chip thinned to 100 micrometres, the chip is concave, with the front side in compression, with a bow of +100 micrometres at room temperature which varies to a bow of -175 micrometres at the SnAg solder reflow temperature, caused by the CTE mismatch between the materials in the CMOS stack and the silicon substrate. A new wafer level process to address the issue of low bump yield be controlling the chip bow has been developed. A back-side dielectric and metal stack of SiN and Al:Si has been deposited on the readout chip wafer to dynamically compensate the stress of the front side stack. In keeping with a 3D process the materials used are compatible with Through Silicon Via (TSV) technology with a TSV last approach which is under development for this chip. It is demonstrated that the amplitude of the correction can be manipulated by the deposition conditions and thickness of the SiN/Al:Si stack. The bow magnitude over the temperature range for the best sample to date is reduced by almost a factor of 4 and the sign of the bow (shape of the die) remains constant. Further development of the backside deposition conditions is on-going with the target of close to zero bow at the solder reflow temperature and a minimal bow magnitude throughout the temperature range. Assemblies produced from FEI4 readout wafers thinned to 100 micrometres with the backside compensation layer have been made for the first time and demonstrate bond yields close to 100%.

Vertically Integrated MEMS SOI Composite Porous Silicon-Crystalline Silicon Cantilever-Array Sensors: Concept for Continuous Sensing of Explosives and Warfare Agents

NASA Astrophysics Data System (ADS)

Stolyarova, Sara; Shemesh, Ariel; Aharon, Oren; Cohen, Omer; Gal, Lior; Eichen, Yoav; Nemirovsky, Yael

This study focuses on arrays of cantilevers made of crystalline silicon (c-Si), using SOI wafers as the starting material and using bulk micromachining. The arrays are subsequently transformed into composite porous silicon-crystalline silicon cantilevers, using a unique vapor phase process tailored for providing a thin surface layer of porous silicon on one side only. This results in asymmetric cantilever arrays, with one side providing nano-structured porous large surface, which can be further coated with polymers, thus providing additional sensing capabilities and enhanced sensing. The c-Si cantilevers are vertically integrated with a bottom silicon die with electrodes allowing electrostatic actuation. Flip Chip bonding is used for the vertical integration. The readout is provided by a sensitive Capacitance to Digital Converter. The fabrication, processing and characterization results are reported. The reported study is aimed towards achieving miniature cantilever chips with integrated readout for sensing explosives and chemical warfare agents in the field.

Flexible Chip Scale Package and Interconnect for Implantable MEMS Movable Microelectrodes for the Brain.

PubMed

Jackson, Nathan; Muthuswamy, Jit

2009-04-01

We report here a novel approach called MEMS microflex interconnect (MMFI) technology for packaging a new generation of Bio-MEMS devices that involve movable microelectrodes implanted in brain tissue. MMFI addresses the need for (i) operating space for movable parts and (ii) flexible interconnects for mechanical isolation. We fabricated a thin polyimide substrate with embedded bond-pads, vias, and conducting traces for the interconnect with a backside dry etch, so that the flexible substrate can act as a thin-film cap for the MEMS package. A double gold stud bump rivet bonding mechanism was used to form electrical connections to the chip and also to provide a spacing of approximately 15-20 µm for the movable parts. The MMFI approach achieved a chip scale package (CSP) that is lightweight, biocompatible, having flexible interconnects, without an underfill. Reliability tests demonstrated minimal increases of 0.35 mΩ, 0.23 mΩ and 0.15 mΩ in mean contact resistances under high humidity, thermal cycling, and thermal shock conditions respectively. High temperature tests resulted in an increase in resistance of > 90 mΩ when aluminum bond pads were used, but an increase of ~ 4.2 mΩ with gold bond pads. The mean-time-to-failure (MTTF) was estimated to be at least one year under physiological conditions. We conclude that MMFI technology is a feasible and reliable approach for packaging and interconnecting Bio-MEMS devices.

Detection of acrylamide in potato chips using a fluorescent sensing method based on acrylamide polymerization-induced distance increase between quantum dots.

PubMed

Hu, Qinqin; Xu, Xiahong; Li, Zhanming; Zhang, Ying; Wang, Jianping; Fu, Yingchun; Li, Yanbin

2014-04-15

Acrylamide is a neurotoxin and potential carcinogen, but is found in various thermally processed foods such as potato chips, biscuits, and coffee. Simple and sensitive methods for on-line detection of acrylamide are needed to ensure food safety. In this paper, a novel fluorescent sensing method based on acrylamide polymerization-induced distance increase between quantum dots (QDs) was proposed for detecting acrylamide in potato chips. The functional QDs were prepared by their binding with N-acryloxysuccinimide (NAS), which was characterized by Fourier transform infrared (FR-IR) spectra. The carbon-carbon double bonds of NAS modified QDs polymerized with assistance of photo initiator under UV irradiation, leading to QDs getting closer along with fluorescence intensity decreasing. Acrylamide in the sample participated in the polymerization and induced an increase of fluorescence intensity. This method possessed a linear range from 3.5×10(-5) to 3.5 g L(-1) (r(2)=0.94) and a limit of detection of 3.5×10(-5) g L(-1). Although the sensitivity and specificity cannot be compared with standard LC-MS/MS analysis, this new method requires much less time and cost, which is promising for on-line rapid detection of acrylamide in food processing. © 2013 Published by Elsevier B.V.

Ten-channel InP-based large-scale photonic integrated transmitter fabricated by SAG technology

NASA Astrophysics Data System (ADS)

Zhang, Can; Zhu, Hongliang; Liang, Song; Cui, Xiao; Wang, Huitao; Zhao, Lingjuan; Wang, Wei

2014-12-01

A 10-channel InP-based large-scale photonic integrated transmitter was fabricated by selective area growth (SAG) technology combined with butt-joint regrowth (BJR) technology. The SAG technology was utilized to fabricate the electroabsorption modulated distributed feedback (DFB) laser (EML) arrays at the same time. The design of coplanar electrodes for electroabsorption modulator (EAM) was used for the flip-chip bonding package. The lasing wavelength of DFB laser could be tuned by the integrated micro-heater to match the ITU grids, which only needs one electrode pad. The average output power of each channel is 250 μW with an injection current of 200 mA. The static extinction ratios of the EAMs for 10 channels tested are ranged from 15 to 27 dB with a reverse bias of 6 V. The frequencies of 3 dB bandwidth of the chip for each channel are around 14 GHz. The novel design and simple fabrication process show its enormous potential in reducing the cost of large-scale photonic integrated circuit (LS-PIC) transmitter with high chip yields.

‘Chip-olate’ and dry-film resists for efficient fabrication, singulation and sealing of microfluidic chips

NASA Astrophysics Data System (ADS)

Temiz, Yuksel; Delamarche, Emmanuel

2014-09-01

This paper describes a technique for high-throughput fabrication and efficient singulation of chips having closed microfluidic structures and takes advantage of dry-film resists (DFRs) for efficient sealing of capillary systems. The technique is illustrated using 4-inch Si/SiO2 wafers. Wafers carrying open microfluidic structures are partially diced to about half of their thickness. Treatments such as surface cleaning are done at wafer-level, then the structures are sealed using low-temperature (45 °C) lamination of a DFR that is pre-patterned using a craft cutter, and ready-to-use chips are finally separated manually like a chocolate bar by applying a small force (≤ 4 N). We further show that some DFRs have low auto-fluorescence at wavelengths typically used for common fluorescent dyes and that mechanical properties of some DFRs allow for the lamination of 200 μm wide microfluidic structures with negligible sagging (~1 μm). The hydrophilicity (advancing contact angle of ~60°) of the DFR supports autonomous capillary-driven flow without the need for additional surface treatment of the microfluidic chips. Flow rates from 1 to 5 µL min-1 are generated using different geometries of channels and capillary pumps. In addition, the ‘chip-olate’ technique is compatible with the patterning of capture antibodies on DFR for use in immunoassays. We believe this technique to be applicable to the fabrication of a wide range of microfluidic and lab-on-a-chip devices and to offer a viable alternative to many labor-intensive processes that are currently based on wafer bonding techniques or on the molding of poly(dimethylsiloxane) (PDMS) layers.

Fabrication of a Silicon Backshort Assembly for Waveguide-Coupled Superconducting Detectors

NASA Technical Reports Server (NTRS)

Crowe, Erik J.; Bennett, Charles L.; Chuss, David T.; Denis, Kevin L.; Eimer, Joseph; Lourie, Nathan; Marriage, Tobias; Moseley, Samuel H.; Rostem, Karwan; Stevenson, Thomas R.;

Dose-dependent X-ray measurements using a 64×64 hybrid GaAs pixel detector with photon counting

NASA Astrophysics Data System (ADS)

Schwarz, C.; Campbell, M.; Goeppert, R.; Ludwig, J.; Mikulec, B.; Rogalla, M.; Runge, K.; Soeldner-Rembold, A.; Smith, K. M.; Snoeys, W.; Watt, J.

2001-03-01

New developments in medical imaging head towards semiconductor detectors flip-chip bonded to CMOS readout chips. In this work, detectors fabricated on SI-GaAs bulk material were bonded to Photon Counting Chips. This PCC consists of a matrix of 64×64 identical square pixels (170 μm×170 μm) with a 15-bit counter in each cell. We investigated the imaging properties of these detector systems under exposure of a dental X-ray tube. First, a dose calibration of the X-ray tube was performed. Fixed pattern noise in flood exposure images was determined for a fixed dose and an image correction method, which uses a gain map, was applied. For characterising the imaging properties, the signal-to-noise ratio (SNR) was calculated as function of exposure dose. Finally, the dynamic range of the system was estimated. Developed in the framework of the MEDIPIX collaboration: CERN, Universities of Freiburg, Glasgow, Naples and Pisa.

Integrated optical transceiver with electronically controlled optical beamsteering

DOE Office of Scientific and Technical Information (OSTI.GOV)

Davids, Paul; DeRose, Christopher; Tauke-Pedretti, Anna

A beam-steering optical transceiver is provided. The transceiver includes one or more modules, each comprising an antenna chip and a control chip bonded to the antenna chip. Each antenna chip has a feeder waveguide, a plurality of row waveguides that tap off from the feeder waveguide, and a plurality of metallic nanoantenna elements arranged in a two-dimensional array of rows and columns such that each row overlies one of the row waveguides. Each antenna chip also includes a plurality of independently addressable thermo-optical phase shifters, each configured to produce a thermo-optical phase shift in a respective row. Each antenna chipmore » also has, for each row, a row-wise heating circuit configured to produce a respective thermo-optic phase shift at each nanoantenna element along its row. The control chip includes controllable current sources for the independently addressable thermo-optical phase shifters and the row-wise heating circuits.« less

Fabrication of polydimethylsiloxane (PDMS) nanofluidic chips with controllable channel size and spacing.

PubMed

Peng, Ran; Li, Dongqing

2016-10-07

The ability to create reproducible and inexpensive nanofluidic chips is essential to the fundamental research and applications of nanofluidics. This paper presents a novel and cost-effective method for fabricating a single nanochannel or multiple nanochannels in PDMS chips with controllable channel size and spacing. Single nanocracks or nanocrack arrays, positioned by artificial defects, are first generated on a polystyrene surface with controllable size and spacing by a solvent-induced method. Two sets of optimal working parameters are developed to replicate the nanocracks onto the polymer layers to form the nanochannel molds. The nanochannel molds are used to make the bi-layer PDMS microchannel-nanochannel chips by simple soft lithography. An alignment system is developed for bonding the nanofluidic chips under an optical microscope. Using this method, high quality PDMS nanofluidic chips with a single nanochannel or multiple nanochannels of sub-100 nm width and height and centimeter length can be obtained with high repeatability.

Separation of superparamagnetic particles through ratcheted Brownian motion and periodically switching magnetic fields.

PubMed

Liu, Fan; Jiang, Li; Tan, Huei Ming; Yadav, Ashutosh; Biswas, Preetika; van der Maarel, Johan R C; Nijhuis, Christian A; van Kan, Jeroen A

2016-11-01

Brownian ratchet based particle separation systems for application in lab on chip devices have drawn interest and are subject to ongoing theoretical and experimental investigations. We demonstrate a compact microfluidic particle separation chip, which implements an extended on-off Brownian ratchet scheme that actively separates and sorts particles using periodically switching magnetic fields, asymmetric sawtooth channel sidewalls, and Brownian motion. The microfluidic chip was made with Polydimethylsiloxane (PDMS) soft lithography of SU-8 molds, which in turn was fabricated using Proton Beam Writing. After bonding of the PDMS chip to a glass substrate through surface activation by oxygen plasma treatment, embedded electromagnets were cofabricated by the injection of InSn metal into electrode channels. This fabrication process enables rapid production of high resolution and high aspect ratio features, which results in parallel electrodes accurately aligned with respect to the separation channel. The PDMS devices were tested with mixtures of 1.51  μ m, 2.47  μ m, and 2.60  μ m superparamagnetic particles suspended in water. Experimental results show that the current device design has potential for separating particles with a size difference around 130 nm. Based on the promising results, we will be working towards extending this design for the separation of cells or biomolecules.

Separation of superparamagnetic particles through ratcheted Brownian motion and periodically switching magnetic fields

PubMed Central

Liu, Fan; Jiang, Li; Tan, Huei Ming; Yadav, Ashutosh; Biswas, Preetika; van der Maarel, Johan R. C.; Nijhuis, Christian A.; van Kan, Jeroen A.

2016-01-01

Brownian ratchet based particle separation systems for application in lab on chip devices have drawn interest and are subject to ongoing theoretical and experimental investigations. We demonstrate a compact microfluidic particle separation chip, which implements an extended on-off Brownian ratchet scheme that actively separates and sorts particles using periodically switching magnetic fields, asymmetric sawtooth channel sidewalls, and Brownian motion. The microfluidic chip was made with Polydimethylsiloxane (PDMS) soft lithography of SU-8 molds, which in turn was fabricated using Proton Beam Writing. After bonding of the PDMS chip to a glass substrate through surface activation by oxygen plasma treatment, embedded electromagnets were cofabricated by the injection of InSn metal into electrode channels. This fabrication process enables rapid production of high resolution and high aspect ratio features, which results in parallel electrodes accurately aligned with respect to the separation channel. The PDMS devices were tested with mixtures of 1.51 μm, 2.47 μm, and 2.60 μm superparamagnetic particles suspended in water. Experimental results show that the current device design has potential for separating particles with a size difference around 130 nm. Based on the promising results, we will be working towards extending this design for the separation of cells or biomolecules. PMID:27917252

The Image Understanding Architecture Project

DTIC Science & Technology

1988-04-01

The error resulted in the frame being reduced in size and incorrectly bonded . The problem has been corrected and3 the design has been re-submitted...Promotional literature, Beaverton, OR, 1985. Nii, 1986] Nil, H.P., The Blackboard Model of Problem Solving and the Evolution of Blackboard...microns. This resulted in a reduction in pad sizes to two thirds of the minimum required for safe bonding . All chips had many wire bonds on the die

Prototyping of Silicon Strip Detectors for the Inner Tracker of the ALICE Experiment

NASA Astrophysics Data System (ADS)

Sokolov, Oleksiy

2006-04-01

The ALICE experiment at CERN will study heavy ion collisions at a center-of-mass energy 5.5˜TeV per nucleon. Particle tracking around the interaction region at radii r<45 cm is done by the Inner Tracking System (ITS), consisting of six cylindrical layers of silicon detectors. The outer two layers of the ITS use double-sided silicon strip detectors. This thesis focuses on testing of these detectors and performance studies of the detector module prototypes at the beam test. Silicon strip detector layers will require about 20 thousand HAL25 front-end readout chips and about 3.5 thousand hybrids each containing 6 HAL25 chips. During the assembly procedure, chips are bonded on a patterned TAB aluminium microcables which connect to all the chip input and output pads, and then the chips are assembled on the hybrids. Bonding failures at the chip or hybrid level may either render the component non-functional or deteriorate its the performance such that it can not be used for the module production. After each bonding operation, the component testing is done to reject the non-functional or poorly performing chips and hybrids. The LabView-controlled test station for this operation has been built at Utrecht University and was successfully used for mass production acceptance tests of chips and hybrids at three production labs. The functionality of the chip registers, bonding quality and analogue functionality of the chips and hybrids are addressed in the test. The test routines were optimized to minimize the testing time to make sure that testing is not a bottleneck of the mass production. For testing of complete modules the laser scanning station with 1060 nm diode laser has been assembled at Utrecht University. The testing method relies of the fact that a response of the detector module to a short collimated laser beam pulse resembles a response to a minimum ionizing particle. A small beam spot size (˜7 μm ) allows to deposit the charge in a narrow region and measure the response of individual detector channels. First several module prototypes have been studied with this setup, the strip gain and charge sharing function have been measured, the later is compared with the model predictions. It was also shown that for a laser beam of a high monochromaticity, interference in the sensor bulk significantly modulates the deposited charge and introduces a systematic error of the gain measurement. Signatures of disconnected strips and pinholes defects have been observed, the response of the disconnected strips to the laser beam has been correlated with the noise measurements. Beam test of four prototype modules have been carried out at PS accelerator at CERN using 7 GeV/c pions. It was demonstrated that the modules provide an excellent signal-to-noise ratio in the range 40-75. The estimated spatial resolution for the normally incident tracks is about 18 μm using the center-of-gravity cluster reconstruction method. A non-iterative method for spatial resolution determination was developed, it was shown that in order to determine the resolution of each individual detector in the telescope, the telescope should consist of at least 5 detectors. The detectors showed high detection efficiency, in the order 99%. It was shown that the particle loss occurs mostly in the defected regions near the noisy strips or strips with a very low gain. The efficiency of the sensor area with nominal characteristics is consistent with 100%.

New results on diamond pixel sensors using ATLAS frontend electronics

NASA Astrophysics Data System (ADS)

Keil, M.; Adam, W.; Berdermann, E.; Bergonzo, P.; de Boer, W.; Bogani, F.; Borchi, E.; Brambilla, A.; Bruzzi, M.; Colledani, C.; Conway, J.; D'Angelo, P.; Dabrowski, W.; Delpierre, P.; Dulinski, W.; Doroshenko, J.; Doucet, M.; van Eijk, B.; Fallou, A.; Fischer, P.; Fizzotti, F.; Kania, D.; Gan, K. K.; Grigoriev, E.; Hallewell, G.; Han, S.; Hartjes, F.; Hrubec, J.; Husson, D.; Kagan, H.; Kaplon, J.; Kass, R.; Knöpfle, K. T.; Koeth, T.; Krammer, M.; Logiudice, A.; mac Lynne, L.; Manfredotti, C.; Meier, D.; Menichelli, D.; Meuser, S.; Mishina, M.; Moroni, L.; Noomen, J.; Oh, A.; Pan, L. S.; Pernicka, M.; Perera, L.; Riester, J. L.; Roe, S.; Rudge, A.; Russ, J.; Sala, S.; Sampietro, M.; Schnetzer, S.; Sciortino, S.; Stelzer, H.; Stone, R.; Suter, B.; Trischuk, W.; Tromson, D.; Vittone, E.; Weilhammer, P.; Wermes, N.; Wetstein, M.; Zeuner, W.; Zoeller, M.

2003-03-01

Diamond is a promising sensor material for future collider experiments due to its radiation hardness. Diamond pixel sensors have been bump bonded to an ATLAS pixel readout chip using PbSn solder bumps. Single chip devices have been characterised by lab measurements and in a high-energy pion beam at CERN. Results on charge collection, spatial resolution, efficiency and the charge carrier lifetime are presented.

The rectenna design on contact lens for wireless powering of the active intraocular pressure monitoring system.

PubMed

Cheng, H W; Jeng, B M; Chen, C Y; Huang, H Y; Chiou, J C; Luo, C H

2013-01-01

This paper proposed a wireless power harvesting system with micro-electro-mechanical-systems (MEMS) fabrication for noninvasive intraocular pressure (IOP) measurement on soft contact lens substructure. The power harvesting IC consists of a loop antenna, an impedance matching network and a rectifier. The proposed IC has been designed and fabricated by CMOS 0.18 um process that operates at the ISM band of 5.8 GHz. The antenna and the power harvesting IC would be bonded together by using flip chip bonding technologies without extra wire interference. The circuit utilized an impedance transformation circuit to boost the input RF signal that improves the circuit performance. The proposed design achieves an RF-to-DC conversion efficiency of 35% at 5.8 GHz.

Automated Hybridization of X-ray Absorber Elements-A Path to Large Format Microcalorimeter Arrays

NASA Technical Reports Server (NTRS)

Moseley, S.; Kelley, R.; Allen, C.; Kilbourne, C.; Costen, N.; Miller, T.

2007-01-01

In the design of microcalorimeters, it is often desirable to produce the X-ray absorber separately from the detector element. In this case, the attachment of the absorber to the detector element with the required thermal and mechanical characteristics is a major challenge. In such arrays, the attachment has been done by hand. This process is not easily extended to the large format arrays required for future X- ray astronomy missions such as the New x-ray Telescope or NeXT. In this paper we present an automated process for attaching absorber tiles to the surface of a large-scale X-ray detector array. The absorbers are attached with stycast epoxy to a thermally isolating polymer structure made of SU-8. SU-8 is a negative epoxy based photo resist produced by Microchem. We describe the fabrication of the X-ray absorbers and their suspension on a handle die in an adhesive matrix. We describe the production process for the polymer isolators on the detector elements. We have developed a new process for the alignment, and simultaneous bonding of the absorber tiles to an entire detector array. This process uses equipment and techniques used in the flip-chip bonding industry and approaches developed in the fabrication of the XRS-2 instrument. XRS-2 was an X-ray spectrometer that was launched on the Suzaku telescope in July 10, 2005. We describe the process and show examples of sample arrays produced by this process. Arrays with up to 300 elements have been bonded. The present tests have used dummy absorbers made of Si. In future work, we will demonstrate bonding of HgTe absorbers.

Contamination control in hybrid microelectronic modules. Part 3: Specifications for coating material and process controls

NASA Technical Reports Server (NTRS)

Himmel, R. P.

1975-01-01

Resin systems for coating hybrids prior to hermetic sealing are described. The resin systems are a flexible silicone junction resin system and a flexible cycloaliphatic epoxy resin system. The coatings are intended for application to the hybrid after all the chips have been assembled and wire bonded, but prior to hermetic sealing of the package. The purpose of the coating is to control particulate contamination by immobilizing particles and by passivating the hybrid. Recommended process controls for the purpose of minimizing contamination in hybrid microcircuit packages are given. Emphasis is placed on those critical hybrid processing steps in which contamination is most likely to occur.

Grinding damage assessment for CAD-CAM restorative materials.

PubMed

Curran, Philippe; Cattani-Lorente, Maria; Anselm Wiskott, H W; Durual, Stéphane; Scherrer, Susanne S

2017-03-01

To assess surface/subsurface damage after grinding with diamond discs on five CAD-CAM restorative materials and to estimate potential losses in strength based on crack size measurements of the generated damage. The materials tested were: Lithium disilicate (LIT) glass-ceramic (e.max CAD), leucite glass-ceramic (LEU) (Empress CAD), feldspar ceramic (VM2) (Vita Mark II), feldspar ceramic-resin infiltrated (EN) (Enamic) and a composite reinforced with nano ceramics (LU) (Lava Ultimate). Specimens were cut from CAD-CAM blocs and pair-wise mirror polished for the bonded interface technique. Top surfaces were ground with diamond discs of respectively 75, 54 and 18μm. Chip damage was measured on the bonded interface using SEM. Fracture mechanics relationships were used to estimate fracture stresses based on average and maximum chip depths assuming these to represent strength limiting flaws subjected to tension and to calculate potential losses in strength compared to manufacturer's data. Grinding with a 75μm diamond disc induced on a bonded interface critical chips averaging 100μm with a potential strength loss estimated between 33% and 54% for all three glass-ceramics (LIT, LEU, VM2). The softer materials EN and LU were little damage susceptible with chips averaging respectively 26μm and 17μm with no loss in strength. Grinding with 18μm diamond discs was still quite detrimental for LIT with average chip sizes of 43μm and a potential strength loss of 42%. It is essential to understand that when grinding glass-ceramics or feldspar ceramics with diamond discs surface and subsurface damage are induced which have the potential of lowering the strength of the ceramic. Careful polishing steps should be carried out after grinding especially when dealing with glass-ceramics. Copyright © 2017 The Academy of Dental Materials. Published by Elsevier Ltd. All rights reserved.

PbS-PbSe IR detector arrays

NASA Technical Reports Server (NTRS)

Barrett, John R. (Inventor)

1986-01-01

A silicon wafer is provided which does not employ individually bonded leads between the IR sensitive elements and the input stages of multiplexers. The wafer is first coated with lead selenide in a first detector array area and is thereafter coated with lead sulfide within a second detector array area. The described steps result in the direct chemical deposition of lead selenide and lead sulfide upon the silicon wafer to eliminate individual wire bonding, bumping, flip chipping, planar interconnecting methods of connecting detector array elements to silicon chip circuitry, e.g., multiplexers, to enable easy fabrication of very long arrays. The electrode structure employed, produces an increase in the electrical field gradient between the electrodes for a given volume of detector material, relative to conventional electrode configurations.

Synthesis of antiviral tetrahydrocarbazole derivatives by photochemical and acid-catalyzed C-H functionalization via intermediate peroxides (CHIPS).

PubMed

Gulzar, Naeem; Klussmann, Martin

2014-06-20

The direct functionalization of C-H bonds is an important and long standing goal in organic chemistry. Such transformations can be very powerful in order to streamline synthesis by saving steps, time and material compared to conventional methods that require the introduction and removal of activating or directing groups. Therefore, the functionalization of C-H bonds is also attractive for green chemistry. Under oxidative conditions, two C-H bonds or one C-H and one heteroatom-H bond can be transformed to C-C and C-heteroatom bonds, respectively. Often these oxidative coupling reactions require synthetic oxidants, expensive catalysts or high temperatures. Here, we describe a two-step procedure to functionalize indole derivatives, more specifically tetrahydrocarbazoles, by C-H amination using only elemental oxygen as oxidant. The reaction uses the principle of C-H functionalization via Intermediate PeroxideS (CHIPS). In the first step, a hydroperoxide is generated oxidatively using visible light, a photosensitizer and elemental oxygen. In the second step, the N-nucleophile, an aniline, is introduced by Brønsted-acid catalyzed activation of the hydroperoxide leaving group. The products of the first and second step often precipitate and can be conveniently filtered off. The synthesis of a biologically active compound is shown.

Fast and reliable method to estimate losses of single-mode waveguides with an arbitrary 2D trajectory.

PubMed

Negredo, F; Blaicher, M; Nesic, A; Kraft, P; Ott, J; Dörfler, W; Koos, C; Rockstuhl, C

2018-06-01

Photonic wire bonds, i.e., freeform waveguides written by 3D direct laser writing, emerge as a technology to connect different optical chips in fully integrated photonic devices. With the long-term vision of scaling up this technology to a large-scale fabrication process, the in situ optimization of the trajectory of photonic wire bonds is at stake. A prerequisite for the real-time optimization is the availability of a fast loss estimator for single-mode waveguides of arbitrary trajectory. Losses occur because of the bending of the waveguides and at transitions among sections of the waveguide with different curvatures. Here, we present an approach that resides on the fundamental mode approximation, i.e., the assumption that the photonic wire bonds predominantly carry their energy in a single mode. It allows us to predict in a quick and reliable way the pertinent losses from pre-computed modal properties of the waveguide, enabling fast design of optimum paths.

Microfabrication of plastic-PDMS microfluidic devices using polyimide release layer and selective adhesive bonding

DOE PAGES

Wang, Shuyu; Yu, Shifeng; Lu, Ming; ...

2017-03-15

In this study, we present an improved method to bond poly(dimethylsiloxane) (PDMS) with polyimide (PI) to develop flexible substrate microfluidic devices. The PI film was separately fabricated on a silicon wafer by spin coating followed by thermal treatment to avoid surface unevenness of the flexible substrate. In this way, we could also integrate flexible substrate into standard micro-electromechanical systems (MEMS) fabrication. Meanwhile, the adhesive epoxy was selectively transferred to the PDMS microfluidic device by a stamp-and-stick method to avoid epoxy clogging the microfluidic channels. To spread out the epoxy evenly on the transferring substrate, we used superhydrophilic vanadium oxide filmmore » coated glass as the transferring substrate. After the bonding process, the flexible substrate could easily be peeled off from the rigid substrate. Contact angle measurement was used to characterize the hydrophicity of the vanadium oxide film. X-ray photoelectron spectroscopy analysis was conducted to study the surface of the epoxy. We further evaluated the bonding quality by peeling tests, which showed a maximum bonding strength of 100 kPa. By injecting with black ink, the plastic microfluidic device was confirmed to be well bonded with no leakage for a day under 1 atm. Finally, this proposed versatile method could bond the microfluidic device and plastic substrate together and be applied in the fabrication of some biosensors and lab-on-a-chip systems.« less

Microfabrication of plastic-PDMS microfluidic devices using polyimide release layer and selective adhesive bonding

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Shuyu; Yu, Shifeng; Lu, Ming

In this study, we present an improved method to bond poly(dimethylsiloxane) (PDMS) with polyimide (PI) to develop flexible substrate microfluidic devices. The PI film was separately fabricated on a silicon wafer by spin coating followed by thermal treatment to avoid surface unevenness of the flexible substrate. In this way, we could also integrate flexible substrate into standard micro-electromechanical systems (MEMS) fabrication. Meanwhile, the adhesive epoxy was selectively transferred to the PDMS microfluidic device by a stamp-and-stick method to avoid epoxy clogging the microfluidic channels. To spread out the epoxy evenly on the transferring substrate, we used superhydrophilic vanadium oxide filmmore » coated glass as the transferring substrate. After the bonding process, the flexible substrate could easily be peeled off from the rigid substrate. Contact angle measurement was used to characterize the hydrophicity of the vanadium oxide film. X-ray photoelectron spectroscopy analysis was conducted to study the surface of the epoxy. We further evaluated the bonding quality by peeling tests, which showed a maximum bonding strength of 100 kPa. By injecting with black ink, the plastic microfluidic device was confirmed to be well bonded with no leakage for a day under 1 atm. Finally, this proposed versatile method could bond the microfluidic device and plastic substrate together and be applied in the fabrication of some biosensors and lab-on-a-chip systems.« less

Rapid bonding of polydimethylsiloxane (PDMS) to various stereolithographically (STL) structurable epoxy resins using photochemically cross-linked intermediary siloxane layers

NASA Astrophysics Data System (ADS)

Wilhelm, Elisabeth; Neumann, Christiane; Sachsenheimer, Kai; Länge, Kerstin; Rapp, Bastian E.

2014-03-01

In this paper we present a fast, low cost bonding technology for combining rigid epoxy components with soft membranes made out of polydimethylsiloxane (PDMS). Both materials are commonly used for microfluidic prototyping. Epoxy resins are often applied when rigid channels are required, that will not deform if exposed to high pressure. PDMS, on the other hand, is a flexible material, which allows integration of membrane valves on the chip. However, the integration of pressure driven components, such as membrane valves and pumps, into a completely flexible device leads to pressure losses. In order to build up pressure driven components with maximum energy efficiency a combination of rigid guiding channels and flexible membranes would be advisable. Stereolithographic (STL) structuring would be an ideal fabrication technique for this purpose, because complex 3D-channels structures can easily be fabricated using this technology. Unfortunately, the STL epoxies cannot be bonded using common bonding techniques. For this reason we propose two UV-light based silanization techniques that enable plasma induced bonding of epoxy components. The entire process including silanization and corona discharge bonding can be carried out within half an hour. Average bond strengths up to 350 kPa (depending on the silane) were determined in ISO-conform tensile testing. The applicability of both techniques for microfluidic applications was proven by hydrolytic stability testing lasting more than 40 hours.

Nanofiber Anisotropic Conductive Films (ACF) for Ultra-Fine-Pitch Chip-on-Glass (COG) Interconnections

NASA Astrophysics Data System (ADS)

Lee, Sang-Hoon; Kim, Tae-Wan; Suk, Kyung-Lim; Paik, Kyung-Wook

2015-11-01

Nanofiber anisotropic conductive films (ACF) were invented, by adapting nanofiber technology to ACF materials, to overcome the limitations of ultra-fine-pitch interconnection packaging, i.e. shorts and open circuits as a result of the narrow space between bumps and electrodes. For nanofiber ACF, poly(vinylidene fluoride) (PVDF) and poly(butylene succinate) (PBS) polymers were used as nanofiber polymer materials. For PVDF and PBS nanofiber ACF, conductive particles of diameter 3.5 μm were incorporated into nanofibers by electrospinning. In ultra-fine-pitch chip-on-glass assembly, insulation was significantly improved by using nanofiber ACF, because nanofibers inside the ACF suppressed the mobility of conductive particles, preventing them from flowing out during the bonding process. Capture of conductive particles was increased from 31% (conventional ACF) to 65%, and stable electrical properties and reliability were achieved by use of nanofiber ACF.

Sample flow switching techniques on microfluidic chips.

PubMed

Pan, Yu-Jen; Lin, Jin-Jie; Luo, Win-Jet; Yang, Ruey-Jen

2006-02-15

This paper presents an experimental investigation into electrokinetically focused flow injection for bio-analytical applications. A novel microfluidic device for microfluidic sample handling is presented. The microfluidic chip is fabricated on glass substrates using conventional photolithographic and chemical etching processes and is bonded using a high-temperature fusion method. The proposed valve-less device is capable not only of directing a single sample flow to a specified output port, but also of driving multiple samples to separate outlet channels or even to a single outlet to facilitate sample mixing. The experimental results confirm that the sample flow can be electrokinetically pre-focused into a narrow stream and guided to the desired outlet port by means of a simple control voltage model. The microchip presented within this paper has considerable potential for use in a variety of applications, including high-throughput chemical analysis, cell fusion, fraction collection, sample mixing, and many other applications within the micro-total-analysis systems field.

Monolithic short wave infrared (SWIR) detector array

NASA Technical Reports Server (NTRS)

1983-01-01

A monolithic self-scanned linear detector array was developed for remote sensing in the 1.1- 2.4-micron spectral region. A high-density IRCCD test chip was fabricated to verify new design approaches required for the detector array. The driving factors in the Schottky barrier IRCCD (Pdsub2Si) process development are the attainment of detector yield, uniformity, adequate quantum efficiency, and lowest possible dark current consistent with radiometric accuracy. A dual-band module was designed that consists of two linear detector arrays. The sensor architecture places the floating diffusion output structure in the middle of the chip, away from the butt edges. A focal plane package was conceptualized and includes a polycrystalline silicon substrate carrying a two-layer, thick-film interconnecting conductor pattern and five epoxy-mounted modules. A polycrystalline silicon cover encloses the modules and bond wires, and serves as a radiation and EMI shield, thermal conductor, and contamination seal.

Plastic lab-on-a-chip for fluorescence excitation with integrated organic semiconductor lasers.

PubMed

Vannahme, Christoph; Klinkhammer, Sönke; Lemmer, Uli; Mappes, Timo

2011-04-25

Laser light excitation of fluorescent markers offers highly sensitive and specific analysis for bio-medical or chemical analysis. To profit from these advantages for applications in the field or at the point-of-care, a plastic lab-on-a-chip with integrated organic semiconductor lasers is presented here. First order distributed feedback lasers based on the organic semiconductor tris(8-hydroxyquinoline) aluminum (Alq3) doped with the laser dye 4-dicyanomethylene-2-methyl-6-(p-dimethylaminostyril)-4H-pyrane (DCM), deep ultraviolet induced waveguides, and a nanostructured microfluidic channel are integrated into a poly(methyl methacrylate) (PMMA) substrate. A simple and parallel fabrication process is used comprising thermal imprint, DUV exposure, evaporation of the laser material, and sealing by thermal bonding. The excitation of two fluorescent marker model systems including labeled antibodies with light emitted by integrated lasers is demonstrated.

Germanium ``hexa'' detector: production and testing

NASA Astrophysics Data System (ADS)

Sarajlić, M.; Pennicard, D.; Smoljanin, S.; Hirsemann, H.; Struth, B.; Fritzsch, T.; Rothermund, M.; Zuvic, M.; Lampert, M. O.; Askar, M.; Graafsma, H.

2017-01-01

Here we present new result on the testing of a Germanium sensor for X-ray radiation. The system is made of 3 × 2 Medipix3RX chips, bump-bonded to a monolithic sensor, and is called ``hexa''. Its dimensions are 45 × 30 mm2 and the sensor thickness was 1.5 mm. The total number of the pixels is 393216 in the matrix 768 × 512 with pixel pitch 55 μ m. Medipix3RX read-out chip provides photon counting read-out with single photon sensitivity. The sensor is cooled to -126°C and noise levels together with flat field response are measured. For -200 V polarization bias, leakage current was 4.4 mA (3.2 μ A/mm2). Due to higher leakage around 2.5% of all pixels stay non-responsive. More than 99% of all pixels are bump bonded correctly. In this paper we present the experimental set-up, threshold equalization procedure, image acquisition and the technique for bump bond quality estimate.

Integrated Inductors for RF Transmitters in CMOS/MEMS Smart Microsensor Systems

PubMed Central

Kim, Jong-Wan; Takao, Hidekuni; Sawada, Kazuaki; Ishida, Makoto

2007-01-01

This paper presents the integration of an inductor by complementary metal-oxide-semiconductor (CMOS) compatible processes for integrated smart microsensor systems that have been developed to monitor the motion and vital signs of humans in various environments. Integration of radio frequency transmitter (RF) technology with complementary metal-oxide-semiconductor/micro electro mechanical systems (CMOS/MEMS) microsensors is required to realize the wireless smart microsensors system. The essential RF components such as a voltage controlled RF-CMOS oscillator (VCO), spiral inductors for an LC resonator and an integrated antenna have been fabricated and evaluated experimentally. The fabricated RF transmitter and integrated antenna were packaged with subminiature series A (SMA) connectors, respectively. For the impedance (50 Ω) matching, a bonding wire type inductor was developed. In this paper, the design and fabrication of the bonding wire inductor for impedance matching is described. Integrated techniques for the RF transmitter by CMOS compatible processes have been successfully developed. After matching by inserting the bonding wire inductor between the on-chip integrated antenna and the VCO output, the measured emission power at distance of 5 m from RF transmitter was -37 dBm (0.2 μW).

Vacuum Gap Microstrip Microwave Resonators for 2.5-D Integration in Quantum Computing

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lewis, Rupert M.; Henry, Michael David; Schroeder, Katlin

We demonstrate vacuum gap λ/2 microwave resonators as a route toward higher integration in superconducting qubit circuits. The resonators are fabricated from pieces on two silicon chips bonded together with an In-Sb bond. Measurements of the devices yield resonant frequencies in good agreement with simulations. Furthermore, we discuss creating low loss circuits in this geometry.

Vacuum Gap Microstrip Microwave Resonators for 2.5-D Integration in Quantum Computing

DOE PAGES

Lewis, Rupert M.; Henry, Michael David; Schroeder, Katlin

2017-02-22

We demonstrate vacuum gap λ/2 microwave resonators as a route toward higher integration in superconducting qubit circuits. The resonators are fabricated from pieces on two silicon chips bonded together with an In-Sb bond. Measurements of the devices yield resonant frequencies in good agreement with simulations. Furthermore, we discuss creating low loss circuits in this geometry.

Self-regenerating and hybrid irreversible/reversible PDMS microfluidic devices.

PubMed

Shiroma, Letícia S; Piazzetta, Maria H O; Duarte-Junior, Gerson F; Coltro, Wendell K T; Carrilho, Emanuel; Gobbi, Angelo L; Lima, Renato S

2016-05-16

This paper outlines a straightforward, fast, and low-cost method to fabricate polydimethylsiloxane (PDMS) chips. Termed sandwich bonding (SWB), this method requires only a laboratory oven. Initially, SWB relies on the reversible bonding of a coverslip over PDMS channels. The coverslip is smaller than the substrate, leaving a border around the substrate exposed. Subsequently, a liquid composed of PDMS monomers and a curing agent is poured onto the structure. Finally, the cover is cured. We focused on PDMS/glass chips because of their key advantages in microfluidics. Despite its simplicity, this method created high-performance microfluidic channels. Such structures featured self-regeneration after leakages and hybrid irreversible/reversible behavior. The reversible nature was achieved by removing the cover of PDMS with acetone. Thus, the PDMS substrate and glass coverslip could be detached for reuse. These abilities are essential in the stages of research and development. Additionally, SWB avoids the use of surface oxidation, half-cured PDMS as an adhesive, and surface chemical modification. As a consequence, SWB allows surface modifications before the bonding, a long time for alignment, the enclosure of sub-micron channels, and the prototyping of hybrid devices. Here, the technique was successfully applied to bond PDMS to Au and Al.

Self-regenerating and hybrid irreversible/reversible PDMS microfluidic devices

PubMed Central

Shiroma, Letícia S.; Piazzetta, Maria H. O.; Duarte-Junior, Gerson F.; Coltro, Wendell K. T.; Carrilho, Emanuel; Gobbi, Angelo L.; Lima, Renato S.

2016-01-01

This paper outlines a straightforward, fast, and low-cost method to fabricate polydimethylsiloxane (PDMS) chips. Termed sandwich bonding (SWB), this method requires only a laboratory oven. Initially, SWB relies on the reversible bonding of a coverslip over PDMS channels. The coverslip is smaller than the substrate, leaving a border around the substrate exposed. Subsequently, a liquid composed of PDMS monomers and a curing agent is poured onto the structure. Finally, the cover is cured. We focused on PDMS/glass chips because of their key advantages in microfluidics. Despite its simplicity, this method created high-performance microfluidic channels. Such structures featured self-regeneration after leakages and hybrid irreversible/reversible behavior. The reversible nature was achieved by removing the cover of PDMS with acetone. Thus, the PDMS substrate and glass coverslip could be detached for reuse. These abilities are essential in the stages of research and development. Additionally, SWB avoids the use of surface oxidation, half-cured PDMS as an adhesive, and surface chemical modification. As a consequence, SWB allows surface modifications before the bonding, a long time for alignment, the enclosure of sub-micron channels, and the prototyping of hybrid devices. Here, the technique was successfully applied to bond PDMS to Au and Al. PMID:27181918

Micro flow-through PCR in a PMMA chip fabricated by KrF excimer laser.

PubMed

Yao, Liying; Liu, Baoan; Chen, Tao; Liu, Shibing; Zuo, Tiechuan

2005-09-01

As the third PCR technology, micro flow-through PCR chip can amplify DNA specifically in an exponential fashion in vitro. Nowadays many academies in the world have successfully amplified DNA using their own-made flow-through PCR chip. In this paper, the ablation principle of PMMA at 248 nm excimer laser was studied, then a PMMA based flow-through PCR chip with 20 cycles was fabricated by excimer laser at 19 kv and 18 mm/min. The chip was bonded together with another cover chip at 105( composite function)C, 160 N and 20 minutes. In the end, it was integrated with electrical thermal thin films and Pt 100 temperature sensors. The temperature controllers was built standard PID digital temperature controller, the temperature control precision was +/- 0.2( composite function)C. The temperature grads between the three temperature zones were 16.5 and 22.2( composite function)C respectively, the gaps between the temperature zones could realize heat insulation.

Single level microelectronic device package with an integral window

DOEpatents

Peterson, Kenneth A.; Watson, Robert D.

2003-12-09

A package with an integral window for housing a microelectronic device. The integral window is bonded directly to the package without having a separate layer of adhesive material disposed in-between the window and the package. The device can be a semiconductor chip, CCD chip, CMOS chip, VCSEL chip, laser diode, MEMS device, or IMEMS device. The package can be formed of a multilayered LTCC or HTCC cofired ceramic material, with the integral window being simultaneously joined to the package during cofiring. The microelectronic device can be flip-chip interconnected so that the light-sensitive side is optically accessible through the window. A glob-top encapsulant or protective cover can be used to protect the microelectronic device and electrical interconnections. The result is a compact, low profile package having an integral window that is hermetically sealed to the package prior to mounting and interconnecting the microelectronic device.

Multilayer-based lab-on-a-chip systems for perfused cell-based assays

NASA Astrophysics Data System (ADS)

Klotzbach, Udo; Sonntag, Frank; Grünzner, Stefan; Busek, Mathias; Schmieder, Florian; Franke, Volker

2014-12-01

A novel integrated technology chain of laser-microstructured multilayer foils for fast, flexible, and low-cost manufacturing of lab-on-a-chip devices especially for complex cell and tissue culture applications, which provides pulsatile fluid flow within physiological ranges at low media-to-cells ratio, was developed and established. Initially the microfluidic system is constructively divided into individual layers, which are formed by separate foils or plates. Based on the functional boundary conditions and the necessary properties of each layer, their corresponding foils and plates are chosen. In the third step, the foils and plates are laser microstructured and functionalized from both sides. In the fourth and last manufacturing step, the multiple plates and foils are joined using different bonding techniques like adhesive bonding, welding, etc. This multilayer technology together with pneumatically driven micropumps and valves permits the manufacturing of fluidic structures and perfusion systems, which spread out above multiple planes. Based on the established lab-on-a-chip platform for perfused cell-based assays, a multilayer microfluidic system with two parallel connected cell culture chambers was successfully implemented.

Body of Knowledge (BOK) for Copper Wire Bonds

NASA Technical Reports Server (NTRS)

Rutkowski, E.; Sampson, M. J.

2015-01-01

Copper wire bonds have replaced gold wire bonds in the majority of commercial semiconductor devices for the latest technology nodes. Although economics has been the driving mechanism to lower semiconductor packaging costs for a savings of about 20% by replacing gold wire bonds with copper, copper also has materials property advantages over gold. When compared to gold, copper has approximately: 25% lower electrical resistivity, 30% higher thermal conductivity, 75% higher tensile strength and 45% higher modulus of elasticity. Copper wire bonds on aluminum bond pads are also more mechanically robust over time and elevated temperature due to the slower intermetallic formation rate - approximately 1/100th that of the gold to aluminum intermetallic formation rate. However, there are significant tradeoffs with copper wire bonding - copper has twice the hardness of gold which results in a narrower bonding manufacturing process window and requires that the semiconductor companies design more mechanically rigid bonding pads to prevent cratering to both the bond pad and underlying chip structure. Furthermore, copper is significantly more prone to corrosion issues. The semiconductor packaging industry has responded to this corrosion concern by creating a palladium coated copper bonding wire, which is more corrosion resistant than pure copper bonding wire. Also, the selection of the device molding compound is critical because use of environmentally friendly green compounds can result in internal CTE (Coefficient of Thermal Expansion) mismatches with the copper wire bonds that can eventually lead to device failures during thermal cycling. Despite the difficult problems associated with the changeover to copper bonding wire, there are billions of copper wire bonded devices delivered annually to customers. It is noteworthy that Texas Instruments announced in October of 2014 that they are shipping microcircuits containing copper wire bonds for safety critical automotive applications. An evaluation of copper wire bond technology for applicability to spaceflight hardware may be warranted along with concurrently compiling a comprehensive understanding of the failure mechanisms involved with copper wire bonded semiconductor devices.

[Preparation of poly(methyl acrylate) microfluidic chips surface-modified by hyperbranched polyamide ester and their application in the separation of biomolecules].

PubMed

Liu, Bing; Lin, Donge; Xu, Lin; Lei, Yanhui; Bo, Qianglong; Shou, Chongqi

2012-05-01

The surface of poly (methyl acrylate) (PMMA) microfluidic chips were modified using hyperbranched polyamide ester via chemical bonding. The contact angles of the modified chips were measured. The surface morphology was observed by scanning electron microscope (SEM) and stereo microscope. The results showed that the surface of the modified chips was coated by a dense, uniform, continuous, hydrophilic layer of hyperbranched polyamide ester. The hydrophilic of the chip surface was markedly improved. The contact angle of the chips modified decreased from 89.9 degrees to 29.5 degrees. The electro osmotic flow (EOF) in the modified microchannel was lower than that in the unmodified microchannel. Adenosine and L-lysine were detected and separated via the modified PMMA microfluidic chips. Compared with unmodified chips, the modified chips successfully separated the two biomolecules. The detection peaks were clear and sharp. The separation efficiencies of adenosine and L-lysine were 8.44 x 10(4) plates/m and 9.82 x 10(4) plates/m respectively, and the resolutions (Rs) was 5.31. The column efficiencies and resolutions of the modified chips were much higher than those of the unmodified chips. It was also observed that the modified chips possessed good reproducibility of migration time. This research may provide a new and effective method to improve the hydrophilicity of the PMMA surface and the application of PMMA microfluidic chips in the determination of trace biomolecules.

Investigation of electromigration behavior in lead-free flip chip solder bumps

NASA Astrophysics Data System (ADS)

Kalkundri, Kaustubh Jayant

Packaging technology has also evolved over time in an effort to keep pace with the demanding requirements. Wirebond and flip chip packaging technologies have become extremely versatile and ubiquitous in catering to myriad applications due to their inherent potential. This research is restricted strictly to flip chip technology. This technology incorporates a process in which the bare chip is turned upside down, i.e., active face down, and is bonded through the I/O to the substrate, hence called flip chip. A solder interconnect that provides electrical connection between the chip and substrate is bumped on a processed silicon wafer prior to dicing for die-attach. The assembly is then reflow-soldered followed by the underfill process to provide the required encapsulation. The demand for smaller and lighter products has increased the number of I/Os without increasing the package sizes, thereby drastically reducing the size of the flip chip solder bumps and their pitch. Reliability assessment and verification of these devices has gained tremendous importance due to their shrinking size. To add to the complexity, changing material sets that are results of recently enacted lead-free solder legislations have raised some compatibility issues that are already being researched. In addition to materials and process related flip chip challenges such as solder-flux compatibility, Coefficient of Thermal Expansion (CTE) mismatch, underfill-flux compatibility and thermal management, flip chip packages are vulnerable to a comparatively newer challenge, namely electromigration observed in solder bumps. It is interesting to note that electromigration has come to the forefront of challenges only recently. It has been exacerbated by the reduction in bump cross-section due to the seemingly continuous shrinking in package size over time. The focus of this research was to understand the overall electromigration behavior in lead-free (SnAg) flip chip solder bumps. The objectives of the research were to comprehend the physics of failure mechanism in electromigration for lead-free solder bumps assembled in a flip chip ceramic package having thick copper under bump metallization and to estimate the unknown critical material parameters from Black's equation that describe failure due to electromigration. In addition, the intent was to verify the 'use condition reliability' by extrapolation from experimental conditions. The methodology adopted for this research was comprised of accelerated electromigration tests on SnAg flip chip solder bumps assembled on ceramic substrate with a thick copper under bump metallization. The experimental approach was comprised of elaborate measurement of the temperature of each sample by separate metallization resistance exhibiting positive resistance characteristics to overcome the variation in Joule heating. After conducting the constant current experiments and analyzing the failed samples, it was found that the primary electromigration failure mode observed was the dissolution of the thick copper under bump metallization in the solder, leading to a change in resistance. The lifetime data obtained from different experiments was solved simultaneously using a multiple regression approach to yield the unknown Black's equation parameters of current density exponent and activation energy. In addition to the implementation of a systematic failure analysis and data analysis procedure, it was also deduced that thermomigration due to the temperature gradient across the chip does impact the overall electromigration behavior. This research and the obtained results were significant in bridging the gap for an overall understanding of this critical failure mode observed in flip chip solder bumps. The measurement of each individual sample temperature instead of an average temperature enabled an accurate analysis for predicting the 'use condition reliability' of a comparable product. The obtained results and the conclusions can be used as potential inputs in future designs and newer generations of flip chip devices that might undergo aggressive scaling. This will enable these devices to retain their functionality during their intended useful life with minimal threat of failure due to the potent issue of electromigration. (Abstract shortened by UMI.)

Design and fabrication of a multilayered polymer microfluidic chip with nanofluidic interconnects via adhesive contact printing.

PubMed

Flachsbart, Bruce R; Wong, Kachuen; Iannacone, Jamie M; Abante, Edward N; Vlach, Robert L; Rauchfuss, Peter A; Bohn, Paul W; Sweedler, Jonathan V; Shannon, Mark A

2006-05-01

The design and fabrication of a multilayered polymer micro-nanofluidic chip is described that consists of poly(methylmethacrylate) (PMMA) layers that contain microfluidic channels separated in the vertical direction by polycarbonate (PC) membranes that incorporate an array of nanometre diameter cylindrical pores. The materials are optically transparent to allow inspection of the fluids within the channels in the near UV and visible spectrum. The design architecture enables nanofluidic interconnections to be placed in the vertical direction between microfluidic channels. Such an architecture allows microchannel separations within the chip, as well as allowing unique operations that utilize nanocapillary interconnects: the separation of analytes based on molecular size, channel isolation, enhanced mixing, and sample concentration. Device fabrication is made possible by a transfer process of labile membranes and the development of a contact printing method for a thermally curable epoxy based adhesive. This adhesive is shown to have bond strengths that prevent leakage and delamination and channel rupture tests exceed 6 atm (0.6 MPa) under applied pressure. Channels 100 microm in width and 20 microm in depth are contact printed without the adhesive entering the microchannel. The chip is characterized in terms of resistivity measurements along the microfluidic channels, electroosmotic flow (EOF) measurements at different pH values and laser-induced-fluorescence (LIF) detection of green-fluorescent protein (GFP) plugs injected across the nanocapillary membrane and into a microfluidic channel. The results indicate that the mixed polymer micro-nanofluidic multilayer chip has electrical characteristics needed for use in microanalytical systems.

Silicon Integrated Optics: Fabrication and Characterization

NASA Astrophysics Data System (ADS)

Shearn, Michael Joseph, II

For decades, the microelectronics industry has sought integration and miniaturization as canonized in Moore's Law, and has continued doubling transistor density about every two years. However, further miniaturization of circuit elements is creating a bandwidth problem as chip interconnect wires shrink as well. A potential solution is the creation of an on-chip optical network with low delays that would be impossible to achieve using metal buses. However, this technology requires integrating optics with silicon microelectronics. The lack of efficient silicon optical sources has stymied efforts of an all-Si optical platform. Instead, the integration of efficient emitter materials, such as III-V semiconductors, with Si photonic structures is a low-cost, CMOS-compatible alternative platform. This thesis focuses on making and measuring on-chip photonic structures suitable for on-chip optical networking. The first part of the thesis assesses processing techniques of silicon and other semiconductor materials. Plasmas for etching and surface modification are described and used to make bonded, hybrid Si/III-V structures. Additionally, a novel masking method using gallium implantation into silicon for pattern definition is characterized. The second part of the thesis focuses on demonstrations of fabricated optical structures. A dense array of silicon devices is measured, consisting of fully-etched grating couplers, low-loss waveguides and ring resonators. Finally, recent progress in the Si/III-V hybrid system is discussed. Supermode control of devices is described, which uses changing Si waveguide width to control modal overlap with the gain material. Hybrid Si/III-V, Fabry-Perot evanescent lasers are demonstrated, utilizing a CMOS-compatible process suitable for integration on in electronics platforms. Future prospects and ultimate limits of Si devices and the hybrid Si/III-V system are also considered.

Label-free sensing of the binding state of MUC1 peptide and anti-MUC1 aptamer solution in fluidic chip by terahertz spectroscopy.

PubMed

Zhao, Xiang; Zhang, Mingkun; Wei, Dongshan; Wang, Yunxia; Yan, Shihan; Liu, Mengwan; Yang, Xiang; Yang, Ke; Cui, Hong-Liang; Fu, Weiling

2017-10-01

The aptamer and target molecule binding reaction has been widely applied for construction of aptasensors, most of which are labeled methods. In contrast, terahertz technology proves to be a label-free sensing tool for biomedical applications. We utilize terahertz absorption spectroscopy and molecular dynamics simulation to investigate the variation of binding-induced collective vibration of hydrogen bond network in a mixed solution of MUC1 peptide and anti-MUC1 aptamer. The results show that binding-induced alterations of hydrogen bond numbers could be sensitively reflected by the variation of terahertz absorption coefficients of the mixed solution in a customized fluidic chip. The minimal detectable concentration is determined as 1 pmol/μL, which is approximately equal to the optimal immobilized concentration of aptasensors.

A method for UV-bonding in the fabrication of glass electrophoretic microchips.

PubMed

Huang, Z; Sanders, J C; Dunsmor, C; Ahmadzadeh, H; Landers, J P

2001-10-01

This paper presents an approach for the development of methodologies amenable to simple and inexpensive microchip fabrication, potentially applicable to dissimilar materials bonding and chip integration. The method involves a UV-curable glue that can be used for glass microchip fabrication bonding at room temperature. This involves nothing more than fabrication of glue "guide channels" into the microchip architecture that upon exposure to the appropriate UV light source, bonds the etched plate and cover plate together. The microchip performance was verified by capillary zone electrophoresis (CZE) of small fluorescent molecules with no microchannel surface modification carried out, as well as with a DNA fragment separation following surface modification. The performance of these UV-bonded electrophoretic microchips indicates that this method may provide an alternative to high temperature bonding.

Comparison of contamination of femoral heads and pre-processed bone chips during hip revision arthroplasty.

PubMed

Mathijssen, N M C; Sturm, P D; Pilot, P; Bloem, R M; Buma, P; Petit, P L; Schreurs, B W

2013-12-01

With bone impaction grafting, cancellous bone chips made from allograft femoral heads are impacted in a bone defect, which introduces an additional source of infection. The potential benefit of the use of pre-processed bone chips was investigated by comparing the bacterial contamination of bone chips prepared intraoperatively with the bacterial contamination of pre-processed bone chips at different stages in the surgical procedure. To investigate baseline contamination of the bone grafts, specimens were collected during 88 procedures before actual use or preparation of the bone chips: in 44 procedures intraoperatively prepared chips were used (Group A) and in the other 44 procedures pre-processed bone chips were used (Group B). In 64 of these procedures (32 using locally prepared bone chips and 32 using pre-processed bone chips) specimens were also collected later in the procedure to investigate contamination after use and preparation of the bone chips. In total, 8 procedures had one or more positive specimen(s) (12.5 %). Contamination rates were not significantly different between bone chips prepared at the operating theatre and pre-processed bone chips. In conclusion, there was no difference in bacterial contamination between bone chips prepared from whole femoral heads in the operating room and pre-processed bone chips, and therefore, both types of bone allografts are comparable with respect to risk of infection.

National Dam Safety Program. Tivoli Lake Dam (Inventory Number N.Y. 52), Hudson River Basin, Rockland County, New York. Phase I Inspection Report,

DTIC Science & Technology

1980-09-30

3/8" pea gravel., Apply I coat of Uniweld or Sika Dur Hi-Mod over old concrete to insure the proper bonding. V 2. Repeat process one for section over...Bay 1. 3. Chip out cracked concrete along Bays 7 and 8, apply one coat Colma Joint Primer and fill with Colma Joint Sealer (As manufactured by Sika ) 4...deck. Cracked concrete should be repaired with Sika Dur. Hi-Mod and application of low slump nonshrink grout’ made with antihydro cement

High-frequency ultrasonic wire bonding systems

PubMed

Tsujino; Yoshihara; Sano; Ihara

2000-03-01

The vibration characteristics of longitudinal-complex transverse vibration systems with multiple resonance frequencies of 350-980 kHz for ultrasonic wire bonding of IC, LSI or electronic devices were studied. The complex vibration systems can be applied for direct welding of semiconductor tips (face-down bonding, flip-chip bonding) and packaging of electronic devices. A longitudinal-complex transverse vibration bonding system consists of a complex transverse vibration rod, two driving longitudinal transducers 7.0 mm in diameter and a transverse vibration welding tip. The vibration distributions along ceramic and stainless-steel welding tips were measured at up to 980 kHz. A high-frequency vibration system with a height of 20.7 mm and a weight of less than 15 g was obtained.

Design and test of data acquisition systems for the Medipix2 chip based on PC standard interfaces

NASA Astrophysics Data System (ADS)

Fanti, Viviana; Marzeddu, Roberto; Piredda, Giuseppina; Randaccio, Paolo

2005-07-01

We describe two readout systems for hybrid detectors using the Medipix2 single photon counting chip, developed within the Medipix Collaboration. The Medipix2 chip (256×256 pixels, 55 μm pitch) has an active area of about 2 cm 2 and is bump-bonded to a pixel semiconductor array of silicon or other semiconductor material. The readout systems we are developing are based on two widespread standard PC interfaces: parallel port and USB (Universal Serial Bus) version 1.1. The parallel port is the simplest PC interface even if slow and the USB is a serial bus interface present nowadays on all PCs and offering good performances.

Low temperature co-fired ceramic packaging of CMOS capacitive sensor chip towards cell viability monitoring.

PubMed

Halonen, Niina; Kilpijärvi, Joni; Sobocinski, Maciej; Datta-Chaudhuri, Timir; Hassinen, Antti; Prakash, Someshekar B; Möller, Peter; Abshire, Pamela; Kellokumpu, Sakari; Lloyd Spetz, Anita

2016-01-01

Cell viability monitoring is an important part of biosafety evaluation for the detection of toxic effects on cells caused by nanomaterials, preferably by label-free, noninvasive, fast, and cost effective methods. These requirements can be met by monitoring cell viability with a capacitance-sensing integrated circuit (IC) microchip. The capacitance provides a measurement of the surface attachment of adherent cells as an indication of their health status. However, the moist, warm, and corrosive biological environment requires reliable packaging of the sensor chip. In this work, a second generation of low temperature co-fired ceramic (LTCC) technology was combined with flip-chip bonding to provide a durable package compatible with cell culture. The LTCC-packaged sensor chip was integrated with a printed circuit board, data acquisition device, and measurement-controlling software. The packaged sensor chip functioned well in the presence of cell medium and cells, with output voltages depending on the medium above the capacitors. Moreover, the manufacturing of microfluidic channels in the LTCC package was demonstrated.

LED Die-Bonded on the Ag/Cu Substrate by a Sn-BiZn-Sn Bonding System

NASA Astrophysics Data System (ADS)

Tang, Y. K.; Hsu, Y. C.; Lin, E. J.; Hu, Y. J.; Liu, C. Y.

2016-12-01

In this study, light emitting diode (LED) chips were die-bonded on a Ag/Cu substrate by a Sn-BixZn-Sn bonding system. A high die-bonding strength is successfully achieved by using a Sn-BixZn-Sn ternary system. At the bonding interface, there is observed a Bi-segregation phenomenon. This Bi-segregation phenomenon solves the problems of the brittle layer-type Bi at the joint interface. Our shear test results show that the bonding interface with Bi-segregation enhances the shear strength of the LED die-bonding joints. The Bi-0.3Zn and Bi-0.5Zn die-bonding cases have the best shear strength among all die-bonding systems. In addition, we investigate the atomic depth profile of the deposited Bi-xZn layer by evaporating Bi-xZn E-gun alloy sources. The initial Zn content of the deposited Bi-Zn alloy layers are much higher than the average Zn content in the deposited Bi-Zn layers.

RFID and Memory Devices Fabricated Integrally on Substrates

NASA Technical Reports Server (NTRS)

Schramm, Harry F.

2004-01-01

Electronic identification devices containing radio-frequency identification (RFID) circuits and antennas would be fabricated integrally with the objects to be identified, according to a proposal. That is to say, the objects to be identified would serve as substrates for the deposition and patterning of the materials of the devices used to identify them, and each identification device would be bonded to the identified object at the molecular level. Vacuum arc vapor deposition (VAVD) is the NASA derived process for depositing layers of material on the substrate. This proposal stands in contrast to the current practice of fabricating RFID and/or memory devices as wafer-based, self-contained integrated-circuit chips that are subsequently embedded in or attached to plastic cards to make smart account-information cards and identification badges. If one relies on such a chip to store data on the history of an object to be tracked and the chip falls off or out of the object, then one loses both the historical data and the means to track the object and verify its identity electronically. Also, in contrast is the manufacturing philosophy in use today to make many memory devices. Today s methods involve many subtractive processes such as etching. This proposal only uses additive methods, building RFID and memory devices from the substrate up in thin layers. VAVD is capable of spraying silicon, copper, and other materials commonly used in electronic devices. The VAVD process sprays most metals and some ceramics. The material being sprayed has a very strong bond with the substrate, whether that substrate is metal, ceramic, or even wood, rock, glass, PVC, or paper. An object to be tagged with an identification device according to the proposal must be compatible with a vacuum deposition process. Temperature is seldom an issue as the substrate rarely reaches 150 F (66 C) during the deposition process. A portion of the surface of the object would be designated as a substrate for the deposition of the device. By use of a vacuum arc vapor deposition apparatus, a thin electrically insulating film would first be deposited on the substrate. Subsequent layers of materials would then be deposited and patterned by use of known integrated-circuit fabrication techniques. The total thickness of the deposited layers could be much less than the 100- m thickness of the thinnest state-of-the-art self-contained microchips. Such a thin deposit could be readily concealed by simply painting over it. Both large vacuum chambers for production runs and portable hand-held devices for in situ applications are available.

Wedge-shaped microfluidic chip for circulating tumor cells isolation and its clinical significance in gastric cancer.

PubMed

Yang, Chaogang; Zhang, Nangang; Wang, Shuyi; Shi, Dongdong; Zhang, Chunxiao; Liu, Kan; Xiong, Bin

2018-05-23

Circulating tumor cells (CTCs) have great potential in both basic research and clinical application for the managements of cancer. However, the complicated fabrication processes and expensive materials of the existing CTCs isolation devices, to a large extent, limit their clinical translation and CTCs' clinical value. Therefore, it remains to be urgently needed to develop a new platform for achieving CTCs detection with low-cost, mass-producible but high performance. In the present study, we introduced a novel wedge-shaped microfluidic chip (named CTC-ΔChip) fabricated by two pieces of glass through wet etching and thermal bonding technique for CTCs isolation, which achieved CTCs enrichment by different size without cell surface expression markers and CTCs identification with three-color immunocytochemistry method (CK+/CD45-/Nucleus+). We validated the feasibility of CTC-ΔChip for detecting CTCs from different types of solid tumor. Furthermore, we applied the newly-developed platform to investigate the clinical significance of CTCs in gastric cancer (GC). Based on "label-free" characteristic, the capture efficiency of CTC-ΔChip can be as high as 93.7 ± 3.2% in DMEM and 91.0 ± 3.0% in whole blood sample under optimized conditions. Clinically, CTC-ΔChip exhibited the feasibility of detecting CTCs from different types of solid tumor, and it identified 7.30 ± 7.29 CTCs from 2 mL peripheral blood with a positive rate of 75% (30/40) in GC patients. Interestingly, we found that GC CTCs count was significantly correlated with multiple systemic inflammation indexes, including the lymphocyte count, platelet count, the level of neutrophil to lymphocyte ratio and platelet to lymphocyte ratio. In addition, we also found that both the positivity rate and CTCs count were significantly associated with multiple clinicopathology parameters. Our novel CTC-ΔChip shows high performance for detecting CTCs from less volume of blood samples of cancer patients and important clinical significance in GC. Owing to the advantages of low-cost and mass-producible, CTC-ΔChip holds great potential of clinical application for cancer therapeutic guidance and prognostic monitoring in the future.

Improved fabrication techniques for infrared bolometers

NASA Technical Reports Server (NTRS)

Lange, A. E.; Mcbride, S. E.; Richards, P. L.; Haller, E. E.; Kreysa, E.

1983-01-01

Ion implantation and sputter metallization are used to produce ohmic electrical contacts to Ge:Ga chips. The method is shown to give a high yield of small monolithic bolometers with very little low-frequency noise. It is noted that when one of the chips is used as the thermometric element of a composite bolometer it must be bonded to a dielectric substrate. The thermal resistance of the conventional epoxy bond is measured and found to be undesirably large. A procedure for soldering the chip to a metallized portion of the substrate in such a way as to reduce this resistance is outlined. An evaluation is made of the contribution of the metal film absorber to the heat capacity of a composite bolometer. It is found that the heat capacity of a NiCr absorber at 1.3 K can dominate the bolometer performance. A Bi absorber possesses significantly lower heat capacity. A low-temperature blackbody calibrator is built to measure the optical responsivity of bolometers. A composite bolometer system with a throughput of approximately 0.1 sr sq cm is constructed using the new techniques. The noise in this bolometer is white above 2.5 Hz and is slightly below the value predicted by thermodynamic equilibrium theory.

Packaging Technologies for 500C SiC Electronics and Sensors

NASA Technical Reports Server (NTRS)

Chen, Liang-Yu

2013-01-01

Various SiC electronics and sensors are currently under development for applications in 500C high temperature environments such as hot sections of aerospace engines and the surface of Venus. In order to conduct long-term test and eventually commercialize these SiC devices, compatible packaging technologies for the SiC electronics and sensors are required. This presentation reviews packaging technologies developed for 500C SiC electronics and sensors to address both component and subsystem level packaging needs for high temperature environments. The packaging system for high temperature SiC electronics includes ceramic chip-level packages, ceramic printed circuit boards (PCBs), and edge-connectors. High temperature durable die-attach and precious metal wire-bonding are used in the chip-level packaging process. A high temperature sensor package is specifically designed to address high temperature micro-fabricated capacitive pressure sensors for high differential pressure environments. This presentation describes development of these electronics and sensor packaging technologies, including some testing results of SiC electronics and capacitive pressure sensors using these packaging technologies.

A Compact Polarization Imager

NASA Technical Reports Server (NTRS)

Thompson, Karl E.; Rust, David M.; Chen, Hua

1995-01-01

A new type of image detector has been designed to analyze the polarization of light simultaneously at all picture elements (pixels) in a scene. The Integrated Dual Imaging Detector (IDID) consists of a polarizing beamsplitter bonded to a custom-designed charge-coupled device with signal-analysis circuitry, all integrated on a silicon chip. The IDID should simplify the design and operation of imaging polarimeters and spectroscopic imagers used, for example, in atmospheric and solar research. Other applications include environmental monitoring and robot vision. Innovations in the IDID include two interleaved 512 x 1024 pixel imaging arrays (one for each polarization plane), large dynamic range (well depth of 10(exp 6) electrons per pixel), simultaneous readout and display of both images at 10(exp 6) pixels per second, and on-chip analog signal processing to produce polarization maps in real time. When used with a lithium niobate Fabry-Perot etalon or other color filter that can encode spectral information as polarization, the IDID can reveal tiny differences between simultaneous images at two wavelengths.

Miniaturized force/torque sensor for in vivo measurements of tissue characteristics.

PubMed

Hessinger, M; Pilic, T; Werthschutzky, R; Pott, P P

2016-08-01

This paper presents the development of a surgical instrument to measure interaction forces/torques with organic tissue during operation. The focus is on the design progress of the sensor element, consisting of a spoke wheel deformation element with a diameter of 12 mm and eight inhomogeneous doped piezoresistive silicon strain gauges on an integrated full-bridge assembly with an edge length of 500 μm. The silicon chips are contacted to flex-circuits via flip chip and bonded on the substrate with a single component adhesive. A signal processing board with an 18 bit serial A/D converter is integrated into the sensor. The design concept of the handheld surgical sensor device consists of an instrument coupling, the six-axis sensor, a wireless communication interface and battery. The nominal force of the sensing element is 10 N and the nominal torque is 1 N-m in all spatial directions. A first characterization of the force sensor results in a maximal systematic error of 4.92 % and random error of 1.13 %.

3D interconnect metrology in CMS/ITRI

NASA Astrophysics Data System (ADS)

Ku, Y. S.; Shyu, D. M.; Hsu, W. T.; Chang, P. Y.; Chen, Y. C.; Pang, H. L.

2011-05-01

Semiconductor device packaging technology is rapidly advancing, in response to the demand for thinner and smaller electronic devices. Three-dimensional chip/wafer stacking that uses through-silicon vias (TSV) is a key technical focus area, and the continuous development of this novel technology has created a need for non-contact characterization. Many of these challenges are novel to the industry due to the relatively large variety of via sizes and density, and new processes such as wafer thinning and stacked wafer bonding. This paper summarizes the developing metrology that has been used during via-middle & via-last TSV process development at EOL/ITRI. While there is a variety of metrology and inspection applications for 3D interconnect processing, the main topics covered here are via CD/depth measurement, thinned wafer inspection and wafer warpage measurement.

Chip-package nano-structured copper and nickel interconnections with metallic and polymeric bonding interfaces

NASA Astrophysics Data System (ADS)

Aggarwal, Ankur

With the semiconductor industry racing toward a historic transition, nano chips with less than 45 nm features demand I/Os in excess of 20,000 that support computing speed in terabits per second, with multi-core processors aggregately providing highest bandwidth at lowest power. On the other hand, emerging mixed signal systems are driving the need for 3D packaging with embedded active components and ultra-short interconnections. Decreasing I/O pitch together with low cost, high electrical performance and high reliability are the key technological challenges identified by the 2005 International Technology Roadmap for Semiconductors (ITRS). Being able to provide several fold increase in the chip-to-package vertical interconnect density is essential for garnering the true benefits of nanotechnology that will utilize nano-scale devices. Electrical interconnections are multi-functional materials that must also be able to withstand complex, sustained and cyclic thermo-mechanical loads. In addition, the materials must be environmentally-friendly, corrosion resistant, thermally stable over a long time, and resistant to electro-migration. A major challenge is also to develop economic processes that can be integrated into back end of the wafer foundry, i.e. with wafer level packaging. Device-to-system board interconnections are typically accomplished today with either wire bonding or solders. Both of these are incremental and run into either electrical or mechanical barriers as they are extended to higher density of interconnections. Downscaling traditional solder bump interconnect will not satisfy the thermo-mechanical reliability requirements at very fine pitches of the order of 30 microns and less. Alternate interconnection approaches such as compliant interconnects typically require lengthy connections and are therefore limited in terms of electrical properties, although expected to meet the mechanical requirements. A novel chip-package interconnection technology is developed to address the IC packaging requirements beyond the ITRS projections and to introduce innovative design and fabrication concepts that will further advance the performance of the chip, the package, and the system board. The nano-structured interconnect technology simultaneously packages all the ICs intact in wafer form with quantum jump in the number of interconnections with the lowest electrical parasitics. The intrinsic properties of nano materials also enable several orders of magnitude higher interconnect densities with the best mechanical properties for the highest reliability and yet provide higher current and heat transfer densities. Nano-structured interconnects provides the ability to assemble the packaged parts on the system board without the use of underfill materials and to enable advanced analog/digital testing, reliability testing, and burn-in at wafer level. This thesis investigates the electrical and mechanical performance of nanostructured interconnections through modeling and test vehicle fabrication. The analytical models evaluate the performance improvements over solder and compliant interconnections. Test vehicles with nano-interconnections were fabricated using low cost electro-deposition techniques and assembled with various bonding interfaces. Interconnections were fabricated at 200 micron pitch to compare with the existing solder joints and at 50 micron pitch to demonstrate fabrication processes at fine pitches. Experimental and modeling results show that the proposed nano-interconnections could enhance the reliability and potentially meet all the system performance requirements for the emerging micro/nano-systems.

Localized heating and bonding technique for MEMS packaging

NASA Astrophysics Data System (ADS)

Cheng, Yu-Ting

Localized heating and bonding techniques have been developed for hermetic and vacuum packaging of MEMS devices, including silicon-to-glass fusion, silicon-gold eutectic, and silicon-to-glass bonding using PSG, indium, aluminum, and aluminum/silicon alloy as the intermediate layer. Line shaped phosphorus-doped polysilicon or gold films are used as resistive microheaters to provide enough thermal energy for bonding. The bonding processes are conducted in the common environment of room temperature and atmospheric pressure and can achieve bonding strength comparable to the fracture toughness of bulk silicon in less than 10 minutes. About 5 watts of input power is needed for localized bonding which can seal a 500 x 500 mum2 area. The total input power is determined by the thermal properties of bonding materials, including the heat capacity and latent heat. Two important bonding results are obtained: (1) The surface step created by the electrical interconnect line can be planarized by reflowing the metal solder. (2) Small applied pressure, less than 1MPa, for intimate contact reduces mechanical damage to the device substrate. This new class of bonding technology has potential applications for MEMS fabrication and packaging that require low temperature processing at the wafer level, excellent bonding strength and hermetic sealing characteristics. A hermetic package based on localized aluminum/silicon-to-glass bonding has been successfully fabricated. Less than 0.2 MPa contact pressure with 46mA input current for two parallel 3.5mum wide polysilicon on-chip microheaters can create as high as 700°C bonding temperature and achieve a strong and reliable bond in 7.5 minutes. Accelerated testing in an autoclave shows some packages survive more than 450 hours under 3 atm, 100%RH and 128°C. Premature failure has been attributed to some unbonded regions on the failed samples. The bonding yield and reliability have been improved by increasing bonding time and applied pressure. Finally, vacuum encapsulation of folded-beam comb-drive mu-resonators used as pressure monitors has been demonstrated using localized aluminum/silicon-to-glass bonding. With 3.4 watt heating power, ˜0.2MPa applied contact pressure, and 90 minutes wait time before bonding, vacuum encapsulation can be achieved with the same vacuum level as the packaging environment which is about 25 mtorr. Metal coating used as diffusion barrier and a longer wait time before bonding are used to improve the vacuum level of the package. Long-term measurement of the Q of un-annealed vacuum-packaged mu-resonators, illustrates stable operation after 19 weeks.

Multi-wafer bonding technology for the integration of a micromachined Mirau interferometer

NASA Astrophysics Data System (ADS)

Wang, Wei-Shan; Lullin, Justine; Froemel, Joerg; Wiemer, Maik; Bargiel, Sylwester; Passilly, Nicolas; Gorecki, Christophe; Gessner, Thomas

2015-02-01

The paper presents the multi-wafer bonding technology as well as the integration of electrical connection to the zscanner wafer of the micromachined array-type Mirau interferometer. A Mirau interferometer, which is a key-component of optical coherence tomography (OCT) microsystem, consists of a microlens doublet, a MOEMS Z-scanner, a focusadjustment spacer and a beam splitter plate. For the integration of this MOEMS device heterogeneous bonding of Si, glass and SOI wafers is necessary. Previously, most of the existing methods for multilayer wafer bonding require annealing at high temperature, i.e., 1100°C. To be compatible with MEMS devices, bonding of different material stacks at temperatures lower than 400°C has also been investigated. However, if more components are involved, it becomes less effective due to the alignment accuracy or degradation of surface quality of the not-bonded side after each bonding operation. The proposed technology focuses on 3D integration of heterogeneous building blocks, where the assembly process is compatible with the materials of each wafer stack and with position accuracy which fits optical requirement. A demonstrator with up to 5 wafers bonded lower than 400°C is presented and bond interfaces are evaluated. To avoid the complexity of through wafer vias, a design which creates electrical connections along vertical direction by mounting a wafer stack on a flip chip PCB is proposed. The approach, which adopts vertically-stacked wafers along with electrical connection functionality, provides not only a space-effective integration of MOEMS device but also a design where the Mirau stack can be further integrated with other components of the OCT microsystem easily.

A Comparison between Shear Bond Strength of VMK Master Porcelain with Three Base-metal Alloys (Ni-cr-T3, VeraBond, Super Cast) and One Noble Alloy (X-33) in Metal-ceramic Restorations

PubMed Central

Ahmadzadeh, A; Neshati, A; Mousavi, N; Epakchi, S; Dabaghi Tabriz, F; Sarbazi, AH

2013-01-01

Statement of Problem: The increase in the use of metal-ceramic restorations and a high prevalence of porcelain chipping entails introducing an alloy which is more compatible with porcelain and causes a stronger bond between the two. This study is to compare shear bond strength of three base-metal alloys and one noble alloy with the commonly used VMK Master Porcelain. Materials and Method: Three different groups of base-metal alloys (Ni-cr-T3, Super Cast, and VeraBond) and one group of noble alloy (X-33) were selected. Each group consisted of 15 alloy samples. All groups went through the casting process and change from wax pattern into metal disks. The VMK Master Porcelain was then fired on each group. All the specimens were put in the UTM; a shear force was loaded until a fracture occurred and the fracture force was consequently recorded. The data were analyzed by SPSS Version 16 and One-Way ANOVA was run to compare the shear strength between the groups. Furthermore, the groups were compared two-by-two by adopting Tukey test. Results: The findings of this study revealed shear bond strength of Ni-Cr-T3 alloy was higher than the three other alloys (94 MPa or 330 N). Super Cast alloy had the second greatest shear bond strength (80. 87Mpa or 283.87 N). Both VeraBond (69.66 MPa or 245 N) and x-33 alloys (66.53 MPa or 234 N) took the third place. Conclusion: Ni-Cr-T3 with VMK Master Porcelain has the greatest shear bond strength. Therefore, employment of this low-cost alloy is recommended in metal-ceramic restorations. PMID:24724144

Development of low fat potato chips through microwave processing.

PubMed

Joshi, A; Rudra, S G; Sagar, V R; Raigond, P; Dutt, S; Singh, B; Singh, B P

2016-08-01

Since snacks high in fats are known to be a significant source of fat and energy intake, these have been put in high dietary restraint category. Therefore, an attempt was made to process potato chips through microwave processing without incorporation of any oil in potato chips. Microwave processing of potato chips was done using microwave power varying from 180 to 600 W using constant sample size. Among eleven different drying models, Parabolic model was found to be the best fit through non-linear regression analysis to illustrate drying kinetics of potato chips. The structural, textural and colour attributes of microwaved potato chips were similar to commercial fried potato chips. It was found that at 600 W after 2.5-3.0 min of processing, potato chips gained the fracturability and crispiness index as that of commercial fried chips. Microwave processing was found suitable for processing of potato chips with low fat content (~3.09 vs 35.5 % in commercial preparation) and with acceptable sensory scores (≥7.6 on 9.0 point on hedonic scale vs 8.0 of control preparation).

Design and Fabrication of an Implantable Cortical Semiconductor Integrated Circuit Electrode Array

DTIC Science & Technology

1990-12-01

25 Array Pads....................25 Polyimide ....................26 III. METHODOLOGY.........................27 Brain Chip Electronics...38 Ionic Permeation. .................. 38 Polyimide . ................... 38 Implantation. .................... 39 Wire Bonding...53 Pad Sensitivity ................. 53 Ionic Permeat:.on. .................. 54 Polyimide . ................... 54 Implantation

DNA decorated carbon nanotube sensors on CMOS circuitry for environmental monitoring

NASA Astrophysics Data System (ADS)

Liu, Yu; Chen, Chia-Ling; Agarwal, V.; Li, Xinghui; Sonkusale, S.; Dokmeci, Mehmet R.; Wang, Ming L.

2010-04-01

Single-walled carbon nanotubes (SWNTs) with their large surface area, high aspect ratio are one of the novel materials which have numerous attractive features amenable for high sensitivity sensors. Several nanotube based sensors including, gas, chemical and biosensors have been demonstrated. Moreover, most of these sensors require off chip components to detect the variations in the signals making them complicated and hard to commercialize. Here we present a novel complementary metal oxide semiconductor (CMOS) integrated carbon nanotube sensors for portable high sensitivity chemical sensing applications. Multiple zincation steps have been developed to ascertain proper electrical connectivity between the carbon nanotubes and the foundry made CMOS circuitry. The SWNTs have been integrated onto (CMOS) circuitry as the feedback resistor of a Miller compensated operational amplifier utilizing low temperature Dielectrophoretic (DEP) assembly process which has been tailored to be compatible with the post-CMOS integration at the die level. Building nanotube sensors directly on commercial CMOS circuitry allows single chip solutions eliminating the need for long parasitic lines and numerous wire bonds. The carbon nanotube sensors realized on CMOS circuitry show strong response to various vapors including Dimethyl methylphosphonate and Dinitrotoluene. The remarkable set of attributes of the SWNTs realized on CMOS electronic chips provides an attractive platform for high sensitivity portable nanotube based bio and chemical sensors.

A battery-free multichannel digital neural/EMG telemetry system for flying insects.

PubMed

Thomas, Stewart J; Harrison, Reid R; Leonardo, Anthony; Reynolds, Matthew S

2012-10-01

This paper presents a digital neural/EMG telemetry system small enough and lightweight enough to permit recording from insects in flight. It has a measured flight package mass of only 38 mg. This system includes a single-chip telemetry integrated circuit (IC) employing RF power harvesting for battery-free operation, with communication via modulated backscatter in the UHF (902-928 MHz) band. An on-chip 11-bit ADC digitizes 10 neural channels with a sampling rate of 26.1 kSps and 4 EMG channels at 1.63 kSps, and telemeters this data wirelessly to a base station. The companion base station transceiver includes an RF transmitter of +36 dBm (4 W) output power to wirelessly power the telemetry IC, and a digital receiver with a sensitivity of -70 dBm for 10⁻⁵ BER at 5.0 Mbps to receive the data stream from the telemetry IC. The telemetry chip was fabricated in a commercial 0.35 μ m 4M1P (4 metal, 1 poly) CMOS process. The die measures 2.36 × 1.88 mm, is 250 μm thick, and is wire bonded into a flex circuit assembly measuring 4.6 × 6.8 mm.

Bench-Top Fabrication of an All-PDMS Microfluidic Electrochemical Cell Sensor Integrating Micro/Nanostructured Electrodes.

PubMed

Saem, Sokunthearath; Zhu, Yujie; Luu, Helen; Moran-Mirabal, Jose

2017-03-31

In recent years, efforts in the development of lab-on-a-chip (LoC) devices for point-of-care (PoC) applications have increased to bring affordable, portable, and sensitive diagnostics to the patients' bedside. To reach this goal, research has shifted from using traditional microfabrication methods to more versatile, rapid, and low-cost options. This work focuses on the benchtop fabrication of a highly sensitive, fully transparent, and flexible poly (dimethylsiloxane) (PDMS) microfluidic (μF) electrochemical cell sensor. The μF device encapsulates 3D structured gold and platinum electrodes, fabricated using a shape-memory polymer shrinking method, which are used to set up an on-chip electrochemical cell. The PDMS to PDMS-structured electrode bonding protocol to fabricate the μF chip was optimized and found to have sufficient bond strength to withstand up to 100 mL/min flow rates. The sensing capabilities of the on-chip electrochemical cell were demonstrated by using cyclic voltammetry to monitor the adhesion of murine 3T3 fibroblasts in the presence of a redox reporter. The charge transfer across the working electrode was reduced upon cell adhesion, which was used as the detection mechanism, and allowed the detection of as few as 24 cells. The effective utilization of simple and low cost bench-top fabrication methods could accelerate the prototyping and development of LoC technologies and bring PoC diagnostics and personalized medicine to the patients' bedside.

Bench-Top Fabrication of an All-PDMS Microfluidic Electrochemical Cell Sensor Integrating Micro/Nanostructured Electrodes

PubMed Central

Saem, Sokunthearath; Zhu, Yujie; Luu, Helen; Moran-Mirabal, Jose

2017-01-01

In recent years, efforts in the development of lab-on-a-chip (LoC) devices for point-of-care (PoC) applications have increased to bring affordable, portable, and sensitive diagnostics to the patients’ bedside. To reach this goal, research has shifted from using traditional microfabrication methods to more versatile, rapid, and low-cost options. This work focuses on the benchtop fabrication of a highly sensitive, fully transparent, and flexible poly (dimethylsiloxane) (PDMS) microfluidic (μF) electrochemical cell sensor. The μF device encapsulates 3D structured gold and platinum electrodes, fabricated using a shape-memory polymer shrinking method, which are used to set up an on-chip electrochemical cell. The PDMS to PDMS-structured electrode bonding protocol to fabricate the μF chip was optimized and found to have sufficient bond strength to withstand up to 100 mL/min flow rates. The sensing capabilities of the on-chip electrochemical cell were demonstrated by using cyclic voltammetry to monitor the adhesion of murine 3T3 fibroblasts in the presence of a redox reporter. The charge transfer across the working electrode was reduced upon cell adhesion, which was used as the detection mechanism, and allowed the detection of as few as 24 cells. The effective utilization of simple and low cost bench-top fabrication methods could accelerate the prototyping and development of LoC technologies and bring PoC diagnostics and personalized medicine to the patients’ bedside. PMID:28362329

Flow lithography in ultraviolet-curable polydimethylsiloxane microfluidic chips

PubMed Central

Kim, Junbeom; An, Heseong; Seo, Yoojin; Jung, Youngmee; Lee, Jong Suk; Bong, Ki Wan

2017-01-01

Flow Lithography (FL) is the technique used for the synthesis of hydrogel microparticles with various complex shapes and distinct chemical compositions by combining microfluidics with photolithography. Although polydimethylsiloxane (PDMS) has been used most widely as almost the sole material for FL, PDMS microfluidic chips have limitations: (1) undesired shrinkage due to the thermal expansion of masters used for replica molding and (2) interfacial delamination between two thermally cured PDMS layers. Here, we propose the utilization of ultraviolet (UV)-curable PDMS (X-34-4184) for FL as an excellent alternative material of the conventional PDMS. Our proposed utilization of the UV-curable PDMS offers three key advantages, observed in our study: (1) UV-curable PDMS exhibited almost the same oxygen permeability as the conventional PDMS. (2) The almost complete absence of shrinkage facilitated the fabrication of more precise reverse duplication of microstructures. (3) UV-cured PDMS microfluidic chips were capable of much stronger interfacial bonding so that the burst pressure increased to ∼0.9 MPa. Owing to these benefits, we demonstrated a substantial improvement of productivity in synthesizing polyethylene glycol diacrylate microparticles via stop flow lithography, by applying a flow time (40 ms) an order of magnitude shorter. Our results suggest that UV-cured PDMS chips can be used as a general platform for various types of flow lithography and also be employed readily in other applications where very precise replication of structures on micro- or sub-micrometer scales and/or strong interfacial bonding are desirable. PMID:28469763

Microfabricated electrochemical sensors for combustion applications

NASA Astrophysics Data System (ADS)

Vulcano Rossi, Vitor A.; Mullen, Max R.; Karker, Nicholas A.; Zhao, Zhouying; Kowarz, Marek W.; Dutta, Prabir K.; Carpenter, Michael A.

2015-05-01

A new design for the miniaturization of an existing oxygen sensor is proposed based on the application of silicon microfabrication technologies to a cm sized O2 sensor demonstrated by Argonne National Laboratory and The Ohio State University which seals a metal/metal oxide within the structure to provide an integrated oxygen reference. The structural and processing changes suggested will result in a novel MEMS-based device meeting the semiconductor industry standards for cost efficiency and mass production. The MEMS design requires thin film depositions to create a YSZ membrane, palladium oxide reference and platinum electrodes. Pt electrodes are studied under operational conditions ensuring film conductivity over prolonged usage. SEM imaging confirms void formation after extended tests, consistent with the literature. Furthermore, hydrophilic bonding of pairs of silicon die samples containing the YSZ membrane and palladium oxide is discussed in order to create hermetic sealed cavities for oxygen reference. The introduction of tensile Si3N4 films to the backside of the silicon die generates bowing of the chips, compromising bond quality. This effect is controlled through the application of pressure during the initial bonding stages. In addition, KOH etching of the bonded die samples is discussed, and a YSZ membrane that survives the etching step is characterized by Raman spectroscopy.

An integrated circuit with transmit beamforming flip-chip bonded to a 2-D CMUT array for 3-D ultrasound imaging.

PubMed

Wygant, Ira O; Jamal, Nafis S; Lee, Hyunjoo J; Nikoozadeh, Amin; Oralkan, Omer; Karaman, Mustafa; Khuri-Yakub, Butrus T

2009-10-01

State-of-the-art 3-D medical ultrasound imaging requires transmitting and receiving ultrasound using a 2-D array of ultrasound transducers with hundreds or thousands of elements. A tight combination of the transducer array with integrated circuitry eliminates bulky cables connecting the elements of the transducer array to a separate system of electronics. Furthermore, preamplifiers located close to the array can lead to improved receive sensitivity. A combined IC and transducer array can lead to a portable, high-performance, and inexpensive 3-D ultrasound imaging system. This paper presents an IC flip-chip bonded to a 16 x 16-element capacitive micromachined ultrasonic transducer (CMUT) array for 3-D ultrasound imaging. The IC includes a transmit beamformer that generates 25-V unipolar pulses with programmable focusing delays to 224 of the 256 transducer elements. One-shot circuits allow adjustment of the pulse widths for different ultrasound transducer center frequencies. For receiving reflected ultrasound signals, the IC uses the 32-elements along the array diagonals. The IC provides each receiving element with a low-noise 25-MHz-bandwidth transimpedance amplifier. Using a field-programmable gate array (FPGA) clocked at 100 MHz to operate the IC, the IC generated properly timed transmit pulses with 5-ns accuracy. With the IC flip-chip bonded to a CMUT array, we show that the IC can produce steered and focused ultrasound beams. We present 2-D and 3-D images of a wire phantom and 2-D orthogonal cross-sectional images (Bscans) of a latex heart phantom.

Amplifier Module for 260-GHz Band Using Quartz Waveguide Transitions

NASA Technical Reports Server (NTRS)

Padmanabhan, Sharmila; Fung, King Man; Kangaslahti, Pekka P.; Peralta, Alejandro; Soria, Mary M.; Pukala, David M.; Sin, Seth; Samoska, Lorene A.; Sarkozy, Stephen; Lai, Richard

2012-01-01

Packaging of MMIC LNA (monolithic microwave integrated circuit low-noise amplifier) chips at frequencies over 200 GHz has always been problematic due to the high loss in the transition between the MMIC chip and the waveguide medium in which the chip will typically be used. In addition, above 200 GHz, wire-bond inductance between the LNA and the waveguide can severely limit the RF matching and bandwidth of the final waveguide amplifier module. This work resulted in the development of a low-loss quartz waveguide transition that includes a capacitive transmission line between the MMIC and the waveguide probe element. This capacitive transmission line tunes out the wirebond inductance (where the wire-bond is required to bond between the MMIC and the probe element). This inductance can severely limit the RF matching and bandwidth of the final waveguide amplifier module. The amplifier module consists of a quartz E-plane waveguide probe transition, a short capacitive tuning element, a short wire-bond to the MMIC, and the MMIC LNA. The output structure is similar, with a short wire-bond at the output of the MMIC, a quartz E-plane waveguide probe transition, and the output waveguide. The quartz probe element is made of 3-mil quartz, which is the thinnest commercially available material. The waveguide band used is WR4, from 170 to 260 GHz. This new transition and block design is an improvement over prior art because it provides for better RF matching, and will likely yield lower loss and better noise figure. The development of high-performance, low-noise amplifiers in the 180-to- 700-GHz range has applications for future earth science and planetary instruments with low power and volume, and astrophysics array instruments for molecular spectroscopy. This frequency band, while suitable for homeland security and commercial applications (such as millimeter-wave imaging, hidden weapons detection, crowd scanning, airport security, and communications), also has applications to future NASA missions. The Global Atmospheric Composition Mission (GACM) in the NRC Decadel Survey will need low-noise amplifiers with extremely low noise temperatures, either at room temperature or for cryogenic applications, for atmospheric remote sensing.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Murray, E.; Floether, F. F.; Cavendish Laboratory, University of Cambridge, J.J. Thomson Avenue, Cambridge CB3 0HE

Fundamental to integrated photonic quantum computing is an on-chip method for routing and modulating quantum light emission. We demonstrate a hybrid integration platform consisting of arbitrarily designed waveguide circuits and single-photon sources. InAs quantum dots (QD) embedded in GaAs are bonded to a SiON waveguide chip such that the QD emission is coupled to the waveguide mode. The waveguides are SiON core embedded in a SiO{sub 2} cladding. A tuneable Mach Zehnder interferometer (MZI) modulates the emission between two output ports and can act as a path-encoded qubit preparation device. The single-photon nature of the emission was verified using themore » on-chip MZI as a beamsplitter in a Hanbury Brown and Twiss measurement.« less

Massively Parallel Rogue Cell Detection Using Serial Time-Encoded Amplified Microscopy of Inertially Ordered Cells in High-Throughput Flow

DTIC Science & Technology

2012-08-01

techniques and STEAM imager. It couples the high-speed capability of the STEAM imager and differential phase contrast imaging of DIC / Nomarski microscopy...On 10 TPE chips, we obtained 9 homogenous and strong bonds, the failed bond being due to operator error and presence of air bubbles in the TPE...instruments, structural dynamics, and microelectromechanical systems (MEMS) via laser-scanning surface vibrometry , and observation of biomechanical motility

Application and Optimization of Stiffness Abruption Structures for Pressure Sensors with High Sensitivity and Anti-Overload Ability

PubMed Central

Xu, Tingzhong; Lu, Dejiang; Zhao, Libo; Jiang, Zhuangde; Wang, Hongyan; Guo, Xin; Li, Zhikang; Zhou, Xiangyang; Zhao, Yulong

2017-01-01

The influence of diaphragm bending stiffness distribution on the stress concentration characteristics of a pressure sensing chip had been analyzed and discussed systematically. According to the analysis, a novel peninsula-island-based diaphragm structure was presented and applied to two differenet diaphragm shapes as sensing chips for pressure sensors. By well-designed bending stiffness distribution of the diaphragm, the elastic potential energy induced by diaphragm deformation was concentrated above the gap position, which remarkably increased the sensitivity of the sensing chip. An optimization method and the distribution pattern of the peninsula-island based diaphragm structure were also discussed. Two kinds of sensing chips combined with the peninsula-island structures distributing along the side edge and diagonal directions of rectangular diaphragm were fabricated and analyzed. By bonding the sensing chips with anti-overload glass bases, these two sensing chips were demonstrated by testing to achieve not only high sensitivity, but also good anti-overload ability. The experimental results showed that the proposed structures had the potential to measure ultra-low absolute pressures with high sensitivity and good anti-overload ability in an atmospheric environment. PMID:28846599

High-Temperature High-Power Packaging Techniques for HEV Traction Applications

DOE Office of Scientific and Technical Information (OSTI.GOV)

Elshabini, Aicha; Barlow, Fred D.

A key issue associated with the wider adoption of hybrid-electric vehicles (HEV) and plug in hybrid-electric vehicles (PHEV) is the implementation of the power electronic systems that are required in these products. One of the primary industry goals is the reduction in the price of these vehicles relative to the cost of traditional gasoline powered vehicles. Today these systems, such as the Prius, utilize one coolant loop for the engine at approximately 100 C coolant temperatures, and a second coolant loop for the inverter at 65 C. One way in which significant cost reduction of these systems could be achievedmore » is through the use of a single coolant loop for both the power electronics as well as the internal combustion engine (ICE). This change in coolant temperature significantly increases the junction temperatures of the devices and creates a number of challenges for both device fabrication and the assembly of these devices into inverters and converters for HEV and PHEV applications. Traditional power modules and the state-of-the-art inverters in the current HEV products, are based on chip and wire assembly and direct bond copper (DBC) on ceramic substrates. While a shift to silicon carbide (SiC) devices from silicon (Si) devices would allow the higher operating temperatures required for a single coolant loop, it also creates a number of challenges for the assembly of these devices into power inverters. While this traditional packaging technology can be extended to higher temperatures, the key issues are the substrate material and conductor stability, die bonding material, wire bonds, and bond metallurgy reliability as well as encapsulation materials that are stable at high operating temperatures. The larger temperature differential during power cycling, which would be created by higher coolant temperatures, places tremendous stress on traditional aluminum wire bonds that are used to interconnect power devices. Selection of the bond metallurgy and wire bond geometry can play a key role in mitigating this stress. An alternative solution would be to eliminate the wire bonds completely through a fundamentally different method of forming a reliable top side interconnect. Similarly, the solders used in most power modules exhibit too low of a liquidus to be viable solutions for maximum junction temperatures of 200 C. Commonly used encapsulation materials, such as silicone gels, also suffer from an inability to operate at 200 C for extended periods of time. Possible solutions to these problems exist in most cases but require changes to the traditional manufacturing process used in these modules. In addition, a number of emerging technologies such as Si nitride, flip-chip assembly methods, and the elimination of base-plates would allow reliable module development for operation of HEV and PHEV inverters at elevated junction temperatures.« less

Ultra-wideband WDM VCSEL arrays by lateral heterogeneous integration

NASA Astrophysics Data System (ADS)

Geske, Jon

Advancements in heterogeneous integration are a driving factor in the development of evermore sophisticated and functional electronic and photonic devices. Such advancements will merge the optical and electronic capabilities of different material systems onto a common integrated device platform. This thesis presents a new lateral heterogeneous integration technology called nonplanar wafer bonding. The technique is capable of integrating multiple dissimilar semiconductor device structures on the surface of a substrate in a single wafer bond step, leaving different integrated device structures adjacent to each other on the wafer surface. Material characterization and numerical simulations confirm that the material quality is not compromised during the process. Nonplanar wafer bonding is used to fabricate ultra-wideband wavelength division multiplexed (WDM) vertical-cavity surface-emitting laser (VCSEL) arrays. The optically-pumped VCSEL arrays span 140 nm from 1470 to 1610 nm, a record wavelength span for devices operating in this wavelength range. The array uses eight wavelength channels to span the 140 nm with all channels separated by precisely 20 nm. All channels in the array operate single mode to at least 65°C with output power uniformity of +/- 1 dB. The ultra-wideband WDM VCSEL arrays are a significant first step toward the development of a single-chip source for optical networks based on coarse WDM (CWDM), a low-cost alternative to traditional dense WDM. The CWDM VCSEL arrays make use of fully-oxidized distributed Bragg reflectors (DBRs) to provide the wideband reflectivity required for optical feedback and lasing across 140 rim. In addition, a novel optically-pumped active region design is presented. It is demonstrated, with an analytical model and experimental results, that the new active-region design significantly improves the carrier uniformity in the quantum wells and results in a 50% lasing threshold reduction and a 20°C improvement in the peak operating temperature of the devices. This thesis investigates the integration and fabrication technologies required to fabricate ultra-wideband WDM VCSEL arrays. The complete device design and fabrication process is presented along with actual device results from completed CWDM VCSEL arrays. Future recommendations for improvements are presented, along with a roadmap toward a final electrically-pumped single-chip source for CWDM applications.

Non-destructive residual pressure self-measurement method for the sensing chip of optical Fabry-Perot pressure sensor.

PubMed

Wang, Xue; Wang, Shuang; Jiang, Junfeng; Liu, Kun; Zhang, Xuezhi; Xiao, Mengnan; Xiao, Hai; Liu, Tiegen

2017-12-11

We introduce a simple residual pressure self-measurement method for the Fabry-Perot (F-P) cavity of optical MEMS pressure sensor. No extra installation is required and the structure of the sensor is unchanged. In the method, the relationship between residual pressure and external pressure under the same diaphragm deflection condition at different temperatures is analyzed by using the deflection formula of the circular plate with clamped edges and the ideal gas law. Based on this, the residual pressure under the flat condition can be obtained by pressure scanning process and calculation process. We carried out the experiment to compare the residual pressures of two batches MEMS sensors fabricated by two kinds of bonding process. The measurement result indicates that our approach is reliable enough for the measurement.

Probability of conductive bond formation in a percolating network of nanowires with fusible tips

NASA Astrophysics Data System (ADS)

Rykaczewski, Konrad; Wang, Robert Y.

2018-03-01

Meeting the heat dissipation demands of microelectronic devices requires development of polymeric composites with high thermal conductivity. This property is drastically improved by percolation networks of metallic filler particles that have their particle-to-particle contact resistances reduced through thermal or electromagnetic fusing. However, composites with fused metallic fillers are electrically conductive, which prevents their application within the chip-board and the inter-chip gaps. Here, we propose that electrically insulating composites for these purposes can be achieved by the application of fusible metallic coatings to the tips of nanowires with thermally conductive but electrically insulating cores. We derive analytical models that relate the ratio of the coated and total nanowire lengths to the fraction of fused, and thus conductive, bonds within percolating networks of these structures. We consider two types of materials for these fusible coatings. First, we consider silver-like coatings, which form only conductive bonds when contacting the silver-like coating of another nanowire. Second, we consider liquid metal-like coatings, which form conductive bonds regardless of whether they contact a coated or an uncoated segment of another nanowire. These models were validated using Monte Carlo simulations, which also revealed that electrical short-circuiting is highly unlikely until most of the wire is coated. Furthermore, we demonstrate that switching the tip coating from silver- to liquid metal-like materials can double the fraction of conductive bonds. Consequently, this work provides motivation to develop scalable methods for fabrication of the hybrid liquid-coated nanowires, whose dispersion in a polymer matrix is predicted to yield highly thermally conductive but electrically insulating composites.

Design and Construction of a Multi-Organ Microfluidic Chip Mimicking the in vivo Microenvironment of Lung Cancer Metastasis.

PubMed

Xu, Zhiyun; Li, Encheng; Guo, Zhe; Yu, Ruofei; Hao, Hualong; Xu, Yitong; Sun, Zhao; Li, Xiancheng; Lyu, Jianxin; Wang, Qi

2016-10-05

Metastasis is a complex pathophysiological process. As the main cause of cancer mortality in humans it represents a serious challenge to both basic researchers and clinicians. Here we report the design and construction of a multi-organ microfluidic chip that closely mimics the in vivo microenvironment of lung cancer metastasis. This multi-organs-on-a-chip includes an upstream "lung" and three downstream "distant organs", with three polydimethylsiloxane (PDMS) layers and two thin PDMS microporous membranes bonded to form three parallel microchannels. Bronchial epithelial, lung cancer, microvascular endothelial, mononuclear, and fibroblast cells were grown separated by the biomembrane in upstream "lung", while astrocytes, osteocytes, and hepatocytes were grown in distant chambers, to mimic lung cancer cell metastasis to the brain, bone, and liver. After culture in this system, lung cancer cells formed a "tumor mass", showed epithelial-mesenchymal transition (with altered expression of E-cadherin, N-cadherin, Snail1, and Snail2) and invasive capacity. A549 cells co-cultured with astrocytes overexpressed CXCR4 protein, indicating damage of astrocytes after cancer cell metastasis to the brain. Osteocytes overexpressed RANKL protein indicates damage of osteocytes after cancer cell metastasis to the bone, and hepatocytes overexpressed AFP protein indicates damage to hepatocytes after cancer cell metastasis to the liver. Finally, in vivo imaging of cancer growth and metastasis in a nude mice model validated the performance of metastasis in the organs-on-chip system. This system provides a useful tool to mimic the in vivo microenvironment of cancer metastasis and to investigate cell-cell interactions during metastasis.

Low-Yellowing Phosphor-in-Glass for High-Power Chip-on-board White LEDs by Optimizing a Low-Melting Sn-P-F-O Glass Matrix.

PubMed

Yoon, Hee Chang; Yoshihiro, Kouhara; Yoo, Heeyeon; Lee, Seung Woo; Oh, Ji Hye; Do, Young Rag

2018-05-09

We introduce a low-melting-point (MP) Sn-P-F-O glass ceramic material into the phosphor-in-glass (PIG) material to realize an 'on-chip' chip-on-board (COB) type of phosphor-converted (pc) white light-emitting diode (WLED) with green (BaSr) 2 SiO 4 :Eu 2+ and red (SrCa)AlSiN 3 :Eu 2+ (SCASN) phosphors. The optimum Sn-P-F-O-based ceramic components can be sintered into the glass phase with a facile one-step heating process at 285 °C for 1 min. Specifically, these soft-fabrication conditions can be optimized to minimize the degradation of the luminescent properties of the red SCASN phosphor as well as the green silicate phosphor in PIG-based white COB-type pc-LEDs owing to the low thermal loss of the phosphors at low fabrication temperatures below 300 °C. Moreover, the constituents of the COB package, in this case the wire bonding and plastic exterior, can be preserved simultaneously from thermal damage. That is, the low sintering temperature of the glass ceramic encapsulant is a very important factor to realize excellent optical qualities of white COB LEDs. The optical performances of low-MP Sn-P-F-O-based PIG on-chip COB-type pc-WLEDs exhibit low yellowing phenomena, good luminous efficacy of 70.9-86.0 lm/W, excellent color rendering index of 94-97 with correlated color temperatures from 2700 to 10000 K, and good long-term stability.

Two different ways for waveguides and optoelectronics components on top of C-MOS

NASA Astrophysics Data System (ADS)

Fedeli, J. M.; Jeannot, S.; Kostrzewa, M.; Di Cioccio, L.; Jousseaume, V.; Orobtchouk, R.; Maury, P.; Zussy, M.

2006-02-01

While fabrication of photonic components at the wafer level is a long standing goal of integrated optics, new applications such as optical interconnects are introducing new challenges for waveguides and optoelectronic component fabrication. Indeed, global interconnects are expected to face severe limitations in the near future. To face this problem, optical links on top of a CMOS circuits could be an alternative. The critical points to perform an optical link on a chip are firstly the realization of compact passive optical distribution and secondly the report of optoelectronic components for the sources and detectors. This paper presents two different approaches for the integration of both waveguides and optoelectronic components. In a first "total bonding" approach, waveguides have been elaborated using classical "Silicon On Insulators" technology and then reported using molecular bonding on top off Si wafers. The S0I substrate was then chemically etched, after what InP dies were moleculary bonded on top of the waveguides. With this approach, optical components with low loses and a good equilibrium are demonsrated. Using molecular bonding, InP dies were reported with no degradation of the optoelectronic properties of the films. In a second approach, using PECVD silicon nitride or amorphous silicon coupled to PECVD silicon oxide, basic optical components are demonstrated. This low temperature technology is compatible with a microelectronic Back End process, allowing an integration of the waveguides directly on top of CMOS circuits. InP dies can then be bonded on top of the waveguides.

Design methodology: edgeless 3D ASICs with complex in-pixel processing for pixel detectors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Fahim Farah, Fahim Farah; Deptuch, Grzegorz W.; Hoff, James R.

The design methodology for the development of 3D integrated edgeless pixel detectors with in-pixel processing using Electronic Design Automation (EDA) tools is presented. A large area 3 tier 3D detector with one sensor layer and two ASIC layers containing one analog and one digital tier, is built for x-ray photon time of arrival measurement and imaging. A full custom analog pixel is 65μm x 65μm. It is connected to a sensor pixel of the same size on one side, and on the other side it has approximately 40 connections to the digital pixel. A 32 x 32 edgeless array withoutmore » any peripheral functional blocks constitutes a sub-chip. The sub-chip is an indivisible unit, which is further arranged in a 6 x 6 array to create the entire 1.248cm x 1.248cm ASIC. Each chip has 720 bump-bond I/O connections, on the back of the digital tier to the ceramic PCB. All the analog tier power and biasing is conveyed through the digital tier from the PCB. The assembly has no peripheral functional blocks, and hence the active area extends to the edge of the detector. This was achieved by using a few flavors of almost identical analog pixels (minimal variation in layout) to allow for peripheral biasing blocks to be placed within pixels. The 1024 pixels within a digital sub-chip array have a variety of full custom, semi-custom and automated timing driven functional blocks placed together. The methodology uses a modified mixed-mode on-top digital implementation flow to not only harness the tool efficiency for timing and floor-planning but also to maintain designer control over compact parasitically aware layout. The methodology uses the Cadence design platform, however it is not limited to this tool.« less

Design methodology: edgeless 3D ASICs with complex in-pixel processing for pixel detectors

NASA Astrophysics Data System (ADS)

Fahim, Farah; Deptuch, Grzegorz W.; Hoff, James R.; Mohseni, Hooman

2015-08-01

The design methodology for the development of 3D integrated edgeless pixel detectors with in-pixel processing using Electronic Design Automation (EDA) tools is presented. A large area 3 tier 3D detector with one sensor layer and two ASIC layers containing one analog and one digital tier, is built for x-ray photon time of arrival measurement and imaging. A full custom analog pixel is 65μm x 65μm. It is connected to a sensor pixel of the same size on one side, and on the other side it has approximately 40 connections to the digital pixel. A 32 x 32 edgeless array without any peripheral functional blocks constitutes a sub-chip. The sub-chip is an indivisible unit, which is further arranged in a 6 x 6 array to create the entire 1.248cm x 1.248cm ASIC. Each chip has 720 bump-bond I/O connections, on the back of the digital tier to the ceramic PCB. All the analog tier power and biasing is conveyed through the digital tier from the PCB. The assembly has no peripheral functional blocks, and hence the active area extends to the edge of the detector. This was achieved by using a few flavors of almost identical analog pixels (minimal variation in layout) to allow for peripheral biasing blocks to be placed within pixels. The 1024 pixels within a digital sub-chip array have a variety of full custom, semi-custom and automated timing driven functional blocks placed together. The methodology uses a modified mixed-mode on-top digital implementation flow to not only harness the tool efficiency for timing and floor-planning but also to maintain designer control over compact parasitically aware layout. The methodology uses the Cadence design platform, however it is not limited to this tool.

Capillary-Driven Microfluidic Chips for Miniaturized Immunoassays: Efficient Fabrication and Sealing of Chips Using a "Chip-Olate" Process.

PubMed

Temiz, Yuksel; Delamarche, Emmanuel

2017-01-01

The fabrication of silicon-based microfluidic chips is invaluable in supporting the development of many microfluidic concepts for research in the life sciences and in vitro diagnostic applications such as the realization of miniaturized immunoassays using capillary-driven chips. While being extremely abundant, the literature covering microfluidic chip fabrication and assay development might not have addressed properly the challenge of fabricating microfluidic chips on a wafer level or the need for dicing wafers to release chips that need then to be further processed, cleaned, rinsed, and dried one by one. Here, we describe the "chip-olate" process wherein microfluidic structures are formed on a silicon wafer, followed by partial dicing, cleaning, and drying steps. Then, integration of reagents (if any) can be done, followed by lamination of a sealing cover. Breaking by hand the partially diced wafer yields individual chips ready for use.

High-speed receiver based on waveguide germanium photodetector wire-bonded to 90nm SOI CMOS amplifier.

PubMed

Pan, Huapu; Assefa, Solomon; Green, William M J; Kuchta, Daniel M; Schow, Clint L; Rylyakov, Alexander V; Lee, Benjamin G; Baks, Christian W; Shank, Steven M; Vlasov, Yurii A

2012-07-30

The performance of a receiver based on a CMOS amplifier circuit designed with 90nm ground rules wire-bonded to a waveguide germanium photodetector is characterized at data rates up to 40Gbps. Both chips were fabricated through the IBM Silicon CMOS Integrated Nanophotonics process on specialty photonics-enabled SOI wafers. At the data rate of 28Gbps which is relevant to the new generation of optical interconnects, a sensitivity of -7.3dBm average optical power is demonstrated with 3.4pJ/bit power-efficiency and 0.6UI horizontal eye opening at a bit-error-rate of 10(-12). The receiver operates error-free (bit-error-rate < 10(-12)) up to 40Gbps with optimized power supply settings demonstrating an energy efficiency of 1.4pJ/bit and 4pJ/bit at data rates of 32Gbps and 40Gbps, respectively, with an average optical power of -0.8dBm.

Suspended liquid subtractive lithography: printing three dimensional channels directly into uncured PDMS

NASA Astrophysics Data System (ADS)

Helmer, D.; Voigt, A.; Wagner, S.; Keller, N.; Sachsenheimer, K.; Kotz, F.; Nargang, T. M.; Rapp, B. E.

2018-02-01

Polydimethylsiloxane (PDMS) is one of the most widely used polymers for the generation of microfluidic chips. The standard procedures of soft lithography require the formation of a new master structure for every design which is timeconsuming and expensive. All channel generated by soft lithography need to be consecutively sealed by bonding which is a process that can proof to be hard to control. Channel cross-sections are largely restricted to squares or flat-topped designs and the generation of truly three-dimensional designs is not straightforward. Here we present Suspended Liquid Subtractive Lithography (SLSL) a method for generating microfluidic channels of nearly arbitrary three-dimensional structures in PDMS that do not require master formation or bonding and give circular channel cross sections which are especially interesting for mimicking in vivo environments. In SLSL, an immiscible liquid is introduced into the uncured PDMS by a capillary mounted on a 3D printer head. The liquid forms continuous "threads" inside the matrix thus creating void suspended channel structures.

Analysis of biological time-lapse microscopic experiment from the point of view of the information theory.

PubMed

Štys, Dalibor; Urban, Jan; Vaněk, Jan; Císař, Petr

2011-06-01

We report objective analysis of information in the microscopic image of the cell monolayer. The process of transfer of information about the cell by the microscope is analyzed in terms of the classical Shannon information transfer scheme. The information source is the biological object, the information transfer channel is the whole microscope including the camera chip. The destination is the model of biological system. The information contribution is analyzed as information carried by a point to overall information in the image. Subsequently we obtain information reflection of the biological object. This is transformed in the biological model which, in information terminology, is the destination. This, we propose, should be constructed as state transitions in individual cells modulated by information bonds between the cells. We show examples of detected cell states in multidimensional state space. This space is reflected as colour channel intensity phenomenological state space. We have also observed information bonds and show examples of them.

Analysis of biological time-lapse microscopic experiment from the point of view of the information theory.

PubMed

Stys, Dalibor; Urban, Jan; Vanek, Jan; Císar, Petr

2010-07-01

We report objective analysis of information in the microscopic image of the cell monolayer. The process of transfer of information about the cell by the microscope is analyzed in terms of the classical Shannon information transfer scheme. The information source is the biological object, the information transfer channel is the whole microscope including the camera chip. The destination is the model of biological system. The information contribution is analyzed as information carried by a point to overall information in the image. Subsequently we obtain information reflection of the biological object. This is transformed in the biological model which, in information terminology, is the destination. This, we propose, should be constructed as state transitions in individual cells modulated by information bonds between the cells. We show examples of detected cell states in multidimensional state space reflected in space an colour channel intensity phenomenological state space. We have also observed information bonds and show examples of them. Copyright 2010 Elsevier Ltd. All rights reserved.

Fully packed capillary electrochromatographic microchip with self-assembly colloidal silica beads.

PubMed

Park, Jongman; Lee, Dami; Kim, Won; Horiike, Shigeyoshi; Nishimoto, Takahiro; Lee, Se Hwan; Ahn, Chong H

2007-04-15

A fully packed capillary electrochromatographic (CEC) microchip showing improved solution and chip handling was developed. Microchannels for the CEC microchip were patterned on a cyclic olefin copolymer substrate by injection molding and packed fully with 0.8-microm monodisperse colloidal silica beads utilizing a self-assembly packing technique. The silica packed chip substrate was covered and thermally press-bonded. After fabrication, the chip was filled with buffer solution by self-priming capillary action. The self-assembly packing at each channel served as a built-in nanofilter allowing quick loading of samples and running buffer solution without filtration. Because of a large surface area-to-volume ratio of the silica packing, reproducible control of electroosmotic flow was possible without leveling of the solutions in the reservoirs resulting 1.3% rsd in migration rate. The capillary electrophoretic separation characteristics of the chip were studied using fluorescein isothiocyanate (FITC)-derivatized amino acids as probe molecules. A mixture of FITC and four FITC-derivatized amino acids was successfully separated with 2-mm separation channel length.

An Integrated Imaging Detector of Polarization and Spectral Content

NASA Technical Reports Server (NTRS)

Rust, D. M.; Thompson, K. E.

1993-01-01

A new type of image detector has been designed to simultaneously analyze the polarization of light at all picture elements in a scene. The Integrated Dual Imaging Detector (IDID) consists of a polarizing beamsplitter bonded to a charge-coupled device (CCD), with signal-analysis circuitry and analog-to-digital converters, all integrated on a silicon chip. It should be capable of 1:10(exp 4) polarization discrimination. The IDID should simplify the design and operation of imaging polarimeters and spectroscopic imagers used, for example, in atmospheric and solar research. Innovations in the IDID include (1) two interleaved 512 x 1024-pixel imaging arrays (one for each polarization plane); (2) large dynamic range (well depth of 10(exp 6) electrons per pixel); (3) simultaneous readout of both images at 10 million pixels per second each; (4) on-chip analog signal processing to produce polarization maps in real time; (5) on-chip 10-bit A/D conversion. When used with a lithium-niobate Fabry-Perot etalon or other color filter that can encode spectral information as polarization, the IDID can collect and analyze simultaneous images at two wavelengths. Precise photometric analysis of molecular or atomic concentrations in the atmosphere is one suggested application. When used in a solar telescope, the IDID will charge the polarization, which can then be converted to maps of the vector magnetic fields on the solar surface.

Design of a front-end integrated circuit for 3D acoustic imaging using 2D CMUT arrays.

PubMed

Ciçek, Ihsan; Bozkurt, Ayhan; Karaman, Mustafa

2005-12-01

Integration of front-end electronics with 2D capacitive micromachined ultrasonic transducer (CMUT) arrays has been a challenging issue due to the small element size and large channel count. We present design and verification of a front-end drive-readout integrated circuit for 3D ultrasonic imaging using 2D CMUT arrays. The circuit cell dedicated to a single CMUT array element consists of a high-voltage pulser and a low-noise readout amplifier. To analyze the circuit cell together with the CMUT element, we developed an electrical CMUT model with parameters derived through finite element analysis, and performed both the pre- and postlayout verification. An experimental chip consisting of 4 X 4 array of the designed circuit cells, each cell occupying a 200 X 200 microm2 area, was formed for the initial test studies and scheduled for fabrication in 0.8 microm, 50 V CMOS technology. The designed circuit is suitable for integration with CMUT arrays through flip-chip bonding and the CMUT-on-CMOS process.

Micro-architecture embedding ultra-thin interlayer to bond diamond and silicon via direct fusion

NASA Astrophysics Data System (ADS)

Kim, Jong Cheol; Kim, Jongsik; Xin, Yan; Lee, Jinhyung; Kim, Young-Gyun; Subhash, Ghatu; Singh, Rajiv K.; Arjunan, Arul C.; Lee, Haigun

2018-05-01

The continuous demand on miniaturized electronic circuits bearing high power density illuminates the need to modify the silicon-on-insulator-based chip architecture. This is because of the low thermal conductivity of the few hundred nanometer-thick insulator present between the silicon substrate and active layers. The thick insulator is notorious for releasing the heat generated from the active layers during the operation of devices, leading to degradation in their performance and thus reducing their lifetime. To avoid the heat accumulation, we propose a method to fabricate the silicon-on-diamond (SOD) microstructure featured by an exceptionally thin silicon oxycarbide interlayer (˜3 nm). While exploiting the diamond as an insulator, we employ spark plasma sintering to render the silicon directly fused to the diamond. Notably, this process can manufacture the SOD microarchitecture via a simple/rapid way and incorporates the ultra-thin interlayer for minute thermal resistance. The method invented herein expects to minimize the thermal interfacial resistance of the devices and is thus deemed as a breakthrough appealing to the current chip industry.

AAO-CNTs electrode on microfluidic flow injection system for rapid iodide sensing.

PubMed

Phokharatkul, Ditsayut; Karuwan, Chanpen; Lomas, Tanom; Nacapricha, Duangjai; Wisitsoraat, Anurat; Tuantranont, Adisorn

2011-06-15

In this work, carbon nanotubes (CNTs) nanoarrays in anodized aluminum oxide (AAO-CNTs) nanopore is integrated on a microfluidic flow injection system for in-channel electrochemical detection of iodide. The device was fabricated from PDMS (polydimethylsiloxane) microchannel bonded on glass substrates that contains three-electrode electrochemical system, including AAO-CNTs as a working electrode, silver as a reference electrode and platinum as an auxiliary electrode. Aluminum, stainless steel catalyst, silver and platinum layers were sputtered on the glass substrate through shadow masks. Aluminum layer was then anodized by two-step anodization process to form nanopore template. CNTs were then grown in AAO template by thermal chemical vapor deposition. The amperometric detection of iodide was performed in 500-μm-wide and 100-μm-deep microchannels on the microfluidic chip. The influences of flow rate, injection volume and detection potential on the current response were optimized. From experimental results, AAO-CNTs electrode on chip offers higher sensitivity and wider dynamic range than CNTs electrode with no AAO template. Copyright © 2011 Elsevier B.V. All rights reserved.

Cu Pillar Low Temperature Bonding and Interconnection Technology of for 3D RF Microsystem

NASA Astrophysics Data System (ADS)

Shi, G. X.; Qian, K. Q.; Huang, M.; Yu, Y. W.; Zhu, J.

2018-03-01

In this paper 3D interconnects technologies used Cu pillars are discussed with respect to RF microsystem. While 2.5D Si interposer and 3D packaging seem to rely to cu pillars for the coming years, RF microsystem used the heterogeneous chip such as GaAs integration with Si interposers should be at low temperature. The pillars were constituted by Cu (2 micron) -Ni (2 micron) -Cu (3 micron) -Sn (1 micron) multilayer metal and total height is 8 micron on the front-side of the wafer by using electroplating. The wafer backside Cu pillar is obtained by temporary bonding, thinning and silicon surface etching. The RF interposers are stacked by Cu-Sn eutectic bonding at 260 °C. Analyzed the reliability of different pillar bonding structure.

Chip PCR. I. Surface passivation of microfabricated silicon-glass chips for PCR.

PubMed Central

Shoffner, M A; Cheng, J; Hvichia, G E; Kricka, L J; Wilding, P

1996-01-01

The microreaction volumes of PCR chips (a microfabricated silicon chip bonded to a piece of flat glass to form a PCR reaction chamber) create a relatively high surface to volume ratio that increases the significance of the surface chemistry in the polymerase chain reaction (PCR). We investigated several surface passivations in an attempt to identify 'PCR friendly' surfaces and used those surfaces to obtain amplifications comparable with those obtained in conventional PCR amplification systems using polyethylene tubes. Surface passivations by a silanization procedure followed by a coating of a selected protein or polynucleotide and the deposition of a nitride or oxide layer onto the silicon surface were investigated. Native silicon was found to be an inhibitor of PCR and amplification in an untreated PCR chip (i.e. native slicon) had a high failure rate. A silicon nitride (Si(3)N(4) reaction surface also resulted in consistent inhibition of PCR. Passivating the PCR chip using a silanizing agent followed by a polymer treatment resulted in good amplification. However, amplification yields were inconsistent and were not always comparable with PCR in a conventional tube. An oxidized silicon (SiO(2) surface gave consistent amplifications comparable with reactions performed in a conventional PCR tube. PMID:8628665

KSC-07pd1241

NASA Image and Video Library

2007-05-17

KENNEDY SPACE CENTER, FLA. -- In the Astrotech Space Operations facility, Orbital Science technicians verify that a computer chip is securely bonded to a side brace on the Dawn spacecraft. The silicon chip holds the names of more than 360,000 space enthusiasts worldwide who signed up to participate in a virtual voyage to the asteroid belt and is about the size of an American five-cent coin. Dawn's mission is to explore two of the asteroid belt's most intriguing and dissimilar occupants: asteroid Vesta and the dwarf planet Ceres. Dawn is scheduled to launch June 30 from Launch Complex 17-B. Photo credit: NASA/George Shelton

Monolithic integration of a silica AWG and Ge photodiodes on Si photonic platform for one-chip WDM receiver.

PubMed

Nishi, Hidetaka; Tsuchizawa, Tai; Kou, Rai; Shinojima, Hiroyuki; Yamada, Takashi; Kimura, Hideaki; Ishikawa, Yasuhiko; Wada, Kazumi; Yamada, Koji

2012-04-09

On the silicon (Si) photonic platform, we monolithically integrated a silica-based arrayed-waveguide grating (AWG) and germanium (Ge) photodiodes (PDs) using low-temperature fabrication technology. We confirmed demultiplexing by the AWG, optical-electrical signal conversion by Ge PDs, and high-speed signal detection at all channels. In addition, we mounted a multichannel transimpedance amplifier/limiting amplifier (TIA/LA) circuit on the fabricated AWG-PD device using flip-chip bonding technology. The results show the promising potential of our Si photonic platform as a photonics-electronics convergence.

KSC-07pd1240

NASA Image and Video Library

2007-05-17

KENNEDY SPACE CENTER, FLA. -- In the Astrotech Space Operations facility, a computer chip is bonded to a side brace on the Dawn spacecraft. The silicon chip holds the names of more than 360,000 space enthusiasts worldwide who signed up to participate in a virtual voyage to the asteroid belt and is about the size of an American five-cent coin. Dawn's mission is to explore two of the asteroid belt's most intriguing and dissimilar occupants: asteroid Vesta and the dwarf planet Ceres. Dawn is scheduled to launch June 30 from Launch Complex 17-B. Photo credit: NASA/Jim Grossmann

Amplification of biological targets via on-chip culture for biosensing

DOE Office of Scientific and Technical Information (OSTI.GOV)

Harper, Jason C.; Edwards, Thayne L.; Carson, Bryan

The present invention, in part, relates to methods and apparatuses for on-chip amplification and/or detection of various targets, including biological targets and any amplifiable targets. In some examples, the microculture apparatus includes a single-use, normally-closed fluidic valve that is initially maintained in the closed position by a valve element bonded to an adhesive coating. The valve is opened using a magnetic force. The valve element includes a magnetic material or metal. Such apparatuses and methods are useful for in-field or real-time detection of targets, especially in limited resource settings.

A MoTe2-based light-emitting diode and photodetector for silicon photonic integrated circuits.

PubMed

Bie, Ya-Qing; Grosso, Gabriele; Heuck, Mikkel; Furchi, Marco M; Cao, Yuan; Zheng, Jiabao; Bunandar, Darius; Navarro-Moratalla, Efren; Zhou, Lin; Efetov, Dmitri K; Taniguchi, Takashi; Watanabe, Kenji; Kong, Jing; Englund, Dirk; Jarillo-Herrero, Pablo

2017-12-01

One of the current challenges in photonics is developing high-speed, power-efficient, chip-integrated optical communications devices to address the interconnects bottleneck in high-speed computing systems. Silicon photonics has emerged as a leading architecture, in part because of the promise that many components, such as waveguides, couplers, interferometers and modulators, could be directly integrated on silicon-based processors. However, light sources and photodetectors present ongoing challenges. Common approaches for light sources include one or few off-chip or wafer-bonded lasers based on III-V materials, but recent system architecture studies show advantages for the use of many directly modulated light sources positioned at the transmitter location. The most advanced photodetectors in the silicon photonic process are based on germanium, but this requires additional germanium growth, which increases the system cost. The emerging two-dimensional transition-metal dichalcogenides (TMDs) offer a path for optical interconnect components that can be integrated with silicon photonics and complementary metal-oxide-semiconductors (CMOS) processing by back-end-of-the-line steps. Here, we demonstrate a silicon waveguide-integrated light source and photodetector based on a p-n junction of bilayer MoTe 2 , a TMD semiconductor with an infrared bandgap. This state-of-the-art fabrication technology provides new opportunities for integrated optoelectronic systems.

A MoTe2-based light-emitting diode and photodetector for silicon photonic integrated circuits

NASA Astrophysics Data System (ADS)

Bie, Ya-Qing; Grosso, Gabriele; Heuck, Mikkel; Furchi, Marco M.; Cao, Yuan; Zheng, Jiabao; Bunandar, Darius; Navarro-Moratalla, Efren; Zhou, Lin; Efetov, Dmitri K.; Taniguchi, Takashi; Watanabe, Kenji; Kong, Jing; Englund, Dirk; Jarillo-Herrero, Pablo

2017-12-01

One of the current challenges in photonics is developing high-speed, power-efficient, chip-integrated optical communications devices to address the interconnects bottleneck in high-speed computing systems. Silicon photonics has emerged as a leading architecture, in part because of the promise that many components, such as waveguides, couplers, interferometers and modulators, could be directly integrated on silicon-based processors. However, light sources and photodetectors present ongoing challenges. Common approaches for light sources include one or few off-chip or wafer-bonded lasers based on III-V materials, but recent system architecture studies show advantages for the use of many directly modulated light sources positioned at the transmitter location. The most advanced photodetectors in the silicon photonic process are based on germanium, but this requires additional germanium growth, which increases the system cost. The emerging two-dimensional transition-metal dichalcogenides (TMDs) offer a path for optical interconnect components that can be integrated with silicon photonics and complementary metal-oxide-semiconductors (CMOS) processing by back-end-of-the-line steps. Here, we demonstrate a silicon waveguide-integrated light source and photodetector based on a p-n junction of bilayer MoTe2, a TMD semiconductor with an infrared bandgap. This state-of-the-art fabrication technology provides new opportunities for integrated optoelectronic systems.

Controlling the type and the form of chip when machining steel

NASA Astrophysics Data System (ADS)

Gruby, S. V.; Lasukov, A. A.; Nekrasov, R. Yu; Politsinsky, E. V.; Arkhipova, D. A.

2016-08-01

The type of the chip produced in the process of machining influences many factors of production process. Controlling the type of chip when cutting metals is important for producing swarf chips and for easing its utilization as well as for protecting the machined surface, cutting tool and the worker. In the given work we provide the experimental data on machining structural steel with implanted tool. The authors show that it is possible to control the chip formation process to produce the required type of chip by selecting the material for machining the tool surface.

MEMS-based thermally-actuated image stabilizer for cellular phone camera

NASA Astrophysics Data System (ADS)

Lin, Chun-Ying; Chiou, Jin-Chern

2012-11-01

This work develops an image stabilizer (IS) that is fabricated using micro-electro-mechanical system (MEMS) technology and is designed to counteract the vibrations when human using cellular phone cameras. The proposed IS has dimensions of 8.8 × 8.8 × 0.3 mm3 and is strong enough to suspend an image sensor. The processes that is utilized to fabricate the IS includes inductive coupled plasma (ICP) processes, reactive ion etching (RIE) processes and the flip-chip bonding method. The IS is designed to enable the electrical signals from the suspended image sensor to be successfully emitted out using signal output beams, and the maximum actuating distance of the stage exceeds 24.835 µm when the driving current is 155 mA. Depending on integration of MEMS device and designed controller, the proposed IS can decrease the hand tremor by 72.5%.

Flexible manufacturing for photonics device assembly

NASA Technical Reports Server (NTRS)

Lu, Shin-Yee; Pocha, Michael D.; Strand, Oliver T.; Young, K. David

1994-01-01

The assembly of photonics devices such as laser diodes, optical modulators, and opto-electronics multi-chip modules (OEMCM), usually requires the placement of micron size devices such as laser diodes, and sub-micron precision attachment between optical fibers and diodes or waveguide modulators (usually referred to as pigtailing). This is a very labor intensive process. Studies done by the opto-electronics (OE) industry have shown that 95 percent of the cost of a pigtailed photonic device is due to the use of manual alignment and bonding techniques, which is the current practice in industry. At Lawrence Livermore National Laboratory, we are working to reduce the cost of packaging OE devices through the use of automation. Our efforts are concentrated on several areas that are directly related to an automated process. This paper will focus on our progress in two of those areas, in particular, an automated fiber pigtailing machine and silicon micro-technology compatible with an automated process.

Fabrication of Silicon Backshorts with Improved Out-of-Band Rejection for Waveguide-Coupled Superconducting Detectors

NASA Technical Reports Server (NTRS)

Crowe, Erik J.; Bennett, Charles L.; Chuss, David T.; Denis, Kevin L.; Eimer, Joseph; Lourie, Nathan; Marriage, Tobias; Moseley, Samuel H.; Rostem, Karwan; Stevenson, Thomas R.;

Non-aqueous electrolytes for isotachophoresis of weak bases and its application to the comprehensive preconcentration of the 20 proteinogenic amino acids in column-coupling ITP/CE-MS.

PubMed

Kler, Pablo A; Huhn, Carolin

2014-11-01

Isotachophoresis (ITP) has long been used alone but also as a preconcentration technique for capillary electrophoresis (CE). Unfortunately, up to now, its application is restricted to relatively strong acids and bases as either the degree of (de)protonation is too low or the water dissociation is too high, evoking zone electrophoresis. With the comprehensive ITP analysis of all 20 proteinogenic amino acids as model analytes, we, here, show that non-aqueous ITP using dimethylsulfoxide as a solvent solves this ITP shortcoming. Dimethylsulfoxide changes the pH regime of analytes and electrolytes but, more importantly, strongly reduces the proton mobility by prohibiting hydrogen bonds and thus, the so-called Zundel-Eigen-Zundel electrical conduction mechanism of flipping hydrogen bonds. The effects are demonstrated in an electrolyte system with taurine or H(+) as terminator, and imidazole as leader together with strong acids such as oxalic and even trifluoroacetic acid as counterions, both impossible to use in aqueous solution. Mass spectrometric as well as capacitively coupled contactless conductivity detection (C(4)D) are used to follow the ITP processes. To demonstrate the preconcentration capabilities of ITP in a two-dimensional set-up, we, here, also demonstrate that our non-aqueous ITP method can be combined with capillary electrophoresis-mass spectrometry in a column-coupling system using a hybrid approach of capillaries coupled to a microfluidic interface. For this, C(4)D was optimized for on-chip detection with the electrodes aligned on top of a thin glass lid of the microfluidic chip.

Transferrable monolithic multicomponent system for near-ultraviolet optoelectronics

NASA Astrophysics Data System (ADS)

Qin, Chuan; Gao, Xumin; Yuan, Jialei; Shi, Zheng; Jiang, Yuan; Liu, Yuhuai; Wang, Yongjin; Amano, Hiroshi

2018-05-01

A monolithic near-ultraviolet multicomponent system is implemented on a 0.8-mm-diameter suspended membrane by integrating a transmitter, waveguide, and receiver into a single chip. Two identical InGaN/Al0.10Ga0.90N multiple-quantum well (MQW) diodes are fabricated using the same process flow, which separately function as a transmitter and receiver. There is a spectral overlap between the emission and detection spectra of the MQW diodes. Therefore, the receiver can respond to changes in the emission of the transmitter. The multicomponent system is mechanically transferred from silicon, and the wire-bonded transmitter on glass experimentally demonstrates spatial light transmission at 200 Mbps using non-return-to-zero on–off keying modulation.

Wafer level fabrication of single cell dispenser chips with integrated electrodes for particle detection

NASA Astrophysics Data System (ADS)

Schoendube, Jonas; Yusof, Azmi; Kalkandjiev, Kiril; Zengerle, Roland; Koltay, Peter

2015-02-01

This work presents the microfabrication and experimental evaluation of a dispenser chip, designed for isolation and printing of single cells by combining impedance sensing and drop-on-demand dispensing. The dispenser chip features 50  ×  55 µm (width × height) microchannels, a droplet generator and microelectrodes for impedance measurements. The chip is fabricated by sandwiching a dry film photopolymer (TMMF) between a silicon and a Pyrex wafer. TMMF has been used to define microfluidic channels, to serve as low temperature (75 °C) bonding adhesive and as etch mask during 300 µm deep HF etching of the Pyrex wafer. Due to the novel fabrication technology involving the dry film resist, it became possible to fabricate facing electrodes at the top and bottom of the channel and to apply electrical impedance sensing for particle detection with improved performance. The presented microchip is capable of dispensing liquid and detecting microparticles via impedance measurement. Single polystyrene particles of 10 µm size could be detected with a mean signal amplitude of 0.39  ±  0.13 V (n=439 ) at particle velocities of up to 9.6 mm s-1 inside the chip.

Modeling of heat transfer in compacted machining chips during friction consolidation process

NASA Astrophysics Data System (ADS)

Abbas, Naseer; Deng, Xiaomin; Li, Xiao; Reynolds, Anthony

2018-04-01

The current study aims to provide an understanding of the heat transfer process in compacted aluminum alloy AA6061 machining chips during the friction consolidation process (FCP) through experimental investigations and mathematical modelling and numerical simulation. Compaction and friction consolidation of machining chips is the first stage of the Friction Extrusion Process (FEP), which is a novel method for recycling machining chips to produce useful products such as wires. In this study, compacted machining chips are modelled as a continuum whose material properties vary with density during friction consolidation. Based on density and temperature dependent thermal properties, the temperature field in the chip material and process chamber caused by frictional heating during the friction consolidation process is predicted. The predicted temperature field is found to compare well with temperature measurements at select points where such measurements can be made using thermocouples.

InP on SOI devices for optical communication and optical network on chip

NASA Astrophysics Data System (ADS)

Fedeli, J.-M.; Ben Bakir, B.; Olivier, N.; Grosse, Ph.; Grenouillet, L.; Augendre, E.; Phillippe, P.; Gilbert, K.; Bordel, D.; Harduin, J.

2011-01-01

For about ten years, we have been developing InP on Si devices under different projects focusing first on μlasers then on semicompact lasers. For aiming the integration on a CMOS circuit and for thermal issue, we relied on SiO2 direct bonding of InP unpatterned materials. After the chemical removal of the InP substrate, the heterostructures lie on top of silicon waveguides of an SOI wafer with a separation of about 100nm. Different lasers or photodetectors have been achieved for off-chip optical communication and for intra-chip optical communication within an optical network. For high performance computing with high speed communication between cores, we developed InP microdisk lasers that are coupled to silicon waveguide and produced 100μW of optical power and that can be directly modulated up to 5G at different wavelengths. The optical network is based on wavelength selective circuits with ring resonators. InGaAs photodetectors are evanescently coupled to the silicon waveguide with an efficiency of 0.8A/W. The fabrication has been demonstrated at 200mm wafer scale in a microelectronics clean room for CMOS compatibility. For off-chip communication, silicon on InP evanescent laser have been realized with an innovative design where the cavity is defined in silicon and the gain localized in the QW of bonded InP hererostructure. The investigated devices operate at continuous wave regime with room temperature threshold current below 100 mA, the side mode suppression ratio is as high as 20dB, and the fibercoupled output power is {7mW. Direct modulation can be achieved with already 6G operation.

Direct grafting of long-lived luminescent indicator dyes to GaN light-emitting diodes for chemical microsensor development.

PubMed

López-Gejo, Juan; Navarro-Tobar, Álvaro; Arranz, Antonio; Palacio, Carlos; Muñoz, Elías; Orellana, Guillermo

2011-10-01

Two new methods for covalent functionalization of GaN based on plasma activation of its surface are presented. Both of them allow attachment of sulfonated luminescent ruthenium(II) indicator dyes to the p- and n-type semiconductor as well as to the surface of nonencapsulated chips of GaN light-emitting diodes (blue LEDs). X-ray photoelectron spectroscopy analysis of the functionalized semiconductor confirms the formation of covalent bonds between the GaN surface and the dye. Confocal fluorescence microscopy with single-photon-timing (SPT) detection has been used for characterization of the functionalized surfaces and LED chips. While the ruthenium complex attached to p-GaN under an oxygen-free atmosphere gives significantly long mean emission lifetimes for the indicator dye (ca. 2000 ns), the n-GaN-functionalized surfaces display surprisingly low values (600 ns), suggesting the occurrence of a quenching process. A photoinduced electron injection from the dye to the semiconductor conduction band, followed by a fast back electron transfer, is proposed to be responsible for the excited ruthenium dye deactivation. This process invalidates the use of the n-GaN/dye system for sensing applications. However, for p-GaN/dye materials, the luminescence decay accelerates in the presence of O(2). The moderate sensitivity is attributed to the fact that only a monolayer of indicator dye is anchored to the semiconductor surface but serves as a demonstrator device. Moreover, the luminescence decays of the functionalized LED chip measured with excitation of either an external (laser) source or the underlying LED emission (from p-GaN/InGaN quantum wells) yield the same mean luminescence lifetime. These results pave the way for using advanced LEDs to develop integrateable optochemical microsensors for gas analysis. © 2011 American Chemical Society

On-chip PMA labeling of foodborne pathogenic bacteria for viable qPCR and qLAMP detection

USDA-ARS?s Scientific Manuscript database

Propidium monoazide (PMA) is a membrane impermeable molecule that covalently bonds to double stranded DNA when exposed to light and inhibits the polymerase activity, thus enabling DNA amplification detection protocols that discriminate between viable and non-viable entities. Here, we present a micro...

Compression Debarking of Stored Wood Chips

Treesearch

James A. Mattson

1974-01-01

Two 750 ft. piles of unbarked chips were stored for 1 year to evaluate the effect of chip storage on the effectiveness of bark-chip separations-segregation methods under study. in processing stored chips suffered more wood loss than fresh chips.

Bump Bonding Using Metal-Coated Carbon Nanotubes

NASA Technical Reports Server (NTRS)

Lamb, James L.; Dickie, Matthew R.; Kowalczyk, Robert S.; Liao, Anna; Bronikowski, Michael J.

2012-01-01

Bump bonding hybridization techniques use arrays of indium bumps to electrically and mechanically join two chips together. Surface-tension issues limit bump sizes to roughly as wide as they are high. Pitches are limited to 50 microns with bumps only 8-14 microns high on each wafer. A new process uses oriented carbon nanotubes (CNTs) with a metal (indium) in a wicking process using capillary actions to increase the aspect ratio and pitch density of the connections for bump bonding hybridizations. It merges the properties of the CNTs and the metal bumps, providing enhanced material performance parameters. By merging the bumps with narrow and long CNTs oriented in the vertical direction, higher aspect ratios can be obtained if the metal can be made to wick. Possible aspect ratios increase from 1:1 to 20:1 for most applications, and to 100:1 for some applications. Possible pitch density increases of a factor of 10 are possible. Standard capillary theory would not normally allow indium or most other metals to be drawn into the oriented CNTs, because they are non-wetting. However, capillary action can be induced through the ability to fabricate oriented CNT bundles to desired spacings, and the use of deposition techniques and temperature to control the size and mobility of the liquid metal streams and associated reservoirs. This hybridization of two technologies (indium bumps and CNTs) may also provide for some additional benefits such as improved thermal management and possible current density increases.

Prototyping of thermoplastic microfluidic chips and their application in high-performance liquid chromatography separations of small molecules.

PubMed

Wouters, Sam; De Vos, Jelle; Dores-Sousa, José Luís; Wouters, Bert; Desmet, Gert; Eeltink, Sebastiaan

2017-11-10

The present paper discusses practical aspects of prototyping of microfluidic chips using cyclic olefin copolymer as substrate and the application in high-performance liquid chromatography. The developed chips feature a 60mm long straight separation channel with circular cross section (500μm i.d.) that was created using a micromilling robot. To irreversibly seal the top and bottom chip substrates, a solvent-vapor-assisted bonding approach was optimized, allowing to approximate the ideal circular channel geometry. Four different approaches to establish the micro-to-macro interface were pursued. The average burst pressure of the microfluidic chips in combination with an encasing holder was established at 38MPa and the maximum burst pressure was 47MPa, which is believed to be the highest ever report for these polymer-based microfluidic chips. Porous polymer monolithic frits were synthesized in-situ via UV-initiated polymerization and their locations were spatially controlled by the application of a photomask. Next, high-pressure slurry packing was performed to introduce 3μm silica reversed-phase particles as the stationary phase in the separation channel. Finally, the application of the chip technology is demonstrated for the separation of alkyl phenones in gradient mode yielding baseline peak widths of 6s by applying a steep gradient of 1.8min at a flow rate of 10μL/min. Copyright © 2017 Elsevier B.V. All rights reserved.

Utilisation of chip thickness models in grinding

NASA Astrophysics Data System (ADS)

Singleton, Roger

Grinding is now a well established process utilised for both stock removal and finish applications. Although significant research is performed in this field, grinding still experiences problems with burn and high forces which can lead to poor quality components and damage to equipment. This generally occurs in grinding when the process deviates from its safe working conditions. In milling, chip thickness parameters are utilised to predict and maintain process outputs leading to improved control of the process. This thesis looks to further the knowledge of the relationship between chip thickness and the grinding process outputs to provide an increased predictive and maintenance modelling capability. Machining trials were undertaken using different chip thickness parameters to understand how these affect the process outputs. The chip thickness parameters were maintained at different grinding wheel diameters for a constant productivity process to determine the impact of chip thickness at a constant material removal rate.. Additional testing using a modified pin on disc test rig was performed to provide further information on process variables. The different chip thickness parameters provide control of different process outputs in the grinding process. These relationships can be described using contact layer theory and heat flux partitioning. The contact layer is defined as the immediate layer beneath the contact arc at the wheel workpiece interface. The size of the layer governs the force experienced during the process. The rate of contact layer removal directly impacts the net power required from the system. It was also found that the specific grinding energy of a process is more dependent on the productivity of a grinding process rather than the value of chip thickness. Changes in chip thickness at constant material removal rate result in microscale changes in the rate of contact layer removal when compared to changes in process productivity. This is a significant piece of information in relation to specific grinding energy where conventional theory states it is primarily dependent on chip thickness..

Design and realization of 144 x 7 TDI ROIC with hybrid integrated test structure

NASA Astrophysics Data System (ADS)

Ceylan, Omer; Kayahan, Huseyin; Yazici, Melik; Baran, Muhammet Burak; Gurbuz, Yasar

2012-06-01

Design and realization of a 144x7 silicon readout integrated circuit (ROIC) based on switched capacitor TDI for MCT LWIR scanning type focal plane arrays (FPAs) and its corresponding hybrid integrated test circuits are presented. TDI operation with 7 detectors improves the SNR of the system by a factor of √7, while oversampling rate of 3 improves the spatial resolution of the system. ROIC supports bidirectional scan, 5 adjustable gain settings, bypass operation, automatic gain adjustment in case of mulfunctioning pixels and pixel select/deselect properties. Integration time of the system can be determined by the help of an external clock. Programming of ROIC can be done in parallel or serial mode according to the needs of the system. All properties except pixel select/deselect property can be performed in parallel mode, while pixel select/deselect property can be performed only in serial mode. ROIC can handle up to 3.75V dynamic range with a load of 25pF and output settling time of 80ns. Input referred noise of the ROIC is less than 750 rms electrons, while the power consumption is less than 100mW. To test ROIC in absence of detector array, a process and temperature compensated current reference array, which supplies uniform input current in range of 1-50nA to ROIC, is designed and measured both in room and cryogenic (77ºK) temperatures. Standard deviations of current reference arrays are measured 3.26% for 1nA and 0.99% for 50nA. ROIC and current reference array are fabricated seperately, and then flip-chip bonded for the test of the system. Flip-chip bonded system including ROIC and current reference test array is successfully measured both in room and cryogenic temperatures, and measurement results are presented. The manufacturing technology is 0.35μm, double poly-Si, four metal, 5V CMOS process.

Medipix2 as a tool for proton beam characterization

NASA Astrophysics Data System (ADS)

Bisogni, M. G.; Cirrone, G. A. P.; Cuttone, G.; Del Guerra, A.; Lojacono, P.; Piliero, M. A.; Romano, F.; Rosso, V.; Sipala, V.; Stefanini, A.

2009-08-01

Proton therapy is a technique used to deliver a highly accurate and effective dose for the treatment of a variety of tumor diseases. The possibility to have an instrument able to give online information could reduce the time necessary to characterize the proton beam. To this aim we propose a detection system for online proton beam characterization based on the Medipix2 chip. Medipix2 is a detection system based on a single event counter read-out chip, bump-bonded to silicon pixel detector. The read-out chip is a matrix of 256×256 cells, 55×55 μm 2 each. To demonstrate the capabilities of Medipix2 as a proton detector, we have used a 62 MeV flux proton beam at the CATANA beam line of the LNS-INFN laboratory. The measurements performed confirmed the good imaging performances of the Medipix2 system also for the characterization of proton beams.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Becker, Julian; Tate, Mark W.; Shanks, Katherine S.

Pixel Array Detectors (PADs) consist of an x-ray sensor layer bonded pixel-by-pixel to an underlying readout chip. This approach allows both the sensor and the custom pixel electronics to be tailored independently to best match the x-ray imaging requirements. Here we describe the hybridization of CdTe sensors to two different charge-integrating readout chips, the Keck PAD and the Mixed-Mode PAD (MM-PAD), both developed previously in our laboratory. The charge-integrating architecture of each of these PADs extends the instantaneous counting rate by many orders of magnitude beyond that obtainable with photon counting architectures. The Keck PAD chip consists of rapid, 8-frame,more » in-pixel storage elements with framing periods <150 ns. The second detector, the MM-PAD, has an extended dynamic range by utilizing an in-pixel overflow counter coupled with charge removal circuitry activated at each overflow. This allows the recording of signals from the single-photon level to tens of millions of x-rays/pixel/frame while framing at 1 kHz. Both detector chips consist of a 128×128 pixel array with (150 µm){sup 2} pixels.« less

Antibody immobilization on to polystyrene substrate--on-chip immunoassay for horse IgG based on fluorescence.

PubMed

Darain, Farzana; Gan, Kai Ling; Tjin, Swee Chuan

2009-06-01

A simple microfluidic immunoassay card was developed based on polystyrene (PS) substrate for the detection of horse IgG, an inexpensive model analyte using fluorescence microscope. The primary antibody was captured onto the PS based on covalent bonding via a self-assembled monolayer (SAM) of thiol to pattern the surface chemistry on a gold-coated PS. The immunosensor chip layers were fabricated from sheets by CO(2) laser ablation. The functionalized PS surfaces after each step were characterized by contact angle measurement, X-ray photoelectron spectroscopy (XPS), and atomic force microscopy (AFM). After the antibody-antigen interaction as a sandwich immunoassay with a fluorescein isothiocyanate (FITC)-conjugated secondary antibody, the intensity of fluorescence was measured on-chip to determine the concentration of the target analyte. The present immunosensor chip showed a linear response range for horse IgG between 1 microg/ml and 80 microg/ml (r = 0.971, n = 3). The detection limit was found to be 0.71 microg/ml. The developed microfluidic system can be extended for various applications including medical diagnostics, microarray detection and observing protein-protein interactions.

Development of a cleaning process for uranium chips machined with a glycol-water-borax coolant

DOE Office of Scientific and Technical Information (OSTI.GOV)

Taylor, P.A.

1984-12-01

A chip-cleaning process has been developed to remove the new glycol-water-borax coolant from oralloy chips. The process involves storing the freshly cut chips in Freon-TDF until they are cleaned, washing with water, and displacing the water with Freon-TDF. The wash water can be reused many times and still yield clean chips and then be added to the coolant to make up for evaporative losses. The Freon-TDF will be cycled by evaporation. The cleaning facility is currently being designed and should be operational by April 1985.

Scalable bonding of nanofibrous polytetrafluoroethylene (PTFE) membranes on microstructures

NASA Astrophysics Data System (ADS)

Mortazavi, Mehdi; Fazeli, Abdolreza; Moghaddam, Saeed

2018-01-01

Expanded polytetrafluoroethylene (ePTFE) nanofibrous membranes exhibit high porosity (80%-90%), high gas permeability, chemical inertness, and superhydrophobicity, which makes them a suitable choice in many demanding fields including industrial filtration, medical implants, bio-/nano- sensors/actuators and microanalysis (i.e. lab-on-a-chip). However, one of the major challenges that inhibit implementation of such membranes is their inability to bond to other materials due to their intrinsic low surface energy and chemical inertness. Prior attempts to improve adhesion of ePTFE membranes to other surfaces involved surface chemical treatments which have not been successful due to degradation of the mechanical integrity and the breakthrough pressure of the membrane. Here, we report a simple and scalable method of bonding ePTFE membranes to different surfaces via the introduction of an intermediate adhesive layer. While a variety of adhesives can be used with this technique, the highest bonding performance is obtained for adhesives that have moderate contact angles with the substrate and low contact angles with the membrane. A thin layer of an adhesive can be uniformly applied onto micro-patterned substrates with feature sizes down to 5 µm using a roll-coating process. Membrane-based microchannel and micropillar devices with burst pressures of up to 200 kPa have been successfully fabricated and tested. A thin layer of the membrane remains attached to the substrate after debonding, suggesting that mechanical interlocking through nanofiber engagement is the main mechanism of adhesion.

Manufacturing and testing VLPC hybrids

NASA Astrophysics Data System (ADS)

Adkins, L. R.; Ingram, C. M.; Anderson, E. J.

1998-11-01

To insure that the manufacture of VLPC devices is a reliable, cost-effective technology, hybrid assembly procedures and testing methods suitable for large scale production have been developed. This technology has been developed under a contract from Fermilab as part of the D-Zero upgrade program. Each assembled hybrid consists of a VLPC chip mounted on an AlN substrate. The VLPC chip is provided with bonding pads (one connected to each pixel) which are wire bonded to gold traces on the substrate. The VLPC/AlN hybrids are mated in a vacuum sealer using solder preforms and a specially designed carbon boat. After mating, the VLPC pads are bonded to the substrate with an automatic wire bonder. Using this equipment we have achieved a thickness tolerance of ±0.0007 inches and a production rate of 100 parts per hour. After assembly the VLPCs are tested for optical response at an operating temperature of 7K. The parts are tested in a custom designed continuous-flow dewar with a capacity 15 hybrids, and one Lake Shore DT470-SD-11 calibrated temperature sensor mounted to an AlN substrate. Our facility includes five of these dewars with an ultimate test capacity of 75 parts per day. During the course of the Dzero program we have assembled more than 4,000 VLPC hybrids and have tested more than 2,500 with a high yield.

Improved fabrication techniques for infrared bolometers

NASA Technical Reports Server (NTRS)

Lange, A. E.; Kreysa, E.; Mcbride, S. E.; Richards, P. L.; Haller, E. E.

1983-01-01

Techniques are described for producing improved infrared bolometers from doped germanium. Ion implantation and sputter metalization have been used to make ohmic electrical contacts to Ge:Ga chips. This method results in a high yield of small monolithic bolometers with very little low-frequency noise. When one of these chips is used as the thermometric element of a composite bolometer, it must be bonded to a dielectric substrate. The thermal resistance of the conventional epoxy bond has been measured and found to be undesirably large. A procedure for soldering the chip to a metalized portion of the substrate is described which reduced this resistance. The contribution of the metal film absorber to the heat capacity of a composite bolometer has been measured. The heat capacity of a NiCr absorber at 1.3 K can dominate the bolometer performance. A Bi absorber has significantly lower heat capacity. A low temperature blackbody calibrator has been built to measure the optical responsivity of bolometers. A composite bolometer system with a throughput of approx. 0.1 sr sq cm was constructed using the new techniques. In negligible background it has an optical NEP of 3.6 10((exp -15) W/sq root of Hz at 1.0 K with a time constant of 20 ms. The noise in this bolometer is white above 2.5 Hz and is somewhat below the value predicted by thermodynamic equilibrium theory. It is in agreement with calculations based on a recent nonequilibrium theory.

PECVD based silicon oxynitride thin films for nano photonic on chip interconnects applications.

PubMed

Sharma, Satinder K; Barthwal, Sumit; Singh, Vikram; Kumar, Anuj; Dwivedi, Prabhat K; Prasad, B; Kumar, Dinesh

2013-01-01

Thin silicon oxynitride (SiO(x)N(y)) films were deposited by low temperature (~300°C) plasma enhanced chemical vapour deposition (PECVD), using SiH(4), N(2)O, NH(3) precursor of the flow rate 25, 100, 30 sccm and subjected to the post deposition annealing (PDA) treatment at 400°C and 600°C for nano optical/photonics on chip interconnects applications. AFM result reveals the variation of roughness from 60.9 Å to 23.4 Å after PDA treatment with respect to the as-deposited films, favourable surface topography for integrated waveguide applications. A model of decrease in island height with the effect of PDA treatment is proposed in support of AFM results. Raman spectroscopy and FTIR measurements are performed in order to define the change in crystallite and chemical bonding of as-deposited as well as PDA treated samples. These outcomes endorsed to the densification of SiO(x)N(y) thin films, due to decrease in Si-N and Si-O bonds strain, as well the O-H, N-H bonds with in oxynitride network. The increase in refractive index and PL intensity of as deposited SiO(x)N(y) thin films to the PDA treated films at 400°C and 600°C are observed. The significant shift of PL spectra peak positions indicate the change in cluster size as the result of PDA treatment, which influence the optical properties of thin films. It might be due to out diffusion of hydrogen containing species from silicon oxynitride films after PDA treatment. In this way, the structural and optical, feasibility of SiO(x)N(y) films are demonstrated in order to obtain high quality thin films for nano optical/photonics on chip interconnects applications. Copyright © 2012 Elsevier Ltd. All rights reserved.

Producing Silicon Carbide for Semiconductor Devices

NASA Technical Reports Server (NTRS)

Hsu, G. C.; Rohatgi, N. K.

1986-01-01

Processes proposed for production of SiC crystals for use in semiconductors operating at temperatures as high as 900 degrees C. Combination of new processes produce silicon carbide chips containing epitaxial layers. Chips of SiC first grown on porous carbon matrices, then placed in fluidized bed, where additional layer of SiC grows. Processes combined to yield complete process. Liquid crystallization process used to make SiC particles or chips for fluidized-bed process.

Iridium Interfacial Stack - IrIS

NASA Technical Reports Server (NTRS)

Spry, David

2012-01-01

Iridium Interfacial Stack (IrIS) is the sputter deposition of high-purity tantalum silicide (TaSi2-400 nm)/platinum (Pt-200 nm)/iridium (Ir-200 nm)/platinum (Pt-200 nm) in an ultra-high vacuum system followed by a 600 C anneal in nitrogen for 30 minutes. IrIS simultaneously acts as both a bond metal and a diffusion barrier. This bondable metallization that also acts as a diffusion barrier can prevent oxygen from air and gold from the wire-bond from infiltrating silicon carbide (SiC) monolithically integrated circuits (ICs) operating above 500 C in air for over 1,000 hours. This TaSi2/Pt/Ir/Pt metallization is easily bonded for electrical connection to off-chip circuitry and does not require extra anneals or masking steps. There are two ways that IrIS can be used in SiC ICs for applications above 500 C: it can be put directly on a SiC ohmic contact metal, such as Ti, or be used as a bond metal residing on top of an interconnect metal. For simplicity, only the use as a bond metal is discussed. The layer thickness ratio of TaSi2 to the first Pt layer deposited thereon should be 2:1. This will allow Si from the TaSi2 to react with the Pt to form Pt2Si during the 600 C anneal carried out after all layers have been deposited. The Ir layer does not readily form a silicide at 600 C, and thereby prevents the Si from migrating into the top-most Pt layer during future anneals and high-temperature IC operation. The second (i.e., top-most) deposited Pt layer needs to be about 200 nm to enable easy wire bonding. The thickness of 200 nm for Ir was chosen for initial experiments; further optimization of the Ir layer thickness may be possible via further experimentation. Ir itself is not easily wire-bonded because of its hardness and much higher melting point than Pt. Below the iridium layer, the TaSi2 and Pt react and form desired Pt2Si during the post-deposition anneal while above the iridium layer remains pure Pt as desired to facilitate easy and strong wire-bonding to the SiC chip circuitry.

Thinning and mounting a Texas Instruments 3-phase CCD

NASA Technical Reports Server (NTRS)

Lesser, M. P.; Leach, R. W.; Angel, J. R. P.

1986-01-01

Thin CCDs with precise control of thickness and surface quality allow astronomers to optimize chips for specific applications. A means of mechanically thinning a TI 800 x 800 CCD with an abrasive slurry of aluminum oxide is presented. Using the same techniques, the abrasives can be replaced with a chemical solution to eliminate subsurface damage. A technique of mounting the CCD which retains the high quality surface generated during thinning is also demonstrated. This requires the backside of the chip to be bonded to a glass window which closely matches silicon's thermal expansion properties. Thinned CCDs require backside treatment to enhance blue and UV quantum efficiency. Two methods are discussed which may be effective with this mounting system.

Programmable synaptic chip for electronic neural networks

NASA Technical Reports Server (NTRS)

Moopenn, A.; Langenbacher, H.; Thakoor, A. P.; Khanna, S. K.

1988-01-01

A binary synaptic matrix chip has been developed for electronic neural networks. The matrix chip contains a programmable 32X32 array of 'long channel' NMOSFET binary connection elements implemented in a 3-micron bulk CMOS process. Since the neurons are kept off-chip, the synaptic chip serves as a 'cascadable' building block for a multi-chip synaptic network as large as 512X512 in size. As an alternative to the programmable NMOSFET (long channel) connection elements, tailored thin film resistors are deposited, in series with FET switches, on some CMOS test chips, to obtain the weak synaptic connections. Although deposition and patterning of the resistors require additional processing steps, they promise substantial savings in silicon area. The performance of synaptic chip in a 32-neuron breadboard system in an associative memory test application is discussed.

A Compact Imaging Detector of Polarization and Spectral Content

NASA Technical Reports Server (NTRS)

Rust, D. M.; Kumar, A.; Thompson, K. E.

1993-01-01

A new type of image detector will simultaneously analyze the polarization of light at all picture elements in a scene. The integrated Dual Imaging Detector (IDID) consists of a polarizing beam splitter bonded to a charge-coupled device (CCD), with signal-analysis circuitry and analog-to-digital converters, all integrated on a silicon chip. The polarizing beam splitter can be either a Ronchi ruling, or an array of cylindrical lenslets, bonded to a birefringent wafer. The wafer, in turn, is bonded to the CCD so that light in the two orthogonal planes of polarization falls on adjacent pairs of pixels. The use of a high-index birefringent material, e.g., rutile, allows the IDID to operate at f-numbers as high as f/3.5. Other aspects of the detector are discussed.

Transfer of InP epilayers by wafer bonding

NASA Astrophysics Data System (ADS)

Hjort, Klas

2004-08-01

Wafer bonding increases the freedom of design in the integration of dissimilar materials. For example, it is interesting to combine III-V compounds that have direct band gap and high mobility with silicon (Si) that is extensively used in microelectronic applications. The interest to integrate III-V-based materials with Si arises primarily from two types of applications: smart pixels for optical intra- and inter-chip interconnects in the so-called optoelectronic integrated circuits, and optoelectronic devices using some material advantages of combining III-V with Si. Also, in the III-V industry larger substrates are crucial for higher efficiency in high-volume production, and especially so for monolithic microwave integrated circuits (MMIC). For indium phosphide (InP) the development of large-area substrates has not been able to keep up with market demands. One way to circumvent this problem is to use silicon substrates that are large-area, low-cost, and mechanically strong with high thermal conductivity. In addition, silicon is transparent at the emission wavelengths most often used in InP-based optoelectronics. Unfortunately, the large lattice-mismatch, 8.1%, between silicon and InP, has limited the success of heteroepitaxial growth. Hence, one alternative to be reviewed is InP-to-Si wafer bonding. When a direct semiconductor interface is not needed there are several other means of wafer bonding, e.g. adhesive, eutectic, and solid-state. These processes can be used for direct integration of small islets of epitaxially thin InP microelectronics onto other substrates, e.g. by transferring of InP-based epilayers to a Si-based microwave circuit by pick-and-place, BCB resist adhesive bonding and sacrificing of the InP substrate.

An analysis of the pull strength behaviors of fine-pitch, flip chip solder interconnections using a Au-Pt-Pd thick film conductor on Low-Temperature, Co-fired Ceramic (LTCC) substrates.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Uribe, Fernando R.; Kilgo, Alice C.; Grazier, John Mark

2008-09-01

The assembly of the BDYE detector requires the attachment of sixteen silicon (Si) processor dice (eight on the top side; eight on the bottom side) onto a low-temperature, co-fired ceramic (LTCC) substrate using 63Sn-37Pb (wt.%, Sn-Pb) in a double-reflow soldering process (nitrogen). There are 132 solder joints per die. The bond pads were gold-platinum-palladium (71Au-26Pt-3Pd, wt.%) thick film layers fired onto the LTCC in a post-process sequence. The pull strength and failure modes provided the quality metrics for the Sn-Pb solder joints. Pull strengths were measured in both the as-fabricated condition and after exposure to thermal cycling (-55/125 C; 15more » min hold times; 20 cycles). Extremely low pull strengths--referred to as the low pull strength phenomenon--were observed intermittently throughout the product build, resulting in added program costs, schedule delays, and a long-term reliability concern for the detector. There was no statistically significant correlation between the low pull strength phenomenon and (1) the LTCC 'sub-floor' lot; (2) grit blasting the LTCC surfaces prior to the post-process steps; (3) the post-process parameters; (4) the conductor pad height (thickness); (5) the dice soldering assembly sequence; or (5) the dice pull test sequence. Formation of an intermetallic compound (IMC)/LTCC interface caused by thick film consumption during either the soldering process or by solid-state IMC formation was not directly responsible for the low-strength phenomenon. Metallographic cross sections of solder joints from dice that exhibited the low pull strength behavior, revealed the presence of a reaction layer resulting from an interaction between Sn from the molten Sn-Pb and the glassy phase at the TKN/LTCC interface. The thick film porosity did not contribute, explicitly, to the occurrence of reaction layer. Rather, the process of printing the very thin conductor pads was too sensitive to minor thixotropic changes to ink, which resulted in inconsistent proportions of metal and glassy phase particles present during the subsequent firing process. The consequences were subtle, intermittent changes to the thick film microstructure that gave rise to the reaction layer and, thus, the low pull strength phenomenon. A mitigation strategy would be the use of physical vapor deposition (PVD) techniques to create thin film bond pads; this is multi-chip module, deposited (MCM-D) technology.« less

Medium density fiberboard from mixed southern hardwoods

Treesearch

George E. Woodson

1977-01-01

Medium-density fiberboards of acceptable quality were made from a mixture of barky chips from 14 southern hardwoods. Boards made from fiber refined at three different plate clearances did not vary significantly in bending, internal bond (IB), or linear expansion. but, lack of replications and the fact that the refiner was not loaded to capacity caused these results to...

Biosensor system-on-a-chip including CMOS-based signal processing circuits and 64 carbon nanotube-based sensors for the detection of a neurotransmitter.

PubMed

Lee, Byung Yang; Seo, Sung Min; Lee, Dong Joon; Lee, Minbaek; Lee, Joohyung; Cheon, Jun-Ho; Cho, Eunju; Lee, Hyunjoong; Chung, In-Young; Park, Young June; Kim, Suhwan; Hong, Seunghun

2010-04-07

We developed a carbon nanotube (CNT)-based biosensor system-on-a-chip (SoC) for the detection of a neurotransmitter. Here, 64 CNT-based sensors were integrated with silicon-based signal processing circuits in a single chip, which was made possible by combining several technological breakthroughs such as efficient signal processing, uniform CNT networks, and biocompatible functionalization of CNT-based sensors. The chip was utilized to detect glutamate, a neurotransmitter, where ammonia, a byproduct of the enzymatic reaction of glutamate and glutamate oxidase on CNT-based sensors, modulated the conductance signals to the CNT-based sensors. This is a major technological advancement in the integration of CNT-based sensors with microelectronics, and this chip can be readily integrated with larger scale lab-on-a-chip (LoC) systems for various applications such as LoC systems for neural networks.

A Study of Chip Formation Feedrates of Various Steels in Low-Speed Milling Process

NASA Astrophysics Data System (ADS)

Prasetyo, L.; Tauviqirrahman, M.; Rusnaldy

2017-05-01

Milling is a process of metal removal by feeding the workpiece a rotating multitoothed cutter. The objective of the study was to investigate the chip characteristics (chip length, width, and thickness) during the milling process by varying the feedrates and the types of materials used based on an experimental approach. The chosen materials were AISI 1020, AISI 1045, AISI 1090, AISI D2, and AISI 4340 with a high-speed steel (HSS) as a cutter. In this work, the feedrates were varied of 5, 10, and 15 mm/minutes with the depth of cut of 0.5 mm and a low spindle speed of 70 rpm. The results show that, in general, increasing the feedrate will lead to the growth of chip length, width, and thickness for all types of materials used. Also, related to the chip shape, AISI 1020 produces the discontinuous chip which can be related to its hardness value.

Studies on spectroscopy of glycerol in THz range using microfluidic chip-integrated micropump

NASA Astrophysics Data System (ADS)

Su, Bo; Han, Xue; Wu, Ying; Zhang, Cunlin

2014-11-01

Terahertz time-domain spectroscopy (THz-TDS) is a detection method of biological molecules with label-free, non-ionizing, non-intrusive, no pollution and real-time monitoring. But owing to the strong THz absorption by water, it is mainly used in the solid state detection of biological molecules. In this paper, we present a microfluidic chip technique for detecting biological liquid samples using the transmission type of THz-TDS system. The microfluidic channel of the microfluidic chip is fabricated in the quartz glass using Micro-Electro-Mechanical System (MEMS) technology and sealed with polydimethylsiloxane (PDMS) diaphragm. The length, width and depth of the microfluidic channel are 25mm, 100μm and 50μm, respectively. The diameter of THz detection zone in the microfluidic channel is 4mm. The thicknesses of quartz glass and PDMS diaphragm are 1mm and 250μm, individually. Another one of the same quartz glass is used to bond with the PDMS for the rigidity and air tightness of the microfluidic chip. In order to realize the automation of sampling and improve the control precise of fluid, a micropump, which comprises PDMS diaphragm, pump chamber, diffuser and nozzle and flat vibration motor, is integrated on the microfluidic chip. The diffuser and nozzle are fabricated on both sides of the pump chamber, which is covered with PDMS diaphragm. The flat vibration motor is stuck on the PDMS diaphragm as the actuator. We study the terahertz absorption spectroscopy characteristics of glycerol with the concentration of 98% in the microfluidic chip by the aid of the THz-TDS system, and the feasibility of the microfluidic chip for the detection of liquid samples is proved.

Teaching Quality Control with Chocolate Chip Cookies

ERIC Educational Resources Information Center

Baker, Ardith

2014-01-01

Chocolate chip cookies are used to illustrate the importance and effectiveness of control charts in Statistical Process Control. By counting the number of chocolate chips, creating the spreadsheet, calculating the control limits and graphing the control charts, the student becomes actively engaged in the learning process. In addition, examining…

A miniature electronic nose system based on an MWNT-polymer microsensor array and a low-power signal-processing chip.

PubMed

Chiu, Shih-Wen; Wu, Hsiang-Chiu; Chou, Ting-I; Chen, Hsin; Tang, Kea-Tiong

2014-06-01

This article introduces a power-efficient, miniature electronic nose (e-nose) system. The e-nose system primarily comprises two self-developed chips, a multiple-walled carbon nanotube (MWNT)-polymer based microsensor array, and a low-power signal-processing chip. The microsensor array was fabricated on a silicon wafer by using standard photolithography technology. The microsensor array comprised eight interdigitated electrodes surrounded by SU-8 "walls," which restrained the material-solvent liquid in a defined area of 650 × 760 μm(2). To achieve a reliable sensor-manufacturing process, we used a two-layer deposition method, coating the MWNTs and polymer film as the first and second layers, respectively. The low-power signal-processing chip included array data acquisition circuits and a signal-processing core. The MWNT-polymer microsensor array can directly connect with array data acquisition circuits, which comprise sensor interface circuitry and an analog-to-digital converter; the signal-processing core consists of memory and a microprocessor. The core executes the program, classifying the odor data received from the array data acquisition circuits. The low-power signal-processing chip was designed and fabricated using the Taiwan Semiconductor Manufacturing Company 0.18-μm 1P6M standard complementary metal oxide semiconductor process. The chip consumes only 1.05 mW of power at supply voltages of 1 and 1.8 V for the array data acquisition circuits and the signal-processing core, respectively. The miniature e-nose system, which used a microsensor array, a low-power signal-processing chip, and an embedded k-nearest-neighbor-based pattern recognition algorithm, was developed as a prototype that successfully recognized the complex odors of tincture, sorghum wine, sake, whisky, and vodka.

32 x 16 CMOS smart pixel array for optical interconnects

NASA Astrophysics Data System (ADS)

Kim, Jongwoo; Guilfoyle, Peter S.; Stone, Richard V.; Hessenbruch, John M.; Choquette, Kent D.; Kiamilev, Fouad E.

2000-05-01

Free space optical interconnects can increase throughput capacities and eliminate much of the energy consumption required for `all electronic' systems. High speed optical interconnects can be achieved by integrating optoelectronic devices with conventional electronics. Smart pixel arrays have been developed which use optical interconnects. An individual smart pixel cell is composed of a vertical cavity surface emitting laser (VCSEL), a photodetector, an optical receiver, a laser driver, and digital logic circuitry. Oxide-confined VCSELs are being developed to operate at 850 nm with a threshold current of approximately 1 mA. Multiple quantum well photodetectors are being fabricated from AlGaAs for use with the 850 nm VCSELs. The VCSELs and photodetectors are being integrated with complementary metal oxide semiconductor (CMOS) circuitry using flip-chip bonding. CMOS circuitry is being integrated with a 32 X 16 smart pixel array. The 512 smart pixels are serially linked. Thus, an entire data stream may be clocked through the chip and output electrically by the last pixel. Electrical testing is being performed on the CMOS smart pixel array. Using an on-chip pseudo random number generator, a digital data sequence was cycled through the chip verifying operation of the digital circuitry. Although, the prototype chip was fabricated in 1.2 micrometers technology, simulations have demonstrated that the array can operate at 1 Gb/s per pixel using 0.5 micrometers technology.

Liquid carry-over in an injection moulded all-polymer chip system for immiscible phase magnetic bead-based solid-phase extraction

NASA Astrophysics Data System (ADS)

Kistrup, Kasper; Skotte Sørensen, Karen; Wolff, Anders; Fougt Hansen, Mikkel

2015-04-01

We present an all-polymer, single-use microfluidic chip system produced by injection moulding and bonded by ultrasonic welding. Both techniques are compatible with low-cost industrial mass-production. The chip is produced for magnetic bead-based solid-phase extraction facilitated by immiscible phase filtration and features passive liquid filling and magnetic bead manipulation using an external magnet. In this work, we determine the system compatibility with various surfactants. Moreover, we quantify the volume of liquid co-transported with magnetic bead clusters from Milli-Q water or a lysis-binding buffer for nucleic acid extraction (0.1 (v/v)% Triton X-100 in 5 M guanidine hydrochloride). A linear relationship was found between the liquid carry-over and mass of magnetic beads used. Interestingly, similar average carry-overs of 1.74(8) nL/μg and 1.72(14) nL/μg were found for Milli-Q water and lysis-binding buffer, respectively.

Disposable luciferase-based microfluidic chip for rapid assay of water pollution.

PubMed

Denisov, Ivan; Lukyanenko, Kirill; Yakimov, Anton; Kukhtevich, Igor; Esimbekova, Elena; Belobrov, Peter

2018-06-21

In the present study, we demonstrate the use of a disposable luciferase-based microfluidic bioassay chip for environmental monitoring and methods for fabrication. The designed microfluidic system includes a chamber with immobilized enzymes of bioluminescent bacteria Photobacterium leiognathi and Vibrio fischeri and their substrates, which dissolve after the introduction of the water sample and thus activate bioluminescent reactions. Limits of detection for copper (II) sulfate, 1,3-dihydroxybenzene and 1,4-benzoquinone for the proposed microfluidic biosensor measured 3 μM, 15 mM, and 2 μM respectively, and these values are higher or close to the level of conventional environmental biosensors based on lyophilized bacteria. Approaches for entrapment of enzymes on poly(methyl methacrylate) (PMMA) plates using a gelatin scaffold and solvent bonding of PMMA chip plates under room temperature were suggested. The proposed microfluidic system may be used with some available luminometers and future portable luminescence readers. © 2018 John Wiley & Sons, Ltd.

Flexible organic TFT bio-signal amplifier using reliable chip component assembly process with conductive adhesive.

PubMed

Yoshimoto, Shusuke; Uemura, Takafumi; Akiyama, Mihoko; Ihara, Yoshihiro; Otake, Satoshi; Fujii, Tomoharu; Araki, Teppei; Sekitani, Tsuyoshi

2017-07-01

This paper presents a flexible organic thin-film transistor (OTFT) amplifier for bio-signal monitoring and presents the chip component assembly process. Using a conductive adhesive and a chip mounter, the chip components are mounted on a flexible film substrate, which has OTFT circuits. This study first investigates the assembly technique reliability for chip components on the flexible substrate. This study also specifically examines heart pulse wave monitoring conducted using the proposed flexible amplifier circuit and a flexible piezoelectric film. We connected the amplifier to a bluetooth device for a wearable device demonstration.

Indium Hybridization of Large Format TES Bolometer Arrays to Readout Multiplexers for Far-Infrared Astronomy

NASA Technical Reports Server (NTRS)

Miller, Timothy M.; Costen, Nick; Allen, Christine

2007-01-01

This conference poster reviews the Indium hybridization of the large format TES bolometer arrays. We are developing a key technology to enable the next generation of detectors. That is the Hybridization of Large Format Arrays using Indium bonded detector arrays containing 32x40 elements which conforms to the NIST multiplexer readout architecture of 1135 micron pitch. We have fabricated and hybridized mechanical models with the detector chips bonded after being fully back-etched. The mechanical support consists of 30 micron walls between elements Demonstrated electrical continuity for each element. The goal is to hybridize fully functional array of TES detectors to NIST readout.

Wood chemical composition as related to properties of handsheets made from loblolly pine refiner groundwood

Treesearch

Charles W. McMillin

1969-01-01

Burst and tear strengths of handsheets made from 48 pulps disk-refined from chips of varying chemical composition decreased with incressing extractive content after the independent effects of fiber morphology were specified. This result was attributed to lessened bond strength caused by reduced surface tension forces and blocking of reactive sites on the fiber surfaces...

From Bonding Wires to Banding Women. Proceedings of the International Consultation on Micro-Chips Technology (Manila, Philippines, October 1986).

ERIC Educational Resources Information Center

Center for Women's Resources, Quezon City (Philippines).

In October 1986, 40 women from 12 countries gathered in the Philippines for a 10-day meeting of organizers, educators, and workers affected by and confronting the international electronics industry in microchip plants and in automated offices. Participants were from Malaysia, Indonesia, Thailand, the Philippines, Hong Kong, Japan, the Netherlands,…

Measurements with Si and GaAs pixel detectors bonded to photon counting readout chips

NASA Astrophysics Data System (ADS)

Schwarz, C.; Campbell, M.; Goeppert, R.; Ludwig, J.; Mikulec, B.; Runge, K.; Smith, K. M.; Snoeys, W.

2001-06-01

Detectors fabricated with SI-GaAs and Si bulk material were bonded to Photon Counting Chips (PCC), developed in the framework of the MEDIPIX Collaboration. The PCC consists of a matrix of 64×64 identical square pixels (170 μm×170 μm) with a 15-bit counter in each cell. We investigated the imaging properties of these detector systems under exposure of a dental X-ray tube at room temperature. The image homogeneity and the mean count rate were determined via flood exposure images and compared. Exposures for GaAs detectors exhibit a 3 times larger spread in count rate per image in comparison to Si detectors. This also results in a 3 times worse signal to noise ratio. IV-characteristics and X-ray images at different values of the detectors bias voltage were also taken and show a 30 times higher leakage current for GaAs. The Si detector is fully active beginning from 70 V, whereas the GaAs detector does not reach full charge collection. The presampling modulation transfer function of both assembly types was measured via slit images and gives a spatial resolution of 4.3 lp/mm for both detector systems.

Interconnect mechanisms in microelectronic packaging

NASA Astrophysics Data System (ADS)

Roma, Maria Penafrancia C.

Global economic, environmental and market developments caused major impact in the microelectronics industry. Astronomical rise of gold metal prices over the last decade shifted the use of copper and silver alloys as bonding wires. Environmental legislation on the restriction of the use of Pb launched worldwide search for lead-free solders and platings. Finally, electrical and digital uses demanded smaller, faster and cheaper devices. Ultra-fine pitch bonding, decreasing bond wire sizes and hard to bond substrates have put the once-robust stitch bond in the center of reliability issues due to stitch bond lift or open wires .Unlike the ball bond, stitch bonding does not lead to intermetallic compound formation but adhesion is dependent on mechanical deformation, interdiffusion, solid solution formation, void formation and mechanical interlocking depending on the wire material, bond configuration, substrate type , thickness and surface condition. Using Au standoff stitch bonds on NiPdAu plated substrates eliminated stitch bond lift even when the Au and Pd layers are reduced. Using the Matano-Boltzmann analysis on a STEM (Scanning Transmission Analysis) concentration profile the interdiffusion coefficient is measured to be 10-16 cm 2/s. Wire pull strength data showed that the wire pull strength is 0.062N and increases upon stress testing. Meanwhile, coating the Cu wire with Pd, not only increases oxidation resistance but also improved adhesion due to the formation of a unique interfacial adhesion layers. Adhesion strength as measured by pull showed the Cu wire bonded to Ag plated Cu substrate (0.132N) to be stronger than the Au wire bonded on the same substrate (0.124N). Ag stitch bonded to Au is predicted to be strong but surface modification made the adhesion stronger. However, on the Ag ball bonded to Al showed multiple IMC formation with unique morphology exposed by ion milling and backscattered scanning electron microscopy. Adding alloying elements in the Ag wire alloy showed differences in adhesion strength and IMC formation. Bond strength by wire pull testing showed the 95Ag alloy with higher values while shear bond testing showed the 88Ag higher bond strength. Use of Cu pillars in flip chips and eutectic bonding in wafer level chip scale packages are direct consequences of diminishing interconnect dimension as a result of the drive for miniaturization. The combination of Cu-Sn interdiffusion, Kirkendall mechanism and heterogeneous vacancy precipitation are the main causes of IMC and void formation in Cu pillar - Sn solder - Cu lead frame sandwich structure. However, adding a Ni barrier agent showed less porous IMC layer as well as void formation as a result of the modified Cu and Sn movement well as the void formation. Direct die to die bonding using Al-Ge eutectic bonds is necessary when 3D integration is needed to reduce the footprint of a package. Hermeticity and adhesion strength are a function of the Al/Ge thickness ratio, bonding pressure, temperature and time. Scanning Electron Microscope (SEM) and Focused Ion Beam (FIB) allowed imaging of interfacial microstructures, porosity, grain morphology while Scanning Transmission Electron microscope (STEM) provided diffusion profile and confirmed interdiffusion. Ion polishing technique provided information on porosity and when imaged using backscattered mode, grain structure confirmed mechanical deformation of the bonds. Measurements of the interfacial bond strength are made by wire pull tests and ball shear tests based on existing industry standard tests. However, for the Al-Ge eutectic bonds, no standard strength is available so a test is developed using the stud pull test method using the Dage 4000 Plus to yield consistent results. Adhesion strengths of 30-40 MPa are found for eutectic bonded packages however, as low as 20MPa was measured in low temperature bonded areas.

Property-driven functional verification technique for high-speed vision system-on-chip processor

NASA Astrophysics Data System (ADS)

Nshunguyimfura, Victor; Yang, Jie; Liu, Liyuan; Wu, Nanjian

2017-04-01

The implementation of functional verification in a fast, reliable, and effective manner is a challenging task in a vision chip verification process. The main reason for this challenge is the stepwise nature of existing functional verification techniques. This vision chip verification complexity is also related to the fact that in most vision chip design cycles, extensive efforts are focused on how to optimize chip metrics such as performance, power, and area. Design functional verification is not explicitly considered at an earlier stage at which the most sound decisions are made. In this paper, we propose a semi-automatic property-driven verification technique. The implementation of all verification components is based on design properties. We introduce a low-dimension property space between the specification space and the implementation space. The aim of this technique is to speed up the verification process for high-performance parallel processing vision chips. Our experimentation results show that the proposed technique can effectively improve the verification effort up to 20% for the complex vision chip design while reducing the simulation and debugging overheads.

Detection of tobacco rattle virus RNA in processed potato chips displaying symptoms of corky ringspot disease

USDA-ARS?s Scientific Manuscript database

A portion of genomic RNA 1 of tobacco rattle tobravirus (TRV) was amplified by reverse transcription polymerase chain reaction from each of eight processed potato chips from three different bags purchased at three locations. The positive chips all had symptoms typical of corky ringspot disease, cau...

Study of process parameter on mist lubrication of Titanium (Grade 5) alloy

NASA Astrophysics Data System (ADS)

Maity, Kalipada; Pradhan, Swastik

2017-02-01

This paper deals with the machinability of Ti-6Al-4V alloy with mist cooling lubrication using carbide inserts. The influence of process parameter on the cutting forces, evolution of tool wear, surface finish of the workpiece, material removal rate and chip reduction coefficient have been investigated. Weighted principal component analysis coupled with grey relational analysis optimization is applied to identify the optimum setting of the process parameter. Optimal condition of the process parameter was cutting speed at 160 m/min, feed at 0.16 mm/rev and depth of cut at 1.6 mm. Effects of cutting speed and depth of cut on the type of chips formation were observed. Most of the chips forms were long tubular and long helical type. Image analyses of the segmented chip were examined to study the shape and size of the saw tooth profile of serrated chips. It was found that by increasing cutting speed from 95 m/min to 160 m/min, the free surface lamella of the chips increased and the visibility of the saw tooth segment became clearer.

Advanced Initiation Systems Manufacturing Level 2 Milestone Completion Summary

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chow, R; Schmidt, M

2009-10-01

Milestone Description - Advanced Initiation Systems Detonator Design and Prototype. Milestone Grading Criteria - Design new generation chip slapper detonator and manufacture a prototype using advanced manufacturing processes, such as all-dry chip metallization and solvent-less flyer coatings. The advanced processes have been developed for manufacturing detonators with high material compatibility and reliability to support future LEPs, e.g. the B61, and new weapons systems. Perform velocimetry measurements to determine slapper velocity as a function of flight distance. A prototype detonator assembly and stripline was designed for low-energy chip slappers. Pictures of the prototype detonator and stripline are shown. All-dry manufacturing processesmore » were used to address compatibility issues. KCP metallized the chips in a physical vapor deposition system through precision-aligned shadow masks. LLNL deposited a solvent-less polyimide flyer with a processes called SLIP, which stands for solvent-less vapor deposition followed by in-situ polymerization. LANL manufactured the high-surface-area (HSA) high explosive (HE) pellets. Test fires of two chip slapper designs, radius and bowtie, were performed at LLNL in the High Explosives Application Facility (HEAF). Test fires with HE were conducted to establish the threshold firing voltages. pictures of the chip slappers before and after test fires are shown. Velocimetry tests were then performed to obtain slapper velocities at or above the threshold firing voltages. Figure 5 shows the slapper velocity as a function of distance and time at the threshold voltage, for both radius and bowtie bridge designs. Both designs were successful at initiating the HE at low energy levels. Summary of Accomplishments are: (1) All-dry process for chip manufacture developed; (2) Solventless process for slapper materials developed; (3) High-surface area explosive pellets developed; (4) High performance chip slappers developed; (5) Low-energy chip slapper detonator designs; and (6) Low-voltage threshold chip slapper detonator demonstrated.« less

Effect of cavity disinfectants on antibacterial activity and microtensile bond strength in class I cavity.

PubMed

Kim, Bo-Ram; Oh, Man-Hwan; Shin, Dong-Hoon

2017-05-31

This study was performed to compare the antibacterial activities of three cavity disinfectants [chlorhexidine (CHX), NaOCl, urushiol] and to evaluate their effect on the microtensile bond strength of Scotchbond Universal Adhesive (3M-ESPE, St. Paul, MN, USA) in class I cavities. In both experiments, class I cavities were prepared in dentin. After inoculation with Streptococcus mutans, the cavities of control group were rinsed and those of CHX, NaOCl and urushiol groups were treated with each disinfectant. Standardized amounts of dentin chips were collected and number of S. mutans was determined. Following the same cavity treatment, same adhesive was applied in etch-and-rinse mode. Then, microtensile bond strength was evaluated. The number of S. mutans was significantly reduced in the cavities treated with CHX, NaOCl, and urushiol compared with control group (p<0.05). However, there was a significant bond strength reduction in NaOCl group, which showed statistical difference compared to the other groups (p<0.05).

New valve and bonding designs for microfluidic biochips containing proteins.

PubMed

Lu, Chunmeng; Xie, Yubing; Yang, Yong; Cheng, Mark M-C; Koh, Chee-Guan; Bai, Yunling; Lee, L James; Juang, Yi-Je

2007-02-01

Two major concerns in the design and fabrication of microfluidic biochips are protein binding on the channel surface and protein denaturing during device assembly. In this paper, we describe new methods to solve these problems. A "fishbone" microvalve design based on the concept of superhydrophobicity was developed to replace the capillary valve in applications where the chip surface requires protein blocking to prevent nonspecific binding. Our experimental results show that the valve functions well in a CD-like ELISA device. The packaging of biochips containing pre-loaded proteins is also a challenging task since conventional sealing methods often require the use of high temperatures, electric voltages, or organic solvents that are detrimental to the protein activity. Using CO2 gas to enhance the diffusion of polymer molecules near the device surface can result in good bonding at low temperatures and low pressure. This bonding method has little influence on the activity of the pre-loaded proteins after bonding.

Fundamental Problems of Hybrid CMOS/Nanodevice Circuits

DTIC Science & Technology

2010-12-14

Development of an area-distributed CMOS/nanodevice interface We have carried out the first design of CMOS chips for the CMOS/nanodevice integration, and...got them fabricated in IBM’ 180-nm 7RF process (via MOSIS, Inc. silicon foundry). Each 44 mm2 chip assembly of the design consists of 4 component... chips , merged together for processing convenience. Each 22 mm2 component chip features two interface arrays, with 1010 vias each, with chip’s MOSFETs

Around Marshall

NASA Image and Video Library

2003-12-01

Helen Cole, the project manager for the Lab-on-a-Chip Applications Development program, and Lisa Monaco, the project scientist for the program, insert a lab on a chip into the Caliper 42 which is specialized equipment that controls processes on commercial chips to support development of lab-on-a-chip applications. The system has special microscopes and imaging systems, so scientists can process and study different types of fluid, chemical, and medical tests conducted on chips. For example, researchers have examined fluorescent bacteria as it flows through the chips' fluid channels or microfluidic capillaries. Researchers at NASA's Marshall Space Flight Center (MSFC) in Huntsville, Alabama, have been studying how the lab-on-a-chip technology can be used for microbial detection, water quality monitoring, and detecting biosignatures of past or present life on Mars. The Marshall Center team is also collaborating with scientists at other NASA centers and at universities to develop custom chip designs for not only space applications, but for many Earth applications, such as for detecting deadly microbes in heating and air systems. (NASA/MSFC/D.Stoffer)

Lab-on a-Chip

NASA Technical Reports Server (NTRS)

2003-01-01

Helen Cole, the project manager for the Lab-on-a-Chip Applications Development program, and Lisa Monaco, the project scientist for the program, insert a lab on a chip into the Caliper 42 which is specialized equipment that controls processes on commercial chips to support development of lab-on-a-chip applications. The system has special microscopes and imaging systems, so scientists can process and study different types of fluid, chemical, and medical tests conducted on chips. For example, researchers have examined fluorescent bacteria as it flows through the chips' fluid channels or microfluidic capillaries. Researchers at NASA's Marshall Space Flight Center (MSFC) in Huntsville, Alabama, have been studying how the lab-on-a-chip technology can be used for microbial detection, water quality monitoring, and detecting biosignatures of past or present life on Mars. The Marshall Center team is also collaborating with scientists at other NASA centers and at universities to develop custom chip designs for not only space applications, but for many Earth applications, such as for detecting deadly microbes in heating and air systems. (NASA/MSFC/D.Stoffer)

CMOS chip planarization by chemical mechanical polishing for a vertically stacked metal MEMS integration

NASA Astrophysics Data System (ADS)

Lee, Hocheol; Miller, Michele H.; Bifano, Thomas G.

2004-01-01

In this paper we present the planarization process of a CMOS chip for the integration of a microelectromechanical systems (MEMS) metal mirror array. The CMOS chip, which comes from a commercial foundry, has a bumpy passivation layer due to an underlying aluminum interconnect pattern (1.8 µm high), which is used for addressing individual micromirror array elements. To overcome the tendency for tilt error in the CMOS chip planarization, the approach is to sputter a thick layer of silicon nitride at low temperature and to surround the CMOS chip with dummy silicon pieces that define a polishing plane. The dummy pieces are first lapped down to the height of the CMOS chip, and then all pieces are polished. This process produced a chip surface with a root-mean-square flatness error of less than 100 nm, including tilt and curvature errors.

An Automatic Baseline Regulation in a Highly Integrated Receiver Chip for JUNO

NASA Astrophysics Data System (ADS)

Muralidharan, P.; Zambanini, A.; Karagounis, M.; Grewing, C.; Liebau, D.; Nielinger, D.; Robens, M.; Kruth, A.; Peters, C.; Parkalian, N.; Yegin, U.; van Waasen, S.

2017-09-01

This paper describes the data processing unit and an automatic baseline regulation of a highly integrated readout chip (Vulcan) for JUNO. The chip collects data continuously at 1 Gsamples/sec. The Primary data processing which is performed in the integrated circuit can aid to reduce the memory and data processing efforts in the subsequent stages. In addition, a baseline regulator compensating a shift in the baseline is described.

Development of polypyrrole based solid-state on-chip microactuators using photolithography

NASA Astrophysics Data System (ADS)

Zhong, Yong; Lundemo, Staffan; Jager, Edwin W. H.

2018-07-01

There is a need for soft microactuators, especially for biomedical applications. We have developed a microfabrication process to create such soft, on-chip polymer based microactuators that can operate in air. The on-chip microactuators were fabricated using standard photolithographic techniques and wet etching, combined with special designed process to micropattern the electroactive polymer polypyrrole that drives the microactuators. By immobilizing a UV-patternable gel containing a liquid electrolyte on top of the electroactive polypyrrole layer, actuation in air was achieved although with reduced movement. Further optimization of the processing is currently on-going. The result shows the possibility to batch fabricate complex microsystems such as microrobotics and micromanipulators based on these solid-state on-chip microactuators using microfabrication methods including standard photolithographic processes.

Femtosecond laser fabrication of fiber based optofluidic platform for flow cytometry applications

NASA Astrophysics Data System (ADS)

Serhatlioglu, Murat; Elbuken, Caglar; Ortac, Bulend; Solmaz, Mehmet E.

2017-02-01

Miniaturized optofluidic platforms play an important role in bio-analysis, detection and diagnostic applications. The advantages of such miniaturized devices are extremely low sample requirement, low cost development and rapid analysis capabilities. Fused silica is advantageous for optofluidic systems due to properties such as being chemically inert, mechanically stable, and optically transparent to a wide spectrum of light. As a three dimensional manufacturing method, femtosecond laser scanning followed by chemical etching shows great potential to fabricate glass based optofluidic chips. In this study, we demonstrate fabrication of all-fiber based, optofluidic flow cytometer in fused silica glass by femtosecond laser machining. 3D particle focusing was achieved through a straightforward planar chip design with two separately fabricated fused silica glass slides thermally bonded together. Bioparticles in a fluid stream encounter with optical interrogation region specifically designed to allocate 405nm single mode fiber laser source and two multi-mode collection fibers for forward scattering (FSC) and side scattering (SSC) signals detection. Detected signal data collected with oscilloscope and post processed with MATLAB script file. We were able to count number of events over 4000events/sec, and achieve size distribution for 5.95μm monodisperse polystyrene beads using FSC and SSC signals. Our platform shows promise for optical and fluidic miniaturization of flow cytometry systems.

PFM2: a 32 × 32 processor for X-ray diffraction imaging at FELs

NASA Astrophysics Data System (ADS)

Manghisoni, M.; Fabris, L.; Re, V.; Traversi, G.; Ratti, L.; Grassi, M.; Lodola, L.; Malcovati, P.; Vacchi, C.; Pancheri, L.; Benkechcache, M. E. A.; Dalla Betta, G.-F.; Xu, H.; Verzellesi, G.; Ronchin, S.; Boscardin, M.; Batignani, G.; Bettarini, S.; Casarosa, G.; Forti, F.; Giorgi, M.; Paladino, A.; Paoloni, E.; Rizzo, G.; Morsani, F.

2016-11-01

This work is concerned with the design of a readout chip for application to experiments at the next generation X-ray Free Electron Lasers (FEL). The ASIC, named PixFEL Matrix (PFM2), has been designed in a 65 nm CMOS technology and consists of 32 × 32 pixels. Each cell covers an area of 110 × 110 μm2 and includes a low-noise charge sensitive amplifier (CSA) with dynamic signal compression, a time-variant shaper used to process the preamplifier output signal, a 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) and digital circuitry for channel control and data readout. Two different solutions for the readout channel, based on different versions of the time-variant filter, have been integrated in the chip. Both solutions can be operated in such a way to cope with the high frame rate (exceeding 1 MHz) foreseen for future X-ray FEL machines. The ASIC will be bump bonded to a slim/active edge pixel sensor to form the first demonstrator for the PixFEL X-ray imager. This work has been carried out in the frame of the PixFEL project funded by Istituto Nazionale di Fisica Nucleare (INFN), Italy.

Cost-effective parallel optical interconnection module based on fully passive-alignment process

NASA Astrophysics Data System (ADS)

Son, Dong Hoon; Heo, Young Soon; Park, Hyoung-Jun; Kang, Hyun Seo; Kim, Sung Chang

2017-11-01

In optical interconnection technology, high-speed and large data transitions with low error rate and cost reduction are key issues for the upcoming 8K media era. The researchers present notable types of optical manufacturing structures of a four-channel parallel optical module by fully passive alignment, which are able to reduce manufacturing time and cost. Each of the components, such as vertical-cavity surface laser/positive-intrinsic negative-photodiode array, microlens array, fiber array, and receiver (RX)/transmitter (TX) integrated circuit, is integrated successfully using flip-chip bonding, die bonding, and passive alignment with a microscope. Clear eye diagrams are obtained by 25.78-Gb/s (for TX) and 25.7-Gb/s (for RX) nonreturn-to-zero signals of pseudorandom binary sequence with a pattern length of 231 to 1. The measured responsivity and minimum sensitivity of the RX are about 0.5 A/W and ≤-6.5 dBm at a bit error rate (BER) of 10-12, respectively. The optical power margin at a BER of 10-12 is 7.5 dB, and cross talk by the adjacent channel is ≤1 dB.

42 CFR 431.998 - Difference resolution and appeal process.

Code of Federal Regulations, 2012 CFR

2012-10-01

... for Estimating Improper Payments in Medicaid and CHIP § 431.998 Difference resolution and appeal... care claims in Medicaid or CHIP within 20 business days after the disposition report of claims review... CHIP agencies with personnel that are responsible for Medicaid and CHIP policy and operations, the...

42 CFR 431.998 - Difference resolution and appeal process.

Code of Federal Regulations, 2011 CFR

2011-10-01

... for Estimating Improper Payments in Medicaid and CHIP § 431.998 Difference resolution and appeal... care claims in Medicaid or CHIP within 20 business days after the disposition report of claims review... CHIP agencies with personnel that are responsible for Medicaid and CHIP policy and operations, the...

42 CFR 431.998 - Difference resolution and appeal process.

Code of Federal Regulations, 2013 CFR

2013-10-01

... for Estimating Improper Payments in Medicaid and CHIP § 431.998 Difference resolution and appeal... care claims in Medicaid or CHIP within 20 business days after the disposition report of claims review... CHIP agencies with personnel that are responsible for Medicaid and CHIP policy and operations, the...

42 CFR 431.998 - Difference resolution and appeal process.

Code of Federal Regulations, 2010 CFR

2010-10-01

... for Estimating Improper Payments in Medicaid and CHIP § 431.998 Difference resolution and appeal... care claims in Medicaid or CHIP within 20 business days after the disposition report of claims review... CHIP agencies with personnel that are responsible for Medicaid and CHIP policy and operations, the...

42 CFR 431.998 - Difference resolution and appeal process.

Code of Federal Regulations, 2014 CFR

2014-10-01

... for Estimating Improper Payments in Medicaid and CHIP § 431.998 Difference resolution and appeal... care claims in Medicaid or CHIP within 20 business days after the disposition report of claims review... CHIP agencies with personnel that are responsible for Medicaid and CHIP policy and operations, the...

Complexity and performance of on-chip biochemical assays

NASA Astrophysics Data System (ADS)

Kopf-Sill, Anne R.; Nikiforov, Theo; Bousse, Luc J.; Nagle, Rob; Parce, J. W.

1997-03-01

The use of microchips for performing biochemical processes has the potential to reduce reagent use and thus assay costs, increase throughput, and automate complex processes. We are building a multifunctional platform that provides sensing and actuation functions for a variety of microchip- based biochemical and analytical processes. Here we describe recent experiments that include on-chip dilution, reagent mixing, reaction, separation, and detection for important classes of biochemical assays. Issues in chip design and control are discussed.

3-D readout-electronics packaging for high-bandwidth massively paralleled imager

DOEpatents

Kwiatkowski, Kris; Lyke, James

2007-12-18

Dense, massively parallel signal processing electronics are co-packaged behind associated sensor pixels. Microchips containing a linear or bilinear arrangement of photo-sensors, together with associated complex electronics, are integrated into a simple 3-D structure (a "mirror cube"). An array of photo-sensitive cells are disposed on a stacked CMOS chip's surface at a 45.degree. angle from light reflecting mirror surfaces formed on a neighboring CMOS chip surface. Image processing electronics are held within the stacked CMOS chip layers. Electrical connections couple each of said stacked CMOS chip layers and a distribution grid, the connections for distributing power and signals to components associated with each stacked CSMO chip layer.

Sensory and Quality Evaluation of Traditional Compared with Power Ultrasound Processed Corn (Zea Mays) Tortilla Chips.

PubMed

Janve, Bhaskar; Yang, Wade; Sims, Charles

2015-06-01

Power ultrasound reduces the traditional corn steeping time from 18 to 1.5 h during tortilla chips dough (masa) processing. This study sought to examine consumer (n = 99) acceptability and quality of tortilla chips made from the masa by traditional compared with ultrasonic methods. Overall appearance, flavor, and texture acceptability scores were evaluated using a 9-point hedonic scale. The baked chips (process intermediate) before and after frying (finished product) were analyzed using a texture analyzer and machine vision. The texture values were determined using the 3-point bend test using breaking force gradient (BFG), peak breaking force (PBF), and breaking distance (BD). The fracturing properties determined by the crisp fracture support rig using fracture force gradient (FFG), peak fracture force (PFF), and fracture distance (FD). The machine vision evaluated the total surface area, lightness (L), color difference (ΔE), Hue (°h), and Chroma (C*). The results were evaluated by analysis of variance and means were separated using Tukey's test. Machine vision values of L, °h, were higher (P < 0.05) and ΔE was lower (P < 0.05) for fried and L, °h were significantly (P < 0.05) higher for baked chips produced from ultra-sonication as compare to traditional. Baked chips texture for ultra-sonication was significantly higher (P < 0.05) on BFG, BPD, PFF, and FD. Fried tortilla chips texture were higher significantly (P < 0.05) in BFG and PFF for ultra-sonication than traditional processing. However, the instrumental differences were not detected in sensory analysis, concluding possibility of power ultrasound as potential tortilla chips processing aid. © 2015 Institute of Food Technologists®

CHIP: A new modulator of human malignant disorders

PubMed Central

Shao, Qianqian; Yang, Gang; Zheng, Lianfang; Zhang, Taiping; Zhao, Yupei

2016-01-01

Carboxyl terminus of Hsc70-interacting protein (CHIP) is known as a chaperone-associated E3 for a variety of protein substrates. It acts as a link between molecular chaperones and ubiquitin–proteasome system. Involved in the process of protein clearance, CHIP plays a critical role in maintaining protein homeostasis in diverse conditions. Here, we provide a comprehensive review of our current understanding of CHIP and summarize recent advances in CHIP biology, with a focus on CHIP in the setting of malignancies. PMID:27007160

Power-Amplifier Module for 145 to 165 GHz

NASA Technical Reports Server (NTRS)

Samoska, Lorene; Peralta, Alejandro

2007-01-01

A power-amplifier module that operates in the frequency range of 145 to 165 GHz has been designed and constructed as a combination of (1) a previously developed monolithic microwave integrated circuit (MMIC) power amplifier and (2) a waveguide module. The amplifier chip was needed for driving a high-electron-mobility-transistor (HEMT) frequency doubler. While it was feasible to connect the amplifier and frequency-doubler chips by use of wire bonds, it was found to be much more convenient to test the amplifier and doubler chips separately. To facilitate separate testing, it was decided to package the amplifier and doubler chips in separate waveguide modules. Figure 1 shows the resulting amplifier module. The amplifier chip was described in "MMIC HEMT Power Amplifier for 140 to 170 GHz" (NPO-30127), NASA Tech Briefs, Vol. 27, No. 11, (November 2003), page 49. To recapitulate: This is a three-stage MMIC power amplifier that utilizes HEMTs as gain elements. The amplifier was originally designed to operate in the frequency range of 140 to 170 GHz. The waveguide module is based on a previously developed lower frequency module, redesigned to support operation in the frequency range of 140 to 220 GHz. Figure 2 presents results of one of several tests of the amplifier module - measurements of output power and gain as functions of input power at an output frequency of 150 GHz. Such an amplifier module has many applications to test equipment for power sources above 100 GHz.

Modified precision-husky progrind H-3045 for chipping biomass

Treesearch

Dana Mitchell; Fernando Seixas; John Klepac

2008-01-01

A specific size of whole tree chip was needed to co-mill wood chips with coal. The specifications are stringent because chips must be mixed with coal, as opposed to a co-firing process. In co-firing, two raw products are conveyed separately to a boiler. In co-milling, such as at Alabama Power's Plant Gadsden, the chip and coal mix must pass through a series of...

Heat stress during development alters post-harvest sugar contents and chip processing quality of potato tubers

USDA-ARS?s Scientific Manuscript database

Environmental stresses that increase tuber contents of the reducing sugars glucose and fructose decrease the value of chipping potatoes because such tubers produce dark-colored chips that are unacceptable to processors and consumers. Stem-end chip defect (SECD), which causes regions of dark color al...

Andy Jenkins Builds Applications Development For Lab-on-a-Chip

NASA Technical Reports Server (NTRS)

2004-01-01

Andy Jenkins, an engineer for the Lab on a Chip Applications Development program, helped build the Applications Development Unit (ADU-25), a one-of-a-kind facility for controlling and analyzing processes on chips with extreme accuracy. Pressure is used to cause fluids to travel through network of fluid pathways, or micro-channels, embossed on the chips through a process similar to the one used to print circuits on computer chips. To make customized chips for various applications, NASA has an agreement with the U.S. Army's Micro devices and Micro fabrication Laboratory at Redstone Arsenal in Huntsville, Alabama, where NASA's Marshall Space Flight Center (MSFC) is located. The Marshall Center team is also collaborating with scientists at other NASA centers and at universities to develop custom chip designs for many applications, such as studying how fluidic systems work in spacecraft and identifying microbes in self-contained life support systems. Chips could even be designed for use on Earth, such as for detecting deadly microbes in heating and air systems. (NASA/MSFC/D.Stoffer)

Multipass comminution process to produce precision wood particles of uniform size and shape with disrupted grain structure from wood chips

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dooley, James H; Lanning, David N

A process of comminution of wood chips (C) having a grain direction to produce a mixture of wood particles (P), wherein the wood chips are characterized by an average length dimension (L.sub.C) as measured substantially parallel to the grain, an average width dimension (W.sub.C) as measured normal to L.sub.C and aligned cross grain, and an average height dimension (H.sub.C) as measured normal to W.sub.C and L.sub.C, and wherein the comminution process comprises the step of feeding the wood chips in a direction of travel substantially randomly to the grain direction one or more times through a counter rotating pair ofmore » intermeshing arrays of cutting discs (D) arrayed axially perpendicular to the direction of wood chip travel.« less

Epoxy Chip-in-Carrier Integration and Screen-Printed Metalization for Multichannel Microfluidic Lab-on-CMOS Microsystems.

PubMed

Li, Lin; Yin, Heyu; Mason, Andrew J

2018-04-01

The integration of biosensors, microfluidics, and CMOS instrumentation provides a compact lab-on-CMOS microsystem well suited for high throughput measurement. This paper describes a new epoxy chip-in-carrier integration process and two planar metalization techniques for lab-on-CMOS that enable on-CMOS electrochemical measurement with multichannel microfluidics. Several design approaches with different fabrication steps and materials were experimentally analyzed to identify an ideal process that can achieve desired capability with high yield and low material and tool cost. On-chip electrochemical measurements of the integrated assembly were performed to verify the functionality of the chip-in-carrier packaging and its capability for microfluidic integration. The newly developed CMOS-compatible epoxy chip-in-carrier process paves the way for full implementation of many lab-on-CMOS applications with CMOS ICs as core electronic instruments.

Fabrication and characterization of semicircular detection electrodes for contactless conductivity detector - CE microchips.

PubMed

Lee, Chia-Yen; Chen, C M; Chang, Guan-Liang; Lin, Che-Hsin; Fu, Lung-Ming

2006-12-01

This study uses simple and reliable microfabrication techniques to fabricate CE biochips, integrating a novel contactless conductivity detector in a miniaturized detection system in a microfluidic biochip. The off-channel electrodes are deposited around side channels by Au sputtering and patterned using a standard "lift-off" process. A vacuum fusion bonding process is employed to seal the lower substrate containing the microchannels and the electrodes to an upper glass cover plate. The variations in the capacitance between the semicircular detection electrodes in the side channels are measured as different samples and ions pass through the detection region of the CE separation channel. Samples of Rhodamine B, commercial sports drinks, mineral waters, and a red wine, respectively, are mixed in different buffer solutions, separated, and successfully detected using the developed device. The semicircular detection electrodes for the contactless conductivity detector have microscale dimensions and provide a valuable contribution to the realization of the lab-on-a-chip concept.

An implantable integrated low-power amplifier-microelectrode array for Brain-Machine Interfaces.

PubMed

Patrick, Erin; Sankar, Viswanath; Rowe, William; Sanchez, Justin C; Nishida, Toshikazu

2010-01-01

One of the important challenges in designing Brain-Machine Interfaces (BMI) is to build implantable systems that have the ability to reliably process the activity of large ensembles of cortical neurons. In this paper, we report the design, fabrication, and testing of a polyimide-based microelectrode array integrated with a low-power amplifier as part of the Florida Wireless Integrated Recording Electrode (FWIRE) project at the University of Florida developing a fully implantable neural recording system for BMI applications. The electrode array was fabricated using planar micromachining MEMS processes and hybrid packaged with the amplifier die using a flip-chip bonding technique. The system was tested both on bench and in-vivo. Acute and chronic neural recordings were obtained from a rodent for a period of 42 days. The electrode-amplifier performance was analyzed over the chronic recording period with the observation of a noise floor of 4.5 microVrms, and an average signal-to-noise ratio of 3.8.

A MoTe2 based light emitting diode and photodetector for silicon photonic integrated circuits

NASA Astrophysics Data System (ADS)

Bie, Ya-Qing; Heuck, M.; Grosso, G.; Furchi, M.; Cao, Y.; Zheng, J.; Navarro-Moratalla, E.; Zhou, L.; Taniguchi, T.; Watanabe, K.; Kong, J.; Englund, D.; Jarillo-Herrero, P.

A key challenge in photonics today is to address the interconnects bottleneck in high-speed computing systems. Silicon photonics has emerged as a leading architecture, partly because many components such as waveguides, interferometers and modulators, could be integrated on silicon-based processors. However, light sources and photodetectors present continued challenges. Common approaches for light source include off-chip or wafer-bonded lasers based on III-V materials, but studies show advantages for directly modulated light sources. The most advanced photodetectors in silicon photonics are based on germanium growth which increases system cost. The emerging two dimensional transition metal dichalcogenides (TMDs) offer a path for optical interconnects components that can be integrated with the CMOS processing by back-end-of-the-line processing steps. Here we demonstrate a silicon waveguide-integrated light source and photodetector based on a p-n junction of bilayer MoTe2, a TMD semiconductor with infrared band gap. The state-of-the-art fabrication technology provides new opportunities for integrated optoelectronic systems.

MEMS Fabry-Perot sensor interrogated by optical system-on-a-chip for simultaneous pressure and temperature sensing.

PubMed

Pang, Cheng; Bae, Hyungdae; Gupta, Ashwani; Bryden, Kenneth; Yu, Miao

2013-09-23

We present a micro-electro-mechanical systems (MEMS) based Fabry-Perot (FP) sensor along with an optical system-on-a-chip (SOC) interrogator for simultaneous pressure and temperature sensing. The sensor employs a simple structure with an air-backed silicon membrane cross-axially bonded to a 45° polished optical fiber. This structure renders two cascaded FP cavities, enabling simultaneous pressure and temperature sensing in close proximity along the optical axis. The optical SOC consists of a broadband source, a MEMS FP tunable filter, a photodetector, and the supporting circuitry, serving as a miniature spectrometer for retrieving the two FP cavity lengths. Within the measured pressure and temperature ranges, experimental results demonstrate that the sensor exhibits a good linear response to external pressure and temperature changes.

High Temperature Performance of a SiC MESFET Based Oscillator

NASA Technical Reports Server (NTRS)

Schwartz, Zachary D.; Ponchak, George E.

2005-01-01

A hybrid, UHF-Band differential oscillator based on 10 w SiC RF Power Metal Semiconductor Field Effect Transistor (MESFET) has been designed, fabricated and characterized through 475 C. Circuit is fabricated on an alumina substrate with thin film spiral inductors, chip capacitors, chip resistors, and wire bonds for all crossovers and interconnectors. The oscillator delivers 15.7 dBm at 515 MHz into a 50 Ohm load at 125 C with a DC to RF conversion efficiency of 2,8%. After tuning the load impedance, the oscillator delivers 18.8 dBm at 610 MHz at 200 C with a DC to RF conversion efficiency of 5.8%. Finally, by tuning the load and bias conditions, the oscillator delivers 4.9 dBm at 453 MHz at 475 C.

Wiring up pre-characterized single-photon emitters by laser lithography

NASA Astrophysics Data System (ADS)

Shi, Q.; Sontheimer, B.; Nikolay, N.; Schell, A. W.; Fischer, J.; Naber, A.; Benson, O.; Wegener, M.

2016-08-01

Future quantum optical chips will likely be hybrid in nature and include many single-photon emitters, waveguides, filters, as well as single-photon detectors. Here, we introduce a scalable optical localization-selection-lithography procedure for wiring up a large number of single-photon emitters via polymeric photonic wire bonds in three dimensions. First, we localize and characterize nitrogen vacancies in nanodiamonds inside a solid photoresist exhibiting low background fluorescence. Next, without intermediate steps and using the same optical instrument, we perform aligned three-dimensional laser lithography. As a proof of concept, we design, fabricate, and characterize three-dimensional functional waveguide elements on an optical chip. Each element consists of one single-photon emitter centered in a crossed-arc waveguide configuration, allowing for integrated optical excitation and efficient background suppression at the same time.

SPROC: A multiple-processor DSP IC

NASA Technical Reports Server (NTRS)

Davis, R.

1991-01-01

A large, single-chip, multiple-processor, digital signal processing (DSP) integrated circuit (IC) fabricated in HP-Cmos34 is presented. The innovative architecture is best suited for analog and real-time systems characterized by both parallel signal data flows and concurrent logic processing. The IC is supported by a powerful development system that transforms graphical signal flow graphs into production-ready systems in minutes. Automatic compiler partitioning of tasks among four on-chip processors gives the IC the signal processing power of several conventional DSP chips.

Optimisation of an oak chips-grape mix maceration process. Influence of chip dose and maceration time.

PubMed

Gordillo, Belén; Baca-Bocanegra, Berta; Rodriguez-Pulído, Francisco J; González-Miret, M Lourdes; García Estévez, Ignacio; Quijada-Morín, Natalia; Heredia, Francisco J; Escribano-Bailón, M Teresa

2016-09-01

Oak chips-related phenolics are able to modify the composition of red wine and modulate the colour stability. In this study, the effect of two maceration techniques, traditional and oak chips-grape mix process, on the phenolic composition and colour of Syrah red wines from warm climate was studied. Two doses of oak chips (3 and 6g/L) at two maceration times (5 and 10days) during fermentation was considered. Changes on phenolic composition (HPLC-DAD-MS), copigmentation/polymerisation (spectrophotometry), and colour (Tristimulus and Differential Colorimetry) were assessed by multivariate statistical techniques. The addition of oak chips at shorter maceration times enhanced phenolic extraction, colour and its stabilisation in comparison to the traditional maceration. On contrast, increasing chip dose in extended maceration time resulted in wines with lighter and less stable colour. Results open the possibility of optimise alternative technological applications to traditional grape maceration for avoiding the common loss of colour of wines from warm climate. Copyright © 2016 Elsevier Ltd. All rights reserved.

Around Marshall

NASA Image and Video Library

2004-02-01

Andy Jenkins, an engineer for the Lab on a Chip Applications Development program, helped build the Applications Development Unit (ADU-25), a one-of-a-kind facility for controlling and analyzing processes on chips with extreme accuracy. Pressure is used to cause fluids to travel through network of fluid pathways, or micro-channels, embossed on the chips through a process similar to the one used to print circuits on computer chips. To make customized chips for various applications, NASA has an agreement with the U.S. Army's Micro devices and Micro fabrication Laboratory at Redstone Arsenal in Huntsville, Alabama, where NASA's Marshall Space Flight Center (MSFC) is located. The Marshall Center team is also collaborating with scientists at other NASA centers and at universities to develop custom chip designs for many applications, such as studying how fluidic systems work in spacecraft and identifying microbes in self-contained life support systems. Chips could even be designed for use on Earth, such as for detecting deadly microbes in heating and air systems. (NASA/MSFC/D.Stoffer)

Imaging label-free biosensor with microfluidic system

NASA Astrophysics Data System (ADS)

Jahns, S.; Glorius, P.; Hansen, M.; Nazirizadeh, Y.; Gerken, M.

2015-06-01

We present a microfluidic system suitable for parallel label-free detection of several biomarkers utilizing a compact imaging measurement system. The microfluidic system contains a filter unit to separate the plasma from human blood and a functionalized, photonic crystal slab sensor chip. The nanostructure of the photonic crystal slab sensor chip is fabricated by nanoimprint lithography of a period grating surface into a photoresist and subsequent deposition of a TiO2 layer. Photonic crystal slabs are slab waveguides supporting quasi-guided modes coupling to far-field radiation, which are sensitive to refractive index changes due to biomarker binding on the functionalized surface. In our imaging read-out system the resulting resonance shift of the quasi-guided mode in the transmission spectrum is converted into an intensity change detectable with a simple camera. By continuously taking photographs of the sensor surface local intensity changes are observed revealing the binding kinetics of the biomarker to its specific target. Data from two distinct measurement fields are used for evaluation. For testing the sensor chip, 1 μM biotin as well as 1 μM recombinant human CD40 ligand were immobilized in spotsvia amin coupling to the sensor surface. Each binding experiment was performed with 250 nM streptavidin and 90 nM CD40 ligand antibody dissolved in phosphate buffered saline. In the next test series, a functionalized sensor chip was bonded onto a 15 mm x 15 mm opening of the 75 mm x 25 mm x 2 mm microfluidic system. We demonstrate the functionality of the microfluidic system for filtering human blood such that only blood plasma was transported to the sensor chip. The results of first binding experiments in buffer with this test chip will be presented.

Hollow Core Bragg Waveguide Design and Fabrication for Enhanced Raman Spectroscopy

NASA Astrophysics Data System (ADS)

Ramanan, Janahan

Raman spectroscopy is a widely used technique to unambiguously ascertain the chemical composition of a sample. The caveat with this technique is its extremely weak optical cross-section, making it difficult to measure Raman signal with standard optical setups. In this thesis, a novel hollow core Bragg Reflection Waveguide was designed to simultaneously increase the generation and collection of Raman scattered photons. A robust fabrication process of this waveguide was developed employing flip-chip bonding methods to securely seal the hollow core channel. The waveguide air-core propagation loss was experimentally measured to be 0.17 dB/cm, and the Raman sensitivity limit was measured to be 3 mmol/L for glycerol solution. The waveguide was also shown to enhance Raman modes of standard household aerosols that could not be seen with other devices.

Lithographic chip identification: meeting the failure analysis challenge

NASA Astrophysics Data System (ADS)

Perkins, Lynn; Riddell, Kevin G.; Flack, Warren W.

1992-06-01

This paper describes a novel method using stepper photolithography to uniquely identify individual chips for permanent traceability. A commercially available 1X stepper is used to mark chips with an identifier or `serial number' which can be encoded with relevant information for the integrated circuit manufacturer. The permanent identification of individual chips can improve current methods of quality control, failure analysis, and inventory control. The need for this technology is escalating as manufacturers seek to provide six sigma quality control for their products and trace fabrication problems to their source. This need is especially acute for parts that fail after packaging and are returned to the manufacturer for analysis. Using this novel approach, failure analysis data can be tied back to a particular batch, wafer, or even a position within a wafer. Process control can be enhanced by identifying the root cause of chip failures. Chip identification also addresses manufacturers concerns with increasing incidences of chip theft. Since chips currently carry no identification other than the manufacturer's name and part number, recovery efforts are hampered by the inability to determine the sales history of a specific packaged chip. A definitive identifier or serial number for each chip would address this concern. The results of chip identification (patent pending) are easily viewed through a low power microscope. Batch number, wafer number, exposure step, and chip location within the exposure step can be recorded, as can dates and other items of interest. An explanation of the chip identification procedure and processing requirements are described. Experimental testing and results are presented, and potential applications are discussed.

Total integrated slidable and valveless solid phase extraction-polymerase chain reaction-capillary electrophoresis microdevice for mini Y chromosome short tandem repeat genotyping.

PubMed

Kim, Yong Tae; Lee, Dohwan; Heo, Hyun Young; Sim, Jeong Eun; Woo, Kwang Man; Kim, Do Hyun; Im, Sung Gap; Seo, Tae Seok

2016-04-15

A fully integrated slidable and valveless microsystem, which performs solid phase DNA extraction (SPE), micro-polymerase chain reaction (μPCR) and micro-capillary electrophoresis (μCE) coupled with a portable genetic analyser, has been developed for forensic genotyping. The use of a slidable chip, in which a 1 μL-volume of the PCR chamber was patterned at the center, does not necessitate any microvalves and tubing systems for fluidic control. The functional micro-units of SPE, μPCR, and μCE were fabricated on a single glass wafer by conventional photolithography, and the integrated microdevice consists of three layers: from top to bottom, a slidable chip, a channel wafer in which a SPE chamber, a mixing microchannel, and a CE microchannel were fabricated, and a Ti/Pt resistance temperature detector (RTD) wafer. The channel glass wafer and the RTD glass wafer were thermally bonded, and the slidable chip was placed on the designated functional unit. The entire process from the DNA extraction using whole human blood sample to identification of target Y chromosomal short tandem repeat (STR) loci was serially carried out with simply sliding the slidable chamber from one to another functional unit. Monoplex and multiplex detection of amelogenin and mini Y STR loci were successfully analysed on the integrated slidable SPE-μPCR-μCE microdevice by using 1 μL whole human blood within 60 min. The proposed advanced genetic analysis microsystem is capable of point-of-care DNA testing with sample-in-answer-out capability, more importantly, without use of complicated microvalves and microtubing systems for liquid transfer. Copyright © 2015 Elsevier B.V. All rights reserved.

Low-voltage high-performance silicon photonic devices and photonic integrated circuits operating up to 30 Gb/s.

PubMed

Kim, Gyungock; Park, Jeong Woo; Kim, In Gyoo; Kim, Sanghoon; Kim, Sanggi; Lee, Jong Moo; Park, Gun Sik; Joo, Jiho; Jang, Ki-Seok; Oh, Jin Hyuk; Kim, Sun Ae; Kim, Jong Hoon; Lee, Jun Young; Park, Jong Moon; Kim, Do-Won; Jeong, Deog-Kyoon; Hwang, Moon-Sang; Kim, Jeong-Kyoum; Park, Kyu-Sang; Chi, Han-Kyu; Kim, Hyun-Chang; Kim, Dong-Wook; Cho, Mu Hee

2011-12-19

We present high performance silicon photonic circuits (PICs) defined for off-chip or on-chip photonic interconnects, where PN depletion Mach-Zehnder modulators and evanescent-coupled waveguide Ge-on-Si photodetectors were monolithically integrated on an SOI wafer with CMOS-compatible process. The fabricated silicon PIC(off-chip) for off-chip optical interconnects showed operation up to 30 Gb/s. Under differential drive of low-voltage 1.2 V(pp), the integrated 1 mm-phase-shifter modulator in the PIC(off-chip) demonstrated an extinction ratio (ER) of 10.5dB for 12.5 Gb/s, an ER of 9.1dB for 20 Gb/s, and an ER of 7.2 dB for 30 Gb/s operation, without adoption of travelling-wave electrodes. The device showed the modulation efficiency of V(π)L(π) ~1.59 Vcm, and the phase-shifter loss of 3.2 dB/mm for maximum optical transmission. The Ge photodetector, which allows simpler integration process based on reduced pressure chemical vapor deposition exhibited operation over 30 Gb/s with a low dark current of 700 nA at -1V. The fabricated silicon PIC(intra-chip) for on-chip (intra-chip) photonic interconnects, where the monolithically integrated modulator and Ge photodetector were connected by a silicon waveguide on the same chip, showed on-chip data transmissions up to 20 Gb/s, indicating potential application in future silicon on-chip optical network. We also report the performance of the hybrid silicon electronic-photonic IC (EPIC), where a PIC(intra-chip) chip and 0.13μm CMOS interface IC chips were hybrid-integrated.

TAB interconnects for space concentrator solar cell arrays

NASA Technical Reports Server (NTRS)

Avery, J.; Bauman, J. S.; Gallagher, P.; Yerkes, J. W.

1993-01-01

The Boeing Company has evaluated the use of Tape Automated Bonding (TAB) and Surface Mount Technology (SMT) for a highly reliable, low cost interconnect for concentrator solar cell arrays. TAB and SMT are currently used in the electronics industry for chip interconnects and printed circuit board assembly. TAB tape consists of sixty-four 3-mil/1-oz tin-plated copper leads on 8-mil centers. The leads are thermocompression gang bonded to GaAs concentrator solar cell with silver contacts. This bond, known as an Inner Lead Bond (ILB), allows for pretesting and sorting capability via nondestruct wire bond pull and flash testing. Destructive wire pull tests resulted in preferred mid-span failures. Improvements in fill factor were attributed to decreased contact resistance on TAB bonded cells. Preliminary thermal cycling and aging tests were shown excellent bond strength and metallurgical results. Auger scans of bond sites reveals an Ag-Cu-Tin composition. Improper bonds are identified through flash testing as a performance degradation. On going testing of cells are underway at Lewis Research Center. SMT techniques are utilized to excise and form TAB leads post ILB. The formed leads' shape isolates thermal mismatches between the cells and the flex circuit they are mounted on. TABed cells are picked and placed with a gantry x-y-z positioning system with pattern recognition. Adhesives are selected to avoid thermal expansion mismatch and promote thermal transfer to the flex circuit. TAB outer lead bonds are parallel gap welded (PGW) to the flex circuit to finish the concentrator solar cell subassembly.

Chip design for thin-film deep ultraviolet LEDs fabricated by laser lift-off of the sapphire substrate

NASA Astrophysics Data System (ADS)

Cho, H. K.; Krüger, O.; Külberg, A.; Rass, J.; Zeimer, U.; Kolbe, T.; Knauer, A.; Einfeldt, S.; Weyers, M.; Kneissl, M.

2017-12-01

We report on a chip design which allows the laser lift-off (LLO) of the sapphire substrate sustaining the epitaxial film of flip-chip mounted deep ultraviolet light emitting diodes. A nanosecond pulsed excimer laser with a wavelength of 248 nm was used for the LLO. A mechanically stable chip design was found to be the key to prevent crack formation in the epitaxial layers and material chipping during the LLO process. Stabilization was achieved by introducing a Ti/Au leveling layer that mechanically supports the fragile epitaxial film. The electrical and optical characterization of devices before and after the LLO process shows that the device performance did not degrade by the LLO.

Ultra-High-Speed DNA Fragment Separations Using Microfabricated Capillary Array Electrophoresis Chips

NASA Astrophysics Data System (ADS)

Woolley, Adam T.; Mathies, Richard A.

1994-11-01

Capillary electrophoresis arrays have been fabricated on planar glass substrates by photolithographic masking and chemical etching techniques. The photolithographically defined channel patterns were etched in a glass substrate, and then capillaries were formed by thermally bonding the etched substrate to a second glass slide. High-resolution electrophoretic separations of φX174 Hae III DNA restriction fragments have been performed with these chips using a hydroxyethyl cellulose sieving matrix in the channels. DNA fragments were fluorescently labeled with dye in the running buffer and detected with a laser-excited, confocal fluorescence system. The effects of variations in the electric field, procedures for injection, and sizes of separation and injection channels (ranging from 30 to 120 μm) have been explored. By use of channels with an effective length of only 3.5 cm, separations of φX174 Hae III DNA fragments from ≈70 to 1000 bp are complete in only 120 sec. We have also demonstrated high-speed sizing of PCR-amplified HLA-DQα alleles. This work establishes methods for high-speed, high-throughput DNA separations on capillary array electrophoresis chips.

Electromigration Failure Mechanism in Sn-Cu Solder Alloys with OSP Cu Surface Finish

NASA Astrophysics Data System (ADS)

Chu, Ming-Hui; Liang, S. W.; Chen, Chih; Huang, Annie T.

2012-09-01

Organic solderable preservative (OSP) has been adopted as the Cu substrate surface finish in flip-chip solder joints for many years. In this study, the electromigration behavior of lead-free Sn-Cu solder alloys with thin-film under bump metallization and OSP surface finish was investigated. The results showed that severe damage occurred on the substrate side (cathode side), whereas the damage on the chip side (cathode side) was not severe. The damage on the substrate side included void formation, copper dissolution, and formation of intermetallic compounds (IMCs). The OSP Cu interface on the substrate side became the weakest point in the solder joint even when thin-film metallization was used on the chip side. Three-dimensional simulations were employed to investigate the current density distribution in the area between the OSP Cu surface finish and the solder. The results indicated that the current density was higher along the periphery of the bonding area between the solder and the Cu pad, consistent with the area of IMC and void formation in our experimental results.

Kansas Department of Transportation 2014 chip seal manual.

DOT National Transportation Integrated Search

2014-03-01

A chip seal is a very effective thin surface treatment process used by maintenance managers to : preserve existing asphalt pavements. The Kansas Department of Transportation (KDOT) 2014 Chip Seal : Manual is a guide that provides guidelines, backgrou...

Synthesis and interface characterization of CNTs on graphene

NASA Astrophysics Data System (ADS)

Zhou, Changjian; Senegor, Richard; Baron, Zachary; Chen, Yihan; Raju, Salahuddin; Vyas, Anshul A.; Chan, Mansun; Chai, Yang; Yang, Cary Y.

2017-02-01

Carbon nanotubes (CNTs) and graphene are potential candidates for future interconnect materials. CNTs are promising on-chip via interconnect materials due to their readily formed vertical structures, their current-carrying capacity, which is much larger than existing on-chip interconnect materials such as copper and tungsten, and their demonstrated ability to grow in patterned vias with sub-50 nm widths; meanwhile, graphene is suitable for horizontal interconnects. However, they both present the challenge of having high-resistance contacts with other conductors. An all-carbon structure is proposed in this paper, which can be formed using the same chemical vapor deposition method for both CNTs and graphene. Vertically aligned CNTs are grown directly on graphene with an Fe or Ni catalyst. The structural characteristics of the graphene and the grown CNTs are analyzed using Raman spectroscopy and electron microscopy techniques. The CNT-graphene interface is studied in detail using transmission electron microscopic analysis of the CNT-graphene heterostructure, which suggests C-C bonding between the two materials. Electrical measurement results confirm the existence of both a lateral conduction path within graphene and a vertical conduction path in the CNT-graphene heterostructure, giving further support to the C-C bonding at the CNT-graphene interface and resulting in potential applications for all-carbon interconnects.

Synthesis and interface characterization of CNTs on graphene.

PubMed

Zhou, Changjian; Senegor, Richard; Baron, Zachary; Chen, Yihan; Raju, Salahuddin; Vyas, Anshul A; Chan, Mansun; Chai, Yang; Yang, Cary Y

2017-02-03

Carbon nanotubes (CNTs) and graphene are potential candidates for future interconnect materials. CNTs are promising on-chip via interconnect materials due to their readily formed vertical structures, their current-carrying capacity, which is much larger than existing on-chip interconnect materials such as copper and tungsten, and their demonstrated ability to grow in patterned vias with sub-50 nm widths; meanwhile, graphene is suitable for horizontal interconnects. However, they both present the challenge of having high-resistance contacts with other conductors. An all-carbon structure is proposed in this paper, which can be formed using the same chemical vapor deposition method for both CNTs and graphene. Vertically aligned CNTs are grown directly on graphene with an Fe or Ni catalyst. The structural characteristics of the graphene and the grown CNTs are analyzed using Raman spectroscopy and electron microscopy techniques. The CNT-graphene interface is studied in detail using transmission electron microscopic analysis of the CNT-graphene heterostructure, which suggests C-C bonding between the two materials. Electrical measurement results confirm the existence of both a lateral conduction path within graphene and a vertical conduction path in the CNT-graphene heterostructure, giving further support to the C-C bonding at the CNT-graphene interface and resulting in potential applications for all-carbon interconnects.

Single-chip microprocessor that communicates directly using light

NASA Astrophysics Data System (ADS)

Sun, Chen; Wade, Mark T.; Lee, Yunsup; Orcutt, Jason S.; Alloatti, Luca; Georgas, Michael S.; Waterman, Andrew S.; Shainline, Jeffrey M.; Avizienis, Rimas R.; Lin, Sen; Moss, Benjamin R.; Kumar, Rajesh; Pavanello, Fabio; Atabaki, Amir H.; Cook, Henry M.; Ou, Albert J.; Leu, Jonathan C.; Chen, Yu-Hsin; Asanović, Krste; Ram, Rajeev J.; Popović, Miloš A.; Stojanović, Vladimir M.

2015-12-01

Data transport across short electrical wires is limited by both bandwidth and power density, which creates a performance bottleneck for semiconductor microchips in modern computer systems—from mobile phones to large-scale data centres. These limitations can be overcome by using optical communications based on chip-scale electronic-photonic systems enabled by silicon-based nanophotonic devices8. However, combining electronics and photonics on the same chip has proved challenging, owing to microchip manufacturing conflicts between electronics and photonics. Consequently, current electronic-photonic chips are limited to niche manufacturing processes and include only a few optical devices alongside simple circuits. Here we report an electronic-photonic system on a single chip integrating over 70 million transistors and 850 photonic components that work together to provide logic, memory, and interconnect functions. This system is a realization of a microprocessor that uses on-chip photonic devices to directly communicate with other chips using light. To integrate electronics and photonics at the scale of a microprocessor chip, we adopt a ‘zero-change’ approach to the integration of photonics. Instead of developing a custom process to enable the fabrication of photonics, which would complicate or eliminate the possibility of integration with state-of-the-art transistors at large scale and at high yield, we design optical devices using a standard microelectronics foundry process that is used for modern microprocessors. This demonstration could represent the beginning of an era of chip-scale electronic-photonic systems with the potential to transform computing system architectures, enabling more powerful computers, from network infrastructure to data centres and supercomputers.

Single-chip microprocessor that communicates directly using light.

PubMed

Sun, Chen; Wade, Mark T; Lee, Yunsup; Orcutt, Jason S; Alloatti, Luca; Georgas, Michael S; Waterman, Andrew S; Shainline, Jeffrey M; Avizienis, Rimas R; Lin, Sen; Moss, Benjamin R; Kumar, Rajesh; Pavanello, Fabio; Atabaki, Amir H; Cook, Henry M; Ou, Albert J; Leu, Jonathan C; Chen, Yu-Hsin; Asanović, Krste; Ram, Rajeev J; Popović, Miloš A; Stojanović, Vladimir M

2015-12-24

Data transport across short electrical wires is limited by both bandwidth and power density, which creates a performance bottleneck for semiconductor microchips in modern computer systems--from mobile phones to large-scale data centres. These limitations can be overcome by using optical communications based on chip-scale electronic-photonic systems enabled by silicon-based nanophotonic devices. However, combining electronics and photonics on the same chip has proved challenging, owing to microchip manufacturing conflicts between electronics and photonics. Consequently, current electronic-photonic chips are limited to niche manufacturing processes and include only a few optical devices alongside simple circuits. Here we report an electronic-photonic system on a single chip integrating over 70 million transistors and 850 photonic components that work together to provide logic, memory, and interconnect functions. This system is a realization of a microprocessor that uses on-chip photonic devices to directly communicate with other chips using light. To integrate electronics and photonics at the scale of a microprocessor chip, we adopt a 'zero-change' approach to the integration of photonics. Instead of developing a custom process to enable the fabrication of photonics, which would complicate or eliminate the possibility of integration with state-of-the-art transistors at large scale and at high yield, we design optical devices using a standard microelectronics foundry process that is used for modern microprocessors. This demonstration could represent the beginning of an era of chip-scale electronic-photonic systems with the potential to transform computing system architectures, enabling more powerful computers, from network infrastructure to data centres and supercomputers.

Disposable world-to-chip interface for digital microfluidics

DOEpatents

Van Dam, R. Michael; Shah, Gaurav; Keng, Pei-Yuin

2017-05-16

The present disclosure sets forth incorporating microfluidic chips interfaces for use with digital microfluidic processes. Methods and devices according to the present disclosure utilize compact, integrated platforms that interface with a chip upstream and downstream of the reaction, as well as between intermediate reaction steps if needed. In some embodiments these interfaces are automated, including automation of a multiple reagent process. Various reagent delivery systems and methods are also disclosed.

Design of an MR image processing module on an FPGA chip

NASA Astrophysics Data System (ADS)

Li, Limin; Wyrwicz, Alice M.

2015-06-01

We describe the design and implementation of an image processing module on a single-chip Field-Programmable Gate Array (FPGA) for real-time image processing. We also demonstrate that through graphical coding the design work can be greatly simplified. The processing module is based on a 2D FFT core. Our design is distinguished from previously reported designs in two respects. No off-chip hardware resources are required, which increases portability of the core. Direct matrix transposition usually required for execution of 2D FFT is completely avoided using our newly-designed address generation unit, which saves considerable on-chip block RAMs and clock cycles. The image processing module was tested by reconstructing multi-slice MR images from both phantom and animal data. The tests on static data show that the processing module is capable of reconstructing 128 × 128 images at speed of 400 frames/second. The tests on simulated real-time streaming data demonstrate that the module works properly under the timing conditions necessary for MRI experiments.

Design of an MR image processing module on an FPGA chip

PubMed Central

Li, Limin; Wyrwicz, Alice M.

2015-01-01

We describe the design and implementation of an image processing module on a single-chip Field-Programmable Gate Array (FPGA) for real-time image processing. We also demonstrate that through graphical coding the design work can be greatly simplified. The processing module is based on a 2D FFT core. Our design is distinguished from previously reported designs in two respects. No off-chip hardware resources are required, which increases portability of the core. Direct matrix transposition usually required for execution of 2D FFT is completely avoided using our newly-designed address generation unit, which saves considerable on-chip block RAMs and clock cycles. The image processing module was tested by reconstructing multi-slice MR images from both phantom and animal data. The tests on static data show that the processing module is capable of reconstructing 128 × 128 images at speed of 400 frames/second. The tests on simulated real-time streaming data demonstrate that the module works properly under the timing conditions necessary for MRI experiments. PMID:25909646

Associative architecture for image processing

NASA Astrophysics Data System (ADS)

Adar, Rutie; Akerib, Avidan

1997-09-01

This article presents a new generation in parallel processing architecture for real-time image processing. The approach is implemented in a real time image processor chip, called the XiumTM-2, based on combining a fully associative array which provides the parallel engine with a serial RISC core on the same die. The architecture is fully programmable and can be programmed to implement a wide range of color image processing, computer vision and media processing functions in real time. The associative part of the chip is based on patented pending methodology of Associative Computing Ltd. (ACL), which condenses 2048 associative processors, each of 128 'intelligent' bits. Each bit can be a processing bit or a memory bit. At only 33 MHz and 0.6 micron manufacturing technology process, the chip has a computational power of 3 billion ALU operations per second and 66 billion string search operations per second. The fully programmable nature of the XiumTM-2 chip enables developers to use ACL tools to write their own proprietary algorithms combined with existing image processing and analysis functions from ACL's extended set of libraries.

Prediction of 3D chip formation in the facing cutting with lathe machine using FEM

NASA Astrophysics Data System (ADS)

Prasetyo, Yudhi; Tauviqirrahman, Mohamad; Rusnaldy

2016-04-01

This paper presents the prediction of the chip formation at the machining process using a lathe machine in a more specific way focusing on facing cutting (face turning). The main purpose is to propose a new approach to predict the chip formation with the variation of the cutting directions i.e., the backward and forward direction. In addition, the interaction between stress analysis and chip formation on cutting process was also investigated. The simulations were conducted using three dimensional (3D) finite element method based on ABAQUS software with aluminum and high speed steel (HSS) as the workpiece and the tool materials, respectively. The simulation result showed that the chip resulted using a backward direction depicts a better formation than that using a conventional (forward) direction.

Comminution process to produce precision wood particles of uniform size and shape with disrupted grain structure from wood chips

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dooley, James H; Lanning, David N

A process of comminution of wood chips (C) having a grain direction to produce a mixture of wood particles (P), wherein the wood chips are characterized by an average length dimension (L.sub.C) as measured substantially parallel to the grain, an average width dimension (W.sub.C) as measured normal to L.sub.C and aligned cross grain, and an average height dimension (H.sub.C) as measured normal to W.sub.C and L.sub.C, and wherein the comminution process comprises the step of feeding the wood chips in a direction of travel substantially randomly to the grain direction through a counter rotating pair of intermeshing arrays of cuttingmore » discs (D) arrayed axially perpendicular to the direction of wood chip travel, wherein the cutting discs have a uniform thickness (T.sub.D), and wherein at least one of L.sub.C, W.sub.C, and H.sub.C is greater than T.sub.D.« less

Fish swarm intelligent to optimize real time monitoring of chips drying using machine vision

NASA Astrophysics Data System (ADS)

Hendrawan, Y.; Hawa, L. C.; Damayanti, R.

2018-03-01

This study attempted to apply machine vision-based chips drying monitoring system which is able to optimise the drying process of cassava chips. The objective of this study is to propose fish swarm intelligent (FSI) optimization algorithms to find the most significant set of image features suitable for predicting water content of cassava chips during drying process using artificial neural network model (ANN). Feature selection entails choosing the feature subset that maximizes the prediction accuracy of ANN. Multi-Objective Optimization (MOO) was used in this study which consisted of prediction accuracy maximization and feature-subset size minimization. The results showed that the best feature subset i.e. grey mean, L(Lab) Mean, a(Lab) energy, red entropy, hue contrast, and grey homogeneity. The best feature subset has been tested successfully in ANN model to describe the relationship between image features and water content of cassava chips during drying process with R2 of real and predicted data was equal to 0.9.

Effect of ultrasound dielectric pretreatment on the oxidation resistance of vacuum-fried apple chips.

PubMed

Shen, Xu; Zhang, Min; Bhandari, Bhesh; Guo, Zhimei

2018-02-15

In order to investigate the effect of ultrasound dielectric pretreatment on the oxidation resistance of vacuum-fried apple chips, apple slices were pretreated at ultrasonic powers of 150, 250 and 400 W for times of 10, 20 and 30 min before vacuum frying. The quality and oxidation resistance of fried apple were evaluated by testing the dielectric properties and comparing the moisture content, oil uptake, color, acid value (AV) and peroxide value (PV) of apple chips. Ultrasonic treatment significantly changed the dielectric properties of apple slices. Moisture and oil contents of apple chips decreased with increasing ultrasonic power and time. During storage, the color retention of fried apple chips processed by ultrasound was improved. AV and PV values of fried apple chips processed by ultrasound were lower, which improved their antioxidant properties. The results of the present study indicated that ultrasound dielectric pretreatment improved not only the quality of vacuum-fried apple chips but also their antioxidant properties. © 2018 Society of Chemical Industry. © 2018 Society of Chemical Industry.

Research and development of biochip technologies in Taiwan

NASA Astrophysics Data System (ADS)

Ting, Solomon J.; Chiou, Arthur E. T.

2000-07-01

Recent advancements in several genome-sequencing projects have stimulated an enormous interest in microarray DNA chip technology, especially in the biomedical sciences and pharmaceutical industries. The DNA chips facilitated the miniaturization of conventional nucleic acid hybridizations, by either robotically spotting thousands of library cDNAs or in situ synthesis of high-density oligonucleotides onto solid supports. These innovations have found a wide range of applications in molecular biology, especially in studying gene expression and discovering new genes from the global view of genomic analysis. The research and development of this powerful tool has also received great attentions in Taiwan. In this paper, we report the current progresses of our DNA chip project, along with the current status of other biochip projects in Taiwan, such as protein chip, PCR chip, electrophoresis chip, olfactory chip, etc. The new development of biochip technologies integrates the biotechnology with the semiconductor processing, the micro- electro-mechanical, optoelectronic, and digital signal processing technologies. Most of these biochip technologies utilitze optical detection methods for data acquisition and analysis. The strengths and advantages of different approaches are compared and discussed in this report.

Towards an integrated optofluidic system for highly sensitive detection of antibiotics in seawater incorporating bimodal waveguide photonic biosensors and complex, active microfluidics

NASA Astrophysics Data System (ADS)

Szydzik, C.; Gavela, A. F.; Roccisano, J.; Herranz de Andrés, S.; Mitchell, A.; Lechuga, L. M.

2016-12-01

We present recent results on the realisation and demonstration of an integrated optofluidic lab-on-a-chip measurement system. The system consists of an integrated on-chip automated microfluidic fluid handling subsystem, coupled with bimodal nano-interferometer waveguide technology, and is applied in the context of detection of antibiotics in seawater. The bimodal waveguide (BMWG) is a highly sensitive label-free biosensor. Integration of complex microfluidic systems with bimodal waveguide technology enables on-chip sample handling and fluid processing capabilities and allows for significant automation of experimental processes. The on-chip fluid-handling subsystem is realised through the integration of pneumatically actuated elastomer pumps and valves, enabling high temporal resolution sample and reagent delivery and facilitating multiplexed detection processes.

An Analysis of the Effects of Chip-groove Geometry on Machining Performance Using Finite Element Methods

NASA Astrophysics Data System (ADS)

Ee, K. C.; Dillon, O. W.; Jawahir, I. S.

2004-06-01

This paper discusses the influence of major chip-groove parameters of a cutting tool on the chip formation process in orthogonal machining using finite element (FE) methods. In the FE formulation, a thermal elastic-viscoplastic material model is used together with a modified Johnson-Cook material law for the flow stress. The chip back-flow angle and the chip up-curl radius are calculated for a range of cutting conditions by varying the chip-groove parameters. The analysis provides greater understanding of the effectiveness of chip-groove configurations and points a way to correlate cutting conditions with tool-wear when machining with a grooved cutting tool.

77 FR 22760 - Proposed Information Collection; Comment Request; Southeast Region Gulf of Mexico Electronic...

Federal Register 2010, 2011, 2012, 2013, 2014

2012-04-17

... electronic logbook memory chip will be removed from the unit and downloaded at the contractor site in College Station, Texas. A new logbook memory chip will replace the removed memory chip, a process taking less than...

New Surface-Enhanced Raman Sensing Chip Designed for On-Site Detection of Active Ricin in Complex Matrices Based on Specific Depurination.

PubMed

Tang, Ji-Jun; Sun, Jie-Fang; Lui, Rui; Zhang, Zong-Mian; Liu, Jing-Fu; Xie, Jian-Wei

2016-01-27

Quick and accurate on-site detection of active ricin has very important realistic significance in view of national security and defense. In this paper, optimized single-stranded oligodeoxynucleotides named poly(21dA), which function as a depurination substrate of active ricin, were screened and chemically attached on gold nanoparticles (AuNPs, ∼100 nm) via the Au-S bond [poly(21dA)-AuNPs]. Subsequently, poly(21dA)-AuNPs were assembled on a dihydrogen lipoic-acid-modified Si wafer (SH-Si), thus forming the specific surface-enhanced Raman spectroscopy (SERS) chip [poly(21dA)-AuNPs@SH-Si] for depurination of active ricin. Under optimized conditions, active ricin could specifically hydrolyze multiple adenines from poly(21dA) on the chip. This depurination-induced composition change could be conveniently monitored by measuring the distinct attenuation of the SERS signature corresponding to adenine. To improve sensitivity of this method, a silver nanoshell was deposited on post-reacted poly(21dA)-AuNPs, which lowered the limit of detection to 8.9 ng mL(-1). The utility of this well-controlled SERS chip was successfully demonstrated in food and biological matrices spiked with different concentrations of active ricin, thus showing to be very promising assay for reliable and rapid on-site detection of active ricin.

Mean-time-to-failure study of flip chip solder joints on Cu/Ni(V)/Al thin-film under-bump-metallization

NASA Astrophysics Data System (ADS)

Choi, W. J.; Yeh, E. C. C.; Tu, K. N.

2003-11-01

Electromigration of eutectic SnPb flip chip solder joints and their mean-time-to-failure (MTTF) have been studied in the temperature range of 100 to 140 °C with current densities of 1.9 to 2.75×104 A/cm2. In these joints, the under-bump-metallization (UBM) on the chip side is a multilayer thin film of Al/Ni(V)/Cu, and the metallic bond-pad on the substrate side is a very thick, electroless Ni layer covered with 30 nm of Au. When stressed at the higher current densities, the MTTF was found to decrease much faster than what is expected from the published Black's equation. The failure occurred by interfacial void propagation at the cathode side, and it is due to current crowding near the contact interface between the solder bump and the thin-film UBM. The current crowding is confirmed by a simulation of current distribution in the solder joint. Besides the interfacial void formation, the intermetallic compounds formed on the UBM as well as the Ni(V) film in the UBM have been found to dissolve completely into the solder bump during electromigration. Therefore, the electromigation failure is a combination of the interfacial void formation and the loss of UBM. Similar findings in eutectic SnAgCu flip chip solder joints have also been obtained and compared.

Design and qualification of the SEU/TD Radiation Monitor chip

NASA Technical Reports Server (NTRS)

Buehler, Martin G.; Blaes, Brent R.; Soli, George A.; Zamani, Nasser; Hicks, Kenneth A.

1992-01-01

This report describes the design, fabrication, and testing of the Single-Event Upset/Total Dose (SEU/TD) Radiation Monitor chip. The Radiation Monitor is scheduled to fly on the Mid-Course Space Experiment Satellite (MSX). The Radiation Monitor chip consists of a custom-designed 4-bit SRAM for heavy ion detection and three MOSFET's for monitoring total dose. In addition the Radiation Monitor chip was tested along with three diagnostic chips: the processor monitor and the reliability and fault chips. These chips revealed the quality of the CMOS fabrication process. The SEU/TD Radiation Monitor chip had an initial functional yield of 94.6 percent. Forty-three (43) SEU SRAM's and 14 Total Dose MOSFET's passed the hermeticity and final electrical tests and were delivered to LL.

Proceedings of the ECOM Hybrid Microcircuit Symposium, 1976

DTIC Science & Technology

1976-06-01

remove both stationary and moving clutter. The hex fast line receiver micrýocircuit is a thin film chip-and-wire microcircuit (shown in Figure 7) which...of the following: (a) multiple usage, (b) high volume production, or (c) moderate volume and multiple usage. These criteria are not hard and fast ...compounding when the circuit complexity increases. O particular concern are open or intermittent bonds, susceptibility to moisture and impurities in the

Hybrid-integrated coherent receiver using silica-based planar lightwave circuit technology

NASA Astrophysics Data System (ADS)

Kim, Jong-Hoi; Choe, Joong-Seon; Choi, Kwang-Seong; Youn, Chun-Ju; Kim, Duk-Jun; Jang, Sun-Hyok; Kwon, Yong-Hwan; Nam, Eun-Soo

2011-12-01

A hybrid-integrated coherent receiver module has been achieved using flip-chip bonding technology, consisting of a silica-based 90°-hybrid planar lightwave circuit (PLC) platform, a spot-size converter integrated waveguide photodiode (SSC-WG-PD), and a dual-channel transimpedance amplifier (TIA). The receiver module shows error-free operation up to 40Gb/s and OSNR sensitivity of 11.5 dB for BER = 10-3 at 25 Gb/s.

Imaging performance of a Timepix detector based on semi-insulating GaAs

NASA Astrophysics Data System (ADS)

Zaťko, B.; Zápražný, Z.; Jakůbek, J.; Šagátová, A.; Boháček, P.; Sekáčová, M.; Korytár, D.; Nečas, V.; Žemlička, J.; Mora, Y.; Pichotka, M.

2018-01-01

This work focused on a Timepix chip [1] coupled with a bulk semi-insulating GaAs sensor. The sensor consisted of a matrix of 256 × 256 pixels with a pitch of 55 μm bump-bonded to a Timepix ASIC. The sensor was processed on a 350 μm-thick SI GaAs wafer. We carried out detector adjustment to optimize its performance. This included threshold equalization with setting up parameters of the Timepix chip, such as Ikrum, Pream, Vfbk, and so on. The energy calibration of the GaAs Timepix detector was realized using a 241Am radioisotope in two Timepix detector modes: time-over-threshold and threshold scan. An energy resolution of 4.4 keV in FWHM (Full Width at Half Maximum) was observed for 59.5 keV γ-photons using threshold scan mode. The X-ray imaging quality of the GaAs Timepix detector was tested using various samples irradiated by an X-ray source with a focal spot size smaller than 8 μm and accelerating voltage up to 80 kV. A 700 μm × 700 μm gold testing object (X-500-200-16Au with Siemens star) fabricated with high precision was used for the spatial resolution testing at different values of X-ray image magnification (up to 45). The measured spatial resolution of our X-ray imaging system was about 4 μm.

Microfluidics for Synthetic Biology: From Design to Execution

PubMed Central

Ferry, M. S.; Razinkov, I. A.; Hasty, J.

2016-01-01

With the expanding interest in cellular responses to dynamic environments, microfluidic devices have become important experimental platforms for biological research. Microfluidic “microchemostat” devices enable precise environmental control while capturing high quality, single-cell gene expression data. For studies of population heterogeneity and gene expression noise, these abilities are crucial. Here, we describe the necessary steps for experimental microfluidics using devices created in our lab as examples. First, we discuss the rational design of microchemostats and the tools available to predict their performance. We carefully analyze the critical parts of an example device, focusing on the most important part of any microchemostat: the cell trap. Next, we present a method for generating on-chip dynamic environments using an integrated fluidic junction coupled to linear actuators. Our system relies on the simple modulation of hydrostatic pressure to alter the mixing ratio between two source reservoirs and we detail the software and hardware behind it. To expand the throughput of microchemostat experiments, we describe how to build larger, parallel versions of simpler devices. To analyze the large amounts of data, we discuss methods for automated cell tracking, focusing on the special problems presented by Saccharomyces cerevisiae cells. The manufacturing of microchemostats is described in complete detail: from the photolithographic processing of the wafer to the final bonding of the PDMS chip to glass coverslip. Finally, the procedures for conducting Escherichia coli and S. cerevisiae microchemostat experiments are addressed. PMID:21601093

Suppression of the vacuolar invertase gene delays senescent sweetening in chipping potatoes

USDA-ARS?s Scientific Manuscript database

Background: Potato chip processors require potato tubers that meet quality specifications for fried chip color, and color depends largely upon tuber sugar contents. At later times in storage, potatoes accumulate sucrose, glucose and fructose. This developmental process, senescent sweetening, manifes...

Design and fabrication of metal briquette machine for shop floor

NASA Astrophysics Data System (ADS)

Pramod, R.; Kumar, G. B. Veeresh; Prashanth B., N.

2017-07-01

Efforts have to be taken to ensure efficient waste management system in shop floors, with minimum utilization of space and energy when it comes to disposing metal chips formed during machining processes. The salvaging of junk metallic chips and the us e of scrap are important for the economic production of a steelworks. For this purpose, we have fabricated a metal chip compaction machine, which can compact the metal chips into small briquettes. The project started with the survey of chips formed in shop floors and the practices involved in waste management. Study was done on the requirements for a better compaction. The heating chamber was designed taking into consideration the temperature required for an easy compaction of the metal chips. The power source for compaction and the pneumatic design for mechanism was done following the appropriate calculations regarding the air pressure provided and thrust required. The processes were tested under different conditions and found effective. The fabrication of the machine has been explained in detail and the results have been discussed.

Rapid wasted-free microfluidic fabrication based on ink-jet approach for microfluidic sensing applications

NASA Astrophysics Data System (ADS)

Jarujareet, Ungkarn; Amarit, Rattasart; Sumriddetchkajorn, Sarun

2016-11-01

Realizing that current microfluidic chip fabrication techniques are time consuming and labor intensive as well as always have material leftover after chip fabrication, this research work proposes an innovative approach for rapid microfluidic chip production. The key idea relies on a combination of a widely-used inkjet printing method and a heat-based polymer curing technique with an electronic-mechanical control, thus eliminating the need of masking and molds compared to typical microfluidic fabrication processes. In addition, as the appropriate amount of polymer is utilized during printing, there is much less amount of material wasted. Our inkjet-based microfluidic printer can print out the desired microfluidic chip pattern directly onto a heated glass surface, where the printed polymer is suddenly cured. Our proof-of-concept demonstration for widely-used single-flow channel, Y-junction, and T-junction microfluidic chips shows that the whole microfluidic chip fabrication process requires only 3 steps with a fabrication time of 6 minutes.

Evaluation of hardware costs of implementing PSK signal detection circuit based on "system on chip"

NASA Astrophysics Data System (ADS)

Sokolovskiy, A. V.; Dmitriev, D. D.; Veisov, E. A.; Gladyshev, A. B.

2018-05-01

The article deals with the choice of the architecture of digital signal processing units for implementing the PSK signal detection scheme. As an assessment of the effectiveness of architectures, the required number of shift registers and computational processes are used when implementing the "system on a chip" on the chip. A statistical estimation of the normalized code sequence offset in the signal synchronization scheme for various hardware block architectures is used.

Characterization and partitioning of the char ash collected after the processing of pine wood chips in a pilot-scale gasification unit

Treesearch

Thomas L. Eberhardt; Hui Pan; Leslie H. Groom; Chi-Leung So

2011-01-01

Southern yellow pine wood chips were used as the feedstock for a pilot-scale gasification unit coupled with a 25 kW generator. The pulp-grade wood chips were relatively free of bark and low in ash content. Processing this feedstock yielded a black/sooty by-product that upon combustion in a muffle furnace resulted in an ash content of about 48%. The term "char ash...

Adiabatic shear mechanisms for the hard cutting process

NASA Astrophysics Data System (ADS)

Yue, Caixu; Wang, Bo; Liu, Xianli; Feng, Huize; Cai, Chunbin

2015-05-01

The most important consequence of adiabatic shear phenomenon is formation of sawtooth chip. Lots of scholars focused on the formation mechanism of sawtooth, and the research often depended on experimental approach. For the present, the mechanism of sawtooth chip formation still remains some ambiguous aspects. This study develops a combined numerical and experimental approach to get deeper understanding of sawtooth chip formation mechanism for Polycrystalline Cubic Boron Nitride (PCBN) tools orthogonal cutting hard steel GCr15. By adopting the Johnson-Cook material constitutive equations, the FEM simulation model established in this research effectively overcomes serious element distortions and cell singularity in high strain domain caused by large material deformation, and the adiabatic shear phenomenon is simulated successfully. Both the formation mechanism and process of sawtooth are simulated. Also, the change features regarding the cutting force as well as its effects on temperature are studied. More specifically, the contact of sawtooth formation frequency with cutting force fluctuation frequency is established. The cutting force and effect of cutting temperature on mechanism of adiabatic shear are investigated. Furthermore, the effects of the cutting condition on sawtooth chip formation are researched. The researching results show that cutting feed has the most important effect on sawtooth chip formation compared with cutting depth and speed. This research contributes a better understanding of mechanism, feature of chip formation in hard turning process, and supplies theoretical basis for the optimization of hard cutting process parameters.

Sequence information signal processor for local and global string comparisons

DOEpatents

Peterson, John C.; Chow, Edward T.; Waterman, Michael S.; Hunkapillar, Timothy J.

1997-01-01

A sequence information signal processing integrated circuit chip designed to perform high speed calculation of a dynamic programming algorithm based upon the algorithm defined by Waterman and Smith. The signal processing chip of the present invention is designed to be a building block of a linear systolic array, the performance of which can be increased by connecting additional sequence information signal processing chips to the array. The chip provides a high speed, low cost linear array processor that can locate highly similar global sequences or segments thereof such as contiguous subsequences from two different DNA or protein sequences. The chip is implemented in a preferred embodiment using CMOS VLSI technology to provide the equivalent of about 400,000 transistors or 100,000 gates. Each chip provides 16 processing elements, and is designed to provide 16 bit, two's compliment operation for maximum score precision of between -32,768 and +32,767. It is designed to provide a comparison between sequences as long as 4,194,304 elements without external software and between sequences of unlimited numbers of elements with the aid of external software. Each sequence can be assigned different deletion and insertion weight functions. Each processor is provided with a similarity measure device which is independently variable. Thus, each processor can contribute to maximum value score calculation using a different similarity measure.

A proposed holistic approach to on-chip, off-chip, test, and package interconnections

NASA Astrophysics Data System (ADS)

Bartelink, Dirk J.

1998-11-01

The term interconnection has traditionally implied a `robust' connection from a transistor or a group of transistors in an IC to the outside world, usually a PC board. Optimum system utilization is done from outside the IC. As an alternative, this paper addresses `unimpeded' transistor-to-transistor interconnection aimed at reaching the high circuit densities and computational capabilities of neighboring IC's. In this view, interconnections are not made to some human-centric place outside the IC world requiring robustness—except for system input and output connections. This unimpeded interconnect style is currently available only through intra-chip signal traces in `system-on-a-chip' implementations, as exemplified by embedded DRAMs. Because the traditional off-chip penalty in performance and wiring density is so large, a merging of complex process technologies is the only option today. It is suggested that, for system integration to move forward, the traditional robustness requirement inherited from conventional packaging interconnect and IC manufacturing test must be discarded. Traditional system assembly from vendor parts requires robustness under shipping, inspection and assembly. The trend toward systems on a chip signifies willingness by semiconductor companies to design and fabricate whole systems in house, so that `in-house' chip-to-chip assembly is not beyond reach. In this scenario, bare chips never leave the controlled environment of the IC fabricator while the two major contributors to off-chip signal penalty, ESD protection and the need to source a 50-ohm test head, are avoided. With in-house assembly, ESD protection can be eliminated with the precautions already familiar in plasma etching. Test interconnection impacts the fundamentals of IC manufacturing, particularly with clock speeds approaching 1GHz, and cannot be an afterthought. It should be an integral part of the chip-to-chip interconnection bandwidth optimization, because—as we must recognize—test is also performed using IC's. A system interconnection is proposed using multiple chips fabricated with conventional silicon processes, including MEMS technology. The system resembles an MCM that can be joined without committing to final assembly to perform at-speed testing. 50-Ohm test probes never load the circuit; only intended neighboring chips are ever connected. A `back-plane' chip provides the connection layers for both inter- and intra-chip signals and also serves as the probe card, in analogy with membrane probes now used for single-chip testing. Intra-chip connections, which require complicated connections during test that exactly match the product, are then properly made and all waveforms and loading conditions under test will be identical to those of the product. The major benefit is that all front-end chip technologies can be merged—logic, memory, RF, even passives. ESD protection is required only on external system connections. Manufacturing test information will accurately characterize process faults and thus avoid the Known-Good-Die problem that has slowed the arrival of conventional MCM's.

On-chip concentration of bacteria using a 3D dielectrophoretic chip and subsequent laser-based DNA extraction in the same chip

NASA Astrophysics Data System (ADS)

Cho, Yoon-Kyoung; Kim, Tae-hyeong; Lee, Jeong-Gun

2010-06-01

We report the on-chip concentration of bacteria using a dielectrophoretic (DEP) chip with 3D electrodes and subsequent laser-based DNA extraction in the same chip. The DEP chip has a set of interdigitated Au post electrodes with 50 µm height to generate a network of non-uniform electric fields for the efficient trapping by DEP. The metal post array was fabricated by photolithography and subsequent Ni and Au electroplating. Three model bacteria samples (Escherichia coli, Staphylococcus epidermidis, Streptococcus mutans) were tested and over 80-fold concentrations were achieved within 2 min. Subsequently, on-chip DNA extraction from the concentrated bacteria in the 3D DEP chip was performed by laser irradiation using the laser-irradiated magnetic bead system (LIMBS) in the same chip. The extracted DNA was analyzed with silicon chip-based real-time polymerase chain reaction (PCR). The total process of on-chip bacteria concentration and the subsequent DNA extraction can be completed within 10 min including the manual operation time.

Microfluidic lung airway-on-a-chip with arrayable suspended gels for studying epithelial and smooth muscle cell interactions.

PubMed

Humayun, Mouhita; Chow, Chung-Wai; Young, Edmond W K

2018-05-01

Chronic lung diseases (CLDs) are regulated by complex interactions between many different cell types residing in lung airway tissues. Specifically, interactions between airway epithelial cells (ECs) and airway smooth muscle cells (SMCs) have been shown in part to play major roles in the pathogenesis of CLDs, but the underlying molecular mechanisms are not well understood. To advance our understanding of lung pathophysiology and accelerate drug development processes, new innovative in vitro tissue models are needed that can reconstitute the complex in vivo microenvironment of human lung tissues. Organ-on-a-chip technologies have recently made significant strides in recapitulating physiological properties of in vivo lung tissue microenvironments. However, novel advancements are still needed to enable the study of airway SMC-EC communication with matrix interactions, and to provide higher throughput capabilities and manufacturability. We have developed a thermoplastic-based microfluidic lung airway-on-a-chip model that mimics the lung airway tissue microenvironment, and in particular, the interactions between SMCs, ECs, and supporting extracellular matrix (ECM). The microdevice is fabricated from acrylic using micromilling and solvent bonding techniques, and consists of three vertically stacked microfluidic compartments with a bottom media reservoir for SMC culture, a middle thin hydrogel layer, and an upper microchamber for achieving air-liquid interface (ALI) culture of the epithelium. A unique aspect of the design lies in the suspended hydrogel with upper and lower interfaces for EC and SMC culture, respectively. A mixture of type I collagen and Matrigel was found to promote EC adhesion and monolayer formation, and SMC adhesion and alignment. Optimal culturing protocols were established that enabled EC-SMC coculture for more than 31 days. Epithelial monolayers displayed common morphological markers including ZO-1 tight junctions and F-actin cell cortices, while SMCs exhibited enhanced cell alignment and expression of α-SMA. The thermoplastic device construction facilitates mass manufacturing, allows EC-SMC coculture systems to be arrayed for increased throughput, and can be disassembled to allow extraction of the suspended gel for downstream analyses. This airway-on-a-chip device has potential to significantly advance our understanding of SMC-EC-matrix interactions, and their roles in the development of CLDs.

Hybrid integrated single-wavelength laser with silicon micro-ring reflector

NASA Astrophysics Data System (ADS)

Ren, Min; Pu, Jing; Krishnamurthy, Vivek; Xu, Zhengji; Lee, Chee-Wei; Li, Dongdong; Gonzaga, Leonard; Toh, Yeow T.; Tjiptoharsono, Febi; Wang, Qian

2018-02-01

A hybrid integrated single-wavelength laser with silicon micro-ring reflector is demonstrated theoretically and experimentally. It consists of a heterogeneously integrated III-V section for optical gain, an adiabatic taper for light coupling, and a silicon micro-ring reflector for both wavelength selection and light reflection. Heterogeneous integration processes for multiple III-V chips bonded to an 8-inch Si wafer have been developed, which is promising for massive production of hybrid lasers on Si. The III-V layer is introduced on top of a 220-nm thick SOI layer through low-temperature wafer-boning technology. The optical coupling efficiency of >85% between III-V and Si waveguide has been achieved. The silicon micro-ring reflector, as the key element of the hybrid laser, is studied, with its maximized reflectivity of 85.6% demonstrated experimentally. The compact single-wavelength laser enables fully monolithic integration on silicon wafer for optical communication and optical sensing application.

Potato processing scenario in India: Industrial constraints, future projections, challenges ahead and remedies - A review.

PubMed

Marwaha, R S; Pandey, S K; Kumar, Dinesh; Singh, S V; Kumar, Parveen

2010-03-01

Indian potato (Solanum tuberosum L.) processing industry has emerged fast due to economic liberalization coupled with growing urbanization, expanding market options and development of indegenous processing varieties. India's first potato processing varieties 'Kufri Chipsona-1' and 'Kufri Chipsona-2' were developed in 1998, followed by an improved processing variety 'Kufri Chipsona-3' in 2005 for the Indian plains and first chipping variety 'Kufri Himsona' for the hills. These varieties have >21% tuber dry matter content, contain low reducing sugars (<0.1% on fresh wt) and are most suitable for producing chips, French fries and dehydrated products. The availability of these varieties and standardization of storage techniques for processing potatoes at 10-12°C with sprout suppressant isopropyl N-(3-chlorophenyl) carbamate have revolutionized the processing scenario within a short span of 10 years. Currently about 4% of total potato produce is being processed in organized and unorganized sector. Potato processing industry mainly comprises 4 segments: potato chips, French fries, potato flakes/powder and other processed products. However, potato chips still continue to be the most popular processed product. The major challenge facing the industries lies in arranging round the year supply of processing varieties at reasonable price for their uninterrupted operation, besides several others which have been discussed at length and addressed with concrete solutions.

Ultrasonic Fingerprint Sensor With Transmit Beamforming Based on a PMUT Array Bonded to CMOS Circuitry.

PubMed

Jiang, Xiaoyue; Tang, Hao-Yen; Lu, Yipeng; Ng, Eldwin J; Tsai, Julius M; Boser, Bernhard E; Horsley, David A

2017-09-01

In this paper, we present a single-chip 65 ×42 element ultrasonic pulse-echo fingerprint sensor with transmit (TX) beamforming based on piezoelectric micromachined ultrasonic transducers directly bonded to a CMOS readout application-specific integrated circuit (ASIC). The readout ASIC was realized in a standard 180-nm CMOS process with a 24-V high-voltage transistor option. Pulse-echo measurements are performed column-by-column in sequence using either one column or five columns to TX the ultrasonic pulse at 20 MHz. TX beamforming is used to focus the ultrasonic beam at the imaging plane where the finger is located, increasing the ultrasonic pressure and narrowing the 3-dB beamwidth to [Formula: see text], a factor of 6.4 narrower than nonbeamformed measurements. The surface of the sensor is coated with a poly-dimethylsiloxane (PDMS) layer to provide good acoustic impedance matching to skin. Scanning laser Doppler vibrometry of the PDMS surface was used to map the ultrasonic pressure field at the imaging surface, demonstrating the expected increase in pressure, and reduction in beamwidth. Imaging experiments were conducted using both PDMS phantoms and real fingerprints. The average image contrast is increased by a factor of 1.5 when beamforming is used.

Protein immobilization on the surface of polydimethylsiloxane and polymethyl methacrylate microfluidic devices.

PubMed

Khnouf, Ruba; Karasneh, Dina; Albiss, Borhan Aldeen

2016-02-01

PDMS and PMMA are two of the most used polymers in the fabrication of lab-on-chip or microfluidic devices. In order to use these polymers in biological applications, it is sometimes essential to be able to bind biomolecules such as proteins and DNA to the surface of these materials. In this work, we have evaluated a number of processes that have been developed to bind protein to PDMS surfaces which include passive adsorption, passive adsorption with glutaraldehyde cross-linking, (3-aminopropyl) triethoxysilane functionalization followed by glutaraldehyde or 1-ethyl-3-(3-dimethylaminopropyl) carbodiimide hydrochloride cross-linkers. It has been shown that the latter technique--using 1-ethyl-3-(3-dimethylaminopropyl) carbodiimide hydrochloride--results in more than twice the bonding of protein to the surface of PDMS microchannels than proteins binding passively. We have also evaluated a few techniques that have been tested for the functionalization of PMMA microchannels where we have found that the use of polyethyleneimine (PEI) has led to the strongest protein-PMMA microchannel bond. We finally demonstrated the effect of PDMS curing methodology on protein adsorption to its surface, and showed that increased curing time is the factor that reduces passive adsorption the most. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Design of an MR image processing module on an FPGA chip.

PubMed

Li, Limin; Wyrwicz, Alice M

2015-06-01

We describe the design and implementation of an image processing module on a single-chip Field-Programmable Gate Array (FPGA) for real-time image processing. We also demonstrate that through graphical coding the design work can be greatly simplified. The processing module is based on a 2D FFT core. Our design is distinguished from previously reported designs in two respects. No off-chip hardware resources are required, which increases portability of the core. Direct matrix transposition usually required for execution of 2D FFT is completely avoided using our newly-designed address generation unit, which saves considerable on-chip block RAMs and clock cycles. The image processing module was tested by reconstructing multi-slice MR images from both phantom and animal data. The tests on static data show that the processing module is capable of reconstructing 128×128 images at speed of 400 frames/second. The tests on simulated real-time streaming data demonstrate that the module works properly under the timing conditions necessary for MRI experiments. Copyright © 2015 Elsevier Inc. All rights reserved.

Novel tool wear monitoring method in milling difficult-to-machine materials using cutting chip formation

NASA Astrophysics Data System (ADS)

Zhang, P. P.; Guo, Y.; Wang, B.

2017-05-01

The main problems in milling difficult-to-machine materials are the high cutting temperature and rapid tool wear. However it is impossible to investigate tool wear in machining. Tool wear and cutting chip formation are two of the most important representations for machining efficiency and quality. The purpose of this paper is to develop the model of tool wear with cutting chip formation (width of chip and radian of chip) on difficult-to-machine materials. Thereby tool wear is monitored by cutting chip formation. A milling experiment on the machining centre with three sets cutting parameters was performed to obtain chip formation and tool wear. The experimental results show that tool wear increases gradually along with cutting process. In contrast, width of chip and radian of chip decrease. The model is developed by fitting the experimental data and formula transformations. The most of monitored errors of tool wear by the chip formation are less than 10%. The smallest error is 0.2%. Overall errors by the radian of chip are less than the ones by the width of chip. It is new way to monitor and detect tool wear by cutting chip formation in milling difficult-to-machine materials.

Neuromorphic vision sensors and preprocessors in system applications

NASA Astrophysics Data System (ADS)

Kramer, Joerg; Indiveri, Giacomo

1998-09-01

A partial review of neuromorphic vision sensors that are suitable for use in autonomous systems is presented. Interfaces are being developed to multiplex the high- dimensional output signals of arrays of such sensors and to communicate them in standard formats to off-chip devices for higher-level processing, actuation, storage and display. Alternatively, on-chip processing stages may be implemented to extract sparse image parameters, thereby obviating the need for multiplexing. Autonomous robots are used to test neuromorphic vision chips in real-world environments and to explore the possibilities of data fusion from different sensing modalities. Examples of autonomous mobile systems that use neuromorphic vision chips for line tracking and optical flow matching are described.

Effect of Minor Titanium Addition on Copper/Diamond Composites Prepared by Hot Forging

NASA Astrophysics Data System (ADS)

Yang, Fei; Sun, Wei; Singh, Ajit; Bolzoni, Leandro

2018-03-01

Copper/diamond composites have great potential to lead the next generation of advanced heat sink materials for use in high-power electronic devices and high-density integrated circuits because of their potential excellent properties of high thermal conductivity and close thermal expansion to the chip materials (e.g., Si, InP, GaAs). However, the poor wettability between copper and diamond presents a challenge for synthesizing copper/diamond composites with effective metallurgical bonding and satisfied thermal performance. In this article, copper/diamond composites were successfully prepared by hot forging of elemental copper and artificial diamond powders with small amounts (0 vol.%, 3 vol.% and 5 vol.%) of titanium additives. Microstructure observation and mechanical tests showed that adding minor titanium additions in the copper/diamond composite resulted in fewer cracks in the composites' microstructure and significantly improved the bonding between the copper and diamond. The strongest bonding strength was achieved for the copper/diamond composite with 3 vol.% titanium addition, and the possible reasons were discussed.

Impact of alternative technique to ageing using oak chips in alcoholic or in malolactic fermentation on volatile and sensory composition of red wines.

PubMed

Gómez García-Carpintero, E; Gómez Gallego, M A; Sánchez-Palomo, E; González Viñas, M A

2012-09-15

This paper reports on a complete study of the effect of wood, in the form of oak chips, on the volatile composition and sensory characteristics of Moravia Agria wines added at different stages of the fermentation process. Aroma compounds were analyzed by gas chromatography-mass spectrometry (GC-MS). Sensory profile was evaluated by experienced wine-testers. Oak chips were added to wines in two dose rates at different stages of the winemaking process: during alcoholic fermentation (AF), during malolactic fermentation (MLF) and in young, red Moravia Agria wine. Wines fermented with oak chips during AF showed higher concentrations of the ethyl esters of straight-chain fatty acids, ethyl, hexyl, isoamyl acetates and superior alcohols than the control wines. The higher concentrations of benzene compound, oak lactones and furanic compounds were found in wines in contact with oak chips during MLF. The use of oak chips gives rise to a different sensorial profile of wines depending of the point of addition. Higher intensities of woody, coconut, vanilla and sweet spices descriptors were obtained when a large dose rate of chips was employed. Copyright © 2012 Elsevier Ltd. All rights reserved.

Micro Machining of Injection Mold Inserts for Fluidic Channel of Polymeric Biochips

PubMed Central

Jung, Woo-Chul; Heo, Young-Moo; Yoon, Gil-Sang; Shin, Kwang-Ho; Chang, Sung-Ho; Kim, Gun-Hee; Cho, Myeong-Woo

2007-01-01

Recently, the polymeric micro-fluidic biochip, often called LOC (lab-on-a-chip), has been focused as a cheap, rapid and simplified method to replace the existing biochemical laboratory works. It becomes possible to form miniaturized lab functionalities on a chip with the development of MEMS technologies. The micro-fluidic chips contain many micro-channels for the flow of sample and reagents, mixing, and detection tasks. Typical substrate materials for the chip are glass and polymers. Typical techniques for microfluidic chip fabrication are utilizing various micro pattern forming methods, such as wet-etching, micro-contact printing, and hot-embossing, micro injection molding, LIGA, and micro powder blasting processes, etc. In this study, to establish the basis of the micro pattern fabrication and mass production of polymeric micro-fluidic chips using injection molding process, micro machining method was applied to form micro-channels on the LOC molds. In the research, a series of machining experiments using micro end-mills were performed to determine optimum machining conditions to improve surface roughness and shape accuracy of designed simplified micro-channels. Obtained conditions were used to machine required mold inserts for micro-channels using micro end-mills. Test injection processes using machined molds and COC polymer were performed, and then the results were investigated.

Optimization of multiplexed PCR on an integrated microfluidic forensic platform for rapid DNA analysis.

PubMed

Estes, Matthew D; Yang, Jianing; Duane, Brett; Smith, Stan; Brooks, Carla; Nordquist, Alan; Zenhausern, Frederic

2012-12-07

This study reports the design, prototyping, and assay development of multiplexed polymerase chain reaction (PCR) on a plastic microfluidic device. Amplification of 17 DNA loci is carried out directly on-chip as part of a system for continuous workflow processing from sample preparation (SP) to capillary electrophoresis (CE). For enhanced performance of on-chip PCR amplification, improved control systems have been developed making use of customized Peltier assemblies, valve actuators, software, and amplification chemistry protocols. Multiple enhancements to the microfluidic chip design have been enacted to improve the reliability of sample delivery through the various on-chip modules. This work has been enabled by the encapsulation of PCR reagents into a solid phase material through an optimized Solid Phase Encapsulating Assay Mix (SPEAM) bead-based hydrogel fabrication process. SPEAM bead technology is reliably coupled with precise microfluidic metering and dispensing for efficient amplification and subsequent DNA short tandem repeat (STR) fragment analysis. This provides a means of on-chip reagent storage suitable for microfluidic automation, with the long shelf-life necessary for point-of-care (POC) or field deployable applications. This paper reports the first high quality 17-plex forensic STR amplification from a reference sample in a microfluidic chip with preloaded solid phase reagents, that is designed for integration with up and downstream processing.

Static adsorptive coating of poly(methyl methacrylate) microfluidic chips for extended usage in DNA separations.

PubMed

Du, Xiao-Guang; Fang, Zhao-Lun

2005-12-01

A simple and robust static adsorptive (dynamic) coating process using 2% hydroxyethylcellulose was developed for surface modification of poly(methyl methacrylate) (PMMA) microfluidic chips for DNA separations, suitable for usage over extended periods, involving hundreds of runs. The coating medium was also used as a sieving matrix for the DNA separations following the coating process. Four consecutive static treatments, by simply filling the PMMA chip channels with sieving matrix once every day, were required for obtaining a stable coating and optimum performance. The performance of the coated chips at different phases of the coating process was studied by consecutive gel electrophoretic separations with LIF detection using a PhiX-174/HaeIII DNA digest sample. The coated chip, with daily renewal of the sieving matrix, showed high stability in performance during a 25-day period of systematic study, involving more than 100 individual runs. The performance of the coated chip also remained almost the same after 3 months of continuous usage, during which over 200 separations were performed. The average precision of migration time for the 603-bp fragment was 1.31% RSD (n = 6) during the 25-day study, with a separation efficiency of 6.5 x 10(4) plates (effective separation length 5.4 cm).

Technology Development of Salak (Salacca Zalacca) Chips With Vacuum Frying Machine Base On Expert System In Kramat-Bangkalan Regency

NASA Astrophysics Data System (ADS)

Rosida, D. F.; Happyanto; Anggraeni; Sugiarto; Hapsari

2018-01-01

Agropolitan Program is one form of regional development to improve agribusiness system and effort to improve the welfare of the community. One of the leading commodities in Bangkalan agroclimates is salak which is a potentially very large commodity to be developed. Salak commodities in Kramat Bangkalan Indonesia have developed varous salak produced such as dates of salak, syrup and dodol salak. Salak chips was the target of innovation from processed salak. The Production of salak chips using frying technology with vacuum system to obtain crunchy chips. To get the results need to be developed synergy technology to combine the process conditions and the right system in producing good quality salak chips. Bangkalan Regency is the potential to continue to develop products using a variety of salak to the processed form of vacuum frying machine based on expert system so that the resulting product would be great texture, aroma and taste. This will make the area of Bangkalan, Indonesia be more independent in producing and increasing revenue.

Comminution process to produce precision wood particles of uniform size and shape with disrupted grain structure from wood chips

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dooley, James H.; Lanning, David N.

A process of comminution of wood chips (C) having a grain direction to produce a mixture of wood particles (P), wherein the wood chips are characterized by an average length dimension (L.sub.C) as measured substantially parallel to the grain, an average width dimension (W.sub.C) as measured normal to L.sub.C and aligned cross grain, and an average height dimension (H.sub.C) as measured normal to W.sub.C and L.sub.C, wherein W.sub.C>L.sub.C, and wherein the comminution process comprises the step of feeding the wood chips in a direction of travel substantially randomly to the grain direction through a counter rotating pair of intermeshing arraysmore » of cutting discs (D) arrayed axially perpendicular to the direction of wood chip travel, wherein the cutting discs have a uniform thickness (T.sub.D), and wherein at least one of L.sub.C, W.sub.C, and H.sub.C is less than T.sub.D.« less

CHIP as a membrane-shuttling proteostasis sensor

PubMed Central

Kopp, Yannick; Martínez-Limón, Adrián; Hofbauer, Harald F; Ernst, Robert; Calloni, Giulia

2017-01-01

Cells respond to protein misfolding and aggregation in the cytosol by adjusting gene transcription and a number of post-transcriptional processes. In parallel to functional reactions, cellular structure changes as well; however, the mechanisms underlying the early adaptation of cellular compartments to cytosolic protein misfolding are less clear. Here we show that the mammalian ubiquitin ligase C-terminal Hsp70-interacting protein (CHIP), if freed from chaperones during acute stress, can dock on cellular membranes thus performing a proteostasis sensor function. We reconstituted this process in vitro and found that mainly phosphatidic acid and phosphatidylinositol-4-phosphate enhance association of chaperone-free CHIP with liposomes. HSP70 and membranes compete for mutually exclusive binding to the tetratricopeptide repeat domain of CHIP. At new cellular locations, access to compartment-specific substrates would enable CHIP to participate in the reorganization of the respective organelles, as exemplified by the fragmentation of the Golgi apparatus (effector function). PMID:29091030

Regeneration of glass nanofluidic chips through a multiple-step sequential thermochemical decomposition process at high temperatures.

PubMed

Xu, Yan; Wu, Qian; Shimatani, Yuji; Yamaguchi, Koji

2015-10-07

Due to the lack of regeneration methods, the reusability of nanofluidic chips is a significant technical challenge impeding the efficient and economic promotion of both fundamental research and practical applications on nanofluidics. Herein, a simple method for the total regeneration of glass nanofluidic chips was described. The method consists of sequential thermal treatment with six well-designed steps, which correspond to four sequential thermal and thermochemical decomposition processes, namely, dehydration, high-temperature redox chemical reaction, high-temperature gasification, and cooling. The method enabled the total regeneration of typical 'dead' glass nanofluidic chips by eliminating physically clogged nanoparticles in the nanochannels, removing chemically reacted organic matter on the glass surface and regenerating permanent functional surfaces of dissimilar materials localized in the nanochannels. The method provides a technical solution to significantly improve the reusability of glass nanofluidic chips and will be useful for the promotion and acceleration of research and applications on nanofluidics.

Analysis of the Production Cost for Various Grades of Biomass Thermal Treatment

DOE Office of Scientific and Technical Information (OSTI.GOV)

Cherry, Robert S.; Wood, Rick A.; Westover, Tyler L.

2013-12-01

Process flow sheets were developed for the thermal treatment of southern pine wood chips at four temperatures (150, 180, 230, and 270 degrees C) and two different scales (20 and 100 ton/hour). The larger capacity processes had as their primary heat source hot gas assumed to be available in quantity from an adjacent biorefinery. Mass and energy balances for these flow sheets were developed using Aspen Plus process simulation software. The hot gas demands in the larger processes, up to 1.9 million lb/hour, were of questionable feasibility because of the volume to be moved. This heat was of low utilitymore » because the torrefaction process, especially at higher temperatures, is a net heat producer if the organic byproduct gases are burned. A thermal treatment flow sheet using wood chips dried in the biorefinery to 10% moisture content (rather than 30% for green chips) with transfer of high temperature steam from the thermal treatment depot to the biorefinery was also examined. The equipment size information from all of these cases was used in several different equipment cost estimating methods to estimate the major equipment costs for each process. From these, factored estimates of other plant costs were determined, leading to estimates (± 30% accuracy) of total plant capital cost. The 20 ton/hour processes were close to 25 million dollars except for the 230 degrees C case using dried wood chips which was only 15 million dollars because of its small furnace. The larger processes ranged from 64-120 million dollars. From these capital costs and projections of several categories of operating costs, the processing cost of thermally treated pine chips was found to be $28-33 per ton depending on the degree of treatment and without any credits for steam generation. If the excess energy output of the two 20 ton/hr depot cases at 270 degrees C can be sold for $10 per million BTU, the net processing cost dropped to $13/ton product starting with green wood chips or only $3 per ton if using dried chips from the biorefinery. Including a 12% return on invested capital raised all of the operating cost results by about $20/ton.« less

An Implantable Neural Sensing Microsystem with Fiber-Optic Data Transmission and Power Delivery

PubMed Central

Park, Sunmee; Borton, David A.; Kang, Mingyu; Nurmikko, Arto V.; Song, Yoon-Kyu

2013-01-01

We have developed a prototype cortical neural sensing microsystem for brain implantable neuroengineering applications. Its key feature is that both the transmission of broadband, multichannel neural data and power required for the embedded microelectronics are provided by optical fiber access. The fiber-optic system is aimed at enabling neural recording from rodents and primates by converting cortical signals to a digital stream of infrared light pulses. In the full microsystem whose performance is summarized in this paper, an analog-to-digital converter and a low power digital controller IC have been integrated with a low threshold, semiconductor laser to extract the digitized neural signals optically from the implantable unit. The microsystem also acquires electrical power and synchronization clocks via optical fibers from an external laser by using a highly efficient photovoltaic cell on board. The implantable unit employs a flexible polymer substrate to integrate analog and digital microelectronics and on-chip optoelectronic components, while adapting to the anatomical and physiological constraints of the environment. A low power analog CMOS chip, which includes preamplifier and multiplexing circuitry, is directly flip-chip bonded to the microelectrode array to form the cortical neurosensor device. PMID:23666130

Microcontact Printing of Thiol-Functionalized Ionic Liquid Microarrays for "Membrane-less" and "Spill-less" Gas Sensors.

PubMed

Gondosiswanto, Richard; Gunawan, Christian A; Hibbert, David B; Harper, Jason B; Zhao, Chuan

2016-11-16

Lab-on-a-chip systems have gained significant interest for both chemical synthesis and assays at the micro-to-nanoscale with a unique set of benefits. However, solvent volatility represents one of the major hurdles to the reliability and reproducibility of the lab-on-a-chip devices for large-scale applications. Here we demonstrate a strategy of combining nonvolatile and functionalized ionic liquids with microcontact printing for fabrication of "wall-less" microreactors and microfluidics with high reproducibility and high throughput. A range of thiol-functionalized ionic liquids have been synthesized and used as inks for microcontact printing of ionic liquid microdroplet arrays onto gold chips. The covalent bonds formed between the thiol-functionalized ionic liquids and the gold substrate offer enhanced stability of the ionic liquid microdroplets, compared to conventional nonfunctionalized ionic liquids, and these microdroplets remain stable in a range of nonpolar and polar solvents, including water. We further demonstrate the use of these open ionic liquid microarrays for fabrication of "membrane-less" and "spill-less" gas sensors with enhanced reproducibility and robustness. Ionic-liquid-based microarray and microfluidics fabricated using the described microcontact printing may provide a versatile platform for a diverse number of applications at scale.

Novel Bonding Technology for Hermetically Sealed Silicon Micropackage

NASA Astrophysics Data System (ADS)

Lee, Duck-Jung; Ju, Byeong-Kwon; Choi, Woo-Beom; Jeong, Jee-Won; Lee, Yun-Hi; Jang, Jin; Lee, Kwang-Bae; Oh, Myung-Hwan

1999-01-01

We performed glass-to-silicon bonding and fabricated a hermetically sealed silicon wafer using silicon direct bonding followed by anodic bonding (SDAB). The hydrophilized glass and silicon wafers in solution were dried and initially bonded in atmosphere as in the silicon direct bonding (SDB) process, but annealing at high temperature was not performed. Anodic bonding was subsequently carried out for the initially bonded specimens. Then the wafer pairs bonded by the SDAB method were different from those bonded by the anodic bonding process only. The effects of the bonding process on the bonded area and tensile strength were investigated as functions of bonding temperature and voltage. Using scanning electron microscopy (SEM), the cross-sectional view of the bonded interface region was observed. In order to investigate the migration of the sodium ions in the bonding process, the concentration of the bonded glass was compared with that of standard glass. The specimen bonded using the SDAB process had higher efficiency than that using the anodic bonding process only.

Revising the role of pH and thermal treatments in aflatoxin content reduction during the tortilla and deep frying processes.

PubMed

Torres, P; Guzmán-Ortiz, M; Ramírez-Wong, B

2001-06-01

Naturally aflatoxin-contaminated corn (Zea mays L.) was made into tortillas, tortilla chips, and corn chips by the traditional and commercial alkaline cooking processes. The traditional nixtamalization (alkaline-cooking) process involved cooking and steeping the corn, whereas the commercial nixtamalization process only steeps the corn in a hot alkaline solution (initially boiling). A pilot plant that includes the cooker, stone grinder, celorio cutter, and oven was used for the experiments. The traditional process eliminated 51.7, 84.5, and 78.8% of the aflatoxins content in tortilla, tortilla chips, and corn chips, respectively. The commercial process was less effective: it removed 29.5, 71.2, and 71.2 of the aflatoxin in the same products. Intermediate and final products did not reach a high enough pH to allow permanent aflatoxin reduction during thermal processing. The cooking or steeping liquor (nejayote) is the only component of the system with a sufficiently high pH (10.2-10.7) to allow modification and detoxification of aflatoxins present in the corn grain. The importance of removal of tip, pericarp, and germ during nixtamalization for aflatoxin reduction in tortilla is evident.

Modified low-temperture direct bonding method for vacuum microelectronics application

NASA Astrophysics Data System (ADS)

Ju, Byeong-Kwon; Lee, Duck-Jung; Choi, Woo-Beom; Lee, Yun-Hi; Jang, Jin; Lee, Kwang-Bae; Oh, Myung-Hwan

1997-06-01

This paper presents the process and experimental results for the improved silicon-to-glass bonding using silicon direct bonding (SDB) followed by anodic bonding. The initial bonding between glass and silicon was caused by the hydrophilic surfaces of silicon-glass ensemble using SDB method. Then the initially bonded specimen had to be strongly bonded by anodic bonding process. The effects of the bonding process parameters on the interface energy were investigated as functions of the bonding temperature and voltage. We found that the specimen which was bonded using SDB process followed by anodic bonding process had higher interface energy than one using anodic bonding process only. The main factor contributing to the higher interface energy in the glass-to-silicon assemble bonded by SDB followed by anodic bonding was investigated by secondary ion mass spectroscopy analysis.

Performance of chip seals using local and minimally processed aggregates for preservation of low traffic volume roadways.

DOT National Transportation Integrated Search

2013-07-01

This report documents the performance of two low traffic volume experimental chip seals constructed using : locally available, minimally processed sand and gravel aggregates after four winters of service. The projects : were constructed by CDOT maint...

Delimbing hybrid poplar prior to processing with a flail/chipper

Treesearch

Bruce Hartsough; Raffaele Spinelli; Steve Pottle

2000-01-01

Processing whole trees into pulp chips with chain flail delimber/debarker/chippers (DDCs) is costly. Production rates of DDCs are limited by the residence time required to remove limbs and bark. Using a pull-through delimber, we delimbed trees prior to flailing and chipping, with the objective of speeding up the latter processes. Pre-delimbing increased the...

Delimbing hybrid poplar prior to processing with a flail/chipper

Treesearch

Bruce R. Hartsough; Raffaele Spinelli; Steve J. Pottle

2002-01-01

Processing whole trees into pulp chips with chain flail delimber/debarker/chippers (DDCs) is costly. Production rates of DDCs are limited by the residence time required to remove limbs and bark. Using a pull-through delimber, we delimbed trees prior to flailing and chipping, with the objective of speeding up the latter processes. Pre-delimbing increased the...

Millimeter And Submillimeter-Wave Integrated Circuits On Quartz

NASA Technical Reports Server (NTRS)

Mehdi, Imran; Mazed, Mohammad; Siegel, Peter; Smith, R. Peter

1995-01-01

Proposed Quartz substrate Upside-down Integrated Device (QUID) relies on UV-curable adhesive to bond semiconductor with quartz. Integrated circuits including planar GaAs Schottky diodes and passive circuit elements (such as bandpass filters) fabricated on quartz substrates. Circuits designed to operate as mixers in waveguide circuit at millimeter and submillimeter wavelengths. Integrated circuits mechanically more robust, larger, and easier to handle than planar Schottky diode chips. Quartz substrate more suitable for waveguide circuits than GaAs substrate.

CHIP promotes thyroid cancer proliferation via activation of the MAPK and AKT pathways

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zhang, Li; Liu, Lianyong; Department of Endocrinology, Shanghai Punan Hospital, Shanghai 200125

The carboxyl terminus of Hsp70-interacting protein (CHIP) is a U box-type ubiquitin ligase that plays crucial roles in various biological processes, including tumor progression. To date, the functional mechanism of CHIP in thyroid cancer remains unknown. Here, we obtained evidence of upregulation of CHIP in thyroid cancer tissues and cell lines. CHIP overexpression markedly enhanced thyroid cancer cell viability and colony formation in vitro and accelerated tumor growth in vivo. Conversely, CHIP knockdown impaired cell proliferation and tumor growth. Notably, CHIP promoted cell growth through activation of MAPK and AKT pathways, subsequently decreasing p27 and increasing cyclin D1 and p-FOXO3a expression. Ourmore » findings collectively indicate that CHIP functions as an oncogene in thyroid cancer, and is therefore a potential therapeutic target for this disease. - Highlights: • CHIP is significantly upregulated in thyroid cancer cells. • Overexpression of CHIP facilitates proliferation and tumorigenesis of thyroid cancer cells. • Silencing of CHIP inhibits the proliferation and tumorigenesis of thyroid cancer cells. • CHIP promotes thyroid cancer cell proliferation via activating the MAPK and AKT pathways.« less

Method of fabricating a PbS-PbSe IR detector array

NASA Technical Reports Server (NTRS)

Barrett, John R. (Inventor)

1987-01-01

A silicon wafer is provided which does not employ individually bonded leads between the IR sensitive elements and the input stages of multiplexers. The wafer is first coated with lead selenide in a first detector array area and is thereafter coated with lead sulfide within a second detector array area. The described steps result in the direct chemical deposition of lead selenide and lead sulfide upon the silicon wafer to eliminate individual wire bonding, bumping, flip chiping, planar interconnecting methods of connecting detector array elements to silicon chip circuitry, e.g., multiplexers, to enable easy fabrication of very long arrays. The electrode structure employed, produces an increase in the electrical field gradient between the electrodes for a given volume of detector material, relative to conventional electrode configurations.

Ultrasonic Vibration Assisted Grinding of Bio-ceramic Materials: Modeling, Simulation, and Experimental Investigations on Edge Chipping

NASA Astrophysics Data System (ADS)

Tesfay, Hayelom D.

Bio-ceramics are those engineered materials that find their applications in the field of biomedical engineering or medicine. They have been widely used in dental restorations, repairing bones, joint replacements, pacemakers, kidney dialysis machines, and respirators. etc. due to their physico-chemical properties, such as excellent corrosion resistance, good biocompatibility, high strength and high wear resistance. Because of their inherent brittleness and hardness nature they are difficult to machine to exact sizes and dimensions. Abrasive machining processes such as grinding is one of the most widely used manufacturing processes for bioceramics. However, the principal technical challenge resulted from these machining is edge chipping. Edge chipping is a common edge failure commonly observed during the machining of bio-ceramic materials. The presence of edge chipping on bio-ceramic products affects dimensional accuracy, increases manufacturing cost, hider their industrial applications and causes potential failure during service. To overcome these technological challenges, a new ultrasonic vibration-assisted grinding (UVAG) manufacturing method has been developed and employed in this research. The ultimate aim of this study is to develop a new cost-effective manufacturing process relevant to eliminate edge chippings in grinding of bio-ceramic materials. In this dissertation, comprehensive investigations will be carried out using experimental, theoretical, and numerical approaches to evaluate the effect of ultrasonic vibrations on edge chipping of bioceramics. Moreover, effects of nine input variables (static load, vibration frequency, grinding depth, spindle speed, grinding distance, tool speed, grain size, grain number, and vibration amplitude) on edge chipping will be studied based on the developed models. Following a description of previous research and existing approaches, a series of experimental tests on three bio-ceramic materials (Lava, partially fired Lava, and Alumina) were conducted. Based on the experimental results, analytical models for UVAG and CG (conventional grinding without ultrasonic vibration) processes were developed. As for the numerical study, an extended finite element method (XFEM) based on Virtual Crack Closure Technique (VCCT) in ABAQUS was used to model the formation of edge chippings both for UVAG and CG processes. The experimental results are compared against the numerical FEA and the analytical models. The experimental, theoretical, and computational simulation results revealed that the edge chipping size of bioceramics can be significantly reduced with the assistance of ultrasonic vibration. The investigation procedures and the results obtained in this dissertation would be used as a reference and practical guidance for choosing reasonable process variables as well as designing mathematical (analytical and numerical) models in manufacturing industries and academic institutions when the edge chippings of brittle materials are expected to be controlled.

Polymer waveguide grating sensor integrated with a thin-film photodetector

PubMed Central

Song, Fuchuan; Xiao, Jing; Xie, Antonio Jou; Seo, Sang-Woo

2014-01-01

This paper presents a planar waveguide grating sensor integrated with a photodetector (PD) for on-chip optical sensing systems which are suitable for diagnostics in the field and in-situ measurements. III–V semiconductor-based thin-film PD is integrated with a polymer based waveguide grating device on a silicon platform. The fabricated optical sensor successfully discriminates optical spectral characteristics of the polymer waveguide grating from the on-chip PD. In addition, its potential use as a refractive index sensor is demonstrated. Based on a planar waveguide structure, the demonstrated sensor chip may incorporate multiple grating waveguide sensing regions with their own optical detection PDs. In addition, the demonstrated processing is based on a post-integration process which is compatible with silicon complementary metal-oxide semiconductor (CMOS) electronics. Potentially, this leads a compact, chip-scale optical sensing system which can monitor multiple physical parameters simultaneously without need for external signal processing. PMID:24466407

Upgrade Recycling of Cast Iron Scrap Chips towards β-FeSi₂ Thermoelectric Materials.

PubMed

Laila, Assayidatul; Nanko, Makoto; Takeda, Masatoshi

2014-09-04

The upgrade recycling of cast-iron scrap chips towards β-FeSi₂ thermoelectric materials is proposed as an eco-friendly and cost-effective production process. By using scrap waste from the machining process of cast-iron components, the material cost to fabricate β-FeSi₂ is reduced and the industrial waste is recycled. In this study, β-FeSi₂ specimens obtained from cast iron scrap chips were prepared both in the undoped form and doped with Al and Co elements. The maximum figure of merit ( ZT ) indicated a thermoelectric performance of approximately 70% in p-type samples and nearly 90% in n-type samples compared to β-FeSi₂ prepared from pure Fe and other published studies. The use of cast iron scrap chips to produce β-FeSi₂ shows promise as an eco-friendly and cost-effective production process for thermoelectric materials.

CHIP promotes thyroid cancer proliferation via activation of the MAPK and AKT pathways.

PubMed

Zhang, Li; Liu, Lianyong; He, Xiaohua; Shen, Yunling; Liu, Xuerong; Wei, Jing; Yu, Fang; Tian, Jianqing

2016-08-26

The carboxyl terminus of Hsp70-interacting protein (CHIP) is a U box-type ubiquitin ligase that plays crucial roles in various biological processes, including tumor progression. To date, the functional mechanism of CHIP in thyroid cancer remains unknown. Here, we obtained evidence of upregulation of CHIP in thyroid cancer tissues and cell lines. CHIP overexpression markedly enhanced thyroid cancer cell viability and colony formation in vitro and accelerated tumor growth in vivo. Conversely, CHIP knockdown impaired cell proliferation and tumor growth. Notably, CHIP promoted cell growth through activation of MAPK and AKT pathways, subsequently decreasing p27 and increasing cyclin D1 and p-FOXO3a expression. Our findings collectively indicate that CHIP functions as an oncogene in thyroid cancer, and is therefore a potential therapeutic target for this disease. Copyright © 2016 Elsevier Inc. All rights reserved.

Ice-assisted transfer of carbon nanotube arrays.

PubMed

Wei, Haoming; Wei, Yang; Lin, Xiaoyang; Liu, Peng; Fan, Shoushan; Jiang, Kaili

2015-03-11

Decoupling the growth and the application of nanomaterials by transfer is an important issue in nanotechnology. Here, we developed an efficient transfer technique for carbon nanotube (CNT) arrays by using ice as a binder to temporarily bond the CNT array and the target substrate. Ice makes it an ultraclean transfer because the evaporation of ice ensures that no contaminants are introduced. The transferred superaligned carbon nanotube (SACNT) arrays not only keep their original appearance and initial alignment but also inherit their spinnability, which is the most desirable feature. The transfer-then-spin strategy can be employed to fabricate patterned CNT arrays, which can act as 3-dimensional electrodes in CNT thermoacoustic chips. Besides, the flip-chipped CNTs are promising field electron emitters. Furthermore, the ice-assisted transfer technique provides a cost-effective solution for mass production of SACNTs, giving CNT technologies a competitive edge, and this method may inspire new ways to transfer other nanomaterials.

Methods and apparatus for mid-infrared sensing

DOEpatents

Lin, Pao Tai; Cai, Yan; Agarwal, Anuradha Murthy; Kimerling, Lionel C.

2015-06-02

A chip-scale, air-clad semiconductor pedestal waveguide can be used as a mid-infrared (mid-IR) sensor capable of in situ monitoring of organic solvents and other analytes. The sensor uses evanescent coupling from a silicon or germanium waveguide, which is highly transparent in the mid-IR portion of the electromagnetic spectrum, to probe the absorption spectrum of fluid surrounding the waveguide. Launching a mid-IR beam into the waveguide exposed to a particular analyte causes attenuation of the evanescent wave's spectral components due to absorption by carbon, oxygen, hydrogen, and/or nitrogen bonds in the surrounding fluid. Detecting these changes at the waveguide's output provides an indication of the type and concentration of one or more compounds in the surrounding fluid. If desired, the sensor may be integrated onto a silicon substrate with a mid-IR light source and a mid-IR detector to form a chip-based spectrometer.

X-ray metrology of an array of active edge pixel sensors for use at synchrotron light sources

NASA Astrophysics Data System (ADS)

Plackett, R.; Arndt, K.; Bortoletto, D.; Horswell, I.; Lockwood, G.; Shipsey, I.; Tartoni, N.; Williams, S.

2018-01-01

We report on the production and testing of an array of active edge silicon sensors as a prototype of a large array. Four Medipix3RX.1 chips were bump bonded to four single chip sized Advacam active edge n-on-n sensors. These detectors were then mounted into a 2 by 2 array and tested on B16 at Diamond Light Source with an x-ray beam spot of 2um. The results from these tests, compared with optical metrology demonstrate that this type of sensor is sensitive to the physical edge of the silicon, with only a modest loss of efficiency in the final two rows of pixels. We present the efficiency maps recorded with the microfocus beam and a sample powder diffraction measurement. These results give confidence that this sensor technology can be used effectively in larger arrays of detectors at synchrotron light sources.

Integrated microsystems packaging approach with LCP

NASA Astrophysics Data System (ADS)

Jaynes, Paul; Shacklette, Lawrence W.

2006-05-01

Within the government communication market there is an increasing push to further miniaturize systems with the use of chip-scale packages, flip-chip bonding, and other advances over traditional packaging techniques. Harris' approach to miniaturization includes these traditional packaging advances, but goes beyond this level of miniaturization by combining the functional and structural elements of a system, thus creating a Multi-Functional Structural Circuit (MFSC). An emerging high-frequency, near hermetic, thermoplastic electronic substrate material, Liquid Crystal Polymer (LCP), is the material that will enable the combination of the electronic circuit and the physical structure of the system. The first embodiment of this vision for Harris is the development of a battlefield acoustic sensor module. This paper will introduce LCP and its advantages for MFSC, present an example of the work that Harris has performed, and speak to LCP MFSCs' potential benefits to miniature communications modules and sensor platforms.

Capacitance Variation Induced by Microfluidic Two-Phase Flow across Insulated Interdigital Electrodes in Lab-On-Chip Devices

PubMed Central

Dong, Tao; Barbosa, Cátia

2015-01-01

Microfluidic two-phase flow detection has attracted plenty of interest in various areas of biology, medicine and chemistry. This work presents a capacitive sensor using insulated interdigital electrodes (IDEs) to detect the presence of droplets in a microchannel. This droplet sensor is composed of a glass substrate, patterned gold electrodes and an insulation layer. A polydimethylsiloxane (PDMS) cover bonded to the multilayered structure forms a microchannel. Capacitance variation induced by the droplet passage was thoroughly investigated with both simulation and experimental work. Olive oil and deionized water were employed as the working fluids in the experiments to demonstrate the droplet sensor. The results show a good sensitivity of the droplet with the appropriate measurement connection. This capacitive droplet sensor is promising to be integrated into a lab-on-chip device for in situ monitoring/counting of droplets or bubbles. PMID:25629705

Evaluation of the thermal conductance of flip-chip bonding structure utilizing the measurement based on Fourier's law of heat conduction at steady-state

NASA Astrophysics Data System (ADS)

Wu, Chia-Yu; Huang, Yin-Hsien; Wu, Hsin-Han; Hsieh, Tsung-Eong

2018-06-01

Fourier's law of heat conduction at steady-state was adopted to establish a measurement method utilizing platinum (Pt) thin-film electrodes as the heater and the temperature sensor. The thermal conductivities (κ's) of Pyrex glass, an epoxy resin and a commercial underfill for flip-chip devices were measured and a good agreement with previously reported values was obtained. The thermal boundary resistances (RTBR's) of Pt/sample interfaces were also extracted for discussing their influence on the thermal conduction of samples. Afterward, the flip-chip samples with 2×2 solder joint array utilizing Si wafers as the die and the substrate, without and with the underfills, were prepared and their thermal conductance were measured. For the sample without underfill, the air presenting in the gap of die and the substrate led to the poor thermal conductance of sample. With the insertion of underfills, the thermal conductance of flip-chip samples improved. The resistance to heat transfer across Si/underfill interfaces was also suppressed and to promote the thermal conductance of samples. The thermal properties of underfill and RTBR at Si/underfill interface were further implanted in the calculation of thermal conductance of flip-chip samples containing various solder joint arrays. The increasing number of solder joints diminished the influence of thermal conduction of underfill and RTBR of Si/underfill interface on the thermal conductance of samples. The insertion of underfill with high-κ value might promote the heat conductance of samples containing low-density solder joint arrays; however, it became insignificant in improving the heat conductance of samples containing high-density solder joint arrays.

A compressive-sensing Fourier-transform on-chip Raman spectrometer

NASA Astrophysics Data System (ADS)

Podmore, Hugh; Scott, Alan; Lee, Regina

2018-02-01

We demonstrate a novel compressive sensing Fourier-transform spectrometer (FTS) for snapshot Raman spectroscopy in a compact format. The on-chip FTS consists of a set of planar-waveguide Mach-Zehnder interferometers (MZIs) arrayed on a photonic chip, effecting a discrete Fourier-transform of the input spectrum. Incoherence between the sampling domain (time), and the spectral domain (frequency) permits compressive sensing retrieval using undersampled interferograms for sparse spectra such as Raman emission. In our fabricated device we retain our chosen bandwidth and resolution while reducing the number of MZIs, e.g. the size of the interferogram, to 1/4th critical sampling. This architecture simultaneously reduces chip footprint and concentrates the interferogram in fewer pixels to improve the signal to noise ratio. Our device collects interferogram samples simultaneously, therefore a time-gated detector may be used to separate Raman peaks from sample fluorescence. A challenge for FTS waveguide spectrometers is to achieve multi-aperture high throughput broadband coupling to a large number of single-mode waveguides. A multi-aperture design allows one to increase the bandwidth and spectral resolution without sacrificing optical throughput. In this device, multi-aperture coupling is achieved using an array of microlenses bonded to the surface of the chip, and aligned with a grid of vertically illuminated waveguide apertures. The microlens array accepts a collimated beam with near 100% fill-factor, and the resulting spherical wavefronts are coupled into the single-mode waveguides using 45& mirrors etched into the waveguide layer via focused ion-beam (FIB). The interferogram from the waveguide outputs is imaged using a CCD, and inverted via l1-norm minimization to correctly retrieve a sparse input spectrum.

Microfluidic Chips Controlled with Elastomeric Microvalve Arrays

PubMed Central

Li, Nianzhen; Sip, Chris; Folch, Albert

2007-01-01

Miniaturized microfluidic systems provide simple and effective solutions for low-cost point-of-care diagnostics and high-throughput biomedical assays. Robust flow control and precise fluidic volumes are two critical requirements for these applications. We have developed microfluidic chips featuring elastomeric polydimethylsiloxane (PDMS) microvalve arrays that: 1) need no extra energy source to close the fluidic path, hence the loaded device is highly portable; and 2) allow for microfabricating deep (up to 1 mm) channels with vertical sidewalls and resulting in very precise features. The PDMS microvalves-based devices consist of three layers: a fluidic layer containing fluidic paths and microchambers of various sizes, a control layer containing the microchannels necessary to actuate the fluidic path with microvalves, and a middle thin PDMS membrane that is bound to the control layer. Fluidic layer and control layers are made by replica molding of PDMS from SU-8 photoresist masters, and the thin PDMS membrane is made by spinning PDMS at specified heights. The control layer is bonded to the thin PDMS membrane after oxygen activation of both, and then assembled with the fluidic layer. The microvalves are closed at rest and can be opened by applying negative pressure (e.g., house vacuum). Microvalve closure and opening are automated via solenoid valves controlled by computer software. Here, we demonstrate two microvalve-based microfluidic chips for two different applications. The first chip allows for storing and mixing precise sub-nanoliter volumes of aqueous solutions at various mixing ratios. The second chip allows for computer-controlled perfusion of microfluidic cell cultures. The devices are easy to fabricate and simple to control. Due to the biocompatibility of PDMS, these microchips could have broad applications in miniaturized diagnostic assays as well as basic cell biology studies. PMID:18989408

An effective way to reduce water absorption to terahertz

NASA Astrophysics Data System (ADS)

Wu, Yaxiong; Su, Bo; He, Jingsuo; Zhang, Cong; Zhang, Hongfei; Zhang, Shengbo; Zhang, Cunlin

2018-01-01

Since many vibrations and rotational levels of biomolecules fall within the THz band, THz spectroscopy can be used to identify biological samples. In addition, most biomolecules need to maintain their biological activity in a liquid environment, but water as polar substance has strong absorption to the THz wave. Thus, it is difficult to detect the sample information in aqueous solution using THz wave. In order to prevent the information of biological samples were masked in the solution, many research methods were used to explore how to reduce the water absorption of terahertz. In this paper, we have developed a real-time chemical methodology through transmission Terahertz time-domain spectroscopy (THz-TDS) system. The material of Zeonor 1020r is used as substrate and cover plate, and PDMS as channel interlayer. The transmission of the empty microfluidic chip is more than 80% in the range of 0.2-2.6 THz by THz-TDS system. Then, experiments were carried out using chips, which were filled with different volumes of 1, 2- propanediol, and it has been proved that the microfluidic chip could reduce the water absorption of terahertz. Finally, in order to further explore the reduction of terahertz to water absorption, we inject different concentrations of electrolyte to the chip. The results show that with the addition of different electrolytes, terahertz transmission line has evident changes. It can be taken into account that the electrolyte has different effects about the hydrogen bonds in the aqueous solution. Some of them can promote water molecules clusters, while others destroy them. Based on the basis of microfluidic chip, the discovery of this phenomenon can provide a way that reduces water absorption of terahertz. This work has laid a solid foundation for the subsequent study in reducing water absorption of terahertz.

Carbon nanotubes for thermal interface materials in microelectronic packaging

NASA Astrophysics Data System (ADS)

Lin, Wei

As the integration scale of transistors/devices in a chip/system keeps increasing, effective cooling has become more and more important in microelectronics. To address the thermal dissipation issue, one important solution is to develop thermal interface materials with higher performance. Carbon nanotubes, given their high intrinsic thermal and mechanical properties, and their high thermal and chemical stabilities, have received extensive attention from both academia and industry as a candidate for high-performance thermal interface materials. The thesis is devoted to addressing some challenges related to the potential application of carbon nanotubes as thermal interface materials in microelectronics. These challenges include: 1) controlled synthesis of vertically aligned carbon nanotubes on various bulk substrates via chemical vapor deposition and the fundamental understanding involved; 2) development of a scalable annealing process to improve the intrinsic properties of synthesized carbon nanotubes; 3) development of a state-of-art assembling process to effectively implement high-quality vertically aligned carbon nanotubes into a flip-chip assembly; 4) a reliable thermal measurement of intrinsic thermal transport property of vertically aligned carbon nanotube films; 5) improvement of interfacial thermal transport between carbon nanotubes and other materials. The major achievements are summarized. 1. Based on the fundamental understanding of catalytic chemical vapor deposition processes and the growth mechanism of carbon nanotube, fast synthesis of high-quality vertically aligned carbon nanotubes on various bulk substrates (e.g., copper, quartz, silicon, aluminum oxide, etc.) has been successfully achieved. The synthesis of vertically aligned carbon nanotubes on the bulk copper substrate by the thermal chemical vapor deposition process has set a world record. In order to functionalize the synthesized carbon nanotubes while maintaining their good vertical alignment, an in situ functionalization process has for the first time been demonstrated. The in situ functionalization renders the vertically aligned carbon nanotubes a proper chemical reactivity for forming chemical bonding with other substrate materials such as gold and silicon. 2. An ultrafast microwave annealing process has been developed to reduce the defect density in vertically aligned carbon nanotubes. Raman and thermogravimetric analyses have shown a distinct defect reduction in the CNTs annealed in microwave for 3 min. Fibers spun from the as-annealed CNTs, in comparison with those from the pristine CNTs, show increases of ˜35% and ˜65%, respectively, in tensile strength (˜0.8 GPa) and modulus (˜90 GPa) during tensile testing; an ˜20% improvement in electrical conductivity (˜80000 S m-1) was also reported. The mechanism of the microwave response of CNTs was discussed. Such a microwave annealing process has been extended to the preparation of reduced graphene oxide. 3. Based on the fundamental understanding of interfacial thermal transport and surface chemistry of metals and carbon nanotubes, two major transfer/assembling processes have been developed: molecular bonding and metal bonding. Effective improvement of the interfacial thermal transport has been achieved by the interfacial bonding. 4. The thermal diffusivity of vertically aligned carbon nanotube (VACNT, multi-walled) films was measured by a laser flash technique, and shown to be ˜30 mm2 s-1 along the tube-alignment direction. The calculated thermal conductivities of the VACNT film and the individual CNTs are ˜27 and ˜540 W m-1 K-1, respectively. The technique was verified to be reliable although a proper sampling procedure is critical. A systematic parametric study of the effects of defects, buckling, tip-to-tip contacts, packing density, and tube-tube interaction on the thermal diffusivity was carried out. Defects and buckling decreased the thermal diffusivity dramatically. An increased packing density was beneficial in increasing the collective thermal conductivity of the VACNT film; however, the increased tube-tube interaction in dense VACNT films decreased the thermal conductivity of the individual CNTs. The tip-to-tip contact resistance was shown to be ˜1x10-7 m2 K W -1. The study will shed light on the potential application of VACNTs as thermal interface materials in microelectronic packaging. 5. A combined process of in situ functionalization and microwave curing has been developed to effective enhance the interface between carbon nanotubes and the epoxy matrix. Effective medium theory has been used to analyze the interfacial thermal resistance between carbon nanotubes and polymer matrix, and that between graphite nanoplatlets and polymer matrix.

Focal Plane Alignment Utilizing Optical CMM

NASA Technical Reports Server (NTRS)

Liebe, Carl Christian; Meras, Patrick L.; Clark, Gerald J.; Sedaka, Jack J.; Kaluzny, Joel V.; Hirsch, Brian; Decker, Todd A.; Scholtz, Christopher R.

2012-01-01

In many applications, an optical detector has to be located relative to mechanical reference points. One solution is to specify stringent requirements on (1) mounting the optical detector relative to the chip carrier, (2) soldering the chip carrier onto the printed circuit board (PCB), and (3) installing the PCB to the mechanical structure of the subsystem. Figure 1 shows a sketch of an optical detector mounted relative to mechanical reference with high positional accuracy. The optical detector is typically a fragile wafer that cannot be physically touched by any measurement tool. An optical coordinate measuring machine (CMM) can be used to position optical detectors relative to mechanical reference points. This approach will eliminate all requirements on positional tolerances. The only requirement is that the PCB is manufactured with oversized holes. An exaggerated sketch of this situation is shown in Figure 2. The sketch shows very loose tolerances on mounting the optical detector in the chip carrier, loose tolerance on soldering the chip carrier to the PCB, and finally large tolerance on where the mounting screws are located. The PCB is held with large screws and oversized holes. The PCB is mounted loosely so it can move freely around. The optical CMM measures the mechanical reference points. Based on these measurements, the required positions of the optical detector corners can be calculated. The optical CMM is commanded to go to the position where one detector corner is supposed to be. This is indicated with the cross-hairs in Figure 2(a). This figure is representative of the image of the optical CMM monitor. Using a suitable tapping tool, the PCB is manually tapped around until the corner of the optical detector is at the crosshairs of the optical CMM. The CMM is commanded to another corner, and the process is repeated a number of times until all corners of the optical detector are within a distance of 10 to 30 microns of the required position. The situation is sketched in Figure 2(b) (the figure also shows the tapping tool and where to tap). At this point the fasteners for the PCB are torqued slightly so the PCB can still move. The PCB location is adjusted again with the tapping tool. This process is repeated 3 to 4 times until the final torque is achieved. The oversized mounting holes are then filled with a liquid bonding agent to secure the board in position (not shown in the sketch). A 10- to 30-micron mounting accuracy has been achieved utilizing this method..

Potential Application of BIOMASS Technology at National Space Technology Laboratories and Mississippi Army Ammunition Plant.

DTIC Science & Technology

1980-02-01

fuel. Based on the survey data, wood chips in the NSTL area are sold for $13 to $16 per wet ton ($14 to $18 Der l03 kg wet), bark for $6 to $7 per wet...truck 3 Chip vans (initially) 1 Pickup (3/4 ton) 1 Front-end loader (for handling at chip pile) This equipment combination assumes all material ]-inch...ing sites in chip vans , preferably with live-beds to aid in unloading. At the processing site the chips would be stored in large piles. A Front-end

The role of simulation in the design of a neural network chip

NASA Technical Reports Server (NTRS)

Desai, Utpal; Roppel, Thaddeus A.; Padgett, Mary L.

1993-01-01

An iterative, simulation-based design procedure for a neural network chip is introduced. For this design procedure, the goal is to produce a chip layout for a neural network in which the weights are determined by transistor gate width-to-length ratios. In a given iteration, the current layout is simulated using the circuit simulator SPICE, and layout adjustments are made based on conventional gradient-decent methods. After the iteration converges, the chip is fabricated. Monte Carlo analysis is used to predict the effect of statistical fabrication process variations on the overall performance of the neural network chip.

A miniature on-chip multi-functional ECG signal processor with 30 µW ultra-low power consumption.

PubMed

Liu, Xin; Zheng, Yuan Jin; Phyu, Myint Wai; Zhao, Bin; Je, Minkyu; Yuan, Xiao Jun

2010-01-01

In this paper, a miniature low-power Electrocardiogram (ECG) signal processing application specific integrated circuit (ASIC) chip is proposed. This chip provides multiple critical functions for ECG analysis using a systematic wavelet transform algorithm and a novel SRAM-based ASIC architecture, while achieves low cost and high performance. Using 0.18 µm CMOS technology and 1 V power supply, this ASIC chip consumes only 29 µW and occupies an area of 3 mm(2). This on-chip ECG processor is highly suitable for reliable real-time cardiac status monitoring applications.

Optical interconnection for a polymeric PLC device using simple positional alignment.

PubMed

Ryu, Jin Hwa; Kim, Po Jin; Cho, Cheon Soo; Lee, El-Hang; Kim, Chang-Seok; Jeong, Myung Yung

2011-04-25

This study proposes a simple cost-effective method of optical interconnection between a planar lightwave circuit (PLC) device chip and an optical fiber. It was conducted to minimize and overcome the coupling loss caused by lateral offset which is due to the process tolerance and the dimensional limitation existing between PLC device chips and fiber array blocks with groove structures. A PLC device chip and a fiber array block were simultaneously fabricated in a series of polymer replication processes using the original master. The dimensions (i.e., width and thickness) of the under-clad of the PLC device chip were identical to those of the fiber array block. The PLC device chip and optical fiber were aligned by simple positional control for the vertical direction of the PLC device chip under a particular condition. The insertion loss of the proposed 1 x 2 multimode optical splitter device interconnection was 4.0 dB at 850 nm and the coupling loss was below 0.1 dB compared with single-fiber based active alignment.

Enrichment of wheat chips with omega-3 fatty acid by flaxseed addition: textural and some physicochemical properties.

PubMed

Yuksel, Ferhat; Karaman, Safa; Kayacier, Ahmed

2014-02-15

In the present study, wheat chips enriched with flaxseed flour were produced and response surface methodology was used for the studying the simultaneous effects of flaxseed level (10-20%), frying temperature (160-180 °C) and frying time (40-60 s) on some physicochemical, textural and sensorial properties and fatty acid composition of wheat chips. Ridge analysis was conducted to determine the optimum levels of processing variables. Predictive regression equations with adequate coefficients of determination (R² ≥ 0.705) to explain the effect of processing variables were constructed. Addition of flaxseed flour increased the dry matter and protein content of samples and increase of frying temperature decreased the hardness values of wheat chips samples. Increment in flaxseed level provided an increase in unsaturated fatty acid content namely omega-3 fatty acids of wheat chips samples. Overall acceptability of chips increased with the increase of frying temperature. Ridge analysis showed that maximum taste score would be at flaxseed level = 10%, frying temperature = 180 °C and frying time = 50 s. Copyright © 2013 Elsevier Ltd. All rights reserved.

Senescence sweetening of chip and fry processing potatoes

USDA-ARS?s Scientific Manuscript database

Potato storage makes the crop available over an extended time period, but increases financial risk to growers and end users. Senescence sweetening limits storage duration for chip and fry processing potatoes because it results in an unacceptable accumulation of reducing sugars that result in dark-co...

Characterization of physiological and molecular processes associated with potato response to Zebra chip disease

USDA-ARS?s Scientific Manuscript database

Transcriptional analyses were applied to identify molecular mechanisms associated with the response of leaf and root potato tissues to ‘Ca. Liberibacter solanacearum’ (Lso) infection, causal agent of zebra chip disease (ZC). Lso infection affected several host processes including defense response-, ...

Developing cold-chipping potato varieties by silencing the vacuolar invertase gene

USDA-ARS?s Scientific Manuscript database

Accumulation of reducing sugars during cold storage is a persistent and costly problem for the potato processing industry. High temperature processing of potato tubers with elevated amounts of reducing sugars results in potato chips, fries and other products that are unacceptable to consumers becaus...

Development of environmentally conscious cleaning process for leadless chip carrier assemblies. Final report

DOE Office of Scientific and Technical Information (OSTI.GOV)

Adams, B.E.

1995-04-01

A cross-functional team of process, product, quality, material, and design lab engineers was assembled to develop an environmentally friendly cleaning process for leadless chip carrier assemblies (LCCAs). Using flush and filter testing, Auger surface analysis, GC-Mass spectrophotometry, production yield results, and electrical testing results over an extended testing period, the team developed an aqueous cleaning process for LCCAs. The aqueous process replaced the Freon vapor degreasing/ultrasonic rinse process.

One-step fabrication of an organ-on-a-chip with spatial heterogeneity using a 3D bioprinting technology.

PubMed

Lee, Hyungseok; Cho, Dong-Woo

2016-07-05

Although various types of organs-on-chips have been introduced recently as tools for drug discovery, the current studies are limited in terms of fabrication methods. The fabrication methods currently available not only need a secondary cell-seeding process and result in severe protein absorption due to the material used, but also have difficulties in providing various cell types and extracellular matrix (ECM) environments for spatial heterogeneity in the organs-on-chips. Therefore, in this research, we introduce a novel 3D bioprinting method for organ-on-a-chip applications. With our novel 3D bioprinting method, it was possible to prepare an organ-on-a-chip in a simple one-step fabrication process. Furthermore, protein absorption on the printed platform was very low, which will lead to accurate measurement of metabolism and drug sensitivity. Moreover, heterotypic cell types and biomaterials were successfully used and positioned at the desired position for various organ-on-a-chip applications, which will promote full mimicry of the natural conditions of the organs. The liver organ was selected for the evaluation of the developed method, and liver function was shown to be significantly enhanced on the liver-on-a-chip, which was prepared by 3D bioprinting. Consequently, the results demonstrate that the suggested 3D bioprinting method is easier and more versatile for production of organs-on-chips.

276 nm Substrate-Free Flip-Chip AlGaN Light-Emitting Diodes

NASA Astrophysics Data System (ADS)

Hwang, Seongmo; Morgan, Daniel; Kesler, Amanda; Lachab, Mohamed; Zhang, Bin; Heidari, Ahmad; Nazir, Haseeb; Ahmad, Iftikhar; Dion, Joe; Fareed, Qhalid; Adivarahan, Vinod; Islam, Monirul; Khan, Asif

2011-03-01

Lateral-conduction, substrate-free flip-chip (SFFC) light-emitting diodes (LEDs) with peak emission at 276 nm are demonstrated for the first time. The AlGaN multiple quantum well LED structures were grown by metal-organic chemical vapor deposition (MOCVD) on thick-AlN laterally overgrown on sapphire substrates. To fabricate the SFFC LEDs, a newly-developed laser-assisted ablation process was employed to separate the substrate from the LED chips. The chips had physical dimensions of 1100×900 µm2, and were comprised of four devices each with a 100×100 µm2 junction area. Electrical and optical characterization of the devices revealed no noticeable degradation to their performance due to the laser-lift-off process.

A scalable neural chip with synaptic electronics using CMOS integrated memristors.

PubMed

Cruz-Albrecht, Jose M; Derosier, Timothy; Srinivasa, Narayan

2013-09-27

The design and simulation of a scalable neural chip with synaptic electronics using nanoscale memristors fully integrated with complementary metal-oxide-semiconductor (CMOS) is presented. The circuit consists of integrate-and-fire neurons and synapses with spike-timing dependent plasticity (STDP). The synaptic conductance values can be stored in memristors with eight levels, and the topology of connections between neurons is reconfigurable. The circuit has been designed using a 90 nm CMOS process with via connections to on-chip post-processed memristor arrays. The design has about 16 million CMOS transistors and 73 728 integrated memristors. We provide circuit level simulations of the entire chip performing neuronal and synaptic computations that result in biologically realistic functional behavior.

On-chip temperature-based digital signal processing for customized wireless microcontroller

NASA Astrophysics Data System (ADS)

Farhah Razanah Faezal, Siti; Isa, Mohd Nazrin Md; Harun, Azizi; Nizam Mohyar, Shaiful; Bahari Jambek, Asral

2017-11-01

Increases in die size and power density inside system-on-chip (SoC) design have brought thermal issue inside the system. Uneven heat-up and increasing in temperature offset on-chip has become a major factor that can limits the system performance. This paper presents the design and simulation of a temperature-based digital signal processing for modern system-on-chip design using the Verilog HDL. This design yields continuous monitoring of temperature and reacts to specified conditions. The simulation of the system has been done on Altera Quartus Software v. 14. With system above, microcontroller can achieve nominal power dissipation and operation is within the temperature range due to the incorporate of an interrupt-based system.

Heterogeneous Integration for Reduced Phase Noise and Improved Reliability of Semiconductor Lasers

NASA Astrophysics Data System (ADS)

Srinivasan, Sudharsanan

Significant savings in cost, power and space are possible in existing optical data transmission networks, sensors and metrology equipment through photonic integration. Photonic integration can be broadly classified into two categories, hybrid and monolithic integration. The former involves assembling multiple single functionality optical devices together into a single package including any optical coupling and/or electronic connections. On the other hand monolithic integration assembles many devices or optical functionalities on a single chip so that all the optical connections are on chip and require no external alignment. This provides a substantial improvement in reliability and simplifies testing. Monolithic integration has been demonstrated on both indium phosphide (InP) and silicon (Si) substrates. Integration on larger 300mm Si substrates can further bring down the cost and has been a major area of research in recent years. Furthermore, with increasing interest from industry, the hybrid silicon platform is emerging as a new technology for integrating various active and passive optical elements on a single chip. This is both in the interest of bringing down manufacturing cost through scaling along with continued improvement in performance and to produce multi-functional photonic integrated circuits (PIC). The goal of this work is twofold. First, we show four laser demonstrations that use the hybrid silicon platform to lower phase noise due to spontaneous emission, based on the following two techniques, viz. confinement factor reduction and negative optical feedback. The first two demonstrations are of mode-locked lasers and the next two are of tunable lasers. Some of the key results include; (a) 14dB white frequency noise reduction of a 20GHz radio-frequency (RF) signal from a harmonically mode-locked long cavity laser with greater than 55dB supermode noise suppression, (b) 8dB white frequency noise reduction from a colliding pulse mode-locked laser by reducing the number of quantum wells and a further 6dB noise reduction using coherent photon seeding from long on-chip coupled cavity, (c) linewidth reduction of a tunable laser down to 160kHz using negative optical feedback from coupled ring resonator mirrors, and (d) linewidth reduction of a widely tunable laser down to 50kHz using on-chip coupled cavity feedback effect. Second, we present the results of a reliability study conducted to investigate the influence of molecular wafer bonding between Si and InP on the lifetime of distributed feedback lasers, a common laser source used in optical communication. No degradation in lasing threshold or slope efficiency was observed after aging the lasers for 5000hrs at 70°C and 2500hrs at 85°C. However, among the three chosen bonding interface layer options, the devices with an interface superlattice layer showed a higher yield for lasers and lower dark current values in the on-chip monitor photodiodes after aging.

Integration of image capture and processing: beyond single-chip digital camera

NASA Astrophysics Data System (ADS)

Lim, SukHwan; El Gamal, Abbas

2001-05-01

An important trend in the design of digital cameras is the integration of capture and processing onto a single CMOS chip. Although integrating the components of a digital camera system onto a single chip significantly reduces system size and power, it does not fully exploit the potential advantages of integration. We argue that a key advantage of integration is the ability to exploit the high speed imaging capability of CMOS image senor to enable new applications such as multiple capture for enhancing dynamic range and to improve the performance of existing applications such as optical flow estimation. Conventional digital cameras operate at low frame rates and it would be too costly, if not infeasible, to operate their chips at high frame rates. Integration solves this problem. The idea is to capture images at much higher frame rates than he standard frame rate, process the high frame rate data on chip, and output the video sequence and the application specific data at standard frame rate. This idea is applied to optical flow estimation, where significant performance improvements are demonstrate over methods using standard frame rate sequences. We then investigate the constraints on memory size and processing power that can be integrated with a CMOS image sensor in a 0.18 micrometers process and below. We show that enough memory and processing power can be integrated to be able to not only perform the functions of a conventional camera system but also to perform applications such as real time optical flow estimation.

Use of optical technique for inspection of warpage of IC packages

NASA Astrophysics Data System (ADS)

Toh, Siew-Lok; Chau, Fook S.; Ong, Sim Heng

2001-06-01

The packaging of IC packages has changed over the years, form dual-in-line, wire-bond, and pin-through-hole in printed wiring board technologies in the 1970s to ball grid array, chip scale and surface mount technologies in the 1990s. Reliability has been a big problem for manufacturers for some moisture-sensitive packages. One of the potential problems in plastic IC packages is moisture-induced popcorn effect which can arise during the reflow process. Shearography is a non-destructive inspection technique that may be used to detect the delamination and warpage of IC packages. It is non-contacting and permits a full-field observation of surface displacement derivatives. Another advantage of this technique is that it is able to give the real-time formation of the fringes which indicate flaws in the IC package under real-time simulation condition of Surface Mount Technology (SMT) IR reflow profile. It is extremely fast and convenient to study the true behavior of the packaging deformation during the SMT process. It can be concluded that shearography has the potential for the real- time detection, in situ and non-destructive inspection of IC packages during the surface mount process.

Hybrid integration of carbon nanotubes in silicon photonic structures

NASA Astrophysics Data System (ADS)

Durán-Valdeiglesias, E.; Zhang, W.; Alonso-Ramos, C.; Le Roux, X.; Serna, S.; Hoang, H. C.; Marris-Morini, D.; Cassan, E.; Intonti, F.; Sarti, F.; Caselli, N.; La China, F.; Gurioli, M.; Balestrieri, M.; Vivien, L.; Filoramo, A.

2017-02-01

Silicon photonics, due to its compatibility with the CMOS platform and unprecedented integration capability, has become the preferred solution for the implementation of next generation optical interconnects to accomplish high efficiency, low energy consumption, low cost and device miniaturization in one single chip. However, it is restricted by silicon itself. Silicon does not have efficient light emission or detection in the telecommunication wavelength range (1.3 μm-1.5 μm) or any electro-optic effect (i.e. Pockels effect). Hence, silicon photonic needs to be complemented with other materials for the realization of optically-active devices, including III-V for lasing and Ge for detection. The very different requirement of these materials results in complex fabrication processes that offset the cost-effectiveness of the Si photonics approach. For this purpose, carbon nanotubes (CNTs) have recently been proposed as an attractive one-dimensional light emitting material. Interestingly, semiconducting single walled CNTs (SWNTs) exhibit room-temperature photo- and electro-luminescence in the near-IR that could be exploited for the implementation of integrated nano-sources. They can also be considered for the realization of photo-detectors and optical modulators, since they rely on intrinsically fast non-linear effects, such as Stark and Kerr effect. All these properties make SWNTs ideal candidates in order to fabricate a large variety of optoelectronic devices, including near-IR sources, modulators and photodetectors on Si photonic platforms. In addition, solution processed SWNTs can be integrated on Si using spin-coating or drop-casting techniques, obviating the need of complex epitaxial growth or chip bonding approaches. Here, we report on our recent progress in the coupling of SWNTs light emission into optical resonators implemented on the silicon-on-insulator (SOI) platform. .

Real-Time Electrical Impedimetric Monitoring of Blood Coagulation Process under Temperature and Hematocrit Variations Conducted in a Microfluidic Chip

PubMed Central

Lei, Kin Fong; Chen, Kuan-Hao; Tsui, Po-Hsiang; Tsang, Ngan-Ming

2013-01-01

Blood coagulation is an extremely complicated and dynamic physiological process. Monitoring of blood coagulation is essential to predict the risk of hemorrhage and thrombosis during cardiac surgical procedures. In this study, a high throughput microfluidic chip has been developed for the investigation of the blood coagulation process under temperature and hematocrit variations. Electrical impedance of the whole blood was continuously recorded by on-chip electrodes in contact with the blood sample during coagulation. Analysis of the impedance change of the blood was conducted to investigate the characteristics of blood coagulation process and the starting time of blood coagulation was defined. The study of blood coagulation time under temperature and hematocrit variations was shown a good agreement with results in the previous clinical reports. The electrical impedance measurement for the definition of blood coagulation process provides a fast and easy measurement technique. The microfluidic chip was shown to be a sensitive and promising device for monitoring blood coagulation process even in a variety of conditions. It is found valuable for the development of point-of-care coagulation testing devices that utilizes whole blood sample in microliter quantity. PMID:24116099

Novel Non-Intrusive Trans-Dermal Remote Wireless Micro-Fluidic Monitoring System Applied to Continuous Glucose and Lactate Assays for Casualty Care and Combat Readiness Assessment

DTIC Science & Technology

2004-09-01

identification of the lettered features. 2.2 BFIT Sampling Chip The BFIT sampling chip is a flexible patch-like chip with a multilayer polymeric metal...PPy) and glucose oxidase (GOD). The BFIT fabrication process uses SU8 as a principal structural material consisting of five steps (Figure 2). This...process is a subset of an earlier technology developed for the polymer material PDMS.11,12,13,14,15 The first step was the deposition of a Teflon

Microshear bond strength of composite resins to enamel and porcelain substrates utilizing unfilled versus filled resins.

PubMed

Najafi-Abrandabadi, Ahmad; Najafi-Abrandabadi, Siamak; Ghasemi, Amir; Kotick, Philip G

2014-11-01

Failures such as marginal discoloration and composite chipping are still the problems of tooth-colored restorations on the substrate of enamel and porcelain, which some of these problems are consequently as a result of failures in the bonding layer. Using filled resin has been recently introduced to increase the bond strength of this layer. The aim of this study was to compare the microshear bond strength (μ-SBS) of composite resins to enamel incubated in periods of 24 h and 9 months and porcelain with unfilled resin and flowable composites (filled resin). In this in vitro study, two groups of 75 enamel samples with different storage times (24 h and 9 months) and a group of 75 porcelain samples were used. They were divided into 5 experimental groups of 15 samples in each. Composite cylinders in tygon tubes were bonded on the surface of acid-etched enamel and pretreated porcelain. Wave, Wave MV, Wave HV, Grandioflow and Margin Bond were used as bonding agents. The μ-SBS was measured at the speed of 1.0 mm/min. The bond strengths were analyzed with one-way analysis of variance (ANOVA) test followed by Tukey test. P < 0.05 was selected as the level of statistical significance in this study. The results showed that for enamel (24 h), the μ-SBS of the Wave MV and Wave HV groups were significantly lower than the Margin Bond group. Tukey test indicated the absence of a significant difference between the μ-SBS of the Wave group and the Margin Bond group. However, the μ-SBS of the Grandioflow group was significantly higher than the one for the Margin Bond as a bonding agent. In enamel (9 months), there was a significant difference between the Grandioflow and Margin Bond groups. Regarding bonding to the porcelain the one-way ANOVA test did not show a significant difference among the groups. This study revealed that flowable composites (filled resins) can be used instead of unfilled resins in bonding composite resins to enamel and porcelain substrates.

Experimental Investigations on the Surface-Driven Capillary Flow of Aqueous Microparticle Suspensions in the Microfluidic Laboratory-On Systems

NASA Astrophysics Data System (ADS)

Mukhopadhyay, Subhadeep

In this work, total 1592 individual leakage-free polymethylmethacrylate (PMMA) microfluidic devices as laboratory-on-a-chip systems are fabricated by maskless lithography, hot embossing lithography, and direct bonding technique. Total 1094 individual Audio Video Interleave Files as experimental outputs related to the surface-driven capillary flow have been recorded and analyzed. The influence of effective viscosity, effect of surface wettability, effect of channel aspect ratio, and effect of centrifugal force on the surface-driven microfluidic flow of aqueous microparticle suspensions have been successfully and individually investigated in these laboratory-on-a-chip systems. Also, 5 micron polystyrene particles have been separated from the aqueous microparticle suspensions in the microfluidic lab-on-a-chip systems of modified design with 98% separation efficiency, and 10 micron polystyrene particles have been separated with 100% separation efficiency. About the novelty of this work, the experimental investigations have been performed on the surface-driven microfluidic flow of aqueous microparticle suspensions with the investigations on the separation time in particle-size based separation mechanism to control these suspensions in the microfluidic lab-on-a-chip systems. This research work contains a total of 10,112 individual experimental outputs obtained using total 30 individual instruments by author’s own hands-on completely during more than three years continuously. Author has performed the experimental investigations on both the fluid statics and fluid dynamics to develop an automated fluid machine.

Rapid and cheap prototyping of a microfluidic cell sorter.

PubMed

Islam, M Z; McMullin, J N; Tsui, Y Y

2011-05-01

Development of a microfluidic device is generally based on fabrication-design-fabrication loop, as, unlike the microelectronics design, there is no rigorous simulation-based verification of the chip before fabrication. This usually results in extremely long, and hence expensive, product development cycle if micro/nano fabrication facilities are used from the beginning of the cycle. Here, we illustrate a novel approach of device prototyping that is fast, cheap, reliable, and most importantly, this technique can be adopted even if no state-of-the-art microfabrication facility is available. A water-jet machine is used to cut the desired microfluidic channels into a thin steel plate which is then used as a template to cut the channels into a thin sheet of a transparent and cheap polymer material named Surlyn® by using a Hot Knife™. The feature-inscribed Surlyn sheet is bonded in between two microscope glass slides by utilizing the techniques which has been being used in curing polymer film between dual layer automotive glasses for years. Optical fibers are inserted from the sides of chip and are bonded by UV epoxy. To study the applicability of this prototyping approach, we made a basic microfluidic sorter and tested its functionalities. Sample containing microparticles is injected into the chip. Light from a 532-nm diode laser is coupled into the optical fiber that delivers light to the interrogation region in the channel. The emitted light from the particle is collected by a photodiode (PD) placed over the detection window. The device sorts the particles into the sorted or waste outlets depending on the level of the PD signal. We used fluorescent latex beads to test the detection and sorting functionalities of the device. We found that the system could detect all the beads that passed through its geometric observation region and could sort almost all the beads it detected. Copyright © 2011 International Society for Advancement of Cytometry.

A MEMS-based, wireless, biometric-like security system

NASA Astrophysics Data System (ADS)

Cross, Joshua D.; Schneiter, John L.; Leiby, Grant A.; McCarter, Steven; Smith, Jeremiah; Budka, Thomas P.

2010-04-01

We present a system for secure identification applications that is based upon biometric-like MEMS chips. The MEMS chips have unique frequency signatures resulting from fabrication process variations. The MEMS chips possess something analogous to a "voiceprint". The chips are vacuum encapsulated, rugged, and suitable for low-cost, highvolume mass production. Furthermore, the fabrication process is fully integrated with standard CMOS fabrication methods. One is able to operate the MEMS-based identification system similarly to a conventional RFID system: the reader (essentially a custom network analyzer) detects the power reflected across a frequency spectrum from a MEMS chip in its vicinity. We demonstrate prototype "tags" - MEMS chips placed on a credit card-like substrate - to show how the system could be used in standard identification or authentication applications. We have integrated power scavenging to provide DC bias for the MEMS chips through the use of a 915 MHz source in the reader and a RF-DC conversion circuit on the tag. The system enables a high level of protection against typical RFID hacking attacks. There is no need for signal encryption, so back-end infrastructure is minimal. We believe this system would make a viable low-cost, high-security system for a variety of identification and authentication applications.

Dynamics of cells function on laser cell-chip system

NASA Astrophysics Data System (ADS)

Kushibiki, Toshihiro; Sano, Tomoko; Ishii, Katsunori; Yoshihashi-Suzuki, Sachiko; Awazu, Kunio

2006-02-01

A new type of cell-cultivation system based on laser processing has been developed for the on-chip cultivation of living cells. We introduce a "laser cell-chip", on which migration of cells, such as stem cells, tumor cells or immunocompetent cells, can be observed. A sheet prepared from epoxy resin was processed by KrF excimer laser (248 nm, 1.6 J/cm2) for preparation of microgrooved surfaces with various groove width, spacing, and depth. A laser cell-chip can make kinetic studies of cell migration depending on the concentration gradient of a chemoattractant. In this study, megakaryocytes were used for the migration on a groove of laser cell-chip by the concentration gradient of the stromal cell derived factor 1 (SDF-1/CXCL12). SDF-1/CXCL12 plays an important and unique role in the regulation of stem/progenitor cell trafficking. A megakaryocyte was migrated on a groove of laser cell-chip depending on the optical concentration gradient of SDF-1/CXCL12. Since SDF-1/CXCL12-induced migration of mature megakaryocyte was known to increase the platelet production in the bone marrow extravascular space, the diagnosis of cell migration on laser cell-chip could provide a new strategy to potentially reconstitute hematopoiesis and avoid life-threatening hemorrhage after myelosuppression or bone marrow failure.

Application of the ANNA neural network chip to high-speed character recognition.

PubMed

Sackinger, E; Boser, B E; Bromley, J; Lecun, Y; Jackel, L D

1992-01-01

A neural network with 136000 connections for recognition of handwritten digits has been implemented using a mixed analog/digital neural network chip. The neural network chip is capable of processing 1000 characters/s. The recognition system has essentially the same rate (5%) as a simulation of the network with 32-b floating-point precision.

Microluminometer chip and method to measure bioluminescence

DOEpatents

Simpson, Michael L [Knoxville, TN; Paulus, Michael J [Knoxville, TN; Sayler, Gary S [Blaine, TN; Applegate, Bruce M [West Lafayette, IN; Ripp, Steven A [Knoxville, TN

2008-05-13

An integrated microluminometer includes an integrated circuit chip having at least one n-well/p-substrate junction photodetector for converting light received into a photocurrent, and a detector on the chip for processing the photocurrent. A distributed electrode configuration including a plurality of spaced apart electrodes disposed on an active region of the photodetector is preferably used to raise efficiency.

Apparatus for converting biomass to a pumpable slurry

DOEpatents

Ergun, Sabri; Schaleger, Larry L.; Wrathall, James A.; Yaghoubzadeh, Nasser

1986-01-01

An apparatus used in the pretreatment of wood chips in a process for converting biomass to a liquid hydrocarbonaceous fuel. The apparatus functions to break down the wood chips to a size distribution that can be readily handled in a slurry form. Low maintenance operation is obtained by hydrolyzing the chips in a pressure vessel having no moving parts.

Non-destructive NIR detection of Zebra Chip disease in whole potatoes (abstract)

USDA-ARS?s Scientific Manuscript database

Potatoes are the 4th biggest food crop worldwide and the leading vegetable crop in the U.S., accounting for 15 percent of vegetable sales. Over 50% of potatoes are consumed as processed products such as French fries and chips. Zebra Chip (ZC) is a disease of potatoes that causes brown discoloration ...

Cassava chip (Manihot esculenta Crantz) as an energy source for ruminant feeding.

PubMed

Wanapat, Metha; Kang, Sungchhang

2015-12-01

Cassava ( Manihot esculenta Crantz) is widely grown in sub-tropical and tropical areas, producing roots as an energy source while the top biomass including leaves and immature stems can be sun-dried and used as cassava hay. Cassava roots can be processed as dried chip or pellet. It is rich in soluble carbohydrate (75 to 85%) but low in crude protein (2 to 3%). Its energy value is comparable to corn meal but has a relatively higher rate of rumen degradation. Higher levels of non-protein nitrogen especially urea (1 to 4%) can be successfully incorporated in concentrates containing cassava chip as an energy source. Cassava chip can also be processed with urea and other ingredients (tallow, sulfur, raw banana meal, cassava hay, and soybean meal) to make products such as cassarea, cassa-ban, and cassaya. Various studies have been conducted in ruminants using cassava chip to replace corn meal in the concentrate mixtures and have revealed satisfactory results in rumen fermentation efficiency and the subsequent production of meat and milk. In addition, it was advantageous when used in combination with rice bran in the concentrate supplement. Practical home-made-concentrate using cassava chip can be easily prepared for use on farms. A recent development has involved enriching protein in cassava chips, yielding yeast fermented cassava chip protein (YEFECAP) of up to 47.5% crude protein, which can be used to replace soybean meal. It is therefore, recommended to use cassava chip as an alternative source of energy to corn meal when the price is economical and it is locally available.

Integrated sample-to-detection chip for nucleic acid test assays.

PubMed

Prakash, R; Pabbaraju, K; Wong, S; Tellier, R; Kaler, K V I S

2016-06-01

Nucleic acid based diagnostic techniques are routinely used for the detection of infectious agents. Most of these assays rely on nucleic acid extraction platforms for the extraction and purification of nucleic acids and a separate real-time PCR platform for quantitative nucleic acid amplification tests (NATs). Several microfluidic lab on chip (LOC) technologies have been developed, where mechanical and chemical methods are used for the extraction and purification of nucleic acids. Microfluidic technologies have also been effectively utilized for chip based real-time PCR assays. However, there are few examples of microfluidic systems which have successfully integrated these two key processes. In this study, we have implemented an electro-actuation based LOC micro-device that leverages multi-frequency actuation of samples and reagents droplets for chip based nucleic acid extraction and real-time, reverse transcription (RT) PCR (qRT-PCR) amplification from clinical samples. Our prototype micro-device combines chemical lysis with electric field assisted isolation of nucleic acid in a four channel parallel processing scheme. Furthermore, a four channel parallel qRT-PCR amplification and detection assay is integrated to deliver the sample-to-detection NAT chip. The NAT chip combines dielectrophoresis and electrostatic/electrowetting actuation methods with resistive micro-heaters and temperature sensors to perform chip based integrated NATs. The two chip modules have been validated using different panels of clinical samples and their performance compared with standard platforms. This study has established that our integrated NAT chip system has a sensitivity and specificity comparable to that of the standard platforms while providing up to 10 fold reduction in sample/reagent volumes.

Fully 3D-Integrated Pixel Detectors for X-Rays

DOE PAGES

Deptuch, Grzegorz W.; Gabriella, Carini; Enquist, Paul; ...

2016-01-01

The vertically integrated photon imaging chip (VIPIC1) pixel detector is a stack consisting of a 500-μm-thick silicon sensor, a two-tier 34-μm-thick integrated circuit, and a host printed circuit board (PCB). The integrated circuit tiers were bonded using the direct bonding technology with copper, and each tier features 1-μm-diameter through-silicon vias that were used for connections to the sensor on one side, and to the host PCB on the other side. The 80-μm-pixel-pitch sensor was the direct bonding technology with nickel bonded to the integrated circuit. The stack was mounted on the board using Sn–Pb balls placed on a 320-μm pitch,more » yielding an entirely wire-bond-less structure. The analog front-end features a pulse response peaking at below 250 ns, and the power consumption per pixel is 25 μW. We successful completed the 3-D integration and have reported here. Additionally, all pixels in the matrix of 64 × 64 pixels were responding on well-bonded devices. Correct operation of the sparsified readout, allowing a single 153-ns bunch timing resolution, was confirmed in the tests on a synchrotron beam of 10-keV X-rays. An equivalent noise charge of 36.2 e - rms and a conversion gain of 69.5 μV/e - with 2.6 e - rms and 2.7 μV/e - rms pixel-to-pixel variations, respectively, were measured.« less

DOE Office of Scientific and Technical Information (OSTI.GOV)

Deptuch, Grzegorz W.; Gabriella, Carini; Enquist, Paul

The vertically integrated photon imaging chip (VIPIC1) pixel detector is a stack consisting of a 500-μm-thick silicon sensor, a two-tier 34-μm-thick integrated circuit, and a host printed circuit board (PCB). The integrated circuit tiers were bonded using the direct bonding technology with copper, and each tier features 1-μm-diameter through-silicon vias that were used for connections to the sensor on one side, and to the host PCB on the other side. The 80-μm-pixel-pitch sensor was the direct bonding technology with nickel bonded to the integrated circuit. The stack was mounted on the board using Sn–Pb balls placed on a 320-μm pitch,more » yielding an entirely wire-bond-less structure. The analog front-end features a pulse response peaking at below 250 ns, and the power consumption per pixel is 25 μW. We successful completed the 3-D integration and have reported here. Additionally, all pixels in the matrix of 64 × 64 pixels were responding on well-bonded devices. Correct operation of the sparsified readout, allowing a single 153-ns bunch timing resolution, was confirmed in the tests on a synchrotron beam of 10-keV X-rays. An equivalent noise charge of 36.2 e - rms and a conversion gain of 69.5 μV/e - with 2.6 e - rms and 2.7 μV/e - rms pixel-to-pixel variations, respectively, were measured.« less

An Embedded Fusion Processor

DTIC Science & Technology

2000-10-01

available from rooksj~,rl.af.mil [4] J. Lyke and G. Forman "Microengineering Aerospace Systems" H . Helvajian editor, The Aerospace Press 1999, Chapter 8...e h I O iinterface chip, and Synchronous Dynamic Random 1K-byte. The only consequence is that after the FIFO is Access Memory (SDRAM). Each interface...shown in figure 4a, that will be used for the 1/O interconnects in place of the perimeter bond pads used in the MCM3A. The 6’ h layer is used to

Investigation of discrete component chip mounting technology for hybrid microelectronic circuits

NASA Technical Reports Server (NTRS)

Caruso, S. V.; Honeycutt, J. O.

1975-01-01

The use of polymer adhesives for high reliability microcircuit applications is a radical deviation from past practices in electronic packaging. Bonding studies were performed using two gold-filled conductive adhesives, 10/90 tin/lead solder and Indalloy no. 7 solder. Various types of discrete components were mounted on ceramic substrates using both thick-film and thin-film metallization. Electrical and mechanical testing were performed on the samples before and after environmental exposure to MIL-STD-883 screening tests.

Optical pumping of deep traps in AlGaN/GaN-on-Si HEMTs using an on-chip Schottky-on-heterojunction light-emitting diode

DOE Office of Scientific and Technical Information (OSTI.GOV)

Li, Baikui; Tang, Xi; Chen, Kevin J., E-mail: eekjchen@ust.hk

2015-03-02

In this work, by using an on-chip integrated Schottky-on-heterojunction light-emitting diode (SoH-LED) which is seamlessly integrated with the AlGaN/GaN high electron mobility transistor (HEMT), we studied the effect of on-chip light illumination on the de-trapping processes of electrons from both surface and bulk traps. Surface trapping was generated by applying OFF-state drain bias stress, while bulk trapping was generated by applying positive substrate bias stress. The de-trapping processes of surface and/or bulk traps were monitored by measuring the recovery of dynamic on-resistance R{sub on} and/or threshold voltage V{sub th} of the HEMT. The results show that the recovery processes ofmore » both dynamic R{sub on} and threshold voltage V{sub th} of the HEMT can be accelerated by the on-chip SoH-LED light illumination, demonstrating the potentiality of on-chip hybrid opto-HEMTs to minimize the influences of traps during dynamic operation of AlGaN/GaN power HEMTs.« less

A 1-channel 3-band wide dynamic range compression chip for vibration transducer of implantable hearing aids.

PubMed

Kim, Dongwook; Seong, Kiwoong; Kim, Myoungnam; Cho, Jinho; Lee, Jyunghyun

2014-01-01

In this paper, a digital audio processing chip which uses a wide dynamic range compression (WDRC) algorithm is designed and implemented for implantable hearing aids system. The designed chip operates at a single voltage of 3.3V and drives a 16 bit parallel input and output at 32 kHz sample. The designed chip has 1-channel 3-band WDRC composed of a FIR filter bank, a level detector, and a compression part. To verify the performance of the designed chip, we measured the frequency separations of bands and compression gain control to reflect the hearing threshold level.

The E3 Ligase CHIP: Insights into Its Structure and Regulation

PubMed Central

Paul, Indranil; Ghosh, Mrinal K.

2014-01-01

The carboxy-terminus of Hsc70 interacting protein (CHIP) is a cochaperone E3 ligase containing three tandem repeats of tetratricopeptide (TPR) motifs and a C-terminal U-box domain separated by a charged coiled-coil region. CHIP is known to function as a central quality control E3 ligase and regulates several proteins involved in a myriad of physiological and pathological processes. Recent studies have highlighted varied regulatory mechanisms operating on the activity of CHIP which is crucial for cellular homeostasis. In this review article, we give a concise account of our current knowledge on the biochemistry and regulation of CHIP. PMID:24868554

Laser doppler blood flow imaging using a CMOS imaging sensor with on-chip signal processing.

PubMed

He, Diwei; Nguyen, Hoang C; Hayes-Gill, Barrie R; Zhu, Yiqun; Crowe, John A; Gill, Cally; Clough, Geraldine F; Morgan, Stephen P

2013-09-18

The first fully integrated 2D CMOS imaging sensor with on-chip signal processing for applications in laser Doppler blood flow (LDBF) imaging has been designed and tested. To obtain a space efficient design over 64 × 64 pixels means that standard processing electronics used off-chip cannot be implemented. Therefore the analog signal processing at each pixel is a tailored design for LDBF signals with balanced optimization for signal-to-noise ratio and silicon area. This custom made sensor offers key advantages over conventional sensors, viz. the analog signal processing at the pixel level carries out signal normalization; the AC amplification in combination with an anti-aliasing filter allows analog-to-digital conversion with a low number of bits; low resource implementation of the digital processor enables on-chip processing and the data bottleneck that exists between the detector and processing electronics has been overcome. The sensor demonstrates good agreement with simulation at each design stage. The measured optical performance of the sensor is demonstrated using modulated light signals and in vivo blood flow experiments. Images showing blood flow changes with arterial occlusion and an inflammatory response to a histamine skin-prick demonstrate that the sensor array is capable of detecting blood flow signals from tissue.

Progress in a novel architecture for high performance processing

NASA Astrophysics Data System (ADS)

Zhang, Zhiwei; Liu, Meng; Liu, Zijun; Du, Xueliang; Xie, Shaolin; Ma, Hong; Ding, Guangxin; Ren, Weili; Zhou, Fabiao; Sun, Wenqin; Wang, Huijuan; Wang, Donglin

2018-04-01

The high performance processing (HPP) is an innovative architecture which targets on high performance computing with excellent power efficiency and computing performance. It is suitable for data intensive applications like supercomputing, machine learning and wireless communication. An example chip with four application-specific integrated circuit (ASIC) cores which is the first generation of HPP cores has been taped out successfully under Taiwan Semiconductor Manufacturing Company (TSMC) 40 nm low power process. The innovative architecture shows great energy efficiency over the traditional central processing unit (CPU) and general-purpose computing on graphics processing units (GPGPU). Compared with MaPU, HPP has made great improvement in architecture. The chip with 32 HPP cores is being developed under TSMC 16 nm field effect transistor (FFC) technology process and is planed to use commercially. The peak performance of this chip can reach 4.3 teraFLOPS (TFLOPS) and its power efficiency is up to 89.5 gigaFLOPS per watt (GFLOPS/W).

42 CFR 431.400 - Basis and purpose.

Code of Federal Regulations, 2013 CFR

2013-10-01

... CHIP demonstration projects that provide for: (i) A process for public notice and comment at the State... Medicaid and CHIP demonstration projects that provides for transparency and public participation. ...

42 CFR 431.400 - Basis and purpose.

Code of Federal Regulations, 2012 CFR

2012-10-01

... CHIP demonstration projects that provide for: (i) A process for public notice and comment at the State... Medicaid and CHIP demonstration projects that provides for transparency and public participation. ...

42 CFR 431.400 - Basis and purpose.

Code of Federal Regulations, 2014 CFR

2014-10-01

... CHIP demonstration projects that provide for: (i) A process for public notice and comment at the State... Medicaid and CHIP demonstration projects that provides for transparency and public participation. ...

Fundamentals of cutting.

PubMed

Williams, J G; Patel, Y

2016-06-06

The process of cutting is analysed in fracture mechanics terms with a view to quantifying the various parameters involved. The model used is that of orthogonal cutting with a wedge removing a layer of material or chip. The behaviour of the chip is governed by its thickness and for large radii of curvature the chip is elastic and smooth cutting occurs. For smaller thicknesses, there is a transition, first to plastic bending and then to plastic shear for small thicknesses and smooth chips are formed. The governing parameters are tool geometry, which is principally the wedge angle, and the material properties of elastic modulus, yield stress and fracture toughness. Friction can also be important. It is demonstrated that the cutting process may be quantified via these parameters, which could be useful in the study of cutting in biology.

3D MOEMS-based optical micro-bench platform for the miniaturization of sensing devices

NASA Astrophysics Data System (ADS)

Garcia-Blanco, Sonia; Caron, Jean-Sol; Leclair, Sébastien; Topart, Patrice A.; Jerominek, Hubert

2008-02-01

As we enter into the 21st century, the need for miniaturized portable diagnostic devices is increasing continuously. Portable devices find important applications for point-of-care diagnostics, patient self-monitoring and in remote areas, such as unpopulated regions where the cost of large laboratory facilities is not justifiable, underdeveloped countries and other remote locations such as space missions. The advantage of miniaturized sensing optical systems includes not only the reduced weight and size but also reduced cost, decreased time to results and robustness (e.g. no need for frequent re-alignments). Recent advances in micro-fabrication and assembly technologies have enabled important developments in the field of miniaturized sensing systems. INO has developed a technology platform for the three dimensional integration of MOEMS on an optical microbench. Building blocks of the platform include microlenses, micromirrors, dichroic beamsplitters, filters and optical fibers, which can be positioned using passive alignment structures to build the desired miniaturised system. The technology involves standard microfabrication, thick resist UV-lithography, thick metal electroplating, soldering, replication in sol-gel materials and flip-chip bonding processes. The technology is compatible with wafer-to-wafer bonding. A placement accuracy of +/- 5 μm has been demonstrated thanks to the integration of alignment marks co registered with other optical elements fabricated on different wafers. In this paper, the building blocks of the technology will be detailed. The design and fabrication of a 5x5 channels light processing unit including optical fibers, mirrors and collimating microlenses will be described. Application of the technology to various kinds of sensing devices will be discussed.

Technology for On-Chip Qubit Control with Microfabricated Surface Ion Traps

DOE Office of Scientific and Technical Information (OSTI.GOV)

Highstrete, Clark; Scott, Sean Michael; Nordquist, Christopher D.

2013-11-01

Trapped atomic ions are a leading physical system for quantum information processing. However, scalability and operational fidelity remain limiting technical issues often associated with optical qubit control. One promising approach is to develop on-chip microwave electronic control of ion qubits based on the atomic hyperfine interaction. This project developed expertise and capabilities at Sandia toward on-chip electronic qubit control in a scalable architecture. The project developed a foundation of laboratory capabilities, including trapping the 171Yb + hyperfine ion qubit and developing an experimental microwave coherent control capability. Additionally, the project investigated the integration of microwave device elements with surface ionmore » traps utilizing Sandia’s state-of-the-art MEMS microfabrication processing. This effort culminated in a device design for a multi-purpose ion trap experimental platform for investigating on-chip microwave qubit control, laying the groundwork for further funded R&D to develop on-chip microwave qubit control in an architecture that is suitable to engineering development.« less

Ubc13 and COOH Terminus of Hsp70-interacting Protein (CHIP) Are Required for Growth Hormone Receptor Endocytosis*

PubMed Central

Slotman, Johan A.; da Silva Almeida, Ana C.; Hassink, Gerco C.; van de Ven, Robert H. A.; van Kerkhof, Peter; Kuiken, Hendrik J.; Strous, Ger J.

2012-01-01

Growth hormone receptor (GHR) endocytosis is a highly regulated process that depends on the binding and activity of the multimeric ubiquitin ligase, SCFβTrCP (Skp Cullin F-box). Despite a specific interaction between β-transducin repeat-containing protein (βTrCP) and the GHR, and a strict requirement for ubiquitination activity, the receptor is not an obligatory target for SCFβTrCP-directed Lys48 polyubiquitination. We now show that also Lys63-linked ubiquitin chain formation is required for GHR endocytosis. We identified both the ubiquitin-conjugating enzyme Ubc13 and the ubiquitin ligase COOH terminus of Hsp70 interacting protein (CHIP) as being connected to this process. Ubc13 activity and its interaction with CHIP precede endocytosis of GHR. In addition to βTrCP, CHIP interacts specifically with the cytosolic tails of the dimeric GHR, identifying both Ubc13 and CHIP as novel factors in the regulation of cell surface availability of GHR. PMID:22433856

Chip level modeling of LSI devices

NASA Technical Reports Server (NTRS)

Armstrong, J. R.

1984-01-01

The advent of Very Large Scale Integration (VLSI) technology has rendered the gate level model impractical for many simulation activities critical to the design automation process. As an alternative, an approach to the modeling of VLSI devices at the chip level is described, including the specification of modeling language constructs important to the modeling process. A model structure is presented in which models of the LSI devices are constructed as single entities. The modeling structure is two layered. The functional layer in this structure is used to model the input/output response of the LSI chip. A second layer, the fault mapping layer, is added, if fault simulations are required, in order to map the effects of hardware faults onto the functional layer. Modeling examples for each layer are presented. Fault modeling at the chip level is described. Approaches to realistic functional fault selection and defining fault coverage for functional faults are given. Application of the modeling techniques to single chip and bit slice microprocessors is discussed.

Hydrothermal carbonization for the preparation of hydrochars from glucose, cellulose, chitin, chitosan and wood chips via low-temperature and their characterization.

PubMed

Simsir, Hamza; Eltugral, Nurettin; Karagoz, Selhan

2017-12-01

In this work, the hydrothermal carbonization of glucose, cellulose, chitin, chitosan and wood chips at 200°C at processing times between 6 and 48h was studied. The carbonization degree of wood chips, cellulose and chitosan obviously increases as function of time. The heating value of glucose increases to 88% upon carbonization for 48h, while it is only 5% for chitin. It is calculated to be between 44 and 73% for wood chips, chitosan and cellulose. Glucose yielded complete formation of spherical hydrochar structures at a shorter processing time, as low as 12h. However, carbon spheres with narrow size (∼560nm) distribution were obtained upon 48h of residence time. Cellulose and wood chips yielded a similar morphology with an irregular size distribution. Chitin seemed not to undergo hydrothermal carbonization, whereas densely aggregated spheres of a uniform size around 42nm were obtained from chitosan after 18h. Copyright © 2017 Elsevier Ltd. All rights reserved.

Stochastic architecture for Hopfield neural nets

NASA Technical Reports Server (NTRS)

Pavel, Sandy

1992-01-01

An expandable stochastic digital architecture for recurrent (Hopfield like) neural networks is proposed. The main features and basic principles of stochastic processing are presented. The stochastic digital architecture is based on a chip with n full interconnected neurons with a pipeline, bit processing structure. For large applications, a flexible way to interconnect many such chips is provided.

Graphene/Si CMOS Hybrid Hall Integrated Circuits

PubMed Central

Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

2014-01-01

Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18 um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process. PMID:24998222

Graphene/Si CMOS hybrid hall integrated circuits.

PubMed

Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

2014-07-07

Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18 um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process.

Transportable GPU (General Processor Units) chip set technology for standard computer architectures

NASA Astrophysics Data System (ADS)

Fosdick, R. E.; Denison, H. C.

1982-11-01

The USAFR-developed GPU Chip Set has been utilized by Tracor to implement both USAF and Navy Standard 16-Bit Airborne Computer Architectures. Both configurations are currently being delivered into DOD full-scale development programs. Leadless Hermetic Chip Carrier packaging has facilitated implementation of both architectures on single 41/2 x 5 substrates. The CMOS and CMOS/SOS implementations of the GPU Chip Set have allowed both CPU implementations to use less than 3 watts of power each. Recent efforts by Tracor for USAF have included the definition of a next-generation GPU Chip Set that will retain the application-proven architecture of the current chip set while offering the added cost advantages of transportability across ISO-CMOS and CMOS/SOS processes and across numerous semiconductor manufacturers using a newly-defined set of common design rules. The Enhanced GPU Chip Set will increase speed by an approximate factor of 3 while significantly reducing chip counts and costs of standard CPU implementations.

ChIP-seq.

PubMed

Kim, Tae Hoon; Dekker, Job

2018-05-01

Owing to its digital nature, ChIP-seq has become the standard method for genome-wide ChIP analysis. Using next-generation sequencing platforms (notably the Illumina Genome Analyzer), millions of short sequence reads can be obtained. The densities of recovered ChIP sequence reads along the genome are used to determine the binding sites of the protein. Although a relatively small amount of ChIP DNA is required for ChIP-seq, the current sequencing platforms still require amplification of the ChIP DNA by ligation-mediated PCR (LM-PCR). This protocol, which involves linker ligation followed by size selection, is the standard ChIP-seq protocol using an Illumina Genome Analyzer. The size-selected ChIP DNA is amplified by LM-PCR and size-selected for the second time. The purified ChIP DNA is then loaded into the Genome Analyzer. The ChIP DNA can also be processed in parallel for ChIP-chip results. © 2018 Cold Spring Harbor Laboratory Press.

Physical and sensory properties of ready to eat apple chips produced by osmo-convective drying.

PubMed

Velickova, Elena; Winkelhausen, Eleonora; Kuzmanova, Slobodanka

2014-12-01

The low cost raw material, apple variety Idared, was turned into value-added product, apple chips. The apple chips were produced in a two-step process consisting of osmotic treatment and conventional drying. Osmotic treatment was carried out in 40 % glucose solution at room temperature, followed by convective drying at 105 °C, till reaching water activity of 0.3. Mechanical properties of the apple chips measured by compression and penetration tests were correlated with the sorption properties. The low browning index, 25.5 and high whitening index, 63.7, proved the good retention of the color of the apple chips. The instrumental characteristics of the apple chips were correlated with the sensory characteristics of the product. The new product was accepted by the 95 % of the panelists. The stored apple chips under modified atmosphere showed no significant changes in the quality parameters over 6 month period.

Wafer-level vacuum/hermetic packaging technologies for MEMS

NASA Astrophysics Data System (ADS)

Lee, Sang-Hyun; Mitchell, Jay; Welch, Warren; Lee, Sangwoo; Najafi, Khalil

2010-02-01

An overview of wafer-level packaging technologies developed at the University of Michigan is presented. Two sets of packaging technologies are discussed: (i) a low temperature wafer-level packaging processes for vacuum/hermeticity sealing, and (ii) an environmentally resistant packaging (ERP) technology for thermal and mechanical control as well as vacuum packaging. The low temperature wafer-level encapsulation processes are implemented using solder bond rings which are first patterned on a cap wafer and then mated with a device wafer in order to encircle and encapsulate the device at temperatures ranging from 200 to 390 °C. Vacuum levels below 10 mTorr were achieved with yields in an optimized process of better than 90%. Pressures were monitored for more than 4 years yielding important information on reliability and process control. The ERP adopts an environment isolation platform in the packaging substrate. The isolation platform is designed to provide low power oven-control, vibration isolation and shock protection. It involves batch flip-chip assembly of a MEMS device onto the isolation platform wafer. The MEMS device and isolation structure are encapsulated at the wafer-level by another substrate with vertical feedthroughs for vacuum/hermetic sealing and electrical signal connections. This technology was developed for high performance gyroscopes, but can be applied to any type of MEMS device.

Design and fabrication of vertically-integrated CMOS image sensors.

PubMed

Skorka, Orit; Joseph, Dileepan

2011-01-01

Technologies to fabricate integrated circuits (IC) with 3D structures are an emerging trend in IC design. They are based on vertical stacking of active components to form heterogeneous microsystems. Electronic image sensors will benefit from these technologies because they allow increased pixel-level data processing and device optimization. This paper covers general principles in the design of vertically-integrated (VI) CMOS image sensors that are fabricated by flip-chip bonding. These sensors are composed of a CMOS die and a photodetector die. As a specific example, the paper presents a VI-CMOS image sensor that was designed at the University of Alberta, and fabricated with the help of CMC Microsystems and Micralyne Inc. To realize prototypes, CMOS dies with logarithmic active pixels were prepared in a commercial process, and photodetector dies with metal-semiconductor-metal devices were prepared in a custom process using hydrogenated amorphous silicon. The paper also describes a digital camera that was developed to test the prototype. In this camera, scenes captured by the image sensor are read using an FPGA board, and sent in real time to a PC over USB for data processing and display. Experimental results show that the VI-CMOS prototype has a higher dynamic range and a lower dark limit than conventional electronic image sensors.

Design and Fabrication of Vertically-Integrated CMOS Image Sensors

PubMed Central

Skorka, Orit; Joseph, Dileepan

2011-01-01

Technologies to fabricate integrated circuits (IC) with 3D structures are an emerging trend in IC design. They are based on vertical stacking of active components to form heterogeneous microsystems. Electronic image sensors will benefit from these technologies because they allow increased pixel-level data processing and device optimization. This paper covers general principles in the design of vertically-integrated (VI) CMOS image sensors that are fabricated by flip-chip bonding. These sensors are composed of a CMOS die and a photodetector die. As a specific example, the paper presents a VI-CMOS image sensor that was designed at the University of Alberta, and fabricated with the help of CMC Microsystems and Micralyne Inc. To realize prototypes, CMOS dies with logarithmic active pixels were prepared in a commercial process, and photodetector dies with metal-semiconductor-metal devices were prepared in a custom process using hydrogenated amorphous silicon. The paper also describes a digital camera that was developed to test the prototype. In this camera, scenes captured by the image sensor are read using an FPGA board, and sent in real time to a PC over USB for data processing and display. Experimental results show that the VI-CMOS prototype has a higher dynamic range and a lower dark limit than conventional electronic image sensors. PMID:22163860

Microfluidics for synthetic biology: from design to execution.

PubMed

Ferry, M S; Razinkov, I A; Hasty, J

2011-01-01

With the expanding interest in cellular responses to dynamic environments, microfluidic devices have become important experimental platforms for biological research. Microfluidic "microchemostat" devices enable precise environmental control while capturing high quality, single-cell gene expression data. For studies of population heterogeneity and gene expression noise, these abilities are crucial. Here, we describe the necessary steps for experimental microfluidics using devices created in our lab as examples. First, we discuss the rational design of microchemostats and the tools available to predict their performance. We carefully analyze the critical parts of an example device, focusing on the most important part of any microchemostat: the cell trap. Next, we present a method for generating on-chip dynamic environments using an integrated fluidic junction coupled to linear actuators. Our system relies on the simple modulation of hydrostatic pressure to alter the mixing ratio between two source reservoirs and we detail the software and hardware behind it. To expand the throughput of microchemostat experiments, we describe how to build larger, parallel versions of simpler devices. To analyze the large amounts of data, we discuss methods for automated cell tracking, focusing on the special problems presented by Saccharomyces cerevisiae cells. The manufacturing of microchemostats is described in complete detail: from the photolithographic processing of the wafer to the final bonding of the PDMS chip to glass coverslip. Finally, the procedures for conducting Escherichia coli and S. cerevisiae microchemostat experiments are addressed. Copyright © 2011 Elsevier Inc. All rights reserved.

Chipping whole trees for fuel chips: a production study

Treesearch

Dana Mitchell; Tom Gallagher

2007-01-01

A time and motion study was conducted to determine the productivity and cost of an in-woods chipping operation when processing whole mall-diameter trees for biomass. The study removed biomass from two overstocked stands and compared the cost of this treatment to existing alternatives. The treatment stands consisted of a 30-year-old longleaf pine stand and a 37-year-old...

Structured laser gain-medium by new bonding for power micro-laser

NASA Astrophysics Data System (ADS)

Kausas, Arvydas; Zheng, Lihe; Taira, Takunori

2017-02-01

In this work, we have compared the Q-switched performance of single rod crystal to a newly developed distributed face cooling structure. This structure was made by surface activated bonding technology and allowed to combine transparent heatsink to a gain crystal at room temperature. The Sapphire and Nd3+:YAG crystal plates were combined in this fashion to produce eight crystal chip which was further used to obtain Q-switch pulses with Cr4+:YAG crystal as saturable absorber. Energy of 9 mJ and pulse duration of 815 ps were achieved. Although the energy obtained with single rod system was 10 mJ, the degradation of the beam prevents such crystal to be used in further applications. This is the first demonstration of distributed face cooling system outperformed conventionally single rod system.

Analog signal processing for optical coherence imaging systems

NASA Astrophysics Data System (ADS)

Xu, Wei

Optical coherence tomography (OCT) and optical coherence microscopy (OCM) are non-invasive optical coherence imaging techniques, which enable micron-scale resolution, depth resolved imaging capability. Both OCT and OCM are based on Michelson interferometer theory. They are widely used in ophthalmology, gastroenterology and dermatology, because of their high resolution, safety and low cost. OCT creates cross sectional images whereas OCM obtains en face images. In this dissertation, the design and development of three increasingly complicated analog signal processing (ASP) solutions for optical coherence imaging are presented. The first ASP solution was implemented for a time domain OCT system with a Rapid Scanning Optical Delay line (RSOD)-based optical signal modulation and logarithmic amplifier (Log amp) based demodulation. This OCT system can acquire up to 1600 A-scans per second. The measured dynamic range is 106dB at 200A-scan per second. This OCT signal processing electronics includes an off-the-shelf filter box with a Log amp circuit implemented on a PCB board. The second ASP solution was developed for an OCM system with synchronized modulation and demodulation and compensation for interferometer phase drift. This OCM acquired micron-scale resolution, high dynamic range images at acquisition speeds up to 45,000 pixels/second. This OCM ASP solution is fully custom designed on a perforated circuit board. The third ASP solution was implemented on a single 2.2 mm x 2.2 mm complementary metal oxide semiconductor (CMOS) chip. This design is expandable to a multiple channel OCT system. A single on-chip CMOS photodetector and ASP channel was used for coherent demodulation in a time domain OCT system. Cross-sectional images were acquired with a dynamic range of 76dB (limited by photodetector responsivity). When incorporated with a bump-bonded InGaAs photodiode with higher responsivity, the expected dynamic range is close to 100dB.

LLNL Partners with IBM on Brain-Like Computing Chip

DOE Office of Scientific and Technical Information (OSTI.GOV)

Van Essen, Brian

Lawrence Livermore National Laboratory (LLNL) will receive a first-of-a-kind brain-inspired supercomputing platform for deep learning developed by IBM Research. Based on a breakthrough neurosynaptic computer chip called IBM TrueNorth, the scalable platform will process the equivalent of 16 million neurons and 4 billion synapses and consume the energy equivalent of a hearing aid battery – a mere 2.5 watts of power. The brain-like, neural network design of the IBM Neuromorphic System is able to infer complex cognitive tasks such as pattern recognition and integrated sensory processing far more efficiently than conventional chips.

LLNL Partners with IBM on Brain-Like Computing Chip

ScienceCinema

Van Essen, Brian

2018-06-25

Lawrence Livermore National Laboratory (LLNL) will receive a first-of-a-kind brain-inspired supercomputing platform for deep learning developed by IBM Research. Based on a breakthrough neurosynaptic computer chip called IBM TrueNorth, the scalable platform will process the equivalent of 16 million neurons and 4 billion synapses and consume the energy equivalent of a hearing aid battery – a mere 2.5 watts of power. The brain-like, neural network design of the IBM Neuromorphic System is able to infer complex cognitive tasks such as pattern recognition and integrated sensory processing far more efficiently than conventional chips.

Perspective: Fabrication of integrated organ-on-a-chip via bioprinting.

PubMed

Yang, Qingzhen; Lian, Qin; Xu, Feng

2017-05-01

Organ-on-a-chip has emerged as a powerful platform with widespread applications in biomedical engineering, such as pathology studies and drug screening. However, the fabrication of organ-on-a-chip is still a challenging task due to its complexity. For an integrated organ-on-a-chip, it may contain four key elements, i.e., a microfluidic chip, live cells/microtissues that are cultured in this chip, components for stimulus loading to mature the microtissues, and sensors for results readout. Recently, bioprinting has been used for fabricating organ-on-a-chip as it enables the printing of multiple materials, including biocompatible materials and even live cells in a programmable manner with a high spatial resolution. Besides, all four elements for organ-on-a-chip could be printed in a single continuous procedure on one printer; in other words, the fabrication process is assembly free. In this paper, we discuss the recent advances of organ-on-a-chip fabrication by bioprinting. Light is shed on the printing strategies, materials, and biocompatibility. In addition, some specific bioprinted organs-on-chips are analyzed in detail. Because the bioprinted organ-on-a-chip is still in its early stage, significant efforts are still needed. Thus, the challenges presented together with possible solutions and future trends are also discussed.

The nanoaquarium: A nanofluidic platform for in situ transmission electron microscopy in liquid media

NASA Astrophysics Data System (ADS)

Grogan, Joseph M.

There are many scientifically interesting and technologically relevant nanoscale phenomena that take place in liquid media. Examples include aggregation and assembly of nanoparticles; colloidal crystal formation; liquid phase growth of structures such as nanowires; electrochemical deposition and etching for fabrication processes and battery applications; interfacial phenomena; boiling and cavitation; and biological interactions. Understanding of these fields would benefit greatly from real-time, in situ transmission electron microscope (TEM) imaging with nanoscale resolution. Most liquids cannot be imaged by traditional TEM due to evaporation in the high vacuum environment and the requirement that samples be very thin. Liquid-cell in situ TEM has emerged as an exciting new experimental technique that hermetically seals a thin slice of liquid between two electron transparent membranes to enable TEM imaging of liquid-based processes. This work presents details of the fabrication of a custom-made liquid-cell in situ TEM device, dubbed the nanoaquarium. The nanoaquarium's highlights include an exceptionally thin sample cross section (10s to 100s of nm); wafer scale processing that enables high-yield mass production; robust hermetic sealing that provides leak-free operation without use of glue, epoxy, or any polymers; compatibility with lab-on-chip technology; and on-chip integrated electrodes for sensing and actuation. The fabrication process is described, with an emphasis on direct wafer bonding. Experimental results involving direct observation of colloid aggregation using an aqueous solution of gold nanoparticles are presented. Quantitative analysis of the growth process agrees with prior results and theory, indicating that the experimental technique does not radically alter the observed phenomenon. For the first time, in situ observations of nanoparticles at a contact line and in an evaporating thin film of liquid are reported, with applications for techniques such as dip-coating and drop-casting, commonly used for depositing nanoparticles on a surface via convective-capillary assembly. Theoretical analysis suggests that the observed particle motion and aggregation are caused by gradients in surface tension and disjoining pressure in the thin liquid film.