31 CFR 1021.311 - Filing obligations.

Code of Federal Regulations, 2011 CFR

2011-07-01

...) Transactions in currency involving cash in include, but are not limited to: (1) Purchases of chips, tokens, and..., but are not limited to: (1) Redemptions of chips, tokens, tickets, and other gaming instruments; (2...

Toxics Release Inventory Chemical Hazard Information Profiles (TRI-CHIP) Dataset

EPA Pesticide Factsheets

The Toxics Release Inventory (TRI) Chemical Hazard Information Profiles (TRI-CHIP) dataset contains hazard information about the chemicals reported in TRI. Users can use this XML-format dataset to create their own databases and hazard analyses of TRI chemicals. The hazard information is compiled from a series of authoritative sources including the Integrated Risk Information System (IRIS). The dataset is provided as a downloadable .zip file that when extracted provides XML files and schemas for the hazard information tables.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wickstrom, Gregory Lloyd; Gale, Jason Carl; Ma, Kwok Kee

The Sandia Secure Processor (SSP) is a new native Java processor that has been specifically designed for embedded applications. The SSP's design is a system composed of a core Java processor that directly executes Java bytecodes, on-chip intelligent IO modules, and a suite of software tools for simulation and compiling executable binary files. The SSP is unique in that it provides a way to control real-time IO modules for embedded applications. The system software for the SSP is a 'class loader' that takes Java .class files (created with your favorite Java compiler), links them together, and compiles a binary. Themore » complete SSP system provides very powerful functionality with very light hardware requirements with the potential to be used in a wide variety of small-system embedded applications. This paper gives a detail description of the Sandia Secure Processor and its unique features.« less

MineLoC: A Rapid Production of Lab-on-a-Chip Biosensors Using 3D Printer and the Sandbox Game, Minecraft.

PubMed

Kim, Kyukwang; Kim, Hyeongkeun; Kim, Seunggyu; Jeon, Jessie S

2018-06-10

Here, MineLoC is described as a pipeline developed to generate 3D printable models of master templates for Lab-on-a-Chip (LoC) by using a popular multi-player sandbox game “Minecraft”. The user can draw a simple diagram describing the channels and chambers of the Lab-on-a-Chip devices with pre-registered color codes which indicate the height of the generated structure. MineLoC converts the diagram into large chunks of blocks (equal sized cube units composing every object in the game) in the game world. The user and co-workers can simultaneously access the game and edit, modify, or review, which is a feature not generally supported by conventional design software. Once the review is complete, the resultant structure can be exported into a stereolithography (STL) file which can be used in additive manufacturing. Then, the Lab-on-a-Chip device can be fabricated by the standard protocol to produce a Lab-on-a-Chip. The simple polydimethylsiloxane (PDMS) device for the bacterial growth measurement used in the previous research was copied by the proposed method. The error calculation by a 3D model comparison showed an accuracy of 86%. It is anticipated that this work will facilitate more use of 3D printer-based Lab-on-a-Chip fabrication, which greatly lowers the entry barrier in the field of Lab-on-a-Chip research.

Lossless compression techniques for maskless lithography data

NASA Astrophysics Data System (ADS)

Dai, Vito; Zakhor, Avideh

2002-07-01

Future lithography systems must produce more dense chips with smaller feature sizes, while maintaining the throughput of one wafer per sixty seconds per layer achieved by today's optical lithography systems. To achieve this throughput with a direct-write maskless lithography system, using 25 nm pixels for 50 nm feature sizes, requires data rates of about 10 Tb/s. In a previous paper, we presented an architecture which achieves this data rate contingent on consistent 25 to 1 compression of lithography data, and on implementation of a decoder-writer chip with a real-time decompressor fabricated on the same chip as the massively parallel array of lithography writers. In this paper, we examine the compression efficiency of a spectrum of techniques suitable for lithography data, including two industry standards JBIG and JPEG-LS, a wavelet based technique SPIHT, general file compression techniques ZIP and BZIP2, our own 2D-LZ technique, and a simple list-of-rectangles representation RECT. Layouts rasterized both to black-and-white pixels, and to 32 level gray pixels are considered. Based on compression efficiency, JBIG, ZIP, 2D-LZ, and BZIP2 are found to be strong candidates for application to maskless lithography data, in many cases far exceeding the required compression ratio of 25. To demonstrate the feasibility of implementing the decoder-writer chip, we consider the design of a hardware decoder based on ZIP, the simplest of the four candidate techniques. The basic algorithm behind ZIP compression is Lempel-Ziv 1977 (LZ77), and the design parameters of LZ77 decompression are optimized to minimize circuit usage while maintaining compression efficiency.

Design of an Elliptic Curve Cryptography processor for RFID tag chips.

PubMed

Liu, Zilong; Liu, Dongsheng; Zou, Xuecheng; Lin, Hui; Cheng, Jian

2014-09-26

Radio Frequency Identification (RFID) is an important technique for wireless sensor networks and the Internet of Things. Recently, considerable research has been performed in the combination of public key cryptography and RFID. In this paper, an efficient architecture of Elliptic Curve Cryptography (ECC) Processor for RFID tag chip is presented. We adopt a new inversion algorithm which requires fewer registers to store variables than the traditional schemes. A new method for coordinate swapping is proposed, which can reduce the complexity of the controller and shorten the time of iterative calculation effectively. A modified circular shift register architecture is presented in this paper, which is an effective way to reduce the area of register files. Clock gating and asynchronous counter are exploited to reduce the power consumption. The simulation and synthesis results show that the time needed for one elliptic curve scalar point multiplication over GF(2163) is 176.7 K clock cycles and the gate area is 13.8 K with UMC 0.13 μm Complementary Metal Oxide Semiconductor (CMOS) technology. Moreover, the low power and low cost consumption make the Elliptic Curve Cryptography Processor (ECP) a prospective candidate for application in the RFID tag chip.

Design of an Elliptic Curve Cryptography Processor for RFID Tag Chips

PubMed Central

Liu, Zilong; Liu, Dongsheng; Zou, Xuecheng; Lin, Hui; Cheng, Jian

2014-01-01

Radio Frequency Identification (RFID) is an important technique for wireless sensor networks and the Internet of Things. Recently, considerable research has been performed in the combination of public key cryptography and RFID. In this paper, an efficient architecture of Elliptic Curve Cryptography (ECC) Processor for RFID tag chip is presented. We adopt a new inversion algorithm which requires fewer registers to store variables than the traditional schemes. A new method for coordinate swapping is proposed, which can reduce the complexity of the controller and shorten the time of iterative calculation effectively. A modified circular shift register architecture is presented in this paper, which is an effective way to reduce the area of register files. Clock gating and asynchronous counter are exploited to reduce the power consumption. The simulation and synthesis results show that the time needed for one elliptic curve scalar point multiplication over GF(2163) is 176.7 K clock cycles and the gate area is 13.8 K with UMC 0.13 μm Complementary Metal Oxide Semiconductor (CMOS) technology. Moreover, the low power and low cost consumption make the Elliptic Curve Cryptography Processor (ECP) a prospective candidate for application in the RFID tag chip. PMID:25264952

The storage system of PCM based on random access file system

NASA Astrophysics Data System (ADS)

Han, Wenbing; Chen, Xiaogang; Zhou, Mi; Li, Shunfen; Li, Gezi; Song, Zhitang

2016-10-01

Emerging memory technologies such as Phase change memory (PCM) tend to offer fast, random access to persistent storage with better scalability. It's a hot topic of academic and industrial research to establish PCM in storage hierarchy to narrow the performance gap. However, the existing file systems do not perform well with the emerging PCM storage, which access storage medium via a slow, block-based interface. In this paper, we propose a novel file system, RAFS, to bring about good performance of PCM, which is built in the embedded platform. We attach PCM chips to the memory bus and build RAFS on the physical address space. In the proposed file system, we simplify traditional system architecture to eliminate block-related operations and layers. Furthermore, we adopt memory mapping and bypassed page cache to reduce copy overhead between the process address space and storage device. XIP mechanisms are also supported in RAFS. To the best of our knowledge, we are among the first to implement file system on real PCM chips. We have analyzed and evaluated its performance with IOZONE benchmark tools. Our experimental results show that the RAFS on PCM outperforms Ext4fs on SDRAM with small record lengths. Based on DRAM, RAFS is significantly faster than Ext4fs by 18% to 250%.

VizieR Online Data Catalog: Equivalent widths and atomic data for GCs (Lamb+, 2015)

NASA Astrophysics Data System (ADS)

Lamb, M. P.; Venn, K. A.; Shetrone, M. D.; Sakari, C. M.; Pritzl, B. J.

2017-11-01

Optical spectra were gathered with the High Resolution Spectrograph (HRS; Tull 1998, Proc. SPIE, 3355, 387) on the HET. The HRS was configured at resolution R=30000 with 2x2 pixel binning using the 2 arcsec fibre. The HRS splits the incoming beam on to two CCD chips, from which the spectral regions 6000-7000 Å (red chip) and 4800-5900 Å (blue chip) were extracted for this work. Two standard stars were also observed, RGB stars with previously published spectral analyses in each of the GCs M3 and M13. (2 data files).

Experimental Investigations on the Surface-Driven Capillary Flow of Aqueous Microparticle Suspensions in the Microfluidic Laboratory-On Systems

NASA Astrophysics Data System (ADS)

Mukhopadhyay, Subhadeep

In this work, total 1592 individual leakage-free polymethylmethacrylate (PMMA) microfluidic devices as laboratory-on-a-chip systems are fabricated by maskless lithography, hot embossing lithography, and direct bonding technique. Total 1094 individual Audio Video Interleave Files as experimental outputs related to the surface-driven capillary flow have been recorded and analyzed. The influence of effective viscosity, effect of surface wettability, effect of channel aspect ratio, and effect of centrifugal force on the surface-driven microfluidic flow of aqueous microparticle suspensions have been successfully and individually investigated in these laboratory-on-a-chip systems. Also, 5 micron polystyrene particles have been separated from the aqueous microparticle suspensions in the microfluidic lab-on-a-chip systems of modified design with 98% separation efficiency, and 10 micron polystyrene particles have been separated with 100% separation efficiency. About the novelty of this work, the experimental investigations have been performed on the surface-driven microfluidic flow of aqueous microparticle suspensions with the investigations on the separation time in particle-size based separation mechanism to control these suspensions in the microfluidic lab-on-a-chip systems. This research work contains a total of 10,112 individual experimental outputs obtained using total 30 individual instruments by author’s own hands-on completely during more than three years continuously. Author has performed the experimental investigations on both the fluid statics and fluid dynamics to develop an automated fluid machine.

An isolated SNM model for high-stability multi-port register file in 65 nm CMOS

NASA Astrophysics Data System (ADS)

Zhang, Yuejun; Wang, Pengjun; Li, Gang

2017-09-01

In modern microprocessors, the multi-port register file is one of the key modules which provides fast and multiple data access for instructions. As the number of access ports in register files increases, stability becomes a key issue due to the voltage fluctuation on bit lines. We propose to apply an isolated inverter to address the voltage fluctuation. To assess the register stability, we derive a closed-form expression of static noise margin (SNM) for our register file. The proposed SNM model can be used as a guideline to predict the impact of several register parameters on the stability and optimize register file designs. To validate the proposed SNM model, we fabricated a test chip of two-write-four-read (2W4R) 1024 bits register file in a TSMC 65 nm low-power CMOS technology. The experimental result shows that the stability of our register file cells with an isolated inverter improve the conventional cells by approximately 2.4 times. Also, the supply voltage causes a fluctuation of SNM of about 65%, while temperature and transistor mismatch cause a fluctuation of SNM of about 20%. Project supported by the National Natural Science Foundation of China (Nos, 61404076, 61474068), the Zhejiang Provincial Natural Science Foundation of China (No. LQ14F040001), the S&T Plan of Zhejiang Provincial Science and Technology Department (No. 2015C31010), the China Spark Program (No. 2015GA701053), the Ningbo Natural Science Foundation (Nos. 2014A610148, 2015A610107), and the K. C. Wong Magna Fund in Ningbo University, China.

Genome-wide Target Enrichment-aided Chip Design: a 66 K SNP Chip for Cashmere Goat.

PubMed

Qiao, Xian; Su, Rui; Wang, Yang; Wang, Ruijun; Yang, Ting; Li, Xiaokai; Chen, Wei; He, Shiyang; Jiang, Yu; Xu, Qiwu; Wan, Wenting; Zhang, Yaolei; Zhang, Wenguang; Chen, Jiang; Liu, Bin; Liu, Xin; Fan, Yixing; Chen, Duoyuan; Jiang, Huaizhi; Fang, Dongming; Liu, Zhihong; Wang, Xiaowen; Zhang, Yanjun; Mao, Danqing; Wang, Zhiying; Di, Ran; Zhao, Qianjun; Zhong, Tao; Yang, Huanming; Wang, Jian; Wang, Wen; Dong, Yang; Chen, Xiaoli; Xu, Xun; Li, Jinquan

2017-08-17

Compared with the commercially available single nucleotide polymorphism (SNP) chip based on the Bead Chip technology, the solution hybrid selection (SHS)-based target enrichment SNP chip is not only design-flexible, but also cost-effective for genotype sequencing. In this study, we propose to design an animal SNP chip using the SHS-based target enrichment strategy for the first time. As an update to the international collaboration on goat research, a 66 K SNP chip for cashmere goat was created from the whole-genome sequencing data of 73 individuals. Verification of this 66 K SNP chip with the whole-genome sequencing data of 436 cashmere goats showed that the SNP call rates was between 95.3% and 99.8%. The average sequencing depth for target SNPs were 40X. The capture regions were shown to be 200 bp that flank target SNPs. This chip was further tested in a genome-wide association analysis of cashmere fineness (fiber diameter). Several top hit loci were found marginally associated with signaling pathways involved in hair growth. These results demonstrate that the 66 K SNP chip is a useful tool in the genomic analyses of cashmere goats. The successful chip design shows that the SHS-based target enrichment strategy could be applied to SNP chip design in other species.

Design and characterization of a 52K SNP chip for goats.

PubMed

Tosser-Klopp, Gwenola; Bardou, Philippe; Bouchez, Olivier; Cabau, Cédric; Crooijmans, Richard; Dong, Yang; Donnadieu-Tonon, Cécile; Eggen, André; Heuven, Henri C M; Jamli, Saadiah; Jiken, Abdullah Johari; Klopp, Christophe; Lawley, Cynthia T; McEwan, John; Martin, Patrice; Moreno, Carole R; Mulsant, Philippe; Nabihoudine, Ibouniyamine; Pailhoux, Eric; Palhière, Isabelle; Rupp, Rachel; Sarry, Julien; Sayre, Brian L; Tircazes, Aurélie; Jun Wang; Wang, Wen; Zhang, Wenguang

2014-01-01

The success of Genome Wide Association Studies in the discovery of sequence variation linked to complex traits in humans has increased interest in high throughput SNP genotyping assays in livestock species. Primary goals are QTL detection and genomic selection. The purpose here was design of a 50-60,000 SNP chip for goats. The success of a moderate density SNP assay depends on reliable bioinformatic SNP detection procedures, the technological success rate of the SNP design, even spacing of SNPs on the genome and selection of Minor Allele Frequencies (MAF) suitable to use in diverse breeds. Through the federation of three SNP discovery projects consolidated as the International Goat Genome Consortium, we have identified approximately twelve million high quality SNP variants in the goat genome stored in a database together with their biological and technical characteristics. These SNPs were identified within and between six breeds (meat, milk and mixed): Alpine, Boer, Creole, Katjang, Saanen and Savanna, comprising a total of 97 animals. Whole genome and Reduced Representation Library sequences were aligned on >10 kb scaffolds of the de novo goat genome assembly. The 60,000 selected SNPs, evenly spaced on the goat genome, were submitted for oligo manufacturing (Illumina, Inc) and published in dbSNP along with flanking sequences and map position on goat assemblies (i.e. scaffolds and pseudo-chromosomes), sheep genome V2 and cattle UMD3.1 assembly. Ten breeds were then used to validate the SNP content and 52,295 loci could be successfully genotyped and used to generate a final cluster file. The combined strategy of using mainly whole genome Next Generation Sequencing and mapping on a contig genome assembly, complemented with Illumina design tools proved to be efficient in producing this GoatSNP50 chip. Advances in use of molecular markers are expected to accelerate goat genomic studies in coming years.

Design and Characterization of a 52K SNP Chip for Goats

PubMed Central

Tosser-Klopp, Gwenola; Bardou, Philippe; Bouchez, Olivier; Cabau, Cédric; Crooijmans, Richard; Dong, Yang; Donnadieu-Tonon, Cécile; Eggen, André; Heuven, Henri C. M.; Jamli, Saadiah; Jiken, Abdullah Johari; Klopp, Christophe; Lawley, Cynthia T.; McEwan, John; Martin, Patrice; Moreno, Carole R.; Mulsant, Philippe; Nabihoudine, Ibouniyamine; Pailhoux, Eric; Palhière, Isabelle; Rupp, Rachel; Sarry, Julien; Sayre, Brian L.; Tircazes, Aurélie; Jun Wang; Wang, Wen; Zhang, Wenguang

2014-01-01

The success of Genome Wide Association Studies in the discovery of sequence variation linked to complex traits in humans has increased interest in high throughput SNP genotyping assays in livestock species. Primary goals are QTL detection and genomic selection. The purpose here was design of a 50–60,000 SNP chip for goats. The success of a moderate density SNP assay depends on reliable bioinformatic SNP detection procedures, the technological success rate of the SNP design, even spacing of SNPs on the genome and selection of Minor Allele Frequencies (MAF) suitable to use in diverse breeds. Through the federation of three SNP discovery projects consolidated as the International Goat Genome Consortium, we have identified approximately twelve million high quality SNP variants in the goat genome stored in a database together with their biological and technical characteristics. These SNPs were identified within and between six breeds (meat, milk and mixed): Alpine, Boer, Creole, Katjang, Saanen and Savanna, comprising a total of 97 animals. Whole genome and Reduced Representation Library sequences were aligned on >10 kb scaffolds of the de novo goat genome assembly. The 60,000 selected SNPs, evenly spaced on the goat genome, were submitted for oligo manufacturing (Illumina, Inc) and published in dbSNP along with flanking sequences and map position on goat assemblies (i.e. scaffolds and pseudo-chromosomes), sheep genome V2 and cattle UMD3.1 assembly. Ten breeds were then used to validate the SNP content and 52,295 loci could be successfully genotyped and used to generate a final cluster file. The combined strategy of using mainly whole genome Next Generation Sequencing and mapping on a contig genome assembly, complemented with Illumina design tools proved to be efficient in producing this GoatSNP50 chip. Advances in use of molecular markers are expected to accelerate goat genomic studies in coming years. PMID:24465974

Sorting cells by their density

PubMed Central

Norouzi, Nazila; Bhakta, Heran C.

2017-01-01

Sorting cells by their type is an important capability in biological research and medical diagnostics. However, most cell sorting techniques rely on labels or tags, which may have limited availability and specificity. Sorting different cell types by their different physical properties is an attractive alternative to labels because all cells intrinsically have these physical properties. But some physical properties, like cell size, vary significantly from cell to cell within a cell type; this makes it difficult to identify and sort cells based on their sizes alone. In this work we continuously sort different cells types by their density, a physical property with much lower cell-to-cell variation within a cell type (and therefore greater potential to discriminate different cell types) than other physical properties. We accomplish this using a 3D-printed microfluidic chip containing a horizontal flowing micron-scale density gradient. As cells flow through the chip, Earth’s gravity makes each cell move vertically to the point where the cell’s density matches the surrounding fluid’s density. When the horizontal channel then splits, cells with different densities are routed to different outlets. As a proof of concept, we use our density sorter chip to sort polymer microbeads by their material (polyethylene and polystyrene) and blood cells by their type (white blood cells and red blood cells). The chip enriches the fraction of white blood cells in a blood sample from 0.1% (in whole blood) to nearly 98% (in the output of the chip), a 1000x enrichment. Any researcher with access to a 3D printer can easily replicate our density sorter chip and use it in their own research using the design files provided as online Supporting Information. Additionally, researchers can simulate the performance of a density sorter chip in their own applications using the Python-based simulation software that accompanies this work. The simplicity, resolution, and throughput of this technique make it suitable for isolating even rare cell types in complex biological samples, in a wide variety of different research and clinical applications. PMID:28723908

VLSI design of a single chip reed-solomon encoder

DOE Office of Scientific and Technical Information (OSTI.GOV)

Truong, T.K.; Deutsch, L.J.; Reed, I.S.

A design for a single chip implementation of a Reed-Solomon encoder is presented. The architecture that leads to this single VLSI chip design makes use of a bit serial finite field multiplication algorithm.

Femtosecond laser fabrication of fiber based optofluidic platform for flow cytometry applications

NASA Astrophysics Data System (ADS)

Serhatlioglu, Murat; Elbuken, Caglar; Ortac, Bulend; Solmaz, Mehmet E.

2017-02-01

Miniaturized optofluidic platforms play an important role in bio-analysis, detection and diagnostic applications. The advantages of such miniaturized devices are extremely low sample requirement, low cost development and rapid analysis capabilities. Fused silica is advantageous for optofluidic systems due to properties such as being chemically inert, mechanically stable, and optically transparent to a wide spectrum of light. As a three dimensional manufacturing method, femtosecond laser scanning followed by chemical etching shows great potential to fabricate glass based optofluidic chips. In this study, we demonstrate fabrication of all-fiber based, optofluidic flow cytometer in fused silica glass by femtosecond laser machining. 3D particle focusing was achieved through a straightforward planar chip design with two separately fabricated fused silica glass slides thermally bonded together. Bioparticles in a fluid stream encounter with optical interrogation region specifically designed to allocate 405nm single mode fiber laser source and two multi-mode collection fibers for forward scattering (FSC) and side scattering (SSC) signals detection. Detected signal data collected with oscilloscope and post processed with MATLAB script file. We were able to count number of events over 4000events/sec, and achieve size distribution for 5.95μm monodisperse polystyrene beads using FSC and SSC signals. Our platform shows promise for optical and fluidic miniaturization of flow cytometry systems.

[Design and arrangement of the CHIP (CHinese In Prato) study].

PubMed

Modesti, Pietro Amedeo; Han, Yang; Jing, Yang; Xiaoling, Wang; Mengyue, Zhang; Zihua, Yang; Jia, Guo; Perruolo, Eleonora; Bini, Lara; Camera, Maira; Biggeri, Annibale; Rapi, Stefano; Hongsheng, Chen; Li, Zhang; Zengli, Wang; Jianbin, Hu; Xiaoyue, Zhao; Zhao, Dong

2014-01-01

Following the rapid economic development, China is experiencing a progressive increase in the incidence of cardiovascular (CV) events and in the prevalence of CV risk factors. According to recent estimations, the prevalence of diabetes sharply increased from 1% in 1980 to 11% in 2013. Migration from China to Europe is now mainly concentrated in Countries of the Southern Europe, e.g., Italy and Spain. The largest Chinese community living in Italy is now settled in Prato, being also one of the largest Chinese community in Europe. Local authorities estimate a number of Chinese citizens living in Prato of over 40,000 individuals, including illegal immigrants. The availability of reliable data on the health needs of Chinese population is thus a recognised priority for the local health system. The creation of a participatory research where Chinese population directly participates in the formation of a group of citizens involved in designing and conducting the survey allows to overcome difficulties due to the lack of official demographic files. Secondly, and most important, this approach makes it possible to effectively pass a prevention message to an elusive population. The purpose of the CHIP (CHinese In Prato) survey is to investigate the prevalence of diabetes and cardiovascular risk factors among Chinese immigrants. Recruitment procedure was started on 8th July 2014.

Design and qualification of the SEU/TD Radiation Monitor chip

NASA Technical Reports Server (NTRS)

Buehler, Martin G.; Blaes, Brent R.; Soli, George A.; Zamani, Nasser; Hicks, Kenneth A.

1992-01-01

This report describes the design, fabrication, and testing of the Single-Event Upset/Total Dose (SEU/TD) Radiation Monitor chip. The Radiation Monitor is scheduled to fly on the Mid-Course Space Experiment Satellite (MSX). The Radiation Monitor chip consists of a custom-designed 4-bit SRAM for heavy ion detection and three MOSFET's for monitoring total dose. In addition the Radiation Monitor chip was tested along with three diagnostic chips: the processor monitor and the reliability and fault chips. These chips revealed the quality of the CMOS fabrication process. The SEU/TD Radiation Monitor chip had an initial functional yield of 94.6 percent. Forty-three (43) SEU SRAM's and 14 Total Dose MOSFET's passed the hermeticity and final electrical tests and were delivered to LL.

78 FR 53159 - Certain Semiconductor Chips With Dram Circuitry, and Modules and Products Containing Same: Notice...

Federal Register 2010, 2011, 2012, 2013, 2014

2013-08-28

... instituted this investigation on December 21, 2011, based on a complaint filed by Elpida Memory, Inc., of Tokyo, Japan, and Elpida Memory (USA) Inc. of Sunnyvale, California (collectively, ``Elpida''). 76 FR...

The VLSI design of a single chip Reed-Solomon encoder

NASA Technical Reports Server (NTRS)

Truong, T. K.; Deutsch, L. J.; Reed, I. S.

1982-01-01

A design for a single chip implementation of a Reed-Solomon encoder is presented. The architecture that leads to this single VLSI chip design makes use of a bit serial finite field multiplication algorithm.

CMOS-array design-automation techniques

NASA Technical Reports Server (NTRS)

Feller, A.; Lombardt, T.

1979-01-01

Thirty four page report discusses design of 4,096-bit complementary metal oxide semiconductor (CMOS) read-only memory (ROM). CMOSROM is either mask or laser programable. Report is divided into six sections; section one describes background of ROM chips; section two presents design goals for chip; section three discusses chip implementation and chip statistics; conclusions and recommendations are given in sections four thru six.

Computer-Aided Design and Fabrication of Wire-Wrap (Trademark) Type Circuit Boards: A New Symbolism and Its Implementation (Conception et Fabrication Automatisees de Circuits par Cablage Enroule: un Nouveau Symbolisme et son Application),

DTIC Science & Technology

1982-02-01

facilitant la transition entre les plans d’ing~nierie 6lectronique et la matrice pertinente d’interconnexions requise pour le montage par c~blage enroul6 Wire...Wrap. Le d~veloppement de prototypes 6lectroniques s’est vu consid6rablement acc6l6r6 par la preparation plus rapide des donn~es d’interconnexions...directory, all located in *APL files (Sect. 7.0). A matrix called BANQUE is also formed by the program L to regroup those chip descriptions of the main

77 FR 33240 - Certain Semiconductor Chips With DRAM Circuitry, and Modules and Products Containing Same...

Federal Register 2010, 2011, 2012, 2013, 2014

2012-06-05

... viewed on the Commission's electronic docket (EDIS) at http://edis.usitc.gov . Hearing-impaired persons... December 21, 2011, based on a complaint filed by Elpida Memory, Inc. of Tokyo, Japan and Elpida Memory (USA...

A Novel Analog Integrated Circuit Design Course Covering Design, Layout, and Resulting Chip Measurement

ERIC Educational Resources Information Center

Lin, Wei-Liang; Cheng, Wang-Chuan; Wu, Chen-Hao; Wu, Hai-Ming; Wu, Chang-Yu; Ho, Kuan-Hsuan; Chan, Chueh-An

2010-01-01

This work describes a novel, first-year graduate-level analog integrated circuit (IC) design course. The course teaches students analog circuit design; an external manufacturer then produces their designs in three different silicon chips. The students, working in pairs, then test these chips to verify their success. All work is completed within…

A 1-channel 3-band wide dynamic range compression chip for vibration transducer of implantable hearing aids.

PubMed

Kim, Dongwook; Seong, Kiwoong; Kim, Myoungnam; Cho, Jinho; Lee, Jyunghyun

2014-01-01

In this paper, a digital audio processing chip which uses a wide dynamic range compression (WDRC) algorithm is designed and implemented for implantable hearing aids system. The designed chip operates at a single voltage of 3.3V and drives a 16 bit parallel input and output at 32 kHz sample. The designed chip has 1-channel 3-band WDRC composed of a FIR filter bank, a level detector, and a compression part. To verify the performance of the designed chip, we measured the frequency separations of bands and compression gain control to reflect the hearing threshold level.

76 FR 72214 - Certain Semiconductor Chips with DRAM Circuitry, and Modules and Products Containing Same Receipt...

Federal Register 2010, 2011, 2012, 2013, 2014

2011-11-22

...://edis.usitc.gov . Hearing-impaired persons are advised that information on this matter can be obtained... Commission has received a complaint filed on behalf of Elpida Memory, Inc. and Elpida Memory (USA) Inc. on...

Best Practices and Joint Calling of the HumanExome BeadChip: The CHARGE Consortium

PubMed Central

Grove, Megan L.; Yu, Bing; Cochran, Barbara J.; Haritunians, Talin; Bis, Joshua C.; Taylor, Kent D.; Hansen, Mark; Borecki, Ingrid B.; Cupples, L. Adrienne; Fornage, Myriam; Gudnason, Vilmundur; Harris, Tamara B.; Kathiresan, Sekar; Kraaij, Robert; Launer, Lenore J.; Levy, Daniel; Liu, Yongmei; Mosley, Thomas; Peloso, Gina M.; Psaty, Bruce M.; Rich, Stephen S.; Rivadeneira, Fernando; Siscovick, David S.; Smith, Albert V.; Uitterlinden, Andre; van Duijn, Cornelia M.; Wilson, James G.; O’Donnell, Christopher J.; Rotter, Jerome I.; Boerwinkle, Eric

2013-01-01

Genotyping arrays are a cost effective approach when typing previously-identified genetic polymorphisms in large numbers of samples. One limitation of genotyping arrays with rare variants (e.g., minor allele frequency [MAF] <0.01) is the difficulty that automated clustering algorithms have to accurately detect and assign genotype calls. Combining intensity data from large numbers of samples may increase the ability to accurately call the genotypes of rare variants. Approximately 62,000 ethnically diverse samples from eleven Cohorts for Heart and Aging Research in Genomic Epidemiology (CHARGE) Consortium cohorts were genotyped with the Illumina HumanExome BeadChip across seven genotyping centers. The raw data files for the samples were assembled into a single project for joint calling. To assess the quality of the joint calling, concordance of genotypes in a subset of individuals having both exome chip and exome sequence data was analyzed. After exclusion of low performing SNPs on the exome chip and non-overlap of SNPs derived from sequence data, genotypes of 185,119 variants (11,356 were monomorphic) were compared in 530 individuals that had whole exome sequence data. A total of 98,113,070 pairs of genotypes were tested and 99.77% were concordant, 0.14% had missing data, and 0.09% were discordant. We report that joint calling allows the ability to accurately genotype rare variation using array technology when large sample sizes are available and best practices are followed. The cluster file from this experiment is available at www.chargeconsortium.com/main/exomechip. PMID:23874508

The role of simulation in the design of a neural network chip

NASA Technical Reports Server (NTRS)

Desai, Utpal; Roppel, Thaddeus A.; Padgett, Mary L.

1993-01-01

An iterative, simulation-based design procedure for a neural network chip is introduced. For this design procedure, the goal is to produce a chip layout for a neural network in which the weights are determined by transistor gate width-to-length ratios. In a given iteration, the current layout is simulated using the circuit simulator SPICE, and layout adjustments are made based on conventional gradient-decent methods. After the iteration converges, the chip is fabricated. Monte Carlo analysis is used to predict the effect of statistical fabrication process variations on the overall performance of the neural network chip.

Framework for reanalysis of publicly available Affymetrix® GeneChip® data sets based on functional regions of interest.

PubMed

Saka, Ernur; Harrison, Benjamin J; West, Kirk; Petruska, Jeffrey C; Rouchka, Eric C

2017-12-06

Since the introduction of microarrays in 1995, researchers world-wide have used both commercial and custom-designed microarrays for understanding differential expression of transcribed genes. Public databases such as ArrayExpress and the Gene Expression Omnibus (GEO) have made millions of samples readily available. One main drawback to microarray data analysis involves the selection of probes to represent a specific transcript of interest, particularly in light of the fact that transcript-specific knowledge (notably alternative splicing) is dynamic in nature. We therefore developed a framework for reannotating and reassigning probe groups for Affymetrix® GeneChip® technology based on functional regions of interest. This framework addresses three issues of Affymetrix® GeneChip® data analyses: removing nonspecific probes, updating probe target mapping based on the latest genome knowledge and grouping probes into gene, transcript and region-based (UTR, individual exon, CDS) probe sets. Updated gene and transcript probe sets provide more specific analysis results based on current genomic and transcriptomic knowledge. The framework selects unique probes, aligns them to gene annotations and generates a custom Chip Description File (CDF). The analysis reveals only 87% of the Affymetrix® GeneChip® HG-U133 Plus 2 probes uniquely align to the current hg38 human assembly without mismatches. We also tested new mappings on the publicly available data series using rat and human data from GSE48611 and GSE72551 obtained from GEO, and illustrate that functional grouping allows for the subtle detection of regions of interest likely to have phenotypical consequences. Through reanalysis of the publicly available data series GSE48611 and GSE72551, we profiled the contribution of UTR and CDS regions to the gene expression levels globally. The comparison between region and gene based results indicated that the detected expressed genes by gene-based and region-based CDFs show high consistency and regions based results allows us to detection of changes in transcript formation.

Embeddable Reconfigurable Neuroprocessors

NASA Technical Reports Server (NTRS)

Daud, Taher; Duong, Tuan; Langenbacher, Harry; Tran, Mua; Thakoor, Anil

1993-01-01

Reconfigurable and cascadable building block neural network chips, fabricated using analog VLSI design tools, are interfaced to a PC. The building block chip designs, the cascadability and the hardware-in-the-loop supervised learning aspects of these chips are described.

Microfluidics on liquid handling stations (μF-on-LHS): an industry compatible chip interface between microfluidics and automated liquid handling stations.

PubMed

Waldbaur, Ansgar; Kittelmann, Jörg; Radtke, Carsten P; Hubbuch, Jürgen; Rapp, Bastian E

2013-06-21

We describe a generic microfluidic interface design that allows the connection of microfluidic chips to established industrial liquid handling stations (LHS). A molding tool has been designed that allows fabrication of low-cost disposable polydimethylsiloxane (PDMS) chips with interfaces that provide convenient and reversible connection of the microfluidic chip to industrial LHS. The concept allows complete freedom of design for the microfluidic chip itself. In this setup all peripheral fluidic components (such as valves and pumps) usually required for microfluidic experiments are provided by the LHS. Experiments (including readout) can be carried out fully automated using the hardware and software provided by LHS manufacturer. Our approach uses a chip interface that is compatible with widely used and industrially established LHS which is a significant advancement towards near-industrial experimental design in microfluidics and will greatly facilitate the acceptance and translation of microfluidics technology in industry.

iTAR: a web server for identifying target genes of transcription factors using ChIP-seq or ChIP-chip data.

PubMed

Yang, Chia-Chun; Andrews, Erik H; Chen, Min-Hsuan; Wang, Wan-Yu; Chen, Jeremy J W; Gerstein, Mark; Liu, Chun-Chi; Cheng, Chao

2016-08-12

Chromatin immunoprecipitation followed by massively parallel DNA sequencing (ChIP-seq) or microarray hybridization (ChIP-chip) has been widely used to determine the genomic occupation of transcription factors (TFs). We have previously developed a probabilistic method, called TIP (Target Identification from Profiles), to identify TF target genes using ChIP-seq/ChIP-chip data. To achieve high specificity, TIP applies a conservative method to estimate significance of target genes, with the trade-off being a relatively low sensitivity of target gene identification compared to other methods. Additionally, TIP's output does not render binding-peak locations or intensity, information highly useful for visualization and general experimental biological use, while the variability of ChIP-seq/ChIP-chip file formats has made input into TIP more difficult than desired. To improve upon these facets, here we present are fined TIP with key extensions. First, it implements a Gaussian mixture model for p-value estimation, increasing target gene identification sensitivity and more accurately capturing the shape of TF binding profile distributions. Second, it enables the incorporation of TF binding-peak data by identifying their locations in significant target gene promoter regions and quantifies their strengths. Finally, for full ease of implementation we have incorporated it into a web server ( http://syslab3.nchu.edu.tw/iTAR/ ) that enables flexibility of input file format, can be used across multiple species and genome assembly versions, and is freely available for public use. The web server additionally performs GO enrichment analysis for the identified target genes to reveal the potential function of the corresponding TF. The iTAR web server provides a user-friendly interface and supports target gene identification in seven species, ranging from yeast to human. To facilitate investigating the quality of ChIP-seq/ChIP-chip data, the web server generates the chart of the characteristic binding profiles and the density plot of normalized regulatory scores. The iTAR web server is a useful tool in identifying TF target genes from ChIP-seq/ChIP-chip data and discovering biological insights.

[A research on real-time ventricular QRS classification methods for single-chip-microcomputers].

PubMed

Peng, L; Yang, Z; Li, L; Chen, H; Chen, E; Lin, J

1997-05-01

Ventricular QRS classification is key technique of ventricular arrhythmias detection in single-chip-microcomputer based dynamic electrocardiogram real-time analyser. This paper adopts morphological feature vector including QRS amplitude, interval information to reveal QRS morphology. After studying the distribution of QRS morphology feature vector of MIT/BIH DB ventricular arrhythmia files, we use morphological feature vector cluster to classify multi-morphology QRS. Based on the method, morphological feature parameters changing method which is suitable to catch occasional ventricular arrhythmias is presented. Clinical experiments verify missed ventricular arrhythmia is less than 1% by this method.

[Design and Implementation of a Novel Networked Sleep Monitoring System].

PubMed

Tian, Yu; Yan, Zhuangzhi; Tao, Jia'an

2015-03-01

To meet the need of cost-effective multi-biosignal monitoring devices nowadays, we designed a system based on super low power MCU. It can collect, record and transfer several signals including ECG, Oxygen saturation, thoracic and abdominal wall expansion, oronasal airflow signal. The data files can be stored on a flash chip and transferred to a computer by a USB module. In addition, the sensing data can be sent wirelessly in real time. Considering that long term work of wireless module consumes much energy, we present a low-power optimization method based on delay constraint. Lower energy consumption comes at the cost of little delay. Experimental results show that it can effectively decrease the energy consumption without changing wireless module and transfer protocol. Besides, our system is powered by two dry batteries and can work at least 8 hours throughout a whole night.

A 1-1/2-level on-chip-decoding bubble memory chip design

NASA Technical Reports Server (NTRS)

Chen, T. T.

1975-01-01

Design includes multi-channel replicator which can reduce chip-writing requirement, selective annihilating switch which can effectively annihilate bubbles with minimum delay, and modified transfer switch which can be used as selective steering-type decoder.

A single VLSI chip for computing syndromes in the (225, 223) Reed-Solomon decoder

NASA Technical Reports Server (NTRS)

Hsu, I. S.; Truong, T. K.; Shao, H. M.; Deutsch, L. J.

1986-01-01

A description of a single VLSI chip for computing syndromes in the (255, 223) Reed-Solomon decoder is presented. The architecture that leads to this single VLSI chip design makes use of the dual basis multiplication algorithm. The same architecture can be applied to design VLSI chips to compute various kinds of number theoretic transforms.

Advanced Initiation Systems Manufacturing Level 2 Milestone Completion Summary

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chow, R; Schmidt, M

2009-10-01

Milestone Description - Advanced Initiation Systems Detonator Design and Prototype. Milestone Grading Criteria - Design new generation chip slapper detonator and manufacture a prototype using advanced manufacturing processes, such as all-dry chip metallization and solvent-less flyer coatings. The advanced processes have been developed for manufacturing detonators with high material compatibility and reliability to support future LEPs, e.g. the B61, and new weapons systems. Perform velocimetry measurements to determine slapper velocity as a function of flight distance. A prototype detonator assembly and stripline was designed for low-energy chip slappers. Pictures of the prototype detonator and stripline are shown. All-dry manufacturing processesmore » were used to address compatibility issues. KCP metallized the chips in a physical vapor deposition system through precision-aligned shadow masks. LLNL deposited a solvent-less polyimide flyer with a processes called SLIP, which stands for solvent-less vapor deposition followed by in-situ polymerization. LANL manufactured the high-surface-area (HSA) high explosive (HE) pellets. Test fires of two chip slapper designs, radius and bowtie, were performed at LLNL in the High Explosives Application Facility (HEAF). Test fires with HE were conducted to establish the threshold firing voltages. pictures of the chip slappers before and after test fires are shown. Velocimetry tests were then performed to obtain slapper velocities at or above the threshold firing voltages. Figure 5 shows the slapper velocity as a function of distance and time at the threshold voltage, for both radius and bowtie bridge designs. Both designs were successful at initiating the HE at low energy levels. Summary of Accomplishments are: (1) All-dry process for chip manufacture developed; (2) Solventless process for slapper materials developed; (3) High-surface area explosive pellets developed; (4) High performance chip slappers developed; (5) Low-energy chip slapper detonator designs; and (6) Low-voltage threshold chip slapper detonator demonstrated.« less

Property-driven functional verification technique for high-speed vision system-on-chip processor

NASA Astrophysics Data System (ADS)

Nshunguyimfura, Victor; Yang, Jie; Liu, Liyuan; Wu, Nanjian

2017-04-01

The implementation of functional verification in a fast, reliable, and effective manner is a challenging task in a vision chip verification process. The main reason for this challenge is the stepwise nature of existing functional verification techniques. This vision chip verification complexity is also related to the fact that in most vision chip design cycles, extensive efforts are focused on how to optimize chip metrics such as performance, power, and area. Design functional verification is not explicitly considered at an earlier stage at which the most sound decisions are made. In this paper, we propose a semi-automatic property-driven verification technique. The implementation of all verification components is based on design properties. We introduce a low-dimension property space between the specification space and the implementation space. The aim of this technique is to speed up the verification process for high-performance parallel processing vision chips. Our experimentation results show that the proposed technique can effectively improve the verification effort up to 20% for the complex vision chip design while reducing the simulation and debugging overheads.

On testing VLSI chips for the big Viterbi decoder

NASA Technical Reports Server (NTRS)

Hsu, I. S.

1989-01-01

A general technique that can be used in testing very large scale integrated (VLSI) chips for the Big Viterbi Decoder (BVD) system is described. The test technique is divided into functional testing and fault-coverage testing. The purpose of functional testing is to verify that the design works functionally. Functional test vectors are converted from outputs of software simulations which simulate the BVD functionally. Fault-coverage testing is used to detect and, in some cases, to locate faulty components caused by bad fabrication. This type of testing is useful in screening out bad chips. Finally, design for testability, which is included in the BVD VLSI chip design, is described in considerable detail. Both the observability and controllability of a VLSI chip are greatly enhanced by including the design for the testability feature.

Electronic p-Chip-Based System for Identification of Glass Slides and Tissue Cassettes in Histopathology Laboratories.

PubMed

Mandecki, Wlodek; Qian, Jay; Gedzberg, Katie; Gruda, Maryanne; Rodriguez, Efrain Frank; Nesbitt, Leslie; Riben, Michael

2018-01-01

The tagging system is based on a small, electronic, wireless, laser-light-activated microtransponder named "p-Chip." The p-Chip is a silicon integrated circuit, the size of which is 600 μm × 600 μm × 100 μm. Each p-Chip contains a unique identification code stored within its electronic memory that can be retrieved with a custom reader. These features allow the p-Chip to be used as an unobtrusive and scarcely noticeable ID tag on glass slides and tissue cassettes. The system is comprised of p-Chip-tagged sample carriers, a dedicated benchtop p-Chip ID reader that can accommodate both objects, and an additional reader (the Wand), with an adapter for reading IDs of glass slides stored vertically in drawers. On slides, p-Chips are attached with adhesive to the center of the short edge, and on cassettes - embedded directly into the plastic. ID readout is performed by bringing the reader to the proximity of the chip. Standard histopathology laboratory protocols were used for testing. Very good ID reading efficiency was observed for both glass slides and cassettes. When processed slides are stored in vertical filing drawers, p-Chips remain readable without the need to remove them from the storage location, thereby improving the speed of searches in collections. On the cassettes, the ID continues to be readable through a thin layer of paraffin. Both slides and tissue cassettes can be read with the same reader, reducing the need for redundant equipment. The p-Chip is stable to all chemical challenges commonly used in the histopathology laboratory, tolerates temperature extremes, and remains durable in long-term storage. The technology is compatible with laboratory information management systems software systems. The p-Chip system is very well suited for identification of glass slides and cassettes in the histopathology laboratory.

Electronic p-Chip-Based System for Identification of Glass Slides and Tissue Cassettes in Histopathology Laboratories

PubMed Central

Mandecki, Wlodek; Qian, Jay; Gedzberg, Katie; Gruda, Maryanne; Rodriguez, Efrain “Frank”; Nesbitt, Leslie; Riben, Michael

2018-01-01

Background: The tagging system is based on a small, electronic, wireless, laser-light-activated microtransponder named “p-Chip.” The p-Chip is a silicon integrated circuit, the size of which is 600 μm × 600 μm × 100 μm. Each p-Chip contains a unique identification code stored within its electronic memory that can be retrieved with a custom reader. These features allow the p-Chip to be used as an unobtrusive and scarcely noticeable ID tag on glass slides and tissue cassettes. Methods: The system is comprised of p-Chip-tagged sample carriers, a dedicated benchtop p-Chip ID reader that can accommodate both objects, and an additional reader (the Wand), with an adapter for reading IDs of glass slides stored vertically in drawers. On slides, p-Chips are attached with adhesive to the center of the short edge, and on cassettes – embedded directly into the plastic. ID readout is performed by bringing the reader to the proximity of the chip. Standard histopathology laboratory protocols were used for testing. Results: Very good ID reading efficiency was observed for both glass slides and cassettes. When processed slides are stored in vertical filing drawers, p-Chips remain readable without the need to remove them from the storage location, thereby improving the speed of searches in collections. On the cassettes, the ID continues to be readable through a thin layer of paraffin. Both slides and tissue cassettes can be read with the same reader, reducing the need for redundant equipment. Conclusions: The p-Chip is stable to all chemical challenges commonly used in the histopathology laboratory, tolerates temperature extremes, and remains durable in long-term storage. The technology is compatible with laboratory information management systems software systems. The p-Chip system is very well suited for identification of glass slides and cassettes in the histopathology laboratory. PMID:29692946

75 FR 5790 - Notice of Receipt of Several Pesticide Petitions Filed for Residues of Pesticide Chemicals in or...

Federal Register 2010, 2011, 2012, 2013, 2014

2010-02-04

... on banana at 0.05 parts per million (ppm). An adequate, validated method (GRM006.01B) is available... insecticide fluazifop-p-butyl, in or on potato, tuber at 1.1 ppm; potato, peel (wet) at 1.1 ppm; potato, chips...

Real-time PCR machine system modeling and a systematic approach for the robust design of a real-time PCR-on-a-chip system.

PubMed

Lee, Da-Sheng

2010-01-01

Chip-based DNA quantification systems are widespread, and used in many point-of-care applications. However, instruments for such applications may not be maintained or calibrated regularly. Since machine reliability is a key issue for normal operation, this study presents a system model of the real-time Polymerase Chain Reaction (PCR) machine to analyze the instrument design through numerical experiments. Based on model analysis, a systematic approach was developed to lower the variation of DNA quantification and achieve a robust design for a real-time PCR-on-a-chip system. Accelerated lift testing was adopted to evaluate the reliability of the chip prototype. According to the life test plan, this proposed real-time PCR-on-a-chip system was simulated to work continuously for over three years with similar reproducibility in DNA quantification. This not only shows the robustness of the lab-on-a-chip system, but also verifies the effectiveness of our systematic method for achieving a robust design.

Architectures for Cognitive Systems

DTIC Science & Technology

2010-02-01

highly modular many- node chip was designed which addressed power efficiency to the maximum extent possible. Each node contains an Asynchronous Field...optimization to perform complex cognitive computing operations. This project focused on the design of the core and integration across a four node chip . A...follow on project will focus on creating a 3 dimensional stack of chips that is enabled by the low power usage. The chip incorporates structures to

Chip design for thin-film deep ultraviolet LEDs fabricated by laser lift-off of the sapphire substrate

NASA Astrophysics Data System (ADS)

Cho, H. K.; Krüger, O.; Külberg, A.; Rass, J.; Zeimer, U.; Kolbe, T.; Knauer, A.; Einfeldt, S.; Weyers, M.; Kneissl, M.

2017-12-01

We report on a chip design which allows the laser lift-off (LLO) of the sapphire substrate sustaining the epitaxial film of flip-chip mounted deep ultraviolet light emitting diodes. A nanosecond pulsed excimer laser with a wavelength of 248 nm was used for the LLO. A mechanically stable chip design was found to be the key to prevent crack formation in the epitaxial layers and material chipping during the LLO process. Stabilization was achieved by introducing a Ti/Au leveling layer that mechanically supports the fragile epitaxial film. The electrical and optical characterization of devices before and after the LLO process shows that the device performance did not degrade by the LLO.

Towards an Analogue Neuromorphic VLSI Instrument for the Sensing of Complex Odours

NASA Astrophysics Data System (ADS)

Ab Aziz, Muhammad Fazli; Harun, Fauzan Khairi Che; Covington, James A.; Gardner, Julian W.

2011-09-01

Almost all electronic nose instruments reported today employ pattern recognition algorithms written in software and run on digital processors, e.g. micro-processors, microcontrollers or FPGAs. Conversely, in this paper we describe the analogue VLSI implementation of an electronic nose through the design of a neuromorphic olfactory chip. The modelling, design and fabrication of the chip have already been reported. Here a smart interface has been designed and characterised for thisneuromorphic chip. Thus we can demonstrate the functionality of the a VLSI neuromorphic chip, producing differing principal neuron firing patterns to real sensor response data. Further work is directed towards integrating 9 separate neuromorphic chips to create a large neuronal network to solve more complex olfactory problems.

A Close Loop Low-Power and High Speed 130 nm CMOS Sample and Hold Circuit Based on Switched Capacitor for ADC Module

NASA Astrophysics Data System (ADS)

Nasir, Z.; Ruslan, S. H.

2017-08-01

A sample and hold (S/H) block is typically used as an analogue to digital interface in the analogue to digital converter (ADC) system. Since ADC is widely used in processing signals, the power consumption of the ADC must be lowered to conserve energy. Therefore the S/H circuit must be of a low powered too. Sampling phase and hold phase are the two phases of the operation cycle of the S/H circuit. Switched capacitor (SC) techniques have been developed in order to allow the integration on a single silicon chip of both digital and analogue functions. By controlling switches around the SC, the SC circuit works by passing charge into and out of a capacitor. SC circuits are suitable for on chip implementations because they replace a resistor with switches and capacitors. In this research, a closed-loop sample and hold circuit based on SC is designed and simulated with Cadence EDA tools. The schematic, layout, and simulation of the circuit is done using generic Silterra 130 nm technology file. All the analysis is done using Virtuoso Analog Design Environment. Layout and schematic are drawn using Virtuoso Schematic Editor and Virtuoso Layout Editor, Calibre is used for post layout simulation. The closed loop S/H circuit based on SC is successfully designed and able to sample and hold the analogue input waveform. The power consumption of the circuit is 0.919 mW and the propagation delay is 64.96 ps.

Numerical investigation of thermal performance of a water-cooled mini-channel heat sink for different chip arrangement

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tikadar, Amitav, E-mail: amitav453@gmail.com; Hossain, Md. Mahamudul; Morshed, A. K. M. M.

Heat transfer from electronic chip is always challenging and very crucial for electronic industry. Electronic chips are assembled in various manners according to the design conditions and limitationsand thus the influence of chip assembly on the overall thermal performance needs to be understand for the efficient design of electronic cooling system. Due to shrinkage of the dimension of channel and continuous increment of thermal load, conventional heat extraction techniques sometimes become inadequate. Due to high surface area to volume ratio, mini-channel have the natural advantage to enhance convective heat transfer and thus to play a vital role in the advancedmore » heat transfer devices with limited surface area and high heat flux. In this paper, a water cooled mini-channel heat sink was considered for electronic chip cooling and five different chip arrangements were designed and studied, namely: the diagonal arrangement, parallel arrangement, stacked arrangement, longitudinal arrangement and sandwiched arrangement. Temperature distribution on the chip surfaces was presented and the thermal performance of the heat sink in terms of overall thermal resistance was also compared. It is found that the sandwiched arrangement of chip provides better thermal performance compared to conventional in line chip arrangement.« less

Physical-level synthesis for digital lab-on-a-chip considering variation, contamination, and defect.

PubMed

Liao, Chen; Hu, Shiyan

2014-03-01

Microfluidic lab-on-a-chips have been widely utilized in biochemical analysis and human health studies due to high detection accuracy, high timing efficiency, and low cost. The increasing design complexity of lab-on-a-chips necessitates the computer-aided design (CAD) methodology in contrast to the classical manual design methodology. A key part in lab-on-a-chip CAD is physical-level synthesis. It includes the lab-on-a-chip placement and routing, where placement is to determine the physical location and the starting time of each operation and routing is to transport each droplet from the source to the destination. In the lab-on-a-chip design, variation, contamination, and defect need to be considered. This work designs a physical-level synthesis flow which simultaneously considers variation, contamination, and defect of the lab-on-a-chip design. It proposes a maze routing based, variation, contamination, and defect aware droplet routing technique, which is seamlessly integrated into an existing placement technique. The proposed technique improves the placement solution for routing and achieves the placement and routing co-optimization to handle variation, contamination, and defect. The simulation results demonstrate that our technique does not use any defective/contaminated grids, while the technique without considering contamination and defect uses 17.0% of the defective/contaminated grids on average. In addition, our routing variation aware technique significantly improves the average routing yield by 51.2% with only 3.5% increase in completion time compared to a routing variation unaware technique.

Real-time PCR Machine System Modeling and a Systematic Approach for the Robust Design of a Real-time PCR-on-a-Chip System

PubMed Central

Lee, Da-Sheng

2010-01-01

Chip-based DNA quantification systems are widespread, and used in many point-of-care applications. However, instruments for such applications may not be maintained or calibrated regularly. Since machine reliability is a key issue for normal operation, this study presents a system model of the real-time Polymerase Chain Reaction (PCR) machine to analyze the instrument design through numerical experiments. Based on model analysis, a systematic approach was developed to lower the variation of DNA quantification and achieve a robust design for a real-time PCR-on-a-chip system. Accelerated lift testing was adopted to evaluate the reliability of the chip prototype. According to the life test plan, this proposed real-time PCR-on-a-chip system was simulated to work continuously for over three years with similar reproducibility in DNA quantification. This not only shows the robustness of the lab-on-a-chip system, but also verifies the effectiveness of our systematic method for achieving a robust design. PMID:22315563

Design and prototyping of a chip-based multi-micro-organoid culture system for substance testing, predictive to human (substance) exposure.

PubMed

Sonntag, Frank; Schilling, Niels; Mader, Katja; Gruchow, Mathias; Klotzbach, Udo; Lindner, Gerd; Horland, Reyk; Wagner, Ilka; Lauster, Roland; Howitz, Steffen; Hoffmann, Silke; Marx, Uwe

2010-07-01

Dynamic miniaturized human multi-micro-organ bioreactor systems are envisaged as a possible solution for the embarrassing gap of predictive substance testing prior to human exposure. A rational approach was applied to simulate and design dynamic long-term cultures of the smallest possible functional human organ units, human "micro-organoids", on a chip the shape of a microscope slide. Each chip contains six identical dynamic micro-bioreactors with three different micro-organoid culture segments each, a feed supply and waste reservoirs. A liver, a brain cortex and a bone marrow micro-organoid segment were designed into each bioreactor. This design was translated into a multi-layer chip prototype and a routine manufacturing procedure was established. The first series of microscopable, chemically resistant and sterilizable chip prototypes was tested for matrix compatibility and primary cell culture suitability. Sterility and long-term human cell survival could be shown. Optimizing the applied design approach and prototyping tools resulted in a time period of only 3 months for a single design and prototyping cycle. This rapid prototyping scheme now allows for fast adjustment or redesign of inaccurate architectures. The designed chip platform is thus ready to be evaluated for the establishment and maintenance of the human liver, brain cortex and bone marrow micro-organoids in a systemic microenvironment. Copyright (c) 2010 Elsevier B.V. All rights reserved.

Fundamental Problems of Hybrid CMOS/Nanodevice Circuits

DTIC Science & Technology

2010-12-14

Development of an area-distributed CMOS/nanodevice interface We have carried out the first design of CMOS chips for the CMOS/nanodevice integration, and...got them fabricated in IBM’ 180-nm 7RF process (via MOSIS, Inc. silicon foundry). Each 44 mm2 chip assembly of the design consists of 4 component... chips , merged together for processing convenience. Each 22 mm2 component chip features two interface arrays, with 1010 vias each, with chip’s MOSFETs

On-chip temperature-based digital signal processing for customized wireless microcontroller

NASA Astrophysics Data System (ADS)

Farhah Razanah Faezal, Siti; Isa, Mohd Nazrin Md; Harun, Azizi; Nizam Mohyar, Shaiful; Bahari Jambek, Asral

2017-11-01

Increases in die size and power density inside system-on-chip (SoC) design have brought thermal issue inside the system. Uneven heat-up and increasing in temperature offset on-chip has become a major factor that can limits the system performance. This paper presents the design and simulation of a temperature-based digital signal processing for modern system-on-chip design using the Verilog HDL. This design yields continuous monitoring of temperature and reacts to specified conditions. The simulation of the system has been done on Altera Quartus Software v. 14. With system above, microcontroller can achieve nominal power dissipation and operation is within the temperature range due to the incorporate of an interrupt-based system.

Controlled and tunable polymer particles' production using a single microfluidic device

NASA Astrophysics Data System (ADS)

Amoyav, Benzion; Benny, Ofra

2018-04-01

Microfluidics technology offers a new platform to control liquids under flow in small volumes. The advantage of using small-scale reactions for droplet generation along with the capacity to control the preparation parameters, making microfluidic chips an attractive technology for optimizing encapsulation formulations. However, one of the drawback in this methodology is the ability to obtain a wide range of droplet sizes, from sub-micron to microns using a single chip design. In fact, typically, droplet chips are used for micron-dimension particles, while nanoparticles' synthesis requires complex chips design (i.e., microreactors and staggered herringbone micromixer). Here, we introduce the development of a highly tunable and controlled encapsulation technique, using two polymer compositions, for generating particles ranging from microns to nano-size using the same simple single microfluidic chip design. Poly(lactic-co-glycolic acid) (PLGA 50:50) or PLGA/polyethylene glycol polymeric particles were prepared with focused-flow chip, yielding monodisperse particle batches. We show that by varying flow rate, solvent, surfactant and polymer composition, we were able to optimize particles' size and decrease polydispersity index, using simple chip designs with no further related adjustments or costs. Utilizing this platform, which offers tight tuning of particle properties, could offer an important tool for formulation development and can potentially pave the way towards a better precision nanomedicine.

Microarray Я US: a user-friendly graphical interface to Bioconductor tools that enables accurate microarray data analysis and expedites comprehensive functional analysis of microarray results.

PubMed

Dai, Yilin; Guo, Ling; Li, Meng; Chen, Yi-Bu

2012-06-08

Microarray data analysis presents a significant challenge to researchers who are unable to use the powerful Bioconductor and its numerous tools due to their lack of knowledge of R language. Among the few existing software programs that offer a graphic user interface to Bioconductor packages, none have implemented a comprehensive strategy to address the accuracy and reliability issue of microarray data analysis due to the well known probe design problems associated with many widely used microarray chips. There is also a lack of tools that would expedite the functional analysis of microarray results. We present Microarray Я US, an R-based graphical user interface that implements over a dozen popular Bioconductor packages to offer researchers a streamlined workflow for routine differential microarray expression data analysis without the need to learn R language. In order to enable a more accurate analysis and interpretation of microarray data, we incorporated the latest custom probe re-definition and re-annotation for Affymetrix and Illumina chips. A versatile microarray results output utility tool was also implemented for easy and fast generation of input files for over 20 of the most widely used functional analysis software programs. Coupled with a well-designed user interface, Microarray Я US leverages cutting edge Bioconductor packages for researchers with no knowledge in R language. It also enables a more reliable and accurate microarray data analysis and expedites downstream functional analysis of microarray results.

Science Issues Associated with the Use of a Microfluidic Chip Designed Specifically for Protein Crystallization

NASA Technical Reports Server (NTRS)

Holmes, Anna M.; Monaco, Lisa; Barnes, Cindy; Spearing, Scott; Jenkins, Andy; Johnson, Todd; Mayer, Derek; Cole, Helen

2003-01-01

The Iterative Biological Crystallization team in partnership with Caliper Technologies has produced a prototype microfluidic chip for batch crystallization that has been designed and tested. The chip is designed for the mixing and dispensing of up to five solutions with possible variation of the recipe being delivered to two growth wells. Developments that have led to the successful on-chip crystallization of a few model proteins have required investigative insight into many different areas, including fluid mixing dynamics, surface treatments, quantification and fidelity of reagent delivery. This presentation will encompass the ongoing studies and data accumulated toward these efforts.

Ultra-dense magnetoresistive mass memory

NASA Technical Reports Server (NTRS)

Daughton, J. M.; Sinclair, R.; Dupuis, T.; Brown, J.

1992-01-01

This report details the progress and accomplishments of Nonvolatile Electronics (NVE), Inc., on the design of the wafer scale MRAM mass memory system during the fifth quarter of the project. NVE has made significant progress this quarter on the one megabit design in several different areas. A test chip, which will verify a working GMR bit with the dimensions required by the 1 Meg chip, has been designed, laid out, and is currently being processed in the NVE labs. This test chip will allow electrical specifications, tolerances, and processing issues to be finalized before construction of the actual chip, thus providing a greater assurance of success of the final 1 Meg design. A model has been developed to accurately simulate the parasitic effects of unselected sense lines. This model gives NVE the ability to perform accurate simulations of the array electronic and test different design concepts. Much of the circuit design for the 1 Meg chip has been completed and simulated and these designs are included. Progress has been made in the wafer scale design area to verify the reliable operation of the 16 K macrocell. This is currently being accomplished with the design and construction of two stand alone test systems which will perform life tests and gather data on reliabiliy and wearout mechanisms for analysis.

Hybridization of Environmental Microbial Community Nucleic Acids by GeoChip.

PubMed

Van Nostrand, Joy D; Yin, Huaqin; Wu, Liyou; Yuan, Tong; Zhou, Jizhong

2016-01-01

Functional gene arrays, like the GeoChip, allow for the study of tens of thousands of genes in a single assay. The GeoChip array (5.0) contains probes for genes involved in geochemical cycling (N, C, S, and P), metal homeostasis, stress response, organic contaminant degradation, antibiotic resistance, secondary metabolism, and virulence factors as well as genes specific for fungi, protists, and viruses. Here, we briefly describe GeoChip design strategies (gene selection and probe design) and discuss minimum quantity and quality requirements for nucleic acids. We then provide detailed protocols for amplification, labeling, and hybridization of samples to the GeoChip.

UW VLSI chip tester

NASA Astrophysics Data System (ADS)

McKenzie, Neil

1989-12-01

We present a design for a low-cost, functional VLSI chip tester. It is based on the Apple MacIntosh II personal computer. It tests chips that have up to 128 pins. All pin drivers of the tester are bidirectional; each pin is programmed independently as an input or an output. The tester can test both static and dynamic chips. Rudimentary speed testing is provided. Chips are tested by executing C programs written by the user. A software library is provided for program development. Tests run under both the Mac Operating System and A/UX. The design is implemented using Xilinx Logic Cell Arrays. Price/performance tradeoffs are discussed.

Addressing On-Chip Power Converstion and Dissipation Issues in Many-Core System-on-a-Chip Based on Conventional Silicon and Emerging Nanotechnologies

NASA Astrophysics Data System (ADS)

Ashenafi, Emeshaw

Integrated circuits (ICs) are moving towards system-on-a-chip (SOC) designs. SOC allows various small and large electronic systems to be implemented in a single chip. This approach enables the miniaturization of design blocks that leads to high density transistor integration, faster response time, and lower fabrication costs. To reap the benefits of SOC and uphold the miniaturization of transistors, innovative power delivery and power dissipation management schemes are paramount. This dissertation focuses on on-chip integration of power delivery systems and managing power dissipation to increase the lifetime of energy storage elements. We explore this problem from two different angels: On-chip voltage regulators and power gating techniques. On-chip voltage regulators reduce parasitic effects, and allow faster and efficient power delivery for microprocessors. Power gating techniques, on the other hand, reduce the power loss incurred by circuit blocks during standby mode. Power dissipation (Ptotal = Pstatic and Pdynamic) in a complementary metal-oxide semiconductor (CMOS) circuit comes from two sources: static and dynamic. A quadratic dependency on the dynamic switching power and a more than linear dependency on static power as a form of gate leakage (subthreshold current) exist. To reduce dynamic power loss, the supply power should be reduced. A significant reduction in power dissipation occurs when portions of a microprocessor operate at a lower voltage level. This reduction in supply voltage is achieved via voltage regulators or converters. Voltage regulators are used to provide a stable power supply to the microprocessor. The conventional off-chip switching voltage regulator contains a passive floating inductor, which is difficult to be implemented inside the chip due to excessive power dissipation and parasitic effects. Additionally, the inductor takes a very large chip area while hampering the scaling process. These limitations make passive inductor based on-chip regulator design very unattractive for SOC integration and multi-/many-core environments. To circumvent the challenges, three alternative techniques based on active circuit elements to replace the passive LC filter of the buck convertor are developed. The first inductorless on-chip switching voltage regulator architecture is based on a cascaded 2nd order multiple feedback (MFB) low-pass filter (LPF). This design has the ability to modulate to multiple voltage settings via pulse-with modulation (PWM). The second approach is a supplementary design utilizing a hybrid low drop-out scheme to lower the output ripple of the switching regulator over a wider frequency range. The third design approach allows the integration of an entire power management system within a single chipset by combining a highly efficient switching regulator with an intermittently efficient linear regulator (area efficient), for robust and highly efficient on-chip regulation. The static power (Pstatic) or subthreshold leakage power (Pleak) increases with technology scaling. To mitigate static power dissipation, power gating techniques are implemented. Power gating is one of the popular methods to manage leakage power during standby periods in low-power high-speed IC design. It works by using transistor based switches to shut down part of the circuit block and put them in the idle mode. The efficiency of a power gating scheme involves minimum Ioff and high Ion for the sleep transistor. A conventional sleep transistor circuit design requires an additional header, footer, or both switches to turn off the logic block. This additional transistor causes signal delay and increases the chip area. We propose two innovative designs for next generation sleep transistor designs. For an above threshold operation, we present a sleep transistor design based on fully depleted silicon-on-insulator (FDSOI) device. For a subthreshold circuit operation, we implement a sleep transistor utilizing the newly developed silicon-on-ferroelectric-insulator field effect transistor (SOFFET). In both of the designs, the ability to control the threshold voltage via bias voltage at the back gate makes both devices more flexible for sleep transistors design than a bulk MOSFET. The proposed approaches simplify the design complexity, reduce the chip area, eliminate the voltage drop by sleep transistor, and improve power dissipation. In addition, the design provides a dynamically controlled Vt for times when the circuit needs to be in a sleep or switching mode.

Assessing the Power of Exome Chips.

PubMed

Page, Christian Magnus; Baranzini, Sergio E; Mevik, Bjørn-Helge; Bos, Steffan Daniel; Harbo, Hanne F; Andreassen, Bettina Kulle

2015-01-01

Genotyping chips for rare and low-frequent variants have recently gained popularity with the introduction of exome chips, but the utility of these chips remains unclear. These chips were designed using exome sequencing data from mainly American-European individuals, enriched for a narrow set of common diseases. In addition, it is well-known that the statistical power of detecting associations with rare and low-frequent variants is much lower compared to studies exclusively involving common variants. We developed a simulation program adaptable to any exome chip design to empirically evaluate the power of the exome chips. We implemented the main properties of the Illumina HumanExome BeadChip array. The simulated data sets were used to assess the power of exome chip based studies for varying effect sizes and causal variant scenarios. We applied two widely-used statistical approaches for rare and low-frequency variants, which collapse the variants into genetic regions or genes. Under optimal conditions, we found that a sample size between 20,000 to 30,000 individuals were needed in order to detect modest effect sizes (0.5% < PAR > 1%) with 80% power. For small effect sizes (PAR <0.5%), 60,000-100,000 individuals were needed in the presence of non-causal variants. In conclusion, we found that at least tens of thousands of individuals are necessary to detect modest effects under optimal conditions. In addition, when using rare variant chips on cohorts or diseases they were not originally designed for, the identification of associated variants or genes will be even more challenging.

Design and fabrication of metal briquette machine for shop floor

NASA Astrophysics Data System (ADS)

Pramod, R.; Kumar, G. B. Veeresh; Prashanth B., N.

2017-07-01

Efforts have to be taken to ensure efficient waste management system in shop floors, with minimum utilization of space and energy when it comes to disposing metal chips formed during machining processes. The salvaging of junk metallic chips and the us e of scrap are important for the economic production of a steelworks. For this purpose, we have fabricated a metal chip compaction machine, which can compact the metal chips into small briquettes. The project started with the survey of chips formed in shop floors and the practices involved in waste management. Study was done on the requirements for a better compaction. The heating chamber was designed taking into consideration the temperature required for an easy compaction of the metal chips. The power source for compaction and the pneumatic design for mechanism was done following the appropriate calculations regarding the air pressure provided and thrust required. The processes were tested under different conditions and found effective. The fabrication of the machine has been explained in detail and the results have been discussed.

Conceptual design of a 10 to the 8th power bit magnetic bubble domain mass storage unit and fabrication, test and delivery of a feasibility model

NASA Technical Reports Server (NTRS)

1972-01-01

The conceptual design of a highly reliable 10 to the 8th power-bit bubble domain memory for the space program is described. The memory has random access to blocks of closed-loop shift registers, and utilizes self-contained bubble domain chips with on-chip decoding. Trade-off studies show that the highest reliability and lowest power dissipation is obtained when the memory is organized on a bit-per-chip basis. The final design has 800 bits/register, 128 registers/chip, 16 chips/plane, and 112 planes, of which only seven are activated at a time. A word has 64 data bits +32 checkbits, used in a 16-adjacent code to provide correction of any combination of errors in one plane. 100 KHz maximum rotational frequency keeps power low (equal to or less than, 25 watts) and also allows asynchronous operation. Data rate is 6.4 megabits/sec, access time is 200 msec to an 800-word block and an additional 4 msec (average) to a word. The fabrication and operation are also described for a 64-bit bubble domain memory chip designed to test the concept of on-chip magnetic decoding. Access to one of the chip's four shift registers for the read, write, and clear functions is by means of bubble domain decoders utilizing the interaction between a conductor line and a bubble.

Methods for Trustworthy Design of On-Chip Bus Interconnect for General-Purpose Processors

DTIC Science & Technology

2012-03-01

Technology Andrew Huang, was able to test the security properties of HyperTransport bus protocol on an Xbox [20]. In his research, he was able to...TRUSTWORTHY DESIGN OF ON -CHIP BUS INTERCONNECT FOR GENERAL-PURPOSE PROCESSORS by Jay F. Elson March 2012 Thesis Advisor: Ted Huffmire Second...AND DATES COVERED Master’s Thesis 4. TITLE AND SUBTITLE Methods for Trustworthy Design of On -Chip Bus Interconnect for General-Purpose Processors 5

Determining the Terminal Velocity of Wood and Bark Chips

Treesearch

John A. Sturos

1972-01-01

Designing an efficient air flotation segregator to segregate bark chips from wood chips requires that the terminal velocities be determined for various pulpwood species. The technique described here uses forced air in a vertical wind tunnel with the chip initially at rest on a stationary screen; when the terminal air velocity in reached, the chip begins to float. A...

Architecture for VLSI design of Reed-Solomon encoders

NASA Technical Reports Server (NTRS)

Liu, K. Y.

1981-01-01

The logic structure of a universal VLSI chip called the symbol-slice Reed-Solomon (RS) encoder chip is discussed. An RS encoder can be constructed by cascading and properly interconnecting a group of such VLSI chips. As a design example, it is shown that a (255,223) RD encoder requiring around 40 discrete CMOS ICs may be replaced by an RS encoder consisting of four identical interconnected VLSI RS encoder chips. Besides the size advantage, the VLSI RS encoder also has the potential advantages of requiring less power and having a higher reliability.

Improved On-Chip Measurement of Delay in an FPGA or ASIC

NASA Technical Reports Server (NTRS)

Chen, Yuan; Burke, Gary; Sheldon, Douglas

2007-01-01

An improved design has been devised for on-chip-circuitry for measuring the delay through a chain of combinational logic elements in a field-programmable gate array (FPGA) or application-specific integrated circuit (ASIC). In the improved design, the delay chain does not include input and output buffers and is not configured as an oscillator. Instead, the delay chain is made part of the signal chain of an on-chip pulse generator. The duration of the pulse is measured on-chip and taken to equal the delay.

Integrated potentiometric detector for use in chip-based flow cells

PubMed

Tantra; Manz

2000-07-01

A new kind of potentiometric chip sensor for ion-selective electrodes (ISE) based on a solvent polymeric membrane is described. The chip sensor is designed to trap the organic cocktail inside the chip and to permit sample solution to flow past the membrane. The design allows the sensor to overcome technical problems of ruggedness and would therefore be ideal for industrial processes. The sensor performance for a Ba2+-ISE membrane based on a Vogtle ionophore showed electrochemical behavior similar to that observed in conventional electrodes and microelectrode arrangements.

Evolvable Smartphone-Based Platforms for Point-of-Care In-Vitro Diagnostics Applications.

PubMed

Patou, François; AlZahra'a Alatraktchi, Fatima; Kjægaard, Claus; Dimaki, Maria; Madsen, Jan; Svendsen, Winnie E

2016-09-03

The association of smart mobile devices and lab-on-chip technologies offers unprecedented opportunities for the emergence of direct-to-consumer in vitro medical diagnostics applications. Despite their clear transformative potential, obstacles remain to the large-scale disruption and long-lasting success of these systems in the consumer market. For instance, the increasing level of complexity of instrumented lab-on-chip devices, coupled to the sporadic nature of point-of-care testing, threatens the viability of a business model mainly relying on disposable/consumable lab-on-chips. We argued recently that system evolvability, defined as the design characteristic that facilitates more manageable transitions between system generations via the modification of an inherited design, can help remedy these limitations. In this paper, we discuss how platform-based design can constitute a formal entry point to the design and implementation of evolvable smart device/lab-on-chip systems. We present both a hardware/software design framework and the implementation details of a platform prototype enabling at this stage the interfacing of several lab-on-chip variants relying on current- or impedance-based biosensors. Our findings suggest that several change-enabling mechanisms implemented in the higher abstraction software layers of the system can promote evolvability, together with the design of change-absorbing hardware/software interfaces. Our platform architecture is based on a mobile software application programming interface coupled to a modular hardware accessory. It allows the specification of lab-on-chip operation and post-analytic functions at the mobile software layer. We demonstrate its potential by operating a simple lab-on-chip to carry out the detection of dopamine using various electroanalytical methods.

Evolvable Smartphone-Based Platforms for Point-of-Care In-Vitro Diagnostics Applications

PubMed Central

Patou, François; AlZahra’a Alatraktchi, Fatima; Kjægaard, Claus; Dimaki, Maria; Madsen, Jan; Svendsen, Winnie E.

2016-01-01

The association of smart mobile devices and lab-on-chip technologies offers unprecedented opportunities for the emergence of direct-to-consumer in vitro medical diagnostics applications. Despite their clear transformative potential, obstacles remain to the large-scale disruption and long-lasting success of these systems in the consumer market. For instance, the increasing level of complexity of instrumented lab-on-chip devices, coupled to the sporadic nature of point-of-care testing, threatens the viability of a business model mainly relying on disposable/consumable lab-on-chips. We argued recently that system evolvability, defined as the design characteristic that facilitates more manageable transitions between system generations via the modification of an inherited design, can help remedy these limitations. In this paper, we discuss how platform-based design can constitute a formal entry point to the design and implementation of evolvable smart device/lab-on-chip systems. We present both a hardware/software design framework and the implementation details of a platform prototype enabling at this stage the interfacing of several lab-on-chip variants relying on current- or impedance-based biosensors. Our findings suggest that several change-enabling mechanisms implemented in the higher abstraction software layers of the system can promote evolvability, together with the design of change-absorbing hardware/software interfaces. Our platform architecture is based on a mobile software application programming interface coupled to a modular hardware accessory. It allows the specification of lab-on-chip operation and post-analytic functions at the mobile software layer. We demonstrate its potential by operating a simple lab-on-chip to carry out the detection of dopamine using various electroanalytical methods. PMID:27598208

Design and implementation of a modulator-based free-space optical backplane for multiprocessor applications.

PubMed

Kirk, Andrew G; Plant, David V; Szymanski, Ted H; Vranesic, Zvonko G; Tooley, Frank A P; Rolston, David R; Ayliffe, Michael H; Lacroix, Frederic K; Robertson, Brian; Bernier, Eric; Brosseau, Daniel F

2003-05-10

Design and implementation of a free-space optical backplane for multiprocessor applications is presented. The system is designed to interconnect four multiprocessor nodes that communicate by using multiplexed 32-bit packets. Each multiprocessor node is electrically connected to an optoelectronic VLSI chip which implements the hyperplane interconnection architecture. The chips each contain 256 optical transmitters (implemented as dual-rail multiple quantum-well modulators) and 256 optical receivers. A rigid free-space microoptical interconnection system that interconnects the transceiver chips in a 512-channel unidirectional ring is implemented. Full design, implementation, and operational details are provided.

Design and implementation of a modulator-based free-space optical backplane for multiprocessor applications

NASA Astrophysics Data System (ADS)

Kirk, Andrew G.; Plant, David V.; Szymanski, Ted H.; Vranesic, Zvonko G.; Tooley, Frank A. P.; Rolston, David R.; Ayliffe, Michael H.; Lacroix, Frederic K.; Robertson, Brian; Bernier, Eric; Brosseau, Daniel F.

2003-05-01

Design and implementation of a free-space optical backplane for multiprocessor applications is presented. The system is designed to interconnect four multiprocessor nodes that communicate by using multiplexed 32-bit packets. Each multiprocessor node is electrically connected to an optoelectronic VLSI chip which implements the hyperplane interconnection architecture. The chips each contain 256 optical transmitters (implemented as dual-rail multiple quantum-well modulators) and 256 optical receivers. A rigid free-space microoptical interconnection system that interconnects the transceiver chips in a 512-channel unidirectional ring is implemented. Full design, implementation, and operational details are provided.

Design of an MR image processing module on an FPGA chip

NASA Astrophysics Data System (ADS)

Li, Limin; Wyrwicz, Alice M.

2015-06-01

We describe the design and implementation of an image processing module on a single-chip Field-Programmable Gate Array (FPGA) for real-time image processing. We also demonstrate that through graphical coding the design work can be greatly simplified. The processing module is based on a 2D FFT core. Our design is distinguished from previously reported designs in two respects. No off-chip hardware resources are required, which increases portability of the core. Direct matrix transposition usually required for execution of 2D FFT is completely avoided using our newly-designed address generation unit, which saves considerable on-chip block RAMs and clock cycles. The image processing module was tested by reconstructing multi-slice MR images from both phantom and animal data. The tests on static data show that the processing module is capable of reconstructing 128 × 128 images at speed of 400 frames/second. The tests on simulated real-time streaming data demonstrate that the module works properly under the timing conditions necessary for MRI experiments.

Design of an MR image processing module on an FPGA chip

PubMed Central

Li, Limin; Wyrwicz, Alice M.

2015-01-01

We describe the design and implementation of an image processing module on a single-chip Field-Programmable Gate Array (FPGA) for real-time image processing. We also demonstrate that through graphical coding the design work can be greatly simplified. The processing module is based on a 2D FFT core. Our design is distinguished from previously reported designs in two respects. No off-chip hardware resources are required, which increases portability of the core. Direct matrix transposition usually required for execution of 2D FFT is completely avoided using our newly-designed address generation unit, which saves considerable on-chip block RAMs and clock cycles. The image processing module was tested by reconstructing multi-slice MR images from both phantom and animal data. The tests on static data show that the processing module is capable of reconstructing 128 × 128 images at speed of 400 frames/second. The tests on simulated real-time streaming data demonstrate that the module works properly under the timing conditions necessary for MRI experiments. PMID:25909646

Use of a double chip seal to correct a flushing hot mix asphalt pavement in Washington State.

DOT National Transportation Integrated Search

2011-04-01

A chip seal constructed on an existing flushed roadway has the potential to result in bleeding or flushing of the new chip seal. The excess binder, if not properly accounted for during design and construction, will migrate to the surface of the chip ...

A 50Mbit/Sec. CMOS Video Linestore System

NASA Astrophysics Data System (ADS)

Jeung, Yeun C.

1988-10-01

This paper reports the architecture, design and test results of a CMOS single chip programmable video linestore system which has 16-bit data words with 1024 bit depth. The delay is fully programmable from 9 to 1033 samples by a 10 bit binary control word. The large 16 bit data word width makes the chip useful for a wide variety of digital video signal processing applications such as DPCM coding, High-Definition TV, and Video scramblers/descramblers etc. For those applications, the conventional large fixed-length shift register or static RAM scheme is not very popular because of its lack of versatility, high power consumption, and required support circuitry. The very high throughput of 50Mbit/sec is made possible by a highly parallel, pipelined dynamic memory architecture implemented in a 2-um N-well CMOS technology. The basic cell of the programmable video linestore chip is an four transistor dynamic RAM element. This cell comprises the majority of the chip's real estate, consumes no static power, and gives good noise immunity to the simply designed sense amplifier. The chip design was done using Bellcore's version of the MULGA virtual grid symbolic layout system. The chip contains approximately 90,000 transistors in an area of 6.5 x 7.5 square mm and the I/Os are TTL compatible. The chip is packaged in a 68-pin leadless ceramic chip carrier package.

Andy Jenkins Builds Applications Development For Lab-on-a-Chip

NASA Technical Reports Server (NTRS)

2004-01-01

Andy Jenkins, an engineer for the Lab on a Chip Applications Development program, helped build the Applications Development Unit (ADU-25), a one-of-a-kind facility for controlling and analyzing processes on chips with extreme accuracy. Pressure is used to cause fluids to travel through network of fluid pathways, or micro-channels, embossed on the chips through a process similar to the one used to print circuits on computer chips. To make customized chips for various applications, NASA has an agreement with the U.S. Army's Micro devices and Micro fabrication Laboratory at Redstone Arsenal in Huntsville, Alabama, where NASA's Marshall Space Flight Center (MSFC) is located. The Marshall Center team is also collaborating with scientists at other NASA centers and at universities to develop custom chip designs for many applications, such as studying how fluidic systems work in spacecraft and identifying microbes in self-contained life support systems. Chips could even be designed for use on Earth, such as for detecting deadly microbes in heating and air systems. (NASA/MSFC/D.Stoffer)

GeneChip Resequencing of the Smallpox Virus Genome Can Identify Novel Strains: a Biodefense Application▿

PubMed Central

Sulaiman, Irshad M.; Tang, Kevin; Osborne, John; Sammons, Scott; Wohlhueter, Robert M.

2007-01-01

We developed a set of seven resequencing GeneChips, based on the complete genome sequences of 24 strains of smallpox virus (variola virus), for rapid characterization of this human-pathogenic virus. Each GeneChip was designed to analyze a divergent segment of approximately 30,000 bases of the smallpox virus genome. This study includes the hybridization results of 14 smallpox virus strains. Of the 14 smallpox virus strains hybridized, only 7 had sequence information included in the design of the smallpox virus resequencing GeneChips; similar information for the remaining strains was not tiled as a reference in these GeneChips. By use of variola virus-specific primers and long-range PCR, 22 overlapping amplicons were amplified to cover nearly the complete genome and hybridized with the smallpox virus resequencing GeneChip set. These GeneChips were successful in generating nucleotide sequences for all 14 of the smallpox virus strains hybridized. Analysis of the data indicated that the GeneChip resequencing by hybridization was fast and reproducible and that the smallpox virus resequencing GeneChips could differentiate the 14 smallpox virus strains characterized. This study also suggests that high-density resequencing GeneChips have potential biodefense applications and may be used as an alternate tool for rapid identification of smallpox virus in the future. PMID:17182757

A scalable neural chip with synaptic electronics using CMOS integrated memristors.

PubMed

Cruz-Albrecht, Jose M; Derosier, Timothy; Srinivasa, Narayan

2013-09-27

The design and simulation of a scalable neural chip with synaptic electronics using nanoscale memristors fully integrated with complementary metal-oxide-semiconductor (CMOS) is presented. The circuit consists of integrate-and-fire neurons and synapses with spike-timing dependent plasticity (STDP). The synaptic conductance values can be stored in memristors with eight levels, and the topology of connections between neurons is reconfigurable. The circuit has been designed using a 90 nm CMOS process with via connections to on-chip post-processed memristor arrays. The design has about 16 million CMOS transistors and 73 728 integrated memristors. We provide circuit level simulations of the entire chip performing neuronal and synaptic computations that result in biologically realistic functional behavior.

Around Marshall

NASA Image and Video Library

2004-02-01

Andy Jenkins, an engineer for the Lab on a Chip Applications Development program, helped build the Applications Development Unit (ADU-25), a one-of-a-kind facility for controlling and analyzing processes on chips with extreme accuracy. Pressure is used to cause fluids to travel through network of fluid pathways, or micro-channels, embossed on the chips through a process similar to the one used to print circuits on computer chips. To make customized chips for various applications, NASA has an agreement with the U.S. Army's Micro devices and Micro fabrication Laboratory at Redstone Arsenal in Huntsville, Alabama, where NASA's Marshall Space Flight Center (MSFC) is located. The Marshall Center team is also collaborating with scientists at other NASA centers and at universities to develop custom chip designs for many applications, such as studying how fluidic systems work in spacecraft and identifying microbes in self-contained life support systems. Chips could even be designed for use on Earth, such as for detecting deadly microbes in heating and air systems. (NASA/MSFC/D.Stoffer)

Overlay improvement by exposure map based mask registration optimization

NASA Astrophysics Data System (ADS)

Shi, Irene; Guo, Eric; Chen, Ming; Lu, Max; Li, Gordon; Li, Rivan; Tian, Eric

2015-03-01

Along with the increased miniaturization of semiconductor electronic devices, the design rules of advanced semiconductor devices shrink dramatically. [1] One of the main challenges of lithography step is the layer-to-layer overlay control. Furthermore, DPT (Double Patterning Technology) has been adapted for the advanced technology node like 28nm and 14nm, corresponding overlay budget becomes even tighter. [2][3] After the in-die mask registration (pattern placement) measurement is introduced, with the model analysis of a KLA SOV (sources of variation) tool, it's observed that registration difference between masks is a significant error source of wafer layer-to-layer overlay at 28nm process. [4][5] Mask registration optimization would highly improve wafer overlay performance accordingly. It was reported that a laser based registration control (RegC) process could be applied after the pattern generation or after pellicle mounting and allowed fine tuning of the mask registration. [6] In this paper we propose a novel method of mask registration correction, which can be applied before mask writing based on mask exposure map, considering the factors of mask chip layout, writing sequence, and pattern density distribution. Our experiment data show if pattern density on the mask keeps at a low level, in-die mask registration residue error in 3sigma could be always under 5nm whatever blank type and related writer POSCOR (position correction) file was applied; it proves random error induced by material or equipment would occupy relatively fixed error budget as an error source of mask registration. On the real production, comparing the mask registration difference through critical production layers, it could be revealed that registration residue error of line space layers with higher pattern density is always much larger than the one of contact hole layers with lower pattern density. Additionally, the mask registration difference between layers with similar pattern density could also achieve under 5nm performance. We assume mask registration excluding random error is mostly induced by charge accumulation during mask writing, which may be calculated from surrounding exposed pattern density. Multi-loading test mask registration result shows that with x direction writing sequence, mask registration behavior in x direction is mainly related to sequence direction, but mask registration in y direction would be highly impacted by pattern density distribution map. It proves part of mask registration error is due to charge issue from nearby environment. If exposure sequence is chip by chip for normal multi chip layout case, mask registration of both x and y direction would be impacted analogously, which has also been proved by real data. Therefore, we try to set up a simple model to predict the mask registration error based on mask exposure map, and correct it with the given POSCOR (position correction) file for advanced mask writing if needed.

Numerical and experimental evaluation of microfluidic sorting devices.

PubMed

Taylor, Jay K; Ren, Carolyn L; Stubley, G D

2008-01-01

The development of lab-on-a-chip devices calls for the isolation or separation of specific bioparticles or cells. The design of a miniaturized cell-sorting device for handheld operation must follow the strict parameters associated with lab-on-a-chip technology. The limitations include applied voltage, high efficiency of cell-separation, reliability, size, flow control, and cost, among others. Currently used designs have achieved successful levels of cell isolation; however, further improvements in the microfluidic chip design are important to incorporate into larger systems. This study evaluates specific design modifications that contribute to the reduction of required applied potential aiming for developing portable devices, improved operation reliability by minimizing induced pressure disturbance when electrokinetic pumping is employed, and improved flow control by incorporating directing streams achieving dynamic sorting and counting. The chip designs fabricated in glass and polymeric materials include asymmetric channel widths for sample focusing, nonuniform channel depth for minimizing induced pressure disturbance, directing streams to assist particle flow control, and online filters for reducing channel blockage. Fluorescence-based visualization experimental results of electrokinetic focusing, flow field phenomena, and dynamic sorting demonstrate the advantages of the chip design. Numerical simulations in COMSOL are validated by the experimental data and used to investigate the effects of channel geometry and fluid properties on the flow field.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nabeel A. Riza

The goals of the Year 2006 Continuation Phase 2 three months period (April 1 to Sept. 30) of this project were to (a) conduct a probe elements industrial environment feasibility study and (b) fabricate embedded optical phase or microstructured SiC chips for individual gas species sensing. Specifically, SiC chips for temperature and pressure probe industrial applications were batch fabricated. Next, these chips were subject to a quality test for use in the probe sensor. A batch of the best chips for probe design were selected and subject to further tests that included sensor performance based on corrosive chemical exposure, powermore » plant soot exposure, light polarization variations, and extreme temperature soaking. Experimental data were investigated in detail to analyze these mentioned industrial parameters relevant to a power plant. Probe design was provided to overcome mechanical vibrations. All these goals have been achieved and are described in detail in the report. The other main focus of the reported work is to modify the SiC chip by fabricating an embedded optical phase or microstructures within the chip to enable gas species sensing under high temperature and pressure. This has been done in the Kar UCF Lab. using a laser-based system whose design and operation is explained. Experimental data from the embedded optical phase-based chip for changing temperatures is provided and shown to be isolated from gas pressure and species. These design and experimentation results are summarized to give positive conclusions on the proposed high temperature high pressure gas species detection optical sensor technology.« less

Experiences with Lab-on-a-chip Technology in Support of NASA Supported Research

NASA Technical Reports Server (NTRS)

Monaco, Lisa

2003-01-01

Under the auspices of the Microgravity Sciences and Application Department at Marshall Space Flight Center, we have custom designed and fabricated a lab-on-a-chip (LOC) device, along with Caliper Technologies, for macromolecular crystal growth. The chip has been designed to deliver specified proportions of up-to five various constituents to one of two growth wells (on-chip) for crystal growth. To date, we have grown crystals of thaumatin, glucose isomerase and appoferitin on the chip. The LOC approach offered many advantages that rendered it highly suitable for space based hardware to perform crystal growth on the International Space Station. The same hardware that was utilized for the crystal growth investigations, has also been used by researchers at Glenn Research Center to investigate aspects of microfluidic phenomenon associated with two-phase flow. Additionally, our LOCAD (Lab-on-a-chip Application Development) team has lent its support to Johnson Space Center s Modular Assay for Solar System Exploration project. At present, the LOCAD team is working on the design and build of a unique lab-on-a-chip breadboard control unit whose function is not commercially available. The breadboard can be used as a test bed for the development of chip size labs for environmental monitoring, crew health monitoring assays, extended flight pharmacological preparations, and many more areas. This unique control unit will be configured for local use and/or remote operation, via the Internet, by other NASA centers. The lab-on-a-chip control unit is being developed with the primary goal of meeting Agency level strategic goals.

Design of a CMOS readout circuit on ultra-thin flexible silicon chip for printed strain gauges

NASA Astrophysics Data System (ADS)

Elsobky, Mourad; Mahsereci, Yigit; Keck, Jürgen; Richter, Harald; Burghartz, Joachim N.

2017-09-01

Flexible electronics represents an emerging technology with features enabling several new applications such as wearable electronics and bendable displays. Precise and high-performance sensors readout chips are crucial for high quality flexible electronic products. In this work, the design of a CMOS readout circuit for an array of printed strain gauges is presented. The ultra-thin readout chip and the printed sensors are combined on a thin Benzocyclobutene/Polyimide (BCB/PI) substrate to form a Hybrid System-in-Foil (HySiF), which is used as an electronic skin for robotic applications. Each strain gauge utilizes a Wheatstone bridge circuit, where four Aerosol Jet® printed meander-shaped resistors form a full-bridge topology. The readout chip amplifies the output voltage difference (about 5 mV full-scale swing) of the strain gauge. One challenge during the sensor interface circuit design is to compensate for the relatively large dc offset (about 30 mV at 1 mA) in the bridge output voltage so that the amplified signal span matches the input range of an analog-to-digital converter (ADC). The circuit design uses the 0. 5 µm mixed-signal GATEFORESTTM technology. In order to achieve the mechanical flexibility, the chip fabrication is based on either back thinned wafers or the ChipFilmTM technology, which enables the manufacturing of silicon chips with a thickness of about 20 µm. The implemented readout chip uses a supply of 5 V and includes a 5-bit digital-to-analog converter (DAC), a differential difference amplifier (DDA), and a 10-bit successive approximation register (SAR) ADC. The circuit is simulated across process, supply and temperature corners and the simulation results indicate excellent performance in terms of circuit stability and linearity.

Design and simulation of a semiconductor chip-based visible - NIR spectrometer for Earth observation

NASA Astrophysics Data System (ADS)

Coote, J.; Woolliams, E.; Fox, N.; Goodyer, I. D.; Sweeney, S. J.

2014-03-01

We present the development of a novel semiconductor chip-based spectrometer for calibration of Earth observation instruments. The chip follows the Solo spectroscopy approach utilising an array of microdisk resonators evanescently coupled to a central waveguide. Each resonator is tuned to select out a specific wavelength from the incoming spectrum, and forms a p-i-n junction in which current is generated when light of the correct wavelength is present. In this paper we discuss important design aspects including the choice of semiconductor material, design of semiconductor quantum well structures for optical absorption, and design and optimisation of the waveguide and resonators.

Chip seal design and specifications : final report.

DOT National Transportation Integrated Search

2016-12-01

Chip seals or seal coats, are a pavement preservation method constructed using a layer of asphalt binder that is covered by a uniformly graded aggregate. The benefits of chip seal include: sealing surface cracks, keeping water from penetrating the su...

DNA Microarray for Rapid Detection and Identification of Food and Water Borne Bacteria: From Dry to Wet Lab.

PubMed

Ranjbar, Reza; Behzadi, Payam; Najafi, Ali; Roudi, Raheleh

2017-01-01

A rapid, accurate, flexible and reliable diagnostic method may significantly decrease the costs of diagnosis and treatment. Designing an appropriate microarray chip reduces noises and probable biases in the final result. The aim of this study was to design and construct a DNA Microarray Chip for a rapid detection and identification of 10 important bacterial agents. In the present survey, 10 unique genomic regions relating to 10 pathogenic bacterial agents including Escherichia coli (E.coli), Shigella boydii, Sh.dysenteriae, Sh.flexneri, Sh.sonnei, Salmonella typhi, S.typhimurium, Brucella sp., Legionella pneumophila, and Vibrio cholera were selected for designing specific long oligo microarray probes. For this reason, the in-silico operations including utilization of the NCBI RefSeq database, Servers of PanSeq and Gview, AlleleID 7.7 and Oligo Analyzer 3.1 was done. On the other hand, the in-vitro part of the study comprised stages of robotic microarray chip probe spotting, bacterial DNAs extraction and DNA labeling, hybridization and microarray chip scanning. In wet lab section, different tools and apparatus such as Nexterion® Slide E, Qarray mini spotter, NimbleGen kit, TrayMix TM S4, and Innoscan 710 were used. A DNA microarray chip including 10 long oligo microarray probes was designed and constructed for detection and identification of 10 pathogenic bacteria. The DNA microarray chip was capable to identify all 10 bacterial agents tested simultaneously. The presence of a professional bioinformatician as a probe designer is needed to design appropriate multifunctional microarray probes to increase the accuracy of the outcomes.

Flip-chip bonded optoelectronic integration based on ultrathin silicon (UTSi) CMOS

NASA Astrophysics Data System (ADS)

Hong, Sunkwang; Ho, Tawei; Zhang, Liping; Sawchuk, Alexander A.

2003-06-01

We describe the design and test of flip-chip bonded optoelectronic CMOS devices based on Peregrine Semiconductor's 0.5 micron Ultra-Thin Silicon on sapphire (UTSi) technology. The UTSi process eliminates the substrate leakage that typically results in crosstalk and reduces parasitic capacitance to the substrate, providing many benefits compared to bulk silicon CMOS. The low-loss synthetic sapphire substrate is optically transparent and has a coefficient of thermal expansion suitable for flip-chip bonding of vertical cavity surface emitting lasers (VCSELs) and detectors. We have designed two different UTSi CMOS chips. One contains a flip-chip bonded 1 x 4 photodiode array, a receiver array, a double edge triggered D-flip flop-based 2047-pattern pseudo random bit stream (PRBS) generator and a quadrature-phase LC-voltage controlled oscillator (VCO). The other chip contains a flip-chip bonded 1 x 4 VCSEL array, a driver array based on high-speed low-voltage differential signals (LVDS) and a full-balanced differential LC-VCO. Each VCSEL driver and receiver has individual input and bias voltage adjustments. Each UTSi chip is mounted on different printed circuit boards (PCBs) which have holes with about 1 mm radius for optical output and input paths through the sapphire substrate. We discuss preliminary testing of these chips.

Chip-set for quality of service support in passive optical networks

NASA Astrophysics Data System (ADS)

Ringoot, Edwin; Hoebeke, Rudy; Slabbinck, B. Hans; Verhaert, Michel

1998-10-01

In this paper the design of a chip-set for QoS provisioning in ATM-based Passive Optical Networks is discussed. The implementation of a general-purpose switch chip on the Optical Network Unit is presented, with focus on the design of the cell scheduling and buffer management logic. The cell scheduling logic supports `colored' grants, priority jumping and weighted round-robin scheduling. The switch chip offers powerful buffer management capabilities enabling the efficient support of GFR and UBR services. Multicast forwarding is also supported. In addition, the architecture of a MAC controller chip developed for a SuperPON access network is introduced. In particular, the permit scheduling logic and its implementation on the Optical Line Termination will be discussed. The chip-set enables the efficient support of services with different service requirements on the SuperPON. The permit scheduling logic built into the MAC controller chip in combination with the cell scheduling and buffer management capabilities of the switch chip can be used by network operators to offer guaranteed service performance to delay sensitive services, and to efficiently and fairly distribute any spare capacity to delay insensitive services.

Innovative Teaching of IC Design and Manufacture Using the Superchip Platform

ERIC Educational Resources Information Center

Wilson, P. R.; Wilcock, R.; McNally, I.; Swabey, M.

2010-01-01

This paper describes how an intelligent chip architecture has allowed a large cohort of undergraduate (UG) students to be given effective practical insight into integrated circuit (IC) design by designing and manufacturing their own ICs. To achieve this, an efficient chip architecture, the "Superchip," was developed, which allows multiple student…

An Innovative Method of Teaching Electronic System Design with PSoC

ERIC Educational Resources Information Center

Ye, Zhaohui; Hua, Chengying

2012-01-01

Programmable system-on-chip (PSoC), which provides a microprocessor and programmable analog and digital peripheral functions in a single chip, is very convenient for mixed-signal electronic system design. This paper presents the experience of teaching contemporary mixed-signal electronic system design with PSoC in the Department of Automation,…

Design of an MR image processing module on an FPGA chip.

PubMed

Li, Limin; Wyrwicz, Alice M

2015-06-01

We describe the design and implementation of an image processing module on a single-chip Field-Programmable Gate Array (FPGA) for real-time image processing. We also demonstrate that through graphical coding the design work can be greatly simplified. The processing module is based on a 2D FFT core. Our design is distinguished from previously reported designs in two respects. No off-chip hardware resources are required, which increases portability of the core. Direct matrix transposition usually required for execution of 2D FFT is completely avoided using our newly-designed address generation unit, which saves considerable on-chip block RAMs and clock cycles. The image processing module was tested by reconstructing multi-slice MR images from both phantom and animal data. The tests on static data show that the processing module is capable of reconstructing 128×128 images at speed of 400 frames/second. The tests on simulated real-time streaming data demonstrate that the module works properly under the timing conditions necessary for MRI experiments. Copyright © 2015 Elsevier Inc. All rights reserved.

An Overview of Electronic Passport Security Features

NASA Astrophysics Data System (ADS)

Říha, Zdeněk

Electronic passports include contactless chip which stores personal data of the passport holder, information about the passport and the issuing institution. In its simplest form an electronic passport contains just a collection of read-only files, more advanced variants can include sophisticated cryptographic mechanisms protecting security of the document and / or privacy of the passport holder. This paper describes security features of electronic passports and discusses their efficiency.

Microfluidic high performance liquid chromatography-chip hyphenation to inductively coupled plasma-mass spectrometry.

PubMed

Bishop, David P; Blanes, Lucas; Wilson, Alexander B; Wilbanks, Thor; Killeen, Kevin; Grimm, Rudolf; Wenzel, Ross; Major, Derek; Macka, Mirek; Clarke, David; Schmid, Robin; Cole, Nerida; Doble, Philip A

2017-05-12

The Agilent Chip Cube Interface is a microfluidic chip-based technology originally designed for nanospray molecular mass spectrometry in which the sample enrichment, nano-column, tubing, connectors and spray tip were integrated into a single biocompatible chip. Here we describe the hyphenation of the Chip Cube Interface to ICP-MS via modification of the standard HPLC chip design and a new total consumption nebuliser suitable for flow rates as low as 300nLmin -1 . The potential of the instrument to eliminate common nanoLC - ICP-MS shortcomings such as leaks, blockages and band-broadening was demonstrated via analysis of cyanocobalamin in equine plasma. The method was linear over three orders of magnitude with an r 2 of 0.9999, the peak area repeatability was 1.9% (n=7), and the detection limit was 14ngmL -1 . This novel configuration of the Chip Cube Interface coupled to ICP-MS is a suitable platform for the analysis of biomolecules associated with trace metals and speciation applications. Copyright © 2017 Elsevier B.V. All rights reserved.

Design of a dual-mode electrochemical measurement and analysis system.

PubMed

Yang, Jr-Fu; Wei, Chia-Ling; Wu, Jian-Fu; Liu, Bin-Da

2013-01-01

A dual-mode electrochemical measurement and analysis system is proposed. This system includes a dual-mode chip, which was designed and fabricated by using TSMC 0.35 µm 3.3 V/5 V 2P4M mixed-signal CMOS process. Two electrochemical measurement and analysis methods, chronopotentiometry and voltammetry, can be performed by using the proposed chip and system. The proposed chip and system are verified successfully by performing voltammetry and chronopotentiometry on solutions.

Sequence information signal processor for local and global string comparisons

DOEpatents

Peterson, John C.; Chow, Edward T.; Waterman, Michael S.; Hunkapillar, Timothy J.

1997-01-01

A sequence information signal processing integrated circuit chip designed to perform high speed calculation of a dynamic programming algorithm based upon the algorithm defined by Waterman and Smith. The signal processing chip of the present invention is designed to be a building block of a linear systolic array, the performance of which can be increased by connecting additional sequence information signal processing chips to the array. The chip provides a high speed, low cost linear array processor that can locate highly similar global sequences or segments thereof such as contiguous subsequences from two different DNA or protein sequences. The chip is implemented in a preferred embodiment using CMOS VLSI technology to provide the equivalent of about 400,000 transistors or 100,000 gates. Each chip provides 16 processing elements, and is designed to provide 16 bit, two's compliment operation for maximum score precision of between -32,768 and +32,767. It is designed to provide a comparison between sequences as long as 4,194,304 elements without external software and between sequences of unlimited numbers of elements with the aid of external software. Each sequence can be assigned different deletion and insertion weight functions. Each processor is provided with a similarity measure device which is independently variable. Thus, each processor can contribute to maximum value score calculation using a different similarity measure.

Improved diamond coring bits developed for dry and chip-flush drilling

NASA Technical Reports Server (NTRS)

Decker, W. E.; Hampe, W. R.; Hampton, W. H.; Simon, A. B.

1971-01-01

Two rotary diamond bit designs, one operating with a chip-flushing fluid, the second including auger section to remove drilled chips, enhance usefulness of tool for exploratory and industrial core-drilling of hard, abrasive mineral deposits and structural masonry.

Systolic array IC for genetic computation

NASA Technical Reports Server (NTRS)

Anderson, D.

1991-01-01

Measuring similarities between large sequences of genetic information is a formidable task requiring enormous amounts of computer time. Geneticists claim that nearly two months of CRAY-2 time are required to run a single comparison of the known database against the new bases that will be found this year, and more than a CRAY-2 year for next year's genetic discoveries, and so on. The DNA IC, designed at HP-ICBD in cooperation with the California Institute of Technology and the Jet Propulsion Laboratory, is being implemented in order to move the task of genetic comparison onto workstations and personal computers, while vastly improving performance. The chip is a systolic (pumped) array comprised of 16 processors, control logic, and global RAM, totaling 400,000 FETS. At 12 MHz, each chip performs 2.7 billion 16 bit operations per second. Using 35 of these chips in series on one PC board (performing nearly 100 billion operations per second), a sequence of 560 bases can be compared against the eventual total genome of 3 billion bases, in minutes--on a personal computer. While the designed purpose of the DNA chip is for genetic research, other disciplines requiring similarity measurements between strings of 7 bit encoded data could make use of this chip as well. Cryptography and speech recognition are two examples. A mix of full custom design and standard cells, in CMOS34, were used to achieve these goals. Innovative test methods were developed to enhance controllability and observability in the array. This paper describes these techniques as well as the chip's functionality. This chip was designed in the 1989-90 timeframe.

On-Chip Power-Combining for High-Power Schottky Diode-Based Frequency Multipliers

NASA Technical Reports Server (NTRS)

Chattopadhyay, Goutam; Mehdi, Imran; Schlecht, Erich T.; Lee, Choonsup; Siles, Jose V.; Maestrini, Alain E.; Thomas, Bertrand; Jung, Cecile D.

2013-01-01

A 1.6-THz power-combined Schottky frequency tripler was designed to handle approximately 30 mW input power. The design of Schottky-based triplers at this frequency range is mainly constrained by the shrinkage of the waveguide dimensions with frequency and the minimum diode mesa sizes, which limits the maximum number of diodes that can be placed on the chip to no more than two. Hence, multiple-chip power-combined schemes become necessary to increase the power-handling capabilities of high-frequency multipliers. The design presented here overcomes difficulties by performing the power-combining directly on-chip. Four E-probes are located at a single input waveguide in order to equally pump four multiplying structures (featuring two diodes each). The produced output power is then recombined at the output using the same concept.

Optimization of a PCRAM Chip for high-speed read and highly reliable reset operations

NASA Astrophysics Data System (ADS)

Li, Xiaoyun; Chen, Houpeng; Li, Xi; Wang, Qian; Fan, Xi; Hu, Jiajun; Lei, Yu; Zhang, Qi; Tian, Zhen; Song, Zhitang

2016-10-01

The widely used traditional Flash memory suffers from its performance limits such as its serious crosstalk problems, and increasing complexity of floating gate scaling. Phase change random access memory (PCRAM) becomes one of the most potential nonvolatile memories among the new memory techniques. In this paper, a 1M-bit PCRAM chip is designed based on the SMIC 40nm CMOS technology. Focusing on the read and write performance, two new circuits with high-speed read operation and highly reliable reset operation are proposed. The high-speed read circuit effectively reduces the reading time from 74ns to 40ns. The double-mode reset circuit improves the chip yield. This 1M-bit PCRAM chip has been simulated on cadence. After layout design is completed, the chip will be taped out for post-test.

Separation and Analysis of Adherent and Non-Adherent Cancer Cells Using a Single-Cell Microarray Chip.

PubMed

Yamamura, Shohei; Yamada, Eriko; Kimura, Fukiko; Miyajima, Kumiko; Shigeto, Hajime

2017-10-21

A new single-cell microarray chip was designed and developed to separate and analyze single adherent and non-adherent cancer cells. The single-cell microarray chip is made of polystyrene with over 60,000 microchambers of 10 different size patterns (31-40 µm upper diameter, 11-20 µm lower diameter). A drop of suspension of adherent carcinoma (NCI-H1650) and non-adherent leukocyte (CCRF-CEM) cells was placed onto the chip, and single-cell occupancy of NCI-H1650 and CCRF-CEM was determined to be 79% and 84%, respectively. This was achieved by controlling the chip design and surface treatment. Analysis of protein expression in single NCI-H1650 and CCRF-CEM cells was performed on the single-cell microarray chip by multi-antibody staining. Additionally, with this system, we retrieved positive single cells from the microchambers by a micromanipulator. Thus, this system demonstrates the potential for easy and accurate separation and analysis of various types of single cells.

A 260-340 GHz Dual Chip Frequency Tripler for THz Frequency Multiplier Chains

NASA Technical Reports Server (NTRS)

Maestrini, Alain; Tripon-Canseliet, Charlotte; Ward, John S.; Gill, John J.; Mehdi, Imran

2006-01-01

We designed and fabricated a fix-tuned balanced frequency tripler working in the 260-340 GHz band to be the first stage of a x3x3x3 multiplier chain to 2.7 THz. The design of a dual-chip version of this multiplier featuring an input splitter / output combiner as part of the input / output matching networks of both chips - with no degradation of the expected bandwidth and efficiency- will be presented.

Development of a CMOS-compatible PCR chip: comparison of design and system strategies

NASA Astrophysics Data System (ADS)

Erill, Ivan; Campoy, Susana; Rus, José; Fonseca, Luis; Ivorra, Antoni; Navarro, Zenón; Plaza, José A.; Aguiló, Jordi; Barbé, Jordi

2004-11-01

In the last decade research in chips for DNA amplification through the polymerase chain reaction (PCR) has been relatively abundant, but has taken very diverse approaches, leaving little common ground for a straightforward comparison of results. Here we report the development of a line of PCR chips that is fully compatible with complementary-metal-oxide-semiconductor (CMOS) technology and its revealing use as a general platform to test and compare a wide range of experimental parameters involved in PCR-chip design and operation. Peltier-heated and polysilicon thin-film driven PCR chips have been produced and directly compared in terms of efficiency, speed and power consumption, showing that thin-film systems run faster and more efficiently than Peltier-based ones, but yield inferior PCR products. Serpentine-like chamber designs have also been compared with standard rectangular designs and with the here reported rhomboidal chamber shape, showing that serpentine-like chambers do not have detrimental effects in PCR efficiency when using non-flow-through schemes, and that chamber design has a strong impact on sample insertion/extraction yields. With an accurate temperature control (±0.2 °C) we have optimized reaction kinetics to yield sound PCR amplifications of 25 µl mixtures in 20 min and with 24.4 s cycle times, confirming that a titrated amount of bovine albumin serum (BSA, 2.5 µg µl-1) is essential to counteract polymerase adsorption at chip walls. The reported use of a CMOS-compatible technological process paves the way for an easy adaption to foundry requirements and for a scalable integration of electro-optic detection and control circuitry.

Architectural Techniques For Managing Non-volatile Caches

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mittal, Sparsh

As chip power dissipation becomes a critical challenge in scaling processor performance, computer architects are forced to fundamentally rethink the design of modern processors and hence, the chip-design industry is now at a major inflection point in its hardware roadmap. The high leakage power and low density of SRAM poses serious obstacles in its use for designing large on-chip caches and for this reason, researchers are exploring non-volatile memory (NVM) devices, such as spin torque transfer RAM, phase change RAM and resistive RAM. However, since NVMs are not strictly superior to SRAM, effective architectural techniques are required for making themmore » a universal memory solution. This book discusses techniques for designing processor caches using NVM devices. It presents algorithms and architectures for improving their energy efficiency, performance and lifetime. It also provides both qualitative and quantitative evaluation to help the reader gain insights and motivate them to explore further. This book will be highly useful for beginners as well as veterans in computer architecture, chip designers, product managers and technical marketing professionals.« less

A demonstration of CMOS VLSI circuit prototyping in support of the site facility using the 1.2 micron standard cell library developed by National Security Agency

NASA Technical Reports Server (NTRS)

Smith, Edwyn D.

1991-01-01

Two silicon CMOS application specific integrated circuits (ASICs), a data generation chip, and a data checker chip were designed. The conversion of the data generator circuitry into a pair of CMOS ASIC chips using the 1.2 micron standard cell library is documented. The logic design of the data checker is discussed. The functions of the control circuitry is described. An accurate estimate of timing relationships is essential to make sure that the logic design performs correctly under practical conditions. Timing and delay information are examined.

The design of high performance, low power triple-track magnetic sensor chip.

PubMed

Wu, Xiulong; Li, Minghua; Lin, Zhiting; Xi, Mengyuan; Chen, Junning

2013-07-09

This paper presents a design of a high performance and low power consumption triple-track magnetic sensor chip which was fabricated in TSMC 0.35 μm CMOS process. This chip is able to simultaneously sense, decode and read out the information stored in triple-track magnetic cards. A reference voltage generating circuit, a low-cost filter circuit, a power-on reset circuit, an RC oscillator, and a pre-decoding circuit are utilized as the basic modules. The triple-track magnetic sensor chip has four states, i.e., reset, sleep, swiping card and data read-out. In sleep state, the internal RC oscillator is closed, which means that the digital part does not operate to optimize energy consumption. In order to improve decoding accuracy and expand the sensing range of the signal, two kinds of circuit are put forward, naming offset correction circuit, and tracking circuit. With these two circuits, the sensing function of this chip can be more efficiently and accurately. We simulated these circuit modules with TSMC technology library. The results showed that these modules worked well within wide range input signal. Based on these results, the layout and tape-out were carried out. The measurement results showed that the chip do function well within a wide swipe speed range, which achieved the design target.

Prototype detection unit for the CHIPS experiment

NASA Astrophysics Data System (ADS)

Pfützner, Maciej M.

2017-09-01

CHIPS (CHerenkov detectors In mine PitS) is an R&D project aiming to develop novel cost-effective neutrino detectors, focused on measuring the CP-violating neutrino mixing phase (δ CP). A single detector module, containing an enclosed volume of purified water, would be submerged in an existing lake, located in a neutrino beam. A staged approach is proposed with first detectors deployed in a flooded mine pit in Northern Minnesota, 7 mrad off-axis from the existing NuMI beam. A small proof-of-principle model (CHIPS-M) has already been tested and the first stage of a fully functional 10 kt module (CHIPS-10) is planned for 2018. One of the instruments submerged on board of CHIPS-M in autumn 2015 was a prototype detection unit, constructed at Nikhef. The unit contains hardware borrowed from the KM3NeT experiment, including 16 3 inch photomultiplier tubes and readout electronics. In addition to testing the mechanical design and data acquisition, the detector was used to record a large sample of cosmic ray muon events. The collected data is valuable for characterising the cosmic muon background and validating a Monte Carlo simulation used to optimise future designs. This paper introduces the CHIPS project, describes the design of the prototype unit, and presents the results of a preliminary data analysis.

The Design of High Performance, Low Power Triple-Track Magnetic Sensor Chip

PubMed Central

Wu, Xiulong; Li, Minghua; Lin, Zhiting; Xi, Mengyuan; Chen, Junning

2013-01-01

This paper presents a design of a high performance and low power consumption triple-track magnetic sensor chip which was fabricated in TSMC 0.35 μm CMOS process. This chip is able to simultaneously sense, decode and read out the information stored in triple-track magnetic cards. A reference voltage generating circuit, a low-cost filter circuit, a power-on reset circuit, an RC oscillator, and a pre-decoding circuit are utilized as the basic modules. The triple-track magnetic sensor chip has four states, i.e., reset, sleep, swiping card and data read-out. In sleep state, the internal RC oscillator is closed, which means that the digital part does not operate to optimize energy consumption. In order to improve decoding accuracy and expand the sensing range of the signal, two kinds of circuit are put forward, naming offset correction circuit, and tracking circuit. With these two circuits, the sensing function of this chip can be more efficiently and accurately. We simulated these circuit modules with TSMC technology library. The results showed that these modules worked well within wide range input signal. Based on these results, the layout and tape-out were carried out. The measurement results showed that the chip do function well within a wide swipe speed range, which achieved the design target. PMID:23839231

Optimization of multiplexed PCR on an integrated microfluidic forensic platform for rapid DNA analysis.

PubMed

Estes, Matthew D; Yang, Jianing; Duane, Brett; Smith, Stan; Brooks, Carla; Nordquist, Alan; Zenhausern, Frederic

2012-12-07

This study reports the design, prototyping, and assay development of multiplexed polymerase chain reaction (PCR) on a plastic microfluidic device. Amplification of 17 DNA loci is carried out directly on-chip as part of a system for continuous workflow processing from sample preparation (SP) to capillary electrophoresis (CE). For enhanced performance of on-chip PCR amplification, improved control systems have been developed making use of customized Peltier assemblies, valve actuators, software, and amplification chemistry protocols. Multiple enhancements to the microfluidic chip design have been enacted to improve the reliability of sample delivery through the various on-chip modules. This work has been enabled by the encapsulation of PCR reagents into a solid phase material through an optimized Solid Phase Encapsulating Assay Mix (SPEAM) bead-based hydrogel fabrication process. SPEAM bead technology is reliably coupled with precise microfluidic metering and dispensing for efficient amplification and subsequent DNA short tandem repeat (STR) fragment analysis. This provides a means of on-chip reagent storage suitable for microfluidic automation, with the long shelf-life necessary for point-of-care (POC) or field deployable applications. This paper reports the first high quality 17-plex forensic STR amplification from a reference sample in a microfluidic chip with preloaded solid phase reagents, that is designed for integration with up and downstream processing.

Using Ant Colony Optimization for Routing in VLSI Chips

NASA Astrophysics Data System (ADS)

Arora, Tamanna; Moses, Melanie

2009-04-01

Rapid advances in VLSI technology have increased the number of transistors that fit on a single chip to about two billion. A frequent problem in the design of such high performance and high density VLSI layouts is that of routing wires that connect such large numbers of components. Most wire-routing problems are computationally hard. The quality of any routing algorithm is judged by the extent to which it satisfies routing constraints and design objectives. Some of the broader design objectives include minimizing total routed wire length, and minimizing total capacitance induced in the chip, both of which serve to minimize power consumed by the chip. Ant Colony Optimization algorithms (ACO) provide a multi-agent framework for combinatorial optimization by combining memory, stochastic decision and strategies of collective and distributed learning by ant-like agents. This paper applies ACO to the NP-hard problem of finding optimal routes for interconnect routing on VLSI chips. The constraints on interconnect routing are used by ants as heuristics which guide their search process. We found that ACO algorithms were able to successfully incorporate multiple constraints and route interconnects on suite of benchmark chips. On an average, the algorithm routed with total wire length 5.5% less than other established routing algorithms.

Hardware architecture design of a fast global motion estimation method

NASA Astrophysics Data System (ADS)

Liang, Chaobing; Sang, Hongshi; Shen, Xubang

2015-12-01

VLSI implementation of gradient-based global motion estimation (GME) faces two main challenges: irregular data access and high off-chip memory bandwidth requirement. We previously proposed a fast GME method that reduces computational complexity by choosing certain number of small patches containing corners and using them in a gradient-based framework. A hardware architecture is designed to implement this method and further reduce off-chip memory bandwidth requirement. On-chip memories are used to store coordinates of the corners and template patches, while the Gaussian pyramids of both the template and reference frame are stored in off-chip SDRAMs. By performing geometric transform only on the coordinates of the center pixel of a 3-by-3 patch in the template image, a 5-by-5 area containing the warped 3-by-3 patch in the reference image is extracted from the SDRAMs by burst read. Patched-based and burst mode data access helps to keep the off-chip memory bandwidth requirement at the minimum. Although patch size varies at different pyramid level, all patches are processed in term of 3x3 patches, so the utilization of the patch-processing circuit reaches 100%. FPGA implementation results show that the design utilizes 24,080 bits on-chip memory and for a sequence with resolution of 352x288 and frequency of 60Hz, the off-chip bandwidth requirement is only 3.96Mbyte/s, compared with 243.84Mbyte/s of the original gradient-based GME method. This design can be used in applications like video codec, video stabilization, and super-resolution, where real-time GME is a necessity and minimum memory bandwidth requirement is appreciated.

The Role of Myoepithelial Maspin in Breast Carcinoma Progression Diagnosis and Screening

DTIC Science & Technology

2003-08-01

expression pro- xenografts, the tumors were essentially avascular and their filing (gene chip analysis) to see whether the different myo- 116 S.H. Barskv...factor; aFGF, acidic fibroblast growth factor; TFGa, transforming growth factor a; TGFP3. transforming growth factor 03; TNFa, tumor necrosis factor a...angiogenesis but containing bound angiogenic inhibitors. These myoepithelial xenografts exhibit only minimal hypoxia but extensive necrosis compared with their

Apparatus and methods for packaging integrated circuit chips with antenna modules providing closed electromagnetic environment for integrated antennas

NASA Technical Reports Server (NTRS)

Gaucher, Brian P. (Inventor); Grzyb, Janusz (Inventor); Liu, Duixian (Inventor); Pfeiffer, Ullrich R. (Inventor)

2008-01-01

Apparatus and methods are provided for packaging IC chips together with integrated antenna modules designed to provide a closed EM (electromagnetic) environment for antenna radiators, thereby allowing antennas to be designed independent from the packaging technology.

Design and standalone characterisation of a capacitively coupled HV-CMOS sensor chip for the CLIC vertex detector

NASA Astrophysics Data System (ADS)

Kremastiotis, I.; Ballabriga, R.; Campbell, M.; Dannheim, D.; Fiergolski, A.; Hynds, D.; Kulis, S.; Peric, I.

2017-09-01

The concept of capacitive coupling between sensors and readout chips is under study for the vertex detector at the proposed high-energy CLIC electron positron collider. The CLICpix Capacitively Coupled Pixel Detector (C3PD) is an active High-Voltage CMOS sensor, designed to be capacitively coupled to the CLICpix2 readout chip. The chip is implemented in a commercial 180 nm HV-CMOS process and contains a matrix of 128×128 square pixels with 25μm pitch. First prototypes have been produced with a standard resistivity of ~20 Ωcm for the substrate and tested in standalone mode. The results show a rise time of ~20 ns, charge gain of 190 mV/ke- and ~40 e- RMS noise for a power consumption of 4.8μW/pixel. The main design aspects, as well as standalone measurement results, are presented.

Mechanical design optimization of a single-axis MOEMS accelerometer based on a grating interferometry cavity for ultrahigh sensitivity

NASA Astrophysics Data System (ADS)

Lu, Qianbo; Bai, Jian; Wang, Kaiwei; Lou, Shuqi; Jiao, Xufen; Han, Dandan; Yang, Guoguang

2016-08-01

The ultrahigh static displacement-acceleration sensitivity of a mechanical sensing chip is essential primarily for an ultrasensitive accelerometer. In this paper, an optimal design to implement to a single-axis MOEMS accelerometer consisting of a grating interferometry cavity and a micromachined sensing chip is presented. The micromachined sensing chip is composed of a proof mass along with its mechanical cantilever suspension and substrate. The dimensional parameters of the sensing chip, including the length, width, thickness and position of the cantilevers are evaluated and optimized both analytically and by finite-element-method (FEM) simulation to yield an unprecedented acceleration-displacement sensitivity. Compared with one of the most sensitive single-axis MOEMS accelerometers reported in the literature, the optimal mechanical design can yield a profound sensitivity improvement with an equal footprint area, specifically, 200% improvement in displacement-acceleration sensitivity with moderate resonant frequency and dynamic range. The modified design was microfabricated, packaged with the grating interferometry cavity and tested. The experimental results demonstrate that the MOEMS accelerometer with modified design can achieve the acceleration-displacement sensitivity of about 150μm/g and acceleration sensitivity of greater than 1500V/g, which validates the effectiveness of the optimal design.

The Design, Fabrication and Characterization of a Transparent Atom Chip

PubMed Central

Chuang, Ho-Chiao; Huang, Chia-Shiuan; Chen, Hung-Pin; Huang, Chi-Sheng; Lin, Yu-Hsin

2014-01-01

This study describes the design and fabrication of transparent atom chips for atomic physics experiments. A fabrication process was developed to define the wire patterns on a transparent glass substrate to create the desired magnetic field for atom trapping experiments. An area on the chip was reserved for the optical access, so that the laser light can penetrate directly through the glass substrate for the laser cooling process. Furthermore, since the thermal conductivity of the glass substrate is poorer than other common materials for atom chip substrate, for example silicon, silicon carbide, aluminum nitride. Thus, heat dissipation copper blocks are designed on the front and back of the glass substrate to improve the electrical current conduction. The testing results showed that a maximum burnout current of 2 A was measured from the wire pattern (with a width of 100 μm and a height of 20 μm) without any heat dissipation design and it can increase to 2.5 A with a heat dissipation design on the front side of the atom chips. Therefore, heat dissipation copper blocks were designed and fabricated on the back of the glass substrate just under the wire patterns which increases the maximum burnout current to 4.5 A. Moreover, a maximum burnout current of 6 A was achieved when the entire backside glass substrate was recessed and a thicker copper block was electroplated, which meets most requirements of atomic physics experiments. PMID:24922456

Programmable on-chip and off-chip network architecture on demand for flexible optical intra-datacenters.

PubMed

Rofoee, Bijan Rahimzadeh; Zervas, Georgios; Yan, Yan; Amaya, Norberto; Qin, Yixuan; Simeonidou, Dimitra

2013-03-11

The paper presents a novel network architecture on demand approach using on-chip and-off chip implementations, enabling programmable, highly efficient and transparent networking, well suited for intra-datacenter communications. The implemented FPGA-based adaptable line-card with on-chip design along with an architecture on demand (AoD) based off-chip flexible switching node, deliver single chip dual L2-Packet/L1-time shared optical network (TSON) server Network Interface Cards (NIC) interconnected through transparent AoD based switch. It enables hitless adaptation between Ethernet over wavelength switched network (EoWSON), and TSON based sub-wavelength switching, providing flexible bitrates, while meeting strict bandwidth, QoS requirements. The on and off-chip performance results show high throughput (9.86Ethernet, 8.68Gbps TSON), high QoS, as well as hitless switch-over.

Design of housing file box of fire academy based on RFID

NASA Astrophysics Data System (ADS)

Li, Huaiyi

2018-04-01

This paper presents a design scheme of intelligent file box based on RFID. The advantages of RFID file box and traditional file box are compared and analyzed, and the feasibility of RFID file box design is analyzed based on the actual situation of our university. After introducing the shape and structure design of the intelligent file box, the paper discusses the working process of the file box, and explains in detail the internal communication principle of the RFID file box and the realization of the control system. The application of the RFID based file box will greatly improve the efficiency of our school's archives management.

SNP Assay Development for Linkage Map Construction, Anchoring Whole-Genome Sequence, and Other Genetic and Genomic Applications in Common Bean

DOE Office of Scientific and Technical Information (OSTI.GOV)

Song, Qijian; Jia, Gaofeng; Hyten, David L.

A total of 992,682 single-nucleotide polymorphisms (SNPs) was identified as ideal for Illumina Infinium II BeadChip design after sequencing a diverse set of 17 common bean (Phaseolus vulgaris L) varieties with the aid of next-generation sequencing technology. From these, two BeadChips each with >5000 SNPs were designed. The BARCBean6K_1 BeadChip was selected for the purpose of optimizing polymorphism among market classes and, when possible, SNPs were targeted to sequence scaffolds in the Phaseolus vulgaris 14× genome assembly with sequence lengths >10 kb. The BARCBean6K_2 BeadChip was designed with the objective of anchoring additional scaffolds and to facilitate orientation of largemore » scaffolds. Analysis of 267 F2 plants from a cross of varieties Stampede × Red Hawk with the two BeadChips resulted in linkage maps with a total of 7040 markers including 7015 SNPs. With the linkage map, a total of 432.3 Mb of sequence from 2766 scaffolds was anchored to create the Phaseolus vulgaris v1.0 assembly, which accounted for approximately 89% of the 487 Mb of available sequence scaffolds of the Phaseolus vulgaris v0.9 assembly. A core set of 6000 SNPs (BARCBean6K_3 BeadChip) with high genotyping quality and polymorphism was selected based on the genotyping of 365 dry bean and 134 snap bean accessions with the BARCBean6K_1 and BARCBean6K_2 BeadChips. The BARCBean6K_3 BeadChip is a useful tool for genetics and genomics research and it is widely used by breeders and geneticists in the United States and abroad.« less

SNP Assay Development for Linkage Map Construction, Anchoring Whole-Genome Sequence, and Other Genetic and Genomic Applications in Common Bean

DOE PAGES

Song, Qijian; Jia, Gaofeng; Hyten, David L.; ...

2015-08-28

A total of 992,682 single-nucleotide polymorphisms (SNPs) was identified as ideal for Illumina Infinium II BeadChip design after sequencing a diverse set of 17 common bean (Phaseolus vulgaris L) varieties with the aid of next-generation sequencing technology. From these, two BeadChips each with >5000 SNPs were designed. The BARCBean6K_1 BeadChip was selected for the purpose of optimizing polymorphism among market classes and, when possible, SNPs were targeted to sequence scaffolds in the Phaseolus vulgaris 14× genome assembly with sequence lengths >10 kb. The BARCBean6K_2 BeadChip was designed with the objective of anchoring additional scaffolds and to facilitate orientation of largemore » scaffolds. Analysis of 267 F2 plants from a cross of varieties Stampede × Red Hawk with the two BeadChips resulted in linkage maps with a total of 7040 markers including 7015 SNPs. With the linkage map, a total of 432.3 Mb of sequence from 2766 scaffolds was anchored to create the Phaseolus vulgaris v1.0 assembly, which accounted for approximately 89% of the 487 Mb of available sequence scaffolds of the Phaseolus vulgaris v0.9 assembly. A core set of 6000 SNPs (BARCBean6K_3 BeadChip) with high genotyping quality and polymorphism was selected based on the genotyping of 365 dry bean and 134 snap bean accessions with the BARCBean6K_1 and BARCBean6K_2 BeadChips. The BARCBean6K_3 BeadChip is a useful tool for genetics and genomics research and it is widely used by breeders and geneticists in the United States and abroad.« less

SNP Assay Development for Linkage Map Construction, Anchoring Whole-Genome Sequence, and Other Genetic and Genomic Applications in Common Bean.

PubMed

Song, Qijian; Jia, Gaofeng; Hyten, David L; Jenkins, Jerry; Hwang, Eun-Young; Schroeder, Steven G; Osorno, Juan M; Schmutz, Jeremy; Jackson, Scott A; McClean, Phillip E; Cregan, Perry B

2015-08-28

A total of 992,682 single-nucleotide polymorphisms (SNPs) was identified as ideal for Illumina Infinium II BeadChip design after sequencing a diverse set of 17 common bean (Phaseolus vulgaris L) varieties with the aid of next-generation sequencing technology. From these, two BeadChips each with >5000 SNPs were designed. The BARCBean6K_1 BeadChip was selected for the purpose of optimizing polymorphism among market classes and, when possible, SNPs were targeted to sequence scaffolds in the Phaseolus vulgaris 14× genome assembly with sequence lengths >10 kb. The BARCBean6K_2 BeadChip was designed with the objective of anchoring additional scaffolds and to facilitate orientation of large scaffolds. Analysis of 267 F2 plants from a cross of varieties Stampede × Red Hawk with the two BeadChips resulted in linkage maps with a total of 7040 markers including 7015 SNPs. With the linkage map, a total of 432.3 Mb of sequence from 2766 scaffolds was anchored to create the Phaseolus vulgaris v1.0 assembly, which accounted for approximately 89% of the 487 Mb of available sequence scaffolds of the Phaseolus vulgaris v0.9 assembly. A core set of 6000 SNPs (BARCBean6K_3 BeadChip) with high genotyping quality and polymorphism was selected based on the genotyping of 365 dry bean and 134 snap bean accessions with the BARCBean6K_1 and BARCBean6K_2 BeadChips. The BARCBean6K_3 BeadChip is a useful tool for genetics and genomics research and it is widely used by breeders and geneticists in the United States and abroad. Copyright © 2015 Song et al.

Optical and Electric Multifunctional CMOS Image Sensors for On-Chip Biosensing Applications.

PubMed

Tokuda, Takashi; Noda, Toshihiko; Sasagawa, Kiyotaka; Ohta, Jun

2010-12-29

In this review, the concept, design, performance, and a functional demonstration of multifunctional complementary metal-oxide-semiconductor (CMOS) image sensors dedicated to on-chip biosensing applications are described. We developed a sensor architecture that allows flexible configuration of a sensing pixel array consisting of optical and electric sensing pixels, and designed multifunctional CMOS image sensors that can sense light intensity and electric potential or apply a voltage to an on-chip measurement target. We describe the sensors' architecture on the basis of the type of electric measurement or imaging functionalities.

Solving wood chip transport problems with computer simulation.

Treesearch

Dennis P. Bradley; Sharon A. Winsauer

1976-01-01

Efficient chip transport operations are difficult to achieve due to frequent and often unpredictable changes in distance to market, chipping rate, time spent at the mill, and equipment costs. This paper describes a computer simulation model that allows a logger to design an efficient transport system in response to these changing factors.

Gas Sensor Test Chip

NASA Technical Reports Server (NTRS)

Buehler, M.; Ryan, M.

1995-01-01

A new test chip is being developed to characterize conducting polymers used in gas sensors. The chip, a seven-layer cofired alumina substrate with gold electrodes, contains 11 comb and U- bend test structures. These structures are designed to measure the sheet resistance, conduction anisotropy, and peripheral conduction of spin-coated films that are not subsequently patterned.

All over the Map: A Progress Report on the State Children's Health Insurance Program (CHIP).

ERIC Educational Resources Information Center

Edmunds, Margo; Teitelbaum, Martha; Gleason, Cassy

The State Children's Health Insurance Program (CHIP) was designed in 1997 to support working families by providing affordable, quality health coverage for their children in an efficient, effective, and coordinated way. This report examines the progress made in implementing CHIP nationwide. Information sources included the following: (1) federal…

Chronic Disease Risk Reduction with a Community-Based Lifestyle Change Programme

ERIC Educational Resources Information Center

Merrill, Ray M; Aldana, Steven G; Greenlaw, Roger L; Salberg, Audrey; Englert, Heike

2008-01-01

Objective To assess whether reduced health risks resulting from the Coronary Health Improvement Project (CHIP) persist through 18 months. Methods: The CHIP is a four-week health education course designed to help individuals reduce cardiovascular risk by improving nutrition and physical activity behaviors. Analyses were based on 211 CHIP enrollees,…

A Single-Chip CMOS Pulse Oximeter with On-Chip Lock-In Detection.

PubMed

He, Diwei; Morgan, Stephen P; Trachanis, Dimitrios; van Hese, Jan; Drogoudis, Dimitris; Fummi, Franco; Stefanni, Francesco; Guarnieri, Valerio; Hayes-Gill, Barrie R

2015-07-14

Pulse oximetry is a noninvasive and continuous method for monitoring the blood oxygen saturation level. This paper presents the design and testing of a single-chip pulse oximeter fabricated in a 0.35 µm CMOS process. The chip includes photodiode, transimpedance amplifier, analogue band-pass filters, analogue-to-digital converters, digital signal processor and LED timing control. The experimentally measured AC and DC characteristics of individual circuits including the DC output voltage of the transimpedance amplifier, transimpedance gain of the transimpedance amplifier, and the central frequency and bandwidth of the analogue band-pass filters, show a good match (within 1%) with the circuit simulations. With modulated light source and integrated lock-in detection the sensor effectively suppresses the interference from ambient light and 1/f noise. In a breath hold and release experiment the single chip sensor demonstrates consistent and comparable performance to commercial pulse oximetry devices with a mean of 1.2% difference. The single-chip sensor enables a compact and robust design solution that offers a route towards wearable devices for health monitoring.

A Single-Chip CMOS Pulse Oximeter with On-Chip Lock-In Detection

PubMed Central

He, Diwei; Morgan, Stephen P.; Trachanis, Dimitrios; van Hese, Jan; Drogoudis, Dimitris; Fummi, Franco; Stefanni, Francesco; Guarnieri, Valerio; Hayes-Gill, Barrie R.

2015-01-01

Pulse oximetry is a noninvasive and continuous method for monitoring the blood oxygen saturation level. This paper presents the design and testing of a single-chip pulse oximeter fabricated in a 0.35 µm CMOS process. The chip includes photodiode, transimpedance amplifier, analogue band-pass filters, analogue-to-digital converters, digital signal processor and LED timing control. The experimentally measured AC and DC characteristics of individual circuits including the DC output voltage of the transimpedance amplifier, transimpedance gain of the transimpedance amplifier, and the central frequency and bandwidth of the analogue band-pass filters, show a good match (within 1%) with the circuit simulations. With modulated light source and integrated lock-in detection the sensor effectively suppresses the interference from ambient light and 1/f noise. In a breath hold and release experiment the single chip sensor demonstrates consistent and comparable performance to commercial pulse oximetry devices with a mean of 1.2% difference. The single-chip sensor enables a compact and robust design solution that offers a route towards wearable devices for health monitoring. PMID:26184225

Chip morphology as a performance predictor during high speed end milling of soda lime glass

NASA Astrophysics Data System (ADS)

Bagum, M. N.; Konneh, M.; Abdullah, K. A.; Ali, M. Y.

2018-01-01

Soda lime glass has application in DNA arrays and lab on chip manufacturing. Although investigation revealed that machining of such brittle material is possible using ductile mode under controlled cutting parameters and tool geometry, it remains a challenging task. Furthermore, ability of ductile machining is usually assed through machined surface texture examination. Soda lime glass is a strain rate and temperature sensitive material. Hence, influence on attainment of ductile surface due to adiabatic heat generated during high speed end milling using uncoated tungsten carbide tool is investigated in this research. Experimental runs were designed using central composite design (CCD), taking spindle speed, feed rate and depth of cut as input variable and tool-chip contact point temperature (Ttc) and the surface roughness (Rt) as responses. Along with machined surface texture, Rt and chip morphology was examined to assess machinability of soda lime glass. The relation between Ttc and chip morphology was examined. Investigation showed that around glass transition temperature (Tg) ductile chip produced and subsequently clean and ductile final machined surface produced.

Speckle Free, Low Coherency, High Brightness, and High Pulse Speed Infrared Collimated Light Sources for Mid-IR Target Designator and Hyperspectral Imaging

DTIC Science & Technology

2007-10-31

designator and hyperspectral imaging 6. AUfHOR(S) Yee-LoyLam 7. PERFORMING ORGANIZATION NAME(S) AND ADDRESS(ES) 8. PERFORMING ORGANIZATION DenseLight...DenseLight Semiconductors CONTENTS 1. Introduction 3 1.1 Overview of Project 3 1.2 Organization of Project 4 1.3 Target...Performance 4 2. SLED Chip Design and Fabrication Development 5 2.1 Organization of Design Stages 5 2.2 SLED Chip Design 6 2.3

Cytometer on a Chip

NASA Technical Reports Server (NTRS)

Fernandez, Salvador M.

2011-01-01

A cytometer now under development exploits spatial sorting of sampled cells on a microarray chip followed by use of grating-coupled surface-plasmon-resonance imaging (GCSPRI) to detect the sorted cells. This cytometer on a chip is a prototype of contemplated future miniature cytometers that would be suitable for rapidly identifying pathogens and other cells of interest in both field and laboratory applications and that would be attractive as alternatives to conventional flow cytometers. The basic principle of operation of a conventional flow cytometer requires fluorescent labeling of sampled cells, stringent optical alignment of a laser beam with a narrow orifice, and flow of the cells through the orifice, which is subject to clogging. In contrast, the principle of operation of the present cytometer on a chip does not require fluorescent labeling of cells, stringent optical alignment, or flow through a narrow orifice. The basic principle of operation of the cytometer on a chip also reduces the complexity, mass, and power of the associated laser and detection systems, relative to those needed in conventional flow cytometry. Instead of making cells flow in single file through a narrow flow orifice for sequential interrogation as in conventional flow cytometry, a liquid containing suspended sampled cells is made to flow over the front surface of a microarray chip on which there are many capture spots. Each capture spot is coated with a thin (approximately 50-nm) layer of gold that is, in turn, coated with antibodies that bind to cell-surface molecules characteristic of one the cell species of interest. The multiplicity of capture spots makes it possible to perform rapid, massively parallel analysis of a large cell population. The binding of cells to each capture spot gives rise to a minute change in the index of refraction at the surface of the chip. This change in the index of refraction is what is sensed in GCSPRI, as described briefly below. The identities of the various species in a sample of cells is spatially encoded in the chip by the pattern of capture spots. The number of cells of a particular species is determined from the magnitude of the GCSPRI signal from that spot. GCSPRI as used here can be summarized as follows: The cytometer chip is fabricated with a diffraction grating on its front surface. The chip is illuminated with a light emitting diode (LED) from the front. By proper choice of grating parameters and of the wavelength and the angle of incidence of a laser beam, laser light can be made to be coupled into an electromagnetic mode that resonates with surface plasmons and thus couples light into surface plasmons. Coupling of light into a surface plasmon at a given location reduces the amount of incident light reflected from that location. A change in the index of refraction at the surface of a capture spot gives rise to a change in the resonance condition. Depending on the specific design, the change in the index of refraction could manifest itself as a brightening or darkening, a change in the wavelength needed to excite the plasmon at a given angle of incidence, or a change in the angle of incidence needed to excite the plasmon at a given wavelength. Whereas a multiwavelength laser system with multichannel detection would be needed to detect multiple species in conventional flow cytometry, it suffices to use an LED and a single detector channel in the GCSPRI approach: this contributes significantly to reductions in cost, complexity, size, mass, and power. GCSPRI cytometer chips could be made of plastic and could be mass-produced cheaply by use of molding and other methods adopted from the manufacture of digital video disks. These methods are amenable to a high degree of miniaturization: such additional features as fluidic channels, reaction chambers, and fluid-coupling ports could readily be incorporated into the chips, without incurring substantial additional costs.

Cytometer on a Chip

NASA Technical Reports Server (NTRS)

Fernandez, Salvador M.

2011-01-01

A cytometer now under development exploits spatial sorting of sampled cells on a microarray chip followed by use of grating-coupled surface-plasmon-resonance imaging (GCSPRI) to detect the sorted cells. This cytometer on a chip is a prototype of contemplated future miniature cytometers that would be suitable for rapidly identifying pathogens and other cells of interest in both field and laboratory applications and that would be attractive as alternatives to conventional flow cytometers. The basic principle of operation of a conventional flow cytometer requires fluorescent labeling of sampled cells, stringent optical alignment of a laser beam with a narrow orifice, and flow of the cells through the orifice, which is subject to clogging. In contrast, the principle of operation of the present cytometer on a chip does not require fluorescent labeling of cells, stringent optical alignment, or flow through a narrow orifice. The basic principle of operation of the cytometer on a chip also reduces the complexity, mass, and power of the associated laser and detection systems, relative to those needed in conventional flow cytometry. Instead of making cells flow in single file through a narrow flow orifice for sequential interrogation as in conventional flow cytometry, a liquid containing suspended sampled cells is made to flow over the front surface of a microarray chip on which there are many capture spots. Each capture spot is coated with a thin (.50-nm) layer of gold that is, in turn, coated with antibodies that bind to cell-surface molecules characteristic of the cell species of interest. The multiplicity of capture spots makes it possible to perform rapid, massively parallel analysis of a large cell population. The binding of cells to each capture spot gives rise to a minute change in the index of refraction at the surface of the chip. This change in the index of refraction is what is sensed in GCSPRI, as described briefly below. The identities of the various species in a sample of cells is spatially encoded in the chip by the pattern of capture spots. The number of cells of a particular species is determined from the magnitude of the GCSPRI signal from that spot. GCSPRI as used here can be summarized as follows: The cytometer chip is fabricated with a diffraction grating on its front surface. The chip is illuminated with a light emitting diode (LED) from the front. By proper choice of grating parameters and of the wavelength and the angle of incidence of a laser beam, laser light can be made to be coupled into an electromagnetic mode that resonates with surface plasmons and thus couples light into surface plasmons. Coupling of light into a surface plasmon at a given location reduces the amount of incident light reflected from that location. A change in the index of refraction at the surface of a capture spot gives rise to a change in the resonance condition. Depending on the specific design, the change in the index of refraction could manifest itself as a brightening or darkening, a change in the wavelength needed to excite the plasmon at a given angle of incidence, or a change in the angle of incidence needed to excite the plasmon at a given wavelength. Whereas a multiwavelength laser system with multichannel detection would be needed to detect multiple species in conventional flow cytometry, it suffices to use an LED and a single detector channel in the GCSPRI approach: this contributes significantly to reductions in cost, complexity, size, mass, and power. GCSPRI cytometer chips could be made of plastic and could be mass-produced cheaply by use of molding and other methods adopted from the manufacture of digital video disks. These methods are amenable to a high degree of miniaturization: such additional features as fluidic channels, reaction chambers, and fluid-coupling ports could readily be incorporated into the chips, without incurring substantial additional costs.

Characterization of radiation effects in 65 nm digital circuits with the DRAD digital radiation test chip

NASA Astrophysics Data System (ADS)

Jara Casas, L. M.; Ceresa, D.; Kulis, S.; Miryala, S.; Christiansen, J.; Francisco, R.; Gnani, D.

2017-02-01

A Digital RADiation (DRAD) test chip has been specifically designed to study the impact of Total Ionizing Dose (TID) (<1 Grad) and Single Event Upset (SEU) on digital logic gates in a 65 nm CMOS technology. Nine different versions of standard cell libraries are studied in this chip, basically differing in the device dimensions, Vt flavor and layout of the device. Each library has eighteen test structures specifically designed to characterize delay degradation and power consumption of the standard cells. For SEU study, a dedicated test structure based on a shift register is designed for each library. TID results up to 500 Mrad are reported.

The GenoChip: A New Tool for Genetic Anthropology

PubMed Central

Elhaik, Eran; Greenspan, Elliott; Staats, Sean; Krahn, Thomas; Tyler-Smith, Chris; Xue, Yali; Tofanelli, Sergio; Francalacci, Paolo; Cucca, Francesco; Pagani, Luca; Jin, Li; Li, Hui; Schurr, Theodore G.; Greenspan, Bennett; Spencer Wells, R.

2013-01-01

The Genographic Project is an international effort aimed at charting human migratory history. The project is nonprofit and nonmedical, and, through its Legacy Fund, supports locally led efforts to preserve indigenous and traditional cultures. Although the first phase of the project was focused on uniparentally inherited markers on the Y-chromosome and mitochondrial DNA (mtDNA), the current phase focuses on markers from across the entire genome to obtain a more complete understanding of human genetic variation. Although many commercial arrays exist for genome-wide single-nucleotide polymorphism (SNP) genotyping, they were designed for medical genetic studies and contain medically related markers that are inappropriate for global population genetic studies. GenoChip, the Genographic Project’s new genotyping array, was designed to resolve these issues and enable higher resolution research into outstanding questions in genetic anthropology. The GenoChip includes ancestry informative markers obtained for over 450 human populations, an ancient human (Saqqaq), and two archaic hominins (Neanderthal and Denisovan) and was designed to identify all known Y-chromosome and mtDNA haplogroups. The chip was carefully vetted to avoid inclusion of medically relevant markers. To demonstrate its capabilities, we compared the FST distributions of GenoChip SNPs to those of two commercial arrays. Although all arrays yielded similarly shaped (inverse J) FST distributions, the GenoChip autosomal and X-chromosomal distributions had the highest mean FST, attesting to its ability to discern subpopulations. The chip performances are illustrated in a principal component analysis for 14 worldwide populations. In summary, the GenoChip is a dedicated genotyping platform for genetic anthropology. With an unprecedented number of approximately 12,000 Y-chromosomal and approximately 3,300 mtDNA SNPs and over 130,000 autosomal and X-chromosomal SNPs without any known health, medical, or phenotypic relevance, the GenoChip is a useful tool for genetic anthropology and population genetics. PMID:23666864

The GenoChip: a new tool for genetic anthropology.

PubMed

Elhaik, Eran; Greenspan, Elliott; Staats, Sean; Krahn, Thomas; Tyler-Smith, Chris; Xue, Yali; Tofanelli, Sergio; Francalacci, Paolo; Cucca, Francesco; Pagani, Luca; Jin, Li; Li, Hui; Schurr, Theodore G; Greenspan, Bennett; Spencer Wells, R

2013-01-01

The Genographic Project is an international effort aimed at charting human migratory history. The project is nonprofit and nonmedical, and, through its Legacy Fund, supports locally led efforts to preserve indigenous and traditional cultures. Although the first phase of the project was focused on uniparentally inherited markers on the Y-chromosome and mitochondrial DNA (mtDNA), the current phase focuses on markers from across the entire genome to obtain a more complete understanding of human genetic variation. Although many commercial arrays exist for genome-wide single-nucleotide polymorphism (SNP) genotyping, they were designed for medical genetic studies and contain medically related markers that are inappropriate for global population genetic studies. GenoChip, the Genographic Project's new genotyping array, was designed to resolve these issues and enable higher resolution research into outstanding questions in genetic anthropology. The GenoChip includes ancestry informative markers obtained for over 450 human populations, an ancient human (Saqqaq), and two archaic hominins (Neanderthal and Denisovan) and was designed to identify all known Y-chromosome and mtDNA haplogroups. The chip was carefully vetted to avoid inclusion of medically relevant markers. To demonstrate its capabilities, we compared the FST distributions of GenoChip SNPs to those of two commercial arrays. Although all arrays yielded similarly shaped (inverse J) FST distributions, the GenoChip autosomal and X-chromosomal distributions had the highest mean FST, attesting to its ability to discern subpopulations. The chip performances are illustrated in a principal component analysis for 14 worldwide populations. In summary, the GenoChip is a dedicated genotyping platform for genetic anthropology. With an unprecedented number of approximately 12,000 Y-chromosomal and approximately 3,300 mtDNA SNPs and over 130,000 autosomal and X-chromosomal SNPs without any known health, medical, or phenotypic relevance, the GenoChip is a useful tool for genetic anthropology and population genetics.

Development of a cleaning process for uranium chips machined with a glycol-water-borax coolant

DOE Office of Scientific and Technical Information (OSTI.GOV)

Taylor, P.A.

1984-12-01

A chip-cleaning process has been developed to remove the new glycol-water-borax coolant from oralloy chips. The process involves storing the freshly cut chips in Freon-TDF until they are cleaned, washing with water, and displacing the water with Freon-TDF. The wash water can be reused many times and still yield clean chips and then be added to the coolant to make up for evaporative losses. The Freon-TDF will be cycled by evaporation. The cleaning facility is currently being designed and should be operational by April 1985.

Microfluidic "thin chips" for chemical separations.

PubMed

Gaspar, Attila; Salgado, Marisol; Stevens, Schetema; Gomez, Frank A

2010-08-01

This paper describes the design, development and application of microfluidic "thin chips" fabricated from PDMS. Thin chips consist of multiple layers of PDMS chemically bonded onto each other. Unlike thicker PDMS chips that suffer from lack of sensitivity due to PDMS absorption in the VIS and UV range, the thinness of these chips allows for the detection of chromophoric species within the microchannel via an external fiber optics detection system. C18-modified reversed-phase silica particles are packed into the microchannel using a temporary taper created by a magnetic valve and separations using both pressure- and electrochromatographic-driven methods are detailed.

Glossiness of Colored Papers based on Computer Graphics Model and Its Measuring Method

NASA Astrophysics Data System (ADS)

Aida, Teizo

In the case of colored papers, the color of surface effects strongly upon the gloss of its paper. The new glossiness for such a colored paper is suggested in this paper. First, using the Achromatic and Chromatic Munsell colored chips, the author obtained experimental equation which represents the relation between lightness V ( or V and saturation C ) and psychological glossiness Gph of these chips. Then, the author defined a new glossiness G for the colored papers, based on the above mentioned experimental equations Gph and Cook-Torrance's reflection model which are widely used in the filed of Computer Graphics. This new glossiness is shown to be nearly proportional to the psychological glossiness Gph. The measuring system for the new glossiness G is furthermore descrived. The measuring time for one specimen is within 1 minute.

Vertical Integration of System-on-Chip Concepts in the Digital Design Curriculum

ERIC Educational Resources Information Center

Tang, Ying; Head, L. M.; Ramachandran, R. P.; Chatman, L. M.

2011-01-01

The rapid evolution of System-on-Chip (SoC) challenges academic curricula to keep pace with multidisciplinary/interdisciplinary system thinking. This paper presents a curricular prototype that cuts across artificial course boundaries and provides a meaningful exploration of diverse facets of SoC design. Specifically, experimental contents of a…

Design and fabricate multi channel microfluidic mold on top of glass slide using SU-8

NASA Astrophysics Data System (ADS)

Azman, N. A. N.; Rajapaksha, R. D. A. A.; Uda, M. N. A.; Hashim, U.

2017-09-01

Microfluidic is the study of fluid in microscale. Microfluidics provides miniaturized fluidic networks for processing and analyzing liquids in the nanoliter to milliliter range. Microfluidic device comprises of some essential segments or structure that are micromixer, microchannel and microchamber. The SU-8 mold is known as the most used technique in microfluidic fabrication due to the characteristic of very gooey polymer that can be spread over a thickness. In this study, in order to reduce the fabrication cost, the development and fabrication of SU-8 mold is replace by using a glass plate instead of silicon wafer which is used in the previous research. We designed a microfluidic chip for use with an IDE sensors to conduct multiplex detection of multiple channels. The microfluidic chip was designed to include multiplex detection for pathogen that consists of multiple channels of simultaneous results. The multi-channel microfluidic chip was designed, including the fluid outlet and inlet. A multi-channel microfluidic chip was used for pathogen detection. This paper sum up the fabrication of lab SU-8 mold using glass slide.

VLSI design of an RSA encryption/decryption chip using systolic array based architecture

NASA Astrophysics Data System (ADS)

Sun, Chi-Chia; Lin, Bor-Shing; Jan, Gene Eu; Lin, Jheng-Yi

2016-09-01

This article presents the VLSI design of a configurable RSA public key cryptosystem supporting the 512-bit, 1024-bit and 2048-bit based on Montgomery algorithm achieving comparable clock cycles of current relevant works but with smaller die size. We use binary method for the modular exponentiation and adopt Montgomery algorithm for the modular multiplication to simplify computational complexity, which, together with the systolic array concept for electric circuit designs effectively, lower the die size. The main architecture of the chip consists of four functional blocks, namely input/output modules, registers module, arithmetic module and control module. We applied the concept of systolic array to design the RSA encryption/decryption chip by using VHDL hardware language and verified using the TSMC/CIC 0.35 m 1P4 M technology. The die area of the 2048-bit RSA chip without the DFT is 3.9 × 3.9 mm2 (4.58 × 4.58 mm2 with DFT). Its average baud rate can reach 10.84 kbps under a 100 MHz clock.

Feasibility study, software design, layout and simulation of a two-dimensional fast Fourier transform machine for use in optical array interferometry

NASA Technical Reports Server (NTRS)

Boriakoff, Valentin; Chen, Wei

1990-01-01

The NASA-Cornell Univ.-Worcester Polytechnic Institute Fast Fourier Transform (FFT) chip based on the architecture of the systolic FFT computation as presented by Boriakoff is implemented into an operating device design. The kernel of the system, a systolic inner product floating point processor, was designed to be assembled into a systolic network that would take incoming data streams in pipeline fashion and provide an FFT output at the same rate, word by word. It was thoroughly simulated for proper operation, and it has passed a comprehensive set of tests showing no operational errors. The black box specifications of the chip, which conform to the initial requirements of the design as specified by NASA, are given. The five subcells are described and their high level function description, logic diagrams, and simulation results are presented. Some modification of the Read Only Memory (ROM) design were made, since some errors were found in it. Because a four stage pipeline structure was used, simulating such a structure is more difficult than an ordinary structure. Simulation methods are discussed. Chip signal protocols and chip pinout are explained.

Rapid and simple half-quantitative measurement alpha-fetoprotein by poly(dimethylsiloxane) microfluidic chip immunochromatographic assay

NASA Astrophysics Data System (ADS)

Tong, Chao; Jin, Qinghui; Zhao, Jianlong

2008-03-01

In this article, a kind of microfluidic method based on MEMS technology combined with gold immunochromatographic assay (GICA) is developed and discussed. Compared to the traditional GICA, this method supplies us convenient, multi-channel, in-parallel, low cost and similar efficiency approach in the fields of alpha-fetopro-tei (AFP)detection. Firstly, we improved the adhesion between the model material SU-8 and Silicon wafer, optimized approaches of the fabrication of the SU-8 model systematically, and fabricate the PDMS micro fluid chip with good reproduction successfully. Secondly, Surface modification and antibody immobilization methods with the GICA on the PDMS micro fluid analysis chip are studied, we choose the PDMS material and transfer GICA to the PDMS micro fluid chip successfully after researching the antibody immobilization efficiency of different materials utilized in fabrication of the micro fluid chip. In order to improve the reaction efficiency of the immobilized antibody, we studied the characteristics of micro fluid without the gas drive, and the fluid velocity control in our design; we also design structure of grove to strengthen the ability of immobilizing the antibody. The stimulation of the structure shows that it achieves great improvement and experiments prove the design is feasible.

Novel 3D micromirror for miniature optical bio-robe SiOB assembly

NASA Astrophysics Data System (ADS)

Singh, Janak; Xu, Yingshun; Premachandran, C. S.; Jason, Teo Hui Siang; Chen, Nanguang

2008-02-01

This article presents design and development of a novel 3D micromirror for large deflection scanning application in invivo optical coherence tomography (OCT) bio-imaging probe. Overall mirror chip size is critical to reduce the diameter of the probe; however, mirror plate itself should not be less than 500 μm as smaller size means reducing the amount of light collected after scattering for OCT imaging. In this study, mirror chip sizes of 1 × 1 mm2 and 1.5 × 1.5 mm2 were developed with respectively 400 and 500 micrometer diameter mirror plates. The design includes electro thermal excitation mechanism in the same plane as mirror plate to achieve 3D free space scanning. Larger deflection requires longer actuators, which usually increase the overall size of the chip. To accommodate longer actuators and keep overall chip size same curved beam actuators are designed and integrated for micromirror scanning. Typical length of the actuators was 800 micrometer, which provided up to 17 degrees deflection. Deep reactive ion etching (DRIE) process module was used extensively to etch high aspect ratio structures and keep the total mirror chip size small.

High-performance packaging for monolithic microwave and millimeter-wave integrated circuits

NASA Technical Reports Server (NTRS)

Shalkhauser, K. A.; Li, K.; Shih, Y. C.

1992-01-01

Packaging schemes were developed that provide low-loss, hermetic enclosure for advanced monolithic microwave and millimeter-wave integrated circuits (MMICs). The package designs are based on a fused quartz substrate material that offers improved radio frequency (RF) performance through 44 gigahertz (GHz). The small size and weight of the packages make them appropriate for a variety of applications, including phased array antenna systems. Packages were designed in two forms; one for housing a single MMIC chip, the second in the form of a multi-chip phased array module. The single chip array module was developed in three separate sizes, for chips of different geometry and frequency requirements. The phased array module was developed to address packaging directly for antenna applications, and includes transmission line and interconnect structures to support multi-element operation. All packages are fabricated using fused quartz substrate materials. As part of the packaging effort, a test fixture was developed to interface the single chip packages to conventional laboratory instrumentation for characterization of the packaged devices. The package and test fixture designs were both developed in a generic sense, optimizing performance for a wide range of possible applications and devices.

Ultra-thin silicon (UTSi) on insulator CMOS transceiver and time-division multiplexed switch chips for smart pixel integration

NASA Astrophysics Data System (ADS)

Zhang, Liping; Sawchuk, Alexander A.

2001-12-01

We describe the design, fabrication and functionality of two different 0.5 micron CMOS optoelectronic integrated circuit (OEIC) chips based on the Peregrine Semiconductor Ultra-Thin Silicon on insulator technology. The Peregrine UTSi silicon- on-sapphire (SOS) technology is a member of the silicon-on- insulator (SOI) family. The low-loss synthetic sapphire substrate is optically transparent and has good thermal conductivity and coefficient of thermal expansion properties, which meet the requirements for flip-chip bonding of VCSELs and other optoelectronic input-output components. One chip contains transceiver and network components, including four channel high-speed CMOS transceiver modules, pseudo-random bit stream (PRBS) generators, a voltage controlled oscillator (VCO) and other test circuits. The transceiver chips can operate in both self-testing mode and networking mode. An on- chip clock and true-single-phase-clock (TSPC) D-flip-flop have been designed to generate a PRBS at over 2.5 Gb/s for the high-speed transceiver arrays to operate in self-testing mode. In the networking mode, an even number of transceiver chips forms a ring network through free-space or fiber ribbon interconnections. The second chip contains four channel optical time-division multiplex (TDM) switches, optical transceiver arrays, an active pixel detector and additional test devices. The eventual applications of these chips will require monolithic OEICs with integrated optical input and output. After fabrication and testing, the CMOS transceiver array dies will be packaged with 850 nm vertical cavity surface emitting lasers (VCSELs), and metal-semiconductor- metal (MSM) or GaAs p-i-n detector die arrays to achieve high- speed optical interconnections. The hybrid technique could be either wire bonding or flip-chip bonding of the CMOS SOS smart-pixel arrays with arrays of VCSELs and photodetectors onto an optoelectronic chip carrier as a multi-chip module (MCM).

No3CoGP: non-conserved and conserved coexpressed gene pairs.

PubMed

Mal, Chittabrata; Aftabuddin, Md; Kundu, Sudip

2014-12-08

Analyzing the microarray data of different conditions, one can identify the conserved and condition-specific genes and gene modules, and thus can infer the underlying cellular activities. All the available tools based on Bioconductor and R packages differ in how they extract differential coexpression and at what level they study. There is a need for a user-friendly, flexible tool which can start analysis using raw or preprocessed microarray data and can report different levels of useful information. We present a GUI software, No3CoGP: Non-Conserved and Conserved Coexpressed Gene Pairs which takes Affymetrix microarray data (.CEL files or log2 normalized.txt files) along with annotation file (.csv file), Chip Definition File (CDF file) and probe file as inputs, utilizes the concept of network density cut-off and Fisher's z-test to extract biologically relevant information. It can identify four possible types of gene pairs based on their coexpression relationships. These are (i) gene pair showing coexpression in one condition but not in the other, (ii) gene pair which is positively coexpressed in one condition but negatively coexpressed in the other condition, (iii) positively and (iv) negatively coexpressed in both the conditions. Further, it can generate modules of coexpressed genes. Easy-to-use GUI interface enables researchers without knowledge in R language to use No3CoGP. Utilization of one or more CPU cores, depending on the availability, speeds up the program. The output files stored in the respective directories under the user-defined project offer the researchers to unravel condition-specific functionalities of gene, gene sets or modules.

Design considerations for a roll crusher/splitter for woody biomass

Treesearch

Donald L. Sirois; Colin Ashmore

1986-01-01

The principal focus of biomass harvesting in the past has been the use of chipping systems to reduce a wide variety of woody materials down to small pieces for easier handling and transporting. However, chipping systems have several short comings that limit their operational environments. For example, a conventional chipping system might not be applicable for...

"Chips with Everything": A Laboratory Exercise for Comparing Subjective and Objective Measurements of Potato Chips

ERIC Educational Resources Information Center

Davies, Cathy

2005-01-01

The following laboratory exercise was designed to aid student understanding of the differences between subjective and objective measurements. Students assess the color and texture of different varieties of potato chip (crisps) by means of an intensity rating scale and a rank test and objectively with a colorimeter and texture analyzer. For data…

Architectural-level power estimation and experimentation

NASA Astrophysics Data System (ADS)

Ye, Wu

With the emergence of a plethora of embedded and portable applications and ever increasing integration levels, power dissipation of integrated circuits has moved to the forefront as a design constraint. Recent years have also seen a significant trend towards designs starting at the architectural (or RT) level. Those demand accurate yet fast RT level power estimation methodologies and tools. This thesis addresses issues and experiments associate with architectural level power estimation. An execution driven, cycle-accurate RT level power simulator, SimplePower, was developed using transition-sensitive energy models. It is based on the architecture of a five-stage pipelined RISC datapath for both 0.35mum and 0.8mum technology and can execute the integer subset of the instruction set of SimpleScalar . SimplePower measures the energy consumed in the datapath, memory and on-chip buses. During the development of SimplePower , a partitioning power modeling technique was proposed to model the energy consumed in complex functional units. The accuracy of this technique was validated with HSPICE simulation results for a register file and a shifter. A novel, selectively gated pipeline register optimization technique was proposed to reduce the datapath energy consumption. It uses the decoded control signals to selectively gate the data fields of the pipeline registers. Simulation results show that this technique can reduce the datapath energy consumption by 18--36% for a set of benchmarks. A low-level back-end compiler optimization, register relabeling, was applied to reduce the on-chip instruction cache data bus switch activities. Its impact was evaluated by SimplePower. Results show that it can reduce the energy consumed in the instruction data buses by 3.55--16.90%. A quantitative evaluation was conducted for the impact of six state-of-art high-level compilation techniques on both datapath and memory energy consumption. The experimental results provide a valuable insight for designers to develop future power-aware compilation frameworks for embedded systems.

Method for protecting chip corners in wet chemical etching of wafers

DOEpatents

Hui, Wing C.

1994-01-01

The present invention is a corner protection mask design that protects chip corners from undercutting during anisotropic etching of wafers. The corner protection masks abut the chip corner point and extend laterally from segments along one or both corner sides of the corner point, forming lateral extensions. The protection mask then extends from the lateral extensions, parallel to the direction of the corner side of the chip and parallel to scribe lines, thus conserving wafer space. Unmasked bomb regions strategically formed in the protection mask facilitate the break-up of the protection mask during etching. Corner protection masks are useful for chip patterns with deep grooves and either large or small chip mask areas. Auxiliary protection masks form nested concentric frames that etch from the center outward are useful for small chip mask patterns. The protection masks also form self-aligning chip mask areas. The present invention is advantageous for etching wafers with thin film windows, microfine and micromechanical structures, and for forming chip structures more elaborate than presently possible.

Method for protecting chip corners in wet chemical etching of wafers

DOEpatents

Hui, W.C.

1994-02-15

The present invention is a corner protection mask design that protects chip corners from undercutting during anisotropic etching of wafers. The corner protection masks abut the chip corner point and extend laterally from segments along one or both corner sides of the corner point, forming lateral extensions. The protection mask then extends from the lateral extensions, parallel to the direction of the corner side of the chip and parallel to scribe lines, thus conserving wafer space. Unmasked bomb regions strategically formed in the protection mask facilitate the break-up of the protection mask during etching. Corner protection masks are useful for chip patterns with deep grooves and either large or small chip mask areas. Auxiliary protection masks form nested concentric frames that etch from the center outward are useful for small chip mask patterns. The protection masks also form self-aligning chip mask areas. The present invention is advantageous for etching wafers with thin film windows, microfine and micromechanical structures, and for forming chip structures more elaborate than presently possible. 63 figures.

An area model for on-chip memories and its application

NASA Technical Reports Server (NTRS)

Mulder, Johannes M.; Quach, Nhon T.; Flynn, Michael J.

1991-01-01

An area model suitable for comparing data buffers of different organizations and arbitrary sizes is described. The area model considers the supplied bandwidth of a memory cell and includes such buffer overhead as control logic, driver logic, and tag storage. The model gave less than 10 percent error when verified against real caches and register files. It is shown that, comparing caches and register files in terms of area for the same storage capacity, caches generally occupy more area per bit than register files for small caches because the overhead dominates the cache area at these sizes. For larger caches, the smaller storage cells in the cache provide a smaller total cache area per bit than the register set. Studying cache performance (traffic ratio) as a function of area, it is shown that, for small caches, direct-mapped caches perform significantly better than four-way set-associative caches and, for caches of medium areas, both direct-mapped and set-associative caches perform better than fully associative caches.

A Survey Of Architectural Approaches for Managing Embedded DRAM and Non-volatile On-chip Caches

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mittal, Sparsh; Vetter, Jeffrey S; Li, Dong

Recent trends of CMOS scaling and increasing number of on-chip cores have led to a large increase in the size of on-chip caches. Since SRAM has low density and consumes large amount of leakage power, its use in designing on-chip caches has become more challenging. To address this issue, researchers are exploring the use of several emerging memory technologies, such as embedded DRAM, spin transfer torque RAM, resistive RAM, phase change RAM and domain wall memory. In this paper, we survey the architectural approaches proposed for designing memory systems and, specifically, caches with these emerging memory technologies. To highlight theirmore » similarities and differences, we present a classification of these technologies and architectural approaches based on their key characteristics. We also briefly summarize the challenges in using these technologies for architecting caches. We believe that this survey will help the readers gain insights into the emerging memory device technologies, and their potential use in designing future computing systems.« less

Considerations on Experimental Design and Data Analysis of Chromatin Immunoprecipitation Experiments.

PubMed

Jordán-Pla, Antonio; Visa, Neus

2018-01-01

Arguably one of the most valuable techniques to study chromatin organization, ChIP is the method of choice to map the contacts established between proteins and genomic DNA. Ever since its inception, more than 30 years ago, ChIP has been constantly evolving, improving, and expanding its capabilities and reach. Despite its widespread use by many laboratories across a wide variety of disciplines, ChIP assays can be sometimes challenging to design, and are often sensitive to variations in practical implementation.In this chapter, we provide a general overview of the ChIP method and its most common variations, with a special focus on ChIP-seq. We try to address some of the most important aspects that need to be taken into account in order to design and perform experiments that generate the most reproducible, high-quality data. Some of the main topics covered include the use of properly characterized antibodies, alternatives to chromatin preparation, the need for proper controls, and some recommendations about ChIP-seq data analysis.

Design, development, fabrication and delivery of register and multiplexer units. [CMOS monolithic chip development

NASA Technical Reports Server (NTRS)

Feller, A.; Lombardi, T.

1978-01-01

Several approaches for implementing the register and multiplexer unit into two CMOS monolithic chip types were evaluated. The CMOS standard cell array technique was selected and implemented. Using this design automation technology, two LSI CMOS arrays were designed, fabricated, packaged, and tested for proper static, functional, and dynamic operation. One of the chip types, multiplexer register type 1, is fabricated on a 0.143 x 0.123 inch chip. It uses nine standard cell types for a total of 54 standard cells. This involves more than 350 transistors and has the functional equivalent of 111 gates. The second chip, multiplexer register type 2, is housed on a 0.12 x 0.12 inch die. It uses 13 standard cell types, for a total of 42 standard cells. It contains more than 300 transistors, the functional equivalent of 112 gates. All of the hermetically sealed units were initially screened for proper functional operation. The static leakage and the dynamic leakage were measured. Dynamic measurements were made and recorded. At 10 V, 14 megabit shifting rates were measured on multiplexer register type 1. At 5 V these units shifted data at a 6.6 MHz rate. The units were designed to operate over the 3 to 15 V operating range and over a temperature range of -55 to 125 C.

Thermal-Aware Test Access Mechanism and Wrapper Design Optimization for System-on-Chips

NASA Astrophysics Data System (ADS)

Yu, Thomas Edison; Yoneda, Tomokazu; Chakrabarty, Krishnendu; Fujiwara, Hideo

Rapid advances in semiconductor manufacturing technology have led to higher chip power densities, which places greater emphasis on packaging and temperature control during testing. For system-on-chips, peak power-based scheduling algorithms have been used to optimize tests under specified power constraints. However, imposing power constraints does not always solve the problem of overheating due to the non-uniform distribution of power across the chip. This paper presents a TAM/Wrapper co-design methodology for system-on-chips that ensures thermal safety while still optimizing the test schedule. The method combines a simplified thermal-cost model with a traditional bin-packing algorithm to minimize test time while satisfying temperature constraints. Furthermore, for temperature checking, thermal simulation is done using cycle-accurate power profiles for more realistic results. Experiments show that even a minimal sacrifice in test time can yield a considerable decrease in test temperature as well as the possibility of further lowering temperatures beyond those achieved using traditional power-based test scheduling.

A high-speed on-chip pseudo-random binary sequence generator for multi-tone phase calibration

NASA Astrophysics Data System (ADS)

Gommé, Liesbeth; Vandersteen, Gerd; Rolain, Yves

2011-07-01

An on-chip reference generator is conceived by adopting the technique of decimating a pseudo-random binary sequence (PRBS) signal in parallel sequences. This is of great benefit when high-speed generation of PRBS and PRBS-derived signals is the objective. The design implemented standard CMOS logic is available in commercial libraries to provide the logic functions for the generator. The design allows the user to select the periodicity of the PRBS and the PRBS-derived signals. The characterization of the on-chip generator marks its performance and reveals promising specifications.

Optical and Electric Multifunctional CMOS Image Sensors for On-Chip Biosensing Applications

PubMed Central

Tokuda, Takashi; Noda, Toshihiko; Sasagawa, Kiyotaka; Ohta, Jun

2010-01-01

In this review, the concept, design, performance, and a functional demonstration of multifunctional complementary metal-oxide-semiconductor (CMOS) image sensors dedicated to on-chip biosensing applications are described. We developed a sensor architecture that allows flexible configuration of a sensing pixel array consisting of optical and electric sensing pixels, and designed multifunctional CMOS image sensors that can sense light intensity and electric potential or apply a voltage to an on-chip measurement target. We describe the sensors’ architecture on the basis of the type of electric measurement or imaging functionalities. PMID:28879978

Development of a versatile lab-on-a-chip enzyme assay platform for pathogen detection in CBRNE scenarios

NASA Astrophysics Data System (ADS)

Klemm, Richard; Schattschneider, Sebastian; Jahn, Tobias; Hlawatsch, Nadine; Julich, Sandra; Becker, Holger; Gärtner, Claudia

2013-05-01

The ability to integrate complete assays on a microfluidic chip helps to greatly simplify instrument requirements and allows the use of lab-on-a-chip technology in the field. A core application for such field-portable systems is the detection of pathogens in a CBRNE scenario such as permanent monitoring of airborne pathogens, e.g. in metro stations or hospitals etc. As one assay methodology for the pathogen identification, enzymatic assays were chosen. In order evaluate different detection strategies, the realized on-chip enzyme assay module has been designed as a general platform chip. In all application cases, the assays are based on immobilized probes located in microfluidic channels. Therefore a microfluidic chip was realized containing a set of three individually addressable channels, not only for detection of the sample itself also to have a set of references for a quantitative analysis. It furthermore includes two turning valves and a waste container for clear and sealed storage of potential pathogenic liquids to avoid contamination of the environment. All liquids remain in the chip and can be disposed of in proper way subsequently to the analysis. The chip design includes four inlet ports consisting of one sample port (Luer interface) and three mini Luer interfaces for fluidic support of e.g. washing buffer, substrate and enzyme solution. The sample can be applied via a special, sealable sampling vessel with integrated female Luer interface. Thereby also pre-anaytical contamination of the environment can be provided. Other reagents that are required for analysis will be stored off chip.

CMOS array design automation techniques

NASA Technical Reports Server (NTRS)

Lombardi, T.; Feller, A.

1976-01-01

The design considerations and the circuit development for a 4096-bit CMOS SOS ROM chip, the ATL078 are described. Organization of the ATL078 is 512 words by 8 bits. The ROM was designed to be programmable either at the metal mask level or by a directed laser beam after processing. The development of a 4K CMOS SOS ROM fills a void left by available ROM chip types, and makes the design of a totally major high speed system more realizable.

Lab-on-a-Chip Design-Build Project with a Nanotechnology Component in a Freshman Engineering Course

ERIC Educational Resources Information Center

Allam, Yosef; Tomasko, David L.; Trott, Bruce; Schlosser, Phil; Yang, Yong; Wilson, Tiffany M.; Merrill, John

2008-01-01

A micromanufacturing lab-on-a-chip project with a nanotechnology component was introduced as an alternate laboratory in the required first-year engineering curriculum at The Ohio State University. Nanotechnology is introduced in related reading and laboratory tours as well as laboratory activities including a quarter-length design, build, and test…

Netlist Oriented Sensitivity Evaluation (NOSE)

DTIC Science & Technology

2017-03-01

developing methodologies to assess sensitivities of alternative chip design netlist implementations. The research is somewhat foundational in that such...Netlist-Oriented Sensitivity Evaluation (NOSE) project was to develop methodologies to assess sensitivities of alternative chip design netlist...analysis to devise a methodology for scoring the sensitivity of circuit nodes in a netlist and thus providing the raw data for any meaningful

A 5.2/5.8 GHz Dual Band On-Off Keying Transmitter Design for Bio-Signal Transmission

NASA Astrophysics Data System (ADS)

Wu, Chang-Hsi; You, Hong-Cheng; Huang, Shun-Zhao

2018-02-01

An architecture of 5.2/5.8-GHz dual-band on-off keying (DBOOK) modulated transmitter is designed in a 0.18-μm CMOS technology. The proposed DBOOK transmitter is used in the biosignal transmission system with high power efficiency and small area. To reduce power consumption and enhance output swing, two pairs of center-tapped transformers are used as both LC tank and source grounding choke for the designed voltage controlled oscillator (VCO). Switching capacitances are used to achieve dual band operations, and a complemented power combiner is used to merge the differential output power of VCO to a single-ended output. Besides, the linearizer circuits are used in the proposed power amplifier with wideband output matching to improve the linearity both at 5.2/5.8-GHz bands. The designed DBOOK transmitter is implemented by dividing it into two chips. One chip implements the dual-band switching VCO and power combiner, and the other chip implements a linear power amplifier including dual-band operation. The first chip drives an output power of 2.2mW with consuming power of 5.13 mW from 1.1 V supply voltage. With the chip size including pad of 0.61 × 0.91 m2, the measured data rate and transmission efficiency attained are 100 Mb/s and 51 pJ/bit, respectively. The second chip, for power enhanced mode, exhibits P1 dB of -9 dBm, IIP3 of 1 dBm, the output power 1 dB compression point of 12.42 dBm, OIP3 of about 21 dBm, maximum output power of 17.02/16.18 dBm, and power added efficiency of 17.13/16.95% for 5.2/ 5.8 GHz. The chip size including pads is 0:693 × 1:084mm2.

Design and process development of a photonic crystal polymer biosensor for point-of-care diagnostics

NASA Astrophysics Data System (ADS)

Dortu, F.; Egger, H.; Kolari, K.; Haatainen, T.; Furjes, P.; Fekete, Z.; Bernier, D.; Sharp, G.; Lahiri, B.; Kurunczi, S.; Sanchez, J.-C.; Turck, N.; Petrik, P.; Patko, D.; Horvath, R.; Eiden, S.; Aalto, T.; Watts, S.; Johnson, N. P.; De La Rue, R. M.; Giannone, D.

2011-07-01

In this work, we report advances in the fabrication and anticipated performance of a polymer biosensor photonic chip developed in the European Union project P3SENS (FP7-ICT4-248304). Due to the low cost requirements of point-ofcare applications, the photonic chip is fabricated from nanocomposite polymeric materials, using highly scalable nanoimprint- lithography (NIL). A suitable microfluidic structure transporting the analyte solutions to the sensor area is also fabricated in polymer and adequately bonded to the photonic chip. We first discuss the design and the simulated performance of a high-Q resonant cavity photonic crystal sensor made of a high refractive index polyimide core waveguide on a low index polymer cladding. We then report the advances in doped and undoped polymer thin film processing and characterization for fabricating the photonic sensor chip. Finally the development of the microfluidic chip is presented in details, including the characterisation of the fluidic behaviour, the technological and material aspects of the 3D polymer structuring and the stable adhesion strategies for bonding the fluidic and the photonic chips, with regards to the constraints imposed by the bioreceptors supposedly already present on the sensors.

Chip-scale thermal management of high-brightness LED packages

NASA Astrophysics Data System (ADS)

Arik, Mehmet; Weaver, Stanton

2004-10-01

The efficiency and reliability of the solid-state lighting devices strongly depend on successful thermal management. Light emitting diodes, LEDs, are a strong candidate for the next generation, general illumination applications. LEDs are making great strides in terms of lumen performance and reliability, however the barrier to widespread use in general illumination still remains the cost or $/Lumen. LED packaging designers are pushing the LED performance to its limits. This is resulting in increased drive currents, and thus the need for lower thermal resistance packaging designs. As the power density continues to rise, the integrity of the package electrical and thermal interconnect becomes extremely important. Experimental results with high brightness LED packages show that chip attachment defects can cause significant thermal gradients across the LED chips leading to premature failures. A numerical study was also carried out with parametric models to understand the chip active layer temperature profile variation due to the bump defects. Finite element techniques were utilized to evaluate the effects of localized hot spots at the chip active layer. The importance of "zero defects" in one of the more popular interconnect schemes; the "epi down" soldered flip chip configuration is investigated and demonstrated.

Chip seal performance measures : best practices.

DOT National Transportation Integrated Search

2015-03-01

The Washington State Department of Transportation (WSDOT) has a long history of designing, constructing, : and maintaining chip seal or bituminous surface treatment pavements. However, to date WSDOT has not : developed pavement performance indicators...

Compact Multimedia Systems in Multi-chip Module Technology

NASA Technical Reports Server (NTRS)

Fang, Wai-Chi; Alkalaj, Leon

1995-01-01

This tutorial paper shows advanced multimedia system designs based on multi-chip module (MCM) technologies that provide essential computing, compression, communication, and storage capabilities for various large scale information highway applications.!.

"Peak tracking chip" for label-free optical detection of bio-molecular interaction and bulk sensing.

PubMed

Bougot-Robin, Kristelle; Li, Shunbo; Zhang, Yinghua; Hsing, I-Ming; Benisty, Henri; Wen, Weijia

2012-10-21

A novel imaging method for bulk refractive index sensing or label-free bio-molecular interaction sensing is presented. This method is based on specially designed "Peak tracking chip" (PTC) involving "tracks" of adjacent resonant waveguide gratings (RWG) "micropads" with slowly evolving resonance position. Using a simple camera the spatial information robustly retrieves the diffraction efficiency, which in turn transduces either the refractive index of the liquids on the tracks or the effective thickness of an immobilized biological layer. Our intrinsically multiplex chip combines tunability and versatility advantages of dielectric guided wave biochips without the need of costly hyperspectral instrumentation. The current success of surface plasmon imaging techniques suggests that our chip proposal could leverage an untapped potential to routinely extend such techniques in a convenient and sturdy optical configuration toward, for instance for large analytes detection. PTC design and fabrication are discussed with challenging process to control micropads properties by varying their period (step of 2 nm) or their duty cycle through the groove width (steps of 4 nm). Through monochromatic imaging of our PTC, we present experimental demonstration of bulk index sensing on the range [1.33-1.47] and of surface biomolecule detection of molecular weight 30 kDa in aqueous solution using different surface densities. A sensitivity of the order of 10(-5) RIU for bulk detection and a sensitivity of the order of ∼10 pg mm(-2) for label-free surface detection are expected, therefore opening a large range of application of our chip based imaging technique. Exploiting and chip design, we expect as well our chip to open new direction for multispectral studies through imaging.

1H, 15N and 13C resonance assignments for free and IEEVD peptide-bound forms of the tetratricopeptide repeat domain from the human E3 ubiquitin ligase CHIP.

PubMed

Zhang, Huaqun; McGlone, Cameron; Mannion, Matthew M; Page, Richard C

2017-04-01

The ubiquitin ligase CHIP catalyzes covalent attachment of ubiquitin to unfolded proteins chaperoned by the heat shock proteins Hsp70/Hsc70 and Hsp90. CHIP interacts with Hsp70/Hsc70 and Hsp90 by binding of a C-terminal IEEVD motif found in Hsp70/Hsc70 and Hsp90 to the tetratricopeptide repeat (TPR) domain of CHIP. Although recruitment of heat shock proteins to CHIP via interaction with the CHIP-TPR domain is well established, alterations in structure and dynamics of CHIP upon binding are not well understood. In particular, the absence of a structure for CHIP-TPR in the free form presents a significant limitation upon studies seeking to rationally design inhibitors that may disrupt interactions between CHIP and heat shock proteins. Here we report the 1 H, 13 C, and 15 N backbone and side chain chemical shift assignments for CHIP-TPR in the free form, and backbone chemical shift assignments for CHIP-TPR in the IEEVD-bound form. The NMR resonance assignments will enable further studies examining the roles of dynamics and structure in regulating interactions between CHIP and the heat shock proteins Hsp70/Hsc70 and Hsp90.

Novel immunoassay formats for integrated microfluidic circuits: diffusion immunoassays (DIA)

NASA Astrophysics Data System (ADS)

Weigl, Bernhard H.; Hatch, Anson; Kamholz, Andrew E.; Yager, Paul

2000-03-01

Novel designs of integrated fluidic microchips allow separations, chemical reactions, and calibration-free analytical measurements to be performed directly in very small quantities of complex samples such as whole blood and contaminated environmental samples. This technology lends itself to applications such as clinical diagnostics, including tumor marker screening, and environmental sensing in remote locations. Lab-on-a-Chip based systems offer many *advantages over traditional analytical devices: They consume extremely low volumes of both samples and reagents. Each chip is inexpensive and small. The sampling-to-result time is extremely short. They perform all analytical functions, including sampling, sample pretreatment, separation, dilution, and mixing steps, chemical reactions, and detection in an integrated microfluidic circuit. Lab-on-a-Chip systems enable the design of small, portable, rugged, low-cost, easy to use, yet extremely versatile and capable diagnostic instruments. In addition, fluids flowing in microchannels exhibit unique characteristics ('microfluidics'), which allow the design of analytical devices and assay formats that would not function on a macroscale. Existing Lab-on-a-chip technologies work very well for highly predictable and homogeneous samples common in genetic testing and drug discovery processes. One of the biggest challenges for current Labs-on-a-chip, however, is to perform analysis in the presence of the complexity and heterogeneity of actual samples such as whole blood or contaminated environmental samples. Micronics has developed a variety of Lab-on-a-Chip assays that can overcome those shortcomings. We will now present various types of novel Lab- on-a-Chip-based immunoassays, including the so-called Diffusion Immunoassays (DIA) that are based on the competitive laminar diffusion of analyte molecules and tracer molecules into a region of the chip containing antibodies that target the analyte molecules. Advantages of this technique are a reduction in reagents, higher sensitivity, minimal preparation of complex samples such as blood, real-time calibration, and extremely rapid analysis.

A Fully Integrated Humidity Sensor System-on-Chip Fabricated by Micro-Stamping Technology

PubMed Central

Huang, Che-Wei; Huang, Yu-Jie; Lu, Shey-Shi; Lin, Chih-Ting

2012-01-01

A fully integrated humidity sensor chip was designed, implemented, and tested. Utilizing the micro-stamping technology, the pseudo-3D sensor system-on-chip (SSoC) architecture can be implemented by stacking sensing materials directly on the top of a CMOS-fabricated chip. The fabricated sensor system-on-chip (2.28 mm × 2.48 mm) integrated a humidity sensor, an interface circuit, a digital controller, and an On-Off Keying (OOK) wireless transceiver. With low power consumption, i.e., 750 μW without RF operation, the sensitivity of developed sensor chip was experimentally verified in the relative humidity (RH) range from 32% to 60%. The response time of the chip was also experimentally verified to be within 5 seconds from RH 36% to RH 64%. As a consequence, the implemented humidity SSoC paves the way toward the an ultra-small sensor system for various applications.

An ultra-low power CMOS image sensor with on-chip energy harvesting and power management capability.

PubMed

Cevik, Ismail; Huang, Xiwei; Yu, Hao; Yan, Mei; Ay, Suat U

2015-03-06

An ultra-low power CMOS image sensor with on-chip energy harvesting and power management capability is introduced in this paper. The photodiode pixel array can not only capture images but also harvest solar energy. As such, the CMOS image sensor chip is able to switch between imaging and harvesting modes towards self-power operation. Moreover, an on-chip maximum power point tracking (MPPT)-based power management system (PMS) is designed for the dual-mode image sensor to further improve the energy efficiency. A new isolated P-well energy harvesting and imaging (EHI) pixel with very high fill factor is introduced. Several ultra-low power design techniques such as reset and select boosting techniques have been utilized to maintain a wide pixel dynamic range. The chip was designed and fabricated in a 1.8 V, 1P6M 0.18 µm CMOS process. Total power consumption of the imager is 6.53 µW for a 96 × 96 pixel array with 1 V supply and 5 fps frame rate. Up to 30 μW of power could be generated by the new EHI pixels. The PMS is capable of providing 3× the power required during imaging mode with 50% efficiency allowing energy autonomous operation with a 72.5% duty cycle.

Sensing systems using chip-based spectrometers

NASA Astrophysics Data System (ADS)

Nitkowski, Arthur; Preston, Kyle J.; Sherwood-Droz, Nicolás.; Behr, Bradford B.; Bismilla, Yusuf; Cenko, Andrew T.; DesRoches, Brandon; Meade, Jeffrey T.; Munro, Elizabeth A.; Slaa, Jared; Schmidt, Bradley S.; Hajian, Arsen R.

2014-06-01

Tornado Spectral Systems has developed a new chip-based spectrometer called OCTANE, the Optical Coherence Tomography Advanced Nanophotonic Engine, built using a planar lightwave circuit with integrated waveguides fabricated on a silicon wafer. While designed for spectral domain optical coherence tomography (SD-OCT) systems, the same miniaturized technology can be applied to many other spectroscopic applications. The field of integrated optics enables the design of complex optical systems which are monolithically integrated on silicon chips. The form factors of these systems can be significantly smaller, more robust and less expensive than their equivalent free-space counterparts. Fabrication techniques and material systems developed for microelectronics have previously been adapted for integrated optics in the telecom industry, where millions of chip-based components are used to power the optical backbone of the internet. We have further adapted the photonic technology platform for spectroscopy applications, allowing unheard-of economies of scale for these types of optical devices. Instead of changing lenses and aligning systems, these devices are accurately designed programmatically and are easily customized for specific applications. Spectrometers using integrated optics have large advantages in systems where size, robustness and cost matter: field-deployable devices, UAVs, UUVs, satellites, handheld scanning and more. We will discuss the performance characteristics of our chip-based spectrometers and the type of spectral sensing applications enabled by this technology.

An Ultra-Low Power CMOS Image Sensor with On-Chip Energy Harvesting and Power Management Capability

PubMed Central

Cevik, Ismail; Huang, Xiwei; Yu, Hao; Yan, Mei; Ay, Suat U.

2015-01-01

An ultra-low power CMOS image sensor with on-chip energy harvesting and power management capability is introduced in this paper. The photodiode pixel array can not only capture images but also harvest solar energy. As such, the CMOS image sensor chip is able to switch between imaging and harvesting modes towards self-power operation. Moreover, an on-chip maximum power point tracking (MPPT)-based power management system (PMS) is designed for the dual-mode image sensor to further improve the energy efficiency. A new isolated P-well energy harvesting and imaging (EHI) pixel with very high fill factor is introduced. Several ultra-low power design techniques such as reset and select boosting techniques have been utilized to maintain a wide pixel dynamic range. The chip was designed and fabricated in a 1.8 V, 1P6M 0.18 µm CMOS process. Total power consumption of the imager is 6.53 µW for a 96 × 96 pixel array with 1 V supply and 5 fps frame rate. Up to 30 μW of power could be generated by the new EHI pixels. The PMS is capable of providing 3× the power required during imaging mode with 50% efficiency allowing energy autonomous operation with a 72.5% duty cycle. PMID:25756863

Around Marshall

NASA Image and Video Library

2003-12-01

Helen Cole, the project manager for the Lab-on-a-Chip Applications Development program, and Lisa Monaco, the project scientist for the program, insert a lab on a chip into the Caliper 42 which is specialized equipment that controls processes on commercial chips to support development of lab-on-a-chip applications. The system has special microscopes and imaging systems, so scientists can process and study different types of fluid, chemical, and medical tests conducted on chips. For example, researchers have examined fluorescent bacteria as it flows through the chips' fluid channels or microfluidic capillaries. Researchers at NASA's Marshall Space Flight Center (MSFC) in Huntsville, Alabama, have been studying how the lab-on-a-chip technology can be used for microbial detection, water quality monitoring, and detecting biosignatures of past or present life on Mars. The Marshall Center team is also collaborating with scientists at other NASA centers and at universities to develop custom chip designs for not only space applications, but for many Earth applications, such as for detecting deadly microbes in heating and air systems. (NASA/MSFC/D.Stoffer)

Transportable GPU (General Processor Units) chip set technology for standard computer architectures

NASA Astrophysics Data System (ADS)

Fosdick, R. E.; Denison, H. C.

1982-11-01

The USAFR-developed GPU Chip Set has been utilized by Tracor to implement both USAF and Navy Standard 16-Bit Airborne Computer Architectures. Both configurations are currently being delivered into DOD full-scale development programs. Leadless Hermetic Chip Carrier packaging has facilitated implementation of both architectures on single 41/2 x 5 substrates. The CMOS and CMOS/SOS implementations of the GPU Chip Set have allowed both CPU implementations to use less than 3 watts of power each. Recent efforts by Tracor for USAF have included the definition of a next-generation GPU Chip Set that will retain the application-proven architecture of the current chip set while offering the added cost advantages of transportability across ISO-CMOS and CMOS/SOS processes and across numerous semiconductor manufacturers using a newly-defined set of common design rules. The Enhanced GPU Chip Set will increase speed by an approximate factor of 3 while significantly reducing chip counts and costs of standard CPU implementations.

Three dimensional, multi-chip module

DOEpatents

Bernhardt, A.F.; Petersen, R.W.

1993-08-31

A plurality of multi-chip modules are stacked and bonded around the perimeter by sold-bump bonds to adjacent modules on, for instance, three sides of the perimeter. The fourth side can be used for coolant distribution, for more interconnect structures, or other features, depending on particular design considerations of the chip set. The multi-chip modules comprise a circuit board, having a planarized interconnect structure formed on a first major surface, and integrated circuit chips bonded to the planarized interconnect surface. Around the periphery of each circuit board, long, narrow dummy chips'' are bonded to the finished circuit board to form a perimeter wall. The wall is higher than any of the chips on the circuit board, so that the flat back surface of the board above will only touch the perimeter wall. Module-to-module interconnect is laser-patterned on the sides of the boards and over the perimeter wall in the same way and at the same time that chip to board interconnect may be laser-patterned.

Three dimensional, multi-chip module

DOEpatents

Bernhardt, Anthony F.; Petersen, Robert W.

1993-01-01

A plurality of multi-chip modules are stacked and bonded around the perimeter by sold-bump bonds to adjacent modules on, for instance, three sides of the perimeter. The fourth side can be used for coolant distribution, for more interconnect structures, or other features, depending on particular design considerations of the chip set. The multi-chip modules comprise a circuit board, having a planarized interconnect structure formed on a first major surface, and integrated circuit chips bonded to the planarized interconnect surface. Around the periphery of each circuit board, long, narrow "dummy chips" are bonded to the finished circuit board to form a perimeter wall. The wall is higher than any of the chips on the circuit board, so that the flat back surface of the board above will only touch the perimeter wall. Module-to-module interconnect is laser-patterned o the sides of the boards and over the perimeter wall in the same way and at the same time that chip to board interconnect may be laser-patterned.

Spectral Demultiplexing in Holographic and Fluorescent On-chip Microscopy

NASA Astrophysics Data System (ADS)

Sencan, Ikbal; Coskun, Ahmet F.; Sikora, Uzair; Ozcan, Aydogan

2014-01-01

Lensfree on-chip imaging and sensing platforms provide compact and cost-effective designs for various telemedicine and lab-on-a-chip applications. In this work, we demonstrate computational solutions for some of the challenges associated with (i) the use of broadband, partially-coherent illumination sources for on-chip holographic imaging, and (ii) multicolor detection for lensfree fluorescent on-chip microscopy. Specifically, we introduce spectral demultiplexing approaches that aim to digitally narrow the spectral content of broadband illumination sources (such as wide-band light emitting diodes or even sunlight) to improve spatial resolution in holographic on-chip microscopy. We also demonstrate the application of such spectral demultiplexing approaches for wide-field imaging of multicolor fluorescent objects on a chip. These computational approaches can be used to replace e.g., thin-film interference filters, gratings or other optical components used for spectral multiplexing/demultiplexing, which can form a desirable solution for cost-effective and compact wide-field microscopy and sensing needs on a chip.

[An integral chip for the multiphase pulse-duration modulation used for voltage changer in biomedical microprocessor systems].

PubMed

Balashov, A M; Selishchev, S V

2004-01-01

An integral chip (IC) was designed for controlling the step-down pulse voltage converter, which is based on the multiphase pulse-duration modulation, for use in biomedical microprocessor systems. The CMOS technology was an optimal basis for the IC designing. An additional feedback circuit diminishes the output voltage dispersion at dynamically changing loads.

Isolation of circulating tumor cells using a microvortex-generating herringbone-chip.

PubMed

Stott, Shannon L; Hsu, Chia-Hsien; Tsukrov, Dina I; Yu, Min; Miyamoto, David T; Waltman, Belinda A; Rothenberg, S Michael; Shah, Ajay M; Smas, Malgorzata E; Korir, George K; Floyd, Frederick P; Gilman, Anna J; Lord, Jenna B; Winokur, Daniel; Springer, Simeon; Irimia, Daniel; Nagrath, Sunitha; Sequist, Lecia V; Lee, Richard J; Isselbacher, Kurt J; Maheswaran, Shyamala; Haber, Daniel A; Toner, Mehmet

2010-10-26

Rare circulating tumor cells (CTCs) present in the bloodstream of patients with cancer provide a potentially accessible source for detection, characterization, and monitoring of nonhematological cancers. We previously demonstrated the effectiveness of a microfluidic device, the CTC-Chip, in capturing these epithelial cell adhesion molecule (EpCAM)-expressing cells using antibody-coated microposts. Here, we describe a high-throughput microfluidic mixing device, the herringbone-chip, or "HB-Chip," which provides an enhanced platform for CTC isolation. The HB-Chip design applies passive mixing of blood cells through the generation of microvortices to significantly increase the number of interactions between target CTCs and the antibody-coated chip surface. Efficient cell capture was validated using defined numbers of cancer cells spiked into control blood, and clinical utility was demonstrated in specimens from patients with prostate cancer. CTCs were detected in 14 of 15 (93%) patients with metastatic disease (median = 63 CTCs/mL, mean = 386 ± 238 CTCs/mL), and the tumor-specific TMPRSS2-ERG translocation was readily identified following RNA isolation and RT-PCR analysis. The use of transparent materials allowed for imaging of the captured CTCs using standard clinical histopathological stains, in addition to immunofluorescence-conjugated antibodies. In a subset of patient samples, the low shear design of the HB-Chip revealed microclusters of CTCs, previously unappreciated tumor cell aggregates that may contribute to the hematogenous dissemination of cancer.

Design and fabrication of a micron scale free-standing specimen for uniaxial micro-tensile tests

NASA Astrophysics Data System (ADS)

Tang, Jun; Wang, Hong; Li, Shi Chen; Liu, Rui; Mao, Sheng Ping; Li, Xue Ping; Zhang, Cong Chun; Ding, Guifu

2009-10-01

This paper presents a novel design and fabrication of test chips with a nickel free-standing specimen for the micro uniaxial tensile test. To fabricate test chips on the quartz substrate significantly reduces the fabrication time, minimizes the number of steps and eliminates the effect of the wet anisotropic etching process on mechanical properties. The test chip can be gripped tightly to the test machine and aligned accurately in the pulling direction; furthermore, the approximately straight design of the specimen rather than the traditional dog-bone structure enables the strain be directly measured by a displacement sensor. Both finite-element method (FEM) analysis and experimental results indicate the reliability of the new design. The test chip can also be extended to other materials. The experimental measured Young's modulus of a thin nickel film and the ultimate tensile strength are approximately 94.5 Gpa and 1.76 Gpa, respectively. The results were substantially supported by the experiment on larger gauge specimens by a commercial dynamic mechanical analysis (DMA) instrument. These specimens were electroplated under the same conditions. The low Young's modulus and the high ultimate tensile strength might be explained by the fine grain in the electroplated structure.

GeneChip{sup {trademark}} screening assay for cystic fibrosis mutations

DOE Office of Scientific and Technical Information (OSTI.GOV)

Cronn, M.T.; Miyada, C.G.; Fucini, R.V.

1994-09-01

GeneChip{sup {trademark}} assays are based on high density, carefully designed arrays of short oligonucleotide probes (13-16 bases) built directly on derivatized silica substrates. DNA target sequence analysis is achieved by hybridizing fluorescently labeled amplification products to these arrays. Fluorescent hybridization signals located within the probe array are translated into target sequence information using the known probe sequence at each array feature. The mutation screening assay for cystic fibrosis includes sets of oligonucleotide probes designed to detect numerous different mutations that have been described in 14 exons and one intron of the CFTR gene. Each mutation site is addressed by amore » sub-array of at least 40 probe sequences, half designed to detect the wild type gene sequence and half designed to detect the reported mutant sequence. Hybridization with homozygous mutant, homozygous wild type or heterozygous targets results in distinctive hybridization patterns within a sub-array, permitting specific discrimination of each mutation. The GeneChip probe arrays are very small (approximately 1 cm{sup 2}). There miniature size coupled with their high information content make GeneChip probe arrays a useful and practical means for providing CF mutation analysis in a clinical setting.« less

Design, processing and testing of LSI arrays, hybrid microelectronics task

NASA Technical Reports Server (NTRS)

Himmel, R. P.; Stuhlbarg, S. M.; Ravetti, R. G.; Zulueta, P. J.; Rothrock, C. W.

1979-01-01

Mathematical cost models previously developed for hybrid microelectronic subsystems were refined and expanded. Rework terms related to substrate fabrication, nonrecurring developmental and manufacturing operations, and prototype production are included. Sample computer programs were written to demonstrate hybrid microelectric applications of these cost models. Computer programs were generated to calculate and analyze values for the total microelectronics costs. Large scale integrated (LST) chips utilizing tape chip carrier technology were studied. The feasibility of interconnecting arrays of LSU chips utilizing tape chip carrier and semiautomatic wire bonding technology was demonstrated.

EPE fundamentals and impact of EUV: Will traditional design-rule calculations work in the era of EUV?

NASA Astrophysics Data System (ADS)

Gabor, Allen H.; Brendler, Andrew C.; Brunner, Timothy A.; Chen, Xuemei; Culp, James A.; Levinson, Harry J.

2018-03-01

The relationship between edge placement error, semiconductor design-rule determination and predicted yield in the era of EUV lithography is examined. This paper starts with the basics of edge placement error and then builds up to design-rule calculations. We show that edge placement error (EPE) definitions can be used as the building blocks for design-rule equations but that in the last several years the term "EPE" has been used in the literature to refer to many patterning errors that are not EPE. We then explore the concept of "Good Fields"1 and use it predict the n-sigma value needed for design-rule determination. Specifically, fundamental yield calculations based on the failure opportunities per chip are used to determine at what n-sigma "value" design-rules need to be tested to ensure high yield. The "value" can be a space between two features, an intersect area between two features, a minimum area of a feature, etc. It is shown that across chip variation of design-rule important values needs to be tested at sigma values between seven and eight which is much higher than the four-sigma values traditionally used for design-rule determination. After recommending new statistics be used for design-rule calculations the paper examines the impact of EUV lithography on sources of variation important for design-rule calculations. We show that stochastics can be treated as an effective dose variation that is fully sampled across every chip. Combining the increased within chip variation from EUV with the understanding that across chip variation of design-rule important values needs to not cause a yield loss at significantly higher sigma values than have traditionally been looked at, the conclusion is reached that across-wafer, wafer-to-wafer and lot-to-lot variation will have to overscale for any technology introducing EUV lithography where stochastic noise is a significant fraction of the effective dose variation. We will emphasize stochastic effects on edge placement error distributions and appropriate design-rule setting. While CD distributions with long tails coming from stochastic effects do bring increased risk of failure (especially on chips that may have over a billion failure opportunities per layer) there are other sources of variation that have sharp cutoffs, i.e. have no tails. We will review these sources and show how distributions with different skew and kurtosis values combine.

Slow Controls Using the Axiom M5235BCC

NASA Astrophysics Data System (ADS)

Hague, Tyler

2008-10-01

The Forward Vertex Detector group at PHENIX plans to adopt the Axiom M5235 Business Card Controller for use as slow controls. It is also being evaluated for slow controls on FermiLab e906. This controller features the Freescale MCF5235 microprocessor. It also has three parallel buses, these being the MCU port, BUS port, and enhanced Time Processing Unit (eTPU) port. The BUS port uses a chip select module with three external chip selects to communicate with peripherals. This will be used to communicate with and configure Field Programmable Gate Arrays (FPGAs). The controller also has an Ethernet port which can use several different protocols such as TCP and UDP. This will be used to transfer files with computers on a network. The M5235 Business Card Controller will be placed in a VME crate along with VME card and a Spartan-3 FPGA.

HPLC-Chip/MS Technology in Proteomic Profiling

NASA Astrophysics Data System (ADS)

Vollmer, Martin; van de Goor, Tom

HPLC-chip/MS is a novel nanoflow analytical technology conducted on a microfabricated chip that allows for highly efficient HPLC separation and superior sensitive MS detection of complex proteomic mixtures. This is possible through on-chip preconcentration and separation with fluidic connection made automatically in a leak-tight fashion. Minimum precolumn and postcolumn peak dispersion and uncompromised ease of use result in compounds eluting in bands of only a few nanoliters. The chip is fabricated out of bio-inert polyimide-containing channels and integrated chip structures, such as an electrospray emitter, columns, and frits manufactured by laser ablation technology. Meanwhile, a variety of HPLC-chips differing in design and stationary phase are commercially available, which provide a comprehensive solution for applications in proteomics, glycomics, biomarker, and pharmaceutical discovery. The HPLC-chip can also be easily integrated into a multidimensional separation workflow where different orthogonal separation techniques are combined to solve a highly complex separation problems. In this chapter, we describe in detail the methodological chip usage and functionality and its application in the elucidation of the protein profile of human nucleoli.

Lab-on a-Chip

NASA Technical Reports Server (NTRS)

2003-01-01

Helen Cole, the project manager for the Lab-on-a-Chip Applications Development program, and Lisa Monaco, the project scientist for the program, insert a lab on a chip into the Caliper 42 which is specialized equipment that controls processes on commercial chips to support development of lab-on-a-chip applications. The system has special microscopes and imaging systems, so scientists can process and study different types of fluid, chemical, and medical tests conducted on chips. For example, researchers have examined fluorescent bacteria as it flows through the chips' fluid channels or microfluidic capillaries. Researchers at NASA's Marshall Space Flight Center (MSFC) in Huntsville, Alabama, have been studying how the lab-on-a-chip technology can be used for microbial detection, water quality monitoring, and detecting biosignatures of past or present life on Mars. The Marshall Center team is also collaborating with scientists at other NASA centers and at universities to develop custom chip designs for not only space applications, but for many Earth applications, such as for detecting deadly microbes in heating and air systems. (NASA/MSFC/D.Stoffer)

Complete data preparation flow for Massively Parallel E-Beam lithography on 28nm node full-field design

NASA Astrophysics Data System (ADS)

Fay, Aurélien; Browning, Clyde; Brandt, Pieter; Chartoire, Jacky; Bérard-Bergery, Sébastien; Hazart, Jérôme; Chagoya, Alexandre; Postnikov, Sergei; Saib, Mohamed; Lattard, Ludovic; Schavione, Patrick

2016-03-01

Massively parallel mask-less electron beam lithography (MP-EBL) offers a large intrinsic flexibility at a low cost of ownership in comparison to conventional optical lithography tools. This attractive direct-write technique needs a dedicated data preparation flow to correct both electronic and resist processes. Moreover, Data Prep has to be completed in a short enough time to preserve the flexibility advantage of MP-EBL. While the MP-EBL tools have currently entered an advanced stage of development, this paper will focus on the data preparation side of the work for specifically the MAPPER Lithography FLX-1200 tool [1]-[4], using the ASELTA Nanographics Inscale software. The complete flow as well as the methodology used to achieve a full-field layout data preparation, within an acceptable cycle time, will be presented. Layout used for Data Prep evaluation was one of a 28 nm technology node Metal1 chip with a field size of 26x33mm2, compatible with typical stepper/scanner field sizes and wafer stepping plans. Proximity Effect Correction (PEC) was applied to the entire field, which was then exported as a single file to MAPPER Lithography's machine format, containing fractured shapes and dose assignments. The Soft Edge beam to beam stitching method was employed in the specific overlap regions defined by the machine format as well. In addition to PEC, verification of the correction was included as part of the overall data preparation cycle time. This verification step was executed on the machine file format to ensure pattern fidelity and accuracy as late in the flow as possible. Verification over the full chip, involving billions of evaluation points, is performed both at nominal conditions and at Process Window corners in order to ensure proper exposure and process latitude. The complete MP-EBL data preparation flow was demonstrated for a 28 nm node Metal1 layout in 37 hours. The final verification step shows that the Edge Placement Error (EPE) is kept below 2.25 nm over an exposure dose variation of 8%.

Analysis of Photonic Networks for a Chip Multiprocessor Using Scientific Applications

DTIC Science & Technology

2009-05-01

Analysis of Photonic Networks for a Chip Multiprocessor Using Scientific Applications Gilbert Hendry†, Shoaib Kamil‡?, Aleksandr Biberman†, Johnnie...electronic networks -on-chip warrants investigating real application traces on functionally compa- rable photonic and electronic network designs. We... network can achieve 75× improvement in energy ef- ficiency for synthetic benchmarks and up to 37× improve- ment for real scientific applications

An ultra-compact and low-power oven-controlled crystal oscillator design for precision timing applications.

PubMed

Lim, Jaehyun; Kim, Hyunsoo; Jackson, Thomas; Choi, Kyusun; Kenny, David

2010-09-01

A novel design for a chip-scale miniature oven-controlled crystal oscillator (OCXO) is presented. In this design, all the main components of an OCXO--consisting of an oscillator, a temperature sensor, a heater, and temperature-control circuitry--are integrated on a single CMOS chip. The OCXO package size can be reduced significantly with this design, because the resonator does not require a separate package and most of the circuitry is integrated on a single CMOS chip. Other characteristics such as power consumption and warm-up time are also improved. Two different types of quartz resonators, an AT-cut tab mesa-type quartz crystal and a frame enclosed resonator, allow miniaturization of the OCXO structure. Neither of these quartz resonator types requires a separate package inside the oven structure; therefore, they can each be directly integrated with the custom-designed CMOS chip. The miniature OCXO achieves a frequency stability of +/- 0.35 ppm with an AT-cut tab mesa-type quartz crystal in the temperature range of 0 °C to 60 °C. The maximum power consumption of this miniature OCXO is 1.2 W at start-up and 303 mW at steady state. The warm-up time to reach the steady state is 190 s. These results using the proposed design are better than or the same as high-frequency commercial OCXOs.

Whole-Cell Electrical Activity Under Direct Mechanical Stimulus by AFM Cantilever Using Planar Patch Clamp Chip Approach

PubMed Central

Upadhye, Kalpesh V.; Candiello, Joseph E.; Davidson, Lance A.; Lin, Hai

2011-01-01

Patch clamp is a powerful tool for studying the properties of ion-channels and cellular membrane. In recent years, planar patch clamp chips have been fabricated from various materials including glass, quartz, silicon, silicon nitride, polydimethyl-siloxane (PDMS), and silicon dioxide. Planar patch clamps have made automation of patch clamp recordings possible. However, most planar patch clamp chips have limitations when used in combination with other techniques. Furthermore, the fabrication methods used are often expensive and require specialized equipments. An improved design as well as fabrication and characterization of a silicon-based planar patch clamp chip are described in this report. Fabrication involves true batch fabrication processes that can be performed in most common microfabrication facilities using well established MEMS techniques. Our planar patch clamp chips can form giga-ohm seals with the cell plasma membrane with success rate comparable to existing patch clamp techniques. The chip permits whole-cell voltage clamp recordings on variety of cell types including Chinese Hamster Ovary (CHO) cells and pheochromocytoma (PC12) cells, for times longer than most available patch clamp chips. When combined with a custom microfluidics chamber, we demonstrate that it is possible to perfuse the extra-cellular as well as intra-cellular buffers. The chamber design allows integration of planar patch clamp with atomic force microscope (AFM). Using our planar patch clamp chip and microfluidics chamber, we have recorded whole-cell mechanosensitive (MS) currents produced by directly stimulating human keratinocyte (HaCaT) cells using an AFM cantilever. Our results reveal the spatial distribution of MS ion channels and temporal details of the responses from MS channels. The results show that planar patch clamp chips have great potential for multi-parametric high throughput studies of ion channel proteins. PMID:22174731

A high-efficiency low-voltage class-E PA for IoT applications in sub-1 GHz frequency range

NASA Astrophysics Data System (ADS)

Zhou, Chenyi; Lu, Zhenghao; Gu, Jiangmin; Yu, Xiaopeng

2017-10-01

We present and propose a complete and iterative integrated-circuit and electro-magnetic (EM) co-design methodology and procedure for a low-voltage sub-1 GHz class-E PA. The presented class-E PA consists of the on-chip power transistor, the on-chip gate driving circuits, the off-chip tunable LC load network and the off-chip LC ladder low pass filter. The design methodology includes an explicit design equation based circuit components values' analysis and numerical derivation, output power targeted transistor size and low pass filter design, and power efficiency oriented design optimization. The proposed design procedure includes the power efficiency oriented LC network tuning, the detailed circuit/EM co-simulation plan on integrated circuit level, package level and PCB level to ensure an accurate simulation to measurement match and first pass design success. The proposed PA is targeted to achieve more than 15 dBm output power delivery and 40% power efficiency at 433 MHz frequency band with 1.5 V low voltage supply. The LC load network is designed to be off-chip for the purpose of easy tuning and optimization. The same circuit can be extended to all sub-1 GHz applications with the same tuning and optimization on the load network at different frequencies. The amplifier is implemented in 0.13 μm CMOS technology with a core area occupation of 400 μm by 300 μm. Measurement results showed that it provided power delivery of 16.42 dBm at antenna with efficiency of 40.6%. A harmonics suppression of 44 dBc is achieved, making it suitable for massive deployment of IoT devices. Project supported by the National Natural Science Foundation of China (No. 61574125) and the Industry Innovation Project of Suzhou City of China (No. SYG201641).

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nabeel A. Riza

The goals of the first six months of this project were to lay the foundations for both the SiC front-end optical chip fabrication as well as the free-space laser beam interferometer designs and preliminary tests. In addition, a Phase I goal was to design and experimentally build the high temperature and pressure infrastructure and test systems that will be used in the next 6 months for proposed sensor experimentation and data processing. All these goals have been achieved and are described in detail in the report. Both design process and diagrams for the mechanical elements as well as the opticalmore » systems are provided. In addition, photographs of the fabricated SiC optical chips, the high temperature & pressure test chamber instrument, the optical interferometer, the SiC sample chip holder, and signal processing data are provided. The design and experimentation results are summarized to give positive conclusions on the proposed novel high temperature optical sensor technology.« less

High performance flight computer developed for deep space applications

NASA Technical Reports Server (NTRS)

Bunker, Robert L.

1993-01-01

The development of an advanced space flight computer for real time embedded deep space applications which embodies the lessons learned on Galileo and modern computer technology is described. The requirements are listed and the design implementation that meets those requirements is described. The development of SPACE-16 (Spaceborne Advanced Computing Engine) (where 16 designates the databus width) was initiated to support the MM2 (Marine Mark 2) project. The computer is based on a radiation hardened emulation of a modern 32 bit microprocessor and its family of support devices including a high performance floating point accelerator. Additional custom devices which include a coprocessor to improve input/output capabilities, a memory interface chip, and an additional support chip that provide management of all fault tolerant features, are described. Detailed supporting analyses and rationale which justifies specific design and architectural decisions are provided. The six chip types were designed and fabricated. Testing and evaluation of a brass/board was initiated.

Robust Bioinformatics Recognition with VLSI Biochip Microsystem

NASA Technical Reports Server (NTRS)

Lue, Jaw-Chyng L.; Fang, Wai-Chi

2006-01-01

A microsystem architecture for real-time, on-site, robust bioinformatic patterns recognition and analysis has been proposed. This system is compatible with on-chip DNA analysis means such as polymerase chain reaction (PCR)amplification. A corresponding novel artificial neural network (ANN) learning algorithm using new sigmoid-logarithmic transfer function based on error backpropagation (EBP) algorithm is invented. Our results show the trained new ANN can recognize low fluorescence patterns better than the conventional sigmoidal ANN does. A differential logarithmic imaging chip is designed for calculating logarithm of relative intensities of fluorescence signals. The single-rail logarithmic circuit and a prototype ANN chip are designed, fabricated and characterized.

Tailoring microfluidic systems for organ-like cell culture applications using multiphysics simulations

NASA Astrophysics Data System (ADS)

Hagmeyer, Britta; Schütte, Julia; Böttger, Jan; Gebhardt, Rolf; Stelzle, Martin

2013-03-01

Replacing animal testing with in vitro cocultures of human cells is a long-term goal in pre-clinical drug tests used to gain reliable insight into drug-induced cell toxicity. However, current state-of-the-art 2D or 3D cell cultures aiming at mimicking human organs in vitro still lack organ-like morphology and perfusion and thus organ-like functions. To this end, microfluidic systems enable construction of cell culture devices which can be designed to more closely resemble the smallest functional unit of organs. Multiphysics simulations represent a powerful tool to study the various relevant physical phenomena and their impact on functionality inside microfluidic structures. This is particularly useful as it allows for assessment of system functions already during the design stage prior to actual chip fabrication. In the HepaChip®, dielectrophoretic forces are used to assemble human hepatocytes and human endothelial cells in liver sinusoid-like structures. Numerical simulations of flow distribution, shear stress, electrical fields and heat dissipation inside the cell assembly chambers as well as surface wetting and surface tension effects during filling of the microchannel network supported the design of this human-liver-on-chip microfluidic system for cell culture applications. Based on the device design resulting thereof, a prototype chip was injection-moulded in COP (cyclic olefin polymer). Functional hepatocyte and endothelial cell cocultures were established inside the HepaChip® showing excellent metabolic and secretory performance.

Design considerations for FET-gated power transistors

NASA Technical Reports Server (NTRS)

Chen, D. Y.; Chin, S. A.

1983-01-01

An FET-bipolar combinational power transistor configuration (tested up to 300 V, 20 A at 100 kHz) is described. The critical parameters for integrating the chips in hybrid form are examined, and an effort to optimize the overall characteristics of the configuration is discussed. Chip considerations are examined with respect to the voltage and current rating of individual chips, the FET surge capability, the choice of triple diffused transistor or epitaxial transistor for the bipolar element, the current tailing effect, and the implementation of the bipolar transistor and an FET as single chip or separate chips. Package considerations are discussed with respect to package material and geometry, surge current capability of bipolar base terminal bonding, and power losses distribution.

Development of a Plastic-Based Microfluidic Immunosensor Chip for Detection of H1N1 Influenza

PubMed Central

Lee, Kyoung G.; Lee, Tae Jae; Jeong, Soon Woo; Choi, Ho Woon; Heo, Nam Su; Park, Jung Youn; Park, Tae Jung; Lee, Seok Jae

2012-01-01

Lab-on-a-chip can provide convenient and accurate diagnosis tools. In this paper, a plastic-based microfluidic immunosensor chip for the diagnosis of swine flu (H1N1) was developed by immobilizing hemagglutinin antigen on a gold surface using a genetically engineered polypeptide. A fluorescent dye-labeled antibody (Ab) was used for quantifying the concentration of Ab in the immunosensor chip using a fluorescent technique. For increasing the detection efficiency and reducing the errors, three chambers and three microchannels were designed in one microfluidic chip. This protocol could be applied to the diagnosis of other infectious diseases in a microfluidic device. PMID:23112630

System on a Chip (SoC) Overview

NASA Technical Reports Server (NTRS)

LaBel, Kenneth A.

2010-01-01

System-on-a-chip or system on chip (SoC or SOC) refers to integrating all components of a computer or other electronic system into a single integrated circuit (chip). It may contain digital, analog, mixed-signal, and often radio-frequency functions all on a single chip substrate. Complexity drives it all: Radiation tolerance and testability are challenges for fault isolation, propagation, and validation. Bigger single silicon die than flown before and technology is scaling below 90nm (new qual methods). Packages have changed and are bigger and more difficult to inspect, test, and understand. Add in embedded passives. Material interfaces are more complex (underfills, processing). New rules for board layouts. Mechanical and thermal designs, etc.

Hybrid integration of VCSELs onto a silicon photonic platform for biosensing application

NASA Astrophysics Data System (ADS)

Lu, Huihui; Lee, Jun Su; Zhao, Yan; Cardile, Paolo; Daly, Aidan; Carroll, Lee; O'Brien, Peter

2017-02-01

This paper presents a technology of hybrid integration vertical cavity surface emitting lasers (VCSELs) directly on silicon photonics chip. By controlling the reflow of the solder balls used for electrical and mechanical bonding, the VCSELs were bonded at 10 degree to achieve the optimum angle-of-incidence to the planar grating coupler through vision based flip-chip techniques. The 1 dB discrepancy between optical loss values of flip-chip passive assembly and active alignment confirmed that the general purpose of the flip-chip design concept is achieved. This hybrid approach of integrating a miniaturized light source on chip opens the possibly of highly compact sensor system, which enable future portable and wearable diagnostics devices.

Design and Performance of a 1 ms High-Speed Vision Chip with 3D-Stacked 140 GOPS Column-Parallel PEs †.

PubMed

Nose, Atsushi; Yamazaki, Tomohiro; Katayama, Hironobu; Uehara, Shuji; Kobayashi, Masatsugu; Shida, Sayaka; Odahara, Masaki; Takamiya, Kenichi; Matsumoto, Shizunori; Miyashita, Leo; Watanabe, Yoshihiro; Izawa, Takashi; Muramatsu, Yoshinori; Nitta, Yoshikazu; Ishikawa, Masatoshi

2018-04-24

We have developed a high-speed vision chip using 3D stacking technology to address the increasing demand for high-speed vision chips in diverse applications. The chip comprises a 1/3.2-inch, 1.27 Mpixel, 500 fps (0.31 Mpixel, 1000 fps, 2 × 2 binning) vision chip with 3D-stacked column-parallel Analog-to-Digital Converters (ADCs) and 140 Giga Operation per Second (GOPS) programmable Single Instruction Multiple Data (SIMD) column-parallel PEs for new sensing applications. The 3D-stacked structure and column parallel processing architecture achieve high sensitivity, high resolution, and high-accuracy object positioning.

Nonvolatile memory chips: critical technology for high-performance recce systems

NASA Astrophysics Data System (ADS)

Kaufman, Bruce

2000-11-01

Airborne recce systems universally require nonvolatile storage of recorded data. Both present and next generation designs make use of flash memory chips. Flash memory devices are in high volume use for a variety of commercial products ranging form cellular phones to digital cameras. Fortunately, commercial applications call for increasing capacities and fast write times. These parameters are important to the designer of recce recorders. Of economic necessity COTS devices are used in recorders that must perform in military avionics environments. Concurrently, recording rates are moving to $GTR10Gb/S. Thus to capture imagery for even a few minutes of record time, tactically meaningful solid state recorders will require storage capacities in the 100s of Gbytes. Even with memory chip densities at present day 512Mb, such capacities require thousands of chips. The demands on packaging technology are daunting. This paper will consider the differing flash chip architectures, both available and projected and discuss the impact on recorder architecture and performance. Emerging nonvolatile memory technologies, FeRAM AND MIRAM will be reviewed with regard to their potential use in recce recorders.

VLSI Design of SVM-Based Seizure Detection System With On-Chip Learning Capability.

PubMed

Feng, Lichen; Li, Zunchao; Wang, Yuanfa

2018-02-01

Portable automatic seizure detection system is very convenient for epilepsy patients to carry. In order to make the system on-chip trainable with high efficiency and attain high detection accuracy, this paper presents a very large scale integration (VLSI) design based on the nonlinear support vector machine (SVM). The proposed design mainly consists of a feature extraction (FE) module and an SVM module. The FE module performs the three-level Daubechies discrete wavelet transform to fit the physiological bands of the electroencephalogram (EEG) signal and extracts the time-frequency domain features reflecting the nonstationary signal properties. The SVM module integrates the modified sequential minimal optimization algorithm with the table-driven-based Gaussian kernel to enable efficient on-chip learning. The presented design is verified on an Altera Cyclone II field-programmable gate array and tested using the two publicly available EEG datasets. Experiment results show that the designed VLSI system improves the detection accuracy and training efficiency.

VHDL Implementation of Sigma-Delta Analog To Digital Converter

NASA Astrophysics Data System (ADS)

Chavan, R. N.; Chougule, D. G.

2010-11-01

Sigma-Delta modulation techniques provide a range of opportunities in a signal processing system for both increasing performance and data path optimization along the silicon area axis in the design space. One of the most challenging tasks in Analog to Digital Converter (ADC) design is to adapt the circuitry to ever new CMOS process technology. For digital circuits the number of gates per square mm app. doubles per chip generation. Integration of analog parts in newer deep submicron technologies is much more tough and additionally complicated because the usable voltage ranges are decreasing with every new integration step. This paper shows an approach which only uses 2 resistors and 1 capacitor which are located outside a pure digital chip. So all integration advantages of pure digital chips are preserved, there is no design effort for a new chip generation and the ADC also can be used for FPGAs. Resolutions of up to 16 bit are achievable. Sample rates in the 1 MHz region are feasible so that the approach is also useful for ADCs for xDSL technologies.

Capillary-driven surface-enhanced Raman scattering (SERS)-based microfluidic chip for abrin detection

NASA Astrophysics Data System (ADS)

Yang, Hao; Deng, Min; Ga, Shan; Chen, Shouhui; Kang, Lin; Wang, Junhong; Xin, Wenwen; Zhang, Tao; You, Zherong; An, Yuan; Wang, Jinglin; Cui, Daxiang

2014-03-01

Herein, we firstly demonstrate the design and the proof-of-concept use of a capillary-driven surface-enhanced Raman scattering (SERS)-based microfluidic chip for abrin detection. The micropillar array substrate was etched and coated with a gold film by microelectromechanical systems (MEMS) process to integrate into a lateral flow test strip. The detection of abrin solutions of various concentrations was performed by the as-prepared microfluidic chip. It was shown that the correlation between the abrin concentration and SERS signal was found to be linear within the range of 0.1 ng/mL to 1 μg/mL with a limit of detection of 0.1 ng/mL. Our microfluidic chip design enhanced the operability of SERS-based immunodiagnostic techniques, significantly reducing the complication and cost of preparation as compared to previous SERS-based works. Meanwhile, this design proved the superiority to conventional lateral flow test strips in respect of both sensitivity and quantitation and showed great potential in the diagnosis and treatment for abrin poisoning as well as on-site screening of abrin-spiked materials.

Advanced chip designs and novel cooling techniques for brightness scaling of industrial, high power diode laser bars

NASA Astrophysics Data System (ADS)

Heinemann, S.; McDougall, S. D.; Ryu, G.; Zhao, L.; Liu, X.; Holy, C.; Jiang, C.-L.; Modak, P.; Xiong, Y.; Vethake, T.; Strohmaier, S. G.; Schmidt, B.; Zimer, H.

2018-02-01

The advance of high power semiconductor diode laser technology is driven by the rapidly growing industrial laser market, with such high power solid state laser systems requiring ever more reliable diode sources with higher brightness and efficiency at lower cost. In this paper we report simulation and experimental data demonstrating most recent progress in high brightness semiconductor laser bars for industrial applications. The advancements are in three principle areas: vertical laser chip epitaxy design, lateral laser chip current injection control, and chip cooling technology. With such improvements, we demonstrate disk laser pump laser bars with output power over 250W with 60% efficiency at the operating current. Ion implantation was investigated for improved current confinement. Initial lifetime tests show excellent reliability. For direct diode applications <1 um smile and >96% polarization are additional requirements. Double sided cooling deploying hard solder and optimized laser design enable single emitter performance also for high fill factor bars and allow further power scaling to more than 350W with 65% peak efficiency with less than 8 degrees slow axis divergence and high polarization.

Designing area optimized application-specific network-on-chip architectures while providing hard QoS guarantees.

PubMed

Khawaja, Sajid Gul; Mushtaq, Mian Hamza; Khan, Shoab A; Akram, M Usman; Jamal, Habib Ullah

2015-01-01

With the increase of transistors' density, popularity of System on Chip (SoC) has increased exponentially. As a communication module for SoC, Network on Chip (NoC) framework has been adapted as its backbone. In this paper, we propose a methodology for designing area-optimized application specific NoC while providing hard Quality of Service (QoS) guarantees for real time flows. The novelty of the proposed system lies in derivation of a Mixed Integer Linear Programming model which is then used to generate a resource optimal Network on Chip (NoC) topology and architecture while considering traffic and QoS requirements. We also present the micro-architectural design features used for enabling traffic and latency guarantees and discuss how the solution adapts for dynamic variations in the application traffic. The paper highlights the effectiveness of proposed method by generating resource efficient NoC solutions for both industrial and benchmark applications. The area-optimized results are generated in few seconds by proposed technique, without resorting to heuristics, even for an application with 48 traffic flows.

Designing Area Optimized Application-Specific Network-On-Chip Architectures while Providing Hard QoS Guarantees

PubMed Central

Khawaja, Sajid Gul; Mushtaq, Mian Hamza; Khan, Shoab A.; Akram, M. Usman; Jamal, Habib ullah

2015-01-01

With the increase of transistors' density, popularity of System on Chip (SoC) has increased exponentially. As a communication module for SoC, Network on Chip (NoC) framework has been adapted as its backbone. In this paper, we propose a methodology for designing area-optimized application specific NoC while providing hard Quality of Service (QoS) guarantees for real time flows. The novelty of the proposed system lies in derivation of a Mixed Integer Linear Programming model which is then used to generate a resource optimal Network on Chip (NoC) topology and architecture while considering traffic and QoS requirements. We also present the micro-architectural design features used for enabling traffic and latency guarantees and discuss how the solution adapts for dynamic variations in the application traffic. The paper highlights the effectiveness of proposed method by generating resource efficient NoC solutions for both industrial and benchmark applications. The area-optimized results are generated in few seconds by proposed technique, without resorting to heuristics, even for an application with 48 traffic flows. PMID:25898016

System-level protection and hardware Trojan detection using weighted voting.

PubMed

Amin, Hany A M; Alkabani, Yousra; Selim, Gamal M I

2014-07-01

The problem of hardware Trojans is becoming more serious especially with the widespread of fabless design houses and design reuse. Hardware Trojans can be embedded on chip during manufacturing or in third party intellectual property cores (IPs) during the design process. Recent research is performed to detect Trojans embedded at manufacturing time by comparing the suspected chip with a golden chip that is fully trusted. However, Trojan detection in third party IP cores is more challenging than other logic modules especially that there is no golden chip. This paper proposes a new methodology to detect/prevent hardware Trojans in third party IP cores. The method works by gradually building trust in suspected IP cores by comparing the outputs of different untrusted implementations of the same IP core. Simulation results show that our method achieves higher probability of Trojan detection over a naive implementation of simple voting on the output of different IP cores. In addition, experimental results show that the proposed method requires less hardware overhead when compared with a simple voting technique achieving the same degree of security.

Backside contacted field effect transistor array for extracellular signal recording.

PubMed

Ingebrandt, S; Yeung, C K; Staab, W; Zetterer, T; Offenhäusser, A

2003-04-01

A new approach to the design of field-effect transistor (FET) sensors and the use of these FETs in detecting extracellular electrophysiological recordings is reported. Backside contacts were engineered by deep reactive ion etching and a gas phase boron doping process of the holes using planar diffusion sources. The metal contacts were designed to fit on top of the bonding pads of a standard industrial 22-pin DIL (dual inline) chip carrier. To minimise contact resistance, the metal backside contacts of the chips were electroless plated with gold. The chips were mounted on top of the bonding pads using a standard flip-chip process and a fineplacer unit previously described. Rat embryonic myocytes were cultured on these new devices (effective growth area 6 x 6 mm(2)) in order to confirm their validity in electrophysiological recording. Copyright 2003 Elsevier Science B.V.

Single board system for fuzzy inference

NASA Technical Reports Server (NTRS)

Symon, James R.; Watanabe, Hiroyuki

1991-01-01

The very large scale integration (VLSI) implementation of a fuzzy logic inference mechanism allows the use of rule-based control and decision making in demanding real-time applications. Researchers designed a full custom VLSI inference engine. The chip was fabricated using CMOS technology. The chip consists of 688,000 transistors of which 476,000 are used for RAM memory. The fuzzy logic inference engine board system incorporates the custom designed integrated circuit into a standard VMEbus environment. The Fuzzy Logic system uses Transistor-Transistor Logic (TTL) parts to provide the interface between the Fuzzy chip and a standard, double height VMEbus backplane, allowing the chip to perform application process control through the VMEbus host. High level C language functions hide details of the hardware system interface from the applications level programmer. The first version of the board was installed on a robot at Oak Ridge National Laboratory in January of 1990.

VLSI processors for signal detection in SETI

NASA Technical Reports Server (NTRS)

Duluk, J. F.; Linscott, I. R.; Peterson, A. M.; Burr, J.; Ekroot, B.; Twicken, J.

1989-01-01

The objective of the Search for Extraterrestrial Intelligence (SETI) is to locate an artificially created signal coming from a distant star. This is done in two steps: (1) spectral analysis of an incoming radio frequency band, and (2) pattern detection for narrow-band signals. Both steps are computationally expensive and require the development of specially designed computer architectures. To reduce the size and cost of the SETI signal detection machine, two custom VLSI chips are under development. The first chip, the SETI DSP Engine, is used in the spectrum analyzer and is specially designed to compute Discrete Fourier Transforms (DFTs). It is a high-speed arithmetic processor that has two adders, one multiplier-accumulator, and three four-port memories. The second chip is a new type of Content-Addressable Memory. It is the heart of an associative processor that is used for pattern detection. Both chips incorporate many innovative circuits and architectural features.

VLSI processors for signal detection in SETI.

PubMed

Duluk, J F; Linscott, I R; Peterson, A M; Burr, J; Ekroot, B; Twicken, J

1989-01-01

The objective of the Search for Extraterrestrial Intelligence (SETI) is to locate an artificially created signal coming from a distant star. This is done in two steps: (1) spectral analysis of an incoming radio frequency band, and (2) pattern detection for narrow-band signals. Both steps are computationally expensive and require the development of specially designed computer architectures. To reduce the size and cost of the SETI signal detection machine, two custom VLSI chips are under development. The first chip, the SETI DSP Engine, is used in the spectrum analyzer and is specially designed to compute Discrete Fourier Transforms (DFTs). It is a high-speed arithmetic processor that has two adders, one multiplier-accumulator, and three four-port memories. The second chip is a new type of Content-Addressable Memory. It is the heart of an associative processor that is used for pattern detection. Both chips incorporate many innovative circuits and architectural features.

VizieR Online Data Catalog: OGLE-III. Magellanic Clouds stellar proper motions (Poleski+, 2012)

NASA Astrophysics Data System (ADS)

Poleski, R.; Soszynski, I.; Udalski, A.; Szymanski, M. K.; Kubiak, M.; Pietrzynski, G.; Wyrzykowski, L.; Ulaczyk, K.

2015-07-01

The OGLE-III project observed the Large Magellanic Cloud, the Small Magellanic Cloud, and the globular cluster 47 Tuc between 2001 and 2009 with the 1.3-m Warsaw telescope, which is situated at the Las Campanas Observatory, Chile. The telescope was equipped with an eight-chip mosaic CCD camera. The field of view was 36'x36' and the pixel scale was 0.26"/pix. I-band filter was used. (5 data files).

VizieR Online Data Catalog: BVR light curves of UZ Leo (Lee+, 2018)

NASA Astrophysics Data System (ADS)

Lee, J. W.; Park, J.-H.

2018-04-01

We performed new CCD photometry of UZ Leo during two observing seasons between 2012 February and 2013 April, using a PIXIS: 2048B CCD and a BVR filter set attached to the 61 cm reflector at Sobaeksan Optical Astronomy Observatory (SOAO) in Korea. The CCD chip has 2048x2048pixels and a pixel size of 13.5um, so the field of view of a CCD frame is 17.6'x17.6'. (1 data file).

Latest generation of ASICs for photodetector readout

NASA Astrophysics Data System (ADS)

Seguin-Moreau, N.

2013-08-01

The OMEGA microelectronics group has designed a new generation of multichannel integrated circuits, the "ROC" family, in AustrianMicroSystem (AMS) SiGe 0.35 μm technology to read out signals from various families of photodetectors. The chip named MAROC (standing for Multi Anode ReadOut Chip) has been designed to read out MultiAnode Photomultipliers (MAPMT), Photomultiplier ARray In SiGe ReadOut Chip (PARISROC) to read out Photomultipliers (PMTs) and SiPM Integrated ReadOut Chip (SPIROC) to readout Silicon PhotoMultiplier (SiPM) detectors and which was the first ASIC to do so. The three of them fulfill the stringent requirements of the future photodetectors, in particular in terms of low noise, radiation hardness, large dynamic range, high density and high speed while keeping low power thanks to the SiGe technology. These multi-channel ASICs are real System on Chip (SoC) as they provide charge, time and photon-counting information which are digitized internally. Their complexity and versatility enable innovative frontier detectors and also cover spin off of these detectors in adjacent fields such as medical or material imaging as well as smart detectors. In this presentation, the three ASIC architectures and test results will be described to give a general panorama of the "ROC" chips.

Plasma micro-nanotextured polymeric micromixer for DNA purification with high efficiency and dynamic range.

PubMed

Kastania, Athina S; Tsougeni, Katerina; Papadakis, George; Gizeli, Electra; Kokkoris, George; Tserepi, Angeliki; Gogolides, Evangelos

2016-10-26

We present a polymeric microfluidic chip capable of purifying DNA through solid phase extraction. It is designed to be used as a module of an integrated Lab-on-chip platform for pathogen detection, but it can also be used as a stand-alone device. The microfluidic channels are oxygen plasma micro-nanotextured, i.e. randomly roughened in the micro-nano scale, a process creating high surface area as well as high density of carboxyl groups (COOH). The COOH groups together with a buffer that contains polyethylene glycol (PEG), NaCl and ethanol are able to bind DNA on the microchannel surface. The chip design incorporates a mixer so that sample and buffer can be efficiently mixed on chip under continuous flow. DNA is subsequently eluted in water. The chip is able to isolate DNA with high recovery efficiency (96± 11%) in an extremely large dynamic range of prepurified Salmonella DNA as well as from Salmonella cell lysates that correspond to a range of 5 to 1.9 × 10 8  cells (0.263 fg to 2 × 500 ng). The chip was evaluated via absorbance measurements, polymerase chain reaction (PCR), and gel electrophoresis. Copyright © 2016 Elsevier B.V. All rights reserved.

A Low Cost Single Chip VDL Compatible Transceiver ASIC

NASA Technical Reports Server (NTRS)

Becker, Robert

2004-01-01

Recent trends in commercial communications system components have focussed almost exclusively on cellular telephone technology. As many of the traditional sources of receiver components have discontinued non-cellular telephone products, the designers of avionics and other low volume radio applications find themselves increasingly unable to find highly integrated components. This is particularly true for low power, low cost applications which cannot afford the lavish current consumption of the software defined radio approach increasingly taken by certified device manufacturers. In this paper, we describe a low power transceiver chip targeting applications from low VHF to low UHF frequencies typical of avionics systems. The chip encompasses a selectable single or double conversion design for the receiver and a low power IF upconversion transmitter. All local oscillators are synthesized and integrated into the chip. An on-chip I-Q modulator and demodulator provide baseband modulation and demodulation capability allowing the use of low power, fixed point signal processing components for signal demodulation. The goal of this program is to demonstrate a low cost VDL mode-3 transceiver using this chip to receive text weather information sent using 4-slot TDMA with no support for voice. The data will be sent from an experimental ground station. This work is funded by NASA Glenn Research Center.

A new statistical methodology predicting chip failure probability considering electromigration

NASA Astrophysics Data System (ADS)

Sun, Ted

In this research thesis, we present a new approach to analyze chip reliability subject to electromigration (EM) whose fundamental causes and EM phenomenon happened in different materials are presented in this thesis. This new approach utilizes the statistical nature of EM failure in order to assess overall EM risk. It includes within-die temperature variations from the chip's temperature map extracted by an Electronic Design Automation (EDA) tool to estimate the failure probability of a design. Both the power estimation and thermal analysis are performed in the EDA flow. We first used the traditional EM approach to analyze the design with a single temperature across the entire chip that involves 6 metal and 5 via layers. Next, we used the same traditional approach but with a realistic temperature map. The traditional EM analysis approach and that coupled with a temperature map and the comparison between the results of considering and not considering temperature map are presented in in this research. A comparison between these two results confirms that using a temperature map yields a less pessimistic estimation of the chip's EM risk. Finally, we employed the statistical methodology we developed considering a temperature map and different use-condition voltages and frequencies to estimate the overall failure probability of the chip. The statistical model established considers the scaling work with the usage of traditional Black equation and four major conditions. The statistical result comparisons are within our expectations. The results of this statistical analysis confirm that the chip level failure probability is higher i) at higher use-condition frequencies for all use-condition voltages, and ii) when a single temperature instead of a temperature map across the chip is considered. In this thesis, I start with an overall review on current design types, common flows, and necessary verifications and reliability checking steps used in this IC design industry. Furthermore, the important concepts about "Scripting Automation" which is used in all the integration of using diversified EDA tools in this research work are also described in detail with several examples and my completed coding works are also put in the appendix for your reference. Hopefully, this construction of my thesis will give readers a thorough understanding about my research work from the automation of EDA tools to the statistical data generation, from the nature of EM to the statistical model construction, and the comparisons among the traditional EM analysis and the statistical EM analysis approaches.

The artificial satellite observation chronograph controlled by single chip microcomputer.

NASA Astrophysics Data System (ADS)

Pan, Guangrong; Tan, Jufan; Ding, Yuanjun

1991-06-01

The instrument specifications, hardware structure, software design, and other characteristics of the chronograph mounting on a theodolite used for artificial satellite observation are presented. The instrument is a real time control system with a single chip microcomputer.

Package Holds Five Monolithic Microwave Integrated Circuits

NASA Technical Reports Server (NTRS)

Mysoor, Narayan R.; Decker, D. Richard; Olson, Hilding M.

1996-01-01

Packages protect and hold monolithic microwave integrated circuit (MMIC) chips while providing dc and radio-frequency (RF) electrical connections for chips undergoing development. Required to be compact, lightweight, and rugged. Designed to minimize undesired resonances, reflections, losses, and impedance mismatches.

High-performance, scalable optical network-on-chip architectures

NASA Astrophysics Data System (ADS)

Tan, Xianfang

The rapid advance of technology enables a large number of processing cores to be integrated into a single chip which is called a Chip Multiprocessor (CMP) or a Multiprocessor System-on-Chip (MPSoC) design. The on-chip interconnection network, which is the communication infrastructure for these processing cores, plays a central role in a many-core system. With the continuously increasing complexity of many-core systems, traditional metallic wired electronic networks-on-chip (NoC) became a bottleneck because of the unbearable latency in data transmission and extremely high energy consumption on chip. Optical networks-on-chip (ONoC) has been proposed as a promising alternative paradigm for electronic NoC with the benefits of optical signaling communication such as extremely high bandwidth, negligible latency, and low power consumption. This dissertation focus on the design of high-performance and scalable ONoC architectures and the contributions are highlighted as follow: 1. A micro-ring resonator (MRR)-based Generic Wavelength-routed Optical Router (GWOR) is proposed. A method for developing any sized GWOR is introduced. GWOR is a scalable non-blocking ONoC architecture with simple structure, low cost and high power efficiency compared to existing ONoC designs. 2. To expand the bandwidth and improve the fault tolerance of the GWOR, a redundant GWOR architecture is designed by cascading different type of GWORs into one network. 3. The redundant GWOR built with MRR-based comb switches is proposed. Comb switches can expand the bandwidth while keep the topology of GWOR unchanged by replacing the general MRRs with comb switches. 4. A butterfly fat tree (BFT)-based hybrid optoelectronic NoC (HONoC) architecture is developed in which GWORs are used for global communication and electronic routers are used for local communication. The proposed HONoC uses less numbers of electronic routers and links than its counterpart of electronic BFT-based NoC. It takes the advantages of GWOR in optical communication and BFT in non-uniform traffic communication and three-dimension (3D) implementation. 5. A cycle-accurate NoC simulator is developed to evaluate the performance of proposed HONoC architectures. It is a comprehensive platform that can simulate both electronic and optical NoCs. Different size HONoC architectures are evaluated in terms of throughput, latency and energy dissipation. Simulation results confirm that HONoC achieves good network performance with lower power consumption.

Microvalve controlled multi-functional microfluidic chip for divisional cell co-culture.

PubMed

Li, Rui; Zhang, Xingjian; Lv, Xuefei; Geng, Lina; Li, Yongrui; Qin, Kuiwei; Deng, Yulin

2017-12-15

Pneumatic micro-valve controlled microfluidic chip provides precise fluidic control for cell manipulation. In this paper, a multi-functional microfluidic chip was designed for three separate experiments: 1. Different cell lines were dispensed and cultured; 2. Three transfected SH-SY5Y cells were introduced and treated with methyl-phenyl-pyridinium (MPP + ) as drug delivery mode; 3. Specific protection and interaction were observed among cell co-culture after nerve damage. The outcomes revealed the potential and practicability of our entire multi-functional pneumatic chip system on different cell biology applications. Copyright © 2017. Published by Elsevier Inc.

Design of Water Temperature Control System Based on Single Chip Microcomputer

NASA Astrophysics Data System (ADS)

Tan, Hanhong; Yan, Qiyan

2017-12-01

In this paper, we mainly introduce a multi-function water temperature controller designed with 51 single-chip microcomputer. This controller has automatic and manual water, set the water temperature, real-time display of water and temperature and alarm function, and has a simple structure, high reliability, low cost. The current water temperature controller on the market basically use bimetal temperature control, temperature control accuracy is low, poor reliability, a single function. With the development of microelectronics technology, monolithic microprocessor function is increasing, the price is low, in all aspects of widely used. In the water temperature controller in the application of single-chip, with a simple design, high reliability, easy to expand the advantages of the function. Is based on the appeal background, so this paper focuses on the temperature controller in the intelligent control of the discussion.

A UVM simulation environment for the study, optimization and verification of HL-LHC digital pixel readout chips

NASA Astrophysics Data System (ADS)

Marconi, S.; Conti, E.; Christiansen, J.; Placidi, P.

2018-05-01

The operating conditions of the High Luminosity upgrade of the Large Hadron Collider are very demanding for the design of next generation hybrid pixel readout chips in terms of particle rate, radiation level and data bandwidth. To this purpose, the RD53 Collaboration has developed for the ATLAS and CMS experiments a dedicated simulation and verification environment using industry-consolidated tools and methodologies, such as SystemVerilog and the Universal Verification Methodology (UVM). This paper presents how the so-called VEPIX53 environment has first guided the design of digital architectures, optimized for processing and buffering very high particle rates, and secondly how it has been reused for the functional verification of the first large scale demonstrator chip designed by the collaboration, which has recently been submitted.

Recent advances in design and fabrication of on-chip micro-supercapacitors

NASA Astrophysics Data System (ADS)

Beidaghi, Majid; Wang, Chunlei

2012-06-01

Recent development in miniaturized electronic devices has increased the demand for power sources that are sufficiently compact and can potentially be integrated on a chip with other electronic components. Miniaturized electrochemical capacitors (EC) or micro-supercapacitors have great potential to complement or replace batteries and electrolytic capacitors in a variety of applications. Recently, we have developed several types of micro-supercapacitors with different structural designs and active materials. Carbon-Microelectromechanical Systems (C-MEMS) with three dimensional (3D) interdigital structures are employed both as electrode material for electric double layer capacitor (EDLC) or as three dimensional (3D) current collectors of pseudo-capacitive materials. More recently, we have also developed microsupercapacitor based on hybrid graphene and carbon nanotube interdigital structures. In this paper, the recent advances in design and fabrication of on-chip micro-supercapacitors are reviewed.

Design of integrated eye tracker-display device for head mounted systems

NASA Astrophysics Data System (ADS)

David, Y.; Apter, B.; Thirer, N.; Baal-Zedaka, I.; Efron, U.

2009-08-01

We propose an Eye Tracker/Display system, based on a novel, dual function device termed ETD, which allows sharing the optical paths of the Eye tracker and the display and on-chip processing. The proposed ETD design is based on a CMOS chip combining a Liquid-Crystal-on-Silicon (LCoS) micro-display technology with near infrared (NIR) Active Pixel Sensor imager. The ET operation allows capturing the Near IR (NIR) light, back-reflected from the eye's retina. The retinal image is then used for the detection of the current direction of eye's gaze. The design of the eye tracking imager is based on the "deep p-well" pixel technology, providing low crosstalk while shielding the active pixel circuitry, which serves the imaging and the display drivers, from the photo charges generated in the substrate. The use of the ETD in the HMD Design enables a very compact design suitable for Smart Goggle applications. A preliminary optical, electronic and digital design of the goggle and its associated ETD chip and digital control, are presented.

Efficacy of CM-Wire, M-Wire, and Nickel-Titanium Instruments for Removing Filling Material from Curved Root Canals: A Micro-Computed Tomography Study.

PubMed

Rodrigues, Clarissa Teles; Duarte, Marco Antonio Hungaro; de Almeida, Marcela Milanezi; de Andrade, Flaviana Bombarda; Bernardineli, Norberti

2016-11-01

The aim of this ex vivo study was to evaluate the removal of filling material after using CM-wire, M-wire, and nickel-titanium instruments in both reciprocating and rotary motions in curved canals. Thirty maxillary lateral incisors were divided into 9 groups according to retreatment procedures: Reciproc R25 followed by Mtwo 40/.04 and ProDesign Logic 50/.01 files; ProDesign R 25/.06 followed by ProDesign Logic 40/.05 and ProDesign Logic 50/.01 files; and Gates-Glidden drills, Hedström files, and K-files up to apical size 30 followed by K-file 40 and K-file 50 up to the working length. Micro-computed tomography scans were performed before and after each reinstrumentation procedure to evaluate root canal filling removal. Statistical analysis was performed with Kruskal-Wallis, Friedman, and Wilcoxon tests (P < .05). No significant differences in filling material removal were found in the 3 groups of teeth. The use of Mtwo and ProDesign Logic 40/.05 rotary files did not enhance filling material removal after the use of reciprocating files. The use of ProDesign Logic 50/.01 files significantly reduced the amount of filling material at the apical levels compared with the use of reciprocating files. Association of reciprocating and rotary files was capable of removing a large amount of filling material in the retreatment of curved canals, irrespective of the type of alloy of the instruments. The use of a ProDesign Logic 50/.01 file for apical preparation significantly reduced the amount of remnant material in the apical portion when compared with reciprocating instruments. Copyright © 2016 American Association of Endodontists. Published by Elsevier Inc. All rights reserved.

Optimized FPGA Implementation of the Thyroid Hormone Secretion Mechanism Using CAD Tools.

PubMed

Alghazo, Jaafar M

2017-02-01

The goal of this paper is to implement the secretion mechanism of the Thyroid Hormone (TH) based on bio-mathematical differential eqs. (DE) on an FPGA chip. Hardware Descriptive Language (HDL) is used to develop a behavioral model of the mechanism derived from the DE. The Thyroid Hormone secretion mechanism is simulated with the interaction of the related stimulating and inhibiting hormones. Synthesis of the simulation is done with the aid of CAD tools and downloaded on a Field Programmable Gate Arrays (FPGAs) Chip. The chip output shows identical behavior to that of the designed algorithm through simulation. It is concluded that the chip mimics the Thyroid Hormone secretion mechanism. The chip, operating in real-time, is computer-independent stand-alone system.

3D capillary stop valves for versatile patterning inside microfluidic chips.

PubMed

Papadimitriou, V A; Segerink, L I; van den Berg, A; Eijkel, J C T

2018-02-13

The patterning of antibodies in microfluidics chips is always a delicate process that is usually done in an open chip before bonding. Typical bonding techniques such as plasma treatment can harm the antibodies with as result that they are removed from our fabrication toolbox. Here we propose a method, based on capillary phenomena using 3D capillary valves, that autonomously and conveniently allows us to pattern liquids inside closed chips. We theoretically analyse the system and demonstrate how our analysis can be used as a design tool for various applications. Chips patterned with the method were used for simple immunodetection of a cardiac biomarker which demonstrates its suitability for antibody patterning. Copyright © 2017 The Authors. Published by Elsevier B.V. All rights reserved.

Design and integration of an all-in-one biomicrofluidic chip

PubMed Central

Liu, Liyu; Cao, Wenbin; Wu, Jingbo; Wen, Weijia; Chang, Donald Choy; Sheng, Ping

2008-01-01

We demonstrate a highly integrated microfluidic chip with the function of DNA amplification. The integrated chip combines giant electrorheological-fluid actuated micromixer and micropump with a microheater array, all formed using soft lithography. Internal functional components are based on polydimethylsiloxane (PDMS) and silver∕carbon black-PDMS composites. The system has the advantages of small size with a high degree of integration, high polymerase chain reaction efficiency, digital control and simple fabrication at low cost. This integration approach shows promise for a broad range of applications in chemical synthesis and biological sensing∕analysis, as different components can be combined to target desired functionalities, with flexible designs of different microchips easily realizable through soft lithography. PMID:19693370

Language Classification using N-grams Accelerated by FPGA-based Bloom Filters

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jacob, A; Gokhale, M

N-Gram (n-character sequences in text documents) counting is a well-established technique used in classifying the language of text in a document. In this paper, n-gram processing is accelerated through the use of reconfigurable hardware on the XtremeData XD1000 system. Our design employs parallelism at multiple levels, with parallel Bloom Filters accessing on-chip RAM, parallel language classifiers, and parallel document processing. In contrast to another hardware implementation (HAIL algorithm) that uses off-chip SRAM for lookup, our highly scalable implementation uses only on-chip memory blocks. Our implementation of end-to-end language classification runs at 85x comparable software and 1.45x the competing hardware design.

Electrokinetic focusing injection methods on microfluidic devices.

PubMed

Fu, Lung-Ming; Yang, Ruey-Jen; Lee, Gwo-Bin

2003-04-15

This paper presents an experimental and numerical investigation into electrokinetic focusing injection on microfluidic chips. The valving characteristics on microfluidic devices are controlled through appropriate manipulations of the electric potential strengths during the sample loading and dispensing steps. The present study also addresses the design and testing of various injection systems used to deliver a sample plug. A novel double-cross injection microfluidic chip is fabricated, which employs electrokinetic focusing to deliver sample plugs of variable volume. The proposed design combines several functions of traditional sample plug injection systems on a single microfluidic chip. The injection technique uses an unique sequence of loading steps with different electric potential distributions and magnitudes within the various channels to effectuate a virtual valve.

3D-glass molds for facile production of complex droplet microfluidic chips.

PubMed

Tovar, Miguel; Weber, Thomas; Hengoju, Sundar; Lovera, Andrea; Munser, Anne-Sophie; Shvydkiv, Oksana; Roth, Martin

2018-03-01

In order to leverage the immense potential of droplet microfluidics, it is necessary to simplify the process of chip design and fabrication. While polydimethylsiloxane (PDMS) replica molding has greatly revolutionized the chip-production process, its dependence on 2D-limited photolithography has restricted the design possibilities, as well as further dissemination of microfluidics to non-specialized labs. To break free from these restrictions while keeping fabrication straighforward, we introduce an approach to produce complex multi-height (3D) droplet microfluidic glass molds and subsequent chip production by PDMS replica molding. The glass molds are fabricated with sub-micrometric resolution using femtosecond laser machining technology, which allows directly realizing designs with multiple levels or even continuously changing heights. The presented technique significantly expands the experimental capabilities of the droplet microfluidic chip. It allows direct fabrication of multilevel structures such as droplet traps for prolonged observation and optical fiber integration for fluorescence detection. Furthermore, the fabrication of novel structures based on sloped channels (ramps) enables improved droplet reinjection and picoinjection or even a multi-parallelized drop generator based on gradients of confinement. The fabrication of these and other 3D-features is currently only available at such resolution by the presented strategy. Together with the simplicity of PDMS replica molding, this provides an accessible solution for both specialized and non-specialized labs to customize microfluidic experimentation and expand their possibilities.

Macromolecular Crystal Growth by Means of Microfluidics

NASA Technical Reports Server (NTRS)

vanderWoerd, Mark; Ferree, Darren; Spearing, Scott; Monaco, Lisa; Molho, Josh; Spaid, Michael; Brasseur, Mike; Curreri, Peter A. (Technical Monitor)

2002-01-01

We have performed a feasibility study in which we show that chip-based, microfluidic (LabChip(TM)) technology is suitable for protein crystal growth. This technology allows for accurate and reliable dispensing and mixing of very small volumes while minimizing bubble formation in the crystallization mixture. The amount of (protein) solution remaining after completion of an experiment is minimal, which makes this technique efficient and attractive for use with proteins, which are difficult or expensive to obtain. The nature of LabChip(TM) technology renders it highly amenable to automation. Protein crystals obtained in our initial feasibility studies were of excellent quality as determined by X-ray diffraction. Subsequent to the feasibility study, we designed and produced the first LabChip(TM) device specifically for protein crystallization in batch mode. It can reliably dispense and mix from a range of solution constituents into two independent growth wells. We are currently testing this design to prove its efficacy for protein crystallization optimization experiments. In the near future we will expand our design to incorporate up to 10 growth wells per LabChip(TM) device. Upon completion, additional crystallization techniques such as vapor diffusion and liquid-liquid diffusion will be accommodated. Macromolecular crystallization using microfluidic technology is envisioned as a fully automated system, which will use the 'tele-science' concept of remote operation and will be developed into a research facility for the International Space Station as well as on the ground.

Interfacing Lab-on-a-Chip Embryo Technology with High-Definition Imaging Cytometry.

PubMed

Zhu, Feng; Hall, Christopher J; Crosier, Philip S; Wlodkowic, Donald

2015-08-01

To spearhead deployment of zebrafish embryo biotests in large-scale drug discovery studies, automated platforms are needed to integrate embryo in-test positioning and immobilization (suitable for high-content imaging) with fluidic modules for continuous drug and medium delivery under microperfusion to developing embryos. In this work, we present an innovative design of a high-throughput three-dimensional (3D) microfluidic chip-based device for automated immobilization and culture and time-lapse imaging of developing zebrafish embryos under continuous microperfusion. The 3D Lab-on-a-Chip array was fabricated in poly(methyl methacrylate) (PMMA) transparent thermoplastic using infrared laser micromachining, while the off-chip interfaces were fabricated using additive manufacturing processes (fused deposition modelling and stereolithography). The system's design facilitated rapid loading and immobilization of a large number of embryos in predefined clusters of traps during continuous microperfusion of drugs/toxins. It was conceptually designed to seamlessly interface with both upright and inverted fluorescent imaging systems and also to directly interface with conventional microtiter plate readers that accept 96-well plates. Compared with the conventional Petri dish assays, the chip-based bioassay was much more convenient and efficient as only small amounts of drug solutions were required for the whole perfusion system running continuously over 72 h. Embryos were spatially separated in the traps that assisted tracing single embryos, preventing interembryo contamination and improving imaging accessibility.

Intelligent Computation for Optimal Fabrication Condition of a Protein Chip with Ni-Co Alloy-Coated Surface.

PubMed

Chang, Yaw-Jen; Chang, Cheng-Hao

2016-06-01

Based on the principle of immobilized metal affinity chromatography (IMAC), it has been found that a Ni-Co alloy-coated protein chip is able to immobilize functional proteins with a His-tag attached. In this study, an intelligent computational approach was developed to promote the performance and repeatability of a Ni-Co alloy-coated protein chip. This approach was launched out of L18 experiments. Based on the experimental data, the fabrication process model of a Ni-Co protein chip was established by using an artificial neural network, and then an optimal fabrication condition was obtained using the Taguchi genetic algorithm. The result was validated experimentally and compared with a nitrocellulose chip. Consequentially, experimental outcomes revealed that the Ni-Co alloy-coated chip, fabricated using the proposed approach, had the best performance and repeatability compared with the Ni-Co chips of an L18 orthogonal array design and the nitrocellulose chip. Moreover, the low fluorescent background of the chip surface gives a more precise fluorescent detection. Based on a small quantity of experiments, this proposed intelligent computation approach can significantly reduce the experimental cost and improve the product's quality. © 2015 Society for Laboratory Automation and Screening.

Multi-scale reflection modulator-based optical interconnects

NASA Astrophysics Data System (ADS)

Nair, Rohit

This dissertation describes the design, analysis, and experimental validation of micro- and macro-optical components for implementing optical interconnects at multiple scales for varied applications. Three distance scales are explored: millimeter, centimeter, and meter-scales. At the millimeter-scale, we propose the use of optical interconnects at the intra-chip level. With the rapid scaling down of CMOS critical dimensions in accordance to Moore's law, the bandwidth requirements of global interconnects in microprocessors has exceeded the capabilities of metal links. These are the wires that connect the most remote parts of the chip and are disproportionately problematic in terms of chip area and power consumption. Consequently, in the mid-2000s, we saw a shift in the chip architecture: a move towards multicore designs. However, this only delays the inevitable communication bottleneck between cores. To satisfy this bandwidth, we propose to replace the global metal interconnects with optical interconnects. We propose to use the hybrid integration of silicon with GaAs/AlAs-based multiple quantum well devices as optical modulators and photodetectors along with polymeric waveguides to transport the light. We use grayscale lithography to fabricate curved facets into the waveguides to couple light into the modulators and photodetectors. Next, at the chip-to-chip level in high-performance multiprocessor computing systems, communication distances vary from a few centimeters to tens of centimeters. An optical design for coupling light from off-chip lasers to on-chip surface-normal modulators is proposed in order to implement chip-to-chip free-space optical interconnects. The method uses a dual-prism module constructed from prisms made of two different glasses. The various alignment tolerances of the proposed system are investigated and found to be well within pick-and-place accuracies. For the off-chip lasers, vertical cavity surface emitting lasers (VCSELs) are proposed. The rationale behind using on-chip modulators rather than VCSELs is to avoid VCSEL thermal loads on chip, and because of higher reliability of modulators than VCSELs. Particularly above 10Gbps, an empirical model developed shows the rapid decrease of VCSEL median time to failure vs. data rate. Thus the proposed interconnect scheme which utilizes continuous wave VCSELs that are externally modulated by on-chip multiple quantum well modulators is applicable for chip-to-chip optical interconnects at 20Gbps and higher line data rates. Finally, for applications such as remote telemetry, where the interrogation distances can vary from a few meters to tens or even hundreds of meters we demonstrate a modulated retroreflector that utilizes InGaAs/InAlAs-based large-area multiple quantum well modulators on all three faces of a retroreflector. The large-area devices, fabricated by metalorganic chemical vapor deposition, are characterized in terms of the yield and leakage currents. A yield higher than that achieved previously using devices fabricated by molecular beam epitaxy is observed. The retroreflector module is constructed using standard FR4 printed circuit boards, thereby simplifying the wiring issue. A high optical contrast ratio of 8.23dB is observed for a drive of 20V. A free-standing PCB retroreflector is explored and found to have insufficient angular tolerances (+/-0.5 degrees). We show that the angular errors in the corner-cube construction can be corrected for using off-the-shelf optical components as opposed to mounting the PCBs on a precision corner cube, as has been done previously.

37 CFR 201.38 - Designation of agent to receive notification of claimed infringement.

Code of Federal Regulations, 2010 CFR

2010-07-01

... person signing the Notice, and by the date of signature. (e) Filing. A service provider may file the.... The Copyright Office does not provide printed forms for filing an Interim Designation of Agent to... shall be accompanied by a filing fee for Recordation of an Interim Designation of Agent to Receive...

Route to one-step microstructure mold fabrication for PDMS microfluidic chip

NASA Astrophysics Data System (ADS)

Lv, Xiaoqing; Geng, Zhaoxin; Fan, Zhiyuan; Wang, Shicai; Su, Yue; Fang, Weihao; Pei, Weihua; Chen, Hongda

2018-04-01

The microstructure mold fabrication for PDMS microfluidic chip remains complex and time-consuming process requiring special equipment and protocols: photolithography and etching. Thus, a rapid and cost-effective method is highly needed. Comparing with the traditional microfluidic chip fabricating process based on the micro-electromechanical system (MEMS), this method is simple and easy to implement, and the whole fabrication process only requires 1-2 h. Different size of microstructure from 100 to 1000 μm was fabricated, and used to culture four kinds of breast cancer cell lines. Cell viability and morphology was assessed when they were cultured in the micro straight channels, micro square holes and the bonding PDMS-glass microfluidic chip. The experimental results indicate that the microfluidic chip is good and meet the experimental requirements. This method can greatly reduce the process time and cost of the microfluidic chip, and provide a simple and effective way for the structure design and in the field of biological microfabrications and microfluidic chips.

Control and measurement of the phase behavior of aqueous solutions using microfluidics

PubMed Central

Shim, Jung-uk; Cristobal, Galder; Link, Darren R.; Thorsen, Todd; Jia, Yanwei; Piattelli, Katie; Fraden, Seth

2008-01-01

A microfluidic device denoted the Phase Chip has been designed to measure and manipulate the phase diagram of multi-component fluid mixtures. The Phase Chip exploits the permeation of water through poly(dimethylsiloxane) (PDMS) in order to controllably vary the concentration of solutes in aqueous nanoliter volume microdrops stored in wells. The permeation of water in the Phase Chip is modeled using the diffusion equation and good agreement between experiment and theory is obtained. The Phase Chip operates by first creating drops of the water/solute mixture whose composition varies sequentially. Next, drops are transported down channels and guided into storage wells using surface tension forces. Finally, the solute concentration of each stored drop is simultaneously varied and measured. Two applications of the Phase Chip are presented. First, the phase diagram of a polymer/salt mixture is measured on-chip and validated off-chip and second, protein crystallization rates are enhanced through the manipulation of the kinetics of nucleation and growth. PMID:17580868

Optic nerve signals in a neuromorphic chip II: Testing and results.

PubMed

Zaghloul, Kareem A; Boahen, Kwabena

2004-04-01

Seeking to match the brain's computational efficiency, we draw inspiration from its neural circuits. To model the four main output (ganglion) cell types found in the retina, we morphed outer and inner retina circuits into a 96 x 60-photoreceptor, 3.5 x 3.3 mm2, 0.35 microm-CMOS chip. Our retinomorphic chip produces spike trains for 3600 ganglion cells (GCs), and consumes 62.7 mW at 45 spikes/s/GC. This chip, which is the first silicon retina to successfully model inner retina circuitry, approaches the spatial density of the retina. We present experimental measurements showing that the chip's subthreshold current-mode circuits realize luminance adaptation, bandpass spatiotemporal filtering, temporal adaptation and contrast gain control. The four different GC outputs produced by our chip encode light onset or offset in a sustained or transient fashion, producing a quadrature-like representation. The retinomorphic chip's circuit design is described in a companion paper [Zaghloul and Boahen (2004)].

Design of wideband solar ultraviolet radiation intensity monitoring and control system

NASA Astrophysics Data System (ADS)

Ye, Linmao; Wu, Zhigang; Li, Yusheng; Yu, Guohe; Jin, Qi

2009-08-01

According to the principle of SCM (Single Chip Microcomputer) and computer communication technique, the system is composed of chips such as ATML89C51, ADL0809, integrated circuit and sensors for UV radiation, which is designed for monitoring and controlling the UV index. This system can automatically collect the UV index data, analyze and check the history database, research the law of UV radiation in the region.

Laser doppler blood flow imaging using a CMOS imaging sensor with on-chip signal processing.

PubMed

He, Diwei; Nguyen, Hoang C; Hayes-Gill, Barrie R; Zhu, Yiqun; Crowe, John A; Gill, Cally; Clough, Geraldine F; Morgan, Stephen P

2013-09-18

The first fully integrated 2D CMOS imaging sensor with on-chip signal processing for applications in laser Doppler blood flow (LDBF) imaging has been designed and tested. To obtain a space efficient design over 64 × 64 pixels means that standard processing electronics used off-chip cannot be implemented. Therefore the analog signal processing at each pixel is a tailored design for LDBF signals with balanced optimization for signal-to-noise ratio and silicon area. This custom made sensor offers key advantages over conventional sensors, viz. the analog signal processing at the pixel level carries out signal normalization; the AC amplification in combination with an anti-aliasing filter allows analog-to-digital conversion with a low number of bits; low resource implementation of the digital processor enables on-chip processing and the data bottleneck that exists between the detector and processing electronics has been overcome. The sensor demonstrates good agreement with simulation at each design stage. The measured optical performance of the sensor is demonstrated using modulated light signals and in vivo blood flow experiments. Images showing blood flow changes with arterial occlusion and an inflammatory response to a histamine skin-prick demonstrate that the sensor array is capable of detecting blood flow signals from tissue.

On-chip infrared sensors: redefining the benefits of scaling

NASA Astrophysics Data System (ADS)

Kita, Derek; Lin, Hongtao; Agarwal, Anu; Yadav, Anupama; Richardson, Kathleen; Luzinov, Igor; Gu, Tian; Hu, Juejun

2017-03-01

Infrared (IR) spectroscopy is widely recognized as a gold standard technique for chemical and biological analysis. Traditional IR spectroscopy relies on fragile bench-top instruments located in dedicated laboratory settings, and is thus not suitable for emerging field-deployed applications such as in-line industrial process control, environmental monitoring, and point-of-care diagnosis. Recent strides in photonic integration technologies provide a promising route towards enabling miniaturized, rugged platforms for IR spectroscopic analysis. It is therefore attempting to simply replace the bulky discrete optical elements used in conventional IR spectroscopy with their on-chip counterparts. This size down-scaling approach, however, cripples the system performance as both the sensitivity of spectroscopic sensors and spectral resolution of spectrometers scale with optical path length. In light of this challenge, we will discuss two novel photonic device designs uniquely capable of reaping performance benefits from microphotonic scaling. We leverage strong optical and thermal confinement in judiciously designed micro-cavities to circumvent the thermal diffusion and optical diffraction limits in conventional photothermal sensors and achieve a record 104 photothermal sensitivity enhancement. In the second example, an on-chip spectrometer design with the Fellgett's advantage is analyzed. The design enables sub-nm spectral resolution on a millimeter-sized, fully packaged chip without moving parts.

Optical time division multiplexer on silicon chip.

PubMed

Aboketaf, Abdelsalam A; Elshaari, Ali W; Preble, Stefan F

2010-06-21

In this work, we experimentally demonstrate a novel broadband optical time division multiplexer (OTDM) on a silicon chip. The fabricated devices generate 20 Gb/s and 40 Gb/s signals starting from a 5 Gb/s input signal. The proposed design has a small footprint of 1mm x 1mm. The system is inherently broadband with a bandwidth of over 100nm making it suitable for high-speed optical networks on chip.

The development of the time-keeping clock with TS-1 single chip microcomputer.

NASA Astrophysics Data System (ADS)

Zhou, Jiguang; Li, Yongan

The authors have developed a time-keeping clock with Intel 8751 single chip microcomputer that has been successfully used in time-keeping station. The hard-soft ware design and performance of the clock are introduced.

CHIP: Facilitating Interprofessional and Culturally Competent Patient Care Through Experiential Learning in China.

PubMed

Mu, Keli; Peck, Kirk; Jensen, Lou; Bracciano, Al; Carrico, Cathy; Feldhacker, Diana

2016-12-01

Health care professionals have advocated for educating culturally competent practitioners. Immersion in international experiences has an impact on student cultural competency and interprofessional development. The China Honors Interprofessional Program (CHIP) at a university in the Midwest is designed to increase students' cultural competency and interprofessional development. From 2009 to 2013, a total of 25 professional students including twelve occupational therapy students, ten physical therapy students and three nursing students were enrolled in the programme. Using a one group pre and posttest research design, this study evaluated the impact of CHIP on the participating students. Both quantitative and qualitative data were collected in the study. Findings of the study revealed that CHIP has impact on students' cultural competency and professional development including gaining appreciation and understanding of the contributions of other healthcare professionals and knowledge and skills in team work. The findings of the study suggested that international immersion experience such as CHIP is an important way to increase students' cultural competency and interprofessional knowledge and skills. Limitations of the study included the small sample in the study, indirect outcome measures and the possible celling effect of the instruments of the study. Future research studies should include a larger and more representative sample, direct outcome measures such as behaviour observation and more rigorous design such as prospective experimental comparison group design. Future research should also examine the long-term effects of international experience on the professional development of occupational therapy students. Copyright © 2016 John Wiley & Sons, Ltd. Copyright © 2016 John Wiley & Sons, Ltd.

Recursive Optimization of Digital Circuits

DTIC Science & Technology

1990-12-14

Obverse- Specification . . . A-23 A.14 Non-MDS Optimization of SAMPLE .. .. .. .. .. .. ..... A-24 Appendix B . BORIS Recursive Optimization System...Software ...... B -i B .1 DESIGN.S File . .... .. .. .. .. .. .. .. .. .. ... ... B -2 B .2 PARSE.S File. .. .. .. .. .. .. .. .. ... .. ... .... B -1i B .3...TABULAR.S File. .. .. .. .. .. .. ... .. ... .. ... B -22 B .4 MDS.S File. .. .. .. .. .. .. .. ... .. ... .. ...... B -28 B .5 COST.S File

Piecewise uniform conduction-like flow channels and method therefor

DOEpatents

Cummings, Eric B [Livermore, CA; Fiechtner, Gregory J [Livermore, CA

2006-02-28

A low-dispersion methodology for designing microfabricated conduction channels for on-chip electrokinetic-based systems is presented. The technique relies on trigonometric relations that apply for ideal electrokinetic flows, allowing faceted channels to be designed on chips using common drafting software and a hand calculator. Flows are rotated and stretched along the abrupt interface between adjacent regions with differing permeability. Regions bounded by interfaces form flow "prisms" that can be combined with other designed prisms to obtain a wide range of turning angles and expansion ratios while minimizing dispersion. Designs are demonstrated using two-dimensional numerical solutions of the Laplace equation.

Adjustment of multi-CCD-chip-color-camera heads

NASA Astrophysics Data System (ADS)

Guyenot, Volker; Tittelbach, Guenther; Palme, Martin

1999-09-01

The principle of beam-splitter-multi-chip cameras consists in splitting an image into differential multiple images of different spectral ranges and in distributing these onto separate black and white CCD-sensors. The resulting electrical signals from the chips are recombined to produce a high quality color picture on the monitor. Because this principle guarantees higher resolution and sensitivity in comparison to conventional single-chip camera heads, the greater effort is acceptable. Furthermore, multi-chip cameras obtain the compete spectral information for each individual object point while single-chip system must rely on interpolation. In a joint project, Fraunhofer IOF and STRACON GmbH and in future COBRA electronic GmbH develop methods for designing the optics and dichroitic mirror system of such prism color beam splitter devices. Additionally, techniques and equipment for the alignment and assembly of color beam splitter-multi-CCD-devices on the basis of gluing with UV-curable adhesives have been developed, too.

Mathematical Simulation for Integrated Linear Fresnel Spectrometer Chip

NASA Technical Reports Server (NTRS)

Park, Yeonjoon; Yoon, Hargoon; Lee, Uhn; King, Glen C.; Choi, Sang H.

2012-01-01

A miniaturized solid-state optical spectrometer chip was designed with a linear gradient-gap Fresnel grating which was mounted perpendicularly to a sensor array surface and simulated for its performance and functionality. Unlike common spectrometers which are based on Fraunhoffer diffraction with a regular periodic line grating, the new linear gradient grating Fresnel spectrometer chip can be miniaturized to a much smaller form-factor into the Fresnel regime exceeding the limit of conventional spectrometers. This mathematical calculation shows that building a tiny motionless multi-pixel microspectrometer chip which is smaller than 1 cubic millimter of optical path volume is possible. The new Fresnel spectrometer chip is proportional to the energy scale (hc/lambda), while the conventional spectrometers are proportional to the wavelength scale (lambda). We report the theoretical optical working principle and new data collection algorithm of the new Fresnel spectrometer to build a compact integrated optical chip.

[Design and Optimization of Microfluidic Chips Used for Mixing Cryoprotectants].

PubMed

Zhou, Xinli; Yi, Xingyue; Zhou, Nanfeng; Yang, Yun

2016-06-01

Microfluidic chips can be used to realize continuous cryoprotectants(CPA)loading/unloading for oocytes,reducing osmotic damage and chemical toxicity of CPA.In this study,five different Y-shape microfluidic chips were fabricated to realize the continuous CPA loading/unloading.The effects of flow rate,entrance angle,aspect ratio and turning radius of microchannels on the mixing efficiency of microfluidic chips were analyzed quantitatively.The experimental results showed that with the decrease of flow rates,the increase of aspect ratios and the decrease of turning raradius of microchannel,the mixing length decreased and the mixing velocity was promoted,while the entrance angle had little effect on the mixing efficiency.However,the operating conditions and structural parameters of the chips in practical application should be determined based on an overall consideration of CPA loading/unloading time and machining accuracy.These results would provide a reference to the application of microfluidic chip in CPA mixing.

Post-OPC verification using a full-chip pattern-based simulation verification method

NASA Astrophysics Data System (ADS)

Hung, Chi-Yuan; Wang, Ching-Heng; Ma, Cliff; Zhang, Gary

2005-11-01

In this paper, we evaluated and investigated techniques for performing fast full-chip post-OPC verification using a commercial product platform. A number of databases from several technology nodes, i.e. 0.13um, 0.11um and 90nm are used in the investigation. Although it has proven that for most cases, our OPC technology is robust in general, due to the variety of tape-outs with complicated design styles and technologies, it is difficult to develop a "complete or bullet-proof" OPC algorithm that would cover every possible layout patterns. In the evaluation, among dozens of databases, some OPC databases were found errors by Model-based post-OPC checking, which could cost significantly in manufacturing - reticle, wafer process, and more importantly the production delay. From such a full-chip OPC database verification, we have learned that optimizing OPC models and recipes on a limited set of test chip designs may not provide sufficient coverage across the range of designs to be produced in the process. And, fatal errors (such as pinch or bridge) or poor CD distribution and process-sensitive patterns may still occur. As a result, more than one reticle tape-out cycle is not uncommon to prove models and recipes that approach the center of process for a range of designs. So, we will describe a full-chip pattern-based simulation verification flow serves both OPC model and recipe development as well as post OPC verification after production release of the OPC. Lastly, we will discuss the differentiation of the new pattern-based and conventional edge-based verification tools and summarize the advantages of our new tool and methodology: 1). Accuracy: Superior inspection algorithms, down to 1nm accuracy with the new "pattern based" approach 2). High speed performance: Pattern-centric algorithms to give best full-chip inspection efficiency 3). Powerful analysis capability: Flexible error distribution, grouping, interactive viewing and hierarchical pattern extraction to narrow down to unique patterns/cells.

A Data Acquisition System Using Single-Chip Microcomputer

NASA Astrophysics Data System (ADS)

Yonyjiang, Dai; Jingkuan, Gao; Lin, Wan; Mingjia, Pi; Jingda, Nan

1989-12-01

A data acquisition system by single-chip microcomputer was designed. It is suitable to the future devlopment of the miniature tidar signal processing epuipment . The characteristics of frequecy response, SNR, D* and NEP of FM-CW CO2 coherent tidar were discussed.

A Single Chip VLSI Implementation of a QPSK/SQPSK Demodulator for a VSAT Receiver Station

NASA Technical Reports Server (NTRS)

Kwatra, S. C.; King, Brent

1995-01-01

This thesis presents a VLSI implementation of a QPSK/SQPSK demodulator. It is designed to be employed in a VSAT earth station that utilizes the FDMA/TDM link. A single chip architecture is used to enable this chip to be easily employed in the VSAT system. This demodulator contains lowpass filters, integrate and dump units, unique word detectors, a timing recovery unit, a phase recovery unit and a down conversion unit. The design stages start with a functional representation of the system by using the C programming language. Then it progresses into a register based representation using the VHDL language. The layout components are designed based on these VHDL models and simulated. Component generators are developed for the adder, multiplier, read-only memory and serial access memory in order to shorten the design time. These sub-components are then block routed to form the main components of the system. The main components are block routed to form the final demodulator.

Focusing analytes from 50 μL into 500 pL: On-chip focusing from large sample volumes using isotachophoresis.

PubMed

van Kooten, Xander F; Truman-Rosentsvit, Marianna; Kaigala, Govind V; Bercovici, Moran

2017-09-05

The use of on-chip isotachophoresis assays for diagnostic applications is often limited by the small volumes of standard microfluidic channels. Overcoming this limitation is particularly important for detection of 'discrete' biological targets (such as bacteria) at low concentrations, where the volume of processed liquid in a standard microchannel might not contain any targets. We present a novel microfluidic chip that enables ITP focusing of target analytes from initial sample volumes of 50 μL into a concentrated zone with a volume of 500 pL, corresponding to a 100,000-fold increase in mean concentration, and a 300,000-fold increase in peak concentration. We present design considerations for limiting sample dispersion in such large-volume focusing (LVF) chips and discuss the trade-off between assay time and Joule heating, which ultimately governs the scalability of LVF designs. Finally, we demonstrate a 100-fold improvement of ITP focusing performance in the LVF chip as compared to conventional microchannels, and apply this enhancement to achieve highly sensitive detection of both molecular targets (DNA, down to 10 fM) and whole bacteria (down to 100 cfu/mL).

AM06: the Associative Memory chip for the Fast TracKer in the upgraded ATLAS detector

NASA Astrophysics Data System (ADS)

Annovi, A.; Beretta, M. M.; Calderini, G.; Crescioli, F.; Frontini, L.; Liberali, V.; Shojaii, S. R.; Stabile, A.

2017-04-01

This paper describes the AM06 chip, which is a highly parallel processor for pattern recognition in the ATLAS high energy physics experiment. The AM06 contains memory banks that store data organized in 18 bit words; a group of 8 words is called "pattern". Each AM06 chip can store up to 131 072 patterns. The AM06 is a large chip, designed in 65 nm CMOS, and it combines full-custom memory arrays, standard logic cells and serializer/deserializer IP blocks at 2 Gbit/s for input/output communication. The overall silicon area is 168 mm2 and the chip contains about 421 million transistors. The AM06 receives the detector data for each event accepted by Level-1 trigger, up to 100 kHz, and it performs a track reconstruction based on hit information from channels of the ATLAS silicon detectors. Thanks to the design of a new associative memory cell and to the layout optimization, the AM06 consumption is only about 1 fJ/bit per comparison. The AM06 has been fabricated and successfully tested with a dedicated test system.

Realization of 10 GHz minus 30dB on-chip micro-optical links with Si-Ge RF bi-polar technology

NASA Astrophysics Data System (ADS)

Ogudo, Kingsley A.; Snyman, Lukas W.; Polleux, Jean-Luc; Viana, Carlos; Tegegne, Zerihun

2014-06-01

Si Avalanche based LEDs technology has been developed in the 650 -850nm wavelength regime [1, 2]. Correspondingly, small micro-dimensioned detectors with pW/μm2 sensitivity have been developed for the same wavelength range utilizing Si-Ge detector technology with detection efficiencies of up to 0.85, and with a transition frequencies of up to 80 GHz [3] A series of on-chip optical links of 50 micron length, utilizing 650 - 850 nm propagation wavelength have been designed and realized, utilizing a Si Ge radio frequency bipolar process. Micron dimensioned optical sources, waveguides and detectors were all integrated on the same chip to form a complete optical link on-chip. Avalanche based Si LEDs (Si Av LEDs), Schottky contacting, TEOS densification strategies, silicon nitride based waveguides, and state of the art Si-Ge bipolar detector technologies were used as key design strategies. Best performances show optical coupling from source to detector of up to 10GHz and - 40dBm total optical link budget loss with a potential transition frequency coupling of up to 40GHz utilizing Si Ge based LEDs. The technology is particularly suitable for application as on-chip optical links, optical MEMS and MOEMS, as well as for optical interconnects utilizing low loss, side surface, waveguide- to-optical fiber coupling. Most particularly is one of our designed waveguide which have a good core axis alignment with the optical source and yield 10GHz -30dB on-chip micro-optical links as shown in Fig 9 (c). The technology as developed has been appropriately IP protected.

Microarray labeling extension values: laboratory signatures for Affymetrix GeneChips

PubMed Central

Lee, Yun-Shien; Chen, Chun-Houh; Tsai, Chi-Neu; Tsai, Chia-Lung; Chao, Angel; Wang, Tzu-Hao

2009-01-01

Interlaboratory comparison of microarray data, even when using the same platform, imposes several challenges to scientists. RNA quality, RNA labeling efficiency, hybridization procedures and data-mining tools can all contribute variations in each laboratory. In Affymetrix GeneChips, about 11–20 different 25-mer oligonucleotides are used to measure the level of each transcript. Here, we report that ‘labeling extension values (LEVs)’, which are correlation coefficients between probe intensities and probe positions, are highly correlated with the gene expression levels (GEVs) on eukayotic Affymetrix microarray data. By analyzing LEVs and GEVs in the publicly available 2414 cel files of 20 Affymetrix microarray types covering 13 species, we found that correlations between LEVs and GEVs only exist in eukaryotic RNAs, but not in prokaryotic ones. Surprisingly, Affymetrix results of the same specimens that were analyzed in different laboratories could be clearly differentiated only by LEVs, leading to the identification of ‘laboratory signatures’. In the examined dataset, GSE10797, filtering out high-LEV genes did not compromise the discovery of biological processes that are constructed by differentially expressed genes. In conclusion, LEVs provide a new filtering parameter for microarray analysis of gene expression and it may improve the inter- and intralaboratory comparability of Affymetrix GeneChips data. PMID:19295132

Complexity and performance of on-chip biochemical assays

NASA Astrophysics Data System (ADS)

Kopf-Sill, Anne R.; Nikiforov, Theo; Bousse, Luc J.; Nagle, Rob; Parce, J. W.

1997-03-01

The use of microchips for performing biochemical processes has the potential to reduce reagent use and thus assay costs, increase throughput, and automate complex processes. We are building a multifunctional platform that provides sensing and actuation functions for a variety of microchip- based biochemical and analytical processes. Here we describe recent experiments that include on-chip dilution, reagent mixing, reaction, separation, and detection for important classes of biochemical assays. Issues in chip design and control are discussed.

Vehicle security encryption based on unlicensed encryption

NASA Astrophysics Data System (ADS)

Huang, Haomin; Song, Jing; Xu, Zhijia; Ding, Xiaoke; Deng, Wei

2018-03-01

The current vehicle key is easy to be destroyed and damage, proposing the use of elliptical encryption algorithm is improving the reliability of vehicle security system. Based on the encryption rules of elliptic curve, the chip's framework and hardware structure are designed, then the chip calculation process simulation has been analyzed by software. The simulation has been achieved the expected target. Finally, some issues pointed out in the data calculation about the chip's storage control and other modules.

Parents and the V-Chip: A Kaiser Family Foundation Survey. How Parents Feel (and What They Know) about TV, the V-Chip, and the TV Ratings System. Toplines.

ERIC Educational Resources Information Center

1999

This report presents the data from a national, random sample survey designed by the Kaiser Family Foundation and Princeton Survey Research Associates (PSRA) and conducted by PSRA by telephone between April 6-26, 1999, when 1001 parents of children ages 2-17 were interviewed about their opinions of television, the V-Chip, and the TV ratings system.…

On-Chip Magnetic Bead Manipulation and Detection Using a Magnetoresistive Sensor-Based Micro-Chip: Design Considerations and Experimental Characterization

PubMed Central

Gooneratne, Chinthaka P.; Kodzius, Rimantas; Li, Fuquan; Foulds, Ian G.; Kosel, Jürgen

2016-01-01

The remarkable advantages micro-chip platforms offer over cumbersome, time-consuming equipment currently in use for bio-analysis are well documented. In this research, a micro-chip that includes a unique magnetic actuator (MA) for the manipulation of superparamagnetic beads (SPBs), and a magnetoresistive sensor for the detection of SPBs is presented. A design methodology, which takes into account the magnetic volume of SPBs, diffusion and heat transfer phenomena, is presented with the aid of numerical analysis to optimize the parameters of the MA. The MA was employed as a magnetic flux generator and experimental analysis with commercially available COMPEL™ and Dynabeads® demonstrated the ability of the MA to precisely transport a small number of SPBs over long distances and concentrate SPBs to a sensing site for detection. Moreover, the velocities of COMPEL™ and Dynabead® SPBs were correlated to their magnetic volumes and were in good agreement with numerical model predictions. We found that 2.8 μm Dynabeads® travel faster, and can be attracted to a magnetic source from a longer distance, than 6.2 μm COMPEL™ beads at magnetic flux magnitudes of less than 10 mT. The micro-chip system could easily be integrated with electronic circuitry and microfluidic functions, paving the way for an on-chip biomolecule quantification device. PMID:27571084

On-Chip Magnetic Bead Manipulation and Detection Using a Magnetoresistive Sensor-Based Micro-Chip: Design Considerations and Experimental Characterization.

PubMed

Gooneratne, Chinthaka P; Kodzius, Rimantas; Li, Fuquan; Foulds, Ian G; Kosel, Jürgen

2016-08-26

The remarkable advantages micro-chip platforms offer over cumbersome, time-consuming equipment currently in use for bio-analysis are well documented. In this research, a micro-chip that includes a unique magnetic actuator (MA) for the manipulation of superparamagnetic beads (SPBs), and a magnetoresistive sensor for the detection of SPBs is presented. A design methodology, which takes into account the magnetic volume of SPBs, diffusion and heat transfer phenomena, is presented with the aid of numerical analysis to optimize the parameters of the MA. The MA was employed as a magnetic flux generator and experimental analysis with commercially available COMPEL™ and Dynabeads(®) demonstrated the ability of the MA to precisely transport a small number of SPBs over long distances and concentrate SPBs to a sensing site for detection. Moreover, the velocities of COMPEL™ and Dynabead(®) SPBs were correlated to their magnetic volumes and were in good agreement with numerical model predictions. We found that 2.8 μm Dynabeads(®) travel faster, and can be attracted to a magnetic source from a longer distance, than 6.2 μm COMPEL™ beads at magnetic flux magnitudes of less than 10 mT. The micro-chip system could easily be integrated with electronic circuitry and microfluidic functions, paving the way for an on-chip biomolecule quantification device.

Read-In Integrated Circuits for Large-Format Multi-Chip Emitter Arrays

DTIC Science & Technology

2015-03-31

chip has been designed and fabricated using ONSEMI C5N process to verify our approach. Keywords: Large scale arrays; Tiling; Mosaic; Abutment ...required. X and y addressing is not a sustainable and easily expanded addressing architecture nor will it work well with abutted RIICs. Abutment Method... Abutting RIICs into an array is challenging because of the precise positioning required to achieve a uniform image. This problem is a new design

Low power laser driver design in 28nm CMOS for on-chip and chip-to-chip optical interconnect

NASA Astrophysics Data System (ADS)

Belfiore, Guido; Szilagyi, Laszlo; Henker, Ronny; Ellinger, Frank

2015-09-01

This paper discusses the challenges and the trade-offs in the design of laser drivers for very-short distance optical communications. A prototype integrated circuit is designed and fabricated in 28 nm super-low-power CMOS technology. The power consumption of the transmitter is 17.2 mW excluding the VCSEL that in our test has a DC power consumption of 10 mW. The active area of the driver is only 0.0045 mm2. The driver can achieve an error-free (BER < 10 -12) electrical data-rate of 25 Gbit/s using a pseudo random bit sequence of 27 -1. When the driver is connected to the VCSEL module an open optical eye is reported at 15 Gbit/s. In the tested bias point the VCSEL module has a measured bandwidth of 10.7 GHz.

Manufacturability of the X Architecture at the 90-nm technology node

NASA Astrophysics Data System (ADS)

Smayling, Michael C.; Sarma, Robin C.; Nagata, Toshiyuki; Arora, Narain; Duane, Michael P.; Oemardani, Shiany; Shah, Santosh

2004-05-01

In this paper, we discuss the results from a test chip that demonstrate the manufacturability and integration-worthiness of the X Architecture at the 90-nm technology node. We discuss how a collaborative effort between the design and chip making communities used the current generation of mask, lithography, wafer processing, inspection and metrology equipment to create 45 degree wires in typical metal pitches for the upper layers on a 90-nm device in a production environment. Cadence Design Systems created the test structure design and chip validation tools for the project. Canon"s KrF ES3 and ArF AS2 scanners were used for the lithography. Applied Materials used its interconnect fabrication technologies to produce the multilayer copper, low-k interconnect on 300-mm wafers. The results were confirmed for critical dimension and defect levels using Applied Materials" wafer inspection and metrology systems.

Color design model of high color rendering index white-light LED module.

PubMed

Ying, Shang-Ping; Fu, Han-Kuei; Hsieh, Hsin-Hsin; Hsieh, Kun-Yang

2017-05-10

The traditional white-light light-emitting diode (LED) is packaged with a single chip and a single phosphor but has a poor color rendering index (CRI). The next-generation package comprises two chips and a single phosphor, has a high CRI, and retains high luminous efficacy. This study employs two chips and two phosphors to improve the diode's color tunability with various proportions of two phosphors and various densities of phosphor in the silicone used. A color design model is established for color fine-tuning of the white-light LED module. The maximum difference between the measured and color-design-model simulated CIE 1931 color coordinates is approximately 0.0063 around a correlated color temperature (CCT) of 2500 K. This study provides a rapid method to obtain the color fine-tuning of a white-light LED module with a high CRI and luminous efficacy.

Microcontroller-based real-time QRS detection.

PubMed

Sun, Y; Suppappola, S; Wrublewski, T A

1992-01-01

The authors describe the design of a system for real-time detection of QRS complexes in the electrocardiogram based on a single-chip microcontroller (Motorola 68HC811). A systematic analysis of the instrumentation requirements for QRS detection and of the various design techniques is also given. Detection algorithms using different nonlinear transforms for the enhancement of QRS complexes are evaluated by using the ECG database of the American Heart Association. The results show that the nonlinear transform involving multiplication of three adjacent, sign-consistent differences in the time domain gives a good performance and a quick response. When implemented with an appropriate sampling rate, this algorithm is also capable of rejecting pacemaker spikes. The eight-bit single-chip microcontroller provides sufficient throughput and shows a satisfactory performance. Implementation of multiple detection algorithms in the same system improves flexibility and reliability. The low chip count in the design also favors maintainability and cost-effectiveness.

The detection of hepatitis c virus core antigen using afm chips with immobolized aptamers.

PubMed

Pleshakova, T O; Kaysheva, A L; Bayzyanova, J М; Anashkina, А S; Uchaikin, V F; Ziborov, V S; Konev, V A; Archakov, A I; Ivanov, Y D

2018-01-01

In the present study, the possibility of hepatitis C virus core antigen (HCVcoreAg) detection in buffer solution, using atomic force microscope chip (AFM-chip) with immobilized aptamers, has been demonstrated. The target protein was detected in 1mL of solution at concentrations from 10 -10 М to 10 -13 М. The registration of aptamer/antigen complexes on the chip surface was carried out by atomic force microscopy (AFM). The further mass-spectrometric (MS) identification of AFM-registered objects on the chip surface allowed reliable identification of HCVcoreAg target protein in the complexes. Aptamers, which were designed for therapeutic purposes, have been shown to be effective in HCVcoreAg detection as probe molecules. Copyright © 2017 Elsevier B.V. All rights reserved.

Terahertz microfluidic chips for detection of amino acids in aqueous solutions

NASA Astrophysics Data System (ADS)

Su, Bo; Zhang, Cong; Fan, Ning; Zhang, Cunlin

2016-11-01

Microfluidic technology can control the fluidic thickness accurately in less than 100 micrometers. So the combination of terahertz (THz) and microfluidic technology becomes one of the most interesting directions towards biological detection. We designed microfluidic chips for terahertz spectroscopy of biological samples in aqueous solutions. Using the terahertz time-domain spectroscopy (THz-TDS) system, we experimentally measured the transmittance of the chips and the THz absorption spectra of L-threonine and L-arginine, respectively. The results indicated the feasibility of performing high sensitivity THz spectroscopy of amino acids solutions. Therefore, the microfluidic chips can realize real-time and label-free measurement for biochemistry samples in THz-TDS system.

Comparative Evaluation of Stress Distribution in Experimentally Designed Nickel-titanium Rotary Files with Varying Cross Sections: A Finite Element Analysis.

PubMed

Basheer Ahamed, Shadir Bughari; Vanajassun, Purushothaman Pranav; Rajkumar, Kothandaraman; Mahalaxmi, Sekar

2018-04-01

Single cross-sectional nickel-titanium (NiTi) rotary instruments during continuous rotations are subjected to constant and variable stresses depending on the canal anatomy. This study was intended to create 2 new experimental, theoretic single-file designs with combinations of triple U (TU), triangle (TR), and convex triangle (CT) cross sections and to compare their bending stresses in simulated root canals with a single cross-sectional instrument using finite element analysis. A 3-dimensional model of the simulated root canal with 45° curvature and NiTi files with 5 cross-sectional designs were created using Pro/ENGINEER Wildfire 4.0 software (PTC Inc, Needham, MA) and ANSYS software (version 17; ANSYS, Inc, Canonsburg, PA) for finite element analysis. The NiTi files of 3 groups had single cross-sectional shapes of CT, TR, and TU designs, and 2 experimental groups had a CT, TR, and TU (CTU) design and a TU, TR, and CT (UTC) design. The file was rotated in simulated root canals to analyze the bending stress, and the von Mises stress value for every file was recorded in MPa. Statistical analysis was performed using the Kruskal-Wallis test and the Bonferroni-adjusted Mann-Whitney test for multiple pair-wise comparison with a P value <.05 (95 %). The maximum bending stress of the rotary file was observed in the apical third of the CT design, whereas comparatively less stress was recorded in the CTU design. The TU and TR designs showed a similar stress pattern at the curvature, whereas the UTC design showed greater stress in the apical and middle thirds of the file in curved canals. All the file designs showed a statistically significant difference. The CTU designed instruments showed the least bending stress on a 45° angulated simulated root canal when compared with all the other tested designs. Copyright © 2017 American Association of Endodontists. Published by Elsevier Inc. All rights reserved.

27 CFR 5.39 - Presence of neutral spirits and coloring, flavoring, and blending materials.

Code of Federal Regulations, 2012 CFR

2012-04-01

... ___ (insert chips, slabs, etc., as appropriate)” shall be stated as a part of the class and type designation... above statement shall not apply to brandy treated with an infusion of oak chip in accordance with § 5.23...

A 1-Gigabit Memory System on a multi-Chip Module for Space Applications

NASA Technical Reports Server (NTRS)

Louie, Marianne E.; Topliffe, Douglas A.; Alkalai, Leon

1996-01-01

Current spaceborne applications desire compact, low weight, and high capacity data storage systems along with the additional requirement of radiation tolerance. This paper discusses a memory system on a multi-chip module (MCM) that is designed for space applications.

On-chip copper-dielectric interference filters for manufacturing of ambient light and proximity CMOS sensors.

PubMed

Frey, Laurent; Masarotto, Lilian; D'Aillon, Patrick Gros; Pellé, Catherine; Armand, Marilyn; Marty, Michel; Jamin-Mornet, Clémence; Lhostis, Sandrine; Le Briz, Olivier

2014-07-10

Filter technologies implemented on CMOS image sensors for spectrally selective applications often use a combination of on-chip organic resists and an external substrate with multilayer dielectric coatings. The photopic-like and near-infrared bandpass filtering functions respectively required by ambient light sensing and user proximity detection through time-of-flight can be fully integrated on chip with multilayer metal-dielectric filters. Copper, silicon nitride, and silicon oxide are the materials selected for a technological proof-of-concept on functional wafers, due to their immediate availability in front-end semiconductor fabs. Filter optical designs are optimized with respect to specific performance criteria, and the robustness of the designs regarding process errors are evaluated for industrialization purposes.

Study on a Real-Time BEAM System for Diagnosis Assistance Based on a System on Chips Design

PubMed Central

Sung, Wen-Tsai; Chen, Jui-Ho; Chang, Kung-Wei

2013-01-01

As an innovative as well as an interdisciplinary research project, this study performed an analysis of brain signals so as to establish BrainIC as an auxiliary tool for physician diagnosis. Cognition behavior sciences, embedded technology, system on chips (SOC) design and physiological signal processing are integrated in this work. Moreover, a chip is built for real-time electroencephalography (EEG) processing purposes and a Brain Electrical Activity Mapping (BEAM) system, and a knowledge database is constructed to diagnose psychosis and body challenges in learning various behaviors and signals antithesis by a fuzzy inference engine. This work is completed with a medical support system developed for the mentally disabled or the elderly abled. PMID:23681095

The optical design of 3D ICs for smartphone and optro-electronics sensing module

NASA Astrophysics Data System (ADS)

Huang, Jiun-Woei

2018-03-01

Smartphone require limit space for image system, current lens, used in smartphones are refractive type, the effective focal length is limited the thickness of phone physical size. Other, such as optro-electronics sensing chips, proximity optical sensors, and UV indexer chips are integrated into smart phone with limit space. Due to the requirement of multiple lens in smartphone, proximity optical sensors, UV indexer and other optro-electronics sensing chips in a limited space of CPU board in future smart phone, optro-electronics 3D IC's integrated with optical lens or components may be a key technology for 3 C products. A design for reflective lens is fitted to CMOS, proximity optical sensors, UV indexer and other optro-electronics sensing chips based on 3-D IC. The reflective lens can be threes times of effective focal lens, and be able to resolve small object. The system will be assembled and integrated in one 3-D IC more easily.

A CMOS Imager with Focal Plane Compression using Predictive Coding

NASA Technical Reports Server (NTRS)

Leon-Salas, Walter D.; Balkir, Sina; Sayood, Khalid; Schemm, Nathan; Hoffman, Michael W.

2007-01-01

This paper presents a CMOS image sensor with focal-plane compression. The design has a column-level architecture and it is based on predictive coding techniques for image decorrelation. The prediction operations are performed in the analog domain to avoid quantization noise and to decrease the area complexity of the circuit, The prediction residuals are quantized and encoded by a joint quantizer/coder circuit. To save area resources, the joint quantizerlcoder circuit exploits common circuitry between a single-slope analog-to-digital converter (ADC) and a Golomb-Rice entropy coder. This combination of ADC and encoder allows the integration of the entropy coder at the column level. A prototype chip was fabricated in a 0.35 pm CMOS process. The output of the chip is a compressed bit stream. The test chip occupies a silicon area of 2.60 mm x 5.96 mm which includes an 80 X 44 APS array. Tests of the fabricated chip demonstrate the validity of the design.

Design of a 40-nm CMOS integrated on-chip oscilloscope for 5-50 GHz spin wave characterization

NASA Astrophysics Data System (ADS)

Egel, Eugen; Csaba, György; Dietz, Andreas; Breitkreutz-von Gamm, Stephan; Russer, Johannes; Russer, Peter; Kreupl, Franz; Becherer, Markus

2018-05-01

Spin wave (SW) devices are receiving growing attention in research as a strong candidate for low power applications in the beyond-CMOS era. All SW applications would require an efficient, low power, on-chip read-out circuitry. Thus, we provide a concept for an on-chip oscilloscope (OCO) allowing parallel detection of the SWs at different frequencies. The readout system is designed in 40-nm CMOS technology and is capable of SW device characterization. First, the SWs are picked up by near field loop antennas, placed below yttrium iron garnet (YIG) film, and amplified by a low noise amplifier (LNA). Second, a mixer down-converts the radio frequency (RF) signal of 5 - 50 GHz to lower intermediate frequencies (IF) around 10 - 50 MHz. Finally, the IF signal can be digitized and analyzed regarding the frequency, amplitude and phase variation of the SWs. The power consumption and chip area of the whole OCO are estimated to 166.4 mW and 1.31 mm2, respectively.

An analog silicon retina with multichip configuration.

PubMed

Kameda, Seiji; Yagi, Tetsuya

2006-01-01

The neuromorphic silicon retina is a novel analog very large scale integrated circuit that emulates the structure and the function of the retinal neuronal circuit. We fabricated a neuromorphic silicon retina, in which sample/hold circuits were embedded to generate fluctuation-suppressed outputs in the previous study [1]. The applications of this silicon retina, however, are limited because of a low spatial resolution and computational variability. In this paper, we have fabricated a multichip silicon retina in which the functional network circuits are divided into two chips: the photoreceptor network chip (P chip) and the horizontal cell network chip (H chip). The output images of the P chip are transferred to the H chip with analog voltages through the line-parallel transfer bus. The sample/hold circuits embedded in the P and H chips compensate for the pattern noise generated on the circuits, including the analog communication pathway. Using the multichip silicon retina together with an off-chip differential amplifier, spatial filtering of the image with an odd- and an even-symmetric orientation selective receptive fields was carried out in real time. The analog data transfer method in the present multichip silicon retina is useful to design analog neuromorphic multichip systems that mimic the hierarchical structure of neuronal networks in the visual system.

Reliability study of high-brightness multiple single emitter diode lasers

NASA Astrophysics Data System (ADS)

Zhu, Jing; Yang, Thomas; Zhang, Cuipeng; Lang, Chao; Jiang, Xiaochen; Liu, Rui; Gao, Yanyan; Guo, Weirong; Jiang, Yuhua; Liu, Yang; Zhang, Luyan; Chen, Louisa

2015-03-01

In this study the chip bonding processes for various chips from various chip suppliers around the world have been optimized to achieve reliable chip on sub-mount for high performance. These chip on sub-mounts, for examples, includes three types of bonding, 8xx nm-1.2W/10.0W Indium bonded lasers, 9xx nm 10W-20W AuSn bonded lasers and 1470 nm 6W Indium bonded lasers will be reported below. The MTTF@25 of 9xx nm chip on sub-mount (COS) is calculated to be more than 203,896 hours. These chips from various chip suppliers are packaged into many multiple single emitter laser modules, using similar packaging techniques from 2 emitters per module to up to 7 emitters per module. A reliability study including aging test is performed on those multiple single emitter laser modules. With research team's 12 years' experienced packaging design and techniques, precise optical and fiber alignment processes and superior chip bonding capability, we have achieved a total MTTF exceeding 177,710 hours of life time with 60% confidence level for those multiple single emitter laser modules. Furthermore, a separated reliability study on wavelength stabilized laser modules have shown this wavelength stabilized module packaging process is reliable as well.

A volumetric meter chip for point-of-care quantitative detection of bovine catalase for food safety control.

PubMed

Cui, Xingye; Hu, Jie; Choi, Jane Ru; Huang, Yalin; Wang, Xuemin; Lu, Tian Jian; Xu, Feng

2016-09-07

A volumetric meter chip was developed for quantitative point-of-care (POC) analysis of bovine catalase, a bioindicator of bovine mastitis, in milk samples. The meter chip displays multiplexed quantitative results by presenting the distance of ink bar advancement that is detectable by the naked eye. The meter chip comprises a poly(methyl methacrylate) (PMMA) layer, a double-sided adhesive (DSA) layer and a glass slide layer fabricated by the laser-etching method, which is typically simple, rapid (∼3 min per chip), and cost effective (∼$0.2 per chip). Specially designed "U shape" reaction cells are covered by an adhesive tape that serves as an on-off switch, enabling the simple operation of the assay. As a proof of concept, we employed the developed meter chip for the quantification of bovine catalase in raw milk samples to detect catalase concentrations as low as 20 μg/mL. The meter chip has great potential to detect various target analytes for a wide range of POC applications. Copyright © 2016 Elsevier B.V. All rights reserved.

ChIP-chip.

PubMed

Kim, Tae Hoon; Dekker, Job

2018-05-01

ChIP-chip can be used to analyze protein-DNA interactions in a region-wide and genome-wide manner. DNA microarrays contain PCR products or oligonucleotide probes that are designed to represent genomic sequences. Identification of genomic sites that interact with a specific protein is based on competitive hybridization of the ChIP-enriched DNA and the input DNA to DNA microarrays. The ChIP-chip protocol can be divided into two main sections: Amplification of ChIP DNA and hybridization of ChIP DNA to arrays. A large amount of DNA is required to hybridize to DNA arrays, and hybridization to a set of multiple commercial arrays that represent the entire human genome requires two rounds of PCR amplifications. The relative hybridization intensity of ChIP DNA and that of the input DNA is used to determine whether the probe sequence is a potential site of protein-DNA interaction. Resolution of actual genomic sites bound by the protein is dependent on the size of the chromatin and on the genomic distance between the probes on the array. As with expression profiling using gene chips, ChIP-chip experiments require multiple replicates for reliable statistical measure of protein-DNA interactions. © 2018 Cold Spring Harbor Laboratory Press.

Using pattern enumeration to accelerate process development and ramp yield

NASA Astrophysics Data System (ADS)

Zhuang, Linda; Pang, Jenny; Xu, Jessy; Tsai, Mengfeng; Wang, Amy; Zhang, Yifan; Sweis, Jason; Lai, Ya-Chieh; Ding, Hua

2016-03-01

During a new technology node process setup phase, foundries do not initially have enough product chip designs to conduct exhaustive process development. Different operational teams use manually designed simple test keys to set up their process flows and recipes. When the very first version of the design rule manual (DRM) is ready, foundries enter the process development phase where new experiment design data is manually created based on these design rules. However, these IP/test keys contain very uniform or simple design structures. This kind of design normally does not contain critical design structures or process unfriendly design patterns that pass design rule checks but are found to be less manufacturable. It is desired to have a method to generate exhaustive test patterns allowed by design rules at development stage to verify the gap of design rule and process. This paper presents a novel method of how to generate test key patterns which contain known problematic patterns as well as any constructs which designers could possibly draw based on current design rules. The enumerated test key patterns will contain the most critical design structures which are allowed by any particular design rule. A layout profiling method is used to do design chip analysis in order to find potential weak points on new incoming products so fab can take preemptive action to avoid yield loss. It can be achieved by comparing different products and leveraging the knowledge learned from previous manufactured chips to find possible yield detractors.

The use of low resistivity substrates for optimal noise reduction, ground referencing, and current conduction in mixed signal ASICs

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zimmerman, T.

1997-12-01

This paper is distilled from a talk given at the 3rd International Meeting on Front End Electronics in Taos, N.M. on Nov. 7,1997. It is based on experience gained by designing and testing the SVX3 128 channel silicon strip detector readout chip. The SVX3 chip organization is shown in Fig. 1. The Front End section consists of an integrator and analog pipeline designed at Fermilab, and the Back End section is an ADC plus sparsification and readout logic designed at LBL. SVX3 is a deadtimeless readout chip, which means that the front end is acquiring low level analog signals whilemore » the back end is digitizing and reading out digital signals. It is thus a true mixed signal chip, and demands close attention to avoid disastrous coupling from the digital to the analog sections. SVX3 is designed in a bulk CMOS process (i.e., the circuits sit in a silicon substrate). In such a process, the substrate becomes a potential coupling path. This paper discusses the effect of the substrate resistivity on coupling, and also goes into a more general discussion of grounding and referencing in mixed signal designs and how low resistivity substrates can be used to advantage. Finally, an alternative power supply current conduction method for ASICs is presented as an additional advantage which can be obtained with low resistivity substrates. 1 ref., 13 figs., 1 tab.« less

Hybrid UV Imager Containing Face-Up AlGaN/GaN Photodiodes

NASA Technical Reports Server (NTRS)

Zheng, Xinyu; Pain, Bedabrata

2005-01-01

A proposed hybrid ultraviolet (UV) image sensor would comprise a planar membrane array of face-up AlGaN/GaN photodiodes integrated with a complementary metal oxide/semiconductor (CMOS) readout-circuit chip. Each pixel in the hybrid image sensor would contain a UV photodiode on the AlGaN/GaN membrane, metal oxide/semiconductor field-effect transistor (MOSFET) readout circuitry on the CMOS chip underneath the photodiode, and a metal via connection between the photodiode and the readout circuitry (see figure). The proposed sensor design would offer all the advantages of comparable prior CMOS active-pixel sensors and AlGaN UV detectors while overcoming some of the limitations of prior (AlGaN/sapphire)/CMOS hybrid image sensors that have been designed and fabricated according to the methodology of flip-chip integration. AlGaN is a nearly ideal UV-detector material because its bandgap is wide and adjustable and it offers the potential to attain extremely low dark current. Integration of AlGaN with CMOS is necessary because at present there are no practical means of realizing readout circuitry in the AlGaN/GaN material system, whereas the means of realizing readout circuitry in CMOS are well established. In one variant of the flip-chip approach to integration, an AlGaN chip on a sapphire substrate is inverted (flipped) and then bump-bonded to a CMOS readout circuit chip; this variant results in poor quantum efficiency. In another variant of the flip-chip approach, an AlGaN chip on a crystalline AlN substrate would be bonded to a CMOS readout circuit chip; this variant is expected to result in narrow spectral response, which would be undesirable in many applications. Two other major disadvantages of flip-chip integration are large pixel size (a consequence of the need to devote sufficient area to each bump bond) and severe restriction on the photodetector structure. The membrane array of AlGaN/GaN photodiodes and the CMOS readout circuit for the proposed image sensor would be fabricated separately.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nabeel A. Riza

The goals of the first six months of this project were to lay the foundations for both the SiC front-end optical chip fabrication as well as the free-space laser beam interferometer designs and preliminary tests. In addition, a Phase I goal was to design and experimentally build the high temperature and pressure infrastructure and test systems that will be used in the next 6 months for proposed sensor experimentation and data processing. All these goals have been achieved and are described in detail in the report. Both design process and diagrams for the mechanical elements as well as the opticalmore » systems are provided. In addition, photographs of the fabricated SiC optical chips, the high temperature & pressure test chamber instrument, the optical interferometer, the SiC sample chip holder, and signal processing data are provided. The design and experimentation results are summarized to give positive conclusions on the proposed novel high temperature optical sensor technology. The goals of the second six months of this project were to conduct high temperature sensing tests using the test chamber and optical sensing instrument designs developed in the first part of the project. In addition, a Phase I goal was to develop the basic processing theory and physics for the proposed first sensor experimentation and data processing. All these goals have been achieved and are described in detail. Both optical experimental design process and sensed temperature are provided. In addition, photographs of the fabricated SiC optical chips after deployment in the high temperature test chamber are shown from a material study point-of-view.« less

Development of CMOS Active Pixel Image Sensors for Low Cost Commercial Applications

NASA Technical Reports Server (NTRS)

Fossum, E.; Gee, R.; Kemeny, S.; Kim, Q.; Mendis, S.; Nakamura, J.; Nixon, R.; Ortiz, M.; Pain, B.; Zhou, Z.;

Test probe for surface mounted leadless chip carrier

DOEpatents

Meyer, Kerry L.; Topolewski, John

1989-05-23

A test probe for a surface mounted leadless chip carrier is disclosed. The probed includes specially designed connector pins which allow size reductions in the probe. A thermoplastic housing provides spring action to ensure good mechanical and electrical contact between the pins and the contact strips of a leadless chip carrier. Other features include flexible wires molded into the housing and two different types of pins alternately placed in the housing. These features allow fabrication of a smaller and simpler test probe.

Test probe for surface mounted leadless chip carrier

DOEpatents

Meyer, K.L.; Topolewski, J.

1987-10-02

A test probe for a surface mounted leadless chip carrier is disclosed. The probe includes specially designed connector pins which allow size reductions in the probe. A thermoplastic housing provides spring action to ensure good mechanical and electrical contact between the pins and the contact strips of a leadless chip carrier. Other features include flexible wires molded into the housing and two different types of pins alternately placed in the housing. These features allow fabrication of a smaller and simpler test probe. 1 fig.

Computer Algorithms and Architectures for Three-Dimensional Eddy-Current Nondestructive Evaluation. Volume 3. Chapters 6-11

DTIC Science & Technology

1989-01-20

addressable memory can be loaded or off- loaded as the number crunching continues. Modem VLSI processors can often process data faster than today’s...Available DSP Chips Texas Instruments was one of the first serious manufacturers of DSP chips. With the Texas Instruments TMS310 DSP chip, modem , voice...Can handle double presicion data types. Texas Instruments TMS32010 T’s first-generation DSP design: a fixed-point DSP that has found its way into modem

Develop draft chip seal cover aggregate specification based on AIMS angularity, shape and texture test results.

DOT National Transportation Integrated Search

2013-03-01

The objective of the study is to improve Oklahoma Department of Transportation (ODOT) chip : seal design and performance through introducing new criteria for the selection of cover : aggregate and binder. These criteria will be based upon the recent ...

System-on-Chip Design and Implementation

ERIC Educational Resources Information Center

Brackenbury, L. E. M.; Plana, L. A.; Pepper, J.

2010-01-01

The system-on-chip module described here builds on a grounding in digital hardware and system architecture. It is thus appropriate for third-year undergraduate computer science and computer engineering students, for post-graduate students, and as a training opportunity for post-graduate research students. The course incorporates significant…

Stress analysis of ultra-thin silicon chip-on-foil electronic assembly under bending

NASA Astrophysics Data System (ADS)

Wacker, Nicoleta; Richter, Harald; Hoang, Tu; Gazdzicki, Pawel; Schulze, Mathias; Angelopoulos, Evangelos A.; Hassan, Mahadi-Ul; Burghartz, Joachim N.

2014-09-01

In this paper we investigate the bending-induced uniaxial stress at the top of ultra-thin (thickness \\leqslant 20 μm) single-crystal silicon (Si) chips adhesively attached with the aid of an epoxy glue to soft polymeric substrate through combined theoretical and experimental methods. Stress is first determined analytically and numerically using dedicated models. The theoretical results are validated experimentally through piezoresistive measurements performed on complementary metal-oxide-semiconductor (CMOS) transistors built on specially designed chips, and through micro-Raman spectroscopy investigation. Stress analysis of strained ultra-thin chips with CMOS circuitry is crucial, not only for the accurate evaluation of the piezoresistive behavior of the built-in devices and circuits, but also for reliability and deformability analysis. The results reveal an uneven bending-induced stress distribution at the top of the Si-chip that decreases from the central area towards the chip's edges along the bending direction, and increases towards the other edges. Near these edges, stress can reach very high values, facilitating the emergence of cracks causing ultimate chip failure.

Characterisation of capacitively coupled HV/HR-CMOS sensor chips for the CLIC vertex detector

NASA Astrophysics Data System (ADS)

Kremastiotis, I.

2017-12-01

The capacitive coupling between an active sensor and a readout ASIC has been considered in the framework of the CLIC vertex detector study. The CLICpix Capacitively Coupled Pixel Detector (C3PD) is a High-Voltage CMOS sensor chip produced in a commercial 180 nm HV-CMOS process for this purpose. The sensor was designed to be connected to the CLICpix2 readout chip. It therefore matches the dimensions of the readout chip, featuring a matrix of 128×128 square pixels with 25μm pitch. The sensor chip has been produced with the standard value for the substrate resistivity (~20 Ωcm) and it has been characterised in standalone testing mode, before receiving and testing capacitively coupled assemblies. The standalone measurement results show a rise time of ~20 ns for a power consumption of 5μW/pixel. Production of the C3PD HV-CMOS sensor chip with higher substrate resistivity wafers (~20, 80, 200 and 1000 Ωcm) is foreseen. The expected benefits of the higher substrate resistivity will be studied using future assemblies with the readout chip.

3D gut-liver chip with a PK model for prediction of first-pass metabolism.

PubMed

Lee, Dong Wook; Ha, Sang Keun; Choi, Inwook; Sung, Jong Hwan

2017-11-07

Accurate prediction of first-pass metabolism is essential for improving the time and cost efficiency of drug development process. Here, we have developed a microfluidic gut-liver co-culture chip that aims to reproduce the first-pass metabolism of oral drugs. This chip consists of two separate layers for gut (Caco-2) and liver (HepG2) cell lines, where cells can be co-cultured in both 2D and 3D forms. Both cell lines were maintained well in the chip, verified by confocal microscopy and measurement of hepatic enzyme activity. We investigated the PK profile of paracetamol in the chip, and corresponding PK model was constructed, which was used to predict PK profiles for different chip design parameters. Simulation results implied that a larger absorption surface area and a higher metabolic capacity are required to reproduce the in vivo PK profile of paracetamol more accurately. Our study suggests the possibility of reproducing the human PK profile on a chip, contributing to accurate prediction of pharmacological effect of drugs.

Development of the Large-Scale Oligonucleotide Chip for the Diagnosis of Plant Viruses and its Practical Use

PubMed Central

Nam, Moon; Kim, Jeong-Seon; Lim, Seungmo; Park, Chung Youl; Kim, Jeong-Gyu; Choi, Hong-Soo; Lim, Hyoun-Sub; Moon, Jae Sun; Lee, Su-Heon

2014-01-01

A large-scale oligonucleotide (LSON) chip was developed for the detection of the plant viruses with known genetic information. The LSON chip contains two sets of 3,978 probes for 538 species of targets including plant viruses, satellite RNAs and viroids. A hundred forty thousand probes, consisting of isolate-, species- and genus-specific probes respectively, are designed from 20,000 of independent nucleotide sequence of plant viruses. Based on the economic importance, the amount of genome information, and the number of strains and/or isolates, one to fifty-one probes for each target virus are selected and spotted on the chip. The standard and field samples for the analysis of the LSON chip have been prepared and tested by RT-PCR. The probe’s specific and/or nonspecific reaction patterns by LSON chip allow us to diagnose the unidentified viruses. Thus, the LSON chip in this study could be highly useful for the detection of unexpected plant viruses, the monitoring of emerging viruses and the fluctuation of the population of major viruses in each plant. PMID:25288985

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nabeel A. Riza

The goals of the this part of the Continuation Phase 2 period (Oct. 1, 06 to March 31, 07) of this project were to (a) fabricate laser-doped SiC wafers and start testing the SiC chips for individual gas species sensing under high temperature and pressure conditions and (b) demonstrate the designs and workings of a temperature probe suited for industrial power generation turbine environment. A focus of the reported work done via Kar UCF LAMP lab. is to fabricate the embedded optical phase or doped microstructures based SiC chips, namely, Chromium (C), Boron (B) and Aluminum (Al) doped 4H-SiC, andmore » to eventually deploy such laser-doped chips to enable gas species sensing under high temperature and pressure. Experimental data is provided from SiC chip optical response for various gas species such as pure N2 and mixtures of N2 and H{sub 2}, N{sub 2} and CO, N{sub 2} and CO{sub 2}, and N{sub 2} and CH{sub 4}. Another main focus of the reported work was a temperature sensor probe assembly design and initial testing. The probe transmit-receive fiber optics were designed and tested for electrically controlled alignment. This probe design was provided to overcome mechanical vibrations in typical industrial scenarios. All these goals have been achieved and are described in detail in the report.« less

Explosively Joining Dissimilar Metal Tubes.

DTIC Science & Technology

1979-11-01

specimens were tested in axial tension-tension fatigue in a Satec high cycle fatigue test machine at 30 Hz. The applied max stress for each test was...BACK CHIP A3 ROTARY FILE ,S AR .STO P9 WIRE BRUSH y es IDENTIFY {STEEL STAMP) N INSPECT ICA) YES GRIND WEtD [LEID k R IJ CA/S. BASE METAL PPEPARATION...Type: Dog bone Test Equipment: Satec SF-1U-1099 Specimen Max. Static Dynamic F a i1 u r e Width Thickness i(No.) Stress Stress Stress(KS0 (KSI) (KSI

Gene Expression Dynamics Inspector (GEDI): for integrative analysis of expression profiles

NASA Technical Reports Server (NTRS)

Eichler, Gabriel S.; Huang, Sui; Ingber, Donald E.

2003-01-01

Genome-wide expression profiles contain global patterns that evade visual detection in current gene clustering analysis. Here, a Gene Expression Dynamics Inspector (GEDI) is described that uses self-organizing maps to translate high-dimensional expression profiles of time courses or sample classes into animated, coherent and robust mosaics images. GEDI facilitates identification of interesting patterns of molecular activity simultaneously across gene, time and sample space without prior assumption of any structure in the data, and then permits the user to retrieve genes of interest. Important changes in genome-wide activities may be quickly identified based on 'Gestalt' recognition and hence, GEDI may be especially useful for non-specialist end users, such as physicians. AVAILABILITY: GEDI v1.0 is written in Matlab, and binary Matlab.dll files which require Matlab to run can be downloaded for free by academic institutions at http://www.chip.org/ge/gedihome.html Supplementary information: http://www.chip.org/ge/gedihome.html.

A Wireless Biomedical Signal Interface System-on-Chip for Body Sensor Networks.

PubMed

Lei Wang; Guang-Zhong Yang; Jin Huang; Jinyong Zhang; Li Yu; Zedong Nie; Cumming, D R S

2010-04-01

Recent years have seen the rapid development of biosensor technology, system-on-chip design, wireless technology. and ubiquitous computing. When assembled into an autonomous body sensor network (BSN), the technologies become powerful tools in well-being monitoring, medical diagnostics, and personal connectivity. In this paper, we describe the first demonstration of a fully customized mixed-signal silicon chip that has most of the attributes required for use in a wearable or implantable BSN. Our intellectual-property blocks include low-power analog sensor interface for temperature and pH, a data multiplexing and conversion module, a digital platform based around an 8-b microcontroller, data encoding for spread-spectrum wireless transmission, and a RF section requiring very few off-chip components. The chip has been fully evaluated and tested by connection to external sensors, and it satisfied typical system requirements.

Lab-on-a-Chip

NASA Technical Reports Server (NTRS)

2004-01-01

Labs on chips are manufactured in many shapes and sizes and can be used for numerous applications, from medical tests to water quality monitoring to detecting the signatures of life on other planets. The eight holes on this chip are actually ports that can be filled with fluids or chemicals. Tiny valves control the chemical processes by mixing fluids that move in the tiny channels that look like lines, connecting the ports. Scientists at NASA's Marshall Space Flight Center (MSFC) in Huntsville, Alabama designed this chip to grow biological crystals on the International Space Station. Through this research, they discovered that this technology is ideally suited for solving the challenges of the Vision for Space Exploration. For example, thousands of chips the size of dimes could be loaded on a Martian rover looking for biosignatures of past or present life. Other types of chips could be placed in handheld devices used to monitor microbes in water or to quickly conduct medical tests on astronauts. (NASA/MSFC/D.Stoffer)

ASIC-based architecture for the real-time computation of 2D convolution with large kernel size

NASA Astrophysics Data System (ADS)

Shao, Rui; Zhong, Sheng; Yan, Luxin

2015-12-01

Bidimensional convolution is a low-level processing algorithm of interest in many areas, but its high computational cost constrains the size of the kernels, especially in real-time embedded systems. This paper presents a hardware architecture for the ASIC-based implementation of 2-D convolution with medium-large kernels. Aiming to improve the efficiency of storage resources on-chip, reducing off-chip bandwidth of these two issues, proposed construction of a data cache reuse. Multi-block SPRAM to cross cached images and the on-chip ping-pong operation takes full advantage of the data convolution calculation reuse, design a new ASIC data scheduling scheme and overall architecture. Experimental results show that the structure can achieve 40× 32 size of template real-time convolution operations, and improve the utilization of on-chip memory bandwidth and on-chip memory resources, the experimental results show that the structure satisfies the conditions to maximize data throughput output , reducing the need for off-chip memory bandwidth.

Develop draft chip seal cover aggregate specification based on aggregate imaging system (AIMS) angularity, shape, and texture test results : final report.

DOT National Transportation Integrated Search

2014-01-01

The objective of the study is to improve Oklahoma Department of Transportation (ODOT) chip seal design and performance through introducing new criteria for the selection of cover aggregate and binder. The study evaluates the shape and texture-related...

Standby Power Management Architecture for Deep-Submicron Systems

DTIC Science & Technology

2006-05-19

Driver 61 5.1 Quark PicoNode System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5.2 Power Domain Architecture... Quark system protocol stack. . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.2 Quark system block diagram...the implementation of the chip using an industry-standard place and route design flow. Lastly some measurements from the chip are presented. 5.1 Quark

A Fast Turn-Around Facility for Very Large Scale Integration (VLSI)

DTIC Science & Technology

1982-06-01

statistics determination, the first test mask set will use the MATRIX chip design which was recently developed here at Stanford. This chip provides...reached when the basewidth is reduced to zero. Such devices, variably known as depleted- base transistors or bipolar static-induction transitors , have been

On-chip optical diode based on silicon photonic crystal heterojunctions.

PubMed

Wang, Chen; Zhou, Chang-Zhu; Li, Zhi-Yuan

2011-12-19

Optical isolation is a long pursued object with fundamental difficulty in integrated photonics. As a step towards this goal, we demonstrate the design, fabrication, and characterization of on-chip wavelength-scale optical diodes that are made from the heterojunction between two different silicon two-dimensional square-lattice photonic crystal slabs with directional bandgap mismatch and different mode transitions. The measured transmission spectra show considerable unidirectional transmission behavior, in good agreement with numerical simulations. The experimental realization of on-chip optical diodes with wavelength-scale size using all-dielectric, passive, and linear silicon photonic crystal structures may help to construct on-chip optical logical devices without nonlinearity or magnetism, and would open up a road towards photonic computers.

Design of Simple Landslide Monitoring System

NASA Astrophysics Data System (ADS)

Meng, Qingjia; Cai, Lingling

2018-01-01

The simple landslide monitoring system is mainly designed for slope, collapse body and surface crack. In the harsh environment, the dynamic displacement data of the disaster body is transmitted to the terminal acquisition system in real time. The main body of the system adopt is PIC32MX795F512. This chip is to realize low power design, wakes the system up through the clock chip, and turns on the switching power supply at set time, which makes the wireless transmission module running during the interval to ensure the maximum battery consumption, so that the system can be stable long term work.

Aspects on Transfer of Aided - Design Files

NASA Astrophysics Data System (ADS)

Goanta, A. M.; Anghelache, D. G.

2016-08-01

At this stage of development of hardware and software, each company that makes design software packages has a certain type of file created and customized in time to distinguish that company from its competitors. Thus today are widely known the DWG files belonging AutoCAD, IPT / IAM belonging to Inventor, PAR / ASM of Solid Edge's, PRT from the NX and so on. Behind every type of file there is a mathematical model which is common to more types of files. A specific aspect of the computer -aided design is that all softwares are working with both individual parts and assemblies, but their approach is different in that some use the same type of file both for each part and for the whole (PRT ), while others use different types of files (IPT / IAM, PAR / ASM, etc.). Another aspect of the computer -aided design is to transfer files between different companies which use different software packages or even the same software package but in different versions. Each of these situations generates distinct issues. Thus, to solve the partial reading by a project different from the native one, transfer files of STEP and IGES type are used

ATLAS, an integrated structural analysis and design system. Volume 4: Random access file catalog

NASA Technical Reports Server (NTRS)

Gray, F. P., Jr. (Editor)

1979-01-01

A complete catalog is presented for the random access files used by the ATLAS integrated structural analysis and design system. ATLAS consists of several technical computation modules which output data matrices to corresponding random access file. A description of the matrices written on these files is contained herein.

Indium phosphide-based monolithically integrated PIN waveguide photodiode readout for resonant cantilever sensors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Siwak, N. P.; Laboratory for the Physical Sciences, 8050 Greenmead Drive, College Park, Maryland 20740; Fan, X. Z.

2014-10-06

An integrated photodiode displacement readout scheme for a microelectromechanical cantilever waveguide resonator sensing platform is presented. III-V semiconductors are used to enable the monolithic integration of passive waveguides with active optical components. This work builds upon previously demonstrated results by measuring the displacement of cantilever waveguide resonators with on-chip waveguide PIN photodiodes. The on-chip integration of the readout provides an additional 70% improvement in mass sensitivity compared to off-chip photodetector designs due to measurement stability and minimized coupling loss. In addition to increased measurement stability, reduced packaging complexity is achieved due to the simplicity of the readout design. We havemore » fabricated cantilever waveguides with integrated photodetectors and experimentally characterized these cantilever sensors with monolithically integrated PIN photodiodes.« less

Design of standard operating procedure production proceses (case study on the home industry Bedugul Baturiti Tabanan Bali)

NASA Astrophysics Data System (ADS)

Kasiani; Suhantono, Djoko; Mirah Kencanawati, AAA

2018-01-01

Candikuning is part of the district of Baturiti, tourism village, better known by the name of Bedugul. No less interesting is the variety of chips produced by two partner groups as a souvenir after the tour, such as Chips: Spinach; beans; Tempeh. The purpose of this research were to design a Standard Operating Procedure (SOP): Production Processes on the Home Industry Bedugul Baturiti Tabanan Bali. The data technic collected use: observation; Documentation; and then interview to collect information. The data analysis technic done by using the Miles & Huberman. Result this research that the draft SOP: Production Processes Chips (Menu). The conclusion in this research SOP Production Processes use with flowchart and description on the Home Industry Bedugul Baturiti Tabanan Bali.

An Integrated Microfabricated Chip with Double Functions as an Ion Source and Air Pump Based on LIGA Technology

PubMed Central

Li, Hua; Jiang, Linxiu; Guo, Chaoqun; Zhu, Jianmin; Jiang, Yongrong; Chen, Zhencheng

2017-01-01

The injection and ionization of volatile organic compounds (VOA) by an integrated chip is experimentally analyzed in this paper. The integrated chip consists of a needle-to-cylinder electrode mounting on the Polymethyl Methacrylate (PMMA) substrate. The needle-to-cylinder electrode is designed and fabricated by Lithographie, Galvanoformung and Abformung (LIGA) technology. In this paper, the needle is connected to a negative power supply of −5 kV and used as the cathode; the cylinder electrodes are composed of two arrays of cylinders and serve as the anode. The ionic wind is produced based on corona and glow discharges of needle-to-cylinder electrodes. The experimental setup is designed to observe the properties of the needle-to-cylinder discharge and prove its functions as an ion source and air pump. In summary, the main results are as follows: (1) the ionic wind velocity produced by the chip is about 0.79 m/s at an applied voltage of −3300 V; (2) acetic acid and ammonia water can be injected through the chip, which is proved by pH test paper; and (3) the current measured by a Faraday cup is about 10 pA for acetic acid and ammonia with an applied voltage of −3185 V. The integrated chip is promising for portable analytical instruments, such as ion mobility spectrometry (IMS), field asymmetric ion mobility spectrometry (FAIMS), and mass spectrometry (MS). PMID:28054980

An Integrated Microfabricated Chip with Double Functions as an Ion Source and Air Pump Based on LIGA Technology.

PubMed

Li, Hua; Jiang, Linxiu; Guo, Chaoqun; Zhu, Jianmin; Jiang, Yongrong; Chen, Zhencheng

2017-01-04

The injection and ionization of volatile organic compounds (VOA) by an integrated chip is experimentally analyzed in this paper. The integrated chip consists of a needle-to-cylinder electrode mounting on the Polymethyl Methacrylate (PMMA) substrate. The needle-to-cylinder electrode is designed and fabricated by Lithographie, Galvanoformung and Abformung (LIGA) technology. In this paper, the needle is connected to a negative power supply of -5 kV and used as the cathode; the cylinder electrodes are composed of two arrays of cylinders and serve as the anode. The ionic wind is produced based on corona and glow discharges of needle-to-cylinder electrodes. The experimental setup is designed to observe the properties of the needle-to-cylinder discharge and prove its functions as an ion source and air pump. In summary, the main results are as follows: (1) the ionic wind velocity produced by the chip is about 0.79 m/s at an applied voltage of -3300 V; (2) acetic acid and ammonia water can be injected through the chip, which is proved by pH test paper; and (3) the current measured by a Faraday cup is about 10 pA for acetic acid and ammonia with an applied voltage of -3185 V. The integrated chip is promising for portable analytical instruments, such as ion mobility spectrometry (IMS), field asymmetric ion mobility spectrometry (FAIMS), and mass spectrometry (MS).

Microfluidic magnetic bead conveyor belt.

PubMed

van Pelt, Stijn; Frijns, Arjan; den Toonder, Jaap

2017-11-07

Magnetic beads play an important role in the miniaturization of clinical diagnostics systems. In lab-on-chip platforms, beads can be made to link to a target species and can then be used for the manipulation and detection of this species. Current bead actuation systems utilize complex on-chip coil systems that offer low field strengths and little versatility. We demonstrate a novel system based on an external rotating magnetic field and on-chip soft-magnetic structures to focus the field locally. These structures were designed and optimized using finite element simulations in order to create a number of local flux density maxima. These maxima, to which the magnetic beads are attracted, move over the chip surface in a continuous way together with the rotation of the external field, resulting in a mechanism similar to that of a conveyor belt. A prototype was fabricated using PDMS molding techniques mixed with iron powder for the magnetic structures. In the subsequent experiments, a quadrupole electromagnet was used to create the rotating external field. We observed that beads formed agglomerates that rolled over the chip surface, just above the magnetic structures. Field rotation frequencies between 0.1-50 Hz were tested resulting in magnetic bead speeds of over 1 mm s -1 for the highest frequency. With this, we have shown that our novel concept works, combining a simple design and simple operation with a powerful and versatile method for bead actuation. This makes it a promising method for further research and utilization in lab-on-chip systems.

FibroChip, a Functional DNA Microarray to Monitor Cellulolytic and Hemicellulolytic Activities of Rumen Microbiota

PubMed Central

Comtet-Marre, Sophie; Chaucheyras-Durand, Frédérique; Bouzid, Ourdia; Mosoni, Pascale; Bayat, Ali R.; Peyret, Pierre; Forano, Evelyne

2018-01-01

Ruminants fulfill their energy needs for growth primarily through microbial breakdown of plant biomass in the rumen. Several biotic and abiotic factors influence the efficiency of fiber degradation, which can ultimately impact animal productivity and health. To provide more insight into mechanisms involved in the modulation of fibrolytic activity, a functional DNA microarray targeting genes encoding key enzymes involved in cellulose and hemicellulose degradation by rumen microbiota was designed. Eight carbohydrate-active enzyme (CAZyme) families (GH5, GH9, GH10, GH11, GH43, GH48, CE1, and CE6) were selected which represented 392 genes from bacteria, protozoa, and fungi. The DNA microarray, designated as FibroChip, was validated using targets of increasing complexity and demonstrated sensitivity and specificity. In addition, FibroChip was evaluated for its explorative and semi-quantitative potential. Differential expression of CAZyme genes was evidenced in the rumen bacterium Fibrobacter succinogenes S85 grown on wheat straw or cellobiose. FibroChip was used to identify the expressed CAZyme genes from the targeted families in the rumen of a cow fed a mixed diet based on grass silage. Among expressed genes, those encoding GH43, GH5, and GH10 families were the most represented. Most of the F. succinogenes genes detected by the FibroChip were also detected following RNA-seq analysis of RNA transcripts obtained from the rumen fluid sample. Use of the FibroChip also indicated that transcripts of fiber degrading enzymes derived from eukaryotes (protozoa and anaerobic fungi) represented a significant proportion of the total microbial mRNA pool. FibroChip represents a reliable and high-throughput tool that enables researchers to monitor active members of fiber degradation in the rumen. PMID:29487591

FibroChip, a Functional DNA Microarray to Monitor Cellulolytic and Hemicellulolytic Activities of Rumen Microbiota.

PubMed

Comtet-Marre, Sophie; Chaucheyras-Durand, Frédérique; Bouzid, Ourdia; Mosoni, Pascale; Bayat, Ali R; Peyret, Pierre; Forano, Evelyne

2018-01-01

Ruminants fulfill their energy needs for growth primarily through microbial breakdown of plant biomass in the rumen. Several biotic and abiotic factors influence the efficiency of fiber degradation, which can ultimately impact animal productivity and health. To provide more insight into mechanisms involved in the modulation of fibrolytic activity, a functional DNA microarray targeting genes encoding key enzymes involved in cellulose and hemicellulose degradation by rumen microbiota was designed. Eight carbohydrate-active enzyme (CAZyme) families (GH5, GH9, GH10, GH11, GH43, GH48, CE1, and CE6) were selected which represented 392 genes from bacteria, protozoa, and fungi. The DNA microarray, designated as FibroChip, was validated using targets of increasing complexity and demonstrated sensitivity and specificity. In addition, FibroChip was evaluated for its explorative and semi-quantitative potential. Differential expression of CAZyme genes was evidenced in the rumen bacterium Fibrobacter succinogenes S85 grown on wheat straw or cellobiose. FibroChip was used to identify the expressed CAZyme genes from the targeted families in the rumen of a cow fed a mixed diet based on grass silage. Among expressed genes, those encoding GH43, GH5, and GH10 families were the most represented. Most of the F. succinogenes genes detected by the FibroChip were also detected following RNA-seq analysis of RNA transcripts obtained from the rumen fluid sample. Use of the FibroChip also indicated that transcripts of fiber degrading enzymes derived from eukaryotes (protozoa and anaerobic fungi) represented a significant proportion of the total microbial mRNA pool. FibroChip represents a reliable and high-throughput tool that enables researchers to monitor active members of fiber degradation in the rumen.

High-power, format-flexible, 885-nm vertical-cavity surface-emitting laser arrays

NASA Astrophysics Data System (ADS)

Wang, Chad; Talantov, Fedor; Garrett, Henry; Berdin, Glen; Cardellino, Terri; Millenheft, David; Geske, Jonathan

2013-03-01

High-power, format flexible, 885 nm vertical-cavity surface-emitting laser (VCSEL) arrays have been developed for solid-state pumping and illumination applications. In this approach, a common VCSEL size format was designed to enable tiling into flexible formats and operating configurations. The fabrication of a common chip size on ceramic submount enables low-cost volume manufacturing of high-power VCSEL arrays. This base VCSEL chip was designed to be 5x3.33 mm2, and produced up to 50 Watts of peak continuous wave (CW) power. To scale to higher powers, multiple chips can be tiled into a combination of series or parallel configurations tailored to the application driver conditions. In actively cooled CW operation, the VCSEL array chips were packaged onto a single water channel cooler, and we have demonstrated 0.5x1, 1x1, and 1x3 cm2 formats, producing 150, 250, and 500 Watts of peak power, respectively, in under 130 A operating current. In QCW operation, the 1x3 cm2 VCSEL module, which contains 18 VCSEL array chips packaged on a single water cooler, produced over 1.3 kW of peak power. In passively cooled packages, multiple chip configurations have been developed for illumination applications, producing over 300 Watts of peak power in QCW operating conditions. These VCSEL chips use a substrate-removed structure to allow for efficient thermal heatsinking to enable high-power operation. This scalable, format flexible VCSEL architecture can be applied to wavelengths ranging from 800 to 1100 nm, and can be used to tailor emission spectral widths and build high-power hyperspectral sources.

Plug-and-play, infrared, laser-mediated PCR in a microfluidic chip.

PubMed

Pak, Nikita; Saunders, D Curtis; Phaneuf, Christopher R; Forest, Craig R

2012-04-01

Microfluidic polymerase chain reaction (PCR) systems have set milestones for small volume (100 nL-5 μL), amplification speed (100-400 s), and on-chip integration of upstream and downstream sample handling including purification and electrophoretic separation functionality. In practice, the microfluidic chips in these systems require either insertion of thermocouples or calibration prior to every amplification. These factors can offset the speed advantages of microfluidic PCR and have likely hindered commercialization. We present an infrared, laser-mediated, PCR system that features a single calibration, accurate and repeatable precision alignment, and systematic thermal modeling and management for reproducible, open-loop control of PCR in 1 μL chambers of a polymer microfluidic chip. Total cycle time is less than 12 min: 1 min to fill and seal, 10 min to amplify, and 1 min to recover the sample. We describe the design, basis for its operation, and the precision engineering in the system and microfluidic chip. From a single calibration, we demonstrate PCR amplification of a 500 bp amplicon from λ-phage DNA in multiple consecutive trials on the same instrument as well as multiple identical instruments. This simple, relatively low-cost plug-and-play design is thus accessible to persons who may not be skilled in assembly and engineering.

VLSI research

NASA Astrophysics Data System (ADS)

Brodersen, R. W.

1984-04-01

A scaled version of the RISC II chip has been fabricated and tested and these new chips have a cycle time that would outperform a VAX 11/780 by about a factor of two on compiled integer C programs. The architectural work on a RISC chip designed for a Smalltalk implementation has been completed. This chip, called SOAR (Smalltalk On a RISC), should run program s4-15 times faster than the Xerox 1100 (Dolphin), a TTL minicomputer, and about as fast as the Xerox 1132 (Dorado), a $100,000 ECL minicomputer. The 1983 VLSI tools tape has been converted for use under the latest UNIX release (4.2). The Magic (formerly called Caddy) layout system will be a unified set of highly automated tools that cover all aspects of the layout process, including stretching, compaction, tiling and routing. A multiple window package and design rule checker for this system have just been completed and compaction and stretching are partially implemented. New slope-based timing models for the Crystal timing analyzer are now fully implemented and in regular use. In an accuracy test using a dozen critical paths from the RISC II processor and cache chips it was found that Crystal's estimates were within 5-10% of SPICE's estimates, while being a factor of 10,000 times faster.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Britton, C.L.; Jagadish, U.; Bryan, W.L.

An Integrated Circuit (IC) readout chip with four channels arranged so as to receive input charge from the corners of the chip was designed for use with 5- to 7-mm pixel detectors. This Application Specific IC (ASIC) can be used for cold neutron imaging, for study of structural order in materials using cold neutron scattering or for particle physics experiments. The ASIC is fabricated in a 0.5-{micro}m n-well AMI process. The design of the ASIC and the test measurements made is reported. Noise measurements are also reported.

Architecture for VLSI design of Reed-Solomon encoders

NASA Technical Reports Server (NTRS)

Liu, K. Y.

1982-01-01

A description is given of the logic structure of the universal VLSI symbol-slice Reed-Solomon (RS) encoder chip, from a group of which an RS encoder may be constructed through cascading and proper interconnection. As a design example, it is shown that an RS encoder presently requiring approximately 40 discrete CMOS ICs may be replaced by an RS encoder consisting of four identical, interconnected VLSI RS encoder chips, offering in addition to greater compactness both a lower power requirement and greater reliability.

Architecture for VLSI design of Reed-Solomon encoders

NASA Astrophysics Data System (ADS)

Liu, K. Y.

1982-02-01

A description is given of the logic structure of the universal VLSI symbol-slice Reed-Solomon (RS) encoder chip, from a group of which an RS encoder may be constructed through cascading and proper interconnection. As a design example, it is shown that an RS encoder presently requiring approximately 40 discrete CMOS ICs may be replaced by an RS encoder consisting of four identical, interconnected VLSI RS encoder chips, offering in addition to greater compactness both a lower power requirement and greater reliability.

Floating Chip Mounting System Driven by Repulsive Force of Permanent Magnets for Multiple On-Site SPR Immunoassay Measurements

PubMed Central

Horiuchi, Tsutomu; Tobita, Tatsuya; Miura, Toru; Iwasaki, Yuzuru; Seyama, Michiko; Inoue, Suzuyo; Takahashi, Jun-ichi; Haga, Tsuneyuki; Tamechika, Emi

2012-01-01

We have developed a measurement chip installation/removal mechanism for a surface plasmon resonance (SPR) immunoassay analysis instrument designed for frequent testing, which requires a rapid and easy technique for changing chips. The key components of the mechanism are refractive index matching gel coated on the rear of the SPR chip and a float that presses the chip down. The refractive index matching gel made it possible to optically couple the chip and the prism of the SPR instrument easily via elastic deformation with no air bubbles. The float has an autonomous attitude control function that keeps the chip parallel in relation to the SPR instrument by employing the repulsive force of permanent magnets between the float and a float guide located in the SPR instrument. This function is realized by balancing the upward elastic force of the gel and the downward force of the float, which experiences a leveling force from the float guide. This system makes it possible to start an SPR measurement immediately after chip installation and to remove the chip immediately after the measurement with a simple and easy method that does not require any fine adjustment. Our sensor chip, which we installed using this mounting system, successfully performed an immunoassay measurement on a model antigen (spiked human-IgG) in a model real sample (non-homogenized milk) that included many kinds of interfering foreign substances without any sample pre-treatment. The ease of the chip installation/removal operation and simple measurement procedure are suitable for frequent on-site agricultural, environmental and medical testing. PMID:23202030

Anti-cancer activity of ZnO chips by sustained zinc ion release.

PubMed

Moon, Seong-Hee; Choi, Won Jin; Choi, Sik-Won; Kim, Eun Hye; Kim, Jiyeon; Lee, Jeong-O; Kim, Seong Hwan

2016-01-01

We report anti-cancer activity of ZnO thin-film-coated chips by sustained release of zinc ions. ZnO chips were fabricated by precisely tuning ZnO thickness using atomic layer deposition, and their potential to release zinc ions relative to the number of deposition cycles was evaluated. ZnO chips exhibited selective cytotoxicity in human B lymphocyte Raji cells while having no effect on human peripheral blood mononuclear cells. Of importance, the half-maximal inhibitory concentration of the ZnO chip on the viability of Raji cells was 121.5 cycles, which was comparable to 65.7 nM of daunorubicin, an anti-cancer drug for leukemia. Molecular analysis of cells treated with ZnO chips revealed that zinc ions released from the chips increased cellular levels of reactive oxygen species, including hydrogen peroxide, which led to the down-regulation of anti-apoptotic molecules (such as HIF-1α, survivin, cIAP-2, claspin, p-53, and XIAP) and caspase-dependent apoptosis. Because the anti-cancer activity of ZnO chips and the mode of action were comparable to those of daunorubicin, the development and optimization of ZnO chips that gradually release zinc ions might have clinical anti-cancer potential. A further understanding of the biological action of ZnO-related products is crucial for designing safe biomaterials with applications in disease treatment.

VLSI design of lossless frame recompression using multi-orientation prediction

NASA Astrophysics Data System (ADS)

Lee, Yu-Hsuan; You, Yi-Lun; Chen, Yi-Guo

2016-01-01

Pursuing an experience of high-end visual quality drives human to demand a higher display resolution and a higher frame rate. Hence, a lot of powerful coding tools are aggregated together in emerging video coding standards to improve coding efficiency. This also makes video coding standards suffer from two design challenges: heavy computation and tremendous memory bandwidth. The first issue can be properly solved by a careful hardware architecture design with advanced semiconductor processes. Nevertheless, the second one becomes a critical design bottleneck for a modern video coding system. In this article, a lossless frame recompression using multi-orientation prediction technique is proposed to overcome this bottleneck. This work is realised into a silicon chip with the technology of TSMC 0.18 µm CMOS process. Its encoding capability can reach full-HD (1920 × 1080)@48 fps. The chip power consumption is 17.31 mW@100 MHz. Core area and chip area are 0.83 × 0.83 mm2 and 1.20 × 1.20 mm2, respectively. Experiment results demonstrate that this work exhibits an outstanding performance on lossless compression ratio with a competitive hardware performance.

Intelligent operations of the data acquisition system of the ATLAS experiment at LHC

NASA Astrophysics Data System (ADS)

Anders, G.; Avolio, G.; Lehmann Miotto, G.; Magnoni, L.

2015-05-01

The ATLAS experiment at the Large Hadron Collider at CERN relies on a complex and highly distributed Trigger and Data Acquisition (TDAQ) system to gather and select particle collision data obtained at unprecedented energy and rates. The Run Control (RC) system is the component steering the data acquisition by starting and stopping processes and by carrying all data-taking elements through well-defined states in a coherent way. Taking into account all the lessons learnt during LHC's Run 1, the RC has been completely re-designed and re-implemented during the LHC Long Shutdown 1 (LS1) phase. As a result of the new design, the RC is assisted by the Central Hint and Information Processor (CHIP) service that can be truly considered its “brain”. CHIP is an intelligent system able to supervise the ATLAS data taking, take operational decisions and handle abnormal conditions. In this paper, the design, implementation and performances of the RC/CHIP system will be described. A particular emphasis will be put on the way the RC and CHIP cooperate and on the huge benefits brought by the Complex Event Processing engine. Additionally, some error recovery scenarios will be analysed for which the intervention of human experts is now rendered unnecessary.

The initial characterization of a revised 10-Gsps analog-to-digital converter board for radio telescopes

NASA Astrophysics Data System (ADS)

Jiango, Homin; Liuo, Howard; Guzzino, Kim

2016-07-01

In this study, the design of a 4 bit, 10-gigasamples-per-second analog-to-digital converter (ADC) printed circuit board assembly (PCBA) was revised, manufactured, and tested. It is used for digitizing radio telescopes. An Adsantec ANST7120-KMA flash ADC chip was used, as in the original design. Associated with the field-programmable gate array platform developed by the Collaboration for Astronomy Signal Processing and Electronics Research community, the developed PCBA provides data acquisition systems with a wider bandwidth and simplifies the intermediate frequency section. The current version of the PCBA exhibits an analog bandwidth of up to 10 GHz (3 dB loss), and the chip exhibits an analog bandwidth of up to 18 GHz. This facilitates second and third Nyquist sampling. The following worstcase performance parameters were obtained from the revised PCBA at over 5 GHz: spurious-free dynamic range of 12 dB, signal-to-noise and distortion ratio of 2 dB, and effective number of bits of 0.7. The design bugs in the ADC chip caused the poor performance. The vendor created a new batch run and confirmed that the ADC chips of the new batch will meet the specifications addressed in its data sheet.

Field-programmable lab-on-a-chip based on microelectrode dot array architecture.

PubMed

Wang, Gary; Teng, Daniel; Lai, Yi-Tse; Lu, Yi-Wen; Ho, Yingchieh; Lee, Chen-Yi

2014-09-01

The fundamentals of electrowetting-on-dielectric (EWOD) digital microfluidics are very strong: advantageous capability in the manipulation of fluids, small test volumes, precise dynamic control and detection, and microscale systems. These advantages are very important for future biochip developments, but the development of EWOD microfluidics has been hindered by the absence of: integrated detector technology, standard commercial components, on-chip sample preparation, standard manufacturing technology and end-to-end system integration. A field-programmable lab-on-a-chip (FPLOC) system based on microelectrode dot array (MEDA) architecture is presented in this research. The MEDA architecture proposes a standard EWOD microfluidic component called 'microelectrode cell', which can be dynamically configured into microfluidic components to perform microfluidic operations of the biochip. A proof-of-concept prototype FPLOC, containing a 30 × 30 MEDA, was developed by using generic integrated circuits computer aided design tools, and it was manufactured with standard low-voltage complementary metal-oxide-semiconductor technology, which allows smooth on-chip integration of microfluidics and microelectronics. By integrating 900 droplet detection circuits into microelectrode cells, the FPLOC has achieved large-scale integration of microfluidics and microelectronics. Compared to the full-custom and bottom-up design methods, the FPLOC provides hierarchical top-down design approach, field-programmability and dynamic manipulations of droplets for advanced microfluidic operations.

High-Performance Microsupercapacitors Based on Bioinspired Graphene Microfibers.

PubMed

Pan, Hui; Wang, Dawei; Peng, Qingfa; Ma, Jun; Meng, Xin; Zhang, Yaopeng; Ma, Yuning; Zhu, Shenmin; Zhang, Di

2018-03-28

The miniaturization of portable electronic devices has fueled the development of microsupercapacitors that hold great potential to complement or even replace microbatteries and electrolytic capacitors. In spite of recent developments taking advantage of printing and lithography, it remains a great challenge to attain a high energy density without sacrificing the power density. Herein, a new protocol mimicking the spider's spinning process is developed to create highly oriented microfibers from graphene-based composites via a purpose-designed microfluidic chip. The orientation provides the microfibers with an electrical conductivity of ∼3 × 10 4 S m -1 , which leads to a high power density; the energy density is sustained by nanocarbons and high-purity metallic molybdenum disulfide. The microfibers are patterned in-plane to fabricate asymmetric microsupercapacitors for flexible and on-chip energy storage. The on-chip microsupercapacitor with a high pattern resolution of 100 μm delivers energy density up to the order of 10 -2 W h cm -3 and retains an ultrahigh power density exceeding 100 W cm -3 in an aqueous electrolyte. This work provides new design of flexible and on-chip asymmetric microsupercapacitors based on microfibers. The unique biomimetic microfluidic fabrication of graphene microfibers for energy storage may also stimulate thinking of the bionic design in many other fields.

Digital isothermal quantification of nucleic acids via simultaneous chemical initiation of recombinase polymerase amplification reactions on SlipChip.

PubMed

Shen, Feng; Davydova, Elena K; Du, Wenbin; Kreutz, Jason E; Piepenburg, Olaf; Ismagilov, Rustem F

2011-05-01

In this paper, digital quantitative detection of nucleic acids was achieved at the single-molecule level by chemical initiation of over one thousand sequence-specific, nanoliter isothermal amplification reactions in parallel. Digital polymerase chain reaction (digital PCR), a method used for quantification of nucleic acids, counts the presence or absence of amplification of individual molecules. However, it still requires temperature cycling, which is undesirable under resource-limited conditions. This makes isothermal methods for nucleic acid amplification, such as recombinase polymerase amplification (RPA), more attractive. A microfluidic digital RPA SlipChip is described here for simultaneous initiation of over one thousand nL-scale RPA reactions by adding a chemical initiator to each reaction compartment with a simple slipping step after instrument-free pipet loading. Two designs of the SlipChip, two-step slipping and one-step slipping, were validated using digital RPA. By using the digital RPA SlipChip, false-positive results from preinitiation of the RPA amplification reaction before incubation were eliminated. End point fluorescence readout was used for "yes or no" digital quantification. The performance of digital RPA in a SlipChip was validated by amplifying and counting single molecules of the target nucleic acid, methicillin-resistant Staphylococcus aureus (MRSA) genomic DNA. The digital RPA on SlipChip was also tolerant to fluctuations of the incubation temperature (37-42 °C), and its performance was comparable to digital PCR on the same SlipChip design. The digital RPA SlipChip provides a simple method to quantify nucleic acids without requiring thermal cycling or kinetic measurements, with potential applications in diagnostics and environmental monitoring under resource-limited settings. The ability to initiate thousands of chemical reactions in parallel on the nanoliter scale using solvent-resistant glass devices is likely to be useful for a broader range of applications.

Digital Isothermal Quantification of Nucleic Acids via Simultaneous Chemical Initiation of Recombinase Polymerase Amplification Reactions on SlipChip

PubMed Central

Shen, Feng; Davydova, Elena K.; Du, Wenbin; Kreutz, Jason E.; Piepenburg, Olaf; Ismagilov, Rustem F.

2011-01-01

In this paper, digital quantitative detection of nucleic acids was achieved at the single-molecule level by chemical initiation of over one thousand sequence-specific, nanoliter, isothermal amplification reactions in parallel. Digital polymerase chain reaction (digital PCR), a method used for quantification of nucleic acids, counts the presence or absence of amplification of individual molecules. However it still requires temperature cycling, which is undesirable under resource-limited conditions. This makes isothermal methods for nucleic acid amplification, such as recombinase polymerase amplification (RPA), more attractive. A microfluidic digital RPA SlipChip is described here for simultaneous initiation of over one thousand nL-scale RPA reactions by adding a chemical initiator to each reaction compartment with a simple slipping step after instrument-free pipette loading. Two designs of the SlipChip, two-step slipping and one-step slipping, were validated using digital RPA. By using the digital RPA SlipChip, false positive results from pre-initiation of the RPA amplification reaction before incubation were eliminated. End-point fluorescence readout was used for “yes or no” digital quantification. The performance of digital RPA in a SlipChip was validated by amplifying and counting single molecules of the target nucleic acid, Methicillin-resistant Staphylococcus aureus (MRSA) genomic DNA. The digital RPA on SlipChip was also tolerant to fluctuations of the incubation temperature (37–42 °C), and its performance was comparable to digital PCR on the same SlipChip design. The digital RPA SlipChip provides a simple method to quantify nucleic acids without requiring thermal cycling or kinetic measurements, with potential applications in diagnostics and environmental monitoring under resource-limited settings. The ability to initiate thousands of chemical reactions in parallel on the nanoliter scale using solvent-resistant glass devices is likely to be useful for a broader range of applications. PMID:21476587

75 FR 80851 - Records Schedules; Availability and Request for Comments

Federal Register 2010, 2011, 2012, 2013, 2014

2010-12-23

..., including highway bridge and tunnel correspondence, designs and plans, geotechnical and hydraulic files... files, asphalt and pavement research files, statewide contract files, delineation files, recycling and...

Autogenous bone chips: influence of a new piezoelectric device (Piezosurgery) on chip morphology, cell viability and differentiation.

PubMed

Chiriac, G; Herten, M; Schwarz, F; Rothamel, D; Becker, J

2005-09-01

The aim of the present study was to investigate the influence of a new piezoelectric device, designed for harvesting autogenous bone chips from intra-oral sites, on chip morphology, cell viability and differentiation. A total of 69 samples of cortical bone chips were randomly gained by either (1) a piezoelectric device (PS), or (2) conventional rotating drills (RD). Shape and size of the bone chips were compared by means of morphometrical analysis. Outgrowing osteoblasts were identified by means of alkaline phosphatase activity (AP), immunhistochemical staining for osteocalcin (OC) synthesis and reverse transcriptase-polymerase chain reaction phenotyping. In 88.9% of the RD and 87.9% of the PS specimens, an outgrowth of adherent cells nearby the bone chips was observed after 6-19 days. Confluence of cells was reached after 4 weeks. Positive staining for AP and OC identified the cells as osteoblasts. The morphometrical analysis revealed a statistically significant more voluminous size of the particles collected with PS than RD. Within the limits of the present study, it may be concluded that both the harvesting methods are not different from each other concerning their detrimental effect on viability and differentiation of cells growing out of autogenous bone chips derived from intra-oral cortical sites.

Fabrication of five-level ultraplanar micromirror arrays by flip-chip assembly

NASA Astrophysics Data System (ADS)

Michalicek, M. Adrian; Bright, Victor M.

2001-10-01

This paper reports a detailed study of the fabrication of various piston, torsion, and cantilever style micromirror arrays using a novel, simple, and inexpensive flip-chip assembly technique. Several rectangular and polar arrays were commercially prefabricated in the MUMPs process and then flip-chip bonded to form advanced micromirror arrays where adverse effects typically associated with surface micromachining were removed. These arrays were bonded by directly fusing the MUMPs gold layers with no complex preprocessing. The modules were assembled using a computer-controlled, custom-built flip-chip bonding machine. Topographically opposed bond pads were designed to correct for slight misalignment errors during bonding and typically result in less than 2 micrometers of lateral alignment error. Although flip-chip micromirror performance is briefly discussed, the means used to create these arrays is the focus of the paper. A detailed study of flip-chip process yield is presented which describes the primary failure mechanisms for flip-chip bonding. Studies of alignment tolerance, bonding force, stress concentration, module planarity, bonding machine calibration techniques, prefabrication errors, and release procedures are presented in relation to specific observations in process yield. Ultimately, the standard thermo-compression flip-chip assembly process remains a viable technique to develop highly complex prototypes of advanced micromirror arrays.

Physical properties and estimated glycemic index of protein-enriched sorghum based chips.

PubMed

Jiang, Hongrui; Hettiararchchy, Navam S; Horax, Ronny

2018-03-01

Sorghum is a gluten-free grain and more attention has been given to the nutritional properties and recently its usage as a wheat replacement in food products. In the present work, protein-enriched sorghum based snack chips, prepared from sorghum meal with soy protein isolates and soy flour to meet the final protein content of 35.7%, were produced. The effect of varying baking powder (1.5-2.5%), dough sheet thickness (0.7-1.7 mm), and baking time (6-12 min) on the physical properties of the snack chips was investigated using a central composite design of response surface methodology. Under baking temperature of 160 °C, with baking powder added, the water activity and puffiness of chips significantly increased. Baking time was the most significant factor for all the parameters detected except for puffiness. The optimized conditions of preparing protein-enriched sorghum chips were baking powder 2.5%, dough sheet thickness 0.7 mm, and baking time 7.66 min. The estimated glycemic index (eGI) of the protein-enriched sorghum chips (eGI = 59.8) was significantly lower than soybean-free sorghum chips. The gluten-free protein-enriched sorghum chips developed could be considered as protein rich with lower intermediate-glycemic index classified healthy snacks and potential commercialization.

Design and fabrication of a multilayered polymer microfluidic chip with nanofluidic interconnects via adhesive contact printing.

PubMed

Flachsbart, Bruce R; Wong, Kachuen; Iannacone, Jamie M; Abante, Edward N; Vlach, Robert L; Rauchfuss, Peter A; Bohn, Paul W; Sweedler, Jonathan V; Shannon, Mark A

2006-05-01

The design and fabrication of a multilayered polymer micro-nanofluidic chip is described that consists of poly(methylmethacrylate) (PMMA) layers that contain microfluidic channels separated in the vertical direction by polycarbonate (PC) membranes that incorporate an array of nanometre diameter cylindrical pores. The materials are optically transparent to allow inspection of the fluids within the channels in the near UV and visible spectrum. The design architecture enables nanofluidic interconnections to be placed in the vertical direction between microfluidic channels. Such an architecture allows microchannel separations within the chip, as well as allowing unique operations that utilize nanocapillary interconnects: the separation of analytes based on molecular size, channel isolation, enhanced mixing, and sample concentration. Device fabrication is made possible by a transfer process of labile membranes and the development of a contact printing method for a thermally curable epoxy based adhesive. This adhesive is shown to have bond strengths that prevent leakage and delamination and channel rupture tests exceed 6 atm (0.6 MPa) under applied pressure. Channels 100 microm in width and 20 microm in depth are contact printed without the adhesive entering the microchannel. The chip is characterized in terms of resistivity measurements along the microfluidic channels, electroosmotic flow (EOF) measurements at different pH values and laser-induced-fluorescence (LIF) detection of green-fluorescent protein (GFP) plugs injected across the nanocapillary membrane and into a microfluidic channel. The results indicate that the mixed polymer micro-nanofluidic multilayer chip has electrical characteristics needed for use in microanalytical systems.

Neuromorphic implementations of neurobiological learning algorithms for spiking neural networks.

PubMed

Walter, Florian; Röhrbein, Florian; Knoll, Alois

2015-12-01

The application of biologically inspired methods in design and control has a long tradition in robotics. Unlike previous approaches in this direction, the emerging field of neurorobotics not only mimics biological mechanisms at a relatively high level of abstraction but employs highly realistic simulations of actual biological nervous systems. Even today, carrying out these simulations efficiently at appropriate timescales is challenging. Neuromorphic chip designs specially tailored to this task therefore offer an interesting perspective for neurorobotics. Unlike Von Neumann CPUs, these chips cannot be simply programmed with a standard programming language. Like real brains, their functionality is determined by the structure of neural connectivity and synaptic efficacies. Enabling higher cognitive functions for neurorobotics consequently requires the application of neurobiological learning algorithms to adjust synaptic weights in a biologically plausible way. In this paper, we therefore investigate how to program neuromorphic chips by means of learning. First, we provide an overview over selected neuromorphic chip designs and analyze them in terms of neural computation, communication systems and software infrastructure. On the theoretical side, we review neurobiological learning techniques. Based on this overview, we then examine on-die implementations of these learning algorithms on the considered neuromorphic chips. A final discussion puts the findings of this work into context and highlights how neuromorphic hardware can potentially advance the field of autonomous robot systems. The paper thus gives an in-depth overview of neuromorphic implementations of basic mechanisms of synaptic plasticity which are required to realize advanced cognitive capabilities with spiking neural networks. Copyright © 2015 Elsevier Ltd. All rights reserved.

An evaluation of the directed flow graph methodology

NASA Technical Reports Server (NTRS)

Snyder, W. E.; Rajala, S. A.

1984-01-01

The applicability of the Directed Graph Methodology (DGM) to the design and analysis of special purpose image and signal processing hardware was evaluated. A special purpose image processing system was designed and described using DGM. The design, suitable for very large scale integration (VLSI) implements a region labeling technique. Two computer chips were designed, both using metal-nitride-oxide-silicon (MNOS) technology, as well as a functional system utilizing those chips to perform real time region labeling. The system is described in terms of DGM primitives. As it is currently implemented, DGM is inappropriate for describing synchronous, tightly coupled, special purpose systems. The nature of the DGM formalism lends itself more readily to modeling networks of general purpose processors.

Advanced power analysis methodology targeted to the optimization of a digital pixel readout chip design and its critical serial powering system

NASA Astrophysics Data System (ADS)

Marconi, S.; Orfanelli, S.; Karagounis, M.; Hemperek, T.; Christiansen, J.; Placidi, P.

2017-02-01

A dedicated power analysis methodology, based on modern digital design tools and integrated with the VEPIX53 simulation framework developed within RD53 collaboration, is being used to guide vital choices for the design and optimization of the next generation ATLAS and CMS pixel chips and their critical serial powering circuit (shunt-LDO). Power consumption is studied at different stages of the design flow under different operating conditions. Significant effort is put into extensive investigations of dynamic power variations in relation with the decoupling seen by the powering network. Shunt-LDO simulations are also reported to prove the reliability at the system level.

Simulations and design of microfabricated interdigitated electrodes for use in a gold nanoparticle enhanced biosensor.

PubMed

Hermansen, Peter; MacKay, Scott; Wishart, David; Jie Chen

2016-08-01

Microfabricated interdigitated electrode chips have been designed for use in a unique gold-nanoparticle based biosensor system. The use of these electrodes will allow for simple, accurate, inexpensive, and portable biosensing, with potential applications in diagnostics, medical research, and environmental testing. To determine the optimal design for these electrodes, finite element analysis simulations were carried out using COMSOL Multiphysics software. The results of these simulations determined some of the optimal design parameters for microfabricating interdigitated electrodes as well as predicting the effects of different electrode materials. Finally, based on the results of these simulations two different kinds of interdigitated electrode chips were made using photolithography.

Physics-based process modeling, reliability prediction, and design guidelines for flip-chip devices

NASA Astrophysics Data System (ADS)

Michaelides, Stylianos

Flip Chip on Board (FCOB) and Chip-Scale Packages (CSPs) are relatively new technologies that are being increasingly used in the electronic packaging industry. Compared to the more widely used face-up wirebonding and TAB technologies, flip-chips and most CSPs provide the shortest possible leads, lower inductance, higher frequency, better noise control, higher density, greater input/output (I/O), smaller device footprint and lower profile. However, due to the short history and due to the introduction of several new electronic materials, designs, and processing conditions, very limited work has been done to understand the role of material, geometry, and processing parameters on the reliability of flip-chip devices. Also, with the ever-increasing complexity of semiconductor packages and with the continued reduction in time to market, it is too costly to wait until the later stages of design and testing to discover that the reliability is not satisfactory. The objective of the research is to develop integrated process-reliability models that will take into consideration the mechanics of assembly processes to be able to determine the reliability of face-down devices under thermal cycling and long-term temperature dwelling. The models incorporate the time and temperature-dependent constitutive behavior of various materials in the assembly to be able to predict failure modes such as die cracking and solder cracking. In addition, the models account for process-induced defects and macro-micro features of the assembly. Creep-fatigue and continuum-damage mechanics models for the solder interconnects and fracture-mechanics models for the die have been used to determine the reliability of the devices. The results predicted by the models have been successfully validated against experimental data. The validated models have been used to develop qualification and test procedures for implantable medical devices. In addition, the research has helped develop innovative face-down devices without the underfill, based on the thorough understanding of the failure modes. Also, practical design guidelines for material, geometry and process parameters for reliable flip-chip devices have been developed.

Microfluidic LC Device with Orthogonal Sample Extraction for On-Chip MALDI-MS Detection

PubMed Central

Lazar, Iulia M.; Kabulski, Jarod L.

2013-01-01

A microfluidic device that enables on-chip matrix assisted laser desorption ionization-mass spectrometry (MALDI-MS) detection for liquid chromatography (LC) separations is described. The device comprises an array of functional elements to carry out LC separations, integrates a novel microchip-MS interface to facilitate the orthogonal transposition of the microfluidic LC channel into an array of reservoirs, and enables sensitive MALDI-MS detection directly from the chip. Essentially, the device provides a snapshot MALDI-MS map of the content of the separation channel present on the chip. The detection of proteins with biomarker potential from MCF10A breast epithelial cell extracts, and detection limits in the low fmol range, are demonstrated. In addition, the design of the novel LC-MALDI-MS chip entices the promotion of a new concept for performing sample separations within the limited time-frame that accompanies the dead-volume of a separation channel. PMID:23592150

Epoxy Chip-in-Carrier Integration and Screen-Printed Metalization for Multichannel Microfluidic Lab-on-CMOS Microsystems.

PubMed

Li, Lin; Yin, Heyu; Mason, Andrew J

2018-04-01

The integration of biosensors, microfluidics, and CMOS instrumentation provides a compact lab-on-CMOS microsystem well suited for high throughput measurement. This paper describes a new epoxy chip-in-carrier integration process and two planar metalization techniques for lab-on-CMOS that enable on-CMOS electrochemical measurement with multichannel microfluidics. Several design approaches with different fabrication steps and materials were experimentally analyzed to identify an ideal process that can achieve desired capability with high yield and low material and tool cost. On-chip electrochemical measurements of the integrated assembly were performed to verify the functionality of the chip-in-carrier packaging and its capability for microfluidic integration. The newly developed CMOS-compatible epoxy chip-in-carrier process paves the way for full implementation of many lab-on-CMOS applications with CMOS ICs as core electronic instruments.

Regeneration of glass nanofluidic chips through a multiple-step sequential thermochemical decomposition process at high temperatures.

PubMed

Xu, Yan; Wu, Qian; Shimatani, Yuji; Yamaguchi, Koji

2015-10-07

Due to the lack of regeneration methods, the reusability of nanofluidic chips is a significant technical challenge impeding the efficient and economic promotion of both fundamental research and practical applications on nanofluidics. Herein, a simple method for the total regeneration of glass nanofluidic chips was described. The method consists of sequential thermal treatment with six well-designed steps, which correspond to four sequential thermal and thermochemical decomposition processes, namely, dehydration, high-temperature redox chemical reaction, high-temperature gasification, and cooling. The method enabled the total regeneration of typical 'dead' glass nanofluidic chips by eliminating physically clogged nanoparticles in the nanochannels, removing chemically reacted organic matter on the glass surface and regenerating permanent functional surfaces of dissimilar materials localized in the nanochannels. The method provides a technical solution to significantly improve the reusability of glass nanofluidic chips and will be useful for the promotion and acceleration of research and applications on nanofluidics.

Open-systems architecture of a standardized command interface chip-set for switching and control of a spacecraft power bus

NASA Technical Reports Server (NTRS)

Ruiz, Ian B.; Burke, Gary R.; Lung, Gerald; Whitaker, William D.; Nowicki, Robert M.

2004-01-01

The Jet Propulsion Laboratory (JPL) has developed a command interface chip-set that primarily consists of two mixed-signal ASICs'; the Command Interface ASIC (CIA) and Analog Interface ASIC (AIA). The Open-systems architecture employed during the design of this chip-set enables its use as both an intelligent gateway between the system's flight computer and the control, actuation, and activation of the spacecraft's loads, valves, and pyrotechnics respectfully as well as the regulator of the spacecraft power bus. Furthermore, the architecture is highly adaptable and employed fault-tolerant design methods enabling a host of other mission uses including reliable remote data collection. The objective of this design is to both provide a needed flight component that meets the stringent environmental requirements of current deep space missions and to add a new element to a growing library that can be used as a standard building block for future missions to the outer planets.

CMOS compatible on-chip telecom-band to mid-infrared supercontinuum generation in dispersion-engineered reverse strip/slot hybrid Si3N4 waveguide

NASA Astrophysics Data System (ADS)

Hui, Zhanqiang; Zhang, Lingxuan; Zhang, Wenfu

2018-01-01

A silicon nitride (Si3N4)-based reverse strip/slot hybrid waveguide with single vertical silica slot is proposed to acquire extremely low and flat chromatic dispersion profile. This is achieved by design and optimization of the geometrical structural parameters of the reverse hybrid waveguide. The flat dispersion varying between ±10 ps/(nm.km) is obtained over 610 nm bandwidth. Both the effective area and nonlinear coefficient of the waveguide across the entire spectral range of interest are investigated. This led to design of an on-chip supercontinuum (SC) source with -30 dB bandwidth of 2996 nm covering from 1.209 to 4.205 μm. Furthermore, we discuss the output signal spectral and temporal characteristic as a function of the pump power. Our waveguide design offers a CMOS compatible, low-cost/high yield (no photolithography or lift-off processes are necessary) on-chip SC source for near- and mid-infrared nonlinear applications.

Design of Architectures and Materials in In-Plane Micro-supercapacitors: Current Status and Future Challenges.

PubMed

Qi, Dianpeng; Liu, Yan; Liu, Zhiyuan; Zhang, Li; Chen, Xiaodong

2017-02-01

The rapid development of integrated electronics and the boom in miniaturized and portable devices have increased the demand for miniaturized and on-chip energy storage units. Currently thin-film batteries or microsized batteries are commercially available for miniaturized devices. However, they still suffer from several limitations, such as short lifetime, low power density, and complex architecture, which limit their integration. Supercapacitors can surmount all these limitations. Particularly for micro-supercapacitors with planar architectures, due to their unique design of the in-plane electrode finger arrays, they possess the merits of easy fabrication and integration into on-chip miniaturized electronics. Here, the focus is on the different strategies to design electrode finger arrays and the material engineering of in-plane micro-supercapacitors. It is expected that the advances in micro-supercapacitors with in-plane architectures will offer new opportunities for the miniaturization and integration of energy-storage units for portable devices and on-chip electronics. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

The Panda Strip Asic: Pasta

NASA Astrophysics Data System (ADS)

Lai, A.

2018-01-01

PASTA is the 64 channel front-end chip, designed in a 110 nm CMOS technology to read out the strip sensors of the Micro Vertex Detector (MVD) of the PANDA experiment. This chip provides high resolution timestamp and deposited charge information by means of the time-over-threshold technique. Its working principle is based on a predecessor, the TOFPET ASIC, that was designed for medical applications. A general restructuring of the architecture was needed, in order to meet the specific requirements imposed by the physics programme of PANDA, especially in terms of radiation tolerance, spatial constraints, and readout in absence of a first level hardware trigger. The first revision of PASTA is currently under evaluation at the Forschungszentrum Jülich, where a data acquisition system dedicated to the MVD prototypes has been developed. This paper describes the main aspect of the chip design, gives an overview of the data acquisition system used for the verification, and shows the first results regarding the performance of PASTA.

Co-Design Method and Wafer-Level Packaging Technique of Thin-Film Flexible Antenna and Silicon CMOS Rectifier Chips for Wireless-Powered Neural Interface Systems.

PubMed

Okabe, Kenji; Jeewan, Horagodage Prabhath; Yamagiwa, Shota; Kawano, Takeshi; Ishida, Makoto; Akita, Ippei

2015-12-16

In this paper, a co-design method and a wafer-level packaging technique of a flexible antenna and a CMOS rectifier chip for use in a small-sized implantable system on the brain surface are proposed. The proposed co-design method optimizes the system architecture, and can help avoid the use of external matching components, resulting in the realization of a small-size system. In addition, the technique employed to assemble a silicon large-scale integration (LSI) chip on the very thin parylene film (5 μm) enables the integration of the rectifier circuits and the flexible antenna (rectenna). In the demonstration of wireless power transmission (WPT), the fabricated flexible rectenna achieved a maximum efficiency of 0.497% with a distance of 3 cm between antennas. In addition, WPT with radio waves allows a misalignment of 185% against antenna size, implying that the misalignment has a less effect on the WPT characteristics compared with electromagnetic induction.

Co-Design Method and Wafer-Level Packaging Technique of Thin-Film Flexible Antenna and Silicon CMOS Rectifier Chips for Wireless-Powered Neural Interface Systems

PubMed Central

Okabe, Kenji; Jeewan, Horagodage Prabhath; Yamagiwa, Shota; Kawano, Takeshi; Ishida, Makoto; Akita, Ippei

2015-01-01

In this paper, a co-design method and a wafer-level packaging technique of a flexible antenna and a CMOS rectifier chip for use in a small-sized implantable system on the brain surface are proposed. The proposed co-design method optimizes the system architecture, and can help avoid the use of external matching components, resulting in the realization of a small-size system. In addition, the technique employed to assemble a silicon large-scale integration (LSI) chip on the very thin parylene film (5 μm) enables the integration of the rectifier circuits and the flexible antenna (rectenna). In the demonstration of wireless power transmission (WPT), the fabricated flexible rectenna achieved a maximum efficiency of 0.497% with a distance of 3 cm between antennas. In addition, WPT with radio waves allows a misalignment of 185% against antenna size, implying that the misalignment has a less effect on the WPT characteristics compared with electromagnetic induction. PMID:26694407

Mobile Phone Chips Reduce Increases in EEG Brain Activity Induced by Mobile Phone-Emitted Electromagnetic Fields.

PubMed

Henz, Diana; Schöllhorn, Wolfgang I; Poeggeler, Burkhard

2018-01-01

Recent neurophysiological studies indicate that exposure to electromagnetic fields (EMFs) generated by mobile phone radiation can exert effects on brain activity. One technical solution to reduce effects of EMFs in mobile phone use is provided in mobile phone chips that are applied to mobile phones or attached to their surfaces. To date, there are no systematical studies on the effects of mobile phone chip application on brain activity and the underlying neural mechanisms. The present study investigated whether mobile phone chips that are applied to mobile phones reduce effects of EMFs emitted by mobile phone radiation on electroencephalographic (EEG) brain activity in a laboratory study. Thirty participants volunteered in the present study. Experimental conditions (mobile phone chip, placebo chip, no chip) were set up in a randomized within-subjects design. Spontaneous EEG was recorded before and after mobile phone exposure for two 2-min sequences at resting conditions. During mobile phone exposure, spontaneous EEG was recorded for 30 min during resting conditions, and 5 min during performance of an attention test (d2-R). Results showed increased activity in the theta, alpha, beta and gamma bands during EMF exposure in the placebo and no chip conditions. Application of the mobile phone chip reduced effects of EMFs on EEG brain activity and attentional performance significantly. Attentional performance level was maintained regarding number of edited characters. Further, a dipole analysis revealed different underlying activation patterns in the chip condition compared to the placebo chip and no chip conditions. Finally, a correlational analysis for the EEG frequency bands and electromagnetic high-frequency (HF) emission showed significant correlations in the placebo chip and no chip condition for the theta, alpha, beta, and gamma bands. In the chip condition, a significant correlation of HF with the theta and alpha bands, but not with the beta and gamma bands was shown. We hypothesize that a reduction of EEG beta and gamma activation constitutes the key neural mechanism in mobile phone chip use that supports the brain to a degree in maintaining its natural activity and performance level during mobile phone use.

Mobile Phone Chips Reduce Increases in EEG Brain Activity Induced by Mobile Phone-Emitted Electromagnetic Fields

PubMed Central

Henz, Diana; Schöllhorn, Wolfgang I.; Poeggeler, Burkhard

2018-01-01

Recent neurophysiological studies indicate that exposure to electromagnetic fields (EMFs) generated by mobile phone radiation can exert effects on brain activity. One technical solution to reduce effects of EMFs in mobile phone use is provided in mobile phone chips that are applied to mobile phones or attached to their surfaces. To date, there are no systematical studies on the effects of mobile phone chip application on brain activity and the underlying neural mechanisms. The present study investigated whether mobile phone chips that are applied to mobile phones reduce effects of EMFs emitted by mobile phone radiation on electroencephalographic (EEG) brain activity in a laboratory study. Thirty participants volunteered in the present study. Experimental conditions (mobile phone chip, placebo chip, no chip) were set up in a randomized within-subjects design. Spontaneous EEG was recorded before and after mobile phone exposure for two 2-min sequences at resting conditions. During mobile phone exposure, spontaneous EEG was recorded for 30 min during resting conditions, and 5 min during performance of an attention test (d2-R). Results showed increased activity in the theta, alpha, beta and gamma bands during EMF exposure in the placebo and no chip conditions. Application of the mobile phone chip reduced effects of EMFs on EEG brain activity and attentional performance significantly. Attentional performance level was maintained regarding number of edited characters. Further, a dipole analysis revealed different underlying activation patterns in the chip condition compared to the placebo chip and no chip conditions. Finally, a correlational analysis for the EEG frequency bands and electromagnetic high-frequency (HF) emission showed significant correlations in the placebo chip and no chip condition for the theta, alpha, beta, and gamma bands. In the chip condition, a significant correlation of HF with the theta and alpha bands, but not with the beta and gamma bands was shown. We hypothesize that a reduction of EEG beta and gamma activation constitutes the key neural mechanism in mobile phone chip use that supports the brain to a degree in maintaining its natural activity and performance level during mobile phone use. PMID:29670503

Charge integration successive approximation analog-to-digital converter for focal plane applications using a single amplifier

NASA Technical Reports Server (NTRS)

Zhou, Zhimin (Inventor); Pain, Bedabrata (Inventor)

1999-01-01

An analog-to-digital converter for on-chip focal-plane image sensor applications. The analog-to-digital converter utilizes a single charge integrating amplifier in a charge balancing architecture to implement successive approximation analog-to-digital conversion. This design requires minimal chip area and has high speed and low power dissipation for operation in the 2-10 bit range. The invention is particularly well suited to CMOS on-chip applications requiring many analog-to-digital converters, such as column-parallel focal-plane architectures.

The Coronary Health Improvement Projects Impact on Lowering Eating, Sleep, Stress, and Depressive Disorders

ERIC Educational Resources Information Center

Merrill, Ray M.; Aldana, Stephen G.; Greenlaw, Roger L.; Diehl, Hans A.

2008-01-01

Background: The Coronary Health Improvement Project (CHIP) is designed to lower cardiovascular risk factors among a group of generally healthy individuals through health education. Purpose: This study will evaluate the efficacy of the CHIP intervention at improving eating, sleep, stress, and depressive disorders. Methods: A health education…

INVESTIGATION OF RECYCLED TIRE CHIPS FOR USE IN GDOT CONCRETE USED TO CONSTRUCT BARRIER WALLS AND OTHER APPLIATIONS–PHASE I

DOT National Transportation Integrated Search

2017-09-01

In 2013, GDOT constructed more than 42,000 LF of concrete barrier utilizing a Class A concrete mixture design (3000 psi). There may be potential for the beneficial utilization of recycled tire chips in concrete barrier applications which can possibly...

On board processor development for NASA's spaceborne imaging radar with system-on-chip technology

NASA Technical Reports Server (NTRS)

Fang, Wai-Chi

2004-01-01

This paper reports a preliminary study result of an on-board spaceborne SAR processor. It consists of a processing requirement analysis, functional specifications, and implementation with system-on-chip technology. Finally, a minimum version of this on-board processor designed for performance evaluation and for partial demonstration is illustrated.

Chocolate Chip Cookies and Rubrics: Helping Students Understand Rubrics in Inclusive Settings.

ERIC Educational Resources Information Center

Hall, Elizabeth Wikfors; Salmon, Susan J.

2003-01-01

This article discusses how teachers can familiarize their students, with and without disabilities, with rubric terminology and the use of rubrics. It addresses why rubrics should be used, designing a rubric, and current uses of rubrics. A chocolate chip cookie rubric is provided as an example. (Contains 7 references.) (CR)

A 0.18 μm CMOS low-power radiation sensor for asynchronous event-driven UWB wireless transmission

NASA Astrophysics Data System (ADS)

Bastianini, S.; Crepaldi, M.; Demarchi, D.; Gabrielli, A.; Lolli, M.; Margotti, A.; Villani, G.; Zhang, Z.; Zoccoli, G.

2013-12-01

The paper describes the design of a readout element, proposed as a radiation monitor, which implements an embedded sensor based on a floating-gate transistor. The paper shows the design of a microelectronic circuit composed of a sensor, an oscillator, a modulator, a transmitter and an integrated antenna. A prototype chip has recently been fabricated and tested exploiting a commercial 180 nm, four metal CMOS technology. Simulation results of the entire behavior of the circuit before submission are presented along with some measurements of the actual chip response. In addition, preliminary tests of the performance of the Ultra-Wide Band transmission via the integrated antenna are summarized. As the complete chip prototype area is less than 1 mm2, the chip fits a large variety of applications, from spot radiation monitoring systems in medicine to punctual measurements of radiation level in High-Energy Physics experiments. A sensitivity of 1 mV/rad was estimated within an absorbed dose range up to 10 krad and a total power consumption of about 165 μW.

Design of a high-efficiency train headlamp with low power consumption using dual half-parabolic aluminized reflectors.

PubMed

Liang, Wei-Lun; Su, Guo-Dung J

2018-02-20

We propose a train headlamp system using dual half-circular parabolic aluminized reflectors. Each half-circular reflector contains five high-efficiency and small-package light-emitting diode (LED) chips, and the halves are 180° rotationally symmetric. For traffic safety, the headlamp satisfies the Code of Federal Regulations. To predict the pattern of illumination, an analytical derivation is developed for the optical path of a ray that is perpendicular to and emitted from the center of an LED chip. This ray represents the main ray emitted from the LED chip and is located at the maximum illuminance of the spot projected by the LED source onto a screen. We then analyze the design systematically to determine the locations of the LED chips in the reflector that minimize electricity consumption while satisfying reliability constraints associated with traffic safety. Compared to a typical train headlamp system with an incandescent or halogen lamp needing several hundred watts, the proposed system only uses 20.18 W to achieve the luminous intensity requirements.

A 0.7 V 6.66-9.36 GHz wide tuning range CMOS LC VCO with small chip size

NASA Astrophysics Data System (ADS)

Chen, Jun-Da; Zhang, Jie

2017-10-01

The circuit designs are based on TSMC 0.18 μm CMOS standard technology model. The designed circuit uses transformer coupling technology in order to decrease chip area and increase the Q value. The switched-capacitor topology array enables the voltage-controlled oscillator (VCO) to be tuned between 6.66 and 9.36 GHz with 4.9 mW power consumption at supply voltage of 0.7 V, and the tuning range of the circuit can reach 33.7%. The measured phase noise is -110.5 dBc/Hz at 1 MHz offset from the carrier frequency of 7.113 GHz. The output power level is about -1.22 dBm. The figure-of-merit and figure-of-merit-with-tuning range of the VCO are about -180.7 and -191.25 dBc/Hz, respectively. The chip area is 0.429 mm2 excluding the pads. The presented ultra-wideband VCO leads to a better performance in terms of power consumption, tuning range, chip size and output power level for low supply voltage.

Design and implementation of a reconfigurable mixed-signal SoC based on field programmable analog arrays

NASA Astrophysics Data System (ADS)

Liu, Lintao; Gao, Yuhan; Deng, Jun

2017-11-01

This work presents a reconfigurable mixed-signal system-on-chip (SoC), which integrates switched-capacitor-based field programmable analog arrays (FPAA), analog-to-digital converter (ADC), digital-to-analog converter, digital down converter , digital up converter, 32-bit reduced instruction-set computer central processing unit (CPU) and other digital IPs on a single chip with 0.18 μm CMOS technology. The FPAA intellectual property could be reconfigured as different function circuits, such as gain amplifier, divider, sine generator, and so on. This single-chip integrated mixed-signal system is a complete modern signal processing system, occupying a die area of 7 × 8 mm 2 and consuming 719 mW with a clock frequency of 150 MHz for CPU and 200 MHz for ADC/DAC. This SoC chip can help customers to shorten design cycles, save board area, reduce the system power consumption and depress the system integration risk, which would afford a big prospect of application for wireless communication. Project supported by the National High Technology and Development Program of China (No. 2012AA012303).

Design and characterization of a hybrid-integrated MEMS scanning grating spectrometer

NASA Astrophysics Data System (ADS)

Grüger, Heinrich; Knobbe, Jens; Pügner, Tino; Schenk, Harald

2013-03-01

Grating spectrometer, like the well-established Czerny-Turner, are based on an optical design consisting of several components. Typically at least two slits, two mirrors, the grating stage and a detector are required. There has been much work to reduce this effort, setups using only one mirror (Ebert - Fastie) or the replacement of the entrance slit through the use of thin optical fibers as well as integrated electronic detector arrays instead of a moving grating and an exit slit and single detector device have been applied. Reduced effort comes along with performance limitations: Either the optical resolution or throughput is affected or the use of the system is limited to the availability of detectors arrays with reasonable price. Components in micro opto electro mechanical systems (MOEMS-) technology and spectroscopic systems based thereon have been developed to improve this situation. Miniaturized scanning gratings fabricated on bonded silicon on insulator (BSOI-) wafers were used to design grating spectrometer for the near infrared requiring single detectors only. Discrete components offer flexibility but also need for adjustment of two mirrors, grating stage, fiber mount and the detector with its slit and optionally a second slit in the entrance area. Further development leads towards the integration of the slits into the MOEMS chip, thus less effort for adjustment. Flexibility might be reduced as adjustments of the optical design or grating spacing would require a new chip with own set of masks. Nevertheless if extreme miniaturization is desired this approach seems to be promising. Besides this, high volume production might be able for a comparable low price. A new chip was developed offering grating, two slits and a cavity for the detector chip. The optical design was adjusted to a planar arrangement of grating and slits. A detector buried in a chip cavity required a new mounting strategy. Other optical components were optimized and fabricated then the systems was assembled with electronics and software adjusted to the new design including some new features like integrated position sensors. A first test of systems to grant function of all components is presented. Further work will be aimed at improved performance like higher resolution and lower SNR.

Construction of 3D multicellular microfluidic chip for an in vitro skin model.

PubMed

Lee, Sojin; Jin, Seon-Pil; Kim, Yeon Kyung; Sung, Gun Yong; Chung, Jin Ho; Sung, Jong Hwan

2017-06-01

Current in vitro skin models do not recapitulate the complex architecture and functions of the skin tissue. In particular, on-chip construction of an in vitro model comprising the epidermis and dermis layer with vascular structure for mass transport has not been reported yet. In this study, we aim to develop a microfluidic, three-dimensional (3D) skin chip with fluidic channels using PDMS and hydrogels. Mass transport within the collagen hydrogel matrix was verified with fluorescent model molecules, and a transport-reaction model of oxygen and glucose inside the skin chip was developed to aid the design of the microfluidic skin chip. Comparison of viabilities of dermal fibroblasts and HaCaT cultured in the chip with various culture conditions revealed that the presence of flow plays a crucial role in maintaining the viability, and both cells were viable after 10 days of air exposure culture. Our 3D skin chip with vascular structures can be a valuable in vitro model for reproducing the interaction between different components of the skin tissue, and thus work as a more physiologically realistic platform for testing skin reaction to cosmetic products and drugs.

Lab-on-a-chip modules for detection of highly pathogenic bacteria: from sample preparation to detection

NASA Astrophysics Data System (ADS)

Julich, S.; Kopinč, R.; Hlawatsch, N.; Moche, C.; Lapanje, A.; Gärtner, C.; Tomaso, H.

2014-05-01

Lab-on-a-chip systems are innovative tools for the detection and identification of microbial pathogens in human and veterinary medicine. The major advantages are small sample volume and a compact design. Several fluidic modules have been developed to transform analytical procedures into miniaturized scale including sampling, sample preparation, target enrichment, and detection procedures. We present evaluation data for single modules that will be integrated in a chip system for the detection of pathogens. A microfluidic chip for purification of nucleic acids was established for cell lysis using magnetic beads. This assay was evaluated with spiked environmental aerosol and swab samples. Bacillus thuringiensis was used as simulant for Bacillus anthracis, which is closely related but non-pathogenic for humans. Stationary PCR and a flow-through PCR chip module were investigated for specific detection of six highly pathogenic bacteria. The conventional PCR assays could be transferred into miniaturized scale using the same temperature/time profile. We could demonstrate that the microfluidic chip modules are suitable for the respective purposes and are promising tools for the detection of bacterial pathogens. Future developments will focus on the integration of these separate modules to an entire lab-on-a-chip system.

Missileborne Artificial Vision System (MAVIS)

NASA Technical Reports Server (NTRS)

Andes, David K.; Witham, James C.; Miles, Michael D.

1994-01-01

Several years ago when INTEL and China Lake designed the ETANN chip, analog VLSI appeared to be the only way to do high density neural computing. In the last five years, however, digital parallel processing chips capable of performing neural computation functions have evolved to the point of rough equality with analog chips in system level computational density. The Naval Air Warfare Center, China Lake, has developed a real time, hardware and software system designed to implement and evaluate biologically inspired retinal and cortical models. The hardware is based on the Adaptive Solutions Inc. massively parallel CNAPS system COHO boards. Each COHO board is a standard size 6U VME card featuring 256 fixed point, RISC processors running at 20 MHz in a SIMD configuration. Each COHO board has a companion board built to support a real time VSB interface to an imaging seeker, a NTSC camera, and to other COHO boards. The system is designed to have multiple SIMD machines each performing different corticomorphic functions. The system level software has been developed which allows a high level description of corticomorphic structures to be translated into the native microcode of the CNAPS chips. Corticomorphic structures are those neural structures with a form similar to that of the retina, the lateral geniculate nucleus, or the visual cortex. This real time hardware system is designed to be shrunk into a volume compatible with air launched tactical missiles. Initial versions of the software and hardware have been completed and are in the early stages of integration with a missile seeker.

Development of polypyrrole based solid-state on-chip microactuators using photolithography

NASA Astrophysics Data System (ADS)

Zhong, Yong; Lundemo, Staffan; Jager, Edwin W. H.

2018-07-01

There is a need for soft microactuators, especially for biomedical applications. We have developed a microfabrication process to create such soft, on-chip polymer based microactuators that can operate in air. The on-chip microactuators were fabricated using standard photolithographic techniques and wet etching, combined with special designed process to micropattern the electroactive polymer polypyrrole that drives the microactuators. By immobilizing a UV-patternable gel containing a liquid electrolyte on top of the electroactive polypyrrole layer, actuation in air was achieved although with reduced movement. Further optimization of the processing is currently on-going. The result shows the possibility to batch fabricate complex microsystems such as microrobotics and micromanipulators based on these solid-state on-chip microactuators using microfabrication methods including standard photolithographic processes.

Insertion of GaAs MMICs into EW systems

NASA Astrophysics Data System (ADS)

Schineller, E. R.; Pospishil, A.; Grzyb, J.

1989-09-01

Development activities on a microwave/mm-wave monolithic IC (MIMIC) program are described, as well as the methodology for inserting these GaAs IC chips into several EW systems. The generic EW chip set developed on the MIMIC program consists of 23 broadband chip types, including amplifiers, oscillators, mixers, switches, variable attenuators, power dividers, and power combiners. These chips are being designed for fabrication using the multifunction self-aligned gate process. The benefits from GaAs IC insertion are quantified by a comparison of hardware units fabricated with existing MIC and digital ECL technology and the same units manufactured with monolithic technology. It is found that major improvements in cost, reliability, size, weight, and performance can be realized. Examples illustrating the methodology for technology insertion are presented.

On-chip spin-controlled orbital angular momentum directional coupling

NASA Astrophysics Data System (ADS)

Xie, Zhenwei; Lei, Ting; Si, Guangyuan; Du, Luping; Lin, Jiao; Min, Changjun; Yuan, Xiaocong

2018-01-01

Optical vortex beams have many potential applications in the particle trapping, quantum encoding, optical orbital angular momentum (OAM) communications and interconnects. However, the on-chip compact OAM detection is still a big challenge. Based on a holographic configuration and a spin-dependent structure design, we propose and demonstrate an on-chip spin-controlled OAM-mode directional coupler, which can couple the OAM signal to different directions due to its topological charge. While the directional coupling function can be switched on/off by altering the spin of incident beam. Both simulation and experimental measurements verify the validity of the proposed approach. This work would benefit the on-chip OAM devices for optical communications and high dimensional quantum coding/decoding in the future.

Statistical evaluation of metal fill widths for emulated metal fill in parasitic extraction methodology

NASA Astrophysics Data System (ADS)

J-Me, Teh; Noh, Norlaili Mohd.; Aziz, Zalina Abdul

2015-05-01

In the chip industry today, the key goal of a chip development organization is to develop and market chips within a short time frame to gain foothold on market share. This paper proposes a design flow around the area of parasitic extraction to improve the design cycle time. The proposed design flow utilizes the usage of metal fill emulation as opposed to the current flow which performs metal fill insertion directly. By replacing metal fill structures with an emulation methodology in earlier iterations of the design flow, this is targeted to help reduce runtime in fill insertion stage. Statistical design of experiments methodology utilizing the randomized complete block design was used to select an appropriate emulated metal fill width to improve emulation accuracy. The experiment was conducted on test cases of different sizes, ranging from 1000 gates to 21000 gates. The metal width was varied from 1 x minimum metal width to 6 x minimum metal width. Two-way analysis of variance and Fisher's least significant difference test were used to analyze the interconnect net capacitance values of the different test cases. This paper presents the results of the statistical analysis for the 45 nm process technology. The recommended emulated metal fill width was found to be 4 x the minimum metal width.

3D Stacked Memory Final Report CRADA No. TC-0494-93

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bernhardt, A.; Beene, G.

TI and LLNL demonstrated: (1) a process for the fabrication of 3-D memory using stacked DRAM chips, and (2) a fast prototyping process for 3-D stacks and MCMs. The metallization to route the chip pads to the sides of the die was carried out in a single high-speed masking step. The mask was not the usual physical one in glass and chrome, but was simply a computer file used to control the laser patterning process. Changes in either chip or customer circuit-board pad layout were easily and inexpensively accommodated, so that prototyping was a natural consequence of the laser patterningmore » process. As in the current TI process, a dielectric layer was added to the wafer, and vias to the chip I/0 pads were formed. All of the steps in Texas Instruments earlier process that were required to gold bump the pads were eliminated, significantly reducing fabrication cost and complexity. Pads were created on the sides of ·the die, which became pads on the side of the stack. In order to extend the process to accommodate non-memory devices with substantially greater I/0 than is required for DRAMs, pads were patterned on two sides of the memory stacks as a proof of principle. Stacking and bonding were done using modifications of the current TI process. After stacking and bonding, the pads on the sides of the dice were connected by application of a polyimide insulator film with laser ablation of the polyimide to form contacts to the pads. Then metallization was accomplished in the same manner as on the individual die.« less

Accessing files in an Internet: The Jade file system

NASA Technical Reports Server (NTRS)

Peterson, Larry L.; Rao, Herman C.

1991-01-01

Jade is a new distribution file system that provides a uniform way to name and access files in an internet environment. It makes two important contributions. First, Jade is a logical system that integrates a heterogeneous collection of existing file systems, where heterogeneous means that the underlying file systems support different file access protocols. Jade is designed under the restriction that the underlying file system may not be modified. Second, rather than providing a global name space, Jade permits each user to define a private name space. These private name spaces support two novel features: they allow multiple file systems to be mounted under one directory, and they allow one logical name space to mount other logical name spaces. A prototype of the Jade File System was implemented on Sun Workstations running Unix. It consists of interfaces to the Unix file system, the Sun Network File System, the Andrew File System, and FTP. This paper motivates Jade's design, highlights several aspects of its implementation, and illustrates applications that can take advantage of its features.

Accessing files in an internet - The Jade file system

NASA Technical Reports Server (NTRS)

Rao, Herman C.; Peterson, Larry L.

1993-01-01

Jade is a new distribution file system that provides a uniform way to name and access files in an internet environment. It makes two important contributions. First, Jade is a logical system that integrates a heterogeneous collection of existing file systems, where heterogeneous means that the underlying file systems support different file access protocols. Jade is designed under the restriction that the underlying file system may not be modified. Second, rather than providing a global name space, Jade permits each user to define a private name space. These private name spaces support two novel features: they allow multiple file systems to be mounted under one directory, and they allow one logical name space to mount other logical name spaces. A prototype of the Jade File System was implemented on Sun Workstations running Unix. It consists of interfaces to the Unix file system, the Sun Network File System, the Andrew File System, and FTP. This paper motivates Jade's design, highlights several aspects of its implementation, and illustrates applications that can take advantage of its features.

Respiration detection chip with integrated temperature-insensitive MEMS sensors and CMOS signal processing circuits.

PubMed

Wei, Chia-Ling; Lin, Yu-Chen; Chen, Tse-An; Lin, Ren-Yi; Liu, Tin-Hao

2015-02-01

An airflow sensing chip, which integrates MEMS sensors with their CMOS signal processing circuits into a single chip, is proposed for respiration detection. Three micro-cantilever-based airflow sensors were designed and fabricated using a 0.35 μm CMOS/MEMS 2P4M mixed-signal polycide process. Two main differences were present among these three designs: they were either metal-covered or metal-free structures, and had either bridge-type or fixed-type reference resistors. The performances of these sensors were measured and compared, including temperature sensitivity and airflow sensitivity. Based on the measured results, the metal-free structure with fixed-type reference resistors is recommended for use, because it has the highest airflow sensitivity and also can effectively reduce the output voltage drift caused by temperature change.

Stitching-aware in-design DPT auto fixing for sub-20nm logic devices

NASA Astrophysics Data System (ADS)

Choi, Soo-Han; Sai Krishna, K. V. V. S.; Pemberton-Smith, David

2017-03-01

As the technology continues to shrink below 20nm, Double Patterning Technology (DPT) becomes one of the mandatory solutions for routing metal layers. From the view point of Place and Route (P&R), the major concerns are how to prevent DPT odd-cycles automatically without sacrificing chip area. Even though the leading-edge P&R tools have advanced algorithms to prevent DPT odd-cycles, it is very hard to prevent the localized DPT odd-cycles, especially in Engineering Change Order (ECO) routing. In the last several years, we developed In-design DPT Auto Fixing method in order to reduce localized DPT odd-cycles significantly during ECO and could achieve remarkable design Turn-Around Times (TATs). But subsequently, as the design complexity continued increasing and chip size continued decreasing, we needed a new In-design DPT Auto Fixing approach to improve the auto. fixing rate. In this paper, we present the Stitching-Aware In-design DPT Auto Fixing method for better fixing rates and smaller chip design. The previous In-design DPT Auto Fixing method detected all DPT odd-cycles and tried to remove oddcycles by increasing the adjacent space. As the metal congestions increase in the newer technology nodes, the older Auto Fixing method has limitations to increase the adjacent space between routing metals. Consequently, the auto fixing rate of older method gets worse with the introduction of the smaller design rules. With DPT stitching enablement at In-design DRC checking procedure, the new Stitching-Aware DPT Auto Fixing method detects the most critical odd-cycles and revolve the odd-cycles automatically. The accuracy of new flow ensures better usage of space in the congested areas, and helps design more smaller chips. By applying the Stitching-Aware DPT Auto Fixing method to sub-20nm logic devices, we can confirm that the auto fixing rate is improved by 2X compared with auto fixing without stitching. Additionally, by developing the better heuristic algorithm and flow for DPT stitching, we can get DPT compliant layout with the acceptable design TATs.

Analytical study of a microfludic DNA amplification chip using water cooling effect.

PubMed

Chen, Jyh Jian; Shen, Chia Ming; Ko, Yu Wei

2013-04-01

A novel continuous-flow polymerase chain reaction (PCR) chip has been analyzed in our work. Two temperature zones are controlled by two external controllers and the other temperature zone at the chip center is controlled by the flow rate of the fluid inside a channel under the glass chip. By employing a water cooling channel at the chip center, the sequence of denaturation, annealing, and extension can be created due to the forced convection effect. The required annealing temperature of PCR less than 313 K can also be demonstrated in this chip. The Poly(methyl methacrylate) (PMMA) cooling channel with the thin aluminum cover is utilized to enhance the temperature uniformity. The size of this chip is 76 mm × 26 mm × 3 mm. This device represents the first demonstration of water cooling thermocycling within continuous-flow PCR microfluidics. The commercial software CFD-ACE+(TM) is utilized to determine the distances between the heating assemblies within the chip. We investigate the influences of various chip materials, operational parameters of the cooling channel and geometric parameters of the chip on the temperature uniformity on the chip surface. Concerning the temperature uniformity of the working zones and the lowest temperature at the annealing zone, the air gap spacing of 1 mm and the cooling channel thicknesses of 1 mm of the PMMA channel with an aluminum cover are recommended in our design. The hydrophobic surface of the PDMS channel was modified by filling it with 20 % Tween 20 solution and then adding bovine serum albumin (BSA) solution to the PCR mixture. DNA fragments with different lengths (372 bp and 478 bp) are successfully amplified with the device.

Design of the micro pressure multi-node measuring system for micro-fluidic chip

NASA Astrophysics Data System (ADS)

Mu, Lili; Guo, Shuheng; Rong, Li; Yin, Ke

2016-01-01

An online multi-node microfludic pressure measuring system was designed in the paper. The research focused on the design of pressure test circuit system and methods on dealing with pressure data collecting. The MPXV7002 micro-pressure sensor was selected to measure the chip inside channel pressure and installed by a silicone tube on different micro-channel measured nodes. The pressure transmission loss was estimated in the paper, and corrected by the filtering and smoothing method. The pressure test experiment was carried out and the data were analyzed. Finally, the measuring system was calibrated. The results showed that the measuring system had high testing precision.

A single chip VLSI Reed-Solomon decoder

NASA Technical Reports Server (NTRS)

Shao, H. M.; Truong, T. K.; Hsu, I. S.; Deutsch, L. J.; Reed, I. S.

1986-01-01

A new VLSI design of a pipeline Reed-Solomon decoder is presented. The transform decoding technique used in a previous design is replaced by a time domain algorithm. A new architecture that implements such an algorithm permits efficient pipeline processing with minimum circuitry. A systolic array is also developed to perform erasure corrections in the new design. A modified form of Euclid's algorithm is implemented by a new architecture that maintains the throughput rate with less circuitry. Such improvements result in both enhanced capability and a significant reduction in silicon area, therefore making it possible to build a pipeline (31,15)RS decoder on a single VLSI chip.

Radiation hard analog circuits for ALICE ITS upgrade

NASA Astrophysics Data System (ADS)

Gajanana, D.; Gromov, V.; Kuijer, P.; Kugathasan, T.; Snoeys, W.

2016-03-01

The ALICE experiment is planning to upgrade the ITS (Inner Tracking System) [1] detector during the LS2 shutdown. The present ITS will be fully replaced with a new one entirely based on CMOS monolithic pixel sensor chips fabricated in TowerJazz CMOS 0.18 μ m imaging technology. The large (3 cm × 1.5 cm = 4.5 cm2) ALPIDE (ALICE PIxel DEtector) sensor chip contains about 500 Kpixels, and will be used to cover a 10 m2 area with 12.5 Gpixels distributed over seven cylindrical layers. The ALPOSE chip was designed as a test chip for the various building blocks foreseen in the ALPIDE [2] pixel chip from CERN. The building blocks include: bandgap and Temperature sensor in four different flavours, and LDOs for powering schemes. One flavour of bandgap and temperature sensor will be included in the ALPIDE chip. Power consumption numbers have dropped very significantly making the use of LDOs less interesting, but in this paper all blocks are presented including measurement results before and after irradiation with neutrons to characterize robustness against displacement damage.

[The development of an intelligent four-channel aggregometer].

PubMed

Guan, X; Wang, M

1998-07-01

The paper introduces the hardware and software design of the instrument. We use 89C52 single-chip computer as the microprocessor to control the amplifier, AD and DA conversion chip to realize the sampling, data process, printout and supervision. The final result is printed out in form of data and aggregation curve from PP40 plotter.

Design and Implement of Low Ripple and Quasi-digital Power Supply

NASA Astrophysics Data System (ADS)

Xiangli, Li; Yanjun, Wei; Hanhong, Qi; Yan, Ma

A switch linearity hybrid power supply based on single chip microcomputer is designed which merged the merits of the switching and linear power supply. Main circuit includes pre-regulator which works in switching mode and series regulator which works in linear mode. Two-stage regulation mode was adopted in the main circuit of the power. A single chip computer (SCM) and high resolution of series D/A and A/D converters are applied to control and measurement which achieved continuous adjustable and low ripple constant current or voltage power supply

Real-Time Reed-Solomon Decoder

NASA Technical Reports Server (NTRS)

Maki, Gary K.; Cameron, Kelly B.; Owsley, Patrick A.

1994-01-01

Generic Reed-Solomon decoder fast enough to correct errors in real time in practical applications designed to be implemented in fewer and smaller very-large-scale integrated, VLSI, circuit chips. Configured to operate in pipelined manner. One outstanding aspect of decoder design is that Euclid multiplier and divider modules contain Galoisfield multipliers configured as combinational-logic cells. Operates at speeds greater than older multipliers. Cellular configuration highly regular and requires little interconnection area, making it ideal for implementation in extraordinarily dense VLSI circuitry. Flight electronics single chip version of this technology implemented and available.

A CMOS 0.18 μm 600 MHz clock multiplier PLL and a pseudo-LVDS driver for the high speed data transmission for the ALICE Inner Tracking System front-end chip

NASA Astrophysics Data System (ADS)

Lattuca, A.; Mazza, G.; Aglieri Rinella, G.; Cavicchioli, C.; Chanlek, N.; Collu, A.; Degerli, Y.; Dorokhov, A.; Flouzat, C.; Gajanana, D.; Gao, C.; Guilloux, F.; Hillemanns, H.; Hristozkov, S.; Junique, A.; Keil, M.; Kim, D.; Kofarago, M.; Kugathasan, T.; Kwon, Y.; Mager, M.; Sielewicz, K. Marek; Marin Tobon, C. Augusto; Marras, D.; Martinengo, P.; Mugnier, H.; Musa, L.; Pham, T. Hung; Puggioni, C.; Reidt, F.; Riedler, P.; Rousset, J.; Siddhanta, S.; Snoeys, W.; Song, M.; Usai, G.; Van Hoorne, J. Willem; Yang, P.

2016-01-01

This work presents the 600 MHz clock multiplier PLL and the pseudo-LVDS driver which are two essential components of the Data Transmission Unit (DTU), a fast serial link for the 1.2 Gb/s data transmission of the ALICE inner detector front-end chip (ALPIDE). The PLL multiplies the 40 MHz input clock in order to obtain the 600 MHz and the 200 MHz clock for a fast serializer which works in Double Data Rate mode. The outputs of the serializer feed the pseudo-LVDS driver inputs which transmits the data from the pixel chip to the patch panel with a limited number of signal lines. The driver drives a 5.3 m-6.5 m long differential transmission line by steering a maximum of 5 mA of current at the target speed. To overcome bandwidth limitations coming from the long cables the pre-emphasis can be applied to the output. Currents for the main and pre-emphasis driver can individually be adjusted using on-chip digital-to-analog converters. The circuits will be integrated in the pixel chip and are designed in the same 0.18 μm CMOS technology and will operate from the same 1.8 V supply. Design and test results of both circuits are presented.

Numerical Investigation of a Chip Printed Antenna Performances for Wireless Implantable Body Area Network Applications

NASA Astrophysics Data System (ADS)

Ramli, N. H.; Jaafar, H.; Lee, Y. S.

2018-03-01

Recently, wireless implantable body area network (WiBAN) system become an active area of research due to their various applications such as healthcare, support systems for specialized occupations and personal communications. Biomedical sensors networks mounted in the human body have drawn greater attention for health care monitoring systems. The implantable chip printed antenna for WiBAN applications is designed and the antenna performances is investigated in term of gain, efficiency, return loss, operating bandwidth and radiation pattern at different environments. This paper is presents the performances of implantable chip printed antenna in selected part of human body (hand, chest, leg, heart and skull). The numerical investigation is done by using human voxel model in built in the CST Microwave Studio Software. Results proved that the chip printed antenna is suitable to implant in the human hand model. The human hand model has less complex structure as it consists of skin, fat, muscle, blood and bone. Moreover, the antenna is implanted under the skin. Therefore the signal propagation path length to the base station at free space environment is considerably short. The antenna’s gain, efficiency and Specific Absorption Rate (SAR) are - 13.62dBi, 1.50 % and 0.12 W/kg respectively; which confirms the safety of the antenna usage. The results of the investigations can be used as guidance while designing chip implantable antenna in future.

Microfluidic Mixing Technology for a Universal Health Sensor

NASA Technical Reports Server (NTRS)

Chan, Eugene Y.; Bae, Candice

2009-01-01

A highly efficient means of microfluidic mixing has been created for use with the rHEALTH sensor an elliptical mixer and passive curvilinear mixing patterns. The rHEALTH sensor provides rapid, handheld, complete blood count, cell differential counts, electrolyte measurements, and other lab tests based on a reusable, flow-based microfluidic platform. These geometries allow for cleaning in a reusable manner, and also allow for complete mixing of fluid streams. The microfluidic mixing is performed by flowing two streams of fluid into an elliptical or curvilinear design that allows the combination of the flows into one channel. The mixing is accomplished by either chaotic advection around micro - fluidic loops. All components of the microfluidic chip are flow-through, meaning that cleaning solution can be introduced into the chip to flush out cells, plasma proteins, and dye. Tests were performed on multiple chip geometries to show that cleaning is efficient in any flowthrough design. The conclusion from these experiments is that the chip can indeed be flushed out with microliter volumes of solution and biological samples are cleaned readily from the chip with minimal effort. The technology can be applied in real-time health monitoring at patient s bedside or in a doctor s office, and real-time clinical intervention in acute situations. It also can be used for daily measurement of hematocrit for patients on anticoagulant drugs, or to detect acute myocardial damage outside a hospital.

GeoChip 3.0 as a high-thoughput tool for analyzing microbial community composition, structure, and functional activity

DOE Office of Scientific and Technical Information (OSTI.GOV)

He, Z.; Deng, Y.; Van Nostrand, J.D.

A new generation of functional gene arrays (FGAs; GeoChip 3.0) has been developed, with {approx}28,000 probes covering approximately 57,000 gene variants from 292 functional gene families involved in carbon, nitrogen, phosphorus and sulfur cycles, energy metabolism, antibiotic resistance, metal resistance and organic contaminant degradation. GeoChip 3.0 also has several other distinct features, such as a common oligo reference standard (CORS) for data normalization and comparison, a software package for data management and future updating and the gyrB gene for phylogenetic analysis. Computational evaluation of probe specificity indicated that all designed probes would have a high specificity to their corresponding targets.more » Experimental analysis with synthesized oligonucleotides and genomic DNAs showed that only 0.0036-0.025% false-positive rates were observed, suggesting that the designed probes are highly specific under the experimental conditions examined. In addition, GeoChip 3.0 was applied to analyze soil microbial communities in a multifactor grassland ecosystem in Minnesota, USA, which showed that the structure, composition and potential activity of soil microbial communities significantly changed with the plant species diversity. As expected, GeoChip 3.0 is a high-throughput powerful tool for studying microbial community functional structure, and linking microbial communities to ecosystem processes and functioning.« less

Research and design of intelligent distributed traffic signal light control system based on CAN bus

NASA Astrophysics Data System (ADS)

Chen, Yu

2007-12-01

Intelligent distributed traffic signal light control system was designed based on technologies of infrared, CAN bus, single chip microprocessor (SCM), etc. The traffic flow signal is processed with the core of SCM AT89C51. At the same time, the SCM controls the CAN bus controller SJA1000/transceiver PCA82C250 to build a CAN bus communication system to transmit data. Moreover, up PC realizes to connect and communicate with SCM through USBCAN chip PDIUSBD12. The distributed traffic signal light control system with three control styles of Vehicle flux, remote and PC is designed. This paper introduces the system composition method and parts of hardware/software design in detail.

An Integrated Unix-based CAD System for the Design and Testing of Custom VLSI Chips

NASA Technical Reports Server (NTRS)

Deutsch, L. J.

1985-01-01

A computer aided design (CAD) system that is being used at the Jet Propulsion Laboratory for the design of custom and semicustom very large scale integrated (VLSI) chips is described. The system consists of a Digital Equipment Corporation VAX computer with the UNIX operating system and a collection of software tools for the layout, simulation, and verification of microcircuits. Most of these tools were written by the academic community and are, therefore, available to JPL at little or no cost. Some small pieces of software have been written in-house in order to make all the tools interact with each other with a minimal amount of effort on the part of the designer.

Digital Filter ASIC for NASA Deep Space Radio Science

NASA Technical Reports Server (NTRS)

Kowalski, James E.

1995-01-01

This paper is about the implementation of an 80 MHz, 16-bit, multi-stage digital filter to decimate by 1600, providing a 50 kHz output with bandpass ripple of less than +/-0.1 dB. The chip uses two decimation by five units and six decimations by two executed by a single decimation by two units. The six decimations by two consist of six halfband filters, five having 30-taps and one having 51-taps. Use of a 16x16 register file for the digital delay lines enables implementation in the Vitesse 350K gate array.

CGO: utilizing and integrating gene expression microarray data in clinical research and data management.

PubMed

Bumm, Klaus; Zheng, Mingzhong; Bailey, Clyde; Zhan, Fenghuang; Chiriva-Internati, M; Eddlemon, Paul; Terry, Julian; Barlogie, Bart; Shaughnessy, John D

2002-02-01

Clinical GeneOrganizer (CGO) is a novel windows-based archiving, organization and data mining software for the integration of gene expression profiling in clinical medicine. The program implements various user-friendly tools and extracts data for further statistical analysis. This software was written for Affymetrix GeneChip *.txt files, but can also be used for any other microarray-derived data. The MS-SQL server version acts as a data mart and links microarray data with clinical parameters of any other existing database and therefore represents a valuable tool for combining gene expression analysis and clinical disease characteristics.

Design, methods, and baseline characteristics of the Kids’ Health Insurance by Educating Lots of Parents (Kids’ HELP) trial: A randomized, controlled trial of the effectiveness of parent mentors in insuring uninsured minority children✰

PubMed Central

Flores, Glenn; Walker, Candy; Lin, Hua; Lee, Michael; Fierro, Marco; Henry, Monica; Massey, Kenneth; Portillo, Alberto

2014-01-01

Background & objectives Six million US children have no health insurance, and substantial racial/ethnic disparities exist. The design, methods, and baseline characteristics are described for Kids’ Health Insurance by Educating Lots of Parents (Kids’ HELP), the first randomized, clinical trial of the effectiveness of Parent Mentors (PMs) in insuring uninsured minority children. Methods & research design Latino and African-American children eligible for but not enrolled in Medicaid/CHIP were randomized to PMs, or a control group receiving traditional Medicaid/CHIP outreach. PMs are experienced parents with ≥ 1 Medicaid/CHIP-covered children. PMs received two days of training, and provide intervention families with information on Medicaid/CHIP eligibility, assistance with application submission, and help maintaining coverage. Primary outcomes include obtaining health insurance, time interval to obtain coverage, and parental satisfaction. A blinded assessor contacts subjects monthly for one year to monitor outcomes. Results Of 49,361 candidates screened, 329 fulfilled eligibility criteria and were randomized. The mean age is seven years for children and 32 years for caregivers; 2/3 are Latino, 1/3 are African-American, and the mean annual family income is $21,857. Half of caregivers were unaware that their uninsured child is Medicaid/CHIP eligible, and 95% of uninsured children had prior insurance. Fifteen PMs completed two-day training sessions. All PMs are female and minority, 60% are unemployed, and the mean annual family income is $20,913. Post-PM-training, overall knowledge/skills test scores significantly increased, and 100% reported being very satisfied/satisfied with the training. Conclusions Kids’ HELP successfully reached target populations, met participant enrollment goals, and recruited and trained PMs. PMID:25476583

Microtechnology in Space: NASA's Lab-on-a-Chip Applications Development Program

NASA Technical Reports Server (NTRS)

Monaco, Lisa; Spearing, Scott; Jenkins, Andy; Symonds, Wes; Mayer, Derek; Gouldie, Edd; Wainwright, Norm; Fries, Marc; Maule, Jake; Toporski, Jan

2004-01-01

NASA's Marshall Space Flight Center (MSFC) Lab on a Chip Application Development LOCAD) team has worked with microfluidic technology for the past few years in an effort to support NASA's Mission. In that time, such microfluidic based Lab-on-a-Chip (LOC) systems have become common technology in clinical and diagnostic laboratories. The approach is most attractive due to its highly miniaturized platform and ability to perform reagent handling (i-e., dilution, mixing, separation) and diagnostics for multiple reactions in an integrated fashion. LOCAD, along with Caliper Life Sciences has successfully developed the first LOC device for macromolecular crystallization using a workstation acquired specifically for designing custom chips, the Caliper 42. LOCAD uses this, along with a novel MSFC-designed and built workstation for microfluidic development. The team has a cadre of LOC devices that can be used to perform initial feasibility testing to determine the efficacy of the LOC approach for a specific application. Once applicability has been established, the LOCAD team, along with the Army's Aviation and Missile Command microfabrication facility, can then begin to custom design and fabricate a device per the user's specifications. This presentation will highlight the LOCAD team's proven and unique expertise that has been utilized to provide end to end capabilities associated with applying microfluidics for applications that include robotic life detection instrumentation, crew health monitoring and microbial and environmental monitoring for human Exploration.

A programmable microsystem using system-on-chip for real-time biotelemetry.

PubMed

Wang, Lei; Johannessen, Erik A; Hammond, Paul A; Cui, Li; Reid, Stuart W J; Cooper, Jonathan M; Cumming, David R S

2005-07-01

A telemetry microsystem, including multiple sensors, integrated instrumentation and a wireless interface has been implemented. We have employed a methodology akin to that for System-on-Chip microelectronics to design an integrated circuit instrument containing several "intellectual property" blocks that will enable convenient reuse of modules in future projects. The present system was optimized for low-power and included mixed-signal sensor circuits, a programmable digital system, a feedback clock control loop and RF circuits integrated on a 5 mm x 5 mm silicon chip using a 0.6 microm, 3.3 V CMOS process. Undesirable signal coupling between circuit components has been investigated and current injection into sensitive instrumentation nodes was minimized by careful floor-planning. The chip, the sensors, a magnetic induction-based transmitter and two silver oxide cells were packaged into a 36 mm x 12 mm capsule format. A base station was built in order to retrieve the data from the microsystem in real-time. The base station was designed to be adaptive and timing tolerant since the microsystem design was simplified to reduce power consumption and size. The telemetry system was found to have a packet error rate of 10(-3) using an asynchronous simplex link. Trials in animal carcasses were carried out to show that the transmitter was as effective as a conventional RF device whilst consuming less power.

A random generation approach to pattern library creation for full chip lithographic simulation

NASA Astrophysics Data System (ADS)

Zou, Elain; Hong, Sid; Liu, Limei; Huang, Lucas; Yang, Legender; Kabeel, Aliaa; Madkour, Kareem; ElManhawy, Wael; Kwan, Joe; Du, Chunshan; Hu, Xinyi; Wan, Qijian; Zhang, Recoo

2017-04-01

As technology advances, the need for running lithographic (litho) checking for early detection of hotspots before tapeout has become essential. This process is important at all levels—from designing standard cells and small blocks to large intellectual property (IP) and full chip layouts. Litho simulation provides high accuracy for detecting printability issues due to problematic geometries, but it has the disadvantage of slow performance on large designs and blocks [1]. Foundries have found a good compromise solution for running litho simulation on full chips by filtering out potential candidate hotspot patterns using pattern matching (PM), and then performing simulation on the matched locations. The challenge has always been how to easily create a PM library of candidate patterns that provides both comprehensive coverage for litho problems and fast runtime performance. This paper presents a new strategy for generating candidate real design patterns through a random generation approach using a layout schema generator (LSG) utility. The output patterns from the LSG are simulated, and then classified by a scoring mechanism that categorizes patterns according to the severity of the hotspots, probability of their presence in the design, and the likelihood of the pattern causing a hotspot. The scoring output helps to filter out the yield problematic patterns that should be removed from any standard cell design, and also to define potential problematic patterns that must be simulated within a bigger context to decide whether or not they represent an actual hotspot. This flow is demonstrated on SMIC 14nm technology, creating a candidate hotspot pattern library that can be used in full chip simulation with very high coverage and robust performance.

SVGA and XGA LCOS microdisplays for HMD applications

NASA Astrophysics Data System (ADS)

Bolotski, Michael; Alvelda, Phillip

1999-07-01

MicroDisplay liquid crystal on silicon (LCOS) display devices are based on a combination of technologies combined with the extreme integration capability of conventionally fabricated CMOS substrates. Two recent SVGA (800 X 600) pixel resolution designs were demonstrated based on 10 micron and 12.5-micron pixel pitch architectures. The resulting microdisplays measure approximately 10 mm and 12 mm in diagonal respectively. Further, an XGA (1024 X 768) resolution display fabricated with a 12.5-micron pixel pitch with a 16-mm diagonal was also demonstrated. Both the larger SVGA and the XGA design were based on the same 12.5-micron pixel-pitch design, demonstrating a quickly scalable design architecture for rapid prototyping life-cycles. All three microdisplay designs described above function in grayscale and high-performance Field-Sequential-Color (FSC) operating modes. The fast liquid crystal operating modes and new scalable high- performance pixel addressing architectures presented in this paper enable substantially improved color, contrast, and brightness while still satisfying the optical, packaging, and power requirements of portable commercial and defense applications including ultra-portable helmet, eyeglass, and heat-mounted systems. The entire suite of The MicroDisplay Corporation's technologies was devised to create a line of mixed-signal application-specific integrated circuits (ASIC) in single-chip display systems. Mixed-signal circuits can integrate computing, memory, and communication circuitry on the same substrate as the display drivers and pixel array for a multifunctional complete system-on-a-chip. For helmet and head-mounted displays this can include capabilities such as the incorporation of customized symbology and information storage directly on the display substrate. System-on-a-chip benefits also include reduced head supported weight requirements through the elimination of off-chip drive electronics.

Wireless neural recording with single low-power integrated circuit.

PubMed

Harrison, Reid R; Kier, Ryan J; Chestek, Cynthia A; Gilja, Vikash; Nuyujukian, Paul; Ryu, Stephen; Greger, Bradley; Solzbacher, Florian; Shenoy, Krishna V

2009-08-01

We present benchtop and in vivo experimental results from an integrated circuit designed for wireless implantable neural recording applications. The chip, which was fabricated in a commercially available 0.6- mum 2P3M BiCMOS process, contains 100 amplifiers, a 10-bit analog-to-digital converter (ADC), 100 threshold-based spike detectors, and a 902-928 MHz frequency-shift-keying (FSK) transmitter. Neural signals from a selected amplifier are sampled by the ADC at 15.7 kSps and telemetered over the FSK wireless data link. Power, clock, and command signals are sent to the chip wirelessly over a 2.765-MHz inductive (coil-to-coil) link. The chip is capable of operating with only two off-chip components: a power/command receiving coil and a 100-nF capacitor.

LLNL Partners with IBM on Brain-Like Computing Chip

DOE Office of Scientific and Technical Information (OSTI.GOV)

Van Essen, Brian

Lawrence Livermore National Laboratory (LLNL) will receive a first-of-a-kind brain-inspired supercomputing platform for deep learning developed by IBM Research. Based on a breakthrough neurosynaptic computer chip called IBM TrueNorth, the scalable platform will process the equivalent of 16 million neurons and 4 billion synapses and consume the energy equivalent of a hearing aid battery – a mere 2.5 watts of power. The brain-like, neural network design of the IBM Neuromorphic System is able to infer complex cognitive tasks such as pattern recognition and integrated sensory processing far more efficiently than conventional chips.

Characterization of 720 and 940 MHz Oscillators with Chip Antenna for Wireless Sensors from Room Temperature to 200 and 250 deg C

NASA Technical Reports Server (NTRS)

Scardelletti, Maximilian C.; Ponchak, George E.

2011-01-01

Oscillators that operate at 720 and 940 MHz and characterized over a temperature range of 25 C to 200 C and 250 C, respectively, are presented. The oscillators are designed on alumina substrates with typical integrated circuit fabrication techniques. Cree SiC MESFETs, thin film metal-insulator-metal capacitors and spiral inductors, and Johanson miniature chip antennas make-up the circuits. The output power and phase noise are presented as a function of temperature and frequency. Index Terms MESFETS, chip antennas, oscillators SiC alumina.

LLNL Partners with IBM on Brain-Like Computing Chip

ScienceCinema

Van Essen, Brian

2018-06-25

Lawrence Livermore National Laboratory (LLNL) will receive a first-of-a-kind brain-inspired supercomputing platform for deep learning developed by IBM Research. Based on a breakthrough neurosynaptic computer chip called IBM TrueNorth, the scalable platform will process the equivalent of 16 million neurons and 4 billion synapses and consume the energy equivalent of a hearing aid battery – a mere 2.5 watts of power. The brain-like, neural network design of the IBM Neuromorphic System is able to infer complex cognitive tasks such as pattern recognition and integrated sensory processing far more efficiently than conventional chips.

Printability Optimization For Fine Pitch Solder Bonding

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kwon, Sang-Hyun; Lee, Chang-Woo; Yoo, Sehoon

2011-01-17

Effect of metal mask and pad design on solder printability was evaluated by DOE in this study. The process parameters were stencil thickness, squeegee angle, squeegee speed, mask separating speed, and pad angle of PCB. The main process parameters for printability were stencil thickness and squeegee angle. The response surface showed that maximum printability of 1005 chip was achieved at the stencil thickness of 0.12 mm while the maximum printability of 0603 and 0402 chip was obtained at the stencil thickness of 0.05 mm. The bonding strength of the MLCC chips was also directly related with the printability.

Improved chip design for integrated solid-phase microextraction in on-line proteomic sample preparation.

PubMed

Bergkvist, Jonas; Ekström, Simon; Wallman, Lars; Löfgren, Mikael; Marko-Varga, György; Nilsson, Johan; Laurell, Thomas

2002-04-01

A recently introduced silicon microextraction chip (SMEC), used for on-line proteomic sample preparation, has proved to facilitate the process of protein identification by sample clean up and enrichment of peptides. It is demonstrated that a novel grid-SMEC design improves the operating characteristics for solid-phase microextraction, by reducing dispersion effects and thereby improving the sample preparation conditions. The structures investigated in this paper are treated both numerically and experimentally. The numerical approach is based on finite element analysis of the microfluidic flow in the microchip. The analysis is accomplished by use of the computational fluid dynamics-module FLOTRAN in the ANSYS software package. The modeling and analysis of the previously reported weir-SMEC design indicates some severe drawbacks, that can be reduced by changing the microextraction chip geometry to the grid-SMEC design. The overall analytical performance was thereby improved and also verified by experimental work. Matrix-assisted laser desorption/ionization mass spectra of model peptides extracted from both the weir-SMEC and the new grid-SMEC support the numerical analysis results. Further use of numerical modeling and analysis of the SMEC structures is also discussed and suggested in this work.

Electrokinetic injection techniques in microfluidic chips.

PubMed

Fu, L M; Yang, R J; Lee, G B; Liu, H H

2002-10-01

The separation efficiency of a microfluidic chip is influenced to a significant degree by the flow field conditions within the injection microchannel. Therefore, an understanding of the physics of the flow within this channel is beneficial in the design and operation of such a system. The configuration of an injection system is determined by the volume of the sample plug that is to be delivered to the separation process. Accordingly, this paper addresses the design and testing of injection systems with a variety of configurations, including a simple cross, a double-T, and a triple-T configuration. This paper also presents the design of a unique multi-T injection configuration. Each injection system cycles through a predetermined series of steps, in which the electric field magnitude and distribution within the various channels is strictly manipulated, to effectuate a virtual valve. The uniquemulti-T configuration injection system presented within this paper has the ability to simulate the functions of the cross, double-T, and triple-T systems through appropriate manipulations of the electric field within its various channels. In other words, the proposed design successfully combines several conventional injection systems within a single microfluidic chip.

Hybrid optofluidic biosensors

NASA Astrophysics Data System (ADS)

Parks, Joshua W.

Optofluidics, born of the desire to create a system containing microfluidic environments with integrated optical elements, has seen dramatic increases in popularity over the last 10 years. In particular, the application of this technology towards chip based molecular sensors has undergone significant development. The most sensitive of these biosensors interface liquid- and solid-core antiresonant reflecting optical waveguides (ARROWs). These sensor chips are created using conventional silicon microfabrication. As such, ARROW technology has previously been unable to utilize state-of-the-art microfluidic developments because the technology used--soft polydimethyl siloxane (PDMS) micromolded chips--is unamenable to the silicon microfabrication workflows implemented in the creation of ARROW detection chips. The original goal of this thesis was to employ hybrid integration, or the connection of independently designed and fabricated optofluidic and microfluidic chips, to create enhanced biosensors with the capability of processing and detecting biological samples on a single hybrid system. After successful demonstration of this paradigm, this work expanded into a new direction--direct integration of sensing and detection technologies on a new platform with dynamic, multi-dimensional photonic re-configurability. This thesis reports a number of firsts, including: • 1,000 fold optical transmission enhancement of ARROW optofluidic detection chips through thermal annealing, • Detection of single nucleic acids on a silicon-based ARROW chip, • Hybrid optofluidic integration of ARROW detection chips and passive PDMS microfluidic chips, • Hybrid optofluidic integration of ARROW detection chips and actively controllable PDMS microfluidic chips with integrated microvalves, • On-chip concentration and detection of clinical Ebola nucleic acids, • Multimode interference (MMI) waveguide based wavelength division multiplexing for detection of single influenza virions, • All PDMS platform created from monolithically integrated solid- and liquid-core waveguides with single particle detection efficiency and directly integrated microvalves, featuring: ∘ Tunable/tailorable PDMS MMI waveguides, ∘ Lightvalves (optical switch/fluidic microvalve) with the ability to dynamically control light and fluid flow simultaneously, ∘ Lightvalve trap architecture with the ability to physically trap, detect, and analyze single biomolecules.

Polydimethylsiloxane SlipChip for mammalian cell culture applications.

PubMed

Chang, Chia-Wen; Peng, Chien-Chung; Liao, Wei-Hao; Tung, Yi-Chung

2015-11-07

This paper reports a polydimethylsiloxane (PDMS) SlipChip for in vitro cell culture applications, multiple-treatment assays, cell co-cultures, and cytokine detection assays. The PDMS SlipChip is composed of two PDMS layers with microfluidic channels on each surface that are separated by a thin silicone fluid (Si-fluid) layer. The integration of Si-fluid enables the two PDMS layers to be slid to different positions; therefore, the channel patterns can be re-arranged for various applications. The SlipChip design significantly reduces the complexity of sample handling, transportation, and treatment processes. To apply the developed SlipChip for cell culture applications, human lung adenocarcinoma epithelial cells (A549) and lung fibroblasts (MRC-5) were cultured to examine the biocompatibility of the developed PDMS SlipChip. Moreover, embryonic pluripotent stem cells (ES-D3) were also cultured in the device to evaluate the retention of their stemness in the device. The experimental results show that cell morphology, viability and proliferation are not affected when the cells are cultured in the SlipChip, indicating that the device is highly compatible with mammalian cell culture. In addition, the stemness of the ES-D3 cells was highly retained after they were cultured in the device, suggesting the feasibility of using the SlipChip for stem cell research. Various cell experiments, such as simultaneous triple staining of cells and co-culture of MRC-5 with A549 cells, were also performed to demonstrate the functionalities of the PDMS SlipChip. Furthermore, we used a cytokine detection assay to evaluate the effect of endotoxin (lipopolysaccharides, LPS) treatment on the cytokine secretion of A549 cells using the SlipChip. The developed PDMS SlipChip provides a straightforward and effective platform for various on-chip in vitro cell cultures and consequent analysis, which is promising for a number of cell biology studies and biomedical applications.

Drivers Motivating Community Health Improvement Plan Completion by Local Public Health Agencies and Community Partners in the Rocky Mountain Region and Western Plains.

PubMed

Hill, Anne; Wolf, Holly J; Scallan, Elaine; Case, Jenny; Kellar-Guenther, Yvonne

There are numerous drivers that motivate completion of community health improvement plans (CHIPs). Some are more obvious and include voluntary public health accreditation, state requirements, federal and state funding, and nonprofit hospital requirements through IRS regulations. Less is known about other drivers, including involvement of diverse partners and belief in best practices, that may motivate CHIP completion. This research investigated the drivers that motivated CHIP completion based on experiences of 51 local public health agencies (LPHAs). An explanatory mixed-methods design, including closed- and open-ended survey questions and key informant interviews, was used to understand the drivers that motivated CHIP completion. Analysis of survey data involved descriptive statistics. Classical content analysis was used for qualitative data to clarify survey findings. The surveys and key informant interviews were conducted in the Rocky Mountain Region and Western Plains among 51 medium and large LPHAs in Colorado, Kansas, Montana, Nebraska, North Dakota, South Dakota, Utah, and Wyoming. More than 50% of respondents were public health directors; the balance of the respondents were division/program directors, accreditation coordinators, and public health planners. CHIP completion. Most LPHAs in the Rocky Mountains and Western Plains have embraced developing and publishing a CHIP, with 80% having completed their plan and another 13% working on it. CHIP completion is motivated by a belief in best practices, with LPHAs and partners seeing the benefit of quality improvement activities linked to the CHIP and the investment of nonprofit hospitals in the process. Completing a CHIP is strengthened through engagement of diverse partners and a well-functioning partnership. The future of CHIP creation depends on LPHAs and partners investing in the CHIP as a best practice, dedicating personnel to CHIP activities, and enhancing leadership skills to contribute to a synergistic partnership by effectively working and communicating with diverse partners and developing and achieving common goals.

The Jade File System. Ph.D. Thesis

NASA Technical Reports Server (NTRS)

Rao, Herman Chung-Hwa

1991-01-01

File systems have long been the most important and most widely used form of shared permanent storage. File systems in traditional time-sharing systems, such as Unix, support a coherent sharing model for multiple users. Distributed file systems implement this sharing model in local area networks. However, most distributed file systems fail to scale from local area networks to an internet. Four characteristics of scalability were recognized: size, wide area, autonomy, and heterogeneity. Owing to size and wide area, techniques such as broadcasting, central control, and central resources, which are widely adopted by local area network file systems, are not adequate for an internet file system. An internet file system must also support the notion of autonomy because an internet is made up by a collection of independent organizations. Finally, heterogeneity is the nature of an internet file system, not only because of its size, but also because of the autonomy of the organizations in an internet. The Jade File System, which provides a uniform way to name and access files in the internet environment, is presented. Jade is a logical system that integrates a heterogeneous collection of existing file systems, where heterogeneous means that the underlying file systems support different file access protocols. Because of autonomy, Jade is designed under the restriction that the underlying file systems may not be modified. In order to avoid the complexity of maintaining an internet-wide, global name space, Jade permits each user to define a private name space. In Jade's design, we pay careful attention to avoiding unnecessary network messages between clients and file servers in order to achieve acceptable performance. Jade's name space supports two novel features: (1) it allows multiple file systems to be mounted under one direction; and (2) it permits one logical name space to mount other logical name spaces. A prototype of Jade was implemented to examine and validate its design. The prototype consists of interfaces to the Unix File System, the Sun Network File System, and the File Transfer Protocol.

Single-Mode Near-Infrared Lasing in a GaAsSb-Based Nanowire Superlattice at Room Temperature

NASA Astrophysics Data System (ADS)

Ren, Dingding; Ahtapodov, Lyubomir; Nilsen, Julie S.; Yang, Jianfeng; Gustafsson, Anders; Huh, Junghwan; Conibeer, Gavin J.; van Helvoort, Antonius T. J.; Fimland, Bjørn-Ove; Weman, Helge

2018-04-01

Semiconductor nanowire lasers can produce guided coherent light emission with miniaturized geometry, bringing about new possibility for a variety of applications including nanophotonic circuits, optical sensing, and on-chip and chip-to-chip optical communications. Here, we report on the realization of single-mode room-temperature lasing from 890 nm to 990 nm utilizing a novel design of single nanowires with GaAsSb-based multiple superlattices as gain medium under optical pumping. The wavelength tunability with comprehensively enhanced lasing performance is shown to result from the unique nanowire structure with efficient gain materials, which delivers a lasing quality factor as high as 1250, a reduced lasing threshold ~ 6 kW cm-2 and a high characteristic temperature ~ 129 K. These results present a major advancement for the design and synthesis of nanowire laser structures, which can pave the way towards future nanoscale integrated optoelectronic systems with stunning performance.

IFSA: a microfluidic chip-platform for frit-based immunoassay protocols

NASA Astrophysics Data System (ADS)

Hlawatsch, Nadine; Bangert, Michael; Miethe, Peter; Becker, Holger; Gärtner, Claudia

2013-03-01

Point-of-care diagnostics (POC) is one of the key application fields for lab-on-a-chip devices. While in recent years much of the work has concentrated on integrating complex molecular diagnostic assays onto a microfluidic device, there is a need to also put comparatively simple immunoassay-type protocols on a microfluidic platform. In this paper, we present the development of a microfluidic cartridge using an immunofiltration approach. In this method, the sandwich immunoassay takes place in a porous frit on which the antibodies have immobilized. The device is designed to be able to handle three samples in parallel and up to four analytical targets per sample. In order to meet the critical cost targets for the diagnostic market, the microfluidic chip has been designed and manufactured using high-volume manufacturing technologies in mind. Validation experiments show comparable sensitivities in comparison with conventional immunofiltration kits.

64 x 64 thresholding photodetector array for optical pattern recognition

NASA Astrophysics Data System (ADS)

Langenbacher, Harry; Chao, Tien-Hsin; Shaw, Timothy; Yu, Jeffrey W.

1993-10-01

A high performance 32 X 32 peak detector array is introduced. This detector consists of a 32 X 32 array of thresholding photo-transistor cells, manufactured with a standard MOSIS digital 2-micron CMOS process. A built-in thresholding function that is able to perform 1024 thresholding operations in parallel strongly distinguishes this chip from available CCD detectors. This high speed detector offers responses from one to 10 milliseconds that is much higher than the commercially available CCD detectors operating at a TV frame rate. The parallel multiple peaks thresholding detection capability makes it particularly suitable for optical correlator and optoelectronically implemented neural networks. The principle of operation, circuit design and the performance characteristics are described. Experimental demonstration of correlation peak detection is also provided. Recently, we have also designed and built an advanced version of a 64 X 64 thresholding photodetector array chip. Experimental investigation of using this chip for pattern recognition is ongoing.

Sparse matrix-vector multiplication on network-on-chip

NASA Astrophysics Data System (ADS)

Sun, C.-C.; Götze, J.; Jheng, H.-Y.; Ruan, S.-J.

2010-12-01

In this paper, we present an idea for performing matrix-vector multiplication by using Network-on-Chip (NoC) architecture. In traditional IC design on-chip communications have been designed with dedicated point-to-point interconnections. Therefore, regular local data transfer is the major concept of many parallel implementations. However, when dealing with the parallel implementation of sparse matrix-vector multiplication (SMVM), which is the main step of all iterative algorithms for solving systems of linear equation, the required data transfers depend on the sparsity structure of the matrix and can be extremely irregular. Using the NoC architecture makes it possible to deal with arbitrary structure of the data transfers; i.e. with the irregular structure of the sparse matrices. So far, we have already implemented the proposed SMVM-NoC architecture with the size 4×4 and 5×5 in IEEE 754 single float point precision using FPGA.

Design and analysis of reflector for uniform light-emitting diode illuminance.

PubMed

Tsai, Chung-Yu

2013-05-01

A light-emitting diode (LED) projection system is proposed, composed of an LED chip and a variable-focus-parabolic (VFP) reflector, in which the focal length varies as a function of the vertical displacement of the incidence point relative to the horizontal centerline of the LED chip. The light-ray paths within the projection system are analyzed using an exact analytical model and a skew-ray tracing approach. The profile of the proposed VFP reflector and the position of the LED chip are then optimized in such a way as to enhance the uniformity of the illuminance distribution on the target region of the image plane. The validity of the optimized design is demonstrated by means of ZEMAX simulations. It is shown that the optimized VFP projector system yields a significant improvement in illuminance uniformity compared to conventional spherical and parabolic projectors and therefore minimizes the glare effect.

MEMS actuators and sensors: observations on their performance and selection for purpose

NASA Astrophysics Data System (ADS)

Bell, D. J.; Lu, T. J.; Fleck, N. A.; Spearing, S. M.

2005-07-01

This paper presents an exercise in comparing the performance of microelectromechanical systems (MEMS) actuators and sensors as a function of operating principle. Data have been obtained from the literature for the mechanical performance characteristics of actuators, force sensors and displacement sensors. On-chip and off-chip actuators and sensors are each sub-grouped into families, classes and members according to their principle of operation. The performance of MEMS sharing common operating principles is compared with each other and with equivalent macroscopic devices. The data are used to construct performance maps showing the capability of existing actuators and sensors in terms of maximum force and displacement capability, resolution and frequency. These can also be used as a preliminary design tool, as shown in a case study on the design of an on-chip tensile test machine for materials in thin-film form.

Shrink-film microfluidic education modules: Complete devices within minutes.

PubMed

Nguyen, Diep; McLane, Jolie; Lew, Valerie; Pegan, Jonathan; Khine, Michelle

2011-06-01

As advances in microfluidics continue to make contributions to diagnostics and life sciences, broader awareness of this expanding field becomes necessary. By leveraging low-cost microfabrication techniques that require no capital equipment or infrastructure, simple, accessible, and effective educational modules can be made available for a broad range of educational needs from middle school demonstrations to college laboratory classes. These modules demonstrate key microfluidic concepts such as diffusion and separation as well as "laboratory on-chip" applications including chemical reactions and biological assays. These modules are intended to provide an interdisciplinary hands-on experience, including chip design, fabrication of functional devices, and experiments at the microscale. Consequently, students will be able to conceptualize physics at small scales, gain experience in computer-aided design and microfabrication, and perform experiments-all in the context of addressing real-world challenges by making their own lab-on-chip devices.

Prototyping the HPDP Chip on STM 65 NM Process

NASA Astrophysics Data System (ADS)

Papadas, C.; Dramitinos, G.; Syed, M.; Helfers, T.; Dedes, G.; Schoellkopf, J.-P.; Dugoujon, L.

2011-08-01

Currently Astrium GmbH is involved in the of the High Performance Data Processor (HPDP) development programme for telecommunication applications under a DLR contract. The HPDP project targets the implementation of the commercially available reconfigurable array processor IP (XPP from the company PACT XPP Technologies) in a radiation hardened technology.In the current complementary development phase funded under the Greek Industry Incentive scheme, it is planned to prototype the HPDP chip in commercial STM 65 nm technology. In addition it is also planned to utilise the preliminary radiation hardened components of this library wherever possible.This abstract gives an overview of the HPDP chip architecture, the basic details of the STM 65 nm process and the design flow foreseen for the prototyping. The paper will discuss the development and integration issues involved in using the STM 65 nm process (also including the available preliminary radiation hardened components) for designs targeted to be used in space applications.

Acceleration of block-matching algorithms using a custom instruction-based paradigm on a Nios II microprocessor

NASA Astrophysics Data System (ADS)

González, Diego; Botella, Guillermo; García, Carlos; Prieto, Manuel; Tirado, Francisco

2013-12-01

This contribution focuses on the optimization of matching-based motion estimation algorithms widely used for video coding standards using an Altera custom instruction-based paradigm and a combination of synchronous dynamic random access memory (SDRAM) with on-chip memory in Nios II processors. A complete profile of the algorithms is achieved before the optimization, which locates code leaks, and afterward, creates a custom instruction set, which is then added to the specific design, enhancing the original system. As well, every possible memory combination between on-chip memory and SDRAM has been tested to achieve the best performance. The final throughput of the complete designs are shown. This manuscript outlines a low-cost system, mapped using very large scale integration technology, which accelerates software algorithms by converting them into custom hardware logic blocks and showing the best combination between on-chip memory and SDRAM for the Nios II processor.

MuTRiG: a mixed signal Silicon Photomultiplier readout ASIC with high timing resolution and gigabit data link

NASA Astrophysics Data System (ADS)

Chen, H.; Briggl, K.; Eckert, P.; Harion, T.; Munwes, Y.; Shen, W.; Stankova, V.; Schultz-Coulon, H. C.

2017-01-01

MuTRiG is a mixed signal Silicon Photomultiplier readout ASIC designed in UMC 180 nm CMOS technology for precise timing and high event rate applications in high energy physics experiments and medical imaging. It is dedicated to the readout of the scintillating fiber detector and the scintillating tile detector of the Mu3e experiment. The MuTRiG chip extends the excellent timing performance of the STiCv3 chip with a fast digital readout for high rate applications. The high timing performance of the fully differential SiPM readout channels and 50 ps time binning TDCs are complemented by an upgraded digital readout logic and a 1.28 Gbps LVDS serial data link. The design of the chip and the characterization results of the analog front-end, TDC and the LVDS data link are presented.

A Streaming Language Implementation of the Discontinuous Galerkin Method

NASA Technical Reports Server (NTRS)

Barth, Timothy; Knight, Timothy

2005-01-01

We present a Brook streaming language implementation of the 3-D discontinuous Galerkin method for compressible fluid flow on tetrahedral meshes. Efficient implementation of the discontinuous Galerkin method using the streaming model of computation introduces several algorithmic design challenges. Using a cycle-accurate simulator, performance characteristics have been obtained for the Stanford Merrimac stream processor. The current Merrimac design achieves 128 Gflops per chip and the desktop board is populated with 16 chips yielding a peak performance of 2 Teraflops. Total parts cost for the desktop board is less than $20K. Current cycle-accurate simulations for discretizations of the 3-D compressible flow equations yield approximately 40-50% of the peak performance of the Merrimac streaming processor chip. Ongoing work includes the assessment of the performance of the same algorithm on the 2 Teraflop desktop board with a target goal of achieving 1 Teraflop performance.

Carbonyl sulfide removal with compost and wood chip biofilters, and in the presence of hydrogen sulfide.

PubMed

Sattler, Melanie L; Garrepalli, Divya R; Nawal, Chandraprakash S

2009-12-01

Carbonyl sulfide (COS) is an odor-causing compound and hazardous air pollutant emitted frequently from wastewater treatment facilities and chemical and primary metals industries. This study examined the effectiveness of biofiltration in removing COS. Specific objectives were to compare COS removal efficiency for various biofilter media; to determine whether hydrogen sulfide (H2S), which is frequently produced along with COS under anaerobic conditions, adversely impacts COS removal; and to determine the maximum elimination capacity of COS for use in biofilter design. Three laboratory-scale polyvinyl chloride biofilter columns were filled with up to 28 in. of biofilter media (aged compost, fresh compost, wood chips, or a compost/wood chip mixture). Inlet COS ranged from 5 to 46 parts per million (ppm) (0.10-9.0 g/m3 hr). Compost and the compost/wood chip mixture produced higher COS removal efficiencies than wood chips alone. The compost and compost/wood chip mixture had a shorter stabilization times compared with wood chips alone. Fresh versus aged compost did not impact COS removal efficiency. The presence of H2S did not adversely impact COS removal for the concentration ratios tested. The maximum elimination capacity is at least 9 g/m3 hr for COS with compost media.

A multichip aVLSI system emulating orientation selectivity of primary visual cortical cells.

PubMed

Shimonomura, Kazuhiro; Yagi, Tetsuya

2005-07-01

In this paper, we designed and fabricated a multichip neuromorphic analog very large scale integrated (aVLSI) system, which emulates the orientation selective response of the simple cell in the primary visual cortex. The system consists of a silicon retina and an orientation chip. An image, which is filtered by a concentric center-surround (CS) antagonistic receptive field of the silicon retina, is transferred to the orientation chip. The image transfer from the silicon retina to the orientation chip is carried out with analog signals. The orientation chip selectively aggregates multiple pixels of the silicon retina, mimicking the feedforward model proposed by Hubel and Wiesel. The chip provides the orientation-selective (OS) outputs which are tuned to 0 degrees, 60 degrees, and 120 degrees. The feed-forward aggregation reduces the fixed pattern noise that is due to the mismatch of the transistors in the orientation chip. The spatial properties of the orientation selective response were examined in terms of the adjustable parameters of the chip, i.e., the number of aggregated pixels and size of the receptive field of the silicon retina. The multichip aVLSI architecture used in the present study can be applied to implement higher order cells such as the complex cell of the primary visual cortex.

Experiences in flip chip production of radiation detectors

NASA Astrophysics Data System (ADS)

Savolainen-Pulli, Satu; Salonen, Jaakko; Salmi, Jorma; Vähänen, Sami

2006-09-01

Modern imaging devices often require heterogeneous integration of different materials and technologies. Because of yield considerations, material availability, and various technological limitations, an extremely fine pitch is necessary to realize high-resolution images. Thus, there is a need for a hybridization technology that is able to join together readout amplifiers and pixel detectors at a very fine pitch. This paper describes radiation detector flip chip production at VTT. Our flip chip technology utilizes 25-μm diameter tin-lead solder bumps at a 50-μm pitch and is based on flux-free bonding. When preprocessed wafers are used, as is the case here, the total yield is defined only partly by the flip chip process. Wafer preprocessing done by a third-party silicon foundry and the flip chip process create different process defects. Wafer-level yield maps (based on probing) provided by the customer are used to select good readout chips for assembly. Wafer probing is often done outside of a real clean room environment, resulting in particle contamination and/or scratches on the wafers. Factors affecting the total yield of flip chip bonded detectors are discussed, and some yield numbers of the process are given. Ways to improve yield are considered, and finally guidelines for process planning and device design with respect to yield optimization are given.

A novel readout integrated circuit for ferroelectric FPA detector

NASA Astrophysics Data System (ADS)

Bai, Piji; Li, Lihua; Ji, Yulong; Zhang, Jia; Li, Min; Liang, Yan; Hu, Yanbo; Li, Songying

2017-11-01

Uncooled infrared detectors haves some advantages such as low cost light weight low power consumption, and superior reliability, compared with cryogenically cooled ones Ferroelectric uncooled focal plane array(FPA) are being developed for its AC response and its high reliability As a key part of the ferroelectric assembly the ROIC determines the performance of the assembly. A top-down design model for uncooled ferroelectric readout integrated circuit(ROIC) has been developed. Based on the optical thermal and electrical properties of the ferroelectric detector the RTIA readout integrated circuit is designed. The noise bandwidth of RTIA readout circuit has been developed and analyzed. A novel high gain amplifier, a high pass filter and a low pass filter circuits are designed on the ROIC. In order to improve the ferroelectric FPA package performance and decrease of package cost a temperature sensor is designed on the ROIC chip At last the novel RTIA ROIC is implemented on 0.6μm 2P3M CMOS silicon techniques. According to the experimental chip test results the temporal root mean square(RMS)noise voltage is about 1.4mV the sensitivity of the on chip temperature sensor is 0.6 mV/K from -40°C to 60°C the linearity performance of the ROIC chip is better than 99% Based on the 320×240 RTIA ROIC, a 320×240 infrared ferroelectric FPA is fabricated and tested. Test results shows that the 320×240 RTIA ROIC meets the demand of infrared ferroelectric FPA.

Biodegradable scaffold with built-in vasculature for organ-on-a-chip engineering and direct surgical anastomosis.

PubMed

Zhang, Boyang; Montgomery, Miles; Chamberlain, M Dean; Ogawa, Shinichiro; Korolj, Anastasia; Pahnke, Aric; Wells, Laura A; Massé, Stéphane; Kim, Jihye; Reis, Lewis; Momen, Abdul; Nunes, Sara S; Wheeler, Aaron R; Nanthakumar, Kumaraswamy; Keller, Gordon; Sefton, Michael V; Radisic, Milica

2016-06-01

We report the fabrication of a scaffold (hereafter referred to as AngioChip) that supports the assembly of parenchymal cells on a mechanically tunable matrix surrounding a perfusable, branched, three-dimensional microchannel network coated with endothelial cells. The design of AngioChip decouples the material choices for the engineered vessel network and for cell seeding in the parenchyma, enabling extensive remodelling while maintaining an open-vessel lumen. The incorporation of nanopores and micro-holes in the vessel walls enhances permeability, and permits intercellular crosstalk and extravasation of monocytes and endothelial cells on biomolecular stimulation. We also show that vascularized hepatic tissues and cardiac tissues engineered by using AngioChips process clinically relevant drugs delivered through the vasculature, and that millimetre-thick cardiac tissues can be engineered in a scalable manner. Moreover, we demonstrate that AngioChip cardiac tissues implanted with direct surgical anastomosis to the femoral vessels of rat hindlimbs establish immediate blood perfusion.

Space Science

NASA Image and Video Library

2004-02-01

Labs on chips are manufactured in many shapes and sizes and can be used for numerous applications, from medical tests to water quality monitoring to detecting the signatures of life on other planets. The eight holes on this chip are actually ports that can be filled with fluids or chemicals. Tiny valves control the chemical processes by mixing fluids that move in the tiny channels that look like lines, connecting the ports. Scientists at NASA's Marshall Space Flight Center (MSFC) in Huntsville, Alabama designed this chip to grow biological crystals on the International Space Station. Through this research, they discovered that this technology is ideally suited for solving the challenges of the Vision for Space Exploration. For example, thousands of chips the size of dimes could be loaded on a Martian rover looking for biosignatures of past or present life. Other types of chips could be placed in handheld devices used to monitor microbes in water or to quickly conduct medical tests on astronauts. (NASA/MSFC/D.Stoffer)

Improving the -3 dB bandwidth of medium power GaN-based LEDs through periodic micro via-holes for visible light communications

NASA Astrophysics Data System (ADS)

Zhou, Zheng; Yan, Bing; Teng, Dongdong; Liu, Lilin; Wang, Gang

2017-06-01

Medium power GaN-based light emitting diode (LED) chips with periodic micro via-holes are designed and fabricated. The active area of each chip is 200 μm×800 μm and the diameter of each micro via-hole is 50 μm. For comparison, an LED chip with only one big via-hole (Diameter=86.6 μm) is also fabricated under the same conditions as the control partner. Both kinds of LED chips have an equal effective PN junction area. Experimentally, the LED with periodic via-holes exhibits higher output optical power and the -3 dB modulation bandwidth by about 33% and 48%, respectively, than the LED with only one bigger via-hole. The method of concurrently improving modulation and optical performances of power-type LED chips through periodic micro via-holes take the advantages of easy fabrication, suitable for mass-production.

Biodegradable scaffold with built-in vasculature for organ-on-a-chip engineering and direct surgical anastomosis

NASA Astrophysics Data System (ADS)

Zhang, Boyang; Montgomery, Miles; Chamberlain, M. Dean; Ogawa, Shinichiro; Korolj, Anastasia; Pahnke, Aric; Wells, Laura A.; Massé, Stéphane; Kim, Jihye; Reis, Lewis; Momen, Abdul; Nunes, Sara S.; Wheeler, Aaron R.; Nanthakumar, Kumaraswamy; Keller, Gordon; Sefton, Michael V.; Radisic, Milica

2016-06-01

We report the fabrication of a scaffold (hereafter referred to as AngioChip) that supports the assembly of parenchymal cells on a mechanically tunable matrix surrounding a perfusable, branched, three-dimensional microchannel network coated with endothelial cells. The design of AngioChip decouples the material choices for the engineered vessel network and for cell seeding in the parenchyma, enabling extensive remodelling while maintaining an open-vessel lumen. The incorporation of nanopores and micro-holes in the vessel walls enhances permeability, and permits intercellular crosstalk and extravasation of monocytes and endothelial cells on biomolecular stimulation. We also show that vascularized hepatic tissues and cardiac tissues engineered by using AngioChips process clinically relevant drugs delivered through the vasculature, and that millimetre-thick cardiac tissues can be engineered in a scalable manner. Moreover, we demonstrate that AngioChip cardiac tissues implanted with direct surgical anastomosis to the femoral vessels of rat hindlimbs establish immediate blood perfusion.

Technology for On-Chip Qubit Control with Microfabricated Surface Ion Traps

DOE Office of Scientific and Technical Information (OSTI.GOV)

Highstrete, Clark; Scott, Sean Michael; Nordquist, Christopher D.

2013-11-01

Trapped atomic ions are a leading physical system for quantum information processing. However, scalability and operational fidelity remain limiting technical issues often associated with optical qubit control. One promising approach is to develop on-chip microwave electronic control of ion qubits based on the atomic hyperfine interaction. This project developed expertise and capabilities at Sandia toward on-chip electronic qubit control in a scalable architecture. The project developed a foundation of laboratory capabilities, including trapping the 171Yb + hyperfine ion qubit and developing an experimental microwave coherent control capability. Additionally, the project investigated the integration of microwave device elements with surface ionmore » traps utilizing Sandia’s state-of-the-art MEMS microfabrication processing. This effort culminated in a device design for a multi-purpose ion trap experimental platform for investigating on-chip microwave qubit control, laying the groundwork for further funded R&D to develop on-chip microwave qubit control in an architecture that is suitable to engineering development.« less

Chip level modeling of LSI devices

NASA Technical Reports Server (NTRS)

Armstrong, J. R.

1984-01-01

The advent of Very Large Scale Integration (VLSI) technology has rendered the gate level model impractical for many simulation activities critical to the design automation process. As an alternative, an approach to the modeling of VLSI devices at the chip level is described, including the specification of modeling language constructs important to the modeling process. A model structure is presented in which models of the LSI devices are constructed as single entities. The modeling structure is two layered. The functional layer in this structure is used to model the input/output response of the LSI chip. A second layer, the fault mapping layer, is added, if fault simulations are required, in order to map the effects of hardware faults onto the functional layer. Modeling examples for each layer are presented. Fault modeling at the chip level is described. Approaches to realistic functional fault selection and defining fault coverage for functional faults are given. Application of the modeling techniques to single chip and bit slice microprocessors is discussed.

A CMOS One-chip Wireless Camera with Digital Image Transmission Function for Capsule Endoscopes

NASA Astrophysics Data System (ADS)

Itoh, Shinya; Kawahito, Shoji; Terakawa, Susumu

This paper presents the design and implementation of a one-chip camera device for capsule endoscopes. This experimental chip integrates functional circuits required for capsule endoscopes and digital image transmission function. The integrated functional blocks include an image array, a timing generator, a clock generator, a voltage regulator, a 10b cyclic A/D converter, and a BPSK modulator. It can be operated autonomously with 3 pins (VDD, GND, and DATAOUT). A prototype image sensor chip which has 320x240 effective pixels was fabricated using 0.25μm CMOS image sensor process and the autonomous imaging was demonstrated. The chip size is 4.84mmx4.34mm. With a 2.0 V power supply, the analog part consumes 950μW and the total power consumption at 2 frames per second (fps) is 2.6mW. Error-free image transmission over a distance of 48cm at 2.5Mbps corresponding to 2fps has been succeeded with inductive coupling.

The Association between Family Meals, TV Viewing during Meals, and Fruit, Vegetables, Soda, and Chips Intake among Latino Children

ERIC Educational Resources Information Center

Andaya, Abegail A.; Arredondo, Elva M.; Alcaraz, John E.; Lindsay, Suzanne P.; Elder, John P.

2011-01-01

Objective: Examine the relationship of family meals to children's consumption of fruit and vegetables as well as soda and chips. Additionally, to assess the relationship between viewing TV during family meals and children's diet. Design: Cross-sectional study that used a questionnaire completed by parents. Setting: Thirteen schools in San Diego,…

Development of the output monitor with single-chip microcomputer in a time-keeping system.

NASA Astrophysics Data System (ADS)

Zhou, Jiguang; Gong, Yuanfang

An output monitor has been designed with Intel 8031 single-chip microcomputer for a time working station. The functions of the instrument include the comparable measurement of the clocks, the buffer output of time and frequency signals, the monitoring and alarming of working state etc. The principle and application of the instrument are described.

Effects of three mulch treatments on initial postfire erosion in north-central Arizona

Treesearch

George H. Riechers; Jan L. Beyers; Peter R. Robichaud; Karen Jennings; Erin Kreutz; Jeff Moll

2008-01-01

Mulching after wildfires is a common treatment designed to protect bare ground from raindrop impact and reduce subsequent erosion. We tested the effectiveness of three mulching methods on the Indian Fire near Prescott, Arizona, USA. The first method felled all fire-killed trees, chipped the logs and limbs, and spread the chips across the hillslope with a mobile...

A Low-Power High-Dynamic-Range Receiver System for In-Probe 3-D Ultrasonic Imaging.

PubMed

Attarzadeh, Hourieh; Xu, Ye; Ytterdal, Trond

2017-10-01

In this paper, a dual-mode low-power, high dynamic-range receiver circuit is designed for the interface with a capacitive micromachined ultrasonic transducer. The proposed ultrasound receiver chip enables the development of an in-probe digital beamforming imaging system. The flexibility of having two operation modes offers a high dynamic range with minimum power sacrifice. A prototype of the chip containing one receive channel, with one variable transimpedance amplifier (TIA) and one analog to digital converter (ADC) circuit is implemented. Combining variable gain TIA functionality with ADC gain settings achieves an enhanced overall high dynamic range, while low power dissipation is maintained. The chip is designed and fabricated in a 65 nm standard CMOS process technology. The test chip occupies an area of 76[Formula: see text] 170 [Formula: see text]. A total average power range of 60-240 [Formula: see text] for a sampling frequency of 30 MHz, and a center frequency of 5 MHz is measured. An instantaneous dynamic range of 50.5 dB with an overall dynamic range of 72 dB is obtained from the receiver circuit.

About Small Streams and Shiny Rocks: Macromolecular Crystal Growth in Microfluidics

NASA Technical Reports Server (NTRS)

vanderWoerd, Mark; Ferree, Darren; Spearing, Scott; Monaco, Lisa; Molho, Josh; Spaid, Michael; Brasseur, Mike; Curreri, Peter A. (Technical Monitor)

2002-01-01

We are developing a novel technique with which we have grown diffraction quality protein crystals in very small volumes, utilizing chip-based, microfluidic ("LabChip") technology. With this technology volumes smaller than achievable with any laboratory pipette can be dispensed with high accuracy. We have performed a feasibility study in which we crystallized several proteins with the aid of a LabChip device. The protein crystals are of excellent quality as shown by X-ray diffraction. The advantages of this new technology include improved accuracy of dispensing for small volumes, complete mixing of solution constituents without bubble formation, highly repeatable recipe and growth condition replication, and easy automation of the method. We have designed a first LabChip device specifically for protein crystallization in batch mode and can reliably dispense and mix from a range of solution constituents. We are currently testing this design. Upon completion additional crystallization techniques, such as vapor diffusion and liquid-liquid diffusion will be accommodated. Macromolecular crystallization using microfluidic technology is envisioned as a fully automated system, which will use the 'tele-science' concept of remote operation and will be developed into a research facility aboard the International Space Station.

SPAD array based TOF SoC design for unmanned vehicle

NASA Astrophysics Data System (ADS)

Pan, An; Xu, Yuan; Xie, Gang; Huang, Zhiyu; Zheng, Yanghao; Shi, Weiwei

2018-03-01

As for the requirement of unmanned-vehicle mobile Lidar system, this paper presents a SoC design based on pulsed TOF depth image sensor. This SoC has a detection range of 300m and detecting resolution of 1.5cm. Pixels are made of SPAD. Meanwhile, SoC adopts a structure of multi-pixel sharing TDC, which significantly reduces chip area and improve the fill factor of light-sensing surface area. SoC integrates a TCSPC module to achieve the functionality of receiving each photon, measuring photon flight time and processing depth information in one chip. The SOC is designed in the SMIC 0.13μm CIS CMOS technology

"Print-n-Shrink" technology for the rapid production of microfluidic chips and protein microarrays.

PubMed

Sollier, Kevin; Mandon, Céline A; Heyries, Kevin A; Blum, Loïc J; Marquette, Christophe A

2009-12-21

An innovative method for the production of microfluidic chips integrating protein spots is described. The technology, called "Print-n-Shrink", is based on the screen-printing of a microfluidic design (using a dielectric ink) onto Polyshrink polystyrene sheets. The initial print which has a minimum size of 15 microm (height) x 230 microm (width) is thermally treated (30 seconds, 163 degrees C) to shrink and generate features of 85 microm (height) x 100 microm (width). Concomitantly, proteins such as monoclonal antibodies or cellular adhesion proteins are spotted onto the Polyshrink sheets and shrunk together with the microfluidic design, creating a complete biochip integrating both complex microfluidic designs and protein spots for bioanalytical applications.

Wireless Interconnects for Intra-chip & Inter-chip Transmission

NASA Astrophysics Data System (ADS)

Narde, Rounak Singh

With the emergence of Internet of Things and information revolution, the demand of high performance computing systems is increasing. The copper interconnects inside the computing chips have evolved into a sophisticated network of interconnects known as Network on Chip (NoC) comprising of routers, switches, repeaters, just like computer networks. When network on chip is implemented on a large scale like in Multicore Multichip (MCMC) systems for High Performance Computing (HPC) systems, length of interconnects increases and so are the problems like power dissipation, interconnect delays, clock synchronization and electrical noise. In this thesis, wireless interconnects are chosen as the substitute for wired copper interconnects. Wireless interconnects offer easy integration with CMOS fabrication and chip packaging. Using wireless interconnects working at unlicensed mm-wave band (57-64GHz), high data rate of Gbps can be achieved. This thesis presents study of transmission between zigzag antennas as wireless interconnects for Multichip multicores (MCMC) systems and 3D IC. For MCMC systems, a four-chips 16-cores model is analyzed with only four wireless interconnects in three configurations with different antenna orientations and locations. Return loss and transmission coefficients are simulated in ANSYS HFSS. Moreover, wireless interconnects are designed, fabricated and tested on a 6'' silicon wafer with resistivity of 55O-cm using a basic standard CMOS process. Wireless interconnect are designed to work at 30GHz using ANSYS HFSS. The fabricated antennas are resonating around 20GHz with a return loss of less than -10dB. The transmission coefficients between antenna pair within a 20mm x 20mm silicon die is found to be varying between -45dB to -55dB. Furthermore, wireless interconnect approach is extended for 3D IC. Wireless interconnects are implemented as zigzag antenna. This thesis extends the work of analyzing the wireless interconnects in 3D IC with different configurations of antenna orientations and coolants. The return loss and transmission coefficients are simulated using ANSYS HFSS.

Highly Efficient Amplifier for Ka-Band Communications

NASA Technical Reports Server (NTRS)

1996-01-01

An amplifier developed under a Small Business Innovation Research (SBIR) contract will have applications for both satellite and terrestrial communications. This power amplifier uses an innovative series bias arrangement of active devices to achieve over 40-percent efficiency at Ka-band frequencies with an output power of 0.66 W. The amplifier is fabricated on a 2.0- by 3.8-square millimeter chip through the use of Monolithic Microwave Integrated Circuit (MMIC) technology, and it uses state-of-the-art, Pseudomorphic High-Electron-Mobility Transistor (PHEMT) devices. Although the performance of the MMIC chip depends on these high-performance devices, the real innovations here are a unique series bias scheme, which results in a high-voltage chip supply, and careful design of the on-chip planar output stage combiner. This design concept has ramifications beyond the chip itself because it opens up the possibility of operation directly from a satellite power bus (usually 28 V) without a dc-dc converter. This will dramatically increase the overall system efficiency. Conventional microwave power amplifier designs utilize many devices all connected in parallel from the bias supply. This results in a low-bias voltage, typically 5 V, and a high bias current. With this configuration, substantial I(sup 2) R losses (current squared times resistance) may arise in the system bias-distribution network. By placing the devices in a series bias configuration, the total current is reduced, leading to reduced distribution losses. Careful design of the on-chip planar output stage power combiner is also important in minimizing losses. Using these concepts, a two-stage amplifier was designed for operation at 33 GHz and fabricated in a standard MMIC foundry process with 0.20-m PHEMT devices. Using a 20-V bias supply, the amplifier achieved efficiencies of over 40 percent with an output power of 0.66 W and a 16-dB gain over a 2-GHz bandwidth centered at 33 GHz. With a 28-V bias, a power level of 1.1 W was achieved with a 12-dB gain and a 36-percent efficiency. This represents the best reported combination of power and efficiency at this frequency. In addition to delivering excellent power and gain, this Ka-band MMIC power amplifier has an efficiency that is 10 percent greater than existing designs. The unique design offers an excellent match for spacecraft applications since the amplifier supply voltage is closely matched to the typical value of spacecraft bus voltage. These amplifiers may be used alone in applications of 1 W or less, or several may be combined or used in an array to produce moderate power, Ka-band transmitters with minimal power combining and less thermal stress owing to the combination of excellent efficiency and power output. The higher voltage operation of this design may also save mass and power because the dc-dc power converter is replaced with a simpler voltage regulator.

A-MADMAN: Annotation-based microarray data meta-analysis tool

PubMed Central

Bisognin, Andrea; Coppe, Alessandro; Ferrari, Francesco; Risso, Davide; Romualdi, Chiara; Bicciato, Silvio; Bortoluzzi, Stefania

2009-01-01

Background Publicly available datasets of microarray gene expression signals represent an unprecedented opportunity for extracting genomic relevant information and validating biological hypotheses. However, the exploitation of this exceptionally rich mine of information is still hampered by the lack of appropriate computational tools, able to overcome the critical issues raised by meta-analysis. Results This work presents A-MADMAN, an open source web application which allows the retrieval, annotation, organization and meta-analysis of gene expression datasets obtained from Gene Expression Omnibus. A-MADMAN addresses and resolves several open issues in the meta-analysis of gene expression data. Conclusion A-MADMAN allows i) the batch retrieval from Gene Expression Omnibus and the local organization of raw data files and of any related meta-information, ii) the re-annotation of samples to fix incomplete, or otherwise inadequate, metadata and to create user-defined batches of data, iii) the integrative analysis of data obtained from different Affymetrix platforms through custom chip definition files and meta-normalization. Software and documentation are available on-line at . PMID:19563634

Sandia Advanced MEMS Design Tools v. 3.0

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yarberry, Victor R.; Allen, James J.; Lantz, Jeffrey W.

This is a major revision to the Sandia Advanced MEMS Design Tools. It replaces all previous versions. New features in this version: Revised to support AutoCAD 2014 and 2015 This CD contains an integrated set of electronic files that: a) Describe the SUMMiT V fabrication process b) Provide enabling educational information (including pictures, videos, technical information) c) Facilitate the process of designing MEMS with the SUMMiT process (prototype file, Design Rule Checker, Standard Parts Library) d) Facilitate the process of having MEMS fabricated at Sandia National Laboratories e) Facilitate the process of having post-fabrication services performed. While there exists somemore » files on the CD that are used in conjunction with software package AutoCAD, these files are not intended for use independent of the CD. Note that the customer must purchase his/her own copy of AutoCAD to use with these files.« less

EROIC: a BiCMOS pseudo-gaussian shaping amplifier for high-resolution X-ray spectroscopy

NASA Astrophysics Data System (ADS)

Buzzetti, Siro; Guazzoni, Chiara; Longoni, Antonio

2003-10-01

We present the design and complete characterization of a fifth-order pseudo-gaussian shaping amplifier with 1 μs shaping time. The circuit is optimized for the read-out of signals coming from Silicon Drift Detectors for high-resolution X-ray spectroscopy. The novelty of the designed chip stands in the use of a current feedback loop to place the poles in the desired position on the s-plane. The amplifier has been designed in 0.8 μm BiCMOS technology and fully tested. The EROIC chip comprises also the peak stretcher, the peak detector, the output buffer to drive the external ADC and the pile-up rejection system. The circuit needs a single +5 V power supply and the dissipated power is 5 mW per channel. The digital outputs can be directly coupled to standard digital CMOS ICs. The measured integral-non-linearity of the whole chip is below 0.05% and the achieved energy resolution at the Mn Kα line detected by a 5 mm 2 Peltier-cooled Silicon Drift Detector is 167 eV FWHM.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nabeel A. Riza

The goals of the first six months of this project were to begin laying the foundations for both the SiC front-end optical chip fabrication techniques for high pressure gas species sensing as well as the design, assembly, and test of a portable high pressure high temperature calibration test cell chamber for introducing gas species. This calibration cell will be used in the remaining months for proposed first stage high pressure high temperature gas species sensor experimentation and data processing. All these goals have been achieved and are described in detail in the report. Both design process and diagrams for themore » mechanical elements as well as the optical systems are provided. Photographs of the fabricated calibration test chamber cell, the optical sensor setup with the calibration cell, the SiC sample chip holder, and relevant signal processing mathematics are provided. Initial experimental data from both the optical sensor and fabricated test gas species SiC chips is provided. The design and experimentation results are summarized to give positive conclusions on the proposed novel high temperature high pressure gas species detection optical sensor technology.« less

Single-chip microprocessor that communicates directly using light

NASA Astrophysics Data System (ADS)

Sun, Chen; Wade, Mark T.; Lee, Yunsup; Orcutt, Jason S.; Alloatti, Luca; Georgas, Michael S.; Waterman, Andrew S.; Shainline, Jeffrey M.; Avizienis, Rimas R.; Lin, Sen; Moss, Benjamin R.; Kumar, Rajesh; Pavanello, Fabio; Atabaki, Amir H.; Cook, Henry M.; Ou, Albert J.; Leu, Jonathan C.; Chen, Yu-Hsin; Asanović, Krste; Ram, Rajeev J.; Popović, Miloš A.; Stojanović, Vladimir M.

2015-12-01

Data transport across short electrical wires is limited by both bandwidth and power density, which creates a performance bottleneck for semiconductor microchips in modern computer systems—from mobile phones to large-scale data centres. These limitations can be overcome by using optical communications based on chip-scale electronic-photonic systems enabled by silicon-based nanophotonic devices8. However, combining electronics and photonics on the same chip has proved challenging, owing to microchip manufacturing conflicts between electronics and photonics. Consequently, current electronic-photonic chips are limited to niche manufacturing processes and include only a few optical devices alongside simple circuits. Here we report an electronic-photonic system on a single chip integrating over 70 million transistors and 850 photonic components that work together to provide logic, memory, and interconnect functions. This system is a realization of a microprocessor that uses on-chip photonic devices to directly communicate with other chips using light. To integrate electronics and photonics at the scale of a microprocessor chip, we adopt a ‘zero-change’ approach to the integration of photonics. Instead of developing a custom process to enable the fabrication of photonics, which would complicate or eliminate the possibility of integration with state-of-the-art transistors at large scale and at high yield, we design optical devices using a standard microelectronics foundry process that is used for modern microprocessors. This demonstration could represent the beginning of an era of chip-scale electronic-photonic systems with the potential to transform computing system architectures, enabling more powerful computers, from network infrastructure to data centres and supercomputers.

Single-chip microprocessor that communicates directly using light.

PubMed

Sun, Chen; Wade, Mark T; Lee, Yunsup; Orcutt, Jason S; Alloatti, Luca; Georgas, Michael S; Waterman, Andrew S; Shainline, Jeffrey M; Avizienis, Rimas R; Lin, Sen; Moss, Benjamin R; Kumar, Rajesh; Pavanello, Fabio; Atabaki, Amir H; Cook, Henry M; Ou, Albert J; Leu, Jonathan C; Chen, Yu-Hsin; Asanović, Krste; Ram, Rajeev J; Popović, Miloš A; Stojanović, Vladimir M

2015-12-24

Data transport across short electrical wires is limited by both bandwidth and power density, which creates a performance bottleneck for semiconductor microchips in modern computer systems--from mobile phones to large-scale data centres. These limitations can be overcome by using optical communications based on chip-scale electronic-photonic systems enabled by silicon-based nanophotonic devices. However, combining electronics and photonics on the same chip has proved challenging, owing to microchip manufacturing conflicts between electronics and photonics. Consequently, current electronic-photonic chips are limited to niche manufacturing processes and include only a few optical devices alongside simple circuits. Here we report an electronic-photonic system on a single chip integrating over 70 million transistors and 850 photonic components that work together to provide logic, memory, and interconnect functions. This system is a realization of a microprocessor that uses on-chip photonic devices to directly communicate with other chips using light. To integrate electronics and photonics at the scale of a microprocessor chip, we adopt a 'zero-change' approach to the integration of photonics. Instead of developing a custom process to enable the fabrication of photonics, which would complicate or eliminate the possibility of integration with state-of-the-art transistors at large scale and at high yield, we design optical devices using a standard microelectronics foundry process that is used for modern microprocessors. This demonstration could represent the beginning of an era of chip-scale electronic-photonic systems with the potential to transform computing system architectures, enabling more powerful computers, from network infrastructure to data centres and supercomputers.

Comparison of Geometric Design of a Brand of Stainless Steel K-Files: An In Vitro Study.

PubMed

Saeedullah, Maryam; Husain, Syed Wilayat

2018-04-01

The purpose of this experimental study was to determine the diametric variations of a brand of handheld stainless-steel K-files, acquired from different countries, in accordance with the available standards. 20 Mani stainless-steel K-files of identical size (ISO#25) were acquired from Pakistan and were designated as Group A while 20 Mani K-files were purchased from London, UK and designated as Group B. Files were assessed using profile projector Nikon B 24V. Data was statistically compared with ISO 3630:1 and ADA 101 by one sample T test. Significant difference was found between Groups A and B. Average discrepancy of Group A fell within the tolerance limit while that of Group B exceeded the limit. Findings in this study call attention towards adherence to the dimensional standards of stainless-steel endodontic files.

Beam test results of a monolithic pixel sensor in the 0.18 μm tower-jazz technology with high resistivity epitaxial layer

NASA Astrophysics Data System (ADS)

Mattiazzo, S.; Aimo, I.; Baudot, J.; Bedda, C.; La Rocca, P.; Perez, A.; Riggi, F.; Spiriti, E.

2015-10-01

The ALICE experiment at CERN will undergo a major upgrade in the second Long LHC Shutdown in the years 2018-2019; this upgrade includes the full replacement of the Inner Tracking System (ITS), deploying seven layers of Monolithic Active Pixel Sensors (MAPS). For the development of the new ALICE ITS, the Tower-Jazz 0.18 μm CMOS imaging sensor process has been chosen as it is possible to use full CMOS in the pixel and different silicon wafers (including high resistivity epitaxial layers). A large test campaign has been carried out on several small prototype chips, designed to optimize the pixel sensor layout and the front-end electronics. Results match the target requirements both in terms of performance and of radiation hardness. Following this development, the first full scale chips have been designed, submitted and are currently under test, with promising results. A telescope composed of 4 planes of Mimosa-28 and 2 planes of Mimosa-18 chips is under development at the DAFNE Beam Test Facility (BTF) at the INFN Laboratori Nazionali di Frascati (LNF) in Italy with the final goal to perform a comparative test of the full scale prototypes. The telescope has been recently used to test a Mimosa-22THRb chip (a monolithic pixel sensor built in the 0.18 μm Tower-Jazz process) and we foresee to perform tests on the full scale chips for the ALICE ITS upgrade at the beginning of 2015. In this contribution we will describe some first measurements of spatial resolution, fake hit rate and detection efficiency of the Mimosa-22THRb chip obtained at the BTF facility in June 2014 with an electron beam of 500 MeV.

The fabrication of a double-layer atom chip with through silicon vias for an ultra-high-vacuum cell

NASA Astrophysics Data System (ADS)

Chuang, Ho-Chiao; Lin, Yun-Siang; Lin, Yu-Hsin; Huang, Chi-Sheng

2014-04-01

This study presents a double-layer atom chip that provides users with increased diversity in the design of the wire patterns and flexibility in the design of the magnetic field. It is more convenient for use in atomic physics experiments. A negative photoresist, SU-8, was used as the insulating layer between the upper and bottom copper wires. The electrical measurement results show that the upper and bottom wires with a width of 100 µm can sustain a 6 A current without burnout. Another focus of this study is the double-layer atom chips integrated with the through silicon via (TSV) technique, and anodically bonded to a Pyrex glass cell, which makes it a desired vacuum chamber for atomic physics experiments. Thus, the bonded glass cell not only significantly reduces the overall size of the ultra-high-vacuum (UHV) chamber but also conducts the high current from the backside to the front side of the atom chip via the TSV under UHV (9.5 × 10-10 Torr). The TSVs with a diameter of 70 µm were etched through by the inductively coupled plasma ion etching and filled by the bottom-up copper electroplating method. During the anodic bonding process, the electroplated copper wires and TSVs on atom chips also need to pass the examination of the required bonding temperature of 250 °C, under an applied voltage of 1000 V. Finally, the UHV test of the double-layer atom chips with TSVs at room temperature can be reached at 9.5 × 10-10 Torr, thus satisfying the requirements of atomic physics experiments under an UHV environment.

A design of LED adaptive dimming lighting system based on incremental PID controller

NASA Astrophysics Data System (ADS)

He, Xiangyan; Xiao, Zexin; He, Shaojia

2010-11-01

As a new generation energy-saving lighting source, LED is applied widely in various technology and industry fields. The requirement of its adaptive lighting technology is more and more rigorous, especially in the automatic on-line detecting system. In this paper, a closed loop feedback LED adaptive dimming lighting system based on incremental PID controller is designed, which consists of MEGA16 chip as a Micro-controller Unit (MCU), the ambient light sensor BH1750 chip with Inter-Integrated Circuit (I2C), and constant-current driving circuit. A given value of light intensity required for the on-line detecting environment need to be saved to the register of MCU. The optical intensity, detected by BH1750 chip in real time, is converted to digital signal by AD converter of the BH1750 chip, and then transmitted to MEGA16 chip through I2C serial bus. Since the variation law of light intensity in the on-line detecting environment is usually not easy to be established, incremental Proportional-Integral-Differential (PID) algorithm is applied in this system. Control variable obtained by the incremental PID determines duty cycle of Pulse-Width Modulation (PWM). Consequently, LED's forward current is adjusted by PWM, and the luminous intensity of the detection environment is stabilized by self-adaptation. The coefficients of incremental PID are obtained respectively after experiments. Compared with the traditional LED dimming system, it has advantages of anti-interference, simple construction, fast response, and high stability by the use of incremental PID algorithm and BH1750 chip with I2C serial bus. Therefore, it is suitable for the adaptive on-line detecting applications.

Optimal Design of Low-Density SNP Arrays for Genomic Prediction: Algorithm and Applications.

PubMed

Wu, Xiao-Lin; Xu, Jiaqi; Feng, Guofei; Wiggans, George R; Taylor, Jeremy F; He, Jun; Qian, Changsong; Qiu, Jiansheng; Simpson, Barry; Walker, Jeremy; Bauck, Stewart

2016-01-01

Low-density (LD) single nucleotide polymorphism (SNP) arrays provide a cost-effective solution for genomic prediction and selection, but algorithms and computational tools are needed for the optimal design of LD SNP chips. A multiple-objective, local optimization (MOLO) algorithm was developed for design of optimal LD SNP chips that can be imputed accurately to medium-density (MD) or high-density (HD) SNP genotypes for genomic prediction. The objective function facilitates maximization of non-gap map length and system information for the SNP chip, and the latter is computed either as locus-averaged (LASE) or haplotype-averaged Shannon entropy (HASE) and adjusted for uniformity of the SNP distribution. HASE performed better than LASE with ≤1,000 SNPs, but required considerably more computing time. Nevertheless, the differences diminished when >5,000 SNPs were selected. Optimization was accomplished conditionally on the presence of SNPs that were obligated to each chromosome. The frame location of SNPs on a chip can be either uniform (evenly spaced) or non-uniform. For the latter design, a tunable empirical Beta distribution was used to guide location distribution of frame SNPs such that both ends of each chromosome were enriched with SNPs. The SNP distribution on each chromosome was finalized through the objective function that was locally and empirically maximized. This MOLO algorithm was capable of selecting a set of approximately evenly-spaced and highly-informative SNPs, which in turn led to increased imputation accuracy compared with selection solely of evenly-spaced SNPs. Imputation accuracy increased with LD chip size, and imputation error rate was extremely low for chips with ≥3,000 SNPs. Assuming that genotyping or imputation error occurs at random, imputation error rate can be viewed as the upper limit for genomic prediction error. Our results show that about 25% of imputation error rate was propagated to genomic prediction in an Angus population. The utility of this MOLO algorithm was also demonstrated in a real application, in which a 6K SNP panel was optimized conditional on 5,260 obligatory SNP selected based on SNP-trait association in U.S. Holstein animals. With this MOLO algorithm, both imputation error rate and genomic prediction error rate were minimal.

Optimal Design of Low-Density SNP Arrays for Genomic Prediction: Algorithm and Applications

PubMed Central

Wu, Xiao-Lin; Xu, Jiaqi; Feng, Guofei; Wiggans, George R.; Taylor, Jeremy F.; He, Jun; Qian, Changsong; Qiu, Jiansheng; Simpson, Barry; Walker, Jeremy; Bauck, Stewart

2016-01-01

Low-density (LD) single nucleotide polymorphism (SNP) arrays provide a cost-effective solution for genomic prediction and selection, but algorithms and computational tools are needed for the optimal design of LD SNP chips. A multiple-objective, local optimization (MOLO) algorithm was developed for design of optimal LD SNP chips that can be imputed accurately to medium-density (MD) or high-density (HD) SNP genotypes for genomic prediction. The objective function facilitates maximization of non-gap map length and system information for the SNP chip, and the latter is computed either as locus-averaged (LASE) or haplotype-averaged Shannon entropy (HASE) and adjusted for uniformity of the SNP distribution. HASE performed better than LASE with ≤1,000 SNPs, but required considerably more computing time. Nevertheless, the differences diminished when >5,000 SNPs were selected. Optimization was accomplished conditionally on the presence of SNPs that were obligated to each chromosome. The frame location of SNPs on a chip can be either uniform (evenly spaced) or non-uniform. For the latter design, a tunable empirical Beta distribution was used to guide location distribution of frame SNPs such that both ends of each chromosome were enriched with SNPs. The SNP distribution on each chromosome was finalized through the objective function that was locally and empirically maximized. This MOLO algorithm was capable of selecting a set of approximately evenly-spaced and highly-informative SNPs, which in turn led to increased imputation accuracy compared with selection solely of evenly-spaced SNPs. Imputation accuracy increased with LD chip size, and imputation error rate was extremely low for chips with ≥3,000 SNPs. Assuming that genotyping or imputation error occurs at random, imputation error rate can be viewed as the upper limit for genomic prediction error. Our results show that about 25% of imputation error rate was propagated to genomic prediction in an Angus population. The utility of this MOLO algorithm was also demonstrated in a real application, in which a 6K SNP panel was optimized conditional on 5,260 obligatory SNP selected based on SNP-trait association in U.S. Holstein animals. With this MOLO algorithm, both imputation error rate and genomic prediction error rate were minimal. PMID:27583971

On-chip enucleation of an oocyte by untethered microrobots

NASA Astrophysics Data System (ADS)

Ichikawa, Akihiko; Sakuma, Shinya; Sugita, Masakuni; Shoda, Tatsuro; Tamakoshi, Takahiro; Akagi, Satoshi; Arai, Fumihito

2014-09-01

We propose a novel on-chip enucleation of an oocyte with zona pellucida by using a combination of untethered microrobots. To achieve enucleation within the closed space of a microfluidic chip, two microrobots, a microknife and a microgripper were integrated into the microfluidic chip. These microrobots were actuated by an external magnetic force produced by permanent magnets placed on the robotic stage. The tip of the microknife was designed by considering the biological geometric feature of an oocyte, i.e. the oocyte has a polar body in maturation stage II. Moreover, the microknife was fabricated by using grayscale lithography, which allows fabrication of three-dimensional microstructures. The microgripper has a gripping function that is independent of the driving mechanism. On-chip enucleation was demonstrated, and the enucleated oocytes are spherical, indicating that the cell membrane of the oocytes remained intact. To confirm successful enucleation using this method, we investigated the viability of oocytes after enucleation. The results show that the production rate, i.e. the ratio between the number of oocytes that reach the blastocyst stage and the number of bovine oocytes after nucleus transfer, is 100%. The technique will contribute to complex cell manipulation such as cell surgery in lab-on-a-chip devices.

Manually Operatable On-Chip Bistable Pneumatic Microstructures for Microfluidic Manipulations

PubMed Central

Chen, A.; Pan, T.

2014-01-01

Bistable microvalves are of particular interest because of their distinct nature requiring energy consumption only during the transition between the open and closed states. This characteristic can be highly advantageous in reducing the number of external inputs and the complexity of control circuitries for microfluidic devices as contemporary lab-on-a-chip platforms are transferring from research settings to low-resource environments with high integratability and small form factor. In this paper, we first present manually operatable, on-chip bistable pneumatic microstructures (BPM) for microfluidic manipulation. The structural design and operation of the BPM devices can be readily integrated into any pneumatically powered microfluidic network consisting of pneumatic and fluidic channels. It is mainly comprised of a vacuum activation chamber (VAC) and a pressure release chamber (PRC), which users have direct control through finger pressing to switch between bistable vacuum state (VS) or atmospheric state (AS). We have integrated multiple BPM devices into a 4-to-1 microfluidic multiplexor to demonstrate on-chip digital flow switching from different sources. Furthermore, we have shown its clinical relevance in a point-of-care diagnostic chip that process blood samples to identify the distinct blood types (A/B/O) on chip. PMID:25007840

Application and Optimization of Stiffness Abruption Structures for Pressure Sensors with High Sensitivity and Anti-Overload Ability

PubMed Central

Xu, Tingzhong; Lu, Dejiang; Zhao, Libo; Jiang, Zhuangde; Wang, Hongyan; Guo, Xin; Li, Zhikang; Zhou, Xiangyang; Zhao, Yulong

2017-01-01

The influence of diaphragm bending stiffness distribution on the stress concentration characteristics of a pressure sensing chip had been analyzed and discussed systematically. According to the analysis, a novel peninsula-island-based diaphragm structure was presented and applied to two differenet diaphragm shapes as sensing chips for pressure sensors. By well-designed bending stiffness distribution of the diaphragm, the elastic potential energy induced by diaphragm deformation was concentrated above the gap position, which remarkably increased the sensitivity of the sensing chip. An optimization method and the distribution pattern of the peninsula-island based diaphragm structure were also discussed. Two kinds of sensing chips combined with the peninsula-island structures distributing along the side edge and diagonal directions of rectangular diaphragm were fabricated and analyzed. By bonding the sensing chips with anti-overload glass bases, these two sensing chips were demonstrated by testing to achieve not only high sensitivity, but also good anti-overload ability. The experimental results showed that the proposed structures had the potential to measure ultra-low absolute pressures with high sensitivity and good anti-overload ability in an atmospheric environment. PMID:28846599

Technologies for autonomous integrated lab-on-chip systems for space missions

NASA Astrophysics Data System (ADS)

Nascetti, A.; Caputo, D.; Scipinotti, R.; de Cesare, G.

2016-11-01

Lab-on-chip devices are ideal candidates for use in space missions where experiment automation, system compactness, limited weight and low sample and reagent consumption are required. Currently, however, most microfluidic systems require external desktop instrumentation to operate and interrogate the chip, thus strongly limiting their use as stand-alone systems. In order to overcome the above-mentioned limitations our research group is currently working on the design and fabrication of "true" lab-on-chip systems that integrate in a single device all the analytical steps from the sample preparation to the detection without the need for bulky external components such as pumps, syringes, radiation sources or optical detection systems. Three critical points can be identified to achieve 'true' lab-on-chip devices: sample handling, analytical detection and signal transduction. For each critical point, feasible solutions are presented and evaluated. Proposed microfluidic actuation and control is based on electrowetting on dielectrics, autonomous capillary networks and active valves. Analytical detection based on highly specific chemiluminescent reactions is used to avoid external radiation sources. Finally, the integration on the same chip of thin film sensors based on hydrogenated amorphous silicon is discussed showing practical results achieved in different sensing tasks.

Manually operatable on-chip bistable pneumatic microstructures for microfluidic manipulations.

PubMed

Chen, Arnold; Pan, Tingrui

2014-09-07

Bistable microvalves are of particular interest because of their distinct nature of requiring energy consumption only during the transition between the open and closed states. This characteristic can be highly advantageous in reducing the number of external inputs and the complexity of control circuitries since microfluidic devices as contemporary lab-on-a-chip platforms are transferring from research settings to low-resource environments with high integrability and a small form factor. In this paper, we first present manually operatable, on-chip bistable pneumatic microstructures (BPMs) for microfluidic manipulation. The structural design and operation of the BPM devices can be readily integrated into any pneumatically powered microfluidic network consisting of pneumatic and fluidic channels. It is mainly composed of a vacuum activation chamber (VAC) and a pressure release chamber (PRC), of which users have direct control through finger pressing to switch either to the bistable vacuum state (VS) or the atmospheric state (AS). We have integrated multiple BPM devices into a 4-to-1 microfluidic multiplexor to demonstrate on-chip digital flow switching from different sources. Furthermore, we have shown its clinical relevance in a point-of-care diagnostic chip that processes blood samples to identify the distinct blood types (A/B/O) on-chip.

Invited Article: Terahertz microfluidic chips sensitivity-enhanced with a few arrays of meta-atoms

NASA Astrophysics Data System (ADS)

Serita, Kazunori; Matsuda, Eiki; Okada, Kosuke; Murakami, Hironaru; Kawayama, Iwao; Tonouchi, Masayoshi

2018-05-01

We present a nonlinear optical crystal (NLOC)-based terahertz (THz) microfluidic chip with a few arrays of split ring resonators (SRRs) for ultra-trace and quantitative measurements of liquid solutions. The proposed chip operates on the basis of near-field coupling between the SRRs and a local emission of point like THz source that is generated in the process of optical rectification in NLOCs on a sub-wavelength scale. The liquid solutions flowing inside the microchannel modify the resonance frequency and peak attenuation in the THz transmission spectra. In contrast to conventional bio-sensing with far/near-field THz waves, our technique can be expected to compactify the chip design as well as realize high sensitive near-field measurement of liquid solutions without any high-power optical/THz source, near-field probes, and prisms. Using this chip, we have succeeded in observing the 31.8 fmol of ion concentration in actual amount of 318 pl water solutions from the shift of the resonance frequency. The technique opens the door to microanalysis of biological samples with THz waves and accelerates development of THz lab-on-chip devices.

A novel bone scraper for intraoral harvesting: a device for filling small bone defects.

PubMed

Zaffe, Davide; D'Avenia, Ferdinando

2007-08-01

To evaluate histologically the morphology and characteristics of bone chips harvested intraorally by Safescraper, a specially designed cortical bone collector. Bone chips harvested near a bone defect or in other intraoral sites were grafted into a post-extractive socket or applied in procedures for maxillary sinus floor augmentation or guided bone regeneration. Core biopsies were performed at implant insertion. Undecalcified specimens embedded in PMMA were studied by histology, histochemistry and SEM. Intraoral harvesting by Safescraper provided a simple, clinically effective regenerative procedure with low morbidity for collecting cortical bone chips (0.9-1.7 mm in length, roughly 100 microm thick). Chips had an oblong or quadrangular shape and contained live osteocytes (mean viability: 45-72%). Bone chip grafting produced newly formed bone tissue suitable for implant insertion. Trabecular bone volume measured on biopsies decreased with time (from 45-55% to 23%). Grafted chips made up 50% or less of the calcified tissue in biopsies. Biopsies presented remodeling activities, new bone formation by apposition and live osteocytes (35% or higher). In conclusion, Safescraper is capable of collecting adequate amounts of cortical bone chips from different intraoral sites. The procedure is effective for treating alveolar defects for endosseous implant insertion and provides good healing of small bone defects after grafting with bone chips. The study indicates that Safescraper is a very useful device for in-office bone harvesting procedures in routine peri-implant bone regeneration.

Study on VCSEL laser heating chip in nuclear magnetic resonance gyroscope

NASA Astrophysics Data System (ADS)

Liang, Xiaoyang; Zhou, Binquan; Wu, Wenfeng; Jia, Yuchen; Wang, Jing

2017-10-01

In recent years, atomic gyroscope has become an important direction of inertial navigation. Nuclear magnetic resonance gyroscope has a stronger advantage in the miniaturization of the size. In atomic gyroscope, the lasers are indispensable devices which has an important effect on the improvement of the gyroscope performance. The frequency stability of the VCSEL lasers requires high precision control of temperature. However, the heating current of the laser will definitely bring in the magnetic field, and the sensitive device, alkali vapor cell, is very sensitive to the magnetic field, so that the metal pattern of the heating chip should be designed ingeniously to eliminate the magnetic field introduced by the heating current. In this paper, a heating chip was fabricated by MEMS process, i.e. depositing platinum on semiconductor substrates. Platinum has long been considered as a good resistance material used for measuring temperature The VCSEL laser chip is fixed in the center of the heating chip. The thermometer resistor measures the temperature of the heating chip, which can be considered as the same temperature of the VCSEL laser chip, by turning the temperature signal into voltage signal. The FPGA chip is used as a micro controller, and combined with PID control algorithm constitute a closed loop control circuit. The voltage applied to the heating resistor wire is modified to achieve the temperature control of the VCSEL laser. In this way, the laser frequency can be controlled stably and easily. Ultimately, the temperature stability can be achieved better than 100mK.

Detection and classification of ebola on microfluidic chips

NASA Astrophysics Data System (ADS)

Lin, Xue; Jin, Xiangyu; Fan, Yunqian; Huang, Qin; Kou, Yue; Zu, Guo; Huang, Shiguang; Liu, Xiaosheng; Huang, Guoliang

2016-10-01

Point-of-care testing (POCT) for an infectious diseases is the prerequisite to control of the disease and limitation of its spread. A microfluidic chip for detection and classification of four strains of Ebola virus was developed and evaluated. This assay was based on reverse transcription loop-mediated isothermal amplification (RT-LAMP) and specific primers for Ebola Zaire virus, Ebola Sudan virus, Ebola Tai Forest virus and Ebola Bundibugyo virus were designed. The sensitivity of the microfluidic chip was under 103 copies per milliliter, as determined by ten repeated tests. This assay is unique in its ability to enable diagnosis of the Ebola infections and simultaneous typing of Ebola virus on a single chip. It offers short reaction time, ease of use and high specificity. These features should enable POCT in remote area during outbreaks of Ebola virus.

Wireless Neural Recording With Single Low-Power Integrated Circuit

PubMed Central

Harrison, Reid R.; Kier, Ryan J.; Chestek, Cynthia A.; Gilja, Vikash; Nuyujukian, Paul; Ryu, Stephen; Greger, Bradley; Solzbacher, Florian; Shenoy, Krishna V.

2010-01-01

We present benchtop and in vivo experimental results from an integrated circuit designed for wireless implantable neural recording applications. The chip, which was fabricated in a commercially available 0.6-μm 2P3M BiCMOS process, contains 100 amplifiers, a 10-bit analog-to-digital converter (ADC), 100 threshold-based spike detectors, and a 902–928 MHz frequency-shift-keying (FSK) transmitter. Neural signals from a selected amplifier are sampled by the ADC at 15.7 kSps and telemetered over the FSK wireless data link. Power, clock, and command signals are sent to the chip wirelessly over a 2.765-MHz inductive (coil-to-coil) link. The chip is capable of operating with only two off-chip components: a power/command receiving coil and a 100-nF capacitor. PMID:19497825

Design of the ANTARES LCM-DAQ board test bench using a FPGA-based system-on-chip approach

NASA Astrophysics Data System (ADS)

Anvar, S.; Kestener, P.; Le Provost, H.

2006-11-01

The System-on-Chip (SoC) approach consists in using state-of-the-art FPGA devices with embedded RISC processor cores, high-speed differential LVDS links and ready-to-use multi-gigabit transceivers allowing development of compact systems with substantial number of IO channels. Required performances are obtained through a subtle separation of tasks between closely cooperating programmable hardware logic and user-friendly software environment. We report about our experience in using the SoC approach for designing the production test bench of the off-shore readout system for the ANTARES neutrino experiment.

The use of hybrid integrated circuit techniques in biotelemetry applications

NASA Technical Reports Server (NTRS)

Fryer, T. B.

1977-01-01

A review is presented of some features of hybrid integrated circuits that make their use advantageous in miniature biotelemetry applications. The various techniques for fabricating resistors, capacitors and interconnections by both thin film and thick film technology are discussed. The use of chip capacitors, resistors, and especially standard IC chips on substrates with fired-on interconnection patterns is emphasized. The review is designed primarily to acquaint biotelemetry users and designers with an overview of this fabrication technique so that they can better communicate their needs with an understanding of its limitations and advantages to facilities specializing in hybrid construction.

Spacecraft computer technology at Southwest Research Institute

NASA Technical Reports Server (NTRS)

Shirley, D. J.

1993-01-01

Southwest Research Institute (SwRI) has developed and delivered spacecraft computers for a number of different near-Earth-orbit spacecraft including shuttle experiments and SDIO free-flyer experiments. We describe the evolution of the basic SwRI spacecraft computer design from those weighing in at 20 to 25 lb and using 20 to 30 W to newer models weighing less than 5 lb and using only about 5 W, yet delivering twice the processing throughput. Because of their reduced size, weight, and power, these newer designs are especially applicable to planetary instrument requirements. The basis of our design evolution has been the availability of more powerful processor chip sets and the development of higher density packaging technology, coupled with more aggressive design strategies in incorporating high-density FPGA technology and use of high-density memory chips. In addition to reductions in size, weight, and power, the newer designs also address the necessity of survival in the harsh radiation environment of space. Spurred by participation in such programs as MSTI, LACE, RME, Delta 181, Delta Star, and RADARSAT, our designs have evolved in response to program demands to be small, low-powered units, radiation tolerant enough to be suitable for both Earth-orbit microsats and for planetary instruments. Present designs already include MIL-STD-1750 and Multi-Chip Module (MCM) technology with near-term plans to include RISC processors and higher-density MCM's. Long term plans include development of whole-core processors on one or two MCM's.

Power-Amplifier Module for 145 to 165 GHz

NASA Technical Reports Server (NTRS)

Samoska, Lorene; Peralta, Alejandro

2007-01-01

A power-amplifier module that operates in the frequency range of 145 to 165 GHz has been designed and constructed as a combination of (1) a previously developed monolithic microwave integrated circuit (MMIC) power amplifier and (2) a waveguide module. The amplifier chip was needed for driving a high-electron-mobility-transistor (HEMT) frequency doubler. While it was feasible to connect the amplifier and frequency-doubler chips by use of wire bonds, it was found to be much more convenient to test the amplifier and doubler chips separately. To facilitate separate testing, it was decided to package the amplifier and doubler chips in separate waveguide modules. Figure 1 shows the resulting amplifier module. The amplifier chip was described in "MMIC HEMT Power Amplifier for 140 to 170 GHz" (NPO-30127), NASA Tech Briefs, Vol. 27, No. 11, (November 2003), page 49. To recapitulate: This is a three-stage MMIC power amplifier that utilizes HEMTs as gain elements. The amplifier was originally designed to operate in the frequency range of 140 to 170 GHz. The waveguide module is based on a previously developed lower frequency module, redesigned to support operation in the frequency range of 140 to 220 GHz. Figure 2 presents results of one of several tests of the amplifier module - measurements of output power and gain as functions of input power at an output frequency of 150 GHz. Such an amplifier module has many applications to test equipment for power sources above 100 GHz.

System-on-Chip Considerations for Heterogeneous Integration of CMOS and Fluidic Bio-Interfaces.

PubMed

Datta-Chaudhuri, Timir; Smela, Elisabeth; Abshire, Pamela A

2016-12-01

CMOS chips are increasingly used for direct sensing and interfacing with fluidic and biological systems. While many biosensing systems have successfully combined CMOS chips for readout and signal processing with passive sensing arrays, systems that co-locate sensing with active circuits on a single chip offer significant advantages in size and performance but increase the complexity of multi-domain design and heterogeneous integration. This emerging class of lab-on-CMOS systems also poses distinct and vexing technical challenges that arise from the disparate requirements of biosensors and integrated circuits (ICs). Modeling these systems must address not only circuit design, but also the behavior of biological components on the surface of the IC and any physical structures. Existing tools do not support the cross-domain simulation of heterogeneous lab-on-CMOS systems, so we recommend a two-step modeling approach: using circuit simulation to inform physics-based simulation, and vice versa. We review the primary lab-on-CMOS implementation challenges and discuss practical approaches to overcome them. Issues include new versions of classical challenges in system-on-chip integration, such as thermal effects, floor-planning, and signal coupling, as well as new challenges that are specifically attributable to biological and fluidic domains, such as electrochemical effects, non-standard packaging, surface treatments, sterilization, microfabrication of surface structures, and microfluidic integration. We describe these concerns as they arise in lab-on-CMOS systems and discuss solutions that have been experimentally demonstrated.

On-chip ultraviolet holography for high-throughput nanoparticle and biomolecule detection

NASA Astrophysics Data System (ADS)

Daloglu, Mustafa Ugur; Ray, Aniruddha; Gorocs, Zoltán.; Xiong, Matthew; Malik, Ravinder; Bitan, Gal; McLeod, Euan; Ozcan, Aydogan

2018-02-01

Nanoparticle and biomolecule imaging has become an important need for various applications. In an effort to find a higher throughput alternative to existing devices, we have designed a lensfree on-chip holographic imaging platform operating at an ultraviolet (UV) wavelength of 266 nm. With a custom-designed free-space light delivery system to illuminate the sample that is placed very close (<0.5 mm) to an opto-electronic image sensor chip, without any imaging lenses in between, the full active area of the imager chip (>16 mm2 ) was utilized as the imaging field-of-view (FOV) capturing holographic signatures of target objects on a chip. These holograms were then digitally back propagated to extract both the amplitude and phase information of the sample. The increased forward scattering from nanoparticles due to this shorter illumination wavelength has enabled us to image individual particles that are smaller than 30 nm over an FOV of >16 mm2 . Our platform was further utilized in high-contrast imaging of nanoscopic biomolecule aggregates since 266 nm illumination light is strongly absorbed by biomolecules including proteins and nucleic acids. Aggregates of Cu/Zn-superoxide dismutase (SOD1), which has been linked to a fatal neurodegenerative disease, ALS (amyotrophic lateral sclerosis), have been imaged with significantly improved contrast compared to imaging at visible wavelengths. This unique UV imaging modality could be valuable for biomedical applications (e.g., viral load measurements) and environmental monitoring including air and water quality monitoring.

A 16X16 Discrete Cosine Transform Chip

NASA Astrophysics Data System (ADS)

Sun, M. T.; Chen, T. C.; Gottlieb, A.; Wu, L.; Liou, M. L.

1987-10-01

Among various transform coding techniques for image compression the Discrete Cosine Transform (DCT) is considered to be the most effective method and has been widely used in the laboratory as well as in the market, place. DCT is computationally intensive. For video application at 14.3 MHz sample rate, a direct implementation of a 16x16 DCT requires a throughput, rate of approximately half a billion multiplications per second. In order to reduce the cost of hardware implementation, a single chip DCT implementation is highly desirable. In this paper, the implementation of a 16x16 DCT chip using a concurrent architecture will be presented. The chip is designed for real-time processing of 14.3 MHz sampled video data. It uses row-column decomposition to implement the two-dimensional transform. Distributed arithmetic combined with hit-serial and hit-parallel structures is used to implement the required vector inner products concurrently. Several schemes are utilized to reduce the size of required memory. The resultant circuit only uses memory, shift registers, and adders. No multipliers are required. It achieves high speed performance with a very regular and efficient integrated circuit realization. The chip accepts 0-bit input and produces 14-bit DCT coefficients. 12 bits are maintained after the first one-dimensional transform. The circuit has been laid out using a 2-μm CMOS technology with a symbolic design tool MULGA. The core contains approximately 73,000 transistors in an area of 7.2 x 7.0

Exploring changes in middle-school student lunch consumption after local school food service policy modifications.

PubMed

Cullen, Karen Weber; Watson, Kathy; Zakeri, Issa; Ralston, Katherine

2006-09-01

This study assessed the impact of changes in school food policy on student lunch consumption in middle schools. Two years of lunch food records were collected from students at three middle schools in the Houston, Texas area. During the first year, no changes occurred in the school food environment. After that school year was completed, chips and dessert foods were removed from the snack bars of all schools by the Food Service Director. Students recorded the amount and source of food and beverage items consumed. Point-of-service purchase machines provided a day-by-day electronic data file with food and beverage purchases from the snack bars during the 2-year period. Independent t-tests and time series analyses were used to document the impact of the policy change on consumption and sales data between the two years. In general, student consumption of sweetened beverages declined and milk, calcium, vitamin A, saturated fat and sodium increased after the policy change. Snack chips consumption from the snack bar declined in year 2; however, consumption of snack chips and candy from vending increased and the number of vending machines in study schools doubled during the study period. Ice cream sales increased significantly in year 2. Policy changes on foods sold in schools can result in changes in student consumption from the targeted environments. However, if all environments do not make similar changes, compensation may occur.

High-power and brightness laser diode modules using new DBR chips

NASA Astrophysics Data System (ADS)

Yu, Hao; Riva, Martina; Rossi, Giammarco; Braglia, Andrea; Perrone, Guido

2018-02-01

The paper reports on the design, manufacturing and preliminary characterization of a new family of compact and high beam quality multi-emitter laser diode modules capable of delivering up to over 400W in a 135/0.15 fiber. The layout exploits a proprietary architecture and is based on innovative narrow linewidth high-power DBR chips, properly combined through spatial, polarization and wavelength multiplexing. The intrinsic wavelength-stabilization of these DBR chips allows the use of the developed modules not only for direct-diode material processing but also in pump sources for ytterbium-doped fiber lasers without the need of external stabilization devices.

Programmable bio-nano-chip system for saliva diagnostics

NASA Astrophysics Data System (ADS)

Christodoulides, Nicolaos; De La Garza, Richard; Simmons, Glennon W.; McRae, Michael P.; Wong, Jorge; Kosten, Thomas R.; Miller, Craig S.; Ebersole, Jeffrey L.; McDevitt, John

2014-06-01

This manuscript describes programmable Bio-Nano-Chip (p-BNC) approach that serves as miniaturized assay platform designed for the rapid detection and quantitation of multiple analytes in biological fluids along with the specific applications in salivary diagnostics intended for the point of need (PON). Included here are oral fluid-based tests for local periodontal disease, systemic cardiac disease and multiplexed tests for drugs of abuse.

Design of digital voice storage and playback system

NASA Astrophysics Data System (ADS)

Tang, Chao

2018-03-01

Based on STC89C52 chip, this paper presents a single chip microcomputer minimum system, which is used to realize the logic control of digital speech storage and playback system. Compared with the traditional tape voice recording system, the system has advantages of small size, low power consumption, The effective solution of traditional voice recording system is limited in the use of electronic and information processing.

Improvement of Michigan climatic files in pavement ME design.

DOT National Transportation Integrated Search

2015-10-01

Climatic inputs have a great influence on Mechanistic-Empirical design results of flexible : and rigid pavements. Currently the state of Michigan has 24 climatic files embedded in Pavement ME : Design (PMED), but several limitations have been identif...

1-Million droplet array with wide-field fluorescence imaging for digital PCR.

PubMed

Hatch, Andrew C; Fisher, Jeffrey S; Tovar, Armando R; Hsieh, Albert T; Lin, Robert; Pentoney, Stephen L; Yang, David L; Lee, Abraham P

2011-11-21

Digital droplet reactors are useful as chemical and biological containers to discretize reagents into picolitre or nanolitre volumes for analysis of single cells, organisms, or molecules. However, most DNA based assays require processing of samples on the order of tens of microlitres and contain as few as one to as many as millions of fragments to be detected. Presented in this work is a droplet microfluidic platform and fluorescence imaging setup designed to better meet the needs of the high-throughput and high-dynamic-range by integrating multiple high-throughput droplet processing schemes on the chip. The design is capable of generating over 1-million, monodisperse, 50 picolitre droplets in 2-7 minutes that then self-assemble into high density 3-dimensional sphere packing configurations in a large viewing chamber for visualization and analysis. This device then undergoes on-chip polymerase chain reaction (PCR) amplification and fluorescence detection to digitally quantify the sample's nucleic acid contents. Wide-field fluorescence images are captured using a low cost 21-megapixel digital camera and macro-lens with an 8-12 cm(2) field-of-view at 1× to 0.85× magnification, respectively. We demonstrate both end-point and real-time imaging ability to perform on-chip quantitative digital PCR analysis of the entire droplet array. Compared to previous work, this highly integrated design yields a 100-fold increase in the number of on-chip digitized reactors with simultaneous fluorescence imaging for digital PCR based assays.

A design of a valid signal selecting and position decoding ASIC for PET using silicon photomultipliers

NASA Astrophysics Data System (ADS)

Cho, M.; Lim, K.-t.; Kim, H.; Yeom, J.-y.; Kim, J.; Lee, C.; Choi, H.; Cho, G.

2017-01-01

In most cases, a PET system has numerous electrical components and channel circuits and thus it would rather be a bulky product. Also, most existing systems receive analog signals from detectors which make them vulnerable to signal distortions. For these reasons, channel reduction techniques are important. In this work, an ASIC for PET module is being proposed. An ASIC chip for 16 PET detector channels, VSSPDC, has been designed and simulated. The main function of the chip is 16-to-1 channel reduction, i.e., finding the position of only the valid signals, signal timing, and magnitudes in all 16 channels at every recorded event. The ASIC comprises four of 4-channel modules and a 2nd 4-to-1 router. A single channel module comprises a transimpedance amplifier for the silicon photomultipliers, dual comparators with high and low level references, and a logic circuitry. While the high level reference was used to test the validity of the signal, the low level reference was used for the timing. The 1-channel module of the ASIC produced an energy pulse by time-over-threshold method and it also produced a time pulse with a fixed delayed time. Since the ASIC chip outputs only a few digital pulses and does not require an external clock, it has an advantage over noise properties. The cadence simulation showed the good performance of the chip as designed.

DFM flow by using combination between design based metrology system and model based verification at sub-50nm memory device

NASA Astrophysics Data System (ADS)

Kim, Cheol-kyun; Kim, Jungchan; Choi, Jaeseung; Yang, Hyunjo; Yim, Donggyu; Kim, Jinwoong

2007-03-01

As the minimum transistor length is getting smaller, the variation and uniformity of transistor length seriously effect device performance. So, the importance of optical proximity effects correction (OPC) and resolution enhancement technology (RET) cannot be overemphasized. However, OPC process is regarded by some as a necessary evil in device performance. In fact, every group which includes process and design, are interested in whole chip CD variation trend and CD uniformity, which represent real wafer. Recently, design based metrology systems are capable of detecting difference between data base to wafer SEM image. Design based metrology systems are able to extract information of whole chip CD variation. According to the results, OPC abnormality was identified and design feedback items are also disclosed. The other approaches are accomplished on EDA companies, like model based OPC verifications. Model based verification will be done for full chip area by using well-calibrated model. The object of model based verification is the prediction of potential weak point on wafer and fast feed back to OPC and design before reticle fabrication. In order to achieve robust design and sufficient device margin, appropriate combination between design based metrology system and model based verification tools is very important. Therefore, we evaluated design based metrology system and matched model based verification system for optimum combination between two systems. In our study, huge amount of data from wafer results are classified and analyzed by statistical method and classified by OPC feedback and design feedback items. Additionally, novel DFM flow would be proposed by using combination of design based metrology and model based verification tools.

IAA RAS Radio Telescope Monitoring System

NASA Astrophysics Data System (ADS)

Mikhailov, A.; Lavrov, A.

2007-07-01

Institute of Applied Astronomy of the Russian Academy of Sciences (IAA RAS) has three identical radio telescopes, the receiving complex of which consists of five two-channel receivers of different bands, six cryogen systems, and additional devices: four local oscillators, phase calibration generators and IF commutator. The design, hardware and data communication protocol are described. The most convenient way to join the devices of the receiving complex into the common monitoring system is to use the interface which allows to connect numerous devices to the data bus. For the purpose of data communication regulation and to exclude conflicts, a data communication protocol has been designed, which operates with complex formatted data sequences. Formation of such sequences requires considerable data processing capability. That is provided by a microcontroller chip in each slave device. The test version of the software for the central computer has been developed in IAA RAS. We are developing the Mark IV FS software extension modules, which will allow us to control the receiving complex of the radio telescope by special SNAP commands from both operator input and schedule files. We are also developing procedures of automatic measurements of SEFD, system noise temperature and other parameters, available both in VLBI and single-dish modes of operation. The system described has been installed on all IAA RAS radio telescopes at "Svetloe", "Zelenchukskaya" and "Badary" observatories. It has proved to be working quite reliably and to show the perfonmance expected.