Single level microelectronic device package with an integral window

DOEpatents

Peterson, Kenneth A.; Watson, Robert D.

2003-12-09

A package with an integral window for housing a microelectronic device. The integral window is bonded directly to the package without having a separate layer of adhesive material disposed in-between the window and the package. The device can be a semiconductor chip, CCD chip, CMOS chip, VCSEL chip, laser diode, MEMS device, or IMEMS device. The package can be formed of a multilayered LTCC or HTCC cofired ceramic material, with the integral window being simultaneously joined to the package during cofiring. The microelectronic device can be flip-chip interconnected so that the light-sensitive side is optically accessible through the window. A glob-top encapsulant or protective cover can be used to protect the microelectronic device and electrical interconnections. The result is a compact, low profile package having an integral window that is hermetically sealed to the package prior to mounting and interconnecting the microelectronic device.

Hybridization of active and passive elements for planar photonic components and interconnects

NASA Astrophysics Data System (ADS)

Pearson, M.; Bidnyk, S.; Balakrishnan, A.

2007-02-01

The deployment of Passive Optical Networks (PON) for Fiber-to-the-Home (FTTH) applications currently represents the fastest growing sector of the telecommunication industry. Traditionally, FTTH transceivers have been manufactured using commodity bulk optics subcomponents, such as thin film filters (TFFs), micro-optic collimating lenses, TO-packaged lasers, and photodetectors. Assembling these subcomponents into a single housing requires active alignment and labor-intensive techniques. Today, the majority of cost reducing strategies using bulk subcomponents has been implemented making future reductions in the price of manufacturing FTTH transceivers unlikely. Future success of large scale deployments of FTTH depends on further cost reductions of transceivers. Realizing the necessity of a radically new packaging approach for assembly of photonic components and interconnects, we designed a novel way of hybridizing active and passive elements into a planar lightwave circuit (PLC) platform. In our approach, all the filtering components were monolithically integrated into the chip using advancements in planar reflective gratings. Subsequently, active components were passively hybridized with the chip using fully-automated high-capacity flip-chip bonders. In this approach, the assembly of the transceiver package required no active alignment and was readily suitable for large-scale production. This paper describes the monolithic integration of filters and hybridization of active components in both silica-on-silicon and silicon-on-insulator PLCs.

Chip Scale Atomic Resonator Frequency Stabilization System With Ultra-Low Power Consumption for Optoelectronic Oscillators.

PubMed

Zhao, Jianye; Zhang, Yaolin; Lu, Haoyuan; Hou, Dong; Zhang, Shuangyou; Wang, Zhong

2016-07-01

We present a long-term chip scale stabilization scheme for optoelectronic oscillators (OEOs) based on a rubidium coherent population trapping (CPT) atomic resonator. By locking a single mode of an OEO to the (85)Rb 3.035-GHz CPT resonance utilizing an improved phase-locked loop (PLL) with a PID regulator, we achieved a chip scale frequency stabilization system for the OEO. The fractional frequency stability of the stabilized OEO by overlapping Allan deviation reaches 6.2 ×10(-11) (1 s) and  ∼ 1.45 ×10 (-11) (1000 s). This scheme avoids a decrease in the extra phase noise performance induced by the electronic connection between the OEO and the microwave reference in common injection locking schemes. The total physical package of the stabilization system is [Formula: see text] and the total power consumption is 400 mW, which provides a chip scale and portable frequency stabilization approach with ultra-low power consumption for OEOs.

Identifying Professional Competencies of the Flip-Chip Packaging Engineer in Taiwan

ERIC Educational Resources Information Center

Guu, Y. H.; Lin, Kuen-Yi; Lee, Lung-Sheng

2014-01-01

This study employed a literature review, expert interviews, and a questionnaire survey to construct a set of two-tier competencies for a flip-chip packaging engineer. The fuzzy Delphi questionnaire was sent to 12 flip-chip engineering experts to identify professional competencies that a flip-chip packaging engineer must have. Four competencies,…

Accelerated thermal and mechanical testing of CSP assemblies

NASA Technical Reports Server (NTRS)

Ghaffarian, R.

2000-01-01

Chip Scale Packages (CSP) are now widely used for many electronic applications including portable and telecommunication products. A test vehicle (TV-1) with eleven package types and pitches was built and tested by the JPL MicrotypeBGA Consortium during 1997 to 1999. Lessons learned by the team were published as a guidelines document for industry use. The finer pitch CSP packages which recently became available were indluded in the next test vehicle of the JPL CSP Consortium.

Microelectronic device package with an integral window

DOEpatents

Peterson, Kenneth A.; Watson, Robert D.

2002-01-01

An apparatus for packaging of microelectronic devices, including an integral window. The microelectronic device can be a semiconductor chip, a CCD chip, a CMOS chip, a VCSEL chip, a laser diode, a MEMS device, or a IMEMS device. The package can include a cofired ceramic frame or body. The package can have an internal stepped structure made of one or more plates, with apertures, which are patterned with metallized conductive circuit traces. The microelectronic device can be flip-chip bonded on the plate to these traces, and oriented so that the light-sensitive side is optically accessible through the window. A cover lid can be attached to the opposite side of the package. The result is a compact, low-profile package, having an integral window that can be hermetically-sealed. The package body can be formed by low-temperature cofired ceramic (LTCC) or high-temperature cofired ceramic (HTCC) multilayer processes with the window being simultaneously joined (e.g. cofired) to the package body during LTCC or HTCC processing. Multiple chips can be located within a single package. The cover lid can include a window. The apparatus is particularly suited for packaging of MEMS devices, since the number of handling steps is greatly reduced, thereby reducing the potential for contamination.

System on a Chip (SoC) Overview

NASA Technical Reports Server (NTRS)

LaBel, Kenneth A.

2010-01-01

System-on-a-chip or system on chip (SoC or SOC) refers to integrating all components of a computer or other electronic system into a single integrated circuit (chip). It may contain digital, analog, mixed-signal, and often radio-frequency functions all on a single chip substrate. Complexity drives it all: Radiation tolerance and testability are challenges for fault isolation, propagation, and validation. Bigger single silicon die than flown before and technology is scaling below 90nm (new qual methods). Packages have changed and are bigger and more difficult to inspect, test, and understand. Add in embedded passives. Material interfaces are more complex (underfills, processing). New rules for board layouts. Mechanical and thermal designs, etc.

Sealed symmetric multilayered microelectronic device package with integral windows

DOEpatents

Peterson, Kenneth A.; Watson, Robert D.

2002-01-01

A sealed symmetric multilayered package with integral windows for housing one or more microelectronic devices. The devices can be a semiconductor chip, a CCD chip, a CMOS chip, a VCSEL chip, a laser diode, a MEMS device, or a IMEMS device. The multilayered package can be formed of a low-temperature cofired ceramic (LTCC) or high-temperature cofired ceramic (HTCC) multilayer processes with the windows being simultaneously joined (e.g. cofired) to the package body during LTCC or HTCC processing. The microelectronic devices can be flip-chip bonded and oriented so that the light-sensitive sides are optically accessible through the windows. The result is a compact, low-profile, sealed symmetric package, having integral windows that can be hermetically-sealed.

High-performance packaging for monolithic microwave and millimeter-wave integrated circuits

NASA Technical Reports Server (NTRS)

Shalkhauser, K. A.; Li, K.; Shih, Y. C.

1992-01-01

Packaging schemes were developed that provide low-loss, hermetic enclosure for advanced monolithic microwave and millimeter-wave integrated circuits (MMICs). The package designs are based on a fused quartz substrate material that offers improved radio frequency (RF) performance through 44 gigahertz (GHz). The small size and weight of the packages make them appropriate for a variety of applications, including phased array antenna systems. Packages were designed in two forms; one for housing a single MMIC chip, the second in the form of a multi-chip phased array module. The single chip array module was developed in three separate sizes, for chips of different geometry and frequency requirements. The phased array module was developed to address packaging directly for antenna applications, and includes transmission line and interconnect structures to support multi-element operation. All packages are fabricated using fused quartz substrate materials. As part of the packaging effort, a test fixture was developed to interface the single chip packages to conventional laboratory instrumentation for characterization of the packaged devices. The package and test fixture designs were both developed in a generic sense, optimizing performance for a wide range of possible applications and devices.

Accelerated Thermal Cycling and Failure Mechanisms

NASA Technical Reports Server (NTRS)

Ghaffarian, R.

1999-01-01

This paper reviews the accelerated thermal cycling test methods that are currently used by industry to characterize the interconnect reliability of commercial-off-the-shelf (COTS) ball grid array (BGA) and chip scale package (CSP) assemblies.

Merging parallel optics packaging and surface mount technologies

NASA Astrophysics Data System (ADS)

Kopp, Christophe; Volpert, Marion; Routin, Julien; Bernabé, Stéphane; Rossat, Cyrille; Tournaire, Myriam; Hamelin, Régis

2008-02-01

Optical links are well known to present significant advantages over electrical links for very high-speed data rate at 10Gpbs and above per channel. However, the transition towards optical interconnects solutions for short and very short reach applications requires the development of innovative packaging solutions that would deal with very high volume production capability and very low cost per unit. Moreover, the optoelectronic transceiver components must be able to move from the edge to anywhere on the printed circuit board, for instance close to integrated circuits with high speed IO. In this paper, we present an original packaging design to manufacture parallel optic transceivers that are surface mount devices. The package combines highly integrated Multi-Chip-Module on glass and usual IC ceramics packaging. The use of ceramic and the development of sealing technologies achieve hermetic requirements. Moreover, thanks to a chip scale package approach the final device exhibits a much minimized footprint. One of the main advantages of the package is its flexibility to be soldered or plugged anywhere on the printed circuit board as any other electronic device. As a demonstrator we present a 2 by 4 10Gbps transceiver operating at 850nm.

Multilayered Microelectronic Device Package With An Integral Window

DOEpatents

Peterson, Kenneth A.; Watson, Robert D.

2004-10-26

A microelectronic package with an integral window mounted in a recessed lip for housing a microelectronic device. The device can be a semiconductor chip, a CCD chip, a CMOS chip, a VCSEL chip, a laser diode, a MEMS device, or a IMEMS device. The package can be formed of a low temperature co-fired ceramic (LTCC) or high temperature cofired ceramic (HTCC) multilayered material, with the integral window being simultaneously joined (e.g. co-fired) to the package body during LTCC or HTCC processing. The microelectronic device can be flip-chip bonded and oriented so that a light-sensitive side is optically accessible through the window. The result is a compact, low profile package, having an integral window mounted in a recessed lip, that can be hermetically sealed.

3D integrated superconducting qubits

NASA Astrophysics Data System (ADS)

Rosenberg, D.; Kim, D.; Das, R.; Yost, D.; Gustavsson, S.; Hover, D.; Krantz, P.; Melville, A.; Racz, L.; Samach, G. O.; Weber, S. J.; Yan, F.; Yoder, J. L.; Kerman, A. J.; Oliver, W. D.

2017-10-01

As the field of quantum computing advances from the few-qubit stage to larger-scale processors, qubit addressability and extensibility will necessitate the use of 3D integration and packaging. While 3D integration is well-developed for commercial electronics, relatively little work has been performed to determine its compatibility with high-coherence solid-state qubits. Of particular concern, qubit coherence times can be suppressed by the requisite processing steps and close proximity of another chip. In this work, we use a flip-chip process to bond a chip with superconducting flux qubits to another chip containing structures for qubit readout and control. We demonstrate that high qubit coherence (T1, T2,echo > 20 μs) is maintained in a flip-chip geometry in the presence of galvanic, capacitive, and inductive coupling between the chips.

High-power, format-flexible, 885-nm vertical-cavity surface-emitting laser arrays

NASA Astrophysics Data System (ADS)

Wang, Chad; Talantov, Fedor; Garrett, Henry; Berdin, Glen; Cardellino, Terri; Millenheft, David; Geske, Jonathan

2013-03-01

High-power, format flexible, 885 nm vertical-cavity surface-emitting laser (VCSEL) arrays have been developed for solid-state pumping and illumination applications. In this approach, a common VCSEL size format was designed to enable tiling into flexible formats and operating configurations. The fabrication of a common chip size on ceramic submount enables low-cost volume manufacturing of high-power VCSEL arrays. This base VCSEL chip was designed to be 5x3.33 mm2, and produced up to 50 Watts of peak continuous wave (CW) power. To scale to higher powers, multiple chips can be tiled into a combination of series or parallel configurations tailored to the application driver conditions. In actively cooled CW operation, the VCSEL array chips were packaged onto a single water channel cooler, and we have demonstrated 0.5x1, 1x1, and 1x3 cm2 formats, producing 150, 250, and 500 Watts of peak power, respectively, in under 130 A operating current. In QCW operation, the 1x3 cm2 VCSEL module, which contains 18 VCSEL array chips packaged on a single water cooler, produced over 1.3 kW of peak power. In passively cooled packages, multiple chip configurations have been developed for illumination applications, producing over 300 Watts of peak power in QCW operating conditions. These VCSEL chips use a substrate-removed structure to allow for efficient thermal heatsinking to enable high-power operation. This scalable, format flexible VCSEL architecture can be applied to wavelengths ranging from 800 to 1100 nm, and can be used to tailor emission spectral widths and build high-power hyperspectral sources.

Multilayered microelectronic device package with an integral window

DOEpatents

Peterson, Kenneth A.; Watson, Robert D.

2003-01-01

An apparatus for packaging of microelectronic devices is disclosed, wherein the package includes an integral window. The microelectronic device can be a semiconductor chip, a CCD chip, a CMOS chip, a VCSEL chip, a laser diode, a MEMS device, or a IMEMS device. The package can comprise, for example, a cofired ceramic frame or body. The package has an internal stepped structure made of a plurality of plates, with apertures, which are patterned with metallized conductive circuit traces. The microelectronic device can be flip-chip bonded on the plate to these traces, and oriented so that the light-sensitive side is optically accessible through the window. A cover lid can be attached to the opposite side of the package. The result is a compact, low-profile package, having an integral window that can be hermetically-sealed. The package body can be formed by low-temperature cofired ceramic (LTCC) or high-temperature cofired ceramic (HTCC) multilayer processes with the window being simultaneously joined (e.g. cofired) to the package body during LTCC or HTCC processing. Multiple chips can be located within a single package, according to some embodiments. The cover lid can include a window. The apparatus is particularly suited for packaging of MEMS devices, since the number of handling steps is greatly reduced, thereby reducing the potential for contamination. The integral window can further include a lens for optically transforming light passing through the window. The package can include an array of binary optic lenslets made integral with the window. The package can include an electrically-switched optical modulator, such as a lithium niobate window attached to the package, for providing a very fast electrically-operated shutter.

Packaged integrated opto-fluidic solution for harmful fluid analysis

NASA Astrophysics Data System (ADS)

Allenet, T.; Bucci, D.; Geoffray, F.; Canto, F.; Couston, L.; Jardinier, E.; Broquin, J.-E.

2016-02-01

Advances in nuclear fuel reprocessing have led to a surging need for novel chemical analysis tools. In this paper, we present a packaged lab-on-chip approach with co-integration of optical and micro-fluidic functions on a glass substrate as a solution. A chip was built and packaged to obtain light/fluid interaction in order for the entire device to make spectral measurements using the photo spectroscopy absorption principle. The interaction between the analyte solution and light takes place at the boundary between a waveguide and a fluid micro-channel thanks to the evanescent part of the waveguide's guided mode that propagates into the fluid. The waveguide was obtained via ion exchange on a glass wafer. The input and the output of the waveguides were pigtailed with standard single mode optical fibers. The micro-scale fluid channel was elaborated with a lithography procedure and hydrofluoric acid wet etching resulting in a 150+/-8 μm deep channel. The channel was designed with fluidic accesses, in order for the chip to be compatible with commercial fluidic interfaces/chip mounts. This allows for analyte fluid in external capillaries to be pumped into the device through micro-pipes, hence resulting in a fully packaged chip. In order to produce this co-integrated structure, two substrates were bonded. A study of direct glass wafer-to-wafer molecular bonding was carried-out to improve detector sturdiness and durability and put forward a bonding protocol with a bonding surface energy of γ>2.0 J.m-2. Detector viability was shown by obtaining optical mode measurements and detecting traces of 1.2 M neodymium (Nd) solute in 12+/-1 μL of 0.01 M and pH 2 nitric acid (HNO3) solvent by obtaining an absorption peak specific to neodymium at 795 nm.

Rapid qualification of CSP assemblies by increase of ramp rates and cycling temperature ranges

NASA Technical Reports Server (NTRS)

Ghaffarian, R.; Kim, N.; Rose, D.; Hunter, B.; Devitt, K.; Long, T.

2001-01-01

Team members representing government agencies and private companies have joined together to pool in-kind resources for developing the quality and reliability of chip scale packages (CSPs) for a variety of projects.

The chip-scale atomic clock : prototype evaluation.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mescher, Mark; Varghese, Mathew; Lutwak, Robert

2007-12-01

The authors have developed a chip-scale atomic clock (CSAC) for applications requiring atomic timing accuracy in portable battery-powered applications. At PTTI/FCS 2005, they reported on the demonstration of a prototype CSAC, with an overall size of 10 cm{sup 3}, power consumption > 150 mW, and short-term stability sy(t) < 1 x 10-9t-1/2. Since that report, they have completed the development of the CSAC, including provision for autonomous lock acquisition and a calibrated output at 10.0 MHz, in addition to modifications to the physics package and system architecture to improve performance and manufacturability.

Integrated Electrode Arrays for Neuro-Prosthetic Implants

NASA Technical Reports Server (NTRS)

Brandon, Erik; Mojarradi, Mohammede

2003-01-01

Arrays of electrodes integrated with chip-scale packages and silicon-based integrated circuits have been proposed for use as medical electronic implants, including neuro-prosthetic devices that might be implanted in brains of patients who suffer from strokes, spinal-cord injuries, or amyotrophic lateral sclerosis. The electrodes of such a device would pick up signals from neurons in the cerebral cortex, and the integrated circuit would perform acquisition and preprocessing of signal data. The output of the integrated circuit could be used to generate, for example, commands for a robotic arm. Electrode arrays capable of acquiring electrical signals from neurons already exist, but heretofore, there has been no convenient means to integrate these arrays with integrated-circuit chips. Such integration is needed in order to eliminate the need for the extensive cabling now used to pass neural signals to data-acquisition and -processing equipment outside the body. The proposed integration would enable progress toward neuro-prostheses that would be less restrictive of patients mobility. An array of electrodes would comprise a set of thin wires of suitable length and composition protruding from and supported by a fine-pitch micro-ball grid array or chip-scale package (see figure). The associated integrated circuit would be mounted on the package face opposite the probe face, using the solder bumps (the balls of the ball grid array) to make the electrical connections between the probes and the input terminals of the integrated circuit. The key innovation is the insertion of probe wires of the appropriate length and material into the solder bumps through a reflow process, thereby fixing the probes in place and electrically connecting them with the integrated circuit. The probes could be tailored to any distribution of lengths and made of any suitable metal that could be drawn into fine wires. Furthermore, the wires could be coated with an insulating layer using anodization or other processes, to achieve the correct electrical impedance. The probe wires and the packaging materials must be biocompatible using such materials as lead-free solders. For protection, the chip and package can be coated with parylene.

Low temperature co-fired ceramic packaging of CMOS capacitive sensor chip towards cell viability monitoring.

PubMed

Halonen, Niina; Kilpijärvi, Joni; Sobocinski, Maciej; Datta-Chaudhuri, Timir; Hassinen, Antti; Prakash, Someshekar B; Möller, Peter; Abshire, Pamela; Kellokumpu, Sakari; Lloyd Spetz, Anita

2016-01-01

Cell viability monitoring is an important part of biosafety evaluation for the detection of toxic effects on cells caused by nanomaterials, preferably by label-free, noninvasive, fast, and cost effective methods. These requirements can be met by monitoring cell viability with a capacitance-sensing integrated circuit (IC) microchip. The capacitance provides a measurement of the surface attachment of adherent cells as an indication of their health status. However, the moist, warm, and corrosive biological environment requires reliable packaging of the sensor chip. In this work, a second generation of low temperature co-fired ceramic (LTCC) technology was combined with flip-chip bonding to provide a durable package compatible with cell culture. The LTCC-packaged sensor chip was integrated with a printed circuit board, data acquisition device, and measurement-controlling software. The packaged sensor chip functioned well in the presence of cell medium and cells, with output voltages depending on the medium above the capacitors. Moreover, the manufacturing of microfluidic channels in the LTCC package was demonstrated.

Laser-induced forward transfer for flip-chip packaging of single dies.

PubMed

Kaur, Kamal S; Van Steenberge, Geert

2015-03-20

Flip-chip (FC) packaging is a key technology for realizing high performance, ultra-miniaturized and high-density circuits in the micro-electronics industry. In this technique the chip and/or the substrate is bumped and the two are bonded via these conductive bumps. Many bumping techniques have been developed and intensively investigated since the introduction of the FC technology in 1960(1) such as stencil printing, stud bumping, evaporation and electroless/electroplating2. Despite the progress that these methods have made they all suffer from one or more than one drawbacks that need to be addressed such as cost, complex processing steps, high processing temperatures, manufacturing time and most importantly the lack of flexibility. In this paper, we demonstrate a simple and cost-effective laser-based bump forming technique known as Laser-induced Forward Transfer (LIFT)3. Using the LIFT technique a wide range of bump materials can be printed in a single-step with great flexibility, high speed and accuracy at RT. In addition, LIFT enables the bumping and bonding down to chip-scale, which is critical for fabricating ultra-miniature circuitry.

The ideal chip is not enough: Issues retarding the success of wide band-gap devices

NASA Astrophysics Data System (ADS)

Kaminski, Nando

2017-04-01

Semiconductor chips made from the wide band-gap (WBG) materials silicon carbide (SiC) or gallium nitride (GaN) are already approaching the theoretical limits given by the respective materials. Unfortunately, their advantages over silicon devices cannot be fully exploited due to limitations imposed by the device packaging or the circuitry around the semiconductors. Stray inductances slow down the switching speed and increase losses, packaging materials limit the maximum temperature and the maximum useful temperature swing, and passives limit the maximum switching frequency. All these issues have to be solved or at least minimised to make WBG attractive for a wider range of applications and, consequently, to profit from the economy of scale.

PICSiP: new system-in-package technology using a high bandwidth photonic interconnection layer for converged microsystems

NASA Astrophysics Data System (ADS)

Tekin, Tolga; Töpper, Michael; Reichl, Herbert

2009-05-01

Technological frontiers between semiconductor technology, packaging, and system design are disappearing. Scaling down geometries [1] alone does not provide improvement of performance, less power, smaller size, and lower cost. It will require "More than Moore" [2] through the tighter integration of system level components at the package level. System-in-Package (SiP) will deliver the efficient use of three dimensions (3D) through innovation in packaging and interconnect technology. A key bottleneck to the implementation of high-performance microelectronic systems, including SiP, is the lack of lowlatency, high-bandwidth, and high density off-chip interconnects. Some of the challenges in achieving high-bandwidth chip-to-chip communication using electrical interconnects include the high losses in the substrate dielectric, reflections and impedance discontinuities, and susceptibility to crosstalk [3]. Obviously, the incentive for the use of photonics to overcome the challenges and leverage low-latency and highbandwidth communication will enable the vision of optical computing within next generation architectures. Supercomputers of today offer sustained performance of more than petaflops, which can be increased by utilizing optical interconnects. Next generation computing architectures are needed with ultra low power consumption; ultra high performance with novel interconnection technologies. In this paper we will discuss a CMOS compatible underlying technology to enable next generation optical computing architectures. By introducing a new optical layer within the 3D SiP, the development of converged microsystems, deployment for next generation optical computing architecture will be leveraged.

An ultra-compact and low-power oven-controlled crystal oscillator design for precision timing applications.

PubMed

Lim, Jaehyun; Kim, Hyunsoo; Jackson, Thomas; Choi, Kyusun; Kenny, David

2010-09-01

A novel design for a chip-scale miniature oven-controlled crystal oscillator (OCXO) is presented. In this design, all the main components of an OCXO--consisting of an oscillator, a temperature sensor, a heater, and temperature-control circuitry--are integrated on a single CMOS chip. The OCXO package size can be reduced significantly with this design, because the resonator does not require a separate package and most of the circuitry is integrated on a single CMOS chip. Other characteristics such as power consumption and warm-up time are also improved. Two different types of quartz resonators, an AT-cut tab mesa-type quartz crystal and a frame enclosed resonator, allow miniaturization of the OCXO structure. Neither of these quartz resonator types requires a separate package inside the oven structure; therefore, they can each be directly integrated with the custom-designed CMOS chip. The miniature OCXO achieves a frequency stability of +/- 0.35 ppm with an AT-cut tab mesa-type quartz crystal in the temperature range of 0 °C to 60 °C. The maximum power consumption of this miniature OCXO is 1.2 W at start-up and 303 mW at steady state. The warm-up time to reach the steady state is 190 s. These results using the proposed design are better than or the same as high-frequency commercial OCXOs.

Novel First-Level Interconnect Techniques for Flip Chip on MEMS Devices

PubMed Central

Sutanto, Jemmy; Anand, Sindhu; Patel, Chetan; Muthuswamy, Jit

2013-01-01

Flip-chip packaging is desirable for microelectro-mechanical systems (MEMS) devices because it reduces the overall package size and allows scaling up the number of MEMS chips through 3-D stacks. In this report, we demonstrate three novel techniques to create first-level interconnect (FLI) on MEMS: 1) Dip and attach technology for Ag epoxy; 2) Dispense technology for solder paste; 3) Dispense, pull, and attach technology (DPAT) for solder paste. The above techniques required no additional microfabrication steps, produced no visible surface contamination on the MEMS active structures, and generated high-aspect-ratio interconnects. The developed FLIs were successfully tested on MEMS moveable microelectrodes microfabricated by SUMMiTVTM process producing no apparent detrimental effect due to outgassing. The bumping processes were successfully applied on Al-deposited bond pads of 100 μm × 100 μm with an average bump height of 101.3 μm for Ag and 184.8 μm for solder (63Sn, 37Pb). DPAT for solder paste produced bumps with the aspect ratio of 1.8 or more. The average shear strengths of Ag and solder bumps were 78 MPa and 689 kPa, respectively. The electrical test on Ag bumps at 794 A/cm2 demonstrated reliable electrical interconnects with negligible resistance. These scalable FLI technologies are potentially useful for MEMS flip-chip packaging and 3-D stacking. PMID:24504168

Transportable GPU (General Processor Units) chip set technology for standard computer architectures

NASA Astrophysics Data System (ADS)

Fosdick, R. E.; Denison, H. C.

1982-11-01

The USAFR-developed GPU Chip Set has been utilized by Tracor to implement both USAF and Navy Standard 16-Bit Airborne Computer Architectures. Both configurations are currently being delivered into DOD full-scale development programs. Leadless Hermetic Chip Carrier packaging has facilitated implementation of both architectures on single 41/2 x 5 substrates. The CMOS and CMOS/SOS implementations of the GPU Chip Set have allowed both CPU implementations to use less than 3 watts of power each. Recent efforts by Tracor for USAF have included the definition of a next-generation GPU Chip Set that will retain the application-proven architecture of the current chip set while offering the added cost advantages of transportability across ISO-CMOS and CMOS/SOS processes and across numerous semiconductor manufacturers using a newly-defined set of common design rules. The Enhanced GPU Chip Set will increase speed by an approximate factor of 3 while significantly reducing chip counts and costs of standard CPU implementations.

On-chip cooling by superlattice-based thin-film thermoelectrics.

PubMed

Chowdhury, Ihtesham; Prasher, Ravi; Lofgreen, Kelly; Chrysler, Gregory; Narasimhan, Sridhar; Mahajan, Ravi; Koester, David; Alley, Randall; Venkatasubramanian, Rama

2009-04-01

There is a significant need for site-specific and on-demand cooling in electronic, optoelectronic and bioanalytical devices, where cooling is currently achieved by the use of bulky and/or over-designed system-level solutions. Thermoelectric devices can address these limitations while also enabling energy-efficient solutions, and significant progress has been made in the development of nanostructured thermoelectric materials with enhanced figures-of-merit. However, fully functional practical thermoelectric coolers have not been made from these nanomaterials due to the enormous difficulties in integrating nanoscale materials into microscale devices and packaged macroscale systems. Here, we show the integration of thermoelectric coolers fabricated from nanostructured Bi2Te3-based thin-film superlattices into state-of-the-art electronic packages. We report cooling of as much as 15 degrees C at the targeted region on a silicon chip with a high ( approximately 1,300 W cm-2) heat flux. This is the first demonstration of viable chip-scale refrigeration technology and has the potential to enable a wide range of currently thermally limited applications.

Co-Design Method and Wafer-Level Packaging Technique of Thin-Film Flexible Antenna and Silicon CMOS Rectifier Chips for Wireless-Powered Neural Interface Systems.

PubMed

Okabe, Kenji; Jeewan, Horagodage Prabhath; Yamagiwa, Shota; Kawano, Takeshi; Ishida, Makoto; Akita, Ippei

2015-12-16

In this paper, a co-design method and a wafer-level packaging technique of a flexible antenna and a CMOS rectifier chip for use in a small-sized implantable system on the brain surface are proposed. The proposed co-design method optimizes the system architecture, and can help avoid the use of external matching components, resulting in the realization of a small-size system. In addition, the technique employed to assemble a silicon large-scale integration (LSI) chip on the very thin parylene film (5 μm) enables the integration of the rectifier circuits and the flexible antenna (rectenna). In the demonstration of wireless power transmission (WPT), the fabricated flexible rectenna achieved a maximum efficiency of 0.497% with a distance of 3 cm between antennas. In addition, WPT with radio waves allows a misalignment of 185% against antenna size, implying that the misalignment has a less effect on the WPT characteristics compared with electromagnetic induction.

Co-Design Method and Wafer-Level Packaging Technique of Thin-Film Flexible Antenna and Silicon CMOS Rectifier Chips for Wireless-Powered Neural Interface Systems

PubMed Central

Okabe, Kenji; Jeewan, Horagodage Prabhath; Yamagiwa, Shota; Kawano, Takeshi; Ishida, Makoto; Akita, Ippei

2015-01-01

In this paper, a co-design method and a wafer-level packaging technique of a flexible antenna and a CMOS rectifier chip for use in a small-sized implantable system on the brain surface are proposed. The proposed co-design method optimizes the system architecture, and can help avoid the use of external matching components, resulting in the realization of a small-size system. In addition, the technique employed to assemble a silicon large-scale integration (LSI) chip on the very thin parylene film (5 μm) enables the integration of the rectifier circuits and the flexible antenna (rectenna). In the demonstration of wireless power transmission (WPT), the fabricated flexible rectenna achieved a maximum efficiency of 0.497% with a distance of 3 cm between antennas. In addition, WPT with radio waves allows a misalignment of 185% against antenna size, implying that the misalignment has a less effect on the WPT characteristics compared with electromagnetic induction. PMID:26694407

AIN-Based Packaging for SiC High-Temperature Electronics

NASA Technical Reports Server (NTRS)

Savrun, Ender

2004-01-01

Packaging made primarily of aluminum nitride has been developed to enclose silicon carbide-based integrated circuits (ICs), including circuits containing SiC-based power diodes, that are capable of operation under conditions more severe than can be withstood by silicon-based integrated circuits. A major objective of this development was to enable packaged SiC electronic circuits to operate continuously at temperatures up to 500 C. AlN-packaged SiC electronic circuits have commercial potential for incorporation into high-power electronic equipment and into sensors that must withstand high temperatures and/or high pressures in diverse applications that include exploration in outer space, well logging, and monitoring of nuclear power systems. This packaging embodies concepts drawn from flip-chip packaging of silicon-based integrated circuits. One or more SiC-based circuit chips are mounted on an aluminum nitride package substrate or sandwiched between two such substrates. Intimate electrical connections between metal conductors on the chip(s) and the metal conductors on external circuits are made by direct bonding to interconnections on the package substrate(s) and/or by use of holes through the package substrate(s). This approach eliminates the need for wire bonds, which have been the most vulnerable links in conventional electronic circuitry in hostile environments. Moreover, the elimination of wire bonds makes it possible to pack chips more densely than was previously possible.

Storage stability of banana chips in polypropylene based nanocomposite packaging films.

PubMed

Manikantan, M R; Sharma, Rajiv; Kasturi, R; Varadharaju, N

2014-11-01

In this study, polypropylene (PP) based nanocomposite films of 15 different compositions of nanoclay, compatibilizer and thickness were developed and used for packaging and storage of banana chips. The effect of nanocomposite films on the quality characteristics viz. moisture content (MC), water activity (WA), total color difference(TCD), breaking force (BF), free fatty acid (FFA), peroxide value(PV), total plate count (TPC) and overall acceptability score of banana chips under ambient condition at every 15 days interval were studied for 120 days. All quality parameters of stored banana chips increased whereas overall acceptability scores decreased during storage. The elevation in FFA, BF and TCD of stored banana chips increased with elapse of storage period as well as with increased proportion of both nanoclay and compatibilizer but decreased by reducing the thickness of film. Among all the packaging materials, the WA of banana chips remained lower than 0.60 i.e. critical limit for microbial growth up to 90 days of storage. The PV of banana chips packaged also remained within the safe limit of 25 meq oxygen kg(-1) throughout the storage period. Among all the nanocomposite films, packaging material having 5 % compatibilizer, 2 % nanoclay & 100 μm thickness (treatment E) and 10 % compatibilizer, 4 % nanoclay & 120 μm thickness (treatment N) showed better stability of measured quality characteristics of banana chips than any other treatment.

Long-Term Stability of NIST Chip-Scale Atomic Clock Physics Packages

DTIC Science & Technology

2007-01-01

vacuum packaging), as has been demonstrated by Lutwak et al. [3]. Nevertheless, we tried to investigate the causes for the frequency shifts of...stability,” Optics Express, 13, 1249-1253. [3] R. Lutwak , J. Deng, W. Riley, M. Varghese, J. Leblanc, G. Tepolt, M. Mescher, D. K. Serkland, K. M. Geib...the 1st Annual Multiconference on Electronics and Photonics, 7-11 November 2006, Guanajuato, Mexico, in press. [6] R. Lutwak , P. Vlitas, M

Integrated circuit package with lead structure and method of preparing the same

NASA Technical Reports Server (NTRS)

Kennedy, B. W. (Inventor)

1973-01-01

A beam-lead integrated circuit package assembly including a beam-lead integrated circuit chip, a lead frame array bonded to projecting fingers of the chip, a rubber potting compound disposed around the chip, and an encapsulating molded plastic is described. The lead frame array is prepared by photographically printing a lead pattern on a base metal sheet, selectively etching to remove metal between leads, and plating with gold. Joining of the chip to the lead frame array is carried out by thermocompression bonding of mating goldplated surfaces. A small amount of silicone rubber is then applied to cover the chip and bonded joints, and the package is encapsulated with epoxy resin, applied by molding.

Silver flip chip interconnect technology and solid state bonding

NASA Astrophysics Data System (ADS)

Sha, Chu-Hsuan

In this dissertation, fluxless transient liquid phase (TLP) bonding and solid state bonding between thermal expansion mismatch materials have been developed using Ag-In binary systems, pure Au, Ag, and Cu-Ag composite. In contrast to the conventional soldering process, fluxless bonding technique eliminates any corrosion and contamination problems caused by flux. Without flux, it is possible to fabricate high quality joints in large bonding areas where the flux is difficult to clean entirely. High quality joints are crucial to bonding thermal expansion mismatch materials since shear stress develops in the bonded pair. Stress concentration at voids in joints could increases breakage probability. In addition, intermetallic compound (IMC) formation between solder and underbump metallurgy (UBM) is essential for interconnect joint formation in conventional soldering process. However, the interface between IMC and solder is shown to be the weak interface that tends to break first during thermal cycling and drop tests. In our solid state bonding technique, there is no IMC involved in the bonding between Au to Au, Ag and Cu, and Ag and Au. All the reliability issues related to IMC or IMC growth is not our concern. To sum up, ductile bonding media, such as Ag or Au, and proper metallic layered structure are utilized in this research to produce high quality joints. The research starts with developing a low temperature fluxless bonding process using electroplated Ag/In/Ag multilayer structures between Si chip and 304 stainless steel (304SS) substrate. Because the outer thin Ag layer effectively protects inner In layer from oxidation, In layer dissolves Ag layer and joints to Ag layer on the to-be-bonded Si chip when temperature reaches the reflow temperature of 166ºC. Joints consist of mainly Ag-rich Ag-In solid solution and Ag2In. Using this fluxless bonding technique, two 304SS substrates can be bonded together as well. From the high magnification SEM images taken at cross-section, there is no void or gap observed. The new bonding technique presented should be valuable in packaging high power electronic devices for high temperature operations. It should also be useful to bond two 304SS parts together at low bonding temperature of 190ºC. Solid state bonding technique is then introduced to bond semiconductor chips, such as Si, to common substrates, such as Cu or alumina, using pure Ag and Au at a temperature matching the typical reflow temperature used in packaging industries, 260°C. In bonding, we realize the possibilities of solid state bonding of Au to Au, Au to Ag, and Ag to Cu. The idea comes from that Cu, Ag, and Au are located in the same column on periodic table, meaning that they have similar electronic configuration. They therefore have a better chance to share electrons. Also, the crystal lattice of Cu, Ag, and Au is the same, face-centered cubic. In the project, the detailed bonding mechanism is beyond the scope and here we determine the bonding by the experimental result. Ag is chosen as the joint material because of its superior physical properties. It has the highest electrical and thermal conductivities among all metals. It has low yield strength and is relatively ductile. Au is considered as well because its excellent ductility and fatigue resistance. Thus, the Ag or Au joints can deform to accommodate the shear strain caused by CTE mismatch between Si and Cu. Ag and Au have melting temperatures higher than 950°C, so the pure Ag or Au joints are expected to sustain in high operating temperature. The resulting joints do not contain any intermetallic compound. Thus, all reliability issues associated with intermetallic growth in commonly used solder joints do not exist anymore. We finally move to the applications of solid state Ag bonding in flip chip interconnects design. At present, nearly all large-scale integrated circuit (IC) chips are packaged with flip-chip technology. This means that the chip is flipped over and the active (front) side is connected to the package using a large number of tiny solder joints, which provide mechanical support, electrical connection, and heat conduction. For chip-to-package level interconnects, a challenge is the severe mismatch in coefficient of thermal expansion (CTE) between chips and package substrates. The interconnect material thus needs to be compliant to deal with the CTE mismatch. At present, nearly all flip-chip interconnects in electronic industries are made of lead-free Sn-based solders. Soft solders are chosen due to high ductility, low yield strength, relatively low melting temperature, and reasonably good electrical and thermal conductivities. In the never ending scaling down trend, more and more transistors are placed on the same Si chip size. This results in larger pin-out numbers and smaller solder joints. According to International Technology Roadmap for Semiconductors (ITRS), by 2018, the pitch in flip-chip interconnects will become smaller than 70mum for high performance applications. Two problems occur. The first is increase in shear strain. The aspect ratio of flip-chip joints is constrained to 0.7 because it goes through molten phase in the reflow process. Therefore, smaller joints become shorter as well, resulting in larger shear strain arising from CTE mismatch between Si chips and package substrates. The second is increase in stress in the joints. Since intermetallic (IMC) thickness in the joint does not scale down with joint size, ratio of IMC thickness to joint height increases. This further enlarges the shear stress because the IMC does not deform as the soft solder does to accommodate CTE mismatch. In this research, the smallest dimension we achieve for Ag flip chip interconnect joint is 15mum in diameter. The ten advantages of Ag flip chip interconnect technology can be identified as (a) High electrical conductivity, 7.7 times of that of Pb-free solders, (b) High thermal conductivity, 5.2 times of that of Pb-free solders, (c) Completely fluxless, (d) No IMCs; all reliability issues associated with IMC and IMC growth do not exist, (e) Ag is very ductile and can manage CTE mismatch between chips and packages, (f) Ag joints can sustain at very high operation temperature because Ag has high melting temperature of 961°C, (g) No molten phase involved; the bump can better keep its shape and geometry, (h) No molten phase involved; bridging of adjacent bumps is less likely to occur, i. Aspect ratio of bumps can be made greater than 1, (j) The size of the bumps is only limited by the lithographic process. Cu-Ag composite flip chip interconnect joints is developed based on three reasons. The first is lower material cost. The second is to strengthen the columns because the yield strength of Cu is 6 times of that of Ag. The third is to avoid possible Ag migration between Ag electrodes under voltage at temperatures above 250°C. This Cu-Ag composite design presents a solution in the path to the scale down roadmap.

Reliability study of high-brightness multiple single emitter diode lasers

NASA Astrophysics Data System (ADS)

Zhu, Jing; Yang, Thomas; Zhang, Cuipeng; Lang, Chao; Jiang, Xiaochen; Liu, Rui; Gao, Yanyan; Guo, Weirong; Jiang, Yuhua; Liu, Yang; Zhang, Luyan; Chen, Louisa

2015-03-01

In this study the chip bonding processes for various chips from various chip suppliers around the world have been optimized to achieve reliable chip on sub-mount for high performance. These chip on sub-mounts, for examples, includes three types of bonding, 8xx nm-1.2W/10.0W Indium bonded lasers, 9xx nm 10W-20W AuSn bonded lasers and 1470 nm 6W Indium bonded lasers will be reported below. The MTTF@25 of 9xx nm chip on sub-mount (COS) is calculated to be more than 203,896 hours. These chips from various chip suppliers are packaged into many multiple single emitter laser modules, using similar packaging techniques from 2 emitters per module to up to 7 emitters per module. A reliability study including aging test is performed on those multiple single emitter laser modules. With research team's 12 years' experienced packaging design and techniques, precise optical and fiber alignment processes and superior chip bonding capability, we have achieved a total MTTF exceeding 177,710 hours of life time with 60% confidence level for those multiple single emitter laser modules. Furthermore, a separated reliability study on wavelength stabilized laser modules have shown this wavelength stabilized module packaging process is reliable as well.

Fundamental study of microelectronic chip response under laser ultrasonic-interferometric inspection using C-scan method

NASA Astrophysics Data System (ADS)

Yang, Lei; Gong, Jie; Ume, I. Charles

2014-02-01

In modern surface mount packaging technologies, such as flip chips, chip scale packages, and ball grid arrays(BGA), chips are attached to the substrates/printed wiring board (PWB) using solder bump interconnections. The quality of solder bumps between the chips and the substrate/board is difficult to inspect. Laser ultrasonic-interferometric technique was proved to be a promising approach for solder bump inspection because of its noncontact and nondestructive characteristics. Different indicators extracted from received signals have been used to predict the potential defects, such as correlation coefficient, error ratio, frequency shifting, etc. However, the fundamental understanding of the chip behavior under laser ultrasonic inspection is still missing. Specifically, it is not sure whether the laser interferometer detected out-of-plane displacements were due to wave propagation or structural vibration when the chip was excited by pulsed laser. Plus, it is found that the received signals are chip dependent. Both challenges impede the interpretation of acquired signals. In this paper, a C-scan method was proposed to study the underlying phenomenon during laser ultrasonic inspection. The full chip was inspected. The response of the chip under laser excitation was visualized in a movie resulted from acquired signals. Specifically, a BGA chip was investigated to demonstrate the effectiveness of this method. By characterizing signals using discrete wavelet transform(DWT), both ultrasonic wave propagation and vibration were observed. Separation of them was successfully achieved using ideal band-pass filter and visualized in resultant movies, too. The observed ultrasonic waves were characterized and their respective speeds were measured by applying 2-D FFT. The C-scan method, combined with different digital signal processing techniques, was proved to be an very effective methodology to learn the behavior of chips under laser excitation. This general procedure can be applied to any unknown chip before inspection. A wealth of information can be provided by this learning procedure, which greatly benefits the interpretation of inspection signals afterwards.

Investigation of electromigration behavior in lead-free flip chip solder bumps

NASA Astrophysics Data System (ADS)

Kalkundri, Kaustubh Jayant

Packaging technology has also evolved over time in an effort to keep pace with the demanding requirements. Wirebond and flip chip packaging technologies have become extremely versatile and ubiquitous in catering to myriad applications due to their inherent potential. This research is restricted strictly to flip chip technology. This technology incorporates a process in which the bare chip is turned upside down, i.e., active face down, and is bonded through the I/O to the substrate, hence called flip chip. A solder interconnect that provides electrical connection between the chip and substrate is bumped on a processed silicon wafer prior to dicing for die-attach. The assembly is then reflow-soldered followed by the underfill process to provide the required encapsulation. The demand for smaller and lighter products has increased the number of I/Os without increasing the package sizes, thereby drastically reducing the size of the flip chip solder bumps and their pitch. Reliability assessment and verification of these devices has gained tremendous importance due to their shrinking size. To add to the complexity, changing material sets that are results of recently enacted lead-free solder legislations have raised some compatibility issues that are already being researched. In addition to materials and process related flip chip challenges such as solder-flux compatibility, Coefficient of Thermal Expansion (CTE) mismatch, underfill-flux compatibility and thermal management, flip chip packages are vulnerable to a comparatively newer challenge, namely electromigration observed in solder bumps. It is interesting to note that electromigration has come to the forefront of challenges only recently. It has been exacerbated by the reduction in bump cross-section due to the seemingly continuous shrinking in package size over time. The focus of this research was to understand the overall electromigration behavior in lead-free (SnAg) flip chip solder bumps. The objectives of the research were to comprehend the physics of failure mechanism in electromigration for lead-free solder bumps assembled in a flip chip ceramic package having thick copper under bump metallization and to estimate the unknown critical material parameters from Black's equation that describe failure due to electromigration. In addition, the intent was to verify the 'use condition reliability' by extrapolation from experimental conditions. The methodology adopted for this research was comprised of accelerated electromigration tests on SnAg flip chip solder bumps assembled on ceramic substrate with a thick copper under bump metallization. The experimental approach was comprised of elaborate measurement of the temperature of each sample by separate metallization resistance exhibiting positive resistance characteristics to overcome the variation in Joule heating. After conducting the constant current experiments and analyzing the failed samples, it was found that the primary electromigration failure mode observed was the dissolution of the thick copper under bump metallization in the solder, leading to a change in resistance. The lifetime data obtained from different experiments was solved simultaneously using a multiple regression approach to yield the unknown Black's equation parameters of current density exponent and activation energy. In addition to the implementation of a systematic failure analysis and data analysis procedure, it was also deduced that thermomigration due to the temperature gradient across the chip does impact the overall electromigration behavior. This research and the obtained results were significant in bridging the gap for an overall understanding of this critical failure mode observed in flip chip solder bumps. The measurement of each individual sample temperature instead of an average temperature enabled an accurate analysis for predicting the 'use condition reliability' of a comparable product. The obtained results and the conclusions can be used as potential inputs in future designs and newer generations of flip chip devices that might undergo aggressive scaling. This will enable these devices to retain their functionality during their intended useful life with minimal threat of failure due to the potent issue of electromigration. (Abstract shortened by UMI.)

Apparatus and methods for packaging integrated circuit chips with antenna modules providing closed electromagnetic environment for integrated antennas

NASA Technical Reports Server (NTRS)

Gaucher, Brian P. (Inventor); Grzyb, Janusz (Inventor); Liu, Duixian (Inventor); Pfeiffer, Ullrich R. (Inventor)

2008-01-01

Apparatus and methods are provided for packaging IC chips together with integrated antenna modules designed to provide a closed EM (electromagnetic) environment for antenna radiators, thereby allowing antennas to be designed independent from the packaging technology.

3D packaging of a microfluidic system with sensory applications

NASA Astrophysics Data System (ADS)

Morrissey, Anthony; Kelly, Gerard; Alderman, John C.

1997-09-01

Among the main benefits of microsystem technology are its contributions to cost reductio, reliability and improved performance. however, the packaging of microsystems, and particularly microsensor, has proven to be one of the biggest limitations to their commercialization and the packaging of silicon sensor devices can be the most costly part of their fabrication. This paper describes the integration of 3D packaging of a microsystem. Central to the operation of the 3D demonstrator is a micromachined silicon membrane pump to supply fluids to a sensing chamber constructed about the active area of a sensor chip. This chip carries ISFET based chemical sensors, pressure sensors and thermal sensors. The electronics required for controlling and regulating the activity of the various sensors ar also available on this chip and as other chips in the 3D assembly. The demonstrator also contains a power supply module with optical fiber interconnections. All of these modules are integrated into a single plastic- encapsulated 3D vertical multichip module. The reliability of such a structure, initially proposed by Val was demonstrated by Barrett et al. An additional module available for inclusion in some of our assemblies is a test chip capable of measuring the packaging-induced stress experienced during and after assembly. The packaging process described produces a module with very high density and utilizes standard off-the-shelf components to minimize costs. As the sensor chip and micropump include micromachined silicon membranes and microvalves, the packaging of such structures has to allow consideration for the minimization of the packaging-induced stresses. With this in mind, low stress techniques, including the use of soft glob-top materials, were employed.

1.65 mm diameter forward-viewing confocal endomicroscopic catheter using a flip-chip bonded electrothermal MEMS fiber scanner.

PubMed

Seo, Yeong-Hyeon; Hwang, Kyungmin; Jeong, Ki-Hun

2018-02-19

We report a 1.65 mm diameter forward-viewing confocal endomicroscopic catheter using a flip-chip bonded electrothermal MEMS fiber scanner. Lissajous scanning was implemented by the electrothermal MEMS fiber scanner. The Lissajous scanned MEMS fiber scanner was precisely fabricated to facilitate flip-chip connection, and bonded with a printed circuit board. The scanner was successfully combined with a fiber-based confocal imaging system. A two-dimensional reflectance image of the metal pattern 'OPTICS' was successfully obtained with the scanner. The flip-chip bonded scanner minimizes electrical packaging dimensions. The inner diameter of the flip-chip bonded MEMS fiber scanner is 1.3 mm. The flip-chip bonded MEMS fiber scanner is fully packaged with a 1.65 mm diameter housing tube, 1 mm diameter GRIN lens, and a single mode optical fiber. The packaged confocal endomicroscopic catheter can provide a new breakthrough for diverse in-vivo endomicroscopic applications.

Defect Inspection of Flip Chip Solder Bumps Using an Ultrasonic Transducer

PubMed Central

Su, Lei; Shi, Tielin; Xu, Zhensong; Lu, Xiangning; Liao, Guanglan

2013-01-01

Surface mount technology has spurred a rapid decrease in the size of electronic packages, where solder bump inspection of surface mount packages is crucial in the electronics manufacturing industry. In this study we demonstrate the feasibility of using a 230 MHz ultrasonic transducer for nondestructive flip chip testing. The reflected time domain signal was captured when the transducer scanning the flip chip, and the image of the flip chip was generated by scanning acoustic microscopy. Normalized cross-correlation was used to locate the center of solder bumps for segmenting the flip chip image. Then five features were extracted from the signals and images. The support vector machine was adopted to process the five features for classification and recognition. The results show the feasibility of this approach with high recognition rate, proving that defect inspection of flip chip solder bumps using the ultrasonic transducer has high potential in microelectronics packaging.

On-chip infrared sensors: redefining the benefits of scaling

NASA Astrophysics Data System (ADS)

Kita, Derek; Lin, Hongtao; Agarwal, Anu; Yadav, Anupama; Richardson, Kathleen; Luzinov, Igor; Gu, Tian; Hu, Juejun

2017-03-01

Infrared (IR) spectroscopy is widely recognized as a gold standard technique for chemical and biological analysis. Traditional IR spectroscopy relies on fragile bench-top instruments located in dedicated laboratory settings, and is thus not suitable for emerging field-deployed applications such as in-line industrial process control, environmental monitoring, and point-of-care diagnosis. Recent strides in photonic integration technologies provide a promising route towards enabling miniaturized, rugged platforms for IR spectroscopic analysis. It is therefore attempting to simply replace the bulky discrete optical elements used in conventional IR spectroscopy with their on-chip counterparts. This size down-scaling approach, however, cripples the system performance as both the sensitivity of spectroscopic sensors and spectral resolution of spectrometers scale with optical path length. In light of this challenge, we will discuss two novel photonic device designs uniquely capable of reaping performance benefits from microphotonic scaling. We leverage strong optical and thermal confinement in judiciously designed micro-cavities to circumvent the thermal diffusion and optical diffraction limits in conventional photothermal sensors and achieve a record 104 photothermal sensitivity enhancement. In the second example, an on-chip spectrometer design with the Fellgett's advantage is analyzed. The design enables sub-nm spectral resolution on a millimeter-sized, fully packaged chip without moving parts.

Thermal management of LEDs: package to system

NASA Astrophysics Data System (ADS)

Arik, Mehmet; Becker, Charles A.; Weaver, Stanton E.; Petroski, James

2004-01-01

Light emitting diodes, LEDs, historically have been used for indicators and produced low amounts of heat. The introduction of high brightness LEDs with white light and monochromatic colors have led to a movement towards general illumination. The increased electrical currents used to drive the LEDs have focused more attention on the thermal paths in the developments of LED power packaging. The luminous efficiency of LEDs is soon expected to reach over 80 lumens/W, this is approximately 6 times the efficiency of a conventional incandescent tungsten bulb. Thermal management for the solid-state lighting applications is a key design parameter for both package and system level. Package and system level thermal management is discussed in separate sections. Effect of chip packages on junction to board thermal resistance was compared for both SiC and Sapphire chips. The higher thermal conductivity of the SiC chip provided about 2 times better thermal performance than the latter, while the under-filled Sapphire chip package can only catch the SiC chip performance. Later, system level thermal management was studied based on established numerical models for a conceptual solid-state lighting system. A conceptual LED illumination system was chosen and CFD models were created to determine the availability and limitations of passive air-cooling.

Flexible packaging of solid-state integrated circuit chips with elastomeric microfluidics

PubMed Central

Zhang, Bowei; Dong, Quan; Korman, Can E.; Li, Zhenyu; Zaghloul, Mona E.

2013-01-01

A flexible technology is proposed to integrate smart electronics and microfluidics all embedded in an elastomer package. The microfluidic channels are used to deliver both liquid samples and liquid metals to the integrated circuits (ICs). The liquid metals are used to realize electrical interconnects to the IC chip. This avoids the traditional IC packaging challenges, such as wire-bonding and flip-chip bonding, which are not compatible with current microfluidic technologies. As a demonstration we integrated a CMOS magnetic sensor chip and associate microfluidic channels on a polydimethylsiloxane (PDMS) substrate that allows precise delivery of small liquid samples to the sensor. Furthermore, the packaged system is fully functional under bending curvature radius of one centimetre and uniaxial strain of 15%. The flexible integration of solid-state ICs with microfluidics enables compact flexible electronic and lab-on-a-chip systems, which hold great potential for wearable health monitoring, point-of-care diagnostics and environmental sensing among many other applications.

Chip-scale white flip-chip light-emitting diode containing indium phosphide/zinc selenide quantum dots

NASA Astrophysics Data System (ADS)

Fan, Bingfeng; Yan, Linchao; Lao, Yuqin; Ma, Yanfei; Chen, Zimin; Ma, Xuejin; Zhuo, Yi; Pei, Yanli; Wang, Gang

2017-08-01

A method for preparing a quantum dot (QD)-white light-emitting diode (WLED) is reported. Holes were etched in the SiO2 layer deposited on the sapphire substrate of the flip-chip LED by inductively coupled plasma, and these holes were then filled with QDs. An ultraviolet-curable resin was then spin-coated on top of the QD-containing SiO2 layer, and the resin was cured to act as a protecting layer. The reflective sidewall structure minimized sidelight leakage. The fabrication of the QD-WLED is simple in preparation and compatible with traditional LED processes, which was the minimum size of the WLED chip-scale integrated package. InP/ZnS core-shell QDs were used as the converter in the WLED. A blue light-emitting diode with a flip-chip structure was used as the excitation source. The QD-WLED exhibited color temperatures from 5900 to 6400 K and Commission Internationale De L'Elcairage color coordinates from (0.315, 0.325) to (0.325, 0.317), under drive currents from 100 to 400 mA. The QD-WLED exhibited stable optoelectronic properties.

Packaging Technologies for 500 C SiC Electronics and Sensors: Challenges in Material Science and Technology

NASA Technical Reports Server (NTRS)

Chen, Liang-Yu; Neudeck, Philip G.; Behelm, Glenn M.; Spry, David J.; Meredith, Roger D.; Hunter, Gary W.

2015-01-01

This paper presents ceramic substrates and thick-film metallization based packaging technologies in development for 500C silicon carbide (SiC) electronics and sensors. Prototype high temperature ceramic chip-level packages and printed circuit boards (PCBs) based on ceramic substrates of aluminum oxide (Al2O3) and aluminum nitride (AlN) have been designed and fabricated. These ceramic substrate-based chip-level packages with gold (Au) thick-film metallization have been electrically characterized at temperatures up to 550C. The 96 alumina packaging system composed of chip-level packages and PCBs has been successfully tested with high temperature SiC discrete transistor devices at 500C for over 10,000 hours. In addition to tests in a laboratory environment, a SiC junction field-effect-transistor (JFET) with a packaging system composed of a 96 alumina chip-level package and an alumina printed circuit board was tested on low earth orbit for eighteen months via a NASA International Space Station experiment. In addition to packaging systems for electronics, a spark-plug type sensor package based on this high temperature interconnection system for high temperature SiC capacitive pressure sensors was also developed and tested. In order to further significantly improve the performance of packaging system for higher packaging density, higher operation frequency, power rating, and even higher temperatures, some fundamental material challenges must be addressed. This presentation will discuss previous development and some of the challenges in material science (technology) to improve high temperature dielectrics for packaging applications.

Towards co-packaging of photonics and microelectronics in existing manufacturing facilities

NASA Astrophysics Data System (ADS)

Janta-Polczynski, Alexander; Cyr, Elaine; Bougie, Jerome; Drouin, Alain; Langlois, Richard; Childers, Darrell; Takenobu, Shotaro; Taira, Yoichi; Lichoulas, Ted W.; Kamlapurkar, Swetha; Engelmann, Sebastian; Fortier, Paul; Boyer, Nicolas; Barwicz, Tymon

2018-02-01

The impact of integrated photonics on optical interconnects is currently muted by challenges in photonic packaging and in the dense integration of photonic modules with microelectronic components on printed circuit boards. Single mode optics requires tight alignment tolerance for optical coupling and maintaining this alignment in a cost-efficient package can be challenging during thermal excursions arising from downstream microelectronic assembly processes. In addition, the form factor of typical fiber connectors is incompatible with the dense module integration expected on printed circuit boards. We have implemented novel approaches to interfacing photonic chips to standard optical fibers. These leverage standard high throughput microelectronic assembly tooling and self-alignment techniques resulting in photonic packaging that is scalable in manufacturing volume and in the number of optical IOs per chip. In addition, using dense optical fiber connectors with space-efficient latching of fiber patch cables results in compact module size and efficient board integration, bringing the optics closer to the logic chip to alleviate bandwidth bottlenecks. This packaging direction is also well suited for embedding optics in multi-chip modules, including both photonic and microelectronic chips. We discuss the challenges and rewards in this type of configuration such as thermal management and signal integrity.

Scalable Manufacturing of Solderable and Stretchable Physiologic Sensing Systems.

PubMed

Kim, Yun-Soung; Lu, Jesse; Shih, Benjamin; Gharibans, Armen; Zou, Zhanan; Matsuno, Kristen; Aguilera, Roman; Han, Yoonjae; Meek, Ann; Xiao, Jianliang; Tolley, Michael T; Coleman, Todd P

2017-10-01

Methods for microfabrication of solderable and stretchable sensing systems (S4s) and a scaled production of adhesive-integrated active S4s for health monitoring are presented. S4s' excellent solderability is achieved by the sputter-deposited nickel-vanadium and gold pad metal layers and copper interconnection. The donor substrate, which is modified with "PI islands" to become selectively adhesive for the S4s, allows the heterogeneous devices to be integrated with large-area adhesives for packaging. The feasibility for S4-based health monitoring is demonstrated by developing an S4 integrated with a strain gauge and an onboard optical indication circuit. Owing to S4s' compatibility with the standard printed circuit board assembly processes, a variety of commercially available surface mount chip components, such as the wafer level chip scale packages, chip resistors, and light-emitting diodes, can be reflow-soldered onto S4s without modifications, demonstrating the versatile and modular nature of S4s. Tegaderm-integrated S4 respiration sensors are tested for robustness for cyclic deformation, maximum stretchability, durability, and biocompatibility for multiday wear time. The results of the tests and demonstration of the respiration sensing indicate that the adhesive-integrated S4s can provide end users a way for unobtrusive health monitoring. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Molded underfill (MUF) encapsulation for flip-chip package: A numerical investigation

NASA Astrophysics Data System (ADS)

Azmi, M. A.; Abdullah, M. K.; Abdullah, M. Z.; Ariff, Z. M.; Saad, Abdullah Aziz; Hamid, M. F.; Ismail, M. A.

2017-07-01

This paper presents the numerical simulation of epoxy molding compound (EMC) filling in multi flip-chip packages during encapsulation process. The empty and a group flip chip packages were considered in the mold cavity in order to study the flow profile of the EMC. SOLIDWORKS software was used for three-dimensional modeling and it was incorporated into fluid analysis software namely as ANSYS FLUENT. The volume of fluid (VOF) technique was used for capturing the flow front profiles and Power Law model was applied for its rheology model. The numerical result are compared and discussed with previous experimental and it was shown a good conformity for model validation. The prediction of flow front was observed and analyzed at different filling time. The possibility and visual of void formation in the package is captured and the number of flip-chip is one factor that contributed to the void formation.

Packaging Technologies for High Temperature Electronics and Sensors

NASA Technical Reports Server (NTRS)

Chen, Liang-Yu; Hunter, Gary W.; Neudeck, Philip G.; Beheim, Glenn M.; Spry, David J.; Meredith, Roger D.

2013-01-01

This paper reviews ceramic substrates and thick-film metallization based packaging technologies in development for 500 C silicon carbide (SiC) electronics and sensors. Prototype high temperature ceramic chip-level packages and printed circuit boards (PCBs) based on ceramic substrates of aluminum oxide (Al2O3) and aluminum nitride (AlN) have been designed and fabricated. These ceramic substrate-based chip-level packages with gold (Au) thick-film metallization have been electrically characterized at temperatures up to 550 C. A 96% alumina based edge connector for a PCB level subsystem interconnection has also been demonstrated recently. The 96% alumina packaging system composed of chip-level packages and PCBs has been tested with high temperature SiC devices at 500 C for over 10,000 hours. In addition to tests in a laboratory environment, a SiC JFET with a packaging system composed of a 96% alumina chip-level package and an alumina printed circuit board mounted on a data acquisition circuit board was launched as a part of the MISSE-7 suite to the International Space Station via a Shuttle mission. This packaged SiC transistor was successfully tested in orbit for eighteen months. A spark-plug type sensor package designed for high temperature SiC capacitive pressure sensors was developed. This sensor package combines the high temperature interconnection system with a commercial high temperature high pressure stainless steel seal gland (electrical feed-through). Test results of a packaged high temperature capacitive pressure sensor at 500 C are also discussed. In addition to the pressure sensor package, efforts for packaging high temperature SiC diode-based gas chemical sensors are in process.

Package Holds Five Monolithic Microwave Integrated Circuits

NASA Technical Reports Server (NTRS)

Mysoor, Narayan R.; Decker, D. Richard; Olson, Hilding M.

1996-01-01

Packages protect and hold monolithic microwave integrated circuit (MMIC) chips while providing dc and radio-frequency (RF) electrical connections for chips undergoing development. Required to be compact, lightweight, and rugged. Designed to minimize undesired resonances, reflections, losses, and impedance mismatches.

Dry-film polymer waveguide for silicon photonics chip packaging.

PubMed

Hsu, Hsiang-Han; Nakagawa, Shigeru

2014-09-22

Polymer waveguide made by dry film process is demonstrated for silicon photonics chip packaging. With 8 μm × 11.5 μm core waveguide, little penalty is observed up to 25 Gbps before or after the light propagate through a 10-km long single-mode fiber (SMF). Coupling loss to SMF is 0.24 dB and 1.31 dB at the polymer waveguide input and output ends, respectively. Alignment tolerance for 0.5 dB loss increase is +/- 1.0 μm along both vertical and horizontal directions for the coupling from the polymer waveguide to SMF. The dry-film polymer waveguide demonstrates promising performance for silicon photonics chip packaging used in next generation optical multi-chip module.

Ten-channel InP-based large-scale photonic integrated transmitter fabricated by SAG technology

NASA Astrophysics Data System (ADS)

Zhang, Can; Zhu, Hongliang; Liang, Song; Cui, Xiao; Wang, Huitao; Zhao, Lingjuan; Wang, Wei

2014-12-01

A 10-channel InP-based large-scale photonic integrated transmitter was fabricated by selective area growth (SAG) technology combined with butt-joint regrowth (BJR) technology. The SAG technology was utilized to fabricate the electroabsorption modulated distributed feedback (DFB) laser (EML) arrays at the same time. The design of coplanar electrodes for electroabsorption modulator (EAM) was used for the flip-chip bonding package. The lasing wavelength of DFB laser could be tuned by the integrated micro-heater to match the ITU grids, which only needs one electrode pad. The average output power of each channel is 250 μW with an injection current of 200 mA. The static extinction ratios of the EAMs for 10 channels tested are ranged from 15 to 27 dB with a reverse bias of 6 V. The frequencies of 3 dB bandwidth of the chip for each channel are around 14 GHz. The novel design and simple fabrication process show its enormous potential in reducing the cost of large-scale photonic integrated circuit (LS-PIC) transmitter with high chip yields.

MEMS packaging: state of the art and future trends

NASA Astrophysics Data System (ADS)

Bossche, Andre; Cotofana, Carmen V. B.; Mollinger, Jeff R.

1998-07-01

Now that the technology for Integrated sensor and MEMS devices has become sufficiently mature to allow mass production, it is expected that the prices of bare chips will drop dramatically. This means that the package prices will become a limiting factor in market penetration, unless low cost packaging solutions become available. This paper will discuss the developments in packaging technology. Both single-chip and multi-chip packaging solutions will be addressed. It first starts with a discussion on the different requirements that have to be met; both from a device point of view (open access paths to the environment, vacuum cavities, etc.) and from the application point of view (e.g. environmental hostility). Subsequently current technologies are judged on their applicability for MEMS and sensor packaging and a forecast is given for future trends. It is expected that the large majority of sensing devices will be applied in relative friendly environments for which plastic packages would suffice. Therefore, on the short term an important role is foreseen for recently developed plastic packaging techniques such as precision molding and precision dispensing. Just like in standard electronic packaging, complete wafer level packaging methods for sensing devices still have a long way to go before they can compete with the highly optimized and automated plastic packaging processes.

Thermal Cycle Reliability and Failure Mechanisms of CCGA and PBGA Assemblies with and without Corner Staking

NASA Technical Reports Server (NTRS)

Ghaffarian, Reza

2008-01-01

Area array packages (AAPs) with 1.27 mm pitch have been the packages of choice for commercial applications; they are now starting to be implemented for use in military and aerospace applications. Thermal cycling characteristics of plastic ball grid array (PBGA) and chip scale package assemblies, because of their wide usage for commercial applications, have been extensively reported on in literature. Thermal cycling represents the on-off environmental condition for most electronic products and therefore is a key factor that defines reliability.However, very limited data is available for thermal cycling behavior of ceramic packages commonly used for the aerospace applications. For high reliability applications, numerous AAPs are available with an identical design pattern both in ceramic and plastic packages. This paper compares assembly reliability of ceramic and plastic packages with the identical inputs/outputs(I/Os) and pattern. The ceramic package was in the form of ceramic column grid array (CCGA) with 560 I/Os peripheral array with the identical pad design as its plastic counterpart.

Food product design: emerging evidence for food policy.

PubMed

Al-Hamdani, Mohammed; Smith, Steven

2017-03-01

The research on the impact of specific brand elements such as food descriptors and package colors is underexplored. We tested whether a "light" color and a "low-calorie" descriptor on food packages gain favorable consumer perception ratings as compared with regular packages. Our online experiment recruited 406 adults in a 3 (product type: Chips versus Juice versus Yoghurt) × 2 (descriptor type: regular versus low-calorie) × 2 (color type: regular versus light) mixed design. Dependent variables were sensory (evaluations of the product's nutritional value and quality), product-based (evaluations of the product's physical appeal), and consumer-based (evaluations of the potential consumers of the product) scales. "Low-calorie" descriptors were found to increase sensory ratings as compared with regular descriptors and light-colored packages received higher product-based ratings as compared with their regular-colored counterparts. Food package color and descriptors present a promising venue for understanding preventative measures against obesity.[Formula: see text].

Leadless Chip Carrier Packaging and CAD/CAM-Supported Wire Wrap Interconnect Technology for Subnanosecond ECL.

DTIC Science & Technology

1981-11-01

Showing Wire . 99 Impregnanted Silicone Rubber Contacts, Chip Carrier, ard Lid 35. Technit Connector For 68-Pad JEDEC Type A Leadless . . 100 Chip Carrier...Points of Various . . . . 124 Solders 4. Composition of Alloys Employed in Dual-In-Line . . . . 128 Package Pins and Plating by Mass Spectrographic...swings, and subnanosecond gate delays and risetimes. Presently, emitter coupled logic (ECL) and current mode logic (CML), both fabricated with silicon tech

Neural Implants, Packaging for Biocompatible Implants, and Improving Fabricated Capacitors

NASA Astrophysics Data System (ADS)

Agger, Elizabeth Rose

We have completed the circuit design and packaging procedure for an NIH-funded neural implant, called a MOTE (Microscale Optoelectronically Transduced Electrode). Neural recording implants for mice have greatly advanced neuroscience, but they are often damaging and limited in their recording location. This project will result in free-floating implants that cause less damage, provide rapid electronic recording, and increase range of recording across the cortex. A low-power silicon IC containing amplification and digitization sub-circuits is powered by a dual-function gallium arsenide photovoltaic and LED. Through thin film deposition, photolithography, and chemical and physical etching, the Molnar Group and the McEuen Group (Applied and Engineering Physics department) will package the IC and LED into a biocompatible implant approximately 100microm3. The IC and LED are complete and we have begun refining this packaging procedure in the Cornell NanoScale Science & Technology Facility. ICs with 3D time-resolved imaging capabilities can image microorganisms and other biological samples given proper packaging. A portable, flat, easily manufactured package would enable scientists to place biological samples on slides directly above the Molnar group's imaging chip. We have developed a packaging procedure using laser cutting, photolithography, epoxies, and metal deposition. Using a flip-chip method, we verified the process by aligning and adhering a sample chip to a holder wafer. In the CNF, we have worked on a long-term metal-insulator-metal (MIM) capacitor characterization project. Former Fellow and continuing CNF user Kwame Amponsah developed the original procedure for the capacitor fabrication, and another former fellow, Jonilyn Longenecker, revised the procedure and began the arduous process of characterization. MIM caps are useful to clean room users as testing devices to verify electronic characteristics of their active circuitry. This project's objective is to determine differences in current-voltage (IV) and capacitor-voltage (CV) relationships across variations in capacitor size and dielectric type. This effort requires an approximately 20-step process repeated for two-to-six varieties (dependent on temperature and thermal versus plasma options) of the following dielectrics: HfO2, SiO2, Al2O3, TaOx, and TiO2.

Physics-based process modeling, reliability prediction, and design guidelines for flip-chip devices

NASA Astrophysics Data System (ADS)

Michaelides, Stylianos

Flip Chip on Board (FCOB) and Chip-Scale Packages (CSPs) are relatively new technologies that are being increasingly used in the electronic packaging industry. Compared to the more widely used face-up wirebonding and TAB technologies, flip-chips and most CSPs provide the shortest possible leads, lower inductance, higher frequency, better noise control, higher density, greater input/output (I/O), smaller device footprint and lower profile. However, due to the short history and due to the introduction of several new electronic materials, designs, and processing conditions, very limited work has been done to understand the role of material, geometry, and processing parameters on the reliability of flip-chip devices. Also, with the ever-increasing complexity of semiconductor packages and with the continued reduction in time to market, it is too costly to wait until the later stages of design and testing to discover that the reliability is not satisfactory. The objective of the research is to develop integrated process-reliability models that will take into consideration the mechanics of assembly processes to be able to determine the reliability of face-down devices under thermal cycling and long-term temperature dwelling. The models incorporate the time and temperature-dependent constitutive behavior of various materials in the assembly to be able to predict failure modes such as die cracking and solder cracking. In addition, the models account for process-induced defects and macro-micro features of the assembly. Creep-fatigue and continuum-damage mechanics models for the solder interconnects and fracture-mechanics models for the die have been used to determine the reliability of the devices. The results predicted by the models have been successfully validated against experimental data. The validated models have been used to develop qualification and test procedures for implantable medical devices. In addition, the research has helped develop innovative face-down devices without the underfill, based on the thorough understanding of the failure modes. Also, practical design guidelines for material, geometry and process parameters for reliable flip-chip devices have been developed.

Design considerations for FET-gated power transistors

NASA Technical Reports Server (NTRS)

Chen, D. Y.; Chin, S. A.

1983-01-01

An FET-bipolar combinational power transistor configuration (tested up to 300 V, 20 A at 100 kHz) is described. The critical parameters for integrating the chips in hybrid form are examined, and an effort to optimize the overall characteristics of the configuration is discussed. Chip considerations are examined with respect to the voltage and current rating of individual chips, the FET surge capability, the choice of triple diffused transistor or epitaxial transistor for the bipolar element, the current tailing effect, and the implementation of the bipolar transistor and an FET as single chip or separate chips. Package considerations are discussed with respect to package material and geometry, surge current capability of bipolar base terminal bonding, and power losses distribution.

3-D readout-electronics packaging for high-bandwidth massively paralleled imager

DOEpatents

Kwiatkowski, Kris; Lyke, James

2007-12-18

Dense, massively parallel signal processing electronics are co-packaged behind associated sensor pixels. Microchips containing a linear or bilinear arrangement of photo-sensors, together with associated complex electronics, are integrated into a simple 3-D structure (a "mirror cube"). An array of photo-sensitive cells are disposed on a stacked CMOS chip's surface at a 45.degree. angle from light reflecting mirror surfaces formed on a neighboring CMOS chip surface. Image processing electronics are held within the stacked CMOS chip layers. Electrical connections couple each of said stacked CMOS chip layers and a distribution grid, the connections for distributing power and signals to components associated with each stacked CSMO chip layer.

Optomechanical Design and Characterization of a Printed-Circuit-Board-Based Free-Space Optical Interconnect Package

NASA Astrophysics Data System (ADS)

Zheng, Xuezhe; Marchand, Philippe J.; Huang, Dawei; Kibar, Osman; Ozkan, Nur S. E.; Esener, Sadik C.

1999-09-01

We present a proof of concept and a feasibility demonstration of a practical packaging approach in which free-space optical interconnects (FSOI s) can be integrated simply on electronic multichip modules (MCM s) for intra-MCM board interconnects. Our system-level packaging architecture is based on a modified folded 4 f imaging system that has been implemented with only off-the-shelf optics, conventional electronic packaging, and passive-assembly techniques to yield a potentially low-cost and manufacturable packaging solution. The prototypical system as built supports 48 independent FSOI channels with 8 separate laser and detector chips, for which each chip consists of a one-dimensional array of 12 devices. All the chips are assembled on a single substrate that consists of a printed circuit board or a ceramic MCM. Optical link channel efficiencies of greater than 90% and interchannel cross talk of less than 20 dB at low frequency have been measured. The system is compact at only 10 in. 3 (25.4 cm 3 ) and is scalable, as it can easily accommodate additional chips as well as two-dimensional optoelectronic device arrays for increased interconnection density.

Novel Micro ElectroMechanical Systems (MEMS) Packaging for the Skin of the Satellite

NASA Technical Reports Server (NTRS)

Darrin, M. Ann; Osiander, Robert; Lehtonen, John; Farrar, Dawnielle; Douglas, Donya; Swanson, Ted

2004-01-01

This paper includes a discussion of the novel packaging techniques that are needed to place MEMS based thermal control devices on the skin of various satellites, eliminating the concern associated with potential particulates &om integration and test or the launch environment. Protection of this MEMS based thermal device is achieved using a novel polymer that is both IR transmissive and electrically conductive. This polymer was originally developed and qualified for space flight application by NASA at the Langley Research Center. The polymer material, commercially known as CPI, is coated with a thin layer of ITO and sandwiched between two window-like frames. The packaging of the MEMS based radiator assembly offers the benefits of micro-scale devices in a chip on board fashion, with the level of protection generally found in packaged parts.

Method of fabricating a microelectronic device package with an integral window

DOEpatents

Peterson, Kenneth A.; Watson, Robert D.

2003-01-01

A method of fabricating a microelectronic device package with an integral window for providing optical access through an aperture in the package. The package is made of a multilayered insulating material, e.g., a low-temperature cofired ceramic (LTCC) or high-temperature cofired ceramic (HTCC). The window is inserted in-between personalized layers of ceramic green tape during stackup and registration. Then, during baking and firing, the integral window is simultaneously bonded to the sintered ceramic layers of the densified package. Next, the microelectronic device is flip-chip bonded to cofired thick-film metallized traces on the package, where the light-sensitive side is optically accessible through the window. Finally, a cover lid is attached to the opposite side of the package. The result is a compact, low-profile package, flip-chip bonded, hermetically-sealed package having an integral window.

An ultra-compact processor module based on the R3000

NASA Astrophysics Data System (ADS)

Mullenhoff, D. J.; Kaschmitter, J. L.; Lyke, J. C.; Forman, G. A.

1992-08-01

Viable high density packaging is of critical importance for future military systems, particularly space borne systems which require minimum weight and size and high mechanical integrity. A leading, emerging technology for high density packaging is multi-chip modules (MCM). During the 1980's, a number of different MCM technologies have emerged. In support of Strategic Defense Initiative Organization (SDIO) programs, Lawrence Livermore National Laboratory (LLNL) has developed, utilized, and evaluated several different MCM technologies. Prior LLNL efforts include modules developed in 1986, using hybrid wafer scale packaging, which are still operational in an Air Force satellite mission. More recent efforts have included very high density cache memory modules, developed using laser pantography. As part of the demonstration effort, LLNL and Phillips Laboratory began collaborating in 1990 in the Phase 3 Multi-Chip Module (MCM) technology demonstration project. The goal of this program was to demonstrate the feasibility of General Electric's (GE) High Density Interconnect (HDI) MCM technology. The design chosen for this demonstration was the processor core for a MIPS R3000 based reduced instruction set computer (RISC), which has been described previously. It consists of the R3000 microprocessor, R3010 floating point coprocessor and 128 Kbytes of cache memory.

Reliability and Characteristics of Wafer-Level Chip-Scale Packages under Current Stress

NASA Astrophysics Data System (ADS)

Chen, Po-Ying; Kung, Heng-Yu; Lai, Yi-Shao; Hsiung Tsai, Ming; Yeh, Wen-Kuan

2008-02-01

In this work, we present a novel approach and method for elucidating the characteristics of wafer-level chip-scale packages (WLCSPs) for electromigration (EM) tests. The die in WLCSP was directly attached to the substrate via a soldered interconnect. The shrinking of the area of the die that is available for power, and the solder bump also shrinks the volume and increases the density of electrons for interconnect efficiency. The bump current density now approaches to 106 A/cm2, at which point the EM becomes a significant reliability issue. As known, the EM failure depends on numerous factors, including the working temperature and the under bump metallization (UBM) thickness. A new interconnection geometry is adopted extensively with moderate success in overcoming larger mismatches between the displacements of components during current and temperature changes. Both environments and testing parameters for WLCSP are increasingly demanded. Although failure mechanisms are considered to have been eliminated or at least made manageable, new package technologies are again challenging its process, integrity and reliability. WLCSP technology was developed to eliminate the need for encapsulation to ensure compatibility with smart-mount technology (SMT). The package has good handing properties but is now facing serious reliability problems. In this work, we investigated the reliability of a WLCSP subjected to different accelerated current stressing conditions at a fixed ambient temperature of 125 °C. A very strong correlation exists between the mean time to failure (MTTF) of the WLCSP test vehicle and the mean current density that is carried by a solder joint. A series of current densities were applied to the WLCSP architecture; Black's power law was employed in a failure mode simulation. Additionally, scanning electron microscopy (SEM) was adopted to determine the differences existing between high- and low-current-density failure modes.

Silicon Carbide Integrated Circuit Chip

NASA Image and Video Library

2015-02-17

A multilevel interconnect silicon carbide integrated circuit chip with co-fired ceramic package and circuit board recently developed at the NASA GRC Smart Sensors and Electronics Systems Branch for high temperature applications. High temperature silicon carbide electronics and compatible packaging technologies are elements of instrumentation for aerospace engine control and long term inner-solar planet explorations.

Development of a package-free transparent disposable biosensor chip for simultaneous measurements of blood constituents and investigation of its storage stability.

PubMed

Nakamura, Hideaki; Tohyama, Kana; Tanaka, Masanori; Shinohara, Shouji; Tokunaga, Yuichi; Kurusu, Fumiyo; Koide, Satoshi; Gotoh, Masao; Karube, Isao

2007-12-15

A package-free transparent disposable biosensor chip was developed by a screen-printing technique. The biosensor chip was fabricated by stacking a substrate with two carbon electrodes on its surface, a spacer consisting of a resist layer and an adhesive layer, and a cover. The structure of the chip keeps the interior of the reaction-detecting section airtight until use. The chip is equipped with double electrochemical measuring elements for the simultaneous measurement of multiple items, and the reagent layer was developed in sample-feeding path. The sample-inlet port and air-discharge port are simultaneously opened by longitudinally folding in two biosensor units with a notch as a boundary. Then the shape of the chip is changed to a V-shape. The reaction-detecting section of the chip has a 1.0 microl sample volume for one biosensor unit. Excellent results were obtained with the chip in initial simultaneous chronoamperometric measurements of both glucose (r=1.00) and lactate (r=0.998) in the same samples. The stability of the enzyme sensor signals of the chip was estimated at ambient atmosphere on 8 testing days during a 6-month period. The results were compared with those obtained for an unpackaged chip used as a control. The package-free chip proved to be twice as good as the control chip in terms of the reproducibility of slopes from 16 calibration curves (one calibration curve: 0, 100, 300, 500 mg dl(-1) glucose; n=3) and 4.6 times better in terms of the reproducibility of correlation coefficients from the 16 calibration curves.

Three-dimensional fit-to-flow microfluidic assembly.

PubMed

Chen, Arnold; Pan, Tingrui

2011-12-01

Three-dimensional microfluidics holds great promise for large-scale integration of versatile, digitalized, and multitasking fluidic manipulations for biological and clinical applications. Successful translation of microfluidic toolsets to these purposes faces persistent technical challenges, such as reliable system-level packaging, device assembly and alignment, and world-to-chip interface. In this paper, we extended our previously established fit-to-flow (F2F) world-to-chip interconnection scheme to a complete system-level assembly strategy that addresses the three-dimensional microfluidic integration on demand. The modular F2F assembly consists of an interfacial chip, pluggable alignment modules, and multiple monolithic layers of microfluidic channels, through which convoluted three-dimensional microfluidic networks can be easily assembled and readily sealed with the capability of reconfigurable fluid flow. The monolithic laser-micromachining process simplifies and standardizes the fabrication of single-layer pluggable polymeric modules, which can be mass-produced as the renowned Lego(®) building blocks. In addition, interlocking features are implemented between the plug-and-play microfluidic chips and the complementary alignment modules through the F2F assembly, resulting in facile and secure alignment with average misalignment of 45 μm. Importantly, the 3D multilayer microfluidic assembly has a comparable sealing performance as the conventional single-layer devices, providing an average leakage pressure of 38.47 kPa. The modular reconfigurability of the system-level reversible packaging concept has been demonstrated by re-routing microfluidic flows through interchangeable modular microchannel layers.

ChIPpeakAnno: a Bioconductor package to annotate ChIP-seq and ChIP-chip data

PubMed Central

2010-01-01

Background Chromatin immunoprecipitation (ChIP) followed by high-throughput sequencing (ChIP-seq) or ChIP followed by genome tiling array analysis (ChIP-chip) have become standard technologies for genome-wide identification of DNA-binding protein target sites. A number of algorithms have been developed in parallel that allow identification of binding sites from ChIP-seq or ChIP-chip datasets and subsequent visualization in the University of California Santa Cruz (UCSC) Genome Browser as custom annotation tracks. However, summarizing these tracks can be a daunting task, particularly if there are a large number of binding sites or the binding sites are distributed widely across the genome. Results We have developed ChIPpeakAnno as a Bioconductor package within the statistical programming environment R to facilitate batch annotation of enriched peaks identified from ChIP-seq, ChIP-chip, cap analysis of gene expression (CAGE) or any experiments resulting in a large number of enriched genomic regions. The binding sites annotated with ChIPpeakAnno can be viewed easily as a table, a pie chart or plotted in histogram form, i.e., the distribution of distances to the nearest genes for each set of peaks. In addition, we have implemented functionalities for determining the significance of overlap between replicates or binding sites among transcription factors within a complex, and for drawing Venn diagrams to visualize the extent of the overlap between replicates. Furthermore, the package includes functionalities to retrieve sequences flanking putative binding sites for PCR amplification, cloning, or motif discovery, and to identify Gene Ontology (GO) terms associated with adjacent genes. Conclusions ChIPpeakAnno enables batch annotation of the binding sites identified from ChIP-seq, ChIP-chip, CAGE or any technology that results in a large number of enriched genomic regions within the statistical programming environment R. Allowing users to pass their own annotation data such as a different Chromatin immunoprecipitation (ChIP) preparation and a dataset from literature, or existing annotation packages, such as GenomicFeatures and BSgenome, provides flexibility. Tight integration to the biomaRt package enables up-to-date annotation retrieval from the BioMart database. PMID:20459804

Enhanced thermaly managed packaging for III-nitride light emitters

NASA Astrophysics Data System (ADS)

Kudsieh, Nicolas

In this Dissertation our work on `enhanced thermally managed packaging of high power semiconductor light sources for solid state lighting (SSL)' is presented. The motivation of this research and development is to design thermally high stable cost-efficient packaging of single and multi-chip arrays of III-nitrides wide bandgap semiconductor light sources through mathematical modeling and simulations. Major issues linked with this technology are device overheating which causes serious degradation in their illumination intensity and decrease in the lifetime. In the introduction the basics of III-nitrides WBG semiconductor light emitters are presented along with necessary thermal management of high power cingulated and multi-chip LEDs and laser diodes. This work starts at chip level followed by its extension to fully packaged lighting modules and devices. Different III-nitride structures of multi-quantum well InGaN/GaN and AlGaN/GaN based LEDs and LDs were analyzed using advanced modeling and simulation for different packaging designs and high thermal conductivity materials. Study started with basic surface mounted devices using conventional packaging strategies and was concluded with the latest thermal management of chip-on-plate (COP) method. Newly discovered high thermal conductivity materials have also been incorporated for this work. Our study also presents the new approach of 2D heat spreaders using such materials for SSL and micro LED array packaging. Most of the work has been presented in international conferences proceedings and peer review journals. Some of the latest work has also been submitted to well reputed international journals which are currently been reviewed for publication. .

Decapsulation Method for Flip Chips with Ceramics in Microelectronic Packaging

NASA Astrophysics Data System (ADS)

Shih, T. I.; Duh, J. G.

2008-06-01

The decapsulation of flip chips bonded to ceramic substrates is a challenging task in the packaging industry owing to the vulnerability of the chip surface during the process. In conventional methods, such as manual grinding and polishing, the solder bumps are easily damaged during the removal of underfill, and the thin chip may even be crushed due to mechanical stress. An efficient and reliable decapsulation method consisting of thermal and chemical processes was developed in this study. The surface quality of chips after solder removal is satisfactory for the existing solder rework procedure as well as for die-level failure analysis. The innovative processes included heat-sink and ceramic substrate removal, solder bump separation, and solder residue cleaning from the chip surface. In the last stage, particular temperatures were selected for the removal of eutectic Pb-Sn, high-lead, and lead-free solders considering their respective melting points.

Use of optical technique for inspection of warpage of IC packages

NASA Astrophysics Data System (ADS)

Toh, Siew-Lok; Chau, Fook S.; Ong, Sim Heng

2001-06-01

The packaging of IC packages has changed over the years, form dual-in-line, wire-bond, and pin-through-hole in printed wiring board technologies in the 1970s to ball grid array, chip scale and surface mount technologies in the 1990s. Reliability has been a big problem for manufacturers for some moisture-sensitive packages. One of the potential problems in plastic IC packages is moisture-induced popcorn effect which can arise during the reflow process. Shearography is a non-destructive inspection technique that may be used to detect the delamination and warpage of IC packages. It is non-contacting and permits a full-field observation of surface displacement derivatives. Another advantage of this technique is that it is able to give the real-time formation of the fringes which indicate flaws in the IC package under real-time simulation condition of Surface Mount Technology (SMT) IR reflow profile. It is extremely fast and convenient to study the true behavior of the packaging deformation during the SMT process. It can be concluded that shearography has the potential for the real- time detection, in situ and non-destructive inspection of IC packages during the surface mount process.

Chip-package nano-structured copper and nickel interconnections with metallic and polymeric bonding interfaces

NASA Astrophysics Data System (ADS)

Aggarwal, Ankur

With the semiconductor industry racing toward a historic transition, nano chips with less than 45 nm features demand I/Os in excess of 20,000 that support computing speed in terabits per second, with multi-core processors aggregately providing highest bandwidth at lowest power. On the other hand, emerging mixed signal systems are driving the need for 3D packaging with embedded active components and ultra-short interconnections. Decreasing I/O pitch together with low cost, high electrical performance and high reliability are the key technological challenges identified by the 2005 International Technology Roadmap for Semiconductors (ITRS). Being able to provide several fold increase in the chip-to-package vertical interconnect density is essential for garnering the true benefits of nanotechnology that will utilize nano-scale devices. Electrical interconnections are multi-functional materials that must also be able to withstand complex, sustained and cyclic thermo-mechanical loads. In addition, the materials must be environmentally-friendly, corrosion resistant, thermally stable over a long time, and resistant to electro-migration. A major challenge is also to develop economic processes that can be integrated into back end of the wafer foundry, i.e. with wafer level packaging. Device-to-system board interconnections are typically accomplished today with either wire bonding or solders. Both of these are incremental and run into either electrical or mechanical barriers as they are extended to higher density of interconnections. Downscaling traditional solder bump interconnect will not satisfy the thermo-mechanical reliability requirements at very fine pitches of the order of 30 microns and less. Alternate interconnection approaches such as compliant interconnects typically require lengthy connections and are therefore limited in terms of electrical properties, although expected to meet the mechanical requirements. A novel chip-package interconnection technology is developed to address the IC packaging requirements beyond the ITRS projections and to introduce innovative design and fabrication concepts that will further advance the performance of the chip, the package, and the system board. The nano-structured interconnect technology simultaneously packages all the ICs intact in wafer form with quantum jump in the number of interconnections with the lowest electrical parasitics. The intrinsic properties of nano materials also enable several orders of magnitude higher interconnect densities with the best mechanical properties for the highest reliability and yet provide higher current and heat transfer densities. Nano-structured interconnects provides the ability to assemble the packaged parts on the system board without the use of underfill materials and to enable advanced analog/digital testing, reliability testing, and burn-in at wafer level. This thesis investigates the electrical and mechanical performance of nanostructured interconnections through modeling and test vehicle fabrication. The analytical models evaluate the performance improvements over solder and compliant interconnections. Test vehicles with nano-interconnections were fabricated using low cost electro-deposition techniques and assembled with various bonding interfaces. Interconnections were fabricated at 200 micron pitch to compare with the existing solder joints and at 50 micron pitch to demonstrate fabrication processes at fine pitches. Experimental and modeling results show that the proposed nano-interconnections could enhance the reliability and potentially meet all the system performance requirements for the emerging micro/nano-systems.

Packaging Technologies for 500C SiC Electronics and Sensors

NASA Technical Reports Server (NTRS)

Chen, Liang-Yu

2013-01-01

Various SiC electronics and sensors are currently under development for applications in 500C high temperature environments such as hot sections of aerospace engines and the surface of Venus. In order to conduct long-term test and eventually commercialize these SiC devices, compatible packaging technologies for the SiC electronics and sensors are required. This presentation reviews packaging technologies developed for 500C SiC electronics and sensors to address both component and subsystem level packaging needs for high temperature environments. The packaging system for high temperature SiC electronics includes ceramic chip-level packages, ceramic printed circuit boards (PCBs), and edge-connectors. High temperature durable die-attach and precious metal wire-bonding are used in the chip-level packaging process. A high temperature sensor package is specifically designed to address high temperature micro-fabricated capacitive pressure sensors for high differential pressure environments. This presentation describes development of these electronics and sensor packaging technologies, including some testing results of SiC electronics and capacitive pressure sensors using these packaging technologies.

chipPCR: an R package to pre-process raw data of amplification curves.

PubMed

Rödiger, Stefan; Burdukiewicz, Michał; Schierack, Peter

2015-09-01

Both the quantitative real-time polymerase chain reaction (qPCR) and quantitative isothermal amplification (qIA) are standard methods for nucleic acid quantification. Numerous real-time read-out technologies have been developed. Despite the continuous interest in amplification-based techniques, there are only few tools for pre-processing of amplification data. However, a transparent tool for precise control of raw data is indispensable in several scenarios, for example, during the development of new instruments. chipPCR is an R: package for the pre-processing and quality analysis of raw data of amplification curves. The package takes advantage of R: 's S4 object model and offers an extensible environment. chipPCR contains tools for raw data exploration: normalization, baselining, imputation of missing values, a powerful wrapper for amplification curve smoothing and a function to detect the start and end of an amplification curve. The capabilities of the software are enhanced by the implementation of algorithms unavailable in R: , such as a 5-point stencil for derivative interpolation. Simulation tools, statistical tests, plots for data quality management, amplification efficiency/quantification cycle calculation, and datasets from qPCR and qIA experiments are part of the package. Core functionalities are integrated in GUIs (web-based and standalone shiny applications), thus streamlining analysis and report generation. http://cran.r-project.org/web/packages/chipPCR. Source code: https://github.com/michbur/chipPCR. stefan.roediger@b-tu.de Supplementary data are available at Bioinformatics online. © The Author 2015. Published by Oxford University Press. All rights reserved. For Permissions, please e-mail: journals.permissions@oup.com.

Packaging Technologies for High Temperature Electronics and Sensors

NASA Technical Reports Server (NTRS)

Chen, Liangyu; Hunter, Gary W.; Neudeck, Philip G.; Beheim, Glenn M.; Spry, David J.; Meredith, Roger D.

2013-01-01

This paper reviews ceramic substrates and thick-film metallization based packaging technologies in development for 500degC silicon carbide (SiC) electronics and sensors. Prototype high temperature ceramic chip-level packages and printed circuit boards (PCBs) based on ceramic substrates of aluminum oxide (Al2O3) and aluminum nitride (AlN) have been designed and fabricated. These ceramic substrate-based chiplevel packages with gold (Au) thick-film metallization have been electrically characterized at temperatures up to 550degC. A 96% alumina based edge connector for a PCB level subsystem interconnection has also been demonstrated recently. The 96% alumina packaging system composed of chip-level packages and PCBs has been tested with high temperature SiC devices at 500degC for over 10,000 hours. In addition to tests in a laboratory environment, a SiC JFET with a packaging system composed of a 96% alumina chip-level package and an alumina printed circuit board mounted on a data acquisition circuit board was launched as a part of the MISSE-7 suite to the International Space Station via a Shuttle mission. This packaged SiC transistor was successfully tested in orbit for eighteen months. A spark-plug type sensor package designed for high temperature SiC capacitive pressure sensors was developed. This sensor package combines the high temperature interconnection system with a commercial high temperature high pressure stainless steel seal gland (electrical feed-through). Test results of a packaged high temperature capacitive pressure sensor at 500degC are also discussed. In addition to the pressure sensor package, efforts for packaging high temperature SiC diode-based gas chemical sensors are in process.

Monolithic silicon-photonic platforms in state-of-the-art CMOS SOI processes [Invited].

PubMed

Stojanović, Vladimir; Ram, Rajeev J; Popović, Milos; Lin, Sen; Moazeni, Sajjad; Wade, Mark; Sun, Chen; Alloatti, Luca; Atabaki, Amir; Pavanello, Fabio; Mehta, Nandish; Bhargava, Pavan

2018-05-14

Integrating photonics with advanced electronics leverages transistor performance, process fidelity and package integration, to enable a new class of systems-on-a-chip for a variety of applications ranging from computing and communications to sensing and imaging. Monolithic silicon photonics is a promising solution to meet the energy efficiency, sensitivity, and cost requirements of these applications. In this review paper, we take a comprehensive view of the performance of the silicon-photonic technologies developed to date for photonic interconnect applications. We also present the latest performance and results of our "zero-change" silicon photonics platforms in 45 nm and 32 nm SOI CMOS. The results indicate that the 45 nm and 32 nm processes provide a "sweet-spot" for adding photonic capability and enhancing integrated system applications beyond the Moore-scaling, while being able to offload major communication tasks from more deeply-scaled compute and memory chips without complicated 3D integration approaches.

CE chips fabricated by injection molding and polyethylene/thermoplastic elastomer film packaging methods.

PubMed

Huang, Fu-Chun; Chen, Yih-Far; Lee, Gwo-Bin

2007-04-01

This study presents a new packaging method using a polyethylene/thermoplastic elastomer (PE/TPE) film to seal an injection-molded CE chip made of either poly(methyl methacrylate) (PMMA) or polycarbonate (PC) materials. The packaging is performed at atmospheric pressure and at room temperature, which is a fast, easy, and reliable bonding method to form a sealed CE chip for chemical analysis and biomedical applications. The fabrication of PMMA and PC microfluidic channels is accomplished by using an injection-molding process, which could be mass-produced for commercial applications. In addition to microfluidic CE channels, 3-D reservoirs for storing biosamples, and CE buffers are also formed during this injection-molding process. With this approach, a commercial CE chip can be of low cost and disposable. Finally, the functionality of the mass-produced CE chip is demonstrated through its successful separation of phiX174 DNA/HaeIII markers. Experimental data show that the S/N for the CE chips using the PE/TPE film has a value of 5.34, when utilizing DNA markers with a concentration of 2 ng/microL and a CE buffer of 2% hydroxypropyl-methylcellulose (HPMC) in Tris-borate-EDTA (TBE) with 1% YO-PRO-1 fluorescent dye. Thus, the detection limit of the developed chips is improved. Lastly, the developed CE chips are used for the separation and detection of PCR products. A mixture of an amplified antibiotic gene for Streptococcus pneumoniae and phiX174 DNA/HaeIII markers was successfully separated and detected by using the proposed CE chips. Experimental data show that these DNA samples were separated within 2 min. The study proposed a promising method for the development of mass-produced CE chips.

Thin glass based packaging and photonic single-mode waveguide integration by ion-exchange technology on board and module level

NASA Astrophysics Data System (ADS)

Brusberg, Lars; Lang, Günter; Schröder, Henning

2011-01-01

The proposed novel packaging approach merges micro-system packaging and glass integrated optics. It provides 3D optical single-mode intra system links to bridge the gap between novel photonic integrated circuits and the glass fibers for inter system interconnects. We introduce our hybrid 3D photonic packaging approach based on thin glass substrates with planar integrated optical single-mode waveguides for fiber-to-chip and chip-to-chip links. Optical mirrors and lenses provide optical mode matching for photonic IC assemblies and optical fiber interconnects. Thin glass is commercially available in panel and wafer formats and characterizes excellent optical and high-frequency properties as reviewed in the paper. That makes it perfect for micro-system packaging. The adopted planar waveguide process based on ion-exchange technology is capable for high-volume manufacturing. This ion-exchange process and the optical propagation are described in detail for thin glass substrates. An extensive characterization of all basic circuit elements like straight and curved waveguides, couplers and crosses proves the low attenuation of the optical circuit elements.

Packaging and testing of multi-wavelength DFB laser array using REC technology

NASA Astrophysics Data System (ADS)

Ni, Yi; Kong, Xuan; Gu, Xiaofeng; Chen, Xiangfei; Zheng, Guanghui; Luan, Jia

2014-02-01

Packaging of distributed feedback (DFB) laser array based on reconstruction-equivalent-chirp (REC) technology is a bridge from chip to system, and influences the practical process of REC chip. In this paper, DFB laser arrays of 4-channel @1310 nm and 8-channel @1550 nm are packaged. Our experimental results show that both these laser arrays have uniform wavelength spacing and larger than 35 dB average Side Mode Suppression Ratio (SMSR). When I=35 mA, we obtain the total output power of 1 mW for 4-channel @1310 nm, and 227 μw for 8-channel @1550 nm respectively. The high frequency characteristics of the packaged chips are also obtained, and the requirements for 4×10 G or even 8×10 G systems can be reached. Our results demonstrate the practical and low cost performance of REC technology and indicate its potential in the future fiber-to-the-home (FTTH) application.

The effects of additives to SnAgCu alloys on microstructure and drop impact reliability of solder joints

NASA Astrophysics Data System (ADS)

Liu, Weiping; Lee, Ning-Cheng

2007-07-01

The impact reliability of solder joints in electronic packages is critical to the lifetime of electronic products, especially those portable devices using area array packages such as ball-grid array (BGA) and chip-scale packages (CSP). Currently, SnAgCu (SAC) solders are most widely used for lead-free applications. However, BGA and CSP solder joints using SAC alloys are fragile and prone to premature interfacial failure, especially under shock loading. To further enhance impact reliability, a family of SAC alloys doped with a small amount of additives such as Mn, Ce, Ti, Bi, and Y was developed. The effects of doping elements on drop test performance, creep resistance, and microstructure of the solder joints were investigated, and the solder joints made with the modified alloys exhibited significantly higher impact reliability.

Chip packaging technique

NASA Technical Reports Server (NTRS)

Jayaraj, Kumaraswamy (Inventor); Noll, Thomas E. (Inventor); Lockwood, Harry F. (Inventor)

2001-01-01

A hermetically sealed package for at least one semiconductor chip is provided which is formed of a substrate having electrical interconnects thereon to which the semiconductor chips are selectively bonded, and a lid which preferably functions as a heat sink, with a hermetic seal being formed around the chips between the substrate and the heat sink. The substrate is either formed of or includes a layer of a thermoplastic material having low moisture permeability which material is preferably a liquid crystal polymer (LCP) and is a multiaxially oriented LCP material for preferred embodiments. Where the lid is a heat sink, the heat sink is formed of a material having high thermal conductivity and preferably a coefficient of thermal expansion which substantially matches that of the chip. A hermetic bond is formed between the side of each chip opposite that connected to the substrate and the heat sink. The thermal bond between the substrate and the lid/heat sink may be a pinched seal or may be provided, for example by an LCP frame which is hermetically bonded or sealed on one side to the substrate and on the other side to the lid/heat sink. The chips may operate in the RF or microwave bands with suitable interconnects on the substrate and the chips may also include optical components with optical fibers being sealed into the substrate and aligned with corresponding optical components to transmit light in at least one direction. A plurality of packages may be physically and electrically connected together in a stack to form a 3D array.

Single-mode glass waveguide technology for optical interchip communication on board level

NASA Astrophysics Data System (ADS)

Brusberg, Lars; Neitz, Marcel; Schröder, Henning

2012-01-01

The large bandwidth demand in long-distance telecom networks lead to single-mode fiber interconnects as result of low dispersion, low loss and dense wavelength multiplexing possibilities. In contrast, multi-mode interconnects are suitable for much shorter lengths up to 300 meters and are promising for optical links between racks and on board level. Active optical cables based on multi-mode fiber links are at the market and research in multi-mode waveguide integration on board level is still going on. Compared to multi-mode, a single-mode waveguide has much more integration potential because of core diameters of around 20% of a multi-mode waveguide by a much larger bandwidth. But light coupling in single-mode waveguides is much more challenging because of lower coupling tolerances. Together with the silicon photonics technology, a single-mode waveguide technology on board-level will be the straight forward development goal for chip-to-chip optical interconnects integration. Such a hybrid packaging platform providing 3D optical single-mode links bridges the gap between novel photonic integrated circuits and the glass fiber based long-distance telecom networks. Following we introduce our 3D photonic packaging approach based on thin glass substrates with planar integrated optical single-mode waveguides for fiber-to-chip and chip-to-chip interconnects. This novel packaging approach merges micro-system packaging and glass integrated optics. It consists of a thin glass substrate with planar integrated singlemode waveguide circuits, optical mirrors and lenses providing an integration platform for photonic IC assembly and optical fiber interconnect. Thin glass is commercially available in panel and wafer formats and characterizes excellent optical and high-frequency properties. That makes it perfect for microsystem packaging. The paper presents recent results in single-mode waveguide technology on wafer level and waveguide characterization. Furthermore the integration in a hybrid packaging process and design issues are discussed.

Detection of solder bump defects on a flip chip using vibration analysis

NASA Astrophysics Data System (ADS)

Liu, Junchao; Shi, Tielin; Xia, Qi; Liao, Guanglan

2012-03-01

Flip chips are widely used in microelectronics packaging owing to the high demand of integration in IC fabrication. Solder bump defects on flip chips are difficult to detect, because the solder bumps are obscured by the chip and substrate. In this paper a nondestructive detection method combining ultrasonic excitation with vibration analysis is presented for detecting missing solder bumps, which is a typical defect in flip chip packaging. The flip chip analytical model is revised by considering the influence of spring mass on mechanical energy of the system. This revised model is then applied to estimate the flip chip resonance frequencies. We use an integrated signal generator and power amplifier together with an air-coupled ultrasonic transducer to excite the flip chips. The vibrations are measured by a laser scanning vibrometer to detect the resonance frequencies. A sensitivity coefficient is proposed to select the sensitive resonance frequency order for defect detection. Finite element simulation is also implemented for further investigation. The results of analytical computation, experiment, and simulation prove the efficacy of the revised flip chip analytical model and verify the effectiveness of this detection method. Therefore, it may provide a guide for the improvement and innovation of the flip chip on-line inspection systems.

Reliability Assessment of Advanced Flip-clip Interconnect Electronic Package Assemblies under Extreme Cold Temperatures (-190 and -120 C)

NASA Technical Reports Server (NTRS)

Ramesham, Rajeshuni; Ghaffarian, Reza; Shapiro, Andrew; Napala, Phil A.; Martin, Patrick A.

2005-01-01

Flip-chip interconnect electronic package boards have been assembled, underfilled, non-destructively evaluated and subsequently subjected to extreme temperature thermal cycling to assess the reliability of this advanced packaging interconnect technology for future deep space, long-term, extreme temperature missions. In this very preliminary study, the employed temperature range covers military specifications (-55 C to 100 C), extreme cold Martian (-120 C to 115 C) and asteroid Nereus (-180 C to 25 C) environments. The resistance of daisy-chained, flip-chip interconnects were measured at room temperature and at various intervals as a function of extreme temperature thermal cycling. Electrical resistance measurements are reported and the tests to date have not shown significant change in resistance as a function of extreme temperature thermal cycling. However, the change in interconnect resistance becomes more noticeable with increasing number of thermal cycles. Further research work has been carried out to understand the reliability of flip-chip interconnect packages under extreme temperature applications (-190 C to 85 C) via continuously monitoring the daisy chain resistance. Adaptation of suitable diagnostic techniques to identify the failure mechanisms is in progress. This presentation will describe the experimental test results of flip-chip testing under extreme temperatures.

Analysis pipelines and packages for Infinium HumanMethylation450 BeadChip (450k) data

PubMed Central

Morris, Tiffany J.; Beck, Stephan

2015-01-01

The Illumina HumanMethylation450 BeadChip has become a popular platform for interrogating DNA methylation in epigenome-wide association studies (EWAS) and related projects as well as resource efforts such as the International Cancer Genome Consortium (ICGC) and the International Human Epigenome Consortium (IHEC). This has resulted in an exponential increase of 450k data in recent years and triggered the development of numerous integrated analysis pipelines and stand-alone packages. This review will introduce and discuss the currently most popular pipelines and packages and is particularly aimed at new 450k users. PMID:25233806

Fabrication of Fresnel micro lens array in borosilicate glass by F2-laser ablation for glass interposer application

NASA Astrophysics Data System (ADS)

Brusberg, Lars; Neitz, Marcel; Schröder, Henning; Fricke-Begemann, Thomas; Ihlemann, Jürgen

2014-03-01

The future need for more bandwidth forces the development of optical transmission solutions for rack-to-rack, boardto- board and chip-to-chip interconnects. The goals are significant reduction of power consumption, highest density and potential for bandwidth scalability to overcome the limitations of the systems today with mostly copper based interconnects. For system integration the enabling of thin glass as a substrate material for electro-optical components with integrated micro-optics for efficient light coupling to integrated optical waveguides or fibers is becoming important. Our glass based packaging approach merges micro-system packaging and glass integrated optics. This kind of packaging consists of a thin glass substrate with integrated micro lenses providing a platform for photonic component assembly and optical fiber or waveguide interconnection. Thin glass is commercially available in panel and wafer size and characterizes excellent optical and high frequency properties. That makes it perfect for microsystem packaging. A suitable micro lens approach has to be comparable with different commercial glasses and withstand post-processing like soldering. A benefit of using laser ablated Fresnel lenses is the planar integration capability in the substrate for highest integration density. In the paper we introduce our glass based packaging concept and the Fresnel lens design for different scenarios like chip-to-fiber, chip-to-optical-printed-circuit-board coupling. Based on the design the Fresnel lenses were fabricated by using a 157 nm fluorine laser ablation system.

Chip-Scale Architectures for Precise Optical Frequency Synthesis

NASA Astrophysics Data System (ADS)

Yang, Jinghui

Scientists and engineers have investigated various types of stable and accurate optical synthesizers, where mode-locked laser based optical frequency comb synthesizers have been widely investigated. These frequency combs bridge the frequencies from optical domain to microwave domain with orders of magnitude difference, providing a metrological tool for various platforms. The demand for highly robust, scalable, compact and cost-effective femtosecond-laser synthesizers, however, are of great importance for applications in air- or space-borne platforms, where low cost and rugged packaging are particularly required. This has been afforded in the past several years due to breakthroughs in chip-scale nanofabrication, bringing advances in optical frequency combs down to semiconductor chips. These platforms, with significantly enhanced light-matter interaction, provide a fertile sandbox for research rich in nonlinear dynamics, and offer a reliable route towards low-phase noise photonic oscillators, broadband optical frequency synthesizers, miniaturized optical clockwork, and coherent terabit communications. The dissertation explores various types of optical frequency comb synthesizers based on nonlinear microresonators. Firstly, the fundamental mechanism of mode-locking in a high-quality factor microresonator is examined, supported by ultrafast optical characterizations, analytical closed-form solutions and numerical modeling. In the evolution of these frequency microcombs, the key nonlinear dynamical effect governing the comb state coherence is rigorously analyzed. Secondly, a prototype of chip-scale optical frequency synthesizer is demonstrated, with the laser frequency comb stabilized down to instrument-limited 50-mHz RF frequency inaccuracies and 10-16 fractional frequency inaccuracies, near the fundamental limits. Thirdly, a globally stable Turing pattern is achieved and characterized in these nonlinear resonators with high-efficiency conversion, subsequently generating coherent high-power terahertz radiation via plasmonic photomixers. Finally, a new universal modality of frequency combs is discussed, including satellite states, dynamical tunability, and high efficiency conversion towards direct chip-scale optical frequency synthesis at the precision metrology frontiers.

27 CFR 19.303 - Addition of caramel to rum or brandy and addition of oak chips to spirits.

Code of Federal Regulations, 2012 CFR

2012-04-01

... or brandy and addition of oak chips to spirits. 19.303 Section 19.303 Alcohol, Tobacco Products and... rum or brandy and addition of oak chips to spirits. A proprietor may add caramel that has no material... oak chips that have not been treated with any chemical to packages of spirits prior to or after the...

27 CFR 19.303 - Addition of caramel to rum or brandy and addition of oak chips to spirits.

Code of Federal Regulations, 2014 CFR

2014-04-01

... or brandy and addition of oak chips to spirits. 19.303 Section 19.303 Alcohol, Tobacco Products and... rum or brandy and addition of oak chips to spirits. A proprietor may add caramel that has no material... oak chips that have not been treated with any chemical to packages of spirits prior to or after the...

27 CFR 19.303 - Addition of caramel to rum or brandy and addition of oak chips to spirits.

Code of Federal Regulations, 2011 CFR

2011-04-01

... or brandy and addition of oak chips to spirits. 19.303 Section 19.303 Alcohol, Tobacco Products and... rum or brandy and addition of oak chips to spirits. A proprietor may add caramel that has no material... oak chips that have not been treated with any chemical to packages of spirits prior to or after the...

27 CFR 19.303 - Addition of caramel to rum or brandy and addition of oak chips to spirits.

Code of Federal Regulations, 2013 CFR

2013-04-01

... or brandy and addition of oak chips to spirits. 19.303 Section 19.303 Alcohol, Tobacco Products and... rum or brandy and addition of oak chips to spirits. A proprietor may add caramel that has no material... oak chips that have not been treated with any chemical to packages of spirits prior to or after the...

Aeroflex Technology as Class-Y Demonstrator

NASA Technical Reports Server (NTRS)

Suh, Jong-ook; Agarwal, Shri; Popelar, Scott

2014-01-01

Modern space field programmable gate array (FPGA) devices with increased functional density and operational frequency, such as Xilinx Virtex 4 (V4) and S (V5), are packaged in non-hermetic ceramic flip chip forms. These next generation space parts were not qualified to the MIL-PRF-38535 Qualified Manufacturer Listing (QML) class-V when they were released because class-V was only intended for hermetic parts. In order to bring Xilinx V5 type packages into the QML system, it was suggested that class-Y be set up as a new category. From 2010 through 2014, a JEDEC G12 task group developed screening and qualification requirements for Class-Y products. The Document Standardization Division of the Defense Logistics Agency (DLA) has completed an engineering practice study. In parallel with the class-Y efforts, the NASA Electronic Parts and Packaging (NEPP) program has funded JPL to study potential reliability issues of the class-Y products. The major hurdle of this task was the absence of adequate research samples. Figure 1-1 shows schematic diagrams of typical structures of class-Y type products. Typically, class-Y products are either in ceramic flip chip column grid array (CGA) or land grid array (LGA) form. In class-Y packages, underfill and heat spread adhesive materials are directly exposed to the spacecraft environment due to their non-hermeticity. One of the concerns originally raised was that the underfill material could degrade due to the spacecraft environment and negatively impact the reliability of the package. In order to study such issues, it was necessary to use ceramic daisy chain flip chip package samples so that continuity of flip chip solder bumps could be monitored during the reliability tests. However, none of the commercially available class-Y daisy chain parts had electrical connections through flip chip solder bumps; only solder columns were daisy chained, which made it impossible to test continuity of flip chip solder bumps without using extremely costly functional parts. Among space parts manufacturers who were interested in producing class-Y products, Aeroflex Microelectronic Solutions-HiRel had been developing assembly processes using their internal R&D classy type samples. In early 2012, JPL and Aeroflex initiated a collaboration to study reliability of the Aeroflex technology as a class-Y demonstrator.

Advanced Packaging Technology Used in Fabricating a High-Temperature Silicon Carbide Pressure Sensor

NASA Technical Reports Server (NTRS)

Beheim, Glenn M.

2003-01-01

The development of new aircraft engines requires the measurement of pressures in hot areas such as the combustor and the final stages of the compressor. The needs of the aircraft engine industry are not fully met by commercially available high-temperature pressure sensors, which are fabricated using silicon. Kulite Semiconductor Products and the NASA Glenn Research Center have been working together to develop silicon carbide (SiC) pressure sensors for use at high temperatures. At temperatures above 850 F, silicon begins to lose its nearly ideal elastic properties, so the output of a silicon pressure sensor will drift. SiC, however, maintains its nearly ideal mechanical properties to extremely high temperatures. Given a suitable sensor material, a key to the development of a practical high-temperature pressure sensor is the package. A SiC pressure sensor capable of operating at 930 F was fabricated using a newly developed package. The durability of this sensor was demonstrated in an on-engine test. The SiC pressure sensor uses a SiC diaphragm, which is fabricated using deep reactive ion etching. SiC strain gauges on the surface of the diaphragm sense the pressure difference across the diaphragm. Conventionally, the SiC chip is mounted to the package with the strain gauges outward, which exposes the sensitive metal contacts on the chip to the hostile measurement environment. In the new Kulite leadless package, the SiC chip is flipped over so that the metal contacts are protected from oxidation by a hermetic seal around the perimeter of the chip. In the leadless package, a conductive glass provides the electrical connection between the pins of the package and the chip, which eliminates the fragile gold wires used previously. The durability of the leadless SiC pressure sensor was demonstrated when two 930 F sensors were tested in the combustor of a Pratt & Whitney PW4000 series engine. Since the gas temperatures in these locations reach 1200 to 1300 F, the sensors were installed in water-cooled jackets, as shown. This was a severe test because the pressure-sensing chips were exposed to the hot combustion gases. Prior to the installation of the SiC pressure sensors, two high-temperature silicon sensors, installed in the same locations, did not survive a single engine run. The durability of the leadless SiC pressure sensor was demonstrated when both SiC sensors operated properly throughout the two runs that were conducted.

Automated platform for determination of LEDs spatial radiation pattern

NASA Astrophysics Data System (ADS)

Vladescu, Marian; Vuza, Dan Tudor

2015-02-01

Nowadays technologies lead to remarkable properties of the light-emitting diodes (LEDs), making them attractive for more and more applications, such as: interior and exterior lighting, outdoor LED panels, traffic signals, automotive (tail and brake lights, backlighting in dashboard and switches), backlighting of display panels, LCD displays, symbols on switches, keyboards, graphic boards and measuring scales. Usually, LEDs are small light sources consisting of a chip placed into a package, which may bring additional optics to this encapsulated ensemble, resulting in a less or more complex spatial distribution of the light intensity, with particular radiation patterns. This paper presents an automated platform designed to allow a quick and accurate determination of the spatial radiation patterns of LEDs encapsulated in various packages. Keywords: LED, luminous

Lithographic chip identification: meeting the failure analysis challenge

NASA Astrophysics Data System (ADS)

Perkins, Lynn; Riddell, Kevin G.; Flack, Warren W.

1992-06-01

This paper describes a novel method using stepper photolithography to uniquely identify individual chips for permanent traceability. A commercially available 1X stepper is used to mark chips with an identifier or `serial number' which can be encoded with relevant information for the integrated circuit manufacturer. The permanent identification of individual chips can improve current methods of quality control, failure analysis, and inventory control. The need for this technology is escalating as manufacturers seek to provide six sigma quality control for their products and trace fabrication problems to their source. This need is especially acute for parts that fail after packaging and are returned to the manufacturer for analysis. Using this novel approach, failure analysis data can be tied back to a particular batch, wafer, or even a position within a wafer. Process control can be enhanced by identifying the root cause of chip failures. Chip identification also addresses manufacturers concerns with increasing incidences of chip theft. Since chips currently carry no identification other than the manufacturer's name and part number, recovery efforts are hampered by the inability to determine the sales history of a specific packaged chip. A definitive identifier or serial number for each chip would address this concern. The results of chip identification (patent pending) are easily viewed through a low power microscope. Batch number, wafer number, exposure step, and chip location within the exposure step can be recorded, as can dates and other items of interest. An explanation of the chip identification procedure and processing requirements are described. Experimental testing and results are presented, and potential applications are discussed.

VLSI research

NASA Astrophysics Data System (ADS)

Brodersen, R. W.

1984-04-01

A scaled version of the RISC II chip has been fabricated and tested and these new chips have a cycle time that would outperform a VAX 11/780 by about a factor of two on compiled integer C programs. The architectural work on a RISC chip designed for a Smalltalk implementation has been completed. This chip, called SOAR (Smalltalk On a RISC), should run program s4-15 times faster than the Xerox 1100 (Dolphin), a TTL minicomputer, and about as fast as the Xerox 1132 (Dorado), a $100,000 ECL minicomputer. The 1983 VLSI tools tape has been converted for use under the latest UNIX release (4.2). The Magic (formerly called Caddy) layout system will be a unified set of highly automated tools that cover all aspects of the layout process, including stretching, compaction, tiling and routing. A multiple window package and design rule checker for this system have just been completed and compaction and stretching are partially implemented. New slope-based timing models for the Crystal timing analyzer are now fully implemented and in regular use. In an accuracy test using a dozen critical paths from the RISC II processor and cache chips it was found that Crystal's estimates were within 5-10% of SPICE's estimates, while being a factor of 10,000 times faster.

RELIC: a novel dye-bias correction method for Illumina Methylation BeadChip.

PubMed

Xu, Zongli; Langie, Sabine A S; De Boever, Patrick; Taylor, Jack A; Niu, Liang

2017-01-03

The Illumina Infinium HumanMethylation450 BeadChip and its successor, Infinium MethylationEPIC BeadChip, have been extensively utilized in epigenome-wide association studies. Both arrays use two fluorescent dyes (Cy3-green/Cy5-red) to measure methylation level at CpG sites. However, performance difference between dyes can result in biased estimates of methylation levels. Here we describe a novel method, called REgression on Logarithm of Internal Control probes (RELIC) to correct for dye bias on whole array by utilizing the intensity values of paired internal control probes that monitor the two color channels. We evaluate the method in several datasets against other widely used dye-bias correction methods. Results on data quality improvement showed that RELIC correction statistically significantly outperforms alternative dye-bias correction methods. We incorporated the method into the R package ENmix, which is freely available from the Bioconductor website ( https://www.bioconductor.org/packages/release/bioc/html/ENmix.html ). RELIC is an efficient and robust method to correct for dye-bias in Illumina Methylation BeadChip data. It outperforms other alternative methods and conveniently implemented in R package ENmix to facilitate DNA methylation studies.

A Time-Domain CMOS Oscillator-Based Thermostat with Digital Set-Point Programming

PubMed Central

Chen, Chun-Chi; Lin, Shih-Hao

2013-01-01

This paper presents a time-domain CMOS oscillator-based thermostat with digital set-point programming [without a digital-to-analog converter (DAC) or external resistor] to achieve on-chip thermal management of modern VLSI systems. A time-domain delay-line-based thermostat with multiplexers (MUXs) was used to substantially reduce the power consumption and chip size, and can benefit from the performance enhancement due to the scaling down of fabrication processes. For further cost reduction and accuracy enhancement, this paper proposes a thermostat using two oscillators that are suitable for time-domain curvature compensation instead of longer linear delay lines. The final time comparison was achieved using a time comparator with a built-in custom hysteresis to generate the corresponding temperature alarm and control. The chip size of the circuit was reduced to 0.12 mm2 in a 0.35-μm TSMC CMOS process. The thermostat operates from 0 to 90 °C, and achieved a fine resolution better than 0.05 °C and an improved inaccuracy of ± 0.6 °C after two-point calibration for eight packaged chips. The power consumption was 30 μW at a sample rate of 10 samples/s. PMID:23385403

Development of Equivalent Material Properties of Microbump for Simulating Chip Stacking Packaging

PubMed Central

Lee, Chang-Chun; Tzeng, Tzai-Liang; Huang, Pei-Chen

2015-01-01

A three-dimensional integrated circuit (3D-IC) structure with a significant scale mismatch causes difficulty in analytic model construction. This paper proposes a simulation technique to introduce an equivalent material composed of microbumps and their surrounding wafer level underfill (WLUF). The mechanical properties of this equivalent material, including Young’s modulus (E), Poisson’s ratio, shear modulus, and coefficient of thermal expansion (CTE), are directly obtained by applying either a tensile load or a constant displacement, and by increasing the temperature during simulations, respectively. Analytic results indicate that at least eight microbumps at the outermost region of the chip stacking structure need to be considered as an accurate stress/strain contour in the concerned region. In addition, a factorial experimental design with analysis of variance is proposed to optimize chip stacking structure reliability with four factors: chip thickness, substrate thickness, CTE, and E-value. Analytic results show that the most significant factor is CTE of WLUF. This factor affects microbump reliability and structural warpage under a temperature cycling load and high-temperature bonding process. WLUF with low CTE and high E-value are recommended to enhance the assembly reliability of the 3D-IC architecture. PMID:28793495

Silicon photonics: some remaining challenges

NASA Astrophysics Data System (ADS)

Reed, G. T.; Topley, R.; Khokhar, A. Z.; Thompson, D. J.; Stanković, S.; Reynolds, S.; Chen, X.; Soper, N.; Mitchell, C. J.; Hu, Y.; Shen, L.; Martinez-Jimenez, G.; Healy, N.; Mailis, S.; Peacock, A. C.; Nedeljkovic, M.; Gardes, F. Y.; Soler Penades, J.; Alonso-Ramos, C.; Ortega-Monux, A.; Wanguemert-Perez, G.; Molina-Fernandez, I.; Cheben, P.; Mashanovich, G. Z.

2016-03-01

This paper discusses some of the remaining challenges for silicon photonics, and how we at Southampton University have approached some of them. Despite phenomenal advances in the field of Silicon Photonics, there are a number of areas that still require development. For short to medium reach applications, there is a need to improve the power consumption of photonic circuits such that inter-chip, and perhaps intra-chip applications are viable. This means that yet smaller devices are required as well as thermally stable devices, and multiple wavelength channels. In turn this demands smaller, more efficient modulators, athermal circuits, and improved wavelength division multiplexers. The debate continues as to whether on-chip lasers are necessary for all applications, but an efficient low cost laser would benefit many applications. Multi-layer photonics offers the possibility of increasing the complexity and effectiveness of a given area of chip real estate, but it is a demanding challenge. Low cost packaging (in particular, passive alignment of fibre to waveguide), and effective wafer scale testing strategies, are also essential for mass market applications. Whilst solutions to these challenges would enhance most applications, a derivative technology is emerging, that of Mid Infra-Red (MIR) silicon photonics. This field will build on existing developments, but will require key enhancements to facilitate functionality at longer wavelengths. In common with mainstream silicon photonics, significant developments have been made, but there is still much left to do. Here we summarise some of our recent work towards wafer scale testing, passive alignment, multiplexing, and MIR silicon photonics technology.

Analysis pipelines and packages for Infinium HumanMethylation450 BeadChip (450k) data.

PubMed

Morris, Tiffany J; Beck, Stephan

2015-01-15

The Illumina HumanMethylation450 BeadChip has become a popular platform for interrogating DNA methylation in epigenome-wide association studies (EWAS) and related projects as well as resource efforts such as the International Cancer Genome Consortium (ICGC) and the International Human Epigenome Consortium (IHEC). This has resulted in an exponential increase of 450k data in recent years and triggered the development of numerous integrated analysis pipelines and stand-alone packages. This review will introduce and discuss the currently most popular pipelines and packages and is particularly aimed at new 450k users. Copyright © 2014 The Authors. Published by Elsevier Inc. All rights reserved.

High Temperature Pt/Alumina Co-Fired System for 500 C Electronic Packaging Applications

NASA Technical Reports Server (NTRS)

Chen, Liang-Yu; Neudeck, Philip G.; Spry, David J.; Beheim, Glenn M.; Hunter, Gary W.

2015-01-01

Gold thick-film metallization and 96 alumina substrate based prototype packaging system developed for 500C SiC electronics and sensors is briefly reviewed, the needs of improvement are discussed. A high temperature co-fired alumina material system based packaging system composed of 32-pin chip-level package and printed circuit board is discussed for packaging 500C SiC electronics and sensors.

Contamination control in hybrid microelectronic modules. Part 2: Selection and evaluation of coating materials

NASA Technical Reports Server (NTRS)

Himmel, R. P.

1975-01-01

The selection, test, and evaluation of organic coating materials for contamination control in hybrid circuits is reported. The coatings were evaluated to determine their suitability for use as a conformal coating over the hybrid microcircuit (including chips and wire bonds) inside a hermetically sealed package. Evaluations included ease of coating application and repair and effect on thin film and thick film resistors, beam leads, wire bonds, transistor chips, and capacitor chips. The coatings were also tested for such properties as insulation resistance, voltage breakdown strength, and capability of immobilizing loose particles inside the packages. The selected coatings were found to be electrically, mechanically, and chemically compatible with all components and materials normally used in hybrid microcircuits.

Light emitting diode package element with internal meniscus for bubble free lens placement

DOEpatents

Tarsa, Eric; Yuan, Thomas C.; Becerra, Maryanne; Yadev, Praveen

2010-09-28

A method for fabricating a light emitting diode (LED) package comprising providing an LED chip and covering at least part of the LED chip with a liquid encapsulant having a radius of curvature. An optical element is provided having a bottom surface with at least a portion having a radius of curvature larger than the liquid encapsulant. The larger radius of curvature portion of the optical element is brought into contact with the liquid encapsulant. The optical element is then moved closer to the LED chip, growing the contact area between said optical element and said liquid encapsulant. The liquid encapsulant is then cured. A light emitting diode comprising a substrate with an LED chip mounted to it. A meniscus ring is on the substrate around the LED chip with the meniscus ring having a meniscus holding feature. An inner encapsulant is provided over the LED chip with the inner encapsulant having a contacting surface on the substrate, with the meniscus holding feature which defines the edge of the contacting surface. An optical element is included having a bottom surface with at least a portion that is concave. The optical element is arranged on the substrate with the concave portion over the LED chip. A contacting encapsulant is included between the inner encapsulant and optical element.

75 FR 447 - In the Matter of Certain Semiconductor Chips With Minimized Chip Package Size and Products...

Federal Register 2010, 2011, 2012, 2013, 2014

2010-01-05

... review (1) the finding that the claim term ``top layer'' recited in claim 1 of the '106 patent means ``an outer layer of the chip assembly upon which the terminals are fixed,'' the requirement that ``the `top layer' is a single layer,'' and the effect of the findings on the infringement analysis, invalidity...

A 50Mbit/Sec. CMOS Video Linestore System

NASA Astrophysics Data System (ADS)

Jeung, Yeun C.

1988-10-01

This paper reports the architecture, design and test results of a CMOS single chip programmable video linestore system which has 16-bit data words with 1024 bit depth. The delay is fully programmable from 9 to 1033 samples by a 10 bit binary control word. The large 16 bit data word width makes the chip useful for a wide variety of digital video signal processing applications such as DPCM coding, High-Definition TV, and Video scramblers/descramblers etc. For those applications, the conventional large fixed-length shift register or static RAM scheme is not very popular because of its lack of versatility, high power consumption, and required support circuitry. The very high throughput of 50Mbit/sec is made possible by a highly parallel, pipelined dynamic memory architecture implemented in a 2-um N-well CMOS technology. The basic cell of the programmable video linestore chip is an four transistor dynamic RAM element. This cell comprises the majority of the chip's real estate, consumes no static power, and gives good noise immunity to the simply designed sense amplifier. The chip design was done using Bellcore's version of the MULGA virtual grid symbolic layout system. The chip contains approximately 90,000 transistors in an area of 6.5 x 7.5 square mm and the I/Os are TTL compatible. The chip is packaged in a 68-pin leadless ceramic chip carrier package.

An architecture for integrating planar and 3D cQED devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Axline, C.; Reagor, M.; Heeres, R.

Numerous loss mechanisms can limit coherence and scalability of planar and 3D-based circuit quantum electrodynamics (cQED) devices, particularly due to their packaging. The low loss and natural isolation of 3D enclosures make them good candidates for coherent scaling. We introduce a coaxial transmission line device architecture with coherence similar to traditional 3D cQED systems. Measurements demonstrate well-controlled external and on-chip couplings, a spectrum absent of cross-talk or spurious modes, and excellent resonator and qubit lifetimes. We integrate a resonator-qubit system in this architecture with a seamless 3D cavity, and separately pattern a qubit, readout resonator, Purcell filter, and high-Q striplinemore » resonator on a single chip. Device coherence and its ease of integration make this a promising tool for complex experiments.« less

Miniature stick-packaging--an industrial technology for pre-storage and release of reagents in lab-on-a-chip systems.

PubMed

van Oordt, Thomas; Barb, Yannick; Smetana, Jan; Zengerle, Roland; von Stetten, Felix

2013-08-07

Stick-packaging of goods in tubular-shaped composite-foil pouches has become a popular technology for food and drug packaging. We miniaturized stick-packaging for use in lab-on-a-chip (LOAC) systems to pre-store and on-demand release the liquid and dry reagents in a volume range of 80-500 μl. An integrated frangible seal enables the pressure-controlled release of reagents and simplifies the layout of LOAC systems, thereby making the package a functional microfluidic release unit. The frangible seal is adjusted to defined burst pressures ranging from 20 to 140 kPa. The applied ultrasonic welding process allows the packaging of temperature sensitive reagents. Stick-packs have been successfully tested applying recovery tests (where 99% (STDV = 1%) of 250 μl pre-stored liquid is released), long-term storage tests (where there is loss of only <0.5% for simulated 2 years) and air transport simulation tests. The developed technology enables the storage of a combination of liquid and dry reagents. It is a scalable technology suitable for rapid prototyping and low-cost mass production.

Heterogeneously integrated microsystem-on-a-chip

DOEpatents

Chanchani, Rajen [Albuquerque, NM

2008-02-26

A microsystem-on-a-chip comprises a bottom wafer of normal thickness and a series of thinned wafers can be stacked on the bottom wafer, glued and electrically interconnected. The interconnection layer comprises a compliant dielectric material, an interconnect structure, and can include embedded passives. The stacked wafer technology provides a heterogeneously integrated, ultra-miniaturized, higher performing, robust and cost-effective microsystem package. The highly integrated microsystem package, comprising electronics, sensors, optics, and MEMS, can be miniaturized both in volume and footprint to the size of a bottle-cap or less.

Cleanup Verification Package for the 118-F-1 Burial Ground

DOE Office of Scientific and Technical Information (OSTI.GOV)

E. J. Farris and H. M. Sulloway

2008-01-10

This cleanup verification package documents completion of remedial action for the 118-F-1 Burial Ground on the Hanford Site. This burial ground is a combination of two locations formerly called Minor Construction Burial Ground No. 2 and Solid Waste Burial Ground No. 2. This waste site received radioactive equipment and other miscellaneous waste from 105-F Reactor operations, including dummy elements and irradiated process tubing; gun barrel tips, steel sleeves, and metal chips removed from the reactor; filter boxes containing reactor graphite chips; and miscellaneous construction solid waste.

Intelligent structures technology

NASA Astrophysics Data System (ADS)

Crawley, Edward F.

1991-07-01

Viewgraphs on intelligent structures technology are presented. Topics covered include: embedding electronics; electrical and mechanical compatibility; integrated circuit chip packaged for embedding; embedding devices within composite structures; test of embedded circuit in G/E coupon; temperature/humidity/bias test; single-chip microcomputer control experiment; and structural shape determination.

Intelligent structures technology

NASA Technical Reports Server (NTRS)

Crawley, Edward F.

1991-01-01

Viewgraphs on intelligent structures technology are presented. Topics covered include: embedding electronics; electrical and mechanical compatibility; integrated circuit chip packaged for embedding; embedding devices within composite structures; test of embedded circuit in G/E coupon; temperature/humidity/bias test; single-chip microcomputer control experiment; and structural shape determination.

Influence of different materials on the thermal behavior of a CDIP-8 ceramic package

NASA Astrophysics Data System (ADS)

Weide, Kirsten; Keck, Christian

1999-08-01

The temperature distribution inside a package is determined by the heat transfer from the package to the ambient, depending on the heat conductivities of the different used materials. With the help of finite element simulations the thermal behavior of the package can be characterized. In precise simulations convection and radiation effects have to be taken into account. In this paper the influence of different materials like the ceramic, the pin and die attach material and adhesive material between the chip and the die attach on the thermal resistance of the ceramic package will be investigated. A finite element model of the ceramic package including a voltage regulator on the chip was created. The simulations were carried out with the finite element program ANSYS. An easy way to take the radiation effect into account, which normally is difficult to handle in the simulation, will be shown. The results of the simulations are verified by infrared measurements. A comparison of the thermal resistance between the best case and worst case for different package materials was done. The thermal conductivity of the ceramic material shows the strongest influence on the thermal resistance.

High-performance packaging for monolithic microwave and millimeter-wave integrated circuits

NASA Technical Reports Server (NTRS)

Shalkhauser, K. A.; Li, K.; Shih, Y. C.

1992-01-01

Packaging schemes are developed that provide low-loss, hermetic enclosure for enhanced monolithic microwave and millimeter-wave integrated circuits. These package schemes are based on a fused quartz substrate material offering improved RF performance through 44 GHz. The small size and weight of the packages make them useful for a number of applications, including phased array antenna systems. As part of the packaging effort, a test fixture was developed to interface the single chip packages to conventional laboratory instrumentation for characterization of the packaged devices.

Ceramic ball grid array package stress analysis

NASA Astrophysics Data System (ADS)

Badri, S. H. B. S.; Aziz, M. H. A.; Ong, N. R.; Sauli, Z.; Alcain, J. B.; Retnasamy, V.

2017-09-01

The ball grid array (BGA), a form of chip scale package (CSP), was developed as one of the most advanced surface mount devices, which may be assembled by an ordinary surface ball bumps are used instead of plated nickel and gold (Ni/Au) bumps. Assembly and reliability of the BGA's printed circuit board (PCB), which is soldered by conventional surface mount technology is considered in this study. The Ceramic Ball Grid Array (CBGA) is a rectangular ceramic package or square-shaped that will use the solder ball for external electrical connections instead of leads or wire for connections. The solder balls will be arranged in an array or grid at the bottom of the ceramic package body. In this study, ANSYS software is used to investigate the stress on the package for 2 balls and 4 balls of the CBGA package with the various force range of 1-3 Newton applied to the top of the die, top of the substrate and side of the substrate. The highest maximum stress was analyzed and the maximum equivalent stress was observed on the solder ball and the die. From the simulation result, the CBGA package with less solder balls experience higher stress compared to the package with many solder balls. Therefore, less number of solder ball on the CBGA package results higher stress and critically affect the reliability of the solder balls itself, substrate and die which can lead to the solder crack and also die crack.

Hybrid macro-micro fluidics system for a chip-based biosensor

NASA Astrophysics Data System (ADS)

Tamanaha, C. R.; Whitman, L. J.; Colton, R. J.

2002-03-01

We describe the engineering of a hybrid fluidics platform for a chip-based biosensor system that combines high-performance microfluidics components with powerful, yet compact, millimeter-scale pump and valve actuators. The microfluidics system includes channels, valveless diffuser-based pumps, and pinch-valves that are cast into a poly(dimethylsiloxane) (PDMS) membrane and packaged along with the sensor chip into a palm-sized plastic cartridge. The microfluidics are driven by pump and valve actuators contained in an external unit (with a volume ~30 cm3) that interfaces kinematically with the PDMS microelements on the cartridge. The pump actuator is a simple-lever, flexure-hinge displacement amplifier that increases the motion of a piezoelectric stack. The valve actuators are an array of cantilevers operated by shape memory alloy wires. All components can be fabricated without the need for complex lithography or micromachining, and can be used with fluids containing micron-sized particulates. Prototypes have been modeled and tested to ensure the delivery of microliter volumes of fluid and the even dispersion of reagents over the chip sensing elements. With this hybrid approach to the fluidics system, the biochemical assay benefits from the many advantages of microfluidics yet we avoid the complexity and unknown reliability of immature microactuator technologies.

ChAMP: updated methylation analysis pipeline for Illumina BeadChips.

PubMed

Tian, Yuan; Morris, Tiffany J; Webster, Amy P; Yang, Zhen; Beck, Stephan; Feber, Andrew; Teschendorff, Andrew E

2017-12-15

The Illumina Infinium HumanMethylationEPIC BeadChip is the new platform for high-throughput DNA methylation analysis, effectively doubling the coverage compared to the older 450 K array. Here we present a significantly updated and improved version of the Bioconductor package ChAMP, which can be used to analyze EPIC and 450k data. Many enhanced functionalities have been added, including correction for cell-type heterogeneity, network analysis and a series of interactive graphical user interfaces. ChAMP is a BioC package available from https://bioconductor.org/packages/release/bioc/html/ChAMP.html. a.teschendorff@ucl.ac.uk or s.beck@ucl.ac.uk or a.feber@ucl.ac.uk. Supplementary data are available at Bioinformatics online. © The Author(s) 2017. Published by Oxford University Press.

Polarity effect of electromigration on mechanical properties of lead-free solder joints

NASA Astrophysics Data System (ADS)

Ren, Fei

The trend of electronic packaging is to package the chips and the associated interconnections in a compact way that allows high speed operation; that allows for sufficient heat removal; that can withstand the thermal cycling associated with the turning on and turning off of the circuits; and that protects the circuits from environmental attack. These goals require that flip chip solder joints have higher resistance to electromigration, stronger mechanical property to sustain thermal mechanical stress, and are lead-free materials to satisfy environment and health concern. With lots of work on chemical reaction, electromigration and mechanical study in flip chip solder joints, however, the interaction between different driving forces is still little known. As a matter of fact, the combination study of chemical, electrical and mechanical is more and more significant to the understanding of the behavior of flip chip solder joints. In this dissertation, I developed one dimensional Cu (wire)-eutectic SnAgCu(ball)-Cu(wire) structure to investigate the interaction between electrical and mechanical force in lead-free solder joints. Electromigration was first conducted. The mechanical behaviors of solder joints before, after, and during electromigration were examined. Electrical current and mechanical stress were applied either in serial or in parallel to the solder joints. Tensile, creep, and drop tests, combined with different electrical current densities (1˜5x10 3A/cm2) and different stressing time (3˜144 hours), have been performed to study the effect of electromigration on the mechanical behavior of solder joints. Nano-indentation test was conducted to study the localized mechanical property of IMC at both interfaces in nanometer scale. Fracture images help analyze the failure mechanism of solder joints driven by both electrical and mechanical forces. The combination study shows a strain build-up during electromigration. Furthermore, a ductile-to-brittle transition in flip chip solder joints induced by electromigration is observed, in which the fracture position migrates from the middle to the cathode interface of the joint with increasing current density and time. The transition is explained by the polarity effect of electromigration, particular due to the accumulation of vacancies at the cathode interface.

NSC 800, 8-bit CMOS microprocessor

NASA Technical Reports Server (NTRS)

Suszko, S. F.

1984-01-01

The NSC 800 is an 8-bit CMOS microprocessor manufactured by National Semiconductor Corp., Santa Clara, California. The 8-bit microprocessor chip with 40-pad pin-terminals has eight address buffers (A8-A15), eight data address -- I/O buffers (AD(sub 0)-AD(sub 7)), six interrupt controls and sixteen timing controls with a chip clock generator and an 8-bit dynamic RAM refresh circuit. The 22 internal registers have the capability of addressing 64K bytes of memory and 256 I/O devices. The chip is fabricated on N-type (100) silicon using self-aligned polysilicon gates and local oxidation process technology. The chip interconnect consists of four levels: Aluminum, Polysi 2, Polysi 1, and P(+) and N(+) diffusions. The four levels, except for contact interface, are isolated by interlevel oxide. The chip is packaged in a 40-pin dual-in-line (DIP), side brazed, hermetically sealed, ceramic package with a metal lid. The operating voltage for the device is 5 V. It is available in three operating temperature ranges: 0 to +70 C, -40 to +85 C, and -55 to +125 C. Two devices were submitted for product evaluation by F. Stott, MTS, JPL Microprocessor Specialist. The devices were pencil-marked and photographed for identification.

Chip-on-Board Technology 1996 Year-end Report (Design, Manufacturing, and Reliability Study)

NASA Technical Reports Server (NTRS)

Le, Binh Q.; Nhan, Elbert; Maurer, Richard H.; Lew, Ark L.; Lander, Juan R.

1996-01-01

The major impetus for flight qualifying Chip-On-Board (COB) packaging technology is the shift in emphasis for space missions to smaller, better, and cheaper spacecraft and satellites resulting from the NASA New Millenium initiative and similar requirements in DoD-sponsored programs. The most important benefit that can potentially be derived from miniaturizing spacecraft and satellites is the significant cost saving realizable if a smaller launch vehicle may be employed. Besides the program cost saving, there are several other advantages to building COB-based space hardware. First, once a well-controlled process is established, COB can be low cost compared to standard Multi-Chip Module (MCM) technology. This cost competitiveness is regarded as a result of the generally greater availability and lower cost of Known Good Die (KGD). Coupled with the elimination of the first level of packaging (chip package), compact, high-density circuit boards can be realized with Printed Wiring Boards (PWB) that can now be made with ever-decreasing feature size in line width and via hole. Since the COB packaging technique in this study is based mainly on populating bare dice on a suitable multi-layer laminate substrate which is not hermetically sealed, die coating for protection from the environment is required. In recent years, significant improvements have been made in die coating materials which further enhance the appeal of COB. Hysol epoxies, silicone, parylene and silicon nitride are desirable because of their compatible Thermal Coefficient of Expansion (TCE) and good moisture resistant capability. These die coating materials have all been used in the space and other industries with varying degrees of success. COB technology, specifically siliconnitride coated hardware, has been flown by Lockheed on the Polar satellite. In addition, DARPA has invested a substantial amount of resources on MCM and COB-related activities recently. With COB on the verge of becoming a dominant player in DoD programs, DARPA is increasing its support of the availability of KGDs which will help decrease their cost. Aside from the various major developments and trends in the space and defense industries that are favorable to the acceptance and widespread use of'COB packaging technology, implementing COB can be appealing in other aspects. Since the interconnection interface is usually the weak link in a system, the overall circuit or system reliability may actually be improved because of the elimination of a level of interconnect/packaging at the chip. With COB, mixing packaging technologies is possible. Because some devices are only available in commercial plastic packages, populating a multi-layer laminate substrate with both bare dice and plastic-package parts is inevitable. Another attractive feature of COB is that re-workability is possible if die coating is applied only on the die top. This method allows local replacement of individual dice that were found to be defective instead of replacing an entire board. In terms of thermal management, unpackaged devices offer a shorter thermal resistance path than their packaged counterparts thereby improving thermal sinking and heat removal from the parts.

Innovative on-chip packaging applied to uncooled IRFPA

NASA Astrophysics Data System (ADS)

Dumont, Geoffroy; Arnaud, Agnès; Impérinetti, Pierre; Vialle, Claire; Rabaud, Wilfried; Goudon, Valérie; Yon, Jean-Jacques

2008-04-01

The Laboratoire Infrarouge (LIR) of the Laboratoire d'Electronique et de Technologie de l'Information (LETI) has been involved in the development of microbolometers for over fifteen years. Two generations of technology have been transferred to ULIS and LETI is still working to improve performances of low cost detectors. Simultaneously, packaging still represents a significant part of detectors price. Reducing production costs would contribute to keep on extending applications of uncooled IRFPA to high volume markets like automotive. Therefore LETI is developing an on-chip packaging technology dedicated to microbolometers. This paper presents an original microcap structure that enables the use of IR window materials as sealing layers to maintain the expected vacuum level. The modelling and integration of an IR window suitable for this structure is also presented. This monolithic packaging technology is performed in a standard collective way, in continuation of bolometers' technology. The CEA-LETI, MINATEC presents status of these developments concerning this innovating technology including optical simulations results and SEM views of technical realizations.

Alumina Based 500 C Electronic Packaging Systems and Future Development

NASA Technical Reports Server (NTRS)

Chen, Liang-Yu

2012-01-01

NASA space and aeronautical missions for probing the inner solar planets as well as for in situ monitoring and control of next-generation aeronautical engines require high-temperature environment operable sensors and electronics. A 96% aluminum oxide and Au thick-film metallization based packaging system including chip-level packages, printed circuit board, and edge-connector is in development for high temperature SiC electronics. An electronic packaging system based on this material system was successfully tested and demonstrated with SiC electronics at 500 C for over 10,000 hours in laboratory conditions previously. In addition to the tests in laboratory environments, this packaging system has more recently been tested with a SiC junction field effect transistor (JFET) on low earth orbit through the NASA Materials on the International Space Station Experiment 7 (MISSE7). A SiC JFET with a packaging system composed of a 96% alumina chip-level package and an alumina printed circuit board mounted on a data acquisition circuit board was launched as a part of the MISSE7 suite to International Space Station via a Shuttle mission and tested on the orbit for eighteen months. A summary of results of tests in both laboratory and space environments will be presented. The future development of alumina based high temperature packaging using co-fired material systems for improved performance at high temperature and more feasible mass production will also be discussed.

Standard semiconductor packaging for high-reliability low-cost MEMS applications

NASA Astrophysics Data System (ADS)

Harney, Kieran P.

2005-01-01

Microelectronic packaging technology has evolved over the years in response to the needs of IC technology. The fundamental purpose of the package is to provide protection for the silicon chip and to provide electrical connection to the circuit board. Major change has been witnessed in packaging and today wafer level packaging technology has further revolutionized the industry. MEMS (Micro Electro Mechanical Systems) technology has created new challenges for packaging that do not exist in standard ICs. However, the fundamental objective of MEMS packaging is the same as traditional ICs, the low cost and reliable presentation of the MEMS chip to the next level interconnect. Inertial MEMS is one of the best examples of the successful commercialization of MEMS technology. The adoption of MEMS accelerometers for automotive airbag applications has created a high volume market that demands the highest reliability at low cost. The suppliers to these markets have responded by exploiting standard semiconductor packaging infrastructures. However, there are special packaging needs for MEMS that cannot be ignored. New applications for inertial MEMS devices are emerging in the consumer space that adds the imperative of small size to the need for reliability and low cost. These trends are not unique to MEMS accelerometers. For any MEMS technology to be successful the packaging must provide the basic reliability and interconnection functions, adding the least possible cost to the product. This paper will discuss the evolution of MEMS packaging in the accelerometer industry and identify the main issues that needed to be addressed to enable the successful commercialization of the technology in the automotive and consumer markets.

Standard semiconductor packaging for high-reliability low-cost MEMS applications

NASA Astrophysics Data System (ADS)

Harney, Kieran P.

2004-12-01

Microelectronic packaging technology has evolved over the years in response to the needs of IC technology. The fundamental purpose of the package is to provide protection for the silicon chip and to provide electrical connection to the circuit board. Major change has been witnessed in packaging and today wafer level packaging technology has further revolutionized the industry. MEMS (Micro Electro Mechanical Systems) technology has created new challenges for packaging that do not exist in standard ICs. However, the fundamental objective of MEMS packaging is the same as traditional ICs, the low cost and reliable presentation of the MEMS chip to the next level interconnect. Inertial MEMS is one of the best examples of the successful commercialization of MEMS technology. The adoption of MEMS accelerometers for automotive airbag applications has created a high volume market that demands the highest reliability at low cost. The suppliers to these markets have responded by exploiting standard semiconductor packaging infrastructures. However, there are special packaging needs for MEMS that cannot be ignored. New applications for inertial MEMS devices are emerging in the consumer space that adds the imperative of small size to the need for reliability and low cost. These trends are not unique to MEMS accelerometers. For any MEMS technology to be successful the packaging must provide the basic reliability and interconnection functions, adding the least possible cost to the product. This paper will discuss the evolution of MEMS packaging in the accelerometer industry and identify the main issues that needed to be addressed to enable the successful commercialization of the technology in the automotive and consumer markets.

Evaluation of copy number variation detection for a SNP array platform

PubMed Central

2014-01-01

Background Copy Number Variations (CNVs) are usually inferred from Single Nucleotide Polymorphism (SNP) arrays by use of some software packages based on given algorithms. However, there is no clear understanding of the performance of these software packages; it is therefore difficult to select one or several software packages for CNV detection based on the SNP array platform. We selected four publicly available software packages designed for CNV calling from an Affymetrix SNP array, including Birdsuite, dChip, Genotyping Console (GTC) and PennCNV. The publicly available dataset generated by Array-based Comparative Genomic Hybridization (CGH), with a resolution of 24 million probes per sample, was considered to be the “gold standard”. Compared with the CGH-based dataset, the success rate, average stability rate, sensitivity, consistence and reproducibility of these four software packages were assessed compared with the “gold standard”. Specially, we also compared the efficiency of detecting CNVs simultaneously by two, three and all of the software packages with that by a single software package. Results Simply from the quantity of the detected CNVs, Birdsuite detected the most while GTC detected the least. We found that Birdsuite and dChip had obvious detecting bias. And GTC seemed to be inferior because of the least amount of CNVs it detected. Thereafter we investigated the detection consistency produced by one certain software package and the rest three software suits. We found that the consistency of dChip was the lowest while GTC was the highest. Compared with the CNVs detecting result of CGH, in the matching group, GTC called the most matching CNVs, PennCNV-Affy ranked second. In the non-overlapping group, GTC called the least CNVs. With regards to the reproducibility of CNV calling, larger CNVs were usually replicated better. PennCNV-Affy shows the best consistency while Birdsuite shows the poorest. Conclusion We found that PennCNV outperformed the other three packages in the sensitivity and specificity of CNV calling. Obviously, each calling method had its own limitations and advantages for different data analysis. Therefore, the optimized calling methods might be identified using multiple algorithms to evaluate the concordance and discordance of SNP array-based CNV calling. PMID:24555668

Flip Chip on Organic Substrates: A Feasibility Study for Space Applications

DTIC Science & Technology

2017-03-01

scheme, a 1752 I/O land grid array (LGA) package with decoupling capacitors, heat sink and optional column attach [1] as shown in Figure 1...investigated the effect of moisture and current loading on the Class Y flip chip on ceramic reliability [ 2 ]. The UT1752FC Class Y technology has...chip assembly to ceramic test substrates, the FA10 die are assembled to build-up organic test substrates as shown in Figure 2 . These assemblies

Rutger's CAM2000 chip architecture

NASA Technical Reports Server (NTRS)

Smith, Donald E.; Hall, J. Storrs; Miyake, Keith

1993-01-01

This report describes the architecture and instruction set of the Rutgers CAM2000 memory chip. The CAM2000 combines features of Associative Processing (AP), Content Addressable Memory (CAM), and Dynamic Random Access Memory (DRAM) in a single chip package that is not only DRAM compatible but capable of applying simple massively parallel operations to memory. This document reflects the current status of the CAM2000 architecture and is continually updated to reflect the current state of the architecture and instruction set.

AIN-Coated Al(2)O(3) Substrates For Electronic Circuits

NASA Technical Reports Server (NTRS)

Kolawa, Elzbieta; Lowry, Lynn; Herman, Martin; Lee, Karen

1996-01-01

Type of improved ceramic substrate for high-frequency, high-power electronic circuits combines relatively high thermal conductivity of aluminum nitride with surface smoothness of alumina. Consists of 15-micrometer layer of AIN deposited on highly polished alumina. Used for packaging millimeter-wave gallium arsenide transmitter chips, power silicon chips, and like.

From functional structure to packaging: full-printing fabrication of a microfluidic chip.

PubMed

Zheng, Fengyi; Pu, Zhihua; He, Enqi; Huang, Jiasheng; Yu, Bocheng; Li, Dachao; Li, Zhihong

2018-05-24

This paper presents a concept of a full-printing methodology aiming at convenient and fast fabrication of microfluidic devices. For the first time, we achieved a microfluidic biochemical sensor with all functional structures fabricated by inkjet printing, including electrodes, immobilized enzymes, microfluidic components and packaging. With the cost-effective and rapid process, this method provides the possibility of quick model validation of a novel lab-on-chip system. In this study, a three-electrode electrochemical system was integrated successfully with glucose oxidase immobilization gel and sealed in an ice channel, forming a disposable microfluidic sensor for glucose detection. This fully-printed chip was characterized and showed good sensitivity and a linear section at a low-level concentration of glucose (0-10 mM). With the aid of automatic equipment, the fully-printed sensor can be massively produced with low cost.

Color design model of high color rendering index white-light LED module.

PubMed

Ying, Shang-Ping; Fu, Han-Kuei; Hsieh, Hsin-Hsin; Hsieh, Kun-Yang

2017-05-10

The traditional white-light light-emitting diode (LED) is packaged with a single chip and a single phosphor but has a poor color rendering index (CRI). The next-generation package comprises two chips and a single phosphor, has a high CRI, and retains high luminous efficacy. This study employs two chips and two phosphors to improve the diode's color tunability with various proportions of two phosphors and various densities of phosphor in the silicone used. A color design model is established for color fine-tuning of the white-light LED module. The maximum difference between the measured and color-design-model simulated CIE 1931 color coordinates is approximately 0.0063 around a correlated color temperature (CCT) of 2500 K. This study provides a rapid method to obtain the color fine-tuning of a white-light LED module with a high CRI and luminous efficacy.

Warpage Characteristics and Process Development of Through Silicon Via-Less Interconnection Technology.

PubMed

Shen, Wen-Wei; Lin, Yu-Min; Wu, Sheng-Tsai; Lee, Chia-Hsin; Huang, Shin-Yi; Chang, Hsiang-Hung; Chang, Tao-Chih; Chen, Kuan-Neng

2018-08-01

In this study, through silicon via (TSV)-less interconnection using the fan-out wafer-level-packaging (FO-WLP) technology and a novel redistribution layer (RDL)-first wafer level packaging are investigated. Since warpage of molded wafer is a critical issue and needs to be optimized for process integration, the evaluation of the warpage issue on a 12-inch wafer using finite element analysis (FEA) at various parameters is presented. Related parameters include geometric dimension (such as chip size, chip number, chip thickness, and mold thickness), materials' selection and structure optimization. The effect of glass carriers with various coefficients of thermal expansion (CTE) is also discussed. Chips are bonded onto a 12-inch reconstituted wafer, which includes 2 RDL layers, 3 passivation layers, and micro bumps, followed by using epoxy molding compound process. Furthermore, an optical surface inspector is adopted to measure the surface profile and the results are compared with the results from simulation. In order to examine the quality of the TSV-less interconnection structure, electrical measurement is conducted and the respective results are presented.

puma: a Bioconductor package for propagating uncertainty in microarray analysis.

PubMed

Pearson, Richard D; Liu, Xuejun; Sanguinetti, Guido; Milo, Marta; Lawrence, Neil D; Rattray, Magnus

2009-07-09

Most analyses of microarray data are based on point estimates of expression levels and ignore the uncertainty of such estimates. By determining uncertainties from Affymetrix GeneChip data and propagating these uncertainties to downstream analyses it has been shown that we can improve results of differential expression detection, principal component analysis and clustering. Previously, implementations of these uncertainty propagation methods have only been available as separate packages, written in different languages. Previous implementations have also suffered from being very costly to compute, and in the case of differential expression detection, have been limited in the experimental designs to which they can be applied. puma is a Bioconductor package incorporating a suite of analysis methods for use on Affymetrix GeneChip data. puma extends the differential expression detection methods of previous work from the 2-class case to the multi-factorial case. puma can be used to automatically create design and contrast matrices for typical experimental designs, which can be used both within the package itself but also in other Bioconductor packages. The implementation of differential expression detection methods has been parallelised leading to significant decreases in processing time on a range of computer architectures. puma incorporates the first R implementation of an uncertainty propagation version of principal component analysis, and an implementation of a clustering method based on uncertainty propagation. All of these techniques are brought together in a single, easy-to-use package with clear, task-based documentation. For the first time, the puma package makes a suite of uncertainty propagation methods available to a general audience. These methods can be used to improve results from more traditional analyses of microarray data. puma also offers improvements in terms of scope and speed of execution over previously available methods. puma is recommended for anyone working with the Affymetrix GeneChip platform for gene expression analysis and can also be applied more generally.

Chip-to-Chip Half Duplex Spiking Data Communication over Power Supply Rails

NASA Astrophysics Data System (ADS)

Hashida, Takushi; Nagata, Makoto

Chip-to-chip serial data communication is superposed on power supply over common Vdd/Vss connections through chip, package, and board traces. A power line transceiver demonstrates half duplex spiking communication at more than 100Mbps. A pair of transceivers consumes 1.35mA from 3.3V, at 130Mbps. On-chip power line LC low pass filter attenuates pseudo-differential communication spikes by 30dB, purifying power supply current for internal circuits. Bi-directional spiking communication was successfully examined in a 90-nm CMOS prototype setup of on-chip waveform capturing. A micro controller forwards clock pulses to and receives data streams from a comparator based waveform capturer formed on a different chip, through a single pair of power and ground traces. The bit error rate is small enough not to degrade waveform acquisition capability, maintaining the spurious free dynamic range of higher than 50dB.

Design and fabrication of a foldable 3D silicon based package for solid state lighting applications

NASA Astrophysics Data System (ADS)

Sokolovskij, R.; Liu, P.; van Zeijl, H. W.; Mimoun, B.; Zhang, G. Q.

2015-05-01

Miniaturization of solid state lighting (SSL) luminaires as well as reduction of packaging and assembly costs are of prime interest for the SSL lighting industry. A novel silicon based LED package for lighting applications is presented in this paper. The proposed design consists of 5 rigid Si tiles connected by flexible polyimide hinges with embedded interconnects (ICs). Electrical, optical and thermal characteristics were taken into consideration during design. The fabrication process involved polyimide (PI) application and patterning, aluminium interconnect integration in the flexible hinge, LED reflector cavity formation and metalization followed by through wafer DRIE etching for chip formation and release. A method to connect chip front to backside without TSVs was also integrated into the process. Post-fabrication wafer level assembly included LED mounting and wirebond, phosphor-based colour conversion and silicone encapsulation. The package formation was finalized by vacuum assisted wrapping around an assembly structure to form a 3D geometry, which is beneficial for omnidirectional lighting. Bending tests were performed on the flexible ICs and optical performance at different temperatures was evaluated. It is suggested that 3D packages can be expanded to platforms for miniaturized luminaire applications by combining monolithic silicon integration and system-in-package (SiP) technologies.

Micro packaged MEMS pressure sensor for intracranial pressure measurement

NASA Astrophysics Data System (ADS)

Xiong, Liu; Yan, Yao; Jiahao, Ma; Yanhang, Zhang; Qian, Wang; Zhaohua, Zhang; Tianling, Ren

2015-06-01

This paper presents a micro packaged MEMS pressure sensor for intracranial pressure measurement which belongs to BioMEMS. It can be used in lumbar puncture surgery to measure intracranial pressure. Miniaturization is key for lumbar puncture surgery because the sensor must be small enough to allow it be placed in the reagent chamber of the lumbar puncture needle. The size of the sensor is decided by the size of the sensor chip and package. Our sensor chip is based on silicon piezoresistive effect and the size is 400 × 400 μm2. It is much smaller than the reported polymer intracranial pressure sensors such as liquid crystal polymer sensors. In terms of package, the traditional dual in-line package obviously could not match the size need, the minimal size of recently reported MEMS-based intracranial pressure sensors after packaging is 10 × 10 mm2. In this work, we are the first to introduce a quad flat no-lead package as the package form of piezoresistive intracranial pressure sensors, the whole size of the sensor is minimized to only 3 × 3 mm2. Considering the liquid measurement environment, the sensor is gummed and waterproof performance is tested; the sensitivity of the sensor is 0.9 × 10-2 mV/kPa. Project supported by the National Natural Science Foundation of China (Nos. 61025021, 61434001), and the ‘Thousands Talents’ Program for Pioneer Researchers and Its Innovation Team, China.

An integrated workflow for analysis of ChIP-chip data.

PubMed

Weigelt, Karin; Moehle, Christoph; Stempfl, Thomas; Weber, Bernhard; Langmann, Thomas

2008-08-01

Although ChIP-chip is a powerful tool for genome-wide discovery of transcription factor target genes, the steps involving raw data analysis, identification of promoters, and correlation with binding sites are still laborious processes. Therefore, we report an integrated workflow for the analysis of promoter tiling arrays with the Genomatix ChipInspector system. We compare this tool with open-source software packages to identify PU.1 regulated genes in mouse macrophages. Our results suggest that ChipInspector data analysis, comparative genomics for binding site prediction, and pathway/network modeling significantly facilitate and enhance whole-genome promoter profiling to reveal in vivo sites of transcription factor-DNA interactions.

Thin-film decoupling capacitors for multi-chip modules

NASA Astrophysics Data System (ADS)

Dimos, D.; Lockwood, S. J.; Schwartz, R. W.; Rogers, M. S.

Thin-film decoupling capacitors based on ferroelectric lead lanthanum zirconate titanate (PLZT) films are being developed for use in advanced packages, such as multi-chip modules. These thin-film decoupling capacitors are intended to replace multi-layer ceramic capacitors for certain applications, since they can be more fully integrated into the packaging architecture. The increased integration that can be achieved should lead to decreased package volume and improved high-speed performance, due to a decrease in interconnect inductance. PLZT films are fabricated by spin coating using metal carboxylate/alkoxide solutions. These films exhibit very high dielectric constants ((var epsilon) greater than or equal to 900), low dielectric losses (tan(delta) = 0.01), excellent insulation resistances (rho greater than 10(exp 13) (Omega)-cm at 125 C), and good breakdown field strengths (E(sub B) = 900 kV/cm). For integrated circuit applications, the PLZT dielectric is less than 1 micron thick, which results in a large capacitance/area (8-9 nF/sq mm). The thin-film geometry and processing conditions also make these capacitors suitable for direct incorporation onto integrated circuits and for packages that require embedded components.

A review of digital microfluidics as portable platforms for lab-on a-chip applications.

PubMed

Samiei, Ehsan; Tabrizian, Maryam; Hoorfar, Mina

2016-07-07

Following the development of microfluidic systems, there has been a high tendency towards developing lab-on-a-chip devices for biochemical applications. A great deal of effort has been devoted to improve and advance these devices with the goal of performing complete sets of biochemical assays on the device and possibly developing portable platforms for point of care applications. Among the different microfluidic systems used for such a purpose, digital microfluidics (DMF) shows high flexibility and capability of performing multiplex and parallel biochemical operations, and hence, has been considered as a suitable candidate for lab-on-a-chip applications. In this review, we discuss the most recent advances in the DMF platforms, and evaluate the feasibility of developing multifunctional packages for performing complete sets of processes of biochemical assays, particularly for point-of-care applications. The progress in the development of DMF systems is reviewed from eight different aspects, including device fabrication, basic fluidic operations, automation, manipulation of biological samples, advanced operations, detection, biological applications, and finally, packaging and portability of the DMF devices. Success in developing the lab-on-a-chip DMF devices will be concluded based on the advances achieved in each of these aspects.

Low-cost optical interconnect module for parallel optical data links

NASA Astrophysics Data System (ADS)

Noddings, Chad; Hirsch, Tom J.; Olla, M.; Spooner, C.; Yu, Jason J.

1995-04-01

We have designed, fabricated, and tested a prototype parallel ten-channel unidirectional optical data link. When scaled to production, we project that this technology will satisfy the following market penetration requirements: (1) up to 70 meters transmission distance, (2) at least 1 gigabyte/second data rate, and (3) 0.35 to 0.50 MByte/second volume selling price. These goals can be achieved by means of the assembly innovations described in this paper: a novel alignment method that is integrated with low-cost, few chip module packaging techniques, yielding high coupling and reducing the component count. Furthermore, high coupling efficiency increases projected reliability reducing the driver's power requirements.

High Coherence Qubit packaging

NASA Astrophysics Data System (ADS)

Pappas, David P.; Wu, Xian; Olivadese, Salvatore B.; Adiga, V. P.; Hertzberg, Jared B.; Bronn, Nicholas T.; Chow, Jerry M.; NIST Team; IBM Team

Development of sockets and associated interconnects for multi-qubit chips is presented. Considerations include thermalization, RF hygiene, non-magnetic environment, and self-alignment of the chips to allow for rapid testing, scalable integration, and high coherence operation. The sockets include wirebond free, vertical take-off launches with pogopins. This allows for high interconnectivity to non-trivial topology of qubits. Furthermore, vertical grounding is accomplished to reduce chip modes and suppress box modes. Low energy loss and high phase coherence is observed using this paradigm. We acknowledge support from IARPA, LPS, and the NIST Quantum Based Metrology Initiative.

Applications of multi-walled carbon nanotube in electronic packaging

PubMed Central

2012-01-01

Thermal management of integrated circuit chip is an increasing important challenge faced today. Heat dissipation of the chip is generally achieved through the die attach material and solders. With the temperature gradients in these materials, high thermo-mechanical stress will be developed in them, and thus they must also be mechanically strong so as to provide a good mechanical support to the chip. The use of multi-walled carbon nanotube to enhance the thermal conductivity, and the mechanical strength of die attach epoxy and Pb-free solder is demonstrated in this work. PMID:22405035

Wireless Interconnects for Intra-chip & Inter-chip Transmission

NASA Astrophysics Data System (ADS)

Narde, Rounak Singh

With the emergence of Internet of Things and information revolution, the demand of high performance computing systems is increasing. The copper interconnects inside the computing chips have evolved into a sophisticated network of interconnects known as Network on Chip (NoC) comprising of routers, switches, repeaters, just like computer networks. When network on chip is implemented on a large scale like in Multicore Multichip (MCMC) systems for High Performance Computing (HPC) systems, length of interconnects increases and so are the problems like power dissipation, interconnect delays, clock synchronization and electrical noise. In this thesis, wireless interconnects are chosen as the substitute for wired copper interconnects. Wireless interconnects offer easy integration with CMOS fabrication and chip packaging. Using wireless interconnects working at unlicensed mm-wave band (57-64GHz), high data rate of Gbps can be achieved. This thesis presents study of transmission between zigzag antennas as wireless interconnects for Multichip multicores (MCMC) systems and 3D IC. For MCMC systems, a four-chips 16-cores model is analyzed with only four wireless interconnects in three configurations with different antenna orientations and locations. Return loss and transmission coefficients are simulated in ANSYS HFSS. Moreover, wireless interconnects are designed, fabricated and tested on a 6'' silicon wafer with resistivity of 55O-cm using a basic standard CMOS process. Wireless interconnect are designed to work at 30GHz using ANSYS HFSS. The fabricated antennas are resonating around 20GHz with a return loss of less than -10dB. The transmission coefficients between antenna pair within a 20mm x 20mm silicon die is found to be varying between -45dB to -55dB. Furthermore, wireless interconnect approach is extended for 3D IC. Wireless interconnects are implemented as zigzag antenna. This thesis extends the work of analyzing the wireless interconnects in 3D IC with different configurations of antenna orientations and coolants. The return loss and transmission coefficients are simulated using ANSYS HFSS.

Nutrition labelling, marketing techniques, nutrition claims and health claims on chip and biscuit packages from sixteen countries.

PubMed

Mayhew, Alexandra J; Lock, Karen; Kelishadi, Roya; Swaminathan, Sumathi; Marcilio, Claudia S; Iqbal, Romaina; Dehghan, Mahshid; Yusuf, Salim; Chow, Clara K

2016-04-01

Food packages were objectively assessed to explore differences in nutrition labelling, selected promotional marketing techniques and health and nutrition claims between countries, in comparison to national regulations. Cross-sectional. Chip and sweet biscuit packages were collected from sixteen countries at different levels of economic development in the EPOCH (Environmental Profile of a Community's Health) study between 2008 and 2010. Seven hundred and thirty-seven food packages were systematically evaluated for nutrition labelling, selected promotional marketing techniques relevant to nutrition and health, and health and nutrition claims. We compared pack labelling in countries with labelling regulations, with voluntary regulations and no regulations. Overall 86 % of the packages had nutrition labels, 30 % had health or nutrition claims and 87 % displayed selected marketing techniques. On average, each package displayed two marketing techniques and one health or nutrition claim. In countries with mandatory nutrition labelling a greater proportion of packages displayed nutrition labels, had more of the seven required nutrients present, more total nutrients listed and higher readability compared with those with voluntary or no regulations. Countries with no health or nutrition claim regulations had fewer claims per package compared with countries with regulations. Nutrition label regulations were associated with increased prevalence and quality of nutrition labels. Health and nutrition claim regulations were unexpectedly associated with increased use of claims, suggesting that current regulations may not have the desired effect of protecting consumers. Of concern, lack of regulation was associated with increased promotional marketing techniques directed at children and misleadingly promoting broad concepts of health.

Development of a MEMS acoustic emission sensor system

NASA Astrophysics Data System (ADS)

Greve, David W.; Oppenheim, Irving J.; Wu, Wei; Wright, Amelia P.

2007-04-01

An improved multi-channel MEMS chip for acoustic emission sensing has been designed and fabricated in 2006 to create a device that is smaller in size, superior in sensitivity, and more practical to manufacture than earlier designs. The device, fabricated in the MUMPS process, contains four resonant-type capacitive transducers in the frequency range between 100 kHz and 500 kHz on a chip with an area smaller than 2.5 sq. mm. The completed device, with its circuit board, electronics, housing, and connectors, possesses a square footprint measuring 25 mm x 25 mm. The small footprint is an important attribute for an acoustic emission sensor, because multiple sensors must typically be arrayed around a crack location. Superior sensitivity was achieved by a combination of four factors: the reduction of squeeze film damping, a resonant frequency approximating a rigid body mode rather than a bending mode, a ceramic package providing direct acoustic coupling to the structural medium, and high-gain amplifiers implemented on a small circuit board. Manufacture of the system is more practical because of higher yield (lower unit costs) in the MUMPS fabrication task and because of a printed circuit board matching the pin array of the MEMS chip ceramic package for easy assembly and compactness. The transducers on the MEMS chip incorporate two major mechanical improvements, one involving squeeze film damping and one involving the separation of resonance modes. For equal proportions of hole area to plate area, a triangular layout of etch holes reduces squeeze film damping as compared to the conventional square layout. The effect is modeled analytically, and is verified experimentally by characterization experiments on the new transducers. Structurally, the transducers are plates with spring supports; a rigid plate would be the most sensitive transducer, and bending decreases the sensitivity. In this chip, the structure was designed for an order-of-magnitude separation between the first and the second mode frequency, strongly approximating the desirable rigid plate limit. The effect is modeled analytically and is verified experimentally by measurement of the resonance frequencies in the new transducers. Another improvement arises from the use of a pin grid array ceramic package, in which the MEMS chip is acoustically coupled to the structure with only two interfaces, through a ceramic medium that is negligible in thickness when compared to wavelengths of interest. Like other acoustic emission sensors, those on the 2006 MEMS chip are sensitive only to displacements normal to the surface on which the device is mounted. To overcome that long-standing limitation, a new MEMS sensor sensitive to in-plane motion has been designed, featuring a different spring-mass mechanism and creating the signal by the change in capacitance between stationary and moving fingers. Predicted damping is much lower for the case of the in-plane sensor, and squeeze-film damping is used selectively to isolate the desired in-plane mechanical response from any unwanted out-of-plane response. The new spring-mass mechanism satisfies the design rules for the PolyMUMPS fabrication (foundry) process. A 3-D MEMS sensor system is presently being fabricated, collocating two in-plane sensors and one out-of-plane sensor at the mm scale, which is very short compared to the acoustic wavelength of interest for stress waves created by acoustic emission events.

Research pressure instrumentation for NASA Space Shuttle main engine, modification no. 5

NASA Technical Reports Server (NTRS)

Anderson, P. J.; Nussbaum, P.; Gustafson, G.

1984-01-01

The advantages of silicon piezoresistive strain sensing technology are being used to achieve the objectives of state of the art pressure sensors for SSME applications. The integration of multiple functions on a single chip is the key attribute being exploited. Progress is reported in transducer packaging and materials; silicon resistor characterization at cryogenic temperatures; chip mounting; and frequency response optimization.

27 CFR 19.343 - Addition of oak chips to spirits and addition of caramel to brandy and rum.

Code of Federal Regulations, 2010 CFR

2010-04-01

... spirits and addition of caramel to brandy and rum. 19.343 Section 19.343 Alcohol, Tobacco Products and... PLANTS Storage § 19.343 Addition of oak chips to spirits and addition of caramel to brandy and rum. Oak... records. Caramel possessing no material sweetening properties may be added to rum or brandy in packages or...

Technology and design of an active-matrix OLED on crystalline silicon direct-view display for a wristwatch computer

NASA Astrophysics Data System (ADS)

Sanford, James L.; Schlig, Eugene S.; Prache, Olivier; Dove, Derek B.; Ali, Tariq A.; Howard, Webster E.

2002-02-01

The IBM Research Division and eMagin Corp. jointly have developed a low-power VGA direct view active matrix OLED display, fabricated on a crystalline silicon CMOS chip. The display is incorporated in IBM prototype wristwatch computers running the Linus operating system. IBM designed the silicon chip and eMagin developed the organic stack and performed the back-end-of line processing and packaging. Each pixel is driven by a constant current source controlled by a CMOS RAM cell, and the display receives its data from the processor memory bus. This paper describes the OLED technology and packaging, and outlines the design of the pixel and display electronics and the processor interface. Experimental results are presented.

Advanced processing of CdTe pixel radiation detectors

NASA Astrophysics Data System (ADS)

Gädda, A.; Winkler, A.; Ott, J.; Härkönen, J.; Karadzhinova-Ferrer, A.; Koponen, P.; Luukka, P.; Tikkanen, J.; Vähänen, S.

2017-12-01

We report a fabrication process of pixel detectors made of bulk cadmium telluride (CdTe) crystals. Prior to processing, the quality and defect density in CdTe material was characterized by infrared (IR) spectroscopy. The semiconductor detector and Flip-Chip (FC) interconnection processing was carried out in the clean room premises of Micronova Nanofabrication Centre in Espoo, Finland. The chip scale processes consist of the aluminum oxide (Al2O3) low temperature thermal Atomic Layer Deposition (ALD), titanium tungsten (TiW) metal sputtering depositions and an electroless Nickel growth. CdTe crystals with the size of 10×10×0.5 mm3 were patterned with several photo-lithography techniques. In this study, gold (Au) was chosen as the material for the wettable Under Bump Metalization (UBM) pads. Indium (In) based solder bumps were grown on PSI46dig read out chips (ROC) having 4160 pixels within an area of 1 cm2. CdTe sensor and ROC were hybridized using a low temperature flip-chip (FC) interconnection technique. The In-Au cold weld bonding connections were successfully connecting both elements. After the processing the detector packages were wire bonded into associated read out electronics. The pixel detectors were tested at the premises of Finnish Radiation Safety Authority (STUK). During the measurement campaign, the modules were tested by exposure to a 137Cs source of 1.5 TBq for 8 minutes. We detected at the room temperature a photopeak at 662 keV with about 2 % energy resolution.

High coherence plane breaking packaging for superconducting qubits.

PubMed

Bronn, Nicholas T; Adiga, Vivekananda P; Olivadese, Salvatore B; Wu, Xian; Chow, Jerry M; Pappas, David P

2018-04-01

We demonstrate a pogo pin package for a superconducting quantum processor specifically designed with a nontrivial layout topology (e.g., a center qubit that cannot be accessed from the sides of the chip). Two experiments on two nominally identical superconducting quantum processors in pogo packages, which use commercially available parts and require modest machining tolerances, are performed at low temperature (10 mK) in a dilution refrigerator and both found to behave comparably to processors in standard planar packages with wirebonds where control and readout signals come in from the edges. Single- and two-qubit gate errors are also characterized via randomized benchmarking, exhibiting similar error rates as in standard packages, opening the possibility of integrating pogo pin packaging with extensible qubit architectures.

High coherence plane breaking packaging for superconducting qubits

NASA Astrophysics Data System (ADS)

Bronn, Nicholas T.; Adiga, Vivekananda P.; Olivadese, Salvatore B.; Wu, Xian; Chow, Jerry M.; Pappas, David P.

2018-04-01

We demonstrate a pogo pin package for a superconducting quantum processor specifically designed with a nontrivial layout topology (e.g., a center qubit that cannot be accessed from the sides of the chip). Two experiments on two nominally identical superconducting quantum processors in pogo packages, which use commercially available parts and require modest machining tolerances, are performed at low temperature (10 mK) in a dilution refrigerator and both found to behave comparably to processors in standard planar packages with wirebonds where control and readout signals come in from the edges. Single- and two-qubit gate errors are also characterized via randomized benchmarking, exhibiting similar error rates as in standard packages, opening the possibility of integrating pogo pin packaging with extensible qubit architectures.

NASA Electronic Parts and Packaging (NEPP) Program - Update

NASA Technical Reports Server (NTRS)

LaBel, Kenneth A.; Sampson, Michael J.

2010-01-01

This slide presentation reviews the goals and mission of the NASA Electronic Parts and Packaging (NEPP) Program. The NEPP mission is to provide guidance to NASA for the selection and application of microelectronics technologies, to improve understanding of the risks related to the use of these technologies in the space environment and to ensure that appropriate research is performed to meet NASA mission assurance needs. The program has been supporting NASA for over 20 years. The focus is on the reliability aspects of electronic devices. In this work the program also supports the electronics industry. There are several areas that the program is involved in: Memories, systems on a chip (SOCs), data conversion devices, power MOSFETS, power converters, scaled CMOS, capacitors, linear devices, fiber optics, and other electronics such as sensors, cryogenic and SiGe that are used in space systems. Each of these area are reviewed with the work that is being done in reliability and effects of radiation on these technologies.

AE (Acoustic Emission) for Flip-Chip CGA/FCBGA Defect Detection

NASA Technical Reports Server (NTRS)

Ghaffarian, Reza

2014-01-01

C-mode scanning acoustic microscopy (C-SAM) is a nondestructive inspection technique that uses ultrasound to show the internal feature of a specimen. A very high or ultra-high-frequency ultrasound passes through a specimen to produce a visible acoustic microimage (AMI) of its inner features. As ultrasound travels into a specimen, the wave is absorbed, scattered or reflected. The response is highly sensitive to the elastic properties of the materials and is especially sensitive to air gaps. This specific characteristic makes AMI the preferred method for finding "air gaps" such as delamination, cracks, voids, and porosity. C-SAM analysis, which is a type of AMI, was widely used in the past for evaluation of plastic microelectronic circuits, especially for detecting delamination of direct die bonding. With the introduction of the flip-chip die attachment in a package; its use has been expanded to nondestructive characterization of the flip-chip solder bumps and underfill. Figure 1.1 compares visual and C-SAM inspection approaches for defect detection, especially for solder joint interconnections and hidden defects. C-SAM is specifically useful for package features like internal cracks and delamination. C-SAM not only allows for the visualization of the interior features, it has the ability to produce images on layer-by-layer basis. Visual inspection; however, is only superior to C-SAM for the exposed features including solder dewetting, microcracks, and contamination. Ideally, a combination of various inspection techniques - visual, optical and SEM microscopy, C-SAM, and X-ray - need to be performed in order to assure quality at part, package, and system levels. This reports presents evaluations performed on various advanced packages/assemblies, especially the flip-chip die version of ball grid array/column grid array (BGA/CGA) using C-SAM equipment. Both external and internal equipment was used for evaluation. The outside facility provided images of the key features that could be detected using the most advanced C-SAM equipment with a skilled operator. Investigation continued using in-house equipment with its limitations. For comparison, representative X-rays of the assemblies were also gathered to show key defect detection features of these non-destructive techniques. Key images gathered and compared are: Compared the images of 2D X-ray and C-SAM for a plastic LGA assembly showing features that could be detected by either NDE technique. For this specific case, X-ray was a clear winner. Evaluated flip-chip CGA and FCBGA assemblies with and without heat sink by C-SAM. Only the FCCGA package that had no heat sink could be fully analyzed for underfill and bump quality. Cross-sectional microscopy did not revealed peripheral delamination features detected by C-SAM. Analyzed a number of fine pitch PBGA assemblies by C-SAM. Even though the internal features of the package assemblies could be detected, C-SAM was unable to detect solder joint failure at either the package or board level. Twenty times touch ups by solder iron with 700degF tip temperature, each with about 5 second duration, did not induce defects to be detected by C-SAM images. Other techniques need to be considered to induce known defects for characterization. Given NASA's emphasis on the use of microelectronic packages and assemblies and quality assurance on workmanship defect detection, understanding key features of various inspection systems that detect defects in the early stages of package and assembly is critical to developing approaches that will minimize future failures. Additional specific, tailored non-destructive inspection approaches could enable low-risk insertion of these advanced electronic packages having hidden and fine features.

Development and Industrialization of InGaN/GaN LEDs on Patterned Sapphire Substrates for Low Cost Emitter Architecture

DOE Office of Scientific and Technical Information (OSTI.GOV)

Flemish, Joseph; Soer, Wouter

2015-11-30

Patterned sapphire substrate (PSS) technology has proven to be an effective approach to improve efficacy and reduce cost of light-emitting diodes (LEDs). The volume emission from the transparent substrate leads to high package efficiency, while the simple and robust architecture of PSS-based LEDs enables low cost. PSS substrates have gained wide use in mid-power LEDs over the past years. In this project, Lumileds has developed and industrialized PSS and epitaxy technology for high- power flip-chip LEDs to bring these benefits to a broader range of applications and accelerate the adoption of energy-efficient solid-state lighting (SSL). PSS geometries were designed formore » highly efficient light extraction in a flip-chip architecture and high-volume manufacturability, and corresponding sapphire patterning and epitaxy manufacturing processes were integrally developed. Concurrently, device and package architectures were developed to take advantage of the PSS flip-chip die in different types of products that meet application needs. The developed PSS and epitaxy technology has been fully implemented in manufacturing at Lumileds’ San Jose, CA location, and incorporated in illumination-grade LED products that have been successfully introduced to the market, including LUXEON Q and LUXEON FlipChip White.« less

A Boundary Scan Test Vehicle for Direct Chip Attach Testing

NASA Technical Reports Server (NTRS)

Parsons, Heather A.; DAgostino, Saverio; Arakaki, Genji

2000-01-01

To facilitate the new faster, better and cheaper spacecraft designs, smaller more mass efficient avionics and instruments are using higher density electronic packaging technologies such as direct chip attach (DCA). For space flight applications, these technologies need to have demonstrated reliability and reasonably well defined fabrication and assembly processes before they will be accepted as baseline designs in new missions. As electronics shrink in size, not only can repair be more difficult, but 49 probing" circuitry can be very risky and it becomes increasingly more difficult to identify the specific source of a problem. To test and monitor these new technologies, the Direct Chip Attach Task, under NASA's Electronic Parts and Packaging Program (NEPP), chose the test methodology of boundary scan testing. The boundary scan methodology was developed for interconnect integrity and functional testing at hard to access electrical nodes. With boundary scan testing, active devices are used and failures can be identified to the specific device and lead. This technology permits the incorporation of "built in test" into almost any circuit and thus gives detailed test access to the highly integrated electronic assemblies. This presentation will describe boundary scan, discuss the development of the boundary scan test vehicle for DCA and current plans for testing of direct chip attach configurations.

Chips in black boxes? Convenience life span, parafood, brandwidth, families, and co-creation.

PubMed

Jacobs, Marc

2015-11-01

Any consumer who opens a bag of potato or corn chips (or crisps in the UK) knows there is no time to waste to enjoy or share them. The convenience life span of chips is limited: it is the shelf or storage life and a very limited time once outside the bag. Many technologies converge to generate the desired effect as a black box, not only of the packaging but also of the chips themselves. The concept of paratext can be applied to printed messages on the package, including the brand name and other texts like advertising (epitexts), which can be expanded into the concept of parafood. These concepts help to discuss technological developments and interpret why this has recently become a negotiation zone for co-creation (see the Do us a flavor campaigns). They are symptoms of changing relations between production, research and development, marketing, and consumption. This paper pays special attention to back stories, underdog brand biographies and narratives about origin. The concept of brandwidth is introduced to sensitize about the limits of combining different stories about chips. A recent brand biography, a family history and a cookery book are used to discuss the phenomenon of cooking with Fritos. Together with the concepts of parafood, brandwidth and black boxes, more reflection and dialogue about the role of history and heritage in marketing put new challenging perspectives on the agenda. Copyright © 2015 Elsevier Ltd. All rights reserved.

Advanced packaging for Integrated Micro-Instruments

NASA Technical Reports Server (NTRS)

Lyke, James L.

1995-01-01

The relationship between packaging, microelectronics, and micro-electrical-mechanical systems (MEMS) is an important one, particularly when the edges of performance boundaries are pressed, as in the case of miniaturized systems. Packaging is a sort of physical backbone that enables the maximum performance of these systems to be realized, and the penalties imposed by conventional packing approaches is particularly limiting for MEMS devices. As such, advanced packaging approaches, such as multi-chip modules (MCM's) have been touted as a true means of electronic 'enablement' for a variety of application domains. Realizing an optimum system of packaging, however, in not as simple as replacing a set of single chip packages with a substrate of interconnections. Research at Phillips Laboratory has turned up a number of integrating options in the two- and three-dimensional rending of miniature systems with physical interconnection structures with intrinsically high performance. Not only do these structures motivate the redesign of integrated circuits (IC's) for lower power, but they possess interesting features that provide a framework for the direct integration of MEMS devices. Cost remains a barrier to the application of MEMS devices, even in space systems. Several innovations are suggested that will result in lower cost and more rapid cycle time. First, the novelty of a 'constant floor plan' MCM which encapsulates a variety of commonly used components into a stockable, easily customized assembly is discussed. Next, the use of low-cost substrates is examined. The anticipated advent of ultra-high density interconnect (UHDI) is suggested as the limit argument of advanced packaging. Finally, the concept of a heterogeneous 3-D MCM system is outlined that allows for the combination of different compatible packaging approaches into a uniformly dense structure that could also include MEMS-based sensors.

The Chip-Scale Atomic Clock - Recent Development Progress

DTIC Science & Technology

2004-09-01

35th Annual Precise Time and Time Interval (PTTI) Meeting 467 THE CHIP-SCALE ATOMIC CLOCK – RECENT DEVELOPMENT PROGRESS R. Lutwak ...1] R. Lutwak , et al., 2003, “The Chip-Scale Atomic Clock – Coherent Population Trapping vs. Conventional Interrogation,” in

77 FR 14569 - Notice of Intent To Grant Exclusive License

Federal Register 2010, 2011, 2012, 2013, 2014

2012-03-12

... Direct Chip Attach Packaging Methodologies and Apparatuses for Harsh Environments, LEW 17,256-1, to... equipment; semiconductor manufacturing; material manufacturing such as metallurgy, refractory processes, and...

Thermal transpiration in zeolites: A mechanism for motionless gas pumps

NASA Astrophysics Data System (ADS)

Gupta, Naveen K.; Gianchandani, Yogesh B.

2008-11-01

We explore the use of a naturally occurring zeolite, clinoptilolite, for a chip-scale, thermal transpiration-based gas pump. The nanopores in clinoptilolite enable the required free-molecular flow, even at atmospheric pressure. The pump utilizes a foil heater located between zeolite disks in a plastic package. A 2.3mm thick zeolite disk generates a typical gas flow rate of 6.6×10-3 cc/min-cm2 with an input power of <300mW/cm2. The performance is constrained by imperfections in clinoptilolite, which provide estimated leakage apertures of 10.2-13.5μm/cm2 of flow cross section. The transient response of the pump is studied to quantify nonidealities.

Preparation of a YAG:Ce phosphor glass by screen-printing technology and its application in LED packaging.

PubMed

Yang, Liang; Chen, Mingxiang; Lv, Zhicheng; Wang, Simin; Liu, Xiaogang; Liu, Sheng

2013-07-01

A simple and practical method for preparing phosphor glass is proposed. Phosphor distribution and element analysis are investigated by optical microscope and field emission scanning electron microscope (FE-SEM). The phosphor particles dispersed in the matrix are vividly observed, and their distributions are uniform. Spectrum distribution and color coordinates dependent on the thickness of the screen-printed phosphor layer coupled with a blue light emitting diode (LED) chip are studied. The luminous efficacy of the 75 μm printed phosphor-layer phosphor glass packaged white LED is 81.24 lm/W at 350 mA. This study opens up many possibilities for applications using the phosphor glass on a selected chip in which emission is well absorbed by all phosphors. The screen-printing technique also offers possibilities for the design and engineering of complex phosphor layers on glass substrates. Phosphor screen-printing technology allows the realization of high stability and thermal conductivity for the phosphor layer. This phosphor glass method provides many possibilities for LED packing, including thin-film flip chip and remote phosphor technology.

CMOS Image Sensor with a Built-in Lane Detector.

PubMed

Hsiao, Pei-Yung; Cheng, Hsien-Chein; Huang, Shih-Shinh; Fu, Li-Chen

2009-01-01

This work develops a new current-mode mixed signal Complementary Metal-Oxide-Semiconductor (CMOS) imager, which can capture images and simultaneously produce vehicle lane maps. The adopted lane detection algorithm, which was modified to be compatible with hardware requirements, can achieve a high recognition rate of up to approximately 96% under various weather conditions. Instead of a Personal Computer (PC) based system or embedded platform system equipped with expensive high performance chip of Reduced Instruction Set Computer (RISC) or Digital Signal Processor (DSP), the proposed imager, without extra Analog to Digital Converter (ADC) circuits to transform signals, is a compact, lower cost key-component chip. It is also an innovative component device that can be integrated into intelligent automotive lane departure systems. The chip size is 2,191.4 × 2,389.8 μm, and the package uses 40 pin Dual-In-Package (DIP). The pixel cell size is 18.45 × 21.8 μm and the core size of photodiode is 12.45 × 9.6 μm; the resulting fill factor is 29.7%.

A proposed holistic approach to on-chip, off-chip, test, and package interconnections

NASA Astrophysics Data System (ADS)

Bartelink, Dirk J.

1998-11-01

The term interconnection has traditionally implied a `robust' connection from a transistor or a group of transistors in an IC to the outside world, usually a PC board. Optimum system utilization is done from outside the IC. As an alternative, this paper addresses `unimpeded' transistor-to-transistor interconnection aimed at reaching the high circuit densities and computational capabilities of neighboring IC's. In this view, interconnections are not made to some human-centric place outside the IC world requiring robustness—except for system input and output connections. This unimpeded interconnect style is currently available only through intra-chip signal traces in `system-on-a-chip' implementations, as exemplified by embedded DRAMs. Because the traditional off-chip penalty in performance and wiring density is so large, a merging of complex process technologies is the only option today. It is suggested that, for system integration to move forward, the traditional robustness requirement inherited from conventional packaging interconnect and IC manufacturing test must be discarded. Traditional system assembly from vendor parts requires robustness under shipping, inspection and assembly. The trend toward systems on a chip signifies willingness by semiconductor companies to design and fabricate whole systems in house, so that `in-house' chip-to-chip assembly is not beyond reach. In this scenario, bare chips never leave the controlled environment of the IC fabricator while the two major contributors to off-chip signal penalty, ESD protection and the need to source a 50-ohm test head, are avoided. With in-house assembly, ESD protection can be eliminated with the precautions already familiar in plasma etching. Test interconnection impacts the fundamentals of IC manufacturing, particularly with clock speeds approaching 1GHz, and cannot be an afterthought. It should be an integral part of the chip-to-chip interconnection bandwidth optimization, because—as we must recognize—test is also performed using IC's. A system interconnection is proposed using multiple chips fabricated with conventional silicon processes, including MEMS technology. The system resembles an MCM that can be joined without committing to final assembly to perform at-speed testing. 50-Ohm test probes never load the circuit; only intended neighboring chips are ever connected. A `back-plane' chip provides the connection layers for both inter- and intra-chip signals and also serves as the probe card, in analogy with membrane probes now used for single-chip testing. Intra-chip connections, which require complicated connections during test that exactly match the product, are then properly made and all waveforms and loading conditions under test will be identical to those of the product. The major benefit is that all front-end chip technologies can be merged—logic, memory, RF, even passives. ESD protection is required only on external system connections. Manufacturing test information will accurately characterize process faults and thus avoid the Known-Good-Die problem that has slowed the arrival of conventional MCM's.

Designing an Electronics Data Package for Printed Circuit Boards (PCBs)

DTIC Science & Technology

2013-08-01

finished PCB flatness deviation should be less than 0.010 inches per inch. 4  The minimum copper wall thickness of plated-thru holes should be...Memory Card International Association)  IPC-6015 MCM-L (Multi-Chip Module – Laminated )  IPC-6016 HDI (High Density Interconnect)  IPC-6018...Interconnect ICT In Circuit Tester IPC Association Connecting Electronics Industries MCM-L Multi-Chip Module – Laminated MIL Military NEMA National

Radiation-Resistant Photon-Counting Detector Package Providing Sub-ps Stability for Laser Time Transfer in Space

NASA Technical Reports Server (NTRS)

Prochzaka, Ivan; Kodat, Jan; Blazej, Josef; Sun, Xiaoli (Editor)

2015-01-01

We are reporting on a design, construction and performance of photon-counting detector packages based on silicon avalanche photodiodes. These photon-counting devices have been optimized for extremely high stability of their detection delay. The detectors have been designed for future applications in fundamental metrology and optical time transfer in space. The detectors have been qualified for operation in space missions. The exceptional radiation tolerance of the detection chip itself and of all critical components of a detector package has been verified in a series of experiments.

Low-dielectric constant insulators for future integrated circuits and packages.

PubMed

Kohl, Paul A

2011-01-01

Future integrated circuits and packages will require extraordinary dielectric materials for interconnects to allow transistor advances to be translated into system-level advances. Exceedingly low-permittivity and low-loss materials are required at every level of the electronic system, from chip-level insulators to packages and printed wiring boards. In this review, the requirements and goals for future insulators are discussed followed by a summary of current state-of-the-art materials and technical approaches. Much work needs to be done for insulating materials and structures to meet future needs.

Epoxy Chip-in-Carrier Integration and Screen-Printed Metalization for Multichannel Microfluidic Lab-on-CMOS Microsystems.

PubMed

Li, Lin; Yin, Heyu; Mason, Andrew J

2018-04-01

The integration of biosensors, microfluidics, and CMOS instrumentation provides a compact lab-on-CMOS microsystem well suited for high throughput measurement. This paper describes a new epoxy chip-in-carrier integration process and two planar metalization techniques for lab-on-CMOS that enable on-CMOS electrochemical measurement with multichannel microfluidics. Several design approaches with different fabrication steps and materials were experimentally analyzed to identify an ideal process that can achieve desired capability with high yield and low material and tool cost. On-chip electrochemical measurements of the integrated assembly were performed to verify the functionality of the chip-in-carrier packaging and its capability for microfluidic integration. The newly developed CMOS-compatible epoxy chip-in-carrier process paves the way for full implementation of many lab-on-CMOS applications with CMOS ICs as core electronic instruments.

Study on vacuum packaging reliability of micromachined quartz tuning fork gyroscopes

NASA Astrophysics Data System (ADS)

Fan, Maoyan; Zhang, Lifang

2017-09-01

Packaging technology of the micromachined quartz tuning fork gyroscopes by vacuum welding has been experimentally studied. The performance of quartz tuning fork is influenced by the encapsulation shell, encapsulation method and fixation of forks. Alloy solder thick film is widely used in the package to avoid the damage of the chip structure by the heat resistance and hot temperature, and this can improve the device performance and welding reliability. The results show that the bases and the lids plated with gold and nickel can significantly improve the airtightness and reliability of the vacuum package. Vacuum packaging is an effective method to reduce the vibration damping, improve the quality factor and further enhance the performance. The threshold can be improved nearly by 10 times.

Neuron array with plastic synapses and programmable dendrites.

PubMed

Ramakrishnan, Shubha; Wunderlich, Richard; Hasler, Jennifer; George, Suma

2013-10-01

We describe a novel neuromorphic chip architecture that models neurons for efficient computation. Traditional architectures of neuron array chips consist of large scale systems that are interfaced with AER for implementing intra- or inter-chip connectivity. We present a chip that uses AER for inter-chip communication but uses fast, reconfigurable FPGA-style routing with local memory for intra-chip connectivity. We model neurons with biologically realistic channel models, synapses and dendrites. This chip is suitable for small-scale network simulations and can also be used for sequence detection, utilizing directional selectivity properties of dendrites, ultimately for use in word recognition.

Performance of High-Speed PWM Control Chips at Cryogenic Temperatures

NASA Technical Reports Server (NTRS)

Elbuluk, Malik E.; Gerber, Scott; Hammoud, Ahmad; Patterson, Richard; Overton, Eric

2001-01-01

The operation of power electronic systems at cryogenic temperatures is anticipated in many NASA space missions such as planetary exploration and deep space probes. In addition to surviving the space hostile environment, electronics capable of low temperature operation would contribute to improving circuit performance, increasing system efficiency, and reducing development and launch costs. As part of the NASA Glenn Low Temperature Electronics Program, several commercial high-speed Pulse Width Modulation (PWM) chips have been characterized in terms of their performance as a function of temperature in the range of 25 to -196 C (liquid nitrogen). These chips ranged in their electrical characteristics, modes of control, packaging options, and applications. The experimental procedures along with the experimental data obtained on the investigated chips are presented and discussed.

Photometric and Colorimetric Assessment of LED Chip Scale Packages by Using a Step-Stress Accelerated Degradation Test (SSADT) Method.

PubMed

Qian, Cheng; Fan, Jiajie; Fang, Jiayi; Yu, Chaohua; Ren, Yi; Fan, Xuejun; Zhang, Guoqi

2017-10-16

By solving the problem of very long test time on reliability qualification for Light-emitting Diode (LED) products, the accelerated degradation test with a thermal overstress at a proper range is regarded as a promising and effective approach. For a comprehensive survey of the application of step-stress accelerated degradation test (SSADT) in LEDs, the thermal, photometric, and colorimetric properties of two types of LED chip scale packages (CSPs), i.e., 4000 °K and 5000 °K samples each of which was driven by two different levels of currents (i.e., 120 mA and 350 mA, respectively), were investigated under an increasing temperature from 55 °C to 150 °C and a systemic study of driving current effect on the SSADT results were also reported in this paper. During SSADT, junction temperatures of the test samples have a positive relationship with their driving currents. However, the temperature-voltage curve, which represents the thermal resistance property of the test samples, does not show significant variance as long as the driving current is no more than the sample's rated current. But when the test sample is tested under an overdrive current, its temperature-voltage curve is observed as obviously shifted to the left when compared to that before SSADT. Similar overdrive current affected the degradation scenario is also found in the attenuation of Spectral Power Distributions (SPDs) of the test samples. As used in the reliability qualification, SSADT provides explicit scenes on color shift and correlated color temperature (CCT) depreciation of the test samples, but not on lumen maintenance depreciation. It is also proved that the varying rates of the color shift and CCT depreciation failures can be effectively accelerated with an increase of the driving current, for instance, from 120 mA to 350 mA. For these reasons, SSADT is considered as a suitable accelerated test method for qualifying these two failure modes of LED CSPs.

Photometric and Colorimetric Assessment of LED Chip Scale Packages by Using a Step-Stress Accelerated Degradation Test (SSADT) Method

PubMed Central

Yu, Chaohua; Fan, Xuejun; Zhang, Guoqi

2017-01-01

By solving the problem of very long test time on reliability qualification for Light-emitting Diode (LED) products, the accelerated degradation test with a thermal overstress at a proper range is regarded as a promising and effective approach. For a comprehensive survey of the application of step-stress accelerated degradation test (SSADT) in LEDs, the thermal, photometric, and colorimetric properties of two types of LED chip scale packages (CSPs), i.e., 4000 °K and 5000 °K samples each of which was driven by two different levels of currents (i.e., 120 mA and 350 mA, respectively), were investigated under an increasing temperature from 55 °C to 150 °C and a systemic study of driving current effect on the SSADT results were also reported in this paper. During SSADT, junction temperatures of the test samples have a positive relationship with their driving currents. However, the temperature-voltage curve, which represents the thermal resistance property of the test samples, does not show significant variance as long as the driving current is no more than the sample’s rated current. But when the test sample is tested under an overdrive current, its temperature-voltage curve is observed as obviously shifted to the left when compared to that before SSADT. Similar overdrive current affected the degradation scenario is also found in the attenuation of Spectral Power Distributions (SPDs) of the test samples. As used in the reliability qualification, SSADT provides explicit scenes on color shift and correlated color temperature (CCT) depreciation of the test samples, but not on lumen maintenance depreciation. It is also proved that the varying rates of the color shift and CCT depreciation failures can be effectively accelerated with an increase of the driving current, for instance, from 120 mA to 350 mA. For these reasons, SSADT is considered as a suitable accelerated test method for qualifying these two failure modes of LED CSPs. PMID:29035300

Demonstration of a Packaged Capacitive Pressure Sensor System Suitable for Jet Turbofan Engine Health Monitoring

NASA Technical Reports Server (NTRS)

Scardelletti, Maximilian C.; Jordan, Jennifer L.; Meredith, Roger D.; Harsh, Kevin; Pilant, Evan; Usrey, Michael W.; Beheim, Glenn M.; Hunter, Gary W.; Zorman, Christian A.

2016-01-01

In this paper, the development and characterization of a packaged pressure sensor system suitable for jet engine health monitoring is demonstrated. The sensing system operates from 97 to 117 MHz over a pressure range from 0 to 350 psi and a temperature range from 25 to 500 deg. The sensing system consists of a Clapp-type oscillator that is fabricated on an alumina substrate and is comprised of a Cree SiC MESFET, MIM capacitors, a wire-wound inductor, chip resistors and a SiCN capacitive pressure sensor. The pressure sensor is located in the LC tank circuit of the oscillator so that a change in pressure causes a change in capacitance, thus changing the resonant frequency of the sensing system. The chip resistors, wire-wound inductors and MIM capacitors have all been characterized at temperature and operational frequency, and perform with less than 5% variance in electrical performance. The measured capacitive pressure sensing system agrees very well with simulated results. The packaged pressure sensing system is specifically designed to measure the pressure on a jet turbofan engine. The packaged system can be installed by way of borescope plug adaptor fitted to a borescope port exposed to the gas path of a turbofan engine.

Passive UHF RFID Tag with Multiple Sensing Capabilities

PubMed Central

Fernández-Salmerón, José; Rivadeneyra, Almudena; Martínez-Martí, Fernando; Capitán-Vallvey, Luis Fermín; Palma, Alberto J.; Carvajal, Miguel A.

2015-01-01

This work presents the design, fabrication, and characterization of a printed radio frequency identification tag in the ultra-high frequency band with multiple sensing capabilities. This passive tag is directly screen printed on a cardboard box with the aim of monitoring the packaging conditions during the different stages of the supply chain. This tag includes a commercial force sensor and a printed opening detector. Hence, the force applied to the package can be measured as well as the opening of the box can be detected. The architecture presented is a passive single-chip RFID tag. An electronic switch has been implemented to be able to measure both sensor magnitudes in the same access without including a microcontroller or battery. Moreover, the chip used here integrates a temperature sensor and, therefore, this tag provides three different parameters in every reading. PMID:26506353

Processing and Characterization of NiTi Shape Memory Alloy Particle Reinforced Sn-In Solders

DTIC Science & Technology

2006-12-01

solders generally operate at a high homologous temperature. Thermally induced grain growth, mechanical stress-induced grain growth and recrystallization ...the number of I/O connects available for flip chip as compared to the wirebond chip For interconnection and packaging, Pb-Sn and eutectic 63Sn...lower melting point is desired. The maximum use temperature for this alloy is around 120°C due to the fact that the eutectic reaction happened at

Fabrication and Qualification of Coated Chip-on-Board Technology for Miniaturized Space Systems

NASA Technical Reports Server (NTRS)

Maurer, R. H.; Le, B. Q.; Nhan, E.; Lew, A. L.; Darrin, M. Ann Garrison

1997-01-01

The results of a study carried out in order to manufacture and verify the quality of chip-on-board (COB) packaging technology are presented. The COB, designed for space applications, was tested under environmental stresses, temperature cycling, and temperature-humidity-bias. Both robustness in space applications and in environmental protection on the ground-complete reliability without hermeticity were searched for. The epoxy-parylene combinations proved to be superior to other materials tested.

Packaging's Contribution for the Effectiveness of the Space Station's Food Service Operation

NASA Technical Reports Server (NTRS)

Rausch, B. A.

1985-01-01

Storage limitations will have a major effect on space station food service. For example: foods with low bulk density such as ice cream, bread, cake, standard type potato chips and other low density snacks, flaked cereals, etc., will exacerbate the problem of space limitations; package containers are inherently volume consuming and refuse creating; and the useful observation that the optimum package is no package at all leads to the tentative conclusion that the least amount of packaging per unit of food, consistent with storage, aesthetics, preservation, cleanliness, cost and disposal criteria, is the most practical food package for the space station. A series of trade offs may have to be made to arrive at the most appropriate package design for a particular type of food taking all the criteria into account. Some of these trade offs are: single serve vs. bulk; conventional oven vs. microwave oven; nonmetallic aseptically vs. non-aseptically packaged foods; and comparison of aseptic vs. nonaseptic food packages. The advantages and disadvantages are discussed.

High Performance Hermetic Package For LiNbO3 Electro-Optic Waveguide Devices

NASA Astrophysics Data System (ADS)

Preston, K. R.; Macdonald, B. M.; Harmon, R. A.; Ford, C. W.; Shaw, R. N.; Reid, I.; Davidson, J. H.; Beaumont, A. R.; Booth, R. C.

1989-02-01

A high performance fibre-tailed package for LiNbO3 electro-optic waveguide devices is described. The package is based around a hermetic metal submodule which contains no epoxy or other organic materials. The LiNbO3 chip is mounted using a soldering technique, and laser welding is used for fibre fixing to give stable, low loss optical coupling to single mode fibres. Optical reflections are minimised by the use of antireflective coatings on the fibre ends and waveguide facets. High speed electrical connections are made via coplanar glass-sealed leadthroughs to LiNb03 travelling wave devices, and packaged device operation to frequencies in excess of 4GHz is demonstrated.

Physics of Failure Analysis of Xilinx Flip Chip CCGA Packages: Effects of Mission Environments on Properties of LP2 Underfill and ATI Lid Adhesive Materials

NASA Technical Reports Server (NTRS)

Suh, Jong-ook

2013-01-01

The Xilinx Virtex 4QV and 5QV (V4 and V5) are next-generation field-programmable gate arrays (FPGAs) for space applications. However, there have been concerns within the space community regarding the non-hermeticity of V4/V5 packages; polymeric materials such as the underfill and lid adhesive will be directly exposed to the space environment. In this study, reliability concerns associated with the non-hermeticity of V4/V5 packages were investigated by studying properties and behavior of the underfill and the lid adhesvie materials used in V4/V5 packages.

Thick photosensitive polyimide film side wall angle variability and scum improvement for IC packaging stress control

NASA Astrophysics Data System (ADS)

Mehta, Sohan Singh; Yeung, Marco; Mirza, Fahad; Raman, Thiagarajan; Longenbach, Travis; Morgan, Justin; Duggan, Mark; Soedibyo, Rio A.; Reidy, Sean; Rabie, Mohamed; Cho, Jae Kyu; Premachandran, C. S.; Faruqui, Danish

2018-03-01

In this paper, we demonstrate photosensitive polyimide (PSPI) profile optimization to effectively reduce stress concentrations and enable PSPI as protection package-induced stress. Through detailed package simulation, we demonstrate 45% reduction in stress as the sidewall angle (SWA) of PSPI is increased from 45 to 80 degrees in Cu pillar package types. Through modulation of coating and develop multi-step baking temperature and time, as well as dose energy and post litho surface treatments, we demonstrate a method for reliably obtaining PSPI sidewall angle >75 degree. Additionally, we experimentally validate the simulation findings that PSPI sidewall angle impacts chip package interaction (CPI). Finally, we conclude this paper with PSPI material and tool qualification requirements for future technology node based on current challenges.

Advanced large scale GaAs monolithic IF switch matrix subsystem

NASA Technical Reports Server (NTRS)

Ch'en, D. R.; Petersen, W. C.; Kiba, W. M.

1992-01-01

Attention is given to a novel chip design and packaging technique to overcome the limitations due to the high signal isolation requirements of advanced communications systems. A hermetically sealed 6 x 6 monolithic GaAs switch matrix subsystem with integral control electronics based on this technique is presented. An 0-dB insertion loss and 60-dB crosspoint isolation over a 3.5-to-6-GHz band were achieved. The internal controller portion of the switching subsystem provides crosspoint control via a standard RS-232 computer interface and can be synchronized with an external systems control computer. The measured performance of this advanced switching subsystem is fully compatible with relatively static 'switchboard' as well as dynamic TDMA modes of operation.

78 FR 42159 - Medicaid and Children's Health Insurance Programs: Essential Health Benefits in Alternative...

Federal Register 2010, 2011, 2012, 2013, 2014

2013-07-15

...This final rule implements provisions of the Patient Protection and Affordable Care Act and the Health Care and Education Reconciliation Act of 2010 (collectively referred to as the Affordable Care Act. This final rule finalizes new Medicaid eligibility provisions; finalizes changes related to electronic Medicaid and the Children's Health Insurance Program (CHIP) eligibility notices and delegation of appeals; modernizes and streamlines existing Medicaid eligibility rules; revises CHIP rules relating to the substitution of coverage to improve the coordination of CHIP coverage with other coverage; and amends requirements for benchmark and benchmark- equivalent benefit packages consistent with sections 1937 of the Social Security Act (which we refer to as ``alternative benefit plans'') to ensure that these benefit packages include essential health benefits and meet certain other minimum standards. This rule also implements specific provisions including those related to authorized representatives, notices, and verification of eligibility for qualifying coverage in an eligible employer-sponsored plan for Affordable Insurance Exchanges. This rule also updates and simplifies the complex Medicaid premium and cost sharing requirements, to promote the most effective use of services, and to assist states in identifying cost sharing flexibilities. It includes transition policies for 2014 as applicable.

SVGA and XGA active matrix microdisplays for head-mounted applications

NASA Astrophysics Data System (ADS)

Alvelda, Phillip; Bolotski, Michael; Brown, Imani L.

2000-03-01

The MicroDisplay Corporation's liquid crystal on silicon (LCOS) display devices are based on the union of several technologies with the extreme integration capability of conventionally fabricated CMOS substrates. The fast liquid crystal operation modes and new scalable high-performance pixel addressing architectures presented in this paper enable substantially improved color, contrast, and brightness while still satisfying the optical, packaging, and power requirements of portable applications. The entire suite of MicroDisplay's technologies was devised to create a line of mixed-signal application-specific integrated circuits (ASICs) in single-chip display systems. Mixed-signal circuits can integrate computing, memory, and communication circuitry on the same substrate as the display drivers and pixel array for a multifunctional complete system-on-a-chip. System-on-a-chip benefits also include reduced head supported weight requirements through the elimination of off-chip drive electronics.

Effect of Slice Error of Glass on Zero Offset of Capacitive Accelerometer

NASA Astrophysics Data System (ADS)

Hao, R.; Yu, H. J.; Zhou, W.; Peng, B.; Guo, J.

2018-03-01

Packaging process had been studied on capacitance accelerometer. The silicon-glass bonding process had been adopted on sensor chip and glass, and sensor chip and glass was adhered on ceramic substrate, the three-layer structure was curved due to the thermal mismatch, the slice error of glass lead to asymmetrical curve of sensor chip. Thus, the sensitive mass of accelerometer deviated along the sensitive direction, which was caused in zero offset drift. It was meaningful to confirm the influence of slice error of glass, the simulation results showed that the zero output drift was 12.3×10-3 m/s2 when the deviation was 40μm.

Self-Patterning of Silica/Epoxy Nanocomposite Underfill by Tailored Hydrophilic-Superhydrophobic Surfaces for 3D Integrated Circuit (IC) Stacking.

PubMed

Tuan, Chia-Chi; James, Nathan Pataki; Lin, Ziyin; Chen, Yun; Liu, Yan; Moon, Kyoung-Sik; Li, Zhuo; Wong, C P

2017-03-15

As microelectronics are trending toward smaller packages and integrated circuit (IC) stacks nowadays, underfill, the polymer composite filled in between the IC chip and the substrate, becomes increasingly important for interconnection reliability. However, traditional underfills cannot meet the requirements for low-profile and fine pitch in high density IC stacking packages. Post-applied underfills have difficulties in flowing into the small gaps between the chip and the substrate, while pre-applied underfills face filler entrapment at bond pads. In this report, we present a self-patterning underfilling technology that uses selective wetting of underfill on Cu bond pads and Si 3 N 4 passivation via surface energy engineering. This novel process, fully compatible with the conventional underfilling process, eliminates the issue of filler entrapment in typical pre-applied underfilling process, enabling high density and fine pitch IC die bonding.

SSI/MSI/LSI/VLSI/ULSI.

ERIC Educational Resources Information Center

Alexander, George

1984-01-01

Discusses small-scale integrated (SSI), medium-scale integrated (MSI), large-scale integrated (LSI), very large-scale integrated (VLSI), and ultra large-scale integrated (ULSI) chips. The development and properties of these chips, uses of gallium arsenide, Josephson devices (two superconducting strips sandwiching a thin insulator), and future…

Single-chip microprocessor that communicates directly using light

NASA Astrophysics Data System (ADS)

Sun, Chen; Wade, Mark T.; Lee, Yunsup; Orcutt, Jason S.; Alloatti, Luca; Georgas, Michael S.; Waterman, Andrew S.; Shainline, Jeffrey M.; Avizienis, Rimas R.; Lin, Sen; Moss, Benjamin R.; Kumar, Rajesh; Pavanello, Fabio; Atabaki, Amir H.; Cook, Henry M.; Ou, Albert J.; Leu, Jonathan C.; Chen, Yu-Hsin; Asanović, Krste; Ram, Rajeev J.; Popović, Miloš A.; Stojanović, Vladimir M.

2015-12-01

Data transport across short electrical wires is limited by both bandwidth and power density, which creates a performance bottleneck for semiconductor microchips in modern computer systems—from mobile phones to large-scale data centres. These limitations can be overcome by using optical communications based on chip-scale electronic-photonic systems enabled by silicon-based nanophotonic devices8. However, combining electronics and photonics on the same chip has proved challenging, owing to microchip manufacturing conflicts between electronics and photonics. Consequently, current electronic-photonic chips are limited to niche manufacturing processes and include only a few optical devices alongside simple circuits. Here we report an electronic-photonic system on a single chip integrating over 70 million transistors and 850 photonic components that work together to provide logic, memory, and interconnect functions. This system is a realization of a microprocessor that uses on-chip photonic devices to directly communicate with other chips using light. To integrate electronics and photonics at the scale of a microprocessor chip, we adopt a ‘zero-change’ approach to the integration of photonics. Instead of developing a custom process to enable the fabrication of photonics, which would complicate or eliminate the possibility of integration with state-of-the-art transistors at large scale and at high yield, we design optical devices using a standard microelectronics foundry process that is used for modern microprocessors. This demonstration could represent the beginning of an era of chip-scale electronic-photonic systems with the potential to transform computing system architectures, enabling more powerful computers, from network infrastructure to data centres and supercomputers.

Single-chip microprocessor that communicates directly using light.

PubMed

Sun, Chen; Wade, Mark T; Lee, Yunsup; Orcutt, Jason S; Alloatti, Luca; Georgas, Michael S; Waterman, Andrew S; Shainline, Jeffrey M; Avizienis, Rimas R; Lin, Sen; Moss, Benjamin R; Kumar, Rajesh; Pavanello, Fabio; Atabaki, Amir H; Cook, Henry M; Ou, Albert J; Leu, Jonathan C; Chen, Yu-Hsin; Asanović, Krste; Ram, Rajeev J; Popović, Miloš A; Stojanović, Vladimir M

2015-12-24

Data transport across short electrical wires is limited by both bandwidth and power density, which creates a performance bottleneck for semiconductor microchips in modern computer systems--from mobile phones to large-scale data centres. These limitations can be overcome by using optical communications based on chip-scale electronic-photonic systems enabled by silicon-based nanophotonic devices. However, combining electronics and photonics on the same chip has proved challenging, owing to microchip manufacturing conflicts between electronics and photonics. Consequently, current electronic-photonic chips are limited to niche manufacturing processes and include only a few optical devices alongside simple circuits. Here we report an electronic-photonic system on a single chip integrating over 70 million transistors and 850 photonic components that work together to provide logic, memory, and interconnect functions. This system is a realization of a microprocessor that uses on-chip photonic devices to directly communicate with other chips using light. To integrate electronics and photonics at the scale of a microprocessor chip, we adopt a 'zero-change' approach to the integration of photonics. Instead of developing a custom process to enable the fabrication of photonics, which would complicate or eliminate the possibility of integration with state-of-the-art transistors at large scale and at high yield, we design optical devices using a standard microelectronics foundry process that is used for modern microprocessors. This demonstration could represent the beginning of an era of chip-scale electronic-photonic systems with the potential to transform computing system architectures, enabling more powerful computers, from network infrastructure to data centres and supercomputers.

Platform technologies for hybrid optoelectronic integration and packaging

NASA Astrophysics Data System (ADS)

Datta, Madhumita

In order to bring fiber-optics closer to individual home and business services, the optical network components have to be inexpensive and reliable. Integration and packaging of optoelectronic devices holds the key to high-volume low-cost component manufacturing. The goal of this dissertation is to propose, study, and demonstrate various ways to integrate optoelectronic devices on a packaging platform to implement cost-effective, functional optical modules. Two types of hybrid integration techniques have been proposed: flip-chip solder bump bonding for high-density two-dimensional array packaging of surface-emitting devices, and solder preform bonding for fiber-coupled edge-emitting semiconductor devices. For flip-chip solder bump bonding, we developed a simple, inexpensive remetallization process called "electroless plating", which converts the aluminum bond pads of foundry-made complementary metal oxide semiconductor (CMOS) chips into solder-bondable and wire-bondable gold surfaces. We have applied for a patent on this remetallization technique. For fiber-pigtailed edge-emitting laser modules, we have studied the coupling characteristics of different types of lensed single-mode fibers including semispherically lensed fiber, cylindrically lensed fiber and conically lensed fiber. We have experimentally demonstrated 66% coupling efficiency with semispherically lensed fiber and 50% efficiency with conically lensed fibers. We have proposed and designed a packaging platform on which lensed fibers can be actively aligned to a laser and solder-attached reliably to the platform so that the alignment is retained. We have designed thin-film nichrome heaters on fused quartz platforms as local heat source to facilitate on-board solder alignment and attachment of fiber. The thermal performance of the heaters was simulated using finite element analysis tool ANSYS prior to fabrication. Using the heater's reworkability advantage, we have estimated the shift of the fiber due to solder shrinkage and introduced a pre-correction in the alignment process to restore optimum coupling efficiency close to 50% with conically lensed fibers. We have applied for a patent on this unique active alignment method through the University of Maryland's Technology Commercialization Office. Although we have mostly concentrated on active alignment platforms, we have proposed the idea of combining the passive alignment advantages of silicon optical benches to the on-board heater-assisted active alignment technique. This passive-active alignment process has the potential of cost-effective array packaging of edge-emitting devices.

Thermal-Aware Test Access Mechanism and Wrapper Design Optimization for System-on-Chips

NASA Astrophysics Data System (ADS)

Yu, Thomas Edison; Yoneda, Tomokazu; Chakrabarty, Krishnendu; Fujiwara, Hideo

Rapid advances in semiconductor manufacturing technology have led to higher chip power densities, which places greater emphasis on packaging and temperature control during testing. For system-on-chips, peak power-based scheduling algorithms have been used to optimize tests under specified power constraints. However, imposing power constraints does not always solve the problem of overheating due to the non-uniform distribution of power across the chip. This paper presents a TAM/Wrapper co-design methodology for system-on-chips that ensures thermal safety while still optimizing the test schedule. The method combines a simplified thermal-cost model with a traditional bin-packing algorithm to minimize test time while satisfying temperature constraints. Furthermore, for temperature checking, thermal simulation is done using cycle-accurate power profiles for more realistic results. Experiments show that even a minimal sacrifice in test time can yield a considerable decrease in test temperature as well as the possibility of further lowering temperatures beyond those achieved using traditional power-based test scheduling.

Effect of processing conditions on the quality characteristics of barley chips.

PubMed

Prakash, Jyoti; Naik, H R; Hussain, Syed Zameer; Singh, Baljit

2015-01-01

The aim of the present study was to study the effect of lime concentration, frying temperature and frying time on quality characteristics of barley chips. Effect of salt concentration and packaging material on the quality and stability of the product was also studied during 180 days of storage under ambient conditions. An increase in fat content of chips was observed with the increase in lime concentration, frying temperature and time, whereas a decreasing trend was observed in moisture content of chips. An increase in amylose content of chips was observed during frying. However, it was found that the amylopectin in chips decreased during frying as frying temperature and time was increased. An increase in colour difference (ΔE) and crispness was noted in chips during frying as frying temperature and time increased. With the increase in lime concentration (0.5 and 1.0 %) both ΔE and break force of chips was found decreased. The results further revealed that there was gradual decrease in fat (%) and amylopectin (%) during storage, whereas moisture (%) and amylose (%) increased during storage period. Organoleptic evaluation of the product revealed that scores of colour, texture, flavour and over all acceptability decrease during storage. However the treatment (salt 2 % and aluminium based laminate) recorded better score with respect to colour, flavour, texture and overall acceptability.

76 FR 14688 - In the Matter of Certain Large Scale Integrated Circuit Semiconductor Chips and Products...

Federal Register 2010, 2011, 2012, 2013, 2014

2011-03-17

... Integrated Circuit Semiconductor Chips and Products Containing the Same; Notice of a Commission Determination... certain large scale integrated circuit semiconductor chips and products containing same by reason of... existence of a domestic industry. The Commission's notice of investigation named several respondents...

Chip-scale sensor system integration for portable health monitoring.

PubMed

Jokerst, Nan M; Brooke, Martin A; Cho, Sang-Yeon; Shang, Allan B

2007-12-01

The revolution in integrated circuits over the past 50 yr has produced inexpensive computing and communications systems that are powerful and portable. The technologies for these integrated chip-scale sensing systems, which will be miniature, lightweight, and portable, are emerging with the integration of sensors with electronics, optical systems, micromachines, microfluidics, and the integration of chemical and biological materials (soft/wet material integration with traditional dry/hard semiconductor materials). Hence, we stand at a threshold for health monitoring technology that promises to provide wearable biochemical sensing systems that are comfortable, inauspicious, wireless, and battery-operated, yet that continuously monitor health status, and can transmit compressed data signals at regular intervals, or alarm conditions immediately. In this paper, we explore recent results in chip-scale sensor integration technology for health monitoring. The development of inexpensive chip-scale biochemical optical sensors, such as microresonators, that are customizable for high sensitivity coupled with rapid prototyping will be discussed. Ground-breaking work in the integration of chip-scale optical systems to support these optical sensors will be highlighted, and the development of inexpensive Si complementary metal-oxide semiconductor circuitry (which makes up the vast majority of computational systems today) for signal processing and wireless communication with local receivers that lie directly on the chip-scale sensor head itself will be examined.

Highly efficient on-chip direct electronic-plasmonic transducers

NASA Astrophysics Data System (ADS)

Du, Wei; Wang, Tao; Chu, Hong-Son; Nijhuis, Christian A.

2017-10-01

Photonic elements can carry information with a capacity exceeding 1,000 times that of electronic components, but, due to the optical diffraction limit, these elements are large and difficult to integrate with modern-day nanoelectronics or upcoming packages, such as three-dimensional integrated circuits or stacked high-bandwidth memories1-3. Surface plasmon polaritons can be confined to subwavelength dimensions and can carry information at high speeds (>100 THz)4-6. To combine the small dimensions of nanoelectronics with the fast operating speed of optics via plasmonics, on-chip electronic-plasmonic transducers that directly convert electrical signals into plasmonic signals (and vice versa) are required. Here, we report electronic-plasmonic transducers based on metal-insulator-metal tunnel junctions coupled to plasmonic waveguides with high-efficiency on-chip generation, manipulation and readout of plasmons. These junctions can be readily integrated into existing technologies, and we thus believe that they are promising for applications in on-chip integrated plasmonic circuits.

75 FR 24742 - In the Matter of Certain Large Scale Integrated Circuit Semiconductor Chips and Products...

Federal Register 2010, 2011, 2012, 2013, 2014

2010-05-05

... Integrated Circuit Semiconductor Chips and Products Containing Same; Notice of Investigation AGENCY: U.S... of certain large scale integrated circuit semiconductor chips and products containing same by reason... alleges that an industry in the United States exists as required by subsection (a)(2) of section 337. The...

The Chip-Scale Atomic Clock - Prototype Evaluation

DTIC Science & Technology

2007-11-01

39th Annual Precise Time and Time Interval (PTTI) Meeting THE CHIP-SCALE ATOMIC CLOCK – PROTOTYPE EVALUATION R. Lutwak *, A. Rashed...been supported by the Defense Advanced Research Projects Agency, Contract # NBCHC020050. REFERENCES [1] R. Lutwak , D. Emmons, W. Riley, and...D.C.), pp. 539-550. [2] R. Lutwak , D. Emmons, T. English, W. Riley, A. Duwel, M. Varghese, D. K. Serkland, and G. M. Peake, 2004, “The Chip-Scale

Wafer-to-wafer bonding of nonplanarized MEMS surfaces using solder

NASA Astrophysics Data System (ADS)

Sparks, D.; Queen, G.; Weston, R.; Woodward, G.; Putty, M.; Jordan, L.; Zarabadi, S.; Jayakar, K.

2001-11-01

The fabrication and reliability of a solder wafer-to-wafer bonding process is discussed. Using a solder reflow process allows vacuum packaging to be accomplished with unplanarized complementary metal-oxide semiconductor (CMOS) surface topography. This capability enables standard CMOS processes, and integrated microelectromechanical systems devices to be packaged at the chip-level. Alloy variations give this process the ability to bond at lower temperatures than most alternatives. Factors affecting hermeticity, shorts, Q values, shifting cavity pressure, wafer saw cleanliness and corrosion resistance will be covered.

Medicaid and Children's Health Insurance Programs: essential health benefits in alternative benefit plans, eligibility notices, fair hearing and appeal processes, and premiums and cost sharing; exchanges: eligibility and enrollment. Final rule.

PubMed

2013-07-15

This final rule implements provisions of the Patient Protection and Affordable Care Act and the Health Care and Education Reconciliation Act of 2010 (collectively referred to as the Affordable Care Act. This final rule finalizes new Medicaid eligibility provisions; finalizes changes related to electronic Medicaid and the Children's Health Insurance Program (CHIP) eligibility notices and delegation of appeals; modernizes and streamlines existing Medicaid eligibility rules; revises CHIP rules relating to the substitution of coverage to improve the coordination of CHIP coverage with other coverage; and amends requirements for benchmark and benchmark-equivalent benefit packages consistent with sections 1937 of the Social Security Act (which we refer to as ``alternative benefit plans'') to ensure that these benefit packages include essential health benefits and meet certain other minimum standards. This rule also implements specific provisions including those related to authorized representatives, notices, and verification of eligibility for qualifying coverage in an eligible employer-sponsored plan for Affordable Insurance Exchanges. This rule also updates and simplifies the complex Medicaid premium and cost sharing requirements, to promote the most effective use of services, and to assist states in identifying cost sharing flexibilities. It includes transition policies for 2014 as applicable.

A novel bonding method for large scale poly(methyl methacrylate) micro- and nanofluidic chip fabrication

NASA Astrophysics Data System (ADS)

Qu, Xingtian; Li, Jinlai; Yin, Zhifu

2018-04-01

Micro- and nanofluidic chips are becoming increasing significance for biological and medical applications. Future advances in micro- and nanofluidics and its utilization in commercial applications depend on the development and fabrication of low cost and high fidelity large scale plastic micro- and nanofluidic chips. However, the majority of the present fabrication methods suffer from a low bonding rate of the chip during thermal bonding process due to air trapping between the substrate and the cover plate. In the present work, a novel bonding technique based on Ar plasma and water treatment was proposed to fully bond the large scale micro- and nanofluidic chips. The influence of Ar plasma parameters on the water contact angle and the effect of bonding conditions on the bonding rate and the bonding strength of the chip were studied. The fluorescence tests demonstrate that the 5 × 5 cm2 poly(methyl methacrylate) chip with 180 nm wide and 180 nm deep nanochannels can be fabricated without any block and leakage by our newly developed method.

Effecting aging time of epoxy molding compound to molding process for integrated circuit packaging

NASA Astrophysics Data System (ADS)

Tachapitunsuk, Jirayu; Ugsornrat, Kessararat; Srisuwitthanon, Warayoot; Thonglor, Panakamon

2017-09-01

This research studied about effecting aging time of epoxy molding compound (EMC) that effect to reliability performance of integrated circuit (IC) package in molding process. Molding process is so important of IC packaging process for protecting IC chip (or die) from temperature and humidity environment using encapsulated EMC. For general molding process, EMC are stored in the frozen at 5°C and left at room temperature at 25 °C for aging time on self before molding of die onto lead frame is 24 hours. The aging time effect to reliability performance of IC package due to different temperature and humidity inside the package. In experiment, aging time of EMC were varied from 0 to 24 hours for molding process of SOIC-8L packages. For analysis, these packages were tested by x-ray and scanning acoustic microscope to analyze properties of EMC with an aging time and also analyzed delamination, internal void, and wire sweep inside the packages with different aging time. The results revealed that different aging time of EMC effect to properties and reliability performance of molding process.

A multi-scale PDMS fabrication strategy to bridge the size mismatch between integrated circuits and microfluidics†

PubMed Central

Muluneh, Melaku

2015-01-01

In recent years there has been great progress harnessing the small-feature size and programmability of integrated circuits (ICs) for biological applications, by building microfluidics directly on top of ICs. However, a major hurdle to the further development of this technology is the inherent size-mismatch between ICs (~mm) and microfluidic chips (~cm). Increasing the area of the ICs to match the size of the microfluidic chip, as has often been done in previous studies, leads to a waste of valuable space on the IC and an increase in fabrication cost (>100×). To address this challenge, we have developed a three dimensional PDMS chip that can straddle multiple length scales of hybrid IC/microfluidic chips. This approach allows millimeter-scale ICs, with no post-processing, to be integrated into a centimeter-sized PDMS chip. To fabricate this PDMS chip we use a combination of soft-lithography and laser micromachining. Soft lithography was used to define micrometer-scale fluid channels directly on the surface of the IC, allowing fluid to be controlled with high accuracy and brought into close proximity to sensors for highly sensitive measurements. Laser micromachining was used to create ~50 μm vias to connect these molded PDMS channels to a larger PDMS chip, which can connect multiple ICs and house fluid connections to the outside world. To demonstrate the utility of this approach, we built and demonstrated an in-flow magnetic cytometer that consisted of a 5 × 5 cm2 microfluidic chip that incorporated a commercial 565 × 1145 μm2 IC with a GMR sensing circuit. We additionally demonstrated the modularity of this approach by building a chip that incorporated two of these GMR chips connected in series. PMID:25284502

A multi-scale PDMS fabrication strategy to bridge the size mismatch between integrated circuits and microfluidics.

PubMed

Muluneh, Melaku; Issadore, David

2014-12-07

In recent years there has been great progress harnessing the small-feature size and programmability of integrated circuits (ICs) for biological applications, by building microfluidics directly on top of ICs. However, a major hurdle to the further development of this technology is the inherent size-mismatch between ICs (~mm) and microfluidic chips (~cm). Increasing the area of the ICs to match the size of the microfluidic chip, as has often been done in previous studies, leads to a waste of valuable space on the IC and an increase in fabrication cost (>100×). To address this challenge, we have developed a three dimensional PDMS chip that can straddle multiple length scales of hybrid IC/microfluidic chips. This approach allows millimeter-scale ICs, with no post-processing, to be integrated into a centimeter-sized PDMS chip. To fabricate this PDMS chip we use a combination of soft-lithography and laser micromachining. Soft lithography was used to define micrometer-scale fluid channels directly on the surface of the IC, allowing fluid to be controlled with high accuracy and brought into close proximity to sensors for highly sensitive measurements. Laser micromachining was used to create ~50 μm vias to connect these molded PDMS channels to a larger PDMS chip, which can connect multiple ICs and house fluid connections to the outside world. To demonstrate the utility of this approach, we built and demonstrated an in-flow magnetic cytometer that consisted of a 5 × 5 cm(2) microfluidic chip that incorporated a commercial 565 × 1145 μm(2) IC with a GMR sensing circuit. We additionally demonstrated the modularity of this approach by building a chip that incorporated two of these GMR chips connected in series.

Partition resampling and extrapolation averaging: approximation methods for quantifying gene expression in large numbers of short oligonucleotide arrays.

PubMed

Goldstein, Darlene R

2006-10-01

Studies of gene expression using high-density short oligonucleotide arrays have become a standard in a variety of biological contexts. Of the expression measures that have been proposed to quantify expression in these arrays, multi-chip-based measures have been shown to perform well. As gene expression studies increase in size, however, utilizing multi-chip expression measures is more challenging in terms of computing memory requirements and time. A strategic alternative to exact multi-chip quantification on a full large chip set is to approximate expression values based on subsets of chips. This paper introduces an extrapolation method, Extrapolation Averaging (EA), and a resampling method, Partition Resampling (PR), to approximate expression in large studies. An examination of properties indicates that subset-based methods can perform well compared with exact expression quantification. The focus is on short oligonucleotide chips, but the same ideas apply equally well to any array type for which expression is quantified using an entire set of arrays, rather than for only a single array at a time. Software implementing Partition Resampling and Extrapolation Averaging is under development as an R package for the BioConductor project.

Construction of large scale switch matrix by interconnecting integrated optical switch chips with EDFAs

NASA Astrophysics Data System (ADS)

Liao, Mingle; Wu, Baojian; Hou, Jianhong; Qiu, Kun

2018-03-01

Large scale optical switches are essential components in optical communication network. We aim to build up a large scale optical switch matrix by the interconnection of silicon-based optical switch chips using 3-stage CLOS structure, where EDFAs are needed to compensate for the insertion loss of the chips. The optical signal-to-noise ratio (OSNR) performance of the resulting large scale optical switch matrix is investigated for TE-mode light and the experimental results are in agreement with the theoretical analysis. We build up a 64 ×64 switch matrix by use of 16 ×16 optical switch chips and the OSNR and receiver sensibility can respectively be improved by 0.6 dB and 0.2 dB by optimizing the gain configuration of the EDFAs.

Development Of A Three-Dimensional Circuit Integration Technology And Computer Architecture

NASA Astrophysics Data System (ADS)

Etchells, R. D.; Grinberg, J.; Nudd, G. R.

1981-12-01

This paper is the first of a series 1,2,3 describing a range of efforts at Hughes Research Laboratories, which are collectively referred to as "Three-Dimensional Microelectronics." The technology being developed is a combination of a unique circuit fabrication/packaging technology and a novel processing architecture. The packaging technology greatly reduces the parasitic impedances associated with signal-routing in complex VLSI structures, while simultaneously allowing circuit densities orders of magnitude higher than the current state-of-the-art. When combined with the 3-D processor architecture, the resulting machine exhibits a one- to two-order of magnitude simultaneous improvement over current state-of-the-art machines in the three areas of processing speed, power consumption, and physical volume. The 3-D architecture is essentially that commonly referred to as a "cellular array", with the ultimate implementation having as many as 512 x 512 processors working in parallel. The three-dimensional nature of the assembled machine arises from the fact that the chips containing the active circuitry of the processor are stacked on top of each other. In this structure, electrical signals are passed vertically through the chips via thermomigrated aluminum feedthroughs. Signals are passed between adjacent chips by micro-interconnects. This discussion presents a broad view of the total effort, as well as a more detailed treatment of the fabrication and packaging technologies themselves. The results of performance simulations of the completed 3-D processor executing a variety of algorithms are also presented. Of particular pertinence to the interests of the focal-plane array community is the simulation of the UNICORNS nonuniformity correction algorithms as executed by the 3-D architecture.

Nonvolatile memory chips: critical technology for high-performance recce systems

NASA Astrophysics Data System (ADS)

Kaufman, Bruce

2000-11-01

Airborne recce systems universally require nonvolatile storage of recorded data. Both present and next generation designs make use of flash memory chips. Flash memory devices are in high volume use for a variety of commercial products ranging form cellular phones to digital cameras. Fortunately, commercial applications call for increasing capacities and fast write times. These parameters are important to the designer of recce recorders. Of economic necessity COTS devices are used in recorders that must perform in military avionics environments. Concurrently, recording rates are moving to $GTR10Gb/S. Thus to capture imagery for even a few minutes of record time, tactically meaningful solid state recorders will require storage capacities in the 100s of Gbytes. Even with memory chip densities at present day 512Mb, such capacities require thousands of chips. The demands on packaging technology are daunting. This paper will consider the differing flash chip architectures, both available and projected and discuss the impact on recorder architecture and performance. Emerging nonvolatile memory technologies, FeRAM AND MIRAM will be reviewed with regard to their potential use in recce recorders.

Silver free III-nitride flip chip light-emitting-diode with wall plug efficiency over 70% utilizing a GaN tunnel junction

NASA Astrophysics Data System (ADS)

Yonkee, B. P.; Young, E. C.; DenBaars, S. P.; Nakamura, S.; Speck, J. S.

2016-11-01

A molecular beam epitaxy regrowth technique was demonstrated on standard industrial patterned sapphire substrate light-emitting diode (LED) epitaxial wafers emitting at 455 nm to form a GaN tunnel junction. By using an HF pretreatment on the wafers before regrowth, a voltage of 3.08 V at 20 A/cm2 was achieved on small area devices. A high extraction package was developed for comparison with flip chip devices which utilize an LED floating in silicone over a BaSO4 coated header and produced a peak external quantum efficiency (EQE) of 78%. A high reflectivity mirror was designed using a seven-layer dielectric coating backed by aluminum which has a calculated angular averaged reflectivity over 98% between 400 and 500 nm. This was utilized to fabricate a flip chip LED which had a peak EQE and wall plug efficiency of 76% and 73%, respectively. This flip chip could increase light extraction over a traditional flip chip LED due to the increased reflectivity of the dielectric based mirror.

A novel readout integrated circuit for ferroelectric FPA detector

NASA Astrophysics Data System (ADS)

Bai, Piji; Li, Lihua; Ji, Yulong; Zhang, Jia; Li, Min; Liang, Yan; Hu, Yanbo; Li, Songying

2017-11-01

Uncooled infrared detectors haves some advantages such as low cost light weight low power consumption, and superior reliability, compared with cryogenically cooled ones Ferroelectric uncooled focal plane array(FPA) are being developed for its AC response and its high reliability As a key part of the ferroelectric assembly the ROIC determines the performance of the assembly. A top-down design model for uncooled ferroelectric readout integrated circuit(ROIC) has been developed. Based on the optical thermal and electrical properties of the ferroelectric detector the RTIA readout integrated circuit is designed. The noise bandwidth of RTIA readout circuit has been developed and analyzed. A novel high gain amplifier, a high pass filter and a low pass filter circuits are designed on the ROIC. In order to improve the ferroelectric FPA package performance and decrease of package cost a temperature sensor is designed on the ROIC chip At last the novel RTIA ROIC is implemented on 0.6μm 2P3M CMOS silicon techniques. According to the experimental chip test results the temporal root mean square(RMS)noise voltage is about 1.4mV the sensitivity of the on chip temperature sensor is 0.6 mV/K from -40°C to 60°C the linearity performance of the ROIC chip is better than 99% Based on the 320×240 RTIA ROIC, a 320×240 infrared ferroelectric FPA is fabricated and tested. Test results shows that the 320×240 RTIA ROIC meets the demand of infrared ferroelectric FPA.

Chip-scale integrated optical interconnects: a key enabler for future high-performance computing

NASA Astrophysics Data System (ADS)

Haney, Michael; Nair, Rohit; Gu, Tian

2012-01-01

High Performance Computing (HPC) systems are putting ever-increasing demands on the throughput efficiency of their interconnection fabrics. In this paper, the limits of conventional metal trace-based inter-chip interconnect fabrics are examined in the context of state-of-the-art HPC systems, which currently operate near the 1 GFLOPS/W level. The analysis suggests that conventional metal trace interconnects will limit performance to approximately 6 GFLOPS/W in larger HPC systems that require many computer chips to be interconnected in parallel processing architectures. As the HPC communications bottlenecks push closer to the processing chips, integrated Optical Interconnect (OI) technology may provide the ultra-high bandwidths needed at the inter- and intra-chip levels. With inter-chip photonic link energies projected to be less than 1 pJ/bit, integrated OI is projected to enable HPC architecture scaling to the 50 GFLOPS/W level and beyond - providing a path to Peta-FLOPS-level HPC within a single rack, and potentially even Exa-FLOPSlevel HPC for large systems. A new hybrid integrated chip-scale OI approach is described and evaluated. The concept integrates a high-density polymer waveguide fabric directly on top of a multiple quantum well (MQW) modulator array that is area-bonded to the Silicon computing chip. Grayscale lithography is used to fabricate 5 μm x 5 μm polymer waveguides and associated novel small-footprint total internal reflection-based vertical input/output couplers directly onto a layer containing an array of GaAs MQW devices configured to be either absorption modulators or photodetectors. An external continuous wave optical "power supply" is coupled into the waveguide links. Contrast ratios were measured using a test rider chip in place of a Silicon processing chip. The results suggest that sub-pJ/b chip-scale communication is achievable with this concept. When integrated into high-density integrated optical interconnect fabrics, it could provide a seamless interconnect fabric spanning the intra-

Silicon-based products and solutions

NASA Astrophysics Data System (ADS)

Painchaud, Y.; Poulin, M.; Pelletier, F.; Latrasse, C.; Gagné, J.-F.; Savard, S.; Robidoux, G.; Picard, M.-.; Paquet, S.; Davidson, C.-.; Pelletier, M.; Cyr, M.; Paquet, C.; Guy, M.; Morsy-Osman, M.; Chagnon, M.; Plant, D. V.

2014-03-01

TeraXion started silicon photonics activities aiming at developing building blocks for new products and customized solutions. Passive and active devices have been developed including MMI couplers, power splitters, Bragg grating filters, high responsivity photodetectors, high speed modulators and variable optical attenuators. Packaging solutions including fiber attachment and hybrid integration using flip-chip were also developed. More specifically, a compact packaged integrated coherent receiver has been realized. Good performances were obtained as demonstrated by our system tests results showing transmission up to 4800 km with BER below hard FEC threshold. The package size is small but still limited by the electrical interface. Migrating to more compact RF interface would allow realizing the full benefit of this technology.

Indium phosphide-based monolithically integrated PIN waveguide photodiode readout for resonant cantilever sensors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Siwak, N. P.; Laboratory for the Physical Sciences, 8050 Greenmead Drive, College Park, Maryland 20740; Fan, X. Z.

2014-10-06

An integrated photodiode displacement readout scheme for a microelectromechanical cantilever waveguide resonator sensing platform is presented. III-V semiconductors are used to enable the monolithic integration of passive waveguides with active optical components. This work builds upon previously demonstrated results by measuring the displacement of cantilever waveguide resonators with on-chip waveguide PIN photodiodes. The on-chip integration of the readout provides an additional 70% improvement in mass sensitivity compared to off-chip photodetector designs due to measurement stability and minimized coupling loss. In addition to increased measurement stability, reduced packaging complexity is achieved due to the simplicity of the readout design. We havemore » fabricated cantilever waveguides with integrated photodetectors and experimentally characterized these cantilever sensors with monolithically integrated PIN photodiodes.« less

Perforated hollow-core optical waveguides for on-chip atomic spectroscopy and gas sensing

DOE Office of Scientific and Technical Information (OSTI.GOV)

Giraud-Carrier, M., E-mail: mgeecee@byu.edu; Hill, C.; Decker, T.

2016-03-28

A hollow-core waveguide structure for on-chip atomic spectroscopy is presented. The devices are based on Anti-Resonant Reflecting Optical Waveguides and may be used for a wide variety of applications which rely on the interaction of light with gases and vapors. The designs presented here feature short delivery paths of the atomic vapor into the hollow waveguide. They also have excellent environmental stability by incorporating buried solid-core waveguides to deliver light to the hollow cores. Completed chips were packaged with an Rb source and the F = 3 ≥ F′ = 2, 3, 4 transitions of the D2 line in {sup 85}Rb were monitored formore » optical absorption. Maximum absorption peak depths of 9% were measured.« less

QTL mapping of potato chip color and tuber traits within an autotetraploid family

USDA-ARS?s Scientific Manuscript database

Cultivated potato (Solanum tuberosum L.) is a highly heterozygous autotetraploid crop species, and this presents challenges for traditional line development and molecular breeding. Recent availability of a single nucleotide polymorphism (SNP) array with 8303 features and software packages for linkag...

Mechanism of Void Prediction in Flip Chip Packages with Molded Underfill

NASA Astrophysics Data System (ADS)

Wu, Kuo-Tsai; Hwang, Sheng-Jye; Lee, Huei-Huang

2017-08-01

Voids have always been present using the molded underfill (MUF) package process, which is a problem that needs further investigation. In this study, the process was studied using the Moldex3D numerical analysis software. The effects of gas (air vent effect) on the overall melt front were also considered. In this isothermal process containing two fluids, the gas and melt colloid interact in the mold cavity. Simulation enabled an appropriate understanding of the actual situation to be gained, and, through analysis, the void region and exact location of voids were predicted. First, the global flow end area was observed to predict the void movement trend, and then the local flow ends were observed to predict the location and size of voids. In the MUF 518 case study, simulations predicted the void region as well as the location and size of the voids. The void phenomenon in a flip chip ball grid array underfill is discussed as part of the study.

Fabrication method to create high-aspect ratio pillars for photonic coupling of board level interconnects

NASA Astrophysics Data System (ADS)

Debaes, C.; Van Erps, J.; Karppinen, M.; Hiltunen, J.; Suyal, H.; Last, A.; Lee, M. G.; Karioja, P.; Taghizadeh, M.; Mohr, J.; Thienpont, H.; Glebov, A. L.

2008-04-01

An important challenge that remains to date in board level optical interconnects is the coupling between the optical waveguides on printed wiring boards and the packaged optoelectronics chips, which are preferably surface mountable on the boards. One possible solution is the use of Ball Grid Array (BGA) packages. This approach offers a reliable attachment despite the large CTE mismatch between the organic FR4 board and the semiconductor materials. Collimation via micro-lenses is here typically deployed to couple the light vertically from the waveguide substrate to the optoelectronics while allowing for a small misalignment between board and package. In this work, we explore the fabrication issues of an alternative approach in which the vertical photonic connection between board and package is governed by a micro-optical pillar which is attached both to the board substrate and to the optoelectronic chips. Such an approach allows for high density connections and small, high-speed detector footprints while maintaining an acceptable tolerance between board and package. The pillar should exhibit some flexibility and thus a high-aspect ratio is preferred. This work presents and compares different fabrication methods and applies different materials for such high-aspect ratio pillars. The different fabrication methods are: photolithography, direct laser writing and deep proton writing. The selection of optical materials that was investigated is: SU8, Ormocers, PU and a multifunctional acrylate polymer. The resulting optical pillars have diameters ranging from 20um up to 80um, with total heights ranging between 30um and 100um (symbol for micron). The aspect-ratio of the fabricated structures ranges from 1.5 to 5.

27 CFR 19.276 - Package scales.

Code of Federal Regulations, 2010 CFR

2010-04-01

... 27 Alcohol, Tobacco Products and Firearms 1 2010-04-01 2010-04-01 false Package scales. 19.276... Package scales. Proprietors shall ensure the accuracy of scales used for weighing packages of spirits through tests conducted at intervals of not more than 6 months or whenever scales are adjusted or repaired...

Crossmodal correspondences in product packaging. Assessing color-flavor correspondences for potato chips (crisps).

PubMed

Piqueras-Fiszman, Betina; Spence, Charles

2011-12-01

We report a study designed to investigate consumers' crossmodal associations between the color of packaging and flavor varieties in crisps (potato chips). This product category was chosen because of the long-established but conflicting color-flavor conventions that exist for the salt and vinegar and cheese and onion flavor varieties in the UK. The use of both implicit and explicit measures of this crossmodal association revealed that consumers responded more slowly, and made more errors, when they had to pair the color and flavor that they implicitly thought of as being "incongruent" with the same response key. Furthermore, clustering consumers by the brand that they normally purchased revealed that the main reason why this pattern of results was observed could be their differing acquaintance with one brand versus another. In addition, when participants tried the two types of crisps from "congruently" and "incongruently" colored packets, some were unable to guess the flavor correctly in the latter case. These strong crossmodal associations did not have a significant effect on participants' hedonic appraisal of the crisps, but did arouse confusion. These results are relevant in terms of R&D, since ascertaining the appropriate color of the packaging across flavor varieties ought normally to help achieve immediate product recognition and consumer satisfaction. Copyright © 2011 Elsevier Ltd. All rights reserved.

A Reduced Order Model for Whole-Chip Thermal Analysis of Microfluidic Lab-on-a-Chip Systems

PubMed Central

Wang, Yi; Song, Hongjun; Pant, Kapil

2013-01-01

This paper presents a Krylov subspace projection-based Reduced Order Model (ROM) for whole microfluidic chip thermal analysis, including conjugate heat transfer. Two key steps in the reduced order modeling procedure are described in detail, including (1) the acquisition of a 3D full-scale computational model in the state-space form to capture the dynamic thermal behavior of the entire microfluidic chip; and (2) the model order reduction using the Block Arnoldi algorithm to markedly lower the dimension of the full-scale model. Case studies using practically relevant thermal microfluidic chip are undertaken to establish the capability and to evaluate the computational performance of the reduced order modeling technique. The ROM is compared against the full-scale model and exhibits good agreement in spatiotemporal thermal profiles (<0.5% relative error in pertinent time scales) and over three orders-of-magnitude acceleration in computational speed. The salient model reusability and real-time simulation capability renders it amenable for operational optimization and in-line thermal control and management of microfluidic systems and devices. PMID:24443647

Development and psychometric properties of the Carer - Head Injury Neurobehavioral Assessment Scale (C-HINAS) and the Carer - Head Injury Participation Scale (C-HIPS): patient and family determined outcome scales.

PubMed

Deb, Shoumitro; Bryant, Eleanor; Morris, Paul G; Prior, Lindsay; Lewis, Glyn; Haque, Sayeed

2007-06-01

Develop and assess the psychometric properties of the Carer - Head Injury Participation Scale (C-HIPS) and its biggest factor the Carer - Head Injury Neurobehavioral Assessment Scale (C-HINAS). Furthermore, the aim was to examine the inter-informant reliability by comparing the self reports of individuals with traumatic brain injury (TBI) with the carer reports on the C-HIPS and the C-HINAS. Thirty-two TBI individuals and 27 carers took part in in-depth qualitative interviews exploring the consequences of the TBI. Interview transcripts were analysed and key themes and concepts were used to construct a 49-item and 58-item patient (Patient - Head Injury Participation Scale [P-HIPS]) and carer outcome measure (C-HIPS) respectively, of which 49 were parallel items and nine additional items were used to assess carer burden. Postal versions of the P-HIPS, C-HIPS, Mayo Portland Adaptability Inventory-3 (MPAI-3), and the Glasgow Outcome Scale-Extended (GOSE) were completed by a cohort of 113 TBI individuals and 80 carers. Data from a sub-group of 66 patient/carer pairs were used to compare inter-informant reliability between the P-HIPS and the C-HIPS, and the P-HINAS and the C-HINAS respectively. All individual 49 items of the C-HIPS and their total score showed good test-retest reliability (0.95) and internal consistency (0.95). Comparisons with the MPAI-3 and GOSE found a good correlation with the MPAI-3 (0.7) and a moderate negative correlation with the GOSE (-0.6). Factor analysis of these items extracted a 4-factor structure which represented the domains 'Emotion/Behavior' (C-HINAS), 'Independence/Community Living', 'Cognition', and 'Physical'. The C-HINAS showed good internal consistency (0.92), test-retest reliability (0.93), and concurrent validity with one MPAI subscale (0.7). Assessment of inter-informant reliability revealed good correspondence between the reports of the patients and the carers for both the C-HIPS (0.83) and the C-HINAS (0.82). Both the C-HINAS and the C-HIPS show strong psychometric properties. The qualitative methodology employed in the construction stage of the questionnaires provided good evidence of face and content validity. Comparisons between the P-HIPS and the C-HIPS, and the P-HINAS and the C-HINAS indicated high levels of agreement suggesting that in situations where the patient is unable to provide self-reports, information provided by the carer could be used.

Extremely Low Frequency-Magnetic Field (ELF-MF) Exposure Characteristics among Semiconductor Workers

PubMed Central

Choi, Sangjun; Cha, Wonseok; Kim, Won; Yoon, Chungsik; Park, Ju-Hyun; Ha, Kwonchul; Park, Donguk

2018-01-01

We assessed the exposure of semiconductor workers to extremely low frequency-magnetic fields (ELF-MF) and identified job characteristics affecting ELF-MF exposure. These were demonstrated by assessing the exposure of 117 workers involved in wafer fabrication (fab) and chip packaging wearing personal dosimeters for a full shift. A portable device was used to monitor ELF-MF in high temporal resolution. All measurements were categorized by operation, job and working activity during working time. ELF-MF exposure of workers were classified based on the quartiles of ELF-MF distribution. The average levels of ELF-MF exposure were 0.56 µT for fab workers, 0.59 µT for chip packaging workers and 0.89 µT for electrical engineers, respectively. Exposure to ELF-MF differed among types of factory, operation, job and activity. Workers engaged in the diffusion and chip testing activities showed the highest ELF-MF exposure. The ELF-MF exposures of process operators were found to be higher than those of maintenance engineers, although peak exposure and/or patterns varied. The groups with the highest quartile ELF-MF exposure level are operators in diffusion, ion implantation, module and testing operations, and maintenance engineers in diffusion, module and testing operations. In conclusion, ELF-MF exposure among workers can be substantially affected by the type of operation and job, and the activity or location. PMID:29614730

An implantable myoelectric sensor based prosthesis control system.

PubMed

DeMichele, Glenn A; Troyk, Philip R; Kerns, Douglas A; Weir, Richard

2006-01-01

We present progress on the design and testing of an upper-extremity prosthesis control system based on implantable myoelectric sensors. The implant consists of a single silicon chip packaged with transmit and receive coils. Forward control telemetry to, and reverse EMG data telemetry from multiple implants has been demonstrated.

Evaluation of advanced microelectronic fluxless solder-bump contacts for hybrid microcircuits

NASA Technical Reports Server (NTRS)

Mandal, R. P.

1976-01-01

Technology for interconnecting monolithic integrated circuit chips with other components is investigated. The advantages and disadvantages of the current flip-chip approach as compared to other interconnection methods are outlined. A fluxless solder-bump contact technology is evaluated. Multiple solder-bump contacts were formed on silicon integrated circuit chips. The solder-bumps, comprised of a rigid nickel under layer and a compliant solder overlayer, were electroformed onto gold device pads with the aid of thick dry film photomasks. Different solder alloys and the use of conductive epoxy for bonding were explored. Fluxless solder-bump bond quality and reliability were evaluated by measuring the effects of centrifuge, thermal cycling, and high temperature storage on bond visual characteristics, bond electrical continuity, and bond shear tests. The applicability and suitability of this technology for hybrid microelectronic packaging is discussed.

Convenience stores and the marketing of foods and beverages through product assortment.

PubMed

Sharkey, Joseph R; Dean, Wesley R; Nalty, Courtney

2012-09-01

Product assortment (presence and variety) is a key in-store marketing strategy to influence consumer choice. Quantifying the product assortment of healthier and less-healthy foods and beverages in convenience stores can inform changes in the food environment. To document product assortment (i.e., presence and variety of specific foods and beverages) in convenience stores. Observational survey data were collected onsite in 2011 by trained promotora-researchers in 192 convenience stores. Frequencies of presence and distributions of variety were calculated in 2012. Paired differences were examined using the Wilcoxon matched-pairs signed-rank test. Convenience stores displayed a large product assortment of sugar-sweetened beverages (median 86.5 unique varieties); candy (76 varieties); salty snacks (77 varieties); fried chips (44 varieties); cookies and pastries (19 varieties); and frozen sweets (21 varieties). This compared with 17 varieties of non-sugar sweetened beverages and three varieties of baked chips. The Wilcoxon signed-rank test confirmed a (p<0.001) greater variety of sugar-sweetened than non-sugar-sweetened beverages, and of fried chips compared with baked chips. Basic food items provided by convenience stores included milk (84% of stores); fresh fruit (33%); fresh vegetables (35%); canned vegetables (78%); white bread (71%); and deli-style packaged meat (57%). Healthier versions of milk, canned fruit, canned tuna, bread, and deli-style packaged meat were displayed in 17%-71% of convenience stores. Convenience stores in this area provide a greater assortment of less-healthy compared with healthier foods and beverages. There are opportunities to influence consumer food choice through programs that alter the balance between healthier and less-healthy foods and beverages in existing convenience stores that serve rural and underserved neighborhoods and communities. Copyright © 2012 American Journal of Preventive Medicine. Published by Elsevier Inc. All rights reserved.

Multi-scale reflection modulator-based optical interconnects

NASA Astrophysics Data System (ADS)

Nair, Rohit

This dissertation describes the design, analysis, and experimental validation of micro- and macro-optical components for implementing optical interconnects at multiple scales for varied applications. Three distance scales are explored: millimeter, centimeter, and meter-scales. At the millimeter-scale, we propose the use of optical interconnects at the intra-chip level. With the rapid scaling down of CMOS critical dimensions in accordance to Moore's law, the bandwidth requirements of global interconnects in microprocessors has exceeded the capabilities of metal links. These are the wires that connect the most remote parts of the chip and are disproportionately problematic in terms of chip area and power consumption. Consequently, in the mid-2000s, we saw a shift in the chip architecture: a move towards multicore designs. However, this only delays the inevitable communication bottleneck between cores. To satisfy this bandwidth, we propose to replace the global metal interconnects with optical interconnects. We propose to use the hybrid integration of silicon with GaAs/AlAs-based multiple quantum well devices as optical modulators and photodetectors along with polymeric waveguides to transport the light. We use grayscale lithography to fabricate curved facets into the waveguides to couple light into the modulators and photodetectors. Next, at the chip-to-chip level in high-performance multiprocessor computing systems, communication distances vary from a few centimeters to tens of centimeters. An optical design for coupling light from off-chip lasers to on-chip surface-normal modulators is proposed in order to implement chip-to-chip free-space optical interconnects. The method uses a dual-prism module constructed from prisms made of two different glasses. The various alignment tolerances of the proposed system are investigated and found to be well within pick-and-place accuracies. For the off-chip lasers, vertical cavity surface emitting lasers (VCSELs) are proposed. The rationale behind using on-chip modulators rather than VCSELs is to avoid VCSEL thermal loads on chip, and because of higher reliability of modulators than VCSELs. Particularly above 10Gbps, an empirical model developed shows the rapid decrease of VCSEL median time to failure vs. data rate. Thus the proposed interconnect scheme which utilizes continuous wave VCSELs that are externally modulated by on-chip multiple quantum well modulators is applicable for chip-to-chip optical interconnects at 20Gbps and higher line data rates. Finally, for applications such as remote telemetry, where the interrogation distances can vary from a few meters to tens or even hundreds of meters we demonstrate a modulated retroreflector that utilizes InGaAs/InAlAs-based large-area multiple quantum well modulators on all three faces of a retroreflector. The large-area devices, fabricated by metalorganic chemical vapor deposition, are characterized in terms of the yield and leakage currents. A yield higher than that achieved previously using devices fabricated by molecular beam epitaxy is observed. The retroreflector module is constructed using standard FR4 printed circuit boards, thereby simplifying the wiring issue. A high optical contrast ratio of 8.23dB is observed for a drive of 20V. A free-standing PCB retroreflector is explored and found to have insufficient angular tolerances (+/-0.5 degrees). We show that the angular errors in the corner-cube construction can be corrected for using off-the-shelf optical components as opposed to mounting the PCBs on a precision corner cube, as has been done previously.

High performance digital read out integrated circuit (DROIC) for infrared imaging

NASA Astrophysics Data System (ADS)

Mizuno, Genki; Olah, Robert; Oduor, Patrick; Dutta, Achyut K.; Dhar, Nibir K.

2016-05-01

Banpil Photonics has developed a high-performance Digital Read-Out Integrated Circuit (DROIC) for image sensors and camera systems targeting various military, industrial and commercial Infrared (IR) imaging applications. The on-chip digitization of the pixel output eliminates the necessity for an external analog-to-digital converter (ADC), which not only cuts costs, but also enables miniaturization of packaging to achieve SWaP-C camera systems. In addition, the DROIC offers new opportunities for greater on-chip processing intelligence that are not possible in conventional analog ROICs prevalent today. Conventional ROICs, which typically can enhance only one high performance attribute such as frame rate, power consumption or noise level, fail when simultaneously targeting the most aggressive performance requirements demanded in imaging applications today. Additionally, scaling analog readout circuits to meet such requirements leads to expensive, high-power consumption with large and complex systems that are untenable in the trend towards SWaP-C. We present the implementation of a VGA format (640x512 pixels 15μm pitch) capacitivetransimpedance amplifier (CTIA) DROIC architecture that incorporates a 12-bit ADC at the pixel level. The CTIA pixel input circuitry has two gain modes with programmable full-well capacity values of 100K e- and 500K e-. The DROIC has been developed with a system-on-chip architecture in mind, where all the timing and biasing are generated internally without requiring any critical external inputs. The chip is configurable with many parameters programmable through a serial programmable interface (SPI). It features a global shutter, low power, and high frame rates programmable from 30 up 500 frames per second in full VGA format supported through 24 LVDS outputs. This DROIC, suitable for hybridization with focal plane arrays (FPA) is ideal for high-performance uncooled camera applications ranging from near IR (NIR) and shortwave IR (SWIR) to mid-wave IR (MWIR) and long-wave IR (LWIR) spectral bands.

Mathematical Simulation for Integrated Linear Fresnel Spectrometer Chip

NASA Technical Reports Server (NTRS)

Park, Yeonjoon; Yoon, Hargoon; Lee, Uhn; King, Glen C.; Choi, Sang H.

2012-01-01

A miniaturized solid-state optical spectrometer chip was designed with a linear gradient-gap Fresnel grating which was mounted perpendicularly to a sensor array surface and simulated for its performance and functionality. Unlike common spectrometers which are based on Fraunhoffer diffraction with a regular periodic line grating, the new linear gradient grating Fresnel spectrometer chip can be miniaturized to a much smaller form-factor into the Fresnel regime exceeding the limit of conventional spectrometers. This mathematical calculation shows that building a tiny motionless multi-pixel microspectrometer chip which is smaller than 1 cubic millimter of optical path volume is possible. The new Fresnel spectrometer chip is proportional to the energy scale (hc/lambda), while the conventional spectrometers are proportional to the wavelength scale (lambda). We report the theoretical optical working principle and new data collection algorithm of the new Fresnel spectrometer to build a compact integrated optical chip.

On the release of cppxfel for processing X-ray free-electron laser images.

PubMed

Ginn, Helen Mary; Evans, Gwyndaf; Sauter, Nicholas K; Stuart, David Ian

2016-06-01

As serial femtosecond crystallography expands towards a variety of delivery methods, including chip-based methods, and smaller collected data sets, the requirement to optimize the data analysis to produce maximum structure quality is becoming increasingly pressing. Here cppxfel , a software package primarily written in C++, which showcases several data analysis techniques, is released. This software package presently indexes images using DIALS (diffraction integration for advanced light sources) and performs an initial orientation matrix refinement, followed by post-refinement of individual images against a reference data set. Cppxfel is released with the hope that the unique and useful elements of this package can be repurposed for existing software packages. However, as released, it produces high-quality crystal structures and is therefore likely to be also useful to experienced users of X-ray free-electron laser (XFEL) software who wish to maximize the information extracted from a limited number of XFEL images.

Packaging Technology for SiC High Temperature Circuits Operable up to 500 Degrees Centigrade

NASA Technical Reports Server (NTRS)

Chen, Lian-Yu

2002-01-01

New high temperature low power 8-pin packages have been fabricated using commercial fabrication service. These packages are made of aluminum nitride and 96 percent alumina with Au metallization. The new design of these packages provides the chips inside with EM shielding. Wirebond geometry control has been achieved for precise mechanical tests. Au wirebond samples with 45 degree heel-angle have been tested using wireloop test module. The geometry control improves the consistency of measurement of the wireloop breaking point.Also reported on is a parametric study of the thermomechanical reliability of a Au thick-film based SiC die-attach assembly using nonlinear finite element analysis (FEA) was conducted to optimize the die-attach thermo-mechanical performance for operation at temperatures from room temperature to 500 degrees Centigrade. This parametric study centered on material selection, structure design and process control.

On the release of cppxfel for processing X-ray free-electron laser images

DOE PAGES

Ginn, Helen Mary; Evans, Gwyndaf; Sauter, Nicholas K.; ...

2016-05-11

As serial femtosecond crystallography expands towards a variety of delivery methods, including chip-based methods, and smaller collected data sets, the requirement to optimize the data analysis to produce maximum structure quality is becoming increasingly pressing. Herecppxfel, a software package primarily written in C++, which showcases several data analysis techniques, is released. This software package presently indexes images using DIALS (diffraction integration for advanced light sources) and performs an initial orientation matrix refinement, followed by post-refinement of individual images against a reference data set.Cppxfelis released with the hope that the unique and useful elements of this package can be repurposed formore » existing software packages. However, as released, it produces high-quality crystal structures and is therefore likely to be also useful to experienced users of X-ray free-electron laser (XFEL) software who wish to maximize the information extracted from a limited number of XFEL images.« less

Ultra-thin silicon (UTSi) on insulator CMOS transceiver and time-division multiplexed switch chips for smart pixel integration

NASA Astrophysics Data System (ADS)

Zhang, Liping; Sawchuk, Alexander A.

2001-12-01

We describe the design, fabrication and functionality of two different 0.5 micron CMOS optoelectronic integrated circuit (OEIC) chips based on the Peregrine Semiconductor Ultra-Thin Silicon on insulator technology. The Peregrine UTSi silicon- on-sapphire (SOS) technology is a member of the silicon-on- insulator (SOI) family. The low-loss synthetic sapphire substrate is optically transparent and has good thermal conductivity and coefficient of thermal expansion properties, which meet the requirements for flip-chip bonding of VCSELs and other optoelectronic input-output components. One chip contains transceiver and network components, including four channel high-speed CMOS transceiver modules, pseudo-random bit stream (PRBS) generators, a voltage controlled oscillator (VCO) and other test circuits. The transceiver chips can operate in both self-testing mode and networking mode. An on- chip clock and true-single-phase-clock (TSPC) D-flip-flop have been designed to generate a PRBS at over 2.5 Gb/s for the high-speed transceiver arrays to operate in self-testing mode. In the networking mode, an even number of transceiver chips forms a ring network through free-space or fiber ribbon interconnections. The second chip contains four channel optical time-division multiplex (TDM) switches, optical transceiver arrays, an active pixel detector and additional test devices. The eventual applications of these chips will require monolithic OEICs with integrated optical input and output. After fabrication and testing, the CMOS transceiver array dies will be packaged with 850 nm vertical cavity surface emitting lasers (VCSELs), and metal-semiconductor- metal (MSM) or GaAs p-i-n detector die arrays to achieve high- speed optical interconnections. The hybrid technique could be either wire bonding or flip-chip bonding of the CMOS SOS smart-pixel arrays with arrays of VCSELs and photodetectors onto an optoelectronic chip carrier as a multi-chip module (MCM).

The silicon chip: A versatile micro-scale platform for micro- and nano-scale systems

NASA Astrophysics Data System (ADS)

Choi, Edward

Cutting-edge advances in micro- and nano-scale technology require instrumentation to interface with the external world. While technology feature sizes are continually being reduced, the size of experimentalists and their instrumentation do not mirror this trend. Hence there is a need for effective application-specific instrumentation to bridge the gap from the micro and nano-scale phenomena being studied to the comparative macro-scale of the human interfaces. This dissertation puts forward the idea that the silicon CMOS integrated circuit, or microchip in short, serves as an excellent platform to perform this functionality. The electronic interfaces designed for the semiconductor industry are particularly attractive as development platforms, and the reduction in feature sizes that has been a hallmark of the industry suggests that chip-scale instrumentation may be more closely coupled to the phenomena of interest, allowing finer control or improved measurement capabilities. Compatibility with commercial processes will further enable economies of scale through mass production, another welcome feature of this approach. Thus chip-scale instrumentation may replace the bulky, expensive, cumbersome-to-operate macro-scale prototypes currently in use for many of these applications. The dissertation examines four specific applications in which the chip may serve as the ideal instrumentation platform. These are nanorod manipulation, polypyrrole bilayer hinge microactuator control, organic transistor hybrid circuits, and contact fluorescence imaging. The thesis is structured around chapters devoted to each of these projects, in addition to a chapter on preliminary work on an RFID system that serves as a wireless interface model. Each of these chapters contains tools and techniques developed for chip-scale instrumentation, from custom scripts for automated layout and data collection to microfabrication processes. Implementation of these tools to develop systems for the applications above is evaluated. The viability of this approach is not limited to the examples listed in this work, and innovative new methodologies beyond those included here may be developed in the future for other systems which would benefit from the versatility of chip-scale platforms.

Moving Beyond 3D Hetero-Integration and Towards Monolithic Integration of Phase-Change RF Switches with SiGe BiCMOS

DTIC Science & Technology

2016-03-31

Corporation, Linthicum, Maryland *Corresponding author: Pavel.Borodulin@ngc.com Abstract: A chip -scale, highly-reconfigurable transmitter and...the technology has been used in a chip -scale, reconfigurable receiver demonstration and ongoing efforts to increase the level of performance and...circuit (RF-FPGA). It consists of a heterogeneous assembly of a SiGe BiCMOS chip with multiple 3D-integrated, low-loss, phase-change switch chiplets

Characterization and partitioning of the char ash collected after the processing of pine wood chips in a pilot-scale gasification unit

Treesearch

Thomas L. Eberhardt; Hui Pan; Leslie H. Groom; Chi-Leung So

2011-01-01

Southern yellow pine wood chips were used as the feedstock for a pilot-scale gasification unit coupled with a 25 kW generator. The pulp-grade wood chips were relatively free of bark and low in ash content. Processing this feedstock yielded a black/sooty by-product that upon combustion in a muffle furnace resulted in an ash content of about 48%. The term "char ash...

Development and psychometric properties of the Carer – Head Injury Neurobehavioral Assessment Scale (C-HINAS) and the Carer – Head Injury Participation Scale (C-HIPS): patient and family determined outcome scales

PubMed Central

Deb, Shoumitro; Bryant, Eleanor; Morris, Paul G; Prior, Lindsay; Lewis, Glyn; Haque, Sayeed

2007-01-01

Objective Develop and assess the psychometric properties of the Carer – Head Injury Participation Scale (C-HIPS) and its biggest factor the Carer – Head Injury Neurobehavioral Assessment Scale (C-HINAS). Furthermore, the aim was to examine the inter-informant reliability by comparing the self reports of individuals with traumatic brain injury (TBI) with the carer reports on the C-HIPS and the C-HINAS. Method Thirty-two TBI individuals and 27 carers took part in in-depth qualitative interviews exploring the consequences of the TBI. Interview transcripts were analysed and key themes and concepts were used to construct a 49-item and 58-item patient (Patient – Head Injury Participation Scale [P-HIPS]) and carer outcome measure (C-HIPS) respectively, of which 49 were parallel items and nine additional items were used to assess carer burden. Postal versions of the P-HIPS, C-HIPS, Mayo Portland Adaptability Inventory-3 (MPAI-3), and the Glasgow Outcome Scale-Extended (GOSE) were completed by a cohort of 113 TBI individuals and 80 carers. Data from a sub-group of 66 patient/carer pairs were used to compare inter-informant reliability between the P-HIPS and the C-HIPS, and the P-HINAS and the C-HINAS respectively. Results All individual 49 items of the C-HIPS and their total score showed good test-retest reliability (0.95) and internal consistency (0.95). Comparisons with the MPAI-3 and GOSE found a good correlation with the MPAI-3 (0.7) and a moderate negative correlation with the GOSE (−0.6). Factor analysis of these items extracted a 4-factor structure which represented the domains ‘Emotion/Behavior’ (C-HINAS), ‘Independence/Community Living’, ‘Cognition’, and ‘Physical’. The C-HINAS showed good internal consistency (0.92), test-retest reliability (0.93), and concurrent validity with one MPAI subscale (0.7). Assessment of inter-informant reliability revealed good correspondence between the reports of the patients and the carers for both the C-HIPS (0.83) and the C-HINAS (0.82). Conclusion Both the C-HINAS and the C-HIPS show strong psychometric properties. The qualitative methodology employed in the construction stage of the questionnaires provided good evidence of face and content validity. Comparisons between the P-HIPS and the C-HIPS, and the P-HINAS and the C-HINAS indicated high levels of agreement suggesting that in situations where the patient is unable to provide self-reports, information provided by the carer could be used. PMID:19300569

White thin-film flip-chip LEDs with uniform color temperature using laser lift-off and conformal phosphor coating technologies.

PubMed

Lin, Huan-Ting; Tien, Ching-Ho; Hsu, Chen-Peng; Horng, Ray-Hua

2014-12-29

We fabricated a phosphor-conversion white light emitting diode (PC-WLED) using a thin-film flip-chip GaN LED with a roughened u-GaN surface (TFFC-SR-LED) that emits blue light at 450 nm wavelength with a conformal phosphor coating that converts the blue light into yellow light. It was found that the TFFC-SR-LED with the thin-film substrate removal process and surface roughening exhibits a power enhancement of 16.1% when compared with the TFFC-LED without a sapphire substrate. When a TFFC-SR-LED with phosphors on a Cu-metal packaging-base (TFFC-SR-Cu-WLED) was operated at a forward-bias current of 350 mA, luminous flux and luminous efficacy were increased by 17.8 and 11.9%, compared to a TFFC-SR-LED on a Cup-shaped packaging-base (TFFC-SR-Cup-WLED). The angular correlated color temperature (CCT) deviation of a TFFC-SR-Cu-WLED reaches 77 K in the range of -70° to + 70° when the average CCT of white LEDs is around 4300 K. Consequently, the TFFC-SR-LED in a conformal coating phosphor structure on a Cu packaging-base could not only increase the luminous flux output, but also improve the angular-dependent CCT uniformity, thereby reducing the yellow ring effect.

Apparatus and Method for Packaging and Integrating Microphotonic Devices

NASA Technical Reports Server (NTRS)

Nguyen, Hung (Inventor)

2008-01-01

An apparatus is disclosed that includes a carrier structure and an optical coupling arrangement. The carrier structure is made of a silicon material and allows for the packaging and integrating of microphotonic devices onto a single chip. The optical coupling mechanism enables laser light to be coupled into and out of a microphotonic resonant disk integrated on the carrier. The carrier provides first, second and third cavities that are dimensioned so as to accommodate the insertion and snug fitting of the microphotonic resonant disk and first and second prisms that are implemented by the optical coupling arrangement to accommodate the laser coupling.

Design automation for complex CMOS/SOS LSI hybrid substrates

NASA Technical Reports Server (NTRS)

Ramondetta, P. W.; Smiley, J. W.

1976-01-01

A design automated approach used to develop thick-film hybrid packages is described. The hybrid packages produced combine thick-film and silicon on sapphire (SOS) laser surface interaction technologies to bring the on-chip performance level of SOS to the subsystem level. Packing densities are improved by a factor of eight over ceramic dual in-line packing; interchip wiring capacitance is low. Due to significant time savings, the design automated approach presented can be expected to yield a 3:1 reduction in cost over the use of manual methods for the initial design of a hybrid.

Fabricating a Microcomputer on a Single Silicon Wafer

NASA Technical Reports Server (NTRS)

Evanchuk, V. L.

1983-01-01

Concept for "microcomputer on a slice" reduces microcomputer costs by eliminating scribing, wiring, and packaging of individual circuit chips. Low-cost microcomputer on silicon slice contains redundant components. All components-central processing unit, input/output circuitry, read-only memory, and random-access memory (CPU, I/O, ROM, and RAM) on placed on single silicon wafer.

Study on the mechanism of color coordinate shift of LED package

NASA Astrophysics Data System (ADS)

Zhuang, Yunyi; Wang, Yong; Yang, Bobo; Li, Zhanguo; Yang, Lei; Zou, Jun

2017-07-01

In the paper, the influences of the chip, silicone and phosphors on the color coordinate shift of LED were studied. In the process of LED baking, it was found that the effect of the chip and silicone on the color coordinate drift is less than 3% through the analysis of each influencing factor. But the influence of the phosphors is large and accounted for 11.11% of the overall impact factors. Therefore, it is important to select the better green phosphors in thermal stability for the LED package and it has a guiding significance to the color coordinate of LED distribution. Project supported by the National Natural Science Foundation of China (No. 11474036), the Natural Science Foundation of Shanghai (No. 12ZR1430900), the Shanghai Institute of Technology Talents Scheme (No. YJ2014-04), the Shanghai Municipal Alliance Program (Nos. Lm201514, Lm201505, Lm201455), the Science and Technology Commission of Shanghai Municipality (CN) (No. 14500503300), the Shanghai Cooperative Project (No. ShanghaiCXY-2013-61), and the Jiashan County Technology Program (No. 20141316).

Ultra Small Integrated Optical Fiber Sensing System

PubMed Central

Van Hoe, Bram; Lee, Graham; Bosman, Erwin; Missinne, Jeroen; Kalathimekkad, Sandeep; Maskery, Oliver; Webb, David J.; Sugden, Kate; Van Daele, Peter; Van Steenberge, Geert

2012-01-01

This paper introduces a revolutionary way to interrogate optical fiber sensors based on fiber Bragg gratings (FBGs) and to integrate the necessary driving optoelectronic components with the sensor elements. Low-cost optoelectronic chips are used to interrogate the optical fibers, creating a portable dynamic sensing system as an alternative for the traditionally bulky and expensive fiber sensor interrogation units. The possibility to embed these laser and detector chips is demonstrated resulting in an ultra thin flexible optoelectronic package of only 40 μm, provided with an integrated planar fiber pigtail. The result is a fully embedded flexible sensing system with a thickness of only 1 mm, based on a single Vertical-Cavity Surface-Emitting Laser (VCSEL), fiber sensor and photodetector chip. Temperature, strain and electrodynamic shaking tests have been performed on our system, not limited to static read-out measurements but dynamically reconstructing full spectral information datasets.

Enhanced light output from a nitride-based power chip of green light-emitting diodes with nano-rough surface using nanoimprint lithography.

PubMed

Huang, H W; Lin, C H; Yu, C C; Lee, B D; Chiu, C H; Lai, C F; Kuo, H C; Leung, K M; Lu, T C; Wang, S C

2008-05-07

Enhanced light extraction from a GaN-based power chip (PC) of green light-emitting diodes (LEDs) with a rough p-GaN surface using nanoimprint lithography is presented. At a driving current of 350 mA and with a chip size of 1 mm × 1 mm packaged on transistor outline (TO)-cans, the light output power of the green PC LEDs with nano-rough p-GaN surface is enhanced by 48% when compared with the same device without a rough p-GaN surface. In addition, by examining the radiation patterns, the green PC LED with nano-rough p-GaN surface shows stronger light extraction with a wider view angle. These results offer promising potential to enhance the light output powers of commercial light-emitting devices by using the technique of nanoimprint lithography under suitable nanopattern design.

Flip chip bumping technology—Status and update

NASA Astrophysics Data System (ADS)

Juergen Wolf, M.; Engelmann, Gunter; Dietrich, Lothar; Reichl, Herbert

2006-09-01

Flip chip technology is a key driver for new complex system architectures and high-density packaging, e.g. sensor or pixel devices. Bumped wafers/dice as key elements become very important in terms of general availability at low cost, high yield and quality level. Today, different materials, e.g. Au, Ni, AuSn, SnAg, SnAgCu, SnCu, etc., are used for flip chip interconnects and different bumping approaches are available. Electroplating is the technology of choice for high-yield wafer bumping for small bump sizes and pitches. Lead-free solder bumps require an increase in knowledge in the field of under bump metallization (UBM) and the interaction of bump and substrate metallization, the formation and growth of intermetallic compounds (IMCs) during liquid- and solid-phase reactions. Results of a new bi-layer UBM of Ni-Cu which is especially designed for small-sized lead-free solder bumps will be discussed.

Ultra-compact 32 × 32 strictly-non-blocking Si-wire optical switch with fan-out LGA interposer.

PubMed

Tanizawa, Ken; Suzuki, Keijiro; Toyama, Munehiro; Ohtsuka, Minoru; Yokoyama, Nobuyuki; Matsumaro, Kazuyuki; Seki, Miyoshi; Koshino, Keiji; Sugaya, Toshio; Suda, Satoshi; Cong, Guangwei; Kimura, Toshio; Ikeda, Kazuhiro; Namiki, Shu; Kawashima, Hitoshi

2015-06-29

We demonstrate a 32 × 32 path-independent-insertion-loss optical path switch that integrates 1024 thermooptic Mach-Zehnder switches and 961 intersections on a small, 11 × 25 mm2 die. The switch is fabricated on a 300-mm-diameter silicon-on-insulator wafer by a complementary metal-oxide semiconductor-compatible process with advanced ArF immersion lithography. For reliable electrical packaging, the switch chip is flip-chip bonded to a ceramic interposer that arranges the electrodes in a 0.5-mm pitch land grid array. The on-chip loss is measured to be 15.8 ± 1.0 dB, and successful switching is demonstrated for digital-coherent 43-Gb/s QPSK signals. The total crosstalk of the switch is estimated to be less than -20 dB at the center wavelength of 1545 nm. The bandwidth narrowing caused by dimensional errors that arise during fabrication is discussed.

New comparison of psychological meaning of colors in samples and objects with semantic ratings

NASA Astrophysics Data System (ADS)

Lee, Tien-Rein

2002-06-01

In color preference and color-meaning research, color chips are widely used as stimuli. Are meanings of isolated color chips generalizeable to contextualized colors? According to Taft (1996), few significant differences exist between chip and object ratings for the same color. A similar survey was performed on 192 college students. This article reports the results of the study comparing semantic rating of color applied to a variety of familiar objects. The objects were a cup, T-shirt, sofa, car, notebook, and MP3 player, all images that represent daily life familiar objects. Subjects rated a set of 16 color chips, against 6 bipolar, 7-step semantic differential scales. The scales consisted of beautiful-ugly, soft-hard, warm-cool, elegant-vulgar, loud- discreet, and masculine-feminine. Analyses performed on the data indicated that unlike Taft's findings on 1996, significant differences existed between chip and object rating for the same color in every scale. The results of the study have implications for the use of color chips in color planning which suggest they are not compatible with the generality of results of the earlier color meaning research. Generally, a color judged to be beautiful, elegant and warm when presented as a chip does not equal beautiful, elegant, and warm when applied to the surface of an object such as a cup, T-shirt, sofa, car.

Two-Volt Josephson Arbitrary Waveform Synthesizer Using Wilkinson Dividers.

PubMed

Flowers-Jacobs, Nathan E; Fox, Anna E; Dresselhaus, Paul D; Schwall, Robert E; Benz, Samuel P

2016-09-01

The root-mean-square (rms) output voltage of the NIST Josephson arbitrary waveform synthesizer (JAWS) has been doubled from 1 V to a record 2 V by combining two new 1 V chips on a cryocooler. This higher voltage will improve calibrations of ac thermal voltage converters and precision voltage measurements that require state-of-the-art quantum accuracy, stability, and signal-to-noise ratio. We achieved this increase in output voltage by using four on-chip Wilkinson dividers and eight inner-outer dc blocks, which enable biasing of eight Josephson junction (JJ) arrays with high-speed inputs from only four high-speed pulse generator channels. This approach halves the number of pulse generator channels required in future JAWS systems. We also implemented on-chip superconducting interconnects between JJ arrays, which reduces systematic errors and enables a new modular chip package. Finally, we demonstrate a new technique for measuring and visualizing the operating current range that reduces the measurement time by almost two orders of magnitude and reveals the relationship between distortion in the output spectrum and output pulse sequence errors.

Integrated on-chip solid state capacitor based on vertically aligned carbon nanofibers, grown using a CMOS temperature compatible process

NASA Astrophysics Data System (ADS)

Saleem, Amin M.; Andersson, Rickard; Desmaris, Vincent; Enoksson, Peter

2018-01-01

Complete miniaturized on-chip integrated solid-state capacitors have been fabricated based on conformal coating of vertically aligned carbon nanofibers (VACNFs), using a CMOS temperature compatible microfabrication processes. The 5 μm long VACNFs, operating as electrode, are grown on a silicon substrate and conformally coated by aluminum oxide dielectric using atomic layer deposition (ALD) technique. The areal (footprint) capacitance density value of 11-15 nF/mm2 is realized with high reproducibility. The CMOS temperature compatible microfabrication, ultra-low profile (less than 7 μm thickness) and high capacitance density would enables direct integration of micro energy storage devices on the active CMOS chip, multi-chip package and passives on silicon or glass interposer. A model is developed to calculate the surface area of VACNFs and the effective capacitance from the devices. It is thereby shown that 71% of surface area of the VACNFs has contributed to the measured capacitance, and by using the entire area the capacitance can potentially be increased.

Design of a high-efficiency train headlamp with low power consumption using dual half-parabolic aluminized reflectors.

PubMed

Liang, Wei-Lun; Su, Guo-Dung J

2018-02-20

We propose a train headlamp system using dual half-circular parabolic aluminized reflectors. Each half-circular reflector contains five high-efficiency and small-package light-emitting diode (LED) chips, and the halves are 180° rotationally symmetric. For traffic safety, the headlamp satisfies the Code of Federal Regulations. To predict the pattern of illumination, an analytical derivation is developed for the optical path of a ray that is perpendicular to and emitted from the center of an LED chip. This ray represents the main ray emitted from the LED chip and is located at the maximum illuminance of the spot projected by the LED source onto a screen. We then analyze the design systematically to determine the locations of the LED chips in the reflector that minimize electricity consumption while satisfying reliability constraints associated with traffic safety. Compared to a typical train headlamp system with an incandescent or halogen lamp needing several hundred watts, the proposed system only uses 20.18 W to achieve the luminous intensity requirements.

Progress in ion torrent semiconductor chip based sequencing.

PubMed

Merriman, Barry; Rothberg, Jonathan M

2012-12-01

In order for next-generation sequencing to become widely used as a diagnostic in the healthcare industry, sequencing instrumentation will need to be mass produced with a high degree of quality and economy. One way to achieve this is to recast DNA sequencing in a format that fully leverages the manufacturing base created for computer chips, complementary metal-oxide semiconductor chip fabrication, which is the current pinnacle of large scale, high quality, low-cost manufacturing of high technology. To achieve this, ideally the entire sensory apparatus of the sequencer would be embodied in a standard semiconductor chip, manufactured in the same fab facilities used for logic and memory chips. Recently, such a sequencing chip, and the associated sequencing platform, has been developed and commercialized by Ion Torrent, a division of Life Technologies, Inc. Here we provide an overview of this semiconductor chip based sequencing technology, and summarize the progress made since its commercial introduction. We described in detail the progress in chip scaling, sequencing throughput, read length, and accuracy. We also summarize the enhancements in the associated platform, including sample preparation, data processing, and engagement of the broader development community through open source and crowdsourcing initiatives. © 2012 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Compact Receiver Front Ends for Submillimeter-Wave Applications

NASA Technical Reports Server (NTRS)

Mehdi, Imran; Chattopadhyay, Goutam; Schlecht, Erich T.; Lin, Robert H.; Sin, Seth; Peralta, Alejandro; Lee, Choonsup; Gill, John J.; Gulkis, Samuel; Thomas, Bertrand C.

2012-01-01

The current generation of submillimeter-wave instruments is relatively mass and power-hungry. The receiver front ends (RFEs) of a submillimeter instrument form the heart of the instrument, and any mass reduction achieved in this subsystem is propagated through the instrument. In the current implementation, the RFE consists of different blocks for the mixer and LO circuits. The motivation for this work is to reduce the mass of the RFE by integrating the mixer and LO circuits in one waveguide block. The mixer and its associated LO chips will all be packaged in a single waveguide package. This will reduce the mass of the RFE and also provide a number of other advantages. By bringing the mixer and LO circuits close together, losses in the waveguide will be reduced. Moreover, the compact nature of the block will allow for better thermal control of the block, which is important in order to reduce gain fluctuations. A single waveguide block with a 600- GHz RFE functionality (based on a subharmonically pumped Schottky diode pair) has been demonstrated. The block is about 3x3x3 cubic centimeters. The block combines the mixer and multiplier chip in a single package. 3D electromagnetic simulations were carried out to design the waveguide circuit around the mixer and multiplier chip. The circuit is optimized to provide maximum output power and maximum bandwidth. An integrated submillimeter front end featuring a 520-600-GHz sub-harmonic mixer and a 260-300-GHz frequency tripler in a single cavity was tested. Both devices used GaAs MMIC membrane planar Schottky diode technology. The sub-harmonic mixer/tripler circuit has been tested using conventional metal-machined blocks. Measurement results on the metal block give best DSB (double sideband) mixer noise temperature of 2,360 K and conversion losses of 7.7 dB at 520 GHz. The LO input power required to pump the integrated tripler/sub-harmonic mixer is between 30 and 50 mW.

Integrated bio-photonics to revolutionize health care enabled through PIX4life and PIXAPP

NASA Astrophysics Data System (ADS)

Jans, Hilde; O'Brien, Peter; Artundo, Iñigo; Porcel, Marco A. G.; Hoofman, Romano; Geuzebroek, Douwe; Dumon, Pieter; van der Vliet, Marcel; Witzens, Jeremy; Bourguignon, Eric; Van Dorpe, Pol; Lagae, Liesbet

2018-02-01

Photonics has become critical to life sciences. However, the field is far from benefiting fully from photonics' capabilities. Today, bulky and expensive optical systems dominate biomedical photonics, even though robust optical functionality can be realized cost-effectively on single photonic integrated circuits (PICs). Such chips are commercially available mostly for telecom applications, and at infrared wavelengths. Although proof-of-concept demonstrations for PICs in life sciences, using visible wavelengths are abundant, the gating factor for wider adoption is limited in resource capacity. Two European pilot lines, PIX4life and PIXAPP, were established to facilitate European R and D in biophotonics, by helping European companies and universities bridge the gap between research and industrial development. Through creation of an open-access model, PIX4life aims to lower barriers to entry for prototyping and validating biophotonics concepts for larger scale production. In addition, PIXAPP enables the assembly and packaging of photonic integrated circuits.

Accelerated Thermal Cycling and Failure Mechanisms for BGA and CSP Assemblies

NASA Technical Reports Server (NTRS)

Ghaffarian, Reza

2000-01-01

This paper reviews the accelerated thermal cycling test methods that are currently used by industry to characterize the interconnect reliability of commercial-off-the-shelf (COTS) ball grid array (BGA) and chip scale package (CSP) assemblies. Acceleration induced failure mechanisms varied from conventional surface mount (SM) failures for CSPs. Examples of unrealistic life projections for other CSPs are also presented. The cumulative cycles to failure for ceramic BGA assemblies performed under different conditions, including plots of their two Weibull parameters, are presented. The results are for cycles in the range of -30 C to 100 C, -55 C to 100 C, and -55 C to 125 C. Failure mechanisms as well as cycles to failure for thermal shock and thermal cycling conditions in the range of -55 C to 125 C were compared. Projection to other temperature cycling ranges using a modified Coffin-Manson relationship is also presented.

Development of the Large-Scale Oligonucleotide Chip for the Diagnosis of Plant Viruses and its Practical Use

PubMed Central

Nam, Moon; Kim, Jeong-Seon; Lim, Seungmo; Park, Chung Youl; Kim, Jeong-Gyu; Choi, Hong-Soo; Lim, Hyoun-Sub; Moon, Jae Sun; Lee, Su-Heon

2014-01-01

A large-scale oligonucleotide (LSON) chip was developed for the detection of the plant viruses with known genetic information. The LSON chip contains two sets of 3,978 probes for 538 species of targets including plant viruses, satellite RNAs and viroids. A hundred forty thousand probes, consisting of isolate-, species- and genus-specific probes respectively, are designed from 20,000 of independent nucleotide sequence of plant viruses. Based on the economic importance, the amount of genome information, and the number of strains and/or isolates, one to fifty-one probes for each target virus are selected and spotted on the chip. The standard and field samples for the analysis of the LSON chip have been prepared and tested by RT-PCR. The probe’s specific and/or nonspecific reaction patterns by LSON chip allow us to diagnose the unidentified viruses. Thus, the LSON chip in this study could be highly useful for the detection of unexpected plant viruses, the monitoring of emerging viruses and the fluctuation of the population of major viruses in each plant. PMID:25288985

Innovative materials tailored for advanced micro-optic applications

NASA Astrophysics Data System (ADS)

Himmelhuber, Roland; Fink, Marion; Pfeiffer, Karl; Ostrzinski, Ute; Klukowska, Anna; Gruetzner, Gabi; Houbertz, Ruth; Wolter, Herbert

2007-02-01

The handling of a continuously increasing amount of data leads to a strong need for high-speed short-range connections. Conventional Cu technology between chips on a board is limited. Optical interconnects will dominate the market, since they can overcome the limitations. One of the issues for materials used, e.g., for waveguides embedded in printed circuit boards (PCBs) is the compatibility with standard epoxies used for PCBs during the entire board fabrication process. Materials applied for optical interconnects should be mechanically and optically reliable, and also allow low-cost production. From the material production side, the process should be easy to up-scale. Therefore, anticipatory research strategy and suitable tailoring is asked for. The handling of light in the UV and visible range often requires the use of specially designed materials. Most polymer materials show an increased yellowing effect upon being exposed to shorter wavelength light. The major influence on the absorption in the UV and visible range of a UV curable material is related to the UV initiator, beside any other chromophores formed mainly during the exposure. Different material approaches will be presented which fulfil the requirements for highly sophisticated applications in optics / optical packaging technology. Firstly, an epoxy-based material system for optical chip-to-chip interconnection will be introduced. Secondly, the adaptation of a UV patternable inorganic-organic hybrid material (ORMOCER ®) originally developed for waveguide applications in the data and telecom regime, will be discussed with respect to applications in the visible regime. Spectroscopy and UV-DSC measurements were carried out to investigate the influence of standard photoinitiators on the optical properties for an ORMOCER ® system suitable for microoptic applications. The results show that the resulting material properties were significantly improved by exchange of the initiators compared to the originally incorporated one.

Mitigating leakage errors due to cavity modes in a superconducting quantum computer

NASA Astrophysics Data System (ADS)

McConkey, T. G.; Béjanin, J. H.; Earnest, C. T.; McRae, C. R. H.; Pagel, Z.; Rinehart, J. R.; Mariantoni, M.

2018-07-01

A practical quantum computer requires quantum bit (qubit) operations with low error probabilities in extensible architectures. We study a packaging method that makes it possible to address hundreds of superconducting qubits by means of coaxial Pogo pins. A qubit chip is housed in a superconducting box, where both box and chip dimensions lead to unwanted modes that can interfere with qubit operations. We analyze these interference effects in the context of qubit coherent leakage and qubit decoherence induced by damped modes. We propose two methods, half-wave fencing and antinode pinning, to mitigate the resulting errors by detuning the resonance frequency of the modes from the qubit frequency. We perform electromagnetic field simulations indicating that the resonance frequency of the modes increases with the number of installed pins and can be engineered to be significantly higher than the highest qubit frequency. We estimate that the error probabilities and decoherence rates due to suitably shifted modes in realistic scenarios can be up to two orders of magnitude lower than the state-of-the-art superconducting qubit error and decoherence rates. Our methods can be extended to different types of packages that do not rely on Pogo pins. Conductive bump bonds, for example, can serve the same purpose in qubit architectures based on flip chip technology. Metalized vias, instead, can be used to mitigate modes due to the increasing size of the dielectric substrate on which qubit arrays are patterned.

Smart and functional polymer materials for smart and functional microfluidic instruments

NASA Astrophysics Data System (ADS)

Gray, Bonnie L.

2014-04-01

As microfluidic systems evolve from "chip-in-the-lab" to true portable lab-on-a-chip (LoC) or lab-in-a-package (LiP) microinstrumentation, there is a need for increasingly miniaturized sensors, actuators, and integration/interconnect technologies with high levels of functionality and self-direction. Furthermore, as microfluidic instruments are increasingly realized in polymer-based rather than glass- or silicon- based platforms, there is a need to realize these highly functional components in materials that are polymer-compatible. Polymers that are altered to possess basic functionality, and even higher-functioning "smart" polymer materials, may help to realize high-functioning and selfdirecting portable microinstrumentation. Stimuli-responsive hydrogels have been recognized for over a decade as beneficial to the development of smart microfluidics systems and instrumentation. In addition, functional materials such as conductive and magnetic composite polymers are being increasingly employed to push microfluidics systems to greater degrees of functionality, portability, and/or flexibility for wearable/implantable systems. Functional and smart polymer materials can be employed to realize electrodes, electronic routing, heaters, mixers, valves, pumps, sensors, and interconnect structures in polymer-based microfluidic systems. Stimuli for such materials can be located on-chip or in a small package, thus greatly increasing the degree of portability and the potential for mechanical flexibility of such systems. This paper will examine the application of functional polymer materials to the development of high-functioning microfluidics instruments with a goal towards self-direction.

On-chip optical diode based on silicon photonic crystal heterojunctions.

PubMed

Wang, Chen; Zhou, Chang-Zhu; Li, Zhi-Yuan

2011-12-19

Optical isolation is a long pursued object with fundamental difficulty in integrated photonics. As a step towards this goal, we demonstrate the design, fabrication, and characterization of on-chip wavelength-scale optical diodes that are made from the heterojunction between two different silicon two-dimensional square-lattice photonic crystal slabs with directional bandgap mismatch and different mode transitions. The measured transmission spectra show considerable unidirectional transmission behavior, in good agreement with numerical simulations. The experimental realization of on-chip optical diodes with wavelength-scale size using all-dielectric, passive, and linear silicon photonic crystal structures may help to construct on-chip optical logical devices without nonlinearity or magnetism, and would open up a road towards photonic computers.

Reliability of Sn/Pb and Lead-Free (SnAgCu) Solders of Surface Mounted Miniaturized Passive Components for Extreme Temperature (-185 C to +125 C) Space Missions

NASA Technical Reports Server (NTRS)

Ramesham, Rajeshuni

2011-01-01

Surface mount electronic package test boards have been assembled using tin/lead (Sn/Pb) and lead-free (Pb-free or SnAgCu or SAC305) solders. The soldered surface mount packages include ball grid arrays (BGA), flat packs, various sizes of passive chip components, etc. They have been optically inspected after assembly and subsequently subjected to extreme temperature thermal cycling to assess their reliability or future deep space, long-term, extreme temperature environmental missions. In this study, the employed temperature range (-185oC to +125oC) covers military specifications (-55oC to +100oC), extreme old Martian (-120oC to +115oC), asteroid Nereus (-180oC to +25oC) and JUNO (-150oC to +120oC) environments. The boards were inspected at room temperature and at various intervals as a function of extreme temperature thermal cycling and bake duration. Electrical resistance measurements made at room temperature are reported and the tests to date have shown some change in resistance as a function of extreme temperature thermal cycling and some showed increase in resistance. However, the change in interconnect resistance becomes more noticeable with increasing number of thermal cycles. Further research work will be carried out to understand the reliability of packages under extreme temperature applications (-185oC to +125oC) via continuously monitoring the daisy chain resistance for BGA, Flat-packs, lead less chip packages, etc. This paper will describe the experimental reliability results of miniaturized passive components (01005, 0201, 0402, 0603, 0805, and 1206) assembled using surface mounting processes with tin-lead and lead-free solder alloys under extreme temperature environments.

Reliability of Sn/Pb and lead-free (SnAgCu) solders of surface mounted miniaturized passive components for extreme temperature (-185°C to +125°C) space missions

NASA Astrophysics Data System (ADS)

Ramesham, Rajeshuni

2011-02-01

Surface mount electronic package test boards have been assembled using tin/lead (Sn/Pb) and lead-free (Pb-free or SnAgCu or SAC305) solders. The soldered surface mount packages include ball grid arrays (BGA), flat packs, various sizes of passive chip components, etc. They have been optically inspected after assembly and subsequently subjected to extreme temperature thermal cycling to assess their reliability for future deep space, long-term, extreme temperature environmental missions. In this study, the employed temperature range (-185°C to +125°C) covers military specifications (-55°C to +100°C), extreme cold Martian (-120°C to +115°C), asteroid Nereus (-180°C to +25°C) and JUNO (-150°C to +120°C) environments. The boards were inspected at room temperature and at various intervals as a function of extreme temperature thermal cycling and bake duration. Electrical resistance measurements made at room temperature are reported and the tests to date have shown some change in resistance as a function of extreme temperature thermal cycling and some showed increase in resistance. However, the change in interconnect resistance becomes more noticeable with increasing number of thermal cycles. Further research work will be carried out to understand the reliability of packages under extreme temperature applications (-185°C to +125°C) via continuously monitoring the daisy chain resistance for BGA, Flat-packs, lead less chip packages, etc. This paper will describe the experimental reliability results of miniaturized passive components (01005, 0201, 0402, 0603, 0805, and 1206) assembled using surface mounting processes with tin-lead and lead-free solder alloys under extreme temperature environments.

Evaluating laser-driven Bremsstrahlung radiation sources for imaging and analysis of nuclear waste packages.

PubMed

Jones, Christopher P; Brenner, Ceri M; Stitt, Camilla A; Armstrong, Chris; Rusby, Dean R; Mirfayzi, Seyed R; Wilson, Lucy A; Alejo, Aarón; Ahmed, Hamad; Allott, Ric; Butler, Nicholas M H; Clarke, Robert J; Haddock, David; Hernandez-Gomez, Cristina; Higginson, Adam; Murphy, Christopher; Notley, Margaret; Paraskevoulakos, Charilaos; Jowsey, John; McKenna, Paul; Neely, David; Kar, Satya; Scott, Thomas B

2016-11-15

A small scale sample nuclear waste package, consisting of a 28mm diameter uranium penny encased in grout, was imaged by absorption contrast radiography using a single pulse exposure from an X-ray source driven by a high-power laser. The Vulcan laser was used to deliver a focused pulse of photons to a tantalum foil, in order to generate a bright burst of highly penetrating X-rays (with energy >500keV), with a source size of <0.5mm. BAS-TR and BAS-SR image plates were used for image capture, alongside a newly developed Thalium doped Caesium Iodide scintillator-based detector coupled to CCD chips. The uranium penny was clearly resolved to sub-mm accuracy over a 30cm(2) scan area from a single shot acquisition. In addition, neutron generation was demonstrated in situ with the X-ray beam, with a single shot, thus demonstrating the potential for multi-modal criticality testing of waste materials. This feasibility study successfully demonstrated non-destructive radiography of encapsulated, high density, nuclear material. With recent developments of high-power laser systems, to 10Hz operation, a laser-driven multi-modal beamline for waste monitoring applications is envisioned. Copyright © 2016. Published by Elsevier B.V.

Maximizing Computational Capability with Minimal Power

DTIC Science & Technology

2009-03-01

Chip -Scale Energy and Power... and Heat Report Documentation Page Form ApprovedOMB No. 0704-0188 Public reporting burden for the collection of...OpticalBench Mounting Posts Imager Chip LCDinterfaced withthecomputer P o l a r i z e r P o l a r i z e r XYZ Translator Optical Slide VMM Computational Pixel...Signal routing power / memory: ? Power does not include comm off chip (i.e. accessing memory) Power = ½ C Vdd2 f for CMOS Chip to Chip (10pF load min

Design, Fabrication, and Characterization of a Microelectromechanical Directional Microphone

DTIC Science & Technology

2011-06-01

7. PERFORMING ORGANIZATION NAME(S) AND ADDRESS(ES) 8. PERFORMING ORGANIZATION REPORT NUMBER 9. SPONSORING/MONITORING AGENCY NAME(S) AND ADDRESS(ES...Figure 5.2 SOIC packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 5.3 Laboratory setup...Mean Squared SOC System-On-Chip SOIC Small Outline Integrated Circuit SOIMUMPS Silicon-On-Insulator Multi-User MEMS Process SPL Sound Pressure Level

Phosphor chessboard packaging for white LEDs in high efficiency and high color performance

NASA Astrophysics Data System (ADS)

Nguyen, Quang-Khoi; Chang, Yu-Yu; Lu, Chun-Yan; Yang, Tsung-Hsun; Chung, Te-Yuan; Sun, Ching-Cherng

2016-09-01

We performed the simulation of white LEDs packaging with different chessboard structures of white light converting phosphor layer covered on GaN die chip. Three different types of chessboard structures are called type 1, type 2 and type 3, respectively. The result of investigation according to the phosphor thickness show the increasing of thickness of phosphor layer are, the decreasing of output blue light power are. Meanwhile, the changes of yellow light are neglect. Type 3 shows highest packaging efficiency of 74.3 % compares with packaging efficiency of type 2 and type 1 (72.5 % and 71.3 %, respectively). Type 3 also shows the most effect of forward light. Attention that the type 3 chessboard structure gets packaging efficiency of 74.3 % at color temperature of daylight as well as high saving of phosphor amount. The color temperatures of three types of chessboard structure are higher than 5000 K, so they are suitable for lighting purpose. The angular correlate color temperature deviation (ACCTD) of type 1, type 2 and type 3 are 6500K, 11500K and 17000K, respectively.

Reliability of high I/O high density CCGA interconnect electronic packages under extreme thermal environments

NASA Astrophysics Data System (ADS)

Ramesham, Rajeshuni

2012-03-01

Ceramic column grid array (CCGA) packages have been increasing in use based on their advantages such as high interconnect density, very good thermal and electrical performances, compatibility with standard surfacemount packaging assembly processes, and so on. CCGA packages are used in space applications such as in logic and microprocessor functions, telecommunications, payload electronics, and flight avionics. As these packages tend to have less solder joint strain relief than leaded packages or more strain relief over lead-less chip carrier packages, the reliability of CCGA packages is very important for short-term and long-term deep space missions. We have employed high density CCGA 1152 and 1272 daisy chained electronic packages in this preliminary reliability study. Each package is divided into several daisy-chained sections. The physical dimensions of CCGA1152 package is 35 mm x 35 mm with a 34 x 34 array of columns with a 1 mm pitch. The dimension of the CCGA1272 package is 37.5 mm x 37.5 mm with a 36 x 36 array with a 1 mm pitch. The columns are made up of 80% Pb/20%Sn material. CCGA interconnect electronic package printed wiring polyimide boards have been assembled and inspected using non-destructive x-ray imaging techniques. The assembled CCGA boards were subjected to extreme temperature thermal atmospheric cycling to assess their reliability for future deep space missions. The resistance of daisy-chained interconnect sections were monitored continuously during thermal cycling. This paper provides the experimental test results of advanced CCGA packages tested in extreme temperature thermal environments. Standard optical inspection and x-ray non-destructive inspection tools were used to assess the reliability of high density CCGA packages for deep space extreme temperature missions.

Polymer dispensing and embossing technology for the lens type LED packaging

NASA Astrophysics Data System (ADS)

Chien, Chien-Lin Chang; Huang, Yu-Che; Hu, Syue-Fong; Chang, Chung-Min; Yip, Ming-Chuen; Fang, Weileun

2013-06-01

This study presents a ring-type micro-structure design on the substrate and its corresponding micro fabrication processes for a lens-type light-emitting diode (LED) package. The dome-type or crater-type silicone lenses are achieved by a dispensing and embossing process rather than a molding process. Silicone with a high viscosity and thixotropy index is used as the encapsulant material. The ring-type micro structure is adopted to confine the dispensed silicone encapsulant so as to form the packaged lens. With the architecture and process described, this LED package technology herein has three merits: (1) the flexibility of lens-type LED package designs is enhanced; (2) a dome-type package design is used to enhance the intensity; (3) a crater-type package design is used to enhance the view angle. Measurement results show the ratio between the lens height and lens radius can vary from 0.4 to 1 by changing the volume of dispensed silicone. The view angles of dome-type and crater-type packages can reach 155° ± 5° and 175° ± 5°, respectively. As compared with the commercial plastic leaded chip carrier-type package, the luminous flux of a monochromatic blue light LED is improved by 15% by the dome-type package (improved by 7% by the crater-type package) and the luminous flux of a white light LED is improved by 25% by the dome-type package (improved by 13% by the crater-type package). The luminous flux of monochromatic blue light LED and white light LED are respectively improved by 8% and 12% by the dome-type package as compare with the crater-type package.

The silicon-glass microreactor with embedded sensors—technology and results of preliminary qualitative tests, toward intelligent microreaction plant

NASA Astrophysics Data System (ADS)

Knapkiewicz, P.

2013-03-01

The technology and preliminary qualitative tests of silicon-glass microreactors with embedded pressure and temperature sensors are presented. The concept of microreactors for leading highly exothermic reactions, e.g. nitration of hydrocarbons, and design process-included computer-aided simulations are described in detail. The silicon-glass microreactor chip consisting of two micromixers (multistream micromixer), reaction channels, cooling/heating chambers has been proposed. The microreactor chip was equipped with a set of pressure and temperature sensors and packaged. Tests of mixing quality, pressure drops in channels, heat exchange efficiency and dynamic behavior of pressure and temperature sensors were documented. Finally, two applications were described.

On-chip photonic particle sensor

NASA Astrophysics Data System (ADS)

Singh, Robin; Ma, Danhao; Agarwal, Anu; Anthony, Brian

2018-02-01

We propose an on-chip photonic particle sensor design that can perform particle sizing and counting for various environmental applications. The sensor is based on micro photonic ring resonators that are able to detect the presence of the free space particles through the interaction with their evanescent electric field tail. The sensor can characterize a wide range of the particle size ranging from a few nano meters to micron ( 1 micron). The photonic platform offers high sensitivity, compactness, fast response of the device. Further, FDTD simulations are performed to analyze different particle-light interactions. Such a compact and portable platform, packaged with integrated photonic circuit provides a useful sensing modality in space shuttle and environmental applications.

Improvement of modulation bandwidth in electroabsorption-modulated laser by utilizing the resonance property in bonding wire.

PubMed

Kwon, Oh Kee; Han, Young Tak; Baek, Yong Soon; Chung, Yun C

2012-05-21

We present and demonstrate a simple and cost-effective technique for improving the modulation bandwidth of electroabsorption-modulated laser (EML). This technique utilizes the RF resonance caused by the EML chip (i.e., junction capacitance) and bonding wire (i.e, wire inductance). We analyze the effects of the lengths of the bonding wires on the frequency responses of EML by using an equivalent circuit model. To verify this analysis, we package a lumped EML chip on the sub-mount and measure its frequency responses. The results show that, by using the proposed technique, we can increase the modulation bandwidth of EML from ~16 GHz to ~28 GHz.

A short review on thermosonic flip chip bonding

NASA Astrophysics Data System (ADS)

Suppiah, Sarveshvaran; Ong, Nestor Rubio; Sauli, Zaliman; Sarukunaselan, Karunavani; Alcain, Jesselyn Barro; Shahimin, Mukhzeer Mohamad; Retnasamy, Vithyacharan

2017-09-01

This review is to study the evolution and key findings, critical technical challenges, solutions and bonding equipment of thermosonic flip chip bonding. Based on the review done, it was found that ultrasonic power, bonding time and force are the three main critical parameters need to be optimized in order to achieve sound and reliable bonding between the die and substrate. A close monitoring of the ultrasonic power helped to prevent over bonding phenomena on flexible substrate. Gold stud bumping is commonly used in thermosonic bonding compared to solder due to its better reliability obtained in the LED and optoelectronic packages. The review comprised short details on the available thermosonic bonding equipment in the semiconductor industry as well.

Thermal conductivity on stud bump interconnection of high power COB LED

NASA Astrophysics Data System (ADS)

Sarukunaselan, K.; Ong, N. R.; Sauli, Z.; Mahmed, N.; Kirtsaeng, S.; Sakuntasathien, S.; Suppiah, S.; Alcain, J. B.; Retnasamy, V.

2017-09-01

In this paper, the impacts of bump dimensions and material conductivity on the thermal performances of a high power chip on board (COB) LED package were investigated using open source software, Elmer. The stud bump acted as interconnection join which has an extra role in dissipating heat generated by the chip to the ambience. Simulation data showed that for a bump with a fixed contact length of 1mm, the most suitable height was 171 µm with material conductivity of 238W/mK or 319W/mK. Materials with thermal conductivity of lower than 20W/mK, had the poorest heat dissipation irrespective of the height.

Chip-Scale Magnetic Source of Cold Atoms

DTIC Science & Technology

2013-06-01

the desert, the roof of the physics building, no air conditioning, shooting stars, coconut and coconuts , hacienda, and margarita. v Acknowledgments I...toner paper was folded around the chip and run through a laminator. The laminator’s heat transferred the toner to the chip. By splashing water on the

RF-Interrogated End-State Chip-Scale Atomic Clock

DTIC Science & Technology

2007-11-01

coherent population trapping,” Electronics Letters 37, (24), 1449-1451. [2] R. Lutwak , P. Vlitas, M. Varghese, M. Mescher, D. K. Serkland, and G. M...367. [9] R. Lutwak , D. Emmons, T. English, W. Riley, A. Duwel, M. Varghese, D. K. Serland, and G. M. Peake, 2003, “Chip-Scale Atomic Clock, Recent

Fully Integrated, Miniature, High-Frequency Flow Probe Utilizing MEMS Leadless SOI Technology

NASA Technical Reports Server (NTRS)

Ned, Alex; Kurtz, Anthony; Shang, Tonghuo; Goodman, Scott; Giemette. Gera (d)

2013-01-01

This work focused on developing, fabricating, and fully calibrating a flowangle probe for aeronautics research by utilizing the latest microelectromechanical systems (MEMS), leadless silicon on insulator (SOI) sensor technology. While the concept of angle probes is not new, traditional devices had been relatively large due to fabrication constraints; often too large to resolve flow structures necessary for modern aeropropulsion measurements such as inlet flow distortions and vortices, secondary flows, etc. Mea surements of this kind demanded a new approach to probe design to achieve sizes on the order of 0.1 in. (.3 mm) diameter or smaller, and capable of meeting demanding requirements for accuracy and ruggedness. This approach invoked the use of stateof- the-art processing techniques to install SOI sensor chips directly onto the probe body, thus eliminating redundancy in sensor packaging and probe installation that have historically forced larger probe size. This also facilitated a better thermal match between the chip and its mount, improving stability and accuracy. Further, the leadless sensor technology with which the SOI sensing element is fabricated allows direct mounting and electrical interconnecting of the sensor to the probe body. This leadless technology allowed a rugged wire-out approach that is performed at the sensor length scale, thus achieving substantial sensor size reductions. The technology is inherently capable of high-frequency and high-accuracy performance in high temperatures and harsh environments.

An SOI CMOS-Based Multi-Sensor MEMS Chip for Fluidic Applications.

PubMed

Mansoor, Mohtashim; Haneef, Ibraheem; Akhtar, Suhail; Rafiq, Muhammad Aftab; De Luca, Andrea; Ali, Syed Zeeshan; Udrea, Florin

2016-11-04

An SOI CMOS multi-sensor MEMS chip, which can simultaneously measure temperature, pressure and flow rate, has been reported. The multi-sensor chip has been designed keeping in view the requirements of researchers interested in experimental fluid dynamics. The chip contains ten thermodiodes (temperature sensors), a piezoresistive-type pressure sensor and nine hot film-based flow rate sensors fabricated within the oxide layer of the SOI wafers. The silicon dioxide layers with embedded sensors are relieved from the substrate as membranes with the help of a single DRIE step after chip fabrication from a commercial CMOS foundry. Very dense sensor packing per unit area of the chip has been enabled by using technologies/processes like SOI, CMOS and DRIE. Independent apparatuses were used for the characterization of each sensor. With a drive current of 10 µA-0.1 µA, the thermodiodes exhibited sensitivities of 1.41 mV/°C-1.79 mV/°C in the range 20-300 °C. The sensitivity of the pressure sensor was 0.0686 mV/(V excit kPa) with a non-linearity of 0.25% between 0 and 69 kPa above ambient pressure. Packaged in a micro-channel, the flow rate sensor has a linearized sensitivity of 17.3 mV/(L/min) -0.1 in the tested range of 0-4.7 L/min. The multi-sensor chip can be used for simultaneous measurement of fluid pressure, temperature and flow rate in fluidic experiments and aerospace/automotive/biomedical/process industries.

An SOI CMOS-Based Multi-Sensor MEMS Chip for Fluidic Applications †

PubMed Central

Mansoor, Mohtashim; Haneef, Ibraheem; Akhtar, Suhail; Rafiq, Muhammad Aftab; De Luca, Andrea; Ali, Syed Zeeshan; Udrea, Florin

2016-01-01

An SOI CMOS multi-sensor MEMS chip, which can simultaneously measure temperature, pressure and flow rate, has been reported. The multi-sensor chip has been designed keeping in view the requirements of researchers interested in experimental fluid dynamics. The chip contains ten thermodiodes (temperature sensors), a piezoresistive-type pressure sensor and nine hot film-based flow rate sensors fabricated within the oxide layer of the SOI wafers. The silicon dioxide layers with embedded sensors are relieved from the substrate as membranes with the help of a single DRIE step after chip fabrication from a commercial CMOS foundry. Very dense sensor packing per unit area of the chip has been enabled by using technologies/processes like SOI, CMOS and DRIE. Independent apparatuses were used for the characterization of each sensor. With a drive current of 10 µA–0.1 µA, the thermodiodes exhibited sensitivities of 1.41 mV/°C–1.79 mV/°C in the range 20–300 °C. The sensitivity of the pressure sensor was 0.0686 mV/(Vexcit kPa) with a non-linearity of 0.25% between 0 and 69 kPa above ambient pressure. Packaged in a micro-channel, the flow rate sensor has a linearized sensitivity of 17.3 mV/(L/min)−0.1 in the tested range of 0–4.7 L/min. The multi-sensor chip can be used for simultaneous measurement of fluid pressure, temperature and flow rate in fluidic experiments and aerospace/automotive/biomedical/process industries. PMID:27827904

Wafer-level vacuum/hermetic packaging technologies for MEMS

NASA Astrophysics Data System (ADS)

Lee, Sang-Hyun; Mitchell, Jay; Welch, Warren; Lee, Sangwoo; Najafi, Khalil

2010-02-01

An overview of wafer-level packaging technologies developed at the University of Michigan is presented. Two sets of packaging technologies are discussed: (i) a low temperature wafer-level packaging processes for vacuum/hermeticity sealing, and (ii) an environmentally resistant packaging (ERP) technology for thermal and mechanical control as well as vacuum packaging. The low temperature wafer-level encapsulation processes are implemented using solder bond rings which are first patterned on a cap wafer and then mated with a device wafer in order to encircle and encapsulate the device at temperatures ranging from 200 to 390 °C. Vacuum levels below 10 mTorr were achieved with yields in an optimized process of better than 90%. Pressures were monitored for more than 4 years yielding important information on reliability and process control. The ERP adopts an environment isolation platform in the packaging substrate. The isolation platform is designed to provide low power oven-control, vibration isolation and shock protection. It involves batch flip-chip assembly of a MEMS device onto the isolation platform wafer. The MEMS device and isolation structure are encapsulated at the wafer-level by another substrate with vertical feedthroughs for vacuum/hermetic sealing and electrical signal connections. This technology was developed for high performance gyroscopes, but can be applied to any type of MEMS device.

A low-latency optical switch architecture using integrated μm SOI-based contention resolution and switching

NASA Astrophysics Data System (ADS)

Mourgias-Alexandris, G.; Moralis-Pegios, M.; Terzenidis, N.; Cherchi, M.; Harjanne, M.; Aalto, T.; Vyrsokinos, K.; Pleros, N.

2018-02-01

The urgent need for high-bandwidth and high-port connectivity in Data Centers has boosted the deployment of optoelectronic packet switches towards bringing high data-rate optics closer to the ASIC, realizing optical transceiver functions directly at the ASIC package for high-rate, low-energy and low-latency interconnects. Even though optics can offer a broad range of low-energy integrated switch fabrics for replacing electronic switches and seamlessly interface with the optical I/Os, the use of energy- and latency-consuming electronic SerDes continues to be a necessity, mainly dictated by the absence of integrated and reliable optical buffering solutions. SerDes undertakes the role of optimally synergizing the lower-speed electronic buffers with the incoming and outgoing optical streams, suggesting that a SerDes-released chip-scale optical switch fabric can be only realized in case all necessary functions including contention resolution and switching can be implemented on a common photonic integration platform. In this paper, we demonstrate experimentally a hybrid Broadcast-and-Select (BS) / wavelength routed optical switch that performs both the optical buffering and switching functions with μm-scale Silicon-integrated building blocks. Optical buffering is carried out in a silicon-integrated variable delay line bank with a record-high on-chip delay/footprint efficiency of 2.6ns/mm2 and up to 17.2 nsec delay capability, while switching is executed via a BS design and a silicon-integrated echelle grating, assisted by SOA-MZI wavelength conversion stages and controlled by a FPGA header processing module. The switch has been experimentally validated in a 3x3 arrangement with 10Gb/s NRZ optical data packets, demonstrating error-free switching operation with a power penalty of <5dB.

missMethyl: an R package for analyzing data from Illumina's HumanMethylation450 platform.

PubMed

Phipson, Belinda; Maksimovic, Jovana; Oshlack, Alicia

2016-01-15

DNA methylation is one of the most commonly studied epigenetic modifications due to its role in both disease and development. The Illumina HumanMethylation450 BeadChip is a cost-effective way to profile >450 000 CpGs across the human genome, making it a popular platform for profiling DNA methylation. Here we introduce missMethyl, an R package with a suite of tools for performing normalization, removal of unwanted variation in differential methylation analysis, differential variability testing and gene set analysis for the 450K array. missMethyl is an R package available from the Bioconductor project at www.bioconductor.org. alicia.oshlack@mcri.edu.au Supplementary data are available at Bioinformatics online. © The Author 2015. Published by Oxford University Press. All rights reserved. For Permissions, please e-mail: journals.permissions@oup.com.

Low-cost and miniaturized 100-Gb/s (2 × 50 Gb/s) PAM-4 TO-packaged ROSA for data center networks.

PubMed

Kang, Sae-Kyoung; Huh, Joon Young; Lee, Jie Hyun; Lee, Joon Ki

2018-03-05

We design and implement a cost-effective and compact 100-Gb/s (2 × 50 Gb/s) PAM-4 receiver optical sub-assembly (ROSA) by using a TO-can package instead of an expensive box-type package. It consists of an optical demultiplexer, two PIN-PDs and a 2-channel linear transimpedance amplifier. The components are passively aligned and assembled using alignment marks engraved on each part. With a real-time PAM-4 DSP chip, we measured the back-to-back receiver sensitivities of the 100-Gb/s ROSA based on TO-56 to be less than -13.2 dBm for both channels at a bit error rate of 2.4e-4. The crosstalk penalty due to the adjacent channel interference was observed around 0.1 dB.

Reliability of Semiconductor Laser Packaging in Space Applications

NASA Technical Reports Server (NTRS)

Gontijo, Ivair; Qiu, Yueming; Shapiro, Andrew A.

2008-01-01

A typical set up used to perform lifetime tests of packaged, fiber pigtailed semiconductor lasers is described, as well as tests performed on a set of four pump lasers. It was found that two lasers failed after 3200, and 6100 hours under device specified bias conditions at elevated temperatures. Failure analysis of the lasers indicates imperfections and carbon contamination of the laser metallization, possibly from improperly cleaned photo resist. SEM imaging of the front facet of one of the lasers, although of poor quality due to the optical fiber charging effects, shows evidence of catastrophic damage at the facet. More stringent manufacturing controls with 100% visual inspection of laser chips are needed to prevent imperfect lasers from proceeding to packaging and ending up in space applications, where failure can result in the loss of a space flight mission.

Microarray Я US: a user-friendly graphical interface to Bioconductor tools that enables accurate microarray data analysis and expedites comprehensive functional analysis of microarray results.

PubMed

Dai, Yilin; Guo, Ling; Li, Meng; Chen, Yi-Bu

2012-06-08

Microarray data analysis presents a significant challenge to researchers who are unable to use the powerful Bioconductor and its numerous tools due to their lack of knowledge of R language. Among the few existing software programs that offer a graphic user interface to Bioconductor packages, none have implemented a comprehensive strategy to address the accuracy and reliability issue of microarray data analysis due to the well known probe design problems associated with many widely used microarray chips. There is also a lack of tools that would expedite the functional analysis of microarray results. We present Microarray Я US, an R-based graphical user interface that implements over a dozen popular Bioconductor packages to offer researchers a streamlined workflow for routine differential microarray expression data analysis without the need to learn R language. In order to enable a more accurate analysis and interpretation of microarray data, we incorporated the latest custom probe re-definition and re-annotation for Affymetrix and Illumina chips. A versatile microarray results output utility tool was also implemented for easy and fast generation of input files for over 20 of the most widely used functional analysis software programs. Coupled with a well-designed user interface, Microarray Я US leverages cutting edge Bioconductor packages for researchers with no knowledge in R language. It also enables a more reliable and accurate microarray data analysis and expedites downstream functional analysis of microarray results.

Nanotechnology for Food Packaging and Food Quality Assessment.

PubMed

Rossi, Marco; Passeri, Daniele; Sinibaldi, Alberto; Angjellari, Mariglen; Tamburri, Emanuela; Sorbo, Angela; Carata, Elisabetta; Dini, Luciana

Nanotechnology has paved the way to innovative food packaging materials and analytical methods to provide the consumers with healthier food and to reduce the ecological footprint of the whole food chain. Combining antimicrobial and antifouling properties, thermal and mechanical protection, oxygen and moisture barrier, as well as to verify the actual quality of food, e.g., sensors to detect spoilage, bacterial growth, and to monitor incorrect storage conditions, or anticounterfeiting devices in food packages may extend the products shelf life and ensure higher quality of foods. Also the ecological footprint of food chain can be reduced by developing new completely recyclable and/or biodegradable packages from natural and eco-friendly resources. The contribution of nanotechnologies to these goals is reviewed in this chapter, together with a description of portable devices ("lab-on-chip," sensors, nanobalances, etc.) which can be used to assess the quality of food and an overview of regulations in force on food contact materials. © 2017 Elsevier Inc. All rights reserved.

Examination of shipping package 9975-04985

DOE Office of Scientific and Technical Information (OSTI.GOV)

Daugherty, W. L.

Package 9975-04985 was examined following the identification of several unexpected conditions during surveillance activities. A heavy layer of corrosion product on the shield and the shield outer diameter being larger that allowed by drawing tolerances contributed to a very tight fit between the upper fiberboard assembly and shield. The average corrosion rate for the shield is estimated to be 0.0018 inch/year or less, which falls within the bounding rate of 0.002 inch/year that has been previously recommended for these packages. Several apparent foreign objects were noted within the package. One object observed on the air shield was identified as tape.more » The other objects were comprised of mostly fine fibers from the cane fiberboard. It is postulated that the upper and lower fiberboard assemblies were able to rub against each other due to the upper fiberboard assembly being held tight to the shield, and a few stray cane chips became frayed under vibratory motions.« less

Lab-on-a-chip modules for detection of highly pathogenic bacteria: from sample preparation to detection

NASA Astrophysics Data System (ADS)

Julich, S.; Kopinč, R.; Hlawatsch, N.; Moche, C.; Lapanje, A.; Gärtner, C.; Tomaso, H.

2014-05-01

Lab-on-a-chip systems are innovative tools for the detection and identification of microbial pathogens in human and veterinary medicine. The major advantages are small sample volume and a compact design. Several fluidic modules have been developed to transform analytical procedures into miniaturized scale including sampling, sample preparation, target enrichment, and detection procedures. We present evaluation data for single modules that will be integrated in a chip system for the detection of pathogens. A microfluidic chip for purification of nucleic acids was established for cell lysis using magnetic beads. This assay was evaluated with spiked environmental aerosol and swab samples. Bacillus thuringiensis was used as simulant for Bacillus anthracis, which is closely related but non-pathogenic for humans. Stationary PCR and a flow-through PCR chip module were investigated for specific detection of six highly pathogenic bacteria. The conventional PCR assays could be transferred into miniaturized scale using the same temperature/time profile. We could demonstrate that the microfluidic chip modules are suitable for the respective purposes and are promising tools for the detection of bacterial pathogens. Future developments will focus on the integration of these separate modules to an entire lab-on-a-chip system.

Pre-release plastic packaging of MEMS and IMEMS devices

DOEpatents

Peterson, Kenneth A.; Conley, William R.

2002-01-01

A method is disclosed for pre-release plastic packaging of MEMS and IMEMS devices. The method can include encapsulating the MEMS device in a transfer molded plastic package. Next, a perforation can be made in the package to provide access to the MEMS elements. The non-ablative material removal process can include wet etching, dry etching, mechanical machining, water jet cutting, and ultrasonic machining, or any combination thereof. Finally, the MEMS elements can be released by using either a wet etching or dry plasma etching process. The MEMS elements can be protected with a parylene protective coating. After releasing the MEMS elements, an anti-stiction coating can be applied. The perforating step can be applied to both sides of the device or package. A cover lid can be attached to the face of the package after releasing any MEMS elements. The cover lid can include a window for providing optical access. The method can be applied to any plastic packaged microelectronic device that requires access to the environment, including chemical, pressure, or temperature-sensitive microsensors; CCD chips, photocells, laser diodes, VCSEL's, and UV-EPROMS. The present method places the high-risk packaging steps ahead of the release of the fragile portions of the device. It also provides protection for the die in shipment between the molding house and the house that will release the MEMS elements and subsequently treat the surfaces.

Lab-on-a-Chip Pathogen Sensors for Food Safety

PubMed Central

Yoon, Jeong-Yeol; Kim, Bumsang

2012-01-01

There have been a number of cases of foodborne illness among humans that are caused by pathogens such as Escherichia coli O157:H7, Salmonella typhimurium, etc. The current practices to detect such pathogenic agents are cell culturing, immunoassays, or polymerase chain reactions (PCRs). These methods are essentially laboratory-based methods that are not at all real-time and thus unavailable for early-monitoring of such pathogens. They are also very difficult to implement in the field. Lab-on-a-chip biosensors, however, have a strong potential to be used in the field since they can be miniaturized and automated; they are also potentially fast and very sensitive. These lab-on-a-chip biosensors can detect pathogens in farms, packaging/processing facilities, delivery/distribution systems, and at the consumer level. There are still several issues to be resolved before applying these lab-on-a-chip sensors to field applications, including the pre-treatment of a sample, proper storage of reagents, full integration into a battery-powered system, and demonstration of very high sensitivity, which are addressed in this review article. Several different types of lab-on-a-chip biosensors, including immunoassay- and PCR-based, have been developed and tested for detecting foodborne pathogens. Their assay performance, including detection limit and assay time, are also summarized. Finally, the use of optical fibers or optical waveguide is discussed as a means to improve the portability and sensitivity of lab-on-a-chip pathogen sensors. PMID:23112625

Advanced Interconnect Roadmap for Space Applications

NASA Technical Reports Server (NTRS)

Galbraith, Lissa

1999-01-01

This paper presents the NASA electronic parts and packaging program for space applications. The topics include: 1) Forecasts; 2) Technology Challenges; 3) Research Directions; 4) Research Directions for Chip on Board (COB); 5) Research Directions for HDPs: Multichip Modules (MCMs); 6) Research Directions for Microelectromechanical systems (MEMS); 7) Research Directions for Photonics; and 8) Research Directions for Materials. This paper is presented in viewgraph form.

Thermal management of high heat flux electronic components in space and aircraft systems, phase 1

NASA Astrophysics Data System (ADS)

Iversen, Arthur H.

1991-03-01

The objectives of this Phase 1 program were to analyze, design, construct and demonstrate the application of curved surface cooling to power devices with the goal of demonstrating greater than 200 W/sq cm chip dissipation while maintaining junction temperatures within specification. Major components of the experiment comprised the test fixture for mounting the device under test and the cooling loop equipment and instrumentation. The work conducted in this Phase 1 study was to establish the basic parameters for the design of an entire class of efficient, compact, lightweight and cost competitive power conversion/conditioning systems for space, aircraft and general DOD requirements. This has been accomplished. Chip power dissipation of greater than 400 W/sq cm was demonstrated, and a general packaging and the thermal management design has been devised to meet the above requirements. The power limit reached was dictated by the junction temperature and not power dissipation, i.e., critical heat flux. The key to the packaging design is a basic construction concept that provides low junction to fluid thermal resistance. High heat flux dissipation without low thermal resistance is useless because excessive junction temperatures will results.

Adjunctive Effects of A Piscean Collagen-Based Controlled-Release Chlorhexidine Chip in the Treatment of Chronic Periodontitis: A Clinical and Microbiological Study

PubMed Central

John, Priya; Lazarus, Flemingson; Selvam, Arul; Prabhuji, Munivenkatappa Lakshmaiah Venkatesh

2015-01-01

Introduction PerioChip a bovine origin gelatine based CHX chip has shown beneficial effects in the management of Chronic Periodontitis. A new fish collagen based CHX chip similar to PerioChip is currently available; however this product has not been thoroughly researched. Aim The aim of the present study was to evaluate the effectiveness of a new Piscean collagen-based controlled-release chlorhexidine chip (CHX chip) as an adjunctive therapy to scaling and root planing (SRP). Settings and Design The study was conducted as a randomised, split-mouth, controlled clinical trial at Krishnadevaraya College of Dental Sciences, Bangalore, India. Materials and Methods In a split–mouth study involving 20 sites in 10 patients with chronic periodontitis, control sites received scaling and root planing and test sites received scaling and root planing (SRP) and the intrapocket CHX chip placement as an adjunct. Subgingival plaque samples were collected from both control and test sites at baseline, 11 days and 11 weeks and the anaerobic colony count were assessed. Clinical parameters that were recorded at baseline and 11 weeks were gingival index, Plaque index, Probing pocket depth (PPD), and Clinical attachment level (CAL). Plaque index was recorded additionally at 11 days. Results In the test group there was a statistically significant reduction in the total anaerobic colony count, gingival index and plaque scores from baseline as compared to control sites at all time intervals. An additional 0.8mm reduction in mean probing pocket depth was noted in the test group. Gain in Clinical attachment level was comparable in both groups. Conclusion The adjunctive use of the new collagen-based CHX chip yielded significant antimicrobial benefit accompanied by a reduction in probing depth and a clinical attachment level gain as compared to SRP alone. This suggests that it may be a useful treatment option of nonsurgical periodontal treatment of chronic periodontitis. PMID:26155567

Mechanical design optimization of a single-axis MOEMS accelerometer based on a grating interferometry cavity for ultrahigh sensitivity

NASA Astrophysics Data System (ADS)

Lu, Qianbo; Bai, Jian; Wang, Kaiwei; Lou, Shuqi; Jiao, Xufen; Han, Dandan; Yang, Guoguang

2016-08-01

The ultrahigh static displacement-acceleration sensitivity of a mechanical sensing chip is essential primarily for an ultrasensitive accelerometer. In this paper, an optimal design to implement to a single-axis MOEMS accelerometer consisting of a grating interferometry cavity and a micromachined sensing chip is presented. The micromachined sensing chip is composed of a proof mass along with its mechanical cantilever suspension and substrate. The dimensional parameters of the sensing chip, including the length, width, thickness and position of the cantilevers are evaluated and optimized both analytically and by finite-element-method (FEM) simulation to yield an unprecedented acceleration-displacement sensitivity. Compared with one of the most sensitive single-axis MOEMS accelerometers reported in the literature, the optimal mechanical design can yield a profound sensitivity improvement with an equal footprint area, specifically, 200% improvement in displacement-acceleration sensitivity with moderate resonant frequency and dynamic range. The modified design was microfabricated, packaged with the grating interferometry cavity and tested. The experimental results demonstrate that the MOEMS accelerometer with modified design can achieve the acceleration-displacement sensitivity of about 150μm/g and acceleration sensitivity of greater than 1500V/g, which validates the effectiveness of the optimal design.

Vacuum packaging of InGaAs focal plane array with four-stage thermoelectric cooler

NASA Astrophysics Data System (ADS)

Mo, De-feng; Liu, Da-fu; Yang, Li-yi; Xu, Qin-fei; Li, Xue

2013-09-01

The InGaAs focal plane array (FPA) detectors, covering the near-infrared 1~2.4 μm wavelength range, have been developed for application in space-based spectroscopy of the Earth atmosphere. This paper shows an all-metal vacuum package design for area array InGaAs detector of 1024×64 pixels, and its architecture will be given. Four-stage thermoelectric cooler (TEC) is used to cool down the FPA chip. To acquire high heat dissipation for TEC's Joule-heat, tungsten copper (CuW80) and kovar (4J29) is used as motherboard and cavity material respectively which joined by brazing. The heat loss including conduction, convection and radiation is analyzed. Finite element model is established to analyze the temperature uniformity of the chip substrate which is made of aluminum nitride (AlN). The performance of The TEC with and without heat load in vacuum condition is tested. The results show that the heat load has little influence to current-voltage relationship of TEC. The temperature difference (ΔT) increases as the input current increases. A linear relationship exists between heat load and ΔT of the TEC. Theoretical analysis and calculation show that the heat loss of radiation and conduction is about 187 mW and 82 mW respectively. Considering the Joule-heat of readout circuit and the heat loss of radiation and conduction, the FPA for a 220 K operation at room temperature can be achieved. As the thickness of AlN chip substrate is thicker than 1 millimeter, the temperature difference can be less than 0.3 K.

Quartz/fused silica chip carriers

NASA Technical Reports Server (NTRS)

1992-01-01

The primary objective of this research and development effort was to develop monolithic microwave integrated circuit (MMIC) packaging which will operate efficiently at millimeter-wave frequencies. The packages incorporated fused silica as the substrate material which was selected due to its favorable electrical properties and potential performance improvement over more conventional materials for Ka-band operation. The first step towards meeting this objective is to develop a package that meets standard mechanical and thermal requirements using fused silica and to be compatible with semiconductor devices operating up to at least 44 GHz. The second step is to modify the package design and add multilayer and multicavity capacity to allow for application specific integrated circuits (ASIC's) to control multiple phase shifters. The final step is to adapt the package design to a phased array module with integral radiating elements. The first task was a continuation of the SBIR Phase 1 work. Phase 1 identified fused silica as a viable substrate material by demonstrating various plating, machining, and adhesion properties. In Phase 2 Task 1, a package was designed and fabricated to validate these findings. Task 2 was to take the next step in packaging and fabricate a multilayer, multichip module (MCM). This package is the predecessor to the phased array module and demonstrates the ability to via fill, circuit print, laminate, and to form vertical interconnects. The final task was to build a phased array module. The radiating elements were to be incorporated into the package instead of connecting to it with wire or ribbon bonds.

Packaging of electro-microfluidic devices

DOEpatents

Benavides, Gilbert L.; Galambos, Paul C.; Emerson, John A.; Peterson, Kenneth A.; Giunta, Rachel K.; Zamora, David Lee; Watson, Robert D.

2003-04-15

A new architecture for packaging surface micromachined electro-microfluidic devices is presented. This architecture relies on two scales of packaging to bring fluid to the device scale (picoliters) from the macro-scale (microliters). The architecture emulates and utilizes electronics packaging technology. The larger package consists of a circuit board with embedded fluidic channels and standard fluidic connectors (e.g. Fluidic Printed Wiring Board). The embedded channels connect to the smaller package, an Electro-Microfluidic Dual-Inline-Package (EMDIP) that takes fluid to the microfluidic integrated circuit (MIC). The fluidic connection is made to the back of the MIC through Bosch-etched holes that take fluid to surface micromachined channels on the front of the MIC. Electrical connection is made to bond pads on the front of the MIC.

Packaging of electro-microfluidic devices

DOEpatents

Benavides, Gilbert L.; Galambos, Paul C.; Emerson, John A.; Peterson, Kenneth A.; Giunta, Rachel K.; Watson, Robert D.

2002-01-01

A new architecture for packaging surface micromachined electro-microfluidic devices is presented. This architecture relies on two scales of packaging to bring fluid to the device scale (picoliters) from the macro-scale (microliters). The architecture emulates and utilizes electronics packaging technology. The larger package consists of a circuit board with embedded fluidic channels and standard fluidic connectors (e.g. Fluidic Printed Wiring Board). The embedded channels connect to the smaller package, an Electro-Microfluidic Dual-Inline-Package (EMDIP) that takes fluid to the microfluidic integrated circuit (MIC). The fluidic connection is made to the back of the MIC through Bosch-etched holes that take fluid to surface micromachined channels on the front of the MIC. Electrical connection is made to bond pads on the front of the MIC.

Wireless poly(dimethylsiloxane) quartz-crystal-microbalance biosensor chip fabricated by nanoimprint lithography for micropump integration aiming at application in lab-on-a-chip

NASA Astrophysics Data System (ADS)

Kato, Fumihito; Noguchi, Hiroyuki; Kodaka, Yukinari; Oshida, Naoya; Ogi, Hirotsugu

2018-07-01

We developed a quartz-crystal-microbalance (QCM) biosensor chip that operates wirelessly via electromagnetic waves, using poly(dimethylsiloxane) (PDMS). An AT-cut quartz oscillator (22–30 µm) is packaged in a microchannel, where it is supported by micropillars without mechanical fixing. As a result, the quartz oscillator is little affected by the thermal stress caused by the difference in the thermal expansion coefficients of the components, and the leakage of the vibration energy of the quartz oscillator is reduced. Consequently, high-frequency (∼56 MHz) measurement with a stable baseline (±∼2 ppm) is realized. We succeeded in repeatedly monitoring the binding reaction between immunoglobulin G (IgG) and Staphylococcus aureus protein A (SPA) with the quartz oscillator on which SPA molecules were immobilized nonspecifically. In addition, the affinity between SPA and IgG was calculated from the association and dissociation curves, and the usefulness of our wireless PDMS QCM biosensor was demonstrated.

Detection of M. tuberculosis using DNA chips combined with an image analysis system.

PubMed

Huang, T-S; Liu, Y-C; Bair, C-H; Sy, C-L; Chen, Y-S; Tu, H-Z; Chen, B-C

2008-01-01

To develop a packaged DNA chip assay (the DR. MTBC Screen assay) for direct detection of the Mycobacterium tuberculosis complex. We described a DNA chip assay based on the IS6110 gene that can be used for the detection of M. tuberculosis complex. Probes were spotted onto the polystyrene strips in the wells of 96-well microtitre plates and used for hybridisation with biotin-labelled amplicon to yield a pattern of visualised positive spots. The plate image was scanned, analysed and interpreted automatically. The results corresponded well with those obtained by conventional culture as well as clinical diagnosis, with sensitivity and specificity rates of respectively 83.8% and 94.2%, and 84.6% and 96.3%. We conclude that the DR. MTBC Screen assay can detect M. tuberculosis complex rapidly in respiratory specimens, readily adapts to routine work and provides a flexible choice to meet different cost-effectiveness and automation needs in TB-endemic countries. The cost for reagents is around US$10 per sample.

Demonstration of Compact and Low-Loss Athermal Arrayed-Waveguide Grating Module Based on 2.5%-Δ Silica-Based Waveguides

NASA Astrophysics Data System (ADS)

Maru, Koichi; Abe, Yukio; Uetsuka, Hisato

2008-10-01

We demonstrated a compact and low-loss athermal arrayed-waveguide grating (AWG) module utilizing silica-based planar lightwave circuit (PLC) technology. Spot-size converters based on a vertical ridge-waveguide taper were integrated with a 2.5%-Δ athermal AWG to reduce the loss at chip-to-fiber interface. Spot-size converters based on a segmented core were formed around resin-filled trenches for athermalization formed in the slab to reduce the diffraction loss at the trenches. A 16-channel athermal AWG module with 100-GHz channel spacing was fabricated. The use of a 2.5%-Δ athermal chip with a single-side fiber array enabled a compact package of the size of 41.6×16.6×4.5 mm3. Athermal characteristics and a small insertion loss of 3.5-3.8 dB were obtained by virtue of low fiber-to-chip coupling loss and athermalization with low excess loss.

Utilization of treated conifer wood chips by Pleurotus (Fr.) P. Karst. species for cultivating mushrooms

Treesearch

Suki C. Croan

2003-01-01

Mushroom-producing white-rot basidiomycetes can grow rapidly and produce heavy mycelial growth on treated conifer wastes with extractive-degrading fungi. This study evaluates the treatment of scaled-up conifer wood chips with Ophiostoma piliferum (Cartapip 97). Treated conifer chips were used as substrates for cultivating mushroom-producing basidiomycetes of various...

"Chips with Everything": A Laboratory Exercise for Comparing Subjective and Objective Measurements of Potato Chips

ERIC Educational Resources Information Center

Davies, Cathy

2005-01-01

The following laboratory exercise was designed to aid student understanding of the differences between subjective and objective measurements. Students assess the color and texture of different varieties of potato chip (crisps) by means of an intensity rating scale and a rank test and objectively with a colorimeter and texture analyzer. For data…

75 FR 51843 - In the Matter of Certain Large Scale Integrated Circuit Semiconductor Chips and Products...

Federal Register 2010, 2011, 2012, 2013, 2014

2010-08-23

... Integrated Circuit Semiconductor Chips and Products Containing the Same; Notice of Commission Decision Not To... semiconductor chips and products containing same by reason of infringement of certain claims of U.S. Patent Nos. 5,933,364 and 6,834,336. The complaint further alleges the existence of a domestic industry. The...

Plasticized methylcellulose coating for reducing oil uptake in potato chips.

PubMed

Tavera-Quiroz, María José; Urriza, Marina; Pinotti, Adriana; Bertola, Nora

2012-05-01

As a result of consumers' health concerns and the trend towards healthier and low-fat food products, research has been undertaken to reduce the amount of fat absorbed in fried foods. This work focused on studying the efficacy of sorbitol and glycerol as plasticizers of methylcellulose coatings used to reduce oil uptake during the frying process of potato chips Changes in color, mechanical properties, water activity and lipid oxidation during storage were monitored. Also, an explanation regarding the different performances between both methylcellulose coatings with and without plasticizer was attained and techniques from the field of packaging films such as dynamic mechanical analyzer (DMA) and Fourier transform infrared spectroscopy were applied to analyze the behavior of coatings submitted to the frying operation. The application of a methylcellulose coating was an adequate choice to reduce oil absorption in fried potato chips. The most effective formulation was 10 g L(-1) methylcellulose with the addition of 7.5 g L(-1) sorbitol. With the incorporation of this formulation, oil absorption was reduced by 30%. Neither the sorbitol concentration nor the presence of the MC coating affected the puncture maximum force and color parameters L and a*. The results of the sensory analysis indicated that the panelists could not distinguish between the coated and uncoated potato chips. Methylcellulose-based coating plasticized with sorbitol could be an alternative for obtaining healthier potato chips. Copyright © 2011 Society of Chemical Industry.

Digital PCR on an integrated self-priming compartmentalization chip.

PubMed

Zhu, Qiangyuan; Qiu, Lin; Yu, Bingwen; Xu, Yanan; Gao, Yibo; Pan, Tingting; Tian, Qingchang; Song, Qi; Jin, Wei; Jin, Qinhan; Mu, Ying

2014-03-21

An integrated on-chip valve-free and power-free microfluidic digital PCR device is for the first time developed by making use of a novel self-priming compartmentalization and simple dehydration control to realize 'divide and conquer' for single DNA molecule detection. The high gas solubility of PDMS is exploited to provide the built-in power of self-priming so that the sample and oil are sequentially sucked into the device to realize sample self-compartmentalization based on surface tension. The lifespan of its self-priming capability was about two weeks tested using an air-tight packaging bottle sealed with a small amount of petroleum jelly, which is significant for a practical platform. The SPC chip contains 5120 independent 5 nL microchambers, allowing the samples to be compartmentalized completely. Using this platform, three different abundances of lung cancer related genes are detected to demonstrate the feasibility and flexibility of the microchip for amplifying a single nucleic acid molecule. For maximal accuracy, within less than 5% of the measurement deviation, the optimal number of positive chambers is between 400 and 1250 evaluated by the Poisson distribution, which means one panel can detect an average of 480 to 4804 template molecules. This device without world-to-chip connections eliminates the constraint of the complex pipeline control, and is an integrated on-chip platform, which would be a significant improvement to digital PCR automation and more user-friendly.

Biocompatible circuit-breaker chip for thermal management of biomedical microsystems

NASA Astrophysics Data System (ADS)

Luo, Yi; Dahmardeh, Masoud; Takahata, Kenichi

2015-05-01

This paper presents a thermoresponsive micro circuit breaker for biomedical applications specifically targeted at electronic intelligent implants. The circuit breaker is micromachined to have a shape-memory-alloy cantilever actuator as a normally closed temperature-sensitive switch to protect the device of interest from overheating, a critical safety feature for smart implants including those that are electrothermally driven with wireless micro heaters. The device is fabricated in a size of 1.5  ×  2.0  ×  0.46 mm3 using biocompatible materials and a chip-based titanium package, exhibiting a nominal cold-state resistance of 14 Ω. The breaker rapidly enters the full open condition when the chip temperature exceeds 63 °C, temporarily breaking the circuit of interest to lower its temperature until chip temperature drops to 51 °C, at which the breaker closes the circuit to allow current to flow through it again, physically limiting the maximum temperature of the circuit. This functionality is tested in combination with a wireless resonant heater powered by radio-frequency electromagnetic radiation, demonstrating self-regulation of heater temperature. The developed circuit-breaker chip operates in a fully passive manner that removes the need for active sensor and circuitry to achieve temperature regulation in a target device, contributing to the miniaturization of biomedical microsystems including electronic smart implants where thermal management is essential.

Direct-referencing Two-dimensional-array Digital Microfluidics Using Multi-layer Printed Circuit Board

PubMed Central

Gong, Jian; Kim, Chang-Jin “CJ”

2008-01-01

Digital (i.e. droplet-based) microfluidics, by the electrowetting-on-dielectric (EWOD) mechanism, has shown great potential for a wide range of applications, such as lab-on-a-chip. While most reported EWOD chips use a series of electrode pads essentially in one-dimensional line pattern designed for specific tasks, the desired universal chips allowing user-reconfigurable paths would require the electrode pads in two-dimensional pattern. However, to electrically access the electrode pads independently, conductive lines need to be fabricated underneath the pads in multiple layers, raising a cost issue especially for disposable chip applications. In this article, we report the building of digital microfluidic plates based on a printed-circuit-board (PCB), in which multilayer electrical access lines were created inexpensively using mature PCB technology. However, due to its surface topography and roughness and resulting high resistance against droplet movement, as-fabricated PCB surfaces require unacceptably high (~500 V) voltages unless coated with or immersed in oil. Our goal is EWOD operations of aqueous droplets not only on oil-covered but also on dry surfaces. To meet varying levels of performances, three types of gradually complex post-PCB microfabrication processes are developed and evaluated. By introducing land-grid-array (LGA) sockets in the packaging, a scalable digital microfluidics system with reconfigurable and low-cost chip is also demonstrated. PMID:19234613

GeoChip 3.0 as a high-thoughput tool for analyzing microbial community composition, structure, and functional activity

DOE Office of Scientific and Technical Information (OSTI.GOV)

He, Z.; Deng, Y.; Van Nostrand, J.D.

A new generation of functional gene arrays (FGAs; GeoChip 3.0) has been developed, with {approx}28,000 probes covering approximately 57,000 gene variants from 292 functional gene families involved in carbon, nitrogen, phosphorus and sulfur cycles, energy metabolism, antibiotic resistance, metal resistance and organic contaminant degradation. GeoChip 3.0 also has several other distinct features, such as a common oligo reference standard (CORS) for data normalization and comparison, a software package for data management and future updating and the gyrB gene for phylogenetic analysis. Computational evaluation of probe specificity indicated that all designed probes would have a high specificity to their corresponding targets.more » Experimental analysis with synthesized oligonucleotides and genomic DNAs showed that only 0.0036-0.025% false-positive rates were observed, suggesting that the designed probes are highly specific under the experimental conditions examined. In addition, GeoChip 3.0 was applied to analyze soil microbial communities in a multifactor grassland ecosystem in Minnesota, USA, which showed that the structure, composition and potential activity of soil microbial communities significantly changed with the plant species diversity. As expected, GeoChip 3.0 is a high-throughput powerful tool for studying microbial community functional structure, and linking microbial communities to ecosystem processes and functioning.« less

Challenges and Opportunities in Gen3 Embedded Cooling with High-Quality Microgap Flow

NASA Technical Reports Server (NTRS)

Bar-Cohen, Avram; Robinson, Franklin L.; Deisenroth, David C.

2018-01-01

Gen3, Embedded Cooling, promises to revolutionize thermal management of advanced microelectronic systems by eliminating the sequential conductive and interfacial thermal resistances which dominate the present 'remote cooling' paradigm. Single-phase interchip microfluidic flow with high thermal conductivity chips and substrates has been used successfully to cool single transistors dissipating more than 40kW/sq cm, but efficient heat removal from transistor arrays, larger chips, and chip stacks operating at these prodigious heat fluxes would require the use of high vapor fraction (quality), two-phase cooling in intra- and inter-chip microgap channels. The motivation, as well as the challenges and opportunities associated with evaporative embedded cooling in realistic form factors, is the focus of this paper. The paper will begin with a brief review of the history of thermal packaging, reflecting the 70-year 'inward migration' of cooling technology from the computer-room, to the rack, and then to the single chip and multichip module with 'remote' or attached air- and liquid-cooled coldplates. Discussion of the limitations of this approach and recent results from single-phase embedded cooling will follow. This will set the stage for discussion of the development challenges associated with application of this Gen3 thermal management paradigm to commercial semiconductor hardware, including dealing with the effects of channel length, orientation, and manifold-driven centrifugal acceleration on the governing behavior.

Design, development, fabrication and delivery of register and multiplexer units. [CMOS monolithic chip development

NASA Technical Reports Server (NTRS)

Feller, A.; Lombardi, T.

1978-01-01

Several approaches for implementing the register and multiplexer unit into two CMOS monolithic chip types were evaluated. The CMOS standard cell array technique was selected and implemented. Using this design automation technology, two LSI CMOS arrays were designed, fabricated, packaged, and tested for proper static, functional, and dynamic operation. One of the chip types, multiplexer register type 1, is fabricated on a 0.143 x 0.123 inch chip. It uses nine standard cell types for a total of 54 standard cells. This involves more than 350 transistors and has the functional equivalent of 111 gates. The second chip, multiplexer register type 2, is housed on a 0.12 x 0.12 inch die. It uses 13 standard cell types, for a total of 42 standard cells. It contains more than 300 transistors, the functional equivalent of 112 gates. All of the hermetically sealed units were initially screened for proper functional operation. The static leakage and the dynamic leakage were measured. Dynamic measurements were made and recorded. At 10 V, 14 megabit shifting rates were measured on multiplexer register type 1. At 5 V these units shifted data at a 6.6 MHz rate. The units were designed to operate over the 3 to 15 V operating range and over a temperature range of -55 to 125 C.

Ultrafast dynamics and stabilization in chip-scale optical frequency combs (Conference Presentation)

NASA Astrophysics Data System (ADS)

Huang, Shu Wei

2017-02-01

Optical frequency comb technology has been the cornerstone for scientific breakthroughs such as precision frequency metrology, re-definition of time, extreme light-matter interaction, and attosecond sciences. Recently emerged Kerr-active microresonators are promising alternatives to the current benchmark femtosecond laser platform. These chip-scale frequency combs, or Kerr combs, are unique in their compact footprints and offer the potential for monolithic electronic and feedback integration, thereby expanding the already remarkable applications of optical frequency combs. In this talk, I will first report the generation and characterization of low-phase-noise Kerr frequency combs. Measurements of the Kerr comb ultrafast dynamics and phase noise will be presented and discussed. Then I will describe novel strategies to fully stabilize Kerr comb line frequencies towards chip-scale optical frequency synthesizers with a relative uncertainty better than 2.7×10-16. I will show that the unique generation physics of Kerr frequency comb can provide an intrinsic self-referenced access to the Kerr comb line frequencies. The strategy improves the optical frequency stability by more than two orders of magnitude, while preserving the Kerr comb's key advantage of low SWaP and potential for chip-scale electronic and photonic integration.

Ultra-high-Q phononic resonators on-chip at cryogenic temperatures

NASA Astrophysics Data System (ADS)

Kharel, Prashanta; Chu, Yiwen; Power, Michael; Renninger, William H.; Schoelkopf, Robert J.; Rakich, Peter T.

2018-06-01

Long-lived, high-frequency phonons are valuable for applications ranging from optomechanics to emerging quantum systems. For scientific as well as technological impact, we seek high-performance oscillators that offer a path toward chip-scale integration. Confocal bulk acoustic wave resonators have demonstrated an immense potential to support long-lived phonon modes in crystalline media at cryogenic temperatures. So far, these devices have been macroscopic with cm-scale dimensions. However, as we push these oscillators to high frequencies, we have an opportunity to radically reduce the footprint as a basis for classical and emerging quantum technologies. In this paper, we present novel design principles and simple microfabrication techniques to create high performance chip-scale confocal bulk acoustic wave resonators in a wide array of crystalline materials. We tailor the acoustic modes of such resonators to efficiently couple to light, permitting us to perform a non-invasive laser-based phonon spectroscopy. Using this technique, we demonstrate an acoustic Q-factor of 2.8 × 107 (6.5 × 106) for chip-scale resonators operating at 12.7 GHz (37.8 GHz) in crystalline z-cut quartz (x-cut silicon) at cryogenic temperatures.

On-chip detection of non-classical light by scalable integration of single-photon detectors

PubMed Central

Najafi, Faraz; Mower, Jacob; Harris, Nicholas C.; Bellei, Francesco; Dane, Andrew; Lee, Catherine; Hu, Xiaolong; Kharel, Prashanta; Marsili, Francesco; Assefa, Solomon; Berggren, Karl K.; Englund, Dirk

2015-01-01

Photonic-integrated circuits have emerged as a scalable platform for complex quantum systems. A central goal is to integrate single-photon detectors to reduce optical losses, latency and wiring complexity associated with off-chip detectors. Superconducting nanowire single-photon detectors (SNSPDs) are particularly attractive because of high detection efficiency, sub-50-ps jitter and nanosecond-scale reset time. However, while single detectors have been incorporated into individual waveguides, the system detection efficiency of multiple SNSPDs in one photonic circuit—required for scalable quantum photonic circuits—has been limited to <0.2%. Here we introduce a micrometer-scale flip-chip process that enables scalable integration of SNSPDs on a range of photonic circuits. Ten low-jitter detectors are integrated on one circuit with 100% device yield. With an average system detection efficiency beyond 10%, and estimated on-chip detection efficiency of 14–52% for four detectors operated simultaneously, we demonstrate, to the best of our knowledge, the first on-chip photon correlation measurements of non-classical light. PMID:25575346

On-chip clearing of arrays of 3-D cell cultures and micro-tissues.

PubMed

Grist, S M; Nasseri, S S; Poon, T; Roskelley, C; Cheung, K C

2016-07-01

Three-dimensional (3-D) cell cultures are beneficial models for mimicking the complexities of in vivo tissues, especially in tumour studies where transport limitations can complicate response to cancer drugs. 3-D optical microscopy techniques are less involved than traditional embedding and sectioning, but are impeded by optical scattering properties of the tissues. Confocal and even two-photon microscopy limit sample imaging to approximately 100-200 μm depth, which is insufficient to image hypoxic spheroid cores. Optical clearing methods have permitted high-depth imaging of tissues without physical sectioning, but they are difficult to implement for smaller 3-D cultures due to sample loss in solution exchange. In this work, we demonstrate a microfluidic platform for high-throughput on-chip optical clearing of breast cancer spheroids using the SeeDB, Clear(T2), and ScaleSQ clearing methods. Although all three methods are able to effectively clear the spheroids, we find that SeeDB and ScaleSQ more effectively clear the sample than Clear(T2); however, SeeDB induces green autofluorescence while ScaleS causes sample expansion. Our unique on-chip implementation permits clearing arrays of 3-D cultures using perfusion while monitoring the 3-D cultures throughout the process, enabling visualization of the clearing endpoint as well as monitoring of transient changes that could induce image artefacts. Our microfluidic device is compatible with on-chip 3-D cell culture, permitting the use of on-chip clearing at the endpoint after monitoring the same spheroids during their culture. This on-chip method has the potential to improve readout from 3-D cultures, facilitating their use in cell-based assays for high-content drug screening and other applications.

A cost-effective 25-Gb/s EML TOSA using all-in-one FPCB wiring and metal optical bench.

PubMed

Han, Young-Tak; Kwon, Oh-Kee; Lee, Dong-Hun; Lee, Chul-Wook; Leem, Young-Ahn; Shin, Jang-Uk; Park, Sang-Ho; Baek, Yongsoon

2013-11-04

We present a cost-effective 25-Gb/s electro-absorption modulator integrated laser (EML) transmitter optical sub-assembly (TOSA) using all-in-one flexible printed circuit board (FPCB) wiring and a metal optical bench (MOB). For a low cost and high bandwidth TOSA, internal and external wirings and feed-through of the TOSA to transmit radio-frequency (RF) signal are configured all-in-one using the FPCB. The FPCB is extended from an exterior of the TOSA package up to an EML chip inside the package through the slit formed on a rear sidewall of the package and die-bonded on the MOB. The EML TOSA shows a modulated output power of more than 3.5 dBm and a clear eye pattern with a dynamic extinction ratio of ~8.4 dB at a data rate of 25.78 Gb/s.

MEMS Direct Chip Attach Packaging Methodologies and Apparatuses for Harsh Environments

NASA Technical Reports Server (NTRS)

Okojie, Robert S. (Inventor)

2009-01-01

Methods of bulk manufacturing high temperature sensor subassembly packages are disclosed and claimed. Sensors are sandwiched between a top cover and a bottom cover so as to enable the peripheries of the top covers, sensors and bottom covers to be sealed and bound securely together are disclosed and claimed. Sensors are placed on the bottom covers leaving the periphery of the bottom cover exposed. Likewise, top covers are placed on the sensors leaving the periphery of the sensor exposed. Individual sensor sub-assemblies are inserted into final packaging elements which are also disclosed and claimed. Methods of directly attaching wires or pins to contact pads on the sensors are disclosed and claimed. Sensors, such as pressure sensors and accelerometers, and headers made out of silicon carbide and aluminum nitride are disclosed and claimed. Reference cavities are formed in some embodiments disclosed and claimed herein where top covers are not employed.

MEMS Direct Chip Attach Packaging Methodologies and Apparatuses for Harsh Environments

NASA Technical Reports Server (NTRS)

Okojie, Robert S. (Inventor)

2005-01-01

Methods of bulk manufacturing high temperature sensor sub-assembly packages are disclosed and claimed. Sensors are sandwiched between a top cover and a bottom cover so as to enable the peripheries of the top covers, sensors and bottom covers to be sealed and bound securely together are disclosed and claimed. Sensors are placed on the bottom covers leaving the periphery of the bottom cover exposed. Likewise, top covers are placed on the sensors leaving the periphery of the sensor exposed. Individual sensor sub- assemblies are inserted into final packaging elements which are also disclosed and claimed. Methods of directly attach- ing wires or pins to contact pads on the sensors are disclosed and claimed. Sensors, such as pressure sensors and accelerometers, and headers made out of silicon carbide and aluminum nitride are disclosed and claimed. Reference cavities are formed in some embodiments disclosed and claimed herein where top covers are not employed.

Compact Multimedia Systems in Multi-chip Module Technology

NASA Technical Reports Server (NTRS)

Fang, Wai-Chi; Alkalaj, Leon

1995-01-01

This tutorial paper shows advanced multimedia system designs based on multi-chip module (MCM) technologies that provide essential computing, compression, communication, and storage capabilities for various large scale information highway applications.!.

Method Of Packaging And Assembling Electro-Microfluidic Devices

DOEpatents

Benavides, Gilbert L.; Galambos, Paul C.; Emerson, John A.; Peterson, Kenneth A.; Giunta, Rachel K.; Zamora, David Lee; Watson, Robert D.

2004-11-23

A new architecture for packaging surface micromachined electro-microfluidic devices is presented. This architecture relies on two scales of packaging to bring fluid to the device scale (picoliters) from the macro-scale (microliters). The architecture emulates and utilizes electronics packaging technology. The larger package consists of a circuit board with embedded fluidic channels and standard fluidic connectors (e.g. Fluidic Printed Wiring Board). The embedded channels connect to the smaller package, an Electro-Microfluidic Dual-Inline-Package (EMDIP) that takes fluid to the microfluidic integrated circuit (MIC). The fluidic connection is made to the back of the MIC through Bosch-etched holes that take fluid to surface micromachined channels on the front of the MIC. Electrical connection is made to bond pads on the front of the MIC.

Bypass diode integration

NASA Technical Reports Server (NTRS)

Shepard, N. F., Jr.

1981-01-01

Protective bypass diodes and mounting configurations which are applicable for use with photovoltaic modules having power dissipation requirements in the 5 to 50 watt range were investigated. Using PN silicon and Schottky diode characterization data on packaged diodes and diode chips, typical diodes were selected as representative for each range of current carrying capacity, an appropriate heat dissipating mounting concept along with its environmental enclosure was defined, and a thermal analysis relating junction temperature as a function of power dissipation was performed. In addition, the heat dissipating mounting device dimensions were varied to determine the effect on junction temperature. The results of the analysis are presented as a set of curves indicating junction temperature as a function of power dissipation for each diode package.

Contamination control in hybrid microelectronic modules. Part 3: Specifications for coating material and process controls

NASA Technical Reports Server (NTRS)

Himmel, R. P.

1975-01-01

Resin systems for coating hybrids prior to hermetic sealing are described. The resin systems are a flexible silicone junction resin system and a flexible cycloaliphatic epoxy resin system. The coatings are intended for application to the hybrid after all the chips have been assembled and wire bonded, but prior to hermetic sealing of the package. The purpose of the coating is to control particulate contamination by immobilizing particles and by passivating the hybrid. Recommended process controls for the purpose of minimizing contamination in hybrid microcircuit packages are given. Emphasis is placed on those critical hybrid processing steps in which contamination is most likely to occur.

New developments on high-efficiency infrared and InGaAlP light-emitting diodes at OSRAM Opto Semiconductors

NASA Astrophysics Data System (ADS)

Broell, Markus; Sundgren, Petrus; Rudolph, Andreas; Schmid, Wolfgang; Vogl, Anton; Behringer, Martin

2014-02-01

We present our latest results on developments of infrared and red light emitting diodes. Both chiptypes are based on the Thinfilm technology. For infrared the brightness has been raised by 25% with respect to former products in a package with standard silicon casting, corresponding to a brightness increase of 33% for the bare chip. In a lab package a wallplug efficiency of more than 72% at a wavelength of 850nm could be reached. For red InGaAlP LEDs we could demonstrate a light output in excess of 200lm/W and a brightness of 133lm at a typical operating current of 350mA.

Finite element analysis of a micromechanical deformable mirror device

NASA Technical Reports Server (NTRS)

Sheerer, T. J.; Nelson, W. E.; Hornbeck, L. J.

1989-01-01

A monolithic spatial light modulator chip was developed consisting of a large number of micrometer-scale mirror cells which can be rotated through an angle by application of an electrostatic field. The field is generated by electronics integral to the chip. The chip has application in photoreceptor based non-impact printing technologies. Chips containing over 16000 cells were fabricated, and were tested to several billions of cycles. Finite Element Analysis (FEA) of the device was used to model both the electrical and mechanical characteristics.

Terahertz MMICs and Antenna-in-Package Technology at 300 GHz for KIOSK Download System

NASA Astrophysics Data System (ADS)

Tajima, Takuro; Kosugi, Toshihiko; Song, Ho-Jin; Hamada, Hiroshi; El Moutaouakil, Amine; Sugiyama, Hiroki; Matsuzaki, Hideaki; Yaita, Makoto; Kagami, Osamu

2016-12-01

Toward the realization of ultra-fast wireless communications systems, the inherent broad bandwidth of the terahertz (THz) band is attracting attention, especially for short-range instant download applications. In this paper, we present our recent progress on InP-based THz MMICs and packaging techniques based on low-temperature co-fibered ceramic (LTCC) technology. The transmitter MMICs are based on 80-nm InP-based high electron mobility transistors (HEMTs). Using the transmitter packaged in an E-plane split-block waveguide and compact lens receiver packaged in LTCC multilayered substrates, we tested wireless data transmission up to 27 Gbps with the simple amplitude key shifting (ASK) modulation scheme. We also present several THz antenna-in-packaging solutions based on substrate integrated waveguide (SIW) technology. A vertical hollow (VH) SIW was applied to a compact medium-gain SIW antenna and low-loss interconnection integrated in LTCC multi-layer substrates. The size of the LTCC antennas with 15-dBi gain is less than 0.1 cm3. For feeding the antenna, we investigated an LTCC-integrated transition and polyimide transition to LTCC VH SIWs. These transitions exhibit around 1-dB estimated loss at 300 GHz and more than 35 GHz bandwidth with 10-dB return loss. The proposed package solutions make antennas and interconnections easy to integrate in a compact LTCC package with an MMIC chip for practical applications.

Sustaining Moore's law with 3D chips

DOE Office of Scientific and Technical Information (OSTI.GOV)

DeBenedictis, Erik P.; Badaroglu, Mustafa; Chen, An

Here, rather than continue the expensive and time-consuming quest for transistor replacement, the authors argue that 3D chips coupled with new computer architectures can keep Moore's law on its traditional scaling path.

Sustaining Moore's law with 3D chips

DOE PAGES

DeBenedictis, Erik P.; Badaroglu, Mustafa; Chen, An; ...

2017-08-01

Here, rather than continue the expensive and time-consuming quest for transistor replacement, the authors argue that 3D chips coupled with new computer architectures can keep Moore's law on its traditional scaling path.

Silicon Photonics: Challenges and Future

DTIC Science & Technology

2007-01-01

process or phonon assisted. It directly impacts the internal quantum efficiency through the relationship : ηi = (1+ (τrad/τ non-rad ))-1 There are...linear cavity approach, the reported differential quantum efficiency is currently low. The measured characteristic temperature (To), is lower than...rule changes • package design 4.1.2 Inter-chip interconnects There is a requirement on the circuit card to transfer data more efficiently between

On-Chip Hardware for Cell Monitoring: Contact Imaging and Notch Filtering

DTIC Science & Technology

2005-07-07

a polymer carrier. Spectrophotometer chosen and purchased for testing optical filters and materials. Characterization and comparison of fabricated...reproducibility of behavior. Multi-level SU8 process developed. Optimization of actuator for closing vial lids and development of lid sealing technology is...bending angles characterized as a function of temperature in NaDBS solution. " Photopatternable polymers are a viable interim packaging solution; through

Linear Fresnel Spectrometer Chip with Gradient Line Grating

NASA Technical Reports Server (NTRS)

Choi, Sang Hyouk (Inventor); Park, Yeonjoon (Inventor)

2015-01-01

A spectrometer that includes a grating that disperses light via Fresnel diffraction according to wavelength onto a sensing area that coincides with an optical axis plane of the grating. The sensing area detects the dispersed light and measures the light intensity associated with each wavelength of the light. Because the spectrometer utilizes Fresnel diffraction, it can be miniaturized and packaged as an integrated circuit.

Advanced Sensors for TBI

DTIC Science & Technology

2016-12-01

SMD-VAC- GP, Virtual Industries) with plastic tip. Then the chip was covered with silicone open-cell foam (0.062” thick, HT -870, Stockwell...the build. 26 We discussed with a sub- contractor in Livermore who might be able to perform the packaging assembly work. Dr. Kotovsky...worked with the sub- contractor on practice assemblies anticipating the new upcoming build. Working through an outside contractor represents an enormous

Nitrogen removal in wood chip combined substrate baffled subsurface-flow constructed wetlands: impact of matrix arrangement and intermittent aeration.

PubMed

Li, Huai; Chi, Zifang; Yan, Baixing; Cheng, Long; Li, Jianzheng

2017-02-01

In this study, two lab-scale baffled subsurface-flow constructed wetlands (BSFCWs), including gravel-wood chips-slag and gravel-slag-wood chips, were operated at different intermittent aeration to evaluate the effect of artificial aeration and slow-released carbon source on the treatment efficiency of high-strength nitrogen wastewater. Results indicated that gravel-slag-wood chips extended aerobic/anaerobic alternating environment to gravel and slag zones and maintained anaerobic condition in the subsequent wood chip section. The order of gravel-slag-wood chip was more beneficial to pollutant removal. Sufficient carbon source supply resulted from wood-chip-framework substrate simultaneously obtained high removals of COD (97%), NH 4 + -N (95%), and TN (94%) in BSFCWs at 2 h aeration per day. The results suggest that intermittent aeration combined with wood chips could achieve high nitrogen removal in BSFCWs.

Self-priming compartmentalization digital LAMP for point-of-care.

PubMed

Zhu, Qiangyuan; Gao, Yibo; Yu, Bingwen; Ren, Hao; Qiu, Lin; Han, Sihai; Jin, Wei; Jin, Qinhan; Mu, Ying

2012-11-21

Digital nucleic acid amplification provides unprecedented opportunities for absolute nucleic acid quantification by counting of single molecules. This technique is useful for molecular genetic analysis in cancer, stem cell, bacterial, non-invasive prenatal diagnosis in which many biologists are interested. This paper describes a self-priming compartmentalization (SPC) microfluidic chip platform for performing digital loop-mediated amplification (LAMP). The energy for the pumping is pre-stored in the degassed bulk PDMS by exploiting the high gas solubility of PDMS; therefore, no additional structures other than channels and reservoirs are required. The sample and oil are sequentially sucked into the channels, and the pressure difference of gas dissolved in PDMS allows sample self-compartmentalization without the need for further chip manipulation such as with pneumatic microvalves and control systems, and so on. The SPC digital LAMP chip can be used like a 384-well plate, so, the world-to-chip fluidic interconnections are avoided. The microfluidic chip contains 4 separate panels, each panel contains 1200 independent 6 nL chambers and can be used to detect 4 samples simultaneously. Digital LAMP on the microfluidic chip was tested quantitatively by using β-actin DNA from humans. The self-priming compartmentalization behavior is roughly predictable using a two-dimensional model. The uniformity of compartmentalization was analyzed by fluorescent intensity and fraction of volume. The results showed that the feasibility and flexibility of the microfluidic chip platform for amplifying single nucleic acid molecules in different chambers made by diluting and distributing sample solutions. The SPC chip has the potential to meet the requirements of a general laboratory: power-free, valve-free, operating at isothermal temperature, inexpensive, sensitive, economizing labour time and reagents. The disposable analytical devices with appropriate air-tight packaging should be useful for point-of-care, and enabling it to become one of the common tools for biology research, especially, in point-of-care testing.

Qualification and Reliability for MEMS and IC Packages

NASA Technical Reports Server (NTRS)

Ghaffarian, Reza

2004-01-01

Advanced IC electronic packages are moving toward miniaturization from two key different approaches, front and back-end processes, each with their own challenges. Successful use of more of the back-end process front-end, e.g. microelectromechanical systems (MEMS) Wafer Level Package (WLP), enable reducing size and cost. Use of direct flip chip die is the most efficient approach if and when the issues of know good die and board/assembly are resolved. Wafer level package solve the issue of known good die by enabling package test, but it has its own limitation, e.g., the I/O limitation, additional cost, and reliability. From the back-end approach, system-in-a-package (SIAP/SIP) development is a response to an increasing demand for package and die integration of different functions into one unit to reduce size and cost and improve functionality. MEMS add another challenging dimension to electronic packaging since they include moving mechanical elements. Conventional qualification and reliability need to be modified and expanded in most cases in order to detect new unknown failures. This paper will review four standards that already released or being developed that specifically address the issues on qualification and reliability of assembled packages. Exposures to thermal cycles, monotonic bend test, mechanical shock and drop are covered in these specifications. Finally, mechanical and thermal cycle qualification data generated for MEMS accelerometer will be presented. The MEMS was an element of an inertial measurement unit (IMU) qualified for NASA Mars Exploration Rovers (MERs), Spirit and Opportunity that successfully is currently roaring the Martian surface

Compact holographic optical neural network system for real-time pattern recognition

NASA Astrophysics Data System (ADS)

Lu, Taiwei; Mintzer, David T.; Kostrzewski, Andrew A.; Lin, Freddie S.

1996-08-01

One of the important characteristics of artificial neural networks is their capability for massive interconnection and parallel processing. Recently, specialized electronic neural network processors and VLSI neural chips have been introduced in the commercial market. The number of parallel channels they can handle is limited because of the limited parallel interconnections that can be implemented with 1D electronic wires. High-resolution pattern recognition problems can require a large number of neurons for parallel processing of an image. This paper describes a holographic optical neural network (HONN) that is based on high- resolution volume holographic materials and is capable of performing massive 3D parallel interconnection of tens of thousands of neurons. A HONN with more than 16,000 neurons packaged in an attache case has been developed. Rotation- shift-scale-invariant pattern recognition operations have been demonstrated with this system. System parameters such as the signal-to-noise ratio, dynamic range, and processing speed are discussed.

Multi-petascale highly efficient parallel supercomputer

DOEpatents

Asaad, Sameh; Bellofatto, Ralph E.; Blocksome, Michael A.; Blumrich, Matthias A.; Boyle, Peter; Brunheroto, Jose R.; Chen, Dong; Cher, Chen -Yong; Chiu, George L.; Christ, Norman; Coteus, Paul W.; Davis, Kristan D.; Dozsa, Gabor J.; Eichenberger, Alexandre E.; Eisley, Noel A.; Ellavsky, Matthew R.; Evans, Kahn C.; Fleischer, Bruce M.; Fox, Thomas W.; Gara, Alan; Giampapa, Mark E.; Gooding, Thomas M.; Gschwind, Michael K.; Gunnels, John A.; Hall, Shawn A.; Haring, Rudolf A.; Heidelberger, Philip; Inglett, Todd A.; Knudson, Brant L.; Kopcsay, Gerard V.; Kumar, Sameer; Mamidala, Amith R.; Marcella, James A.; Megerian, Mark G.; Miller, Douglas R.; Miller, Samuel J.; Muff, Adam J.; Mundy, Michael B.; O'Brien, John K.; O'Brien, Kathryn M.; Ohmacht, Martin; Parker, Jeffrey J.; Poole, Ruth J.; Ratterman, Joseph D.; Salapura, Valentina; Satterfield, David L.; Senger, Robert M.; Smith, Brian; Steinmacher-Burow, Burkhard; Stockdell, William M.; Stunkel, Craig B.; Sugavanam, Krishnan; Sugawara, Yutaka; Takken, Todd E.; Trager, Barry M.; Van Oosten, James L.; Wait, Charles D.; Walkup, Robert E.; Watson, Alfred T.; Wisniewski, Robert W.; Wu, Peng

2015-07-14

A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency.

Autonomous micro and nano sensors for upstream oil and gas

NASA Astrophysics Data System (ADS)

Chapman, David; Trybula, Walt

2015-06-01

This paper describes the development of autonomous electronic micro and nanoscale sensor systems for very harsh downhole oilfield conditions and provides an overview of the operational requirements necessary to survive and make direct measurements of subsurface conditions. One of several significant developmental challenges is selecting appropriate technologies that are simultaneously miniaturize-able, integrate-able, harsh environment capable, and economically viable. The Advanced Energy Consortium (AEC) is employing a platform approach to developing and testing multi-chip, millimeter and micron-scale systems in a package at elevated temperature and pressure in API brine and oil analogs, with the future goal of miniaturized systems that enable the collection of previously unattainable data. The ultimate goal is to develop subsurface nanosensor systems that can be injected into oil and gas well bores, to gather and record data, providing an unparalleled level of direct reservoir characterization. This paper provides a status update on the research efforts and developmental successes at the AEC.

Quantum interference in heterogeneous superconducting-photonic circuits on a silicon chip.

PubMed

Schuck, C; Guo, X; Fan, L; Ma, X; Poot, M; Tang, H X

2016-01-21

Quantum information processing holds great promise for communicating and computing data efficiently. However, scaling current photonic implementation approaches to larger system size remains an outstanding challenge for realizing disruptive quantum technology. Two main ingredients of quantum information processors are quantum interference and single-photon detectors. Here we develop a hybrid superconducting-photonic circuit system to show how these elements can be combined in a scalable fashion on a silicon chip. We demonstrate the suitability of this approach for integrated quantum optics by interfering and detecting photon pairs directly on the chip with waveguide-coupled single-photon detectors. Using a directional coupler implemented with silicon nitride nanophotonic waveguides, we observe 97% interference visibility when measuring photon statistics with two monolithically integrated superconducting single-photon detectors. The photonic circuit and detector fabrication processes are compatible with standard semiconductor thin-film technology, making it possible to implement more complex and larger scale quantum photonic circuits on silicon chips.

Inherent polarization entanglement generated from a monolithic semiconductor chip

PubMed Central

Horn, Rolf T.; Kolenderski, Piotr; Kang, Dongpeng; Abolghasem, Payam; Scarcella, Carmelo; Frera, Adriano Della; Tosi, Alberto; Helt, Lukas G.; Zhukovsky, Sergei V.; Sipe, J. E.; Weihs, Gregor; Helmy, Amr S.; Jennewein, Thomas

2013-01-01

Creating miniature chip scale implementations of optical quantum information protocols is a dream for many in the quantum optics community. This is largely because of the promise of stability and scalability. Here we present a monolithically integratable chip architecture upon which is built a photonic device primitive called a Bragg reflection waveguide (BRW). Implemented in gallium arsenide, we show that, via the process of spontaneous parametric down conversion, the BRW is capable of directly producing polarization entangled photons without additional path difference compensation, spectral filtering or post-selection. After splitting the twin-photons immediately after they emerge from the chip, we perform a variety of correlation tests on the photon pairs and show non-classical behaviour in their polarization. Combined with the BRW's versatile architecture our results signify the BRW design as a serious contender on which to build large scale implementations of optical quantum processing devices. PMID:23896982

Single-pipetting microfluidic assay device for rapid detection of Salmonella from poultry package.

PubMed

Fronczek, Christopher F; You, David J; Yoon, Jeong-Yeol

2013-02-15

A direct, sensitive, near-real-time, handheld optical immunoassay device was developed to detect Salmonella typhimurium in the naturally occurring liquid from fresh poultry packages (hereafter "chicken matrix"), with just single pipetting of sample (i.e., no filtration, culturing and/or isolation, thus reducing the assay time and the error associated with them). Carboxylated, polystyrene microparticles were covalently conjugated with anti-Salmonella, and the immunoagglutination due to the presence of Salmonella was detected by reading the Mie scatter signals from the microfluidic channels using a handheld device. The presence of chicken matrix did not affect the light scatter signal, since the optical parameters (particle size d, wavelength of incident light λ and scatter angle θ) were optimized to minimize the effect of sample matrix (animal tissues and blood proteins, etc.). The sample was loaded into a microfluidic chip that was split into two channels, one pre-loaded with vacuum-dried, antibody-conjugated particles and the other with vacuum-dried, bovine serum albumin-conjugated particles. This eliminated the need for a separate negative control, effectively minimizing chip-to-chip and sample-to-sample variations. Particles and the sample were diffused in-channel through chemical agitation by Tween 80, also vacuum-dried within the microchannels. Sequential mixing of the sample to the reagents under a strict laminar flow condition synergistically improved the reproducibility and linearity of the assay. In addition, dried particles were shown to successfully detect lower Salmonella concentrations for up to 8 weeks. The handheld device contains simplified circuitry eliminating unnecessary adjustment stages, providing a stable signal, thus maximizing sensitivity. Total assay time was 10 min, and the detection limit 10 CFU mL(-1) was observed in all matrices, demonstrating the suitability of this device for field assays. Copyright © 2012 Elsevier B.V. All rights reserved.

RF-Trapped Chip Scale Helium Ion Pump (RFT-CHIP)

DTIC Science & Technology

2016-04-06

14. ABSTRACT A miniaturized (~1 cc) magnet -less RF electron trap for a helium ion pump is studied, addressing challenges associated with active...pump, ion pump, electron trap, magnet -less, MEMS, radiofrequency 16. SECURITY CLASSIFICATION OF: 17. LIMITATION OF ABSTRACT 18. NUMBER OF PAGES 19a...scale ion pumps. The Penning cell structure consists of three electrodes (an anode and two cathodes) and a magnet . Planar titanium cathodes are

Fabrication and Characterization of Bi2Te3-Based Chip-Scale Thermoelectric Energy Harvesting Devices

NASA Astrophysics Data System (ADS)

Cornett, Jane; Chen, Baoxing; Haidar, Samer; Berney, Helen; McGuinness, Pat; Lane, Bill; Gao, Yuan; He, Yifan; Sun, Nian; Dunham, Marc; Asheghi, Mehdi; Goodson, Ken; Yuan, Yi; Najafi, Khalil

2017-05-01

Thermoelectric energy harvesters convert otherwise wasted heat into electrical energy. As a result, they have the potential to play a critical role in the autonomous wireless sensor network signal chain. In this paper, we present work carried out on the development of Bi2Te3-based thermoelectric chip-scale energy harvesting devices. Process flow, device demonstration and characterization are highlighted.

Array Receivers and Sound Sources for Three Dimensional Shallow Water Acoustic Field Experiments

DTIC Science & Technology

2016-12-06

upgrade included improving the SHRU clocks by utilizing chip- scale atomic clocks (CSAC), enlarging battery packs to extend the operation duration, and...instrument upgrade included improving the SHRU clocks by utilizing chip-scale atomic clocks (CSAC), enlarging battery packs to extend the operation...Changing the deployment configuration to use dual pressure housings to augment the alkaline primary battery payload to achieve the one-year duration

A Programmable and Configurable Mixed-Mode FPAA SoC

DTIC Science & Technology

2016-03-17

A Programmable and Configurable Mixed-Mode FPAA SoC Sahil Shah, Sihwan Kim, Farhan Adil, Jennifer Hasler, Suma George, Michelle Collins, Richard...Abstract: The authors present a Floating-Gate based, System-On-Chip large-scale Field- Programmable Analog Array IC that integrates divergent concepts...Floating-Gate, SoC, Command Word Classification This paper presents a Floating-Gate (FG) based, System- On-Chip (SoC) large-scale Field- Programmable

Design, processing and testing of LSI arrays, hybrid microelectronics task

NASA Technical Reports Server (NTRS)

Himmel, R. P.; Stuhlbarg, S. M.; Ravetti, R. G.; Zulueta, P. J.; Rothrock, C. W.

1979-01-01

Mathematical cost models previously developed for hybrid microelectronic subsystems were refined and expanded. Rework terms related to substrate fabrication, nonrecurring developmental and manufacturing operations, and prototype production are included. Sample computer programs were written to demonstrate hybrid microelectric applications of these cost models. Computer programs were generated to calculate and analyze values for the total microelectronics costs. Large scale integrated (LST) chips utilizing tape chip carrier technology were studied. The feasibility of interconnecting arrays of LSU chips utilizing tape chip carrier and semiautomatic wire bonding technology was demonstrated.

Polymer waveguides for electro-optical integration in data centers and high-performance computers.

PubMed

Dangel, Roger; Hofrichter, Jens; Horst, Folkert; Jubin, Daniel; La Porta, Antonio; Meier, Norbert; Soganci, Ibrahim Murat; Weiss, Jonas; Offrein, Bert Jan

2015-02-23

To satisfy the intra- and inter-system bandwidth requirements of future data centers and high-performance computers, low-cost low-power high-throughput optical interconnects will become a key enabling technology. To tightly integrate optics with the computing hardware, particularly in the context of CMOS-compatible silicon photonics, optical printed circuit boards using polymer waveguides are considered as a formidable platform. IBM Research has already demonstrated the essential silicon photonics and interconnection building blocks. A remaining challenge is electro-optical packaging, i.e., the connection of the silicon photonics chips with the system. In this paper, we present a new single-mode polymer waveguide technology and a scalable method for building the optical interface between silicon photonics chips and single-mode polymer waveguides.

Microfluidic valve array control system integrating a fluid demultiplexer circuit

NASA Astrophysics Data System (ADS)

Kawai, Kentaro; Arima, Kenta; Morita, Mizuho; Shoji, Shuichi

2015-06-01

This paper proposes an efficient control method for the large-scale integration of microvalves in microfluidic systems. The proposed method can control 2n individual microvalves with 2n + 2 control lines (where n is an integer). The on-chip valves are closed by applying pressure to a control line, similar to conventional pneumatic microvalves. Another control line closes gate valves between the control line to the on-chip valves and the on-chip valves themselves, to preserve the state of the on-chip valves. The remaining control lines select an activated gate valve. While the addressed gate valve is selected by the other control lines, the corresponding on-chip valve is actuated by applying input pressure to the control line to the on-chip valves. Using this method would substantially reduce the number of world-to-chip connectors and off-chip valve controllers. Experiments conducted using a fabricated 28 microvalve array device, comprising 256 individual on-chip valves controlled with 18 (2   ×   8 + 2) control lines, yielded switching speeds for the selected on-chip valve under 90 ms.

Development of low fat potato chips through microwave processing.

PubMed

Joshi, A; Rudra, S G; Sagar, V R; Raigond, P; Dutt, S; Singh, B; Singh, B P

2016-08-01

Since snacks high in fats are known to be a significant source of fat and energy intake, these have been put in high dietary restraint category. Therefore, an attempt was made to process potato chips through microwave processing without incorporation of any oil in potato chips. Microwave processing of potato chips was done using microwave power varying from 180 to 600 W using constant sample size. Among eleven different drying models, Parabolic model was found to be the best fit through non-linear regression analysis to illustrate drying kinetics of potato chips. The structural, textural and colour attributes of microwaved potato chips were similar to commercial fried potato chips. It was found that at 600 W after 2.5-3.0 min of processing, potato chips gained the fracturability and crispiness index as that of commercial fried chips. Microwave processing was found suitable for processing of potato chips with low fat content (~3.09 vs 35.5 % in commercial preparation) and with acceptable sensory scores (≥7.6 on 9.0 point on hedonic scale vs 8.0 of control preparation).

Integrated Optoelectronic Position Sensor for Scanning Micromirrors.

PubMed

Cheng, Xiang; Sun, Xinglin; Liu, Yan; Zhu, Lijun; Zhang, Xiaoyang; Zhou, Liang; Xie, Huikai

2018-03-26

Scanning micromirrors have been used in a wide range of areas, but many of them do not have position sensing built in, which significantly limits their application space. This paper reports an integrated optoelectronic position sensor (iOE-PS) that can measure the linear displacement and tilting angle of electrothermal MEMS (Micro-electromechanical Systems) scanning mirrors. The iOE-PS integrates a laser diode and its driving circuits, a quadrant photo-detector (QPD) and its readout circuits, and a band-gap reference all on a single chip, and it has been fabricated in a standard 0.5 μm CMOS (Complementary Metal Oxide Semiconductor) process. The footprint of the iOE-PS chip is 5 mm × 5 mm. Each quadrant of the QPD has a photosensitive area of 500 µm × 500 µm and the spacing between adjacent quadrants is 500 μm. The iOE-PS chip is simply packaged underneath of an electrothermally-actuated MEMS mirror. Experimental results show that the iOE-PS has a linear response when the MEMS mirror plate moves vertically between 2.0 mm and 3.0 mm over the iOE-PS chip or scans from -5 to +5°. Such MEMS scanning mirrors integrated with the iOE-PS can greatly reduce the complexity and cost of the MEMS mirrors-enabled modules and systems.

A novel model for simulating the racing effect in capillary-driven underfill process in flip chip

NASA Astrophysics Data System (ADS)

Zhu, Wenhui; Wang, Kanglun; Wang, Yan

2018-04-01

Underfill is typically applied in flip chips to increase the reliability of the electronic packagings. In this paper, the evolution of the melt-front shape of the capillary-driven underfill flow is studied through 3D numerical analysis. Two different models, the prevailing surface force model and the capillary model based on the wetted wall boundary condition, are introduced to test their applicability, where level set method is used to track the interface of the two phase flow. The comparison between the simulation results and experimental data indicates that, the surface force model produces better prediction on the melt-front shape, especially in the central area of the flip chip. Nevertheless, the two above models cannot simulate properly the racing effect phenomenon that appears during underfill encapsulation. A novel ‘dynamic pressure boundary condition’ method is proposed based on the validated surface force model. Utilizing this approach, the racing effect phenomenon is simulated with high precision. In addition, a linear relationship is derived from this model between the flow front location at the edge of the flip chip and the filling time. Using the proposed approach, the impact of the underfill-dispensing length on the melt-front shape is also studied.

Real-time label-free biosensing with integrated planar waveguide ring resonators

NASA Astrophysics Data System (ADS)

Sohlström, Hans; Gylfason, Kristinn B.; Hill, Daniel

2010-05-01

We review the use of planar integrated optical waveguide ring resonators for label free bio-sensing and present recent results from two European biosensor collaborations: SABIO and InTopSens. Planar waveguide ring resonators are attractive for label-free biosensing due to their small footprint, high Q-factors, and compatibility with on-chip optics and microfluidics. This enables integrated sensor arrays for compact labs-on-chip. One application of label-free sensor arrays is for point-of-care medical diagnostics. Bringing such powerful tools to the single medical practitioner is an important step towards personalized medicine, but requires addressing a number of issues: improving limit of detection, managing the influence of temperature, parallelization of the measurement for higher throughput and on-chip referencing, efficient light-coupling strategies to simplify alignment, and packaging of the optical chip and integration with microfluidics. From the SABIO project we report refractive index measurement and label-free biosensing in an 8-channel slotwaveguide ring resonator sensor array, within a compact cartridge with integrated microfluidics. The sensors show a volume sensing detection limit of 5 x 10-6 RIU and a surface sensing detection limit of 0.9 pg/mm2. From the InTopSens project we report early results on silicon-on-insulator racetrack resonators.

Fine-grained parallelism accelerating for RNA secondary structure prediction with pseudoknots based on FPGA.

PubMed

Xia, Fei; Jin, Guoqing

2014-06-01

PKNOTS is a most famous benchmark program and has been widely used to predict RNA secondary structure including pseudoknots. It adopts the standard four-dimensional (4D) dynamic programming (DP) method and is the basis of many variants and improved algorithms. Unfortunately, the O(N(6)) computing requirements and complicated data dependency greatly limits the usefulness of PKNOTS package with the explosion in gene database size. In this paper, we present a fine-grained parallel PKNOTS package and prototype system for accelerating RNA folding application based on FPGA chip. We adopted a series of storage optimization strategies to resolve the "Memory Wall" problem. We aggressively exploit parallel computing strategies to improve computational efficiency. We also propose several methods that collectively reduce the storage requirements for FPGA on-chip memory. To the best of our knowledge, our design is the first FPGA implementation for accelerating 4D DP problem for RNA folding application including pseudoknots. The experimental results show a factor of more than 50x average speedup over the PKNOTS-1.08 software running on a PC platform with Intel Core2 Q9400 Quad CPU for input RNA sequences. However, the power consumption of our FPGA accelerator is only about 50% of the general-purpose micro-processors.

Performance of the THS4302 and the Class V Radiation-Tolerant THS4304-SP Silicon Germanium Wideband Amplifiers at Extreme Temperatures

NASA Technical Reports Server (NTRS)

Patterson, Richard L.; Elbuluk, Malik; Hammoud, Ahmad; VanKeuls, Frederick W.

2009-01-01

This report discusses the performance of silicon germanium, wideband gain amplifiers under extreme temperatures. The investigated devices include Texas Instruments THS4304-SP and THS4302 amplifiers. Both chips are manufactured using the BiCom3 process based on silicon germanium technology along with silicon-on-insulator (SOI) buried oxide layers. The THS4304-SP device was chosen because it is a Class V radiation-tolerant (150 kRad, TID silicon), voltage-feedback operational amplifier designed for use in high-speed analog signal applications and is very desirable for NASA missions. It operates with a single 5 V power supply [1]. It comes in a 10-pin ceramic flatpack package, and it provides balanced inputs, low offset voltage and offset current, and high common mode rejection ratio. The fixed-gain THS4302 chip, which comes in a 16-pin leadless package, offers high bandwidth, high slew rate, low noise, and low distortion [2]. Such features have made the amplifier useful in a number of applications such as wideband signal processing, wireless transceivers, intermediate frequency (IF) amplifier, analog-to-digital converter (ADC) preamplifier, digital-to-analog converter (DAC) output buffer, measurement instrumentation, and medical and industrial imaging.

Effect of micro-scale texturing on the cutting tool performance

NASA Astrophysics Data System (ADS)

Vasumathy, D.; Meena, Anil

2018-05-01

The present study is mainly focused on the cutting performance of the micro-scale textured carbide tools while turning AISI 304 austenitic stainless steel under dry cutting environment. The texture on the rake face of the carbide tools was fabricated by laser machining. The cutting performance of the textured tools was further compared with conventional tools in terms of cutting forces, tool wear, machined surface quality and chip curl radius. SEM and EDS analyses have been also performed to better understand the tool surface characteristics. Results show that the grooves help in breaking the tool-chip contact leading to a lesser tool-chip contact area which results in reduced iron (Fe) adhesion to the tool.

Power-Amplifier Module for 145 to 165 GHz

NASA Technical Reports Server (NTRS)

Samoska, Lorene; Peralta, Alejandro

2007-01-01

A power-amplifier module that operates in the frequency range of 145 to 165 GHz has been designed and constructed as a combination of (1) a previously developed monolithic microwave integrated circuit (MMIC) power amplifier and (2) a waveguide module. The amplifier chip was needed for driving a high-electron-mobility-transistor (HEMT) frequency doubler. While it was feasible to connect the amplifier and frequency-doubler chips by use of wire bonds, it was found to be much more convenient to test the amplifier and doubler chips separately. To facilitate separate testing, it was decided to package the amplifier and doubler chips in separate waveguide modules. Figure 1 shows the resulting amplifier module. The amplifier chip was described in "MMIC HEMT Power Amplifier for 140 to 170 GHz" (NPO-30127), NASA Tech Briefs, Vol. 27, No. 11, (November 2003), page 49. To recapitulate: This is a three-stage MMIC power amplifier that utilizes HEMTs as gain elements. The amplifier was originally designed to operate in the frequency range of 140 to 170 GHz. The waveguide module is based on a previously developed lower frequency module, redesigned to support operation in the frequency range of 140 to 220 GHz. Figure 2 presents results of one of several tests of the amplifier module - measurements of output power and gain as functions of input power at an output frequency of 150 GHz. Such an amplifier module has many applications to test equipment for power sources above 100 GHz.

System-on-Chip Considerations for Heterogeneous Integration of CMOS and Fluidic Bio-Interfaces.

PubMed

Datta-Chaudhuri, Timir; Smela, Elisabeth; Abshire, Pamela A

2016-12-01

CMOS chips are increasingly used for direct sensing and interfacing with fluidic and biological systems. While many biosensing systems have successfully combined CMOS chips for readout and signal processing with passive sensing arrays, systems that co-locate sensing with active circuits on a single chip offer significant advantages in size and performance but increase the complexity of multi-domain design and heterogeneous integration. This emerging class of lab-on-CMOS systems also poses distinct and vexing technical challenges that arise from the disparate requirements of biosensors and integrated circuits (ICs). Modeling these systems must address not only circuit design, but also the behavior of biological components on the surface of the IC and any physical structures. Existing tools do not support the cross-domain simulation of heterogeneous lab-on-CMOS systems, so we recommend a two-step modeling approach: using circuit simulation to inform physics-based simulation, and vice versa. We review the primary lab-on-CMOS implementation challenges and discuss practical approaches to overcome them. Issues include new versions of classical challenges in system-on-chip integration, such as thermal effects, floor-planning, and signal coupling, as well as new challenges that are specifically attributable to biological and fluidic domains, such as electrochemical effects, non-standard packaging, surface treatments, sterilization, microfabrication of surface structures, and microfluidic integration. We describe these concerns as they arise in lab-on-CMOS systems and discuss solutions that have been experimentally demonstrated.

Advanced Flip Chips in Extreme Temperature Environments

NASA Technical Reports Server (NTRS)

Ramesham, Rajeshuni

2010-01-01

The use of underfill materials is necessary with flip-chip interconnect technology to redistribute stresses due to mismatching coefficients of thermal expansion (CTEs) between dissimilar materials in the overall assembly. Underfills are formulated using organic polymers and possibly inorganic filler materials. There are a few ways to apply the underfills with flip-chip technology. Traditional capillary-flow underfill materials now possess high flow speed and reduced time to cure, but they still require additional processing steps beyond the typical surface-mount technology (SMT) assembly process. Studies were conducted using underfills in a temperature range of -190 to 85 C, which resulted in an increase of reliability by one to two orders of magnitude. Thermal shock of the flip-chip test articles was designed to induce failures at the interconnect sites (-40 to 100 C). The study on the reliability of flip chips using underfills in the extreme temperature region is of significant value for space applications. This technology is considered as an enabling technology for future space missions. Flip-chip interconnect technology is an advanced electrical interconnection approach where the silicon die or chip is electrically connected, face down, to the substrate by reflowing solder bumps on area-array metallized terminals on the die to matching footprints of solder-wettable pads on the chosen substrate. This advanced flip-chip interconnect technology will significantly improve the performance of high-speed systems, productivity enhancement over manual wire bonding, self-alignment during die joining, low lead inductances, and reduced need for attachment of precious metals. The use of commercially developed no-flow fluxing underfills provides a means of reducing the processing steps employed in the traditional capillary flow methods to enhance SMT compatibility. Reliability of flip chips may be significantly increased by matching/tailoring the CTEs of the substrate material and the silicon die or chip, and also the underfill materials. Advanced packaging interconnects technology such as flip-chip interconnect test boards have been subjected to various extreme temperature ranges that cover military specifications and extreme Mars and asteroid environments. The eventual goal of each process step and the entire process is to produce components with 100 percent interconnect and satisfy the reliability requirements. Underfill materials, in general, may possibly meet demanding end use requirements such as low warpage, low stress, fine pitch, high reliability, and high adhesion.

Robust optical sensors for safety critical automotive applications

NASA Astrophysics Data System (ADS)

De Locht, Cliff; De Knibber, Sven; Maddalena, Sam

2008-02-01

Optical sensors for the automotive industry need to be robust, high performing and low cost. This paper focuses on the impact of automotive requirements on optical sensor design and packaging. Main strategies to lower optical sensor entry barriers in the automotive market include: Perform sensor calibration and tuning by the sensor manufacturer, sensor test modes on chip to guarantee functional integrity at operation, and package technology is key. As a conclusion, optical sensor applications are growing in automotive. Optical sensor robustness matured to the level of safety critical applications like Electrical Power Assisted Steering (EPAS) and Drive-by-Wire by optical linear arrays based systems and Automated Cruise Control (ACC), Lane Change Assist and Driver Classification/Smart Airbag Deployment by camera imagers based systems.

Planned development of a 3D computer based on free-space optical interconnects

NASA Astrophysics Data System (ADS)

Neff, John A.; Guarino, David R.

1994-05-01

Free-space optical interconnection has the potential to provide upwards of a million data channels between planes of electronic circuits. This may result in the planar board and backplane structures of today giving away to 3-D stacks of wafers or multi-chip modules interconnected via channels running perpendicular to the processor planes, thereby eliminating much of the packaging overhead. Three-dimensional packaging is very appealing for tightly coupled fine-grained parallel computing where the need for massive numbers of interconnections is severely taxing the capabilities of the planar structures. This paper describes a coordinated effort by four research organizations to demonstrate an operational fine-grained parallel computer that achieves global connectivity through the use of free space optical interconnects.

Pulp Chip Quality from In-woods Chippers Coupled with Chain Flail Delimbers-Debarkers: Does it Match Conventional Woodyard Quality?

Treesearch

W.F. Watson; A.A. Twaddle; B.J. Stokes

1991-01-01

Chain flail delimber-debarkers have gained a degree of acceptance in the Southern USA, especially for processing thinnings from pine plantations. TIzis Technical Release compares the quality of chips produced by in-woods chippers teamed with chain flail delimber-debarkers, with chips produced in conventional large-scale woodyards, to be a guideline as to what may occur...

Submillimeter-Wave Amplifier Module with Integrated Waveguide Transitions

NASA Technical Reports Server (NTRS)

Samoska, Lorene; Chattopadhyay, Goutam; Pukala, David; Gaier, Todd; Soria, Mary; ManFung, King; Deal, William; Mei, Gerry; Radisic, Vesna; Lai, Richard

2009-01-01

To increase the usefulness of monolithic millimeter-wave integrated circuit (MMIC) components at submillimeter-wave frequencies, a chip has been designed that incorporates two integrated, radial E-plane probes with an MMIC amplifier in between, thus creating a fully integrated waveguide module. The integrated amplifier chip has been fabricated in 35-nm gate length InP high-electron-mobility-transistor (HEMT) technology. The radial probes were mated to grounded coplanar waveguide input and output lines in the internal amplifier. The total length of the internal HEMT amplifier is 550 m, while the total integrated chip length is 1,085 m. The chip thickness is 50 m with the chip width being 320 m. The internal MMIC amplifier is biased through wire-bond connections to the gates and drains of the chip. The chip has 3 stages, employing 35-nm gate length transistors in each stage. Wire bonds from the DC drain and gate pads are connected to off-chip shunt 51-pF capacitors, and additional off-chip capacitors and resistors are added to the gate and drain bias lines for low-frequency stability of the amplifier. Additionally, bond wires to the grounded coplanar waveguide pads at the RF input and output of the internal amplifier are added to ensure good ground connections to the waveguide package. The S-parameters of the module, not corrected for input or output waveguide loss, are measured at the waveguide flange edges. The amplifier module has over 10 dB of gain from 290 to 330 GHz, with a peak gain of over 14 dB at 307 GHz. The WR2.2 waveguide cutoff is again observed at 268 GHz. The module is biased at a drain current of 27 mA, a drain voltage of 1.24 V, and a gate voltage of +0.21 V. Return loss of the module is very good between 5 to 25 dB. This result illustrates the usefulness of the integrated radial probe transition, and the wide (over 10-percent) bandwidth that one can expect for amplifier modules with integrated radial probes in the submillimeter-regime (>300 GHz).

A novel miniaturized PCR multi-reactor array fabricated using flip-chip bonding techniques

NASA Astrophysics Data System (ADS)

Zou, Zhi-Qing; Chen, Xiang; Jin, Qing-Hui; Yang, Meng-Su; Zhao, Jian-Long

2005-08-01

This paper describes a novel miniaturized multi-chamber array capable of high throughput polymerase chain reaction (PCR). The structure of the proposed device is verified by using finite element analysis (FEA) to optimize the thermal performance, and then implemented on a glass-silicon substrate using a standard MEMS process and post-processing. Thermal analysis simulation and verification of each reactor cell is equipped with integrated Pt temperature sensors and heaters at the bottom of the reaction chamber for real-time accurate temperature sensing and control. The micro-chambers are thermally separated from each other, and can be controlled independently. The multi-chip array was packaged on a printed circuit board (PCB) substrate using a conductive polymer flip-chip bonding technique, which enables effective heat dissipation and suppresses thermal crosstalk between the chambers. The designed system has successfully demonstrated a temperature fluctuation of ±0.5 °C during thermal multiplexing of up to 2 × 2 chambers, a full speed of 30 min for 30 cycle PCR, as well as the capability of controlling each chamber digitally and independently.

Reliability of High I/O High Density CCGA Interconnect Electronic Packages under Extreme Thermal Environment

NASA Technical Reports Server (NTRS)

Ramesham, Rajeshuni

2012-01-01

This paper provides the experimental test results of advanced CCGA packages tested in extreme temperature thermal environments. Standard optical inspection and x-ray non-destructive inspection tools were used to assess the reliability of high density CCGA packages for deep space extreme temperature missions. Ceramic column grid array (CCGA) packages have been increasing in use based on their advantages such as high interconnect density, very good thermal and electrical performances, compatibility with standard surface-mount packaging assembly processes, and so on. CCGA packages are used in space applications such as in logic and microprocessor functions, telecommunications, payload electronics, and flight avionics. As these packages tend to have less solder joint strain relief than leaded packages or more strain relief over lead-less chip carrier packages, the reliability of CCGA packages is very important for short-term and long-term deep space missions. We have employed high density CCGA 1152 and 1272 daisy chained electronic packages in this preliminary reliability study. Each package is divided into several daisy-chained sections. The physical dimensions of CCGA1152 package is 35 mm x 35 mm with a 34 x 34 array of columns with a 1 mm pitch. The dimension of the CCGA1272 package is 37.5 mm x 37.5 mm with a 36 x 36 array with a 1 mm pitch. The columns are made up of 80% Pb/20%Sn material. CCGA interconnect electronic package printed wiring polyimide boards have been assembled and inspected using non-destructive x-ray imaging techniques. The assembled CCGA boards were subjected to extreme temperature thermal atmospheric cycling to assess their reliability for future deep space missions. The resistance of daisy-chained interconnect sections were monitored continuously during thermal cycling. This paper provides the experimental test results of advanced CCGA packages tested in extreme temperature thermal environments. Standard optical inspection and x-ray non-destructive inspection tools were used to assess the reliability of high density CCGA packages for deep space extreme temperature missions. Keywords: Extreme temperatures, High density CCGA qualification, CCGA reliability, solder joint failures, optical inspection, and x-ray inspection.

Stratified randomization controls better for batch effects in 450K methylation analysis: a cautionary tale.

PubMed

Buhule, Olive D; Minster, Ryan L; Hawley, Nicola L; Medvedovic, Mario; Sun, Guangyun; Viali, Satupaitea; Deka, Ranjan; McGarvey, Stephen T; Weeks, Daniel E

2014-01-01

Batch effects in DNA methylation microarray experiments can lead to spurious results if not properly handled during the plating of samples. Two pilot studies examining the association of DNA methylation patterns across the genome with obesity in Samoan men were investigated for chip- and row-specific batch effects. For each study, the DNA of 46 obese men and 46 lean men were assayed using Illumina's Infinium HumanMethylation450 BeadChip. In the first study (Sample One), samples from obese and lean subjects were examined on separate chips. In the second study (Sample Two), the samples were balanced on the chips by lean/obese status, age group, and census region. We used methylumi, watermelon, and limma R packages, as well as ComBat, to analyze the data. Principal component analysis and linear regression were, respectively, employed to identify the top principal components and to test for their association with the batches and lean/obese status. To identify differentially methylated positions (DMPs) between obese and lean males at each locus, we used a moderated t-test. Chip effects were effectively removed from Sample Two but not Sample One. In addition, dramatic differences were observed between the two sets of DMP results. After "removing" batch effects with ComBat, Sample One had 94,191 probes differentially methylated at a q-value threshold of 0.05 while Sample Two had zero differentially methylated probes. The disparate results from Sample One and Sample Two likely arise due to the confounding of lean/obese status with chip and row batch effects. Even the best possible statistical adjustments for batch effects may not completely remove them. Proper study design is vital for guarding against spurious findings due to such effects.

Stratified randomization controls better for batch effects in 450K methylation analysis: a cautionary tale

PubMed Central

Buhule, Olive D.; Minster, Ryan L.; Hawley, Nicola L.; Medvedovic, Mario; Sun, Guangyun; Viali, Satupaitea; Deka, Ranjan; McGarvey, Stephen T.; Weeks, Daniel E.

2014-01-01

Background: Batch effects in DNA methylation microarray experiments can lead to spurious results if not properly handled during the plating of samples. Methods: Two pilot studies examining the association of DNA methylation patterns across the genome with obesity in Samoan men were investigated for chip- and row-specific batch effects. For each study, the DNA of 46 obese men and 46 lean men were assayed using Illumina's Infinium HumanMethylation450 BeadChip. In the first study (Sample One), samples from obese and lean subjects were examined on separate chips. In the second study (Sample Two), the samples were balanced on the chips by lean/obese status, age group, and census region. We used methylumi, watermelon, and limma R packages, as well as ComBat, to analyze the data. Principal component analysis and linear regression were, respectively, employed to identify the top principal components and to test for their association with the batches and lean/obese status. To identify differentially methylated positions (DMPs) between obese and lean males at each locus, we used a moderated t-test. Results: Chip effects were effectively removed from Sample Two but not Sample One. In addition, dramatic differences were observed between the two sets of DMP results. After “removing” batch effects with ComBat, Sample One had 94,191 probes differentially methylated at a q-value threshold of 0.05 while Sample Two had zero differentially methylated probes. The disparate results from Sample One and Sample Two likely arise due to the confounding of lean/obese status with chip and row batch effects. Conclusion: Even the best possible statistical adjustments for batch effects may not completely remove them. Proper study design is vital for guarding against spurious findings due to such effects. PMID:25352862

A scalable self-priming fractal branching microchannel net chip for digital PCR.

PubMed

Zhu, Qiangyuan; Xu, Yanan; Qiu, Lin; Ma, Congcong; Yu, Bingwen; Song, Qi; Jin, Wei; Jin, Qinhan; Liu, Jinyu; Mu, Ying

2017-05-02

As an absolute quantification method at the single-molecule level, digital PCR has been widely used in many bioresearch fields, such as next generation sequencing, single cell analysis, gene editing detection and so on. However, existing digital PCR methods still have some disadvantages, including high cost, sample loss, and complicated operation. In this work, we develop an exquisite scalable self-priming fractal branching microchannel net digital PCR chip. This chip with a special design inspired by natural fractal-tree systems has an even distribution and 100% compartmentalization of the sample without any sample loss, which is not available in existing chip-based digital PCR methods. A special 10 nm nano-waterproof layer was created to prevent the solution from evaporating. A vacuum pre-packaging method called self-priming reagent introduction is used to passively drive the reagent flow into the microchannel nets, so that this chip can realize sequential reagent loading and isolation within a couple of minutes, which is very suitable for point-of-care detection. When the number of positive microwells stays in the range of 100 to 4000, the relative uncertainty is below 5%, which means that one panel can detect an average of 101 to 15 374 molecules by the Poisson distribution. This chip is proved to have an excellent ability for single molecule detection and quantification of low expression of hHF-MSC stem cell markers. Due to its potential for high throughput, high density, low cost, lack of sample and reagent loss, self-priming even compartmentalization and simple operation, we envision that this device will significantly expand and extend the application range of digital PCR involving rare samples, liquid biopsy detection and point-of-care detection with higher sensitivity and accuracy.

Three-dimensional integrated circuits for lab-on-chip dielectrophoresis of nanometer scale particles

NASA Astrophysics Data System (ADS)

Dickerson, Samuel J.; Noyola, Arnaldo J.; Levitan, Steven P.; Chiarulli, Donald M.

2007-01-01

In this paper, we present a mixed-technology micro-system for electronically manipulating and optically detecting virusscale particles in fluids that is designed using 3D integrated circuit technology. During the 3D fabrication process, the top-most chip tier is assembled upside down and the substrate material is removed. This places the polysilicon layer, which is used to create geometries with the process' minimum feature size, in close proximity to a fluid channel etched into the top of the stack. By taking advantage of these processing features inherent to "3D chip-stacking" technology, we create electrode arrays that have a gap spacing of 270 nm. Using 3D CMOS technology also provides the ability to densely integrate analog and digital control circuitry for the electrodes by using the additional levels of the chip stack. We show simulations of the system with a physical model of a Kaposi's sarcoma-associated herpes virus, which has a radius of approximately 125 nm, being dielectrophoretically arranged into striped patterns. We also discuss how these striped patterns of trapped nanometer scale particles create an effective diffraction grating which can then be sensed with macro-scale optical techniques.

From Global to Cloud Resolving Scale: Experiments with a Scale- and Aerosol-Aware Physics Package and Impact on Tracer Transport

NASA Astrophysics Data System (ADS)

Grell, G. A.; Freitas, S. R.; Olson, J.; Bela, M.

2017-12-01

We will start by providing a summary of the latest cumulus parameterization modeling efforts at NOAA's Earth System Research Laboratory (ESRL) will be presented on both regional and global scales. The physics package includes a scale-aware parameterization of subgrid cloudiness feedback to radiation (coupled PBL, microphysics, radiation, shallow and congestus type convection), the stochastic Grell-Freitas (GF) scale- and aerosol-aware convective parameterization, and an aerosol aware microphysics package. GF is based on a stochastic approach originally implemented by Grell and Devenyi (2002) and described in more detail in Grell and Freitas (2014, ACP). It was expanded to include PDF's for vertical mass flux, as well as modifications to improve the diurnal cycle. This physics package will be used on different scales, spanning global to cloud resolving, to look at the impact on scalar transport and numerical weather prediction.

Low temperature fluidized wood chip drying with monoterpene analysis

Treesearch

Bridget N. Bero; Alarick Reiboldt; Ward Davis; Natalie Bedard; Evan Russell

2011-01-01

This paper describes the drying of ponderosa pine wood chips at low (20°C and 50°C) temperatures using a bench-scale batch pulsed fluidizer to evaluate both volatile pine oils (monoterpenes) and moisture losses during drying.

Reliability and Qualification of Hardware to Enhance the Mission Assurance of JPL/NASA Projects

NASA Technical Reports Server (NTRS)

Ramesham, Rajeshuni

2010-01-01

Packaging Qualification and Verification (PQV) and life testing of advanced electronic packaging, mechanical assemblies (motors/actuators), and interconnect technologies (flip-chip), platinum temperature thermometer attachment processes, and various other types of hardware for Mars Exploration Rover (MER)/Mars Science Laboratory (MSL), and JUNO flight projects was performed to enhance the mission assurance. The qualification of hardware under extreme cold to hot temperatures was performed with reference to various project requirements. The flight like packages, assemblies, test coupons, and subassemblies were selected for the study to survive three times the total number of expected temperature cycles resulting from all environmental and operational exposures occurring over the life of the flight hardware including all relevant manufacturing, ground operations, and mission phases. Qualification/life testing was performed by subjecting flight-like qualification hardware to the environmental temperature extremes and assessing any structural failures, mechanical failures or degradation in electrical performance due to either overstress or thermal cycle fatigue. Experimental flight qualification test results will be described in this presentation.

Reliability Analysis/Assessment of Advanced Technologies

DTIC Science & Technology

1990-05-01

34, Reliability Physics 1980 , IEEE, p. 165. 25. RADC-TR-83-244. 26. Towner, Janet M., et. al., "Aluminum Electromigration Under Pulsed D.C. Conditions...Duvvury, Redwine, Kitagawa, Haas, Chuang, Beydler, Hyslop , "Impact of Hot Carriers On DRAM circuits", 1987 IEEE/IRPS. 58. Cahoon, Thornewell, Tsai...et. a]., "Substrate for Large Silicon Chip and Full Wafer Packaging", Semiconductor International, pp. 149-156, April 1980 . 5. T.E. Lewis and D.L

Natural Convection Cooling of a Three by Three Array of Leadless Chip Carrier Packages in a Dielectric Liquid

DTIC Science & Technology

1994-03-24

sources. gathering and maintaining the data needed, and completing and reviewing the collection of information. Send comments regarding ths burden estimate...for .oration Operations and Reports. 1215 Jefferson Davis Highway. Suite 1204. Arlington. VA 22202-4302. and to the Office of Management and Budget...ceramic substrate was examined. Baseline data were obtained for cooling with pure dielectric liquids. The effects of addition of high thermal

Silicon photonics integrated circuits: a manufacturing platform for high density, low power optical I/O's.

PubMed

Absil, Philippe P; Verheyen, Peter; De Heyn, Peter; Pantouvaki, Marianna; Lepage, Guy; De Coster, Jeroen; Van Campenhout, Joris

2015-04-06

Silicon photonics integrated circuits are considered to enable future computing systems with optical input-outputs co-packaged with CMOS chips to circumvent the limitations of electrical interfaces. In this paper we present the recent progress made to enable dense multiplexing by exploiting the integration advantage of silicon photonics integrated circuits. We also discuss the manufacturability of such circuits, a key factor for a wide adoption of this technology.

Latest Progress in High Power VECSELs

DTIC Science & Technology

2013-01-01

are more efficient, and can be tailored to an application. In this manuscript we lay out some advantages to VECSELs as compared to many in-plane...semiconductor lasers. We review common fabrication and packaging techniques in Section 2. In Section 3, we discuss both small- signal and large-signal... out LR coating MQW DBR VECSEL chip Heat Spreader output coupler HR flat mirror BF at Brewster’s angle HR flat mirror HR curved mirror signal beam out

Beam test results of a monolithic pixel sensor in the 0.18 μm tower-jazz technology with high resistivity epitaxial layer

NASA Astrophysics Data System (ADS)

Mattiazzo, S.; Aimo, I.; Baudot, J.; Bedda, C.; La Rocca, P.; Perez, A.; Riggi, F.; Spiriti, E.

2015-10-01

The ALICE experiment at CERN will undergo a major upgrade in the second Long LHC Shutdown in the years 2018-2019; this upgrade includes the full replacement of the Inner Tracking System (ITS), deploying seven layers of Monolithic Active Pixel Sensors (MAPS). For the development of the new ALICE ITS, the Tower-Jazz 0.18 μm CMOS imaging sensor process has been chosen as it is possible to use full CMOS in the pixel and different silicon wafers (including high resistivity epitaxial layers). A large test campaign has been carried out on several small prototype chips, designed to optimize the pixel sensor layout and the front-end electronics. Results match the target requirements both in terms of performance and of radiation hardness. Following this development, the first full scale chips have been designed, submitted and are currently under test, with promising results. A telescope composed of 4 planes of Mimosa-28 and 2 planes of Mimosa-18 chips is under development at the DAFNE Beam Test Facility (BTF) at the INFN Laboratori Nazionali di Frascati (LNF) in Italy with the final goal to perform a comparative test of the full scale prototypes. The telescope has been recently used to test a Mimosa-22THRb chip (a monolithic pixel sensor built in the 0.18 μm Tower-Jazz process) and we foresee to perform tests on the full scale chips for the ALICE ITS upgrade at the beginning of 2015. In this contribution we will describe some first measurements of spatial resolution, fake hit rate and detection efficiency of the Mimosa-22THRb chip obtained at the BTF facility in June 2014 with an electron beam of 500 MeV.

Recent lab-on-chip developments for novel drug discovery.

PubMed

Khalid, Nauman; Kobayashi, Isao; Nakajima, Mitsutoshi

2017-07-01

Microelectromechanical systems (MEMS) and micro total analysis systems (μTAS) revolutionized the biochemical and electronic industries, and this miniaturization process became a key driver for many markets. Now, it is a driving force for innovations in life sciences, diagnostics, analytical sciences, and chemistry, which are called 'lab-on-a-chip, (LOC)' devices. The use of these devices allows the development of fast, portable, and easy-to-use systems with a high level of functional integration for applications such as point-of-care diagnostics, forensics, the analysis of biomolecules, environmental or food analysis, and drug development. In this review, we report on the latest developments in fabrication methods and production methodologies to tailor LOC devices. A brief overview of scale-up strategies is also presented together with their potential applications in drug delivery and discovery. The impact of LOC devices on drug development and discovery has been extensively reviewed in the past. The current research focuses on fast and accurate detection of genomics, cell mutations and analysis, drug delivery, and discovery. The current research also differentiates the LOC devices into new terminology of microengineering, like organ-on-a-chip, stem cells-on-a-chip, human-on-a-chip, and body-on-a-chip. Key challenges will be the transfer of fabricated LOC devices from lab-scale to industrial large-scale production. Moreover, extensive toxicological studies are needed to justify the use of microfabricated drug delivery vehicles in biological systems. It will also be challenging to transfer the in vitro findings to suitable and promising in vivo models. WIREs Syst Biol Med 2017, 9:e1381. doi: 10.1002/wsbm.1381 For further resources related to this article, please visit the WIREs website. © 2017 Wiley Periodicals, Inc.

Quantum interference in heterogeneous superconducting-photonic circuits on a silicon chip

PubMed Central

Schuck, C.; Guo, X.; Fan, L.; Ma, X.; Poot, M.; Tang, H. X.

2016-01-01

Quantum information processing holds great promise for communicating and computing data efficiently. However, scaling current photonic implementation approaches to larger system size remains an outstanding challenge for realizing disruptive quantum technology. Two main ingredients of quantum information processors are quantum interference and single-photon detectors. Here we develop a hybrid superconducting-photonic circuit system to show how these elements can be combined in a scalable fashion on a silicon chip. We demonstrate the suitability of this approach for integrated quantum optics by interfering and detecting photon pairs directly on the chip with waveguide-coupled single-photon detectors. Using a directional coupler implemented with silicon nitride nanophotonic waveguides, we observe 97% interference visibility when measuring photon statistics with two monolithically integrated superconducting single-photon detectors. The photonic circuit and detector fabrication processes are compatible with standard semiconductor thin-film technology, making it possible to implement more complex and larger scale quantum photonic circuits on silicon chips. PMID:26792424

Low loss hollow-core waveguide on a silicon substrate

NASA Astrophysics Data System (ADS)

Yang, Weijian; Ferrara, James; Grutter, Karen; Yeh, Anthony; Chase, Chris; Yue, Yang; Willner, Alan E.; Wu, Ming C.; Chang-Hasnain, Connie J.

2012-07-01

Optical-fiber-based, hollow-core waveguides (HCWs) have opened up many new applications in laser surgery, gas sensors, and non-linear optics. Chip-scale HCWs are desirable because they are compact, light-weight and can be integrated with other devices into systems-on-a-chip. However, their progress has been hindered by the lack of a low loss waveguide architecture. Here, a completely new waveguiding concept is demonstrated using two planar, parallel, silicon-on-insulator wafers with high-contrast subwavelength gratings to reflect light in-between. We report a record low optical loss of 0.37 dB/cm for a 9-μm waveguide, mode-matched to a single mode fiber. Two-dimensional light confinement is experimentally realized without sidewalls in the HCWs, which is promising for ultrafast sensing response with nearly instantaneous flow of gases or fluids. This unique waveguide geometry establishes an entirely new scheme for low-cost chip-scale sensor arrays and lab-on-a-chip applications.

A monolithically integrated polarization entangled photon pair source on a silicon chip

PubMed Central

Matsuda, Nobuyuki; Le Jeannic, Hanna; Fukuda, Hiroshi; Tsuchizawa, Tai; Munro, William John; Shimizu, Kaoru; Yamada, Koji; Tokura, Yasuhiro; Takesue, Hiroki

2012-01-01

Integrated photonic circuits are one of the most promising platforms for large-scale photonic quantum information systems due to their small physical size and stable interferometers with near-perfect lateral-mode overlaps. Since many quantum information protocols are based on qubits defined by the polarization of photons, we must develop integrated building blocks to generate, manipulate, and measure the polarization-encoded quantum state on a chip. The generation unit is particularly important. Here we show the first integrated polarization-entangled photon pair source on a chip. We have implemented the source as a simple and stable silicon-on-insulator photonic circuit that generates an entangled state with 91 ± 2% fidelity. The source is equipped with versatile interfaces for silica-on-silicon or other types of waveguide platforms that accommodate the polarization manipulation and projection devices as well as pump light sources. Therefore, we are ready for the full-scale implementation of photonic quantum information systems on a chip. PMID:23150781

RAM Technology Study.

DTIC Science & Technology

1980-01-03

characteristics. 4 2 Example of MOS scaling. 18 3 RAM chip area comparison. 31 4 Summary of RAM switching response. 34 5 Summary of RAM power dissipation...array to retain the data after power is removed (volatility). The level of chip complexity is that of the most complex arrays in current production and is...4) ..4 L) . C U ~~~~ -- -- t 0 -, 4 4 . . Data in the Read-Only-Memory is defined by the metallization pattern during chip fabrication. The stored

Packaging of structural health monitoring components

NASA Astrophysics Data System (ADS)

Kessler, Seth S.; Spearing, S. Mark; Shi, Yong; Dunn, Christopher T.

2004-07-01

Structural Health Monitoring (SHM) technologies have the potential to realize economic benefits in a broad range of commercial and defense markets. Previous research conducted by Metis Design and MIT has demonstrated the ability of Lamb waves methods to provide reliable information regarding the presence, location and type of damage in composite specimens. The present NSF funded program was aimed to study manufacturing, packaging and interface concepts for critical SHM components. The intention is to be able to cheaply manufacture robust actuating/sensing devices, and isolate them from harsh operating environments including natural, mechanical, or electrical extremes. Currently the issues related to SHM system durability have remained undressed. During the course of this research several sets of test devices were fabricated and packaged to protect the piezoelectric component assemblies for robust operation. These assemblies were then tested in hot and wet conditions, as well as in electrically noisy environments. Future work will aim to package the other supporting components such as the battery and wireless chip, as well as integrating all of these components together for operation. SHM technology will enable the reduction or complete elimination of scheduled inspections, and will allow condition-based maintenance for increased reliability and reduced overall life-cycle costs.

Management of Chronic Periodontitis Using Chlorhexidine Chip and Diode Laser-A Clinical Study.

PubMed

Jose, Kachapilly Arun; Ambooken, Majo; Mathew, Jayan Jacob; Issac, Annie Valayil; Kunju, Ajithkumar Parachalil; Parameshwaran, Renjith Athirkandathil

2016-04-01

The use of adjuncts like chlorhexidine local delivery and diode laser decontamination have been found to improve the clinical outcomes of scaling and root planing in non-surgical periodontal therapy in patients with chronic periodontitis. To evaluate the effects of diode laser and chlorhexidine chip as adjuncts to scaling and root planing in the management of chronic periodontitis. The objective is to evaluate the outcome of chlorhexidine chip and diode laser as adjuncts to scaling and root planing on clinical parameters like Plaque Index, Gingival Index, probing pocket depth and clinical attachment level. Department of Periodontics. Randomized clinical trial with split mouth design. Fifteen chronic periodontitis patients having a probing pocket depth of 5mm-7mm on at least one interproximal site in each quadrant of the mouth were included in the study. After initial treatment, four sites in each patient were randomly subjected to scaling and root planing (control), chlorhexidine chip application (CHX chip group), diode laser (810 nm) decontamination (Diode laser group) or combination of both (Diode laser and chip group). Plaque Index (PI), Gingival Index (GI), probing pocket depth (PPD) and clinical attachment level (CAL) were assessed at baseline, one month and three months. Results were statistically analysed using paired T test, one-way ANOVA, Tukey's HSD test and repeated measure ANOVA. Post-treatment, the test and control sites showed a statistically significant reduction in PI, GI, PPD, and CAL. After three months, a mean PPD reduction of 1.47±0.52 mm in control group, 1.40±0.83 mm in diode laser group, 2.67±0.62 mm in CHX group, and 2.80± 0.77 mm in combination group was seen. The mean gain in CAL were 1.47±0.52 mm in the control group, 1.40±0.83 mm in diode laser group, 2.67± 0.49 mm in CHX group and 2.67± 0.82 mm in combination group respectively. The differences in PPD reduction and CAL gain between control group and CHX chip and combination groups were statistically significant (p<0.05) at three months, whereas, the diode laser group did not show any significant difference from the control group. Chlorhexidine local delivery alone or in combination with diode laser decontamination is effective in reducing probing pocket depth and improving clinical attachment levels when used as adjuncts to scaling and root planing in non-surgical periodontal therapy of patients with chronic periodontitis.

Management of Chronic Periodontitis Using Chlorhexidine Chip and Diode Laser-A Clinical Study

PubMed Central

Ambooken, Majo; Mathew, Jayan Jacob; Issac, Annie Valayil; Kunju, Ajithkumar Parachalil; Parameshwaran, Renjith Athirkandathil

2016-01-01

Introduction The use of adjuncts like chlorhexidine local delivery and diode laser decontamination have been found to improve the clinical outcomes of scaling and root planing in non-surgical periodontal therapy in patients with chronic periodontitis. Aim To evaluate the effects of diode laser and chlorhexidine chip as adjuncts to scaling and root planing in the management of chronic periodontitis. The objective is to evaluate the outcome of chlorhexidine chip and diode laser as adjuncts to scaling and root planing on clinical parameters like Plaque Index, Gingival Index, probing pocket depth and clinical attachment level. Study and Design Department of Periodontics. Randomized clinical trial with split mouth design. Materials and Methods Fifteen chronic periodontitis patients having a probing pocket depth of 5mm-7mm on at least one interproximal site in each quadrant of the mouth were included in the study. After initial treatment, four sites in each patient were randomly subjected to scaling and root planing (control), chlorhexidine chip application (CHX chip group), diode laser (810 nm) decontamination (Diode laser group) or combination of both (Diode laser and chip group). Plaque Index (PI), Gingival Index (GI), probing pocket depth (PPD) and clinical attachment level (CAL) were assessed at baseline, one month and three months. Statistical analysis Results were statistically analysed using paired T test, one-way ANOVA, Tukey’s HSD test and repeated measure ANOVA. Results Post-treatment, the test and control sites showed a statistically significant reduction in PI, GI, PPD, and CAL. After three months, a mean PPD reduction of 1.47±0.52 mm in control group, 1.40±0.83 mm in diode laser group, 2.67±0.62 mm in CHX group, and 2.80± 0.77 mm in combination group was seen. The mean gain in CAL were 1.47±0.52 mm in the control group, 1.40±0.83 mm in diode laser group, 2.67± 0.49 mm in CHX group and 2.67± 0.82 mm in combination group respectively. The differences in PPD reduction and CAL gain between control group and CHX chip and combination groups were statistically significant (p<0.05) at three months, whereas, the diode laser group did not show any significant difference from the control group. Conclusion Chlorhexidine local delivery alone or in combination with diode laser decontamination is effective in reducing probing pocket depth and improving clinical attachment levels when used as adjuncts to scaling and root planing in non-surgical periodontal therapy of patients with chronic periodontitis. PMID:27190958

Ferric plasmonic nanoparticles, aptamers, and magnetofluidic chips: toward the development of diagnostic surface-enhanced Raman spectroscopy assays

NASA Astrophysics Data System (ADS)

Marks, Haley; Huang, Po-Jung; Mabbott, Samuel; Graham, Duncan; Kameoka, Jun; Coté, Gerard

2016-12-01

Conjugation of aptamers and their corresponding analytes onto plasmonic nanoparticles mediates the formation of nanoparticle assemblies: molecularly bound nanoclusters that cause a measurable change in the colloid's optical properties. The optimization of a surface-enhanced Raman spectroscopy (SERS) competitive binding assay utilizing plasmonic "target" and magnetic "probe" nanoparticles for the detection of the toxin bisphenol-A (BPA) is presented. These assay nanoclusters were housed inside three types of optofluidic chips patterned with magnetically activated nickel pads, in either a straight or array pattern. Both Fe2O3 and Fe2CoO4 were compared as potential magnetic cores for the silver-coated probe nanoparticles. We found that the Ag@Fe2O3 particles were, on average, more uniform in size and more stable than Ag@Fe2CoO4, whereas the addition of cobalt significantly improved the collection time of particles. Using Raman mapping of the assay housed within the magnetofluidic chips, it was determined that a 1×5 array of 50 μm square nickel pads provided the most uniform SERS enhancement of the assay (coefficient of variation ˜25%) within the magnetofluidic chip. Additionally, the packaged assay demonstrated the desired response to BPA, verifying the technology's potential to translate magnetic nanoparticle assays into a user-free optical analysis platform.

Low-to-high refractive index contrast transition (RICT) device for low loss polymer-based optical coupling

NASA Astrophysics Data System (ADS)

Calabretta, N.; Cooman, I. A.; Stabile, R.

2018-04-01

We propose for the first time a coupling device concept for passive low-loss optical coupling, which is compatible with the ‘generic’ indium phosphide (InP) multi-project-wafer manufacturing. A low-to-high vertical refractive index contrast transition InP waveguide is designed and tapered down to adiabatically couple light into a top polymer waveguide. The on-chip embedded polymer waveguide is engineered at the chip facets for offering refractive-index and spot-size-matching to silica fiber-arrays. Numerical analysis shows that coupling losses lower than 1.5 dB can be achieved for a TE-polarized light between the InP waveguide and the on-chip embedded polymer waveguide at 1550 nm wavelength. The performance is mainly limited by the difficulty to control single-mode operation. However, coupling losses lower than 1.9 dB can be achieved for a bandwidth as large as 200 nm. Moreover, the foreseen fabrication process steps are indicated, which are compatible with the ‘generic’ InP multi-project-wafer manufacturing. A fabrication error tolerance study is performed, indicating that fabrication errors occur only in 0.25 dB worst case excess losses, as long as high precision lithography is used. The obtained results are promising and may open the route to large port counts and cheap packaging of InP-based photonic integrated chips.

Integrated Optoelectronic Position Sensor for Scanning Micromirrors

PubMed Central

Cheng, Xiang; Sun, Xinglin; Liu, Yan; Zhu, Lijun; Zhang, Xiaoyang; Zhou, Liang

2018-01-01

Scanning micromirrors have been used in a wide range of areas, but many of them do not have position sensing built in, which significantly limits their application space. This paper reports an integrated optoelectronic position sensor (iOE-PS) that can measure the linear displacement and tilting angle of electrothermal MEMS (Micro-electromechanical Systems) scanning mirrors. The iOE-PS integrates a laser diode and its driving circuits, a quadrant photo-detector (QPD) and its readout circuits, and a band-gap reference all on a single chip, and it has been fabricated in a standard 0.5 μm CMOS (Complementary Metal Oxide Semiconductor) process. The footprint of the iOE-PS chip is 5 mm × 5 mm. Each quadrant of the QPD has a photosensitive area of 500 µm × 500 µm and the spacing between adjacent quadrants is 500 μm. The iOE-PS chip is simply packaged underneath of an electrothermally-actuated MEMS mirror. Experimental results show that the iOE-PS has a linear response when the MEMS mirror plate moves vertically between 2.0 mm and 3.0 mm over the iOE-PS chip or scans from −5 to +5°. Such MEMS scanning mirrors integrated with the iOE-PS can greatly reduce the complexity and cost of the MEMS mirrors-enabled modules and systems. PMID:29587451

A programmable microsystem using system-on-chip for real-time biotelemetry.

PubMed

Wang, Lei; Johannessen, Erik A; Hammond, Paul A; Cui, Li; Reid, Stuart W J; Cooper, Jonathan M; Cumming, David R S

2005-07-01

A telemetry microsystem, including multiple sensors, integrated instrumentation and a wireless interface has been implemented. We have employed a methodology akin to that for System-on-Chip microelectronics to design an integrated circuit instrument containing several "intellectual property" blocks that will enable convenient reuse of modules in future projects. The present system was optimized for low-power and included mixed-signal sensor circuits, a programmable digital system, a feedback clock control loop and RF circuits integrated on a 5 mm x 5 mm silicon chip using a 0.6 microm, 3.3 V CMOS process. Undesirable signal coupling between circuit components has been investigated and current injection into sensitive instrumentation nodes was minimized by careful floor-planning. The chip, the sensors, a magnetic induction-based transmitter and two silver oxide cells were packaged into a 36 mm x 12 mm capsule format. A base station was built in order to retrieve the data from the microsystem in real-time. The base station was designed to be adaptive and timing tolerant since the microsystem design was simplified to reduce power consumption and size. The telemetry system was found to have a packet error rate of 10(-3) using an asynchronous simplex link. Trials in animal carcasses were carried out to show that the transmitter was as effective as a conventional RF device whilst consuming less power.

Active books: the design of an implantable stimulator that minimizes cable count using integrated circuits very close to electrodes.

PubMed

Liu, Xiao; Demosthenous, Andreas; Vanhoestenberghe, Anne; Jiang, Dai; Donaldson, Nick

2012-06-01

This paper presents an integrated stimulator that can be embedded in implantable electrode books for interfacing with nerve roots at the cauda equina. The Active Book overcomes the limitation of conventional nerve root stimulators which can only support a small number of stimulating electrodes due to cable count restriction through the dura. Instead, a distributed stimulation system with many tripole electrodes can be configured using several Active Books which are addressed sequentially. The stimulator was fabricated in a 0.6-μm high-voltage CMOS process and occupies a silicon area of 4.2 × 6.5 mm(2). The circuit was designed to deliver up to 8 mA stimulus current to tripole electrodes from an 18 V power supply. Input pad count is limited to five (two power and three control lines) hence requiring a specific procedure for downloading stimulation commands to the chip and extracting information from it. Supported commands include adjusting the amplitude of stimulus current, varying the current ratio at the two anodes in each channel, and measuring relative humidity inside the chip package. In addition to stimulation mode, the chip supports quiescent mode, dissipating less than 100 nA current from the power supply. The performance of the stimulator chip was verified with bench tests including measurements using tripoles in saline.

Nanophotonic lab-on-a-chip platforms including novel bimodal interferometers, microfluidics and grating couplers.

PubMed

Duval, Daphné; González-Guerrero, Ana Belén; Dante, Stefania; Osmond, Johann; Monge, Rosa; Fernández, Luis J; Zinoviev, Kirill E; Domínguez, Carlos; Lechuga, Laura M

2012-05-08

One of the main limitations for achieving truly lab-on-a-chip (LOC) devices for point-of-care diagnosis is the incorporation of the "on-chip" detection. Indeed, most of the state-of-the-art LOC devices usually require complex read-out instrumentation, losing the main advantages of portability and simplicity. In this context, we present our last advances towards the achievement of a portable and label-free LOC platform with highly sensitive "on-chip" detection by using nanophotonic biosensors. Bimodal waveguide interferometers fabricated by standard silicon processes have been integrated with sub-micronic grating couplers for efficient light in-coupling, showing a phase resolution of 6.6 × 10(-4)× 2π rad and a limit of detection of 3.3 × 10(-7) refractive index unit (RIU) in bulk. A 3D network of SU-8 polymer microfluidics monolithically assembled at the wafer-level was included, ensuring perfect sealing and compact packaging. To overcome some of the drawbacks inherent to interferometric read-outs, a novel all-optical wavelength modulation system has been implemented, providing a linear response and a direct read-out of the phase variation. Sensitivity, specificity and reproducibility of the wavelength modulated BiMW sensor has been demonstrated through the label-free immunodetection of the human hormone hTSH at picomolar level using a reliable biofunctionalization process.

Reliable, Low-Cost, Low-Weight, Non-Hermetic Coating for MCM Applications

NASA Technical Reports Server (NTRS)

Jones, Eric W.; Licari, James J.

2000-01-01

Through an Air Force Research Laboratory sponsored STM program, reliable, low-cost, low-weight, non-hermetic coatings for multi-chip-module(MCK applications were developed. Using the combination of Sandia Laboratory ATC-01 test chips, AvanTeco's moisture sensor chips(MSC's), and silicon slices, we have shown that organic and organic/inorganic overcoatings are reliable and practical non-hermetic moisture and oxidation barriers. The use of the MSC and unpassivated ATC-01 test chips provided rapid test results and comparison of moisture barrier quality of the overcoatings. The organic coatings studied were Parylene and Cyclotene. The inorganic coatings were Al2O3 and SiO2. The choice of coating(s) is dependent on the environment that the device(s) will be exposed to. We have defined four(4) classes of environments: Class I(moderate temperature/moderate humidity). Class H(high temperature/moderate humidity). Class III(moderate temperature/high humidity). Class IV(high temperature/high humidity). By subjecting the components to adhesion, FTIR, temperature-humidity(TH), pressure cooker(PCT), and electrical tests, we have determined that it is possible to reduce failures 50-70% for organic/inorganic coated components compared to organic coated components. All materials and equipment used are readily available commercially or are standard in most semiconductor fabrication lines. It is estimated that production cost for the developed technology would range from $1-10/module, compared to $20-200 for hermetically sealed packages.

Ferric plasmonic nanoparticles, aptamers, and magnetofluidic chips: toward the development of diagnostic surface-enhanced Raman spectroscopy assays

PubMed Central

Marks, Haley; Huang, Po-Jung; Mabbott, Samuel; Graham, Duncan; Kameoka, Jun; Coté, Gerard

2016-01-01

Abstract. Conjugation of aptamers and their corresponding analytes onto plasmonic nanoparticles mediates the formation of nanoparticle assemblies: molecularly bound nanoclusters that cause a measurable change in the colloid’s optical properties. The optimization of a surface-enhanced Raman spectroscopy (SERS) competitive binding assay utilizing plasmonic “target” and magnetic “probe” nanoparticles for the detection of the toxin bisphenol-A (BPA) is presented. These assay nanoclusters were housed inside three types of optofluidic chips patterned with magnetically activated nickel pads, in either a straight or array pattern. Both Fe2O3 and Fe2CoO4 were compared as potential magnetic cores for the silver-coated probe nanoparticles. We found that the Ag@Fe2O3 particles were, on average, more uniform in size and more stable than Ag@Fe2CoO4, whereas the addition of cobalt significantly improved the collection time of particles. Using Raman mapping of the assay housed within the magnetofluidic chips, it was determined that a 1×5 array of 50  μm square nickel pads provided the most uniform SERS enhancement of the assay (coefficient of variation ∼25%) within the magnetofluidic chip. Additionally, the packaged assay demonstrated the desired response to BPA, verifying the technology’s potential to translate magnetic nanoparticle assays into a user-free optical analysis platform. PMID:27997017

Matched wideband low-noise amplifiers for radio astronomy.

PubMed

Weinreb, S; Bardin, J; Mani, H; Jones, G

2009-04-01

Two packaged low noise amplifiers for the 0.3-4 GHz frequency range are described. The amplifiers can be operated at temperatures of 300-4 K and achieve noise temperatures in the 5 K range (<0.1 dB noise figure) at 15 K physical temperature. One amplifier utilizes commercially available, plastic-packaged SiGe transistors for first and second stages; the second amplifier is identical except it utilizes an experimental chip transistor as the first stage. Both amplifiers use resistive feedback to provide input reflection coefficient S11<-10 dB over a decade bandwidth with gain over 30 dB. The amplifiers can be used as rf amplifiers in very low noise radio astronomy systems or as i.f. amplifiers following superconducting mixers operating in the millimeter and submillimeter frequency range.

The Design and Implementation of NASA's Advanced Flight Computing Module

NASA Technical Reports Server (NTRS)

Alkakaj, Leon; Straedy, Richard; Jarvis, Bruce

1995-01-01

This paper describes a working flight computer Multichip Module developed jointly by JPL and TRW under their respective research programs in a collaborative fashion. The MCM is fabricated by nCHIP and is packaged within a 2 by 4 inch Al package from Coors. This flight computer module is one of three modules under development by NASA's Advanced Flight Computer (AFC) program. Further development of the Mass Memory and the programmable I/O MCM modules will follow. The three building block modules will then be stacked into a 3D MCM configuration. The mass and volume of the flight computer MCM achieved at 89 grams and 1.5 cubic inches respectively, represent a major enabling technology for future deep space as well as commercial remote sensing applications.

High data rate Reed-Solomon encoding and decoding using VLSI technology

NASA Technical Reports Server (NTRS)

Miller, Warner; Morakis, James

1987-01-01

Presented as an implementation of a Reed-Solomon encode and decoder, which is 16-symbol error correcting, each symbol is 8 bits. This Reed-Solomon (RS) code is an efficient error correcting code that the National Aeronautics and Space Administration (NASA) will use in future space communications missions. A Very Large Scale Integration (VLSI) implementation of the encoder and decoder accepts data rates up 80 Mbps. A total of seven chips are needed for the decoder (four of the seven decoding chips are customized using 3-micron Complementary Metal Oxide Semiconduction (CMOS) technology) and one chip is required for the encoder. The decoder operates with the symbol clock being the system clock for the chip set. Approximately 1.65 billion Galois Field (GF) operations per second are achieved with the decoder chip set and 640 MOPS are achieved with the encoder chip.

Biosensor system-on-a-chip including CMOS-based signal processing circuits and 64 carbon nanotube-based sensors for the detection of a neurotransmitter.

PubMed

Lee, Byung Yang; Seo, Sung Min; Lee, Dong Joon; Lee, Minbaek; Lee, Joohyung; Cheon, Jun-Ho; Cho, Eunju; Lee, Hyunjoong; Chung, In-Young; Park, Young June; Kim, Suhwan; Hong, Seunghun

2010-04-07

We developed a carbon nanotube (CNT)-based biosensor system-on-a-chip (SoC) for the detection of a neurotransmitter. Here, 64 CNT-based sensors were integrated with silicon-based signal processing circuits in a single chip, which was made possible by combining several technological breakthroughs such as efficient signal processing, uniform CNT networks, and biocompatible functionalization of CNT-based sensors. The chip was utilized to detect glutamate, a neurotransmitter, where ammonia, a byproduct of the enzymatic reaction of glutamate and glutamate oxidase on CNT-based sensors, modulated the conductance signals to the CNT-based sensors. This is a major technological advancement in the integration of CNT-based sensors with microelectronics, and this chip can be readily integrated with larger scale lab-on-a-chip (LoC) systems for various applications such as LoC systems for neural networks.

A user's guide to the ssWavelets package

Treesearch

J.H. ​Gove

2017-01-01

ssWavelets is an R package that is meant to be used in conjunction with the sampSurf package (Gove, 2012) to perform wavelet decomposition on the results of a sampling surface simulation. In general, the wavelet filter decomposes the sampSurf simulation results by scale (distance), with each scale corresponding to a different level of the...

On-chip spectroscopy with thermally tuned high-Q photonic crystal cavities

DOE Office of Scientific and Technical Information (OSTI.GOV)

Liapis, Andreas C., E-mail: andreas.liapis@gmail.com; Gao, Boshen; Siddiqui, Mahmudur R.

2016-01-11

Spectroscopic methods are a sensitive way to determine the chemical composition of potentially hazardous materials. Here, we demonstrate that thermally tuned high-Q photonic crystal cavities can be used as a compact high-resolution on-chip spectrometer. We have used such a chip-scale spectrometer to measure the absorption spectra of both acetylene and hydrogen cyanide in the 1550 nm spectral band and show that we can discriminate between the two chemical species even though the two materials have spectral features in the same spectral region. Our results pave the way for the development of chip-size chemical sensors that can detect toxic substances.

Phase Equilibria of the Sn-Ni-Si Ternary System and Interfacial Reactions in Sn-(Cu)/Ni-Si Couples

NASA Astrophysics Data System (ADS)

Fang, Gu; Chen, Chih-chi

2015-07-01

Interfacial reactions in Sn/Ni-4.5 wt.%Si and Sn-Cu/Ni-4.5 wt.%Si couples at 250°C, and Sn-Ni-Si ternary phase equilibria at 250°C were investigated in this study. Ni-Si alloys, which are nonmagnetic, can be regarded as a diffusion barrier layer material in flip chip packaging. Solder/Ni-4.5 wt.%Si interfacial reactions are crucial to the reliability of soldered joints. Phase equilibria information is essential for development of solder/Ni-Si materials. No ternary compound is present in the Sn-Ni-Si ternary system at 250°C. Extended solubility of Si in the phases Ni3Sn2 and Ni3Sn is 3.8 and 6.1 at.%, respectively. As more Si dissolves in these phases their lattice constants decrease. No noticeable ternary solubility is observed for the other intermetallics. Interfacial reactions in solder/Ni-4.5 wt.%Si are similar to those for solder/Ni. Si does not alter the reaction phases. No Si solubility in the reaction phases was detected, although rates of growth of the reaction phases were reduced. Because the alloy Ni-4.5 wt.%Si reacts more slowly with solders than pure Ni, the Ni-4.5 wt.%Si alloy could be a potential new diffusion barrier layer material for flip chip packaging.

RCP: a novel probe design bias correction method for Illumina Methylation BeadChip.

PubMed

Niu, Liang; Xu, Zongli; Taylor, Jack A

2016-09-01

The Illumina HumanMethylation450 BeadChip has been extensively utilized in epigenome-wide association studies. This array and its successor, the MethylationEPIC array, use two types of probes-Infinium I (type I) and Infinium II (type II)-in order to increase genome coverage but differences in probe chemistries result in different type I and II distributions of methylation values. Ignoring the difference in distributions between the two probe types may bias downstream analysis. Here, we developed a novel method, called Regression on Correlated Probes (RCP), which uses the existing correlation between pairs of nearby type I and II probes to adjust the beta values of all type II probes. We evaluate the effect of this adjustment on reducing probe design type bias, reducing technical variation in duplicate samples, improving accuracy of measurements against known standards, and retention of biological signal. We find that RCP is statistically significantly better than unadjusted data or adjustment with alternative methods including SWAN and BMIQ. We incorporated the method into the R package ENmix, which is freely available from the Bioconductor website (https://www.bioconductor.org/packages/release/bioc/html/ENmix.html). niulg@ucmail.uc.edu Supplementary data are available at Bioinformatics online. Published by Oxford University Press 2016. This work is written by US Government employees and is in the public domain in the US.

Evaluation of a fast and flexible OPC package: OPTISSIMO

NASA Astrophysics Data System (ADS)

Maurer, Wilhelm; Waas, Thomas; Eisenmann, Hans

1996-12-01

It is out of question, that current state-of-the-art lithography--printing 350 nm structures with i-line tools or 250 nm structures with DUV tools--needs to correct for proximity effects (OPC). Otherwise, all the well-known effects like line-end shortening, linewidth variation as a function of adjacent patterns, linewidth non-linearity, etc. will produce a pattern, that is significantly different from the intended design. In this paper, we report first evaluation results of OPTISSIMO, a software package for automatic proximity correction. Besides the ability to handle full-chip designs by preserving as much as possible of the original data-hierarchy, there are significant options for the user. A large number of choices can be made to balance between the precision of the correction and the complexity of the corrected design. The main target of our evaluations was to check for full-chip OPC for the gate level of a state-of-the-art design. This corresponds to print either linewidths in the 350 nm to 400 nm range with i-line lithography or 250 nm/300 nm linewidth with DUV lithography. Taking 400 nm i-line lithography as an example, 3% precision OPC which has been demonstrated. By using hierarchical data handling, it was shown, that even the data complexity of a 256 M DRAM can be managed within reasonable time.

A coral-on-a-chip microfluidic platform enabling live-imaging microscopy of reef-building corals

PubMed Central

Shapiro, Orr H.; Kramarsky-Winter, Esti; Gavish, Assaf R.; Stocker, Roman; Vardi, Assaf

2016-01-01

Coral reefs, and the unique ecosystems they support, are facing severe threats by human activities and climate change. Our understanding of these threats is hampered by the lack of robust approaches for studying the micro-scale interactions between corals and their environment. Here we present an experimental platform, coral-on-a-chip, combining micropropagation and microfluidics to allow direct microscopic study of live coral polyps. The small and transparent coral micropropagates are ideally suited for live-imaging microscopy, while the microfluidic platform facilitates long-term visualization under controlled environmental conditions. We demonstrate the usefulness of this approach by imaging coral micropropagates at previously unattainable spatio-temporal resolutions, providing new insights into several micro-scale processes including coral calcification, coral–pathogen interaction and the loss of algal symbionts (coral bleaching). Coral-on-a-chip thus provides a powerful method for studying coral physiology in vivo at the micro-scale, opening new vistas in coral biology. PMID:26940983

Nanoliter-Scale Oil-Air-Droplet Chip-Based Single Cell Proteomic Analysis.

PubMed

Li, Zi-Yi; Huang, Min; Wang, Xiu-Kun; Zhu, Ying; Li, Jin-Song; Wong, Catherine C L; Fang, Qun

2018-04-17

Single cell proteomic analysis provides crucial information on cellular heterogeneity in biological systems. Herein, we describe a nanoliter-scale oil-air-droplet (OAD) chip for achieving multistep complex sample pretreatment and injection for single cell proteomic analysis in the shotgun mode. By using miniaturized stationary droplet microreaction and manipulation techniques, our system allows all sample pretreatment and injection procedures to be performed in a nanoliter-scale droplet with minimum sample loss and a high sample injection efficiency (>99%), thus substantially increasing the analytical sensitivity for single cell samples. We applied the present system in the proteomic analysis of 100 ± 10, 50 ± 5, 10, and 1 HeLa cell(s), and protein IDs of 1360, 612, 192, and 51 were identified, respectively. The OAD chip-based system was further applied in single mouse oocyte analysis, with 355 protein IDs identified at the single oocyte level, which demonstrated its special advantages of high enrichment of sequence coverage, hydrophobic proteins, and enzymatic digestion efficiency over the traditional in-tube system.

A low-frequency chip-scale optomechanical oscillator with 58 kHz mechanical stiffening and more than 100th-order stable harmonics.

PubMed

Huang, Yongjun; Flores, Jaime Gonzalo Flor; Cai, Ziqiang; Yu, Mingbin; Kwong, Dim-Lee; Wen, Guangjun; Churchill, Layne; Wong, Chee Wei

2017-06-29

For the sensitive high-resolution force- and field-sensing applications, the large-mass microelectromechanical system (MEMS) and optomechanical cavity have been proposed to realize the sub-aN/Hz 1/2 resolution levels. In view of the optomechanical cavity-based force- and field-sensors, the optomechanical coupling is the key parameter for achieving high sensitivity and resolution. Here we demonstrate a chip-scale optomechanical cavity with large mass which operates at ≈77.7 kHz fundamental mode and intrinsically exhibiting large optomechanical coupling of 44 GHz/nm or more, for both optical resonance modes. The mechanical stiffening range of ≈58 kHz and a more than 100 th -order harmonics are obtained, with which the free-running frequency instability is lower than 10 -6 at 100 ms integration time. Such results can be applied to further improve the sensing performance of the optomechanical inspired chip-scale sensors.

A coral-on-a-chip microfluidic platform enabling live-imaging microscopy of reef-building corals.

PubMed

Shapiro, Orr H; Kramarsky-Winter, Esti; Gavish, Assaf R; Stocker, Roman; Vardi, Assaf

2016-03-04

Coral reefs, and the unique ecosystems they support, are facing severe threats by human activities and climate change. Our understanding of these threats is hampered by the lack of robust approaches for studying the micro-scale interactions between corals and their environment. Here we present an experimental platform, coral-on-a-chip, combining micropropagation and microfluidics to allow direct microscopic study of live coral polyps. The small and transparent coral micropropagates are ideally suited for live-imaging microscopy, while the microfluidic platform facilitates long-term visualization under controlled environmental conditions. We demonstrate the usefulness of this approach by imaging coral micropropagates at previously unattainable spatio-temporal resolutions, providing new insights into several micro-scale processes including coral calcification, coral-pathogen interaction and the loss of algal symbionts (coral bleaching). Coral-on-a-chip thus provides a powerful method for studying coral physiology in vivo at the micro-scale, opening new vistas in coral biology.

A Fast Turn-Around Facility for Very Large Scale Integration (VLSI)

DTIC Science & Technology

1982-06-01

statistics determination, the first test mask set will use the MATRIX chip design which was recently developed here at Stanford. This chip provides...reached when the basewidth is reduced to zero. Such devices, variably known as depleted- base transistors or bipolar static-induction transitors , have been

On testing VLSI chips for the big Viterbi decoder

NASA Technical Reports Server (NTRS)

Hsu, I. S.

1989-01-01

A general technique that can be used in testing very large scale integrated (VLSI) chips for the Big Viterbi Decoder (BVD) system is described. The test technique is divided into functional testing and fault-coverage testing. The purpose of functional testing is to verify that the design works functionally. Functional test vectors are converted from outputs of software simulations which simulate the BVD functionally. Fault-coverage testing is used to detect and, in some cases, to locate faulty components caused by bad fabrication. This type of testing is useful in screening out bad chips. Finally, design for testability, which is included in the BVD VLSI chip design, is described in considerable detail. Both the observability and controllability of a VLSI chip are greatly enhanced by including the design for the testability feature.

Rapid analysis of protein interactions: On-chip micropurification of recombinant protein expressed in Esherichia coli.

PubMed

Natsume, Tohru; Taoka, Masato; Manki, Hiroshi; Kume, Shouen; Isobe, Toshiaki; Mikoshiba, Katsuhiko

2002-09-01

We describe a rapid analysis of interactions between antibodies and a recombinant protein present in total cell lysates. Using a surface plasmon resonance biosensor, a low concentration of glutathione-S-transferase (GST) fused protein expressed in small scale Esherichia coli culture was purified on an anti-GST antibody immobilized sensor chip. The 'on-chip purification' was verified using matrix-assisted laser desorption/ionization-time of flight mass spectrometry by measuring the molecular masses of recombinant proteins purified on the sensor chip. The specific binding of monoclonal antibodies for the on-chip micropurified recombinant proteins can then be monitored, thus enabling kinetic analysis and epitope mapping of the bound antibodies. This approach reduced time, resources and sample consumption by avoiding conventional steps related to concentration and purification.

Determination of pore-scale hydrate phase equilibria in sediments using lab-on-a-chip technology.

PubMed

Almenningen, Stian; Flatlandsmo, Josef; Kovscek, Anthony R; Ersland, Geir; Fernø, Martin A

2017-11-21

We present an experimental protocol for fast determination of hydrate stability in porous media for a range of pressure and temperature (P, T) conditions. Using a lab-on-a-chip approach, we gain direct optical access to dynamic pore-scale hydrate formation and dissociation events to study the hydrate phase equilibria in sediments. Optical pore-scale observations of phase behavior reproduce the theoretical hydrate stability line with methane gas and distilled water, and demonstrate the accuracy of the new method. The procedure is applicable for any kind of hydrate transitions in sediments, and may be used to map gas hydrate stability zones in nature.

Concurrent heterogeneous neural model simulation on real-time neuromimetic hardware.

PubMed

Rast, Alexander; Galluppi, Francesco; Davies, Sergio; Plana, Luis; Patterson, Cameron; Sharp, Thomas; Lester, David; Furber, Steve

2011-11-01

Dedicated hardware is becoming increasingly essential to simulate emerging very-large-scale neural models. Equally, however, it needs to be able to support multiple models of the neural dynamics, possibly operating simultaneously within the same system. This may be necessary either to simulate large models with heterogeneous neural types, or to simplify simulation and analysis of detailed, complex models in a large simulation by isolating the new model to a small subpopulation of a larger overall network. The SpiNNaker neuromimetic chip is a dedicated neural processor able to support such heterogeneous simulations. Implementing these models on-chip uses an integrated library-based tool chain incorporating the emerging PyNN interface that allows a modeller to input a high-level description and use an automated process to generate an on-chip simulation. Simulations using both LIF and Izhikevich models demonstrate the ability of the SpiNNaker system to generate and simulate heterogeneous networks on-chip, while illustrating, through the network-scale effects of wavefront synchronisation and burst gating, methods that can provide effective behavioural abstractions for large-scale hardware modelling. SpiNNaker's asynchronous virtual architecture permits greater scope for model exploration, with scalable levels of functional and temporal abstraction, than conventional (or neuromorphic) computing platforms. The complete system illustrates a potential path to understanding the neural model of computation, by building (and breaking) neural models at various scales, connecting the blocks, then comparing them against the biology: computational cognitive neuroscience. Copyright © 2011 Elsevier Ltd. All rights reserved.

Study of silicone-based materials for the packaging of optoelectronic devices

NASA Astrophysics Data System (ADS)

Lin, Yeong-Her

The first part of this work is to evaluate the main materials used for the packaging of high power light-emitting diodes (LEDs), i.e., the die attach materials, the encapsulant materials, and high color rendering index(CRI) sol-gel composite materials. All of these materials had been discussed the performance, reliability, and issues in high power LED packages. High power white LEDs are created either from blue or near-ultraviolet chips encapsulated with a yellow phosphor, or from red-green-blue LED light mixing systems. The phosphor excited by blue LED chip was mostly used in experiment of this dissertation. The die attach materials contains filler particles possessing a maximum particle size less than 1.5 mum in diameter blended with epoxy polymer matrix. Such compositions enable thin bond line thickness, which decreases thermal resistance that exists between thermal interface materials and the corresponding mating surfaces. The thermal conductivity of nano silver die attach materials is relatively low, the thermal resistance from the junction to board is just 1.6 KW-1 in the bond line thickness of 5.3 mum, which is much lower than the thermal resistance using conventional die attach materials. The silicone die attach adhesive made in the lab cures through the free radical reaction of epoxy-functional organopolysiloxane and through the hydrosilylation reaction between alkenyl-functional organopolysiloxane and silicone-boned hydrogen-functional organopolysiloxane. By the combination of the free radical reaction and the hydrosilylation reaction, the low-molecular-weight silicone oil will not be out-migrated and not contaminate wire bondability to the LED chip and lead frame. Hence, the silicone die attach adhesive made in the lab can pass all reliability tests, such as operating life test JEDEC 85°C/85RH and room temperature operating life test. For LED encapsulating materials, most of commercial silicone encapsulants still suffer thermal/radiation induced degradations, and thus cause reliability issues and shorten the lifetime. A new high performance silicone has been developed and its performance has been compared with other commercial silicone products in the packaging of high power white LEDs. The high performance silicone also has better results than commercial high refractive index silicone and optical grade epoxy under JEDEC reliability standard for moisture sensitivity test. In synthesis of red dye-doped particles by sol-gel method, it is a novel method to get high color rendering index (CRI) LEDs. These red dye-doped particles, with average diameter of 5 mum, can be mixed with liquid encapsulants to form a uniform distribution in polymer matrix. The red dye-doped particles can be excited by phosphor-emitted yellow light instead of blue light from LED chip. Therefore, warm white LEDs with high CRI can be gotten at high lumen efficiency. The second part of this work is silicone elastomer for biomedical applications, especially in making urological implantable devices. A cross-linked, heat curable, addition-reaction silicone material is prepared. The material may be molded or formed into one or more medical devices. One such medical device could be a catheter used in urological applications. The material is a long term indwelling material that resists encrustation like a metal stent, but is more comfortable because it is silicone-based. The material can be made relatively cheaply compared to metal stents. Furthermore, the material is biocompatible with bladder epithelial cells.

Improved chip design for integrated solid-phase microextraction in on-line proteomic sample preparation.

PubMed

Bergkvist, Jonas; Ekström, Simon; Wallman, Lars; Löfgren, Mikael; Marko-Varga, György; Nilsson, Johan; Laurell, Thomas

2002-04-01

A recently introduced silicon microextraction chip (SMEC), used for on-line proteomic sample preparation, has proved to facilitate the process of protein identification by sample clean up and enrichment of peptides. It is demonstrated that a novel grid-SMEC design improves the operating characteristics for solid-phase microextraction, by reducing dispersion effects and thereby improving the sample preparation conditions. The structures investigated in this paper are treated both numerically and experimentally. The numerical approach is based on finite element analysis of the microfluidic flow in the microchip. The analysis is accomplished by use of the computational fluid dynamics-module FLOTRAN in the ANSYS software package. The modeling and analysis of the previously reported weir-SMEC design indicates some severe drawbacks, that can be reduced by changing the microextraction chip geometry to the grid-SMEC design. The overall analytical performance was thereby improved and also verified by experimental work. Matrix-assisted laser desorption/ionization mass spectra of model peptides extracted from both the weir-SMEC and the new grid-SMEC support the numerical analysis results. Further use of numerical modeling and analysis of the SMEC structures is also discussed and suggested in this work.

Efficient color mixing through étendue conservation using freeform optics

NASA Astrophysics Data System (ADS)

Sorgato, Simone; Mohedano, Rubén.; Chaves, Julio; Cvetkovic, Aleksandra; Hernández, Maikel; Benitez, Pablo; Miñano, Juan C.; Thienpont, Hugo; Duerr, Fabian

2015-08-01

Today's SSL illumination market shows a clear trend to high flux packages with higher efficiency and higher CRI, realized by means of multiple color chips and phosphors. Such light sources require the optics to provide both near- and far-field color mixing. This design problem is particularly challenging for collimated luminaries, since traditional diffusers cannot be employed without enlarging the exit aperture and reducing brightness. Furthermore, diffusers compromise the light output ratio (efficiency) of the lamps to which they are applied. A solution, based on Köhler integration, consisting of a spherical cap comprising spherical microlenses on both its interior and exterior sides was presented in 2012. The diameter of this so-called Shell-Mixer was 3 times that of the chip array footprint. A new version of the Shell-Mixer, based on the Edge Ray Principle and conservation of etendue, where neither the outer shape of the cap nor the surfaces of the lenses are constrained to spheres or 2D Cartesian ovals will be shown in this work. The new shell is freeform, only twice as large as the original chip-array and equals the original model in terms of color uniformity, brightness and efficiency.

A Conductometric Indium Oxide Semiconducting Nanoparticle Enzymatic Biosensor Array

PubMed Central

Lee, Dongjin; Ondrake, Janet; Cui, Tianhong

2011-01-01

We report a conductometric nanoparticle biosensor array to address the significant variation of electrical property in nanomaterial biosensors due to the random network nature of nanoparticle thin-film. Indium oxide and silica nanoparticles (SNP) are assembled selectively on the multi-site channel area of the resistors using layer-by-layer self-assembly. To demonstrate enzymatic biosensing capability, glucose oxidase is immobilized on the SNP layer for glucose detection. The packaged sensor chip onto a ceramic pin grid array is tested using syringe pump driven feed and multi-channel I–V measurement system. It is successfully demonstrated that glucose is detected in many different sensing sites within a chip, leading to concentration dependent currents. The sensitivity has been found to be dependent on the channel length of the resistor, 4–12 nA/mM for channel lengths of 5–20 μm, while the apparent Michaelis-Menten constant is 20 mM. By using sensor array, analytical data could be obtained with a single step of sample solution feeding. This work sheds light on the applicability of the developed nanoparticle microsensor array to multi-analyte sensors, novel bioassay platforms, and sensing components in a lab-on-a-chip. PMID:22163696

Nanofiber Anisotropic Conductive Films (ACF) for Ultra-Fine-Pitch Chip-on-Glass (COG) Interconnections

NASA Astrophysics Data System (ADS)

Lee, Sang-Hoon; Kim, Tae-Wan; Suk, Kyung-Lim; Paik, Kyung-Wook

2015-11-01

Nanofiber anisotropic conductive films (ACF) were invented, by adapting nanofiber technology to ACF materials, to overcome the limitations of ultra-fine-pitch interconnection packaging, i.e. shorts and open circuits as a result of the narrow space between bumps and electrodes. For nanofiber ACF, poly(vinylidene fluoride) (PVDF) and poly(butylene succinate) (PBS) polymers were used as nanofiber polymer materials. For PVDF and PBS nanofiber ACF, conductive particles of diameter 3.5 μm were incorporated into nanofibers by electrospinning. In ultra-fine-pitch chip-on-glass assembly, insulation was significantly improved by using nanofiber ACF, because nanofibers inside the ACF suppressed the mobility of conductive particles, preventing them from flowing out during the bonding process. Capture of conductive particles was increased from 31% (conventional ACF) to 65%, and stable electrical properties and reliability were achieved by use of nanofiber ACF.

Smart substrates: Making multi-chip modules smarter

NASA Astrophysics Data System (ADS)

Wunsch, T. F.; Treece, R. K.

1995-05-01

A novel multi-chip module (MCM) design and manufacturing methodology which utilizes active CMOS circuits in what is normally a passive substrate realizes the 'smart substrate' for use in highly testable, high reliability MCMS. The active devices are used to test the bare substrate, diagnose assembly errors or integrated circuit (IC) failures that require rework, and improve the testability of the final MCM assembly. A static random access memory (SRAM) MCM has been designed and fabricated in Sandia Microelectronics Development Laboratory in order to demonstrate the technical feasibility of this concept and to examine design and manufacturing issues which will ultimately determine the economic viability of this approach. The smart substrate memory MCM represents a first in MCM packaging. At the time the first modules were fabricated, no other company or MCM vendor had incorporated active devices in the substrate to improve manufacturability and testability, and thereby improve MCM reliability and reduce cost.

Monolithic short wave infrared (SWIR) detector array

NASA Technical Reports Server (NTRS)

1983-01-01

A monolithic self-scanned linear detector array was developed for remote sensing in the 1.1- 2.4-micron spectral region. A high-density IRCCD test chip was fabricated to verify new design approaches required for the detector array. The driving factors in the Schottky barrier IRCCD (Pdsub2Si) process development are the attainment of detector yield, uniformity, adequate quantum efficiency, and lowest possible dark current consistent with radiometric accuracy. A dual-band module was designed that consists of two linear detector arrays. The sensor architecture places the floating diffusion output structure in the middle of the chip, away from the butt edges. A focal plane package was conceptualized and includes a polycrystalline silicon substrate carrying a two-layer, thick-film interconnecting conductor pattern and five epoxy-mounted modules. A polycrystalline silicon cover encloses the modules and bond wires, and serves as a radiation and EMI shield, thermal conductor, and contamination seal.

Controlled thermal expansion printed wiring boards based on liquid crystal polymer dielectrics

NASA Technical Reports Server (NTRS)

Knoll, Thomas E.; Blizard, Kent; Jayaraj, K.; Rubin, Leslie S.

1994-01-01

Dielectric materials based on innovative Liquid Crystal Polymers (LCP's) have been used to fabricate surface mount printed wiring boards (PWB's) with a coefficient of thermal expansion matched to leadless ceramic chip carriers. Proprietary and patented polymer processing technology has resulted in self reinforcing material with balanced in-plane mechanical properties. In addition, LCP's possess excellent electrical properties, including a low dielectric constant (less than 2.9) and very low moisture absorption (less than 0.02%). LCP-based multilayer boards processed with conventional drilling and plating processes show improved performance over other materials because they eliminate the surface flatness problems of glass or aramid reinforcements. Laser drilling of blind vias in the LCP dielectric provides a very high density for use in direct chip attach and area array packages. The material is ideally suited for MCM-L and PCMCIA applications fabricated with very thin dielectric layers of the liquid crystal polymer.

Thermal Peak Management Using Organic Phase Change Materials for Latent Heat Storage in Electronic Applications

PubMed Central

Maxa, Jacob; Novikov, Andrej; Nowottnick, Mathias

2017-01-01

Modern high power electronics devices consists of a large amount of integrated circuits for switching and supply applications. Beside the benefits, the technology exhibits the problem of an ever increasing power density. Nowadays, heat sinks that are directly mounted on a device, are used to reduce the on-chip temperature and dissipate the thermal energy to the environment. This paper presents a concept of a composite coating for electronic components on printed circuit boards or electronic assemblies that is able to buffer a certain amount of thermal energy, dissipated from a device. The idea is to suppress temperature peaks in electronic components during load peaks or electronic shorts, which otherwise could damage or destroy the device, by using a phase change material to buffer the thermal energy. The phase change material coating could be directly applied on the chip package or the PCB using different mechanical retaining jigs.

Ultra-dense magnetoresistive mass memory

NASA Technical Reports Server (NTRS)

Daughton, J. M.; Sinclair, R.; Dupuis, T.; Brown, J.

1992-01-01

This report details the progress and accomplishments of Nonvolatile Electronics (NVE), Inc., on the design of the wafer scale MRAM mass memory system during the fifth quarter of the project. NVE has made significant progress this quarter on the one megabit design in several different areas. A test chip, which will verify a working GMR bit with the dimensions required by the 1 Meg chip, has been designed, laid out, and is currently being processed in the NVE labs. This test chip will allow electrical specifications, tolerances, and processing issues to be finalized before construction of the actual chip, thus providing a greater assurance of success of the final 1 Meg design. A model has been developed to accurately simulate the parasitic effects of unselected sense lines. This model gives NVE the ability to perform accurate simulations of the array electronic and test different design concepts. Much of the circuit design for the 1 Meg chip has been completed and simulated and these designs are included. Progress has been made in the wafer scale design area to verify the reliable operation of the 16 K macrocell. This is currently being accomplished with the design and construction of two stand alone test systems which will perform life tests and gather data on reliabiliy and wearout mechanisms for analysis.

Heterogeneous Integration for Reduced Phase Noise and Improved Reliability of Semiconductor Lasers

NASA Astrophysics Data System (ADS)

Srinivasan, Sudharsanan

Significant savings in cost, power and space are possible in existing optical data transmission networks, sensors and metrology equipment through photonic integration. Photonic integration can be broadly classified into two categories, hybrid and monolithic integration. The former involves assembling multiple single functionality optical devices together into a single package including any optical coupling and/or electronic connections. On the other hand monolithic integration assembles many devices or optical functionalities on a single chip so that all the optical connections are on chip and require no external alignment. This provides a substantial improvement in reliability and simplifies testing. Monolithic integration has been demonstrated on both indium phosphide (InP) and silicon (Si) substrates. Integration on larger 300mm Si substrates can further bring down the cost and has been a major area of research in recent years. Furthermore, with increasing interest from industry, the hybrid silicon platform is emerging as a new technology for integrating various active and passive optical elements on a single chip. This is both in the interest of bringing down manufacturing cost through scaling along with continued improvement in performance and to produce multi-functional photonic integrated circuits (PIC). The goal of this work is twofold. First, we show four laser demonstrations that use the hybrid silicon platform to lower phase noise due to spontaneous emission, based on the following two techniques, viz. confinement factor reduction and negative optical feedback. The first two demonstrations are of mode-locked lasers and the next two are of tunable lasers. Some of the key results include; (a) 14dB white frequency noise reduction of a 20GHz radio-frequency (RF) signal from a harmonically mode-locked long cavity laser with greater than 55dB supermode noise suppression, (b) 8dB white frequency noise reduction from a colliding pulse mode-locked laser by reducing the number of quantum wells and a further 6dB noise reduction using coherent photon seeding from long on-chip coupled cavity, (c) linewidth reduction of a tunable laser down to 160kHz using negative optical feedback from coupled ring resonator mirrors, and (d) linewidth reduction of a widely tunable laser down to 50kHz using on-chip coupled cavity feedback effect. Second, we present the results of a reliability study conducted to investigate the influence of molecular wafer bonding between Si and InP on the lifetime of distributed feedback lasers, a common laser source used in optical communication. No degradation in lasing threshold or slope efficiency was observed after aging the lasers for 5000hrs at 70°C and 2500hrs at 85°C. However, among the three chosen bonding interface layer options, the devices with an interface superlattice layer showed a higher yield for lasers and lower dark current values in the on-chip monitor photodiodes after aging.

Materials and processing science: Limits for microelectronics

NASA Astrophysics Data System (ADS)

Rosenberg, R.

1988-09-01

The theme of this talk will be to illustrate examples of technologies that will drive materials and processing sciences to the limit and to describe some of the research being pursued to understand materials interactions which are pervasive to projected structure fabrication. It is to be expected that the future will see a progression to nanostructures where scaling laws will be tested and quantum transport will become more in evidence, to low temperature operation for tighter control and improved performance, to complex vertical profiles where 3D stacking and superlattices will produce denser packing and device flexibility, to faster communication links with optoelectronics, and to compatible packaging technologies. New low temperature processing techniques, such as epitaxy of silicon, PECVD of dielectrics, low temperature high pressure oxidation, silicon-germanium heterostructures, etc., must be combined with shallow metallurgies, new lithographic technologies, maskless patterning, rapid thermal processing (RTP) to produce needed profile control, reduce process incompatibilities and develop new device geometries. Materials interactions are of special consequence for chip substrates and illustrations of work in metal-ceramic and metal-polymer adhesion will be offered.

Rapid prototyping of 2D glass microfluidic devices based on femtosecond laser assisted selective etching process

NASA Astrophysics Data System (ADS)

Kim, Sung-Il; Kim, Jeongtae; Koo, Chiwan; Joung, Yeun-Ho; Choi, Jiyeon

2018-02-01

Microfluidics technology which deals with small liquid samples and reagents within micro-scale channels has been widely applied in various aspects of biological, chemical, and life-scientific research. For fabricating microfluidic devices, a silicon-based polymer, PDMS (Polydimethylsiloxane), is widely used in soft lithography, but it has several drawbacks for microfluidic applications. Glass has many advantages over PDMS due to its excellent optical, chemical, and mechanical properties. However, difficulties in fabrication of glass microfluidic devices that requires multiple skilled steps such as MEMS technology taking several hours to days, impedes broad application of glass based devices. Here, we demonstrate a rapid and optical prototyping of a glass microfluidic device by using femtosecond laser assisted selective etching (LASE) and femtosecond laser welding. A microfluidic droplet generator was fabricated as a demonstration of a microfluidic device using our proposed prototyping. The fabrication time of a single glass chip containing few centimeter long and complex-shaped microfluidic channels was drastically reduced in an hour with the proposed laser based rapid and simple glass micromachining and hermetic packaging technique.

Analysis of ChIP-seq Data in R/Bioconductor.

PubMed

de Santiago, Ines; Carroll, Thomas

2018-01-01

The development of novel high-throughput sequencing methods for ChIP (chromatin immunoprecipitation) has provided a very powerful tool to study gene regulation in multiple conditions at unprecedented resolution and scale. Proactive quality-control and appropriate data analysis techniques are of critical importance to extract the most meaningful results from the data. Over the last years, an array of R/Bioconductor tools has been developed allowing researchers to process and analyze ChIP-seq data. This chapter provides an overview of the methods available to analyze ChIP-seq data based primarily on software packages from the open-source Bioconductor project. Protocols described in this chapter cover basic steps including data alignment, peak calling, quality control and data visualization, as well as more complex methods such as the identification of differentially bound regions and functional analyses to annotate regulatory regions. The steps in the data analysis process were demonstrated on publicly available data sets and will serve as a demonstration of the computational procedures routinely used for the analysis of ChIP-seq data in R/Bioconductor, from which readers can construct their own analysis pipelines.

Technology-design-manufacturing co-optimization for advanced mobile SoCs

NASA Astrophysics Data System (ADS)

Yang, Da; Gan, Chock; Chidambaram, P. R.; Nallapadi, Giri; Zhu, John; Song, S. C.; Xu, Jeff; Yeap, Geoffrey

2014-03-01

How to maintain the Moore's Law scaling beyond the 193 immersion resolution limit is the key question semiconductor industry needs to answer in the near future. Process complexity will undoubtfully increase for 14nm node and beyond, which brings both challenges and opportunities for technology development. A vertically integrated design-technologymanufacturing co-optimization flow is desired to better address the complicated issues new process changes bring. In recent years smart mobile wireless devices have been the fastest growing consumer electronics market. Advanced mobile devices such as smartphones are complex systems with the overriding objective of providing the best userexperience value by harnessing all the technology innovations. Most critical system drivers are better system performance/power efficiency, cost effectiveness, and smaller form factors, which, in turns, drive the need of system design and solution with More-than-Moore innovations. Mobile system-on-chips (SoCs) has become the leading driver for semiconductor technology definition and manufacturing. Here we highlight how the co-optimization strategy influenced architecture, device/circuit, process technology and package, in the face of growing process cost/complexity and variability as well as design rule restrictions.

Packaging of ferroelectric liquid crystal-on-silicon spatial light modulators

NASA Astrophysics Data System (ADS)

Lin, W.; Morozova, Nina D.; Ju, TehHua; Zhang, Weidong; Lee, Yung-Cheng; McKnight, Douglas J.; Johnson, Kristina M.

1996-11-01

A self-pulling soldering technology has been demonstrated for assembling liquid crystal on silicon (LCOS) spatial light modulators (SLMs). One of the major challenges in manufacturing the LCOS modules is to reproducibly control the thickness of the gap between the very large scale integrated circuit (VLSI) chip and the cover glass. The liquid crystal material is sandwiched between the VLSI chop and the cover glass which is coated with a transparent conductor. Solder joints with different profiles and sizes have been designed to provide surface tension forces to control the gap accommodating the ferroelectric liquid crystal layer in the range of a micron level with sub- micron uniformity. The optimum solder joint design is defined as a joint that results in the maximum pulling force. This technology provides an automatic, batch assembly process for a LCOS SLM through one reflow process. Fluxless soldering technology is used to assemble the module. This approach avoids residues from chemical of flux and oxides, and eliminates potential contamination to the device. Two different LCOS SLM designs and the process optimization are described.

3D printed high density, reversible, chip-to-chip microfluidic interconnects.

PubMed

Gong, Hua; Woolley, Adam T; Nordin, Gregory P

2018-02-13

Our latest developments in miniaturizing 3D printed microfluidics [Gong et al., Lab Chip, 2016, 16, 2450; Gong et al., Lab Chip, 2017, 17, 2899] offer the opportunity to fabricate highly integrated chips that measure only a few mm on a side. For such small chips, an interconnection method is needed to provide the necessary world-to-chip reagent and pneumatic connections. In this paper, we introduce simple integrated microgaskets (SIMs) and controlled-compression integrated microgaskets (CCIMs) to connect a small device chip to a larger interface chip that implements world-to-chip connections. SIMs or CCIMs are directly 3D printed as part of the device chip, and therefore no additional materials or components are required to make the connection to the larger 3D printed interface chip. We demonstrate 121 chip-to-chip interconnections in an 11 × 11 array for both SIMs and CCIMs with an areal density of 53 interconnections per mm 2 and show that they withstand fluid pressures of 50 psi. We further demonstrate their reusability by testing the devices 100 times without seal failure. Scaling experiments show that 20 × 20 interconnection arrays are feasible and that the CCIM areal density can be increased to 88 interconnections per mm 2 . We then show the utility of spatially distributed discrete CCIMs by using an interconnection chip with 28 chip-to-world interconnects to test 45 3D printed valves in a 9 × 5 array. Each valve is only 300 μm in diameter (the smallest yet reported for 3D printed valves). Every row of 5 valves is tested to at least 10 000 actuations, with one row tested to 1 000 000 actuations. In all cases, there is no sign of valve failure, and the CCIM interconnections prove an effective means of using a single interface chip to test a series of valve array chips.

An economic evaluation of a chlorhexidine chip for treating chronic periodontitis: the CHIP (chlorhexidine in periodontitis) study.

PubMed

Henke, C J; Villa, K F; Aichelmann-Reidy, M E; Armitage, G C; Eber, R M; Genco, R J; Killoy, W J; Miller, D P; Page, R C; Polson, A M; Ryder, M I; Silva, S J; Somerman, M J; Van Dyke, T E; Wolff, L F; Evans, C J; Finkelman, R D

2001-11-01

The authors previously suggested that an adjunctive, controlled-release chlorhexidine, or CHX, chip may reduce periodontal surgical needs at little additional cost. This article presents an economic analysis of the CHX chip in general dental practice. In a one-year prospective clinical trial, 484 chronic periodontitis patients in 52 general practices across the United States were treated with either scaling and root planing, or SRP, plus any therapy prescribed by treating, unblinded dentists; or SRP plus other therapy as above but including the CHX chip. Economic data were collected from bills, case report forms and 12-month treatment recommendations from blinded periodontist evaluators. Total dental charges were higher for SRP + CHX chip patients vs. SRP patients when CHX chip costs were included (P = .027) but lower when CHX chip costs were excluded (P = .012). About one-half of the CHX chip acquisition cost was offset by savings in other charges. SRP + CHX chip patients were about 50 percent less likely to undergo surgical procedures than were SRP patients (P = .021). At the end of the trial, periodontist evaluators recommended similar additional procedures for both groups: SRP, about 46 percent; maintenance, about 37 percent; surgery, 56 percent for SRP alone and 63 percent for SRP + CHX chip. Adjunctive CHX chip use for general-practice patients with periodontitis increased costs but reduced surgeries over one year. At study's end, periodontists recommended similar additional surgical treatment for both groups. In general practice, routine use of the CHX chip suggests that costs will be partially offset by reduced surgery over at least one year.

Incorporating biopulping technology into wood yard operations

Treesearch

Gary M. Scott; Eric Horn; Masood Akhtar; Ross E. Swaney; Michael J. Lentz; David F. Shipley

1998-01-01

Biopulping is the treatment of wood chips and other lignocellulosic materials with lignin-degrading fungi prior to pulping. Ten years of industry-sponsored research has demonstrated the technical feasibility of the technology for mechanical pulping at a laboratory scale. Two 50-ton outdoor chip pile trials recently conducted at the USDA Forest Service, Forest Products...

Advanced chip designs and novel cooling techniques for brightness scaling of industrial, high power diode laser bars

NASA Astrophysics Data System (ADS)

Heinemann, S.; McDougall, S. D.; Ryu, G.; Zhao, L.; Liu, X.; Holy, C.; Jiang, C.-L.; Modak, P.; Xiong, Y.; Vethake, T.; Strohmaier, S. G.; Schmidt, B.; Zimer, H.

2018-02-01

The advance of high power semiconductor diode laser technology is driven by the rapidly growing industrial laser market, with such high power solid state laser systems requiring ever more reliable diode sources with higher brightness and efficiency at lower cost. In this paper we report simulation and experimental data demonstrating most recent progress in high brightness semiconductor laser bars for industrial applications. The advancements are in three principle areas: vertical laser chip epitaxy design, lateral laser chip current injection control, and chip cooling technology. With such improvements, we demonstrate disk laser pump laser bars with output power over 250W with 60% efficiency at the operating current. Ion implantation was investigated for improved current confinement. Initial lifetime tests show excellent reliability. For direct diode applications <1 um smile and >96% polarization are additional requirements. Double sided cooling deploying hard solder and optimized laser design enable single emitter performance also for high fill factor bars and allow further power scaling to more than 350W with 65% peak efficiency with less than 8 degrees slow axis divergence and high polarization.

On-chip dual-comb source for spectroscopy.

PubMed

Dutt, Avik; Joshi, Chaitanya; Ji, Xingchen; Cardenas, Jaime; Okawachi, Yoshitomo; Luke, Kevin; Gaeta, Alexander L; Lipson, Michal

2018-03-01

Dual-comb spectroscopy is a powerful technique for real-time, broadband optical sampling of molecular spectra, which requires no moving components. Recent developments with microresonator-based platforms have enabled frequency combs at the chip scale. However, the need to precisely match the resonance wavelengths of distinct high quality-factor microcavities has hindered the development of on-chip dual combs. We report the simultaneous generation of two microresonator combs on the same chip from a single laser, drastically reducing experimental complexity. We demonstrate broadband optical spectra spanning 51 THz and low-noise operation of both combs by deterministically tuning into soliton mode-locked states using integrated microheaters, resulting in narrow (<10 kHz) microwave beat notes. We further use one comb as a reference to probe the formation dynamics of the other comb, thus introducing a technique to investigate comb evolution without auxiliary lasers or microwave oscillators. We demonstrate high signal-to-noise ratio absorption spectroscopy spanning 170 nm using the dual-comb source over a 20-μs acquisition time. Our device paves the way for compact and robust spectrometers at nanosecond time scales enabled by large beat-note spacings (>1 GHz).

Multi-scale Modeling and Analysis of Nano-RFID Systems on HPC Setup

NASA Astrophysics Data System (ADS)

Pathak, Rohit; Joshi, Satyadhar

In this paper we have worked out on some the complex modeling aspects such as Multi Scale modeling, MATLAB Sugar based modeling and have shown the complexities involved in the analysis of Nano RFID (Radio Frequency Identification) systems. We have shown the modeling and simulation and demonstrated some novel ideas and library development for Nano RFID. Multi scale modeling plays a very important role in nanotech enabled devices properties of which cannot be explained sometimes by abstraction level theories. Reliability and packaging still remains one the major hindrances in practical implementation of Nano RFID based devices. And to work on them modeling and simulation will play a very important role. CNTs is the future low power material that will replace CMOS and its integration with CMOS, MEMS circuitry will play an important role in realizing the true power in Nano RFID systems. RFID based on innovations in nanotechnology has been shown. MEMS modeling of Antenna, sensors and its integration in the circuitry has been shown. Thus incorporating this we can design a Nano-RFID which can be used in areas like human implantation and complex banking applications. We have proposed modeling of RFID using the concept of multi scale modeling to accurately predict its properties. Also we give the modeling of MEMS devices that are proposed recently that can see possible application in RFID. We have also covered the applications and the advantages of Nano RFID in various areas. RF MEMS has been matured and its devices are being successfully commercialized but taking it to limits of nano domains and integration with singly chip RFID needs a novel approach which is being proposed. We have modeled MEMS based transponder and shown the distribution for multi scale modeling for Nano RFID.

Chip-scale fluorescence microscope based on a silo-filter complementary metal-oxide semiconductor image sensor.

PubMed

Ah Lee, Seung; Ou, Xiaoze; Lee, J Eugene; Yang, Changhuei

2013-06-01

We demonstrate a silo-filter (SF) complementary metal-oxide semiconductor (CMOS) image sensor for a chip-scale fluorescence microscope. The extruded pixel design with metal walls between neighboring pixels guides fluorescence emission through the thick absorptive filter to the photodiode of a pixel. Our prototype device achieves 13 μm resolution over a wide field of view (4.8 mm × 4.4 mm). We demonstrate bright-field and fluorescence longitudinal imaging of living cells in a compact, low-cost configuration.

Optimization of a PCRAM Chip for high-speed read and highly reliable reset operations

NASA Astrophysics Data System (ADS)

Li, Xiaoyun; Chen, Houpeng; Li, Xi; Wang, Qian; Fan, Xi; Hu, Jiajun; Lei, Yu; Zhang, Qi; Tian, Zhen; Song, Zhitang

2016-10-01

The widely used traditional Flash memory suffers from its performance limits such as its serious crosstalk problems, and increasing complexity of floating gate scaling. Phase change random access memory (PCRAM) becomes one of the most potential nonvolatile memories among the new memory techniques. In this paper, a 1M-bit PCRAM chip is designed based on the SMIC 40nm CMOS technology. Focusing on the read and write performance, two new circuits with high-speed read operation and highly reliable reset operation are proposed. The high-speed read circuit effectively reduces the reading time from 74ns to 40ns. The double-mode reset circuit improves the chip yield. This 1M-bit PCRAM chip has been simulated on cadence. After layout design is completed, the chip will be taped out for post-test.

Wafer Scale Integration of CMOS Chips for Biomedical Applications via Self-Aligned Masking.

PubMed

Uddin, Ashfaque; Milaninia, Kaveh; Chen, Chin-Hsuan; Theogarajan, Luke

2011-12-01

This paper presents a novel technique for the integration of small CMOS chips into a large area substrate. A key component of the technique is the CMOS chip based self-aligned masking. This allows for the fabrication of sockets in wafers that are at most 5 µm larger than the chip on each side. The chip and the large area substrate are bonded onto a carrier such that the top surfaces of the two components are flush. The unique features of this technique enable the integration of macroscale components, such as leads and microfluidics. Furthermore, the integration process allows for MEMS micromachining after CMOS die-wafer integration. To demonstrate the capabilities of the proposed technology, a low-power integrated potentiostat chip for biosensing implemented in the AMI 0.5 µm CMOS technology is integrated in a silicon substrate. The horizontal gap and the vertical displacement between the chip and the large area substrate measured after the integration were 4 µm and 0.5 µm, respectively. A number of 104 interconnects are patterned with high-precision alignment. Electrical measurements have shown that the functionality of the chip is not affected by the integration process.

Research on Optical Transmitter and Receiver Module Used for High-Speed Interconnection between CPU and Memory

NASA Astrophysics Data System (ADS)

He, Huimin; Liu, Fengman; Li, Baoxia; Xue, Haiyun; Wang, Haidong; Qiu, Delong; Zhou, Yunyan; Cao, Liqiang

2016-11-01

With the development of the multicore processor, the bandwidth and capacity of the memory, rather than the memory area, are the key factors in server performance. At present, however, the new architectures, such as fully buffered DIMM (FBDIMM), hybrid memory cube (HMC), and high bandwidth memory (HBM), cannot be commercially applied in the server. Therefore, a new architecture for the server is proposed. CPU and memory are separated onto different boards, and optical interconnection is used for the communication between them. Each optical module corresponds to each dual inline memory module (DIMM) with 64 channels. Compared to the previous technology, not only can the architecture realize high-capacity and wide-bandwidth memory, it also can reduce power consumption and cost, and be compatible with the existing dynamic random access memory (DRAM). In this article, the proposed module with system-in-package (SiP) integration is demonstrated. In the optical module, the silicon photonic chip is included, which is a promising technology to be applied in the next-generation data exchanging centers. And due to the bandwidth-distance performance of the optical interconnection, SerDes chips are introduced to convert the 64-bit data at 800 Mbps from/to 4-channel data at 12.8 Gbps after/before they are transmitted though optical fiber. All the devices are packaged on cheap organic substrates. To ensure the performance of the whole system, several optimization efforts have been performed on the two modules. High-speed interconnection traces have been designed and simulated with electromagnetic simulation software. Steady-state thermal characteristics of the transceiver module have been evaluated by ANSYS APLD based on finite-element methodology (FEM). Heat sinks are placed at the hotspot area to ensure the reliability of all working chips. Finally, this transceiver system based on silicon photonics is measured, and the eye diagrams of data and clock signals are verified.

An analog silicon retina with multichip configuration.

PubMed

Kameda, Seiji; Yagi, Tetsuya

2006-01-01

The neuromorphic silicon retina is a novel analog very large scale integrated circuit that emulates the structure and the function of the retinal neuronal circuit. We fabricated a neuromorphic silicon retina, in which sample/hold circuits were embedded to generate fluctuation-suppressed outputs in the previous study [1]. The applications of this silicon retina, however, are limited because of a low spatial resolution and computational variability. In this paper, we have fabricated a multichip silicon retina in which the functional network circuits are divided into two chips: the photoreceptor network chip (P chip) and the horizontal cell network chip (H chip). The output images of the P chip are transferred to the H chip with analog voltages through the line-parallel transfer bus. The sample/hold circuits embedded in the P and H chips compensate for the pattern noise generated on the circuits, including the analog communication pathway. Using the multichip silicon retina together with an off-chip differential amplifier, spatial filtering of the image with an odd- and an even-symmetric orientation selective receptive fields was carried out in real time. The analog data transfer method in the present multichip silicon retina is useful to design analog neuromorphic multichip systems that mimic the hierarchical structure of neuronal networks in the visual system.

Low-cost compact thermal imaging sensors for body temperature measurement

NASA Astrophysics Data System (ADS)

Han, Myung-Soo; Han, Seok Man; Kim, Hyo Jin; Shin, Jae Chul; Ahn, Mi Sook; Kim, Hyung Won; Han, Yong Hee

2013-06-01

This paper presents a 32x32 microbolometer thermal imaging sensor for human body temperature measurement. Waferlevel vacuum packaging technology allows us to get a low cost and compact imaging sensor chip. The microbolometer uses V-W-O film as sensing material and ROIC has been designed 0.35-um CMOS process in UMC. A thermal image of a human face and a hand using f/1 lens convinces that it has a potential of human body temperature for commercial use.

Manufacturing Methods and Technology Engineering (MM&TE) Program for the Establishment of Production Techniques for High Density Thick Film Circuits Used in Crystal Oscillators. Volume I.

DTIC Science & Technology

1980-04-01

incorporate the high reliability ceramic-packaged quartz crystal resonator developed at ERADCOM, and utilize beam -leaded devices wherever possible...the form of a truncated cylinder. The rather complex module outline is best accomplished through the use of a precast potting shell filled with a low...crossover connections are achieved by means of thick-film dielectric material. Chip components attached to the metallized substrate complete the circuits

Electrostatically Actuated Resonant Microcantilever Beam in CMOS Technology for the Detection of Chemical Weapons

DTIC Science & Technology

2005-01-01

sorption . In this regard, the length ( ) and 1530-437X/$20.00 © 2005 IEEE Report Documentation Page Form ApprovedOMB No. 0704-0188 Public reporting...temperature. The beam’s resonant frequency shift re- sponse resulting from analyte sorption increases with increasing thickness of the polymer layer. At...pneumatic tubing used for all gas wetted parts was PFA . The chip mounted in the Kyocera package was sealed by positioning a Combo Lid (Chelsea Technology

Investigation of discrete component chip mounting technology for hybrid microelectronic circuits

NASA Technical Reports Server (NTRS)

Caruso, S. V.; Honeycutt, J. O.

1975-01-01

The use of polymer adhesives for high reliability microcircuit applications is a radical deviation from past practices in electronic packaging. Bonding studies were performed using two gold-filled conductive adhesives, 10/90 tin/lead solder and Indalloy no. 7 solder. Various types of discrete components were mounted on ceramic substrates using both thick-film and thin-film metallization. Electrical and mechanical testing were performed on the samples before and after environmental exposure to MIL-STD-883 screening tests.

Microelectromechanical Systems (MEMS) Broadband Light Source Developed

NASA Technical Reports Server (NTRS)

Tuma, Margaret L.

2003-01-01

A miniature, low-power broadband light source has been developed for aerospace applications, including calibrating spectrometers and powering miniature optical sensors. The initial motivation for this research was based on flight tests of a Fabry-Perot fiberoptic temperature sensor system used to detect aircraft engine exhaust gas temperature. Although the feasibility of the sensor system was proven, the commercial light source optically powering the device was identified as a critical component requiring improvement. Problems with the light source included a long stabilization time (approximately 1 hr), a large amount of heat generation, and a large input electrical power (6.5 W). Thus, we developed a new light source to enable the use of broadband optical sensors in aerospace applications. Semiconductor chip-based light sources, such as lasers and light-emitting diodes, have a relatively narrow range of emission wavelengths in comparison to incandescent sources. Incandescent light sources emit broadband radiation from visible to infrared wavelengths; the intensity at each wavelength is determined by the filament temperature and the materials chosen for the filament and the lamp window. However, present commercial incandescent light sources are large in size and inefficient, requiring several watts of electrical power to obtain the desired optical power, and they emit a large percentage of the input power as heat that must be dissipated. The miniature light source, developed jointly by the NASA Glenn Research Center, the Jet Propulsion Laboratory, and the Lighting Innovations Institute, requires one-fifth the electrical input power of some commercial light sources, while providing similar output light power that is easily coupled to an optical fiber. Furthermore, it is small, rugged, and lightweight. Microfabrication technology was used to reduce the size, weight, power consumption, and potential cost-parameters critical to future aerospace applications. This chip-based light source has the potential for monolithic fabrication with on-chip drive electronics. Other uses for these light sources are in systems for vehicle navigation, remote sensing applications such as monitoring bridges for stress, calibration sources for spectrometers, light sources for space sensors, display lighting, addressable arrays, and industrial plant monitoring. Two methods for filament fabrication are being developed: wet-chemical etching and laser ablation. Both yield a 25-mm-thick tungsten spiral filament. The proof-of-concept filament shown was fabricated with the wet etch method. Then it was tested by heating it in a vacuum chamber using about 1.25 W of electrical power; it generated bright, blackbody radiation at approximately 2650 K. The filament was packaged in Glenn's clean-room facilities. This design uses three chips vacuum-sealed with glass tape. The bottom chip consists of a reflective film deposited on silicon, the middle chip contains a tungsten filament bonded to silicon, and the top layer is a transparent window. Lifetime testing on the package will begin shortly. The emitted optical power is expected to be approximately 1.0 W with the spectral peak at 1.1 mm.

An Overview of Wide Bandgap Silicon Carbide Sensors and Electronics Development at NASA Glenn Research Center

NASA Technical Reports Server (NTRS)

Hunter, Gary W.; Neudeck, Philip G.; Beheim, Glenn M.; Okojie, Robert S.; Chen, Liangyu; Spry, D.; Trunek, A.

2007-01-01

A brief overview is presented of the sensors and electronics development work ongoing at NASA Glenn Research Center which is intended to meet the needs of future aerospace applications. Three major technology areas are discussed: 1) high temperature SiC electronics, 2) SiC gas sensor technology development, and 3) packaging of harsh environment devices. Highlights of this work include world-record operation of SiC electronic devices including 500?C JFET transistor operation with excellent properties, atomically flat SiC gas sensors integrated with an on-chip temperature detector/heater, and operation of a packaged AC amplifier. A description of the state-of-the-art is given for each topic. It is concluded that significant progress has been made and that given recent advancements the development of high temperature smart sensors is envisioned.

The Use of Metal Filled Via Holes for Improving Isolation in LTCC RF and Wireless Multichip Packages

NASA Technical Reports Server (NTRS)

Ponchak, George E.; Chun, Donghoon; Yook, Jong-Gwan; Katehi, Linda P. B.

1999-01-01

LTCC MCMs (Low Temperature Cofired Ceramic MultiChip Module) for RF and wireless systems often use metal filled via holes to improve isolation between the stripline and microstrip interconnects. In this paper, results from a 3D-FEM electromagnetic characterization of microstrip and stripline interconnects with metal filled via fences for isolation are presented. It is shown that placement of a via hole fence closer than three times the substrate height to the transmission lines increases radiation and coupling. Radiation loss and reflections are increased when a short via fence is used in areas suspected of having high radiation. Also, via posts should not be separated by more than three times the substrate height for low radiation loss, coupling, and suppression of higher order modes in a package.

A microfluidic thermometer: Precise temperature measurements in microliter- and nanoliter-scale volumes

PubMed Central

McKenzie, Brittney A.

2017-01-01

Measuring the temperature of a sample is a fundamental need in many biological and chemical processes. When the volume of the sample is on the microliter or nanoliter scale (e.g., cells, microorganisms, precious samples, or samples in microfluidic devices), accurate measurement of the sample temperature becomes challenging. In this work, we demonstrate a technique for accurately determining the temperature of microliter volumes using a simple 3D-printed microfluidic chip. We accomplish this by first filling “microfluidic thermometer” channels on the chip with substances with precisely known freezing/melting points. We then use a thermoelectric cooler to create a stable and linear temperature gradient along these channels within a measurement region on the chip. A custom software tool (available as online Supporting Information) is then used to find the locations of solid-liquid interfaces in the thermometer channels; these locations have known temperatures equal to the freezing/melting points of the substances in the channels. The software then uses the locations of these interfaces to calculate the temperature at any desired point within the measurement region. Using this approach, the temperature of any microliter-scale on-chip sample can be measured with an uncertainty of about a quarter of a degree Celsius. As a proof-of-concept, we use this technique to measure the unknown freezing point of a 50 microliter volume of solution and demonstrate its feasibility on a 400 nanoliter sample. Additionally, this technique can be used to measure the temperature of any on-chip sample, not just near-zero-Celsius freezing points. We demonstrate this by using an oil that solidifies near room temperature (coconut oil) in a microfluidic thermometer to measure on-chip temperatures well above zero Celsius. By providing a low-cost and simple way to accurately measure temperatures in small volumes, this technique should find applications in both research and educational laboratories. PMID:29284028

Thick resist for MEMS processing

NASA Astrophysics Data System (ADS)

Brown, Joe; Hamel, Clifford

2001-11-01

The need for technical innovation is always present in today's economy. Microfabrication methods have evolved in support of the demand for smaller and faster integrated circuits with price performance improvements always in the scope of the manufacturing design engineer. The dispersion of processing technology spans well beyond IC fabrication today with batch fabrication and wafer scale processing lending advantages to MEMES applications from biotechnology to consumer electronics from oil exploration to aerospace. Today the demand for innovative processing techniques that enable technology is apparent where only a few years ago appeared too costly or not reliable. In high volume applications where yield and cost improvements are measured in fractions of a percent it is imperative to have process technologies that produce consistent results. Only a few years ago thick resist coatings were limited to thickness less than 20 microns. Factors such as uniformity, edge bead and multiple coatings made high volume production impossible. New developments in photoresist formulation combined with advanced coating equipment techniques that closely controls process parameters have enable thick photoresist coatings of 70 microns with acceptable uniformity and edge bead in one pass. Packaging of microelectronic and micromechanical devices is often a significant cost factor and a reliability issue for high volume low cost production. Technologies such as flip- chip assembly provide a solution for cost and reliability improvements over wire bond techniques. The processing for such technology demands dimensional control and presents a significant cost savings if it were compatible with mainstream technologies. Thick photoresist layers, with good sidewall control would allow wafer-bumping technologies to penetrate the barriers to yield and production where costs for technology are the overriding issue. Single pass processing is paramount to the manufacturability of packaging technology. Uniformity and edge bead control defined the success of process implementation. Today advanced packaging solutions are created with thick photoresist coatings. The techniques and results will be presented.

Fabrication and characterization of microfabricated on-chip microelectrochemical cell for biosensing applications

NASA Astrophysics Data System (ADS)

Said, N. A. Mohd; Twomey, K.; Herzog, G.; Ogurtsov, V. I.

2017-03-01

The fabrication of on-chip microelectrochemical cell on Si wafer by means of photolithography is described here. The single on-chip microelectrochemical cell device has dimensions of 100 × 380 mm with integrated Pt counter electrode (CE), Ag/AgCl reference electrode (RE) and gold microelectrode array of 500 nm recess depth as the working electrode (WE). Two geometries of electrode array were implemented, band and disc, with fixed diameter/width of 10 µm; and varied centre-to-centre spacing (d) and number of electrodes (N) in the array. The on-chip microelectrochemical cell structure has been designed to facilitate further WE biomodifications. Firstly, the developed microelectrochemical cell does not require packaging hence reducing the production cost and time. Secondly, the working electrode (WE) on the microelectrochemical cell is positioned towards the end of the chip enabling modification of the working electrode surface to be carried out for surface bio-functionalisation without affecting both the RE and CE surface conditions. The developed on-chip microelectrochemical cell was examined with scanning electron microscopy (SEM) and characterised by two electrochemical techniques. Both cyclic voltammetry (CV) and electrochemical impedance spectroscopy (EIS) were performed in 1 mM ferrocenecarboxylic acid (FCA) in 0.01 M phosphate buffered saline (PBS) solution at pH7.4. Electrochemical experiments showed that in the case of halving the interspacing distance of the microdisc WE array (50 nm instead of 100 nm), the voltammogram shifted from a steady-state CV (feature of hemispherical diffusion) to an inclined peak-shaped CV (feature of linear diffusion) albeit the arrays had the same surface area. In terms of EIS it was also found that linear diffusion dominates the surface instead of hemispherical diffusion once the interspacing distance was reduced, supporting the fact that closely packed arrays may behave like a macroelectrode

GeoChip 3.0: A High Throughput Tool for Analyzing Microbial Community, Composition, Structure, and Functional Activity

DOE Office of Scientific and Technical Information (OSTI.GOV)

He, Zhili; Deng, Ye; Nostrand, Joy Van

2010-05-17

Microarray-based genomic technology has been widely used for microbial community analysis, and it is expected that microarray-based genomic technologies will revolutionize the analysis of microbial community structure, function and dynamics. A new generation of functional gene arrays (GeoChip 3.0) has been developed, with 27,812 probes covering 56,990 gene variants from 292 functional gene families involved in carbon, nitrogen, phosphorus and sulfur cycles, energy metabolism, antibiotic resistance, metal resistance, and organic contaminant degradation. Those probes were derived from 2,744, 140, and 262 species for bacteria, archaea, and fungi, respectively. GeoChip 3.0 has several other distinct features, such as a common oligomore » reference standard (CORS) for data normalization and comparison, a software package for data management and future updating, and the gyrB gene for phylogenetic analysis. Our computational evaluation of probe specificity indicated that all designed probes had a high specificity to their corresponding targets. Also, experimental analysis with synthesized oligonucleotides and genomic DNAs showed that only 0.0036percent-0.025percent false positive rates were observed, suggesting that the designed probes are highly specific under the experimental conditions examined. In addition, GeoChip 3.0 was applied to analyze soil microbial communities in a multifactor grassland ecosystem in Minnesota, USA, which demonstrated that the structure, composition, and potential activity of soil microbial communities significantly changed with the plant species diversity. All results indicate that GeoChip 3.0 is a high throughput powerful tool for studying microbial community functional structure, and linking microbial communities to ecosystem processes and functioning. To our knowledge, GeoChip 3.0 is the most comprehensive microarrays currently available for studying microbial communities associated with geobiochemical cycling, global climate change, bioenergy, agricuture, land use, ecosystem management, environmental cleanup and restoration, bioreactor systems, and human health.« less

Using the developed cross-flow filtration chip for collecting blood plasma under high flow rate condition and applying the immunoglobulin E detection

NASA Astrophysics Data System (ADS)

Yeh, Chia-Hsien; Hung, Chia-Wei; Wu, Chun-Han; Lin, Yu-Cheng

2014-09-01

This paper presents a cross-flow filtration chip for separating blood cells (white blood cells, red blood cells, and platelets) and obtaining blood plasma from human blood. Our strategy is to flow the sample solution in parallel to the membrane, which can generate a parallel shear stress to remove the clogging microparticles on the membrane, so the pure sample solution is obtained in the reservoir. The cross-flow filtration chip includes a cross-flow layer, a Ni-Pd alloy micro-porous membrane, and a reservoir layer. The three layers are packaged in a polymethylmethacrylate (PMMA) frame to create the cross-flow filtration chip. Various dilutions of the blood sample (original, 2 × , 3 × , 5 × , and 10×), pore sizes with different diameters (1 µm, 2 µm, 4 µm, 7 µm, and 10 µm), and different flow rates (1 mL/min, 3 mL/min, 5 mL/min, 7 mL/min, and 10 mL/min) are tested to determine their effects on filtration percentage. The best filtration percentage is 96.2% when the dilution of the blood sample is 10 × , the diameter of pore size of a Ni-Pd alloy micro-porous membrane is 2 µm, and the flow rate is 10 mL/min. Finally, for the clinical tests of the immunoglobulin E (IgE) concentration, the cross-flow filtration chip is used to filter the blood of the allergy patients to obtain the blood plasma. This filtered blood plasma is compared with that obtained using the conventional centrifugation based on the enzyme-linked immunosorbent assay. The results reveal that these two blood separation methods have similar detection trends. The proposed filtration chip has the advantages of low cost, short filtration time, and easy operation and thus can be applied to the separation of microparticles, cells, bacteria, and blood.

Laser applications in advanced chip packaging

NASA Astrophysics Data System (ADS)

Müller, Dirk; Held, Andrew; Pätzel, Rainer; Clark, Dave; van Nunen, Joris

2016-03-01

While applications such as drilling μ-vias and laser direct imaging have been well established in the electronics industry, the mobile device industry's push for miniaturization is generating new demands for packaging technologies that allow for further reduction in feature size while reducing manufacturing cost. CO lasers have recently become available and their shorter wavelength allows for a smaller focus and drilling hole diameters down to 25μm whilst keeping the cost similar to CO2 lasers. Similarly, nanosecond UV lasers have gained significantly in power, become more reliable and lower in cost. On a separate front, the cost of ownership reduction for Excimer lasers has made this class of lasers attractive for structuring redistribution layers of IC substrates with feature sizes down to 2μm. Improvements in reliability and lower up-front cost for picosecond lasers is enabling applications that previously were only cost effective with mechanical means or long-pulsed lasers. We can now span the gamut from 100μm to 2μm for via drilling and can cost effectively structure redistribution layers with lasers instead of UV lamps or singulate packages with picosecond lasers.

funtooNorm: an R package for normalization of DNA methylation data when there are multiple cell or tissue types.

PubMed

Oros Klein, Kathleen; Grinek, Stepan; Bernatsky, Sasha; Bouchard, Luigi; Ciampi, Antonio; Colmegna, Ines; Fortin, Jean-Philippe; Gao, Long; Hivert, Marie-France; Hudson, Marie; Kobor, Michael S; Labbe, Aurelie; MacIsaac, Julia L; Meaney, Michael J; Morin, Alexander M; O'Donnell, Kieran J; Pastinen, Tomi; Van Ijzendoorn, Marinus H; Voisin, Gregory; Greenwood, Celia M T

2016-02-15

DNA methylation patterns are well known to vary substantially across cell types or tissues. Hence, existing normalization methods may not be optimal if they do not take this into account. We therefore present a new R package for normalization of data from the Illumina Infinium Human Methylation450 BeadChip (Illumina 450 K) built on the concepts in the recently published funNorm method, and introducing cell-type or tissue-type flexibility. funtooNorm is relevant for data sets containing samples from two or more cell or tissue types. A visual display of cross-validated errors informs the choice of the optimal number of components in the normalization. Benefits of cell (tissue)-specific normalization are demonstrated in three data sets. Improvement can be substantial; it is strikingly better on chromosome X, where methylation patterns have unique inter-tissue variability. An R package is available at https://github.com/GreenwoodLab/funtooNorm, and has been submitted to Bioconductor at http://bioconductor.org. © The Author 2015. Published by Oxford University Press.

Effect of device package on optical, spectral, and thermal properties of InGaN/GaN near-ultraviolet lateral light-emitting diodes

NASA Astrophysics Data System (ADS)

Lee, Soo Hyun; Guan, Xiang-Yu; Jeon, Soo-Kun; Yu, Jae Su

2017-09-01

We investigated the package effect on the temperature-dependent optical and spectral characteristics of InGaN/GaN near-ultraviolet (NUV) lateral light-emitting diodes (LLEDs) on the metal heatsink (MH) and package (PKG) in the injection current range of 0 - 500 mA at 298 and 358 K. For the NUV LLEDs on the MH, the device characteristics reflected directly its chip performance. For the NUV LLEDs on the PKG, the rapidly varied spectral shift as well as the reduced device efficiency was observed due to the increased number of layers with relatively low thermal conductivities. The junction temperature ( T j ) and thermal resistance of the NUV LLEDs on the PKG were also significantly increased compared to the NUV LLEDs on the MH. The three-dimensional heat transfer simulations for both the devices were carried out to obtain the temperature distributions by finite element method. The theoretically calculated T j values showed a good agreement with the experimentally measured T j values.

Sandwich-Architectured Poly(lactic acid)-Graphene Composite Food Packaging Films.

PubMed

Goh, Kunli; Heising, Jenneke K; Yuan, Yang; Karahan, Huseyin E; Wei, Li; Zhai, Shengli; Koh, Jia-Xuan; Htin, Nanda M; Zhang, Feimo; Wang, Rong; Fane, Anthony G; Dekker, Matthijs; Dehghani, Fariba; Chen, Yuan

2016-04-20

Biodegradable food packaging promises a more sustainable future. Among the many different biopolymers used, poly(lactic acid) (PLA) possesses the good mechanical property and cost-effectiveness necessary of a biodegradable food packaging. However, PLA food packaging suffers from poor water vapor and oxygen barrier properties compared to many petroleum-derived ones. A key challenge is, therefore, to simultaneously enhance both the water vapor and oxygen barrier properties of the PLA food packaging. To address this issue, we design a sandwich-architectured PLA-graphene composite film, which utilizes an impermeable reduced graphene oxide (rGO) as the core barrier and commercial PLA films as the outer protective encapsulation. The synergy between the barrier and the protective encapsulation results in a significant 87.6% reduction in the water vapor permeability. At the same time, the oxygen permeability is reduced by two orders of magnitude when evaluated under both dry and humid conditions. The excellent barrier properties can be attributed to the compact lamellar microstructure and the hydrophobicity of the rGO core barrier. Mechanistic analysis shows that the large rGO lateral dimension and the small interlayer spacing between the rGO sheets have created an extensive and tortuous diffusion pathway, which is up to 1450-times the thickness of the rGO barrier. In addition, the sandwiched architecture has imbued the PLA-rGO composite film with good processability, which increases the manageability of the film and its competency to be tailored. Simulations using the PLA-rGO composite food packaging film for edible oil and potato chips also exhibit at least eight-fold extension in the shelf life of these oxygen and moisture sensitive food products. Overall, these qualities have demonstrated the high potential of a sandwich-architectured PLA-graphene composite film for food packaging applications.

Digital isothermal quantification of nucleic acids via simultaneous chemical initiation of recombinase polymerase amplification reactions on SlipChip.

PubMed

Shen, Feng; Davydova, Elena K; Du, Wenbin; Kreutz, Jason E; Piepenburg, Olaf; Ismagilov, Rustem F

2011-05-01

In this paper, digital quantitative detection of nucleic acids was achieved at the single-molecule level by chemical initiation of over one thousand sequence-specific, nanoliter isothermal amplification reactions in parallel. Digital polymerase chain reaction (digital PCR), a method used for quantification of nucleic acids, counts the presence or absence of amplification of individual molecules. However, it still requires temperature cycling, which is undesirable under resource-limited conditions. This makes isothermal methods for nucleic acid amplification, such as recombinase polymerase amplification (RPA), more attractive. A microfluidic digital RPA SlipChip is described here for simultaneous initiation of over one thousand nL-scale RPA reactions by adding a chemical initiator to each reaction compartment with a simple slipping step after instrument-free pipet loading. Two designs of the SlipChip, two-step slipping and one-step slipping, were validated using digital RPA. By using the digital RPA SlipChip, false-positive results from preinitiation of the RPA amplification reaction before incubation were eliminated. End point fluorescence readout was used for "yes or no" digital quantification. The performance of digital RPA in a SlipChip was validated by amplifying and counting single molecules of the target nucleic acid, methicillin-resistant Staphylococcus aureus (MRSA) genomic DNA. The digital RPA on SlipChip was also tolerant to fluctuations of the incubation temperature (37-42 °C), and its performance was comparable to digital PCR on the same SlipChip design. The digital RPA SlipChip provides a simple method to quantify nucleic acids without requiring thermal cycling or kinetic measurements, with potential applications in diagnostics and environmental monitoring under resource-limited settings. The ability to initiate thousands of chemical reactions in parallel on the nanoliter scale using solvent-resistant glass devices is likely to be useful for a broader range of applications.

Digital Isothermal Quantification of Nucleic Acids via Simultaneous Chemical Initiation of Recombinase Polymerase Amplification Reactions on SlipChip

PubMed Central

Shen, Feng; Davydova, Elena K.; Du, Wenbin; Kreutz, Jason E.; Piepenburg, Olaf; Ismagilov, Rustem F.

2011-01-01

In this paper, digital quantitative detection of nucleic acids was achieved at the single-molecule level by chemical initiation of over one thousand sequence-specific, nanoliter, isothermal amplification reactions in parallel. Digital polymerase chain reaction (digital PCR), a method used for quantification of nucleic acids, counts the presence or absence of amplification of individual molecules. However it still requires temperature cycling, which is undesirable under resource-limited conditions. This makes isothermal methods for nucleic acid amplification, such as recombinase polymerase amplification (RPA), more attractive. A microfluidic digital RPA SlipChip is described here for simultaneous initiation of over one thousand nL-scale RPA reactions by adding a chemical initiator to each reaction compartment with a simple slipping step after instrument-free pipette loading. Two designs of the SlipChip, two-step slipping and one-step slipping, were validated using digital RPA. By using the digital RPA SlipChip, false positive results from pre-initiation of the RPA amplification reaction before incubation were eliminated. End-point fluorescence readout was used for “yes or no” digital quantification. The performance of digital RPA in a SlipChip was validated by amplifying and counting single molecules of the target nucleic acid, Methicillin-resistant Staphylococcus aureus (MRSA) genomic DNA. The digital RPA on SlipChip was also tolerant to fluctuations of the incubation temperature (37–42 °C), and its performance was comparable to digital PCR on the same SlipChip design. The digital RPA SlipChip provides a simple method to quantify nucleic acids without requiring thermal cycling or kinetic measurements, with potential applications in diagnostics and environmental monitoring under resource-limited settings. The ability to initiate thousands of chemical reactions in parallel on the nanoliter scale using solvent-resistant glass devices is likely to be useful for a broader range of applications. PMID:21476587

Freeform étendue-preserving optics for light and color mixing

NASA Astrophysics Data System (ADS)

Sorgato, Simone; Mohedano, Rubén.; Chaves, Julio; Cvetkovic, Aleksandra; Hernández, Maikel; Benítez, Pablo; Miñano, Juan C.; Thienpont, Hugo; Duerr, Fabian

2015-09-01

Today's SSL illumination market shows a clear trend towards high flux packages with higher efficiency and higher CRI, realized by means of multiple color chips and phosphors. Such light sources require the optics to provide both near- and far-field color mixing. This design problem is particularly challenging for collimated luminaries, since traditional diffusers cannot be employed without enlarging the exit aperture and reducing brightness (so increasing étendue). Furthermore, diffusers compromise the light output ratio (efficiency) of the lamps to which they are applied. A solution, based on Köhler integration, consisting of a spherical cap comprising spherical microlenses on both its interior and exterior sides was presented in 2012. When placed on top of an inhomogeneous multichip Lambertian LED, this so-called Shell-Mixer creates a homogeneous (both spatially and angularly) virtual source, also Lambertian, where the images of the chips merge. The virtual source is located at the same position with essentially the same size of the original source. The diameter of this optics was 3 times that of the chip-array footprint. In this work, we present a new version of the Shell-Mixer, based on the Edge Ray Principle, where neither the overall shape of the cap nor the surfaces of the lenses are constrained to spheres or rotational Cartesian ovals. This new Shell- Mixer is freeform, only twice as large as the original chip-array and equals the original model in terms of brightness, color uniformity and efficiency.

Detection of micro solder balls using active thermography and probabilistic neural network

NASA Astrophysics Data System (ADS)

He, Zhenzhi; Wei, Li; Shao, Minghui; Lu, Xingning

2017-03-01

Micro solder ball/bump has been widely used in electronic packaging. It has been challenging to inspect these structures as the solder balls/bumps are often embedded between the component and substrates, especially in flip-chip packaging. In this paper, a detection method for micro solder ball/bump based on the active thermography and the probabilistic neural network is investigated. A VH680 infrared imager is used to capture the thermal image of the test vehicle, SFA10 packages. The temperature curves are processed using moving average technique to remove the peak noise. And the principal component analysis (PCA) is adopted to reconstruct the thermal images. The missed solder balls can be recognized explicitly in the second principal component image. Probabilistic neural network (PNN) is then established to identify the defective bump intelligently. The hot spots corresponding to the solder balls are segmented from the PCA reconstructed image, and statistic parameters are calculated. To characterize the thermal properties of solder bump quantitatively, three representative features are selected and used as the input vector in PNN clustering. The results show that the actual outputs and the expected outputs are consistent in identification of the missed solder balls, and all the bumps were recognized accurately, which demonstrates the viability of the PNN in effective defect inspection in high-density microelectronic packaging.

Compact electro-optical module with polymer waveguides on a flexible substrate for high-density board-level communication

NASA Astrophysics Data System (ADS)

Weiss, J. R. M.; Lamprecht, T.; Meier, N.; Dangel, R.; Horst, F.; Jubin, D.; Beyeler, R.; Offrein, B. J.

2010-02-01

We report on the co-packaging of electrical CMOS transceiver and VCSEL chip arrays on a flexible electrical substrate with optical polymer waveguides. The electro-optical components are attached to the substrate edge and butt-coupled to the waveguides. Electrically conductive silver-ink connects them to the substrate at an angle of 90°. The final assembly contacts the surface of a package laminate with an integrated compressible connector. The module can be folded to save space, requires only a small footprint on the package laminate and provides short electrical high-speed signal paths. With our approach, the electro-optical package becomes a compact electro-optical module with integrated polymer waveguides terminated with either optical connectors (e.g., at the card edge) or with an identical assembly for a second processor on the board. Consequently, no costly subassemblies and connectors are needed, and a very high integration density and scalability to virtually arbitrary channel counts and towards very high data rates (20+ Gbps) become possible. Future cost targets of much less than US$1 per Gbps will be reached by employing standard PCB materials and technologies that are well established in the industry. Moreover, our technology platform has both electrical and optical connectivity and functionality.

Small-scale, self-propagating combustion realized with on-chip porous silicon.

PubMed

Piekiel, Nicholas W; Morris, Christopher J

2015-05-13

For small-scale energy applications, energetic materials represent a high energy density source that, in certain cases, can be accessed with a very small amount of energy input. Recent advances in microprocessing techniques allow for the implementation of a porous silicon energetic material onto a crystalline silicon wafer at the microscale; however, combustion at a small length scale remains to be fully investigated, particularly with regards to the limitations of increased relative heat loss during combustion. The present study explores the critical dimensions of an on-chip porous silicon energetic material (porous silicon + sodium perchlorate (NaClO4)) required to propagate combustion. We etched ∼97 μm wide and ∼45 μm deep porous silicon channels that burned at a steady rate of 4.6 m/s, remaining steady across 90° changes in direction. In an effort to minimize the potential on-chip footprint for energetic porous silicon, we also explored the minimum spacing between porous silicon channels. We demonstrated independent burning of porous silicon channels at a spacing of <40 μm. Using this spacing, it was possible to have a flame path length of >0.5 m on a chip surface area of 1.65 cm(2). Smaller porous silicon channels of ∼28 μm wide and ∼14 μm deep were also utilized. These samples propagated combustion, but at times, did so unsteadily. This result may suggest that we are approaching a critical length scale for self-propagating combustion in a porous silicon energetic material.

Pressure-Sensor Assembly Technique

NASA Technical Reports Server (NTRS)

Pruzan, Daniel A.

2003-01-01

Nielsen Engineering & Research (NEAR) recently developed an ultrathin data acquisition system for use in turbomachinery testing at NASA Glenn Research Center. This system integrates a microelectromechanical- systems- (MEMS-) based absolute pressure sensor [0 to 50 psia (0 to 345 kPa)], temperature sensor, signal-conditioning application-specific integrated circuit (ASIC), microprocessor, and digital memory into a package which is roughly 2.8 in. (7.1 cm) long by 0.75 in. (1.9 cm) wide. Each of these components is flip-chip attached to a thin, flexible circuit board and subsequently ground and polished to achieve a total system thickness of 0.006 in. (0.15 mm). Because this instrument is so thin, it can be quickly adhered to any surface of interest where data can be collected without disrupting the flow being investigated. One issue in the development of the ultrathin data acquisition system was how to attach the MEMS pressure sensor to the circuit board in a manner which allowed the sensor s diaphragm to communicate with the ambient fluid while providing enough support for the chip to survive the grinding and polishing operations. The technique, developed by NEAR and Jabil Technology Services Group (San Jose, CA), is described below. In the approach developed, the sensor is attached to the specially designed circuit board, see Figure 1, using a modified flip-chip technique. The circular diaphragm on the left side of the sensor is used to actively measure the ambient pressure, while the diaphragm on the right is used to compensate for changes in output due to temperature variations. The circuit board is fabricated with an access hole through it so that when the completed system is installed onto a wind tunnel model (chip side down), the active diaphragm is exposed to the environment. After the sensor is flip-chip attached to the circuit board, the die is underfilled to support the chip during the subsequent grinding and polishing operations. To prevent this underfill material from getting onto the sensor s diaphragms, the circuit board is fabricated with two 25- micrometer-tall polymer rings, sized so that the diaphragms fit inside the rings once the chip is attached.

Coping with Health Problems: Developing a Reliable and Valid Multidimensional Measure.

ERIC Educational Resources Information Center

Endler, Norman S.; Parker, James D. A.; Summerfeldt, Laura J.

1998-01-01

A self-report measure, the Coping with Health Injuries and Problems Scale (CHIP), was developed to identify basic coping dimensions for responding to health problems. The CHIP factor structure, established with samples of 532 adults and 598 adults in Canada, is cross-validated with 390 general medical patients and 286 chronic back pain patients.…

Production, Cost and Chip Characteristics of In-Woods Microchipping

Treesearch

J. Thompson; W. Sprinkle

2013-01-01

Emerging markets for biomass have increased the interest in producing microchips in the field. As a component of a large United States Department of Energy (DOE) funded project, microchipping has been trialed on a limited scale. The goal of the research was to evaluate the production, cost and chip characteristics of a mobile disc chipper configured to produce...

Estimating minimal important differences for several scales assessing function and quality of life in patients with attention-deficit/hyperactivity disorder.

PubMed

Hodgkins, Paul; Lloyd, Andrew; Erder, M Haim; Setyawan, Juliana; Weiss, Margaret D; Sasané, Rahul; Nafees, Beenish

2017-02-01

Defining minimal important difference (MID) is critical to interpreting patient-reported outcomes data and treatment efficacy in clinical trials. This study estimates the MID for the Weiss Functional Impairment Rating Scale-Parent Report (WFIRS-P) and the Child Health and Illness Profile-Parent Report (CHIP-CE-PRF76) among parents of young people with attention-deficit/hyperactivity disorder (ADHD) in the UK. Parents of children (6-12 years; n=100) and adolescents (13-17 years; n=117) with ADHD completed a socio-demographic form, the CHIP-CE-PRF76, the WFIRS-P, and the Pediatric Quality of Life scale at baseline and 4 weeks later. At follow-up, a subset of parents completed anchor questions measuring change in the child/adolescent from baseline. MIDs were estimated using anchor-based and distribution-based methods, and separately for children and adolescents. The MID estimates for overall change in the WFIRS-P total score ranged from 11.31 (standard error of measurement) to 13.47 (anchor) for the total sample. The range of MID estimates for the CHIP-CE-PRF76 varied by domain: 6.80-7.41 (satisfaction), 6.18-7.34 (comfort), 5.60-6.72 (resilience), 6.06-7.57 (risk avoidance), and 4.00-5.63 (achievement) for the total sample. Overall, MID estimates for WFIRS-P MID and CHIP-CE-PRF76 were slightly higher for adolescents than for children. This study estimated MIDs for these instruments using several methods. The observed convergence of the MID estimates increases confidence in their reliability and could assist clinicians and decision makers in deriving meaningful interpretations of observed changes in the WFIRS-P and CHIP-CE in clinical trials and practice.

NMR spectroscopy of single sub-nL ova with inductive ultra-compact single-chip probes

PubMed Central

Grisi, Marco; Vincent, Franck; Volpe, Beatrice; Guidetti, Roberto; Harris, Nicola; Beck, Armin; Boero, Giovanni

2017-01-01

Nuclear magnetic resonance (NMR) spectroscopy enables non-invasive chemical studies of intact living matter. However, the use of NMR at the volume scale typical of microorganisms is hindered by sensitivity limitations, and experiments on single intact organisms have so far been limited to entities having volumes larger than 5 nL. Here we show NMR spectroscopy experiments conducted on single intact ova of 0.1 and 0.5 nL (i.e. 10 to 50 times smaller than previously achieved), thereby reaching the relevant volume scale where life development begins for a broad variety of organisms, humans included. Performing experiments with inductive ultra-compact (1 mm2) single-chip NMR probes, consisting of a low noise transceiver and a multilayer 150 μm planar microcoil, we demonstrate that the achieved limit of detection (about 5 pmol of 1H nuclei) is sufficient to detect endogenous compounds. Our findings suggest that single-chip probes are promising candidates to enable NMR-based study and selection of microscopic entities at biologically relevant volume scales. PMID:28317887

Parachute Dynamics Investigations Using a Sensor Package Airdropped from a Small-Scale Airplane

NASA Technical Reports Server (NTRS)

Dooley, Jessica; Lorenz, Ralph D.

2005-01-01

We explore the utility of various sensors by recovering parachute-probe dynamics information from a package released from a small-scale, remote-controlled airplane. The airdrops aid in the development of datasets for the exploration of planetary probe trajectory recovery algorithms, supplementing data collected from instrumented, full-scale tests and computer models.

Effect of Various Packaging Methods on Small-Scale Hanwoo (Korean Native Cattle) during Refrigerated Storage

PubMed Central

Yu, Hwan Hee; Song, Myung Wook; Kim, Tae-Kyung; Choi, Yun-Sang; Cho, Gyu Yong; Lee, Na-Kyoung; Paik, Hyun-Dong

2018-01-01

Abstract The objective of this study was to investigate comparison of physicochemical, microbiological, and sensory characteristics of Hanwoo eye of round by various packaging methods [wrapped packaging (WP), modified atmosphere packaging (MAP), vacuum packaging (VP) with three different vacuum films, and vacuum skin packaging (VSP)] at a small scale. Packaged Hanwoo beef samples were stored in refrigerated conditions (4±1°C) for 28 days. Packaged beef was sampled on days 0, 7, 14, 21, and 28. Physicochemical [pH, surface color, thiobarbituric acid reactive substances (TBARS), and volatile basic nitrogen (VBN) values], microbiological, and sensory analysis of packaged beef samples were performed. VP and VSP samples showed low TBARS and VBN values, and pH and surface color did not change substantially during the 28-day period. For VSP, total viable bacteria, psychrotrophic bacteria, lactic acid bacteria, and coliform counts were lower than those for other packaging systems. Salmonella spp. and Escherichia coli O157:H7 were not detected in any packaged beef samples. A sensory analysis showed that the scores for appearance, flavor, color, and overall acceptability did not change significantly until day 7. In total, VSP was effective with respect to significantly higher a* values, physicochemical stability, and microbial safety in Hanwoo packaging (p<0.05). PMID:29805283

Optical wireless link between a nanoscale antenna and a transducing rectenna.

PubMed

Dasgupta, Arindam; Mennemanteuil, Marie-Maxime; Buret, Mickaël; Cazier, Nicolas; Colas-des-Francs, Gérard; Bouhelier, Alexandre

2018-05-18

Initiated as a cable-replacement solution, short-range wireless power transfer has rapidly become ubiquitous in the development of modern high-data throughput networking in centimeter to meter accessibility range. Wireless technology is now penetrating a higher level of system integration for chip-to-chip and on-chip radiofrequency interconnects. However, standard CMOS integrated millimeter-wave antennas have typical size commensurable with the operating wavelength, and are thus an unrealistic solution for downsizing transmitters and receivers to the micrometer and nanometer scale. Herein, we demonstrate a light-in and electrical signal-out, on-chip wireless near-infrared link between a 220 nm optical antenna and a sub-nanometer rectifying antenna converting the transmitted optical energy into direct electrical current. The co-integration of subwavelength optical functional devices with electronic transduction offers a disruptive solution to interface photons and electrons at the nanoscale for on-chip wireless optical interconnects.

Laser Light-field Fusion for Wide-field Lensfree On-chip Phase Contrast Microscopy of Nanoparticles

NASA Astrophysics Data System (ADS)

Kazemzadeh, Farnoud; Wong, Alexander

2016-12-01

Wide-field lensfree on-chip microscopy, which leverages holography principles to capture interferometric light-field encodings without lenses, is an emerging imaging modality with widespread interest given the large field-of-view compared to lens-based techniques. In this study, we introduce the idea of laser light-field fusion for lensfree on-chip phase contrast microscopy for detecting nanoparticles, where interferometric laser light-field encodings acquired using a lensfree, on-chip setup with laser pulsations at different wavelengths are fused to produce marker-free phase contrast images of particles at the nanometer scale. As a proof of concept, we demonstrate, for the first time, a wide-field lensfree on-chip instrument successfully detecting 300 nm particles across a large field-of-view of ~30 mm2 without any specialized or intricate sample preparation, or the use of synthetic aperture- or shift-based techniques.

A new technique to detect antibody-antigen reaction (biological interactions) on a localized surface plasmon resonance (LSPR) based nano ripple gold chip

NASA Astrophysics Data System (ADS)

Saleem, Iram; Widger, William; Chu, Wei-Kan

2017-07-01

We demonstrate that the gold nano-ripple localized surface plasmon resonance (LSPR) chip is a low cost and a label-free method for detecting the presence of an antigen. A uniform stable layer of an antibody was coated on the surface of a nano-ripple gold pattern chip followed by the addition of different concentrations of the antigen. A red shift was observed in the LSPR spectral peak caused by the change in the local refractive index in the vicinity of the nanostructure. The LSPR chip was fabricated using oblique gas cluster ion beam (GCIB) irradiation. The plasmon-resonance intensity of the scattered light was measured by a simple optical spectroscope. The gold nano ripple chip shows monolayer scale sensitivity and high selectivity. The LSPR substrate was used to detect antibody-antigen reaction of rabbit X-DENTT antibody and DENTT blocking peptide (antigen).

Laser Light-field Fusion for Wide-field Lensfree On-chip Phase Contrast Microscopy of Nanoparticles.

PubMed

Kazemzadeh, Farnoud; Wong, Alexander

2016-12-13

Wide-field lensfree on-chip microscopy, which leverages holography principles to capture interferometric light-field encodings without lenses, is an emerging imaging modality with widespread interest given the large field-of-view compared to lens-based techniques. In this study, we introduce the idea of laser light-field fusion for lensfree on-chip phase contrast microscopy for detecting nanoparticles, where interferometric laser light-field encodings acquired using a lensfree, on-chip setup with laser pulsations at different wavelengths are fused to produce marker-free phase contrast images of particles at the nanometer scale. As a proof of concept, we demonstrate, for the first time, a wide-field lensfree on-chip instrument successfully detecting 300 nm particles across a large field-of-view of ~30 mm 2 without any specialized or intricate sample preparation, or the use of synthetic aperture- or shift-based techniques.

Qubit entanglement between ring-resonator photon-pair sources on a silicon chip

PubMed Central

Silverstone, J. W.; Santagati, R.; Bonneau, D.; Strain, M. J.; Sorel, M.; O'Brien, J. L.; Thompson, M. G.

2015-01-01

Entanglement—one of the most delicate phenomena in nature—is an essential resource for quantum information applications. Scalable photonic quantum devices must generate and control qubit entanglement on-chip, where quantum information is naturally encoded in photon path. Here we report a silicon photonic chip that uses resonant-enhanced photon-pair sources, spectral demultiplexers and reconfigurable optics to generate a path-entangled two-qubit state and analyse its entanglement. We show that ring-resonator-based spontaneous four-wave mixing photon-pair sources can be made highly indistinguishable and that their spectral correlations are small. We use on-chip frequency demultiplexers and reconfigurable optics to perform both quantum state tomography and the strict Bell-CHSH test, both of which confirm a high level of on-chip entanglement. This work demonstrates the integration of high-performance components that will be essential for building quantum devices and systems to harness photonic entanglement on the large scale. PMID:26245267

Face classification using electronic synapses

NASA Astrophysics Data System (ADS)

Yao, Peng; Wu, Huaqiang; Gao, Bin; Eryilmaz, Sukru Burc; Huang, Xueyao; Zhang, Wenqiang; Zhang, Qingtian; Deng, Ning; Shi, Luping; Wong, H.-S. Philip; Qian, He

2017-05-01

Conventional hardware platforms consume huge amount of energy for cognitive learning due to the data movement between the processor and the off-chip memory. Brain-inspired device technologies using analogue weight storage allow to complete cognitive tasks more efficiently. Here we present an analogue non-volatile resistive memory (an electronic synapse) with foundry friendly materials. The device shows bidirectional continuous weight modulation behaviour. Grey-scale face classification is experimentally demonstrated using an integrated 1024-cell array with parallel online training. The energy consumption within the analogue synapses for each iteration is 1,000 × (20 ×) lower compared to an implementation using Intel Xeon Phi processor with off-chip memory (with hypothetical on-chip digital resistive random access memory). The accuracy on test sets is close to the result using a central processing unit. These experimental results consolidate the feasibility of analogue synaptic array and pave the way toward building an energy efficient and large-scale neuromorphic system.

Face classification using electronic synapses.

PubMed

Yao, Peng; Wu, Huaqiang; Gao, Bin; Eryilmaz, Sukru Burc; Huang, Xueyao; Zhang, Wenqiang; Zhang, Qingtian; Deng, Ning; Shi, Luping; Wong, H-S Philip; Qian, He

2017-05-12

Conventional hardware platforms consume huge amount of energy for cognitive learning due to the data movement between the processor and the off-chip memory. Brain-inspired device technologies using analogue weight storage allow to complete cognitive tasks more efficiently. Here we present an analogue non-volatile resistive memory (an electronic synapse) with foundry friendly materials. The device shows bidirectional continuous weight modulation behaviour. Grey-scale face classification is experimentally demonstrated using an integrated 1024-cell array with parallel online training. The energy consumption within the analogue synapses for each iteration is 1,000 × (20 ×) lower compared to an implementation using Intel Xeon Phi processor with off-chip memory (with hypothetical on-chip digital resistive random access memory). The accuracy on test sets is close to the result using a central processing unit. These experimental results consolidate the feasibility of analogue synaptic array and pave the way toward building an energy efficient and large-scale neuromorphic system.

MOBE-ChIP: Probing Cell Type-Specific Binding Through Large-Scale Chromatin Immunoprecipitation.

PubMed

Wang, Shenqi; Lau, On Sun

2018-01-01

In multicellular organisms, the initiation and maintenance of specific cell types often require the activity of cell type-specific transcriptional regulators. Understanding their roles in gene regulation is crucial but probing their DNA targets in vivo, especially in a genome-wide manner, remains a technical challenge with their limited expression. To improve the sensitivity of chromatin immunoprecipitation (ChIP) for detecting the cell type-specific signals, we have developed the Maximized Objects for Better Enrichment (MOBE)-ChIP, where ChIP is performed at a substantially larger experimental scale and under low background conditions. Here, we describe the procedure in the study of transcription factors in the model plant Arabidopsis. However, with some modifications, the technique should also be implemented in other systems. Besides cell type-specific studies, MOBE-ChIP can also be used as a general strategy to improve ChIP signals.

Highly localized distributed Brillouin scattering response in a photonic integrated circuit

NASA Astrophysics Data System (ADS)

Zarifi, Atiyeh; Stiller, Birgit; Merklein, Moritz; Li, Neuton; Vu, Khu; Choi, Duk-Yong; Ma, Pan; Madden, Stephen J.; Eggleton, Benjamin J.

2018-03-01

The interaction of optical and acoustic waves via stimulated Brillouin scattering (SBS) has recently reached on-chip platforms, which has opened new fields of applications ranging from integrated microwave photonics and on-chip narrow-linewidth lasers, to phonon-based optical delay and signal processing schemes. Since SBS is an effect that scales exponentially with interaction length, on-chip implementation on a short length scale is challenging, requiring carefully designed waveguides with optimized opto-acoustic overlap. In this work, we use the principle of Brillouin optical correlation domain analysis to locally measure the SBS spectrum with high spatial resolution of 800 μm and perform a distributed measurement of the Brillouin spectrum along a spiral waveguide in a photonic integrated circuit. This approach gives access to local opto-acoustic properties of the waveguides, including the Brillouin frequency shift and linewidth, essential information for the further development of high quality photonic-phononic waveguides for SBS applications.

Monitoring CO2 invasion processes at the pore scale using geological labs on chip.

PubMed

Morais, S; Liu, N; Diouf, A; Bernard, D; Lecoutre, C; Garrabos, Y; Marre, S

2016-09-21

In order to investigate at the pore scale the mechanisms involved during CO2 injection in a water saturated pore network, a series of displacement experiments is reported using high pressure micromodels (geological labs on chip - GLoCs) working under real geological conditions (25 < T (°C) < 75 and 4.5 < p (MPa) < 8). The experiments were focused on the influence of three experimental parameters: (i) the p, T conditions, (ii) the injection flow rates and (iii) the pore network characteristics. By using on-chip optical characterization and imaging approaches, the CO2 saturation curves as a function of either time or the number of pore volume injected were determined. Three main mechanisms were observed during CO2 injection, namely, invasion, percolation and drying, which are discussed in this paper. Interestingly, besides conventional mechanisms, two counterintuitive situations were observed during the invasion and drying processes.

The fastclime Package for Linear Programming and Large-Scale Precision Matrix Estimation in R.

PubMed

Pang, Haotian; Liu, Han; Vanderbei, Robert

2014-02-01

We develop an R package fastclime for solving a family of regularized linear programming (LP) problems. Our package efficiently implements the parametric simplex algorithm, which provides a scalable and sophisticated tool for solving large-scale linear programs. As an illustrative example, one use of our LP solver is to implement an important sparse precision matrix estimation method called CLIME (Constrained L 1 Minimization Estimator). Compared with existing packages for this problem such as clime and flare, our package has three advantages: (1) it efficiently calculates the full piecewise-linear regularization path; (2) it provides an accurate dual certificate as stopping criterion; (3) it is completely coded in C and is highly portable. This package is designed to be useful to statisticians and machine learning researchers for solving a wide range of problems.

DOE Office of Scientific and Technical Information (OSTI.GOV)

McAdams, Brian J.; Pearson, Raymond A.

With the continuing trend of decreasing feature sizes in flip-chip assemblies, the reliability tolerance to interfacial flaws is also decreasing. Small-scale disbonds will become more of a concern, pointing to the need for a better understanding of the initiation stage of interfacial delamination. With most accepted adhesion metric methodologies tailored to predict failure under the prior existence of a disbond, the study of the initiation phenomenon is open to development and standardization of new testing procedures. Traditional fracture mechanics approaches are not suitable, as the mathematics assume failure to originate at a disbond or crack tip. Disbond initiation is believedmore » to first occur at free edges and corners, which act as high stress concentration sites and exhibit singular stresses similar to a crack tip, though less severe in intensity. As such, a 'fracture mechanics-like' approach may be employed which defines a material parameter--a critical stress intensity factor (K{sub c})--that can be used to predict when initiation of a disbond at an interface will occur. The factors affecting the adhesion of underfill/polyimide interfaces relevant to flip-chip assemblies were investigated in this study. The study consisted of two distinct parts: a comparison of the initiation and propagation phenomena and a comparison of the relationship between sub-critical and critical initiation of interfacial failure. The initiation of underfill interfacial failure was studied by characterizing failure at a free-edge with a critical stress intensity factor. In comparison with the interfacial fracture toughness testing, it was shown that a good correlation exists between the initiation and propagation of interfacial failures. Such a correlation justifies the continuing use of fracture mechanics to predict the reliability of flip-chip packages. The second aspect of the research involved fatigue testing of tensile butt joint specimens to determine lifetimes at sub-critical load levels. The results display an interfacial strength ranking similar to that observed during monotonic testing. The fatigue results indicate that monotonic fracture mechanics testing may be an adequate screening tool to help predict cyclic underfill failure; however lifetime data is required to predict reliability.« less

Efficacy of 10% whole Azadirachta indica (neem) chip as an adjunct to scaling and root planning in chronic periodontitis: A clinical and microbiological study.

PubMed

Vennila, K; Elanchezhiyan, S; Ilavarasu, Sugumari

2016-01-01

Anti-microbial therapy is essential along with conventional therapy in the management of periodontal disease. Instead of systemic chemical agents, herbal products could be used as antimicrobial agents. Herbal local drug delivery systems are effective alternative for systemic therapy in managing the chronic periodontal disease. In this study, 10% neem oil chip was used as a local drug delivery system to evaluate the efficacy in the periodontal disease management. Twenty otherwise healthy patients with the bilateral periodontal probing depth of 5-6 mm were included in the study. After scaling and root planning (SRP), 10% nonabsorbable neem chip was placed in the pocket in one side of the arch. Other side was done with SRP only. Clinical parameters were recorded on the baseline, 7th day, and 21st day. Plaque samples were obtained for a microbiological study on the baseline and 21st day. Porphyromonas gingivalis strains were seen using quantitative and qualitative polymerase chain reaction assay. All results were statistically evaluated. Clinical parameters showed statistically improved on the neem chip sites and presence of P. gingivalis strains were significantly reduced on the neem chip sites. Hence, 10% neem oil local delivery system delivers desired effects on P. gingivalis. Further research is needed to evaluate the neem oil efficacy on other periodontal pathogens.

European MEMS foundries

NASA Astrophysics Data System (ADS)

Salomon, Patric R.

2003-01-01

According to the latest release of the NEXUS market study, the market for MEMS or Microsystems Technology (MST) is predicted to grow to $68B by the year 2005, with systems containing these components generating even higher revenues and growth. The latest advances in MST/MEMS technology have enabled the design of a new generation of microsystems that are smaller, cheaper, more reliable, and consume less power. These integrated systems bring together numerous analog/mixed signal microelectronics blocks and MEMS functions on a single chip or on two or more chips assembled within an integrated package. In spite of all these advances in technology and manufacturing, a system manufacturer either faces a substantial up-front R&D investment to create his own infrastructure and expertise, or he can use design and foundry services to get the initial product into the marketplace fast and with an affordable investment. Once he has a viable product, he can still think about his own manufacturing efforts and investments to obtain an optimized high volume manufacturing for the specific product. One of the barriers to successful exploitation of MEMS/MST technology has been the lack of access to industrial foundries capable of producing certified microsystems devices in commercial quantities, including packaging and test. This paper discusses Multi-project wafer (MPW) runs, requirements for foundries and gives some examples of foundry business models. Furthermore, this paper will give an overview on MST/MEMS services that are available in Europe, including pure commercial activities, European project activities (e.g. Europractice), and some academic services.

Microstructural Evolution of Ni-Sn Transient Liquid Phase Sintering Bond during High-Temperature Aging

NASA Astrophysics Data System (ADS)

Feng, Hongliang; Huang, Jihua; Peng, Xianwen; Lv, Zhiwei; Wang, Yue; Yang, Jian; Chen, Shuhai; Zhao, Xingke

2018-05-01

For high-temperature-resistant packaging of new generation power chip, a chip packaging simulation structure of Ni/Ni-Sn/Ni was bonded by a transient liquid-phase sintering process. High-temperature aging experiments were carried out to investigate joint heat stability. The microstructural evolution and mechanism during aging, and mechanical properties after aging were analyzed. The results show that the 30Ni-70Sn bonding layer as-bonded at 340°C for 240 min is mainly composed of Ni3Sn4 and residual Ni particles. When aged at 350°C, because of the difficulty of nucleation for Ni3Sn and quite slow growth of Ni3Sn2, the bonding layer is stable and the strength of that doesn't change obviously with aging time. When aging temperature increased to 500°C, however, the residual Ni particles were gradually dissolved and the bonding layer formed a stable structure with dominated Ni3Sn2 after 36 h. Meanwhile, due to the volume shrinkage (4.43%) from Ni3Sn2 formation, a number of voids were formed. The shear strength shows an increase, resulting from Ni3Sn2 formation, but then it decreases slightly caused by voids. After aging at 500°C for 100 h, shear strength is still maintained at 29.6 MPa. In addition, the mechanism of void formation was analyzed and microstructural evolution model was also established.

Silicon photonics devices for metro applications

NASA Astrophysics Data System (ADS)

Fukuda, H.; Kikuchi, K.; Jizodo, M.; Kawamura, Y.; Takeda, K.; Honda, K.

2017-01-01

Digital coherent technology is considered an attractive way of realizing both high-speed metro links and long distance transmissions. In metro areas, there is a strong demand for a smaller, faster transceiver module. This demand is mainly driven by the rapidly increasing data center interconnection traffic, where transmission capacity per faceplane is a key feature. Therefore, optical integration technology is desired. Since compensation in digital coherent technology is performed in the electrical or digital domain, users can deal with those optics performances that are not compensated for digitally. This means using a new material that cannot provide perfect characteristics but that is suitable for miniaturization and integration is possible. Silicon photonics (SiPh) is considered an attractive technology that would enable the significant miniaturization of optical circuits and be capable of optical integration with high manufacturability. While SiPh-based devices have begun to be deployed for very short or short reach links on the basis of direct detection technology, their digital coherent applications have recently been investigated in view of their integration capability. This paper describes recent progress on SiPh-based integrated optical devices for high-speed digital coherent transceivers targeting metro links. An optical modulator and receiver with related circuits have been integrated into a single SiPh chip. TEC-free operation under non-hermetic conditions and the direct attachment of optical fibers have both been realized. Very thin and small packaging with sufficient performance has been demonstrated by using the SiPh chip co-packaged with high-speed ICs.

VCSEL technology for medical diagnostics and therapeutics

NASA Astrophysics Data System (ADS)

Hibbs-Brenner, M. K.; Johnson, K. L.; Bendett, M.

2009-02-01

In the 1990's a new laser technology, Vertical Cavity Surface Emitting Lasers, or VCSELs, emerged and transformed the data communication industry. The combination of performance characteristics, reliability and performance/cost ratio allowed high data rate communication to occur over short distances at a commercially viable price. VCSELs have not been widely used outside of this application space, but with the development of new attributes, such as a wider range of available wavelengths, the demonstration of arrays of VCSELs on a single chip, and a variety of package form factors, VCSELs can have a significant impact on medical diagnostic and therapeutic applications. One area of potential application is neurostimulation. Researchers have previously demonstrated the feasibility of using 1850nm light for nerve stimulation. The ability to create an array of VCSELs emitting at this wavelength would allow significantly improved spatial resolution, and multiple parallel channels of stimulation. For instance, 2D arrays of 100 lasers or more can be integrated on a single chip less than 2mm on a side. A second area of interest is non-invasive sensing. Performance attributes such as the narrow spectral width, low power consumption, and packaging flexibility open up new possibilities in non-invasive and/or continuous sensing. This paper will suggest ways in which VCSELs can be implemented within these application areas, and the advantages provided by the unique performance characteristics of the VCSEL. The status of VCSEL technology as a function of available wavelength and array size and form factors will be summarized.

A polarization converting device for an interfering enhanced CPT atomic clock.

PubMed

Wang, Kewei; Tian, Yuan; Yin, Yi; Wang, Yuanchao; Gu, Sihong

2017-11-01

With interfering enhanced coherent population trapping (CPT) signals, a CPT atomic clock with improved frequency stability performance can be realized. We explore an optical device that converts single-polarized bichromatic light to left and right circularly polarized superposed bichromatic light to generate interfering enhanced CPT resonance with atoms. We have experimentally studied a tabletop CPT atomic clock apparatus with a microfabricated 87 Rb atomic chip-scale cell, and the study results show that it is promising to realize a compact CPT atomic clock, even a chip-scale CPT atomic clock through microfabrication, with improved frequency stability performance.

A polarization converting device for an interfering enhanced CPT atomic clock

NASA Astrophysics Data System (ADS)

Wang, Kewei; Tian, Yuan; Yin, Yi; Wang, Yuanchao; Gu, Sihong

2017-11-01

With interfering enhanced coherent population trapping (CPT) signals, a CPT atomic clock with improved frequency stability performance can be realized. We explore an optical device that converts single-polarized bichromatic light to left and right circularly polarized superposed bichromatic light to generate interfering enhanced CPT resonance with atoms. We have experimentally studied a tabletop CPT atomic clock apparatus with a microfabricated 87Rb atomic chip-scale cell, and the study results show that it is promising to realize a compact CPT atomic clock, even a chip-scale CPT atomic clock through microfabrication, with improved frequency stability performance.