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Sample records for circuit asic application

  1. Memory-Based Structured Application Specific Integrated Circuit (ASIC) Study

    DTIC Science & Technology

    2008-10-01

    phase switching technique," Electronics Letters, vol. 37, no. 14, pp. 875-877, Jul 2001. [10] W. Dally and B. Towles , Principles and Practices of...and A. Alvandpour, "A six-port 57gb/s double-pumped nonblocking router core," VLSI Circuits, 2005. Digest of Technical Papers . 2005 Symposium on, pp

  2. A Low Power Application-Specific Integrated Circuit (ASIC) Implementation of Wavelet Transform/Inverse Transform

    DTIC Science & Technology

    2001-03-01

    A unique ASIC was designed implementing the Haar Wavelet transform for image compression/decompression. ASIC operations include performing the Haar... wavelet transform on a 512 by 512 square pixel image, preparing the image for transmission by quantizing and thresholding the transformed data, and...performing the inverse Haar wavelet transform , returning the original image with only minor degradation. The ASIC is based on an existing four-chip FPGA

  3. Characteristics and development report for the SA3871 Intent Controller application specific integrated circuit (ASIC)

    SciTech Connect

    Simpson, R.L.; Meyer, B.T.

    1995-08-01

    This report describes the design and development activities that were involved in the SA3871 Intent Controller ASIC. The SA3871 is a digital gate array component developed for the MC4396 Trajectory Sensing Signal Generator for use in the B61-3/4/10 system as well as a possible future B61-MAST system.

  4. TOFPET ASIC for PET applications

    NASA Astrophysics Data System (ADS)

    Rolo, M. D.; Bugalho, R.; Gonçalves, F.; Mazza, G.; Rivetti, A.; Silva, J. C.; Silva, R.; Varela, J.

    2013-02-01

    A 64-channel ASIC for Time-of-Flight Positron Emission Tomography (TOF PET) imaging has been designed and simulated. The circuit is optimized for the readout of signals produced by the scintillation of a L(Y)SO crystal optically coupled to a silicon photomultiplier (SiPM). Developed in the framework of the EndoTOFPET-US collaboration [1], the ASIC is integrated in the external PET plate and performs timing, digitization and data transmission for 511 keV and lower-energy events due to Compton scattering. Multi-event buffering capability allows event rates up to 100 kHz per channel. The channel cell includes a low input impedance low-noise current conveyor and two trans-impedance amplifier branches separately optimized for energy and time resolution. Two voltage mode discriminators generate respectively a fast trigger for accurate timing and a signal for time-over-threshold calculation, used for charge measurement. The digitization of these signals is done by two low-power TDCs, providing coarse and fine time stamps that are saved into a local register and later managed by a global controller, which builds-up the 40-bit event data and runs the interface with the data acquisition back-end. Running at 160 MHz the chip yields a 50 ps time binning and dissipates ≊ 7 mW per channel (simulated for 40 kHz event rate p/channel) for high capacitance photodetectors (9 mm2 active area Silicon Photomultiplier with 320 pF terminal capacitance). The minimum SNR of 23.5 dB expected with this capacitance should allow triggering on the first photoelectron to achieve the envisaged timing performance for a TOF-PET system.

  5. ASIC Readout Circuit Architecture for Large Geiger Photodiode Arrays

    NASA Technical Reports Server (NTRS)

    Vasile, Stefan; Lipson, Jerold

    2012-01-01

    The objective of this work was to develop a new class of readout integrated circuit (ROIC) arrays to be operated with Geiger avalanche photodiode (GPD) arrays, by integrating multiple functions at the pixel level (smart-pixel or active pixel technology) in 250-nm CMOS (complementary metal oxide semiconductor) processes. In order to pack a maximum of functions within a minimum pixel size, the ROIC array is a full, custom application-specific integrated circuit (ASIC) design using a mixed-signal CMOS process with compact primitive layout cells. The ROIC array was processed to allow assembly in bump-bonding technology with photon-counting infrared detector arrays into 3-D imaging cameras (LADAR). The ROIC architecture was designed to work with either common- anode Si GPD arrays or common-cathode InGaAs GPD arrays. The current ROIC pixel design is hardwired prior to processing one of the two GPD array configurations, and it has the provision to allow soft reconfiguration to either array (to be implemented into the next ROIC array generation). The ROIC pixel architecture implements the Geiger avalanche quenching, bias, reset, and time to digital conversion (TDC) functions in full-digital design, and uses time domain over-sampling (vernier) to allow high temporal resolution at low clock rates, increased data yield, and improved utilization of the laser beam.

  6. Rad-Hard Structured ASIC Body of Knowledge

    NASA Technical Reports Server (NTRS)

    Heidecker, Jason

    2013-01-01

    Structured Application-Specific Integrated Circuit (ASIC) technology is a platform between traditional ASICs and Field-Programmable Gate Arrays (FPGA). The motivation behind structured ASICs is to combine the low nonrecurring engineering costs (NRE) costs of FPGAs with the high performance of ASICs. This report provides an overview of the structured ASIC platforms that are radiation-hardened and intended for space application

  7. Design for ASIC reliability for low-temperature applications

    NASA Technical Reports Server (NTRS)

    Chen, Yuan; Mojaradi, Mohammad; Westergard, Lynett; Billman, Curtis; Cozy, Scott; Burke, Gary; Kolawa, Elizabeth

    2005-01-01

    In this paper, we present a methodology to design for reliability for low temperature applications without requiring process improvement. The developed hot carrier aging lifetime projection model takes into account both the transistor substrate current profile and temperature profile to determine the minimum transistor size needed in order to meet reliability requirements. The methodology is applicable for automotive, military, and space applications, where there can be varying temperature ranges. A case study utilizing this methodology is given to design for reliability into a custom application-specific integrated circuit (ASIC) for a Mars exploration mission.

  8. Circuit design and simulation of a transmit beamforming ASIC for high-frequency ultrasonic imaging systems.

    PubMed

    Athanasopoulos, Georgios I; Carey, Stephen J; Hatfield, John V

    2011-07-01

    This paper describes the design of a programmable transmit beamformer application-specific integrated circuit (ASIC) with 8 channels for ultrasound imaging systems. The system uses a 20-MHz reference clock. A digital delay-locked loop (DLL) was designed with 50 variable delay elements, each of which provides a clock with different phase from a single reference. Two phase detectors compare the phase difference of the reference clock with the feedback clock, adjusting the delay of the delay elements to bring the feedback clock signal in phase with the reference clock signal. Two independent control voltages for the delay elements ensure that the mark space ratio of the pulses remain at 50%. By combining a 10- bit asynchronous counter with the delays from the DLL, each channel can be programmed to give a maximum time delay of 51 μs with 1 ns resolution. It can also give bursts of up to 64 pulses. Finally, for a single pulse, it can adjust the pulse width between 9 ns and 100 ns by controlling the current flowing through a capacitor in a one-shot circuit, for use with 40-MHz and 5-MHz transducers, respectively.

  9. ASIC design at Fermilab

    SciTech Connect

    Yarema, R.

    1991-06-01

    In the past few years, ASIC (Application Specific Integrated Circuit) design has become important at Fermilab. The purpose of this paper is to present an overview of the in-house ASIC design activity which has taken place. This design effort has added much value to the high energy physics program and physics capability at Fermilab. The two approaches to ASIC development being pursued at Fermilab are examined by looking at some of the types of projects where ASICs are being used or contemplated. To help estimate the cost of future designs, a cost comparison is given to show the relative development and production expenses for these two ASIC approaches. 5 refs., 14 figs., 7 tabs.

  10. An Energy-Efficient ASIC for Wireless Body Sensor Networks in Medical Applications.

    PubMed

    Xiaoyu Zhang; Hanjun Jiang; Lingwei Zhang; Chun Zhang; Zhihua Wang; Xinkai Chen

    2010-02-01

    An energy-efficient application-specific integrated circuit (ASIC) featured with a work-on-demand protocol is designed for wireless body sensor networks (WBSNs) in medical applications. Dedicated for ultra-low-power wireless sensor nodes, the ASIC consists of a low-power microcontroller unit (MCU), a power-management unit (PMU), reconfigurable sensor interfaces, communication ports controlling a wireless transceiver, and an integrated passive radio-frequency (RF) receiver with energy harvesting ability. The MCU, together with the PMU, provides quite flexible communication and power-control modes for energy-efficient operations. The always-on passive RF receiver with an RF energy harvesting block offers the sensor nodes the capability of work-on-demand with zero standby power. Fabricated in standard 0.18-¿m complementary metal-oxide semiconductor technology, the ASIC occupies a die area of 2 mm × 2.5 mm. A wireless body sensor network sensor-node prototype using this ASIC only consumes < 10-nA current under the passive standby mode, and < 10 ¿A under the active standby mode, when supplied by a 3-V battery.

  11. A Batteryless Sensor ASIC for Implantable Bio-Impedance Applications.

    PubMed

    Rodriguez, Saul; Ollmar, Stig; Waqar, Muhammad; Rusu, Ana

    2016-06-01

    The measurement of the biological tissue's electrical impedance is an active research field that has attracted a lot of attention during the last decades. Bio-impedances are closely related to a large variety of physiological conditions; therefore, they are useful for diagnosis and monitoring in many medical applications. Measuring living tissues, however, is a challenging task that poses countless technical and practical problems, in particular if the tissues need to be measured under the skin. This paper presents a bio-impedance sensor ASIC targeting a battery-free, miniature size, implantable device, which performs accurate 4-point complex impedance extraction in the frequency range from 2 kHz to 2 MHz. The ASIC is fabricated in 150 nm CMOS, has a size of 1.22 mm × 1.22 mm and consumes 165 μA from a 1.8 V power supply. The ASIC is embedded in a prototype which communicates with, and is powered by an external reader device through inductive coupling. The prototype is validated by measuring the impedances of different combinations of discrete components, measuring the electrochemical impedance of physiological solution, and performing ex vivo measurements on animal organs. The proposed ASIC is able to extract complex impedances with around 1 Ω resolution; therefore enabling accurate wireless tissue measurements.

  12. Applications of ASICs to Avionics (Applications des ASICs dans les Equipements Avioniques)

    DTIC Science & Technology

    1992-02-01

    NORTH:ATLANTIC TREATY ORGANIZATION Published February 199 Best Availjable CopyI ~ adAa~bl~roiBc Best Available Copy AGARD-AG-329 - ADVISORY GROUP FOR...Atlantic Treaty Organization Organisation du TraitW de I’Atlantique Nord The Mission of AGARD According to its Charter, the mission of AGARD is to bring...des equipements militaires et avioniques en particulier reposent sur le silicium des ASICs. JM. Brice iUi Contents pawe Preface/Priface iii Reference

  13. Test and verification of a reactor protection system application-specific integrated circuit

    SciTech Connect

    Battle, R.E.; Turner, G.W.; Vandermolen, R.I.; Vitalbo, C.; Naser, J.

    1997-03-01

    Application-specific integrated circuits (ASICs) were utilized in the design of nuclear plant safety systems because they have certain advantages over software-based systems and analog-based systems. An advantage they have over software-based systems is that an ASIC design can be simple enough to not include branch statements and also can be thoroughly tested. A circuit card on which an ASIC is mounted can be configured to replace various versions of older analog equipment with fewer design types required. The approach to design and testing of ASICs for safety system applications is discussed in this paper. Included are discussions of the ASIC architecture, how it is structured to assist testing, and of the functional and enhanced circuit testing.

  14. Development of a CdTe pixel detector with a window comparator ASIC for high energy X-ray applications

    NASA Astrophysics Data System (ADS)

    Hirono, T.; Toyokawa, H.; Furukawa, Y.; Honma, T.; Ikeda, H.; Kawase, M.; Koganezawa, T.; Ohata, T.; Sato, M.; Sato, G.; Takagaki, M.; Takahashi, T.; Watanabe, S.

    2011-09-01

    We have developed a photon-counting-type CdTe pixel detector (SP8-01). SP8-01 was designed as a prototype of a high-energy X-ray imaging detector for experiments using synchrotron radiation. SP8-01 has a CdTe sensor of 500 μm thickness, which has an absorption efficiency of almost 100% up to 50 keV and 45% even at 100 keV. A full-custom application specific integrated circuit (ASIC) was designed as a readout circuit of SP8-01, which is equipped with a window-type discriminator. The upper discriminator realizes a low-background measurement, because X-ray beams from the monochromator contain higher-order components beside the fundamental X-rays in general. ASIC chips were fabricated with a TSMC 0.25 μm CMOS process, and CdTe sensors were bump-bonded to the ASIC chips by a gold-stud bonding technique. Beam tests were performed at SPring-8. SP8-01 detected X-rays up to 120 keV. The capability of SP8-01 as an imaging detector for high-energy X-ray synchrotron radiation was evaluated with its performance characteristics.

  15. SODR Memory Control Buffer Control ASIC

    NASA Technical Reports Server (NTRS)

    Hodson, Robert F.

    1994-01-01

    The Spacecraft Optical Disk Recorder (SODR) is a state of the art mass storage system for future NASA missions requiring high transmission rates and a large capacity storage system. This report covers the design and development of an SODR memory buffer control applications specific integrated circuit (ASIC). The memory buffer control ASIC has two primary functions: (1) buffering data to prevent loss of data during disk access times, (2) converting data formats from a high performance parallel interface format to a small computer systems interface format. Ten 144 p in, 50 MHz CMOS ASIC's were designed, fabricated and tested to implement the memory buffer control function.

  16. Application-specific integrated circuit design for a typical pressurized water reactor pressure channel trip

    SciTech Connect

    Battle, R.E.; Manges, W.W.; Emery, M.S.; Vendermolen, R.I.; Bhatt, S.

    1994-03-01

    This article discusses the use of application-specific integrated circuits (ASICs) in nuclear plant safety systems. ASICs have certain advantages over software-based systems because they can be simple enough to be thoroughly tested, and they can be tailored to replace existing equipment. An architecture to replace a pressurized water reactor pressure channel trip is presented. Methods of implementing digital algorithms are also discussed.

  17. ASIC For Complex Fixed-Point Arithmetic

    NASA Technical Reports Server (NTRS)

    Petilli, Stephen G.; Grimm, Michael J.; Olson, Erlend M.

    1995-01-01

    Application-specific integrated circuit (ASIC) performs 24-bit, fixed-point arithmetic operations on arrays of complex-valued input data. High-performance, wide-band arithmetic logic unit (ALU) designed for use in computing fast Fourier transforms (FFTs) and for performing ditigal filtering functions. Other applications include general computations involved in analysis of spectra and digital signal processing.

  18. Structured Application-Specific Integrated Circuit (ASIC) Study

    DTIC Science & Technology

    2008-06-01

    including foreign nationals. Copies may be obtained from the Defense Technical Information Center (DTIC) (http://www.dtic.mil). AFRL-RY-WP-TR-2008...scientific and technical information exchange and its publication does not constitute the Government’s approval or disapproval of its ideas or findings...No. 0704-0188 The public reporting burden for this collection of information is estimated to average 1 hour per response, including the time for

  19. An Energy efficient application specific integrated circuit for electrocardiogram feature detection and its potential for ambulatory cardiovascular disease detection.

    PubMed

    Jain, Sanjeev Kumar; Bhaumik, Basabi

    2016-03-01

    A novel algorithm based on forward search is developed for real-time electrocardiogram (ECG) signal processing and implemented in application specific integrated circuit (ASIC) for QRS complex related cardiovascular disease diagnosis. The authors have evaluated their algorithm using MIT-BIH database and achieve sensitivity of 99.86% and specificity of 99.93% for QRS complex peak detection. In this Letter, Physionet PTB diagnostic ECG database is used for QRS complex related disease detection. An ASIC for cardiovascular disease detection is fabricated using 130-nm CMOS high-speed process technology. The area of the ASIC is 0.5 mm(2). The power dissipation is 1.73 μW at the operating frequency of 1 kHz with a supply voltage of 0.6 V. The output from the ASIC is fed to their Android application that generates diagnostic report and can be sent to a cardiologist through email. Their ASIC result shows average failed detection rate of 0.16% for six leads data of 290 patients in PTB diagnostic ECG database. They also have implemented a low-leakage version of their ASIC. The ASIC dissipates only 45 pJ with a supply voltage of 0.9 V. Their proposed ASIC is most suitable for energy efficient telemetry cardiovascular disease detection system.

  20. Command Interface ASIC - Analog Interface ASIC Chip Set

    NASA Technical Reports Server (NTRS)

    Ruiz, Baldes; Jaffe, Burton; Burke, Gary; Lung, Gerald; Pixler, Gregory; Plummer, Joe; Katanyoutanant,, Sunant; Whitaker, William

    2003-01-01

    A command interface application-specific integrated circuit (ASIC) and an analog interface ASIC have been developed as a chip set for remote actuation and monitoring of a collection of switches, which can be used to control generic loads, pyrotechnic devices, and valves in a high-radiation environment. The command interface ASIC (CIA) can be used alone or in combination with the analog interface ASIC (AIA). Designed primarily for incorporation into spacecraft control systems, they are also suitable for use in high-radiation terrestrial environments (e.g., in nuclear power plants and facilities that process radioactive materials). The primary role of the CIA within a spacecraft or other power system is to provide a reconfigurable means of regulating the power bus, actuating all valves, firing all pyrotechnic devices, and controlling the switching of power to all switchable loads. The CIA is a mixed-signal (analog and digital) ASIC that includes an embedded microcontroller with supporting fault-tolerant switch control and monitoring circuitry that is capable of connecting to a redundant set of interintegrated circuit (I(sup 2)C) buses. Commands and telemetry requests are communicated to the CIA. Adherence to the I(sup 2)C bus standard helps to reduce development costs by facilitating the use of previously developed, commercially available components. The AIA is a mixed-signal ASIC that includes the analog circuitry needed to connect the CIA to a custom higher powered version of the I(sup 2)C bus. The higher-powered version is designed to enable operation with bus cables longer than those contemplated in the I(sup 2)C standard. If there are multiple higher-power I(sup 2)C-like buses, then there must an AIA between the CIA and each such bus. The AIA includes two identical interface blocks: one for the side-A I(sup 2)C clock and data buses and the other for the side B buses. All the AIAs on each side are powered from a common power converter module (PCM). Sides A and B

  1. An introduction to future truly wearable medical devices--from application to ASIC.

    PubMed

    Casson, Alexander J; Logesparan, Lojini; Rodriguez-Villegas, Esther

    2010-01-01

    This talk will provide an introduction to the "Towards future truly wearable medical devices: from application to ASIC" mini-symposium. For user comfort and acceptance long term physiological sensors must be discrete, comfortable and easy to use. These requirements place stringent limits on all aspects of the system design: from the overall application aim, to power generation issues, to low power electronic design techniques. For successful devices design issues in all of these areas must be solved simultaneously. The work here presents an overview and introduction to these topics.

  2. STiC — a mixed mode silicon photomultiplier readout ASIC for time-of-flight applications

    NASA Astrophysics Data System (ADS)

    Harion, T.; Briggl, K.; Chen, H.; Fischer, P.; Gil, A.; Kiworra, V.; Ritzert, M.; Schultz-Coulon, H.-C.; Shen, W.; Stankova, V.

    2014-02-01

    STiC is an application specific integrated circuit (ASIC) for the readout of silicon photomultipliers. The chip has been designed to provide a very high timing resolution for time-of-flight applications in medical imaging and particle physics. It is dedicated in particular to the EndoToFPET-US project, which is developing an endoscopic PET detector combined with ultrasound imaging for early pancreas and prostate cancer detection. This PET system aims to provide a spatial resolution of 1 mm and a time-of-flight resolution of 200 ps FWHM. The analog frontend of STiC can use either a differential or single ended connection to the SiPM. The time and energy information of the detector signal is encoded into two time stamps. A special linearized time-over-threshold method is used to obtain a linear relation between the signal charge and the measured signal width, improving the energy resolution. The trigger signals are digitized by an integrated TDC module with a resolution of less than 20 ps. The TDC data is stored in an internal memory and transfered over a 160 MBit/s serial link using 8/10 bit encoding. First coincidence measurements using a 3.1 × 3.1 × 15 mm3 LYSO crystal and a S10362-33-50 Hamamtsu MPPC show a coincidence time resolution of less than 285 ps. We present details on the chip design as well as first characterization measurements.

  3. Petiroc and Citiroc: front-end ASICs for SiPM read-out and ToF applications

    NASA Astrophysics Data System (ADS)

    Fleury, J.; Callier, S.; de La Taille, C.; Seguin, N.; Thienpont, D.; Dulucq, F.; Ahmad, S.; Martin, G.

    2014-01-01

    Petiroc and Citiroc are the two latest ASIC from Weeroc dedicated to SiPM read-out. Petiroc is a 16-channel front-end ASIC designed to readout silicon photomultipliers (SiPMs) for particle time-of-flight measurement applications. It combines a very fast and low-jitter trigger with an accurate charge measurement. Citiroc is a 32-channel front-end ASIC designed to readout silicon photo-multipliers (SiPM). It allows triggering down to 1/3 pe and provides the charge measurement with a good noise rejection. Moreover, Citiroc outputs the 32-channel triggers with a high accuracy (100 ps). Each channel of both ASICs combines a trigger path with an accurate charge measurement path. An adjustment of the SiPM high voltage is possible using a channel-by-channel input DAC. That allows a fine SiPM gain and dark noise adjustment at the system level to correct for the non-uniformity of SiPMs. Timing measurement down to 16 ps RMS jitter for Petiroc and 100 ps RMS for Citiroc is possible along with 1% linearity energy measurement up to 2500 pe. The power consumption is around 3.5 mW/channel for Petiroc and 3 mW/channel for Citiroc, excluding ASICs outing buffer.

  4. Performance of FBK SiPMs coupled to PETA3 read-out ASIC for PET application

    NASA Astrophysics Data System (ADS)

    Piemonte, Claudio; Gola, Alberto; Tarolli, Alessandro; Fisher, Peter; Ritzert, Michael; Schulz, Volkmar; Solf, Torsten

    2013-08-01

    In this paper we show the energy and timing resolution performances of FBK SiPMs coupled to the PETA3 ASIC for PET application. We developed a measurement set-up to characterize single SiPMs coupled to scintillator exploiting the detector stack developed within the HYPERImage project. In this way we are able to characterize the combined SiPM/ASIC performance with the same signal chain (from the sensor to the ASIC board) used in the PET system. We show that using two scintillator detectors, composed of a 3 × 3 × 5mm3 LYSO crystal coupled to a 3 × 3mm2 SiPM, an intra-stack CRT of about 200 ps FWHM can be obtained.

  5. Wireless ultra-wide-band transmission prototype ASICs for low-power space and radiation applications

    NASA Astrophysics Data System (ADS)

    Gabrielli, A.; Crepaldi, M.; Demarchi, D.; Motto Ros, P.; Villani, G.

    2014-11-01

    The paper describes the design and the fabrication of a microelectronic circuit composed of a sensor, an oscillator, a modulator, a transmitter and an antenna. The chip embeds a custom radiation sensor, provided by the silicon foundry that has fabricated the prototypes, but in principle the entire system can read a general sensor, as long as a proper interface circuit is used. The natural application for this circuit is radiation monitoring but the low-power budget extends the applications to space where wireless readout circuits can be applied to any type of sensors, even if not radiation sensitive devices.

  6. Multichannel readout ASIC design flow for high energy physics and cosmic rays experiments

    NASA Astrophysics Data System (ADS)

    Voronin, A.; Malankin, E.

    2016-02-01

    In the large-scale high energy physics and astrophysics experiments multi-channel readout application specific integrated circuits (ASICs) are widely used. The ASICs for such experiments are complicated systems, which usually include both analog and digital building blocks. The complexity and large number of channels in such ASICs require the proper methodological approach to their design. The paper represents the mixed-signal design flow of the ASICs for high energy physics and cosmic rays experiments. This flow was successfully embedded to the development of the read-out ASIC prototype for the muon chambers of the CBM experiment. The approach was approved in UMC CMOS MMRF 180 nm process. The design flow enable to analyse the mixed-signal system operation on the different levels: functional, behavioural, schematic and post layout including parasitic elements. The proposed design flow allows reducing the simulation period and eliminating the functionality mismatches on the very early stage of the design.

  7. A 2D 4×4 Channel Readout ASIC for Pixelated CdTe Detectors for Medical Imaging Applications

    PubMed Central

    Macias-Montero, Jose-Gabriel; Sarraj, Maher; Chmeissani, Mokhtar; Martínez, Ricardo; Puigdengoles, Carles

    2015-01-01

    We present a 16-channel readout integrated circuit (ROIC) with nanosecond-resolution time to digital converter (TDC) for pixelated Cadmium Telluride (CdTe) gamma-ray detectors. The 4 × 4 pixel array ROIC is the proof of concept of the 10 × 10 pixel array readout ASIC for positron-emission tomography (PET) scanner, positron-emission mammography (PEM) scanner, and Compton gamma camera. The electronics of each individual pixel integrates an analog front-end with switchable gain, an analog to digital converter (ADC), configuration registers, and a 4-state digital controller. For every detected photon, the pixel electronics provides the energy deposited in the detector with 10-bit resolution, and a fast trigger signal for time stamp. The ASIC contains the 16-pixel matrix electronics, a digital controller, five global voltage references, a TDC, a temperature sensor, and a band-gap based current reference. The ASIC has been fabricated with TSMC 0.25 μm mixed-signal CMOS technology and occupies an area of 5.3 mm × 6.8 mm. The TDC shows a resolution of 95.5 ps, a precision of 600 ps at full width half maximum (FWHM), and a power consumption of 130 μW. In acquisition mode, the total power consumption of every pixel is 200 μW. An equivalent noise charge (ENC) of 160 e−RMS at maximum gain and negative polarity conditions has been measured at room temperature. PMID:26744545

  8. A 2D 4×4 Channel Readout ASIC for Pixelated CdTe Detectors for Medical Imaging Applications.

    PubMed

    Macias-Montero, Jose-Gabriel; Sarraj, Maher; Chmeissani, Mokhtar; Martínez, Ricardo; Puigdengoles, Carles

    2015-10-01

    We present a 16-channel readout integrated circuit (ROIC) with nanosecond-resolution time to digital converter (TDC) for pixelated Cadmium Telluride (CdTe) gamma-ray detectors. The 4 × 4 pixel array ROIC is the proof of concept of the 10 × 10 pixel array readout ASIC for positron-emission tomography (PET) scanner, positron-emission mammography (PEM) scanner, and Compton gamma camera. The electronics of each individual pixel integrates an analog front-end with switchable gain, an analog to digital converter (ADC), configuration registers, and a 4-state digital controller. For every detected photon, the pixel electronics provides the energy deposited in the detector with 10-bit resolution, and a fast trigger signal for time stamp. The ASIC contains the 16-pixel matrix electronics, a digital controller, five global voltage references, a TDC, a temperature sensor, and a band-gap based current reference. The ASIC has been fabricated with TSMC 0.25 μm mixed-signal CMOS technology and occupies an area of 5.3 mm × 6.8 mm. The TDC shows a resolution of 95.5 ps, a precision of 600 ps at full width half maximum (FWHM), and a power consumption of 130 μW. In acquisition mode, the total power consumption of every pixel is 200 μW. An equivalent noise charge (ENC) of 160 e(-)RMS at maximum gain and negative polarity conditions has been measured at room temperature.

  9. Thermal Radiometer Signal Processing Using Radiation Hard CMOS Application Specific Integrated Circuits for Use in Harsh Planetary Environments

    NASA Technical Reports Server (NTRS)

    Quilligan, G.; DuMonthier, J.; Aslam, S.; Lakew, B.; Kleyner, I.; Katz, R.

    2015-01-01

    Thermal radiometers such as proposed for the Europa Clipper flyby mission require low noise signal processing for thermal imaging with immunity to Total Ionizing Dose (TID) and Single Event Latchup (SEL). Described is a second generation Multi- Channel Digitizer (MCD2G) Application Specific Integrated Circuit (ASIC) that accurately digitizes up to 40 thermopile pixels with greater than 50 Mrad (Si) immunity TID and 174 MeV-sq cm/mg SEL. The MCD2G ASIC uses Radiation Hardened By Design (RHBD) techniques with a 180 nm CMOS process node.

  10. Thermal Radiometer Signal Processing using Radiation Hard CMOS Application Specific Integrated Circuits for use in Harsh Planetary Environments

    NASA Astrophysics Data System (ADS)

    Quilligan, G.; DuMonthier, J.; Aslam, S.; Lakew, B.; Kleyner, I.; Katz, R.

    2015-10-01

    Thermal radiometers such as proposed for the Europa Clipper flyby mission [1] require low noise signal processing for thermal imaging with immunity to Total Ionizing Dose (TID) and Single Event Latchup (SEL). Described is a second generation Multi- Channel Digitizer (MCD2G) Application Specific Integrated Circuit (ASIC) that accurately digitizes up to 40 thermopile pixels with greater than 50 Mrad (Si) immunity TID and 174 MeV-cm2/mg SEL. The MCD2G ASIC uses Radiation Hardened By Design (RHBD) techniques with a 180 nm CMOS process node.

  11. Front-end ASICs for high-energy astrophysics in space

    NASA Astrophysics Data System (ADS)

    Gevin, O.; Limousin, O.; Meuris, A.

    2016-07-01

    In most of embedded imaging systems for space applications, high granularity and increasing size of focal planes justify an almost systematic use of integrated circuits. . To fulfill challenging requirements for excellent spatial and energy resolution, integrated circuits must fit the sensors perfectly and interface the system such a way to optimize simultaneously noise, geometry and architecture. Moreover, very low power consumption and radiation tolerance are mandatory to envision a use onboard a payload in space. Consequently, being part of an optimized detection system for space, the integrated circuit is specifically designed for each application and becomes an Application Specific Integrated Circuits (ASIC). The paper focuses on mixed analog and digital signal ASICs for spectro-imaging systems in the keVMeV energy band. The first part of the paper summarizes the main advantages conferred by the use of front-end ASICs for highenergy astrophysics instruments in space mission. Space qualification of ASICs requires the chip to be radiation hard. The paper will shortly describe some of the typical hardening techniques and give some guidelines that an ASIC designer should follow to choose the most efficient technology for his project. The first task of the front-end electronics is to convert the charge coming from the detector into a voltage. For most of the Silicon detectors (CCD, DEPFET, SDD) this is conversion happens in the detector itself. For other sensor materials, charge preamplifiers operate the conversion. The paper shortly describes the different key parameters of charge preamplifiers and the binding parameters for the design. Filtering is generally mandatory in order to increase the signal to noise ratio or to reduce the duration of the signal. After a brief review on the main noise sources, the paper reviews noise-filtering techniques that are commonly used in Integrated circuits designs. The way sensors and ASICs are interconnected together plays a

  12. ASIC-enabled High Resolution Optical Time Domain Reflectometer

    NASA Astrophysics Data System (ADS)

    Skendzic, Sandra

    Fiber optics has become the preferred technology in communication systems because of what it has to offer: high data transmission rates, immunity to electromagnetic interference, and lightweight, flexible cables. An optical time domain reflectometer (OTDR) provides a convenient method of locating and diagnosing faults (e.g. break in a fiber) along a fiber that can obstruct crucial optical pathways. Both the ability to resolve the precise location of the fault and distinguish between two discrete, closely spaced faults are figures of merit. This thesis presents an implementation of a high resolution OTDR through the use of a compact and programmable ASIC (application specific integrated circuit). The integration of many essential OTDR functions on a single chip is advantageous over existing commercial instruments because it enables small, lightweight packaging, and offers low power and cost efficiency. Furthermore, its compactness presents the option of placing multiple ASICs in parallel, which can conceivably ease the characterization of densely populated fiber optic networks. The OTDR ASIC consists of a tunable clock, pattern generator, precise timer, electrical receiver, and signal sampling circuit. During OTDR operation, the chip generates narrow electrical pulse, which can then be converted to optical format when coupled with an external laser diode driver. The ASIC also works with an external photodetector to measure the timing and amplitude of optical reflections in a fiber. It has a 1 cm sampling resolution, which allows for a 2 cm spatial resolution. While this OTDR ASIC has been previously demonstrated for multimode fiber fault diagnostics, this thesis focuses on extending its functionality to single mode fiber. To validate this novel approach to OTDR, this thesis is divided into five chapters: (1) introduction, (2) implementation, (3), performance of ASIC-based OTDR, (4) exploration in optical pre-amplification with a semiconductor optical amplifier, and

  13. Monolithical integration of polymer-based microfluidic structures on application-specific integrated circuits

    NASA Astrophysics Data System (ADS)

    Chemnitz, Steffen; Schafer, Heiko; Schumacher, Stephanie; Koziy, Volodymyr; Fischer, Alexander; Meixner, Alfred J.; Ehrhardt, Dietmar; Bohm, Markus

    2003-04-01

    In this paper, a concept for a monolithically integrated chemical lab on microchip is presented. It contains an ASIC (Application Specific Integrated Circuit), an interface to the polymer based microfluidic layer and a Pyrex glass cap. The top metal layer of the ASIC is etched off and replaced by a double layer metallization, more suitable to microfluidic and electrophoresis systems. The metallization consists of an approximately 50 nm gold layer and a 10 nm chromium layer, acting as adhesion promoter. A necessary prerequisite is a planarized ASIC topography. SU-8 is used to serve as microfluidic structure because of its excellent aspect ratio. This polymer layer contains reservoirs, channels, mixers and electrokinetic micro pumps. The typical channel cross section is 10μm"10μm. First experimental results on a microfluidic pump, consisting of pairs of interdigitated electrodes on the bottom of the channel and without any moving parts show a flow of up to 50μm per second for low AC-voltages in the range of 5 V for aqueous fluids. The microfluidic system is irreversibly sealed with a 150μm thick Pyrex glass plate bonded to the SU-8-layer, supported by oxygen plasma. Due to capillary forces and surfaces properties of the walls the system is self-priming. The technologies for the fabrication of the microfluidic system and the preparation of the interface between the lab layer and the ASIC are presented.

  14. A project plans to develop two ASICs for CCD controller

    NASA Astrophysics Data System (ADS)

    Song, Qian; Wei, Mingzhi; Sun, Quan; Zhang, Yuheng

    2016-07-01

    Astronomical instrumentation, in many cases, especially the large field of view application while huge mosaic CCD or CMOS camera is needed, requires the camera electronics to be much more compact and of much smaller the size than the controller used to be. Making the major parts of CCD driving circuits into an ASIC or ASICs can greatly bring down the controller's volume, weight and power consumption and make it easier to control the crosstalk brought up by the long length of the cables that connect the CCD output ports and the signal processing electronics, and, therefore, is the most desirable approach to build the large mosaic CCD camera. A project endeavors to make two ASICs, one to achieve CCD signal processing and another to provide the clock drives and bias voltages, is introduced. The first round of design of the two ASICs has been completed and the devices have just been manufactured. Up to now the test of one of the two, the signal processing ASIC, was partially done and the linearity has reached the requirement of the design.

  15. ASIC for SDD-Based X-Ray Spectrometers

    SciTech Connect

    G De Geronimo; P Rehak; K Ackley; G Carini; W Chen; J Fried; J Keister; S Li; Z Li; et al.

    2011-12-31

    We present an application-specific integrated circuit (ASIC) for high-resolution x-ray spectrometers (XRS). The ASIC reads out signals from pixelated silicon drift detectors (SDDs). The pixel does not have an integrated field effect transistor (FET); rather, readout is accomplished by wire-bonding the anodes to the inputs of the ASIC. The ASIC dissipates 32 mW, and offers 16 channels of low-noise charge amplification, high-order shaping with baseline stabilization, discrimination, a novel pile-up rejector, and peak detection with an analog memory. The readout is sparse and based on custom low-power tristatable low-voltage differential signaling (LPT-LVDS). A unit of 64 SDD pixels, read out by four ASICs, covers an area of 12.8 cm{sup 2} and dissipates with the sensor biased about 15 mW/cm{sup 2}. As a tile-based system, the 64-pixel units cover a large detection area. Our preliminary measurements at -44 C show a FWHM of 145 eV at the 5.9 keV peak of a {sup 55}Fe source, and less than 80 eV on a test-pulse line at 200 eV.

  16. ASIC for SDD-Based X-ray Spectrometers

    SciTech Connect

    De Geronimo, G.; Fried, J.; Rehak, P.; Ackley, K.; Carini, G.; Chen, W.; Keister, J.; Li, S.; Li, Z.; Pinelli, D.A.; Siddons, D.P.; Vernon, E.; Gaskin, J.A.; Ramsey, B.D.; Tyson, T.A.

    2010-06-16

    We present an application-specific integrated circuit (ASIC) for high-resolution x-ray spectrometers (XRS). The ASIC reads out signals from pixelated silicon drift detectors (SDDs). The pixel does not have an integrated field effect transistor (FET); rather, readout is accomplished by wire-bonding the anodes to the inputs of the ASIC. The ASIC dissipates 32 mW, and offers 16 channels of low-noise charge amplification, high-order shaping with baseline stabilization, discrimination, a novel pile-up rejector, and peak detection with an analog memory. The readout is sparse and based on custom low-power tristatable low-voltage differential signaling (LPT-LVDS). A unit of 64 SDD pixels, read out by four ASICs, covers an area of 12.8 cm{sup 2} and dissipates with the sensor biased about 15 mW/cm{sup 2}. As a tile-based system, the 64-pixel units cover a large detection area. Our preliminary measurements at -44 C show a FWHM of 145 eV at the 5.9 keV peak of a {sup 55}Fe source, and less than 80 eV on a test-pulse line at 200 eV.

  17. A Radiation Hardened by Design CMOS ASIC for Thermopile Readouts

    NASA Technical Reports Server (NTRS)

    Quilligan, G.; Aslam, S.; DuMonthier, J.

    2012-01-01

    A radiation hardened by design (RHBD) mixed-signal application specific integrated circuit (ASIC) has been designed for a thermopile readout for operation in the harsh Jovian orbital environment. The multi-channel digitizer (MCD) ASIC includes 18 low noise amplifier channels which have tunable gain/filtering coefficients, a 16-bit sigma-delta analog-digital converter (SDADC) and an on-chip controller. The 18 channels, SDADC and controller were designed to operate with immunity to single event latchup (SEL) and to at least 10 Mrad total ionizing dose (TID). The ASIC also contains a radiation tolerant 16-bit 20 MHz Nyquist ADC for general purpose instrumentation digitizer needs. The ASIC is currently undergoing fabrication in a commercial 180 nm CMOS process. Although this ASIC was designed specifically for the harsh radiation environment of the NASA led JEO mission it is suitable for integration into instrumentation payloads 011 the ESA JUICE mission where the radiation hardness requirements are slightly less stringent.

  18. Integrated acoustooptic circuits and applications.

    PubMed

    Tsai, C S

    1992-01-01

    The recent development of titanium-indiffusion proton-exchange (TIPE) microlenses and lens arrays has made possible the construction of a variety of single- and multichannel integrated acoustooptic (AO) and acoustooptic-electrooptic (EO) circuits in LiNbO(3) channel-planar waveguides 0.1x1.0x2.0 cm(3) in size. These hybrid AO and AO-EO circuits can be fabricated through compatible and well-established technologies. The most recent realization of ion-milled microlenses and lens arrays together with the recent development of gigahertz AO Bragg modulators and EO Bragg modulator arrays have also paved the way for construction of similar but monolithic AO and AO-EO GaAs/GaAlAs waveguides of comparable size. Both types of integrated AO and AO-EO circuits suggest versatile applications in communications signal processing, and computing. Efficient and simultaneous excitation of the channel waveguide array using an ion-milled planar microlens array has facilitated the demonstration of some of these applications.

  19. Development of a low noise readout ASIC for CZT detectors for gamma-ray spectroscopy applications

    NASA Astrophysics Data System (ADS)

    Luo, J.; Deng, Z.; Wang, G.; Li, H.; Liu, Y.

    2012-08-01

    A multi-channel readout ASIC for pixelated CZT detectors has been developed for gamma-ray spectroscopy applications. Each channel consists of a low noise dual-stage charge sensitive amplifier (CSA), a CR-(RC)4 semi-Gaussian shaper and a class-AB output buffer. The equivalent noise charge (ENC) of input PMOS transistor is optimized for 5 pF input capacitance and 1 μs peaking time using gm/ID design methodology. The gain can be adjusted from 100 mV/fC to 400 mV/fC and the peaking time can be adjusted from 1 μs to 4 μs. A 16-channel chip has been designed and fabricated in 0.35 μm 2P4M CMOS technology. The test results show that the chip works well and fully satisfies the design specifications. The ENC was measured to be 72 e + 26 e/pF at 1 μs peaking time and 86 e + 20 e/pF at 4 μs peaking time. The non-uniformity of the channel gain and ENC was less than ±12% and ±11% respectively for 16 channels in one chip. The chip was also tested with a pixelated CZT detector at room temperature. The measured energy resolution at 59.5 keV photopeak of 241Am and 122 keV photopeak of 57Co were 4.5% FWHM and 2.8% FWHM for the central area pixels, respectively.

  20. An application specific integrated circuit based multi-anode microchannel array readout system

    NASA Technical Reports Server (NTRS)

    Smeins, Larry G.; Stechman, John M.; Cole, Edward H.

    1991-01-01

    Size reduction of two new multi-anode microchannel array (MAMA) readout systems is described. The systems are based on two analog and one digital application specific integrated circuits (ASICs). The new readout systems reduce volume over previous discrete designs by 80 percent while improving electrical performance on virtually every significant parameter. Emphasis is made on the packaging used to achieve the volume reduction. Surface mount technology (SMT) is combined with modular construction for the analog portion of the readout. SMT reliability concerns and the board area impact of MIL SPEC SMT components is addressed. Package selection for the analog ASIC is discussed. Future sytems will require even denser packaging and the volume reduction progression is shown.

  1. Operational Excellence through Schedule Optimization and Production Simulation of Application Specific Integrated Circuits.

    SciTech Connect

    Flory, John Andrew; Padilla, Denise D.; Gauthier, John H.; Zwerneman, April Marie; Miller, Steven P

    2016-05-01

    Upcoming weapon programs require an aggressive increase in Application Specific Integrated Circuit (ASIC) production at Sandia National Laboratories (SNL). SNL has developed unique modeling and optimization tools that have been instrumental in improving ASIC production productivity and efficiency, identifying optimal operational and tactical execution plans under resource constraints, and providing confidence in successful mission execution. With ten products and unprecedented levels of demand, a single set of shared resources, highly variable processes, and the need for external supplier task synchronization, scheduling is an integral part of successful manufacturing. The scheduler uses an iterative multi-objective genetic algorithm and a multi-dimensional performance evaluator. Schedule feasibility is assessed using a discrete event simulation (DES) that incorporates operational uncertainty, variability, and resource availability. The tools provide rapid scenario assessments and responses to variances in the operational environment, and have been used to inform major equipment investments and workforce planning decisions in multiple SNL facilities.

  2. An application specific integrated circuit based multi-anode microchannel array readout system

    NASA Technical Reports Server (NTRS)

    Smeins, Larry G.; Stechman, John M.; Cole, Edward H.

    1991-01-01

    Size reduction of two new multi-anode microchannel array (MAMA) readout systems is described. The systems are based on two analog and one digital application specific integrated circuits (ASICs). The new readout systems reduce volume over previous discrete designs by 80 percent while improving electrical performance on virtually every significant parameter. Emphasis is made on the packaging used to achieve the volume reduction. Surface mount technology (SMT) is combined with modular construction for the analog portion of the readout. SMT reliability concerns and the board area impact of MIL SPEC SMT components is addressed. Package selection for the analog ASIC is discussed. Future sytems will require even denser packaging and the volume reduction progression is shown.

  3. The Pulse Width Modulator ASIC for Deep Space Missions

    NASA Technical Reports Server (NTRS)

    Carr, Gregory A.; Wester, Gene W.; Lam, Barbara; Bennett, Johnny; Franco, Lauro; Woo, Erika

    2004-01-01

    The Jet Propulsion Laboratory has started the development of a Pulse Width Modulator Application Specific Integrated Circuit (PWMA). This development is leveraging the previous development of the Switch Control ASIC (SCA). The purpose of the development is to provide the control for a selected range of power converter topologies and to meet the stringent environmental requirements of deep space missions. The PWMA will include several power control functions that are not normally included on the off-the-shelf components available today. One key functional requirement is the ability to implement an N + K redundant power converter with the ability to control the charging of a battery. Other applications will be the typical point of load isolated and non-isolated power converters. The purpose the development is not only to provide a much needed flight part, but also to accelerate the engineering process by using a standard cell library from previous ASIC developments. Under previous developments with Boeing and Lockheed Martin, JPL has produced three ASICs. Each ASIC has been implemented by using an analog standard cell library. One such development was the SCA, which is design to provide a floating power switch control. The functional verification of this ASIC has been completed and the cells used have been targeted for the new development of the PWMA. The primary function of the PWMA is to provide the control function of a point of load power converter. The design is an isolated 60 W converter with a 33 V output. In architecting the design, several functions were left up to the power converter design in order to make the ASIC more generic. The ASIC can be used for several power converter topologies and power levels. Some additional features have been added to the ASIC to provide the interfaces for multi-phase topologies and battery control functions. An N+K fault tolerant strategy has been implemented in order to provide the battery control functions. The PWMA has

  4. The Pulse Width Modulator ASIC for Deep Space Missions

    NASA Technical Reports Server (NTRS)

    Carr, Gregory A.; Wester, Gene W.; Lam, Barbara; Bennett, Johnny; Franco, Lauro; Woo, Erika

    2004-01-01

    The Jet Propulsion Laboratory has started the development of a Pulse Width Modulator Application Specific Integrated Circuit (PWMA). This development is leveraging the previous development of the Switch Control ASIC (SCA). The purpose of the development is to provide the control for a selected range of power converter topologies and to meet the stringent environmental requirements of deep space missions. The PWMA will include several power control functions that are not normally included on the off-the-shelf components available today. One key functional requirement is the ability to implement an N + K redundant power converter with the ability to control the charging of a battery. Other applications will be the typical point of load isolated and non-isolated power converters. The purpose the development is not only to provide a much needed flight part, but also to accelerate the engineering process by using a standard cell library from previous ASIC developments. Under previous developments with Boeing and Lockheed Martin, JPL has produced three ASICs. Each ASIC has been implemented by using an analog standard cell library. One such development was the SCA, which is design to provide a floating power switch control. The functional verification of this ASIC has been completed and the cells used have been targeted for the new development of the PWMA. The primary function of the PWMA is to provide the control function of a point of load power converter. The design is an isolated 60 W converter with a 33 V output. In architecting the design, several functions were left up to the power converter design in order to make the ASIC more generic. The ASIC can be used for several power converter topologies and power levels. Some additional features have been added to the ASIC to provide the interfaces for multi-phase topologies and battery control functions. An N+K fault tolerant strategy has been implemented in order to provide the battery control functions. The PWMA has

  5. TOFPET2: a high-performance ASIC for time and amplitude measurements of SiPM signals in time-of-flight applications

    NASA Astrophysics Data System (ADS)

    Di Francesco, A.; Bugalho, R.; Oliveira, L.; Pacher, L.; Rivetti, A.; Rolo, M.; Silva, J. C.; Silva, R.; Varela, J.

    2016-03-01

    We present a readout and digitization ASIC featuring low-noise and low-power for time-of flight (TOF) applications using SiPMs. The circuit is designed in standard CMOS 110 nm technology, has 64 independent channels and is optimized for time-of-flight measurement in Positron Emission Tomography (TOF-PET). The input amplifier is a low impedance current conveyor based on a regulated common-gate topology. Each channel has quad-buffered analogue interpolation TDCs (time binning 20 ps) and charge integration ADCs with linear response at full scale (1500 pC). The signal amplitude can also be derived from the measurement of time-over-threshold (ToT). Simulation results show that for a single photo-electron signal with charge 200 (550) fC generated by a SiPM with 320 pF capacitance the circuit has 24 (30) dB SNR, 75(39) ps r.m.s. resolution, and 4(8) mW power consumption. The event rate is 600 kHz per channel, with up to 2 MHz dark counts rejection.

  6. The future of automation for high-volume wafer fabrication and ASIC manufacturing

    NASA Astrophysics Data System (ADS)

    Hughes, Randall A.; Shott, John D.

    1986-12-01

    A framework is given to analyze the future trends in semiconductor manufacturing automation systems, focusing specifically on the needs of ASIC (application-specific integrated circuit) or custom integrated circuit manufacturing. Advances in technologies such as gate arrays and standard cells now make it significantly easier to obtain system cost and performance advantages by integrating nonstandard functions on silicon. ASICs are attractive to U.S. manufacturers because they place a premium on sophisticated design tools, familiarity with customer needs and applications, and fast turn-around fabrication. These are areas where U.S. manufacturers believe they have an advantage and, consequently, will not suffer from the severe price/manufacturing competition encountered in conventional high-volume semiconductor products. Previously, automation was often considered viable only for high-volume manufacturing, but automation becomes a necessity in the new ASIC environment.

  7. Low-cost photovoltaic inverters incorporating application-specific integrated circuits

    SciTech Connect

    O`Sullivan, G.A.; O`Sullivan, J.A.

    1993-10-01

    The positive impact of designing a power conditioner control system for photovoltaic applications with an application-specific integrated circuit (ASIC) as the main control element was demonstrated with detailed computer simulations in Phase I of a two phase Small Business Innovative Research Grant issued by the US Department of Energy. Completion of the design, building and testing of three prototypes using different power semiconductors was successfully accomplished in Phase II. The power rating for the residential utility intertied Sunverters Model 753-4-200 is 5 kW. A stand-alone inverter suitable for operation from a photovoltaic array with or without a battery for energy storage was also developed in this effort. A much needed intermediate power level 50-kW three-phase power conditioner, Sunverter Model 759-4-200, was the third product to evolve from the research and development. All designs take advantage of the ASIC and a complementary microprocessor sampled-data control system. The ASIC-controlled power conditioners provide the high reliability, high efficiency, and low cost needed for photovoltaic applications. They cover the power range from the residential level to utility-sized installations.

  8. Low-cost photovoltaic inverters incorporating application-specific integrated circuits

    NASA Astrophysics Data System (ADS)

    Osullivan, George A.; Osullivan, Joseph A.

    1993-10-01

    The positive impact of designing a power conditioner control system for photovoltaic applications with an application-specific integrated circuit (ASIC) as the main control element was demonstrated with detailed computer simulations in Phase 1 of a two phase Small Business Innovative Research Grant issued by the US Department of Energy. Completion of the design, building and testing of three prototypes using different power semiconductors was successfully accomplished in Phase 2. The power rating for the residential utility intertied Sunverters Model 753-4-200 is 5 kW. A stand-alone inverter suitable for operation from a photovoltaic array with or without a battery for energy storage was also developed in this effort. A much needed intermediate power level 50-kW three-phase power conditioner, Sunverter Model 759-4-200, was the third product to evolve from the research and development. All designs take advantage of the ASIC and a complementary microprocessor sampled-data control system. The ASIC-controlled power conditioners provide the high reliability, high efficiency, and low cost needed for photovoltaic applications. They cover the power range from the residential level to utility-sized installations.

  9. Digital circuits for computer applications: A compilation

    NASA Technical Reports Server (NTRS)

    1972-01-01

    The innovations in this updated series of compilations dealing with electronic technology represent a carefully selected collection of digital circuits which have direct application in computer oriented systems. In general, the circuits have been selected as representative items of each section and have been included on their merits of having universal applications in digital computers and digital data processing systems. As such, they should have wide appeal to the professional engineer and scientist who encounter the fundamentals of digital techniques in their daily activities. The circuits are grouped as digital logic circuits, analog to digital converters, and counters and shift registers.

  10. A CMOS application-specified-integrated-circuit for 40 GHz high-electron-mobility-transistors automatic biasing

    NASA Astrophysics Data System (ADS)

    De Matteis, M.; De Blasi, M.; Vallicelli, E. A.; Zannoni, M.; Gervasi, M.; Bau, A.; Passerini, A.; Baschirotto, A.

    2017-02-01

    This paper presents the design and the experimental results of a CMOS Automatic Control System (ACS) for the biasing of High-Electron-Mobility-Transistors (HEMT). The ACS is the first low-power mixed-signal Application-Specified-Integrated-Circuit (ASIC) able to automatically set and regulate the operating point of an off-chip 6 HEMT Low-Noise-Amplifiers (LNAs), hence it composes a two-chip system (the ACS+LNAs) to be used in the Large Scale Polarization Explorer (LSPE) stratospheric balloon for Cosmic Microwave Background (CMB) signal observation. The hereby presented ACS ASIC provides a reliable instrumentation for gradual and very stable LNAs characterization, switching-on, and operating point (<4 mV accuracy). Moreover, it simplifies the electronic instrumentation needed for biasing the LNAs, since it replaces several off-the-shelf and digital programmable device components. The ASIC prototype has been implemented in a CMOS 0.35 μ m technology (12 mm2 area occupancy). It operates at 4 kHz clock frequency. The power consumption of one-channel ASIC (biasing one LNA) is 3.6 mW, whereas 30 mW are consumed by a single LNA device.

  11. A CMOS application-specified-integrated-circuit for 40 GHz high-electron-mobility-transistors automatic biasing.

    PubMed

    De Matteis, M; De Blasi, M; Vallicelli, E A; Zannoni, M; Gervasi, M; Bau, A; Passerini, A; Baschirotto, A

    2017-02-01

    This paper presents the design and the experimental results of a CMOS Automatic Control System (ACS) for the biasing of High-Electron-Mobility-Transistors (HEMT). The ACS is the first low-power mixed-signal Application-Specified-Integrated-Circuit (ASIC) able to automatically set and regulate the operating point of an off-chip 6 HEMT Low-Noise-Amplifiers (LNAs), hence it composes a two-chip system (the ACS+LNAs) to be used in the Large Scale Polarization Explorer (LSPE) stratospheric balloon for Cosmic Microwave Background (CMB) signal observation. The hereby presented ACS ASIC provides a reliable instrumentation for gradual and very stable LNAs characterization, switching-on, and operating point (<4 mV accuracy). Moreover, it simplifies the electronic instrumentation needed for biasing the LNAs, since it replaces several off-the-shelf and digital programmable device components. The ASIC prototype has been implemented in a CMOS 0.35 μm technology (12 mm(2) area occupancy). It operates at 4 kHz clock frequency. The power consumption of one-channel ASIC (biasing one LNA) is 3.6 mW, whereas 30 mW are consumed by a single LNA device.

  12. CMOS neurostimulation ASIC with 100 channels, scaleable output, and bidirectional radio-frequency telemetry.

    PubMed

    Suaning, G J; Lovell, N H

    2001-02-01

    100-channel neurostimulation circuit comprising a complementary metal oxide semiconductor (CMOS), application-specific integrated circuit (ASIC) has been designed, constructed and tested. The ASIC forms a significant milestone and an integral component of a 100-electrode neurostimulation system being developed by the authors. The system comprises an externally worn transmitter and a body implantable stimulator. The purpose of the system is to communicate both data and power across tissue via radio-frequency (RF) telemetry such that externally programmable, constant current, charge balanced, biphasic stimuli may be delivered to neural tissue at 100 unique sites. An intrinsic reverse telemetry feature of the ASIC has been designed such that information pertaining to the device function, reconstruction of the stimulation voltage waveform, and the measurement of impedance may be obtained through noninvasive means. To compensate for the paucity of data pertaining to the stimulation thresholds necessary in evoking a physiological response, the ASIC has been designed with scaleable current output. The ASIC has been designed primarily as a treatment of degenerative disorders of the retina whereby the 100 channels are to be utilized in the delivery of a pattern of stimuli of varying intensity and or duty cycle to the surviving neural tissue of the retina. However, it is conceivable that other fields of neurostimulation such as cochlear prosthetics and functional electronic stimulation may benefit from the employment of the system.

  13. Development of a low-noise, 4th-order readout ASIC for CdZnTe detectors in gamma spectrometer applications

    NASA Astrophysics Data System (ADS)

    Wang, Jia; Su, Lin; Wei, Xiaomin; Zheng, Ran; Hu, Yann

    2016-09-01

    This paper presents an ASIC readout circuit development, which aims to achieve low noise. In order to compensate the leakage current and improve gain, a dual-stage CSA has been utilized. A 4th-order high-linearity shaper is proposed to obtain a Semi-Gaussian wave and further decrease the noise induced by the leakage current. The ASIC has been designed and fabricated in a standard commercial 2P4M 0.35 μm CMOS process. Die area of one channel is about 1190 μm×147 μm. The input charge range is 1.8 fC. The peaking time can be adjusted from 1 μs to 3 μs. Measured ENC is about 55e- (rms) at input capacitor of 0 F. The gain is 271 mV/fC at the peaking time of 1 μs.

  14. A Low-Power Correlator ASIC for Arrays with Many Antennas

    NASA Technical Reports Server (NTRS)

    D'Addario, Larry R.; Wang, Douglas

    2016-01-01

    We report the design of a new application-specific integrated circuit (ASIC) for use in radio telescope correlators. It supports the construction of correlators for an arbitrarily large number of signals. The ASIC uses an intrinsically low-power architecture along with design techniques and a process that together result in unprecedentedly low power consumption. The design is flexible in that it can support telescopes with almost any number of antennas N. It is intended for use in an "FX" correlator, where a uniform filter bank breaks each signal into separate frequency channels prior to correlation.

  15. Small Microprocessor for ASIC or FPGA Implementation

    NASA Technical Reports Server (NTRS)

    Kleyner, Igor; Katz, Richard; Blair-Smith, Hugh

    2011-01-01

    A small microprocessor, suitable for use in applications in which high reliability is required, was designed to be implemented in either an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA). The design is based on commercial microprocessor architecture, making it possible to use available software development tools and thereby to implement the microprocessor at relatively low cost. The design features enhancements, including trapping during execution of illegal instructions. The internal structure of the design yields relatively high performance, with a significant decrease, relative to other microprocessors that perform the same functions, in the number of microcycles needed to execute macroinstructions. The problem meant to be solved in designing this microprocessor was to provide a modest level of computational capability in a general-purpose processor while adding as little as possible to the power demand, size, and weight of a system into which the microprocessor would be incorporated. As designed, this microprocessor consumes very little power and occupies only a small portion of a typical modern ASIC or FPGA. The microprocessor operates at a rate of about 4 million instructions per second with clock frequency of 20 MHz.

  16. Automated radiation hard ASIC design tool

    NASA Technical Reports Server (NTRS)

    White, Mike; Bartholet, Bill; Baze, Mark

    1993-01-01

    A commercial based, foundry independent, compiler design tool (ChipCrafter) with custom radiation hardened library cells is described. A unique analysis approach allows low hardness risk for Application Specific IC's (ASIC's). Accomplishments, radiation test results, and applications are described.

  17. CNFET-based voltage rectifier circuit for biomedical implantable applications

    NASA Astrophysics Data System (ADS)

    Tu, Yonggen; Qian, Libo; Xia, Yinshui

    2017-02-01

    Carbon nanotube field effect transistor (CNFET) shows lower threshold voltage and smaller leakage current in comparison to its CMOS counterpart. In this paper, two kinds of CNFET-based rectifiers, full-wave rectifiers and voltage doubler rectifiers are presented for biomedical implantable applications. Based on the standard 32 nm CNFET model, the electrical performance of CNFET rectifiers is analyzed and compared. Simulation results show the voltage conversion efficiency (VCE) and power conversion efficiency (PCE) achieve 70.82% and 72.49% for CNFET full-wave rectifiers and 56.60% and 61.17% for CNFET voltage double rectifiers at typical 1.0 V input voltage excitation, which are higher than that of CMOS design. Moreover, considering the controllable property of CNFET threshold voltage, the effect of various design parameters on the electrical performance is investigated. It is observed that the VCE and PCE of CNFET rectifier increase with increasing CNT diameter and number of tubes. The proposed results would provide some guidelines for design and optimization of CNFET-based rectifier circuits. Project supported by the National Natural Science Foundation of China (Nos. 61131001, 61404077, 61571248), the Science and Technology Fund of Zhejiang Province (No. 2015C31090), the Natural Science Foundation of Ningbo (No. 2014A610147), State Key Laboratory of ASIC & System (No. 2015KF006) and the K. C. Wong Magna Fund in Ningbo University.

  18. Dedicated multichannel readout ASIC coupled with single crystal diamond for dosimeter application

    NASA Astrophysics Data System (ADS)

    Fabbri, A.; Falco, M. D.; De Notaristefani, F.; Galasso, M.; Marinelli, M.; Orsolini Cencelli, V.; Tortora, L.; Verona, C.; Verona Rinati, G.

    2013-02-01

    This paper reports on the tests of a low-noise, multi-channel readout integrated circuit used as a readout electronic front-end for a diamond multi-pixel dosimeter. The system is developed for dose distribution measurement in radiotherapy applications. The first 10-channel prototype chip was designed and fabricated in a 0.18 um CMOS process. Every channel includes a charge integrator with a 10 pF capacitor and a double slope A/D converter. The diamond multi-pixel detector, based on CVD synthetic single crystal diamond Schottky diodes, is made by a 3 × 3 sensor matrix. The overall device has been tested under irradiation with 6 MeV radio therapeutic photon beams at the Policlinico ``Tor Vergata'' (PTV) hospital. Measurements show a 20 fA RMS leakage current from the front-end input stage and a negligible dark current from the diamond detector, a stable temporal response and a good linear behaviour as a function of both dose and dose rate. These characteristics were common to each tested channel.

  19. ASIC-based design of NMR system health monitor for mission/safety-critical applications.

    PubMed

    Balasubramanian, P

    2016-01-01

    N-modular redundancy (NMR) is a generic fault tolerance scheme that is widely used in safety-critical circuit/system designs to guarantee the correct operation with enhanced reliability. In passive NMR, at least a majority (N + 1)/2 out of N function modules is expected to operate correctly at any time, where N is odd. Apart from a conventional realization of the NMR system, it would be useful to provide a concurrent indication of the system's health so that an appropriate remedial action may be initiated depending upon an application's safety criticality. In this context, this article presents the novel design of a generic NMR system health monitor which features: (i) early fault warning logic, that is activated upon the production of a conflicting result by even one output of any arbitrary function module, and (ii) error signalling logic, which signals an error when the number of faulty function modules unfortunately attains a majority and the system outputs may no more be reliable. Two sample implementations of NMR systems viz. triple modular redundancy and quintuple modular redundancy with the proposed system health monitoring are presented in this work, with a 4-bit ALU used for the function modules. The simulations are performed using a 32/28 nm CMOS process technology.

  20. An asynchronous data acquisition ASIC with a data-push architecture

    NASA Astrophysics Data System (ADS)

    Mani, S.; Burlingame, E.; Bloom, P.; Glenn, S.; Holbrook, B.; Hopman, P.; Lin, F.; Rojas, S.

    1995-02-01

    We report on a digital circuit for data acquisition that has been developed for high energy physics applications. Its function is to receive asynchronous voltage pulses, time-stamp them individually and transmit them sequentially on an external bus. A 16-channel design has been fabricated as an application specific integrated circuit (ASIC) using the HP 1.2 μm double-metal, single-polysilicon process. Test results made on prototype chips indicate that the circuit performs within specifications for an operating clock frequency of 25 MHz and a working environment temperature of 0°C to 40°C.

  1. A closed-loop MEMS accelerometer with capacitive sensing interface ASIC

    NASA Astrophysics Data System (ADS)

    Liu, Minjie; Chi, Baoyong; Liu, Yunfeng; Dong, Jingxin

    2013-01-01

    A closed-loop MEMS accelerometer with capacitive sensing interface ASIC (application specific integrated circuit) is presented. The parasitic-insensitive switched-capacitor sample-charge architecture is used to implement the capacitive sensing, which is crucial to the case where sensor and interface ASIC are combined in a two-chip approach to implement the closed-loop MEMS accelerometer. Based on the 0.35 µm CMOS sensing interface ASIC, an accelerometer prototype has been implemented, in which force-rebalance with the lag-proportional-integral controller is applied to improve the system stability and frequency response performance, and the testing results indicate the sensitivity of the presented accelerometer is 650 mV/g, the full measurement range ±15 g, the non-linearity 0.098% and the noise floor 23.17 µg/rt-Hz.

  2. Front End Spectroscopy ASIC for Germanium Detectors

    NASA Astrophysics Data System (ADS)

    Wulf, Eric

    the anode and cathode of the device to allow the depth of the interaction within the crystal to be determined. Dr. De Geronimo has developed similar timing circuits for CZT detector ASICs. Furthermore, the timing circuitry of the ASIC is at the very end of the analog section, simplifying and mitigating risks in the redesign. In the first year, we propose to tweak the gain settings and to add timing to the silicon ASIC to match the requirements of a germanium detector. The design specifications of the ASIC will include advice from our collaborators Dr. Boggs from COSI and Dr. Shih from GRIPS. By using a master ASIC designer to integrate his proven front-end and back-end with only minor modifications, we are maximizing the probability of success. NRL has a commercial cross-strip germanium detector with 30 pF of capacitance per strip, including the flex circuit from the detector to the outside of the cryostat. The COSI and GRIPS detectors have a similar capacitance per strip on the outside of their mechanically cooled cryostat. The second year of the program will be devoted to testing the newly fabricated germanium cross-strip ASIC with the NRL germanium detector. At the end of the second year, NASA will have a TRL 5 ASIC for germanium detectors, allowing future missions, including COSI, GRX, and GRIPS, to operate within their thermal and electrical envelopes. At the end of the third year, a detector on COSI will be instrumented with the new ASIC allowing for a TRL 6 demonstration during the following COSI balloon flight.

  3. Very Low-Power Consumption Analog Pulse Processing ASIC for Semiconductor Radiation Detectors

    SciTech Connect

    Wessendorf, K.O.; Lund, J.C.; Brunett, B.A.; Laguna, G.R.; Clements, J.W.

    1999-08-23

    We describe a very-low power consumption circuit for processing the pulses from a semiconductor radiation detector. The circuit was designed for use with a cadmium zinc telluride (CZT) detector for unattended monitoring of stored nuclear materials. The device is intended to be battery powered and operate at low duty-cycles over a long period of time. This system will provide adequate performance for medium resolution gamma-ray pulse-height spectroscopy applications. The circuit incorporates the functions of a charge sensitive preamplifier, shaping amplifier, and peak sample and hold circuit. An application specific integrated circuit (ASIC) version of the design has been designed, built and tested. With the exception of the input field effect transistor (FET), the circuit is constructed using bipolar components. In this paper the design philosophy and measured performance characteristics of the circuit are described.

  4. A High-Performance Deformable Mirror with Integrated Driver ASIC for Space Based Active Optics

    NASA Astrophysics Data System (ADS)

    Shelton, Chris

    Direct imaging of exoplanets is key to fully understanding these systems through spectroscopy and astrometry. The primary impediment to direct imaging of exoplanets is the extremely high brightness ratio between the planet and its parent star. Direct imaging requires a technique for contrast suppression, which include coronagraphs, and nulling interferometers. Deformable mirrors (DMs) are essential to both of these techniques. With space missions in mind, Microscale is developing a novel DM with direct integration of DM and its electronic control functions in a single small envelope. The Application Specific Integrated Circuit (ASIC) is key to the shrinking of the electronic control functions to a size compatible with direct integration with the DM. Through a NASA SBIR project, Microscale, with JPL oversight, has successfully demonstrated a unique deformable mirror (DM) driver ASIC prototype based on an ultra-low power switch architecture. Microscale calls this the Switch-Mode ASIC, or SM-ASIC, and has characterized it for a key set of performance parameters, and has tested its operation with a variety of actuator loads, such as piezo stack and unimorph, and over a wide temperature range. These tests show the SM-ASIC's capability of supporting active optics in correcting aberrations of a telescope in space. Microscale has also developed DMs to go with the SM-ASIC driver. The latest DM version produced uses small piezo stack elements in an 8x8 array, bonded to a novel silicon facesheet structure fabricated monolithically into a polished mirror on one side and mechanical linkage posts that connect to the piezoelectric stack actuators on the other. In this Supporting Technology proposal we propose to further develop the ASIC-DM and have assembled a very capable team to do so. It will be led by JPL, which has considerable expertise with DMs used in Adaptive Optics systems, with high-contrast imaging systems for exoplanet missions, and with designing DM driver

  5. SPIDR, a general-purpose readout system for pixel ASICs

    NASA Astrophysics Data System (ADS)

    van der Heijden, B.; Visser, J.; van Beuzekom, M.; Boterenbrood, H.; Kulis, S.; Munneke, B.; Schreuder, F.

    2017-02-01

    The SPIDR (Speedy PIxel Detector Readout) system is a flexible general-purpose readout platform that can be easily adapted to test and characterize new and existing detector readout ASICs. It is originally designed for the readout of pixel ASICs from the Medipix/Timepix family, but other types of ASICs or front-end circuits can be read out as well. The SPIDR system consists of an FPGA board with memory and various communication interfaces, FPGA firmware, CPU subsystem and an API library on the PC . The FPGA firmware can be adapted to read out other ASICs by re-using IP blocks. The available IP blocks include a UDP packet builder, 1 and 10 Gigabit Ethernet MAC's and a "soft core" CPU . Currently the firmware is targeted at the Xilinx VC707 development board and at a custom board called Compact-SPIDR . The firmware can easily be ported to other Xilinx 7 series and ultra scale FPGAs. The gap between an ASIC and the data acquisition back-end is bridged by the SPIDR system. Using the high pin count VITA 57 FPGA Mezzanine Card (FMC) connector only a simple chip carrier PCB is required. A 1 and a 10 Gigabit Ethernet interface handle the connection to the back-end. These can be used simultaneously for high-speed data and configuration over separate channels. In addition to the FMC connector, configurable inputs and outputs are available for synchronization with other detectors. A high resolution (≈ 27 ps bin size) Time to Digital converter is provided for time stamping events in the detector. The SPIDR system is frequently used as readout for the Medipix3 and Timepix3 ASICs. Using the 10 Gigabit Ethernet interface it is possible to read out a single chip at full bandwidth or up to 12 chips at a reduced rate. Another recent application is the test-bed for the VeloPix ASIC, which is developed for the Vertex Detector of the LHCb experiment. In this case the SPIDR system processes the 20 Gbps scrambled data stream from the VeloPix and distributes it over four 10 Gigabit

  6. Microwave integrated circuits for space applications

    NASA Technical Reports Server (NTRS)

    Leonard, Regis F.; Romanofsky, Robert R.

    1991-01-01

    Monolithic microwave integrated circuits (MMIC), which incorporate all the elements of a microwave circuit on a single semiconductor substrate, offer the potential for drastic reductions in circuit weight and volume and increased reliability, all of which make many new concepts in electronic circuitry for space applications feasible, including phased array antennas. NASA has undertaken an extensive program aimed at development of MMICs for space applications. The first such circuits targeted for development were an extension of work in hybrid (discrete component) technology in support of the Advanced Communication Technology Satellite (ACTS). It focused on power amplifiers, receivers, and switches at ACTS frequencies. More recent work, however, focused on frequencies appropriate for other NASA programs and emphasizes advanced materials in an effort to enhance efficiency, power handling capability, and frequency of operation or noise figure to meet the requirements of space systems.

  7. Microwave integrated circuits for space applications

    NASA Astrophysics Data System (ADS)

    Leonard, Regis F.; Romanofsky, Robert R.

    Monolithic microwave integrated circuits (MMIC), which incorporate all the elements of a microwave circuit on a single semiconductor substrate, offer the potential for drastic reductions in circuit weight and volume and increased reliability, all of which make many new concepts in electronic circuitry for space applications feasible, including phased array antennas. NASA has undertaken an extensive program aimed at development of MMICs for space applications. The first such circuits targeted for development were an extension of work in hybrid (discrete component) technology in support of the Advanced Communication Technology Satellite (ACTS). It focused on power amplifiers, receivers, and switches at ACTS frequencies. More recent work, however, focused on frequencies appropriate for other NASA programs and emphasizes advanced materials in an effort to enhance efficiency, power handling capability, and frequency of operation or noise figure to meet the requirements of space systems.

  8. ASICs Approach for the Implementation of a Symmetric Triangular Fuzzy Coprocessor and Its Application to Adaptive Filtering

    NASA Technical Reports Server (NTRS)

    Starks, Scott; Abdel-Hafeez, Saleh; Usevitch, Bryan

    1997-01-01

    This paper discusses the implementation of a fuzzy logic system using an ASICs design approach. The approach is based upon combining the inherent advantages of symmetric triangular membership functions and fuzzy singleton sets to obtain a novel structure for fuzzy logic system application development. The resulting structure utilizes a fuzzy static RAM to store the rule-base and the end-points of the triangular membership functions. This provides advantages over other approaches in which all sampled values of membership functions for all universes must be stored. The fuzzy coprocessor structure implements the fuzzification and defuzzification processes through a two-stage parallel pipeline architecture which is capable of executing complex fuzzy computations in less than 0.55us with an accuracy of more than 95%, thus making it suitable for a wide range of applications. Using the approach presented in this paper, a fuzzy logic rule-base can be directly downloaded via a host processor to an onchip rule-base memory with a size of 64 words. The fuzzy coprocessor's design supports up to 49 rules for seven fuzzy membership functions associated with each of the chip's two input variables. This feature allows designers to create fuzzy logic systems without the need for additional on-board memory. Finally, the paper reports on simulation studies that were conducted for several adaptive filter applications using the least mean squared adaptive algorithm for adjusting the knowledge rule-base.

  9. Applications of hydrocyclones in Bayer circuit

    SciTech Connect

    Patnaik, S.K.; Brahma, R.; Das, P.

    1996-10-01

    Due to its operational simplicity, effectiveness, low space requirement and maintenance cost, hydrocyclones of different sizes and materials of construction are progressively finding more and more applications in the Bayer circuit for producing alumina from bauxite. In alumina refining processes, hydrocyclones are most effectively used in the areas like closed circuit grinding, sand separation, sand washing, removal of residual solid from spent liquor and second stage filtrate to enhance plant productivity, and classification of hydrate particles for product and seed granulometry control.

  10. Advancing therapeutic applications of synthetic gene circuits.

    PubMed

    Higashikuni, Yasutomi; Chen, William Cw; Lu, Timothy K

    2017-10-01

    Synthetic biology aims to introduce new sense-and-respond capabilities into living cells, which would enable novel therapeutic strategies. The development of regulatory elements, molecular computing devices, and effector screening technologies has enabled researchers to design synthetic gene circuits in many organisms, including mammalian cells. Engineered gene networks, such as closed-loop circuits or Boolean logic gate circuits, can be used to program cells to perform specific functions with spatiotemporal control and restoration of homeostasis in response to the extracellular environment and intracellular signaling. In addition, genetically modified microbes can be designed as local delivery of therapeutic molecules. In this review, we will discuss recent advances in therapeutic applications of synthetic gene circuits, as well as challenges and future opportunities for biomedicine. Copyright © 2017. Published by Elsevier Ltd.

  11. ASICs and cardiovascular homeostasis.

    PubMed

    Abboud, François M; Benson, Christopher J

    2015-07-01

    In this review we address primarily the role of ASICs in determining sensory signals from arterial baroreceptors, peripheral chemoreceptors, and cardiopulmonary and somatic afferents. Alterations in these sensory signals during acute cardiovascular stresses result in changes in sympathetic and parasympathetic activities that restore cardiovascular homeostasis. In pathological states, however, chronic dysfunctions of these afferents result in serious sympatho-vagal imbalances with significant increases in mortality and morbidity. We identified a role for ASIC2 in the mechano-sensitivity of aortic baroreceptors and of ASIC3 in the pH sensitivity of carotid bodies. In spontaneously hypertensive rats, we reported decreased expression of ASIC2 in nodose ganglia neurons and overexpression of ASIC3 in carotid bodies. This reciprocal expression of ASIC2 and ASIC3 results in reciprocal changes in sensory sensitivity of baro- and chemoreceptors and a consequential synergistic exaggeration sympathetic nerve activity. A similar reciprocal sensory dysautonomia prevails in heart failure and increases the risk of mortality. There is also evidence that ASIC heteromers in skeletal muscle afferents contribute significantly to the exercise pressor reflex. In cardiac muscle afferents of the dorsal root ganglia, they contribute to nociception and to the detrimental sympathetic activation during ischemia. Finally, we report that an inhibitory influence of ASIC2-mediated baroreceptor activity suppresses the sympatho-excitatory reflexes of the chemoreceptors and skeletal muscle afferents, as well as the ASIC1a-mediated excitation of central neurons during fear, threat, or panic. The translational potential of activation of ASIC2 in cardiovascular disease states may be a beneficial sympatho-inhibition and parasympathetic activation. This article is part of the Special Issue entitled 'Acid-Sensing Ion Channels in the Nervous System'.

  12. ASIC design and data communications for the Boston retinal prosthesis.

    PubMed

    Shire, Douglas B; Ellersick, William; Kelly, Shawn K; Doyle, Patrick; Priplata, Attila; Drohan, William; Mendoza, Oscar; Gingerich, Marcus; McKee, Bruce; Wyatt, John L; Rizzo, Joseph F

    2012-01-01

    We report on the design and testing of a custom application-specific integrated circuit (ASIC) that has been developed as a key component of the Boston retinal prosthesis. This device has been designed for patients who are blind due to age-related macular degeneration or retinitis pigmentosa. Key safety and communication features of the low-power ASIC are described, as are the highly configurable neural stimulation current waveforms that are delivered to its greater than 256 output electrodes. The ASIC was created using an 0.18 micron Si fabrication process utilizing standard 1.8 volt CMOS transistors as well as 20 volt lightly doped drain FETs. The communication system receives frequency-shift keyed inputs at 6.78 MHz from an implanted secondary coil, and transmits data back to the control unit through a lower-bandwidth channel that employs load-shift keying. The design's safety is ensured by on-board electrode voltage monitoring, stimulus charge limits, error checking of data transmitted to the implant, and comprehensive self-test and performance monitoring features. Each stimulus cycle is initiated by a transmitted word with a full 32-bit error check code. Taken together, these features allow researchers to safely and wirelessly tailor retinal stimulation and vision recovery for each patient.

  13. ASIC for High Rate 3D Position Sensitive Detectors

    SciTech Connect

    Vernon, E.; De Geronimo, G.; Ackley, K.; Fried, J.; He, Z.; Herman, C.; Zhang, F.

    2010-06-16

    We report on the development of an application specific integrated circuit (ASIC) for 3D position sensitive detectors (3D PSD). The ASIC is designed to operate with pixelated wide bandgap sensors like Cadmium-Zinc-Telluride (CZT), Mercuric Iodide (Hgl2) and Thallium Bromide (TIBr). It measures the amplitudes and timings associated with an ionizing event on 128 anodes, the anode grid, and the cathode. Each channel provides low-noise charge amplification, high-order shaping with peaking time adjustable from 250 ns to 12 {micro}s, gain adjustable to 20 mV/fC or 120 mV/fC (for a dynamic range of 3.2 MeV and 530 keV in CZT), amplitude discrimination with 5-bit trimming, and positive and negative peak and timing detections. The readout can be full or sparse, based on a flag and single- or multi-cycle token passing. All channels, triggered channels only, or triggered with neighbors can be read out thus increasing the rate capability of the system to more than 10 kcps. The ASIC dissipates 330 mW which corresponds to about 2.5 mW per channel.

  14. Front-end ASIC for pixilated wide bandgap detectors

    NASA Astrophysics Data System (ADS)

    Vernon, Emerson; de Geronimo, Gianluigi; Fried, Jack; Herman, Cedric; Zhang, Feng; He, Zhong

    2009-08-01

    A CMOS application specific integrated circuit (ASIC) was developed for 3D Position Sensitive Detectors (PSD). The preamplifiers were optimized for pixellated Cadmium-Zinc-Telluride (CZT) Mercuric-Iodide (HgI2) and Thallium Bromide (TlBr) sensors. The ASIC responds to an ionizing event in the sensor by measuring both amplitude and timing in the pertinent anode and cathode channels. Each channel is sensitive to events and transients of positive or negative polarity and performs low-noise charge amplification, high-order shaping, peak and timing detection along with analog storage and multiplexing. Three methodologies are implemented to perform timing measurement in the cathode channel. Multiple sparse modes are available for the readout of channel data. The ASIC integrates 130 channels in an area of 12 x 9 mm2 and dissipates ~330 mW. With a CZT detector connected and biased, an electronic resolution of ~200 e- rms for charges up to 100 fC was measured. Spectral data from the University of Michigan revealed a cumulative single-pixel resolution of ~0.55 % FWHM at 662 KeV.

  15. DS Sentry: an acquisition ASIC for smart, micro-power sensing applications

    NASA Astrophysics Data System (ADS)

    Liobe, John; Fiscella, Mark; Moule, Eric; Balon, Mark; Bocko, Mark; Ignjatovic, Zeljko

    2011-06-01

    Unattended ground monitoring that combines seismic and acoustic information can be a highly valuable tool in intelligence gathering; however there are several prerequisites for this approach to be viable. The first is high sensitivity as well as the ability to discriminate real threats from noise and other spurious signals. By combining ground sensing with acoustic and image monitoring this requirement may be achieved. Moreover, the DS Sentry®provides innate spurious signal rejection by the "active-filtering" technique employed as well as embedding some basic statistical analysis. Another primary requirement is spatial and temporal coverage. The ideal is uninterrupted, long-term monitoring of an area. Therefore, sensors should be densely deployed and consume very little power. Furthermore, sensors must be inexpensive and easily deployed to allow dense placements in critical areas. The ADVIS DS Sentry®, which is a fully-custom integrated circuit that enables smart, micro-power monitoring of dynamic signals, is the foundation of the proposed system. The core premise behind this technology is the use of an ultra-low power front-end for active monitoring of dynamic signals in conjunction with a highresolution, Σ Δ-based analog-to-digital converter, which utilizes a novel noise rejection technique and is only employed when a potential threat has been detected. The DS Sentry® can be integrated with seismic accelerometers and microphones and user-programmed to continuously monitor for signals with specific signatures such as impacts, footsteps, excavation noise, vehicle-induced ground vibrations, or speech, while consuming only microwatts of power. This will enable up to several years of continuous monitoring on a single small battery while concurrently mitigating false threats.

  16. Development of n+-in-p planar pixel quadsensor flip-chipped with FE-I4 readout ASICs

    NASA Astrophysics Data System (ADS)

    Unno, Y.; Kamada, S.; Yamamura, K.; Yamamoto, H.; Hanagaki, K.; Hori, R.; Ikegami, Y.; Nakamura, K.; Takubo, Y.; Takashima, R.; Tojo, J.; Kono, T.; Nagai, R.; Saito, S.; Sugibayashi, K.; Hirose, M.; Jinnouchi, O.; Sato, S.; Sawai, H.; Hara, K.; Sato, Kz.; Sato, Kj.; Iwabuchi, S.; Suzuki, J.

    2017-01-01

    We have developed flip-chip modules applicable to the pixel detector for the HL-LHC. New radiation-tolerant n+-in-p planar pixel sensors of a size of four FE-I4 application-specific integrated circuits (ASICs) are laid out in a 6-in wafer. Variation in readout connection for the pixels at the boundary of ASICs is implemented in the design of quadsensors. Bump bonding technology is developed for four ASICs onto one quadsensor. Both sensors and ASICs are thinned to 150 μm before bump bonding, and are held flat with vacuum chucks. Using lead-free SnAg solder bumps, we encounter deficiency with large areas of disconnected bumps after thermal stress treatment, including irradiation. Surface oxidation of the solder bumps is identified as a critical source of this deficiency after bump bonding trials, using SnAg bumps with solder flux, indium bumps, and SnAg bumps with a newly-introduced hydrogen-reflow process. With hydrogen-reflow, we establish flux-less bump bonding technology with SnAg bumps, appropriate for mass production of the flip-chip modules with thin sensors and thin ASICs.

  17. 20 CFR 416.1485 - Application of circuit court law.

    Code of Federal Regulations, 2010 CFR

    2010-04-01

    ... 20 Employees' Benefits 2 2010-04-01 2010-04-01 false Application of circuit court law. 416.1485... Determinations and Decisions Court Remand Cases § 416.1485 Application of circuit court law. The procedures which follow apply to administrative determinations or decisions on claims involving the application of circuit...

  18. 20 CFR 404.985 - Application of circuit court law.

    Code of Federal Regulations, 2010 CFR

    2010-04-01

    ... 20 Employees' Benefits 2 2010-04-01 2010-04-01 false Application of circuit court law. 404.985... and Decisions Court Remand Cases § 404.985 Application of circuit court law. The procedures which follow apply to administrative determinations or decisions on claims involving the application of circuit...

  19. 20 CFR 404.985 - Application of circuit court law.

    Code of Federal Regulations, 2012 CFR

    2012-04-01

    ... 20 Employees' Benefits 2 2012-04-01 2012-04-01 false Application of circuit court law. 404.985... and Decisions Court Remand Cases § 404.985 Application of circuit court law. The procedures which follow apply to administrative determinations or decisions on claims involving the application of circuit...

  20. 20 CFR 416.1485 - Application of circuit court law.

    Code of Federal Regulations, 2013 CFR

    2013-04-01

    ... 20 Employees' Benefits 2 2013-04-01 2013-04-01 false Application of circuit court law. 416.1485... Determinations and Decisions Court Remand Cases § 416.1485 Application of circuit court law. The procedures which follow apply to administrative determinations or decisions on claims involving the application of circuit...

  1. 20 CFR 404.985 - Application of circuit court law.

    Code of Federal Regulations, 2013 CFR

    2013-04-01

    ... 20 Employees' Benefits 2 2013-04-01 2013-04-01 false Application of circuit court law. 404.985... and Decisions Court Remand Cases § 404.985 Application of circuit court law. The procedures which follow apply to administrative determinations or decisions on claims involving the application of circuit...

  2. 20 CFR 404.985 - Application of circuit court law.

    Code of Federal Regulations, 2011 CFR

    2011-04-01

    ... 20 Employees' Benefits 2 2011-04-01 2011-04-01 false Application of circuit court law. 404.985... and Decisions Court Remand Cases § 404.985 Application of circuit court law. The procedures which follow apply to administrative determinations or decisions on claims involving the application of circuit...

  3. 20 CFR 404.985 - Application of circuit court law.

    Code of Federal Regulations, 2014 CFR

    2014-04-01

    ... 20 Employees' Benefits 2 2014-04-01 2014-04-01 false Application of circuit court law. 404.985... and Decisions Court Remand Cases § 404.985 Application of circuit court law. The procedures which follow apply to administrative determinations or decisions on claims involving the application of circuit...

  4. 20 CFR 416.1485 - Application of circuit court law.

    Code of Federal Regulations, 2014 CFR

    2014-04-01

    ... 20 Employees' Benefits 2 2014-04-01 2014-04-01 false Application of circuit court law. 416.1485... Determinations and Decisions Court Remand Cases § 416.1485 Application of circuit court law. The procedures which follow apply to administrative determinations or decisions on claims involving the application of circuit...

  5. 20 CFR 416.1485 - Application of circuit court law.

    Code of Federal Regulations, 2012 CFR

    2012-04-01

    ... 20 Employees' Benefits 2 2012-04-01 2012-04-01 false Application of circuit court law. 416.1485... Determinations and Decisions Court Remand Cases § 416.1485 Application of circuit court law. The procedures which follow apply to administrative determinations or decisions on claims involving the application of circuit...

  6. A DES ASIC Suitable for Network Encryption at 10 Gbps and Beyond

    SciTech Connect

    Gass, Karl; Pierson, Lyndon G.; Robertson, Perry J.; Wilcox, D. Craig; Witzke, Edward L.

    1999-04-30

    The Sandia National Laboratories (SNL) Data Encryption Standard (DES) Application Specific Integrated Circuit (ASIC) is the fastest known implementation of the DES algorithm as defined in the Federal Information Processing Standards (FIPS) Publication 46-2. DES is used for protecting data by cryptographic means. The SNL DES ASIC, over 10 times faster than other currently available DES chips, is a high-speed, filly pipelined implementation offering encryption, decryption, unique key input, or algorithm bypassing on each clock cycle. Operating beyond 105 MHz on 64 bit words, this device is capable of data throughputs greater than 6.7 Billion bits per second (tester limited). Simulations predict proper operation up to 9.28 Billion bits per second. In low frequency, low data rate applications, the ASIC consumes less that one milliwatt of power. The device has features for passing control signals synchronized to throughput data. Three SNL DES ASICS may be easily cascaded to provide the much greater security of triple-key, triple-DES.

  7. A Framework for Robust Multivariable Optimization of Integrated Circuits in Space Applications

    NASA Technical Reports Server (NTRS)

    DuMonthier, Jeffrey; Suarez, George

    2013-01-01

    Application Specific Integrated Circuit (ASIC) design for space applications involves multiple challenges of maximizing performance, minimizing power and ensuring reliable operation in extreme environments. This is a complex multidimensional optimization problem which must be solved early in the development cycle of a system due to the time required for testing and qualification severely limiting opportunities to modify and iterate. Manual design techniques which generally involve simulation at one or a small number of corners with a very limited set of simultaneously variable parameters in order to make the problem tractable are inefficient and not guaranteed to achieve the best possible results within the performance envelope defined by the process and environmental requirements. What is required is a means to automate design parameter variation, allow the designer to specify operational constraints and performance goals, and to analyze the results in a way which facilitates identifying the tradeoffs defining the performance envelope over the full set of process and environmental corner cases. The system developed by the Mixed Signal ASIC Group (MSAG) at the Goddard Space Flight Center is implemented as framework of software modules, templates and function libraries. It integrates CAD tools and a mathematical computing environment, and can be customized for new circuit designs with only a modest amount of effort as most common tasks are already encapsulated. Customization is required for simulation test benches to determine performance metrics and for cost function computation. Templates provide a starting point for both while toolbox functions minimize the code required. Once a test bench has been coded to optimize a particular circuit, it is also used to verify the final design. The combination of test bench and cost function can then serve as a template for similar circuits or be re-used to migrate the design to different processes by re-running it with the

  8. Compensated current injection circuit, theory and applications

    NASA Astrophysics Data System (ADS)

    Fontana, Giorgio

    2003-03-01

    This article presents a detailed description, analysis and example of the practical application of a wide frequency band voltage-to-current converter. The converter is characterized by a combination of positive and negative feedback loops. This feature allows compensation for parasitic impedance connected in parallel with the useful load, which in turn keeps an excitation current flowing through the useful load independent of its impedance. The simplicity of the circuit and its good electrical properties are additional advantages of the scheme.

  9. Diagnostic applications of nucleic acid circuits.

    PubMed

    Jung, Cheulhee; Ellington, Andrew D

    2014-06-17

    CONSPECTUS: While the field of DNA computing and molecular programming was engendered in large measure as a curiosity-driven exercise, it has taken on increasing importance for analytical applications. This is in large measure because of the modularity of DNA circuitry, which can serve as a programmable intermediate between inputs and outputs. These qualities may make nucleic acid circuits useful for making decisions relevant to diagnostic applications. This is especially true given that nucleic acid circuits can potentially directly interact with and be triggered by diagnostic nucleic acids and other analytes. Chemists are, by and large, unaware of many of these advances, and this Account provides a means of touching on what might seem to be an arcane field. We begin by explaining nucleic acid amplification reactions that can lead to signal amplification, such as catalytic hairpin assembly (CHA) and the hybridization chain reaction (HCR). In these circuits, a single-stranded input acts on kinetically trapped substrates via exposed toeholds and strand exchange reactions, refolding the substrates and allowing them to interact with one another. As multiple duplexes (CHA) or concatemers of increasing length (HCR) are generated, there are opportunities to couple these outputs to different analytical modalities, including transduction to fluorescent, electrochemical, and colorimetric signals. Because both amplification and transduction are at their root dependent on the programmability of Waston-Crick base pairing, nucleic acid circuits can be much more readily tuned and adapted to new applications than can many other biomolecular amplifiers. As an example, robust methods for real-time monitoring of isothermal amplification reactions have been developed recently. Beyond amplification, nucleic acid circuits can include logic gates and thresholding components that allow them to be used for analysis and decision making. Scalable and complex DNA circuits (seesaw gates

  10. ASPIC and CABAC: two ASICs to readout and pilot CCD

    NASA Astrophysics Data System (ADS)

    Antilogus, P.; Bailly, P.; Barrillon, P.; Dhellot, M.; El berni, A.; Jeglot, J.; Juramy-Gilles, C.; Lebbolo, H.; Martin, D.; Moniez, M.; Vallerand, P.

    2017-03-01

    For several years, a group of engineers and physicists from LAL and LPNHE have been working on the design of two front end ASICs dedicated to Charge Couple Devices (CCD). ASPIC (Analogue Signal Processing Integrated Circuit), designed in AMS CMOS 0.35 μm 5V technology, is meant to readout and process the analog signals of CCDs. CABAC (Clocks And Biases ASIC for CCDs), designed in AMS CMOS 0.35 μm 50V technology, produces the clocks and biases needed by the CCDs to work at their full potential. This paper presents the performances of the final versions of these two ASICs.

  11. Radio-Frequency Electronics, Circuits and Applications

    NASA Astrophysics Data System (ADS)

    Hagen, Jon B.

    This accessible and comprehensive book provides an introduction to the basic concepts and key circuits of radio frequency systems, covering fundamental principles which apply to all radio devices, from wireless data transceivers on semiconductor chips to high-power broadcast transmitters. Topics covered include filters, amplifiers, oscillators, modulators, low-noise amplifiers, phase-locked loops, and transformers. Applications of radio frequency systems are described in such areas as communications, radio and television broadcasting, radar, and radio astronomy. The book contains many exercises, and assumes only a knowledge of elementary electronics and circuit analysis. It will be an ideal textbook for advanced undergraduate and graduate courses in electrical engineering, as well as an invaluable reference for researchers and professional engineers in this area, or for those moving into the field of wireless communications.

  12. Front-end readout ASIC for charged particle counting with the RADEM instrument on the ESA JUICE mission

    NASA Astrophysics Data System (ADS)

    Stein, Timo A.; Pâhlsson, Philip; Meier, Dirk; Hasanbegovic, Amir; Otnes Berge, Hans Kristian; Altan, Mehmet Akif; Ackermann, Jörg; Najafiuchevler, Bahram; Azman, Suleyman; Talebi, Jahanzad; Olsen, Alf; Gheorghe, Codin; Steenari, David; Øya, Petter; Johansen, Tor Magnus; Maehlum, Gunnar

    2016-07-01

    The detector readout for the Radiation-hard Electron Monitor (RADEM) aboard the JUpiter ICy moons Explorer (JUICE) uses a custom-made application-specific integrated circuit (ASIC, model: IDE3466) for the charge signal readout from silicon radiation sensors. RADEM measures the total ionizing dose and dose rate for protons (5 MeV to 250 MeV), electrons (0.3 MeV to 40 MeV) and ions. RADEM has in total three chips of the same design: one chip for the proton and ion detector, one for the electron detector, and one for the directional detector. The ASIC has 36 chargesensitive pre-amplifiers (CSA), 36 counters of 22-bits each, and one analogue output for multiplexing the pulse heights from all channels. The counters count pulses from charged particles in the silicon sensors depending on the charge magnitude and the coincidence trigger pattern from the 36 channels. We have designed the ASIC in 0.35-μm CMOS process and an ASIC wafer lot has been manufactured at AMS. This article presents the ASIC design specifications and design validation results. The preliminary results from tests with bare chips indicate that the design meets the technical requirements.

  13. Ionizing radiation effects on a 64-channel charge measurement ASIC designed in CMOS 0.35 μm technology

    NASA Astrophysics Data System (ADS)

    La Rosa, A.; Marchetto, F.; Pardo, J.; Donetti, M.; Attili, A.; Bourhaleb, F.; Cirio, R.; Garella, M. A.; Giordanengo, S.; Givehchi, N.; Iliescu, S.; Mazza, G.; Pecka, A.; Peroni, C.; Pittà, G.

    2008-08-01

    A 64-channel circuit Application Specific Integrated Circuit (ASIC) for charge measurement has been designed in CMOS 0.35 μm technology and characterized with electrical tests. The ASIC has been conceived to be used as a front-end for dosimetry and beam monitoring detector read-out. For that application, the circuitry is housed at a few centimeters from the irradiated area of the detectors and therefore radiation damages can affect the chip performances. The ASIC has been tested on an X-ray beam. In this paper, the results of the test and an estimate of the expected lifetime of the ASIC in a standard radio-therapeutical treatment environment are presented. An increase of the background current of 2 fA/Gy has been observed at low doses, whilst the gain changes by less than 3% when irradiated up to 15 kGy. Furthermore it has been assessed that, when used as an on-line beam monitor and the annealing effect has been taken into account, the background current increase is ˜440 fA/year.

  14. FRONT-END ASIC FOR HIGH RESOLUTION X-RAY SPECTROMETERS.

    SciTech Connect

    DE GERONIMO,G.; CHEN, W.; FRIED, J.; LI, Z.; PINELLI, D.A.; REHAK, P.; VERNON, E.; GASKIN, J.A.; RAMSEY, B.D.; ANELLI, G.

    2007-10-27

    We present an application specific integrated circuit (ASIC) for high-resolution x-ray spectrometers. The ASIC is designed to read out signals from a pixelated silicon drift detector (SDD). Each hexagonal pixel has an area of 15 mmz and an anode capacitance of less than 100 fF. There is no integrated Field Effect transistor (FET) in the pixel, rather, the readout is done by wirebonding the anodes to the inputs of the ASIC. The ASIC provides 14 channels of low-noise charge amplification, high-order shaping with baseline stabilization, and peak detection with analog memory. The readout is sparse and based on low voltage differential signaling. An interposer provides all the interconnections required to bias and operate the system. The channel dissipates 1.6 mW. The complete 14-pixel unit covers an area of 210 mm{sup 2}, dissipates 12 mW cm{sup -2}, and can be tiled to cover an arbitrarily large detection area. We measured a preliminary resolution of 172 eV at -35 C on the 6 keV peak of a {sup 55}Fe source.

  15. A wireless capsule system with ASIC for monitoring the physiological signals of the human gastrointestinal tract.

    PubMed

    Xu, Fei; Yan, Guozheng; Zhao, Kai; Lu, Li; Gao, Jinyang; Liu, Gang

    2014-12-01

    This paper presents the design of a wireless capsule system for monitoring the physiological signals of the human gastrointestinal (GI) tract. The primary components of the system include a wireless capsule, a portable data recorder, and a workstation. Temperature, pH, and pressure sensors; an RF transceiver; a controlling and processing application specific integrated circuit (ASIC); and batteries were applied in a wireless capsule. Decreasing capsule size, improving sensor precision, and reducing power needs were the primary challenges; these were resolved by employing micro sensors, optimized architecture, and an ASIC design that include power management, clock management, a programmable gain amplifier (PGA), an A/D converter (ADC), and a serial peripheral interface (SPI) communication unit. The ASIC has been fabricated in 0.18- μm CMOS technology with a die area of 5.0 mm × 5.0 mm. The wireless capsule integrating the ASIC controller measures Φ 11 mm × 26 mm. A data recorder and a workstation were developed, and 20 cases of human experiments were conducted in hospitals. Preprocessing in the workstation can significantly improve the quality of the data, and 76 original features were determined by mathematical statistics. Based on the 13 optimal features achieved in the evaluation of the features, the clustering algorithm can identify the patients who lack GI motility with a recognition rate reaching 83.3%.

  16. A Wireless Capsule Endoscope System With Low-Power Controlling and Processing ASIC.

    PubMed

    Xinkai Chen; Xiaoyu Zhang; Linwei Zhang; Xiaowen Li; Nan Qi; Hanjun Jiang; Zhihua Wang

    2009-02-01

    This paper presents the design of a wireless capsule endoscope system. The proposed system is mainly composed of a CMOS image sensor, a RF transceiver and a low-power controlling and processing application specific integrated circuit (ASIC). Several design challenges involving system power reduction, system miniaturization and wireless wake-up method are resolved by employing optimized system architecture, integration of an area and power efficient image compression module, a power management unit (PMU) and a novel wireless wake-up subsystem with zero standby current in the ASIC design. The ASIC has been fabricated in 0.18-mum CMOS technology with a die area of 3.4 mm * 3.3 mm. The digital baseband can work under a power supply down to 0.95 V with a power dissipation of 1.3 mW. The prototype capsule based on the ASIC and a data recorder has been developed. Test result shows that proposed system architecture with local image compression lead to an average of 45% energy reduction for transmitting an image frame.

  17. Burst Mode ASIC-Based Modem

    NASA Technical Reports Server (NTRS)

    1997-01-01

    The NASA Lewis Research Center is sponsoring the Advanced Communication Technology Insertion (ACTION) for Commercial Space Applications program. The goal of the program is to expedite the development of new technology with a clear path towards productization and enhancing the competitiveness of U.S. manufacturers. The industry has made significant investment in developing ASIC-based modem technology for continuous-mode applications and has made investigations into East, reliable acquisition of burst-mode digital communication signals. With rapid advances in analog and digital communications ICs, it is expected that more functions will be integrated onto these parts in the near future. In addition custom ASIC's can also be developed to address the areas not covered by the other IC's. Using the commercial chips and custom ASIC's, lower-cost, compact, reliable, and high-performance modems can be built for demanding satellite communication application. This report outlines a frequency-hop burst modem design based on commercially available chips.

  18. NIRCA ASIC for the readout of focal plane arrays

    NASA Astrophysics Data System (ADS)

    Pâhlsson, Philip; Steenari, David; Øya, Petter; Otnes Berge, Hans Kristian; Meier, Dirk; Olsen, Alf; Hasanbegovic, Amir; Altan, Mehmet A.; Najafiuchevler, Bahram; Talebi, Jahanzad; Azman, Suleyman; Gheorghe, Codin; Ackermann, Jörg; Mæhlum, Gunnar; Johansen, Tor Magnus; Stein, Timo

    2016-05-01

    This work is a continuation of our preliminary tests on NIRCA - the Near Infrared Readout and Controller ASIC [1]. The primary application for NIRCA is future astronomical science and Earth observation missions where NIRCA will be used with mercury cadmium telluride image sensors (HgCdTe, or MCT) [2], [3]. Recently we have completed the ASIC tests in the cryogenic environment down to 77 K. We have verified that NIRCA provides to the readout integrated circuit (ROIC) regulated power, bias voltages, and fully programmable digital sequences with sample control of the analogue to digital converters (ADC). Both analog and digital output from the ROIC can be acquired and image data is 8b/10bencoded and delivered via serial interface. The NIRCA also provides temperature measurement, and monitors several analog and digital input channels. The preliminary work confirms that NIRCA is latch-up immune and able to operate down to 77 K. We have tested the performance of the 12-bit ADC with pre-amplifier to have 10.8 equivalent number of bits (ENOB) at 1.4 Msps and maximum sampling speed at 2 Msps. The 1.8-V and 3.3-V output regulators and the 10-bit DACs show good linearity and work as expected. A programmable sequencer is implemented as a micro-controller with a custom instruction set. Here we describe the special operations of the sequencer with regards to the applications and a novel approach to parallel real-time hardware outputs. The test results of the working prototype ASIC show good functionality and performance from room temperature down to 77 K. The versatility of the chip makes the architecture a possible candidate for other research areas, defense or industrial applications that require analog and digital acquisition, voltage regulation, and digital signal generation.

  19. Fabrication Security and Trust of Domain-Specific ASIC Processors

    DTIC Science & Technology

    2016-10-30

    defense applications are placed on the chart according to their requirements. Besides performance, embedded system developers must also consider design ... embedded in the design . For example, an ASIC processor potentially has a 10-1,000X performance advantage over its FPGA and GPP counterparts, but...Configurability; Programmability; Untrusted Fabrication; ASIC Processor; IP Protection; Obfuscation. I. INTRODUCTION Embedded systems can be

  20. VLSI circuits and systems for microphotonic applications

    NASA Astrophysics Data System (ADS)

    Lachowicz, S.; Rassau, A.; Kim, C.; Lee, S.-M.

    2005-12-01

    This paper describes various VLSI systems for microphotonic applications. The first project investigates an optimum phase design implementing a multi phase Opto-ULSI processor for multi-function capable optical networks. This research is oriented around the initial development of an 8 phase Opto-ULSI processor that implements a Beam Steering (BS) Opto-ULSI processor (OUP) for integrated intelligent photonic system (IIPS), while investigating the optimal phase characteristics and developing compensation for the nonlinearity of liquid crystal. The second part provides an insight into realisation of a novel 3-D configurable chip based on "sea-of-pixels" architecture, which is highly suitable for applications in multimedia systems as well as for computation of coefficients for generation of holograms required in optical switches. The paper explores strategies for implementation of distributed primitives for arithmetic processing. This entails optimisation of basic cells that would allow using these primitives as part of a 3-D "sea-of-pixel" configurable processing array. The concept of 3-D Soft-Chip Technology (SCT) entails integration of "Soft-Processing Circuits" with "Soft-Configurable Circuits", which effectively manipulates hardware primitives through vertical integration of control and data. Thus the notion of 3-D Soft-Chip emerges as a new design paradigm for content-rich multimedia, telecommunication and photonic-based networking system applications. Combined with the effective manipulation of configurable hardware arithmetic primitives, highly efficient and powerful soft configurable processing systems can be realized.

  1. XAMPS Detectors Readout ASIC for LCLS

    SciTech Connect

    Dragone, A; Pratte, J.F.; Rehak, P.; Carini, G.A.; Herbst, R.; O'Connor, P.; Siddons, D.P.; /BNL, NSLS

    2008-12-18

    An ASIC for the readout of signals from X-ray Active Matrix Pixel Sensor (XAMPS) detectors to be used at the Linac Coherent Light Source (LCLS) is presented. The X-ray Pump Probe (XPP) instrument, for which the ASIC has been designed, requires a large input dynamic range on the order of 104 photons at 8 keV with a resolution of half a photon FWHM. Due to the size of the pixel and the length of the readout line, large input capacitance is expected, leading to stringent requirement on the noise optimization. Furthermore, the large number of pixels needed for a good position resolution and the fixed LCLS beam period impose limitations on the time available for the single pixel readout. Considering the periodic nature of the LCLS beam, the ASIC developed for this application is a time-variant system providing low-noise charge integration, filtering and correlated double sampling. In order to cope with the large input dynamic range a charge pump scheme implementing a zero-balance measurement method has been introduced. It provides an on chip 3-bit coarse digital conversion of the integrated charge. The residual charge is sampled using correlated double sampling into analog memory and measured with the required resolution. The first 64 channel prototype of the ASIC has been fabricated in TSMC CMOS 0.25 {micro}m technology. In this paper, the ASIC architecture and performances are presented.

  2. Trigger Data Serializer ASIC chip for the ATLAS New Small Wheel sTGC Detector

    NASA Astrophysics Data System (ADS)

    Meng, Xiangting; Wang, Jinhong; Guan, Liang; Sang, Ziru; Chapman, John; Zhou, Bing; Zhu, Junjie

    2015-04-01

    The small-strip thin-gap chambers (sTGC) will be used as the trigger device for the Phase-I upgrade of the ATLAS new small wheel (nSW) muon detector. An Application-Specific Integrated Circuit (ASIC) chip is needed to collect digital signals from both pad and strip detectors and serialize the outputs to the circuitry located on the rim of the nSW. The large number of input channels (128 differential input channels), short time available to prepare and transmit trigger data (<100 ns), high speed output data rate (4.8 Gbps), harsh radiation environment (about 300 kRad), and low power consumption (<1 W) impose great challenges for the design of this ASIC chip using the IBM 130 nm CMOS process. We will present our design and test results based on the prototype chip we build.

  3. Design of a video capsule endoscopy system with low-power ASIC for monitoring gastrointestinal tract.

    PubMed

    Liu, Gang; Yan, Guozheng; Zhu, Bingquan; Lu, Li

    2016-11-01

    In recent years, wireless capsule endoscopy (WCE) has been a state-of-the-art tool to examine disorders of the human gastrointestinal tract painlessly. However, system miniaturization, enhancement of the image-data transfer rate and power consumption reduction for the capsule are still key challenges. In this paper, a video capsule endoscopy system with a low-power controlling and processing application-specific integrated circuit (ASIC) is designed and fabricated. In the design, these challenges are resolved by employing a microimage sensor, a novel radio frequency transmitter with an on-off keying modulation rate of 20 Mbps, and an ASIC structure that includes a clock management module, a power-efficient image compression module and a power management unit. An ASIC-based prototype capsule, which measures Φ11 mm × 25 mm, has been developed here. Test results show that the designed ASIC consumes much less power than most of the other WCE systems and that its total power consumption per frame is the least. The image compression module can realize high near-lossless compression rate (3.69) and high image quality (46.2 dB). The proposed system supports multi-spectral imaging, including white light imaging and autofluorescence imaging, at a maximum frame rate of 24 fps and with a resolution of 400 × 400. Tests and in vivo trials in pigs have proved the feasibility of the entire system, but further improvements in capsule control and compression performance inside the ASIC are needed in the future.

  4. Synthetic mammalian gene circuits for biomedical applications.

    PubMed

    Ye, Haifeng; Aubel, Dominique; Fussenegger, Martin

    2013-12-01

    Synthetic biology is the science of reassembling cataloged and standardized biological items in a systematic and rational manner to create and engineer functional biological designer devices, systems and organisms with novel and useful, preferably therapeutic functions. Synthetic biology has significantly advanced the design of complex genetic networks that can reprogram metabolic activities in mammalian cells and provide novel therapeutic strategies for future gene-based and cell-based therapies. Synthetic biology-inspired therapeutic strategies provide new opportunities for improving human health in the 21st century. This review covers the most recent synthetic mammalian circuits designed for therapy of diseases such as metabolic disorders, cancer, and immune disorders. We conclude by discussing current challenges and future perspectives for biomedical applications of synthetic mammalian gene networks.

  5. Replication of Space-Shuttle Computers in FPGAs and ASICs

    NASA Technical Reports Server (NTRS)

    Ferguson, Roscoe C.

    2008-01-01

    A document discusses the replication of the functionality of the onboard space-shuttle general-purpose computers (GPCs) in field-programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs). The purpose of the replication effort is to enable utilization of proven space-shuttle flight software and software-development facilities to the extent possible during development of software for flight computers for a new generation of launch vehicles derived from the space shuttles. The replication involves specifying the instruction set of the central processing unit and the input/output processor (IOP) of the space-shuttle GPC in a hardware description language (HDL). The HDL is synthesized to form a "core" processor in an FPGA or, less preferably, in an ASIC. The core processor can be used to create a flight-control card to be inserted into a new avionics computer. The IOP of the GPC as implemented in the core processor could be designed to support data-bus protocols other than that of a multiplexer interface adapter (MIA) used in the space shuttle. Hence, a computer containing the core processor could be tailored to communicate via the space-shuttle GPC bus and/or one or more other buses.

  6. READOUT ASIC FOR 3D POSITION-SENSITIVE DETECTORS.

    SciTech Connect

    DE GERONIMO,G.; VERNON, E.; ACKLEY, K.; DRAGONE, A.; FRIED, J.; OCONNOR, P.; HE, Z.; HERMAN, C.; ZHANG, F.

    2007-10-27

    We describe an application specific integrated circuit (ASIC) for 3D position-sensitive detectors. It was optimized for pixelated CZT sensors, and it measures, corresponding to an ionizing event, the energy and timing of signals from 121 anodes and one cathode. Each channel provides low-noise charge amplification, high-order shaping, along with peak- and timing-detection. The cathode's timing can be measured in three different ways: the first is based on multiple thresholds on the charge amplifier's voltage output; the second uses the threshold crossing of a fast-shaped signal; and the third measures the peak amplitude and timing from a bipolar shaper. With its power of 2 mW per channel the ASIC measures, on a CZT sensor Connected and biased, charges up to 100 fC with an electronic resolution better than 200 e{sup -} rms. Our preliminary spectral measurements applying a simple cathode/mode ratio correction demonstrated a single-pixel resolution of 4.8 keV (0.72 %) at 662 keV, with the electronics and leakage current contributing in total with 2.1 keV.

  7. Development of a multi-sensor CMOS ASIC

    NASA Astrophysics Data System (ADS)

    van der Merwe, D. G.

    2016-02-01

    A multi-sensor application specific integrated circuit has been developed with a number of sensors: capacitive, inductive, magnetic, ambient light, infrared and acceleration. The capacitive sensing is implemented using a unique, patented, charge transfer technique allowing the measurement of very small capacitances while at the same time eliminating the effects of unwanted parasitic capacitances in the measurement circuit. For cost effective implementation the charge transfer measurement circuit has been has been modified, augmented and expanded to not only measure capacitance but also to act as the measurement circuit for all the sensors. Enabling the multi-sensor chip to measure acceleration on a range of MEMs accelerometer chips including a single axis accelerometer, a dual axis xy accelerometer and a z-axis accelerometer, innovative and patent pending techniques have been developed and implemented on standard CMOS. The CMOS ASIC and a MEMs chip will be double bonded in a plastic package offering multi-sensor capability in a small low cost package.

  8. Integrated circuit cell library

    NASA Technical Reports Server (NTRS)

    Whitaker, Sterling R. (Inventor); Miles, Lowell H. (Inventor)

    2005-01-01

    According to the invention, an ASIC cell library for use in creation of custom integrated circuits is disclosed. The ASIC cell library includes some first cells and some second cells. Each of the second cells includes two or more kernel cells. The ASIC cell library is at least 5% comprised of second cells. In various embodiments, the ASIC cell library could be 10% or more, 20% or more, 30% or more, 40% or more, 50% or more, 60% or more, 70% or more, 80% or more, 90% or more, or 95% or more comprised of second cells.

  9. 20 CFR 405.515 - Application of circuit court law.

    Code of Federal Regulations, 2010 CFR

    2010-04-01

    ... 20 Employees' Benefits 2 2010-04-01 2010-04-01 false Application of circuit court law. 405.515 Section 405.515 Employees' Benefits SOCIAL SECURITY ADMINISTRATION ADMINISTRATIVE REVIEW PROCESS FOR ADJUDICATING INITIAL DISABILITY CLAIMS Judicial Review § 405.515 Application of circuit court law. We will...

  10. 20 CFR 405.515 - Application of circuit court law.

    Code of Federal Regulations, 2013 CFR

    2013-04-01

    ... 20 Employees' Benefits 2 2013-04-01 2013-04-01 false Application of circuit court law. 405.515 Section 405.515 Employees' Benefits SOCIAL SECURITY ADMINISTRATION ADMINISTRATIVE REVIEW PROCESS FOR ADJUDICATING INITIAL DISABILITY CLAIMS Judicial Review § 405.515 Application of circuit court law. We will...

  11. 20 CFR 405.515 - Application of circuit court law.

    Code of Federal Regulations, 2011 CFR

    2011-04-01

    ... 20 Employees' Benefits 2 2011-04-01 2011-04-01 false Application of circuit court law. 405.515 Section 405.515 Employees' Benefits SOCIAL SECURITY ADMINISTRATION ADMINISTRATIVE REVIEW PROCESS FOR ADJUDICATING INITIAL DISABILITY CLAIMS Judicial Review § 405.515 Application of circuit court law. We will...

  12. 20 CFR 405.515 - Application of circuit court law.

    Code of Federal Regulations, 2014 CFR

    2014-04-01

    ... 20 Employees' Benefits 2 2014-04-01 2014-04-01 false Application of circuit court law. 405.515 Section 405.515 Employees' Benefits SOCIAL SECURITY ADMINISTRATION ADMINISTRATIVE REVIEW PROCESS FOR ADJUDICATING INITIAL DISABILITY CLAIMS Judicial Review § 405.515 Application of circuit court law. We will...

  13. 20 CFR 405.515 - Application of circuit court law.

    Code of Federal Regulations, 2012 CFR

    2012-04-01

    ... 20 Employees' Benefits 2 2012-04-01 2012-04-01 false Application of circuit court law. 405.515 Section 405.515 Employees' Benefits SOCIAL SECURITY ADMINISTRATION ADMINISTRATIVE REVIEW PROCESS FOR ADJUDICATING INITIAL DISABILITY CLAIMS Judicial Review § 405.515 Application of circuit court law. We will...

  14. Digital matched filter ASIC

    NASA Astrophysics Data System (ADS)

    Magill, D. T.; Edwards, G.

    The architecture of a digital matched filter (DMF) and the selected technology used is described. The characteristics of the DMF ASIC are summarized in tabular form. Three architectures are considered for the implementation of a DMF ASIC. First, there is the conventional trapped delay line architecture which requires a large adder tree. The second architecture is the systolic array DMF which consists of a number of identical stages cascaded together. The third architecture is the bank-of-correlators DMF, in which the reference code is recirculated around through the delay line. Since the objective is to maximize the length of the DMF, the tapped delay line architecture is selected. The tapped delay form is designed to support BPSK, QPSK, and OQPSK chip modulation. Matched filter lengths of up to 256 chips can be supported by cascading 4 ASICs. The DMF is designed as a gate array using an advanced double metal, 1.5 micron CMOS process. The regularity of FIR filter architecture allows the core of the device to be laid out very compactly, resulting in efficient usage of the gate array.

  15. Simultaneous Disruption of Mouse ASIC1a, ASIC2 and ASIC3 Genes Enhances Cutaneous Mechanosensitivity

    PubMed Central

    Kang, Sinyoung; Jang, Jun Ho; Price, Margaret P.; Gautam, Mamta; Benson, Christopher J.; Gong, Huiyu; Welsh, Michael J.; Brennan, Timothy J.

    2012-01-01

    Three observations have suggested that acid-sensing ion channels (ASICs) might be mammalian cutaneous mechanoreceptors; they are structurally related to Caenorhabditis elegans mechanoreceptors, they are localized in specialized cutaneous mechanosensory structures, and mechanical displacement generates an ASIC-dependent depolarization in some neurons. However, previous studies of mice bearing a single disrupted ASIC gene showed only subtle or no alterations in cutaneous mechanosensitivity. Because functional redundancy of ASIC subunits might explain limited phenotypic alterations, we hypothesized that disrupting multiple ASIC genes would markedly impair cutaneous mechanosensation. We found the opposite. In behavioral studies, mice with simultaneous disruptions of ASIC1a, -2 and -3 genes (triple-knockouts, TKOs) showed increased paw withdrawal frequencies when mechanically stimulated with von Frey filaments. Moreover, in single-fiber nerve recordings of cutaneous afferents, mechanical stimulation generated enhanced activity in A-mechanonociceptors of ASIC TKOs compared to wild-type mice. Responses of all other fiber types did not differ between the two genotypes. These data indicate that ASIC subunits influence cutaneous mechanosensitivity. However, it is unlikely that ASICs directly transduce mechanical stimuli. We speculate that physical and/or functional association of ASICs with other components of the mechanosensory transduction apparatus contributes to normal cutaneous mechanosensation. PMID:22506072

  16. Improved On-Chip Measurement of Delay in an FPGA or ASIC

    NASA Technical Reports Server (NTRS)

    Chen, Yuan; Burke, Gary; Sheldon, Douglas

    2007-01-01

    An improved design has been devised for on-chip-circuitry for measuring the delay through a chain of combinational logic elements in a field-programmable gate array (FPGA) or application-specific integrated circuit (ASIC). In the improved design, the delay chain does not include input and output buffers and is not configured as an oscillator. Instead, the delay chain is made part of the signal chain of an on-chip pulse generator. The duration of the pulse is measured on-chip and taken to equal the delay.

  17. pMUT+ASIC integrated platform for wide range ultrasonic imaging

    NASA Astrophysics Data System (ADS)

    Tillak, J.; Saeed, N.; Khazaaleh, S.; Viegas, J.; Yoo, J.

    2017-03-01

    We propose an integrated platform of Aluminum Nitrate (AlN) based Piezoelectric Micromachined Ultrasonic Transducer (pMUT) phased array with Application Specific Integrated Circuit (ASIC) for medical imaging and industrial diagnosis. The ASIC provides wide driving range for frequencies between 100 kHz and 5 MHz and channelscalable, programmable application adaptive transmitting beamformer. The system supports operation in various media, including gasses, liquids and biological tissue. The scan resolution for 5 MHz operation is 68 μm in air. The beamformer covers a test volume from -30° to +30° with a step of 3° and scan depth of 10 cm. The ASIC system features low noise receiver electronics, power saving transmission circuitry, and high-voltage drive of large capacitance transducer (up to 500 pF). Integrated pMUT phased array consists of 4 channels of single-membrane ultrasonic transducer of 400 nm deflection and 20 pF feed-thru capacitance, which produce 15 Pa pressure at 500 μm distance from the surface of the transducers. The active area of the ASIC is (700×1490) μm2, which includes channel scalable TX, 8-channale low noise RX, digital back end with autonomous beamformer and power management unit. The system is battery powered with 3.3V-5V standard supply, representing a truly portable solution for ultrasonic applications. Given the CMOS-compatible fabrication process for the AlN pMUTs, dense, miniaturized arrays are possible. Furthermore the smooth surface of dielectric AlN renders optical quality MEMS surfaces for integration in miniaturized photonic + ultrasound microsystems.

  18. Acid-sensing ion channels (ASICs) in mouse skeletal muscle afferents are heteromers composed of ASIC1a, ASIC2, and ASIC3 subunits

    PubMed Central

    Gautam, Mamta; Benson, Christopher J.

    2013-01-01

    Acid-sensing ion channels (ASICs) are expressed in skeletal muscle afferents, in which they sense extracellular acidosis and other metabolites released during ischemia and exercise. ASICs are formed as homotrimers or heterotrimers of several isoforms (ASIC1a, ASIC1b, ASIC2a, ASIC2b, and ASIC3), with each channel displaying distinct properties. To dissect the ASIC composition in muscle afferents, we used whole-cell patch-clamp recordings to study the properties of acid-evoked currents (amplitude, pH sensitivity, the kinetics of desensitization and recovery from desensitization, and pharmacological modulation) in isolated, labeled mouse muscle afferents from wild-type (C57BL/6J) and specific ASIC−/− mice. We found that ASIC-like currents in wild-type muscle afferents displayed fast desensitization, indicating that they are carried by heteromeric channels. Currents from ASIC1a−/− muscle afferents were less pH-sensitive and displayed faster recovery, currents from ASIC2−/− mice showed diminished potentiation by zinc, and currents from ASIC3−/− mice displayed slower desensitization than those from wild-type mice. Finally, ASIC-like currents were absent from triple-null mice lacking ASIC1a, ASIC2a, and ASIC3. We conclude that ASIC1a, ASIC2a, and ASIC3 heteromers are the principle channels in skeletal muscle afferents. These results will help us understand the role of ASICs in exercise physiology and provide a molecular target for potential drug therapies to treat muscle pain.—Gautam, M., Benson, C. J. Acid-sensing ion channels (ASICs) in mouse skeletal muscle afferents are heteromers composed of ASIC1a, ASIC2, and ASIC3 subunits. PMID:23109675

  19. ASIC design in the KM3NeT detector

    NASA Astrophysics Data System (ADS)

    Gajanana, D.; Gromov, V.; Timmer, P.

    2013-02-01

    In the KM3NeT project [1], Cherenkov light from the muon interactions with transparent matter around the detector, is used to detect neutrinos. Photo multiplier tubes (PMT) used as photon sensor, are housed in a glass sphere (aka Optical Module) to detect single photons from the Cherenkov light. The PMT needs high operational voltage ( ~ 1.5 kV) and is generated by a Cockroft-Walton (CW) multiplier circuit. The electronics required to control the PMT's and collect the signals is integrated in two ASIC's namely: 1) a front-end mixed signal ASIC (PROMiS) for the readout of the PMT and 2) an analog ASIC (CoCo) to generate pulses for charging the CW circuit and to control the feedback of the CW circuit. In this article, we discuss the two integrated circuits and test results of the complete setup. PROMiS amplifies the input charge, converts it to a pulse width and delivers the information via LVDS signals. These LVDS signals carry accurate information on the Time of arrival ( < 2 ns) and Time over Threshold. A PROM block provides unique identification to the chip. The chip communicates with the control electronics via an I2C bus. This unique combination of the ASIC's results in a very cost and power efficient PMT base design.

  20. High performance protection circuit for power electronics applications

    SciTech Connect

    Tudoran, Cristian D. Dădârlat, Dorin N.; Toşa, Nicoleta; Mişan, Ioan

    2015-12-23

    In this paper we present a high performance protection circuit designed for the power electronics applications where the load currents can increase rapidly and exceed the maximum allowed values, like in the case of high frequency induction heating inverters or high frequency plasma generators. The protection circuit is based on a microcontroller and can be adapted for use on single-phase or three-phase power systems. Its versatility comes from the fact that the circuit can communicate with the protected system, having the role of a “sensor” or it can interrupt the power supply for protection, in this case functioning as an external, independent protection circuit.

  1. A Correlation-based Timing Calibration and Diagnostic Technique for Fast Digitizing ASICs

    NASA Astrophysics Data System (ADS)

    Nishimura, Kurtis; Romero-Wolf, Andrés; the Large Area Picosecond Photodetector Collaboration [1

    A general procedure for precision timing calibration of waveform digitizing systems is presented. Application specific integrated circuits (ASICs) implementing this functionality are increasingly used in high-energy physics as replacements for stand-alone time-to-digital and analog-to-digital modules. However, process variations cause such ASICs to have irregularly spaced timing intervals between samples, so careful calibration is required to improve the timing resolution of such systems. The procedure presented here exploits correlations between nearby samples of a sine wave of known frequency to obtain the time difference between them. As only the correlations are used, the procedure can be performed without knowledge of the phase of the input signal, and converges with smaller data samples than other common techniques. It also serves as a valuable diagnostic tool, allowing a fast, visual, qualitative check of gain mismatches between sampling cells and other ADC artifacts. Work is continuing to extend the procedure to fit for timing intervals in the face of such non-idealities. We present both the algorithm and example calibration results from a commercial oscilloscope and the PSEC-3 ASIC. For the latter, we have also applied the calibration to improve timing resolution in the readout of a prototype microchannel plate photomultiplier tube with a stripline anode configuration.

  2. An analogue front-end ASIC prototype designed for PMT signal readout

    NASA Astrophysics Data System (ADS)

    Liu, Jian-Feng; Zhao, Lei; Yu, Li; Liang, Yu; Qin, Jia-Jun; Yang, Yun-Fan; Wu, Wei-Hao; Liu, Shu-Bin; An, Qi

    2016-06-01

    The Water Cherenkov Detector Array (WCDA) is one of the core detectors in the Large High Altitude Air Shower Observatory (LHAASO), and it consists of 3600 photomultiplier tubes (PMTs). Both high resolution time and charge measurement are required over a large dynamic range from 1 photoelectron (P.E.) to 4000 P.E. The prototype of an analogue front-end Application Specific Integrated Circuit (ASIC) fabricated using Global Foundry 0.35 μm CMOS technology is designed to read out the PMT signal in the WCDA. This ASIC employs leading edge discrimination and an (RC)4 shaping structure. Combined with the following Time-to-Digital Converter (TDC) and Analog-to-Digital Converter (ADC), both the arrival time and charge of the PMT signal can be measured. Initial test results indicate that time resolution is better than 350 ps and charge resolution is better than 10% at 1 P.E. and better than 1% with large input signals (300 P.E. to 4000 P.E.). Besides, this ASIC has a good channel-to-channel isolation of more than 84 dB and the temperature dependency of charge measurement is less than 5% in the range 0-50°C. Supported by Knowledge Innovation Program of Chinese Academy of Sciences (KJCX2-YW-N27), National Natural Science Foundation of China (11175174) and CAS Center for Excellence in Particle Physics (CCEPP)

  3. ASIC for Small Angle Neutron Scattering Experiments at the SNS

    NASA Astrophysics Data System (ADS)

    De Geronimo, Gianluigi; Fried, Jack; Smith, Graham C.; Yu, Bo; Vernon, Emerson; Britton, Charles L.; Bryan, William L.; Clonts, Lloyd G.; Frank, Shane S.

    2007-06-01

    We present an ASIC for a 3He gas detector to be used in small angle neutron scattering experiments at the spallation neutron source in oak ridge. The ASIC is composed of 64 channels with low noise charge amplification, filtering, timing and amplitude measurement circuits, where an innovative current-mode peak-detector and digitizer (PDAD) is adopted. The proposed PDAD provides at the same time peak detection and A/D conversion in real time, at low power, and without requiring a clock signal. The channels share an efficient data sparsification and derandomization scheme, a 30-bit 256 deep FIFO, and low voltage differential signaling.

  4. Monolithic readout circuits for RHIC

    SciTech Connect

    O`Connor, P.; Harder, J.

    1991-12-31

    Several CMOS ASICs have been developed for a proposed RHIC experiment. This paper discusses why ASIC implementation was chosen for certain functions, circuit specifications and the design techniques used to meet them, and results of simulations and early prototypes. By working closely together from an early stage in the planning process, in-house ASIC designers and detector and data acquisition experimenters can achieve optimal use of this important technology.

  5. A low-power 12.5 Gbps serial link transmitter ASIC for particle detectors in 65 nm CMOS

    NASA Astrophysics Data System (ADS)

    Feng, Y.; Chen, J.; You, Y.; Tang, Y.; Fan, Q.; Zuo, Z.; Pendyala, P.; Gong, D.; Liu, T.; Ye, J.

    2017-02-01

    This paper presents a 12.5 Gbps serial link transmitter application-specific integrated circuit (ASIC) designed in a 65-nm CMOS technology. The ASIC mainly includes an LC-VCO phase-locked-loop (PLL), a 16:1 serializer and a CML driver. Simulation results show that the PLL achieves a 7-to-14 GHz frequency tuning range and an RMS jitter of 0.4 pS. The serializer has a deterministic jitter of 9 pS and a programmable output swing from 200 mV to 1.0 V. The PLL and the serializer consumes 39.6 mW and 73 mW from a 1.2 V power supply, respectively.

  6. Design and test of a 64-channel charge measurement ASIC developed in CMOS 0.35 μm technology

    NASA Astrophysics Data System (ADS)

    La Rosa, A.; Mazza, G.; Donetti, M.; Marchetto, F.; Luetto, L.; Attili, A.; Bourhaleb, F.; Cirio, R.; Garella, M. A.; Giordanengo, S.; Givehchi, N.; Iliescu, S.; Pardo, J.; Pecka, A.; Peroni, C.; Pittà, G.

    2007-12-01

    A 64-channel charge measurement (Application-Specific Integrated Circuit) ASIC has been designed and tested: it is intended to serve as a front-end electronic read-out for detectors to monitor and measure radiotherapeutical beams. The ASIC has been designed in a CMOS 0.35 μm technology with particular attention to the linearity over a wide input range and can accept currents of both polarities. The linearity is better than 1.5% for a dynamic range of the input current between 500 pA and 3 μA. For a charge resolution of 350 fC, the spread (r.m.s.) of the gain is less than 1%.

  7. Multipurpose Test Structures and Process Characterization using 0.13 μm CMOS: The CHAMP ASIC

    NASA Astrophysics Data System (ADS)

    Cooney, Michael; Andrew, Matt; Nishimura, Kurtis; Ruckman, Larry; Varner, Gary; Grabas, Hervé; Oberla, Eric; Genat, Jean-Francois; Large Area Picosecond Photodetector Collaboration

    The University of Hawaii (UH) in collaboration with the University of Chicago (UC) submitted a test Application Specific Integrated Circuit (ASIC), the Chicago-Hawaii ASIC MultiPurpose (CHAMP), composed of a number of discrete test elements in a 0.13 μm CMOS process. This paper describes the structures submitted by UH and UC. Hawaii designs include high speed flip-flops, voltage controlled ring oscillators and delay lines, an Low Voltage Differential Signal (LVDS) receiver, a set of four 64-cell waveform samplers with shared input, an analog storage and comparator structure, as well as a 12-bit Digital to Analog Converter (DAC). The Chicago designs include voltage controlled delay lines, delay locked loops, voltage controlled ring oscillators, transmission lines, and resistors. Each of the structures will be described, with simulation and test results presented.

  8. Superconducting quantum circuits theory and application

    NASA Astrophysics Data System (ADS)

    Deng, Xiuhao

    Superconducting quantum circuit models are widely used to understand superconducting devices. This thesis consists of four studies wherein the superconducting quantum circuit is used to illustrate challenges related to quantum information encoding and processing, quantum simulation, quantum signal detection and amplification. The existence of scalar Aharanov-Bohm phase has been a controversial topic for decades. Scalar AB phase, defined as time integral of electric potential, gives rises to an extra phase factor in wavefunction. We proposed a superconducting quantum Faraday cage to detect temporal interference effect as a consequence of scalar AB phase. Using the superconducting quantum circuit model, the physical system is solved and resulting AB effect is predicted. Further discussion in this chapter shows that treating the experimental apparatus quantum mechanically, spatial scalar AB effect, proposed by Aharanov-Bohm, can't be observed. Either a decoherent interference apparatus is used to observe spatial scalar AB effect, or a quantum Faraday cage is used to observe temporal scalar AB effect. The second study involves protecting a quantum system from losing coherence, which is crucial to any practical quantum computation scheme. We present a theory to encode any qubit, especially superconducting qubits, into a universal quantum degeneracy point (UQDP) where low frequency noise is suppressed significantly. Numerical simulations for superconducting charge qubit using experimental parameters show that its coherence time is prolong by two orders of magnitude using our universal degeneracy point approach. With this improvement, a set of universal quantum gates can be performed at high fidelity without losing too much quantum coherence. Starting in 2004, the use of circuit QED has enabled the manipulation of superconducting qubits with photons. We applied quantum optical approach to model coupled resonators and obtained a four-wave mixing toolbox to operate photons

  9. Acid-sensing ion channels 1a (ASIC1a) inhibit neuromuscular transmission in female mice

    PubMed Central

    Lino, Noelia G.; González-Inchauspe, Carlota M. F.; González, Laura E.; Colettis, Natalia; Vattino, Lucas G.; Wunsch, Amanda M.; Wemmie, John A.; Uchitel, Osvaldo D.

    2013-01-01

    Acid-sensing ion channels (ASIC) open in response to extracellular acidosis. ASIC1a, a particular subtype of these channels, has been described to have a postsynaptic distribution in the brain, being involved not only in ischemia and epilepsy, but also in fear and psychiatric pathologies. High-frequency stimulation of skeletal motor nerve terminals (MNTs) can induce presynaptic pH changes in combination with an acidification of the synaptic cleft, known to contribute to muscle fatigue. Here, we studied the role of ASIC1a channels on neuromuscular transmission. We combined a behavioral wire hanging test with electrophysiology, pharmacological, and immunofluorescence techniques to compare wild-type and ASIC1a lacking mice (ASIC1a −/− knockout). Our results showed that 1) ASIC1a −/− female mice were weaker than wild type, presenting shorter times during the wire hanging test; 2) spontaneous neurotransmitter release was reduced by ASIC1a activation, suggesting a presynaptic location of these channels at individual MNTs; 3) ASIC1a-mediated effects were emulated by extracellular local application of acid saline solutions (pH = 6.0; HEPES/MES-based solution); and 4) immunofluorescence techniques revealed the presence of ASIC1a antigens on MNTs. These results suggest that ASIC1a channels might be involved in controlling neuromuscular transmission, muscle contraction and fatigue in female mice. PMID:24336653

  10. Acid-sensing ion channels 1a (ASIC1a) inhibit neuromuscular transmission in female mice.

    PubMed

    Urbano, Francisco J; Lino, Noelia G; González-Inchauspe, Carlota M F; González, Laura E; Colettis, Natalia; Vattino, Lucas G; Wunsch, Amanda M; Wemmie, John A; Uchitel, Osvaldo D

    2014-02-15

    Acid-sensing ion channels (ASIC) open in response to extracellular acidosis. ASIC1a, a particular subtype of these channels, has been described to have a postsynaptic distribution in the brain, being involved not only in ischemia and epilepsy, but also in fear and psychiatric pathologies. High-frequency stimulation of skeletal motor nerve terminals (MNTs) can induce presynaptic pH changes in combination with an acidification of the synaptic cleft, known to contribute to muscle fatigue. Here, we studied the role of ASIC1a channels on neuromuscular transmission. We combined a behavioral wire hanging test with electrophysiology, pharmacological, and immunofluorescence techniques to compare wild-type and ASIC1a lacking mice (ASIC1a (-/-) knockout). Our results showed that 1) ASIC1a (-/-) female mice were weaker than wild type, presenting shorter times during the wire hanging test; 2) spontaneous neurotransmitter release was reduced by ASIC1a activation, suggesting a presynaptic location of these channels at individual MNTs; 3) ASIC1a-mediated effects were emulated by extracellular local application of acid saline solutions (pH = 6.0; HEPES/MES-based solution); and 4) immunofluorescence techniques revealed the presence of ASIC1a antigens on MNTs. These results suggest that ASIC1a channels might be involved in controlling neuromuscular transmission, muscle contraction and fatigue in female mice.

  11. Transient waveform recording utilizing TARGET7 ASIC

    NASA Astrophysics Data System (ADS)

    Zhang, J.; Liu, S.; Wang, Y.; Yang, C.; Zhu, X.; Feng, C.; An, Q.

    2017-04-01

    TARGET7, the 7th-generation TeV Array Readout with GSPS (Gigabit Samples Per Second) sampling and Experimental Trigger ASIC, has been initially designed to monolithically and inexpensively instrument large deployments of semiconductor photon detectors for large neutrino and muon detectors. It is a switched capacitor array (SCA) based transient waveform recorder with 3-dB bandwidth of 500 MHz; a large dynamic range of 1.8 V; high sampling rate (typically 1 GSPS); high channel density (16 channels per ASIC); low power consumption (0<1 mW/channel) and deep analog storage buffer (16,384 samples per channel). Moreover, each channel has an integrated Wilkinson ADC (Analog-to-Digital Convertor) for digitization. In this paper, a test board with the chip is described. Calibration methods, timing performance as well as its application possibility in charge measurement with a comparison to an oscilloscope are studied.

  12. Towards Evolving Electronic Circuits for Autonomous Space Applications

    NASA Technical Reports Server (NTRS)

    Lohn, Jason D.; Haith, Gary L.; Colombano, Silvano P.; Stassinopoulos, Dimitris

    2000-01-01

    The relatively new field of Evolvable Hardware studies how simulated evolution can reconfigure, adapt, and design hardware structures in an automated manner. Space applications, especially those requiring autonomy, are potential beneficiaries of evolvable hardware. For example, robotic drilling from a mobile platform requires high-bandwidth controller circuits that are difficult to design. In this paper, we present automated design techniques based on evolutionary search that could potentially be used in such applications. First, we present a method of automatically generating analog circuit designs using evolutionary search and a circuit construction language. Our system allows circuit size (number of devices), circuit topology, and device values to be evolved. Using a parallel genetic algorithm, we present experimental results for five design tasks. Second, we investigate the use of coevolution in automated circuit design. We examine fitness evaluation by comparing the effectiveness of four fitness schedules. The results indicate that solution quality is highest with static and co-evolving fitness schedules as compared to the other two dynamic schedules. We discuss these results and offer two possible explanations for the observed behavior: retention of useful information, and alignment of problem difficulty with circuit proficiency.

  13. Stability of the Baseline Holder in Readout Circuits For Radiation Detectors.

    PubMed

    Chen, Y; Cui, Y; O'Connor, P; Seo, Y; Camarda, G S; Hossain, A; Roy, U; Yang, G; James, R B

    2016-02-01

    Baseline holder (BLH) circuits are used widely to stabilize the analog output of application-specific integrated circuits (ASICs) for high-count-rate applications. The careful design of BLH circuits is vital to the overall stability of the analog-signal-processing chain in ASICs. Recently, we observed self-triggered fluctuations in an ASIC in which the shaping circuits have a BLH circuit in the feedback loop. In fact, further investigations showed that methods of enhancing small-signal stabilities cause an even worse situation. To resolve this problem, we used large-signal analyses to study the circuit's stability. We found that a relatively small gain for the error amplifier and a small current in the non-linear stage of the BLH are required to enhance stability in large-signal analysis, which will compromise the properties of the BLH. These findings were verified by SPICE simulations. In this paper, we present our detailed analysis of the BLH circuits, and propose an improved version of them that have only minimal self-triggered fluctuations. We summarize the design considerations both for the stability and the properties of the BLH circuits.

  14. Mobile Learning Based Worked Example in Electric Circuit (WEIEC) Application to Improve the High School Students' Electric Circuits Interpretation Ability

    ERIC Educational Resources Information Center

    Yadiannur, Mitra; Supahar

    2017-01-01

    This research aims to determine the feasibility and effectivity of mobile learning based Worked Example in Electric Circuits (WEIEC) application in improving the high school students' electric circuits interpretation ability on Direct Current Circuits materials. The research method used was a combination of Four-D Models and ADDIE model. The…

  15. Mongoose ASIC microcontroller programming guide

    NASA Technical Reports Server (NTRS)

    Smith, Brian S.

    1993-01-01

    The 'Mongoose' ASIC microcontroller is a radiation-hard implementation of the R3000 microprocessor. This document describes the internals of the microcontroller in a level of detail necessary for someone implementing a software design.

  16. Mongoose ASIC microcontroller programming guide

    NASA Astrophysics Data System (ADS)

    Smith, Brian S.

    1993-09-01

    The 'Mongoose' ASIC microcontroller is a radiation-hard implementation of the R3000 microprocessor. This document describes the internals of the microcontroller in a level of detail necessary for someone implementing a software design.

  17. Development of a compact radiation-hardened low-noise front-end readout ASIC for CZT-based hard X-ray imager

    NASA Astrophysics Data System (ADS)

    Gao, W.; Gan, B.; Li, X.; Wei, T.; Gao, D.; Hu, Y.

    2015-04-01

    In this paper, we present the development and performances of a radiation-hardened front-end readout application-specific integrated circuit (ASIC) dedicated to CZT detectors for a hard X-ray imager in space applications. The readout channel consists of a charge sensitive amplifier (CSA), a CR-RC shaper, a fast shaper, a discriminator and a driving buffer. With the additional digital filtering, the readout channel can achieve very low noise performances and low power dissipation. An eight-channel prototype ASIC is designed and fabricated in 0.35 μm CMOS process. The energy range of the detected X-rays is evaluated as 1.45 keV to 281 keV. The gain is larger than 100 mV/fC. The equivalent noise charge (ENC) of the ASIC is 53 e- at zero farad plus 10 e- per picofarad. The power dissipation is less than 4.4 mW/channel. Through the measurement with a CZT detector, the energy resolution is less than 3.45 keV (FWHM) under the irradiation of the radioactive source 241Am. The radiation effect experiments indicate that the proposed ASIC can resist the total ionization dose (TID) irradiation of higher than 200 krad (Si).

  18. 1998 technology roadmap for integrated circuits used in critical applications

    SciTech Connect

    Dellin, T.A.

    1998-09-01

    Integrated Circuits (ICs) are being extensively used in commercial and government applications that have extreme consequences of failure. The rapid evolution of the commercial microelectronics industry presents serious technical and supplier challenges to this niche critical IC marketplace. This Roadmap was developed in conjunction with the Using ICs in Critical Applications Workshop which was held in Albuquerque, NM, November 11--12, 1997.

  19. Design Methodology: ASICs with complex in-pixel processing for Pixel Detectors

    SciTech Connect

    Fahim, Farah

    2014-10-31

    The development of Application Specific Integrated Circuits (ASIC) for pixel detectors with complex in-pixel processing using Computer Aided Design (CAD) tools that are, themselves, mainly developed for the design of conventional digital circuits requires a specialized approach. Mixed signal pixels often require parasitically aware detailed analog front-ends and extremely compact digital back-ends with more than 1000 transistors in small areas below 100μm x 100μm. These pixels are tiled to create large arrays, which have the same clock distribution and data readout speed constraints as in, for example, micro-processors. The methodology uses a modified mixed-mode on-top digital implementation flow to not only harness the tool efficiency for timing and floor-planning but also to maintain designer control over compact parasitically aware layout.

  20. Low power RF amplifier circuit for ion trap applications.

    PubMed

    Noriega, J R; García-Delgado, L A; Gómez-Fuentes, R; García-Juárez, A

    2016-09-01

    A low power RF amplifier circuit for ion trap applications is presented and described. The amplifier is based on a class-D half-bridge amplifier with a voltage mirror driver. The RF amplifier is composed of an RF class-D amplifier, an envelope modulator to ramp up the RF voltage during the ion analysis stage, a detector or amplitude demodulation circuit for sensing the output signal amplitude, and a feedback amplifier that linearizes the steady state output of the amplifier. The RF frequency is set by a crystal oscillator and the series resonant circuit is tuned to the oscillator frequency. The resonant circuit components have been chosen, in this case, to operate at 1 MHz. In testings, the class-D stage operated at a maximum of 78 mW at 1.1356 MHz producing 225 V peak.

  1. Low power RF amplifier circuit for ion trap applications

    NASA Astrophysics Data System (ADS)

    Noriega, J. R.; García-Delgado, L. A.; Gómez-Fuentes, R.; García-Juárez, A.

    2016-09-01

    A low power RF amplifier circuit for ion trap applications is presented and described. The amplifier is based on a class-D half-bridge amplifier with a voltage mirror driver. The RF amplifier is composed of an RF class-D amplifier, an envelope modulator to ramp up the RF voltage during the ion analysis stage, a detector or amplitude demodulation circuit for sensing the output signal amplitude, and a feedback amplifier that linearizes the steady state output of the amplifier. The RF frequency is set by a crystal oscillator and the series resonant circuit is tuned to the oscillator frequency. The resonant circuit components have been chosen, in this case, to operate at 1 MHz. In testings, the class-D stage operated at a maximum of 78 mW at 1.1356 MHz producing 225 V peak.

  2. LEC GaAs for integrated circuit applications

    NASA Technical Reports Server (NTRS)

    Kirkpatrick, C. G.; Chen, R. T.; Homes, D. E.; Asbeck, P. M.; Elliott, K. R.; Fairman, R. D.; Oliver, J. D.

    1984-01-01

    Recent developments in liquid encapsulated Czochralski techniques for the growth of semiinsulating GaAs for integrated circuit applications have resulted in significant improvements in the quality and quantity of GaAs material suitable for device processing. The emergence of high performance GaAs integrated circuit technologies has accelerated the demand for high quality, large diameter semiinsulating GaAs substrates. The new device technologies, including digital integrated circuits, monolithic microwave integrated circuits and charge coupled devices have largely adopted direct ion implantation for the formation of doped layers. Ion implantation lends itself to good uniformity and reproducibility, high yield and low cost; however, this technique also places stringent demands on the quality of the semiinsulating GaAs substrates. Although significant progress was made in developing a viable planar ion implantation technology, the variability and poor quality of GaAs substrates have hindered progress in process development.

  3. Printed circuits and their applications: Which way forward?

    NASA Astrophysics Data System (ADS)

    Cantatore, E.

    2015-09-01

    The continuous advancements in printed electronics make nowadays feasible the design of printed circuits which enable meaningful applications. Examples include ultra-low cost sensors embedded in food packaging, large-area sensing surfaces and biomedical assays. This paper offers an overview of state-of-the-art digital and analog circuit blocks, manufactured with a printed complementary organic TFT technology. An analog to digital converter and an RFID tag implemented exploiting these building blocks are also described. The main remaining drawbacks of the printed technology described are identified, and new approaches to further improve the state of the art, enabling more innovative applications are discussed.

  4. Stability of the Baseline Holder in Readout Circuits For Radiation Detectors

    PubMed Central

    Chen, Y.; Cui, Y.; O’Connor, P.; Seo, Y.; Camarda, G. S.; Hossain, A.; Roy, U.; Yang, G.; James, R. B.

    2016-01-01

    Baseline holder (BLH) circuits are used widely to stabilize the analog output of application-specific integrated circuits (ASICs) for high-count-rate applications. The careful design of BLH circuits is vital to the overall stability of the analog-signal-processing chain in ASICs. Recently, we observed self-triggered fluctuations in an ASIC in which the shaping circuits have a BLH circuit in the feedback loop. In fact, further investigations showed that methods of enhancing small-signal stabilities cause an even worse situation. To resolve this problem, we used large-signal analyses to study the circuit’s stability. We found that a relatively small gain for the error amplifier and a small current in the non-linear stage of the BLH are required to enhance stability in large-signal analysis, which will compromise the properties of the BLH. These findings were verified by SPICE simulations. In this paper, we present our detailed analysis of the BLH circuits, and propose an improved version of them that have only minimal self-triggered fluctuations. We summarize the design considerations both for the stability and the properties of the BLH circuits. PMID:27182081

  5. ASIC channel inhibition enhances excitotoxic neuronal death in an in vitro model of spinal cord injury.

    PubMed

    Mazzone, Graciela L; Veeraraghavan, Priyadharishini; Gonzalez-Inchauspe, Carlota; Nistri, Andrea; Uchitel, Osvaldo D

    2017-02-20

    In the spinal cord high extracellular glutamate evokes excitotoxic damage with neuronal loss and severe locomotor impairment. During the cell dysfunction process, extracellular pH becomes acid and may activate acid-sensing ion channels (ASICs) which could be important contributors to neurodegenerative pathologies. Our previous studies have shown that transient application of the glutamate analog kainate (KA) evokes delayed excitotoxic death of spinal neurons, while white matter is mainly spared. The present goal was to enquire if ASIC channels modulated KA damage in relation to locomotor network function and cell death. Mouse spinal cord slices were treated with KA (0.01 or 0.1mM) for 1h, and then washed out for 24h prior to analysis. RT-PCR results showed that KA (at 0.01mM concentration that is near-threshold for damage) increased mRNA expression of ASIC1a, ASIC1b, ASIC2 and ASIC3, an effect reversed by the ASIC inhibitor 4',6-diamidino-2-phenylindole (DAPI). A KA neurotoxic dose (0.1mM) reduced ASIC1a and ASIC2 expression. Cell viability assays demonstrated KA-induced large damage in spinal slices from mice with ASIC1a gene ablation. Likewise, immunohistochemistry indicated significant neuronal loss when KA was followed by the ASIC inhibitors DAPI or amiloride. Electrophysiological recording from ventral roots of isolated spinal cords showed that alternating oscillatory cycles were slowed down by 0.01mMKA, and intensely inhibited by subsequently applied DAPI or amiloride. Our data suggest that early rise in ASIC expression and function counteracted deleterious effects on spinal networks by raising the excitotoxicity threshold, a result with potential implications for improving neuroprotection. Copyright © 2016 IBRO. Published by Elsevier Ltd. All rights reserved.

  6. A 64-channel integrated circuit for signal readout from coordinate detectors

    NASA Astrophysics Data System (ADS)

    Aulchenko, V.; Shekhtman, L.; Zhulanov, V.

    2017-05-01

    A specialized integrated circuit was developed for the readout of signal from coordinate detectors of different types, including gas micro-pattern detectors and silicon microstrip detectors. The ASIC includes 64 channels, each containing a low-noise charge-sensitive amplifier with a connectable feedback capacitor and resistor, and fast reset of the feedback capacitor. Each channel of the ASIC also contains 100 cells of analogue memory where the signal can be stored at a rate of 10 MHz. The pitch of input pads is 50 μm and the chip size is 5× 5 mm2. The equivalent noise charge of the ASIC channel is about 2000 electrons with 10 pF capacitance at the input and maximal signal before saturation corresponds to 2× 106 electrons. The first application for this ASIC is the detector for imaging of explosions at a synchrotron radiation beam (DIMEX), where it has to substitute the old and slower APC128 ASIC. The full-size electronics including 8 ASICs for 512 channels was assembled and tested.

  7. GaAs IMPATT diodes for microstrip circuit applications.

    NASA Technical Reports Server (NTRS)

    Wisseman, W. R.; Tserng, H. Q.; Shaw, D. W.; Mcquiddy, D. N.

    1972-01-01

    GaAs IMPATT diodes with plated heat sinks are shown to be particularly well suited for microstrip circuit applications. Details of materials growth and device fabrication procedures are given, and experimental results are presented for a GaAs IMPATT microstrip oscillator operating at X band.

  8. GaAs IMPATT diodes for microstrip circuit applications.

    NASA Technical Reports Server (NTRS)

    Wisseman, W. R.; Tserng, H. Q.; Shaw, D. W.; Mcquiddy, D. N.

    1972-01-01

    GaAs IMPATT diodes with plated heat sinks are shown to be particularly well suited for microstrip circuit applications. Details of materials growth and device fabrication procedures are given, and experimental results are presented for a GaAs IMPATT microstrip oscillator operating at X band.

  9. Rad-Hard Microcontroller for Space Applications

    NASA Astrophysics Data System (ADS)

    Habinc, Sandi; Johansson, Fredrik; Sturesson, Fredrik; Simlastik, Martin; Hjorth, Magnus; Andersson, Jan; Redant, Steven; Sijbers, Wim; Thys, Geert; Monteleone, Claudio

    2015-09-01

    This paper describes a mixed-signal LEON3FT microcontroller ASIC (Application Specific Integrated Circuit) targeting embedded control applications with hard real-time requirements. The prototype device is currently in development at Cobham Gaisler, Sweden, and IMEC, Belgium, in the activity Microcontroller for embedded space applications, initiated and funded by the European Space Agency (ESA).

  10. 116 dB dynamic range CMOS readout circuit for MEMS capacitive accelerometer

    NASA Astrophysics Data System (ADS)

    Shanli, Long; Yan, Liu; Kejun, He; Xinggang, Tang; Qian, Chen

    2014-09-01

    A high stability in-circuit reprogrammable technique control system for a capacitive MEMS accelerometer is presented. Modulation and demodulation are used to separate the signal from the low frequency noise. A low-noise low-offset charge integrator is employed in this circuit to implement a capacitance-to-voltage converter and minimize the noise and offset. The application-specific integrated circuit (ASIC) is fabricated in a 0.5 μm one-ploy three-metal CMOS process. The measured results of the proposed circuit show that the noise floor of the ASIC is -116 dBV, the sensitivity of the accelerometer is 66 mV/g with a nonlinearity of 0.5%. The chip occupies 3.5 × 2.5 mm2 and the current is 3.5 mA.

  11. Design and Measurement of a Low-Noise 64-Channels Front-End Readout ASIC for CdZnTe Detectors

    SciTech Connect

    Gan, Bo; Wei, Tingcun; Gao, Wu; Liu, Hui; Hu, Yann

    2015-07-01

    Cadmium zinc telluride (CdZnTe) detectors, as one of the principal detectors for the next-generation X-ray and γ-ray imagers, have high energy resolution and supporting electrode patterning in the radiation environment at room-temperature. In the present, a number of internationally renowned research institutions and universities are actively using these detector systems to carry out researches of energy spectrum analysis, medical imaging, materials characterization, high-energy physics, nuclear plant monitoring, and astrophysics. As the most important part of the readout system for the CdZnTe detector, the front-end readout application specific integrated circuit (ASIC) would have an important impact on the performances of the whole detector system. In order to ensure the small signal to noise ratio (SNR) and sufficient range of the output signal, it is necessary to design a front-end readout ASIC with very low noise and very high dynamic range. In addition, radiation hardness should be considered when the detectors are utilized in the space applications and high energy physics experiments. In this paper, we present measurements and performances of a novel multi-channel radiation-hardness low-noise front-end readout ASIC for CdZnTe detectors. The readout circuits in each channel consist of charge sensitive amplifier, leakage current compensation circuit (LCC), CR-RC shaper, S-K filter, inverse proportional amplifier, peak detect and hold circuit (PDH), discriminator and trigger logic, time sequence control circuit and driving buffer. All of 64 readout channels' outputs enter corresponding inputs of a 64 channel multiplexer. The output of the mux goes directly out of the chip via the output buffer. The 64-channel readout ASIC is implemented using the TSMC 0.35 μm mixed-signal CMOS technology. The die size of the prototype chip is 2.7 mm x 8 mm. At room temperature, the equivalent noise level of a typical channel reaches 66 e{sup -} (rms) at zero farad for a power

  12. Design and performances of a low-noise and radiation-hardened readout ASIC for CdZnTe detectors

    NASA Astrophysics Data System (ADS)

    Bo, Gan; Tingcun, Wei; Wu, Gao; Yongcai, Hu

    2016-06-01

    In this paper, we present the design and performances of a low-noise and radiation-hardened front-end readout application specific integrated circuit (ASIC) dedicated to CdZnTe detectors for a hard X-ray imager in space applications. The readout channel is comprised of a charge sensitive amplifier, a CR-RC shaping amplifier, an analog output buffer, a fast shaper, and a discriminator. An 8-channel prototype ASIC is designed and fabricated in TSMC 0.35-μm mixed-signal CMOS technology, the die size of the prototype chip is 2.2 × 2.2 mm2. The input energy range is from 5 to 350 keV. For this 8-channel prototype ASIC, the measured electrical characteristics are as follows: the overall gain of the readout channel is 210 V/pC, the linearity error is less than 2%, the crosstalk is less than 0.36%, The equivalent noise charge of a typical channel is 52.9 e- at zero farad plus 8.2 e- per picofarad, and the power consumption is less than 2.4 mW/channel. Through the measurement together with a CdZnTe detector, the energy resolution is 5.9% at the 59.5-keV line under the irradiation of the radioactive source 241Am. The radiation effect experiments show that the proposed ASIC can resist the total ionization dose (TID) irradiation of higher than 200 krad(Si). Project supported by the National Key Scientific Instrument and Equipment Development Project (No. 2011YQ040082), the National Natural Science Foundation of China (Nos. 11475136, 11575144, 61176094), and the Shaanxi Natural Science Foundation of China (No. 2015JM1016).

  13. The VeloPix ASIC

    NASA Astrophysics Data System (ADS)

    Poikela, T.; Ballabriga, R.; Buytaert, J.; Llopart, X.; Wong, W.; Campbell, M.; Wyllie, K.; van Beuzekom, M.; Schipper, J.; Miryala, S.; Gromov, V.

    2017-01-01

    VeloPix, a 130 nm CMOS technology chip with data driven and zero suppressed readout, will be used as a readout chip for the hybrid pixel system of the LHCb Vertex Locator (VELO) upgrade. The upgrade, scheduled for LHC Run-3, will enable the experiment to be read out at 40 MHz in trigger-less mode, with event selection being performed in the CPU farm. The highest occupancy ASICs will experience rates of more than 900 Mhits/s, and the closest pixels are 5.1 mm from the LHC beams. This paper will present the VeloPix ASIC along with the first test results without a sensor.

  14. Applications of carbon nanotubes on integrated circuits

    NASA Astrophysics Data System (ADS)

    Zhang, Min

    The microelectronics technology falls within the boundaries of that definition. Carbon nanotube (CNT) is a promising alternative material for the future nanoelectronics. Owing to the unique properties of CNTs and the maturity of CMOS IC technology, the integration of the two technologies will take advantages of both. In this work, we demonstrate a new local silicon-gate carbon nanotube field-effect transistor (CNFET) by combining the in situ CNT growth technology and the SOI technology. The proposed CNFET structure has realized individual device operation, batch fabrication, low parasitics and better compatibility to the CMOS process at the same time. The configuration proposes a feasible approach to integrate the CNTs to CMOS platform for the first time, which makes CNT a step closer to application. The CNFETs show advanced DC characteristics. The ambipolar conductance and the scaling effect of the CNFETs have been analyzed based on the SB modulated conductance mechanism. Investigation of radio-frequency (RF) characteristics of CNTs is essential for their application. RF transmission characteristics of the semiconducting and metallic CNTs are investigated to the frequency of 12 GHz using the full two-port S-parameter methodology for the first time. Without the effect of the parasitics, the signal transmission capability of the CNTs maintains at a constant level and shows no degeneration even at a high frequency of 12 GHz. An empirical RLC element model has been proposed to fit the RF response of the CNT array. Capacitive contact is reported between the CNTs and the metal electrodes. We also explore the high-frequency properties of the local silicon-gate CNFET as an active device by measuring its S parameters using a common-source configuration. In addition, we demonstrate the application of CNT as via/contact filler to solve the problems of copper vias used in ICs nowadays. We have optimized the fabrication process for the CNT via integration. The CNT vias with

  15. CWICOM: A Highly Integrated & Innovative CCSDS Image Compression ASIC

    NASA Astrophysics Data System (ADS)

    Poupat, Jean-Luc; Vitulli, Raffaele

    2013-08-01

    The space market is more and more demanding in terms of on image compression performances. The earth observation satellites instrument resolution, the agility and the swath are continuously increasing. It multiplies by 10 the volume of picture acquired on one orbit. In parallel, the satellites size and mass are decreasing, requiring innovative electronic technologies reducing size, mass and power consumption. Astrium, leader on the market of the combined solutions for compression and memory for space application, has developed a new image compression ASIC which is presented in this paper. CWICOM is a high performance and innovative image compression ASIC developed by Astrium in the frame of the ESA contract n°22011/08/NLL/LvH. The objective of this ESA contract is to develop a radiation hardened ASIC that implements the CCSDS 122.0-B-1 Standard for Image Data Compression, that has a SpaceWire interface for configuring and controlling the device, and that is compatible with Sentinel-2 interface and with similar Earth Observation missions. CWICOM stands for CCSDS Wavelet Image COMpression ASIC. It is a large dynamic, large image and very high speed image compression ASIC potentially relevant for compression of any 2D image with bi-dimensional data correlation such as Earth observation, scientific data compression… The paper presents some of the main aspects of the CWICOM development, such as the algorithm and specification, the innovative memory organization, the validation approach and the status of the project.

  16. Chopper Circuits Developed for EV Drive Application

    NASA Astrophysics Data System (ADS)

    Tsuruta, Yukinori; Kawamura, Atsuo

    In this paper, the technical stream on a high efficiency and high frequency chopper for the automotive industry, new energy and energy conservation technology field is surveyed. QRAS (Quasi-resonant Regenerating Active Snubber) and SAZZ (Snubber Assisted Zero Voltage and Zero Current Transition) topologies aimed for the electric vehicle (EV) drive application are proposed. 25kHz-8kW QRAS, 100kHz-8kW SAZZ choppers and 50kHz-25kW bilateral SAZZ-1 chopper are constructed and tested under rating conditions. It is verified that SAZZ topology retains high efficiency even at the increased operating frequency of 100kHz. It is shown that high efficiency can be realized at high operating frequency even in high power converters by QRAS and newly proposed SAZZ soft switching topologies.

  17. Multiplexed detection of cardiac biomarkers in serum with nanowire arrays using readout ASIC.

    PubMed

    Zhang, Guo-Jun; Chai, Kevin Tshun Chuan; Luo, Henry Zhan Hong; Huang, Joon Min; Tay, Ignatius Guang Kai; Lim, Andy Eu-Jin; Je, Minkyu

    2012-05-15

    Early detection of cardiac biomarkers for diagnosis of heart attack is the key to saving lives. Conventional method of detection like the enzyme-linked immunosorbent assay (ELISA) is time consuming and low in sensitivity. Here, we present a label-free detection system consisting of an array of silicon nanowire sensors and an interface readout application specific integrated circuit (ASIC). This system provides a rapid solution that is highly sensitive and is able to perform direct simultaneous-multiplexed detection of cardiac biomarkers in serum. Nanowire sensor arrays were demonstrated to have the required selectivity and sensitivity to perform multiplexed detection of 100 fg/ml troponin T, creatine kinase MM, and creatine kinase MB in serum. A good correlation between measurements from a probe station and the readout ASIC was obtained. Our detection system is expected to address the existing limitations in cardiac health management that are currently imposed by the conventional testing platform, and opens up possibilities in the development of a miniaturized device for point-of-care diagnostic applications.

  18. A Novel Front-End ASIC With Post Digital Filtering and Calibration for CZT-Based PET Detector

    SciTech Connect

    Gao, W.; Yin, J.; Li, C.; Zeng, H.; Gao, D.; Hu, Y.

    2015-07-01

    This paper presents a novel front-end electronics based on a front-end ASIC with post digital filtering and calibration dedicated to CZT detectors for PET imaging. A cascade amplifier based on split-leg topology is selected to realize the charge-sensitive amplifier (CSA) for the sake of low noise performances and the simple scheme of the power supplies. The output of the CSA is connected to a variable-gain amplifier to generate the compatible signals for the A/D conversion. A multi-channel single-slope ADC is designed to sample multiple points for the digital filtering and shaping. The digital signal processing algorithms are implemented by a FPGA. To verify the proposed scheme, a front-end readout prototype ASIC is designed and implemented in 0.35 μm CMOS process. In a single readout channel, a CSA, a VGA, a 10-bit ADC and registers are integrated. Two dummy channels, bias circuits, and time controller are also integrated. The die size is 2.0 mm x 2.1 mm. The input range of the ASIC is from 2000 e{sup -} to 100000 e{sup -}, which is suitable for the detection of the X-and gamma ray from 11.2 keV to 550 keV. The linearity of the output voltage is less than 1 %. The gain of the readout channel is 40.2 V/pC. The static power dissipation is about 10 mW/channel. The above tested results show that the electrical performances of the ASIC can well satisfy PET imaging applications. (authors)

  19. Design of versatile ASIC and protocol tester for CBM readout system

    NASA Astrophysics Data System (ADS)

    Zabołotny, W. M.; Byszuk, A. P.; Emschermann, D.; Gumiński, M.; Juszczyk, B.; Kasiński, K.; Kasprowicz, G.; Lehnert, J.; Müller, W. F. J.; Poźniak, K.; Romaniuk, R.; Szczygieł, R.

    2017-02-01

    Silicon Tracking System (STS), Muon Chamber (MUCH) and Transition Radiation Detector (TRD) subdetectors in the Compressed Baryonic Matter (CBM) detector system at Facility for Antiproton and Ion Research (FAIR) use the same innovative protocol ensuring reliable synchronization of the communication link between the controller and the front-end ASIC, transmission of time-deterministic commands to the ASIC and efficient readout of data. The paper describes the FPGA-based tester platform which can be used both for the verification of the protocol implementation in a front-end ASIC at the design stage, and for testing of the produced ASICs. Due to its modularity, the platform can be easily adapted for different integrated circuits and readout systems.

  20. ASIC3 channels in multimodal sensory perception.

    PubMed

    Li, Wei-Guang; Xu, Tian-Le

    2011-01-19

    Acid-sensing ion channels (ASICs), which are members of the sodium-selective cation channels belonging to the epithelial sodium channel/degenerin (ENaC/DEG) family, act as membrane-bound receptors for extracellular protons as well as nonproton ligands. At least five ASIC subunits have been identified in mammalian neurons, which form both homotrimeric and heterotrimeric channels. The highly proton sensitive ASIC3 channels are predominantly distributed in peripheral sensory neurons, correlating with their roles in multimodal sensory perception, including nociception, mechanosensation, and chemosensation. Different from other ASIC subunit composing ion channels, ASIC3 channels can mediate a sustained window current in response to mild extracellular acidosis (pH 7.3-6.7), which often occurs accompanied by many sensory stimuli. Furthermore, recent evidence indicates that the sustained component of ASIC3 currents can be enhanced by nonproton ligands including the endogenous metabolite agmatine. In this review, we first summarize the growing body of evidence for the involvement of ASIC3 channels in multimodal sensory perception and then discuss the potential mechanisms underlying ASIC3 activation and mediation of sensory perception, with a special emphasis on its role in nociception. We conclude that ASIC3 activation and modulation by diverse sensory stimuli represent a new avenue for understanding the role of ASIC3 channels in sensory perception. Furthermore, the emerging implications of ASIC3 channels in multiple sensory dysfunctions including nociception allow the development of new pharmacotherapy.

  1. TARGET: A digitizing and trigger ASIC for the Cherenkov telescope array

    NASA Astrophysics Data System (ADS)

    Funk, S.; Jankowsky, D.; Katagiri, H.; Kraus, M.; Okumura, A.; Schoorlemmer, H.; Shigenaka, A.; Tajima, H.; Tibaldo, L.; Varner, G.; Zink, A.; Zorn, J.

    2017-01-01

    The future ground-based gamma-ray observatory Cherenkov Telescope Array (CTA) will feature multiple types of imaging atmospheric Cherenkov telescopes, each with thousands of pixels. To be affiordable, camera concepts for these telescopes have to feature low cost per channel and at the same time meet the requirements for CTA in order to achieve the desired scientific goals. We present the concept of the TeV Array Readout Electronics with GSa/s sampling and Event Trigger (TARGET) Application Specific Circuit (ASIC), envisaged to be used in the cameras of various CTA telescopes, e.g. the Gamma-ray Cherenkov Telescope (GCT), a proposed 2-Mirror Small-Sized Telescope, and the Schwarzschild-Couder Telescope (SCT), a proposed Medium-Sized Telescope. In the latest version of this readout concept the sampling and trigger parts are split into dedicated ASICs, TARGET C and T5TEA, both providing 16 parallel input channels. TARGET C features a tunable sampling rate (usually 1 GSa/s), a 16k sample deep buffier for each channel and on-demand digitization and transmission of waveforms with typical spans of ˜100 ns. The trigger ASIC, T5TEA, provides 4 low voltage diffierential signal (LVDS) trigger outputs and can generate a pedestal voltage independently for each channel. Trigger signals are generated by T5TEA based on the analog sum of the input in four independent groups of four adjacent channels and compared to a threshold set by the user. Thus, T5TEA generates four LVDS trigger outputs, as well as 16 pedestal voltages fed to TARGET C independently for each channel. We show preliminary results of the characterization and testing of TARGET C and T5TEA.

  2. Airbag accelerometer with a simple switched-capacitor readout ASIC

    NASA Astrophysics Data System (ADS)

    Tsugai, Masahiro; Hirata, Yoshiaki; Tanimoto, Koji; Usami, Teruo; Araki, Toru; Otani, Hiroshi

    1997-09-01

    A bulk micromachined capacitive accelerometer for airbag applications based on (110) silicon anisotropic KOH etching is presented. The sensor is a two-chip accelerometer that consists of a glass-silicon-glass stacked sense element and an interface ASIC containing an impedance converter for capacitance detection, an EPROM and DACs for digital trimming, and a self-test feature for diagnosis. A simple switched-capacitor readout circuit with DC offset error cancellation scheme is proposed as the impedance converter. The dependence of narrow gap etching, surface roughness, and uniformity of the groove depth on the KOH concentration are also investigated for the fabrication of the device, and it is shown that the etch rate of the plane intrinsically controls the depth of the narrow gap with a KOH concentration of over 30 wt. percent, and smooth surface and uniformity of groove depth are obtained at 40 wt. percent KOH. The nonlinearity of the output is about 1.5 percent FS. The temperature coefficient of sensitivity and the off-axis sensitivity are 150 ppm/degree C and 2 percent respectively. The dimensions of the sensor are 10.3 X 10.3 X 3 mm.

  3. FRONT-END ASIC FOR A SILICON COMPTON TELESCOPE.

    SciTech Connect

    DE GERONIMO,G.; FRIED, J.; FROST, E.; PHLIPS, B.; VERNON, E.; WULF, E.A.

    2007-10-27

    We describe a front-end application specific integrated circuit (ASIC) developed for a silicon Compton telescope. Composed of 32 channels, it reads out signals in both polarities from each side of a Silicon strip sensor, 2 mm thick 27 cm long, characterized by a strip capacitance of 30 pF. Each front-end channel provides low-noise charge amplification, shaping with a stabilized baseline, discrimination, and peak detection with an analog memory. The channels can process events simultaneously, and the read out is sparsified. The charge amplifier makes uses a dual-cascode configuration and dual-polarity adaptive reset, The low-hysteresis discriminator and the multi-phase peak detector process signals with a dynamic range in excess of four hundred. An equivalent noise charge (ENC) below 200 electrons was measured at 30 pF, with a slope of about 4.5 electrons/pF at a peaking time of 4 {micro}s. With a total dissipated power of 5 mW the channel covers an energy range up to 3.2 MeV.

  4. [Flexible print circuit technology application in biomedical engineering].

    PubMed

    Jiang, Lihua; Cao, Yi; Zheng, Xiaolin

    2013-06-01

    Flexible print circuit (FPC) technology has been widely applied in variety of electric circuits with high precision due to its advantages, such as low-cost, high specific fabrication ability, and good flexibility, etc. Recently, this technology has also been used in biomedical engineering, especially in the development of microfluidic chip and microelectrode array. The high specific fabrication can help making microelectrode and other micro-structure equipment. And good flexibility allows the micro devices based on FPC technique to be easily packaged with other parts. In addition, it also reduces the damage of microelectrodes to the tissue. In this paper, the application of FPC technology in biomedical engineering is introduced. Moreover, the important parameters of FPC technique and the development trend of prosperous applications is also discussed.

  5. 20 CFR 410.670c - Application of circuit court law.

    Code of Federal Regulations, 2010 CFR

    2010-04-01

    ... 20 Employees' Benefits 2 2010-04-01 2010-04-01 false Application of circuit court law. 410.670c..., Administrative Review, Finality of Decisions, and Representation of Parties § 410.670c Application of circuit... involving the application of circuit court law. (a) The Administration will apply a holding in a United...

  6. 20 CFR 410.670c - Application of circuit court law.

    Code of Federal Regulations, 2011 CFR

    2011-04-01

    ... 20 Employees' Benefits 2 2011-04-01 2011-04-01 false Application of circuit court law. 410.670c..., Administrative Review, Finality of Decisions, and Representation of Parties § 410.670c Application of circuit... involving the application of circuit court law. (a) The Administration will apply a holding in a United...

  7. Integrated optical circuits and components: Design and applications

    NASA Astrophysics Data System (ADS)

    Hutcheson, Lynn D.

    This book focuses on the practical aspects of designing, fabricating, and testing integrated optical circuits and devices, covering concepts, theory, design criteria, materials, and applications. Device performance limits are explained, and a guide is given to fabricating lithium niobate and gallium arsenide devices. Techniques for integrating optics with electronics on a single substrate are demonstrated. New and novel developments are reviewed, and prospects for the future of this technology are considered.

  8. 3D probe array integrated with a front-end 100-channel neural recording ASIC

    NASA Astrophysics Data System (ADS)

    Cheng, Ming-Yuan; Yao, Lei; Tan, Kwan Ling; Lim, Ruiqi; Li, Peng; Chen, Weiguo

    2014-12-01

    Brain-machine interface technology can improve the lives of spinal cord injury victims and amputees. A neural interface system, consisting of a 3D probe array and a custom low-power (1 mW) 100-channel (100-ch) neural recording application-specific integrated circuit (ASIC), was designed and implemented to monitor neural activity. In this study, a microassembly 3D probe array method using a novel lead transfer technique was proposed to overcome the bonding plane mismatch encountered during orthogonal assembly. The proposed lead transfer technique can be completed using standard micromachining and packaging processes. The ASIC can be stacking-integrated with the probe array, minimizing the form factor of the assembled module. To minimize trauma to brain cells, the profile of the integrated probe array was controlled within 730 μm. The average impedance of the assembled probe was approximately 0.55 MΩ at 1 kHz. To verify the functionality of the integrated neural probe array, bench-top signal acquisitions were performed and discussed.

  9. Data encryption standard ASIC design and development report.

    SciTech Connect

    Robertson, Perry J.; Pierson, Lyndon George; Witzke, Edward L.

    2003-10-01

    This document describes the design, fabrication, and testing of the SNL Data Encryption Standard (DES) ASIC. This device was fabricated in Sandia's Microelectronics Development Laboratory using 0.6 {micro}m CMOS technology. The SNL DES ASIC was modeled using VHDL, then simulated, and synthesized using Synopsys, Inc. software and finally IC layout was performed using Compass Design Automation's CAE tools. IC testing was performed by Sandia's Microelectronic Validation Department using a HP 82000 computer aided test system. The device is a single integrated circuit, pipelined realization of DES encryption and decryption capable of throughputs greater than 6.5 Gb/s. Several enhancements accommodate ATM or IP network operation and performance scaling. This design is the latest step in the evolution of DES modules.

  10. Digital circuits using universal logic gates

    NASA Technical Reports Server (NTRS)

    Whitaker, Sterling R. (Inventor); Miles, Lowell H. (Inventor); Cameron, Eric G. (Inventor); Donohoe, Gregory W. (Inventor); Gambles, Jody W. (Inventor)

    2004-01-01

    According to the invention, a digital circuit design embodied in at least one of a structural netlist, a behavioral netlist, a hardware description language netlist, a full-custom ASIC, a semi-custom ASIC, an IP core, an integrated circuit, a hybrid of chips, one or more masks, a FPGA, and a circuit card assembly is disclosed. The digital circuit design includes first and second sub-circuits. The first sub-circuits comprise a first percentage of the digital circuit design and the second sub-circuits comprise a second percentage of the digital circuit design. Each of the second sub-circuits is substantially comprised of one or more kernel circuits. The kernel circuits are comprised of selection circuits. The second percentage is at least 5%. In various embodiments, the second percentage could be at least 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, or 95%.

  11. Millimeter-wave and optoelectronic applications of heterostructure integrated circuits

    NASA Technical Reports Server (NTRS)

    Pavlidis, Dimitris

    1991-01-01

    The properties are reviewed of heterostructure devices for microwave-monolithic-integrated circuits (MMICs) and optoelectronic integrated circuits (OICs). Specific devices examined include lattice-matched and pseudomorphic InAlAs/InGaAs high-electron mobility transistors (HEMTs), mixer/multiplier diodes, and heterojunction bipolar transistors (HBTs) developed with a number of materials. MMICs are reviewed that can be employed for amplification, mixing, and signal generation, and receiver/transmitter applications are set forth for OICs based on GaAs and InP heterostructure designs. HEMTs, HBTs, and junction-FETs can be utilized in combination with PIN, MSM, and laser diodes to develop novel communication systems based on technologies that combine microwave and photonic capabilities.

  12. Capturing a failure of an ASIC in-situ, using infrared radiometry and image processing software

    NASA Technical Reports Server (NTRS)

    Ruiz, Ronald P.

    2003-01-01

    Failures in electronic devices can sometimes be tricky to locate-especially if they are buried inside radiation-shielded containers designed to work in outer space. Such was the case with a malfunctioning ASIC (Application Specific Integrated Circuit) that was drawing excessive power at a specific temperature during temperature cycle testing. To analyze the failure, infrared radiometry (thermography) was used in combination with image processing software to locate precisely where the power was being dissipated at the moment the failure took place. The IR imaging software was used to make the image of the target and background, appear as unity. As testing proceeded and the failure mode was reached, temperature changes revealed the precise location of the fault. The results gave the design engineers the information they needed to fix the problem. This paper describes the techniques and equipment used to accomplish this failure analysis.

  13. Linearity enhancement design of a 16-channel low-noise front-end readout ASIC for CdZnTe detectors

    NASA Astrophysics Data System (ADS)

    Zeng, Huiming; Wei, Tingcun; Wang, Jia

    2017-03-01

    A 16-channel front-end readout application-specific integrated circuit (ASIC) with linearity enhancement design for cadmium zinc telluride (CdZnTe) detectors is presented in this paper. The resistors in the slow shaper are realized using a high-Z circuit to obtain constant resistance value instead of using only a metal-oxide-semiconductor (MOS) transistor, thus the shaping time of the slow shaper can be kept constant for different amounts of input energies. As a result, the linearity of conversion gain is improved significantly. The ASIC was designed and fabricated in a 0.35 μm CMOS process with a die size of 2.60 mm×3.53 mm. The tested results show that a typical channel provides an equivalent noise charge (ENC) of 109.7e-+16.3e-/pF with a power consumption of 4 mW and achieves a conversion gain of 87 mV/fC with a nonlinearity of <0.4%. The linearity of conversion gain is improved by at least 86.6% as compared with the traditional approaches using the same front-end readout architecture and manufacture process. Moreover, the inconsistency among channels is <0.3%. An energy resolution of 2.975 keV (FWHM) for gamma rays of 59.5 keV was measured by connecting the ASIC to a 5 mm×5 mm ×2 mm CdZnTe detector at room temperature. The front-end readout ASIC presented in this paper achieves an outstanding linearity performance without compromising the noise, power consumption, and chip size performances.

  14. VEGA: A low-power front-end ASIC for large area multi-linear X-ray silicon drift detectors: Design and experimental characterization

    NASA Astrophysics Data System (ADS)

    Ahangarianabhari, Mahdi; Macera, Daniele; Bertuccio, Giuseppe; Malcovati, Piero; Grassi, Marco

    2015-01-01

    We present the design and the first experimental characterization of VEGA, an Application Specific Integrated Circuit (ASIC) designed to read out large area monolithic linear Silicon Drift Detectors (SDD's). VEGA consists of an analog and a digital/mixed-signal section to accomplish all the functionalities and specifications required for high resolution X-ray spectroscopy in the energy range between 500 eV and 50 keV. The analog section includes a charge sensitive preamplifier, a shaper with 3-bit digitally selectable shaping times from 1.6 μs to 6.6 μs and a peak stretcher/sample-and-hold stage. The digital/mixed-signal section includes an amplitude discriminator with coarse and fine threshold level setting, a peak discriminator and a logic circuit to fulfill pile-up rejection, signal sampling, trigger generation, channel reset and the preamplifier and discriminators disabling functionalities. A Serial Peripherical Interface (SPI) is integrated in VEGA for loading and storing all configuration parameters in an internal register within few microseconds. The VEGA ASIC has been designed and manufactured in 0.35 μm CMOS mixed-signal technology in single and 32 channel versions with dimensions of 200 μm×500 μm per channel. A minimum intrinsic Equivalent Noise Charge (ENC) of 12 electrons r.m.s. at 3.6 μs peaking time and room temperature is measured and the linearity error is between -0.9% and +0.6% in the whole input energy range. The total power consumption is 481 μW and 420 μW per channel for the single and 32 channels version, respectively. A comparison with other ASICs for X-ray SDD's shows that VEGA has a suitable low noise and offers high functionality as ADC-ready signal processing but at a power consumption that is a factor of four lower than other similar existing ASICs.

  15. Performance of an analog ASIC developed for the front-end electronics of the soft x-ray imager onboard ASTRO-H

    NASA Astrophysics Data System (ADS)

    Nakajima, H.; Idehara, T.; Matsuura, D.; Anabuki, N.; Tsunemi, H.; Doty, J. P.; Ikeda, H.

    2009-08-01

    We report on the performance of an analog application-specified integrated circuit (ASIC) developed for the front-end electronics of the X-ray CCD camera system (SXI: Soft X-ray Imager) onboard the ASTRO-H satellite. The ASIC consists of four identical channels and they simultaneously process the CCD signals at the pixel rate of 68kHz. Delta-Sigma modulator is adopted to achieve effective noise shaping and obtain a high resolution decimal values with relatively simple circuits. We will implement 16 ASIC chips in total in the focal plane assembly. The results of the unit test shows that it works properly with moderately low input noise of <30μV at the pixel rate of 80kHz. Power consumption is sufficiently low of 150mW. Dynamic range of input signals is +-20mV that covers effective energy range of the CCD chips of SXI (0.2-20keV). The integrated non-linearity of 0.2% satisfies the same performance as the conventional CCD detectors in orbit. The radiation tolerance against total ionizing dose (TID) effect and single event latch-up (SEL) has also been investigated. The irradiation test using 60Co gamma-rays and proton beam showed that the ASIC has sufficient tolerance against TID up to 200 and 167krad respectively, which thoroughly exceeds the expected operating duration in the planned low-inclination low-earth orbit. The irradiation of the Fe ion beam also showed no latch-up nor malfunctions up to the fluence of 4.7x10^7ions. The threshold against SEL is larger than 1.68MeVcm^2/mg, which is sufficiently high enough that SEL events should not be a major cause of instrument downtime.

  16. NMDAR-Mediated Hippocampal Neuronal Death is Exacerbated by Activities of ASIC1a

    PubMed Central

    Gao, Su; Yu, Yang; Ma, Zhi-Yuan; Sun, Hui; Zhang, Yong-Li; Wang, Xing-Tao; Wang, Chaoyun; Fan, Wei-Ming; Zheng, Qing-Yin

    2015-01-01

    NMDARs and ASIC1a both exist in central synapses and mediate important physiological and pathological conditions, but the functional relationship between them is unclear. Here we report several novel findings that may shed light on the functional relationship between these two ion channels in the excitatory postsynaptic membrane of mouse hippocampus. Firstly, NMDAR activation induced by either NMDA or OGD led to increased [Ca2+]i and greater apoptotic and necrotic cell deaths in cultured hippocampal neurons; these cell deaths were prevented by application of NMDAR antagonists. Secondly, ASIC1a activation induced by pH 6.0 extracellular solution (ECS) showed similar increases in apoptotic and necrotic cell deaths; these cell deaths were prevented by ASIC1a antagonists, and also by NMDAR antagonists. Since increased [Ca2+]i leads to increased cell deaths and since NMDAR exhibits much greater calcium permeability than ASIC1a, these data suggest that ASIC1a-induced neuronal death is mediated through activation of NMDARs. Thirdly, treatment of hippocampal cultures with both NMDA and acidic ECS induced greater degrees of cell deaths than either NMDA or acidic ECS treatment alone. These results suggest that ASIC1a activation up-regulates NMDAR function. Additional data supporting the functional relationship between ASIC1a and NMDAR are found in our electrophysiology experiments in hippocampal slices, where stimulation of ASIC1a induced a marked increase in NMDAR EPSC amplitude, and inhibition of ASIC1a resulted in a decrease in NMDAR EPSC amplitude. In summary, we present evidence that ASIC1a activity facilitates NMDAR function and exacerbates NMDAR-mediated neuronal death in pathological conditions. These findings are invaluable to the search for novel therapeutic targets in the treatment of brain ischemia. PMID:25947342

  17. A fast, low power and low noise charge sensitive amplifier ASIC for a UV imaging single photon detector

    NASA Astrophysics Data System (ADS)

    Seljak, A.; Cumming, H. S.; Varner, G.; Vallerga, J.; Raffanti, R.; Virta, V.

    2017-04-01

    NASA has funded, through their Strategic Astrophysics Technology (SAT) program, the development of a cross strip (XS) microchannel plate (MCP) detector with the intention to increase its technology readiness level (TRL), enabling prototyping for future NASA missions. One aspect of the development is to convert the large and high powered laboratory Parallel Cross Strip (PXS) readout electronics into application specific integrated circuits (ASICs) to decrease their mass, volume, and power consumption (all limited resources in space) and to make them more robust to the environments of rocket launch and space. The redesign also foresees to increase the overall readout event rate, and decrease the noise contribution of the readout system. This work presents the design and verification of the first stage for the new readout system, the 16 channel charge sensitive amplifier ASIC, called the CSAv3. The single channel amplifier is composed of a charge sensitive amplifier (pre-amplifier), a pole zero cancellation circuit and a shaping amplifier. An additional output stage buffer allows polarity selection of the output analog signal. The operation of the amplifier is programmable via serial bus. It provides an equivalent noise charge (ENC) of around 600 e^- and a baseline gain of 10 mV/fC. The full scale pulse shaped output signal is confined within 100 ns, without long recovery tails, enabling up to 10 MHz periodic event rates without signal pile up. This ASIC was designed and fabricated in 130 nm, TSMC CMOS 1.2 V technology. In addition, we briefly discuss the construction of the readout system and plans for the future work.

  18. Delay locked loop integrated circuit.

    SciTech Connect

    Brocato, Robert Wesley

    2007-10-01

    This report gives a description of the development of a Delay Locked Loop (DLL) integrated circuit (IC). The DLL was developed and tested as a stand-alone IC test chip to be integrated into a larger application specific integrated circuit (ASIC), the Quadrature Digital Waveform Synthesizer (QDWS). The purpose of the DLL is to provide a digitally programmable delay to enable synchronization between an internal system clock and external peripherals with unknown clock skew. The DLL was designed and fabricated in the IBM 8RF process, a 0.13 {micro}m CMOS process. It was designed to operate with a 300MHz clock and has been tested up to 500MHz.

  19. Integral Battery Power Limiting Circuit for Intrinsically Safe Applications

    NASA Technical Reports Server (NTRS)

    Burns, Bradley M.; Blalock, Norman N.

    2010-01-01

    A circuit topology has been designed to guarantee the output of intrinsically safe power for the operation of electrical devices in a hazardous environment. This design uses a MOSFET (metal oxide semiconductor field-effect transistor) as a switch to connect and disconnect power to a load. A test current is provided through a separate path to the load for monitoring by a comparator against a preset threshold level. The circuit is configured so that the test current will detect a fault in the load and open the switch before the main current can respond. The main current passes through the switch and then an inductor. When a fault occurs in the load, the current through the inductor cannot change immediately, but the voltage drops immediately to safe levels. The comparator detects this drop and opens the switch before the current in the inductor has a chance to respond. This circuit protects both the current and voltage from exceeding safe levels. Typically, this type of protection is accomplished by a fuse or a circuit breaker, but in order for a fuse or a circuit breaker to blow or trip, the current must exceed the safe levels momentarily, which may be just enough time to ignite anything in a hazardous environment. To prevent this from happening, a fuse is typically current-limited by the addition of the resistor to keep the current within safe levels while the fuse reacts. The use of a resistor is acceptable for non-battery applications where the wasted energy and voltage drop across the resistor can be tolerated. The use of the switch and inductor minimizes the wasted energy. For example, a circuit runs from a 3.6-V battery that must be current-limited to 200 mA. If the circuit normally draws 10 mA, then an 18-ohm resistor would drop 180 mV during normal operation, while a typical switch (0.02 ohm) and inductor (0.97 ohm) would only drop 9.9 mV. From a power standpoint, the current-limiting resistor protection circuit wastes about 18 times more power than the

  20. Trends in integrated circuit design for particle physics experiments

    NASA Astrophysics Data System (ADS)

    Atkin, E. V.

    2017-01-01

    Integrated circuits are one of the key complex units available to designers of multichannel detector setups. A whole number of factors makes Application Specific Integrated Circuits (ASICs) valuable for Particle Physics and Astrophysics experiments. Among them the most important ones are: integration scale, low power dissipation, radiation tolerance. In order to make possible future experiments in the intensity, cosmic, and energy frontiers today ASICs should provide new level of functionality at a new set of constraints and trade-offs, like low-noise high-dynamic range amplification and pulse shaping, high-speed waveform sampling, low power digitization, fast digital data processing, serialization and data transmission. All integrated circuits, necessary for physical instrumentation, should be radiation tolerant at an earlier not reached level (hundreds of Mrad) of total ionizing dose and allow minute almost 3D assemblies. The paper is based on literary source analysis and presents an overview of the state of the art and trends in nowadays chip design, using partially own ASIC lab experience. That shows a next stage of ising micro- and nanoelectronics in physical instrumentation.

  1. Acid-Sensing Ion Channel 2a (ASIC2a) Promotes Surface Trafficking of ASIC2b via Heteromeric Assembly

    PubMed Central

    Kweon, Hae-Jin; Kim, Dong-Il; Bae, Yeonju; Park, Jae-Yong; Suh, Byung-Chang

    2016-01-01

    Acid-sensing ion channels (ASICs) are proton-activated cation channels that play important roles as typical proton sensors during pathophysiological conditions and normal synaptic activities. Among the ASIC subunits, ASIC2a and ASIC2b are alternative splicing products from the same gene, ACCN1. It has been shown that ASIC2 isoforms have differential subcellular distribution: ASIC2a targets the cell surface by itself, while ASIC2b resides in the ER. However, the underlying mechanism for this differential subcellular localization remained to be further elucidated. By constructing ASIC2 chimeras, we found that the first transmembrane (TM1) domain and the proximal post-TM1 domain (17 amino acids) of ASIC2a are critical for membrane targeting of the proteins. We also observed that replacement of corresponding residues in ASIC2b by those of ASIC2a conferred proton-sensitivity as well as surface expression to ASIC2b. We finally confirmed that ASIC2b is delivered to the cell surface from the ER by forming heteromers with ASIC2a, and that the N-terminal region of ASIC2a is additionally required for the ASIC2a-dependent membrane targeting of ASIC2b. Together, our study supports an important role of ASIC2a in membrane targeting of ASIC2b. PMID:27477936

  2. AMPLITUDE AND TIME MEASUREMENT ASIC WITH ANALOG DERANDOMIZATION.

    SciTech Connect

    O CONNOR,P.; DE GERONIMO,G.; KANDASAMY,A.

    2002-11-10

    We describe a new ASIC for accurate and efficient processing of high-rate pulse signals from highly segmented detectors. In contrast to conventional approaches, this circuit affords a dramatic reduction in data volume through the use of analog techniques (precision peak detectors and time-to-amplitude converters) together with fast arbitration and sequencing logic to concentrate the data before digitization. In operation the circuit functions like a data-driven analog first-in, first-out (FIFO) memory between the preamplifiers and the ADC. Peak amplitudes of pulses arriving at any one of the 32 inputs are sampled, stored, and queued for readout and digitization through a single output port. Hit timing, pulse risetime, and channel address are also available at the output. Prototype chips have been fabricated in 0.35 micron CMOS and tested. First results indicate proper functionality for pulses down to 30 ns peaking time and input rates up to 1.6 MHz/channel. Amplitude accuracy of the peak detect and hold circuit is 0.3% (absolute). TAC accuracy is within 0.3% of full scale. Power consumption is less than 2 mW/channel. Compared with conventional techniques such as track-and-hold and analog memory, this new ASIC will enable efficient pulse height measurement at 20 to 300 times higher rates.

  3. Transient recovery voltage considerations in the application of medium voltage circuit breakers

    SciTech Connect

    Swindler, D.L.; Schwartz, P.; Hamer, P.S.; Lambert, S.R.

    1995-12-31

    Medium Voltage Circuit Breakers can fail to interrupt 3-phase fault currents when power systems have Transient Recovery Voltage (TRV) characteristics which exceed the rating of the circuit breaker. This paper examines the application of 13.8kV generation and load switchgear for an oil refinery in which circuit parameters as originally designed would have exceeded the 13.8kV circuit breakers TRV ratings had corrective measures not been taken. This paper illustrates this case and discusses the basis of TRV, how TRV is assessed, and alternative actions taken to bring circuits to within the 13.8 kV circuit breaker ratings.

  4. STAR cluster-finder ASIC

    SciTech Connect

    Botlo, M.; LeVine, M.J.; Scheetz, R.A.

    1997-12-31

    The STAR experiment reads out a TPC and an SVT (silicon vertex tracker), both of which require in-line pedestal subtraction, compression of ADC values from 10-bit to 8-bit, and location of time sequences representing responses to charged-particle tracks. The STAR cluster finder ASIC responds to all of these needs. Pedestal subtraction and compression are performed using lookup tables in attached RAM. We describe its design and implementation, as well as testing methodology and results of tests performed on foundry prototypes.

  5. A demonstration of CMOS VLSI circuit prototyping in support of the site facility using the 1.2 micron standard cell library developed by National Security Agency

    NASA Technical Reports Server (NTRS)

    Smith, Edwyn D.

    1991-01-01

    Two silicon CMOS application specific integrated circuits (ASICs), a data generation chip, and a data checker chip were designed. The conversion of the data generator circuitry into a pair of CMOS ASIC chips using the 1.2 micron standard cell library is documented. The logic design of the data checker is discussed. The functions of the control circuitry is described. An accurate estimate of timing relationships is essential to make sure that the logic design performs correctly under practical conditions. Timing and delay information are examined.

  6. Advanced polymer systems for optoelectronic integrated circuit applications

    NASA Astrophysics Data System (ADS)

    Eldada, Louay A.; Stengel, Kelly M. T.; Shacklette, Lawrence W.; Norwood, Robert A.; Xu, Chengzeng; Wu, Chengjiu; Yardley, James T.

    1997-01-01

    An advanced versatile low-cost polymeric waveguide technology is proposed for optoelectronic integrated circuit applications. We have developed high-performance organic polymeric materials that can be readily made into both multimode and single-mode optical waveguide structures of controlled numerical aperture (NA) and geometry. These materials are formed from highly crosslinked acrylate monomers with specific linkages that determine properties such as flexibility, toughness, loss, and stability against yellowing and humidity. These monomers are intermiscible, providing for precise adjustment of the refractive index from 1.30 to 1.60. Waveguides are formed photolithographically, with the liquid monomer mixture polymerizing upon illumination in the UV via either mask exposure or laser direct-writing. A wide range of rigid and flexible substrates can be used, including glass, quartz, oxidized silicon, glass-filled epoxy printed circuit board substrate, and flexible polyimide film. We discuss the use of these materials on chips and on multi-chip modules (MCMs), specifically in transceivers where we adaptively produced waveguides on vertical-cavity surface-emitting lasers (VCSELs) embedded in transmitter MCMs and on high- speed photodetector chips in receiver MCMs. Light coupling from and to chips is achieved by cutting 45 degree mirrors using excimer laser ablation. The fabrication of our polymeric structures directly on the modules provides for stability, ruggedness, and hermeticity in packaging.

  7. A front-end ASIC design for non-uniformity correction

    NASA Astrophysics Data System (ADS)

    Shen, X.; Ding, R. J.; Lin, J. M.; Liu, F.

    2008-12-01

    A front-end design of an ASIC that implements calibration and correction for IRFPA non-uniformity is presented. An algorithm suitable for ASIC implementation is introduced, and one kind of architecture that implements this algorithm has been designed. We map the architecture to TSMC 0.25um process. After evaluating the chip area and operation speed, we confirm that this architect will also be effective when the FPA scale in enlarged to 1Kby1K. Finally the flow of circuit implementation and method of verification are introduced briefly.

  8. Integrated input protection against discharges for Micro Pattern Gas Detectors readout ASICs

    NASA Astrophysics Data System (ADS)

    Fiutowski, T.; Dąbrowski, W.; Koperny, S.; Wiącek, P.

    2017-02-01

    Immunity against possible random discharges inside active detector volume of MPGDs is one of the key aspects that should be addressed in the design of the front-end electronics. This issue becomes particularly critical for systems with high channel counts and high density readout employing the front-end electronics built as multichannel ASICs implemented in modern CMOS technologies, for which the breakdown voltages are in the range of a few Volts. The paper presents the design of various input protection structures integrated in the ASIC manufactured in a 350 nm CMOS process and test results using an electrical circuit to mimic discharges in the detectors.

  9. Extending the Constrained Random Simulation Methodology into Physical Device Verification for Processor-Based ASICs

    DTIC Science & Technology

    2016-03-17

    Integrity Software Systems , Dept.02622 Sandia National Laboratories Albuquerque, New Mexico 87185 USA alschre@sandia.gov Melissa N. Wirtz Embedded ...hardware is a desired goal of ASIC and system designers . One method of achieving this goal is possible with processor-based ASICs. By converting the random...in three different embedded processing applications, each with unique interface requirements and has successfully passed all system tests to date

  10. Analog front-end design of the STS/MUCH-XYTER2—full size prototype ASIC for the CBM experiment

    NASA Astrophysics Data System (ADS)

    Kleczek, Rafal

    2017-01-01

    The design of the analog front-end of the STS/MUCH-XYTER2 ASIC, a full-size prototype chip for the Silicon Tracking System (STS, based on double-sided silicon strip sensors) and Muon Chamber (MUCH, based on gas sensors) detectors is presented. The ASIC contains 128 charge processing channels, each built of a charge sensitive amplifier, a polarity selection circuit and two pulse shaping amplifiers forming two parallel signal paths. The first path is used for timing measurement with a fast discriminator. The second path allows low-noise amplitude measurement with a 5-bit continuous-time flash ADC. Different operating conditions and constraints posed by two target detectors' applications require front-end electronics flexibility to meet extended system-wise requirements. The presented circuit implements switchable shaper peaking time, gain switching and trimming, input amplifier pulsed reset circuit, fail-safe measures. The power consumption is scalable (for the STS and the MUCH modes), but limited to 10 mW/channel.

  11. BAE Systems Radiation Hardened SpaceWire ASIC and Roadmap

    NASA Technical Reports Server (NTRS)

    Berger, Richard; Milliser, Myrna; Kapcio, Paul; Stanley, Dan; Moser, David; Koehler, Jennifer; Rakow, Glenn; Schnurr, Richard

    2006-01-01

    An Application Specific Integrated Circuit (ASIC) that implements the SpaceWire protocol has been developed in a radiation hardened 0.25 micron CMOS, technology. This effort began in March 2003 as a joint development between the NASA Goddard Space Flight Center (GSFC) and BAE Systems. The BAE Systems SpaceWire ASlC is comprised entirely of reusable core elements, many of which are already flight-proven. It incorporates a 4-port SpaceWire router with two local ports, dual PC1 bus interfaces, a microcontroller, 32KB of internal memory, -and a memory controller for additional external memory use. The SpaceWire ASlC is planned for use on both the Geostationary Operational Environmental Satellites (GOES)-R and the Lunar Reconnaissance Orbiter (LRO). Engineering parts have already been delivered to both programs. This paper discusses the SpaceWire protocol and those elements of it that have been built into the current SpaceWire reusable core. There are features within the core that go beyond the current standard that can be enabled or disabled by the user and these will be described. The adaptation of SpaceWire to BAE Systems' On Chip Bus (OCB) for compatibility with the other reusable cores will be discussed. Optional configurations within user systems will be shown. The physical imp!ementation of the design will be described and test results from the hardware will be discussed. Finally, the BAE Systems roadmap for SpaceWire developments will be discussed, including some products already in design as well as longer term plans.

  12. Rethinking ASIC design with next generation lithography and process integration

    NASA Astrophysics Data System (ADS)

    Vaidyanathan, Kaushik; Liu, Renzhi; Liebmann, Lars; Lai, Kafai; Strojwas, Andrzej; Pileggi, Larry

    2013-03-01

    Given the deployment delays for EUV, several next generation lithography (NGL) options are being actively researched. Several cost-effective NGL solutions, such as self-aligned double patterning through sidewall image transfer (SIT) and directed self-assembly (DSA), in conjunction with process integration challenges, mandate grating-like pattern design. As part of the GRATEdd project, we have evaluated the design cost of grating-based design for ASICs (application specific ICs). Based on our observations we have engineered fundamental changes to the primary ASIC design components to make scaling affordable and useful in deeply scaled sub-20 nm technologies: unidirectional-M1 based standard cells, application-specific smart SRAM synthesis, and statistical and self-healing analog design.

  13. Hybrid planar lightwave circuits for defense and aerospace applications

    NASA Astrophysics Data System (ADS)

    Zhang, Hua; Bidnyk, Serge; Yang, Shiquan; Balakrishnan, Ashok; Pearson, Matt; O'Keefe, Sean

    2010-04-01

    We present innovations in Planar Lightwave Circuits (PLCs) that make them ideally suited for use in advanced defense and aerospace applications. We discuss PLCs that contain no micro-optic components, no moving parts, pose no spark or fire hazard, are extremely small and lightweight, and are capable of transporting and processing a range of optical signals with exceptionally high performance. This PLC platform is designed for on-chip integration of active components such as lasers and detectors, along with transimpedance amplifiers and other electronics. These active components are hybridly integrated with our silica-on-silicon PLCs using fully-automated robotics and image recognition technology. This PLC approach has been successfully applied to the design and fabrication of multi-channel transceivers for aerospace applications. The chips contain hybrid DFB lasers and high-efficiency detectors, each capable of running over 10 Gb/s, with mixed digital and analog traffic multiplexed to a single optical fiber. This highlyintegrated functionality is combined onto a silicon chip smaller than 4 x 10 mm, weighing < 5 grams. These chip-based transceivers have been measured to withstand harsh g-forces, including sinusoidal vibrations with amplitude of 20 g acceleration, followed by mechanical shock of 500 g acceleration. The components operate over a wide range of temperatures, with no device failures after extreme temperature cycling through a range of > 125 degC, and more than 2,000 hours operating at 95 degC ambient air temperature. We believe that these recent advancements in planar lightwave circuits are poised to revolutionize optical communications and interconnects in the aerospace and defense industries.

  14. A 64-channel readout ASIC for nanowire biosensor array with electrical calibration scheme.

    PubMed

    Chai, Kevin T C; Choe, Kunil; Bernal, Olivier D; Gopalakrishnan, Pradeep K; Zhang, Guo-Jun; Kang, Tae Goo; Je, Minkyu

    2010-01-01

    A 1.8-mW, 18.5-mm(2) 64-channel current readout ASIC was implemented in 0.18-µm CMOS together with a new calibration scheme for silicon nanowire biosensor arrays. The ASIC consists of 64 channels of dedicated readout and conditioning circuits which incorporate correlated double sampling scheme to reduce the effect of 1/f noise and offset from the analog front-end. The ASIC provides a 10-bit digital output with a sampling rate of 300 S/s whilst achieving a minimum resolution of 7 pA(rms). A new electrical calibration method was introduced to mitigate the issue of large variations in the nano-scale sensor device parameters and optimize the sensor sensitivity. The experimental results show that the proposed calibration technique improved the sensitivity by 2 to 10 times and reduced the variation between dataset by 9 times.

  15. Science Enabling ASICs and FEEs for the JUICE and JEO Missions

    NASA Technical Reports Server (NTRS)

    Paschalidis, Nicholas; Sittler, Ed; Cooper, John; Christian, Eric; Moore, Tom

    2011-01-01

    A family of science enabling radiation hard Application Specific Integrated Circuits (ASICs), Front End Electronics (FEEs) and Event Processing Systems, with flight heritage on many NASA missions, is presented. These technologies play an important role in the miniaturization of instruments -and spacecraft systems- at the same time increasing performance and reducing power. The technologies target time of flight, position sensing, and energy measurements as well as standard housekeeping and telemetry functions for particle and fields instruments, but find applications in other instrument categories too. More specifically the technologies include: the TOF chip, 1D and 2D Delay Lines with MCP detectors, for high precision fast and low power time of flight and position sensing; the Energy chip for multichannel SSD readout with time over threshold and standard voltage read out for TDC and ADC digitization; Fast multi channel read out chip with commandable thresholds; the TRIO chip for multiplexed ADC and housekeeping etc. It should be mentioned that the ASICs include basic trigger capabilities to enable random event processing in a heavy background of penetrators and UV foreground. Typical instruments include time of flight versus energy and look angle particle analyzers such as: plasma composition, energetic particle, neutral atom imaging as well as fast plasma and deltaE/E ion/electron telescopes. Flight missions include: Cassini/LEMMS, IMAGE/HENA, MESSENGER/EPPS/MLA/X-ray/MLA, STEREO, PLUTO-NH/PEPSSI/LORI, IBEX-Lo, JUNO/JEDI, RBSP/RBSPICE, MMS/HPCA/EPD, SO/SIS. Given the proven capability on heavy radiation missions such as JUNO, MMS and RBSB, as well diverse long duration missions such as MESSENGER, PLUTO and Cassini, it is expected that these technologies will play an important role in the particle and fields (at least) instruments on the upcoming JUICE and JEO missions.

  16. Design and fabrication of an infrared optical pyrometer ASIC as a diagnostic for shock physics experiments

    NASA Astrophysics Data System (ADS)

    Gordon, Jared

    Optical pyrometry is the sensing of thermal radiation emitted from an object using a photoconductive device to convert photons into electrons, and is an important diagnostic tool in shock physics experiments. Data obtained from an optical pyrometer can be used to generate a blackbody curve of the material prior to and after being shocked by a high speed projectile. The sensing element consists of an InGaAs photodiode array, biasing circuitry, and multiple transimpedance amplifiers to boost the weak photocurrent from the noisy dark current into a signal that can eventually be digitized. Once the circuit elements have been defined, more often than not commercial-off-the-shelf (COTS) components are inadequate to satisfy every requirement for the diagnostic, and therefore a custom application specific design has to be considered. This thesis outlines the initial challenges with integrating the photodiode array block with multiple COTS transimpedance amplifiers onto a single chip, and offers a solution to a comparable optical pyrometer that uses the same type of photodiodes in conjunction with a re-designed transimpedance amplifier integrated onto a single chip. The final design includes a thorough analysis of the transimpedance amplifier along with modeling the circuit behavior which entails schematics, simulations, and layout. An alternative circuit is also investigated that incorporates an approach to multiplex the signals from each photodiode onto one data line and not only increases the viable real estate on the chip, but also improves the behavior of the photodiodes as they are subjected to less thermal load. The optical pyrometer application specific integrated circuit (ASIC) for shock physic experiments includes a transimpedance amplifier (TIA) with a 100 kΩ gain operating at bandwidth of 30 MHz, and an input-referred noise RMS current of 50 nA that is capable of driving a 50 Ω load.

  17. ASIC for high-speed-gating and free running operation of SPADs

    NASA Astrophysics Data System (ADS)

    Rochas, Alexis; Guillaume-Gentil, Christophe; Gautier, Jean-Daniel; Pauchard, Alexandre; Ribordy, Gregoire; Zbinden, Hugo; Leblebici, Yusuf; Monat, Laurent

    2007-05-01

    Single photon detection at telecom wavelengths is of importance in many industrial applications ranging from quantum cryptography, quantum optics, optical time domain reflectometry, non-invasive testing of VLSI circuits, eye-safe LIDAR to laser ranging. In practical applications, the combination of an InGaAs/InP APD with an appropriate electronic circuit still stands as the best solution in comparison with emerging technologies such as superconducting single photon detectors, MCP-PMTs for the near IR or up-conversion technique. An ASIC dedicated to the operation of InGaAs/InP APDs in both gated mode and free-running mode is presented. The 1.6mm2 chip is fabricated in a CMOS technology. It combines a gate generator, a voltage limiter, a fast comparator, a precise timing circuit for the gate signal processing and an output stage. A pulse amplitude of up to +7V can be achieved, which allows the operation of commercially available APDs at a single photon detection probability larger than 25% at 1.55μm. The avalanche quenching process is extremely fast, thus reducing the afterpulsing effects. The packaging of the diode in close proximity with the quenching circuit enables high speed gating at frequencies larger than 10MHz. The reduced connection lengths combined with impedance adaptation technique provide excellent gate quality, free of oscillations or bumps. The excess bias voltage is thus constant over the gate width leading to a stable single photon detection probability and timing resolution. The CMOS integration guarantees long-term stability, reliability and compactness.

  18. A design of a valid signal selecting and position decoding ASIC for PET using silicon photomultipliers

    NASA Astrophysics Data System (ADS)

    Cho, M.; Lim, K.-t.; Kim, H.; Yeom, J.-y.; Kim, J.; Lee, C.; Choi, H.; Cho, G.

    2017-01-01

    In most cases, a PET system has numerous electrical components and channel circuits and thus it would rather be a bulky product. Also, most existing systems receive analog signals from detectors which make them vulnerable to signal distortions. For these reasons, channel reduction techniques are important. In this work, an ASIC for PET module is being proposed. An ASIC chip for 16 PET detector channels, VSSPDC, has been designed and simulated. The main function of the chip is 16-to-1 channel reduction, i.e., finding the position of only the valid signals, signal timing, and magnitudes in all 16 channels at every recorded event. The ASIC comprises four of 4-channel modules and a 2nd 4-to-1 router. A single channel module comprises a transimpedance amplifier for the silicon photomultipliers, dual comparators with high and low level references, and a logic circuitry. While the high level reference was used to test the validity of the signal, the low level reference was used for the timing. The 1-channel module of the ASIC produced an energy pulse by time-over-threshold method and it also produced a time pulse with a fixed delayed time. Since the ASIC chip outputs only a few digital pulses and does not require an external clock, it has an advantage over noise properties. The cadence simulation showed the good performance of the chip as designed.

  19. ASIC or PIC? Implantable stimulators based on semi-custom CMOS technology or low-power microcontroller architecture.

    PubMed

    Salmons, S; Gunning, G T; Taylor, I; Grainger, S R; Hitchings, D J; Blackhurst, J; Jarvis, J C

    2001-01-01

    To gain a better understanding of the effects of chronic stimulation on mammalian muscles we needed to generate patterns of greater variety and complexity than simple constant-frequency or burst patterns. We describe here two approaches to the design of implantable neuromuscular stimulators that can satisfy these requirements. Devices of both types were developed and used in long-term experiments. The first device was based on a semi-custom Application Specific Integrated Circuit (ASIC). This approach has the advantage that the circuit can be completely tested at every stage of development and production, assuring a high degree of reliability. It has the drawback of inflexibility: the patterns are produced by state machines implemented in silicon, so each new set of patterns requires a fresh production run, which is costly and time-consuming. The second device was based on a commercial microcontroller (Microchip PIC16C84). The functionality of this type of circuit is specified in software rather than in silicon hardware, allowing a single device to be programmed for different functions. With the use of features designed to improve fault-tolerance we found this approach to be as reliable as that based on ASICs. The encapsulated devices can easily be accommodated subcutaneously on the flank of a rabbit and a recent version is small enough to implant into the peritoneal cavity of rats. The current devices are programmed with a predetermined set of 12 patterns before assembly; the desired pattern is selected after implantation with an electronic flash gun. The operating current drain is less than 40 microA.

  20. High Rate Digital Demodulator ASIC

    NASA Technical Reports Server (NTRS)

    Ghuman, Parminder; Sheikh, Salman; Koubek, Steve; Hoy, Scott; Gray, Andrew

    1998-01-01

    The architecture of High Rate (600 Mega-bits per second) Digital Demodulator (HRDD) ASIC capable of demodulating BPSK and QPSK modulated data is presented in this paper. The advantages of all-digital processing include increased flexibility and reliability with reduced reproduction costs. Conventional serial digital processing would require high processing rates necessitating a hardware implementation in other than CMOS technology such as Gallium Arsenide (GaAs) which has high cost and power requirements. It is more desirable to use CMOS technology with its lower power requirements and higher gate density. However, digital demodulation of high data rates in CMOS requires parallel algorithms to process the sampled data at a rate lower than the data rate. The parallel processing algorithms described here were developed jointly by NASA's Goddard Space Flight Center (GSFC) and the Jet Propulsion Laboratory (JPL). The resulting all-digital receiver has the capability to demodulate BPSK, QPSK, OQPSK, and DQPSK at data rates in excess of 300 Mega-bits per second (Mbps) per channel. This paper will provide an overview of the parallel architecture and features of the HRDR ASIC. In addition, this paper will provide an over-view of the implementation of the hardware architectures used to create flexibility over conventional high rate analog or hybrid receivers. This flexibility includes a wide range of data rates, modulation schemes, and operating environments. In conclusion it will be shown how this high rate digital demodulator can be used with an off-the-shelf A/D and a flexible analog front end, both of which are numerically computer controlled, to produce a very flexible, low cost high rate digital receiver.

  1. Mathematical modelling of fractional order circuit elements and bioimpedance applications

    NASA Astrophysics Data System (ADS)

    Moreles, Miguel Angel; Lainez, Rafael

    2017-05-01

    In this work a classical derivation of fractional order circuits models is presented. Generalised constitutive equations in terms of fractional Riemann-Liouville derivatives are introduced in the Maxwell's equations for each circuit element. Next the Kirchhoff voltage law is applied in a RCL circuit configuration. It is shown that from basic properties of Fractional Calculus, a fractional differential equation model with Caputo derivatives is obtained. Thus standard initial conditions apply. Finally, models for bioimpedance are revisited.

  2. Application of telecom planar lightwave circuits for homeland security sensing

    NASA Astrophysics Data System (ADS)

    Veldhuis, Gert J.; Elders, Job; van Weerden, Harm; Amersfoort, Martin

    2004-03-01

    Over the past decade, a massive effort has been made in the development of planar lightwave circuits (PLCs) for application in optical telecommunications. Major advances have been made, on both the technological and functional performance front. Highly sophisticated software tools that are used to tailor designs to required functional performance support these developments. In addition extensive know-how in the field of packaging, testing, and failure mode and effects analysis (FMEA) has been built up in the struggle for meeting the stringent Telcordia requirements that apply to telecom products. As an example, silica-on-silicon is now a mature technology available at several industrial foundries around the world, where, on the performance front, the arrayed-waveguide grating (AWG) has evolved into an off-the-shelf product. The field of optical chemical-biological (CB) sensors for homeland security application can greatly benefit from the advances as described above. In this paper we discuss the currently available technologies, device concepts, and modeling tools that have emerged from the telecommunications arena and that can effectively be applied to the field of homeland security. Using this profound telecom knowledge base, standard telecom components can readily be tailored for detecting CB agents. Designs for telecom components aim at complete isolation from the environment to exclude impact of environmental parameters on optical performance. For sensing applications, the optical path must be exposed to the measurand, in this area additional development is required beyond what has already been achieved in telecom development. We have tackled this problem, and are now in a position to apply standard telecom components for CB sensing. As an example, the application of an AWG as a refractometer is demonstrated, and its performance evaluated.

  3. An array of virtual Frisch-grid CdZnTe detectors and a front-end application-specific integrated circuit for large-area position-sensitive gamma-ray cameras.

    PubMed

    Bolotnikov, A E; Ackley, K; Camarda, G S; Cherches, C; Cui, Y; De Geronimo, G; Fried, J; Hodges, D; Hossain, A; Lee, W; Mahler, G; Maritato, M; Petryk, M; Roy, U; Salwen, C; Vernon, E; Yang, G; James, R B

    2015-07-01

    We developed a robust and low-cost array of virtual Frisch-grid CdZnTe detectors coupled to a front-end readout application-specific integrated circuit (ASIC) for spectroscopy and imaging of gamma rays. The array operates as a self-reliant detector module. It is comprised of 36 close-packed 6 × 6 × 15 mm(3) detectors grouped into 3 × 3 sub-arrays of 2 × 2 detectors with the common cathodes. The front-end analog ASIC accommodates up to 36 anode and 9 cathode inputs. Several detector modules can be integrated into a single- or multi-layer unit operating as a Compton or a coded-aperture camera. We present the results from testing two fully assembled modules and readout electronics. The further enhancement of the arrays' performance and reduction of their cost are possible by using position-sensitive virtual Frisch-grid detectors, which allow for accurate corrections of the response of material non-uniformities caused by crystal defects.

  4. An array of virtual Frisch-grid CdZnTe detectors and a front-end application-specific integrated circuit for large-area position-sensitive gamma-ray cameras

    SciTech Connect

    Bolotnikov, A. E. Ackley, K.; Camarda, G. S.; Cherches, C.; Cui, Y.; De Geronimo, G.; Fried, J.; Hossain, A.; Mahler, G.; Maritato, M.; Roy, U.; Salwen, C.; Vernon, E.; Yang, G.; James, R. B.; Hodges, D.; Lee, W.; Petryk, M.

    2015-07-15

    We developed a robust and low-cost array of virtual Frisch-grid CdZnTe detectors coupled to a front-end readout application-specific integrated circuit (ASIC) for spectroscopy and imaging of gamma rays. The array operates as a self-reliant detector module. It is comprised of 36 close-packed 6 × 6 × 15 mm{sup 3} detectors grouped into 3 × 3 sub-arrays of 2 × 2 detectors with the common cathodes. The front-end analog ASIC accommodates up to 36 anode and 9 cathode inputs. Several detector modules can be integrated into a single- or multi-layer unit operating as a Compton or a coded-aperture camera. We present the results from testing two fully assembled modules and readout electronics. The further enhancement of the arrays’ performance and reduction of their cost are possible by using position-sensitive virtual Frisch-grid detectors, which allow for accurate corrections of the response of material non-uniformities caused by crystal defects.

  5. Software solution for autonomous observations with H2RG detectors and SIDECAR ASICs for the RATIR camera

    NASA Astrophysics Data System (ADS)

    Klein, Christopher R.; Kubánek, Petr; Butler, Nathaniel R.; Fox, Ori D.; Kutyrev, Alexander S.; Rapchun, David A.; Bloom, Joshua S.; Farah, Alejandro; Gehrels, Neil; Georgiev, Leonid; González, J. Jesús; Lee, William H.; Lotkin, Gennadiy N.; Moseley, Samuel H.; Prochaska, J. Xavier; Ramirez-Ruiz, Enrico; Richer, Michael G.; Robinson, Frederick D.; Román-Zúñiga, Carlos; Samuel, Mathew V.; Sparr, Leroy M.; Tucker, Corey; Watson, Alan M.

    2012-07-01

    The Reionization And Transients InfraRed (RATIR) camera has been built for rapid Gamma-Ray Burst (GRB) followup and will provide quasi-simultaneous imaging in ugriZY JH. The optical component uses two 2048 × 2048 pixel Finger Lakes Imaging ProLine detectors, one optimized for the SDSS u, g, and r bands and one optimized for the SDSS i band. The infrared portion incorporates two 2048 × 2048 pixel Teledyne HgCdTe HAWAII-2RG detectors, one with a 1.7-micron cutoff and one with a 2.5-micron cutoff. The infrared detectors are controlled by Teledyne's SIDECAR (System for Image Digitization Enhancement Control And Retrieval) ASICs (Application Specific Integrated Circuits). While other ground-based systems have used the SIDECAR before, this system also utilizes Teledyne's JADE2 (JWST ASIC Drive Electronics) interface card and IDE (Integrated Development Environment). Here we present a summary of the software developed to interface the RATIR detectors with Remote Telescope System, 2nd Version (RTS2) software. RTS2 is an integrated open source package for remote observatory control under the Linux operating system and will autonomously coordinate observatory dome, telescope pointing, detector, filter wheel, focus stage, and dewar vacuum compressor operations. Where necessary we have developed custom interfaces between RTS2 and RATIR hardware, most notably for cryogenic focus stage motor drivers and temperature controllers. All detector and hardware interface software developed for RATIR is freely available and open source as part of the RTS2 distribution.

  6. Design of beam steering electronic circuits for medical applications

    NASA Astrophysics Data System (ADS)

    Safar, Mohammad A. A. A.

    This thesis deals with the theory and design of a hemispherical antenna array circuit that is capable to operate in the intermediate zones. By doing that, this array can be used in Hyperthermia Treatment for Brain Cancer in which the aim is to noninvasively focus the fields at microwave frequencies to the location of the tumor cells in the brain. Another possible application of the array is to offer an alternative means of sustaining Deep Brain Stimulation other than using the traditional (surgical) approach. The new noninvasive technique is accomplished by the use of a hemispherical antenna array placed on the human's head. The array uses a new beamforming technique that achieves 3 dimensional beamforming or focusing of the magnetic field of antennas to desired points in the brain to achieve either cell death by temperature rise (Hyperthermia Application) or to cause brain stimulation and hopefully alleviate the affects of Parkinson's Disease (Deep Brain Stimulation). The main obstacle in this design was that the far field approximation that is usually used when designing antenna arrays does not apply in this case since the hemispherical array is in close proximity to where the magnetic field is desired to be focused. The antenna array problem is approached as a boundary-valued problem with the human head being modeled as a three layered hemisphere. The exact expressions for electromagnetic fields are derived. Health issues such as electric field exposure and specific absorption rate (SAR) are considered. After developing the main antenna and beamforming theory, a neural network is designed to accomplish the beamforming technique used. The radio-frequency (RF) transmitter was designed to transmit the fields at a frequency of 1.8 GHz. The antenna array can also be used as a receiver. The antenna and beamforming theory is presented. A new reception technique is shown which enables the array to receive multiple magnetic field sources from within the hemispherical

  7. Practical applications of digital integrated circuits. Part 3: Practical sequential theory and synchronous circuits

    NASA Technical Reports Server (NTRS)

    1973-01-01

    Here, the 7400 line of transistor to transistor logic (TTL) devices is emphasized almost exclusively where hardware is concerned. However, it should be noted that the logic theory contained herein applies to all hardware. Discussed here are synchronous binary UP counters, synchronous DOWN and UP/DOWN counters, integrated circuit counters, shift registers, sequential techniques, and designing sequential counting machines.

  8. Development of the analog ASIC for multi-channel readout X-ray CCD camera

    NASA Astrophysics Data System (ADS)

    Nakajima, Hiroshi; Matsuura, Daisuke; Idehara, Toshihiro; Anabuki, Naohisa; Tsunemi, Hiroshi; Doty, John P.; Ikeda, Hirokazu; Katayama, Haruyoshi; Kitamura, Hisashi; Uchihori, Yukio

    2011-03-01

    We report on the performance of an analog application-specific integrated circuit (ASIC) developed aiming for the front-end electronics of the X-ray CCD camera system onboard the next X-ray astronomical satellite, ASTRO-H. It has four identical channels that simultaneously process the CCD signals. Distinctive capability of analog-to-digital conversion enables us to construct a CCD camera body that outputs only digital signals. As the result of the front-end electronics test, it works properly with low input noise of ≤30μV at the pixel rate below 100 kHz. The power consumption is sufficiently low of ˜150mW/chip. The input signal range of ±20 mV covers the effective energy range of the typical X-ray photon counting CCD (up to 20 keV). The integrated non-linearity is 0.2% that is similar as those of the conventional CCDs in orbit. We also performed a radiation tolerance test against the total ionizing dose (TID) effect and the single event effect. The irradiation test using 60Co and proton beam showed that the ASIC has the sufficient tolerance against TID up to 200 krad, which absolutely exceeds the expected amount of dose during the period of operating in a low-inclination low-earth orbit. The irradiation of Fe ions with the fluence of 5.2×108 Ion/cm2 resulted in no single event latchup (SEL), although there were some possible single event upsets. The threshold against SEL is higher than 1.68 MeV cm2/mg, which is sufficiently high enough that the SEL event should not be one of major causes of instrument downtime in orbit.

  9. An efficient real time superresolution ASIC system

    NASA Astrophysics Data System (ADS)

    Reddy, Dikpal; Yue, Zhanfeng; Topiwala, Pankaj

    2008-04-01

    Superresolution of images is an important step in many applications like target recognition where the input images are often grainy and of low quality due to bandwidth constraints. In this paper, we present a real-time superresolution application implemented in ASIC/FPGA hardware, and capable of 30 fps of superresolution by 16X in total pixels. Consecutive frames from the video sequence are grouped and the registered values between them are used to fill the pixels in the higher resolution image. The registration between consecutive frames is evaluated using the algorithm proposed by Schaum et al. The pixels are filled by averaging a fixed number of frames associated with the smallest error distances. The number of frames (the number of nearest neighbors) is a user defined parameter whereas the weights in the averaging process are decided by inverting the corresponding smallest error distances. Wiener filter is used to post process the image. Different input parameters, such as size of input image, enlarging factor and the number of nearest neighbors, can be tuned conveniently by the user. We use a maximum word size of 32 bits to implement the algorithm in Matlab Simulink as well as the hardware, which gives us a fine balance between the number of bits and performance. The algorithm performs with real time speed with very impressive superresolution results.

  10. Integrated Cryogenic Electronics Testbed (ICE-T) for Evaluation of Superconductor and Cryo-Semiconductor Integrated Circuits

    NASA Astrophysics Data System (ADS)

    Dotsenko, V. V.; Sahu, A.; Chonigman, B.; Tang, J.; Lehmann, A. E.; Gupta, V.; Talalevskii, A.; Ruotolo, S.; Sarwana, S.; Webber, R. J.; Gupta, D.

    2017-02-01

    Research and development of cryogenic application-specific integrated circuits (ASICs), such as high-frequency (tens of GHz) semiconductor and superconductor mixed-signal circuits and large-scale (>10,000 Josephson Junctions) superconductor digital circuits, have long been hindered by the absence of specialized cryogenic test apparatus. During their iterative development phase, most ASICs require many additional input-output lines for applying independent bias controls, injecting test signals, and monitoring outputs of different sub-circuits. We are developing a full suite of modular test apparatus based on cryocoolers that do not consume liquid helium, and support extensive electrical interfaces to standard and custom test equipment. Our design separates the cryogenics from electrical connections, allowing even inexperienced users to conduct testing by simply mounting their ASIC on a removable electrical insert. Thermal connections between the cold stages and the inserts are made with robust thermal links. ICE-T accommodates two independent electrical inserts at the same time. We have designed various inserts, such as universal ones with all 40 or 80 coaxial cables and those with customized wiring and temperature-controlled stages. ICE-T features fast thermal cycling for rapid testing, enables detailed testing over long periods (days to months, if necessary), and even supports automated testing of digital ICs with modular additions.

  11. Short Circuit Analysis of Induction Machines Wind Power Application

    SciTech Connect

    Starke, Michael R; Smith, Travis M; Howard, Dustin; Harley, Ronald

    2012-01-01

    he short circuit behavior of Type I (fixed speed) wind turbine-generators is analyzed in this paper to aid in the protection coordination of wind plants of this type. A simple network consisting of one wind turbine-generator is analyzed for two network faults: a three phase short circuit and a phase A to ground fault. Electromagnetic transient simulations and sequence network calculations are compared for the two fault scenarios. It is found that traditional sequence network calculations give accurate results for the short circuit currents in the balanced fault case, but are inaccurate for the un-faulted phases in the unbalanced fault case. The time-current behavior of the fundamental frequency component of the short circuit currents for both fault cases are described, and found to differ significantly in the unbalanced and balanced fault cases

  12. Development of integrated thermionic circuits for high-temperature applications

    NASA Technical Reports Server (NTRS)

    Mccormick, J. B.; Wilde, D.; Depp, S.; Hamilton, D. J.; Kerwin, W.; Derouin, C.; Roybal, L.; Wooley, R.

    1981-01-01

    Integrated thermionic circuits (ITC) capable of extended operation in ambient temperatures up to 500 C are studied. A set of practical design and performance equations is demonstrated. Experimental results are discussed in which both devices and simple circuits were successfully operated in 5000 C environments for extended periods. It is suggested that ITC's may become an important technology for high temperature instrumentation and control systems in geothermal and other high temperature environments.

  13. Development of thermionic integrated circuits for applications in hostile environments

    SciTech Connect

    McCormik, J.B.; Lynn, D.K.; Wilde, D.; Cowan, R.; Hamilton, D.J.; Kerwin, W.; Dooley, R.

    1984-04-10

    This report describes a class of devices known as thermionic integrated circuits (TICs) that are capable of extended operation in ambient temperatures up to 500/sup 0/C and in high radiation environments. The evolution of the TIC concept is discussed. A set of practical design and performance equations is demonstrated. Recent experimental results are discussed in which both devices and simple circuits have successfully operated in 500/sup 0/C environments for extended periods of time.

  14. Y-Ba-Cu-O superconducting/GaAs semiconducting hybrid circuits for microwave applications

    NASA Technical Reports Server (NTRS)

    Bhasin, K. B.; Toncich, S. S.; Chorey, C. M.; Rohrer, N. J.; Valco, G. J.

    1993-01-01

    A two pole superconducting bandpass filter was combined with a packaged GaAs low noise amplifier, and a superconducting X-band oscillator was designed, fabricated, and tested. Both circuits were compared to normal metal circuits at 77K. The results of these experiments, technical issues, and potential applications are presented.

  15. ASIC2a-dependent increase of ASIC3 surface expression enhances the sustained component of the currents

    PubMed Central

    Kweon, Hae-Jin; Cho, Jin-Hwa; Jang, Il-Sung; Suh, Byung-Chang

    2016-01-01

    Acid-sensing ion channels (ASICs) are proton-gated cation channels widely expressed in the nervous system. Proton sensing by ASICs has been known to mediate pain, mechanosensation, taste transduction, learning and memory, and fear. In this study, we investigated the differential subcellular localization of ASIC2a and ASIC3 in heterologous expression systems. While ASIC2a targeted the cell surface itself, ASIC3 was mostly accumulated in the ER with partial expression in the plasma membrane. However, when ASIC3 was co-expressed with ASIC2a, its surface expression was markedly increased. By using bimolecular fluorescence complementation (BiFC) assay, we confirmed the heteromeric association between ASIC2a and ASIC3 subunits. In addition, we observed that the ASIC2a-dependent surface trafficking of ASIC3 remarkably enhanced the sustained component of the currents. Our study demonstrates that ASIC2a can increase the membrane conductance sensitivity to protons by facilitating the surface expression of ASIC3 through herteromeric assembly. [BMB Reports 2016; 49(10): 542-547] PMID:27241858

  16. A CMOS ASIC Design for SiPM Arrays

    PubMed Central

    Dey, Samrat; Banks, Lushon; Chen, Shaw-Pin; Xu, Wenbin; Lewellen, Thomas K.; Miyaoka, Robert S.; Rudell, Jacques C.

    2012-01-01

    Our lab has previously reported on novel board-level readout electronics for an 8×8 silicon photomultiplier (SiPM) array featuring row/column summation technique to reduce the hardware requirements for signal processing. We are taking the next step by implementing a monolithic CMOS chip which is based on the row-column architecture. In addition, this paper explores the option of using diagonal summation as well as calibration to compensate for temperature and process variations. Further description of a timing pickoff signal which aligns all of the positioning (spatial channels) pulses in the array is described. The ASIC design is targeted to be scalable with the detector size and flexible to accommodate detectors from different vendors. This paper focuses on circuit implementation issues associated with the design of the ASIC to interface our Phase II MiCES FPGA board with a SiPM array. Moreover, a discussion is provided for strategies to eventually integrate all the analog and mixed-signal electronics with the SiPM, on either a single-silicon substrate or multi-chip module (MCM). PMID:24825923

  17. σ-1 Receptor Inhibition of ASIC1a Channels is Dependent on a Pertussis Toxin-Sensitive G-Protein and an AKAP150/Calcineurin Complex.

    PubMed

    Mari, Yelenis; Katnik, Christopher; Cuevas, Javier

    2015-10-01

    ASIC1a channels play a major role in various pathophysiological conditions including depression, anxiety, epilepsy, and neurodegeneration following ischemic stroke. Sigma-1 (σ-1) receptor stimulation depresses the activity of ASIC1a channels in cortical neurons, but the mechanism(s) by which σ-1 receptors exert their influence on ASIC1a remains unknown. Experiments were undertaken to elucidate the signaling cascade linking σ-1 receptors to ASIC1a channels. Immunohistochemical studies showed that σ-1 receptors, ASIC1a and A-kinase anchoring peptide 150 colocalize in the plasma membrane of the cell body and processes of cortical neurons. Fluorometric Ca(2+) imaging experiments showed that disruption of the macromolecular complexes containing AKAP150 diminished the effects of the σ-1 on ASIC1a, as did application of the calcineurin inhibitors, cyclosporin A and FK-506. Moreover, whole-cell patch clamp experiments showed that σ-1 receptors were less effective at decreasing ASIC1a-mediated currents in the presence of the VIVIT peptide, which binds to calcineurin and prevents cellular effects dependent on AKAP150/calcineurin interaction. The coupling of σ-1 to ASIC1a was also disrupted by preincubation of the neurons in the G-protein inhibitor, pertussis toxin (PTX). Taken together, our data reveal that σ-1 receptor block of ASIC1a function is dependent on activation of a PTX-sensitive G-protein and stimulation of AKAP150 bound calcineurin.

  18. Micropower circuits for bidirectional wireless telemetry in neural recording applications.

    PubMed

    Neihart, Nathan M; Harrison, Reid R

    2005-11-01

    State-of-the art neural recording systems require electronics allowing for transcutaneous, bidirectional data transfer. As these circuits will be implanted near the brain, they must be small and low power. We have developed micropower integrated circuits for recovering clock and data signals over a transcutaneous power link. The data recovery circuit produces a digital data signal from an ac power waveform that has been amplitude modulated. We have also developed an FM transmitter with the lowest power dissipation reported for biosignal telemetry. The FM transmitter consists of a low-noise biopotential amplifier and a voltage controlled oscillator used to transmit amplified neural signals at a frequency near 433 MHz. All circuits were fabricated in a standard 0.5-microm CMOS VLSI process. The resulting chip is powered through a wireless inductive link. The power consumption of the clock and data recovery circuits is measured to be 129 microW; the power consumption of the transmitter is measured to be 465 microW when using an external surface mount inductor. Using a parasitic antenna less than 2 mm long, a received power level was measured to be -59.73 dBm at a distance of one meter.

  19. ASICs as therapeutic targets for migraine

    PubMed Central

    2015-01-01

    Migraine is the most common neurological disorder and one of the most common chronic pain conditions. Despite its prevalence, the pathophysiology leading to migraine is poorly understood and the identification of new therapeutic targets has been slow. Several processes are currently thought to contribute to migraine including altered activity in the hypothalamus, cortical-spreading depression (CSD), and afferent sensory input from the cranial meninges. Decreased extracellular pH and subsequent activation of acid-sensing ion channels (ASICs) may contribute to each of these processes and may thus play a role in migraine pathophysiology. Although few studies have directly examined a role of ASICs in migraine, studies directly examining a connection have generated promising results including efficacy of ASIC blockers in both preclinical migraine models and in human migraine patients. The purpose of this review is to discuss the pathophysiology thought to contribute to migraine and findings that implicate decreased pH and/or ASICs in these events, as well as propose issues to be resolved in future studies of ASICs and migraine. PMID:25582295

  20. Asynchronous data readout system for multichannel ASIC

    NASA Astrophysics Data System (ADS)

    Ivanov, P. Y.; Atkin, E. V.

    2016-02-01

    The data readout system of multichannel data-driven ASIC, requiring high-speed (320 Mb/s) output data serialization is described. Its structure, based on a limited number of FIFO blocks, provides a lossless data transfer. The solution has been realized as a separate test IP block in the prototyped 8 channel ASIC, intended for the muon chamber of CBM experiment at FAIR. The block was developed for the UMC 0.18 μm MMRF CMOS process and prototyped via Europractice. Main parameters of the chip are given.

  1. Circuit for Communication Over Power Lines

    NASA Technical Reports Server (NTRS)

    Krasowski, Michael J.; Prokop, Normal F.; Greer, Lawrence C., III; Nappier, Jennifer

    2011-01-01

    Many distributed systems share common sensors and instruments along with a common power line supplying current to the system. A communication technique and circuit has been developed that allows for the simple inclusion of an instrument, sensor, or actuator node within any system containing a common power bus. Wherever power is available, a node can be added, which can then draw power for itself, its associated sensors, and actuators from the power bus all while communicating with other nodes on the power bus. The technique modulates a DC power bus through capacitive coupling using on-off keying (OOK), and receives and demodulates the signal from the DC power bus through the same capacitive coupling. The circuit acts as serial modem for the physical power line communication. The circuit and technique can be made of commercially available components or included in an application specific integrated circuit (ASIC) design, which allows for the circuit to be included in current designs with additional circuitry or embedded into new designs. This device and technique moves computational, sensing, and actuation abilities closer to the source, and allows for the networking of multiple similar nodes to each other and to a central processor. This technique also allows for reconfigurable systems by adding or removing nodes at any time. It can do so using nothing more than the in situ power wiring of the system.

  2. A Spaceborne Synthetic Aperture Radar Partial Fixed-Point Imaging System Using a Field- Programmable Gate Array—Application-Specific Integrated Circuit Hybrid Heterogeneous Parallel Acceleration Technique

    PubMed Central

    Li, Bingyi; Chen, Liang; Wei, Chunpeng; Xie, Yizhuang; Chen, He; Yu, Wenyue

    2017-01-01

    With the development of satellite load technology and very large scale integrated (VLSI) circuit technology, onboard real-time synthetic aperture radar (SAR) imaging systems have become a solution for allowing rapid response to disasters. A key goal of the onboard SAR imaging system design is to achieve high real-time processing performance with severe size, weight, and power consumption constraints. In this paper, we analyse the computational burden of the commonly used chirp scaling (CS) SAR imaging algorithm. To reduce the system hardware cost, we propose a partial fixed-point processing scheme. The fast Fourier transform (FFT), which is the most computation-sensitive operation in the CS algorithm, is processed with fixed-point, while other operations are processed with single precision floating-point. With the proposed fixed-point processing error propagation model, the fixed-point processing word length is determined. The fidelity and accuracy relative to conventional ground-based software processors is verified by evaluating both the point target imaging quality and the actual scene imaging quality. As a proof of concept, a field- programmable gate array—application-specific integrated circuit (FPGA-ASIC) hybrid heterogeneous parallel accelerating architecture is designed and realized. The customized fixed-point FFT is implemented using the 130 nm complementary metal oxide semiconductor (CMOS) technology as a co-processor of the Xilinx xc6vlx760t FPGA. A single processing board requires 12 s and consumes 21 W to focus a 50-km swath width, 5-m resolution stripmap SAR raw data with a granularity of 16,384 × 16,384. PMID:28672813

  3. A Spaceborne Synthetic Aperture Radar Partial Fixed-Point Imaging System Using a Field- Programmable Gate Array-Application-Specific Integrated Circuit Hybrid Heterogeneous Parallel Acceleration Technique.

    PubMed

    Yang, Chen; Li, Bingyi; Chen, Liang; Wei, Chunpeng; Xie, Yizhuang; Chen, He; Yu, Wenyue

    2017-06-24

    With the development of satellite load technology and very large scale integrated (VLSI) circuit technology, onboard real-time synthetic aperture radar (SAR) imaging systems have become a solution for allowing rapid response to disasters. A key goal of the onboard SAR imaging system design is to achieve high real-time processing performance with severe size, weight, and power consumption constraints. In this paper, we analyse the computational burden of the commonly used chirp scaling (CS) SAR imaging algorithm. To reduce the system hardware cost, we propose a partial fixed-point processing scheme. The fast Fourier transform (FFT), which is the most computation-sensitive operation in the CS algorithm, is processed with fixed-point, while other operations are processed with single precision floating-point. With the proposed fixed-point processing error propagation model, the fixed-point processing word length is determined. The fidelity and accuracy relative to conventional ground-based software processors is verified by evaluating both the point target imaging quality and the actual scene imaging quality. As a proof of concept, a field- programmable gate array-application-specific integrated circuit (FPGA-ASIC) hybrid heterogeneous parallel accelerating architecture is designed and realized. The customized fixed-point FFT is implemented using the 130 nm complementary metal oxide semiconductor (CMOS) technology as a co-processor of the Xilinx xc6vlx760t FPGA. A single processing board requires 12 s and consumes 21 W to focus a 50-km swath width, 5-m resolution stripmap SAR raw data with a granularity of 16,384 × 16,384.

  4. Monolithic Microwave Integrated Circuit (MMIC) technology for space communications applications

    NASA Technical Reports Server (NTRS)

    Connolly, Denis J.; Bhasin, Kul B.; Romanofsky, Robert R.

    1987-01-01

    Future communications satellites are likely to use gallium arsenide (GaAs) monolithic microwave integrated-circuit (MMIC) technology in most, if not all, communications payload subsystems. Multiple-scanning-beam antenna systems are expected to use GaAs MMIC's to increase functional capability, to reduce volume, weight, and cost, and to greatly improve system reliability. RF and IF matrix switch technology based on GaAs MMIC's is also being developed for these reasons. MMIC technology, including gigabit-rate GaAs digital integrated circuits, offers substantial advantages in power consumption and weight over silicon technologies for high-throughput, on-board baseband processor systems. For the more distant future pseudomorphic indium gallium arsenide (InGaAs) and other advanced III-V materials offer the possibility of MMIC subsystems well up into the millimeter wavelength region. All of these technology elements are in NASA's MMIC program. Their status is reviewed.

  5. Monolithic Microwave Integrated Circuit (MMIC) technology for space communications applications

    NASA Technical Reports Server (NTRS)

    Connolly, Denis J.; Bhasin, Kul B.; Romanofsky, Robert R.

    1987-01-01

    Future communications satellites are likely to use gallium arsenide (GaAs) monolithic microwave integrated-circuit (MMIC) technology in most, if not all, communications payload subsystems. Multiple-scanning-beam antenna systems are expected to use GaAs MMICs to increase functional capability, to reduce volume, weight, and cost, and to greatly improve system reliability. RF and IF matrix switch technology based on GaAs MMICs is also being developed for these reasons. MMIC technology, including gigabit-rate GaAs digital integrated circuits, offers substantial advantages in power consumption and weight over silicon technologies for high-throughput, on-board baseband processor systems. For the more distant future pseudomorphic indium gallium arsenide (InGaAs) and other advanced III-V materials offer the possibility of MMIC subsystems well up into the millimeter wavelength region. All of these technology elements are in NASA's MMIC program. Their status is reviewed.

  6. Metamaterials for circuit QED: Quantum simulations and other applications

    NASA Astrophysics Data System (ADS)

    Taketani, Bruno G.; Wilhelm, Frank K.

    2014-03-01

    The ability to design periodically structured materials not present in nature provides scientists with new tools, ranging from sub-wavelength imaging to well controlled band structures for wave propagation in photonic crystals. Superconducting metamaterials have been recently proposed to manipulate the density-of-modes of transmission lines [D. J. Egger and F. K. Wilhelm, Phys. Rev. Letters 111, 163601 (2013)]. We further build on these ideas and develop a toolbox for environment manipulation based on nano-structured, periodic, lossless, superconducting circuits. In particular we show that high density of low energy states can be achieved using a superlattice arrangement of left-handed circuit elements. Multimode, ultra-strong coupling of superconducing qubits to such engineered environments thus allow for experimental implementation of quantum simulation of interesting new phenomena as well as for complex quantum state engineering.

  7. Signal Digitizer and Cross-Correlation Application Specific Integrated Circuit

    NASA Technical Reports Server (NTRS)

    Baranauskas, Dalius (Inventor); Baranauskas, Gytis (Inventor); Zelenin, Denis (Inventor); Kangaslahti, Pekka (Inventor); Tanner, Alan B. (Inventor); Lim, Boon H. (Inventor)

    2017-01-01

    According to one embodiment, a cross-correlator comprises a plurality of analog front ends (AFEs), a cross-correlation circuit and a data serializer. Each of the AFEs comprises a variable gain amplifier (VGA) and a corresponding analog-to-digital converter (ADC) in which the VGA receives and modifies a unique analog signal associates with a measured analog radio frequency (RF) signal and the ADC produces digital data associated with the modified analog signal. Communicatively coupled to the AFEs, the cross-correlation circuit performs a cross-correlation operation on the digital data produced from different measured analog RF signals. The data serializer is communicatively coupled to the summing and cross-correlating matrix and continuously outputs a prescribed amount of the correlated digital data.

  8. Packaging printed circuit boards: A production application of interactive graphics

    NASA Technical Reports Server (NTRS)

    Perrill, W. A.

    1975-01-01

    The structure and use of an Interactive Graphics Packaging Program (IGPP), conceived to apply computer graphics to the design of packaging electronic circuits onto printed circuit boards (PCB), were described. The intent was to combine the data storage and manipulative power of the computer with the imaginative, intuitive power of a human designer. The hardware includes a CDC 6400 computer and two CDC 777 terminals with CRT screens, light pens, and keyboards. The program is written in FORTRAN 4 extended with the exception of a few functions coded in COMPASS (assembly language). The IGPP performs four major functions for the designer: (1) data input and display, (2) component placement (automatic or manual), (3) conductor path routing (automatic or manual), and (4) data output. The most complex PCB packaged to date measured 16.5 cm by 19 cm and contained 380 components, two layers of ground planes and four layers of conductors mixed with ground planes.

  9. Monolithic Microwave Integrated Circuit (MMIC) technology for space communications applications

    NASA Astrophysics Data System (ADS)

    Connolly, Denis J.; Bhasin, Kul B.; Romanofsky, Robert R.

    Future communications satellites are likely to use gallium arsenide (GaAs) monolithic microwave integrated-circuit (MMIC) technology in most, if not all, communications payload subsystems. Multiple-scanning-beam antenna systems are expected to use GaAs MMICs to increase functional capability, to reduce volume, weight, and cost, and to greatly improve system reliability. RF and IF matrix switch technology based on GaAs MMICs is also being developed for these reasons. MMIC technology, including gigabit-rate GaAs digital integrated circuits, offers substantial advantages in power consumption and weight over silicon technologies for high-throughput, on-board baseband processor systems. For the more distant future pseudomorphic indium gallium arsenide (InGaAs) and other advanced III-V materials offer the possibility of MMIC subsystems well up into the millimeter wavelength region. All of these technology elements are in NASA's MMIC program. Their status is reviewed.

  10. Monolithic Microwave Integrated Circuit (MMIC) technology for space communications applications

    NASA Technical Reports Server (NTRS)

    Connolly, Denis J.; Bhasin, Kul B.; Romanofsky, Robert R.

    1987-01-01

    Future communications satellites are likely to use gallium arsenide (GaAs) monolithic microwave integrated-circuit (MMIC) technology in most, if not all, communications payload subsystems. Multiple-scanning-beam antenna systems are expected to use GaAs MMIC's to increase functional capability, to reduce volume, weight, and cost, and to greatly improve system reliability. RF and IF matrix switch technology based on GaAs MMIC's is also being developed for these reasons. MMIC technology, including gigabit-rate GaAs digital integrated circuits, offers substantial advantages in power consumption and weight over silicon technologies for high-throughput, on-board baseband processor systems. For the more distant future pseudomorphic indium gallium arsenide (InGaAs) and other advanced III-V materials offer the possibility of MMIC subsystems well up into the millimeter wavelength region. All of these technology elements are in NASA's MMIC program. Their status is reviewed.

  11. Monolithic Microwave Integrated Circuit (MMIC) technology for space communications applications

    NASA Astrophysics Data System (ADS)

    Connolly, Denis J.; Bhasin, Kul B.; Romanofsky, Robert R.

    1987-10-01

    Future communications satellites are likely to use gallium arsenide (GaAs) monolithic microwave integrated-circuit (MMIC) technology in most, if not all, communications payload subsystems. Multiple-scanning-beam antenna systems are expected to use GaAs MMIC's to increase functional capability, to reduce volume, weight, and cost, and to greatly improve system reliability. RF and IF matrix switch technology based on GaAs MMIC's is also being developed for these reasons. MMIC technology, including gigabit-rate GaAs digital integrated circuits, offers substantial advantages in power consumption and weight over silicon technologies for high-throughput, on-board baseband processor systems. For the more distant future pseudomorphic indium gallium arsenide (InGaAs) and other advanced III-V materials offer the possibility of MMIC subsystems well up into the millimeter wavelength region. All of these technology elements are in NASA's MMIC program. Their status is reviewed.

  12. Design and application of cotranscriptional non-enzymatic RNA circuits and signal transducers

    PubMed Central

    Bhadra, Sanchita; Ellington, Andrew D.

    2014-01-01

    Nucleic acid circuits are finding increasing real-life applications in diagnostics and synthetic biology. Although DNA has been the main operator in most nucleic acid circuits, transcriptionally produced RNA circuits could provide powerful alternatives for reagent production and their use in cells. Towards these goals, we have implemented a particular nucleic acid circuit, catalytic hairpin assembly, using RNA for both information storage and processing. Our results demonstrated that the design principles developed for DNA circuits could be readily translated to engineering RNA circuits that operated with similar kinetics and sensitivities of detection. Not only could purified RNA hairpins perform amplification reactions but RNA hairpins transcribed in vitro also mediated amplification, even without purification. Moreover, we could read the results of the non-enzymatic amplification reactions using a fluorescent RNA aptamer ‘Spinach’ that was engineered to undergo sequence-specific conformational changes. These advances were applied to the end-point and real-time detection of the isothermal strand displacement amplification reaction that produces single-stranded DNAs as part of its amplification cycle. We were also able to readily engineer gate structures with RNA similar to those that have previously formed the basis of DNA circuit computations. Taken together, these results validate an entirely new chemistry for the implementation of nucleic acid circuits. PMID:24493736

  13. Design and application of cotranscriptional non-enzymatic RNA circuits and signal transducers.

    PubMed

    Bhadra, Sanchita; Ellington, Andrew D

    2014-04-01

    Nucleic acid circuits are finding increasing real-life applications in diagnostics and synthetic biology. Although DNA has been the main operator in most nucleic acid circuits, transcriptionally produced RNA circuits could provide powerful alternatives for reagent production and their use in cells. Towards these goals, we have implemented a particular nucleic acid circuit, catalytic hairpin assembly, using RNA for both information storage and processing. Our results demonstrated that the design principles developed for DNA circuits could be readily translated to engineering RNA circuits that operated with similar kinetics and sensitivities of detection. Not only could purified RNA hairpins perform amplification reactions but RNA hairpins transcribed in vitro also mediated amplification, even without purification. Moreover, we could read the results of the non-enzymatic amplification reactions using a fluorescent RNA aptamer 'Spinach' that was engineered to undergo sequence-specific conformational changes. These advances were applied to the end-point and real-time detection of the isothermal strand displacement amplification reaction that produces single-stranded DNAs as part of its amplification cycle. We were also able to readily engineer gate structures with RNA similar to those that have previously formed the basis of DNA circuit computations. Taken together, these results validate an entirely new chemistry for the implementation of nucleic acid circuits.

  14. Integrating Optogenetic and Pharmacological Approaches to Study Neural Circuit Function: Current Applications and Future Directions

    PubMed Central

    Mason, Alex O.

    2013-01-01

    Optogenetic strategies to control genetically distinct populations of neurons with light have been rapidly evolving and widely adopted by the neuroscience community as one of the most important tool sets to study neural circuit function. Although optogenetics have already reshaped neuroscience by allowing for more precise control of circuit function compared with traditional techniques, current limitations of these approaches should be considered. Here, we discuss several strategies that combine optogenetic and contemporary pharmacological techniques to further increase the specificity of neural circuit manipulation. We also discuss recent advances that allow for the selective modulation of cellular function and gene expression with light. In addition, we outline a novel application of optogenetic circuit analysis for causally addressing the role of pathway-specific neural activity in mediating alterations in postsynaptic transcriptional processing in genetically defined neurons. By determining how optogenetic activation of specific neural circuits causally contributes to alterations in gene expression in a high-throughput fashion, novel biologic targets for future pharmacological intervention may be uncovered. Lastly, extending this experimental pipeline to selectively target pharmacotherapies to genetically defined neuronal populations or circuits will not only provide more selective control of neural circuits, but also may lead to the development of neural circuit specific pharmacological therapeutics. PMID:23319548

  15. Electrical Devices and Circuits for Low Temperature Space Applications

    NASA Technical Reports Server (NTRS)

    Patterson, R. L.; Hammond, A.; Dickman, J. E.; Gerber, S.; Overton, E.; Elbuluk, M.

    2003-01-01

    The environmental temperature in many NASA missions, such as deep space probes and outer planetary exploration, is significantly below the range for which conventional commercial-off-the-shelf electronics is designed. Presently, spacecraft operating in the cold environment of such deep space missions carry a large number of radioisotope or other heating units in order to maintain the surrounding temperature of the on-board electronics at approximately 20 C. Electronic devices and circuits capable of operation at cryogenic temperatures will not only tolerate the harsh environment of deep space but also will reduce system size and weight by eliminating or reducing the heating units and their associate structures; thereby reducing system development cost as well as launch costs. In addition, power electronic circuits designed for operation at low temperatures are expected to result in more efficient systems than those at room temperature. This improvement results from better behavior in the electrical and thermal properties of some semiconductor and dielectric materials at low temperatures. An on-going research and development program on low temperature electronics at the NASA Glenn Research Center focuses on the development of efficient electrical systems and circuits capable of surviving and exploiting the advantages of low temperature environments. An overview of the program will be presented in this paper. A description of the low temperature test facilities along with selected data obtained from in-house component testing will also be discussed. On-going research activities that are being performed in collaboration with various organizations will also be presented.

  16. GEMMA and GEMINI, two dedicated mixed-signal ASICs for Triple-GEM detectors readout

    NASA Astrophysics Data System (ADS)

    Pezzotta, A.; Croci, G.; Costantini, A.; De Matteis, M.; Tagnani, D.; Corradi, G.; Murtas, F.; Gorini, G.; Baschirotto, A.

    2016-03-01

    GEMMA and GEMINI, two integrated-circuit front-ends for the Triple-GEM detector are presented. These two ASICs aim to improve detector readout performance in terms of count rate, adaptability, portability and power consumption. GEMMA target is to embed counting, timing and spectroscopic measurements in a single 8-channel device, managing a detector capacitance up to 15 pF. On the other hand, GEMINI is dedicated to counting measurements, embedding 16 channels with a detector capacitance up to 40 pF. Both prototypes, fabricated in 130 nm and 180 nm CMOS respectively, feature an automatic on-chip calibration circuit, compensating for process/temperature variations.

  17. Small circuits for cryptography.

    SciTech Connect

    Torgerson, Mark Dolan; Draelos, Timothy John; Schroeppel, Richard Crabtree; Miller, Russell D.; Anderson, William Erik

    2005-10-01

    This report examines a number of hardware circuit design issues associated with implementing certain functions in FPGA and ASIC technologies. Here we show circuit designs for AES and SHA-1 that have an extremely small hardware footprint, yet show reasonably good performance characteristics as compared to the state of the art designs found in the literature. Our AES performance numbers are fueled by an optimized composite field S-box design for the Stratix chipset. Our SHA-1 designs use register packing and feedback functionalities of the Stratix LE, which reduce the logic element usage by as much as 72% as compared to other SHA-1 designs.

  18. Filter-bank based digital sub-banding ASIC architecture for coherent optical receivers

    NASA Astrophysics Data System (ADS)

    Nazarathy, Moshe; Tolmachev, Alex

    2013-01-01

    We introduce a highly efficient high performance architecture for the digital signal processing of high speed coherent optical receivers. Our ASIC signal processing architecture ports for the first time to optical reception efficient filter bank signal processing structures. The resulting optical receiver ASICs are applicable to long-haul and metro photonic communication and provide substantial energy efficiency saving 30%-50% in power consumption. We aim to develop an ultra-high-speed optical receiver ASIC for transporting 160 Gb/s in a 25 GHz optical band - seven such channels will together carry 1Tb/s (plus overhead) in our 'TeraSanta' project of TeraBitPerSecond efficient transponders.

  19. High temperature superconducting thin film microwave circuits: Fabrication, characterization, and applications

    NASA Technical Reports Server (NTRS)

    Bhasin, K. B.; Warner, J. D.; Romanofsky, R. R.; Heinen, V. O.; Chorey, C. M.

    1990-01-01

    Epitaxial YBa2Cu3O7 films were grown on several microwave substrates. Surface resistance and penetration depth measurements were performed to determine the quality of these films. Here the properties of these films on key microwave substrates are described. The fabrication and characterization of a microwave ring resonator circuit to determine transmission line losses are presented. Lower losses than those observed in gold resonator circuits were observed at temperatures lower than critical transition temperature. Based on these results, potential applications of microwave superconducting circuits such as filters, resonators, oscillators, phase shifters, and antenna elements in space communication systems are identified.

  20. Mixed application MMIC technologies - Progress in combining RF, digital and photonic circuits

    NASA Technical Reports Server (NTRS)

    Swirhun, S.; Bendett, M.; Sokolov, V.; Bauhahn, P.; Sullivan, C.; Mactaggart, R.; Mukherjee, S.; Hibbs-Brenner, M.; Mondal, J.

    1991-01-01

    Approaches for future 'mixed application' monolithic integrated circuits (ICs) employing optical receive/transmit, RF amplification and modulation and digital control functions are discussed. We focus on compatibility of the photonic component fabrication with conventional RF and digital IC technologies. Recent progress at Honeywell in integrating several parts of the desired RF/digital/photonic circuit integration suite required for construction of a future millimeter-wave optically-controlled phased-array element are illustrated.

  1. Metamaterial-Based Patch Antennas and Adaptive Rectifying Circuits for High Power Rectenna Applications

    DTIC Science & Technology

    2005-01-01

    FUNDING NUMBERS Metamaterial-based Patch Antennas and Adaptive Rectifying Circuits for High N00014-04-1-0320 Power Rectenna Applications 6. AUTHOR(S...CODE Approved for public release; distribution unlimited. The efforts of this project considered two technological aspects of rectennas systems. One...technology that was emphasized power-adaptive rectifying circuits (PARCs). If a rectenna system is to be integrated into an autonomous vehicle system

  2. Proton and non-proton activation of ASIC channels

    PubMed Central

    Gautschi, Ivan; van Bemmelen, Miguel Xavier; Schild, Laurent

    2017-01-01

    The Acid-Sensing Ion Channels (ASIC) exhibit a fast desensitizing current when activated by pH values below 7.0. By contrast, non-proton ligands are able to trigger sustained ASIC currents at physiological pHs. To analyze the functional basis of the ASIC desensitizing and sustained currents, we have used ASIC1a and ASIC2a mutants with a cysteine in the pore vestibule for covalent binding of different sulfhydryl reagents. We found that ASIC1a and ASIC2a exhibit two distinct currents, a proton-induced desensitizing current and a sustained current triggered by sulfhydryl reagents. These currents differ in their pH dependency, their sensitivity to the sulfhydryl reagents, their ionic selectivity and their relative magnitude. We propose a model for ASIC1 and ASIC2 activity where the channels can function in two distinct modes, a desensitizing mode and a sustained mode depending on the activating ligands. The pore vestibule of the channel represents a functional site for binding non-proton ligands to activate ASIC1 and ASIC2 at neutral pH and to prevent channel desensitization. PMID:28384246

  3. Development of low-noise high-speed analog ASIC for X-ray CCD cameras and wide-band X-ray imaging sensors

    NASA Astrophysics Data System (ADS)

    Nakajima, Hiroshi; Hirose, Shin-nosuke; Imatani, Ritsuko; Nagino, Ryo; Anabuki, Naohisa; Hayashida, Kiyoshi; Tsunemi, Hiroshi; Doty, John P.; Ikeda, Hirokazu; Kitamura, Hisashi; Uchihori, Yukio

    2016-09-01

    We report on the development and performance evaluation of the mixed-signal Application Specific Integrated Circuit (ASIC) developed for the signal processing of onboard X-ray CCD cameras and various types of X-ray imaging sensors in astrophysics. The quick and low-noise readout is essential for the pile-up free imaging spectroscopy with a future X-ray telescope. Our goal is the readout noise of 5e- r . m . s . at the pixel rate of 1 Mpix/s that is about 10 times faster than those of the currently working detectors. We successfully developed a low-noise ASIC as the front-end electronics of the Soft X-ray Imager onboard Hitomi that was launched on February 17, 2016. However, it has two analog-to-digital converters per chain due to the limited processing speed and hence we need to correct the difference of gain to obtain the X-ray spectra. Furthermore, its input equivalent noise performance is not satisfactory (> 100 μV) at the pixel rate higher than 500 kpix/s. Then we upgrade the design of the ASIC with the fourth-order ΔΣ modulators to enhance its inherent noise-shaping performance. Its performance is measured using pseudo CCD signals with variable processing speed. Although its input equivalent noise is comparable with the conventional one, the integrated non-linearity (0.1%) improves to about the half of that of the conventional one. The radiation tolerance is also measured with regard to the total ionizing dose effect and the single event latch-up using protons and Xenon, respectively. The former experiment shows that all of the performances does not change after imposing the dose corresponding to 590 years in a low earth orbit. We also put the upper limit on the frequency of the latch-up to be once per 48 years.

  4. In Vivo Application of Optogenetics for Neural Circuit Analysis

    PubMed Central

    2012-01-01

    Optogenetics combines optical and genetic methods to rapidly and reversibly control neural activities or other cellular functions. Using genetic methods, specific cells or anatomical pathways can be sensitized to light through exogenous expression of microbial light activated opsin proteins. Using optical methods, opsin expressing cells can be rapidly and reversibly controlled by pulses of light of specific wavelength. With the high spatial temporal precision, optogenetic tools have enabled new ways to probe the causal role of specific cells in neural computation and behavior. Here, we overview the current state of the technology, and provide a brief introduction to the practical considerations in applying optogenetics in vivo to analyze neural circuit functions. PMID:22896801

  5. A 130 nm ASIC prototype for the NA62 Gigatracker readout

    NASA Astrophysics Data System (ADS)

    Dellacasa, G.; Garbolino, S.; Marchetto, F.; Martoiu, S.; Mazza, G.; Rivetti, A.; Wheadon, R.

    2011-09-01

    One of the most challenging detectors of the NA62 experiment is the silicon tracker, called Gigatracker. It consists of three hybrid silicon pixel stations, each one covering an area of 27 mm×60 mm. While the maximum pixel size is fairly large, 300 μm×300 μm the system has to sustain a very high particle rate, 1.5 MHz/mm 2, which corresponds to 800 MHz for each station. To obtain an efficient tracking with such a high rate the required track timing resolution is 150 ps (rms). Therefore the front-end ASIC should provide for each pixel a 200 ps time measurement capability, thus leading to the requirement of time walk compensation and very compact TDCs. Moreover, Single Event Upset protection has to be implemented in order to protect the digital circuitry. An ASIC prototype has been realized in CMOS 130 nm technology, containing three pixel columns. The chip performs the time walk compensation by a Constant Fraction Discriminator circuit, while the time measurement is performed by a Time to Amplitude Converter based TDC, both of them implemented on each pixel cell. The End of Column circuit containing only digital logic is responsible for the data readout from the pixel cell. The whole chip works with a system clock of 160 MHz and the digital logic is SEU protected by the use of Hamming codes. The detailed architecture of the ASIC prototype and test results are presented.

  6. 4D ICE: A 2D Array Transducer with Integrated ASIC in a 10 Fr Catheter for Real-Time 3D Intracardiac Echocardiography.

    PubMed

    Wildes, Douglas; Lee, Warren; Haider, Bruno; Cogan, Scott; Sundaresan, Krishnakumar; Mills, David; Yetter, Christopher; Hart, Patrick; Haun, Christopher; Concepcion, Mikael; Kirkhorn, Johan; Bitoun, Marc

    2016-10-12

    We developed a 2.5 x 6.6 mm 2D array transducer with integrated transmit/receive ASIC for 4D ICE (real-time 3D IntraCardiac Echocardiography) applications. The ASIC and transducer design were optimized so that the high voltage transmit, low-voltage TGC (time-gain control) and preamp, subaperture beamformer, and digital control circuits for each transducer element all fit within the 0.019 mm2 area of the element. The transducer assembly was deployed in a 10 Fr (3.3 mm diameter) catheter, integrated with a GE Vivid1 E9 ultrasound imaging system, and evaluated in three pre-clinical studies. 2D image quality and imaging modes were comparable to commercial 2D ICE catheters. The 4D field of view was at least 90° x 60° x 8 cm and could be imaged at 30 volumes/sec, sufficient to visualize cardiac anatomy and other diagnostic and therapy catheters. 4D ICE should significantly reduce X-ray fluoroscopy use and dose during electrophysiology (EP) ablation procedures. 4D ICE may be able to replace trans-esophageal echocardiography (TEE), and the associated risks and costs of general anesthesia, for guidance of some structural heart procedures.

  7. Field testing of overcurrent trip units for low voltage circuit breakers used in DC applications

    SciTech Connect

    Davis, E.L.; Funk, D.L.

    1994-08-01

    This Tech Note investigates and provides recommendations for field testing the overcurrent trip units of low voltage circuit breakers used in direct current (DC) applications. Although industry guidance is available for field testing low voltage circuit breakers in alternating current (AC) applications, guidance for testing breakers used in DC circuits is virtually nonexistent. Fault theory and breaker operating principles are discussed at a depth necessary to technically substantiate recommended practices contained in this Tech Note. The response of low voltage circuit breaker overcurrent trip units to AC and DC current is compared to facilitate an understanding of the issues and concerns surrounding overcurrent test methods for low voltage circuit breakers used in dc applications. The applicability of this information to a test program for DC system breakers is described in detail. This Tech Note addresses whether or not overcurrent test results obtained using UAC current are representative of a breaker`s performance under DC conditions. This document demonstrates that technically valid test results can be obtained using either AC or DC test methods. The final recommendations presented favor AC testing over DC testing based on familiarity with the test method and economic considerations; however, it is stressed that either test method can yield technically acceptable results. The potential benefits and limitations of each test method, AC or DC, should be understood thoroughly before selecting a test method or interpreting test results.

  8. Modeling and simulation of carbon nanotube field effect transistor and its circuit application

    NASA Astrophysics Data System (ADS)

    Singh, Amandeep; Saini, Dinesh Kumar; Agarwal, Dinesh; Aggarwal, Sajal; Khosla, Mamta; Raj, Balwinder

    2016-07-01

    The carbon nanotube field effect transistor (CNTFET) is modelled for circuit application. The model is based on the transport mechanism and it directly relates the transport mechanism with the chirality. Also, it does not consider self consistent equations and thus is used to develop the HSPICE compatible circuit model. For validation of the model, it is applied to the top gate CNTFET structure and the MATLAB simulation results are compared with the simulations of a similar structure created in NanoTCAD ViDES. For demonstrating the circuit compatibility of the model, two circuits viz. inverter and SRAM are designed and simulated in HSPICE. Finally, SRAM performance metrics are compared with those of device simulations from Nano TCAD ViDES.

  9. Plasmonic nanopatch array for optical integrated circuit applications

    PubMed Central

    Qu, Shi-Wei; Nie, Zai-Ping

    2013-01-01

    Future plasmonic integrated circuits with the capability of extremely high-speed data processing at optical frequencies will be dominated by the efficient optical emission (excitation) from (of) plasmonic waveguides. Towards this goal, plasmonic nanoantennas, currently a hot topic in the field of plasmonics, have potential to bridge the mismatch between the wave vector of free-space photonics and that of the guided plasmonics. To manipulate light at will, plasmonic nanoantenna arrays will definitely be more efficient than isolated nanoantennas. In this article, the concepts of microwave antenna arrays are applied to efficiently convert plasmonic waves in the plasmonic waveguides into free-space optical waves or vice versa. The proposed plasmonic nanoantenna array, with nanopatch antennas and a coupled wedge plasmon waveguide, can also act as an efficient spectrometer to project different wavelengths into different directions, or as a spatial filter to absorb a specific wavelength at a specified incident angle. PMID:24201454

  10. Plasmonic nanopatch array for optical integrated circuit applications

    NASA Astrophysics Data System (ADS)

    Qu, Shi-Wei; Nie, Zai-Ping

    2013-11-01

    Future plasmonic integrated circuits with the capability of extremely high-speed data processing at optical frequencies will be dominated by the efficient optical emission (excitation) from (of) plasmonic waveguides. Towards this goal, plasmonic nanoantennas, currently a hot topic in the field of plasmonics, have potential to bridge the mismatch between the wave vector of free-space photonics and that of the guided plasmonics. To manipulate light at will, plasmonic nanoantenna arrays will definitely be more efficient than isolated nanoantennas. In this article, the concepts of microwave antenna arrays are applied to efficiently convert plasmonic waves in the plasmonic waveguides into free-space optical waves or vice versa. The proposed plasmonic nanoantenna array, with nanopatch antennas and a coupled wedge plasmon waveguide, can also act as an efficient spectrometer to project different wavelengths into different directions, or as a spatial filter to absorb a specific wavelength at a specified incident angle.

  11. Plasmonic nanopatch array for optical integrated circuit applications.

    PubMed

    Qu, Shi-Wei; Nie, Zai-Ping

    2013-11-08

    Future plasmonic integrated circuits with the capability of extremely high-speed data processing at optical frequencies will be dominated by the efficient optical emission (excitation) from (of) plasmonic waveguides. Towards this goal, plasmonic nanoantennas, currently a hot topic in the field of plasmonics, have potential to bridge the mismatch between the wave vector of free-space photonics and that of the guided plasmonics. To manipulate light at will, plasmonic nanoantenna arrays will definitely be more efficient than isolated nanoantennas. In this article, the concepts of microwave antenna arrays are applied to efficiently convert plasmonic waves in the plasmonic waveguides into free-space optical waves or vice versa. The proposed plasmonic nanoantenna array, with nanopatch antennas and a coupled wedge plasmon waveguide, can also act as an efficient spectrometer to project different wavelengths into different directions, or as a spatial filter to absorb a specific wavelength at a specified incident angle.

  12. Preliminary validation results of an ASIC for the readout and control of near-infrared large array detectors

    NASA Astrophysics Data System (ADS)

    Pâhlsson, Philip; Meier, Dirk; Otnes Berge, Hans Kristian; Øya, Petter; Steenari, David; Olsen, Alf; Hasanbegovic, Amir; Altan, Mehmet A.; Najafiuchevler, Bahram; Talebi, Jahanzad; Azman, Suleyman; Gheorghe, Codin; Ackermann, Jörg; Mæhlum, Gunnar

    2015-06-01

    In this paper we present initial test results of the Near Infrared Readout and Controller ASIC (NIRCA), designed for large area image sensors under contract from the European Space Agency (ESA) and the Norwegian Space Center. The ASIC is designed to read out image sensors based on mercury cadmium telluride (HgCdTe, or MCT) operating down to 77 K. IDEAS has developed, designed and initiated testing of NIRCA with promising results, showing complete functionality of all ASIC sub-components. The ASIC generates programmable digital signals to clock out the contents of an image array and to amplify, digitize and transfer the resulting pixel charge. The digital signals can be programmed into the ASIC during run-time and allows for windowing and custom readout schemes. The clocked out voltages are amplified by programmable gain amplifiers and digitized by 12-bit, 3-Msps successive approximation register (SAR) analogue-to-digital converters (ADC). Digitized data is encoded using 8-bit to 10-bit encoding and transferred over LVDS to the readout system. The ASIC will give European researchers access to high spectral sensitivity, very low noise and radiation hardened readout electronics for astronomy and Earth observation missions operating at 77 K and room temperature. The versatility of the chip makes the architecture a possible candidate for other research areas, or defense or industrial applications that require analog and digital acquisition, voltage regulation, and digital signal generation.

  13. Single event effect characterization of the mixed-signal ASIC developed for CCD camera in space use

    NASA Astrophysics Data System (ADS)

    Nakajima, Hiroshi; Fujikawa, Mari; Mori, Hideki; Kan, Hiroaki; Ueda, Shutaro; Kosugi, Hiroko; Anabuki, Naohisa; Hayashida, Kiyoshi; Tsunemi, Hiroshi; Doty, John P.; Ikeda, Hirokazu; Kitamura, Hisashi; Uchihori, Yukio

    2013-12-01

    We present the single event effect (SEE) tolerance of a mixed-signal application-specific integrated circuit (ASIC) developed for a charge-coupled device camera onboard a future X-ray astronomical mission. We adopted proton and heavy ion beams at HIMAC/NIRS in Japan. The particles with high linear energy transfer (LET) of 57.9 MeV cm2/mg is used to measure the single event latch-up (SEL) tolerance, which results in a sufficiently low cross-section of σSEL<4.2×10-11 cm2/(Ion×ASIC). The single event upset (SEU) tolerance is estimated with various kinds of species with wide range of energy. Taking into account that a part of the protons creates recoiled heavy ions that have higher LET than that of the incident protons, we derived the probability of SEU event as a function of LET. Then the SEE event rate in a low-earth orbit is estimated considering a simulation result of LET spectrum. SEL rate is below once per 49 years, which satisfies the required latch-up tolerance. The upper limit of the SEU rate is derived to be 1.3×10-3 events/s. Although the SEU events cannot be distinguished from the signals of X-ray photons from astronomical objects, the derived SEU rate is below 1.3% of expected non-X-ray background rate of the detector and hence these events should not be a major component of the instrumental background.

  14. Improving ASIC Reuse with Embedded FPGA Fabrics

    DTIC Science & Technology

    2016-03-31

    of many system -on-chip designers [2], these hard FPGA blocks are not widely available as commercial IP. As a result, soft FPGA blocks [3][4][5][6...flows. The remaining sections of this paper outline the design of this embedded FPGA block and its physical realization. Embedded FPGA Fabric The...convert RTL designs into embedded FPGA programming bit streams. First, a commercial ASIC tool (Synopsys DesignCompiler) is used for front-end

  15. Application of the DRS4 chip for GHz waveform digitizing circuits

    NASA Astrophysics Data System (ADS)

    Yang, Hai-Bo; Su, Hong; Kong, Jie; Cheng, Ke; Chen, Jin-Da; Du, Cheng-Ming; Zhang, Jing-Zhe

    2015-05-01

    A new fast waveform sampling digitizing circuit based on the domino ring sampler (DRS), a switched capacitor array (SCA) chip, is presented in this paper, which is different from the traditional waveform digitizing circuit constructed with an analog to digital converter (ADC) or time to digital converter. A DRS4 chip is used as a core device in our circuit, which has a fast sampling rate up to five gigabit samples per second (GSPS). Quite satisfactory results are acquired by the preliminary performance test for this circuit board. Eight channels can be provided by one board, which has a 1 V input dynamic range for each channel. The circuit linearity is better than 0.1%, the noise is less than 0.5 mV (root mean square, RMS), and its time resolution is about 50 ps. Several boards can be cascaded to construct a multi-board system. The advantages of high resolution, low cost, low power dissipation, high channel density and small size make the circuit board useful not only for physics experiments, but also for other applications. Supported by National Natural Science Foundation of China (11305233), Specific Fund Research Based on Large-scale Science Instrument Facilities of China (2011YQ12009604)

  16. A distributed current stimulator ASIC for high density neural stimulation.

    PubMed

    Jeong Hoan Park; Chaebin Kim; Seung-Hee Ahn; Tae Mok Gwon; Joonsoo Jeong; Sang Beom Jun; Sung June Kim

    2016-08-01

    This paper presents a novel distributed neural stimulator scheme. Instead of a single stimulator ASIC in the package, multiple ASICs are embedded at each electrode site for stimulation with a high density electrode array. This distributed architecture enables the simplification of wiring between electrodes and stimulator ASIC that otherwise could become too complex as the number of electrode increases. The individual ASIC chip is designed to have a shared data bus that independently controls multiple stimulating channels. Therefore, the number of metal lines is determined by the distributed ASICs, not by the channel number. The function of current steering is also implemented within each ASIC in order to increase the effective number of channels via pseudo channel stimulation. Therefore, the chip area can be used more efficiently. The designed chip was fabricated with area of 0.3 mm2 using 0.18 μm BCDMOS process, and the bench-top test was also conducted to validate chip performance.

  17. [Acid-Sensing Ion Channels (ASICs) in pain].

    PubMed

    Lingueglia, Eric

    2014-01-01

    The discovery of new drug targets represents a real opportunity for developing fresh strategies against pain. Ion channels are interesting targets because they are directly involved in the detection and the transmission of noxious stimuli by sensory fibres of the peripheral nervous system and by neurons of the spinal cord. Acid-Sensing Ion Channels (ASICs) have emerged as important players in the pain pathway. They are neuronal, voltage-independent depolarizing sodium channels activated by extracellular protons. The ASIC family comprises several subunits that need to associate into homo- or hetero-trimers to form a functional channel. The ASIC1 and ASIC3 isoforms are particularly important in sensory neurons, whereas ASIC1a, alone or in association with ASIC2, is essential in the central nervous system. The potent analgesic effects associated with their inhibition in animals (which can be comparable to those of morphine) and data suggesting a role in human pain illustrate the therapeutic potential of these channels.

  18. Kitaev honeycomb tensor networks: Exact unitary circuits and applications

    NASA Astrophysics Data System (ADS)

    Schmoll, Philipp; Orús, Román

    2017-01-01

    The Kitaev honeycomb model is a paradigm of exactly solvable models, showing nontrivial physical properties such as topological quantum order, Abelian and non-Abelian anyons, and chirality. Its solution is one of the most beautiful examples of the interplay of different mathematical techniques in condensed matter physics. In this paper, we show how to derive a tensor network (TN) description of the eigenstates of this spin-1/2 model in the thermodynamic limit, and in particular for its ground state. In our setting, eigenstates are naturally encoded by an exact 3d TN structure made of fermionic unitary operators, corresponding to the unitary quantum circuit building up the many-body quantum state. In our derivation we review how the different "solution ingredients" of the Kitaev honeycomb model can be accounted for in the TN language, namely, Jordan-Wigner transformation, braidings of Majorana modes, fermionic Fourier transformation, and Bogoliubov transformation. The TN built in this way allows for a clear understanding of several properties of the model. In particular, we show how the fidelity diagram is straightforward both at zero temperature and at finite temperature in the vortex-free sector. We also show how the properties of two-point correlation functions follow easily. Finally, we also discuss the pros and cons of contracting of our 3d TN down to a 2d projected entangled pair state (PEPS) with finite bond dimension. The results in this paper can be extended to generalizations of the Kitaev model, e.g., to other lattices, spins, and dimensions.

  19. Laser pulse peak holding circuit for low cost laser tracking applications

    NASA Astrophysics Data System (ADS)

    Zhang, Wei; Zhang, He; Zhang, Xiangjin; Chen, Yong

    2016-10-01

    In the low cost laser tracking applications, the width of the laser echo pulses received by four-quadrant photodetector from an illuminated target are narrow, and are only a few hundred or dozens of nanoseconds. In order to obtain the peak of these narrow laser pulses of nS level, by using peak holding technique, a simplified transconductance peak holding circuit model is constructed, taking into account of low cost applications with large number of requirements. The key parameters of the transconductance peak holding circuit such as response time, droop rate and bandwidth are analyzed for narrow laser pulse signals. The transconductance peak holding circuit is designed using a low-cost integrated chip OPA615, then is simulated by the software PSpice tools. Finally, a circuit board is manufactured for further tests. The results show that: the bandwidth of the circuit is about 76.4 MHz, response time is about 7 ns, and droop rate is about 5.7 mV/μs. The peaks of narrow laser pulses are effectively acquired, meeting the needs for the subsequent low speed and low cost A/D converter.

  20. A Very Fast Switched Attenuator Circuit for Microwave and R.F. Applications.

    PubMed

    Quine, Richard W; Tseytlin, Mark; Eaton, Sandra S; Eaton, Gareth R

    2010-04-01

    An electronic circuit was designed and constructed that can switch an r.f. signal between two amplitude levels at very fast speed (less than 10 ns). The circuit incorporates a TTL control for convenient interfacing to existing equipment. The attenuation of the more attenuated state can be adjusted to be up to 12 dB more than for the less attenuated state. The initial application was in Pulsed Electron Paramagnetic Resonance (EPR) spectroscopy to produce a π/2 - π pulse sequence with pulses of equal time duration and 6 dB difference in amplitude. A new method for measuring electron spin echoes for narrow, homogeneously-broadened lines is described.

  1. Design of bandgap reference circuits in a 65 nm CMOS technology for HL-LHC applications

    NASA Astrophysics Data System (ADS)

    Traversi, G.; De Canio, F.; Gaioni, L.; Manghisoni, M.; Ratti, L.; Re, V.

    2015-02-01

    This work is concerned with the design and characterization of bandgap reference circuits capable of operating with a power supply of 1.2 V in view of applications to HL-LHC experiments. Due to the harsh environment foreseen for these devices, different solutions have been considered and implemented in a 65 nm CMOS technology. Together with a conventional structure which exploits bipolar devices, a smaller solution based on pn diodes and a version with MOS transistors biased in weak inversion region are included. This paper intends to describe and compare the features of the different circuits designed.

  2. Lignan from Thyme Possesses Inhibitory Effect on ASIC3 Channel Current*

    PubMed Central

    Dubinnyi, Maxim A.; Osmakov, Dmitry I.; Koshelev, Sergey G.; Kozlov, Sergey A.; Andreev, Yaroslav A.; Zakaryan, Naira A.; Dyachenko, Igor A.; Bondarenko, Dmitry A.; Arseniev, Alexander S.; Grishin, Eugene V.

    2012-01-01

    A novel compound was identified in the acidic extract of Thymus armeniacus collected in the Lake Sevan region of Armenia. This compound, named “sevanol,” to our knowledge is the first low molecular weight natural molecule that has a reversible inhibition effect on both the transient and the sustained current of human ASIC3 channels expressed in Xenopus laevis oocytes. Sevanol completely blocked the transient component (IC50 353 ± 23 μm) and partially (∼45%) inhibited the amplitude of the sustained component (IC50 of 234 ± 53 μm). Other types of acid-sensing ion channel (ASIC) channels were intact to sevanol application, except ASIC1a, which showed more than six times less affinity to it as compared with the inhibitory action on the ASIC3 channel. To elucidate the structure of sevanol, the set of NMR spectra in two solvents (d6-DMSO and D2O) was collected, and the complete chemical structure was confirmed by liquid chromatography-mass spectrometry with electrospray ionization (LC-ESI+-MS) fragmentation. This compound is a new lignan built up of epiphyllic acid and two isocitryl esters in positions 9 and 10. In vivo administration of sevanol (1–10 mg/kg) significantly reversed thermal hyperalgesia induced by complete Freund's adjuvant injection and reduced response to acid in a writhing test. Thus, we assume the probable considerable role of sevanol in known analgesic and anti-inflammatory properties of thyme. PMID:22854960

  3. Reconfigurable 2D cMUT-ASIC arrays for 3D ultrasound image

    NASA Astrophysics Data System (ADS)

    Song, Jongkeun; Jung, Sungjin; Kim, Youngil; Cho, Kyungil; Kim, Baehyung; Lee, Seunghun; Na, Junseok; Yang, Ikseok; Kwon, Oh-kyong; Kim, Dongwook

    2012-03-01

    This paper describes the design and implementations of the complete 2D capacitive micromachined ultrasound transducer electronics and its analog front-end module for transmitting high voltage ultrasound pulses and receiving its echo signals to realize 3D ultrasound image. In order to minimize parasitic capacitances and ultimately improve signal-to- noise ratio (SNR), cMUT has to be integrate with Tx/Rx electronics. Additionally, in order to integrate 2D cMUT array module, significant optimized high voltage pulser circuitry, low voltage analog/digital circuit design and packaging challenges are required due to high density of elements and small pitch of each element. We designed 256(16x16)- element cMUT and reconfigurable driving ASIC composed of 120V high voltage pulser, T/R switch, low noise preamplifier and digital control block to set Tx frequency of ultrasound and pulse train in each element. Designed high voltage analog ASIC was successfully bonded with 2D cMUT array by flip-chip bonding process and it connected with analog front-end board to transmit pulse-echo signals. This implementation of reconfigurable cMUT-ASIC-AFE board enables us to produce large aperture 2D transducer array and acquire high quality of 3D ultrasound image.

  4. System-level integrated circuit (SLIC) development for phased array antenna applications

    NASA Technical Reports Server (NTRS)

    Shalkhauser, K. A.; Raquet, C. A.

    1991-01-01

    A microwave/millimeter wave system-level integrated circuit (SLIC) being developed for use in phased array antenna applications is described. The program goal is to design, fabricate, test, and deliver an advanced integrated circuit that merges radio frequency (RF) monolithic microwave integrated circuit (MMIC) technologies with digital, photonic, and analog circuitry that provide control, support, and interface functions. As a whole, the SLIC will offer improvements in RF device performance, uniformity, and stability while enabling accurate, rapid, repeatable control of the RF signal. Furthermore, the SLIC program addresses issues relating to insertion of solid state devices into antenna systems, such as the reduction in number of bias, control, and signal lines. Program goals, approach, and status are discussed.

  5. System-Level Integrated Circuit (SLIC) development for phased array antenna applications

    NASA Technical Reports Server (NTRS)

    Shalkhauser, K. A.; Raquet, C. A.

    1991-01-01

    A microwave/millimeter wave system-level integrated circuit (SLIC) being developed for use in phased array antenna applications is described. The program goal is to design, fabricate, test, and deliver an advanced integrated circuit that merges radio frequency (RF) monolithic microwave integrated circuit (MMIC) technologies with digital, photonic, and analog circuitry that provide control, support, and interface functions. As a whole, the SLIC will offer improvements in RF device performance, uniformity, and stability while enabling accurate, rapid, repeatable control of the RF signal. Furthermore, the SLIC program addresses issues relating to insertion of solid state devices into antenna systems, such as the reduction in number of bias, control, and signal lines. Program goals, approach, and status are discussed.

  6. System-level integrated circuit (SLIC) development for phased array antenna applications

    NASA Technical Reports Server (NTRS)

    Shalkhauser, K. A.; Raquet, C. A.

    1991-01-01

    A microwave/millimeter wave system-level integrated circuit (SLIC) being developed for use in phased array antenna applications is described. The program goal is to design, fabricate, test, and deliver an advanced integrated circuit that merges radio frequency (RF) monolithic microwave integrated circuit (MMIC) technologies with digital, photonic, and analog circuitry that provide control, support, and interface functions. As a whole, the SLIC will offer improvements in RF device performance, uniformity, and stability while enabling accurate, rapid, repeatable control of the RF signal. Furthermore, the SLIC program addresses issues relating to insertion of solid state devices into antenna systems, such as the reduction in number of bias, control, and signal lines. Program goals, approach, and status are discussed.

  7. An extremely low power voltage reference with high PSRR for power-aware ASICs

    NASA Astrophysics Data System (ADS)

    Jihai, Duan; Dongyu, Deng; Weilin, Xu; Baolin, Wei

    2015-09-01

    An extremely low power voltage reference without resistors is presented for power-aware ASICs. In order to reduce the power dissipation, an Oguey current reference source is used to reduce the static current; a cascode current mirror is used to increase the power supply rejection ratio (PSRR) and reduce the line sensitivity of the circuit. The voltage reference is fabricated in SMIC 0.18-μm CMOS process. The measured results for the voltage reference demonstrate that the temperature coefficient of the voltage is 66 ppm/°C in a range from 25 to 100 °C. The line sensitivity is 0.9% in a supply voltage range of 1.8 to 3.3 V, and PSRR is -49 dB at 100 Hz. The power dissipation is 200 nW. The chip area is 0.01 mm2. The circuit can be used as an elementary circuit block for power-aware ASICs. Project supported by the National Natural Science Foundation of China (Nos. 61161003, 61264001, 61166004) and the Guangxi Natural Science Foundation (No. 2013GXNSFAA019333).

  8. MATRIX: a 15 ps resistive interpolation TDC ASIC based on a novel regular structure

    NASA Astrophysics Data System (ADS)

    Mauricio, J.; Gascón, D.; Ciaglia, D.; Gómez, S.; Fernández, G.; Sanuy, A.

    2016-12-01

    This paper presents a 4-channel TDC ASIC with the following features: 15-ps LSB (9.34 ps after calibration), 10-ps jitter, < 4-ps time resolution, up to 10 MHz of sustained input rate per channel, 45 mW of power consumption and very low area (910×215 μm2) in a commercial 180 nm technology. The main contribution of this work is the novel design of the clock interpolation circuitry based on a resistive interpolation mesh circuit (patented), a two-dimensional regular structure with very good properties in terms of power consumption, area and low process variability.

  9. Development of a dedicated readout ASIC for TPC based X-ray polarimeter

    NASA Astrophysics Data System (ADS)

    Zhang, Hongyan; Deng, Zhi; Li, Hong; Liu, Yinong; Feng, Hua

    2016-07-01

    X-ray polarimetry with time projection chambers was firstly proposed by JK Black in 2007 and has been greatly developed since then. It measured two dimensional photoelectron tracks with one dimensional strip and the other dimension was estimated by the drift time from the signal waveforms. A readout ASIC, APV25, originally developed for CMS silicon trackers was used and has shown some limitations such as waveform sampling depth. A dedicated ASIC was developed for TPC based X-ray polarimeters in this paper. It integrated 32 channel circuits and each channel consisted of an analog front-end and a waveform sampler based on switched capacitor array. The analog front-end has a charge sensitive preamplifier with a gain of 25 mV/fC, a CR-RC shaper with a peaking time of 25 ns, a baseline holder and a discriminator for self-triggering. The SCA has a buffer latency of 3.2 μs with 64 cells operating at 20 MSPS. The ASIC was fabricated in a 0.18 μm CMOS process. The equivalent noise charge (ENC) of the analog front-end was measured to be 274.8 e+34.6 e/pF. The effective resolution of the SCA was 8.8 bits at sampling rate up to 50 MSPS. The total power consumption was 2.8 mW per channel. The ASIC was also tested with real TPC detectors and two dimensional photoelectron tracks have been successfully acquired. More tests and analysis on the sensitivity to the polarimetry are undergoing and will be presented in this paper.

  10. Large dynamic range 64-channel ASIC for CZT or CdTe detectors

    NASA Astrophysics Data System (ADS)

    Glasser, F.; Villard, P.; Rostaing, J. P.; Accensi, M.; Baffert, N.; Girard, J. L.

    2003-08-01

    We present a customized 64-channel ASIC, named ALIX, developed in a 0.8 μm CMOS technology. This circuit is dedicated to measure charges from semi-conductor X-ray detectors like Cadmium Zinc Telluride (CZT) or Cadmium Telluride CdTe. The specificity of ALIX is to be able to measure charges over a very large dynamic range (from 10 fC to 3 nC), and to store eight measurements in a very short time (from every 250 ns to a few ms). Up to eight images are stored inside the ASIC and each image can be read out in 64 μs. A new acquisition sequence can then be started. Two analog readouts are available, one for the X-ray signal and one for the offset and afterglow measurement in case of pulsed X-rays. The outputs are converted into digital values by two off-chip 14 bits Analog-to-Digital Converters (ADC). A first version of ALIX has been tested with CZT and CdTe detectors under high-energy pulsed X-ray photons (20 MeV, 60 ns pulses every 250 ns). We will present the different results of linearity and signal-to-noise ratio. A second version of ALIX has been designed with some corrections. Electrical tests performed on 85 ASICS showed that the corrections were successful. We are now able to integrate them behind a 64×32 pixels 1 mm pitch CZT detector. Such an ASIC could also be used for strip detectors where a large dynamic range and a fast response are necessary.

  11. A simple tachometer circuit

    NASA Technical Reports Server (NTRS)

    Dimeff, J.

    1972-01-01

    Electric circuit to measure frequency of repetitive sinusoidal or rectangular wave is presented. Components of electric circuit and method of operation are explained. Application of circuit as tachometer for automobile is discussed.

  12. Applications of optogenetic and chemogenetic methods to seizure circuits: Where to go next?

    PubMed

    Forcelli, Patrick A

    2017-08-09

    Epilepsy is the quintessential circuit disorder, with seizure activity propagating through anatomically constrained pathways. These pathways, necessary for normal sensory, motor, and cognitive function, are hijacked during seizures. Understanding the network architecture at the level of both local microcircuits and distributed macrocircuits may provide new therapeutic avenues for the treatment of epilepsy. Over the past decade, optogenetic and chemogenetic tools have enabled previously impossible levels of functional circuit mapping in neuroscience. In this review, examples of the application of optogenetics and chemogenetics to epilepsy are raised, the comparative strengths and weaknesses of these approaches are discussed for both preclinical and translational applications, and recent applications of these approaches in other areas of neuroscience are highlighted. These points are raised in an effort to highlight the potential of these methods to address additional unanswered questions in epilepsy. © 2017 Wiley Periodicals, Inc.

  13. Radiation hardness by design for mixed signal infrared readout circuit applications

    NASA Astrophysics Data System (ADS)

    Gaalema, Stephen; Gates, James; Dobyns, David; Pauls, Greg; Wall, Bruce

    2013-09-01

    Readout integrated circuits (ROICs) to support space-based infrared detection applications often have severe radiation tolerance requirements. Radiation hardness-by-design (RHBD) significantly enhances the radiation tolerance of commercially available CMOS and custom radiation hardened fabrication techniques are not required. The combination of application specific design techniques, enclosed gate architecture nFETs and intrinsic thin oxide radiation hardness of 180 nm process node commercial CMOS allows realization of high performance mixed signal circuits. Black Forest Engineering has used RHBD techniques to develop ROICs with integrated A/D conversion that operate over a wide range of temperatures (40K-300K) to support infrared detection. ROIC radiation tolerance capability for 256x256 LWIR area arrays and 1x128 thermopile linear arrays is presented. The use of 130 nm CMOS for future ROIC RHBD applications is discussed.

  14. An Efficient Hardware Circuit for Spike Sorting Based on Competitive Learning Networks.

    PubMed

    Chen, Huan-Yuan; Chen, Chih-Chang; Hwang, Wen-Jyi

    2017-09-28

    This study aims to present an effective VLSI circuit for multi-channel spike sorting. The circuit supports the spike detection, feature extraction and classification operations. The detection circuit is implemented in accordance with the nonlinear energy operator algorithm. Both the peak detection and area computation operations are adopted for the realization of the hardware architecture for feature extraction. The resulting feature vectors are classified by a circuit for competitive learning (CL) neural networks. The CL circuit supports both online training and classification. In the proposed architecture, all the channels share the same detection, feature extraction, learning and classification circuits for a low area cost hardware implementation. The clock-gating technique is also employed for reducing the power dissipation. To evaluate the performance of the architecture, an application-specific integrated circuit (ASIC) implementation is presented. Experimental results demonstrate that the proposed circuit exhibits the advantages of a low chip area, a low power dissipation and a high classification success rate for spike sorting.

  15. The STAR cluster-finder ASIC

    SciTech Connect

    Botlo, M.; LeVine, M.J.; Scheetz, R.A.; Schulz, M.W.; Short, P.; Woods, J.; Crosetto, D.

    1997-12-01

    STAR is a large TPC-based experiment at RHIC, the relativistic heavy ion collider at Brookhaven National Laboratory. The STAR experiment reads out a TPC and an SVT (silicon vertex tracker), both of which require in-line pedestal subtraction, compression of ADC values from 10-bit to 8-bit, and location of time sequences representing responses to charged-particle tracks. The STAR cluster finder ASIC responds to all of these needs. Pedestal subtraction and compression are performed using lookup tables in attached RAM. The authors describe its design and implementation, as well as testing methodology and results of tests performed on foundry prototypes.

  16. The LENA ASIC: Emulating an Obsolete Processor

    NASA Astrophysics Data System (ADS)

    Carayon, J. L.; Mary, L.; Bertrand, J.; Manni, F.

    2013-08-01

    From 10 years, CNES and his partners TAS and Astrium have developed and flown with great success a serie of microsatellites (Demeter, Parasol, Picard etc..), which avionics is based onto a central OBC computer. The OBC is built around a central transputer IMST805 processor, which is now obsolete: the strategic procurement lot done at the beginning of the project is too old now for Quality insurance reasons. The paper describes the LENA ASIC (Logic Emulation for New Architectures) and the approach taken at CNES for the replacement of the Transputer T805 used for Myriade OBC computer to allow production of new microsatellites at a low cost in the next decade.

  17. Introduction to the Highlights of the 26th ASIC Conference.

    PubMed

    Nehlig, Astrid

    2017-09-10

    The 26th ASIC Conference that was held in 2016 in Kunming, China has been marking the 50th anniversary of the creation of ASIC. The meeting in China was well attended by over 400 participants from all over the world and allowed fruitful exchanges among participants from all horizons of coffee science.

  18. Expert System for ASIC Imaging

    NASA Astrophysics Data System (ADS)

    Gupta, Shri N.; Arshak, Khalil I.; McDonnell, Pearse; Boyce, Conor; Duggan, Andrew

    1989-07-01

    With the developments in the techniques of artificial intelligence over the last few years, development of advisory, scheduling and similar class of problems has become very convenient using tools such as PROLOG. In this paper an expert system has been described which helps lithographers and process engineers in several ways. The methodology used is to model each work station according to its input, output and control parameters, combine these work stations in a logical sequence based on past experience and work out process schedule for a job. In addition, all the requirements vis-a-vis a particular job parameters are converted into decision rules. One example is the exposure time, develop time for a wafer with different feature sizes would be different. This expert system has been written in Turbo Prolog. By building up a large number of rules, one can tune the program to any facility and use it for as diverse applications as advisory help, trouble shooting etc. Leitner (1) has described an advisory expert system that is being used at National Semiconductor. This system is quite different from the one being reported in the present paper. The approach is quite different for one. There is stress on job flow and process for another.

  19. Integrated circuit design considerations for spacecraft VLSI implemented in standard CMOS processes

    NASA Astrophysics Data System (ADS)

    Martin, Mark Noel

    2000-10-01

    In this dissertation I will examine issues concerning the use of custom Application Specific Integrated Circuits (ASIC)s, fabricated at commercial foundries, for use in spacecraft. I will examine this subject from the fabrication, device, circuit and system level. I begin with an overview of integrated circuit fabrication and post processing technology used to physically alter the circuit and enhance its electrical performance. I examine the MOS transistor and its variant the Floating-Gate MOS transistor from a device perspective. I discuss a model, derived from the electrostatics of the MOS structure, that is continuous over the entire region of operation while maintaining a small set of physical parameters. Secondly, the operation of the Floating-Gate MOSFET, a device finding increasing usage in adaptive systems, will be presented. The model is then expanded to include the effects of exposure to ionizing radiation on MOSFETs. From a circuit perspective, I will examine the issue of power and energy usage in a digital system. The current-mode design approach will be reviewed as an introduction to Current-Mode-Differential-Logic, a low energy logic family. I will discuss Floating-Gate-Logic, an application of floating-gate transistors to solve the low-power problem by adjusting device thresholds. The second half of the dissertation will be focused on radiation effects in MOS devices. I begin by describing the, rather unpleasant, environment that spacecraft operate in. I continue with a discussion on two main effects of radiation exposure that engineers need to contend with, radiation induced latchup and total-dose exposure. I will provide results from different experiments designed to evaluate a commercial CMOS process's usability for a space application. Finally I describe an application that utilizes the negative effects of radiation on floating-gate MOS devices, an integrated, electronic micro-dosimeter.

  20. A 2013 Survey on Pressure Monitoring in Adult Cardiopulmonary Bypass Circuits: Modes and Applications.

    PubMed

    Rigg, Laura; Searles, Bruce; Darling, Edward Morse

    2014-12-01

    Pressure data acquired from multiple sites of extracorporeal circuits can be an important parameter to monitor for the safe conduct of cardiopulmonary bypass (CPB). Although previous surveys demonstrate that CPB circuit pressure monitoring is widely used, there are very little data cataloging specific applications of this practice. Therefore, the purpose of this study is to survey the perfusion community to catalog 1) primary CPB circuit site pressure monitoring locations; 2) type of manometers used; 3) pressure monitoring interface and servoregulation with pump console; and 4) the rationale and documentation associated with pressure monitoring during CPB. In June 2013, a validated 27-question online survey was sent directly through an e-mail link to the chief perfusionists in the northeast United States. Completed surveys were received from 75 of 117 surveys deployed yielding a 64% response rate. Arterial line pressure monitoring during CPB is reported by 99% with six distinct circuit site locations identified. Cardioplegia system pressure was monitored by 95% of the centers. For vacuum-assisted venous drainage (VAVD) users, the venous pressure was measured by 72% of the responding centers. Arterial line pressure servoregulation of the arterial pump was indicated by 61% of respondents and 75% of centers record arterial line pressure in their perfusion record. Most centers (77%) report the use of a transducer that is integrated into the pump console providing a digital pressure display, whereas 20% combine an aneroid gauge manometer with the integrated digital transducer. This study demonstrates that the practice of arterial line pressure monitoring during CPB is nearly universal. However, the selection of the pressure monitoring site on the circuit, modes of monitoring pressure, and their applications are highly variable across the perfusion community.

  1. A 2013 Survey on Pressure Monitoring in Adult Cardiopulmonary Bypass Circuits: Modes and Applications

    PubMed Central

    Rigg, Laura; Searles, Bruce; Darling, Edward Morse

    2014-01-01

    Abstract: Pressure data acquired from multiple sites of extracorporeal circuits can be an important parameter to monitor for the safe conduct of cardiopulmonary bypass (CPB). Although previous surveys demonstrate that CPB circuit pressure monitoring is widely used, there are very little data cataloging specific applications of this practice. Therefore, the purpose of this study is to survey the perfusion community to catalog 1) primary CPB circuit site pressure monitoring locations; 2) type of manometers used; 3) pressure monitoring interface and servoregulation with pump console; and 4) the rationale and documentation associated with pressure monitoring during CPB. In June 2013, a validated 27-question online survey was sent directly through an e-mail link to the chief perfusionists in the northeast United States. Completed surveys were received from 75 of 117 surveys deployed yielding a 64% response rate. Arterial line pressure monitoring during CPB is reported by 99% with six distinct circuit site locations identified. Cardioplegia system pressure was monitored by 95% of the centers. For vacuum-assisted venous drainage (VAVD) users, the venous pressure was measured by 72% of the responding centers. Arterial line pressure servoregulation of the arterial pump was indicated by 61% of respondents and 75% of centers record arterial line pressure in their perfusion record. Most centers (77%) report the use of a transducer that is integrated into the pump console providing a digital pressure display, whereas 20% combine an aneroid gauge manometer with the integrated digital transducer. This study demonstrates that the practice of arterial line pressure monitoring during CPB is nearly universal. However, the selection of the pressure monitoring site on the circuit, modes of monitoring pressure, and their applications are highly variable across the perfusion community. PMID:26357797

  2. DC, frequency characterization of Dual Gated Graphene FET (GFET) Compact Model and its Circuit Application - Doubler Circuit

    NASA Astrophysics Data System (ADS)

    Bala Tripura Sundari, B.; Arya Raj, K.

    2017-08-01

    A Graphene FET(GFET) based on computational closed form expressions termed as compact model using quasi ballistic approach for circuit simulation is developed. The Verilog - A dual gated GFET model is developed for a channel length of 90 nm and a width of 1 μm and is found to have a better equivalent current and a higher Ion/Ioff ratio has been attained than the single gated model. It demonstrates the effect of body bias on the conductivity characteristics, as shown by the shift of the Dirac point. Also the frequency characterization of the model is obtained and verified by development of frequency multiplier circuits - doubler; the performance has been compared to have maintained in terms of spectral purity but having a better output amplitude validating the DC characteristics of the dual gated VS model used in the doubler circuit.

  3. Low power smartdust receiver with novel applications and improvements of an RF power harvesting circuit

    NASA Astrophysics Data System (ADS)

    Salter, Thomas Steven, Jr.

    Smartdust is the evolution of wireless sensor networks to cubic centimeter dimensions or less. Smartdust systems have advantages in cost, flexibility, and rapid deployment that make them ideal for many military, medical, and industrial applications. This work addresses the limitations of prior works of research to provide sufficient lifetime and performance for Smartdust sensor networks through the design, fabrication and testing of a novel low power receiver for use in a Smartdust transceiver. Through the novel optimization of a multi-stage LNA design and novel application of a power matched Villard voltage doubler circuit, a 1.0 V, 1.6 mW low power On-Off Key (OOK) receiver operating at 2.2 GHz is fabricated using 0.13 um CMOS technology. To facilitate data transfer in adverse RF propagation environments (1/r3 loss), the chip receives a 1 Mbps data signal with a sensitivity of -90 dBm while consuming just 1.6 nJ/bit. The receiver operates without the addition of any external passives facilitating its application in Smartdust scale (cm 3) wireless sensor networks. This represents an order of magnitude decrease in power consumption over receiver designs of comparable sensitivity. In an effort to further extend the lifetime of the Smartdust transceiver, RF power harvesting is explored as a power source. The small scale of Smartdust sensor networks poses unique challenges in the design of RF power scavenging systems. To meet these challenges, novel design improvements to an RF power scavenging circuit integrated directly onto CMOS are presented. These improvements include a reduction in the threshold voltage of diode connected MOSFET and sources of circuit parasitics that are unique to integrated circuits. Utilizing these improvements, the voltage necessary to drive Smartdust circuitry (1 V) with a greater than 20% RF to DC conversion efficiency was generated from RF energy levels measured in the environment (66 uW). This represents better than double the RF to DC

  4. ASIC3, a sensor of acidic and primary inflammatory pain.

    PubMed

    Deval, Emmanuel; Noël, Jacques; Lay, Nadège; Alloui, Abdelkrim; Diochot, Sylvie; Friend, Valérie; Jodar, Martine; Lazdunski, Michel; Lingueglia, Eric

    2008-11-19

    Acid-sensing ion channels (ASICs) are cationic channels activated by extracellular acidosis that are expressed in both central and peripheral nervous systems. Although peripheral ASICs seem to be natural sensors of acidic pain (e.g., in inflammation, ischaemia, lesions or tumours), a direct demonstration is still lacking. We show that approximately 60% of rat cutaneous sensory neurons express ASIC3-like currents. Native as well as recombinant ASIC3 respond synergistically to three different inflammatory signals that are slight acidifications (approximately pH 7.0), hypertonicity and arachidonic acid (AA). Moderate pH, alone or in combination with hypertonicity and AA, increases nociceptors excitability and produces pain suppressed by the toxin APETx2, a specific blocker of ASIC3. Both APETx2 and the in vivo knockdown of ASIC3 with a specific siRNA also have potent analgesic effects against primary inflammation-induced hyperalgesia in rat. Peripheral ASIC3 channels are thus essential sensors of acidic pain and integrators of molecular signals produced during inflammation where they contribute to primary hyperalgesia.

  5. Characteristics of a multichannel low-noise front-end ASIC for CZT-based small animal PET imaging

    NASA Astrophysics Data System (ADS)

    Gao, W.; Liu, H.; Gan, B.; Hu, Y.

    2014-05-01

    In this paper, we present the design and characteristics of a novel low-noise front-end readout application-specific integrated circuit dedicated to CdZnTe (CZT) detectors for a small animal PET imaging system. A low-noise readout method based on the charge integration and the delayed peak detection is proposed. An eight-channel front-end readout prototype chip is designed and implemented in a 0.35 μm CMOS process. The die size is 2.3 mm ×2.3 mm. The prototype chip is tested in different methods including electronic test, energy spectrum test and irradiation test. The input range of the ASIC is from 2000e- to 180,000e-, reflecting the energy of the gamma ray from 11.2 keV to 1 MeV. The gain of the readout channel is 65 mV/fC at the shaping time of 1 μs. The best test result of the equivalent noise charge (ENC) is 58.9 e- at zero farad plus 5.4 e- per picofarad. The nonlinearity and the crosstalk are less than 3% and less than 2%, respectively, at the room temperature. The static power dissipation is about 3 mW/channel.

  6. Development of an ASIC for Si/CdTe detectors in a radioactive substance visualizing system

    NASA Astrophysics Data System (ADS)

    Harayama, Atsushi; Takeda, Shin`ichiro; Sato, Goro; Ikeda, Hirokazu; Watanabe, Shin; Takahashi, Tadayuki

    2014-11-01

    We report on the recent development of a 64-channel analog front-end ASIC for a new gamma-ray imaging system designed to visualize radioactive substances. The imaging system employs a novel Compton camera which consists of silicon (Si) and cadmium telluride (CdTe) detectors. The ASIC is intended for the readout of pixel/pad detectors utilizing Si/CdTe as detector materials, and covers a dynamic range up to 1.4 MeV. The readout chip consists of 64 identical signal channels and was implemented with X-FAB 0.35 μm CMOS technology. Each channel contains a charge-sensitive amplifier, a pole-zero cancellation circuit, a low-pass filter, a comparator, and a sample-hold circuit, along with a Wilkinson-type A-to-D converter. We observed an equivalent noise charge of 500 e- and a noise slope of 5 e-/pF (r.m.s.) with a power consumption of 2.1 mW per channel. The chip works well when connected to Schottky CdTe diodes, and delivers spectra with good energy resolution, such as 12 keV (FWHM) at 662 keV and 24 keV (FWHM) at 1.33 MeV.

  7. A new hyperchaotic circuit with two memristors and its application in image encryption

    NASA Astrophysics Data System (ADS)

    Wang, Zhulin; Min, Fuhong; Wang, Enrong

    2016-09-01

    Memristor is a kind of resistance with a memory function and its special properties decide its broad prospect for application. At present, the focus and difficulty of the research in memristor lie in the establishment of new models and related applications. Therefore, in this paper a new continuous and smooth memristor model is put forward first and the correctness of this new model is proved through the study in the phase trajectory relationship between voltage and current. Then based on Chua's circuit, a new fifth-order hyper-chaotic circuit including two new memristor models is designed and the dimensionless mathematical model is deduced. By the classical nonlinear method of circuit analysis, the dissipation of the new system is put into study in this paper. It is proved through numerical simulation, bifurcation diagram, Lyapunov spectrum that the new system has its unique dynamical behavior. At last, chaotic sequence of the new system is used to encrypt the image and the encrypted histogram, the correlation and anti-attack capability between adjacent pixels and the key sensitivity are emphatically analyzed. It turns out that when applied to image encryption, the newly proposed memristor chaotic system has relatively high safety performance.

  8. Neural CMOS-integrated circuit and its application to data classification.

    PubMed

    Göknar, Izzet Cem; Yildiz, Merih; Minaei, Shahram; Deniz, Engin

    2012-05-01

    Implementation and new applications of a tunable complementary metal-oxide-semiconductor-integrated circuit (CMOS-IC) of a recently proposed classifier core-cell (CC) are presented and tested with two different datasets. With two algorithms-one based on Fisher's linear discriminant analysis and the other based on perceptron learning, used to obtain CCs' tunable parameters-the Haberman and Iris datasets are classified. The parameters so obtained are used for hard-classification of datasets with a neural network structured circuit. Classification performance and coefficient calculation times for both algorithms are given. The CC has 6-ns response time and 1.8-mW power consumption. The fabrication parameters used for the IC are taken from CMOS AMS 0.35-μm technology.

  9. Self-consistent radiation-based simulation of electric arcs: II. Application to gas circuit breakers

    NASA Astrophysics Data System (ADS)

    Iordanidis, A. A.; Franck, C. M.

    2008-07-01

    An accurate and robust method for radiative heat transfer simulation for arc applications was presented in the previous paper (part I). In this paper a self-consistent mathematical model based on computational fluid dynamics and a rigorous radiative heat transfer model is described. The model is applied to simulate switching arcs in high voltage gas circuit breakers. The accuracy of the model is proven by comparison with experimental data for all arc modes. The ablation-controlled arc model is used to simulate high current PTFE arcs burning in cylindrical tubes. Model accuracy for the lower current arcs is evaluated using experimental data on the axially blown SF6 arc in steady state and arc resistance measurements close to current zero. The complete switching process with the arc going through all three phases is also simulated and compared with the experimental data from an industrial circuit breaker switching test.

  10. A Very Fast Switched Attenuator Circuit for Microwave and R.F. Applications

    PubMed Central

    Quine, Richard W.; Tseytlin, Mark; Eaton, Sandra S.; Eaton, Gareth R.

    2011-01-01

    An electronic circuit was designed and constructed that can switch an r.f. signal between two amplitude levels at very fast speed (less than 10 ns). The circuit incorporates a TTL control for convenient interfacing to existing equipment. The attenuation of the more attenuated state can be adjusted to be up to 12 dB more than for the less attenuated state. The initial application was in Pulsed Electron Paramagnetic Resonance (EPR) spectroscopy to produce a π/2 – π pulse sequence with pulses of equal time duration and 6 dB difference in amplitude. A new method for measuring electron spin echoes for narrow, homogeneously-broadened lines is described. PMID:21546999

  11. Two aspects of ASIC function: Synaptic plasticity and neuronal injury.

    PubMed

    Huang, Yan; Jiang, Nan; Li, Jun; Ji, Yong-Hua; Xiong, Zhi-Gang; Zha, Xiang-ming

    2015-07-01

    Extracellular brain pH fluctuates in both physiological and disease conditions. The main postsynaptic proton receptor is the acid-sensing ion channels (ASICs). During the past decade, much progress has been made on protons, ASICs, and neurological disease. This review summarizes the recent progress on synaptic role of protons and our current understanding of how ASICs contribute to various types of neuronal injury in the brain. This article is part of the Special Issue entitled 'Acid-Sensing Ion Channels in the Nervous System'. Copyright © 2015 Elsevier Ltd. All rights reserved.

  12. Mice lacking acid-sensing ion channels (ASIC) 1 or 2, but not ASIC3, show increased pain behaviour in the formalin test.

    PubMed

    Staniland, Amelia A; McMahon, Stephen B

    2009-07-01

    Extracellular acidification is a component of the inflammatory process and may be a factor driving the pain accompanying it. Acid-sensing ion channels (ASICs) are neuronal proton sensors and evidence suggests they are involved in signalling inflammatory pain. The aims of this study were to (1) clarify the role of ASICs in nociception and (2) confirm their involvement in inflammatory pain and determine whether this was subunit specific. This was achieved by (1) direct comparison of the sensitivity of ASIC1, ASIC2, ASIC3 and TRPV1 knockout mice versus wildtype littermates to acute thermal and mechanical noxious stimuli and (2) studying the behavioural responses of each transgenic strain to hind paw inflammation with either complete Freund's adjuvant (CFA) or formalin. Naïve ASIC1(-/-) and ASIC2(-/-) mice responded normally to acute noxious stimuli, whereas ASIC3(-/-) mice were hypersensitive to high intensity thermal stimuli. CFA injection decreased mechanical and thermal withdrawal thresholds for up to 8 days. ASIC2(-/-) mice had increased mechanical sensitivity on day 1 post-CFA compared to wildtype controls. TRPV1(-/-) mice had significantly reduced thermal, but not mechanical, hyperalgesia on all days after inflammation. Following formalin injection, ASIC1(-/-) and ASIC2(-/-), but not ASIC3(-/-) or TRPV1(-/-), mice showed enhanced pain behaviour, predominantly in the second phase of the test. These data suggest that whilst ASICs may play a role in mediating inflammatory pain, this role is likely to be modulatory and strongly dependent on channel subtype.

  13. A 200 C Universal Gate Driver Integrated Circuit for Extreme Environment Applications

    SciTech Connect

    Tolbert, Leon M; Huque, Mohammad A; Islam, Syed K; Blalock, Benjamin J

    2012-01-01

    High-temperature power converters (dc-dc, dc-ac, etc.) have enormous potential in extreme environment applications, including automotive, aerospace, geothermal, nuclear, and well logging. For successful realization of such high-temperature power conversion modules, the associated control electronics also need to perform at high temperature. This paper presents a silicon-on-insulator (SOI) based high-temperature gate driver integrated circuit (IC) incorporating an on-chip low-power temperature sensor and demonstrating an improved peak output current drive over our previously reported work. This driver IC has been primarily designed for automotive applications, where the underhood temperature can reach 200 C. This new gate driver prototype has been designed and implemented in a 0.8 {micro}m, 2-poly, and 3-metal bipolar CMOS-DMOS (Double-Diffused Metal-Oxide Semiconductor) on SOI process and has been successfully tested for up to 200 C ambient temperature driving a SiC MOSFET and a SiC normally-ON JFET. The salient feature of the proposed universal gate driver is its ability to drive power switches over a wide range of gate turn-ON voltages such as MOSFET (0 to 20 V), normally-OFF JFET (-7 to 3 V), and normally-ON JFET (-20 to 0 V). The measured peak output current capability of the driver is around 5 A and is thus capable of driving several power switches connected in parallel. An ultralow-power on-chip temperature supervisory circuit has also been integrated into the die to safeguard the driver circuit against excessive die temperature ({ge}220 C). This approach utilizes increased diode leakage current at higher temperature to monitor the die temperature. The power consumption of the proposed temperature sensor circuit is below 10 {micro}W for operating temperature up to 200 C.

  14. Recovery Act: High-Temperature Circuit Boards for use in Geothermal Well Monitoring Applications

    SciTech Connect

    Hooker, Matthew; Fabian, Paul

    2013-05-01

    The U.S. Department of Energy is leading the development of alternative energy sources that will ensure the long-term energy independence of our nation. One of the key renewable resources currently being advanced is geothermal energy. To tap into the large potential offered by generating power from the heat of the earth, and for geothermal energy to be more widely used, it will be necessary to drill deeper wells to reach the hot, dry rock located up to 10 km beneath the earth’s surface. In this instance, water will be introduced into the well to create a geothermal reservoir. A geothermal well produced in this manner is referred to as an enhanced geothermal system (EGS). EGS reservoirs are typically at depths of 3 to 10 km, and the temperatures at these depths have become a limiting factor in the application of existing downhole technologies. These high temperatures are especially problematic for electronic systems such as downhole data-logging tools, which are used to map and characterize the fractures and high-permeability regions in underground formations. Information provided by these tools is assessed so that underground formations capable of providing geothermal energy can be identified, and the subsequent drilling operations can be accurately directed to those locations. The mapping of geothermal resources involves the design and fabrication of sensor packages, including the electronic control modules, to quantify downhole conditions (300°C temperature, high pressure, seismic activity, etc.). Because of the extreme depths at which these measurements are performed, it is most desirable to perform the sensor signal processing downhole and then transmit the information to the surface. This approach necessitates the use of high-temperature electronics that can operate in the downhole environment. Downhole signal processing in EGS wells will require the development and demonstration of circuit boards that can withstand the elevated temperatures found at these

  15. Active counter electrode in a-SiC electrochemical metallization memory

    NASA Astrophysics Data System (ADS)

    Morgan, K. A.; Fan, J.; Huang, R.; Zhong, L.; Gowers, R.; Ou, J. Y.; Jiang, L.; De Groot, C. H.

    2017-08-01

    Cu/amorphous-SiC (a-SiC) electrochemical metallization memory cells have been fabricated with two different counter electrode (CE) materials, W and Au, in order to investigate the role of CEs in a non-oxide semiconductor switching matrix. In a positive bipolar regime with Cu filaments forming and rupturing, the CE influences the OFF state resistance and minimum current compliance. Nevertheless, a similarity in SET kinetics is seen for both CEs, which differs from previously published SiO2 memories, confirming that CE effects are dependent on the switching layer material or type. Both a-SiC memories are able to switch in the negative bipolar regime, indicating Au and W filaments. This confirms that CEs can play an active role in a non-oxide semiconducting switching matrix, such as a-SiC. By comparing both Au and W CEs, this work shows that W is superior in terms of a higher R OFF/R ON ratio, along with the ability to switch at lower current compliances making it a favourable material for future low energy applications. With its CMOS compatibility, a-SiC/W is an excellent choice for future resistive memory applications.

  16. Development of a Position Decoding ASIC for SPECT using Silicon Photomultiplier

    NASA Astrophysics Data System (ADS)

    Cho, M.; Kim, H.; Lim, K. T.; Cho, G.

    2016-01-01

    Single Photon Emission Computed Tomography(SPECT) is a widely used diagnosis modality for detecting metabolic diseases. In general, SPECT system is consisted of a sensor, a pre-amplifier, position decoding circuits(PDC) and a data acquisition(DAQ) system. Due to such complexity, it is quite costly to assemble SPECT system by putting discrete components together. Moreover, using discrete components would make the system rather bulky. In this work, we designed a channel module ASIC for SPECT system. This system was composed of a transimpedance amplifier(TIA), comparators and digital logics. In this particular module, a TIA was selected as a preamplifier because the decay time and the rise time are shorter than that of other preamplifier topologies. In the proposed module, the amplified pulse from the TIA was split into two separate signals and each signal was then fed into two comparators with different reference levels, e.g., a low and high level. Then an XOR gate combined the comparator outputs and the output of XOR gate was sent to the suceeding digital logic. Furthermore, the output of each component in the module is composed of a signal packet. The packet includes the information on the energy, the time and the position of the incident photon. The energy and position information of a detected radiation can be derived from the output of the D-flipflop(DFF) in the module via time-over-threshold(TOT). The timing information was measured using a delayed rising edge from the low-level referenced comparator. There are several advantages in developing the channel module ASIC. First of all, the ASIC has only digital outputs and thus a correction circuit for analog signal distortion can be neglected. In addition, it is possible to cut down the system production cost because the volume of the system can be reduced due to the compactness of ASIC. The benefits of channel module is not only limited to SPECT but also beneficial to many other radiation detecting systems.

  17. GATING CIRCUITS

    DOEpatents

    Merrill, L.C.

    1958-10-14

    Control circuits for vacuum tubes are described, and a binary counter having an improved trigger circuit is reported. The salient feature of the binary counter is the application of the input signal to the cathode of each of two vacuum tubes through separate capacitors and the connection of each cathode to ground through separate diodes. The control of the binary counter is achieved in this manner without special pulse shaping of the input signal. A further advantage of the circuit is the simplicity and minimum nuruber of components required, making its use particularly desirable in computer machines.

  18. An electronic-nose sensor node based on a polymer-coated surface acoustic wave array for wireless sensor network applications.

    PubMed

    Tang, Kea-Tiong; Li, Cheng-Han; Chiu, Shih-Wen

    2011-01-01

    This study developed an electronic-nose sensor node based on a polymer-coated surface acoustic wave (SAW) sensor array. The sensor node comprised an SAW sensor array, a frequency readout circuit, and an Octopus II wireless module. The sensor array was fabricated on a large K(2) 128° YX LiNbO3 sensing substrate. On the surface of this substrate, an interdigital transducer (IDT) was produced with a Cr/Au film as its metallic structure. A mixed-mode frequency readout application specific integrated circuit (ASIC) was fabricated using a TSMC 0.18 μm process. The ASIC output was connected to a wireless module to transmit sensor data to a base station for data storage and analysis. This sensor node is applicable for wireless sensor network (WSN) applications.

  19. Equivalent-circuit modeling of a MEMS phase detector for phase-locked loop applications

    NASA Astrophysics Data System (ADS)

    Han, Juzheng; Liao, Xiaoping

    2016-05-01

    This paper presents an equivalent-circuit model of a MEMS phase detector and deals with its application in phase-locked loops (PLLs). Due to the dc voltage output of the MEMS phase detector, the low-pass filter which is essential in a conventional PLL can be omitted. Thus, the layout area can be miniaturized and the consumed power can be saved. The signal transmission inside the phase detector is realized in circuit model by waveguide modules while the electric-thermal-electric conversion is illustrated in circuit term based on analogies between thermal and electrical variables. Losses are taken into consideration in the modeling. Measurement verifications for the phase detector model are conducted at different input powers 11, 14 and 17 dBm at 10 GHz. The maximum discrepancies between the simulated and measured results are 0.14, 0.42 and 1.13 mV, respectively. A new structure of PLL is constructed by connecting the presented model directly to a VCO module in the simulation platform. It allows to model the transient behaviors of the PLL at both locked and out of lock conditions. The VCO output frequency is revealed to be synchronized with the reference frequency within the hold range. All the modeling and simulation are performed in Advanced Design System (ADS) software.

  20. Charge pump CMOS circuit based on internal clock voltage boosting for bio-medical applications

    NASA Astrophysics Data System (ADS)

    Anantha, Raghavendra R.; Srivastava, Ashok; Ajmera, Pratul K.

    2005-05-01

    The charge pump CMOS circuit designs are presented for bio-medical applications wherein the clock voltage is boosted internally. Four and six-stage charge pumps are implemented in 1.5 μm n-well CMOS process. The charge pump circuits can be operated in 1.2 V - 3 V power supply voltage range. Outputs of 12.5 V and 17.8 V are measured from four and six-stage charge pumps, respectively with a 3 V power supply. The charge pump circuits can also be used to generate clock voltage higher than the input clock voltage. In the present design, the clock voltages, 8 V and 11 V have been generated from four-stage and six-stage charge pumps, respectively which are nearly 2.5 and 4 times the input clock voltage of 3 V. The technique of boosting the clock internally has been applied in implementation of a bio-implantable battery powered electrical stimulation chip.

  1. ASICs Mediate Pain and Inflammation in Musculoskeletal Diseases

    PubMed Central

    Abdelhamid, Ramy E.

    2015-01-01

    Chronic musculoskeletal pain is debilitating and affects ∼20% of adults. Tissue acidosis is present in painful musculoskeletal diseases like rheumatoid arthritis. ASICs are located on skeletal muscle and joint nociceptors as well as on nonneuronal cells in the muscles and joints, where they mediate nociception. This review discusses the properties of different types of ASICs, factors affecting their pH sensitivity, and their role in musculoskeletal hyperalgesia and inflammation. PMID:26525344

  2. SLVS Transmitter and Receiver for CBM MUCH ASIC

    NASA Astrophysics Data System (ADS)

    Bulbakov, I.

    2017-01-01

    Scalable Low Voltage Signaling (SLVS) Transmitter (Tx) and Receiver (Rx) IP blocks are designed in the UMC 180 nm CMOS technology as component of the readout ASIC for the muon chambers (MUCH) of the Compressed Baryonic Matter (CBM) experiment at FAIR (Darmstadt, Germany). These blocks are a prototype of the physical layer of the e-link interface that is used for ASIC-GBTx connection. The experimental results at 320 Mbit/s are presented.

  3. An equivalent circuit model of supercapacitors for applications in wireless sensor networks

    NASA Astrophysics Data System (ADS)

    Yang, Hengzhao; Zhang, Ying

    2011-04-01

    Energy harvesting technologies have been extensively researched to develop long-lived wireless sensor networks. To better utilize the harvested energy, various energy storage systems are proposed. A simple circuit model is developed to describe supercapacitor behavior, which uses two resistor-capacitor branches with different time constants to characterize the charging and redistribution processes, and a variable leakage resistance (VLR) to characterize the self-discharge process. The voltage and temperature dependence of the VLR values is also discussed. Results show that the VLR model is more accurate than the energy recursive equation (ERE) models for short term wireless sensor network applications.

  4. Development of a flight qualified 100 x 100 mm MCP UV detector using advanced cross strip anodes and associated ASIC electronics

    NASA Astrophysics Data System (ADS)

    Vallerga, John; McPhate, Jason; Tremsin, Anton; Siegmund, Oswald; Raffanti, Rick; Cumming, Harley; Seljak, Andrej; Virta, Vihtori; Varner, Gary

    2016-07-01

    Photon counting microchannel plate (MCP) imagers have been the detector of choice for most UV astronomical missions over the last three decades (e.g. EUVE, FUSE, COS on Hubble etc.) and been mentioned for instruments on future large telescopes in space such as LUVOIR14. Using cross strip anodes, improvements in the MCP laboratory readout technology have resulted in better spatial resolution (x10), temporal resolution (x 1000) and output event rate (x100), all the while operating at lower gain (x10) resulting in lower high voltage requirements and longer MCP lifetimes. A crossed strip anode MCP readout starts with a set of orthogonal conducting strips (e.g. 80 x 80), typically spaced at a 635 micron pitch onto which charge clouds from MCP amplified events land. Each strip has its own charge sensitive amplifier that is sampled continuously by a dedicated analog to digital converter (ADC). All of the ADC digital output lines are fed into a field programmable gate array (FGPA) which can detect charge events landing on the strips, measure the peak amplitudes of those charge events and calculate their spatial centroid along with their time of arrival (X,Y,T) and pass this information to a downstream computer. Laboratory versions of these electronics have demonstrated < 20 microns FWHM spatial resolution, count rates on the order of 2 MHz, and temporal resolution of 1ns. In 2012 our group at U.C. Berkeley, along with our partners at the U. Hawaii, received a NASA Strategic Astrophysics Technology (SAT) grant to raise the TRL of a cross strip detector from 4 to 6 by replacing most of the 19" rack mounted, high powered electronics with application specific integrated circuits (ASICs) which will lower the power, mass, and volume requirements of the detector electronics. We were also tasked to design and fabricate a "standard" 50mm square active area MCP detector incorporating these electronics that can be environmentally qualified for flight (temperature, vacuum, vibration

  5. Experimental characterization of the 192 channel Clear-PEM frontend ASIC coupled to a multi-pixel APD readout of LYSO:Ce crystals

    NASA Astrophysics Data System (ADS)

    Albuquerque, Edgar; Bexiga, Vasco; Bugalho, Ricardo; Carriço, Bruno; Ferreira, Cláudia S.; Ferreira, Miguel; Godinho, Joaquim; Gonçalves, Fernando; Leong, Carlos; Lousã, Pedro; Machado, Pedro; Moura, Rui; Neves, Pedro; Ortigão, Catarina; Piedade, Fernando; Pinheiro, João F.; Rego, Joel; Rivetti, Angelo; Rodrigues, Pedro; Silva, José C.; Silva, Manuel M.; Teixeira, Isabel C.; Teixeira, João P.; Trindade, Andreia; Varela, João

    2009-01-01

    In the framework of the Clear-PEM project for the construction of a high-resolution scanner for breast cancer imaging, a very compact and dense frontend electronics system has been developed for readout of multi-pixel S8550 Hamamatsu APDs. The frontend electronics are instrumented with a mixed-signal Application-Specific Integrated Circuit (ASIC), which incorporates 192 low-noise charge pre-amplifiers, shapers, analog memory cells and digital control blocks. Pulses are continuously stored in memory cells at clock frequency. Channels above a common threshold voltage are readout for digitization by off-chip free-sampling ADCs. The ASIC has a size of 7.3×9.8 mm2 and was implemented in a AMS 0.35 μm CMOS technology. In this paper the experimental characterization of the Clear-PEM frontend ASIC, reading out multi-pixel APDs coupled to LYSO:Ce crystal matrices, is presented. The chips were mounted on a custom test board connected to six APD arrays and to the data acquisition system. Six 32-pixel LYSO:Ce crystal matrices coupled on both sides to APD arrays were readout by two test boards. All 384 channels were operational. The chip power consumption is 660 mW (3.4 mW per channel). A very stable behavior of the chip was observed, with an estimated ENC of 1200-1300e- at APD gain 100. The inter-channel noise dispersion and mean baseline variation is less than 8% and 0.5%, respectively. The spread in the gain between different channels is found to be 1.5%. Energy resolution of 16.5% at 511 keV and 12.8% at 662 keV has been measured. Timing measurements between the two APDs that readout the same crystal is extracted and compared with detailed Monte Carlo simulations. At 511 keV the measured single photon time RMS resolution is 1.30 ns, in very good agreement with the expected value of 1.34 ns.

  6. Monolithic Active Pixel Matrix with Binary Counters (MAMBO) ASIC

    SciTech Connect

    Khalid, Farah F.; Deptuch, Grzegorz; Shenai, Alpana; Yarema, Raymond J.; /Fermilab

    2010-11-01

    Monolithic Active Matrix with Binary Counters (MAMBO) is a counting ASIC designed for detecting and measuring low energy X-rays from 6-12 keV. Each pixel contains analogue functionality implemented with a charge preamplifier, CR-RC{sup 2} shaper and a baseline restorer. It also contains a window comparator which can be trimmed by 4 bit DACs to remove systematic offsets. The hits are registered by a 12 bit ripple counter which is reconfigured as a shift register to serially output the data from the entire ASIC. Each pixel can be tested individually. Two diverse approaches have been used to prevent coupling between the detector and electronics in MAMBO III and MAMBO IV. MAMBO III is a 3D ASIC, the bottom ASIC consists of diodes which are connected to the top ASIC using {mu}-bump bonds. The detector is decoupled from the electronics by physically separating them on two tiers and using several metal layers as a shield. MAMBO IV is a monolithic structure which uses a nested well approach to isolate the detector from the electronics. The ASICs are being fabricated using the SOI 0.2 {micro}m OKI process, MAMBO III is 3D bonded at T-Micro and MAMBO IV nested well structure was developed in collaboration between OKI and Fermilab.

  7. Monolithic active pixel matrix with binary counters (MAMBO III) ASIC

    SciTech Connect

    Khalid, Farah; Deptuch, Grzegorz; Shenai, Alpana; Yarema, Raymond; /Fermilab

    2010-01-01

    Monolithic Active Matrix with Binary Counters (MAMBO) is a counting ASIC designed for detecting and measuring low energy X-rays from 6-12keV. Each pixel contains analogue functionality implemented with a charge preamplifier, CR-RC{sup 2} shaper and a baseline restorer. It also contains a window comparator which can be trimmed by 4 bit DACs to remove systematic offsets. The hits are registered by a 12 bit ripple counter which is reconfigured as a shift register to serially output the data from the entire ASIC. Each pixel can be tested individually. Two diverse approaches have been used to prevent coupling between the detector and electronics in MAMBO III and MAMBO IV. MAMBO III is a 3D ASIC, the bottom ASIC consists of diodes which are connected to the top ASIC using {mu}-bump bonds. The detector is decoupled from the electronics by physically separating them on two tiers and using several metal layers as a shield. MAMBO IV is a monolithic structure which uses a nested well approach to isolate the detector from the electronics. The ASICs are being fabricated using the SOI 0.2 {micro}m OKI process, MAMBO III is 3D bonded at T-Micro and MAMBO IV nested well structure was developed in collaboration between OKI and Fermilab.

  8. Review of hybrid pixel detector readout ASICs for spectroscopic X-ray imaging

    NASA Astrophysics Data System (ADS)

    Ballabriga, R.; Alozy, J.; Campbell, M.; Frojdh, E.; Heijne, E. H. M.; Koenig, T.; Llopart, X.; Marchal, J.; Pennicard, D.; Poikela, T.; Tlustos, L.; Valerio, P.; Wong, W.; Zuber, M.

    2016-01-01

    Semiconductor detector readout chips with pulse processing electronics have made possible spectroscopic X-ray imaging, bringing an improvement in the overall image quality and, in the case of medical imaging, a reduction in the X-ray dose delivered to the patient. In this contribution we review the state of the art in semiconductor-detector readout ASICs for spectroscopic X-ray imaging with emphasis on hybrid pixel detector technology. We discuss how some of the key challenges of the technology (such as dealing with high fluxes, maintaining spectral fidelity, power consumption density) are addressed by the various ASICs. In order to understand the fundamental limits of the technology, the physics of the interaction of radiation with the semiconductor detector and the process of signal induction in the input electrodes of the readout circuit are described. Simulations of the process of signal induction are presented that reveal the importance of making use of the small pixel effect to minimize the impact of the slow motion of holes and hole trapping in the induced signal in high-Z sensor materials. This can contribute to preserve fidelity in the measured spectrum with relatively short values of the shaper peaking time. Simulations also show, on the other hand, the distortion in the energy spectrum due to charge sharing and fluorescence photons when the pixel pitch is decreased. However, using recent measurements from the Medipix3 ASIC, we demonstrate that the spectroscopic information contained in the incoming photon beam can be recovered by the implementation in hardware of an algorithm whereby the signal from a single photon is reconstructed and allocated to the pixel with the largest deposition.

  9. Inverter Circuits Using ZnO Nanoparticle Based Thin-Film Transistors for Flexible Electronic Applications

    PubMed Central

    Vidor, Fábio F.; Meyers, Thorsten; Hilleringmann, Ulrich

    2016-01-01

    Innovative systems exploring the flexibility and the transparency of modern semiconducting materials are being widely researched by the scientific community and by several companies. For a low-cost production and large surface area applications, thin-film transistors (TFTs) are the key elements driving the system currents. In order to maintain a cost efficient integration process, solution based materials are used as they show an outstanding tradeoff between cost and system complexity. In this paper, we discuss the integration process of ZnO nanoparticle TFTs using a high-k resin as gate dielectric. The performance in dependence on the transistor structure has been investigated, and inverted staggered setups depict an improved performance over the coplanar device increasing both the field-effect mobility and the ION/IOFF ratio. Aiming at the evaluation of the TFT characteristics for digital circuit applications, inverter circuits using a load TFT in the pull-up network and an active TFT in the pull-down network were integrated. The inverters show reasonable switching characteristics and V/V gains. Conjointly, the influence of the geometry ratio and the supply voltage on the devices have been analyzed. Moreover, as all integration steps are suitable to polymeric templates, the fabrication process is fully compatible to flexible substrates. PMID:28335282

  10. Nanomaterials, Devices and Interface Circuits: Applications for Optoelectronic and Energy Harvesting

    NASA Astrophysics Data System (ADS)

    Purahmad, Mohsen

    developed a model which strongly conciliates some strongly divergent opinions behind operation of the semiconductor piezoelectric nano-generators. In order to develop such a physics-based model, first the electrostatic potential and depletion width in piezoelectric semiconductor NWs are derived by considering a non-depleted region and a surface depleted region and solving the Poisson equation. By determining the piezoelectric induced charge density, in terms of equivalent density of charges, the effect of piezoelectric charges on the surface depletion region and the distributed electric potential in NW have been investigated. The numerical results demonstrate that the ZnO NWs with smaller radii have a larger surface depletion region which results in a stronger surface potential and depletion region perturbation by induced piezoelectric charges. In the last part of our study on piezoelectric energy harvesters the low power interface circuits which are one of the fundamental building blocks of any self-powered devices has been studied. Utilization of piezoelectric energy harvesters to power electronic devices has attracted significant attention recently. However, the power generated by a piezoelectric energy harvester is too small to power an electronic device directly. Hence, a low power, efficient interface circuit between the energy harvester and a storage unit is essential in any piezoelectric energy harvesting system. Here, a new interface circuit topology for piezoelectric energy harvesting applications is proposed and various design factors for circuit-level optimization are discussed. In the proposed interface circuit a peak detector circuit operating in the sub-threshold region with power dissipation around 160 nW together with a delay circuit form the control block, which is one of the more important units of the piezoelectric energy harvesting systems. (Abstract shortened by UMI.)

  11. Improving Design Efficiency for Large-Scale Heterogeneous Circuits

    NASA Astrophysics Data System (ADS)

    Gregerson, Anthony

    Despite increases in logic density, many Big Data applications must still be partitioned across multiple computing devices in order to meet their strict performance requirements. Among the most demanding of these applications is high-energy physics (HEP), which uses complex computing systems consisting of thousands of FPGAs and ASICs to process the sensor data created by experiments at particles accelerators such as the Large Hadron Collider (LHC). Designing such computing systems is challenging due to the scale of the systems, the exceptionally high-throughput and low-latency performance constraints that necessitate application-specific hardware implementations, the requirement that algorithms are efficiently partitioned across many devices, and the possible need to update the implemented algorithms during the lifetime of the system. In this work, we describe our research to develop flexible architectures for implementing such large-scale circuits on FPGAs. In particular, this work is motivated by (but not limited in scope to) high-energy physics algorithms for the Compact Muon Solenoid (CMS) experiment at the LHC. To make efficient use of logic resources in multi-FPGA systems, we introduce Multi-Personality Partitioning, a novel form of the graph partitioning problem, and present partitioning algorithms that can significantly improve resource utilization on heterogeneous devices while also reducing inter-chip connections. To reduce the high communication costs of Big Data applications, we also introduce Information-Aware Partitioning, a partitioning method that analyzes the data content of application-specific circuits, characterizes their entropy, and selects circuit partitions that enable efficient compression of data between chips. We employ our information-aware partitioning method to improve the performance of the hardware validation platform for evaluating new algorithms for the CMS experiment. Together, these research efforts help to improve the efficiency

  12. A Multi-Functional Planar Lightwave Circuit for Optical Signal Processing Applications

    NASA Astrophysics Data System (ADS)

    Samadi, Payman

    Ultrafast optical signal processing is now a necessary tool in several domains of science and technology such as high-speed telecommunication, biomedicine, microscopy and radar systems. Optical arbitrary waveform generation is an optical signal processing function which has applications in optical telecommunication networks, sampling, and photonically-assisted RF waveform generation. Furthermore, performing optical signal processing in photonic integrated circuits is crucial for system integration and overcoming the speed limitations in electrical to optical conversion. In this thesis, we introduce a silica-based planar lightwave circuit which performs several optical signal processing functions. We start by reviewing the material system used to fabricate the device. We justify the choice of the material for our application and explain the fabrication process and the experiments to characterize the device. Then we introduce the fundamental theory of our device which is based on pulse repetition rate multiplication (PRRM) and shaping. We review the theory of direct time-domain approach to perform the PRRM and shaping. Experiments to measure the impulse response of the device, perform PRRM and polarization dependence characterization is shown as well. Three main applications of our device is presented next. First we use the PLC device with non-linear optics to generate multiple pulse trains at different wavelengths and different repetition rates. Second, we use the fundamental of the previous application to perform demultiplexing of optical time division multiplexed signals. Our approach is flexible in a sense that it can demultiplex any tributary channel of lower rate data, also it works for both amplitude and phase modulated data. Finally, using the second generation of our PLC device, we photonically generate radio frequency waveforms. We are able to generate various pulse shapes which are generally hard to generate using electronics at frequencies up to 80 GHz

  13. Development of arrays of Silicon Drift Detectors and readout ASIC for the SIDDHARTA experiment

    NASA Astrophysics Data System (ADS)

    Quaglia, R.; Schembari, F.; Bellotti, G.; Butt, A. D.; Fiorini, C.; Bombelli, L.; Giacomini, G.; Ficorella, F.; Piemonte, C.; Zorzi, N.

    2016-07-01

    This work deals with the development of new Silicon Drift Detectors (SDDs) and readout electronics for the upgrade of the SIDDHARTA experiment. The detector is based on a SDDs array organized in a 4×2 format with each SDD square shaped with 64 mm2 (8×8) active area. The total active area of the array is therefore 32×16 mm2 while the total area of the detector (including 1 mm border dead area) is 34 × 18mm2. The SIDDHARTA apparatus requires 48 of these modules that are designed and manufactured by Fondazione Bruno Kessler (FBK). The readout electronics is composed by CMOS preamplifiers (CUBEs) and by the new SFERA (SDDs Front-End Readout ASIC) circuit. SFERA is a 16-channels readout ASIC designed in a 0.35 μm CMOS technology, which features in each single readout channel a high order shaping amplifier (9th order Semi-Gaussian complex-conjugate poles) and a high efficiency pile-up rejection logic. The outputs of the channels are connected to an analog multiplexer for the external analog to digital conversion. An on-chip 12-bit SAR ADC is also included. Preliminary measurements of the detectors in the single SDD format are reported. Also measurements of low X-ray energies are reported in order to prove the possible extension to the soft X-ray range.

  14. Performance of an optical encoder based on a nondiffractive beam implemented with a specific photodetection integrated circuit and a diffractive optical element.

    PubMed

    Quintián, Fernando Perez; Calarco, Nicolás; Lutenberg, Ariel; Lipovetzky, José

    2015-09-01

    In this paper, we study the incremental signal produced by an optical encoder based on a nondiffractive beam (NDB). The NDB is generated by means of a diffractive optical element (DOE). The detection system is composed by an application specific integrated circuit (ASIC) sensor. The sensor consists of an array of eight concentric annular photodiodes, each one provided with a programmable gain amplifier. In this way, the system is able to synthesize a nonuniform detectivity. The contrast, amplitude, and harmonic content of the sinusoidal output signal are analyzed. The influence of the cross talk among the annular photodiodes is placed in evidence through the dependence of the signal contrast on the wavelength.

  15. Miniaturized Antennas and Metamaterial-Based Transmission Line Components in Microwave Circuits Applications

    NASA Astrophysics Data System (ADS)

    Chi, Pei-Ling

    This dissertation presents two diversities of miniaturization approaches to the antennas and microwave passive circuit components. The first approach is based on the unique metamaterial transmission line structures. The metamaterial structure or the left-handed structure is an artificial structure that is dispersion engineerable from its constituent parameters. By means of the left-handed transmission lines or the composite right/left-handed (CRLH) transmission lines to replace the conventional microstrip lines, microwave circuit components can be miniaturized via controlling the phase responses at the frequencies of interest, which saves the footprint size. Specifically, this idea was implemented on the dual-band 180°0 and 90° hybrid couplers and both of them demonstrate considerable size reductions in the experiments. On the other hand, the second methodology leading to miniaturization is taking advantage of the slow wave structures. The slow wave structures presented in this dissertation are formed using the capacitive loading periodically. The effective propagation constant beta is enhanced by increasing the effective shunt capacitance in the equivalent circuit model derived from the conventional transmission line theory. The associated guided wavelength is therefore decreased and the same physical structure is capable of operating at lower frequencies. The slow wave structures are employed for compact antenna applications. In particular, the slow wave enhancement factor (SWE), which is defined as the ratio of the loaded to the unloaded propagation constants (beta//beta), is investigated using the loaded unit cell of the equivalent transmission line model and utilized as a design tool for an arbitrary size reduction. It is shown that the SWE agrees very well with miniaturization factor, and therefore load parameters in the circuit model can be readily obtained when a specific size reduction is attempted. Slow wave antennas will be exemplified in the third

  16. A multi-channel fully differential programmable integrated circuit for neural recording application

    NASA Astrophysics Data System (ADS)

    Yun, Gui; Xu, Zhang; Yuan, Wang; Ming, Liu; Weihua, Pei; Kai, Liang; Suibiao, Huang; Bin, Li; Hongda, Chen

    2013-10-01

    A multi-channel, fully differential programmable chip for neural recording application is presented. The integrated circuit incorporates eight neural recording amplifiers with tunable bandwidth and gain, eight 4th-order Bessel switch capacitor filters, an 8-to-1 analog time-division multiplexer, a fully differential successive approximation register analog-to-digital converter (SAR ADC), and a serial peripheral interface for communication. The neural recording amplifier presents a programmable gain from 53 dB to 68 dB, a tunable low cut-off frequency from 0.1 Hz to 300 Hz, and 3.77 μVrms input-referred noise over a 5 kHz bandwidth. The SAR ADC digitizes signals at maximum sampling rate of 20 kS/s per channel and achieves an ENOB of 7.4. The integrated circuit is designed and fabricated in 0.18-μm CMOS mix-signal process. We successfully performed a multi-channel in-vivo recording experiment from a rat cortex using the neural recording chip.

  17. A novel nanoscaled Schottky barrier based transmission gate and its digital circuit applications

    NASA Astrophysics Data System (ADS)

    Kumar, Sunil; Loan, Sajad A.; Alamoud, Abdulrahman M.

    2017-04-01

    In this work we propose and simulate a compact nanoscaled transmission gate (TG) employing a single Schottky barrier based transistor in the transmission path and a single transistor based Sajad-Sunil-Schottky (SSS) device as an inverter. Therefore, just two transistors are employed to realize a complete transmission gate which normally consumes four transistors in the conventional technology. The transistors used to realize the transmission path and the SSS inverter in the proposed TG are the double gate Schottky barrier devices, employing stacks of two metal silicides, platinum silicide (PtSi) and erbium silicide (ErSi). It has been observed that the realization of the TG gate by the proposed technology has resulted into a compact structure, with reduced component count, junctions, interconnections and regions in comparison to the conventional technology. The further focus of this work is on the application part of the proposed technology. So for the first time, the proposed technology has been used to realize various combinational circuits, like a two input AND gate, a 2:1 multiplexer and a two input XOR circuits. It has been observed that the transistor count has got reduced by half in a TG, two input AND gate, 2:1 multiplexer and in a two input XOR gate. Therefore, a significant reduction in transistor count and area requirement can be achieved by using the proposed technology. The proposed technology can be also used to perform the compact realization of other combinational and sequential circuitry in future.

  18. Heterostructure-based high-speed/high-frequency electronic circuit applications

    NASA Astrophysics Data System (ADS)

    Zampardi, P. J.; Runge, K.; Pierson, R. L.; Higgins, J. A.; Yu, R.; McDermott, B. T.; Pan, N.

    1999-08-01

    With the growth of wireless and lightwave technologies, heterostructure electronic devices are commodity items in the commercial marketplace [Browne J. Power-amplifier MMICs drive commercial circuits. Microwaves & RF, 1998. p. 116-24.]. In particular, HBTs are an attractive device for handset power amplifiers at 900 MHz and 1.9 GHz for CDMA applications [Lum E. GaAs technology rides the wireless wave. Proceedings of the 1997 GaAs IC Symposium, 1997. p. 11-13; "Rockwell Ramps Up". Compound Semiconductor, May/June 1997.]. At higher frequencies, both HBTs and p-HEMTs are expected to dominate the marketplace. For high-speed lightwave circuit applications, heterostructure based products on the market for OC-48 (2.5 Gb/s) and OC-192 (10 Gb/s) are emerging [http://www.nb.rockwell.com/platforms/network_access/nahome.html#5.; http://www.nortel.com/technology/opto/receivers/ptav2.html.]. Chips that operate at 40 Gb/ have been demonstrated in a number of research laboratories [Zampardi PJ, Pierson RL, Runge K, Yu R, Beccue SM, Yu J, Wang KC. hybrid digital/microwave HBTs for >30 Gb/s optical communications. IEDM Technical Digest, 1995. p. 803-6; Swahn T, Lewin T, Mokhtari M, Tenhunen H, Walden R, Stanchina W. 40 Gb/s 3 Volt InP HBT ICs for a fiber optic demonstrator system. Proceedings of the 1996 GaAs IC Symposium, 1996. p. 125-8; Suzuki H, Watanabe K, Ishikawa K, Masuda H, Ouchi K, Tanoue T, Takeyari R. InP/InGaAs HBT ICs for 40 Gbit/s optical transmission systems. Proceedings of the 1997 GaAs IC Symposium, 1997. p. 215-8]. In addition to these two markets, another area where heterostructure devices are having significant impact is for data conversion [Walden RH. Analog-to digital convertor technology comparison. Proceedings of the 1994 GaAs IC Symposium, 1994. p. 217-9; Poulton K, Knudsen K, Corcoran J, Wang KC, Nubling RB, Chang M-CF, Asbeck PM, Huang RT. A 6-b, 4 GSa/s GaAs HBT ADC. IEEE J Solid-State Circuits 1995;30:1109-18; Nary K, Nubling R, Beccue S, Colleran W

  19. Synchronous and asynchronous multiplexer circuits for medical imaging realized in CMOS 0.18um technology

    NASA Astrophysics Data System (ADS)

    Długosz, R.; Iniewski, K.

    2007-05-01

    Multiplexers are one of the most important elements in readout front-end ASICs for multi-element detectors in medical imaging. The purpose of these ASICs is to detect signals appearing randomly in many channels and to collect the detected data in an ordered fashion (de-randomization) in order to send it to an external ADC. ASIC output stage functionality can be divided into two: pulse detection and multiplexing. The pulse detection block is responsible for detecting maximum values of signals arriving from the shaper, sending a flag signal indicating that the peak signal has been detected and storing the pulse in an analog memory until read by ADC. The multiplexer in turn is responsible for searching for active flags, controlling the channel that has detected the peak signal and performing reset functions after readout. There are several types of multiplexers proposed in this paper, which can be divided into several classes: synchronous, synchronized and asynchronous. Synchronous circuits require availability of the multiphase clock generator, which increases the power dissipation, but simultaneously provide very convenient mechanism that enables unambiguous choice of the active channel. This characteristics leads to 100% effectiveness in data processing and no data loss. Asynchronous multiplexers do not require clock generators and because of that have simpler structure, are faster and more power efficient, especially when data samples occur seldom at the ASIC's inputs. The main problem of the asynchronous solution is when data on two or more inputs occur almost at the same time, shorter than the multiplexer's reaction time. In this situation some data can be lost. In many applications loss of the order of 1% of the data is acceptable, which makes use of asynchronous multiplexers possible. For applications when the lower loss is desirable a new hierarchy mechanism has been introduced. One of proposed solutions is a synchronized binary tree structure, that uses many

  20. Enzyme-based logic gates and circuits-analytical applications and interfacing with electronics.

    PubMed

    Katz, Evgeny; Poghossian, Arshak; Schöning, Michael J

    2017-01-01

    The paper is an overview of enzyme-based logic gates and their short circuits, with specific examples of Boolean AND and OR gates, and concatenated logic gates composed of multi-step enzyme-biocatalyzed reactions. Noise formation in the biocatalytic reactions and its decrease by adding a "filter" system, converting convex to sigmoid response function, are discussed. Despite the fact that the enzyme-based logic gates are primarily considered as components of future biomolecular computing systems, their biosensing applications are promising for immediate practical use. Analytical use of the enzyme logic systems in biomedical and forensic applications is discussed and exemplified with the logic analysis of biomarkers of various injuries, e.g., liver injury, and with analysis of biomarkers characteristic of different ethnicity found in blood samples on a crime scene. Interfacing of enzyme logic systems with modified electrodes and semiconductor devices is discussed, giving particular attention to the interfaces functionalized with signal-responsive materials. Future perspectives in the design of the biomolecular logic systems and their applications are discussed in the conclusion. Graphical Abstract Various applications and signal-transduction methods are reviewed for enzyme-based logic systems.

  1. Terahertz imaging technique and application in large scale integrated circuit failure inspection

    NASA Astrophysics Data System (ADS)

    Di, Zhi-gang; Yao, Jian-quan; Jia, Chun-rong; Xu, De-gang; Bing, Pi-bin; Yang, Peng-fei; Zheng, Yi-bo

    2010-11-01

    Terahertz ray, as a new style optic source, usually means the electromagnetic whose frequencies lies in between 0.1THz~10THz, the waveband region of the electromagnetic spectrum lies in the gap between microwaves and infrared ray. With the development of laser techniques, quantum trap techniques and compound semiconductor techniques, many new terahertz techniques have been pioneered, motivated in part by the vast range of possible applications for terahertz imaging, sensing, and spectroscopy. THz imaging technique was introduced, and THz imaging can give us not only the density picture but also the phase information within frequency domain. Consequently, images of suspicious objects such as concealed metallic or metal weapons are much sharper and more readily identified when imaged with THz imaging scanners. On the base of these, the application of THz imaging in nondestructive examination, more concretely in large scale circuit failure inspection was illuminated, and the important techniques of this application were introduced, also future prospects were discussed. With the development of correlative technology of THz, we can draw a conclusion that THz imaging technology will have nice application foreground.

  2. Onboard calibration circuit for the DAMPE BGO calorimeter front-end electronics

    NASA Astrophysics Data System (ADS)

    Zhang, De-Liang; Feng, Chang-Qing; Zhang, Jun-Bin; Wang, Qi; Ma, Si-Yuan; Shen, Zhong-Tao; Jiang, Di; Gao, Shan-Shan; Zhang, Yun-Long; Guo, Jian-Hua; Liu, Shu-Bin; An, Qi

    2016-05-01

    DAMPE (DArk Matter Particle Explorer) is a scientific satellite which is mainly aimed at indirectly searching for dark matter in space. One critical sub-detector of the DAMPE payload is the BGO (bismuth germanium oxide) calorimeter, which contains 1848 PMT (photomultiplier tube) dynodes and 16 FEE (Front-End Electronics) boards. VA160 and VATA160, two 32-channel low power ASICs (Application Specific Integrated Circuits), are adopted as the key components on the FEEs to perform charge measurement for the PMT signals. In order to monitor the parameter drift which may be caused by temperature variation, aging, or other environmental factors, an onboard calibration circuit is designed for the VA160 and VATA160 ASICs. It is mainly composed of a 12-bit DAC (Digital to Analog Converter), an operational amplifier and an analog switch. Test results showed that a dynamic range of 0-30 pC with a precision of 5 fC (Root Meam Square, RMS) was achieved, which covers the VA160’s input range. It can be used to compensate for the temperature drift and test the trigger function of the FEEs. The calibration circuit has been implemented for the front-end electronics of the BGO Calorimeter and verified by all the environmental tests for both Qualification Model and Flight Model of DAMPE. The DAMPE satellite was launched at the end of 2015 and the calibration circuit will operate periodically in space. Supported by Strategic Priority Research Program on Space Science of Chinese Academy of Sciences (XDA04040202-4), and National Basic Research Program (973 Program) of China (2010CB833002) and National Natural Science Foundation of China (11273070)

  3. A low-noise 64-channel front-end readout ASIC for CdZnTe detectors aimed to hard X-ray imaging systems

    NASA Astrophysics Data System (ADS)

    Gan, B.; Wei, T.; Gao, W.; Liu, H.; Hu, Y.

    2016-04-01

    In this paper, we report on the recent development of a 64-channel low-noise front-end readout ASIC for CdZnTe detectors aimed to hard X-ray imaging systems. The readout channel is comprised of a charge sensitive amplifier, a leakage current compensation circuit, a CR-RC shaper, two S-K filters, an inverse proportional amplifier, a peak-detect-and-hold circuit, a discriminator and trigger logic, a time sequence control circuit and a driving buffer. The readout ASIC is implemented in TSMC 0.35 μm mixed-signal CMOS technology, the die size of the prototype chip is 2.7 mm×8.0 mm. The overall gain of the readout channel is 200 mV/fC, the power consumption is less than 8 mW/channel, the linearity error is less than 1%, the inconsistency among the channels is less than 2.86%, and the equivalent noise charge of a typical channel is 66 e- at zero farad plus 14 e- per picofarad. By connecting this readout ASIC to an 8×8 pixel CdZnTe detector, we obtained an energy spectrum, the energy resolution of which is 4.5% at the 59.5 keV line of 241Am source.

  4. Graphene-based tunable non-foster circuit for VHF applications

    NASA Astrophysics Data System (ADS)

    Tian, Jing; Nagarkoti, Deepak Singh; Rajab, Khalid Z.; Hao, Yang

    2016-06-01

    This paper presents a negative impedance converter (NIC) based on graphene field effect transistors (GFETs) for VHF applications. The NIC is designed following Linvill's open circuit stable (OCS) topology. The DC modelling parameters of GFET are extracted from a device measured by Meric et al. [IEEE Electron Devices Meeting, 23.2.1 (2010)] Estimated parasitics are also taken into account. Simulation results from Keysight Advanced Design System (ADS) show good NIC performance up to 200 MHz and the value of negative capacitance is directly proportional to the capacitive load. In addition, it has been shown that by varying the supply voltage the value of negative capacitance can also be tuned. The NIC stability has been tested up to 2 GHz (10 times the maximum operation frequency) using Nyquist stability criterion to ensure there are no oscillation issues.

  5. Carbon Nanotubes, Semiconductor Nanowires and Graphene for Thin Film Transistor and Circuit Applications

    NASA Astrophysics Data System (ADS)

    Pribat, Didier; Cojocaru, Costel-Sorin

    2011-03-01

    In this paper, we briefly review the use of carbon nanotubes and semiconductor nanowires, which represent a new class of nanomaterials actively studied for thin film transistors and electronics applications. Although these nanomaterials are usually synthesised at moderate to high temperatures, they can be transferred to any kind of substrate after growth, paving the way for the fabrication of flexible displays and large area electronics systems on plastic. Over the past few years, the field has progressed well beyond the realisation of elementary devices, since active matrix displays driven by nanowire thin film transistors have been demonstrated, as well as the fabrication of medium scale integrated circuits based on random arrays of carbon nanotubes. Also, graphene, a new nanomaterial has appeared in the landscape; although it is a zero gap semiconductor, it can still be used to make transistors, provided narrow ribbons or bilayers are used. Graphene is also a serious contender for the replacement of oxide-based transparent conducting films.

  6. Graphene-based tunable non-foster circuit for VHF applications

    SciTech Connect

    Tian, Jing; Nagarkoti, Deepak Singh; Rajab, Khalid Z.; Hao, Yang

    2016-06-15

    This paper presents a negative impedance converter (NIC) based on graphene field effect transistors (GFETs) for VHF applications. The NIC is designed following Linvill’s open circuit stable (OCS) topology. The DC modelling parameters of GFET are extracted from a device measured by Meric et al. [IEEE Electron Devices Meeting, 23.2.1 (2010)] Estimated parasitics are also taken into account. Simulation results from Keysight Advanced Design System (ADS) show good NIC performance up to 200 MHz and the value of negative capacitance is directly proportional to the capacitive load. In addition, it has been shown that by varying the supply voltage the value of negative capacitance can also be tuned. The NIC stability has been tested up to 2 GHz (10 times the maximum operation frequency) using Nyquist stability criterion to ensure there are no oscillation issues.

  7. Radiation-hardened CMOS integrated circuit development for space nuclear power applications

    NASA Astrophysics Data System (ADS)

    Gover, J. E.; Gregory, B. L.

    Examination of the types of systems required for space nuclear power applications suggests a need for microelectronics technology that can function during and after exposure to radiation levels exceeding 1 x 10 to the 16th neutrons/sq cm and gamma ray doses in excess of 1 x 10 to the 7th rad(Si). Radiation-hardened Complimentary Metal Oxide Silicon and Silicon Nitride Oxide Silicon (SNOS) ICs presently in development at Sandia National Laboratories' Center for Radiation-Hardened Microelectronics satisfy these radiation requirements. Future integrated circuit development will further advance the radiation hardness capabilities while extending the IC technology to 32-bit enhanced microprocessors and 1-Mbyte SNOS EEPROM memories.

  8. Thermocouple-Signal-Conditioning Circuit

    NASA Technical Reports Server (NTRS)

    Simon, Richard A.

    1991-01-01

    Thermocouple-signal-conditioning circuit acting in conjunction with thermocouple, exhibits electrical behavior of voltage in series with resistance. Combination part of input bridge circuit of controller. Circuit configured for either of two specific applications by selection of alternative resistances and supply voltages. Includes alarm circuit detecting open circuit in thermocouple and provides off-scale output to signal malfunctions.

  9. a Circuit Model of Quantum Cascade Lasers Applicable to both Small and Large Current Drives

    NASA Astrophysics Data System (ADS)

    Haldar, M. K.; Webb, J. F.

    2010-06-01

    In this paper, a circuit model is devised to analyze nonlinear behaviour of quantum cascade lasers. Such nonlinear behavior influences the light output when the laser is driven by currents comparable to the average (DC) current. The simplified 2-level rate equations are first improved. Next, the circuit model is obtained following the approach for interband lasers. The difference between the circuit models of quantum cascade lasers and interband lasers is pointed out. The circuit model is simpler compared to that obtained from a 3-level model. Unlike a circuit model derived earlier from the 2-level model, the present model can handle both small and large current drives.

  10. Catalytic nucleic acids (DNAzymes) as functional units for logic gates and computing circuits: from basic principles to practical applications.

    PubMed

    Orbach, Ron; Willner, Bilha; Willner, Itamar

    2015-03-11

    This feature article addresses the implementation of catalytic nucleic acids as functional units for the construction of logic gates and computing circuits, and discusses the future applications of these systems. The assembly of computational modules composed of DNAzymes has led to the operation of a universal set of logic gates, to field programmable logic gates and computing circuits, to the development of multiplexers/demultiplexers, and to full-adder systems. Also, DNAzyme cascades operating as logic gates and computing circuits were demonstrated. DNAzyme logic systems find important practical applications. These include the use of DNAzyme-based systems for sensing and multiplexed analyses, for the development of controlled release and drug delivery systems, for regulating intracellular biosynthetic pathways, and for the programmed synthesis and operation of cascades.

  11. ASIC1 promotes differentiation of neuroblastoma by negatively regulating Notch signaling pathway.

    PubMed

    Liu, Mingli; Inoue, Koichi; Leng, Tiandong; Zhou, An; Guo, Shanchun; Xiong, Zhi-Gang

    2017-01-31

    In neurons, up-regulation of Notch activity either inhibits neurite extension or causes retraction of neurites. Conversely, inhibition of Notch1 facilitates neurite extension. Acid-sensing ion channels (ASICs) are a family of proton-gated cation channels, which play critical roles in synaptic plasticity, learning and memory and spine morphogenesis. Our pilot proteomics data from ASIC1a knock out mice implicated that ASIC1a may play a role in regulating Notch signaling, therefore, we explored whether or not ASIC1a regulates neurite growth during neuronal development through Notch signaling. In this study, we determined the effects of ASIC1a on neurite growth in a mouse neuroblastoma cell line, NS20Y cells, by modulating ASIC1a expression. We also determined the relationship between ASIC1a and Notch signaling on neuronal differentiation. Our results showed that down-regulation of ASIC1a in NS20Y cells inhibits CPT-cAMP induced neurite growth, while over expression of ASIC1a promotes its growth. In addition, down-regulation of ASIC1a increased the expression of Notch1 and its target gene Survivin while inhibitor of Notch significantly prevented the neurite extension induced by ASIC1a in NS20Y cells. These data indicate that Notch1 signaling may be required for ASIC1a-mediated neurite growth and neuronal differentiation.

  12. Development of the multichannel data processing ASIC design flow

    NASA Astrophysics Data System (ADS)

    Ivanov, P. Y.; Atkin, E. V.; Normanov, D. D.; Shumkin, O. V.

    2017-01-01

    In modern multichannel data processing digital systems the number of channels ranges from some hundred thousand to millions. The basis of the elemental base of these systems are ASICs. Their most important characteristics are performance, power consumption and occupied area. ASIC design is a time and labor consuming process. In order to improve performance and reduce the designing time it is proposed to supplement the standard design flow with an optimization stage of the channel parameters based on the most efficient use of chip area and power consumption.

  13. Printed circuit boards as platform for disposable lab-on-a-chip applications

    NASA Astrophysics Data System (ADS)

    Leiterer, Christian; Urban, Matthias; Fritzsche, Wolfgang; Goldys, Ewa; Inglis, David

    2015-12-01

    An increasing demand in performance from electronic devices has resulted in continuous shrinking of electronic components. This shrinkage has demanded that the primary integration platform, the printed circuit board (PCB), follow this same trend. Today, PCB companies offer ~100 micron sized features (depth and width) which mean they are becoming suitable as physical platforms for Lab-on-a-Chip (LOC) and microfluidic applications. Compared to current lithographic based fluidic approaches; PCB technology offers several advantages that are useful for this technology. These include: Being easily designed and changed using free software, robust structures that can often be reused, chip layouts that can be ordered from commercial PCB suppliers at very low cost (1 AUD each in this work), and integration of electrodes at no additional cost. Here we present the application of PCB technology in connection with microfluidics for several biomedical applications. In case of commercialization the costs for each device can be even further decreased to approximately one tenth of its current cost.

  14. Integrated circuit for SAW and MEMS sensors

    NASA Astrophysics Data System (ADS)

    Fischer, Wolf-Joachim; Koenig, Peter; Ploetner, Matthias; Hermann, Rudiger; Stab, Helmut

    2001-11-01

    The sensor processor circuit has been developed for hand-held devices used in industrial and environmental applications, such as on-line process monitoring. Thereby devices with SAW sensors or MEMS resonators will benefit from this processor especially. Up to 8 sensors can be connected to the circuit as multisensors or sensor arrays. Two sensor processors SP1 and SP2 for different applications are presented in this paper. The SP-1 chip has a PCMCIA interface which can be used for the program and data transfer. SAW sensors which are working in the frequency range from 80 MHz to 160 MHz can be connected to the processor directly. It is possible to use the new SP-2 chip fabricated in a 0.5(mu) CMOS process for SAW devices with a maximum frequency of 600 MHz. An on-chip analog-digital-converter (ADC) and 6 PWM modules support the development of high-miniaturized intelligent sensor systems We have developed a multi-SAW sensor system with this ASIC that manages the requirements on control as well as signal generation and storage and provides an interface to the PC and electronic devices on the board. Its low power consumption and its PCMCIA plug fulfil the requirements of small size and mobility. For this application sensors have been developed to detect hazardous gases in ambient air. Sensors with differently modified copper-phthalocyanine films are capable of detecting NO2 and O3, whereas those with a hyperbranched polyester film respond to NH3.

  15. Fabrication, electrical characterization, and detection application of graphene-sheet-based electrical circuits.

    PubMed

    Peng, Yitian; Lei, Jianping

    2014-01-01

    The distribution of potential, electric field, and gradient of square of electric field was simulated via a finite element method for dielectrophoresis (DEP) assembly. Then reduced graphene oxide sheets (RGOS)- and graphene oxide sheets (GOS)-based electrical circuits were fabricated via DEP assembly. The mechanically exfoliated graphene sheets (MEGS)-based electrical circuit was also fabricated for comparison. The electrical transport properties of three types of graphene-based electrical circuits were measured. The MEGS-based electrical circuit possesses the best electrical conductivity, and the GOS-based electrical circuit has the poorest electrical conductivity among all three circuits. The three types of electrical circuits were applied for the detection of copper ions (Cu(2+)). The RGOS-based electrical circuit can detect the Cu(2+) when the concentration of Cu(2+) was as low as 10 nM in solution. The GOS-based electrical circuit can only detect Cu(2+) after chemical reduction. The possible mechanism of electron transfer was proposed for the detection. The facile fabrication method and excellent performance imply the RGOS-based electrical circuit has great potential to be applied to metal ion sensors.

  16. Modification of circuit module of dye-sensitized solar cells (DSSC) for solar windows applications

    NASA Astrophysics Data System (ADS)

    Hastuti, S. D.; Nurosyid, F.; Supriyanto, A.; Suryana, R.

    2016-11-01

    This research has been conducted to obtain a modification of circuit producing the best efficiency of solar window modules as an alternative energy for daily usage. Solar window module was constructed by DSSC cells. In the previous research, solar window was created by a single cell of DSSC. Because it had small size, it could not be applied in the manufacture of solar window. Fabrication of solar window required a larger size of DSSC cell. Therefore, in the next research, a module of solar window was fabricated by connecting few cells of DSSC. It was done by using external electrical circuit method which was modified in the formation of series circuit and parallel circuit. Its fabrication used six cells of DSSC with the size of each cell was 1 cm × 9 cm. DSSC cells were sandwich structures constructed by an active layer of TiO2 as the working electrode, electrolyte solution, dye, and carbon layer. Characterization of module was started one by one, from one cell, two cells, three cells, until six cells of a module. It was conducted to recognize the increasing efficiency value as the larger surface area given. The efficiency of solar window module with series circuit was 0.06%, while using parallel circuit was 0.006%. Module with series circuit generated the higher voltage as the larger surface area. Meanwhile, module through parallel circuit tended to produce the constant voltage as the larger surface area. It was caused by the influence of resistance within the cable in each module. Module with circuit parallel used a longer cable than module with series circuit, so that its resistance increased. Therefore, module with parallel circuit generated voltage that tended to be constant and resulted small efficiency compared to the module with series circuit. It could be concluded that series external circuit was the best modification which could produce the higher efficiency.

  17. Characterization of Novel Thin-Films and Structures for Integrated Circuit and Photovoltaic Applications

    NASA Astrophysics Data System (ADS)

    Zhao, Zhao

    Thin films have been widely used in various applications. This research focuses on the characterization of novel thin films in the integrated circuits and photovoltaic techniques. The ion implanted layer in silicon can be treated as ion implanted thin film, which plays an essential role in the integrated circuits fabrication. Novel rapid annealing methods, i.e. microwave annealing and laser annealing, are conducted to activate ion dopants and repair the damages, and then are compared with the conventional rapid thermal annealing (RTA). In terms of As+ and P+ implanted Si, the electrical and structural characterization confirms that the microwave and laser annealing can achieve more efficient dopant activation and recrystallization than conventional RTA. The efficient dopant activation in microwave annealing is attributed to ion hopping under microwave field, while the liquid phase growth in laser annealing provides its efficient dopant activation. The characterization of dopants diffusion shows no visible diffusion after microwave annealing, some extent of end range of diffusion after RTA, and significant dopant diffusion after laser annealing. For photovoltaic applications, an indium-free novel three-layer thin-film structure (transparent composited electrode (TCE)) is demonstrated as a promising transparent conductive electrode for solar cells. The characterization of TCE mainly focuses on its optical and electrical properties. Transfer matrix method for optical transmittance calculation is validated and proved to be a desirable method for predicting transmittance of TCE containing continuous metal layer, and can estimate the trend of transmittance as the layer thickness changes. TiO2/Ag/TiO2 (TAgT) electrode for organic solar cells (OSCs) is then designed using numerical simulation and shows much higher Haacke figure of merit than indium tin oxide (ITO). In addition, TAgT based OSC shows better performance than ITO based OSC when compatible hole transfer layer

  18. System-Level Integrated Circuit (SLIC) Technology Development for Phased Array Antenna Applications

    NASA Technical Reports Server (NTRS)

    Windyka, John A.; Zablocki, Ed G.

    1997-01-01

    This report documents the efforts and progress in developing a 'system-level' integrated circuit, or SLIC, for application in advanced phased array antenna systems. The SLIC combines radio-frequency (RF) microelectronics, digital and analog support circuitry, and photonic interfaces into a single micro-hybrid assembly. Together, these technologies provide not only the amplitude and phase control necessary for electronic beam steering in the phased array, but also add thermally-compensated automatic gain control, health and status feedback, bias regulation, and reduced interconnect complexity. All circuitry is integrated into a compact, multilayer structure configured for use as a two-by-four element phased array module, operating at 20 Gigahertz, using a Microwave High-Density Interconnect (MHDI) process. The resultant hardware is constructed without conventional wirebonds, maintains tight inter-element spacing, and leads toward low-cost mass production. The measured performances and development issues associated with both the two-by-four element module and the constituent elements are presented. Additionally, a section of the report describes alternative architectures and applications supported by the SLIC electronics. Test results show excellent yield and performance of RF circuitry and full automatic gain control for multiple, independent channels. Digital control function, while suffering from lower manufacturing yield, also proved successful.

  19. The RFET—a reconfigurable nanowire transistor and its application to novel electronic circuits and systems

    NASA Astrophysics Data System (ADS)

    Mikolajick, T.; Heinzig, A.; Trommer, J.; Baldauf, T.; Weber, W. M.

    2017-04-01

    With CMOS scaling reaching physical limits in the next decade, new approaches are required to enhance the functionality of electronic systems. Reconfigurability on the device level promises to realize more complex systems with a lower device count. In the last five years a number of interesting concepts have been proposed to realize such a device level reconfiguration. Among these the reconfigurable field effect transistor (RFET), a device that can be configured between an n-channel and p-channel behavior by applying an electrical signal, can be considered as an end-of-roadmap extension of current technology with only small modifications and even simplifications to the process flow. This article gives a review on the RFET basics and current status. In the first sections state-of-the-art of reconfigurable devices will be summarized and the RFET will be introduced together with related devices based on silicon nanowire technology. The device optimization with respect to device symmetry and performance will be discussed next. The potential of the RFET device technology will then be shown by discussing selected circuit implementations making use of the unique advantages of this device concept. The basic device concept was also extended towards applications in flexible devices and sensors, also extending the capabilities towards so-called More-than-Moore applications where new functionalities are implemented in CMOS-based processes. Finally, the prospects of RFET device technology will be discussed.

  20. Silicon-On-Insulator (SOI) Devices and Mixed-Signal Circuits for Extreme Temperature Applications

    NASA Technical Reports Server (NTRS)

    Patterson, Richard; Hammoud, Ahmad; Elbuluk, Malik

    2008-01-01

    Electronic systems in planetary exploration missions and in aerospace applications are expected to encounter extreme temperatures and wide thermal swings in their operational environments. Electronics designed for such applications must, therefore, be able to withstand exposure to extreme temperatures and to perform properly for the duration of the missions. Electronic parts based on silicon-on-insulator (SOI) technology are known, based on device structure, to provide faster switching, consume less power, and offer better radiation-tolerance compared to their silicon counterparts. They also exhibit reduced current leakage and are often tailored for high temperature operation. However, little is known about their performance at low temperature. The performance of several SOI devices and mixed-signal circuits was determined under extreme temperatures, cold-restart, and thermal cycling. The investigations were carried out to establish a baseline on the functionality and to determine suitability of these devices for use in space exploration missions under extreme temperatures. The experimental results obtained on selected SOI devices are presented and discussed in this paper.

  1. Development of custom radiation-tolerant DCDC converter ASICs

    NASA Astrophysics Data System (ADS)

    Faccio, F.; Michelis, S.; Orlandi, S.; Blanchot, G.; Fuentes, C.; Saggini, S.; Ongaro, F.

    2010-11-01

    Based on a detailed study of the radiation tolerance of high-voltage transistors, 2 commercial CMOS technologies have been selected for the design of synchronous buck DCDC converter ASICs. Three prototype converters have been produced, embedding increasingly sophisticated functions. The electrical and radiation performance of these prototypes is presented.

  2. ENaCs and ASICs as therapeutic targets.

    PubMed

    Qadri, Yawar J; Rooj, Arun K; Fuller, Catherine M

    2012-04-01

    The epithelial Na(+) channel (ENaC) and acid-sensitive ion channel (ASIC) branches of the ENaC/degenerin superfamily of cation channels have drawn increasing attention as potential therapeutic targets in a variety of diseases and conditions. Originally thought to be solely expressed in fluid absorptive epithelia and in neurons, it has become apparent that members of this family exhibit nearly ubiquitous expression. Therapeutic opportunities range from hypertension, due to the role of ENaC in maintaining whole body salt and water homeostasis, to anxiety disorders and pain associated with ASIC activity. As a physiologist intrigued by the fundamental mechanics of salt and water transport, it was natural that Dale Benos, to whom this series of reviews is dedicated, should have been at the forefront of research into the amiloride-sensitive sodium channel. The cloning of ENaC and subsequently the ASIC channels has revealed a far wider role for this channel family than was previously imagined. In this review, we will discuss the known and potential roles of ENaC and ASIC subunits in the wide variety of pathologies in which these channels have been implicated. Some of these, such as the role of ENaC in Liddle's syndrome are well established, others less so; however, all are related in that the fundamental defect is due to inappropriate channel activity.

  3. ENaCs and ASICs as therapeutic targets

    PubMed Central

    Qadri, Yawar J.; Rooj, Arun K.

    2012-01-01

    The epithelial Na+ channel (ENaC) and acid-sensitive ion channel (ASIC) branches of the ENaC/degenerin superfamily of cation channels have drawn increasing attention as potential therapeutic targets in a variety of diseases and conditions. Originally thought to be solely expressed in fluid absorptive epithelia and in neurons, it has become apparent that members of this family exhibit nearly ubiquitous expression. Therapeutic opportunities range from hypertension, due to the role of ENaC in maintaining whole body salt and water homeostasis, to anxiety disorders and pain associated with ASIC activity. As a physiologist intrigued by the fundamental mechanics of salt and water transport, it was natural that Dale Benos, to whom this series of reviews is dedicated, should have been at the forefront of research into the amiloride-sensitive sodium channel. The cloning of ENaC and subsequently the ASIC channels has revealed a far wider role for this channel family than was previously imagined. In this review, we will discuss the known and potential roles of ENaC and ASIC subunits in the wide variety of pathologies in which these channels have been implicated. Some of these, such as the role of ENaC in Liddle's syndrome are well established, others less so; however, all are related in that the fundamental defect is due to inappropriate channel activity. PMID:22277752

  4. ASIC2 Subunits Target Acid-Sensing Ion Channels to the Synapse via an Association with PSD-95

    PubMed Central

    Zha, Xiang-ming; Costa, Vivian; Harding, Anne Marie S.; Reznikov, Leah; Benson, Christopher J.; Welsh, Michael J.

    2009-01-01

    Acid-sensing ion channel-1a (ASIC1a) mediates H+-gated current to influence normal brain physiology and impact several models of disease. Although ASIC2 subunits are widely expressed in brain and modulate ASIC1a current, their function remains poorly understood. We identified ASIC2a in dendrites, dendritic spines, and brain synaptosomes. This localization largely relied on ASIC2a binding to PSD-95 and matched that of ASIC1a, which does not co-immunoprecipitate with PSD-95. We found that ASIC2 and ASIC1a associated in brain, and through its interaction with PSD-95, ASIC2 increased ASIC1a localization in dendritic spines. Consistent with earlier work showing that acidic pH elevated spine [Ca2+]i by activating ASIC1a, loss of ASIC2 decreased the percentage of spines responding to acid. Moreover, like a reduction of ASIC1a, the number of spine synapses fell in ASIC2-/- neurons. These results indicate that ASIC2 facilitates ASIC1a localization and function in dendritic spines and suggest that the two subunits work in concert to regulate neuronal function. PMID:19571134

  5. Correlation between stimulation strength and onset time of signal traveling within the neocortical neural circuits under caffeine application.

    PubMed

    Yoshimura, Hiroshi; Honjo, Miho; Sugai, Tokio; Kaneyama, Keiseki; Segami, Natsuki; Kato, Nobuo

    2011-08-01

    In general, strength of input to neocortical neural circuits affects the amplitude of postsynaptic potentials (PSPs), thereby modulating the way signals are transmitted within the circuits. Caffeine is one of the pharmacological agents able to modulate synaptic activities. The present study investigated how strength of input affects signal propagation in neocortical circuits under the application of caffeine. Spatio-temporal neural activities were observed from visual cortical slices of rats using optical recording methods with voltage-sensitive dye. Electrical stimulations were applied to white matter in the primary visual cortex with bath-application of caffeine. When the strength of stimulation was 0.3mA, signals propagated from the site of stimulation in the primary visual cortex toward the secondary visual cortex along vertical and horizontal pathways. When stimulation strength was reduced from 0.3mA to 0.07mA, start of signal propagation was delayed about 25ms without affecting field PSP amplitude or the manner of signal propagation. Conversely, co-application of caffeine and d-2-amino-5-phosphonovaleric acid (d-AP5) did not induce delays in signal start. These findings suggest that conversion of neural code from amplitude code to temporal code is inducible at the level of neocortical circuits in an N-methyl-d-aspartate (NMDA) receptor activity-dependent manner.

  6. The application of deterministic spectral domain method to the analysis of planar circuit discontinuities on open substrates

    NASA Astrophysics Data System (ADS)

    McLean, James Stuart; Itoh, Tatsuo

    1990-08-01

    A deterministic formulation of the method of moments carried out in the spectral domain is extended to include the effects of two-dimensional, two-component current flow in planar transmission line discontinuities on open substrates. The method includes the effects of space-wave and surface-wave radiation through the use of the exact spectral domain Green's function. The procedure and formulation of the method are described in detail. Also, techniques used to increase the numerical efficiency are described in detail. The method is used to determine accurate circuit models of three types of planar circuit discontinuities on open substrates: microstrip open-end discontinuities, slotline short-circuit discontinuities, and microstrip gap discontinuities. The analysis is then applied to gap-coupled resonators. The coupling between cascaded gap discontinuities is shown to be significant when the substrate is electrically thick since surface wave excitation is strong. Possibilities for further applications of the method to more complicated discontinuities are discussed.

  7. ASIC1 contributes to pulmonary vascular smooth muscle store-operated Ca(2+) entry.

    PubMed

    Jernigan, Nikki L; Paffett, Michael L; Walker, Benjimen R; Resta, Thomas C

    2009-08-01

    Acid-sensing ion channels (ASIC) are voltage-insensitive, cationic channels that have recently been identified in vascular smooth muscle (VSM). It is possible that ASIC contribute to vascular reactivity via Na(+) and Ca(2+) conductance; however, their function in VSM is largely unknown. In pulmonary VSM, store-operated Ca(2+) entry (SOCE) plays a significant role in vasoregulatory mechanisms such as hypoxic pulmonary vasoconstriction and receptor-mediated arterial constriction. Therefore, we hypothesized that ASIC contribute to SOCE in pulmonary VSM. We examined SOCE resulting from depletion of intracellular Ca(2+) stores with cyclopiazonic acid in isolated small pulmonary arteries and primary cultured pulmonary arterial smooth muscle cells by measuring 1) changes in VSM [Ca(2+)](i) using fura-2 indicator dye, 2) Mn(2+) quenching of fura-2 fluorescence, and 3) store-operated Ca(2+) and Na(+) currents using conventional whole cell patch-clamp configuration in voltage-clamp mode. The role of ASIC was assessed by the use of the ASIC inhibitors, amiloride, benzamil, and psalmotoxin 1, or siRNA directed towards ASIC1, ASIC2, or ASIC3 isoforms. We found that store-operated VSM [Ca(2+)](i) responses, Mn(2+) influx, and inward cationic currents were attenuated by either pharmacological ASIC inhibition or treatment with ASIC1 siRNA. These data establish a unique role for ASIC1 in mediating SOCE in pulmonary VSM and provide new insight into mechanisms of VSM Ca(2+) entry and pulmonary vasoregulation.

  8. Evidence for the involvement of ASIC3 in sensory mechanotransduction in proprioceptors

    PubMed Central

    Lin, Shing-Hong; Cheng, Yuan-Ren; Banks, Robert W.; Min, Ming-Yuan; Bewick, Guy S.; Chen, Chih-Cheng

    2016-01-01

    Acid-sensing ion channel 3 (ASIC3) is involved in acid nociception, but its possible role in neurosensory mechanotransduction is disputed. We report here the generation of Asic3-knockout/eGFPf-knockin mice and subsequent characterization of heterogeneous expression of ASIC3 in the dorsal root ganglion (DRG). ASIC3 is expressed in parvalbumin (Pv+) proprioceptor axons innervating muscle spindles. We further generate a floxed allele of Asic3 (Asic3f/f) and probe the role of ASIC3 in mechanotransduction in neurite-bearing Pv+ DRG neurons through localized elastic matrix movements and electrophysiology. Targeted knockout of Asic3 disrupts spindle afferent sensitivity to dynamic stimuli and impairs mechanotransduction in Pv+ DRG neurons because of substrate deformation-induced neurite stretching, but not to direct neurite indentation. In behavioural tasks, global knockout (Asic3−/−) and Pv-Cre::Asic3f/f mice produce similar deficits in grid and balance beam walking tasks. We conclude that, at least in mouse, ASIC3 is a molecular determinant contributing to dynamic mechanosensitivity in proprioceptors. PMID:27161260

  9. Low-noise low-power readout electronics circuit development in standard CMOS technology for 4 K applications

    NASA Astrophysics Data System (ADS)

    Merken, Patrick; Souverijns, Tim; Putzeys, Jan; Creten, Ybe; Van Hoof, Chris

    2006-06-01

    In the framework of the Photodetector Array Camera and Spectrometer (PACS) project IMEC designed the Cold Readout Electronics (CRE) for the Ge:Ga far-infrared detector array. Key specifications for this circuit were high linearity, low power consumption and low noise at an operating temperature of 4.2K. We have implemented this circuit in a standard CMOS technology which guarantees high yield and uniformity, and design portability. A drawback of this approach is the anomalous behavior of CMOS transistors at temperatures below 30-40K. These cryogenic phenomena disturb the normal functionality of commonly used circuits. We were able to overcome these problems and developed a library of digital and analog building blocks based on the modeling of cryogenic behavior, and on adapted design and layout techniques. We will present the design of the 18 channel CRE circuit, its interface with the Ge:Ga sensor, and its electrical performance. We will show how the library that was developed for PACS served as a baseline for the designs used in the Darwin-far-infrared detector array, where a cryogenic 180 channel, 30μm pitch, Readout Integrated Circuit (ROIC) for flip-chip integration was developed. Other designs and topologies for low noise and low power applications will be equally presented.

  10. Fabrication of Ultra-Thin Printed Organic TFT CMOS Logic Circuits Optimized for Low-Voltage Wearable Sensor Applications

    PubMed Central

    Takeda, Yasunori; Hayasaka, Kazuma; Shiwaku, Rei; Yokosawa, Koji; Shiba, Takeo; Mamada, Masashi; Kumaki, Daisuke; Fukuda, Kenjiro; Tokito, Shizuo

    2016-01-01

    Ultrathin electronic circuits that can be manufactured by using conventional printing technologies are key elements necessary to realize wearable health sensors and next-generation flexible electronic devices. Due to their low level of power consumption, complementary (CMOS) circuits using both types of semiconductors can be easily employed in wireless devices. Here, we describe ultrathin CMOS logic circuits, for which not only the source/drain electrodes but also the semiconductor layers were printed. Both p-type and n-type organic thin film transistor devices were employed in a D-flip flop circuit in the newly developed stacked structure and exhibited excellent electrical characteristics, including good carrier mobilities of 0.34 and 0.21 cm2 V−1 sec−1, and threshold voltages of nearly 0 V with low operating voltages. These printed organic CMOS D-flip flop circuits exhibit operating frequencies of 75 Hz and demonstrate great potential for flexible and printed electronics technology, particularly for wearable sensor applications with wireless connectivity. PMID:27157914

  11. Energy and Timing Measurement with Time-Based Detector Readout for PET Applications: Principle and Validation with Discrete Circuit Components

    PubMed Central

    Sun, Xishan; Lan, Allan K.; Bircher, Chad; Deng, Zhi; Liu, Yinong; Shao, Yiping

    2011-01-01

    A new signal processing method for PET application has been developed, with discrete circuit components to measure energy and timing of a gamma interaction based solely on digital timing processing without using an amplitude-to-digital convertor (ADC) or a constant fraction discriminator (CFD). A single channel discrete component time-based readout (TBR) circuit was implemented in a PC board. Initial circuit functionality and performance evaluations have been conducted. Accuracy and linearity of signal amplitude measurement were excellent, as measured with test pulses. The measured timing accuracy from test pulses reached to less than 300 ps, a value limited mainly by the timing jitter of the prototype electronics circuit. Both suitable energy and coincidence timing resolutions (~18% and ~1.0 ns) have been achieved with 3 × 3 × 20 mm3 LYSO scintillator and photomultiplier tube-based detectors. With its relatively simple circuit and low cost, TBR is expected to be a suitable front-end signal readout electronics for compact PET or other radiation detectors requiring the reading of a large number of detector channels and demanding high performance for energy and timing measurement. PMID:21743761

  12. Fabrication of Ultra-Thin Printed Organic TFT CMOS Logic Circuits Optimized for Low-Voltage Wearable Sensor Applications

    NASA Astrophysics Data System (ADS)

    Takeda, Yasunori; Hayasaka, Kazuma; Shiwaku, Rei; Yokosawa, Koji; Shiba, Takeo; Mamada, Masashi; Kumaki, Daisuke; Fukuda, Kenjiro; Tokito, Shizuo

    2016-05-01

    Ultrathin electronic circuits that can be manufactured by using conventional printing technologies are key elements necessary to realize wearable health sensors and next-generation flexible electronic devices. Due to their low level of power consumption, complementary (CMOS) circuits using both types of semiconductors can be easily employed in wireless devices. Here, we describe ultrathin CMOS logic circuits, for which not only the source/drain electrodes but also the semiconductor layers were printed. Both p-type and n-type organic thin film transistor devices were employed in a D-flip flop circuit in the newly developed stacked structure and exhibited excellent electrical characteristics, including good carrier mobilities of 0.34 and 0.21 cm2 V‑1 sec‑1, and threshold voltages of nearly 0 V with low operating voltages. These printed organic CMOS D-flip flop circuits exhibit operating frequencies of 75 Hz and demonstrate great potential for flexible and printed electronics technology, particularly for wearable sensor applications with wireless connectivity.

  13. Energy and Timing Measurement with Time-Based Detector Readout for PET Applications: Principle and Validation with Discrete Circuit Components.

    PubMed

    Sun, Xishan; Lan, Allan K; Bircher, Chad; Deng, Zhi; Liu, Yinong; Shao, Yiping

    2011-06-11

    A new signal processing method for PET application has been developed, with discrete circuit components to measure energy and timing of a gamma interaction based solely on digital timing processing without using an amplitude-to-digital convertor (ADC) or a constant fraction discriminator (CFD). A single channel discrete component time-based readout (TBR) circuit was implemented in a PC board. Initial circuit functionality and performance evaluations have been conducted. Accuracy and linearity of signal amplitude measurement were excellent, as measured with test pulses. The measured timing accuracy from test pulses reached to less than 300 ps, a value limited mainly by the timing jitter of the prototype electronics circuit. Both suitable energy and coincidence timing resolutions (~18% and ~1.0 ns) have been achieved with 3 × 3 × 20 mm(3) LYSO scintillator and photomultiplier tube-based detectors. With its relatively simple circuit and low cost, TBR is expected to be a suitable front-end signal readout electronics for compact PET or other radiation detectors requiring the reading of a large number of detector channels and demanding high performance for energy and timing measurement.

  14. Fabrication of Ultra-Thin Printed Organic TFT CMOS Logic Circuits Optimized for Low-Voltage Wearable Sensor Applications.

    PubMed

    Takeda, Yasunori; Hayasaka, Kazuma; Shiwaku, Rei; Yokosawa, Koji; Shiba, Takeo; Mamada, Masashi; Kumaki, Daisuke; Fukuda, Kenjiro; Tokito, Shizuo

    2016-05-09

    Ultrathin electronic circuits that can be manufactured by using conventional printing technologies are key elements necessary to realize wearable health sensors and next-generation flexible electronic devices. Due to their low level of power consumption, complementary (CMOS) circuits using both types of semiconductors can be easily employed in wireless devices. Here, we describe ultrathin CMOS logic circuits, for which not only the source/drain electrodes but also the semiconductor layers were printed. Both p-type and n-type organic thin film transistor devices were employed in a D-flip flop circuit in the newly developed stacked structure and exhibited excellent electrical characteristics, including good carrier mobilities of 0.34 and 0.21 cm(2) V(-1) sec(-1), and threshold voltages of nearly 0 V with low operating voltages. These printed organic CMOS D-flip flop circuits exhibit operating frequencies of 75 Hz and demonstrate great potential for flexible and printed electronics technology, particularly for wearable sensor applications with wireless connectivity.

  15. Performance of a Low Noise Front-end ASIC for Si/CdTe Detectors in Compton Gamma-ray Telescope

    SciTech Connect

    Tajima, H

    2004-03-29

    Compton telescopes based on semiconductor technologies are being developed to explore the gamma-ray universe in an energy band 0.1-20 MeV, which is not well covered by the present or near-future gamma-ray telescopes. The key feature of such Compton telescopes is the high energy resolution that is crucial for high angular resolution and high background rejection capability. The energy resolution around 1 keV is required to approach physical limit of the angular resolution due to Doppler broadening. We have developed a low noise front-end ASIC (Application-Specific Integrated Circuit), VA32TA, to realize this goal for the readout of Double-sided Silicon Strip Detector (DSSD) and Cadmium Telluride (CdTe) pixel detector which are essential elements of the semiconductor Compton telescope. We report on the design and test results of the VA32TA. We have reached an energy resolution of 1.3 keV (FWHM) for 60 keV and 122 keV at 0 C with a DSSD and 1.7 keV (FWHM) with a CdTe detector.

  16. Three-dimensional stacked structured ASIC devices and methods of fabrication thereof

    DOEpatents

    Shinde, Subhash L.; Teifel, John; Flores, Richard S.; Jarecki Jr., Robert L.; Bauer, Todd

    2015-11-19

    A 3D stacked sASIC is provided that includes a plurality of 2D reconfigurable structured structured ASIC (sASIC) levels interconnected through hard-wired arrays of 3D vias. The 2D sASIC levels may contain logic, memory, analog functions, and device input/output pad circuitry. During fabrication, these 2D sASIC levels are stacked on top of each other and fused together with 3D metal vias. Such 3D vias may be fabricated as through-silicon vias (TSVs). They may connect to the back-side of the 2D sASIC level, or they may be connected to top metal pads on the front-side of the 2D sASIC level.

  17. Mathematical simulation application for research of nonuniform distributed-parameter circuit transients

    NASA Astrophysics Data System (ADS)

    Kuleshova, E. O.; Plyusnin, A. A.; Shandarova, E. B.; Tikhomirova, O. V.

    2016-04-01

    This paper considers the simulation capability of nonuniform distributed-parameter circuit transients by using MatLab Simulink. This approach is capable of determining currents and voltages of nodes for power networks of any configurations and modes. The paper contains results of nonuniform line simulations in idle, short-circuit and load modes.

  18. Wideband phase modulator works directly on carrier. [application of varactor compensated microwave circuit

    NASA Technical Reports Server (NTRS)

    Rippy, R. R.

    1975-01-01

    Multiplier-induced problems related to undesirable effects of the varactor multiplier on the modulation spectrum are eliminated in a modulator circuit which operates directly at the desired output frequency. The principles of operation of the new circuit are discussed and attention is given to requirements for high-Q components and the possibility of linear frequency deviation.

  19. Application of a new arc model for the evaluation of short-circuit breaking tests

    SciTech Connect

    Habedank, U. )

    1993-10-01

    A new arc model is introduced, which describes the behavior of a circuit-breaker using four constant parameters. Comparison of measurement and calculation shows that the description is relatively exact. By means of this model more information about the arc quenching capability of a circuit-breaker can be obtained from switching tests than was possible up to now. Examples are given.

  20. Wideband phase modulator works directly on carrier. [application of varactor compensated microwave circuit

    NASA Technical Reports Server (NTRS)

    Rippy, R. R.

    1975-01-01

    Multiplier-induced problems related to undesirable effects of the varactor multiplier on the modulation spectrum are eliminated in a modulator circuit which operates directly at the desired output frequency. The principles of operation of the new circuit are discussed and attention is given to requirements for high-Q components and the possibility of linear frequency deviation.

  1. Hidden hyperchaos and electronic circuit application in a 5D self-exciting homopolar disc dynamo

    NASA Astrophysics Data System (ADS)

    Wei, Zhouchao; Moroz, Irene; Sprott, J. C.; Akgul, Akif; Zhang, Wei

    2017-03-01

    We report on the finding of hidden hyperchaos in a 5D extension to a known 3D self-exciting homopolar disc dynamo. The hidden hyperchaos is identified through three positive Lyapunov exponents under the condition that the proposed model has just two stable equilibrium states in certain regions of parameter space. The new 5D hyperchaotic self-exciting homopolar disc dynamo has multiple attractors including point attractors, limit cycles, quasi-periodic dynamics, hidden chaos or hyperchaos, as well as coexisting attractors. We use numerical integrations to create the phase plane trajectories, produce bifurcation diagram, and compute Lyapunov exponents to verify the hidden attractors. Because no unstable equilibria exist in two parameter regions, the system has a multistability and six kinds of complex dynamic behaviors. To the best of our knowledge, this feature has not been previously reported in any other high-dimensional system. Moreover, the 5D hyperchaotic system has been simulated using a specially designed electronic circuit and viewed on an oscilloscope, thereby confirming the results of the numerical integrations. Both Matlab and the oscilloscope outputs produce similar phase portraits. Such implementations in real time represent a new type of hidden attractor with important consequences for engineering applications.

  2. Hidden hyperchaos and electronic circuit application in a 5D self-exciting homopolar disc dynamo.

    PubMed

    Wei, Zhouchao; Moroz, Irene; Sprott, J C; Akgul, Akif; Zhang, Wei

    2017-03-01

    We report on the finding of hidden hyperchaos in a 5D extension to a known 3D self-exciting homopolar disc dynamo. The hidden hyperchaos is identified through three positive Lyapunov exponents under the condition that the proposed model has just two stable equilibrium states in certain regions of parameter space. The new 5D hyperchaotic self-exciting homopolar disc dynamo has multiple attractors including point attractors, limit cycles, quasi-periodic dynamics, hidden chaos or hyperchaos, as well as coexisting attractors. We use numerical integrations to create the phase plane trajectories, produce bifurcation diagram, and compute Lyapunov exponents to verify the hidden attractors. Because no unstable equilibria exist in two parameter regions, the system has a multistability and six kinds of complex dynamic behaviors. To the best of our knowledge, this feature has not been previously reported in any other high-dimensional system. Moreover, the 5D hyperchaotic system has been simulated using a specially designed electronic circuit and viewed on an oscilloscope, thereby confirming the results of the numerical integrations. Both Matlab and the oscilloscope outputs produce similar phase portraits. Such implementations in real time represent a new type of hidden attractor with important consequences for engineering applications.

  3. Free space and waveguide Talbot effect: phase relations and planar light circuit applications

    NASA Astrophysics Data System (ADS)

    Nikkhah, H.; Zheng, Q.; Hasan, I.; Abdul-Majid, S.; Hall, T. J.

    2012-10-01

    Optical fields that are periodic in the transverse plane self-image periodically as they propagate along the optical axis: a phenomenon known as the Talbot effect. A transfer matrix may be defined that relates the amplitude and phase of point sources placed on a particular grid at the input to their respective multiple images at an image plane. The free-space Talbot effect may be mapped to the waveguide Talbot effect. Applying this mapping to the transfer matrix enables the prediction of the phase and amplitude relations between the ports of a Multimode Interference (MMI) coupler- a planar waveguide device. The transfer matrix approach has not previously been applied to the free-space case and its mapping to the waveguide case provides greater clarity and physical insight into the phase relationships than previous treatments. The paper first introduces the underlying physics of the Talbot effect in free space with emphasis on the positions along the optical axis at which images occur; their multiplicity; and their relative phase relations determined by the Gauss Quadratic Sum of number theory. The analysis is then adapted to predict the phase relationships between the ports of an MMI. These phase relationships are critical to planar light circuit (PLC) applications such as 90° optical hybrids for coherent optical receiver front-ends, external optical I-Q modulators for coherent optical transmitters; and optical phased array switches. These applications are illustrated by results obtained from devices that have been fabricated and tested by the PTLab in Si micro-photonic integration platforms.

  4. Linear integrated circuits

    NASA Astrophysics Data System (ADS)

    Young, T.

    This book is intended to be used as a textbook in a one-semester course at a variety of levels. Because of self-study features incorporated, it may also be used by practicing electronic engineers as a formal and thorough introduction to the subject. The distinction between linear and digital integrated circuits is discussed, taking into account digital and linear signal characteristics, linear and digital integrated circuit characteristics, the definitions for linear and digital circuits, applications of digital and linear integrated circuits, aspects of fabrication, packaging, and classification and numbering. Operational amplifiers are considered along with linear integrated circuit (LIC) power requirements and power supplies, voltage and current regulators, linear amplifiers, linear integrated circuit oscillators, wave-shaping circuits, active filters, DA and AD converters, demodulators, comparators, instrument amplifiers, current difference amplifiers, analog circuits and devices, and aspects of troubleshooting.

  5. Leu85 in the beta1-beta2 linker of ASIC1 slows activation and decreases the apparent proton affinity by stabilizing a closed conformation.

    PubMed

    Li, Tianbo; Yang, Youshan; Canessa, Cecilia M

    2010-07-16

    Acid-sensing ion channels (ASICs) are proton-activated channels expressed in neurons of the central and peripheral nervous systems where they modulate neuronal activity in response to external increases in proton concentration. The size of ASIC1 currents evoked by a given local acidification is determined by the number of channels in the plasma membrane and by the apparent proton affinities for activation and steady-state desensitization of the channel. Thus, the magnitude of the pH drop and the value of the baseline pH both are functionally important. Recent characterization of ASIC1s from an increasing number of species has made evident that proton affinities of these channels vary across vertebrates. We found that in species with high baseline plasma pH, e.g. frog, shark, and fish, ASIC1 has high proton affinity compared with the mammalian channel. The beta1-beta2 linker in the extracellular domain, specifically by the substitution M85L, determines the interspecies differences in proton affinities and also the time course of ASIC1 macroscopic currents. The mechanism underlying these observations is a delay in channel opening after application of protons, most likely by stabilizing a closed conformation that decreases the apparent affinity to protons and also slows the rise and decay phases of the current. Together, the results suggest evolutionary adaptation of ASIC1 to match the value of the species-specific plasma pH. At the molecular level, adaptation is achieved by substitutions of nonionizable residues rather than by modification of the channel proton sensor.

  6. Application of circuit simulation method for differential modeling of TIM-2 iron uptake and metabolism in mouse kidney cells.

    PubMed

    Xie, Zhijian; Harrison, Scott H; Torti, Suzy V; Torti, Frank M; Han, Jian

    2013-01-01

    Circuit simulation is a powerful methodology to generate differential mathematical models. Due to its highly accurate modeling capability, circuit simulation can be used to investigate interactions between the parts and processes of a cellular system. Circuit simulation has become a core technology for the field of electrical engineering, but its application in biology has not yet been fully realized. As a case study for evaluating the more advanced features of a circuit simulation tool called Advanced Design System (ADS), we collected and modeled laboratory data for iron metabolism in mouse kidney cells for a H ferritin (HFt) receptor, T cell immunoglobulin and mucin domain-2 (TIM-2). The internal controlling parameters of TIM-2 associated iron metabolism were extracted and the ratios of iron movement among cellular compartments were quantified by ADS. The differential model processed by circuit simulation demonstrated a capability to identify variables and predict outcomes that could not be readily measured by in vitro experiments. For example, an initial rate of uptake of iron-loaded HFt (Fe-HFt) was 2.17 pmol per million cells. TIM-2 binding probability with Fe-HFt was 16.6%. An average of 8.5 min was required for the complex of TIM-2 and Fe-HFt to form an endosome. The endosome containing HFt lasted roughly 2 h. At the end of endocytosis, about 28% HFt remained intact and the rest was degraded. Iron released from degraded HFt was in the labile iron pool (LIP) and stimulated the generation of endogenous HFt for new storage. Both experimental data and the model showed that TIM-2 was not involved in the process of iron export. The extracted internal controlling parameters successfully captured the complexity of TIM-2 pathway and the use of circuit simulation-based modeling across a wider range of cellular systems is the next step for validating the significance and utility of this method.

  7. Numerical Simulation Bidirectional Chaotic Synchronization of Spiegel-Moore Circuit and Its Application for Secure Communication

    NASA Astrophysics Data System (ADS)

    Sanjaya, W. S. M.; Anggraeni, D.; Denya, R.; Ismail, N.

    2017-03-01

    Spiegel-Moore is a dynamical chaotic system which shows irregular variability in the luminosity of stars. In this paper present the performed the design and numerical simulation of the synchronization Spiegel-Moore circuit and applied to security system for communication. The initial study in this paper is to analyze the eigenvalue structures, various attractors, Bifurcation diagram, and Lyapunov exponent analysis. We have studied the dynamic behavior of the system in the case of the bidirectional coupling via a linear resistor. Both experimental and simulation results have shown that chaotic synchronization is possible. Finally, the effectiveness of the bidirectional coupling scheme between two identical Spiegel-Moore circuits in a secure communication system is presented in details. Integration of theoretical electronic circuit, the numerical simulation by using MATLAB®, as well as the implementation of circuit simulations by using Multisim® has been performed in this study.

  8. PMGA and its application in area and power optimization for ternary FPRM circuit

    NASA Astrophysics Data System (ADS)

    Pengjun, Wang; Kangping, Li; Huihong, Zhang

    2016-01-01

    Based on the research of population migration algorithms (PMAs), a population migration genetic algorithm (PMGA) is proposed, combining a PMA with a genetic algorithm. A scheme of area and power optimization for a ternary FPRM circuit is proposed by using the PMGA. Firstly, according to the ternary FPRM logic function expression, area and power estimation models are established. Secondly, the PMGA is used to search for the best area and power polarity. Finally, 10 MCNC Benchmark circuits are used to verify the effectiveness of the proposed method. The results show that the ternary FPRM circuits optimized by the PMGA saved 13.33% area and 20.00% power on average than the corresponding FPRM circuits optimized by a whole annealing genetic algorithm. Project supported by the Natural Science Foundation of Zhejiang Province (No. LY13F040003), the National Natural Science Foundation of China (Nos. 61234002, 61306041), and the K. C. Wong Magna Fund in Ningbo University.

  9. Development of closed-loop interface circuits for capacitive transducers with application to a MEMS capacitive microphone

    NASA Astrophysics Data System (ADS)

    Kadirvel, Karthik

    There has been a trend towards miniaturization and batch fabrication of sensors inspired by a similar trend in the electronics industry using novel fabrication techniques used in micro electromechanical system (MEMS) fabrication. Capacitive microphones, whose common applications include aeroacoustic measurement and cell phones, is one such sensor whose dimensions are being aggressively scaled down. In measurement microphones, miniaturization will facilitate improved measurement precision, and in cell phones, miniaturization will reduce printer circuit board space and complexity. Both applications will benefit from the potential cost reduction brought by the batch fabrication of sensors. As sensor geometry is scaled down, improved circuit techniques are required to measure the sensor output. This is because at small geometries sensor capacitance is comparable to unwanted parasitic capacitance which reduces the transducer sensitivity. Also, at reduced sensor geometry, the voltage required to bias the microphone could cause the microphone plates to pull in. The goal of this work is to design and characterize interface circuits that are suitable for miniature capacitive transducers. To achieve this goal, the performance of existing open and closed-loop interface circuits are investigated. Scaling of the performance metrics of the microphone and interface circuit as sensor geometry decreases is also investigated. A proof of concept closed-loop analog controller for a MEMS capacitive microphone is designed. A test apparatus is developed to characterize the system over the audio range by operating the microphone in a helium medium which increases the bandwidth of the test apparatus. Characterization of the microphone in open and closed loop mode of operation is presented. Results show that stable closed loop operation of the microphone is feasible with increased sensitivity and the potential to address pull-in issues.

  10. Double-differential recording and AGC using microcontrolled variable gain ASIC.

    PubMed

    Rieger, Robert; Deng, Shin-Liang

    2013-01-01

    Low-power wearable recording of biopotentials requires acquisition front-ends with high common-mode rejection for interference suppression and adjustable gain to provide an optimum signal range to a cascading analogue-to-digital stage. A microcontroller operated double-differential (DD) recording setup and automatic gain control circuit (AGC) are discussed which reject common-mode interference and provide tunable gain, thus compensating for imbalance and variation in electrode interface impedance. Custom-designed variable gain amplifiers (ASIC) are used as part of the recording setup. The circuit gain and balance is set by the timing of microcontroller generated clock signals. Measured results are presented which confirm that improved common-mode rejection is achieved compared to a single differential amplifier in the presence of input network imbalance. Practical measured examples further validate gain control suitable for biopotential recording and power-line rejection for wearable ECG and EMG recording. The prototype front-end consumes 318 μW including amplifiers and microcontroller.

  11. Design Implementation and Testing of a VLSI High Performance ASIC for Extracting the Phase of a Complex Signal

    NASA Astrophysics Data System (ADS)

    Altmeyer, Ronald C.

    2002-09-01

    This thesis documents the research, circuit design, and simulation testing of a VLSI (Very Large Scale Integration) ASIC which extracts phase angle information from a complex sampled signal using the arctangent relationship: (phi=tan/-1 (Q/1). Specifically, the circuit will convert the In-Phase and Quadrature terms into their corresponding phase angle. The design specifications were to implement the design in CMOS (Complementary Metal Oxide Semiconductors) technology with a minimum transistor count and ability to operate at a clock frequency of 700 MHz. Research on the arctangent function was performed to determine mathematical calculation methods and the CORDIC method was chosen to achieve the stated design specifications. MATLAB simulations were used to calculate and verify accuracy and to implement Quine-McClusky logic minimization. T-SPICE netlists were generated and simulations were run to determine transistor and circuit electrical operation and timing. Finally, overall circuit logic functionality of all possible input combinations was completed using a VHDL (VHSIC(Very High Speed Integrated Circuit) Hardware Description Language) simulation program.

  12. QIE10: a new front-end custom integrated circuit for high-rate experiments

    NASA Astrophysics Data System (ADS)

    Baumbaugh, A.; Dal Monte, L.; Drake, G.; Freeman, J.; Hare, D.; Hernandez Rojas, H.; Hughes, E.; Los, S.; Mendez Mendez, D.; Proudfoot, J.; Shaw, T.; Tully, C.; Vidal, R.; Whitmore, J.; Zimmerman, T.

    2014-01-01

    We present results on a new version of the QIE (Charge Integrator and Encoder), a custom Application Specific Integrated Circuit (ASIC) designed at Fermilab. Developed specifically for the measurement of charge from photo-detectors in high-rate environments, this most recent addition to the QIE family features 3 fC sensitivity, 17-bits of dynamic range with logarithmic response, a Time-to-Digital Converter (TDC) with sub-nanosecond resolution, and internal charge injection. The device is capable of dead-timeless operation at 40 MHz, making it ideal for calorimetry at the Large hadron Collider (LHC). We present bench measurements and integration studies that characterize the performance, radiation tolerance measurements, and plans for deployment in the Atlas and CMS detectors as part of the Phase 1 and Phase 2 upgrades.

  13. Novel Asymmetric Tunnel Source Transistors for Energy Efficient Circuits and Mixed Signal Applications

    NASA Astrophysics Data System (ADS)

    Jhaveri, Ritesh Atul

    Over the history of integrated circuits, a gargantuan increase in speed and performance has been achieved due to the trend of scaling. In recent years, however, many daunting challenges arise as we scale into sub-32nm regime. The building block of the MOSFET device, Silicon, is being pushed to its performance limitation. New materials and design methodologies are being investigated to extract better performance. In this study, we concentrate on two flavors of Novel Source Tunneling Transistors: the Schottky Tunnel Source FET and the Source Pocket band-to-band tunneling FET. Schottky barrier FETs have recently attracted attention as a viable alternative to conventional CMOS transistors for sub-32nm technology nodes. In this study, an asymmetric Schottky Tunnel Source SOI FET (STS-FET) has been proposed. The STS-FET has the source/drain regions replaced with metal/silicide as opposed to highly doped silicon in conventional devices. The main feature of this device is the injection of carriers through gate controlled Schottky barrier tunneling at the source. The optimized device structure shows improved performance as compared to conventional Schottky FETs. The analog performance of the STS-FET was studied and the device was found to be a superior alternative to conventional CMOS transistors. Various process modules were designed and developed. The STS-FET was then fabricated with NiSi technology and successfully demonstrated for 0.11mum gate lengths. The high immunity to short channel effects and the excellent analog performance of the device makes it an attractive candidate for continued scaling into sub 32nm node as well as mixed signal applications. Energy Efficiency is also an important concern for sub-32nm CMOS integrated circuits. Scaling of devices to below 32nm leads to an increase in active power dissipation (CVDD2.f) and off-state power (IOFF·VDD). Hence, new device innovations are being explored to address these problems. In this study, a novel source

  14. PACIFIC: A 64-channel ASIC for scintillating fiber tracking in LHCb upgrade

    NASA Astrophysics Data System (ADS)

    Gascon, D.; Chanal, H.; Comerma, A.; Gomez, S.; Han, X.; Mazorra, J.; Mauricio, J.; Pillet, N.; Yengui, F.; Vandaele, R.

    2015-04-01

    The LHCb detector will be upgraded during the next LHC shutdown in 2018/19 [1]. The tracker system will have a major overhaul. Its components will be replaced with new technologies in order to cope with the increased hit occupancy and radiation environment. Here we describe a detector made of scintillating fibers read out by silicon photomultipliers (SiPM), with a view to its application for this upgrade. This technology has been shown to achieve high efficiency and spatial resolution, but its integration within a LHCb experiment presents new challenges. This article gives an overview of the R&D status of the low-Power ASIC for the sCIntillating FIbres traCker (PACIFIC) chip implemented in a 130 nm CMOS technology. The PACIFIC chip is a 64-channel ASIC which can be connected to a SiPM without the need of any external component. It includes analog signal processing and digitization. The first stage is a current conveyor followed by a tunable fast shaper (≈10 ns) and a gated integrator. The digitization is performed using a 3 threshold non-linear flash ADC operating at 40 MHz. The PACIFIC chip has the ability to cope with different SiPM suppliers with a power consumption below 8 mW per channel and it is radiation-tolerant. Lastly, simulation and test results show the proper read out of the SiPMs with the PACIFIC chip.

  15. Development of the read-out ASIC for muon chambers

    NASA Astrophysics Data System (ADS)

    Atkin, E.; Bulbakov, I.; Gusev, A.; Malankin, E.; Normanov, D.; Sagdiev, I.; Shumikhin, V.; Shumkin, O.; Ivanov, P.; Vinogradov, S.; Voronin, A.; Samsonov, V.; Ivanov, V.

    2016-02-01

    A front-end prototype ASIC for muon chambers is presented. ASIC was designed and prototyped in the CMOS UMC MMRF 180 nm process via Europractice. The chip includes 8 analog processing channels, each consisting of a preamplifier, two shapers (fast and slow), differential comparator and an area efficient 6 bit SAR ADC with 1.2 mW power consumption at 50 Msps. The chip also includes the threshold DAC and digital serializer. The design has the following features: dynamic range of 100 fC, channel hit rate of 2 MHz, ENC of 1000 e- at 50 pF, power consumption of 10 mW per channel, 6 bit SAR ADC.

  16. ASIC1A in the bed nucleus of the stria terminalis mediates TMT-evoked freezing

    PubMed Central

    Taugher, Rebecca J.; Ghobbeh, Ali; Sowers, Levi P.; Fan, Rong; Wemmie, John A.

    2015-01-01

    Mice display an unconditioned freezing response to TMT, a predator odor isolated from fox feces. Here we found that in addition to freezing, TMT caused mice to decrease breathing rate, perhaps because of the aversive smell. Consistent with this possibility, olfactory bulb lesions attenuated this effect of TMT, as well as freezing. Interestingly, butyric acid, another foul odor, also caused mice to reduce breathing rate. However, unlike TMT, butyric acid did not induce freezing. Thus, although these aversive odors may affect breathing, the unpleasant smell and suppression of breathing by themselves are insufficient to cause freezing. Because the acid-sensing ion channel-1A (ASIC1A) has been previously implicated in TMT-evoked freezing, we tested whether Asic1a disruption also altered breathing. We found that TMT reduced breathing rate in both Asic1a+/+ and Asic1a−/− mice, suggesting that ASIC1A is not required for TMT to inhibit breathing and that the absence of TMT-evoked freezing in the Asic1a−/− mice is not due to an inability to detect TMT. These observations further indicate that ASIC1A must affect TMT freezing in another way. Because the bed nucleus of the stria terminalis (BNST) has been critically implicated in TMT-evoked freezing and robustly expresses ASIC1A, we tested whether ASIC1A in the BNST plays a role in TMT-evoked freezing. We disrupted ASIC1A in the BNST of Asic1aloxP/loxP mice by delivering Cre recombinase to the BNST with an adeno-associated virus (AAV) vector. We found that disrupting ASIC1A in the BNST reduced TMT-evoked freezing relative to control mice in which a virus expressing eGFP was injected. To test whether ASIC1A in the BNST was sufficient to increase TMT-evoked freezing, we used another AAV vector to express ASIC1A in the BNST of Asic1a−/− mice. We found region-restricted expression of ASIC1A in the BNST increased TMT-elicited freezing. Together, these data suggest that the BNST is a key site of ASIC1A action in TMT

  17. Test bench development for the radiation Hard GBTX ASIC

    NASA Astrophysics Data System (ADS)

    Leitao, P.; Feger, S.; Porret, D.; Baron, S.; Wyllie, K.; Barros Marin, M.; Figueiredo, D.; Francisco, R.; Da Silva, J. C.; Grassi, T.; Moreira, P.

    2015-01-01

    This paper presents the development of the GBTX radiation hard ASIC test bench. Developed for the LHC accelerator upgrade programs, the GBTX implements a bidirectional 4.8 Gb/s link between the radiation hard on-detector custom electronics and the off-detector systems. The test bench was used for functional testing of the GBTX and to evaluate its performance in a radiation environment, by conducting Total Ionizing Dose and Single-Event Upsets tests campaigns.

  18. Course-Grain Reconfigurable ASIC through Multiplexer Based Switches

    DTIC Science & Technology

    2015-09-15

    processors that have ASIC-like performance and FPGA -like flexibility. Figure 2: Embedded processing system design space based on data points collected...reconfigurable structures like FPGA . Figure 2 summarizes the performance and flexibility of three embedded processing techniques: FPGAs , GPPs and...physical system ). Switches were tested by programming them at the full speed for which they were designed in this proof of concept, 50 MHz, and up to

  19. Acid-sensing ion channels (ASICs) 2 and 4.2 are expressed in the retina of the adult zebrafish.

    PubMed

    Viña, E; Parisi, V; Sánchez-Ramos, C; Cabo, R; Guerrera, M C; Quirós, L M; Germanà, A; Vega, J A; García-Suárez, O

    2015-05-01

    Acid-sensing ion channels (ASICs) are H(+)-gated, voltage-insensitive cation channels involved in synaptic transmission, mechanosensation and nociception. Different ASICs have been detected in the retina of mammals but it is not known whether they are expressed in adult zebrafish, a commonly used animal model to study the retina in both normal and pathological conditions. We study the expression and distribution of ASIC2 and ASIC4 in the retina of adult zebrafish and its regulation by light using PCR, in situ hybridization, western blot and immunohistochemistry. We detected mRNA encoding zASIC2 and zASIC4.2 but not zASIC4.1. ASIC2, at the mRNA or protein level, was detected in the outer nuclear layer, the outer plexiform layer, the inner plexiform layer, the retinal ganglion cell layer and the optic nerve. ASIC4 was expressed in the photoreceptors layer and to a lesser extent in the retinal ganglion cell layer. Furthermore, the expression of both ASIC2 and ASIC4.2 was down-regulated by light and darkness. These results are the first demonstration that ASIC2 and ASIC4 are expressed in the adult zebrafish retina and suggest that zebrafish could be used as a model organism for studying retinal pathologies involving ASICs.

  20. JPIC-Rad-Hard JPEG2000 Image Compression ASIC

    NASA Astrophysics Data System (ADS)

    Zervas, Nikos; Ginosar, Ran; Broyde, Amitai; Alon, Dov

    2010-08-01

    JPIC is a rad-hard high-performance image compression ASIC for the aerospace market. JPIC implements tier 1 of the ISO/IEC 15444-1 JPEG2000 (a.k.a. J2K) image compression standard [1] as well as the post compression rate-distortion algorithm, which is part of tier 2 coding. A modular architecture enables employing a single JPIC or multiple coordinated JPIC units. JPIC is designed to support wide data sources of imager in optical, panchromatic and multi-spectral space and airborne sensors. JPIC has been developed as a collaboration of Alma Technologies S.A. (Greece), MBT/IAI Ltd (Israel) and Ramon Chips Ltd (Israel). MBT IAI defined the system architecture requirements and interfaces, The JPEG2K-E IP core from Alma implements the compression algorithm [2]. Ramon Chips adds SERDES interfaces and host interfaces and integrates the ASIC. MBT has demonstrated the full chip on an FPGA board and created system boards employing multiple JPIC units. The ASIC implementation, based on Ramon Chips' 180nm CMOS RadSafe[TM] RH cell library enables superior radiation hardness.

  1. Space qualification and performance results of the SIDECAR ASIC

    NASA Astrophysics Data System (ADS)

    Loose, Markus; Beletic, James; Garnett, James; Muradian, Norair

    2006-06-01

    The SIDECAR ASIC is a fully integrated FPA controller system-on-a-chip. Compared to conventional control electronics, it requires significantly less power, less space and less weight. The SIDECAR ASIC, which can operate at ambient and cryogenic temperatures, is currently being space-qualified for integration in the science instruments of the James Webb Space Telescope (JWST). This paper gives an overview of the SIDECAR architecture and its supporting drive electronics. It describes the JWST flight configuration including the custom packaging approach. Test results obtained as part of the space qualification effort are presented. CDS noise of the ASIC itself amounts to less than 25 μV for full 2K x 2K data frames. The noise reduces to less than 6 μV for up-the-ramp-sampling with 88 frames. Based on the existing qualification results and a number of additional tests in the next few months, NASA Technology Readiness Level 6 (TRL6) will be demonstrated by August 2006.

  2. The Ion Channel ASIC2 is Required for Baroreceptor and Autonomic Control of the Circulation

    PubMed Central

    Lu, Yongjun; Ma, Xiuying; Sabharwal, Rasna; Snitsarev, Vladislav; Morgan, Donald; Rahmouni, Kamal; Drummond, Heather A.; Whiteis, Carol A.; Costa, Vivian; Price, Margaret; Benson, Christopher; Welsh, Michael J.; Chapleau, Mark W.; Abboud, François M.

    2009-01-01

    SUMMARY Arterial baroreceptors provide a neural sensory input that reflexly regulates the autonomic drive of the circulation. Our goal was to test the hypothesis that a member of the acid sensing ion channel (ASIC) subfamily of the DEG/ENaC superfamily is an important determinant of the arterial baroreceptor reflex. We found that aortic baroreceptor neurons in the nodose ganglia and their terminals express ASIC2. Conscious ASIC2 null mice developed hypertension, had exaggerated sympathetic and depressed parasympathetic control of the circulation, and a decreased gain of the baroreflex, all indicative of an impaired baroreceptor reflex. Multiple measures of baroreceptor activity each suggests that mechanosensitivity is diminished in ASIC2- null mice. The results define ASIC2 as an important determinant of autonomic circulatory control and of baroreceptor sensitivity. The genetic disruption of ASIC2 recapitulates the pathological dysautonomia seen in heart failure and hypertension and defines a molecular defect that may be relevant to its development. PMID:20064394

  3. Measuring user similarity using electric circuit analysis: application to collaborative filtering.

    PubMed

    Yang, Joonhyuk; Kim, Jinwook; Kim, Wonjoon; Kim, Young Hwan

    2012-01-01

    We propose a new technique of measuring user similarity in collaborative filtering using electric circuit analysis. Electric circuit analysis is used to measure the potential differences between nodes on an electric circuit. In this paper, by applying this method to transaction networks comprising users and items, i.e., user-item matrix, and by using the full information about the relationship structure of users in the perspective of item adoption, we overcome the limitations of one-to-one similarity calculation approach, such as the Pearson correlation, Tanimoto coefficient, and Hamming distance, in collaborative filtering. We found that electric circuit analysis can be successfully incorporated into recommender systems and has the potential to significantly enhance predictability, especially when combined with user-based collaborative filtering. We also propose four types of hybrid algorithms that combine the Pearson correlation method and electric circuit analysis. One of the algorithms exceeds the performance of the traditional collaborative filtering by 37.5% at most. This work opens new opportunities for interdisciplinary research between physics and computer science and the development of new recommendation systems.

  4. Measuring User Similarity Using Electric Circuit Analysis: Application to Collaborative Filtering

    PubMed Central

    Yang, Joonhyuk; Kim, Jinwook; Kim, Wonjoon; Kim, Young Hwan

    2012-01-01

    We propose a new technique of measuring user similarity in collaborative filtering using electric circuit analysis. Electric circuit analysis is used to measure the potential differences between nodes on an electric circuit. In this paper, by applying this method to transaction networks comprising users and items, i.e., user–item matrix, and by using the full information about the relationship structure of users in the perspective of item adoption, we overcome the limitations of one-to-one similarity calculation approach, such as the Pearson correlation, Tanimoto coefficient, and Hamming distance, in collaborative filtering. We found that electric circuit analysis can be successfully incorporated into recommender systems and has the potential to significantly enhance predictability, especially when combined with user-based collaborative filtering. We also propose four types of hybrid algorithms that combine the Pearson correlation method and electric circuit analysis. One of the algorithms exceeds the performance of the traditional collaborative filtering by 37.5% at most. This work opens new opportunities for interdisciplinary research between physics and computer science and the development of new recommendation systems PMID:23145095

  5. Measuring circuit

    DOEpatents

    Sun, Shan C.; Chaprnka, Anthony G.

    1977-01-11

    An automatic gain control circuit functions to adjust the magnitude of an input signal supplied to a measuring circuit to a level within the dynamic range of the measuring circuit while a log-ratio circuit adjusts the magnitude of the output signal from the measuring circuit to the level of the input signal and optimizes the signal-to-noise ratio performance of the measuring circuit.

  6. Arrayed Waveguide Gratings and Their Application Using Super-High-Δ Silica-Based Planar Lightwave Circuit Technology

    NASA Astrophysics Data System (ADS)

    Maru, Koichi; Uetsuka, Hisato

    This paper reviews our recent progress on arrayed waveguide gratings (AWGs) using super-high-Δ silica-based planar lightwave circuit (PLC) technology and their application to integrated optical devices. Factors affecting the chip size of AWGs and the impact of increasing relative index difference Δ on the chip size are investigated, and the fabrication result of a compact athermal AWG using 2.5%-Δ silica-based waveguides is presented. As an application of super-high-Δ AWGs to integrated devices, a flat-passband multi/demultiplexer consisting of an AWG and cascaded MZIs is presented.

  7. Module failure isolation circuit for paralleled inverters. [preventing system failure during power conditioning for spacecraft applications

    NASA Technical Reports Server (NTRS)

    Nagano, S. (Inventor)

    1979-01-01

    A module failure isolation circuit is described which senses and averages the collector current of each paralled inverter power transistor and compares the collector current of each power transistor the average collector current of all power transistors to determine when the sensed collector current of a power transistor in any one inverter falls below a predetermined ratio of the average collector current. The module associated with any transistor that fails to maintain a current level above the predetermined radio of the average collector current is then shut off. A separate circuit detects when there is no load, or a light load, to inhibit operation of the isolation circuit during no load or light load conditions.

  8. Analysis of the possibility of a PGA309 integrated circuit application in pressure sensors

    NASA Astrophysics Data System (ADS)

    Walendziuk, Wojciech; Baczewski, Michal; Idzkowski, Adam

    2016-09-01

    This article present the results of research concerning the analysis of the possibilities of applying a PGA309 integrated circuit in transducers used for pressure measurement. The experiments were done with the use of a PGA309EVM-USB evaluation circuit with a BD|SENSORS pressure sensor. A specially prepared MATLAB script was used in the process of the calibration setting choice and the results analysis. The article discusses the worked out algorithm that processes the measurement results, i.e. the algorithm which calculates the desired gain and the offset adjustment voltage of the transducer measurement bridge in relation to the input signal range of the integrated circuit and the temperature of the environment (temperature compensation). The checking procedure was conducted in a measurement laboratory and the obtained result were analyzed and discussed.

  9. Application of Error Correcting Codes in Fault-Tolerant Logic Design for VLSI Circuits

    DTIC Science & Technology

    1992-08-14

    Difference between par Erroneous bit( s ) expected and actual (do) (unidirectional) residue(dr) 8(5) 0 d7d6 10 (3) 0 d5d4 3( 10 ) 0 d4d3 4(9) 0 d2dl 9(4) 0...indicating the presence of the s -on transistor. Since C for any fault, the circuit never produces an incorrect code word i.e. 10 instead of 01 or vice...way that P2 82 P for any defect (break or s -on) in the circuit the outputs 1 P4 -- will assume a value of 01 or 10 . For a fault-free circuit the

  10. Analysis and application of two-current-source circuit as a signal conditioner for resistive sensors

    NASA Astrophysics Data System (ADS)

    Idzkowski, Adam; Gołębiowski, Jerzy; Walendziuk, Wojciech

    2017-05-01

    The article presents the analysis of metrological properties of a two-current-source supplied circuit. It includes such data as precise and simplified equations for two circuit output voltages in the function of relative resistance increments of sensors. Moreover, graphs showing nonlinearity coefficients of both output voltages for two resistance increments varying widely are presented. Graphs of transfer resistances, depending on relative increments of sensors resistance were also created. The article also contains a description of bridge-based circuit realization with the use of a computer and a data acquisition (DAQ) card. Laboratory measurement of the difference and sum of relative resistance increments of two resistance decade boxes were carried out indirectly with the use of the created measurement system. Measurement errors were calculated and included in the article, as well.

  11. Peltier effect exchanges in contact thermocouples - Application to the characterization of new thermoelectric circuits

    NASA Astrophysics Data System (ADS)

    Berrached, N.-E.

    Results from an investigation of coupling in thermoelectric circuits manufactured by electrodeposition of a metallic conductor on a conducting foil made of a different material are presented. The study was undertaken to define the significant factors in the design and manufacture of thermal fluxmeters. Theoretical considerations indicate that the voltage appearing between output connections is proportional to the average spatial thermal gradient on the sensitive surface of the thermoelement. A figure of merit is defined for the coupling of the contact thermocouples. Localized thermal exchanges of opposite sign are shown to occur due to the passage of current, and are concentrated at the boundaries of each thermoelement. Nonisothermal tangential thermal gradients appear on the surface of the circuit. Experimental studies confirm the appearance of the gradients by their IR signatures. Finally, the gradients are determined to be affected by the thickness and conductivity of the medium placed between the emitter and detector circuits.

  12. Photonic Integrated Circuit (PIC) Device Structures: Background, Fabrication Ecosystem, Relevance to Space Systems Applications, and Discussion of Related Radiation Effects

    NASA Technical Reports Server (NTRS)

    Alt, Shannon

    2016-01-01

    Electronic integrated circuits are considered one of the most significant technological advances of the 20th century, with demonstrated impact in their ability to incorporate successively higher numbers transistors and construct electronic devices onto a single CMOS chip. Photonic integrated circuits (PICs) exist as the optical analog to integrated circuits; however, in place of transistors, PICs consist of numerous scaled optical components, including such "building-block" structures as waveguides, MMIs, lasers, and optical ring resonators. The ability to construct electronic and photonic components on a single microsystems platform offers transformative potential for the development of technologies in fields including communications, biomedical device development, autonomous navigation, and chemical and atmospheric sensing. Developing on-chip systems that provide new avenues for integration and replacement of bulk optical and electro-optic components also reduces size, weight, power and cost (SWaP-C) limitations, which are important in the selection of instrumentation for specific flight projects. The number of applications currently emerging for complex photonics systems-particularly in data communications-warrants additional investigations when considering reliability for space systems development. This Body of Knowledge document seeks to provide an overview of existing integrated photonics architectures; the current state of design, development, and fabrication ecosystems in the United States and Europe; and potential space applications, with emphasis given to associated radiation effects and reliability.

  13. The application of standardized control and interface circuits to three dc to dc power converters.

    NASA Technical Reports Server (NTRS)

    Yu, Y.; Biess, J. J.; Schoenfeld, A. D.; Lalli, V. R.

    1973-01-01

    Standardized control and interface circuits were applied to the three most commonly used dc to dc converters: the buck-boost converter, the series-switching buck regulator, and the pulse-modulated parallel inverter. The two-loop ASDTIC regulation control concept was implemented by using a common analog control signal processor and a novel digital control signal processor. This resulted in control circuit standardization and superior static and dynamic performance of the three dc-to-dc converters. Power components stress control, through active peak current limiting and recovery of switching losses, was applied to enhance reliability and converter efficiency.

  14. Optical FFT/IFFT circuit realization using arrayed waveguide gratings and the applications in all-optical OFDM system.

    PubMed

    Wang, Zhenxing; Kravtsov, Konstantin S; Huang, Yue-Kai; Prucnal, Paul R

    2011-02-28

    Arrayed waveguide gratings (AWG) are widely used as wavelength division multiplexers (MUX) and demultiplexers (DEMUX) in optical networks. Here we propose and demonstrate that conventional AWGs can also be used as integrated spectral filters to realize a Fast Fourier transform (FFT) and its inverse form (IFFT). More specifically, we point out that the wavelength selection conditions of AWGs when used as wavelength MUX/DEMUX also enable them to perform FFT/IFFT functions. Therefore, previous research on AWGs can now be applied to optical FFT/IFFT circuit design. Compared with other FFT/IFFT optical circuits, AWGs have less structural complexity, especially for a large number of inputs and outputs. As an important application, AWGs can be used in optical OFDM systems. We propose an all-optical OFDM system with AWGs and demonstrate the simulation results. Overall, the AWG provides a feasible solution for all-optical OFDM systems, especially with a large number of optical subcarriers.

  15. SEMICONDUCTOR INTEGRATED CIRCUITS: A high-performance, low-power σ Δ ADC for digital audio applications

    NASA Astrophysics Data System (ADS)

    Hao, Luo; Yan, Han; Cheung, Ray C. C.; Xiaoxia, Han; Shaoyu, Ma; Peng, Ying; Dazhong, Zhu

    2010-05-01

    A high-performance low-power σ Δ analog-to-digital converter (ADC) for digital audio applications is described. It consists of a 2-1 cascaded σ Δ modulator and a decimation filter. Various design optimizations are implemented in the system design, circuit implementation and layout design, including a high-overload-level coefficient-optimized modulator architecture, a power-efficient class A/AB operational transconductance amplifier, as well as a multi-stage decimation filter conserving area and power consumption. The ADC is implemented in the SMIC 0.18-μm CMOS mixed-signal process. The experimental chip achieves a peak signal-to-noise-plus-distortion ratio of 90 dB and a dynamic range of 94 dB over 22.05-kHz audio band and occupies 2.1 mm2, which dissipates only 2.1 mA quiescent current in the analog circuits.

  16. Acid-sensing ion channel 2 (asic 2) and trkb interrelationships within the intervertebral disc

    PubMed Central

    Cuesta, Antonio; Viña, Eliseo; Cabo, Roberto; Vázquez, Gorka; Cobo, Ramón; García-Suárez, Olivia; García-Cosamalón, José; Vega, José A

    2015-01-01

    The cells of the intervertebral disc (IVD) have an unusual acidic and hyperosmotic microenvironment. They express acid-sensing ion channels (ASICs), gated by extracellular protons and mechanical forces, as well as neurotrophins and their signalling receptors. In the nervous tissues some neurotrophins regulate the expression of ASICs. The expression of ASIC2 and TrkB in human normal and degenerated IVD was assessed using quantitative-PCR, Western blot, and immunohistochemistry. Moreover, we investigated immunohistochemically the expression of ASIC2 in the IVD of TrkB-deficient mice. ASIC2 and TrkB mRNAs were found in normal human IVD and both increased significantly in degenerated IVD. ASIC2 and TrkB proteins were also found co-localized in a variable percentage of cells, being significantly higher in degenerated IVD than in controls. The murine IVD displayed ASIC2 immunoreactivity which was absent in the IVD of TrkB-deficient mice. Present results demonstrate the occurrence of ASIC2 and TrkB in the human IVD, and the increased expression of both in pathological IVD suggest their involvement in IVD degeneration. These data also suggest that TrkB-ligands might be involved in the regulation of ASIC2 expression, and therefore in mechanisms by which the IVD cells accommodate to low pH and hypertonicity. PMID:26617738

  17. Applications of laser-generated surface acoustic waves for copper film process monitoring in integrated circuit industry (abstract)

    NASA Astrophysics Data System (ADS)

    Gostein, Michael; Maznev, A. A.; Krastev, Plamen; Mazurenko, Alex

    2003-01-01

    We describe applications of a compact commercial instrument for laser generation and detection of surface acoustic waves (SAWs) to problems in metal film process control for the integrated circuit (IC) industry. [M. Gostein, M. Banet, M. Joffe, A. A. Maznev, R. Sacco, J. A. Rogers, and K. A. Nelson, in Handbook of Silicon Semiconductor Metrology, edited by A. C. Diebold (Marcel Dekker, New York, 2001)] The IC industry is undergoing dramatic changes with the continued drive to reduce feature size and increase circuit speed. One of the most important of these changes is the industry-wide move to replace circuit interconnect processes based on aluminum metallization with copper-based processes. The unique process challenges of copper metallization, coupled with the increasing cost of IC manufacturing in general, have resulted in an increased need for metal film thickness measurement for process control. Laser-generated and detected surface acoustic waves provide an ideal method for nondestructively measuring film thickness on product wafers as they move through an IC factory. A patented version of the technique has been incorporated into a commercial high-throughput measurement station. The measurement station analyzes specialized test structures in the scribe lines in between IC chips on a product wafer. Here, we describe application of the technique to all stages of the copper metallization process, including measurement of seed-layer copper and its associated underlying barrier metals, measurement of electroplated copper deposited atop the seed layer, and measurement of remaining copper film thickness following a chemical-mechanical polishing step. We highlight special capabilities to measure test arrays of submicron metal lines that closely resemble actual circuit elements. In addition, we discuss characterization of the elastic properties of typical and emerging thin film materials used in the semiconductor industry, which is a necessary step in setting up the

  18. MUSIC: An 8 channel readout ASIC for SiPM arrays

    NASA Astrophysics Data System (ADS)

    Gómez, Sergio; Gascón, David; Fernández, Gerard; Sanuy, Andreu; Mauricio, Joan; Graciani, Ricardo; Sanchez, David

    2016-04-01

    This paper presents an 8 channel ASIC for SiPM anode readout based on a novel low input impedance current conveyor (under patent1). This Multiple Use SiPM Integrated Circuit (MUSIC) has been designed to serve several purposes, including, for instance, the readout of SiPM arrays for some of the Cherenkov Telescope Array (CTA) cameras. The current division scheme at the very front end part of the circuit splits the input current into differently scaled copies which are connected to independent current mirrors. The circuit contains a tunable pole zero cancellation of the SiPM recovery time constant to deal with sensors from different manufacturers. Decay times up to 100 ns are supported covering most of the available SiPM devices in the market. MUSIC offers three main features: (1) differential output of the sum of the individual input channels; (2) 8 individual single ended analog outputs and; (3) 8 individual binary outputs. The digital outputs encode the amount of collected charge in the duration of the digital signal using a time over threshold technique. For each individual channel, the user must select the analog or digital output. Each functionality, the signal sum and the 8 A/D outputs, include a selectable dual-gain configuration. Moreover, the signal sum implements dual-gain output providing a 15 bit dynamic range. Full die simulation results of the MUSIC designed using AMS 0.35 µm SiGe technology are presented: total die size of 9 mm2, 500 MHz bandwidth for channel sum and 150 MHz bandwidth for A/D channels, low input impedance (≍32 Ω), single photon output pulse width at half maximum (FWHM) between 5 and 10 ns and with a power consumption of ≍ 30 mW/ch plus ≍ 200 mW for the 8 ch sum. Encapsulated prototype samples of the MUSIC are expected by March 2016.

  19. Application of Input-State of the System Transformation for Linearization of Selected Electrical Circuits

    NASA Astrophysics Data System (ADS)

    Zawadzki, Andrzej; Różowicz, Sebastian

    2016-05-01

    The paper presents a transformation of nonlinear electric circuit into linear one through changing coordinates (local diffeomorphism) with the use of closed feedback loop. The necessary conditions that must be fulfilled by nonlinear system to enable carrying out linearizing procedures are presented. Numerical solutions of state equations for the nonlinear system and equivalent linearized system are included.

  20. Analysis of Wave Propagation in Stratified Structures Using Circuit Analogues, with Application to Electromagnetic Absorbers

    ERIC Educational Resources Information Center

    Sjoberg, Daniel

    2008-01-01

    This paper presents an overview of how circuit models can be used for analysing wave propagation in stratified structures. Relatively complex structures can be analysed using models which are accessible to undergraduate students. Homogeneous slabs are modelled as transmission lines, and thin sheets between the slabs are modelled as lumped…

  1. The application of printed circuit board technology for fabrication of multi-channel micro-drives.

    PubMed

    Szabó, I; Czurkó, A; Csicsvari, J; Hirase, H; Leinekugel, X; Buzsáki, G

    2001-01-30

    A modular multichannel microdrive ('hyperdrive') is described. The microdrive uses printed circuit board technology and flexible fused silica capillaries. The modular design allows for the fabrication of 4-32 independently movable electrodes or 'tetrodes'. The drives are re-usable and re-loading the drive with electrodes is simple.

  2. Multirate Integration Properties of Waveform Relaxation with Applications to Circuit Simulation and Parallel Computation

    DTIC Science & Technology

    1985-11-18

    A R. Newton reviewed this thesis, and through discussion offered many suggestions on circuit simulation techniques. Along with Prof. Desoer and Prof...Berkeley, Electronics Research Laboratory, 1985 ’ [35] W. Rudin, Functional Analysis, McGraw-HiD, 1969. [36] C. A. Desoer and E. S. Kuh, Basic

  3. Analysis of Wave Propagation in Stratified Structures Using Circuit Analogues, with Application to Electromagnetic Absorbers

    ERIC Educational Resources Information Center

    Sjoberg, Daniel

    2008-01-01

    This paper presents an overview of how circuit models can be used for analysing wave propagation in stratified structures. Relatively complex structures can be analysed using models which are accessible to undergraduate students. Homogeneous slabs are modelled as transmission lines, and thin sheets between the slabs are modelled as lumped…

  4. Dielectric Circuit Board Bonding.

    DTIC Science & Technology

    circuit boards to form subassemblies and the bonding of subassemblies together. The finished circuit may include a bonded-in ground plate of copper...The patent application describes a method and apparatus for bonding of dielectric circuit boards for microwave use, the bonding together of several...wire cloth or the like and may include through- plate holes. The technique includes the build-up of thin films to provide strength, toughness and

  5. The role of periodontal ASIC3 in orofacial pain induced by experimental tooth movement in rats.

    PubMed

    Gao, Meiya; Long, Hu; Ma, Wenqiang; Liao, Lina; Yang, Xin; Zhou, Yang; Shan, Di; Huang, Renhuan; Jian, Fan; Wang, Yan; Lai, Wenli

    2016-12-01

    This study aimed to clarify the roles of Acid-sensing ion channel 3 (ASIC3) in orofacial pain following experimental tooth movement. Sixty male Sprague-Dawley rats were divided into the experimental group (40g, n = 30) and the sham group (0g, n = 30). Closed coil springs were ligated between maxillary incisor and molars to achieve experimental tooth movement. Rat grimace scale (RGS) scores were assessed at 0, 1, 3, 5, 7, and 14 days after the placement of the springs. ASIC3 immunostaining was performed and the expression levels of ASIC3 were measured through integrated optical density/area in Image-Pro Plus 6.0. Moreover, 18 rats were divided into APETx2 group (n = 6), amiloride group (n = 6), and vehicle group (n = 6), and RGS scores were obtained compared among them to verify the roles of ASIC3 in orofacial pain following tooth movement. ASIC3 expression levels became significantly higher in the experimental group than in sham group on 1, 3, and 5 days and became similar on 7 and 14 days. Pain levels (RGS scores) increased in both groups and were significantly higher in the experimental group on 1, 3, 5, and 7 days and were similar on 14 days. Periodontal ASIC3 expression levels were correlated with orofacial pain levels following experimental tooth movement. Periodontal administrations of ASIC3 antagonists (APETx2 and amiloride) could alleviate pain. This study needs to be better evidenced by RNA interference of ASIC3 in periodontal tissues in rats following experimental tooth movement. Moreover, we hope further studies would concentrate on the pain perception of ASIC3 knockout (ASIC3(-/-)) mice. Our results suggest that periodontal ASIC3 plays an important role in orofacial pain induced by experimental tooth movement. © The Author 2015. Published by Oxford University Press on behalf of the European Orthodontic Society. All rights reserved. For permissions, please email: journals.permissions@oup.com.

  6. Implementation of nanoscale circuits using dual metal gate engineered nanowire MOSFET with high-k dielectrics for low power applications

    NASA Astrophysics Data System (ADS)

    Charles Pravin, J.; Nirmal, D.; Prajoon, P.; Ajayan, J.

    2016-09-01

    This work covers the impact of dual metal gate engineered Junctionless MOSFET with various high-k dielectric in Nanoscale circuits for low power applications. Due to gate engineering in junctionless MOSFET, graded potential is obtained and results in higher electron velocity of about 31% for HfO2 than SiO2 in the channel region, which in turn improves the carrier transport efficiency. The simulation is done using sentaurus TCAD, ON current, OFF current, ION/IOFF ratio, DIBL, gain, transconductance and transconductance generation factor parameters are analysed. When using HfO2, DIBL shows a reduction of 61.5% over SiO2. The transconductance and transconductance generation factor shows an improvement of 44% and 35% respectively. The gain and output resistance also shows considerable improvement with high-k dielectrics. Using this device, inverter circuit is implemented with different high-k dielectric material and delay have been decreased by 4% with HfO2 when compared to SiO2. In addition, a significant reduction in power dissipation of the inverter circuit is obtained with high-k dielectric Dual Metal Surround Gate Junctionless Transistor than SiO2 based device. From the analysis, it is found that HfO2 will be a better alternative for the future nanoscale device.

  7. All-optical switching with bacteriorhodopsin protein coated microcavities and its application to low power computing circuits

    NASA Astrophysics Data System (ADS)

    Roy, Sukhdev; Prasad, Mohit; Topolancik, Juraj; Vollmer, Frank

    2010-03-01

    We show all-optical switching of an input infrared laser beam at 1310 nm by controlling the photoinduced retinal isomerization to tune the resonances in a silica microsphere coated with three bacteriorhodopsin (BR) protein monolayers. The all-optical tunable resonant coupler re-routes the infrared beam between two tapered fibers in 50 μs using a low power (<200 μW) green (532 nm) and blue (405 nm) pump beams. The basic switching configuration has been used to design all-optical computing circuits, namely, half and full adder/subtractor, de-multiplexer, multiplexer, and an arithmetic unit. The design requires 2n-1 switches to realize n bit computation. The designs combine the exceptional sensitivities of BR and high-Q microcavities and the versatile tree architecture for realizing low power circuits and networks (approximately mW power budget). The combined advantages of high Q-factor, tunability, compactness, and low power control signals, with the flexibility of cascading switches to form circuits, and reversibility and reconfigurability to realize arithmetic and logic functions, makes the designs promising for practical applications. The designs are general and can be implemented (i) in both fiber-optic and integrated optic formats, (ii) with any other coated photosensitive material, or (iii) any externally controlled microresonator switch.

  8. Process design kit and circuits at a 2 µm technology node for flexible wearable electronics applications (Conference Presentation)

    NASA Astrophysics Data System (ADS)

    Torres-Miranda, Miguel; Petritz, Andreas; Gold, Herbert; Stadlober, Barbara

    2016-09-01

    In this work we present our most advanced technology node of organic thin film transistors (OTFTs) manufactured with a channel length as short as 2 μm by contact photolithography and a self-alignment process directly on a plastic substrate. Our process design kit (PDK) is described with P-type transistors, capacitors and 3 metal layers for connections of complex circuits. The OTFTs are composed of a double dielectric layer with a photopatternable ultra thin polymer (PNDPE) and alumina, with a thickness on the order of 100 nm. The organic semiconductor is either Pentacene or DNTT, which have a stable average mobility up to 0.1 cm2/Vs. Finally, a polymer (e.g.: Parylene-C) is used as a passivation layer. We describe also our design rules for the placement of standard circuit cells. A "plastic wafer" is fabricated containing 49 dies. Each die of 1 cm2 has between 25 to 50 devices, proving larger scale integration in such a small space, unique in organic technologies. Finally, we present the design (by simulations using a Spice model for OTFTs) and the test of analog and digital basic circuits: amplifiers with DC gains of about 20 dB, comparators, inverters and logic gates working in the frequency range of 1-10 kHz. These standard circuit cells could be used for signal conditioning and integrated as active matrices for flexible sensors from 3rd party institutions, thus opening our fab to new ideas and sophisticated pre-industrial low cost applications for the emerging fields of biomedical devices and wearable electronics for virtual/augmented reality.

  9. Thermoelastic properties of plain weave composites for circuit board applications: A comparison of models and experiments

    SciTech Connect

    Ockers, J.M.; Sottos, N.R.

    1994-12-31

    The results of several micromechanical models are presented for predicting the properties of woven glass epoxy substrates used in multilayer circuit boards. Two new models are formulated and the predictions of the elastic moduli, Poisson`s ratios, and expansion coefficients are compared with the results of previously developed one and two dimensional models. The properties of several commercially pressed circuit boards are determined experimentally and compared with all of the different models. One of the newly proposed models, which does not use classical lamination theory, results in a significant improvement for the prediction of the Poisson`s ratios. Finally, parametric studies are performed to predict the influence of fabric geometry on the in-plane thermal expansion coefficients and elastic moduli. Optimal weaving parameters are identified which lead to improved dimensional stability.

  10. Scalable Sensor Data Processor: A Multi-Core Payload Data Processor ASIC

    NASA Astrophysics Data System (ADS)

    Berrojo, L.; Moreno, R.; Regada, R.; Garcia, E.; Trautner, R.; Rauwerda, G.; Sunesen, K.; He, Y.; Redant, S.; Thys, G.; Andersson, J.; Habinc, S.

    2015-09-01

    The Scalable Sensor Data Processor (SSDP) project, under ESA contract and with TAS-E as prime contractor, targets the development of a multi-core ASIC for payload data processing to be used, among other terrestrial and space application areas, in future scientific and exploration missions with harsh radiation environments. The SSDP is a mixed-signal heterogeneous multi-core System-on-Chip (SoC). It combines GPP and NoC-based DSP subsystems with on-chip ADCs and several standard space I/Fs to make a flexible, configurable and scalable device. The NoC comprises two state-of-the-art fixed point Xentium® DSP processors, providing the device with high data processing capabilities.

  11. Methods of fabricating applique circuits

    DOEpatents

    Dimos, Duane B.; Garino, Terry J.

    1999-09-14

    Applique circuits suitable for advanced packaging applications are introduced. These structures are particularly suited for the simple integration of large amounts (many nanoFarads) of capacitance into conventional integrated circuit and multichip packaging technology. In operation, applique circuits are bonded to the integrated circuit or other appropriate structure at the point where the capacitance is required, thereby minimizing the effects of parasitic coupling. An immediate application is to problems of noise reduction and control in modern high-frequency circuitry.

  12. High fidelity equivalent circuit representation of induction motor determined by finite elements for electric vehicle drive applications

    SciTech Connect

    Vamvakari, A.; Kandianis, A.; Kladas, A.; Manias, S. )

    1999-05-01

    The paper presents the methodology for determination of an induction motor model suitable for harmonic representation on inverter supply. Harmonic iron losses are considered by convenient modifications of the standard equivalent circuit while the parameter variations for different operating conditions are determined by finite element modelling. The proposed motor representation is particularly important in cases that the drive efficiency is of major concern over a wide range of operating conditions such as in electrical vehicle applications. The method is illustrated with respect to an experimental set-up involving a 1,5 kW squirrel cage induction motor supplied by a PWM inverter.

  13. Application of the leak-before-break concept to the primary circuit piping of the Leningrad NPP

    SciTech Connect

    Eperin, A.P.; Zakharzhevsky, Yu.O.; Arzhaev, A.I.

    1997-04-01

    A two-year Finnish-Russian cooperation program has been initiated in 1995 to demonstrate the applicability of the leak-before-break concept (LBB) to the primary circuit piping of the Leningrad NPP. The program includes J-R curve testing of authentic pipe materials at full operating temperature, screening and computational LBB analyses complying with the USNRC Standard Review Plan 3.6.3, and exchange of LBB-related information with emphasis on NDE. Domestic computer codes are mainly used, and all tests and analyses are independently carried out by each party. The results are believed to apply generally to RBMK type plants of the first generation.

  14. Integrated circuit debug through FPGA emulation: application to a PIC-18 macrocell

    NASA Astrophysics Data System (ADS)

    Garcia-Valderas, Mario; de la Torre-Arnanz, Eduardo; Casado-Ortiz, Fernando; Entrena-Arrontes, Luis; Riesgo-Alcaide, Teresa

    2005-06-01

    FPGA emulation has become a common way to check if a digital circuit has been correctly designed. Although in the last years FPGA vendors have developed tools to embed logic analysers along with circuits in FPGAs, like Chipscope ILA from Xilinx, FPGA emulation still lacks the availability of more effective and versatile debug methods and tools. In order to check microprocessor system designs, several approaches have been used, including several combinations of logic simulators, instruction simulators, hardware emulators and in-circuit emulators. Nowadays, System-On-Chip design requires the implementation of microprocessor cores in FPGAs for prototyping. These cores do not usually include built-in debug features. In this paper, methods and tools for the development and operation of FPGA debug features are presented. Debug features are implemented in FPGAs through the insertion of JTAG accessible debug modules into the target design. The debug modules that have already been designed offer features that range from simple event detection and signal monitoring to the most powerful and resource consuming, like tracing, complex event and sequence detection and microprocessor in-circuit emulation. The most important properties of the presented debug features are their high configurability, which allow adjusting them to available logic resources, remote control of debug logic and expandability by means of user customized debug blocks. Tools have been developed to automate the required tasks: debug logic selection and configuration, debug logic insertion and debug logic operation. The proposed methods and tools have been applied to a microprocessor system based on a PIC-18 macrocell and implemented in a Xilinx Spartan-3 FPGA.

  15. Investigation on critical breakdown electric field of hot carbon dioxide for gas circuit breaker applications

    NASA Astrophysics Data System (ADS)

    Sun, Hao; Rong, Mingzhe; Wu, Yi; Chen, Zhexin; Yang, Fei; Murphy, Anthony B.; Zhang, Hantian

    2015-02-01

    Sulfur hexafluoride (SF6) gas is widely used in high-voltage circuit breakers, but due to its high global warming potential, substitutes are being sought. CO2 has been investigated as a candidate based on its arc interruption performance. The hot gas in the circuit breaker after current zero, with a complicated species composition caused by the dissociation and many other reactions, will lead to the electrical breakdown, which is one of the major concerns in assessing the arc interruption performance. Despite this, little research has been reported on the dielectric strength of hot CO2. In this paper, the dielectric properties of hot CO2 related to the dielectric recovery phase of the circuit breaker were investigated in the temperature range from 300 to 4000 K and in the pressure range from 0.01 to 1.0 MPa. Under the assumptions of local thermodynamic equilibrium (LTE) and local chemical equilibrium (LCE), the equilibrium compositions of hot CO2 were obtained based on Gibbs free energy minimization. The cross sections for interactions between electrons and the species are presented. The critical reduced electric field strength of CO2 was determined by balancing electron generation and loss. These were evaluated using the electron energy distribution function (EEDF) derived from the two-term Boltzmann transport equation. The result indicates that unlike SF6 or air, in hot CO2 the reduced critical electric field strength does not change monotonically with increasing heavy-particle temperature from 300 to 4000 K. CO2 has a superior dielectric strength to pure SF6 above 2500 K at 0.5 MPa, which means it has the potential to improve the interruption performance of the circuit breakers, while reducing the global warming effect. Good agreement was found with published experimental results and calculations for CO2 at room temperature, and with previous calculations for hot CO2.

  16. Application of drive circuit based on L298N in direct current motor speed control system

    NASA Astrophysics Data System (ADS)

    Yin, Liuliu; Wang, Fang; Han, Sen; Li, Yuchen; Sun, Hao; Lu, Qingjie; Yang, Cheng; Wang, Quanzhao

    2016-10-01

    In the experiment of researching the nanometer laser interferometer, our design of laser interferometer circuit system is up to the wireless communication technique of the 802.15.4 IEEE standard, and we use the RF TI provided by Basic to receive the data on speed control system software. The system's hardware is connected with control module and the DC motor. However, in the experiment, we found that single chip microcomputer control module is very difficult to drive the DC motor directly. The reason is that the DC motor's starting and braking current is larger than the causing current of the single chip microcomputer control module. In order to solve this problem, we add a driving module that control board can transmit PWM wave signal through I/O port to drive the DC motor, the driving circuit board can come true the function of the DC motor's positive and reversal rotation and speed adjustment. In many various driving module, the L298N module's integrated level is higher compared with other driver module. The L298N model is easy to control, it not only can control the DC motor, but also achieve motor speed control by modulating PWM wave that the control panel output. It also has the over-current protection function, when the motor lock, the L298N model can protect circuit and motor. So we use the driver module based on L298N to drive the DC motor. It is concluded that the L298N driver circuit module plays a very important role in the process of driving the DC motor in the DC motor speed control system.

  17. VeloPix: the pixel ASIC for the LHCb upgrade

    NASA Astrophysics Data System (ADS)

    Poikela, T.; De Gaspari, M.; Plosila, J.; Westerlund, T.; Ballabriga, R.; Buytaert, J.; Campbell, M.; Llopart, X.; Wyllie, K.; Gromov, V.; van Beuzekom, M.; Zivkovic, V.

    2015-01-01

    The LHCb Vertex Detector (VELO) will be upgraded in 2018 along with the other subsystems of LHCb in order to enable full readout at 40 MHz, with the data fed directly to the software triggering algorithms. The upgraded VELO is a lightweight hybrid pixel detector operating in vacuum in close proximity to the LHC beams. The readout will be provided by a dedicated front-end ASIC, dubbed VeloPix, matched to the LHCb readout requirements and the 55 × 55 μm VELO pixel dimensions. The chip is closely related to the Timepix3, from the Medipix family of ASICs. The principal challenge that the chip has to meet is a hit rate of up to 900 Mhits/s, resulting in a required output bandwidth of more than 16 Gbit/s. The occupancy across the chip is also very non-uniform, and the radiation levels reach an integrated 400 Mrad over the lifetime of the detector.VeloPix is a binary pixel readout chip with a data driven readout, designed in 130 nm CMOS technology. The pixels are combined into groups of 2 × 4 super pixels, enabling a shared logic and a reduction of bandwidth due to combined address and time stamp information. The pixel hits are combined with other simultaneous hits in the same super pixel, time stamped, and immediately driven off-chip. The analog front-end must be sufficiently fast to accurately time stamp the data, with a small enough dead time to minimize data loss in the most occupied regions of the chip. The data is driven off chip with a custom designed high speed serialiser. The current status of the ASIC design, the chip architecture and the simulations will be described.

  18. Preparation of graphite conductive paint and its application to the construction of RC circuits on paper

    NASA Astrophysics Data System (ADS)

    Grisales, C.; Herrera, N.; Fajardo, F.

    2016-09-01

    We describe a simple procedure for the preparation of graphite-based conductive paint and determine its basic transport properties when applied, comparing them to those of pencil strokes. Ohm’s law was fulfilled on the applied paint, which makes it an ideal strategy to teach the relations between a resistor’s length, width and resistance. The conductive paint was used in the construction of RC circuits on paper in a simple and didactic format. Using only the paint and a piece of cardboard, a completely functional parallel plate capacitor can be constructed with different plate geometries; in particular, we painted circular and rectangular plates. The charge and discharge cycles of the two RC circuits painted were observed in the oscilloscope. We obtained characteristic times and estimated the value of the dielectric constant of paper, which serves as a dielectric between the plates of the capacitors. We found conductive paint to be a useful and easy method to teach basic electricity and circuit concepts in fundamental courses and lab practices because it allows one to visualise properties such as the dependence of resistance and capacitance with geometric factors using a specific material.

  19. Characterization of bandgap reference circuits designed for high energy physics applications

    NASA Astrophysics Data System (ADS)

    Traversi, G.; De Canio, F.; Gaioni, L.; Manghisoni, M.; Mattiazzo, S.; Ratti, L.; Re, V.; Riceputi, E.

    2016-07-01

    The objective of this work is to design a high performance bandgap voltage reference circuit in a standard commercial 65 nm CMOS technology capable of operating in harsh radiation environments. A prototype circuit based on three different devices (diode, bipolar transistor and MOSFET) was fabricated and tested. Measurement results show a temperature variation as low as ±3.4 mV over a temperature range of 170 ° C (-30 °C to 140 °C) and a line regulation at room temperature of 5.2%/V. Measured VREF is 690 mV±15 mV (3σ) for 26 samples on the same wafer. Circuits correctly operate with supply voltages in the range from 1.32 V down to 0.78 V. A reference voltage shift of only 7.6 mV (around 1.1%) was measured after irradiation with 10 keV X-rays up to an integrated dose of 225 Mrad (SiO2).

  20. Clinical application of circuit training for subacute stroke patients: a preliminary study

    PubMed Central

    Kim, Sun Mi; Han, Eun Young; Kim, Bo Ryun; Hyun, Chul Woong

    2016-01-01

    [Purpose] To investigate how task-oriented circuit training for the recovery motor control of the lower-extremity, balance and walking endurance could be clinically applied to subacute stroke inpatient group therapy. [Subjects and Methods] Twenty subacute stroke patients were randomly assigned to the intervention group (n=10) or the control group (n=10). The intervention consisted of a structured, progressive, inpatient circuit training program focused on mobility and gait training as well as physical fitness training that was performed for 90 minutes, 5 days a week for 4 weeks. The control group received individual physiotherapy of neurodevelopmental treatment for 60 minutes, 5 days a week for 4 weeks. Outcome measures were lower-extremity motor control, balance, gait endurance and activities of daily living before and after 4 weeks. [Results] There were no significant differences at baseline between the two groups. After 4 weeks, both groups showed significant improvements in all outcome measures, but there were no significant differences between the two groups during the invention period. [Conclusion] In spite of the small sample size, these findings suggest that task-oriented circuit training might be used as a cost-effective and alternative method of individual physiotherapy for the motor recovery of lower-extremity, balance and walking endurance of subacute stroke patients. PMID:26957751

  1. ASIC-dependent LTP at multiple glutamatergic synapses in amygdala network is required for fear memory

    PubMed Central

    Chiang, Po-Han; Chien, Ta-Chun; Chen, Chih-Cheng; Yanagawa, Yuchio; Lien, Cheng-Chang

    2015-01-01

    Genetic variants in the human ortholog of acid-sensing ion channel-1a subunit (ASIC1a) gene are associated with panic disorder and amygdala dysfunction. Both fear learning and activity-induced long-term potentiation (LTP) of cortico-basolateral amygdala (BLA) synapses are impaired in ASIC1a-null mice, suggesting a critical role of ASICs in fear memory formation. In this study, we found that ASICs were differentially expressed within the amygdala neuronal population, and the extent of LTP at various glutamatergic synapses correlated with the level of ASIC expression in postsynaptic neurons. Importantly, selective deletion of ASIC1a in GABAergic cells, including amygdala output neurons, eliminated LTP in these cells and reduced fear learning to the same extent as that found when ASIC1a was selectively abolished in BLA glutamatergic neurons. Thus, fear learning requires ASIC-dependent LTP at multiple amygdala synapses, including both cortico-BLA input synapses and intra-amygdala synapses on output neurons. PMID:25988357

  2. ASIC3 is required for development of fatigue-induced hyperalgesia

    PubMed Central

    Gregory, Nicholas S.; Brito, Renan G.; Oliveira Fusaro, Maria Cláudia G; Sluka, Kathleen A.

    2015-01-01

    An acute bout of exercise can exacerbate pain, hindering participation in regular exercise and daily activities. The mechanisms underlying pain in response to acute exercise are poorly understood. We hypothesized that proton accumulation during muscle fatigue activates ASIC3 on muscle nociceptors to produce hyperalgesia. We investigated the role of ASIC3 using genetic and pharmacological approaches in a model of fatigue-enhanced hyperalgesia. This model uses two injections of pH 5.0 saline into muscle in combination with an electrically-induced fatigue of the same muscle just prior to the second injection of acid to induce mechanical hyperalgesia. We show a significant decrease in muscle force and decrease in muscle pH after 6 minutes of electrical stimulation. Genetic deletion of ASIC3 using knockout mice and pharmacological blockade of ASIC3 with APETx2 in muscle prevents the fatigue-enhanced hyperalgesia. However, ASIC3−/− mice and APETx2 have no effect on the fatigue response. Genetic deletion of ASIC3 in primary afferents innervating muscle using an HSV-1 expressing miRNA to ASIC3 surprisingly had no effect on the development of the hyperalgesia. Muscle fatigue increased the number of macrophages in muscle, and removal of macrophages from muscle with clodronate liposomes prevented the development of fatigue-enhanced hyperalgesia. Thus, these data suggest that fatigue reduces pH in muscle that subsequently activates ASIC3 on macrophages to enhance hyperalgesia to muscle insult. PMID:25577172

  3. Single event effect hardness for the front-end ASICs in the DAMPE satellite BGO calorimeter

    NASA Astrophysics Data System (ADS)

    Gao, Shan-Shan; Jiang, Di; Feng, Chang-Qing; Xi, Kai; Liu, Shu-Bin; An, Qi

    2016-01-01

    The Dark Matter Particle Explorer (DAMPE) is a Chinese scientific satellite designed for cosmic ray studies with a primary scientific goal of indirect detection of dark matter particles. As a crucial sub-detector, the BGO calorimeter measures the energy spectrum of cosmic rays in the energy range from 5 GeV to 10 TeV. In order to implement high-density front-end electronics (FEE) with the ability to measure 1848 signals from 616 photomultiplier tubes on the strictly constrained satellite platform, two kinds of 32-channel front-end ASICs, VA160 and VATA160, are customized. However, a space mission period of more than 3 years makes single event effects (SEEs) become threats to reliability. In order to evaluate SEE sensitivities of these chips and verify the effectiveness of mitigation methods, a series of laser-induced and heavy ion-induced SEE tests were performed. Benefiting from the single event latch-up (SEL) protection circuit for power supply, the triple module redundancy (TMR) technology for the configuration registers and the optimized sequential design for the data acquisition process, 52 VA160 chips and 32 VATA160 chips have been applied in the flight model of the BGO calorimeter with radiation hardness assurance. Supported by Strategic Priority Research Program on Space Science of the Chinese Academy of Sciences (XDA04040202-4) and Fundamental Research Funds for the Central Universities (WK2030040048)

  4. A 15 GSa/s, 1.5 GHz bandwidth waveform digitizing ASIC

    NASA Astrophysics Data System (ADS)

    Oberla, Eric; Genat, Jean-Francois; Grabas, Hervé; Frisch, Henry; Nishimura, Kurtis; Varner, Gary

    2014-01-01

    The PSEC4 custom integrated circuit was designed for the recording of fast waveforms for use in large-area time-of-flight detector systems. The ASIC has been fabricated using the IBM-8RF 0.13 μm CMOS process. On each of the six analog channels, PSEC4 employs a switched capacitor array (SCA) of 256 samples deep, a ramp-compare ADC with 10.5 bits of DC dynamic range, and a serial data readout with the capability of region-of-interest windowing to reduce dead time. The sampling rate can be adjusted between 4 and 15 Gigasamples/second (GSa/s) on all channels and is servo-controlled on-chip with a low-jitter delay-locked loop (DLL). The input signals are passively coupled on-chip with a -3 dB analog bandwidth of 1.5 GHz. The power consumption in quiescent sampling mode is less than 50 mW/chip; at a sustained trigger and a readout rate of 50 kHz the chip draws 100 mW. After fixed-pattern pedestal subtraction, the uncorrected integral non-linearity is 0.15% over a 750 mV dynamic range. With a linearity correction, a full 1 V signal voltage range is available. The sampling timebase has a fixed-pattern non-linearity with an RMS of 13%, which can be corrected for precision waveform feature extraction and timing.

  5. ASIC3 Contributes to the Blunted Muscle Metaboreflex in Heart Failure

    PubMed Central

    Xing, Jihong; Lu, Jian; Li, Jianhua

    2014-01-01

    Introduction During exercise, the sympathetic nervous system is activated and blood pressure and heart rate increase. In heart failure (HF), the muscle metaboreceptor contribution to sympathetic outflow is attenuated and the mechanoreceptor contribution is accentuated. Previous studies suggest that lactic acid stimulates acid sensing channel subtype 3 (ASIC3), inducing a neurally mediated pressor response. Thus, we hypothesized that the pressor response to ASIC3 stimulation is smaller in HF rats due to attenuation in expression and function of ASIC3 in sensory nerves. Methods Lactic acid was injected into the arterial blood supply of the hindlimb to stimulate ASIC3 in muscle afferent nerves and evoke the muscle metaboreceptor response in control rats and HF rats. Also, western blot analysis was employed to examine expression of ASIC3 in dorsal root ganglion (DRG) and patch clamp to examine current response with ASIC3 activation. Results Lactic acid (4 µmol/kg) increased mean arterial pressure by 28±5 mmHg in controls (n=6) but only by 16±3 mmHg (P<0.05 vs. control) in HF (n=8). In addition, HF decreased the protein levels of ASIC3 in DRG (optical density: 1.03±0.02 in control vs. 0.79±0.03 in HF, P<0.05; n=6 in each group). The peak current amplitude of dorsal DRG neuron in response to ASIC3 stimulation is smaller in HF rats than that in control rats. Conclusions Compared with controls, cardiovascular responses to lactic acid administered into the hindlimb muscles are blunted in HF rats owing to attenuated ASIC3. This suggests that ASIC3 plays a role in engagement in the attenuated metaboreceptor component of the exercise pressor reflex in HF. PMID:24983337

  6. Tunable silica-on-silicon planar lightwave circuits for signal processing applications

    NASA Astrophysics Data System (ADS)

    Callender, Claire L.; Dumais, Patrick; Jacob, Sarkis; Blanchetière, Chantal; Ledderhof, Chris; Samadi, Payman; Kostko, Irina A.; Xia, Bing; Chen, Lawrence R.

    2009-06-01

    The development of silica planar lightwave circuits (PLCs) employing multiple phase-shifting elements to achieve optical signal processing is presented. Thermo-optic switching in Mach Zehnder interferometer (MZI) structures has been demonstrated with typical switching powers of 250-300 mW. 6-loop lattice-form MZI devices designed with specific filter responses have been fabricated, packaged, and tested. 10 GHz to 40 GHz pulse repetition rate multiplication has been achieved, and the tunability of the 6 phase control elements allows the generation of arbitrary 4-bit binary code patterns. Further improvements in complexity, power consumption, loss, and polarization sensitivity in these devices are discussed.

  7. Numerical solution of stiff systems of ordinary differential equations with applications to electronic circuits

    NASA Technical Reports Server (NTRS)

    Rosenbaum, J. S.

    1971-01-01

    Systems of ordinary differential equations in which the magnitudes of the eigenvalues (or time constants) vary greatly are commonly called stiff. Such systems of equations arise in nuclear reactor kinetics, the flow of chemically reacting gas, dynamics, control theory, circuit analysis and other fields. The research reported develops an A-stable numerical integration technique for solving stiff systems of ordinary differential equations. The method, which is called the generalized trapezoidal rule, is a modification of the trapezoidal rule. However, the method is computationally more efficient than the trapezoidal rule when the solution of the almost-discontinuous segments is being calculated.

  8. PHEMT as a circuit element for high impedance nanopower amplifiers for ultra-low temperatures application

    NASA Astrophysics Data System (ADS)

    Korolev, A. M.; Shulga, V. M.; Gritsenko, I. A.; Sheshin, G. A.

    2015-04-01

    In this work, high electron mobility transistor (HEMT) was studied as a circuit element for amplifiers operating at temperatures of the order of 10-100 mK. To characterize the HEMT, the relative parameters are proposed to be used. HEMT characteristics were measured at a temperature of 50 mK for the first time. It follows from the reported studies that the power consumption of high-impedance HEMT-based amplifiers can be reduced down to hundreds of nanowatt or even lower.

  9. A novel boost circuit design and in situ electricity application for elemental sulfur recovery

    NASA Astrophysics Data System (ADS)

    Liu, Jia; Feng, Yujie; He, Weihua; Gong, Yuanyuan; Qu, Youpeng; Ren, Nanqi

    2014-02-01

    A novel system containing a microbial electrochemical system (MES) for electricity generation and sulfate conversion, a novel boost circuit (NBC) for in situ utilization of the electrical energy and an electrochemical deposition cell (ECD) to recover sulfur in water is designed and established. This combined system has a higher energy utilization efficiency of 63.6% than that of conventional sulfate reduction reactors with an elemental sulfur recovery efficiency up to 46.5 ± 1.5% without net energy input. This system offers a promising, and cost-effective approach for sulfate wastewater treatment.

  10. Dual-quadrature coherent receiver for 100G Ethernet applications based on polymer planar lightwave circuit.

    PubMed

    Wang, Jin; Kroh, Marcel; Theurer, Abongwa; Zawadzki, Crispin; Schmidt, Detlef; Ludwig, Reinhold; Lauermann, Matthias; Zhang, Ziyang; Beling, Andreas; Matiss, Andreas; Schubert, Colja; Steffan, Andreas; Keil, Norbert; Grote, Norbert

    2011-12-12

    A dual-quadrature coherent receiver based on a polymer planar lightwave circuit (PLC) is presented. This receiver comprises two separate optical 90°-hybrid chips made of polymer waveguides and hybridly integrated with InGaAs/InP photodiode (PD) arrays. The packaged receiver was successfully operated in 112 Gbit/s dual-polarization quadrature phase-shift keying (QPSK) transmission experiments. In back-to-back configuration the OSNR requirement for a BER value of 10(-3) was 15.1 dB which has to be compared to a theoretical limit of 13.8 dB.

  11. Optically controlled microwave devices and circuits: Emerging applications in space communications systems

    NASA Technical Reports Server (NTRS)

    Bhasin, Kul B.; Simons, Rainee N.

    1987-01-01

    Optical control of microwave devices and circuits by an optical fiber has the potential to simplify signal distribution networks in high frequency communications systems. The optical response of two terminal and three terminal (GaAs MESFET, HEMT, PBT) microwave devices are compared and several schemes for controlling such devices by modulated optical signals examined. Monolithic integration of optical and microwave functions on a single semiconductor substrate is considered to provide low power, low loss, and reliable digital and analog optical links for signal distribution.

  12. ASIC for calorimetric measurements in the astrophysical experiment NUCLEON

    NASA Astrophysics Data System (ADS)

    Atkin, E.; Voronin, A.; Karmanov, D.; Kudryashov, I.; Kovalev, I.; Shumikhin, V.

    2016-02-01

    A satellite with the NUCLEON apparatus was launched in Dec. 2014. The space NUCLEON project of ROSCOSMOS is designed to investigate cosmic ray nuclei energy spectra from 100 GeV to 1000 TeV as well as cosmic ray electron spectra from 20 GeV to 3 TeV. The method of energy determination by means of a silicon instrument for measuring the particle charge of cosmic rays and the calorimetric system were developed. The main parameters, that determine the quality of calorimetric systems are linearity of transfer characteristic and the dynamic range of input signals, which should reach 30 000 MIPs (minimum ionizing particles). The ASIC, satisfying these requirements, consisting of 32 channels with a unique dynamic range from 1 to 40000 MIPs, signal to noise ratio not less than 2.5 at a shaper peaking time of 2 μs and a low power consumption of 1.5 mW/channel has been designed. The first results of the ASIC functionality in space are presented.

  13. A planar lightwave circuit based micro interrogator and its applications to the interrogation of multiplexed optical fiber Bragg grating sensors

    NASA Astrophysics Data System (ADS)

    Xiao, Gaozhi; Mrad, Nezih; Guo, Honglei; Zhang, Zhiyi; Yao, Jianping

    2008-12-01

    Optical fiber Bragg grating sensors have found potential applications in many fields, but the lack of a simple, field deployable and low cost interrogation system is hindering their deployment. To tackle this, we have developed a micro optical sensor interrogator using a monolithically integrated planar lightwave circuit based echelle diffractive grating demultiplexer and a detector array. The design and development of this device are presented in this paper. It has been found that the measurement range of this micro interrogator is more than 25 nm with better than 1 pm resolution. This paper also reports the applications of the micro interrogator developed to the monitoring of commercial optical fiber Bragg grating (FBG) temperature sensors and mechanical sensors. The results obtained are very satisfactory and in some cases, they are better than those obtained using commercial bench top lab equipment.

  14. Applications of the Fokker-Planck equation in circuit quantum electrodynamics

    NASA Astrophysics Data System (ADS)

    Elliott, Matthew; Ginossar, Eran

    2016-10-01

    We study exact solutions of the steady-state behavior of several nonlinear open quantum systems which can be applied to the field of circuit quantum electrodynamics. Using Fokker-Planck equations in the generalized P representation, we investigate the analytical solutions of two fundamental models. First, we solve for the steady-state response of a linear cavity that is coupled to an approximate transmon qubit and use this solution to study both the weak and strong driving regimes, using analytical expressions for the moments of both cavity and transmon fields, along with the Husimi Q function for the transmon. Second, we revist exact solutions of a quantum Duffing oscillator, which is driven both coherently and parametrically while also experiencing decoherence by the loss of single photons and pairs of photons. We use this solution to discuss both stabilization of Schrödinger cat states and the generation of squeezed states in parametric amplifiers, in addition to studying the Q functions of the different phases of the quantum system. The field of superconducting circuits, with its strong nonlinearities and couplings, has provided access to parameter regimes in which returning to these exact quantum optics methods can provide valuable insights.

  15. Comparison of a new integrated current source with the modified Howland circuit for EIT applications.

    PubMed

    Hong, Hongwei; Rahal, Mohamad; Demosthenous, Andreas; Bayford, Richard H

    2009-10-01

    Multi-frequency electrical impedance tomography (MF-EIT) systems require current sources that are accurate over a wide frequency range (1 MHz) and with large load impedance variations. The most commonly employed current source design in EIT systems is the modified Howland circuit (MHC). The MHC requires tight matching of resistors to achieve high output impedance and may suffer from instability over a wide frequency range in an integrated solution. In this paper, we introduce a new integrated current source design in CMOS technology and compare its performance with the MHC. The new integrated design has advantages over the MHC in terms of power consumption and area. The output current and the output impedance of both circuits were determined through simulations and measurements over the frequency range of 10 kHz to 1 MHz. For frequencies up to 1 MHz, the measured maximum variation of the output current for the integrated current source is 0.8% whereas for the MHC the corresponding value is 1.5%. Although the integrated current source has an output impedance greater than 1 MOmega up to 1 MHz in simulations, in practice, the impedance is greater than 160 kOmega up to 1 MHz due to the presence of stray capacitance.

  16. ChromAIX: a high-rate energy-resolving photon-counting ASIC for spectal computed tomography

    NASA Astrophysics Data System (ADS)

    Steadman, Roger; Herrmann, Christoph; Mülhens, Oliver; Maeding, Dale G.; Colley, James; Firlit, Ted; Luhta, Randy; Chappo, Marc; Harwood, Brian; Kosty, Doug

    2010-04-01

    In Computed Tomography applications a major opportunity has been identified in the exploitation of the spectral information inherently available due to the polychromatic emission of the X-ray tube. Current CT technology based on indirect-conversion and integrating-mode detection can be used to some extent to distinguish the two predominant physical causes of energy-dependent attenuation (photo-electric effect and Compton effect) by using dual-energy techniques, e.g. kVp switching, dual-source or detector stacking. Further improvements can be achieved by transitioning to direct-conversion technologies and counting-mode detection, which inherently exhibits a better signal-to-noise ratio. Further including energy discrimination, enables new applications, which are not feasible with dual-energy techniques, e.g. the possibility to discriminate K-edge features (contrast agents, e.g. Gadolinium) from the other contributions to the x-ray attenuation of a human body. The capability of providing energy-resolved information with more than two different measurements is referred to as Spectral CT. To study the feasibility of Spectral CT, an energy-resolving proprietary photon counting ASIC (ChromAIX) has been designed to provide high count-rate capabilities while offering energy discrimination. The ChromAIX ASIC consists of an arrangement of 4 by 16 pixels with an isotropic pitch of 300 μm. Each pixel contains a number of independent energy discriminators with their corresponding 12-bit counters with continuous read-out capability. Observed Poissonian count-rates exceeding 10 Mcps (corresponding to approximately 27 Mcps incident mean Poisson rate) have been experimentally validated through electrical characterization. The measured noise of 2.6 mVRMS (4 keV FWHM) adheres to specifications. The ChromAIX ASIC has been specifically designed to support direct-converting materials CdZnTe and CdTe.

  17. Investigation of measurement distortion and application of finite element modeling to magnetic material characterization in a closed-circuit

    NASA Astrophysics Data System (ADS)

    Pugh, Barry Kevin

    becomes statistically significant at the t-test risk level of alpha = 0.05 significance level at approximately a 14° gap. The successful use of FEM in determining the closed circuit corrective methodology has led to the identification of the potential for a similar open circuit application. The calculation of the demagnetizing factor, N, required for open circuit measurements is a difficult exercise and, in the past, could only be precisely calculated for an ellipsoidal sample. For other regular geometries N was determined experimentally or calculated using certain assumptions. Either method introduces errors. This application used FEM to calculate the spherical demagnetizing factor of a magnetic sphere within a long solenoid. The FEM results indicated a demagnetizing factor N = 0.333 in all three axis. This result is in agreement with widely published and accepted results for such an arrangement. The hysteresis distortion complicates identifying and developing new magnetic materials. Only a comprehensive understanding of the phenomenon can help to establish effective correction methods, which is important for infrastructure enhancement in scientific research and for development of advanced modern technology to accurately characterize new magnetic materials.

  18. ADDER CIRCUIT

    DOEpatents

    Jacobsohn, D.H.; Merrill, L.C.

    1959-01-20

    An improved parallel addition unit is described which is especially adapted for use in electronic digital computers and characterized by propagation of the carry signal through each of a plurality of denominationally ordered stages within a minimum time interval. In its broadest aspects, the invention incorporates a fast multistage parallel digital adder including a plurality of adder circuits, carry-propagation circuit means in all but the most significant digit stage, means for conditioning each carry-propagation circuit during the time period in which information is placed into the adder circuits, and means coupling carry-generation portions of thc adder circuit to the carry propagating means.

  19. Control of threshold voltage in organic thin-film transistors by modifying gate electrode surface with MoOX aqueous solution and inverter circuit applications

    NASA Astrophysics Data System (ADS)

    Shiwaku, Rei; Yoshimura, Yudai; Takeda, Yasunori; Fukuda, Kenjiro; Kumaki, Daisuke; Tokito, Shizuo

    2015-02-01

    We controlled the threshold voltage of organic thin-film transistors (TFTs) by treating only the gate electrode surface with a MoOX aqueous solution and used them to build inverter circuits. The threshold voltage was changed by varying the concentration of the MoOX aqueous solution. A strong correlation between the work function of the gate electrode and the threshold voltage was observed. The threshold voltage of one of the two organic TFT devices in the inverter circuit was selectively changed by +2.3 V by reducing the concentration of the MoOx solution. We controlled the switching voltage of p-type organic inverter circuits and obtained excellent inverter characteristics. These results indicate that using a MoOx aqueous solution to control the threshold voltage is very useful for integrated circuits applications.

  20. Application of Printed Circuit Board Technology to FT-ICR MS Analyzer Cell Construction and Prototyping

    SciTech Connect

    Leach, Franklin E.; Norheim, Randolph V.; Anderson, Gordon A.; Pasa-Tolic, Ljiljana

    2014-12-01

    Although Fourier transform ion cyclotron resonance mass spectrometry (FT-ICRMS) remains themass spectrometry platform that provides the highest levels of performance for mass accuracy and resolving power, there is room for improvement in analyzer cell design as the ideal quadrupolar trapping potential has yet to be generated for a broadband MS experiment. To this end, analyzer cell designs have improved since the field’s inception, yet few research groups participate in this area because of the high cost of instrumentation efforts. As a step towards reducing this barrier to participation and allowing for more designs to be physically tested, we introduce a method of FT-ICR analyzer cell prototyping utilizing printed circuit boards at modest vacuum conditions. This method allows for inexpensive devices to be readily fabricated and tested over short intervals and should open the field to laboratories lacking or unable to access high performance machine shop facilities because of the required financial investment.

  1. Application of printed circuit board technology to FT-ICR MS analyzer cell construction and prototyping.

    PubMed

    Leach, Franklin E; Norheim, Randolph; Anderson, Gordon; Pasa-Tolic, Ljiljana

    2014-12-01

    Although Fourier transform ion cyclotron resonance mass spectrometry (FT-ICR MS) remains the mass spectrometry platform that provides the highest levels of performance for mass accuracy and resolving power, there is room for improvement in analyzer cell design as the ideal quadrupolar trapping potential has yet to be generated for a broadband MS experiment. To this end, analyzer cell designs have improved since the field's inception, yet few research groups participate in this area because of the high cost of instrumentation efforts. As a step towards reducing this barrier to participation and allowing for more designs to be physically tested, we introduce a method of FT-ICR analyzer cell prototyping utilizing printed circuit boards at modest vacuum conditions. This method allows for inexpensive devices to be readily fabricated and tested over short intervals and should open the field to laboratories lacking or unable to access high performance machine shop facilities because of the required financial investment.

  2. Single facet slotted Fabry-Perot laser and its application in photonic integrated circuits

    NASA Astrophysics Data System (ADS)

    Yang, Hua; Morrissey, Padraic; Lu, Qiao Y.; Cotter, William; Daunt, Chris L. L. M.; O'Callaghan, James; Guo, Wei H.; Han, Wei; Donegan, John F.; Corbett, Brian; Peters, Frank H.

    2012-11-01

    In this paper, a single facet slotted Fabry-Perot (FP) laser is demonstrated to provide tunable, single mode operation and has been monolithically integrated into a photonic integrated circuit (PIC) with semiconductor optical amplifiers and a multimode interference coupler. These lasers are designed by incorporating slots into the ridge of traditional FP cavity lasers to achieve single mode output, integrability and tunability. With the feature size of the slots around 1μm, standard photolithographic techniques can be used in the fabrication of the devices. This provides a time and cost advantage in comparison to ebeam or holographic lithography as used for defining gratings in distributed feedback (DFB) or distrusted Bragg reflector (DBR) lasers, which are typically used in PICs. The competitive integrable single mode laser also enables the PIC to be fabricated using only one epitaxial growth and one etch process as is done with standard FP lasers. This process simplicity can reduce the cost and increase the yield.

  3. New Breakdown Electric Field Calculation for SF6 High Voltage Circuit Breaker Applications

    NASA Astrophysics Data System (ADS)

    Robin-Jouan, Ph.; Yousfi, M.

    2007-12-01

    The critical electric fields of hot SF6 are calculated including both electron and ion kinetics in wide ranges of temperature and pressure, namely from 300 K up to 4000 K and 2 atmospheres up to 32 atmospheres respectively. Based on solving a multi-term electron Boltzmann equation the calculations use improved electron-gas collision cross sections for twelve SF6 dissociation products with a particular emphasis on the electron-vibrating molecule interactions. The ion kinetics is also considered and its role on the critical field becomes non negligible as the temperature is above 2000 K. These critical fields are then used in hydrodynamics simulations which correctly predict the circuit breaker behaviours observed in the case of breaking tests.

  4. Differential effects of ASIC3 and TRPV1 deletion on gastroesophageal sensation in mice.

    PubMed

    Bielefeldt, Klaus; Davis, Brian M

    2008-01-01

    Using a recently developed in vitro preparation of vagal afferent pathways, we examined the role of TRPV1 and ASIC3 on the mechano- and chemosensitive properties of gastroesophageal sensory neurons. Esophagus, stomach, and the intact vagus nerves up to the central terminations were carefully dissected from TRPV1 and ASIC3 knockout mice and wild-type controls. The organ preparation was placed in a superfusion chamber to obtain intracellular recordings from the soma of nodose neurons during luminal stimulation of esophagus and stomach. The proximal esophagus and distal stomach were separately intubated to allow perfusion and graded luminal distension. In wild-type mice, mechanosensitive neurons were activated by low distension pressures and encoded stimulus intensity over the entire range tested. Luminal acidification significantly transiently increased the resting frequency but did not alter responses to subsequent mechanical stimulation. ASIC3 and TRPV1 knockout significantly blunted responses to distension compared with wild-type controls, with deletion of TRPV1 having a more significant effect than ASIC3 deletion. Luminal acidification did not activate mechanosensory neurons in ASIC3 and TRPV1 knockout mice. Our data demonstrate a role of TRPV1 in chemo- and mechanosensation of gastroesophageal afferents. ASIC3 may contribute to acid sensation but plays a more subtle role in responses to distending stimuli. Considering the importance of acid in dyspeptic symptoms and gastroesophageal reflux, TRPV1 or ASIC3 may be an attractive target for treatment strategies in patients who do not respond to acid suppressive therapy.

  5. Tissue acidosis induces neuronal necroptosis via ASIC1a channel independent of its ionic conduction.

    PubMed

    Wang, Yi-Zhi; Wang, Jing-Jing; Huang, Yu; Liu, Fan; Zeng, Wei-Zheng; Li, Ying; Xiong, Zhi-Gang; Zhu, Michael X; Xu, Tian-Le

    2015-11-02

    Acidotoxicity is common among neurological disorders, such as ischemic stroke. Traditionally, Ca(2+) influx via homomeric acid-sensing ion channel 1a (ASIC1a) was considered to be the leading cause of ischemic acidotoxicity. Here we show that extracellular protons trigger a novel form of neuronal necroptosis via ASIC1a, but independent of its ion-conducting function. We identified serine/threonine kinase receptor interaction protein 1 (RIP1) as a critical component of this form of neuronal necroptosis. Acid stimulation recruits RIP1 to the ASIC1a C-terminus, causing RIP1 phosphorylation and subsequent neuronal death. In a mouse model of focal ischemia, middle cerebral artery occlusion causes ASIC1a-RIP1 association and RIP1 phosphorylation in affected brain areas. Deletion of the Asic1a gene significantly prevents RIP1 phosphorylation and brain damage, suggesting ASIC1a-mediated RIP1 activation has an important role in ischemic neuronal injury. Our findings indicate that extracellular protons function as a novel endogenous ligand that triggers neuronal necroptosis during ischemia via ASIC1a independent of its channel function.

  6. Tissue acidosis induces neuronal necroptosis via ASIC1a channel independent of its ionic conduction

    PubMed Central

    Wang, Yi-Zhi; Wang, Jing-Jing; Huang, Yu; Liu, Fan; Zeng, Wei-Zheng; Li, Ying; Xiong, Zhi-Gang; Zhu, Michael X; Xu, Tian-Le

    2015-01-01

    Acidotoxicity is common among neurological disorders, such as ischemic stroke. Traditionally, Ca2+ influx via homomeric acid-sensing ion channel 1a (ASIC1a) was considered to be the leading cause of ischemic acidotoxicity. Here we show that extracellular protons trigger a novel form of neuronal necroptosis via ASIC1a, but independent of its ion-conducting function. We identified serine/threonine kinase receptor interaction protein 1 (RIP1) as a critical component of this form of neuronal necroptosis. Acid stimulation recruits RIP1 to the ASIC1a C-terminus, causing RIP1 phosphorylation and subsequent neuronal death. In a mouse model of focal ischemia, middle cerebral artery occlusion causes ASIC1a-RIP1 association and RIP1 phosphorylation in affected brain areas. Deletion of the Asic1a gene significantly prevents RIP1 phosphorylation and brain damage, suggesting ASIC1a-mediated RIP1 activation has an important role in ischemic neuronal injury. Our findings indicate that extracellular protons function as a novel endogenous ligand that triggers neuronal necroptosis during ischemia via ASIC1a independent of its channel function. DOI: http://dx.doi.org/10.7554/eLife.05682.001 PMID:26523449

  7. Effect of polymer aggregation on the open circuit voltage in organic photovoltaic cells: aggregation-induced conjugated polymer gel and its application for preventing open circuit voltage drop.

    PubMed

    Kim, Bong-Gi; Jeong, Eun Jeong; Park, Hui Joon; Bilby, David; Guo, L Jay; Kim, Jinsang

    2011-03-01

    To investigate the structure-dependent aggregation behavior of conjugated polymers and the effect of aggregation on the device performance of conjugated polymer photovoltaic cells, new conjugated polymers (PVTT and CN-PVTT) having the same regioregularity but different intermolecular packing were prepared and characterized by means of UV-vis spectroscopy and atomic force microscopy (AFM). Photovoltaic devices were prepared with these polymers under different polymer-aggregate conditions. Polymer aggregation induced by thermal annealing increases the short circuit current but provides no advantage in the overall power conversion efficiency because of a decrease in the open circuit voltage. The device fabricated from a pre-aggregated polymer suspension, acquired from ultrasonic agitation of a conjugated polymer gel, showed enhanced performance because of better phase separation and reduced recombination between polymer/PCBM.

  8. A technique for evaluating the application of the pin-level stuck-at fault model to VLSI circuits

    NASA Technical Reports Server (NTRS)

    Palumbo, Daniel L.; Finelli, George B.

    1987-01-01

    Accurate fault models are required to conduct the experiments defined in validation methodologies for highly reliable fault-tolerant computers (e.g., computers with a probability of failure of 10 to the -9 for a 10-hour mission). Described is a technique by which a researcher can evaluate the capability of the pin-level stuck-at fault model to simulate true error behavior symptoms in very large scale integrated (VLSI) digital circuits. The technique is based on a statistical comparison of the error behavior resulting from faults applied at the pin-level of and internal to a VLSI circuit. As an example of an application of the technique, the error behavior of a microprocessor simulation subjected to internal stuck-at faults is compared with the error behavior which results from pin-level stuck-at faults. The error behavior is characterized by the time between errors and the duration of errors. Based on this example data, the pin-level stuck-at fault model is found to deliver less than ideal performance. However, with respect to the class of faults which cause a system crash, the pin-level, stuck-at fault model is found to provide a good modeling capability.

  9. Laboratory measurement of material electrical properties: Extending the application of lumped-circuit equivalent models to 1 GHz

    NASA Astrophysics Data System (ADS)

    Levitskaya, Tsylya M.; Sternberg, Ben K.

    2000-03-01

    For measurements of material electrical properties in a frequency range from 1 kHz to 1 GHz, we used a laboratory method based on the concept of lumped R, L, and C circuit elements. While this method has typically been used at frequencies of less than 100 MHz, we have extended its application up to 1 GHz. The complex electrical parameters of a material, such as resistivity, conductivity, and dielectric permittivity were obtained by measuring magnitude Z and phase ϕ of the sample impedance Z. We relate the material electrical parameters to either series or parallel lumped-circuit equivalent models. Depending on the frequency range, two different designs of the sample holder can be used: (1) a parallel-plate capacitor with disk electrodes, for low frequencies (from 1 kHz to 100 MHz), and (2) a coaxial capacitor, for a broad band up to higher frequencies (from 1 kHz to 1 GHz). Measured values of the sample impedance usually include errors due to effects from the sample holder and its connections to the instrument. These effects, caused by the inductance, resistance, and stray capacitance of the measuring system, are taken into account. Our measurements of several standard materials, including air, Teflon, octanol, butanol, and methanol, showed that the relative standard deviation from the mean for the dielectric permittivity (in the range where it is frequency independent) is typically less than 1%. The difference between our mean values and previously published values for these standard materials is also less than 1%.

  10. Towards Practical Application of Paper based Printed Circuits: Capillarity Effectively Enhances Conductivity of the Thermoplastic Electrically Conductive Adhesives

    PubMed Central

    Wu, Haoyi; Chiang, Sum Wai; Lin, Wei; Yang, Cheng; Li, Zhuo; Liu, Jingping; Cui, Xiaoya; Kang, Feiyu; Wong, Ching Ping

    2014-01-01

    Direct printing nanoparticle-based conductive inks onto paper substrates has encountered difficulties e.g. the nanoparticles are prone to penetrate into the pores of the paper and become partially segmented, and the necessary low-temperature-sintering process is harmful to the dimension-stability of paper. Here we prototyped the paper-based circuit substrate in combination with printed thermoplastic electrically conductive adhesives (ECA), which takes the advantage of the capillarity of paper and thus both the conductivity and mechanical robustness of the printed circuitsweredrastically improved without sintering process. For instance, the electrical resistivity of the ECA specimen on a pulp paper (6 × 10−5Ω·cm, with 50 wt% loading of Ag) was only 14% of that on PET film than that on PET film. This improvement has been found directly related to the sizing degree of paper, in agreement with the effective medium approximation simulation results in this work. The thermoplastic nature also enables excellent mechanical strength of the printed ECA to resist repeated folding. Considering the generality of the process and the wide acceptance of ECA technique in the modern electronic packages, this method may find vast applications in e.g. circuit boards, capacitive touch pads, and radio frequency identification antennas, which have been prototyped in the manuscript. PMID:25182052

  11. Towards Practical Application of Paper based Printed Circuits: Capillarity Effectively Enhances Conductivity of the Thermoplastic Electrically Conductive Adhesives

    NASA Astrophysics Data System (ADS)

    Wu, Haoyi; Chiang, Sum Wai; Lin, Wei; Yang, Cheng; Li, Zhuo; Liu, Jingping; Cui, Xiaoya; Kang, Feiyu; Wong, Ching Ping

    2014-09-01

    Direct printing nanoparticle-based conductive inks onto paper substrates has encountered difficulties e.g. the nanoparticles are prone to penetrate into the pores of the paper and become partially segmented, and the necessary low-temperature-sintering process is harmful to the dimension-stability of paper. Here we prototyped the paper-based circuit substrate in combination with printed thermoplastic electrically conductive adhesives (ECA), which takes the advantage of the capillarity of paper and thus both the conductivity and mechanical robustness of the printed circuitsweredrastically improved without sintering process. For instance, the electrical resistivity of the ECA specimen on a pulp paper (6 × 10-5Ω.cm, with 50 wt% loading of Ag) was only 14% of that on PET film than that on PET film. This improvement has been found directly related to the sizing degree of paper, in agreement with the effective medium approximation simulation results in this work. The thermoplastic nature also enables excellent mechanical strength of the printed ECA to resist repeated folding. Considering the generality of the process and the wide acceptance of ECA technique in the modern electronic packages, this method may find vast applications in e.g. circuit boards, capacitive touch pads, and radio frequency identification antennas, which have been prototyped in the manuscript.

  12. Advanced circuit breaker technology and its application in live-tank, GIS and dead-tank switchgear

    SciTech Connect

    Kirchesch, P.; Thiel, H.G.; McCabe, A.

    1995-10-01

    The arc in conventional gas-blast circuit breakers is merely a passive element to be quenched by a trans-sonic gas flow of sufficient pressure. The latter is generated mechanically by rather simple means, but is not the most suitable for present day applications. The arc in a self-blast breaker is an active element controlling the breaker action in a complicated manner from contact separation to extinction at one of the subsequent current zeros. For these reasons, the development of the 3rd Generation SF{sub 6} switchgear requires high-level research activities including arc physics, flow dynamics, material sciences and mechanics. The theoretical modeling has pointed out to be a valuable tool to approach the final design sufficiently closely already before the series of switching tests are performed. Further steps of improvement require highly sophisticated CFD in order to obtain high-resolution space-time patterns of the interesting physical quantities and to point out the influence of details of the design. The reward for these efforts is the new generation of high-technology circuit breakers designed as open terminal, GIS or dead-tank switchgear which guarantees a safe power distribution with minimum maintenance during a long service life.

  13. Implementation of a Synchronized Oscillator Circuit for Fast Sensing and Labeling of Image Objects

    PubMed Central

    Kowalski, Jacek; Strzelecki, Michal; Kim, Hyongsuk

    2011-01-01

    We present an application-specific integrated circuit (ASIC) CMOS chip that implements a synchronized oscillator cellular neural network with a matrix size of 32 × 32 for object sensing and labeling in binary images. Networks of synchronized oscillators are a recently developed tool for image segmentation and analysis. Its parallel network operation is based on a “temporary correlation” theory that attempts to describe scene recognition as if performed by the human brain. The synchronized oscillations of neuron groups attract a person’s attention if he or she is focused on a coherent stimulus (image object). For more than one perceived stimulus, these synchronized patterns switch in time between different neuron groups, thus forming temporal maps that code several features of the analyzed scene. In this paper, a new oscillator circuit based on a mathematical model is proposed, and the network architecture and chip functional blocks are presented and discussed. The proposed chip is implemented in AMIS 0.35 μm C035M-D 5M/1P technology. An application of the proposed network chip for the segmentation of insulin-producing pancreatic islets in magnetic resonance liver images is presented. PMID:22163803

  14. Implementation of a synchronized oscillator circuit for fast sensing and labeling of image objects.

    PubMed

    Kowalski, Jacek; Strzelecki, Michal; Kim, Hyongsuk

    2011-01-01

    We present an application-specific integrated circuit (ASIC) CMOS chip that implements a synchronized oscillator cellular neural network with a matrix size of 32 × 32 for object sensing and labeling in binary images. Networks of synchronized oscillators are a recently developed tool for image segmentation and analysis. Its parallel network operation is based on a "temporary correlation" theory that attempts to describe scene recognition as if performed by the human brain. The synchronized oscillations of neuron groups attract a person's attention if he or she is focused on a coherent stimulus (image object). For more than one perceived stimulus, these synchronized patterns switch in time between different neuron groups, thus forming temporal maps that code several features of the analyzed scene. In this paper, a new oscillator circuit based on a mathematical model is proposed, and the network architecture and chip functional blocks are presented and discussed. The proposed chip is implemented in AMIS 0.35 μm C035M-D 5M/1P technology. An application of the proposed network chip for the segmentation of insulin-producing pancreatic islets in magnetic resonance liver images is presented.

  15. Reconfigurable ASIC for a low level trigger system in Cherenkov Telescope Cameras

    NASA Astrophysics Data System (ADS)

    Gascon, D.; Barrio, J. A.; Blanch, O.; Boix, J.; Delagnes, E.; Delgado, C.; Freixas, L.; Guilloux, F.; Coto, R. L.; Griffiths, S.; Martínez, G.; Martínez, O.; Sanuy, A.; Tejedor, L. Á.

    2016-11-01

    A versatile and reconfigurable ASIC is presented, which implements two different concepts of low level trigger (L0) for Cherenkov telescopes: the Majority trigger (sum of discriminated inputs) and the Sum trigger concept (analogue clipped sum of inputs). Up to 7 input signals can be processed following one or both of the previous trigger concepts. Each differential pair output of the discriminator is also available as a LVDS output. Differential circuitry using local feedback allows the ASIC to achieve high speed (500 MHz) while maintaining good linearity in a 1 Vpp range. Experimental results are presented. A number of prototype camera designs of the Cherenkov Telescope Array (CTA) project will use this ASIC.

  16. Direct visualization of the trimeric structure of the ASIC1a channel, using AFM imaging

    SciTech Connect

    Carnally, Stewart M.; Dev, Harveer S.; Stewart, Andrew P.; Barrera, Nelson P.; Van Bemmelen, Miguel X.; Schild, Laurent; Henderson, Robert M.; Edwardson, J.Michael

    2008-08-08

    There has been confusion about the subunit stoichiometry of the degenerin family of ion channels. Recently, a crystal structure of acid-sensing ion channel (ASIC) 1a revealed that it assembles as a trimer. Here, we used atomic force microscopy (AFM) to image unprocessed ASIC1a bound to mica. We detected a mixture of subunit monomers, dimers and trimers. In some cases, triple-subunit clusters were clearly visible, confirming the trimeric structure of the channel, and indicating that the trimer sometimes disaggregated after adhesion to the mica surface. This AFM-based technique will now enable us to determine the subunit arrangement within heteromeric ASICs.

  17. Tailored benzoxazines as novel resin systems for printed circuit boards in high temperature e-mobility applications

    SciTech Connect

    Troeger, K. Darka, R. Khanpour Neumeyer, T. Altstaedt, V.

    2014-05-15

    This study focuses on the development of Bisphenol-F-benzoxazine resins blended with different ratios of a trifunctional epoxy resin suitable as matrix for substrates for high temperature printed circuit board (HT-PCB) applications. With the benzoxazine blends glass transition temperatures of more than 190 °C could be achieved in combination with a coefficient of thermal expansion in thickness direction (z-CTE) of less than 60 ppm/K without adding any fillers. This shows the high potential of the benzoxazine-epoxy blend systems as substrate materials for HT-PCBs. To understand the thermal behavior of the different formulations, the apparent crosslink density was calculated based on data from Dynamic Mechanical Analysis. Laminates in laboratory scale were prepared and characterized to demonstrate the transformation of the neat resin properties into real electronic substrate properties. The produced laminates exhibit a z-CTE below 40 ppm/K.

  18. Silicon/III-V laser with super-compact diffraction grating for WDM applications in electronic-photonic integrated circuits.

    PubMed

    Wang, Yadong; Wei, Yongqiang; Huang, Yingyan; Tu, Yongming; Ng, Doris; Lee, Cheewei; Zheng, Yunan; Liu, Boyang; Ho, Seng-Tiong

    2011-01-31

    We have demonstrated a heterogeneously integrated III-V-on-Silicon laser based on an ultra-large-angle super-compact grating (SCG). The SCG enables single-wavelength operation due to its high-spectral-resolution aberration-free design, enabling wavelength division multiplexing (WDM) applications in Electronic-Photonic Integrated Circuits (EPICs). The SCG based Si/III-V laser is realized by fabricating the SCG on silicon-on-insulator (SOI) substrate. Optical gain is provided by electrically pumped heterogeneous integrated III-V material on silicon. Single-wavelength lasing at 1550 nm with an output power of over 2 mW and a lasing threshold of around 150 mA were achieved.

  19. Characterization of microwave MESFET circuits under laser illumination. Applications to phased array radar, microwave communications, and digital clock control

    NASA Astrophysics Data System (ADS)

    Genco, Sheryl M.

    1994-10-01

    Optical injection of MESFET's directly affects the operating characteristics of the devices. The MESFET properties, induced by optical injection, can stabilize oscillator operating frequency, control amplifier gain, and open the door for feasible integrated microwave-optical devices. The optical injection of DC MESFET's, oscillators, and amplifiers is explored. Systems applications, including phased array radar, wave division multiplexing (WDM), and computer clock control, are provided. The main contributions of this research are analyzing the modulation properties of the locked laser subsystem, using the locked laser system to inject MESFET devices and characterizing the photo-effects in MESFET circuits, reducing the phase noise in a microwave oscillator via optical injection, and developing a theoretical description of the injection properties of oscillators that can be used to describe an injection locked laser and a microwave oscillator with a change of constants.

  20. Characterization of Microwave Mesfet Circuits Under Laser Illumination: Applications to Phased Array Radar, Microwave Communications and Digital Clock Control.

    NASA Astrophysics Data System (ADS)

    Genco, Sheryl Marie

    Optical injection of MESFETs directly affects the operating characteristics of the devices. The MESFET properties, induced by optical injection, can stabilize oscillator operating frequency, control amplifier gain and open the door for feasible integrated microwave-optical devices. The optical injection of DC MESFETs, oscillators, and amplifiers, is explored. Systems applications, including phased array radar, wave division multiplexing (WDM) and computer clock control, are provided. The main contributions of this research are analyzing the modulation properties of the locked laser subsystem, using the locked laser system to inject MESFET devices and characterizing the photo-effects in MESFET circuits, reducing the phase noise in a microwave oscillator via optical injection and developing a theoretical description of the injection properties of oscillators that can be used to describe an injection locked laser and a microwave oscillator with a change of constants.

  1. Triple implant (In,Ga)As/InP n-p-n heterojunction bipolar transistors for integrated circuit applications

    NASA Astrophysics Data System (ADS)

    Masum Choudhury, A. N. M.; Tabatabaie-Alavi, K.; Fonstad, C. G.

    1984-07-01

    For the first time (In,Ga)As/InP n-p-n heterojunction bipolar transistors (HJBT's) applicable to integrated circuits have been fabricated by triple ion implantation. The base has been formed by beryllium ion implantation and the collector by silicon ion implantation. The implants were made into an LPE-grown n-n (In,Ga)As/InP heterostructure on an n(+)-InP substrate. This inverted mode emitter-down heterojunction transistor structure demonstrates to a maximum current gain of 7 with no hysteresis in the characteristics. The ideality factors of the I(B) versus V(BE) and I(C) versus V(BE) characteristics with V(CB) = 0, are 1.25 and 1.08, respectively, indicating that the defect level in the heterojunction is low and that minority-carrier injection and diffusion is the dominant current flow mechanism.

  2. Microscale solid-state thermal diodes enabling ambient temperature thermal circuits for energy applications.

    PubMed

    Wang, Song; Cottrill, Anton L; Kunai, Yuichiro; Toland, Aubrey R; Liu, Pingwei; Wang, Wen-Jun; Strano, Michael S

    2017-05-24

    Thermal diodes, or devices that transport thermal energy asymmetrically, analogous to electrical diodes, hold promise for thermal energy harvesting and conservation, as well as for phononics or information processing. The junction of a phase change material and phase invariant material can form a thermal diode; however, there are limited constituent materials available for a given target temperature, particularly near ambient. In this work, we demonstrate that a micro and nanoporous polystyrene foam can house a paraffin-based phase change material, fused to PMMA, to produce mechanically robust, solid-state thermal diodes capable of ambient operation with Young's moduli larger than 11.5 MPa and 55.2 MPa above and below the melting transition point, respectively. Moreover, the composites show significant changes in thermal conductivity above and below the melting point of the constituent paraffin and rectification that is well-described by our previous theory and the Maxwell-Eucken model. Maximum thermal rectifications range from 1.18 to 1.34. We show that such devices perform reliably enough to operate in thermal diode bridges, dynamic thermal circuits capable of transforming oscillating temperature inputs into single polarity temperature differences - analogous to an electrical diode bridge with widespread implications for transient thermal energy harvesting and conservation. Overall, our approach yields mechanically robust, solid-state thermal diodes capable of engineering design from a mathematical model of phase change and thermal transport, with implications for energy harvesting.

  3. Application of glass-nonmetals of waste printed circuit boards to produce phenolic moulding compound.

    PubMed

    Guo, Jie; Rao, Qunli; Xu, Zhenming

    2008-05-01

    The aim of this study was to investigate the feasibility of using glass-nonmetals, a byproduct of recycling waste printed circuit boards (PCBs), to replace wood flour in production of phenolic moulding compound (PMC). Glass-nonmetals were attained by two-step crushing and corona electrostatic separating processes. Glass-nonmetals with particle size shorter than 0.07 mm were in the form of single fibers and resin powder, with the biggest portion (up to 34.6 wt%). Properties of PMC with glass-nonmetals (PMCGN) were compared with reference PMC and the national standard of PMC (PF2C3). When the adding content of glass-nonmetals was 40 wt%, PMCGN exhibited flexural strength of 82 MPa, notched impact strength of 2.4 kJ/m(2), heat deflection temperature of 175 degrees C, and dielectric strength of 4.8 MV/m, all of which met the national standard. Scanning electron microscopy (SEM) showed strong interfacial bonding between glass fibers and the phenolic resin. All the results showed that the use of glass-nonmetals as filler in PMC represented a promising method for resolving the environmental pollutions and reducing the cost of PMC, thus attaining both environmental and economic benefits.

  4. Programmable Differential Delay Circuit With Fine Delay Adjustment

    DOEpatents

    DeRyckere, John F.; Jenkins, Philip Nord; Cornett, Frank Nolan

    2002-07-09

    Circuitry that provides additional delay to early arriving signals such that all data signals arrive at a receiving latch with same path delay. The delay of a forwarded clock reference is also controlled such that the capturing clock edge will be optimally positioned near quadrature (depending on latch setup/hold requirements). The circuitry continuously adapts to data and clock path delay changes and digital filtering of phase measurements reduce errors brought on by jittering data edges. The circuitry utilizes only the minimum amount of delay necessary to achieve objective thereby limiting any unintended jitter. Particularly, this programmable differential delay circuit with fine delay adjustment is designed to allow the skew between ASICS to be minimized. This includes skew between data bits, between data bits and clocks as well as minimizing the overall skew in a channel between ASICS.

  5. Monolithic microwave integrated circuits

    NASA Astrophysics Data System (ADS)

    Pucel, R. A.

    Monolithic microwave integrated circuits (MMICs), a new microwave technology which is expected to exert a profound influence on microwave circuit designs for future military systems as well as for the commercial and consumer markets, is discussed. The book contains an historical discussion followed by a comprehensive review presenting the current status in the field. The general topics of the volume are: design considerations, materials and processing considerations, monolithic circuit applications, and CAD, measurement, and packaging techniques. All phases of MMIC technology are covered, from design to testing.

  6. Acid-sensing ion channel (ASIC) structure and function: Insights from spider, snake and sea anemone venoms.

    PubMed

    Cristofori-Armstrong, Ben; Rash, Lachlan D

    2017-04-27

    Acid-sensing ion channels (ASICs) are proton-activated cation channels that are expressed in a variety of neuronal and non-neuronal tissues. As proton-gated channels, they have been implicated in many pathophysiological conditions where pH is perturbed. Venom derived compounds represent the most potent and selective modulators of ASICs described to date, and thus have been invaluable as pharmacological tools to study ASIC structure, function, and biological roles. There are now ten ASIC modulators described from animal venoms, with those from snakes and spiders favouring ASIC1, while the sea anemones preferentially target ASIC3. Some modulators, such as the prototypical ASIC1 modulator PcTx1 have been studied in great detail, while some of the newer members of the club remain largely unstudied. Here we review the current state of knowledge on venom derived ASIC modulators, with a particular focus on their molecular interaction with ASICs, what they have taught us about channel structure, and what they might still reveal about ASIC function and pathophysiological roles. Copyright © 2017 Elsevier Ltd. All rights reserved.

  7. Local ASIC3 modulates pain and disease progression in a rat model of osteoarthritis

    PubMed Central

    2012-01-01

    Background Recent data have suggested a relationship between acute arthritic pain and acid sensing ion channel 3 (ASIC3) on primary afferent fibers innervating joints. The purpose of this study was to clarify the role of ASIC3 in a rat model of osteoarthritis (OA) which is considered a degenerative rather than an inflammatory disease. Methods We induced OA via intra-articular mono-iodoacetate (MIA) injection, and evaluated pain-related behaviors including weight bearing measured with an incapacitance tester and paw withdrawal threshold in a von Frey hair test, histology of affected knee joint, and immunohistochemistry of knee joint afferents. We also assessed the effect of ASIC3 selective peptide blocker (APETx2) on pain behavior, disease progression, and ASIC3 expression in knee joint afferents. Results OA rats showed not only weight-bearing pain but also mechanical hyperalgesia outside the knee joint (secondary hyperalgesia). ASIC3 expression in knee joint afferents was significantly upregulated approximately twofold at Day 14. Continuous intra-articular injections of APETx2 inhibited weight distribution asymmetry and secondary hyperalgesia by attenuating ASIC3 upregulation in knee joint afferents. Histology of ipsilateral knee joint showed APETx2 worked chondroprotectively if administered in the early, but not late phase. Conclusions Local ASIC3 immunoreactive nerve is strongly associated with weight-bearing pain and secondary hyperalgesia in MIA-induced OA model. APETx2 inhibited ASIC3 upregulation in knee joint afferents regardless of the time-point of administration. Furthermore, early administration of APETx2 prevented cartilage damage. APETx2 is a novel, promising drug for OA by relieving pain and inhibiting disease progression. PMID:22909215

  8. Micromachined piezoresistive inclinometer with oscillator-based integrated interface circuit and temperature readout

    NASA Astrophysics Data System (ADS)

    Dalola, Simone; Ferrari, Vittorio; Marioli, Daniele

    2012-03-01

    In this paper a dual-chip system for inclination measurement is presented. It consists of a MEMS (microelectromechanical system) piezoresistive accelerometer manufactured in silicon bulk micromachining and a CMOS (complementary metal oxide semiconductor) ASIC (application specific integrated circuit) interface designed for resistive-bridge sensors. The sensor is composed of a seismic mass symmetrically suspended by means of four flexure beams that integrate two piezoresistors each to detect the applied static acceleration, which is related to inclination with respect to the gravity vector. The ASIC interface is based on a relaxation oscillator where the frequency and the duty cycle of a rectangular-wave output signal are related to the fractional bridge imbalance and the overall bridge resistance of the sensor, respectively. The latter is a function of temperature; therefore the sensing element itself can be advantageously used to derive information for its own thermal compensation. DC current excitation of the sensor makes the configuration unaffected by wire resistances and parasitic capacitances. Therefore, a modular system results where the sensor can be placed remotely from the electronics without suffering accuracy degradation. The inclination measurement system has been characterized as a function of the applied inclination angle at different temperatures. At room temperature, the experimental sensitivity of the system results in about 148 Hz/g, which corresponds to an angular sensitivity around zero inclination angle of about 2.58 Hz deg-1. This is in agreement with finite element method simulations. The measured output fluctuations at constant temperature determine an equivalent resolution of about 0.1° at midrange. In the temperature range of 25-65 °C the system sensitivity decreases by about 10%, which is less than the variation due to the microsensor alone thanks to thermal compensation provided by the current excitation of the bridge and the positive

  9. TOFPET 2: A high-performance circuit for PET time-of-flight

    NASA Astrophysics Data System (ADS)

    Di Francesco, Agostino; Bugalho, Ricardo; Oliveira, Luis; Rivetti, Angelo; Rolo, Manuel; Silva, Jose C.; Varela, Joao

    2016-07-01

    We present a readout and digitization ASIC featuring low-noise and low-power for time-of flight (TOF) applications using SiPMs. The circuit is designed in standard CMOS 110 nm technology, has 64 independent channels and is optimized for time-of-flight measurement in Positron Emission Tomography (TOF-PET). The input amplifier is a low impedance current conveyor based on a regulated common-gate topology. Each channel has quad-buffered analogue interpolation TDCs (time binning 20 ps) and charge integration ADCs with linear response at full scale (1500 pC). The signal amplitude can also be derived from the measurement of time-over-threshold (ToT). Simulation results show that for a single photo-electron signal with charge 200 (550) fC generated by a SiPM with (320 pF) capacitance the circuit has 24 (30) dB SNR, 75 (39) ps r.m.s. resolution, and 4 (8) mW power consumption. The event rate is 600 kHz per channel, with up to 2 MHz dark counts rejection.

  10. ASIC1a Deficient Mice Show Unaltered Neurodegeneration in the Subacute MPTP Model of Parkinson Disease

    PubMed Central

    Komnig, Daniel; Imgrund, Silke; Reich, Arno; Gründer, Stefan; Falkenburger, Björn H.

    2016-01-01

    Inflammation contributes to the death of dopaminergic neurons in Parkinson disease and can be accompanied by acidification of extracellular pH, which may activate acid-sensing ion channels (ASIC). Accordingly, amiloride, a non-selective inhibitor of ASIC, was protective in an acute 1-methyl-4-phenyl-1,2,3,6-tetrahydropyridine (MPTP) mouse model of Parkinson disease. To complement these findings we determined MPTP toxicity in mice deficient for ASIC1a, the most common ASIC isoform in neurons. MPTP was applied i.p. in doses of 30 mg per kg on five consecutive days. We determined the number of dopaminergic neurons in the substantia nigra, assayed by stereological counting 14 days after the last MPTP injection, the number of Nissl positive neurons in the substantia nigra, and the concentration of catecholamines in the striatum. There was no difference between ASIC1a-deficient mice and wildtype controls. We are therefore not able to confirm that ASIC1a are involved in MPTP toxicity. The difference might relate to the subacute MPTP model we used, which more closely resembles the pathogenesis of Parkinson disease, or to further targets of amiloride. PMID:27820820

  11. Acid-sensing ion channels (ASICs): pharmacology and implication in pain.

    PubMed

    Deval, Emmanuel; Gasull, Xavier; Noël, Jacques; Salinas, Miguel; Baron, Anne; Diochot, Sylvie; Lingueglia, Eric

    2010-12-01

    Tissue acidosis is a common feature of many painful conditions. Protons are indeed among the first factors released by injured tissues, inducing a local pH fall that depolarizes peripheral free terminals of nociceptors and leads to pain. ASICs are excitatory cation channels directly gated by extracellular protons that are expressed in the nervous system. In sensory neurons, they act as "chemo-electrical" transducers and are involved in somatic and visceral nociception. Two highly specific inhibitory peptides isolated from animal venoms have considerably helped in the understanding of the physiological roles of these channels in pain. At the peripheral level, ASIC3 is important for inflammatory pain. Its expression and its activity are potentiated by several pain mediators present in the "inflammatory soup" that sensitize nociceptors. ASICs have also been involved in some aspects of mechanosensation and mechanonociception, notably in the gastrointestinal tract, but the underlying mechanisms remain to be determined. At the central level, ASIC1a is largely expressed in spinal cord neurons where it has been proposed to participate in the processing of noxious stimuli and in central sensitization. Blocking ASIC1a in the spinal cord also produces a potent analgesia in a broad range of pain conditions through activation of the opiate system. Targeting ASIC channels at different levels of the nervous system could therefore be an interesting strategy for the relief of pain.

  12. Acid-sensing ion channels (ASICs): therapeutic targets for neurological diseases and their regulation.

    PubMed

    Kweon, Hae-Jin; Suh, Byung-Chang

    2013-06-01

    Extracellular acidification occurs not only in pathological conditions such as inflammation and brain ischemia, but also in normal physiological conditions such as synaptic transmission. Acid-sensing ion channels (ASICs) can detect a broad range of physiological pH changes during pathological and synaptic cellular activities. ASICs are voltage-independent, proton-gated cation channels widely expressed throughout the central and peripheral nervous system. Activation of ASICs is involved in pain perception, synaptic plasticity, learning and memory, fear, ischemic neuronal injury, seizure termination, neuronal degeneration, and mechanosensation. Therefore, ASICs emerge as potential therapeutic targets for manipulating pain and neurological diseases. The activity of these channels can be regulated by many factors such as lactate, Zn(2+), and Phe-Met-Arg-Phe amide (FMRFamide)-like neuropeptides by interacting with the channel's large extracellular loop. ASICs are also modulated by G protein-coupled receptors such as CB1 cannabinoid receptors and 5-HT2. This review focuses on the physiological roles of ASICs and the molecular mechanisms by which these channels are regulated.

  13. ASIC1a Deficient Mice Show Unaltered Neurodegeneration in the Subacute MPTP Model of Parkinson Disease.

    PubMed

    Komnig, Daniel; Imgrund, Silke; Reich, Arno; Gründer, Stefan; Falkenburger, Björn H

    2016-01-01

    Inflammation contributes to the death of dopaminergic neurons in Parkinson disease and can be accompanied by acidification of extracellular pH, which may activate acid-sensing ion channels (ASIC). Accordingly, amiloride, a non-selective inhibitor of ASIC, was protective in an acute 1-methyl-4-phenyl-1,2,3,6-tetrahydropyridine (MPTP) mouse model of Parkinson disease. To complement these findings we determined MPTP toxicity in mice deficient for ASIC1a, the most common ASIC isoform in neurons. MPTP was applied i.p. in doses of 30 mg per kg on five consecutive days. We determined the number of dopaminergic neurons in the substantia nigra, assayed by stereological counting 14 days after the last MPTP injection, the number of Nissl positive neurons in the substantia nigra, and the concentration of catecholamines in the striatum. There was no difference between ASIC1a-deficient mice and wildtype controls. We are therefore not able to confirm that ASIC1a are involved in MPTP toxicity. The difference might relate to the subacute MPTP model we used, which more closely resembles the pathogenesis of Parkinson disease, or to further targets of amiloride.

  14. CAD-II: the second version current-mode readout ASIC for high-resolution timing measurements

    NASA Astrophysics Data System (ADS)

    Yuan, Z. X.; Deng, Z.; Wang, Y.; Liu, Y. N.

    2016-07-01

    This paper presents the second version of a fully current-mode front-end ASIC, CAD (Current Amplifier and Discriminator), for MRPC detectors for TOF applications. Several upgrades have been made in this new version, including: 1). Using differential input stages with input impedance down to 30 Ω and LVDS compatible outputs; 2). Much higher current gain and bandwidth of 4.5 A/A and 380 MHz 3). Fabricated in 0.18 μ m CMOS process instead of 0.35 μ m CMOS technology used in CAD-I. The detailed design of the ASIC will be described as well as the measurement results. The single-ended input impedance could be as low as 32 Ω and the power consumption was measured to be 15 mW per channel. Input referred RMS noise current was about 0.56 μ A. The threshold could be set as low as 4.5 μ A referred to input, corresponding to 9 fC for the typical MRPC detector signal with 2 ns width. Sub-10 ps resolution has been measured for input signal above 200 μ A.

  15. Basic Guidelines for Application of Performance Standards to Commissioning of DCS Digital Circuits

    DTIC Science & Technology

    1992-06-01

    International Telecommunications Satellite Consortium (INTELSAT), the Telecommunications Industries Association (TIA, formerly Electronic Industries ...These performance specifications are in turn based on industry standards where applicable and on military requireme-ts where necessary. Some users will...performance standards. Its advantages include (1) EFS is the industry -wide standard in the United States; (2) all modern bit error rate test

  16. Adapting Team-Based Learning for Application in the Basic Electric Circuit Theory Sequence

    ERIC Educational Resources Information Center

    O'Connell, Robert M.

    2015-01-01

    Team-based learning (TBL) is a form of student-centered active learning in which students independently study new conceptual material before it is treated in the classroom, and then subsequently spend considerable classroom time working in groups on increasingly challenging problems and applications based on that new material. TBL provides…

  17. Transient Performance Improvement Circuit (TPIC)s for DC-DC converter applications

    NASA Astrophysics Data System (ADS)

    Lim, Sungkeun

    of the slow inductor current slew rate which is determined by the input voltage, output voltage, and the inductance. The remaining inductor current in the power delivery path will charge the output capacitors and develop a voltage across the ESR. As a result, large output voltage spikes occur during load current transients. Due to their limited control bandwidth, traditional VRs can not sufficiently respond rapidly to certain load transients. As a result, a large output voltage spike can occur during load transients, hence requiring a large amount of bulk capacitance to decouple the VR from the load [2]. If the remaining inductor current is removed from the power stage or the inductor current slew rate is changed, the output voltage spikes can be clamped, allowing the output capacitance to be reduced. A new design methodology for a Transient Performance Improvement Circuit(TPIC) based on controlling the output impedance of a regulator is presented. The TPIC works in parallel with a voltage regulator (VR)'s ceramic capacitors to achieve faster voltage regulation without the need for a large bulk capacitance, and can serve as a replacement for bulk capacitors. The specific function of the TPIC is to mimic the behavior of the bulk capacitance in a traditional VRM by sinking and sourcing large currents during transients, allowing the VR to respond quickly to current transients without the need for a large bulk capacitance. This will allow fast transient response without the need for a large bulk capacitor. The main challenge in applying the TPIC is creating a design which will not interfere with VR operation. A TPIC for a 4 Switch Buck-Boost (4SBB) converter is presented which functions by con- trolling the inductor current slew rate during load current transients. By increasing the inductor current slew rate, the remaining inductor current can be removed from the 4SBB power delivery path and the output voltage spike can be clamped. A second TPIC is presented which is

  18. Sensor readout detector circuit

    DOEpatents

    Chu, Dahlon D.; Thelen, Jr., Donald C.

    1998-01-01

    A sensor readout detector circuit is disclosed that is capable of detecting sensor signals down to a few nanoamperes or less in a high (microampere) background noise level. The circuit operates at a very low standby power level and is triggerable by a sensor event signal that is above a predetermined threshold level. A plurality of sensor readout detector circuits can be formed on a substrate as an integrated circuit (IC). These circuits can operate to process data from an array of sensors in parallel, with only data from active sensors being processed for digitization and analysis. This allows the IC to operate at a low power level with a high data throughput for the active sensors. The circuit may be used with many different types of sensors, including photodetectors, capacitance sensors, chemically-sensitive sensors or combinations thereof to provide a capability for recording transient events or for recording data for a predetermined period of time following an event trigger. The sensor readout detector circuit has applications for portable or satellite-based sensor systems.

  19. Sensor readout detector circuit

    DOEpatents

    Chu, D.D.; Thelen, D.C. Jr.

    1998-08-11

    A sensor readout detector circuit is disclosed that is capable of detecting sensor signals down to a few nanoamperes or less in a high (microampere) background noise level. The circuit operates at a very low standby power level and is triggerable by a sensor event signal that is above a predetermined threshold level. A plurality of sensor readout detector circuits can be formed on a substrate as an integrated circuit (IC). These circuits can operate to process data from an array of sensors in parallel, with only data from active sensors being processed for digitization and analysis. This allows the IC to operate at a low power level with a high data throughput for the active sensors. The circuit may be used with many different types of sensors, including photodetectors, capacitance sensors, chemically-sensitive sensors or combinations thereof to provide a capability for recording transient events or for recording data for a predetermined period of time following an event trigger. The sensor readout detector circuit has applications for portable or satellite-based sensor systems. 6 figs.

  20. Bioinspired Polarization Imaging Sensors: From Circuits and Optics to Signal Processing Algorithms and Biomedical Applications

    PubMed Central

    York, Timothy; Powell, Samuel B.; Gao, Shengkui; Kahan, Lindsey; Charanya, Tauseef; Saha, Debajit; Roberts, Nicholas W.; Cronin, Thomas W.; Marshall, Justin; Achilefu, Samuel; Lake, Spencer P.; Raman, Baranidharan; Gruev, Viktor

    2015-01-01

    In this paper, we present recent work on bioinspired polarization imaging sensors and their applications in biomedicine. In particular, we focus on three different aspects of these sensors. First, we describe the electro–optical challenges in realizing a bioinspired polarization imager, and in particular, we provide a detailed description of a recent low-power complementary metal–oxide–semiconductor (CMOS) polarization imager. Second, we focus on signal processing algorithms tailored for this new class of bioinspired polarization imaging sensors, such as calibration and interpolation. Third, the emergence of these sensors has enabled rapid progress in characterizing polarization signals and environmental parameters in nature, as well as several biomedical areas, such as label-free optical neural recording, dynamic tissue strength analysis, and early diagnosis of flat cancerous lesions in a murine colorectal tumor model. We highlight results obtained from these three areas and discuss future applications for these sensors. PMID:26538682

  1. A High Power Solid State Circuit Breaker for Military Hybrid Electric Vehicle Applications

    DTIC Science & Technology

    2012-08-01

    Electric Vehicle Applications Page 2 of 8 Silicon MOSFETs, SiC MOSFETs, and IGBTs are all worth considering with regard to extremely fast...over IGBTs for minimizing the steady- state conduction loss, since the IGBT static losses become quite large at high currents and voltages. MOSFETs...high voltage, high current, and high temperature environments. COMPARISON OF SWITCH TECHNOLOGIES We first compared SiC MOSFET, Si IGBT , and Si

  2. SVGA and XGA active matrix microdisplays for head-mounted applications

    NASA Astrophysics Data System (ADS)

    Alvelda, Phillip; Bolotski, Michael; Brown, Imani L.

    2000-03-01

    The MicroDisplay Corporation's liquid crystal on silicon (LCOS) display devices are based on the union of several technologies with the extreme integration capability of conventionally fabricated CMOS substrates. The fast liquid crystal operation modes and new scalable high-performance pixel addressing architectures presented in this paper enable substantially improved color, contrast, and brightness while still satisfying the optical, packaging, and power requirements of portable applications. The entire suite of MicroDisplay's technologies was devised to create a line of mixed-signal application-specific integrated circuits (ASICs) in single-chip display systems. Mixed-signal circuits can integrate computing, memory, and communication circuitry on the same substrate as the display drivers and pixel array for a multifunctional complete system-on-a-chip. System-on-a-chip benefits also include reduced head supported weight requirements through the elimination of off-chip drive electronics.

  3. MULTIPLIER CIRCUIT

    DOEpatents

    Thomas, R.E.

    1959-01-20

    An electronic circuit is presented for automatically computing the product of two selected variables by multiplying the voltage pulses proportional to the variables. The multiplier circuit has a plurality of parallel resistors of predetermined values connected through separate gate circults between a first input and the output terminal. One voltage pulse is applied to thc flrst input while the second voltage pulse is applied to control circuitry for the respective gate circuits. Thc magnitude of the second voltage pulse selects the resistors upon which the first voltage pulse is imprcssed, whereby the resultant output voltage is proportional to the product of the input voltage pulses

  4. Serotonin facilitates peripheral pain sensitivity in a manner that depends on the nonproton ligand sensing domain of ASIC3 channel.

    PubMed

    Wang, Xiang; Li, Wei-Guang; Yu, Ye; Xiao, Xian; Cheng, Jin; Zeng, Wei-Zheng; Peng, Zhong; Xi Zhu, Michael; Xu, Tian-Le

    2013-03-06

    Tissue acidosis and inflammatory mediators play critical roles in inflammatory pain. Extracellular acidosis activates acid-sensing ion channels (ASICs), which have emerged as key sensors for extracellular protons in the central and peripheral nervous systems and play key roles in pain sensation and transmission. Additionally, inflammatory mediators, such as serotonin (5-HT), are known to enhance pain sensation. However, functional interactions among protons, inflammatory mediators, and ASICs in pain sensation are poorly understood. In the present study, we show that 5-HT, a classical pro-inflammatory mediator, specifically enhances the proton-evoked sustained, but not transient, currents mediated by homomeric ASIC3 channels and heteromeric ASIC3/1a and ASIC3/1b channels. Unexpectedly, the effect of 5-HT on ASIC3 channels does not involve activation of 5-HT receptors, but is mediated via a functional interaction between 5-HT and ASIC3 channels. We further show that the effect of 5-HT on ASIC3 channels depends on the newly identified nonproton ligand sensing domain. Finally, coapplication of 5-HT and acid significantly increased pain-related behaviors as assayed by the paw-licking test in mice, which was largely attenuated in ASIC3 knock-out mice, and inhibited by the nonselective ASIC inhibitor amiloride. Together, these data identify ASIC3 channels as an unexpected molecular target for acute actions of 5-HT in inflammatory pain sensation and reveal an important role of ASIC3 channels in regulating inflammatory pain via coincident detection of extracellular protons and inflammatory mediators.

  5. Selective Processing Techniques for Electronics and Opto-Electronic Applications: Quantum-Well Devices and Integrated Optic Circuits

    DTIC Science & Technology

    1993-02-10

    new technology is to have sufficient control of processing to *- describable by an appropriate elecromagnetic model . build useful devices. For example...3. W aveguide Modulators .................................. 7 B. Integrated Optical Device and Circuit Modeling ... ................... .. 10 C...following categories: A. Integrated Optical Devices and Technology B. Integrated Optical Device and Circuit Modeling C. Cryogenic Etching for Low

  6. Integrated coherent matter wave circuits

    DOE PAGES

    Ryu, C.; Boshier, M. G.

    2015-09-21

    An integrated coherent matter wave circuit is a single device, analogous to an integrated optical circuit, in which coherent de Broglie waves are created and then launched into waveguides where they can be switched, divided, recombined, and detected as they propagate. Applications of such circuits include guided atom interferometers, atomtronic circuits, and precisely controlled delivery of atoms. We report experiments demonstrating integrated circuits for guided coherent matter waves. The circuit elements are created with the painted potential technique, a form of time-averaged optical dipole potential in which a rapidly moving, tightly focused laser beam exerts forces on atoms through theirmore » electric polarizability. Moreover, the source of coherent matter waves is a Bose–Einstein condensate (BEC). Finally, we launch BECs into painted waveguides that guide them around bends and form switches, phase coherent beamsplitters, and closed circuits. These are the basic elements that are needed to engineer arbitrarily complex matter wave circuitry.« less

  7. MuTRiG: a mixed signal Silicon Photomultiplier readout ASIC with high timing resolution and gigabit data link

    NASA Astrophysics Data System (ADS)

    Chen, H.; Briggl, K.; Eckert, P.; Harion, T.; Munwes, Y.; Shen, W.; Stankova, V.; Schultz-Coulon, H. C.

    2017-01-01

    MuTRiG is a mixed signal Silicon Photomultiplier readout ASIC designed in UMC 180 nm CMOS technology for precise timing and high event rate applications in high energy physics experiments and medical imaging. It is dedicated to the readout of the scintillating fiber detector and the scintillating tile detector of the Mu3e experiment. The MuTRiG chip extends the excellent timing performance of the STiCv3 chip with a fast digital readout for high rate applications. The high timing performance of the fully differential SiPM readout channels and 50 ps time binning TDCs are complemented by an upgraded digital readout logic and a 1.28 Gbps LVDS serial data link. The design of the chip and the characterization results of the analog front-end, TDC and the LVDS data link are presented.

  8. Computationally efficient ASIC implementation of space-time block decoding

    NASA Astrophysics Data System (ADS)

    Cavus, Enver; Daneshrad, Babak

    2002-12-01

    In this paper, we describe a computationally efficient ASIC design that leads to a highly efficient power and area implementation of space-time block decoder compared to a direct implementation of the original algorithm. Our study analyzes alternative methods of evaluating as well as implementing the previously reported maximum likelihood algorithms (Tarokh et al. 1998) for a more favorable hardware design. In our previous study (Cavus et al. 2001), after defining some intermediate variables at the algorithm level, highly computationally efficient decoding approaches, namely sign and double-sign methods, are developed and their effectiveness are illustrated for 2x2, 8x3 and 8x4 systems using BPSK, QPSK, 8-PSK, or 16-QAM modulation. In this work, alternative architectures for the decoder implementation are investigated and an implementation having a low computation approach is proposed. The applied techniques at the higher algorithm and architectural levels lead to a substantial simplification of the hardware architecture and significantly reduced power consumption. The proposed architecture is being fabricated in TSMC 0.18 μ process.

  9. Upregulation of acid-sensing ion channel ASIC1a in spinal dorsal horn neurons contributes to inflammatory pain hypersensitivity.

    PubMed

    Duan, Bo; Wu, Long-Jun; Yu, Yao-Qing; Ding, Yu; Jing, Liang; Xu, Lin; Chen, Jun; Xu, Tian-Le

    2007-10-10

    Development of chronic pain involves alterations in peripheral nociceptors as well as elevated neuronal activity in multiple regions of the CNS. Previous pharmacological and behavioral studies suggest that peripheral acid-sensing ion channels (ASICs) contribute to pain sensation, and the expression of ASIC subunits is elevated in the rat spinal dorsal horn (SDH) in an inflammatory pain model. However, the cellular distribution and the functional consequence of increased ASIC subunit expression in the SDH remain unclear. Here, we identify the Ca2+-permeable, homomeric ASIC1a channels as the predominant ASICs in rat SDH neurons and downregulation of ASIC1a by local rat spinal infusion with specific inhibitors or antisense oligonucleotides markedly attenuated complete Freund's adjuvant (CFA)-induced thermal and mechanical hypersensitivity. Moreover, in vivo electrophysiological recording showed that the elevated ASIC1a activity is required for two forms of central sensitization: C-fiber-induced "wind-up" and CFA-induced hypersensitivity of SDH nociceptive neurons. Together, our results reveal that increased ASIC activity in SDH neurons promotes pain by central sensitization. Specific blockade of Ca2+-permeable ASIC1a channels thus may have antinociceptive effect by reducing or preventing the development of central sensitization induced by inflammation.

  10. InGaAs/InP heterojunction bipolar transistors for ultra-low power circuit applications

    SciTech Connect

    Chang, P.C.; Baca, A.G.; Hafich, M.J.; Ashby, C.I.

    1998-08-01

    For many modern day portable electronic applications, low power high speed devices have become very desirable. Very high values of f{sub T} and f{sub MAX} have been reported with InGaAs/InP heterojunction bipolar transistors (HBTs), but only under high bias and high current level operating conditions. An InGaAs/InP ultra-lowpower HBT with f{sub MAX} greater than 10 GHz operating at less than 20 {micro}A has been reported for the first time in this work. The results are obtained on a 2.5 x 5 {micro}m{sup 2} device, corresponding to less than 150 A/cm{sup 2} of current density. These are the lowest current levels at which f{sub MAX} {ge} 10 GHz has been reported.

  11. ERK-mediated NF-κB activation through ASIC1 in response to acidosis

    PubMed Central

    Chen, B; Liu, J; Ho, T-T; Ding, X; Mo, Y-Y

    2016-01-01

    Acidic microenvironment is a common feature of solid tumors. We have previously shown that neuron specific acid-sensing ion channel 1 (ASIC1) is expressed in breast cancer, and it is responsible for acidosis-induced cellular signaling through AKT, leading to nuclear factor-κB (NF-κB) activation, and cell invasion and metastasis. However, AKT is frequently activated in cancer. Thus, a key question is whether ASIC1-mediated cell signaling still takes place in the cancer cells carrying constitutively active AKT. In the present study, we show that among four prostate cancer cell lines tested, 22Rv1 cells express the highest level of phosphorylated AKT that is not impacted by acidosis. However, acidosis can still induce NF-κB activation during which extracellular signal-regulated kinase (ERK) serves as an alternative pathway for ASIC-mediated cell signaling. Inhibition of ERK by chemical inhibitors or small interfering RNAs suppresses the acidosis-induced NF-κB activity through regulation of the inhibitory subunit IκBα phosphorylation. Furthermore, suppression of ASIC1-mediated generation of reactive oxygen species (ROS) by ROS scavengers, such as glutathione or N-acetyl-cysteine causes a decrease in ERK phosphorylation and degradation of IκBα. Finally, ASIC1 is upregulated in a subset of prostate cancer cases and ASIC1 knockout by CRISPR/Cas9 significantly suppresses cell invasion, and castration resistance both in vitro and in vivo. Together, these results support the significance of ASIC1-ROS-ERK-IκBα-NF-κB axis in prostate tumorigenesis, especially in the constitutively active AKT background. PMID:27941930

  12. TRIPPING CIRCUIT

    DOEpatents

    Lees, G.W.; McCormick, E.D.

    1962-05-22

    A tripping circuit employing a magnetic amplifier for tripping a reactor in response to power level, period, or instrument failure is described. A reference winding and signal winding are wound in opposite directions on the core. Current from an ion chamber passes through both windings. If the current increases at too fast a rate, a shunt circuit bypasses one or the windings and the amplifier output reverses polarity. (AEC)

  13. Powering an Implantable Minipump with a Multi-layered Printed Circuit Coil for Drug Infusion Applications in Rodents

    PubMed Central

    Givrad, Tina K.; Maarek, Jean-Michel I.; Moore, William H.; Holschneider, Daniel P.

    2014-01-01

    We report the use of a multi-layer printed coil circuit for powering (36–94 mW) an implantable microbolus infusion pump (MIP) that can be activated remotely for use in drug infusion in nontethered, freely moving small animals. This implantable device provides a unique experimental tool with applications in the fields of animal behavior, pharmacology, physiology, and functional brain imaging. Two different designs are described: a battery-less pump usable when the animal is inside a home-cage surrounded by a primary inductive coil and a pump powered by a rechargeable battery that can be used for studies outside the homecage. The use of printed coils for powering of small devices by inductive power transfer presents significant advantages over similar approaches using hand-wound coils in terms of ease of manufacturing and uniformity of design. The high efficiency of a class-E oscillator allowed powering of the minipumps without the need for close physical contact of the primary and secondary coils, as is currently the case for most devices powered by inductive power transfer. PMID:20033778

  14. Application of Derrick Corporation's stack sizer technology for slimes reduction in 6 inch clean coal hydrocyclone circuits

    SciTech Connect

    Brodzik, P.

    2009-04-15

    The article discusses the successful introduction of Derrick Corporation's Stack Sizer technology for removing minus 200 mesh slimes from 6-inch coal hydrocyclone underflow prior to froth flotation or dewatering by screen bowl centrifuges. In 2006, the James River Coal Company selected the Stack Sizer fitted with Derrick 150 micron and 100 micron urethane screen panels for removal of the minus 100 mesh high ash clay fraction from the clean coal spiral product circuits. After this application proved successful, Derrick Corporation introduced new 75 micron urethane screen panels for use on the Stack Sizer. Evaluation of feed slurry to flotation cells and screen bowl centrifuges showed significant amounts of minus 75 micron that could potentially be removed by efficient screening technology. Removal of the minus 75 micron fraction was sought to reduce ash and moisture content of the final clean coal product. Full-scale lab tests confirmed that the Stack Sizer fitted with Derrick 75 micron urethane screen panels consistently reduced the minus 75 micron percentage in coal slurry from 6-inch clean coal hydrocyclone underflow that is approximately 15 to 20% solid by-weight and 30 to 60% minus 75 micron to a clean coal fraction that is approximately 13 to 16% minus 75 micron. As a result total ash is reduced from approximately 36 to 38% in the hydrocyclone underflow to 14 to 16% in the oversize product fraction form the Stack Sizers. 1 fig., 2 tabs., 5 photos.

  15. Powering an implantable minipump with a multi-layered printed circuit coil for drug infusion applications in rodents.

    PubMed

    Givrad, Tina K; Maarek, Jean-Michel I; Moore, William H; Holschneider, Daniel P

    2010-03-01

    We report the use of a multi-layer printed coil circuit for powering (36-94 mW) an implantable microbolus infusion pump (MIP) that can be activated remotely for use in drug infusion in nontethered, freely moving small animals. This implantable device provides a unique experimental tool with applications in the fields of animal behavior, pharmacology, physiology, and functional brain imaging. Two different designs are described: a battery-less pump usable when the animal is inside a home-cage surrounded by a primary inductive coil and a pump powered by a rechargeable battery that can be used for studies outside the home-cage. The use of printed coils for powering of small devices by inductive power transfer presents significant advantages over similar approaches using hand-wound coils in terms of ease of manufacturing and uniformity of design. The high efficiency of a class-E oscillator allowed powering of the minipumps without the need for close physical contact of the primary and secondary coils, as is currently the case for most devices powered by inductive power transfer.

  16. Retropath: automated pipeline for embedded metabolic circuits.

    PubMed

    Carbonell, Pablo; Parutto, Pierre; Baudier, Claire; Junot, Christophe; Faulon, Jean-Loup

    2014-08-15

    Metabolic circuits are a promising alternative to other conventional genetic circuits as modular parts implementing functionalities required for synthetic biology applications. To date, metabolic design has been mainly focused on production circuits. Emergent applications such as smart therapeutics, however, require circuits that enable sensing and regulation. Here, we present RetroPath, an automated pipeline for embedded metabolic circuits that explores the circuit design space from a given set of specifications and selects the best circuits to implement based on desired constraints. Synthetic biology circuits embedded in a chassis organism that are capable of controlling the production, processing, sensing, and the release of specific molecules were enumerated in the metabolic space through a standard procedure. In that way, design and implementation of applications such as therapeutic circuits that autonomously diagnose and treat disease, are enabled, and their optimization is streamlined.

  17. The RS685012 Polymorphism of ACCN2, the Human Ortholog of Murine Acid-Sensing Ion Channel (ASIC1) Gene, is Highly Represented in Patients with Panic Disorder.

    PubMed

    Gugliandolo, Agnese; Gangemi, Chiara; Caccamo, Daniela; Currò, Monica; Pandolfo, Gianluca; Quattrone, Diego; Crucitti, Manuela; Zoccali, Rocco Antonio; Bruno, Antonio; Muscatello, Maria Rosaria Anna

    2016-03-01

    Panic disorder (PD) is a disabling anxiety disorder that is characterized by unexpected, recurrent panic attacks, associated with fear of dying and worrying about possible future attacks or other behavioral changes as a consequence of the attacks. The acid-sensing ion channels (ASICs) are a family of proton-sensing channels expressed throughout the nervous system. Their activity is linked to a variety of behaviors including fear, anxiety, pain, depression, learning, and memory. The human analog of ASIC1a is the amiloride-sensitive cation channel 2 (ACCN2). Adenosine A2A receptors are suggested to play an important role in different brain circuits and pathways involved in anxiety reactions. In this work we aimed to evaluate the distribution of ACCN2 rs685012 and ADORA2A rs2298383 polymorphisms in PD patients compared with healthy subjects. We found no association between ADORA2A polymorphism and PD. Instead, the C mutated allele for ACCN2 rs685012 polymorphism was significantly more frequent in patients than in controls. On the contrary, the TT homozygous wild-type genotype and also the ACCN2 TT/ADORA2A CT diplotype were significantly more represented in controls. These results are suggestive for a role of ACCN2 rs685012 polymorphism in PD development in Caucasian people.

  18. Interface circuits for quartz crystal sensors in scanning probe microscopy applications

    NASA Astrophysics Data System (ADS)

    Jersch, Johann; Maletzky, Tobias; Fuchs, Harald

    2006-08-01

    Complementary to industrial cantilever based force sensors in scanning probe microscopy (SPM), symmetrical quartz crystal resonators (QCRs), e.g., tuning fork, trident tuning fork, and needle quartz sensors, are of great interest. A self-excitation scheme with QCR is particularly promising and allows the development of cheap SPM heads with excellent characteristics. We have developed a high performance electronic interface based on an amplitude controlled oscillator and a phase-locked loop frequency demodulator applicable for QCR with frequencies from 10 up to 10MHz. The oscillation amplitude of the sensing tip can be set from thermal noise level up to amplitudes of a tenth of nanometers. The device is small, cheap, and highly sensitive in amplitude and frequency measurements. Important features of the design are grounded QCR, parasitic capacity compensation, bridge schematic, and high temperature stability. Characteristic experimental data of the device and its operation in combination with a commercial SPM and a homemade scanning near-field optical microscope are reported. By using the 1MHz needle quartz resonator with a standard atomic force microscope tip attached, atomic scale resolution in ambient conditions is achieved. Furthermore, reproducible measurements on very soft materials (Langmuir-Blodgett layers) with a very stiff needle quartz (˜400000N/m) are possible.

  19. Scalable, efficient ASICS for the square kilometre array: From A/D conversion to central correlation

    NASA Astrophysics Data System (ADS)

    Schmatz, M. L.; Jongerius, R.; Dittmann, G.; Anghel, A.; Engbersen, T.; van Lunteren, J.; Buchmann, P.

    2014-05-01

    The Square Kilometre Array (SKA) is a future radio telescope, currently being designed by the worldwide radio-astronomy community. During the first of two construction phases, more than 250,000 antennas will be deployed, clustered in aperture-array stations. The antennas will generate 2.5 Pb/s of data, which needs to be processed in real time. For the processing stages from A/D conversion to central correlation, we propose an ASIC solution using only three chip architectures. The architecture is scalable - additional chips support additional antennas or beams - and versatile - it can relocate its receiver band within a range of a few MHz up to 4GHz. This flexibility makes it applicable to both SKA phases 1 and 2. The proposed chips implement an antenna and station processor for 289 antennas with a power consumption on the order of 600W and a correlator, including corner turn, for 911 stations on the order of 90 kW.

  20. Transmission lines implementation on HDI flex circuits for the CMS tracker upgrade

    NASA Astrophysics Data System (ADS)

    Blanchot, G.; De Canio, F.; Gadek, T.; Honma, A.; Kovacs, M.; Rose, P.; Traversi, G.

    2016-01-01

    The upgrade of the CMS tracker at the HL-LHC relies on hybrid modules built on high density interconnecting flexible circuits. They contain several flip chip readout ASICs having high speed digital ports required for configuration and data readout, implemented as customized Scalable Low-Voltage Signalling (SLVS) differential pairs. This paper presents the connectivity requirements on the CMS tracker hybrids; it compares several transmission line implementations in terms of board area, achievable impedances and expected crosstalk. The properties obtained by means of simulations are compared with measurements made on a dedicated test circuit. The different transmission line implementations are also tested using a custom 65nm SLVS driver and receiver prototype ASIC.