Simple Optoelectronic Feedback in Microwave Oscillators

NASA Technical Reports Server (NTRS)

Maleki, Lute; Iltchenko, Vladimir

2009-01-01

A proposed method of stabilizing microwave and millimeter-wave oscillators calls for the use of feedback in optoelectronic delay lines characterized by high values of the resonance quality factor (Q). The method would extend the applicability of optoelectronic feedback beyond the previously reported class of optoelectronic oscillators that comprise two-port electronic amplifiers in closed loops with high-Q feedback circuits.

Dynamic simulation of perturbation responses in a closed-loop virtual arm model.

PubMed

Du, Yu-Fan; He, Xin; Lan, Ning

2010-01-01

A closed-loop virtual arm (VA) model has been developed in SIMULINK environment by adding spinal reflex circuits and propriospinal neural networks to the open-loop VA model developed in early study [1]. An improved virtual muscle model (VM4.0) is used to speed up simulation and to generate more precise recruitment of muscle force at low levels of muscle activation. Time delays in the reflex loops are determined by their synaptic connections and afferent transmission back to the spinal cord. Reflex gains are properly selected so that closed-loop responses are stable. With the closed-loop VA model, we are developing an approach to evaluate system behaviors by dynamic simulation of perturbation responses. Joint stiffness is calculated based on simulated perturbation responses by a least-squares algorithm in MATLAB. This method of dynamic simulation will be essential for further evaluation of feedforward and reflex control of arm movement and position.

Design of a delay-locked-loop-based time-to-digital converter

NASA Astrophysics Data System (ADS)

Zhaoxin, Ma; Xuefei, Bai; Lu, Huang

2013-09-01

A time-to-digital converter (TDC) based on a reset-free and anti-harmonic delay-locked loop (DLL) circuit for wireless positioning systems is discussed and described. The DLL that generates 32-phase clocks and a cycle period detector is employed to avoid “false locking". Driven by multiphase clocks, an encoder detects pulses and outputs the phase of the clock when the pulse arrives. The proposed TDC was implemented in SMIC 0.18 μm CMOS technology, and its core area occupies 0.7 × 0.55 mm2. The reference frequency ranges from 20 to 150 MHz. An LSB resolution of 521 ps can be achieved by using a reference clock of 60 MHz and the DNL is less than ±0.75 LSB. It dissipates 31.5 mW at 1.8 V supply voltage.

Commutated automatic gain control system

NASA Technical Reports Server (NTRS)

Yost, S. R.

1982-01-01

A commutated automatic gain control (AGC) system was designed and built for a prototype Loran C receiver. The receiver uses a microcomputer to control a memory aided phase-locked loop (MAPLL). The microcomputer also controls the input/output, latitude/longitude conversion, and the recently added AGC system. The circuit designed for the AGC is described, and bench and flight test results are presented. The AGC circuit described actually samples starting at a point 40 microseconds after a zero crossing determined by the software lock pulse ultimately generated by a 30 microsecond delay and add network in the receiver front end envelope detector.

Photonic integrated circuit optical buffer for packet-switched networks.

PubMed

Burmeister, Emily F; Mack, John P; Poulsen, Henrik N; Masanović, Milan L; Stamenić, Biljana; Blumenthal, Daniel J; Bowers, John E

2009-04-13

A chip-scale optical buffer performs autonomous contention resolution for 40-byte packets with 99% packet recovery. The buffer consists of a fast, InP-based 2 x 2 optical switch and a silica-on-silicon low loss delay loop. The buffer is demonstrated in recirculating operation, but may be reconfigured in feed-forward operation for longer packet lengths. The recirculating buffer provides packet storage in integer multiples of the delay length of 12.86 ns up to 64.3 ns with 98% packet recovery. The buffer is used to resolve contention between two 40 Gb/s packet streams using multiple photonic chip optical buffers.

Radiation-hardened-by-design clocking circuits in 0.13-μm CMOS technology

NASA Astrophysics Data System (ADS)

You, Y.; Huang, D.; Chen, J.; Gong, D.; Liu, T.; Ye, J.

2014-01-01

We present a single-event-hardened phase-locked loop for frequency generation applications and a digital delay-locked loop for DDR2 memory interface applications. The PLL covers a 12.5 MHz to 500 MHz frequency range with an RMS Jitter (RJ) of 4.70-pS. The DLL operates at 267 MHz and has a phase resolution of 60-pS. Designed in 0.13-μm CMOS technology, the PLL and the DLL are hardened against SEE for charge injection of 250 fC. The PLL and the DLL consume 17 mW and 22 mW of power under a 1.5 V power supply, respectively.

Delayed coupling to feedback inhibition during a critical period for the integration of adult-born granule cells

PubMed Central

Temprana, Silvio G.; Mongiat, Lucas A.; Yang, Sung M.; Trinchero, Mariela F.; Alvarez, Diego D.; Kropff, Emilio; Giacomini, Damiana; Beltramone, Natalia; Lanuza, Guillermo M.; Schinder, Alejandro F.

2014-01-01

SUMMARY Developing granule cells (GCs) of the adult dentate gyrus undergo a critical period of enhanced activity and synaptic plasticity before becoming mature. The impact of developing GCs on the activity of preexisting dentate circuits remains unknown. Here we combine optogenetics, acute slice electrophysiology, and in vivo chemogenetics to activate GCs at different stages of maturation to study the recruitment of local target networks. We show that immature (four-week-old) GCs can efficiently drive distal CA3 targets, but poorly activate proximal interneurons responsible for feedback inhibition (FBI). As new GCs transition towards maturity, they reliably recruit GABAergic feedback loops that restrict spiking of neighbor GCs, a mechanism that would promote sparse coding. Such inhibitory loop impinges only weakly in new cohorts of young GCs. A computational model reveals that the delayed coupling of new GCs to FBI could be crucial to achieve a fine-grain representation of novel inputs in the dentate gyrus. PMID:25533485

Delayed coupling to feedback inhibition during a critical period for the integration of adult-born granule cells.

PubMed

Temprana, Silvio G; Mongiat, Lucas A; Yang, Sung M; Trinchero, Mariela F; Alvarez, Diego D; Kropff, Emilio; Giacomini, Damiana; Beltramone, Natalia; Lanuza, Guillermo M; Schinder, Alejandro F

2015-01-07

Developing granule cells (GCs) of the adult dentate gyrus undergo a critical period of enhanced activity and synaptic plasticity before becoming mature. The impact of developing GCs on the activity of preexisting dentate circuits remains unknown. Here we combine optogenetics, acute slice electrophysiology, and in vivo chemogenetics to activate GCs at different stages of maturation to study the recruitment of local target networks. We show that immature (4-week-old) GCs can efficiently drive distal CA3 targets but poorly activate proximal interneurons responsible for feedback inhibition (FBI). As new GCs transition toward maturity, they reliably recruit GABAergic feedback loops that restrict spiking of neighbor GCs, a mechanism that would promote sparse coding. Such inhibitory loop impinges only weakly in new cohorts of young GCs. A computational model reveals that the delayed coupling of new GCs to FBI could be crucial to achieve a fine-grain representation of novel inputs in the dentate gyrus. Copyright © 2015 Elsevier Inc. All rights reserved.

Low power digitally controlled oscillator designs with a novel 3-transistor XNOR gate

NASA Astrophysics Data System (ADS)

Kumar, Manoj; Arya, Sandeep K.; Pandey, Sujata

2012-03-01

Digital controlled oscillators (DCOs) are the core of all digital phase locked loop (ADPLL) circuits. Here, DCO structures with reduced hardware and power consumption having full digital control have been proposed. Three different DCO architectures have been proposed based on ring based topology. Three, four and five bit controlled DCO with NMOS, PMOS and NMOS & PMOS transistor switching networks are presented. A three-transistor XNOR gate has been used as the inverter which is used as the delay cell. Delay has been controlled digitally with a switch network of NMOS and PMOS transistors. The three bit DCO with one NMOS network shows frequency variations of 1.6141-1.8790 GHz with power consumption variations 251.9224-276.8591 μW. The four bit DCO with one NMOS network shows frequency variation of 1.6229-1.8868 GHz with varying power consumption of 251.9225-278.0740 μW. A six bit DCO with one NMOS switching network gave an output frequency of 1.7237-1.8962 GHz with power consumption of 251.928-278.998 μW. Output frequency and power consumption results for 4 & 6 bit DCO circuits with one PMOS and NMOS & PMOS switching network have also been presented. The phase noise parameter with an offset frequency of 1 MHz has also been reported for the proposed circuits. Comparisons with earlier reported circuits have been made and the present approach shows advantages over previous circuits.

Phase-lock-loop application for fiber optic receiver

NASA Astrophysics Data System (ADS)

Ruggles, Stephen L.; Wills, Robert W.

1991-02-01

Phase-locked loop circuits are frequently employed in communication systems. In recent years, digital phase-locked loop circuits were utilized in optical communications systems. In an optical transceiver system, the digital phase-locked loop circuit is connected to the output of the receiver to extract a clock signal from the received coded data (NRZ, Bi-Phase, or Manchester). The clock signal is then used to reconstruct or recover the original data from the coded data. A theoretical approach to the design of a digital phase-locked loop circuit operation at 1 and 50 MHz is described. Hardware implementation of a breadboard design to function at 1 MHz and a printed-circuit board designed to function at 50 MHz were assembled using emitter coupled logic (ECL) to verify experimentally the theoretical design.

Phase-lock-loop application for fiber optic receiver

NASA Technical Reports Server (NTRS)

Ruggles, Stephen L.; Wills, Robert W.

1991-01-01

Phase-locked loop circuits are frequently employed in communication systems. In recent years, digital phase-locked loop circuits were utilized in optical communications systems. In an optical transceiver system, the digital phase-locked loop circuit is connected to the output of the receiver to extract a clock signal from the received coded data (NRZ, Bi-Phase, or Manchester). The clock signal is then used to reconstruct or recover the original data from the coded data. A theoretical approach to the design of a digital phase-locked loop circuit operation at 1 and 50 MHz is described. Hardware implementation of a breadboard design to function at 1 MHz and a printed-circuit board designed to function at 50 MHz were assembled using emitter coupled logic (ECL) to verify experimentally the theoretical design.

High-Speed, High-Resolution Time-to-Digital Conversion

NASA Technical Reports Server (NTRS)

Katz, Richard; Kleyner, Igor; Garcia, Rafael

2013-01-01

This innovation is a series of time-tag pulses from a photomultiplier tube, featuring short time interval between pulses (e.g., 2.5 ns). Using the previous art, dead time between pulses is too long, or too much hardware is required, including a very-high-speed demultiplexer. A faster method is needed. The goal of this work is to provide circuits to time-tag pulses that arrive at a high rate using the hardwired logic in an FPGA - specifically the carry chain - to create what is (in effect) an analog delay line. High-speed pulses travel down the chain in a "wave." For instance, a pulse train has been demonstrated from a 1- GHz source reliably traveling down the carry chain. The size of the carry chain is over 10 ns in the time domain. Thus, multiple pulses will travel down the carry chain in a wave simultaneously. A register clocked by a low-skew clock takes a "snapshot" of the wave. Relatively simple logic can extract the pulses from the snapshot picture by detecting the transitions between logic states. The propagation delay of CMOS (complementary metal oxide semiconductor) logic circuits will differ and/or change as a result of temperature, voltage, age, radiation, and manufacturing variances. The time-to-digital conversion circuits can be calibrated with test signals, or the changes can be nulled by a separate on-die calibration channel, in a closed loop circuit.

Practical applications of current loop signal conditioning

NASA Astrophysics Data System (ADS)

Anderson, Karl F.

1994-10-01

This paper describes a variety of practical application circuits based on the current loop signal conditioning paradigm. Equations defining the circuit response are also provided. The constant current loop is a fundamental signal conditioning circuit concept that can be implemented in a variety of configurations for resistance-based transducers, such as strain gages and resistance temperature devices. The circuit features signal conditioning outputs which are unaffected by extremely large variations in lead wire resistance, direct current frequency response, and inherent linearity with respect to resistance change. Sensitivity of this circuit is double that of a Wheatstone bridge circuit. Electrical output is zero for resistance change equals zero. The same excitation and output sense wires can serve multiple transducers. More application arrangements are possible with constant current loop signal conditioning than with the Wheatstone bridge.

Current loop signal conditioning: Practical applications

NASA Technical Reports Server (NTRS)

Anderson, Karl F.

1995-01-01

This paper describes a variety of practical application circuits based on the current loop signal conditioning paradigm. Equations defining the circuit response are also provided. The constant current loop is a fundamental signal conditioning circuit concept that can be implemented in a variety of configurations for resistance-based transducers, such as strain gages and resistance temperature detectors. The circuit features signal conditioning outputs which are unaffected by extremely large variations in lead wire resistance, direct current frequency response, and inherent linearity with respect to resistance change. Sensitivity of this circuit is double that of a Wheatstone bridge circuit. Electrical output is zero for resistance change equals zero. The same excitation and output sense wires can serve multiple transducers. More application arrangements are possible with constant current loop signal conditioning than with the Wheatstone bridge.

Accurate time delay technology in simulated test for high precision laser range finder

NASA Astrophysics Data System (ADS)

Chen, Zhibin; Xiao, Wenjian; Wang, Weiming; Xue, Mingxi

2015-10-01

With the continuous development of technology, the ranging accuracy of pulsed laser range finder (LRF) is higher and higher, so the maintenance demand of LRF is also rising. According to the dominant ideology of "time analog spatial distance" in simulated test for pulsed range finder, the key of distance simulation precision lies in the adjustable time delay. By analyzing and comparing the advantages and disadvantages of fiber and circuit delay, a method was proposed to improve the accuracy of the circuit delay without increasing the count frequency of the circuit. A high precision controllable delay circuit was designed by combining the internal delay circuit and external delay circuit which could compensate the delay error in real time. And then the circuit delay accuracy could be increased. The accuracy of the novel circuit delay methods proposed in this paper was actually measured by a high sampling rate oscilloscope actual measurement. The measurement result shows that the accuracy of the distance simulated by the circuit delay is increased from +/- 0.75m up to +/- 0.15m. The accuracy of the simulated distance is greatly improved in simulated test for high precision pulsed range finder.

Frequency control circuit for all-digital phase-lock loops

NASA Technical Reports Server (NTRS)

Anderson, T. O.

1973-01-01

Phase-lock loop references all its operations to fixed high-frequency service clock operating at highest speed which digital circuits permit. Wide-range control circuit provides linear control of frequency of reference signal. It requires only two counters in combination with control circuit consisting only of flip-flop and gate.

A fast-locking PLL with all-digital locked-aid circuit

NASA Astrophysics Data System (ADS)

Kao, Shao-Ku; Hsieh, Fu-Jen

2013-02-01

In this article, a fast-locking phase-locked loop (PLL) with an all-digital locked-aid circuit is proposed and analysed. The proposed topology is based on two tuning loops: frequency and phase detections. A frequency detection loop is used to accelerate frequency locking time, and a phase detection loop is used to adjust fine phase errors between the reference and feedback clocks. The proposed PLL circuit is designed based on the 0.35 µm CMOS process with a 3.3 V supply voltage. Experimental results show that the locking time of the proposed PLL achieves a 87.5% reduction from that of a PLL without the locked-aid circuit.

Feedback loop compensates for rectifier nonlinearity

NASA Technical Reports Server (NTRS)

1966-01-01

Signal processing circuit with two negative feedback loops rectifies two sinusoidal signals which are 180 degrees out of phase and produces a single full-wave rectified output signal. Each feedback loop incorporates a feedback rectifier to compensate for the nonlinearity of the circuit.

Precise delay measurement through combinatorial logic

NASA Technical Reports Server (NTRS)

Burke, Gary R. (Inventor); Chen, Yuan (Inventor); Sheldon, Douglas J. (Inventor)

2010-01-01

A high resolution circuit and method for facilitating precise measurement of on-chip delays for FPGAs for reliability studies. The circuit embeds a pulse generator on an FPGA chip having one or more groups of LUTS (the "LUT delay chain"), also on-chip. The circuit also embeds a pulse width measurement circuit on-chip, and measures the duration of the generated pulse through the delay chain. The pulse width of the output pulse represents the delay through the delay chain without any I/O delay. The pulse width measurement circuit uses an additional asynchronous clock autonomous from the main clock and the FPGA propagation delay can be displayed on a hex display continuously for testing purposes.

A Method for Measuring the Effective Throughput Time Delay in Simulated Displays Involving Manual Control

NASA Technical Reports Server (NTRS)

Jewell, W. F.; Clement, W. F.

1984-01-01

The advent and widespread use of the computer-generated image (CGI) device to simulate visual cues has a mixed impact on the realism and fidelity of flight simulators. On the plus side, CGIs provide greater flexibility in scene content than terrain boards and closed circuit television based visual systems, and they have the potential for a greater field of view. However, on the minus side, CGIs introduce into the visual simulation relatively long time delays. In many CGIs, this delay is as much as 200 ms, which is comparable to the inherent delay time of the pilot. Because most GCIs use multiloop processing and smoothing algorithms and are linked to a multiloop host computer, it is seldom possible to identify a unique throughput time delay, and it is therefore difficult to quantify the performance of the closed loop pilot simulator system relative to the real world task. A method to address these issues using the critical task tester is described. Some empirical results from applying the method are presented, and a novel technique for improving the performance of GCIs is discussed.

Heart-Rate and Breath-Rate Monitor

NASA Technical Reports Server (NTRS)

Cooper, T. G.

1983-01-01

Circuit requiring only four integrated circuits (IC's) measures both heart rate and breath rate. Phase-locked loops lock on heart-rate and respiration-rate input signals. Each loop IC contains two phase comparators. Positive-edge-triggered circuit used in making monitors insensitive to dutycycle variations.

Hidden attractors in dynamical models of phase-locked loop circuits: Limitations of simulation in MATLAB and SPICE

NASA Astrophysics Data System (ADS)

Kuznetsov, N. V.; Leonov, G. A.; Yuldashev, M. V.; Yuldashev, R. V.

2017-10-01

During recent years it has been shown that hidden oscillations, whose basin of attraction does not overlap with small neighborhoods of equilibria, may significantly complicate simulation of dynamical models, lead to unreliable results and wrong conclusions, and cause serious damage in drilling systems, aircrafts control systems, electromechanical systems, and other applications. This article provides a survey of various phase-locked loop based circuits (used in satellite navigation systems, optical, and digital communication), where such difficulties take place in MATLAB and SPICE. Considered examples can be used for testing other phase-locked loop based circuits and simulation tools, and motivate the development and application of rigorous analytical methods for the global analysis of phase-locked loop based circuits.

Survey Of High Speed Test Techniques

NASA Astrophysics Data System (ADS)

Gheewala, Tushar

1988-02-01

The emerging technologies for the characterization and production testing of high-speed devices and integrated circuits are reviewed. The continuing progress in the field of semiconductor technologies will, in the near future, demand test techniques to test 10ps to lOOps gate delays, 10 GHz to 100 GHz analog functions and 10,000 to 100,000 gates on a single chip. Clearly, no single test technique would provide a cost-effective answer to all the above demands. A divide-and-conquer approach based on a judicial selection of parametric, functional and high-speed tests will be required. In addition, design-for-test methods need to be pursued which will include on-chip test electronics as well as circuit techniques that minimize the circuit performance sensitivity to allowable process variations. The electron and laser beam based test technologies look very promising and may provide the much needed solutions to not only the high-speed test problem but also to the need for high levels of fault coverage during functional testing.

Apparatus and Method for Compensating for Process, Voltage, and Temperature Variation of the Time Delay of a Digital Delay Line

NASA Technical Reports Server (NTRS)

Seefeldt, James (Inventor); Feng, Xiaoxin (Inventor); Roper, Weston (Inventor)

2013-01-01

A process, voltage, and temperature (PVT) compensation circuit and a method of continuously generating a delay measure are provided. The compensation circuit includes two delay lines, each delay line providing a delay output. The two delay lines may each include a number of delay elements, which in turn may include one or more current-starved inverters. The number of delay lines may differ between the two delay lines. The delay outputs are provided to a combining circuit that determines an offset pulse based on the two delay outputs and then averages the voltage of the offset pulse to determine a delay measure. The delay measure may be one or more currents or voltages indicating an amount of PVT compensation to apply to input or output signals of an application circuit, such as a memory-bus driver, dynamic random access memory (DRAM), a synchronous DRAM, a processor or other clocked circuit.

Circuit Regulates Speed Of dc Motor

NASA Technical Reports Server (NTRS)

Weaver, Charles; Padden, Robin; Brown, Floyd A., Jr.

1990-01-01

Driving circuit regulates speed of small dc permanent-magnet motor in tape recorder. Two nested feedback loops maintain speed within 1 percent of constant value. Inner loop provides coarse regulation, while outer loop removes most of variation in speed that remains in the presence of regulation by the inner loop. Compares speed of motor with commanded speed and adjusts current supplied to motor accordingly.

Delay test generation for synchronous sequential circuits

NASA Astrophysics Data System (ADS)

Devadas, Srinivas

1989-05-01

We address the problem of generating tests for delay faults in non-scan synchronous sequential circuits. Delay test generation for sequential circuits is a considerably more difficult problem than delay testing of combinational circuits and has received much less attention. In this paper, we present a method for generating test sequences to detect delay faults in sequential circuits using the stuck-at fault sequential test generator STALLION. The method is complete in that it will generate a delay test sequence for a targeted fault given sufficient CPU time, if such a sequence exists. We term faults for which no delay test sequence exists, under out test methodology, sequentially delay redundant. We describe means of eliminating sequential delay redundancies in logic circuits. We present a partial-scan methodology for enhancing the testability of difficult-to-test of untestable sequential circuits, wherein a small number of flip-flops are selected and made controllable/observable. The selection process guarantees the elimination of all sequential delay redundancies. We show that an intimate relationship exists between state assignment and delay testability of a sequential machine. We describe a state assignment algorithm for the synthesis of sequential machines with maximal delay fault testability. Preliminary experimental results using the test generation, partial-scan and synthesis algorithm are presented.

Integrated mixed signal control IC for 500-kHz switching frequency buck regulator

NASA Astrophysics Data System (ADS)

Chen, Keng; Zhang, Hong

2015-12-01

The main purpose for this work is to study the challenges of designing a digital buck regulator using pipelined analog to digital converter (ADC). Although pipelined ADC can achieve high sampling speed, it will introduce additional phase lag to the buck circuit. Along with the latency brought by processing time of additional digital circuits, as well as the time delay associated with the switching frequency, the closed loop will be unstable; moreover, raw ADC outputs have low signal-to-noise ratio, which usually need back-end calibration. In order to compensate these phase lag and make control loop unconditional stable, as well as boost up signal-to-noise ratio of the ADC block with cost-efficient design, a finite impulse response filter followed by digital proportional-integral-derivative blocks were designed. All these digital function blocks were optimised with processing speed. In the system simulation, it can be found that this controller achieved output regulation within 10% of nominal 5 V output voltage under 1 A/µs load transient condition; moreover, with the soft-start method, there is no turn-on overshooting. The die size of this controller is controlled within 3 mm2 by using 180 nm CMOS technology.

PRECISION TIME-DELAY CIRCUIT

DOEpatents

Creveling, R.

1959-03-17

A tine-delay circuit which produces a delay time in d. The circuit a capacitor, an te back resistance, connected serially with the anode of the diode going to ground. At the start of the time delay a negative stepfunction is applied to the series circuit and initiates a half-cycle transient oscillatory voltage terminated by a transient oscillatory voltage of substantially higher frequency. The output of the delay circuit is taken at the junction of the inductor and diode where a sudden voltage rise appears after the initiation of the higher frequency transient oscillations.

Design of optical axis jitter control system for multi beam lasers based on FPGA

NASA Astrophysics Data System (ADS)

Ou, Long; Li, Guohui; Xie, Chuanlin; Zhou, Zhiqiang

2018-02-01

A design of optical axis closed-loop control system for multi beam lasers coherent combining based on FPGA was introduced. The system uses piezoelectric ceramics Fast Steering Mirrors (FSM) as actuator, the Fairfield spot detection of multi beam lasers by the high speed CMOS camera for optical detecting, a control system based on FPGA for real-time optical axis jitter suppression. The algorithm for optical axis centroid detecting and PID of anti-Integral saturation were realized by FPGA. Optimize the structure of logic circuit by reuse resource and pipeline, as a result of reducing logic resource but reduced the delay time, and the closed-loop bandwidth increases to 100Hz. The jitter of laser less than 40Hz was reduced 40dB. The cost of the system is low but it works stably.

Neuroelectric Tuning of Cortical Oscillations by Apical Dendrites in Loop Circuits

PubMed Central

LaBerge, David; Kasevich, Ray S.

2017-01-01

Bundles of relatively long apical dendrites dominate the neurons that make up the thickness of the cerebral cortex. It is proposed that a major function of the apical dendrite is to produce sustained oscillations at a specific frequency that can serve as a common timing unit for the processing of information in circuits connected to that apical dendrite. Many layer 5 and 6 pyramidal neurons are connected to thalamic neurons in loop circuits. A model of the apical dendrites of these pyramidal neurons has been used to simulate the electric activity of the apical dendrite. The results of that simulation demonstrated that subthreshold electric pulses in these apical dendrites can be tuned to specific frequencies and also can be fine-tuned to narrow bandwidths of less than one Hertz (1 Hz). Synchronous pulse outputs from the circuit loops containing apical dendrites can tune subthreshold membrane oscillations of neurons they contact. When the pulse outputs are finely tuned, they function as a local “clock,” which enables the contacted neurons to synchronously communicate with each other. Thus, a shared tuning frequency can select neurons for membership in a circuit. Unlike layer 6 apical dendrites, layer 5 apical dendrites can produce burst firing in many of their neurons, which increases the amplitude of signals in the neurons they contact. This difference in amplitude of signals serves as basis of selecting a sub-circuit for specialized processing (e.g., sustained attention) within the typically larger layer 6-based circuit. After examining the sustaining of oscillations in loop circuits and the processing of spikes in network circuits, we propose that cortical functioning can be globally viewed as two systems: a loop system and a network system. The loop system oscillations influence the network system’s timing and amplitude of pulse signals, both of which can select circuits that are momentarily dominant in cortical activity. PMID:28659768

Neuroelectric Tuning of Cortical Oscillations by Apical Dendrites in Loop Circuits.

PubMed

LaBerge, David; Kasevich, Ray S

2017-01-01

Bundles of relatively long apical dendrites dominate the neurons that make up the thickness of the cerebral cortex. It is proposed that a major function of the apical dendrite is to produce sustained oscillations at a specific frequency that can serve as a common timing unit for the processing of information in circuits connected to that apical dendrite. Many layer 5 and 6 pyramidal neurons are connected to thalamic neurons in loop circuits. A model of the apical dendrites of these pyramidal neurons has been used to simulate the electric activity of the apical dendrite. The results of that simulation demonstrated that subthreshold electric pulses in these apical dendrites can be tuned to specific frequencies and also can be fine-tuned to narrow bandwidths of less than one Hertz (1 Hz). Synchronous pulse outputs from the circuit loops containing apical dendrites can tune subthreshold membrane oscillations of neurons they contact. When the pulse outputs are finely tuned, they function as a local "clock," which enables the contacted neurons to synchronously communicate with each other. Thus, a shared tuning frequency can select neurons for membership in a circuit. Unlike layer 6 apical dendrites, layer 5 apical dendrites can produce burst firing in many of their neurons, which increases the amplitude of signals in the neurons they contact. This difference in amplitude of signals serves as basis of selecting a sub-circuit for specialized processing (e.g., sustained attention) within the typically larger layer 6-based circuit. After examining the sustaining of oscillations in loop circuits and the processing of spikes in network circuits, we propose that cortical functioning can be globally viewed as two systems: a loop system and a network system. The loop system oscillations influence the network system's timing and amplitude of pulse signals, both of which can select circuits that are momentarily dominant in cortical activity.

Performance constraints and compensation for teleoperation with delay

NASA Technical Reports Server (NTRS)

Mclaughlin, J. S.; Staunton, B. D.

1989-01-01

A classical control perspective is used to characterize performance constraints and evaluate compensation techniques for teleoperation with delay. Use of control concepts such as open and closed loop performance, stability, and bandwidth yield insight to the delay problem. Teleoperator performance constraints are viewed as an open loop time delay lag and as a delay-induced closed loop bandwidth constraint. These constraints are illustrated with a simple analytical tracking example which is corroborated by a real time, 'man-in-the-loop' tracking experiment. The experiment also provides insight to those controller characteristics which are unique to a human operator. Predictive displays and feedforward commands are shown to provide open loop compensation for delay lag. Low pass filtering of telemetry or feedback signals is interpreted as closed loop compensation used to maintain a sufficiently low bandwidth for stability. A new closed loop compensation approach is proposed that uses a reactive (or force feedback) hand controller to restrict system bandwidth by impeding operator inputs.

Investigation of the Frequency Shift of a SAD Circuit Loop and the Internal Micro-Cantilever in a Gas Sensor

PubMed Central

Guan, Liu; Zhao, Jiahao; Yu, Shijie; Li, Peng; You, Zheng

2010-01-01

Micro-cantilever sensors for mass detection using resonance frequency have attracted considerable attention over the last decade in the field of gas sensing. For such a sensing system, an oscillator circuit loop is conventionally used to actuate the micro-cantilever, and trace the frequency shifts. In this paper, gas experiments are introduced to investigate the mechanical resonance frequency shifts of the micro-cantilever within the circuit loop(mechanical resonance frequency, MRF) and resonating frequency shifts of the electric signal in the oscillator circuit (system working frequency, SWF). A silicon beam with a piezoelectric zinc oxide layer is employed in the experiment, and a Self-Actuating-Detecting (SAD) circuit loop is built to drive the micro-cantilever and to follow the frequency shifts. The differences between the two resonating frequencies and their shifts are discussed and analyzed, and a coefficient α related to the two frequency shifts is confirmed. PMID:22163588

Design of a delayed XOR phase detector for an optical phase-locked loop toward high-speed coherent laser communication.

PubMed

Liu, Yang; Tong, Shoufeng; Chang, Shuai; Song, Yansong; Dong, Yan; Zhao, Xin; An, Zhe; Yu, Fuwan

2018-05-10

Optical phase-locked loops are an effective detection method in high-speed and long-distance laser communication. Although this method can detect weak signal light and maintain a small bit error rate, it is difficult to perform because identifying the phase difference between the signal light and the local oscillator accurately has always been a technical challenge. Thus, a series of studies is conducted to address this issue. First, a delayed exclusive or gate (XOR) phase detector with multi-level loop compound control is proposed. Then, a 50 ps delay line and relative signal-to-noise ratio control at 15 dB are produced through theoretical derivation and simulation. Thereafter, a phase discrimination module is designed on a 15  cm×5  cm printed circuit board board. Finally, the experiment platform is built for verification. Experimental results show that the phase discrimination range is -1.1 to 1.1 GHz, and the gain is 0.82 mV/MHz. Three times the standard deviation, that is, 0.064 V, is observed between the test and theoretical values. The accuracy of phase detection is better than 0.07 V, which meets the design standards. A coherent carrier recovery test system is established. The delayed XOR gate has good performance in this system. When the communication rate is 5 Gbps, the system realizes a bit error rate of 1.55×10 -8 when the optical power of the signal is -40.4  dBm. When the communication rate is increased to 10 Gbps, the detection sensitivity drops to -39.5  dBm and still shows good performance in high-speed communications. This work provides a reference for future high-speed coherent homodyne detection in space. Ideas for the next phase of this study are presented at the end of this paper.

Sensitivity and Switching Delay in Trigger Circuits; SENSIBILITA E RITARDO ENI CIRCUITI A SCATTO

DOE Office of Scientific and Technical Information (OSTI.GOV)

De Lotto, I.; Stanchi, L.

The problem of regeneration in trigger circuits is studied, particularly in relation to switching delay and switching time. The factors that affect the speed, such as the threshold as a function of the input signal duration, are examined. The sensitivity of the circuit is also discussed. The characteristics of the dipole equivalent to a trigger circuit are determined, and the switching delay and switching rise time are examined using considerable simplifications (circuits with constant parameters) and graphical methods. For the particular case of a transistor circuit, the equation of the equivalent circuit is derived taking into account the nonlinearity ofmore » the parameters. This equation is processed by means of an analog computer. Using experimental data, the circuits are classified according to their sensitivity and the switching delay. A merit figure is obtained for synthetically evaluating different circuits and optimizing circuit sensitivity and speed. (auth)« less

Dual-circuit, multiple-effect refrigeration system and method

DOEpatents

DeVault, Robert C.

1995-01-01

A dual circuit absorption refrigeration system comprising a high temperature single-effect refrigeration loop and a lower temperature double-effect refrigeration loop separate from one another and provided with a double-condenser coupling therebetween. The high temperature condenser of the single-effect refrigeration loop is double coupled to both of the generators in the double-effect refrigeration loop to improve internal heat recovery and a heat and mass transfer additive such as 2-ethyl-1-hexanol is used in the lower temperature double-effect refrigeration loop to improve the performance of the absorber in the double-effect refrigeration loop.

Behaviour of fractional loop delay zero crossing digital phase locked loop (FR-ZCDPLL)

NASA Astrophysics Data System (ADS)

Nasir, Qassim

2018-01-01

This article analyses the performance of the first-order zero crossing digital phase locked loops (FR-ZCDPLL) when fractional loop delay is added to loop. The non-linear dynamics of the loop is presented, analysed and examined through bifurcation behaviour. Numerical simulation of the loop is conducted to proof the mathematical analysis of the loop operation. The results of the loop simulation show that the proposed FR-ZCDPLL has enhanced the performance compared to the conventional zero crossing DPLL in terms of wider lock range, captured range and stable operation region. In addition, extensive experimental simulation was conducted to find the optimum loop parameters for different loop environmental conditions. The addition of the fractional loop delay network in the conventional loop also reduces the phase jitter and its variance especially when the signal-to-noise ratio is low.

Open-loop digital frequency multiplier

NASA Technical Reports Server (NTRS)

Moore, R. C.

1977-01-01

Monostable multivibrator is implemented by using digital integrated circuits where multiplier constant is too large for conventional phase-locked-loop integrated circuit. A 400 Hz clock is generated by divide-by-N counter from 1 Hz timing reference.

Inverse spin Hall effect in a closed loop circuit

DOE Office of Scientific and Technical Information (OSTI.GOV)

Omori, Y.; Auvray, F.; Wakamura, T.

We present measurements of inverse spin Hall effects (ISHEs), in which the conversion of a spin current into a charge current via the ISHE is detected not as a voltage in a standard open circuit but directly as the charge current generated in a closed loop. The method is applied to the ISHEs of Bi-doped Cu and Pt. The derived expression of ISHE for the loop structure can relate the charge current flowing into the loop to the spin Hall angle of the SHE material and the resistance of the loop.

Electronic circuits

NASA Technical Reports Server (NTRS)

1976-01-01

Twenty-nine circuits and circuit techniques developed for communications and instrumentation technology are described. Topics include pulse-code modulation, phase-locked loops, data coding, data recording, detection circuits, logic circuits, oscillators, and amplifiers.

Design and verification of large-moment transmitter loops for geophysical applications

NASA Astrophysics Data System (ADS)

Sternberg, Ben K.; Dvorak, Steven L.; Feng, Wanjie

2017-01-01

In this paper we discuss the modeling, design and verification of large-moment transmitter (TX) loops for geophysical applications. We first develop two equivalent circuit models for TX loops. We show that the equivalent inductance can be predicted using one of two empirical formulas. The stray capacitance of the loop is then calculated using the measured self-resonant frequency and the loop inductance. We model the losses associated with both the skin effect and the dissipation factor in both of these equivalent circuits. We find that the two equivalent circuit models produce the same results provided that the dissipation factor is small. Next we compare the measured input impedances for three TX loops that were constructed with different wire configurations with the equivalent circuit model. We found excellent agreement between the measured and simulated results after adjusting the dissipation factor. Since the skin effect and dissipation factor yield good agreement with measurements, the proximity effect is negligible in the three TX loops that we tested. We found that the effects of the dissipation factor dominated those of the skin effect when the wires were relatively close together. When the wires were widely separated, then the skin effect was the dominant loss mechanism. We also found that loops with wider wire separations exhibited higher self-resonant frequencies and better high-frequency performance.

Flip-flop resolving time test circuit

NASA Technical Reports Server (NTRS)

Rosenberger, F.; Chaney, T. J.

1982-01-01

Integrated circuit (IC) flip-flop resolving time parameters are measured by wafer probing, without need of dicing or bonding, throught the incorporation of test structures on an IC together with the flip-flop to be measured. Several delays that are fabricated as part of the test circuit, including a voltage-controlled delay with a resolution of a few picosecs, are calibrated as part of the test procedure by integrating them into, and out of, the delay path of a ring oscillator. Each of the delay values is calculated by subtracting the period of the ring oscillator with the delay omitted from the period with the delay included. The delay measurement technique is sufficiently general for other applications. The technique is illustrated for the case of the flip-flop parameters of a 5-micron feature size NMOS circuit.

Design and verification of wide-band, simultaneous, multi-frequency, tuning circuits for large moment transmitter loops

NASA Astrophysics Data System (ADS)

Dvorak, Steven L.; Sternberg, Ben K.; Feng, Wanjie

2017-03-01

In this paper we discuss the design and verification of wide-band, multi-frequency, tuning circuits for large-moment Transmitter (TX) loops. Since these multi-frequency, tuned-TX loops allow for the simultaneous transmission of multiple frequencies at high-current levels, they are ideally suited for frequency-domain geophysical systems that collect data while moving, such as helicopter mounted systems. Furthermore, since multi-frequency tuners use the same TX loop for all frequencies, instead of using separate tuned-TX loops for each frequency, they allow for the use of larger moment TX loops. In this paper we discuss the design and simulation of one- and three-frequency tuned TX loops and then present measurement results for a three-frequency, tuned-TX loop.

A fast, robust and tunable synthetic gene oscillator.

PubMed

Stricker, Jesse; Cookson, Scott; Bennett, Matthew R; Mather, William H; Tsimring, Lev S; Hasty, Jeff

2008-11-27

One defining goal of synthetic biology is the development of engineering-based approaches that enable the construction of gene-regulatory networks according to 'design specifications' generated from computational modelling. This approach provides a systematic framework for exploring how a given regulatory network generates a particular phenotypic behaviour. Several fundamental gene circuits have been developed using this approach, including toggle switches and oscillators, and these have been applied in new contexts such as triggered biofilm development and cellular population control. Here we describe an engineered genetic oscillator in Escherichia coli that is fast, robust and persistent, with tunable oscillatory periods as fast as 13 min. The oscillator was designed using a previously modelled network architecture comprising linked positive and negative feedback loops. Using a microfluidic platform tailored for single-cell microscopy, we precisely control environmental conditions and monitor oscillations in individual cells through multiple cycles. Experiments reveal remarkable robustness and persistence of oscillations in the designed circuit; almost every cell exhibited large-amplitude fluorescence oscillations throughout observation runs. The oscillatory period can be tuned by altering inducer levels, temperature and the media source. Computational modelling demonstrates that the key design principle for constructing a robust oscillator is a time delay in the negative feedback loop, which can mechanistically arise from the cascade of cellular processes involved in forming a functional transcription factor. The positive feedback loop increases the robustness of the oscillations and allows for greater tunability. Examination of our refined model suggested the existence of a simplified oscillator design without positive feedback, and we construct an oscillator strain confirming this computational prediction.

CAN LARGE TIME DELAYS OBSERVED IN LIGHT CURVES OF CORONAL LOOPS BE EXPLAINED IN IMPULSIVE HEATING?

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lionello, Roberto; Linker, Jon A.; Mikić, Zoran

The light curves of solar coronal loops often peak first in channels associated with higher temperatures and then in those associated with lower temperatures. The delay times between the different narrowband EUV channels have been measured for many individual loops and recently for every pixel of an active region observation. The time delays between channels for an active region exhibit a wide range of values. The maximum time delay in each channel pair can be quite large, i.e., >5000 s. These large time delays make-up 3%–26% (depending on the channel pair) of the pixels where a trustworthy, positive time delaymore » is measured. It has been suggested that these time delays can be explained by simple impulsive heating, i.e., a short burst of energy that heats the plasma to a high temperature, after which the plasma is allowed to cool through radiation and conduction back to its original state. In this paper, we investigate whether the largest observed time delays can be explained by this hypothesis by simulating a series of coronal loops with different heating rates, loop lengths, abundances, and geometries to determine the range of expected time delays between a set of four EUV channels. We find that impulsive heating cannot address the largest time delays observed in two of the channel pairs and that the majority of the large time delays can only be explained by long, expanding loops with photospheric abundances. Additional observations may rule out these simulations as an explanation for the long time delays. We suggest that either the time delays found in this manner may not be representative of real loop evolution, or that the impulsive heating and cooling scenario may be too simple to explain the observations, and other potential heating scenarios must be explored.« less

Entrainment and high-density three-dimensional mapping in right atrial macroreentry provide critical complementary information: Entrainment may unmask "visual reentry" as passive.

PubMed

Pathik, Bhupesh; Lee, Geoffrey; Nalliah, Chrishan; Joseph, Stephen; Morton, Joseph B; Sparks, Paul B; Sanders, Prashanthan; Kistler, Peter M; Kalman, Jonathan M

2017-10-01

With the recent advent of high-density (HD) 3-dimensional (3D) mapping, the utility of entrainment is uncertain. However, the limitations of visual representation and interpretation of these high-resolution 3D maps are unclear. The purpose of this study was to determine the strengths and limitations of both HD 3D mapping and entrainment mapping during mapping of right atrial macroreentry. Fifteen patients were studied. The number and type of circuits accounting for ≥90% of the tachycardia cycle length using HD 3D mapping were verified using systematic entrainment mapping. Entrainment sites with an unexpectedly long postpacing interval despite proximity to the active circuit were evaluated. Based on HD 3D mapping, 27 circuits were observed: 12 peritricuspid, 2 upper loop reentry, 10 lower loop reentry, and 3 lateral wall circuits. With entrainment, 17 of the 27 circuits were active: all 12 peritricuspid and 2 upper loop reentry. However, lower loop reentry was confirmed in only 3 of 10, and none of the 3 lateral wall circuits were present. Mean percentage of tachycardia cycle length covered by active circuits was 98% ± 1% vs 97% ± 2% for passive circuits (P = .09). None of the 345 entrainment runs terminated tachycardia or changed tachycardia mechanism. In 8 of 15 patients, 13 examples of unexpectedly long postpacing interval were observed at entrainment sites located distal to localized zones of slow conduction seen on HD 3D mapping. Using HD 3D mapping, "visual reentry" may be due to passive circuitous propagation rather than a critical reentrant circuit. HD 3D mapping provides new insights into regional conduction and helps explain unusual entrainment phenomena. Copyright © 2017 Heart Rhythm Society. Published by Elsevier Inc. All rights reserved.

Stabilization of self-mode-locked quantum dash lasers by symmetric dual-loop optical feedback

NASA Astrophysics Data System (ADS)

Asghar, Haroon; Wei, Wei; Kumar, Pramod; Sooudi, Ehsan; McInerney, John. G.

2018-02-01

We report experimental studies of the influence of symmetric dual-loop optical feedback on the RF linewidth and timing jitter of self-mode-locked two-section quantum dash lasers emitting at 1550 nm. Various feedback schemes were investigated and optimum levels determined for narrowest RF linewidth and low timing jitter, for single-loop and symmetric dual-loop feedback. Two symmetric dual-loop configurations, with balanced and unbalanced feedback ratios, were studied. We demonstrate that unbalanced symmetric dual loop feedback, with the inner cavity resonant and fine delay tuning of the outer loop, gives narrowest RF linewidth and reduced timing jitter over a wide range of delay, unlike single and balanced symmetric dual-loop configurations. This configuration with feedback lengths 80 and 140 m narrows the RF linewidth by 4-67x and 10-100x, respectively, across the widest delay range, compared to free-running. For symmetric dual-loop feedback, the influence of different power split ratios through the feedback loops was determined. Our results show that symmetric dual-loop feedback is markedly more effective than single-loop feedback in reducing RF linewidth and timing jitter, and is much less sensitive to delay phase, making this technique ideal for applications where robustness and alignment tolerance are essential.

Equivalent circuit simulation of HPEM-induced transient responses at nonlinear loads

NASA Astrophysics Data System (ADS)

Kotzev, Miroslav; Bi, Xiaotang; Kreitlow, Matthias; Gronwald, Frank

2017-09-01

In this paper the equivalent circuit modeling of a nonlinearly loaded loop antenna and its transient responses to HPEM field excitations are investigated. For the circuit modeling the general strategy to characterize the nonlinearly loaded antenna by a linear and a nonlinear circuit part is pursued. The linear circuit part can be determined by standard methods of antenna theory and numerical field computation. The modeling of the nonlinear circuit part requires realistic circuit models of the nonlinear loads that are given by Schottky diodes. Combining both parts, appropriate circuit models are obtained and analyzed by means of a standard SPICE circuit simulator. It is the main result that in this way full-wave simulation results can be reproduced. Furthermore it is clearly seen that the equivalent circuit modeling offers considerable advantages with respect to computation speed and also leads to improved physical insights regarding the coupling between HPEM field excitation and nonlinearly loaded loop antenna.

Time delay compensation for closed-loop insulin delivery systems: a simulation study.

PubMed

Reboldi, G P; Home, P D; Calabrese, G; Fabietti, P G; Brunetti, P; Massi Benedetti, M

1991-06-01

Closed loop insulin therapy certainly represents the best possible approach to insulin replacement. However, present limitations preclude wider application of the so-called artificial pancreas. Therefore, a thorough understanding of these limitations is needed to design better systems for future long-term use. The present simulation study was design: to obtain better information on the impact of the measurement delay of currently available closed-loop devices both during closed-loop insulin delivery and blood glucose clamp studies, and to design and test a time delay compensator based on the method originally described by O.J. Smith. Simulations were performed on a Compaq Deskpro 486/25 personal computer under MS-DOS operating system using Simnon rel. 3.00 software. There was a direct relationship between measurement delay and amount of insulin delivered, i.e., the longer the delay the higher the insulin dose needed to control a rise in blood glucose; the closed-loop response in presence of a time delay was qualitatively impaired both during insulin delivery and blood glucose clamp studies; time delay compensation was effective in reducing the insulin dose and improving controller stability during the early phase of clamp studies. However, the robustness of a Smith's predictor-based controller should be carefully evaluated before implementation in closed-loop systems can be considered.

Mitigating Communication Delays in Remotely Connected Hardware-in-the-loop Experiments

DOE Office of Scientific and Technical Information (OSTI.GOV)

Cale, James; Johnson, Brian; Dall'Anese, Emiliano

Here, this paper introduces a potential approach for mitigating the effects of communication delays between multiple, closed-loop hardware-in-the-loop experiments which are virtually connected, yet physically separated. The method consists of an analytical method for the compensation of communication delays, along with the supporting computational and communication infrastructure. The control design leverages tools for the design of observers for the compensation of measurement errors in systems with time-varying delays. The proposed methodology is validated through computer simulation and hardware experimentation connecting hardware-in-the-loop experiments conducted between laboratories separated by a distance of over 100 km.

Mitigating Communication Delays in Remotely Connected Hardware-in-the-loop Experiments

DOE PAGES

Cale, James; Johnson, Brian; Dall'Anese, Emiliano; ...

2018-03-30

Here, this paper introduces a potential approach for mitigating the effects of communication delays between multiple, closed-loop hardware-in-the-loop experiments which are virtually connected, yet physically separated. The method consists of an analytical method for the compensation of communication delays, along with the supporting computational and communication infrastructure. The control design leverages tools for the design of observers for the compensation of measurement errors in systems with time-varying delays. The proposed methodology is validated through computer simulation and hardware experimentation connecting hardware-in-the-loop experiments conducted between laboratories separated by a distance of over 100 km.

Electronic Circuit Experiments and SPICE Simulation of Double Covering Bifurcation of 2-Torus Quasi-Periodic Flow in Phase-Locked Loop Circuit

NASA Astrophysics Data System (ADS)

Kamiyama, Kyohei; Endo, Tetsuro; Imai, Isao; Komuro, Motomasa

2016-06-01

Double covering (DC) bifurcation of a 2-torus quasi-periodic flow in a phase-locked loop circuit was experimentally investigated using an electronic circuit and via SPICE simulation; in the circuit, the input radio-frequency signal was frequency modulated by the sum of two asynchronous sinusoidal baseband signals. We observed both DC and period-doubling bifurcations of a discrete map on two Poincaré sections, which were realized by changing the sample timing from one baseband sinusoidal signal to the other. The results confirm the DC bifurcation of the original flow.

Digital tanlock loop architecture with no delay

NASA Astrophysics Data System (ADS)

Al-Kharji AL-Ali, Omar; Anani, Nader; Al-Araji, Saleh; Al-Qutayri, Mahmoud; Ponnapalli, Prasad

2012-02-01

This article proposes a new architecture for a digital tanlock loop which eliminates the time-delay block. The ? (rad) phase shift relationship between the two channels, which is generated by the delay block in the conventional time-delay digital tanlock loop (TDTL), is preserved using two quadrature sampling signals for the loop channels. The proposed system outperformed the original TDTL architecture, when both systems were tested with frequency shift keying input signal. The new system demonstrated better linearity and acquisition speed as well as improved noise performance compared with the original TDTL architecture. Furthermore, the removal of the time-delay block enables all processing to be digitally performed, which reduces the implementation complexity. Both the original TDTL and the new architecture without the delay block were modelled and simulated using MATLAB/Simulink. Implementation issues, including complexity and relation to simulation of both architectures, are also addressed.

System and circuitry to provide stable transconductance for biasing

NASA Technical Reports Server (NTRS)

Garverick, Steven L. (Inventor); Yu, Xinyu (Inventor)

2012-01-01

An amplifier system can include an input amplifier configured to receive an analog input signal and provide an amplified signal corresponding to the analog input signal. A tracking loop is configured to employ delta modulation for tracking the amplified signal, the tracking loop providing a corresponding output signal. A biasing circuit is configured to adjust a bias current to maintain stable transconductance over temperature variations, the biasing circuit providing at least one bias signal for biasing at least one of the input amplifier and the tracking loop, whereby the circuitry receiving the at least one bias signal exhibits stable performance over the temperature variations. In another embodiment the biasing circuit can be utilized in other applications.

Teaching Electric Circuits with Multiple Batteries: A Qualitative Approach

ERIC Educational Resources Information Center

Smith, David P.; van Kampen, Paul

2011-01-01

We have investigated preservice science teachers' qualitative understanding of circuits consisting of multiple batteries in single and multiple loops using a pretest and post-test method and classroom observations. We found that most students were unable to explain the effects of adding batteries in single and multiple loops, as they tended to use…

A dual-loop adaptive control for minimizing time response delay in real-time structural vibration control with magnetorheological (MR) devices

NASA Astrophysics Data System (ADS)

Chen, Xi; Li, Yancheng; Li, Jianchun; Gu, Xiaoyu

2018-01-01

Time delay is a challenge issue faced by the real-time control application of the magnetorheological (MR) devices. Not to deal with it properly may jeopardize the effectiveness of the control, even lead to instability of the control system or catastrophic failure. This paper proposes a dual-loop adaptive control to address the response time delay associated with MR devices. In the proposed dual-loop control, the inner loop is designed to compensate the time delay of MR device induced by the PWM current driver. While the outer loop control can be any structural control algorithm with aims to reducing structural responses of a building during extreme loadings. Here an adaptive control strategy is adopted. To verify the proposed dual-loop control, a smart base isolation system employing magnetorheological elastomer base isolators is used as an example to illustrate the control effect. Numerical study is then conducted using a 5 -storey shear building model equipped with smart base isolation system. The result shows that with the implementation of the inner loop, the control current can instantly follow the control command which reduce the possibility of instability caused by the time delay. Comparative studies are conducted between three control strategies, i.e. dual-loop control, Lyapunov’s direct method based control and optimal passive base isolation control. The results of the study have demonstrated that the proposed dual-loop control strategy can achieve much better performance than the other two control strategies.

A 16-Channel CMOS Chopper-Stabilized Analog Front-End ECoG Acquisition Circuit for a Closed-Loop Epileptic Seizure Control System.

PubMed

Wu, Chung-Yu; Cheng, Cheng-Hsiang; Chen, Zhi-Xin

2018-06-01

In this paper, a 16-channel analog front-end (AFE) electrocorticography signal acquisition circuit for a closed-loop seizure control system is presented. It is composed of 16 input protection circuits, 16 auto-reset chopper-stabilized capacitive-coupled instrumentation amplifiers (AR-CSCCIA) with bandpass filters, 16 programmable transconductance gain amplifiers, a multiplexer, a transimpedance amplifier, and a 128-kS/s 10-bit delta-modulated successive-approximation-register analog-to-digital converter (SAR ADC). In closed-loop seizure control system applications, the stimulator shares the same electrode with the AFE amplifier for effective suppression of epileptic seizures. To prevent from overstress in MOS devices caused by high stimulation voltage, an input protection circuit with a high-voltage-tolerant switch is proposed for the AFE amplifier. Moreover, low input-referred noise is achieved by using the chopper modulation technique in the AR-CSCCIA. To reduce the undesired effects of chopper modulation, an improved offset reduction loop is proposed to reduce the output offset generated by input chopper mismatches. The digital ripple reduction loop is also used to reduce the chopper ripple. The fabricated AFE amplifier has 49.1-/59.4-/67.9-dB programmable gain and 2.02-μVrms input referred noise in a bandwidth of 0.59-117 Hz. The measured power consumption of the AFE amplifier is 3.26 μW per channel, and the noise efficiency factor is 3.36. The in vivo animal test has been successfully performed to verify the functions. It is shown that the proposed AFE acquisition circuit is suitable for implantable closed-loop seizure control systems.

Measuring Information-Transfer Delays

PubMed Central

Wibral, Michael; Pampu, Nicolae; Priesemann, Viola; Siebenhühner, Felix; Seiwert, Hannes; Lindner, Michael; Lizier, Joseph T.; Vicente, Raul

2013-01-01

In complex networks such as gene networks, traffic systems or brain circuits it is important to understand how long it takes for the different parts of the network to effectively influence one another. In the brain, for example, axonal delays between brain areas can amount to several tens of milliseconds, adding an intrinsic component to any timing-based processing of information. Inferring neural interaction delays is thus needed to interpret the information transfer revealed by any analysis of directed interactions across brain structures. However, a robust estimation of interaction delays from neural activity faces several challenges if modeling assumptions on interaction mechanisms are wrong or cannot be made. Here, we propose a robust estimator for neuronal interaction delays rooted in an information-theoretic framework, which allows a model-free exploration of interactions. In particular, we extend transfer entropy to account for delayed source-target interactions, while crucially retaining the conditioning on the embedded target state at the immediately previous time step. We prove that this particular extension is indeed guaranteed to identify interaction delays between two coupled systems and is the only relevant option in keeping with Wiener’s principle of causality. We demonstrate the performance of our approach in detecting interaction delays on finite data by numerical simulations of stochastic and deterministic processes, as well as on local field potential recordings. We also show the ability of the extended transfer entropy to detect the presence of multiple delays, as well as feedback loops. While evaluated on neuroscience data, we expect the estimator to be useful in other fields dealing with network dynamics. PMID:23468850

TECHNICAL DESIGN NOTE: Picosecond resolution programmable delay line

NASA Astrophysics Data System (ADS)

Suchenek, Mariusz

2009-11-01

The note presents implementation of a programmable delay line for digital signals. The tested circuit has a subnanosecond delay range programmable with a resolution of picoseconds. Implementation of the circuit was based on low-cost components, easily available on the market.

Variable Delay Element For Jitter Control In High Speed Data Links

DOEpatents

Livolsi, Robert R.

2002-06-11

A circuit and method for decreasing the amount of jitter present at the receiver input of high speed data links which uses a driver circuit for input from a high speed data link which comprises a logic circuit having a first section (1) which provides data latches, a second section (2) which provides a circuit generates a pre-destorted output and for compensating for level dependent jitter having an OR function element and a NOR function element each of which is coupled to two inputs and to a variable delay element as an input which provides a bi-modal delay for pulse width pre-distortion, a third section (3) which provides a muxing circuit, and a forth section (4) for clock distribution in the driver circuit. A fifth section is used for logic testing the driver circuit.

A high resolution on-chip delay sensor with low supply-voltage sensitivity for high-performance electronic systems.

PubMed

Sheng, Duo; Lai, Hsiu-Fan; Chan, Sheng-Min; Hong, Min-Rong

2015-02-13

An all-digital on-chip delay sensor (OCDS) circuit with high delay-measurement resolution and low supply-voltage sensitivity for efficient detection and diagnosis in high-performance electronic system applications is presented. Based on the proposed delay measurement scheme, the quantization resolution of the proposed OCDS can be reduced to several picoseconds. Additionally, the proposed cascade-stage delay measurement circuit can enhance immunity to supply-voltage variations of the delay measurement resolution without extra self-biasing or calibration circuits. Simulation results show that the delay measurement resolution can be improved to 1.2 ps; the average delay resolution variation is 0.55% with supply-voltage variations of ±10%. Moreover, the proposed delay sensor can be implemented in an all-digital manner, making it very suitable for high-performance electronic system applications as well as system-level integration.

Dynamic autofocus for continuous-scanning time-delay-and-integration image acquisition in automated microscopy.

PubMed

Bravo-Zanoguera, Miguel E; Laris, Casey A; Nguyen, Lam K; Oliva, Mike; Price, Jeffrey H

2007-01-01

Efficient image cytometry of a conventional microscope slide means rapid acquisition and analysis of 20 gigapixels of image data (at 0.3-microm sampling). The voluminous data motivate increased acquisition speed to enable many biomedical applications. Continuous-motion time-delay-and-integrate (TDI) scanning has the potential to speed image acquisition while retaining sensitivity, but the challenge of implementing high-resolution autofocus operating simultaneously with acquisition has limited its adoption. We develop a dynamic autofocus system for this need using: 1. a "volume camera," consisting of nine fiber optic imaging conduits to charge-coupled device (CCD) sensors, that acquires images in parallel from different focal planes, 2. an array of mixed analog-digital processing circuits that measure the high spatial frequencies of the multiple image streams to create focus indices, and 3. a software system that reads and analyzes the focus data streams and calculates best focus for closed feedback loop control. Our system updates autofocus at 56 Hz (or once every 21 microm of stage travel) to collect sharply focused images sampled at 0.3x0.3 microm(2)/pixel at a stage speed of 2.3 mms. The system, tested by focusing in phase contrast and imaging long fluorescence strips, achieves high-performance closed-loop image-content-based autofocus in continuous scanning for the first time.

A HWIL test facility of infrared imaging laser radar using direct signal injection

NASA Astrophysics Data System (ADS)

Wang, Qian; Lu, Wei; Wang, Chunhui; Wang, Qi

2005-01-01

Laser radar has been widely used these years and the hardware-in-the-loop (HWIL) testing of laser radar become important because of its low cost and high fidelity compare with On-the-Fly testing and whole digital simulation separately. Scene generation and projection two key technologies of hardware-in-the-loop testing of laser radar and is a complicated problem because the 3D images result from time delay. The scene generation process begins with the definition of the target geometry and reflectivity and range. The real-time 3D scene generation computer is a PC based hardware and the 3D target models were modeled using 3dsMAX. The scene generation software was written in C and OpenGL and is executed to extract the Z-buffer from the bit planes to main memory as range image. These pixels contain each target position x, y, z and its respective intensity and range value. Expensive optical injection technologies of scene projection such as LDP array, VCSEL array, DMD and associated scene generation is ongoing. But the optical scene projection is complicated and always unaffordable. In this paper a cheaper test facility was described that uses direct electronic injection to provide rang images for laser radar testing. The electronic delay and pulse shaping circuits inject the scenes directly into the seeker's signal processing unit.

The Trade-Off Mechanism in Mammalian Circadian Clock Model with Two Time Delays

NASA Astrophysics Data System (ADS)

Yan, Jie; Kang, Xiaxia; Yang, Ling

Circadian clock is an autonomous oscillator which orchestrates the daily rhythms of physiology and behaviors. This study is devoted to explore how a positive feedback loop affects the dynamics of mammalian circadian clock. We simplify an experimentally validated mathematical model in our previous work, to a nonlinear differential equation with two time delays. This simplified mathematical model incorporates the pacemaker of mammalian circadian clock, a negative primary feedback loop, and a critical positive auxiliary feedback loop, Rev-erbα/Cry1 loop. We perform analytical studies of the system. Delay-dependent conditions for the asymptotic stability of the nontrivial positive steady state of the model are investigated. We also prove the existence of Hopf bifurcation, which leads to self-sustained oscillation of mammalian circadian clock. Our theoretical analyses show that the oscillatory regime is reduced upon the participation of the delayed positive auxiliary loop. However, further simulations reveal that the auxiliary loop can enable the circadian clock gain widely adjustable amplitudes and robust period. Thus, the positive auxiliary feedback loop may provide a trade-off mechanism, to use the small loss in the robustness of oscillation in exchange for adaptable flexibility in mammalian circadian clock. The results obtained from the model may gain new insights into the dynamics of biological oscillators with interlocked feedback loops.

Log amplifier with pole-zero compensation

DOEpatents

Brookshier, W.

1985-02-08

A logarithmic amplifier circuit provides pole-zero compensation for improved stability and response time over 6-8 decades of input signal frequency. The amplifer circuit includes a first operational amplifier with a first feedback loop which includes a second, inverting operational amplifier in a second feedstock loop. The compensated output signal is provided by the second operational amplifier with the log elements, i.e., resistors, and the compensating capacitors in each of the feedback loops having equal values so that each break point is offset by a compensating break point or zero.

Log amplifier with pole-zero compensation

DOEpatents

Brookshier, William

1987-01-01

A logarithmic amplifier circuit provides pole-zero compensation for improved stability and response time over 6-8 decades of input signal frequency. The amplifier circuit includes a first operational amplifier with a first feedback loop which includes a second, inverting operational amplifier in a second feedback loop. The compensated output signal is provided by the second operational amplifier with the log elements, i.e., resistors, and the compensating capacitors in each of the feedback loops having equal values so that each break point or pole is offset by a compensating break point or zero.

The magnetosphere as system

NASA Astrophysics Data System (ADS)

Siscoe, G. L.

2012-12-01

What is a system? A group of elements interacting with each other so as to create feedback loops. A system gets complex as the number of feedback loops increases and as the feedback loops exhibit time delays. Positive and negative feedback loops with time delays can give a system intrinsic time dependence and emergent properties. A system generally has input and output flows of something (matter, energy, money), which, if time variable, add an extrinsic component to its behavior. The magnetosphere is a group of elements interacting through feedback loops, some with time delays, driven by energy and mass inflow from a variable solar wind and outflow into the atmosphere and solar wind. The magnetosphere is a complex system. With no solar wind, there is no behavior. With solar wind, there is behavior from intrinsic and extrinsic causes. As a contribution to taking a macroscopic view of magnetospheric dynamics, to treating the magnetosphere as a globally integrated, complex entity, I will discus the magnetosphere as a system, its feedback loops, time delays, emergent behavior, and intrinsic and extrinsic behavior modes.

Differential Resonant Ring YIG Tuned Oscillator

NASA Technical Reports Server (NTRS)

Parrott, Ronald A.

2010-01-01

A differential SiGe oscillator circuit uses a resonant ring-oscillator topology in order to electronically tune the oscillator over multi-octave bandwidths. The oscillator s tuning is extremely linear, because the oscillator s frequency depends on the magnetic tuning of a YIG sphere, whose resonant frequency is equal to a fundamental constant times the DC magnetic field. This extremely simple circuit topology uses two coupling loops connecting a differential pair of SiGe bipolar transistors into a feedback configuration using a YIG tuned filter creating a closed-loop ring oscillator. SiGe device technology is used for this oscillator in order to keep the transistor s 1/f noise to an absolute minimum in order to achieve minimum RF phase noise. The single-end resonant ring oscillator currently has an advantage in fewer parts, but when the oscillation frequency is greater than 16 GHz, the package s parasitic behavior couples energy to the sphere and causes holes and poor phase noise performance. This is because the coupling to the YIG is extremely low, so that the oscillator operates at near the unloaded Q. With the differential resonant ring oscillator, the oscillation currents are just in the YIG coupling mechanisms. The phase noise is even better, and the physical size can be reduced to permit monolithic microwave integrated circuit oscillators. This invention is a YIG tuned oscillator circuit making use of a differential topology to simultaneously achieve an extremely broadband electronic tuning range and ultra-low phase noise. As a natural result of its differential circuit topology, all reactive elements, such as tuning stubs, which limit tuning bandwidth by contributing excessive open loop phase shift, have been eliminated. The differential oscillator s open-loop phase shift is associated with completely non-dispersive circuit elements such as the physical angle of the coupling loops, a differential loop crossover, and the high-frequency phase shift of the n-p-n transistors. At the input of the oscillator s feedback loop is a pair of differentially connected n-p-n SiGe transistors that provides extremely high gain, and because they are bulk-effect devices, extremely low 1/f noise (leading to ultralow RF phase noise). The 1/f corner frequency for n-p-n SiGe transistors is approximately 500 Hz. The RF energy from the transistor s collector output is connected directly to the top-coupling loop (the excitation loop) of a single-sphere YIG tuned filter. A uniform magnetic field to bias the YIG must be at a right angle to any vector associated with an RF current in a coupling loop in order for the precession to interact with the RF currents.

A review on high-resolution CMOS delay lines: towards sub-picosecond jitter performance.

PubMed

Abdulrazzaq, Bilal I; Abdul Halin, Izhal; Kawahito, Shoji; Sidek, Roslina M; Shafie, Suhaidi; Yunus, Nurul Amziah Md

2016-01-01

A review on CMOS delay lines with a focus on the most frequently used techniques for high-resolution delay step is presented. The primary types, specifications, delay circuits, and operating principles are presented. The delay circuits reported in this paper are used for delaying digital inputs and clock signals. The most common analog and digitally-controlled delay elements topologies are presented, focusing on the main delay-tuning strategies. IC variables, namely, process, supply voltage, temperature, and noise sources that affect delay resolution through timing jitter are discussed. The design specifications of these delay elements are also discussed and compared for the common delay line circuits. As a result, the main findings of this paper are highlighting and discussing the followings: the most efficient high-resolution delay line techniques, the trade-off challenge found between CMOS delay lines designed using either analog or digitally-controlled delay elements, the trade-off challenge between delay resolution and delay range and the proposed solutions for this challenge, and how CMOS technology scaling can affect the performance of CMOS delay lines. Moreover, the current trends and efforts used in order to generate output delayed signal with low jitter in the sub-picosecond range are presented.

Two integrator loop quadrature oscillators: A review.

PubMed

Soliman, Ahmed M

2013-01-01

A review of the two integrator loop oscillator circuits providing two quadrature sinusoidal output voltages is given. All the circuits considered employ the minimum number of capacitors namely two except one circuit which uses three capacitors. The circuits considered are classified to four different classes. The first class includes floating capacitors and floating resistors and the active building blocks realizing these circuits are the Op Amp or the OTRA. The second class employs grounded capacitors and includes floating resistors and the active building blocks realizing these circuits are the DCVC or the unity gain cells or the CFOA. The third class employs grounded capacitors and grounded resistors and the active building blocks realizing these circuits are the CCII. The fourth class employs grounded capacitors and no resistors and the active building blocks realizing these circuits are the TA. Transformation methods showing the generation of different classes from each other is given in details and this is one of the main objectives of this paper.

Design of surface acoustic wave filters for the multiplex transmission system of multilevel inverter circuits

NASA Astrophysics Data System (ADS)

Kubo, Keita; Kanai, Nanae; Kobayashi, Fumiya; Goka, Shigeyoshi; Wada, Keiji; Kakio, Shoji

2017-07-01

We designed surface acoustic wave (SAW) filters for a multiplex transmission system of multilevel inverter circuits, and applied them to a single-phase three-level inverter. To reduce the transmission delay time of the SAW filters, a four-channel SAW filter array was fabricated and its characteristics were measured. The delay time of the SAW filters was <350 ns, and the delay time difference was reduced to ≤184 ns, less than half that previously reported. The SAW filters withstood up to 990 V, which is sufficient for the inverters used in most domestic appliances. A single-phase three-level inverter with the fabricated SAW filters worked with a total delay time shorter than our target delay time of 2.5 µs. The delay time difference of the proposed system was 0.26 µs, which is sufficient for preventing the inverter circuit from short-circuiting. The SAW filters controlled a multilevel inverter system with simple signal wiring and high dielectric withstanding voltages.

The constant current loop - A new paradigm for resistance signal conditioning

NASA Astrophysics Data System (ADS)

Anderson, Karl F.

A practical single constant current loop circuit for the signal conditioning of variable-resistance transducers has been synthesized, analyzed, and demonstrated. The strain gage and the resistance temperature device are examples of variable-resistance sensors. Lead wires connect variable-resistance sensors to remotely located signal-conditioning hardware. The presence of lead wires in the conventional Wheatstone bridge signal-conditioning circuit introduces undesired effects that reduce the quality of the data from the remote sensors. A practical approach is presented for suppressing essentially all lead wire resistance effects while indicating only the change in resistance value. An adaptation of the current loop circuit is presented that simultaneously provides an output signal voltage directly proportional to transducer resistance change and provides temperature information that is unaffected by transducer and lead wire resistance variations.

The constant current loop - A new paradigm for resistance signal conditioning

NASA Technical Reports Server (NTRS)

Anderson, Karl F.

1993-01-01

A practical single constant current loop circuit for the signal conditioning of variable-resistance transducers has been synthesized, analyzed, and demonstrated. The strain gage and the resistance temperature device are examples of variable-resistance sensors. Lead wires connect variable-resistance sensors to remotely located signal-conditioning hardware. The presence of lead wires in the conventional Wheatstone bridge signal-conditioning circuit introduces undesired effects that reduce the quality of the data from the remote sensors. A practical approach is presented for suppressing essentially all lead wire resistance effects while indicating only the change in resistance value. An adaptation of the current loop circuit is presented that simultaneously provides an output signal voltage directly proportional to transducer resistance change and provides temperature information that is unaffected by transducer and lead wire resistance variations.

Break-before-make CMOS inverter for power-efficient delay implementation.

PubMed

Puhan, Janez; Raič, Dušan; Tuma, Tadej; Bűrmen, Árpád

2014-01-01

A modified static CMOS inverter with two inputs and two outputs is proposed to reduce short-circuit current in order to increment delay and reduce power overhead where slow operation is required. The circuit is based on bidirectional delay element connected in series with the PMOS and NMOS switching transistors. It provides differences in the dynamic response so that the direct-path current in the next stage is reduced. The switching transistors are never ON at the same time. Characteristics of various delay element implementations are presented and verified by circuit simulations. Global optimization procedure is used to obtain the most power-efficient transistor sizing. The performance of the modified CMOS inverter chain is compared to standard implementation for various delays. The energy (charge) per delay is reduced up to 40%. The use of the proposed delay element is demonstrated by implementing a low-power delay line and a leading-edge detector cell.

Break-before-Make CMOS Inverter for Power-Efficient Delay Implementation

PubMed Central

Raič, Dušan

2014-01-01

A modified static CMOS inverter with two inputs and two outputs is proposed to reduce short-circuit current in order to increment delay and reduce power overhead where slow operation is required. The circuit is based on bidirectional delay element connected in series with the PMOS and NMOS switching transistors. It provides differences in the dynamic response so that the direct-path current in the next stage is reduced. The switching transistors are never ON at the same time. Characteristics of various delay element implementations are presented and verified by circuit simulations. Global optimization procedure is used to obtain the most power-efficient transistor sizing. The performance of the modified CMOS inverter chain is compared to standard implementation for various delays. The energy (charge) per delay is reduced up to 40%. The use of the proposed delay element is demonstrated by implementing a low-power delay line and a leading-edge detector cell. PMID:25538951

Steady-state probability density function of the phase error for a DPLL with an integrate-and-dump device

NASA Technical Reports Server (NTRS)

Simon, M.; Mileant, A.

1986-01-01

The steady-state behavior of a particular type of digital phase-locked loop (DPLL) with an integrate-and-dump circuit following the phase detector is characterized in terms of the probability density function (pdf) of the phase error in the loop. Although the loop is entirely digital from an implementation standpoint, it operates at two extremely different sampling rates. In particular, the combination of a phase detector and an integrate-and-dump circuit operates at a very high rate whereas the loop update rate is very slow by comparison. Because of this dichotomy, the loop can be analyzed by hybrid analog/digital (s/z domain) techniques. The loop is modeled in such a general fashion that previous analyses of the Real-Time Combiner (RTC), Subcarrier Demodulator Assembly (SDA), and Symbol Synchronization Assembly (SSA) fall out as special cases.

Perception as a closed-loop convergence process.

PubMed

Ahissar, Ehud; Assa, Eldad

2016-05-09

Perception of external objects involves sensory acquisition via the relevant sensory organs. A widely-accepted assumption is that the sensory organ is the first station in a serial chain of processing circuits leading to an internal circuit in which a percept emerges. This open-loop scheme, in which the interaction between the sensory organ and the environment is not affected by its concurrent downstream neuronal processing, is strongly challenged by behavioral and anatomical data. We present here a hypothesis in which the perception of external objects is a closed-loop dynamical process encompassing loops that integrate the organism and its environment and converging towards organism-environment steady-states. We discuss the consistency of closed-loop perception (CLP) with empirical data and show that it can be synthesized in a robotic setup. Testable predictions are proposed for empirical distinction between open and closed loop schemes of perception.

Perception as a closed-loop convergence process

PubMed Central

Ahissar, Ehud; Assa, Eldad

2016-01-01

Perception of external objects involves sensory acquisition via the relevant sensory organs. A widely-accepted assumption is that the sensory organ is the first station in a serial chain of processing circuits leading to an internal circuit in which a percept emerges. This open-loop scheme, in which the interaction between the sensory organ and the environment is not affected by its concurrent downstream neuronal processing, is strongly challenged by behavioral and anatomical data. We present here a hypothesis in which the perception of external objects is a closed-loop dynamical process encompassing loops that integrate the organism and its environment and converging towards organism-environment steady-states. We discuss the consistency of closed-loop perception (CLP) with empirical data and show that it can be synthesized in a robotic setup. Testable predictions are proposed for empirical distinction between open and closed loop schemes of perception. DOI: http://dx.doi.org/10.7554/eLife.12830.001 PMID:27159238

Northwest Laboratory for Integrated Systems, University of Washington, Semiannual Technical Report Number 1, July 1-November 8, 1991

DTIC Science & Technology

1991-11-08

only simple bounds on delays but also relate the delays in linear inequalities so that tradeoffs are apparent. We model circuits as communicating...set of linear inequalities constraining the variables. These relations provide synthesis tools with information about tradeoffs between circuit delays...available to express the original circuit as a graph of elementary gates and then cover the graph’s fanout-free trees with collections of three-input

Monitoring Digital Closed-Loop Feedback Systems

NASA Technical Reports Server (NTRS)

Katz, Richard; Kleyner, Igor

2011-01-01

A technique of monitoring digital closed-loop feedback systems has been conceived. The basic idea is to obtain information on the performances of closed-loop feedback circuits in such systems to aid in the determination of the functionality and integrity of the circuits and of performance margins. The need for this technique arises as follows: Some modern digital systems include feedback circuits that enable other circuits to perform with precision and are tolerant of changes in environment and the device s parameters. For example, in a precision timing circuit, it is desirable to make the circuit insensitive to variability as a result of the manufacture of circuit components and to the effects of temperature, voltage, radiation, and aging. However, such a design can also result in masking the indications of damaged and/or deteriorating components. The present technique incorporates test circuitry and associated engineering-telemetry circuitry into an embedded system to monitor the closed-loop feedback circuits, using spare gates that are often available in field programmable gate arrays (FPGAs). This technique enables a test engineer to determine the amount of performance margin in the system, detect out of family circuit performance, and determine one or more trend(s) in the performance of the system. In one system to which the technique has been applied, an ultra-stable oscillator is used as a reference for internal adjustment of 12 time-to-digital converters (TDCs). The feedback circuit produces a pulse-width-modulated signal that is fed as a control input into an amplifier, which controls the circuit s operating voltage. If the circuit s gates are determined to be operating too slowly or rapidly when their timing is compared with that of the reference signal, then the pulse width increases or decreases, respectively, thereby commanding the amplifier to increase or reduce, respectively, its output level, and "adjust" the speed of the circuits. The nominal frequency of the TDC s pulse width modulated outputs is approximately 40 kHz. In this system, the technique is implemented by means of a monitoring circuit that includes a 20-MHz sampling circuit and a 24-bit accumulator with a gate time of 10 ms. The monitoring circuit measures the duty cycle of each of the 12 TDCs at a repetition rate of 28 Hz. The accumulator content is reset to all zeroes at the beginning of each measurement period and is then incremented or decremented based of the value of the state of the pulse width modulated signal. Positive or negative values in the accumulator correspond to duty cycles greater or less, respectively, than 50 percent.

[Research progress of mammalian synthetic biology in biomedical field].

PubMed

Yang, Linfeng; Yin, Jianli; Wang, Meiyan; Ye, Haifeng

2017-03-25

Although still in its infant stage, synthetic biology has achieved remarkable development and progress during the past decade. Synthetic biology applies engineering principles to design and construct gene circuits uploaded into living cells or organisms to perform novel or improved functions, and it has been widely used in many fields. In this review, we describe the recent advances of mammalian synthetic biology for the treatment of diseases. We introduce common tools and design principles of synthetic gene circuits, and then we demonstrate open-loop gene circuits induced by different trigger molecules used in disease diagnosis and close-loop gene circuits used for biomedical applications. Finally, we discuss the perspectives and potential challenges of synthetic biology for clinical applications.

Learning the Art of Electronics

NASA Astrophysics Data System (ADS)

Hayes, Thomas C.; Horowitz, Paul

2016-03-01

1. DC circuits; 2. RC circuits; 3. Diode circuits; 4. Transistors I; 5. Transistors II; 6. Operational amplifiers I; 7. Operational amplifiers II: nice positive feedback; 8. Operational amplifiers III; 9. Operational amplifiers IV: nasty positive feedback; 10. Operational amplifiers V: PID motor control loop; 11. Voltage regulators; 12. MOSFET switches; 13. Group audio project; 14. Logic gates; 15. Logic compilers, sequential circuits, flip-flops; 16. Counters; 17. Memory: state machines; 18. Analog to digital: phase-locked loop; 19. Microcontrollers and microprocessors I: processor/controller; 20. I/O, first assembly language; 21. Bit operations; 22. Interrupt: ADC and DAC; 23. Moving pointers, serial buses; 24. Dallas Standalone Micro, SiLabs SPI RAM; 25. Toys in the attic; Appendices; Index.

Hypervelocity gun. [using both electric and chemical energy for projectile propulsion

NASA Technical Reports Server (NTRS)

Ford, F. C.; Biehl, A. J. (Inventor)

1965-01-01

A velocity amplifier system which uses both electric and chemical energy for projectile propulsion is provided in a compact hypervelocity gun suitable for laboratory use. A relatively heavy layer of a tamping material such as concrete encloses a loop of an electrically conductive material. An explosive charge at least partially surrounding the loop is adapted to collapse the loop upon detonation of the charge. A source of electricity charges the loop through two leads, and an electric switch which is activated by the charge explosive charge, disconnects the leads from the source of electricity and short circuits them. An opening in the tamping material extends to the loop and forms a barrel. The loop, necked down in the opening, forms the sabot on which the projectile is located. When the loop is electrically charged and the explosive detonated, the loop is short circuited and collapsed thus building up a magnetic field which acts as a sabot catcher. The sabot is detached from the loop and the sabot and projectile are accelerated to hypervelocity.

Efforts to Reduce International Space Station Crew Maintenance Time in the Management of the Extravehicular Mobility Unit Transport Loop Water Quality

NASA Technical Reports Server (NTRS)

Etter,David; Rector, Tony; Boyle, robert; Zande, Chris Vande

2012-01-01

The EMU (Extravehicular Mobility Unit) contains a semi-closed-loop re-circulating water circuit (Transport Loop) to absorb heat into a LCVG (Liquid Coolant and Ventilation Garment) worn by the astronaut. A second, single-pass water circuit (Feed-water Loop) provides water to a cooling device (Sublimator) containing porous plates, and that water sublimates through the porous plates to space vacuum. The cooling effect from the sublimation of this water translates to a cooling of the LCVG water that circulates through the Sublimator. The quality of the EMU Transport Loop water is maintained through the use of a water processing kit (ALCLR - Airlock Cooling Loop Remediation) that is used to periodically clean and disinfect the water circuit. Opportunities to reduce crew time associated with ALCLR operations include a detailed review of the historical water quality data for evidence to support an extension to the implementation cycle. Furthermore, an EMU returned after 2-years of use on the ISS (International Space Station) is being used as a test bed to evaluate the results of extended and repeated ALCLR implementation cycles. Finally, design, use and on-orbit location enhancements to the ALCLR kit components are being considered to allow the implementation cycle to occur in parallel with other EMU maintenance and check-out activities, and to extend the life of the ALCLR kit components. These efforts are undertaken to reduce the crew-time and logistics burdens for the EMU, while ensuring the long-term health of the EMU water circuits for a post- Shuttle 6-year service life.

Efforts to Reduce International Space Station Crew Maintenance for the Management of the Extravehicular Mobility Unit Transport Loop Water Quality

NASA Technical Reports Server (NTRS)

Steele, John W.; Etter, David; Rector, Tony; Boyle, Robert; Vandezande, Christopher

2013-01-01

The EMU (Extravehicular Mobility Unit) contains a semi-closed-loop re-circulating water circuit (Transport Loop) to absorb heat into a LCVG (Liquid Coolant and Ventilation Garment) worn by the astronaut. A second, single-pass water circuit (Feed-water Loop) provides water to a cooling device (Sublimator) containing porous plates, and that water sublimates through the porous plates to space vacuum. The cooling effect from the sublimation of this water translates to a cooling of the LCVG water that circulates through the Sublimator. The quality of the EMU Transport Loop water is maintained through the use of a water processing kit (ALCLR Airlock Cooling Loop Remediation) that is used to periodically clean and disinfect the water circuit. Opportunities to reduce crew time associated with on-orbit ALCLR operations include a detailed review of the historical water quality data for evidence to support an extension to the implementation cycle. Furthermore, an EMU returned after 2-years of use on the ISS (International Space Station) is being used as a test bed to evaluate the results of extended and repeated ALCLR implementation cycles. Finally, design, use and on-orbit location enhancements to the ALCLR kit components are being considered to allow the implementation cycle to occur in parallel with other EMU maintenance and check-out activities, and to extend the life of the ALCLR kit components. These efforts are undertaken to reduce the crew-time and logistics burdens for the EMU, while ensuring the long-term health of the EMU water circuits for a post-Shuttle 6-year service life.

Estimating the circuit delay of FPGA with a transfer learning method

NASA Astrophysics Data System (ADS)

Cui, Xiuhai; Liu, Datong; Peng, Yu; Peng, Xiyuan

2017-10-01

With the increase of FPGA (Field Programmable Gate Array, FPGA) functionality, FPGA has become an on-chip system platform. Due to increase the complexity of FPGA, estimating the delay of FPGA is a very challenge work. To solve the problems, we propose a transfer learning estimation delay (TLED) method to simplify the delay estimation of different speed grade FPGA. In fact, the same style different speed grade FPGA comes from the same process and layout. The delay has some correlation among different speed grade FPGA. Therefore, one kind of speed grade FPGA is chosen as a basic training sample in this paper. Other training samples of different speed grade can get from the basic training samples through of transfer learning. At the same time, we also select a few target FPGA samples as training samples. A general predictive model is trained by these samples. Thus one kind of estimation model is used to estimate different speed grade FPGA circuit delay. The framework of TRED includes three phases: 1) Building a basic circuit delay library which includes multipliers, adders, shifters, and so on. These circuits are used to train and build the predictive model. 2) By contrasting experiments among different algorithms, the forest random algorithm is selected to train predictive model. 3) The target circuit delay is predicted by the predictive model. The Artix-7, Kintex-7, and Virtex-7 are selected to do experiments. Each of them includes -1, -2, -2l, and -3 different speed grade. The experiments show the delay estimation accuracy score is more than 92% with the TLED method. This result shows that the TLED method is a feasible delay assessment method, especially in the high-level synthesis stage of FPGA tool, which is an efficient and effective delay assessment method.

Cerebro-cerebellar circuits in autism spectrum disorder.

PubMed

D'Mello, Anila M; Stoodley, Catherine J

2015-01-01

The cerebellum is one of the most consistent sites of abnormality in autism spectrum disorder (ASD) and cerebellar damage is associated with an increased risk of ASD symptoms, suggesting that cerebellar dysfunction may play a crucial role in the etiology of ASD. The cerebellum forms multiple closed-loop circuits with cerebral cortical regions that underpin movement, language, and social processing. Through these circuits, cerebellar dysfunction could impact the core ASD symptoms of social and communication deficits and repetitive and stereotyped behaviors. The emerging topography of sensorimotor, cognitive, and affective subregions in the cerebellum provides a new framework for interpreting the significance of regional cerebellar findings in ASD and their relationship to broader cerebro-cerebellar circuits. Further, recent research supports the idea that the integrity of cerebro-cerebellar loops might be important for early cortical development; disruptions in specific cerebro-cerebellar loops in ASD might impede the specialization of cortical regions involved in motor control, language, and social interaction, leading to impairments in these domains. Consistent with this concept, structural, and functional differences in sensorimotor regions of the cerebellum and sensorimotor cerebro-cerebellar circuits are associated with deficits in motor control and increased repetitive and stereotyped behaviors in ASD. Further, communication and social impairments are associated with atypical activation and structure in cerebro-cerebellar loops underpinning language and social cognition. Finally, there is converging evidence from structural, functional, and connectivity neuroimaging studies that cerebellar right Crus I/II abnormalities are related to more severe ASD impairments in all domains. We propose that cerebellar abnormalities may disrupt optimization of both structure and function in specific cerebro-cerebellar circuits in ASD.

Cerebro-cerebellar circuits in autism spectrum disorder

PubMed Central

D'Mello, Anila M.; Stoodley, Catherine J.

2015-01-01

The cerebellum is one of the most consistent sites of abnormality in autism spectrum disorder (ASD) and cerebellar damage is associated with an increased risk of ASD symptoms, suggesting that cerebellar dysfunction may play a crucial role in the etiology of ASD. The cerebellum forms multiple closed-loop circuits with cerebral cortical regions that underpin movement, language, and social processing. Through these circuits, cerebellar dysfunction could impact the core ASD symptoms of social and communication deficits and repetitive and stereotyped behaviors. The emerging topography of sensorimotor, cognitive, and affective subregions in the cerebellum provides a new framework for interpreting the significance of regional cerebellar findings in ASD and their relationship to broader cerebro-cerebellar circuits. Further, recent research supports the idea that the integrity of cerebro-cerebellar loops might be important for early cortical development; disruptions in specific cerebro-cerebellar loops in ASD might impede the specialization of cortical regions involved in motor control, language, and social interaction, leading to impairments in these domains. Consistent with this concept, structural, and functional differences in sensorimotor regions of the cerebellum and sensorimotor cerebro-cerebellar circuits are associated with deficits in motor control and increased repetitive and stereotyped behaviors in ASD. Further, communication and social impairments are associated with atypical activation and structure in cerebro-cerebellar loops underpinning language and social cognition. Finally, there is converging evidence from structural, functional, and connectivity neuroimaging studies that cerebellar right Crus I/II abnormalities are related to more severe ASD impairments in all domains. We propose that cerebellar abnormalities may disrupt optimization of both structure and function in specific cerebro-cerebellar circuits in ASD. PMID:26594140

Base drive circuit

DOEpatents

Lange, A.C.

1995-04-04

An improved base drive circuit having a level shifter for providing bistable input signals to a pair of non-linear delays. The non-linear delays provide gate control to a corresponding pair of field effect transistors through a corresponding pair of buffer components. The non-linear delays provide delayed turn-on for each of the field effect transistors while an associated pair of transistors shunt the non-linear delays during turn-off of the associated field effect transistor. 2 figures.

Apparatus for and method of monitoring for breached fuel elements

DOEpatents

Gross, K.C.; Strain, R.V.

1981-04-28

This invention teaches improved apparatus for the method of detecting a breach in cladded fuel used in a nuclear reactor. The detector apparatus uses a separate bypass loop for conveying part of the reactor coolant away from the core, and at least three separate delayed-neutron detectors mounted proximate this detector loop. The detectors are spaced apart so that the coolant flow time from the core to each detector is different, and these differences are known. The delayed-neutron activity at the detectors is a function of the delay time after the reaction in the fuel until the coolant carrying the delayed-neutron emitter passes the respective detector. This time delay is broken down into separate components including an isotopic holdup time required for the emitter to move through the fuel from the reaction to the coolant at the breach, and two transit times required for the emitter now in the coolant to flow from the breach to the detector loop and then via the loop to the detector.

Differential transimpedance amplifier circuit for correlated differential amplification

DOEpatents

Gresham, Christopher A [Albuquerque, NM; Denton, M Bonner [Tucson, AZ; Sperline, Roger P [Tucson, AZ

2008-07-22

A differential transimpedance amplifier circuit for correlated differential amplification. The amplifier circuit increase electronic signal-to-noise ratios in charge detection circuits designed for the detection of very small quantities of electrical charge and/or very weak electromagnetic waves. A differential, integrating capacitive transimpedance amplifier integrated circuit comprising capacitor feedback loops performs time-correlated subtraction of noise.

Digital time delay

DOEpatents

Martin, A.D.

1986-05-09

Method and apparatus are provided for generating an output pulse following a trigger pulse at a time delay interval preset with a resolution which is high relative to a low resolution available from supplied clock pulses. A first lumped constant delay provides a first output signal at predetermined interpolation intervals corresponding to the desired high resolution time interval. Latching circuits latch the high resolution data to form a first synchronizing data set. A selected time interval has been preset to internal counters and corrected for circuit propagation delay times having the same order of magnitude as the desired high resolution. Internal system clock pulses count down the counters to generate an internal pulse delayed by an internal which is functionally related to the preset time interval. A second LCD corrects the internal signal with the high resolution time delay. A second internal pulse is then applied to a third LCD to generate a second set of synchronizing data which is complementary with the first set of synchronizing data for presentation to logic circuits. The logic circuits further delay the internal output signal with the internal pulses. The final delayed output signal thereafter enables the output pulse generator to produce the desired output pulse at the preset time delay interval following input of the trigger pulse.

Research on key technologies of LADAR echo signal simulator

NASA Astrophysics Data System (ADS)

Xu, Rui; Shi, Rui; Ye, Jiansen; Wang, Xin; Li, Zhuo

2015-10-01

LADAR echo signal simulator is one of the most significant components of hardware-in-the-loop (HWIL) simulation systems for LADAR, which is designed to simulate the LADAR return signal in laboratory conditions. The device can provide the laser echo signal of target and background for imaging LADAR systems to test whether it is of good performance. Some key technologies are investigated in this paper. Firstly, the 3D model of typical target is built, and transformed to the data of the target echo signal based on ranging equation and targets reflection characteristics. Then, system model and time series model of LADAR echo signal simulator are established. Some influential factors which could induce fixed delay error and random delay error on the simulated return signals are analyzed. In the simulation system, the signal propagating delay of circuits and the response time of pulsed lasers are belong to fixed delay error. The counting error of digital delay generator, the jitter of system clock and the desynchronized between trigger signal and clock signal are a part of random delay error. Furthermore, these system insertion delays are analyzed quantitatively, and the noisy data are obtained. The target echo signals are got by superimposing of the noisy data and the pure target echo signal. In order to overcome these disadvantageous factors, a method of adjusting the timing diagram of the simulation system is proposed. Finally, the simulated echo signals are processed by using a detection algorithm to complete the 3D model reconstruction of object. The simulation results reveal that the range resolution can be better than 8 cm.

The role of the medial prefrontal cortex in trace fear extinction

PubMed Central

Kwapis, Janine L.; Jarome, Timothy J.

2015-01-01

The extinction of delay fear conditioning relies on a neural circuit that has received much attention and is relatively well defined. Whether this established circuit also supports the extinction of more complex associations, however, is unclear. Trace fear conditioning is a better model of complex relational learning, yet the circuit that supports extinction of this memory has received very little attention. Recent research has indicated that trace fear extinction requires a different neural circuit than delay extinction; trace extinction requires the participation of the retrosplenial cortex, but not the amygdala, as noted in a previous study. Here, we tested the roles of the prelimbic and infralimbic regions of the medial prefrontal cortex in trace and delay fear extinction by blocking NMDA receptors during extinction learning. We found that the prelimbic cortex is necessary for trace, but not for delay fear extinction, whereas the infralimbic cortex is involved in both types of extinction. These results are consistent with the idea that trace fear associations require plasticity in multiple cortical areas for successful extinction. Further, the infralimbic cortex appears to play a role in extinction regardless of whether the animal was initially trained in trace or delay conditioning. Together, our results provide new information about how the neural circuits supporting trace and delay fear extinction differ. PMID:25512576

Resonant electrodynamic heating of stellar coronal loops: An LRC circuit analogue

NASA Technical Reports Server (NTRS)

Ionson, J. A.

1980-01-01

The electrodynamic coupling of stellar coronal loops to underlying beta velocity fields. A rigorous analysis revealed that the physics can be represented by a simple yet equivalent LRC circuit analogue. This analogue points to the existence of global structure oscillations which resonantly excite internal field line oscillations at a spatial resonance within the coronal loop. Although the width of this spatial resonance, as well as the induced currents and coronal velocity field, explicitly depend upon viscosity and resistivity, the resonant form of the generalized electrodynamic heating function is virtually independent of irreversibilities. This is a classic feature of high quality resonators that are externally driven by a broad band source of spectral power. Applications to solar coronal loops result in remarkable agreement with observations.

Design and implementation of a simple acousto optic dual control circuit

NASA Astrophysics Data System (ADS)

Li, Biqing; Li, Zhao

2017-04-01

This page proposed a simple light control circuit which designed by using power supply circuit, sonic circuits, electric circuit and delay circuit four parts. The main chip for CD4011, have inside of the four and to complete the sonic or circuit, electric, delay logic circuit. During the day, no matter how much a pedestrian voice, is ever shine light bulb. Dark night, circuit in a body to make the microphone as long as testing noise, and will automatically be bright for pedestrians lighting, several minutes after the automatic and put out, effective energy saving. Applicable scope and the working principle of the circuit principle diagram and given device parameters selection, power saving effect is obvious, at the same time greatly reduce the maintenance quantity, saving money, use effect is good.

T-111 Rankine system corrosion test loop, volume 1

NASA Technical Reports Server (NTRS)

Harrison, R. W.; Hoffman, E. E.; Smith, J. P.

1975-01-01

Results are given of a program whose objective was to determine the performance of refractory metal alloys in a two loop Rankine test system. The test system consisted of a circulating lithium circuit heated to 1230 C maximum transferring heat to a boiling potassium circuit with a 1170 C superheated vapor temperature. The results demonstrate the suitability of the selected refractory alloys to perform from a chemical compatibility standpoint.

Designing Estimator/Predictor Digital Phase-Locked Loops

NASA Technical Reports Server (NTRS)

Statman, J. I.; Hurd, W. J.

1988-01-01

Signal delays in equipment compensated automatically. New approach to design of digital phase-locked loop (DPLL) incorporates concepts from estimation theory and involves decomposition of closed-loop transfer function into estimator and predictor. Estimator provides recursive estimates of phase, frequency, and higher order derivatives of phase with respect to time, while predictor compensates for delay, called "transport lag," caused by PLL equipment and by DPLL computations.

A closed-loop time-alignment system for baseband combining

NASA Technical Reports Server (NTRS)

Feria, Y.

1994-01-01

In baseband combining, the key element is the time alignment of the baseband signals. This article describes a closed-loop time-alignment system that estimates and adjusts the relative delay between two baseband signals received from two different antennas for the signals to be coherently combined. This system automatically determines which signal is advanced and delays it accordingly with a resolution of a sample period. The performance of the loop is analyzed, and the analysis is verified through simulation. The variance of the delay estimates and the signal-to-noise ratio degradation in the simulations agree with the theoretical calculations.

Experimental Apparatus for the Observation of the Topological Change Associated with Dynamical Monodromy

NASA Astrophysics Data System (ADS)

Salmon, Daniel; Nerem, M. Perry; Aubin, Seth; Delos, John

Monodromy means ``once around a path,'' therefore systems that have non-trivial monodromy are systems such that, when taken around a closed circuit in some space, the system has changed state in some way. Classical systems that exhibit non-trivial Hamiltonian monodromy have action and angle variables that are multivalued functions. A family, or loop, of trajectories of this system has a topological change upon traversing a monodromy circuit. We present an experimental apparatus for observing this topological change. A family of particles moving in a cylindrically symmetric champagne-bottle potential exhibits non-trivial Hamiltonian monodromy. At the center of this system is a classically forbidden region. By following a monodromy circuit, a loop of initial conditions on one side of the forbidden region can be made to evolve continuously into a loop that surrounds the forbidden region. We realize this system using a spherical pendulum, having at its end a permanent magnet. Magnetic fields generated by coils can then be used to create the champagne-bottle potential, as well as drive the pendulum through the monodromy circuit.

78 FR 8638 - Self-Regulatory Organizations; National Stock Exchange, Inc.; Notice of Filing and Immediate...

Federal Register 2010, 2011, 2012, 2013, 2014

2013-02-06

... Change To Delay the Operative Date of Rule 11.20A Regarding Market-Wide Circuit Breakers Due to... the market- wide circuit breakers on a pilot basis for a period scheduled to start on February 4, 2013... changed to April 8, 2013. The proposal would delay the operative date of the market-wide circuit breaker...

Finite-dimensional modeling of network-induced delays for real-time control systems

NASA Technical Reports Server (NTRS)

Ray, Asok; Halevi, Yoram

1988-01-01

In integrated control systems (ICS), a feedback loop is closed by the common communication channel, which multiplexes digital data from the sensor to the controller and from the controller to the actuator along with the data traffic from other control loops and management functions. Due to asynchronous time-division multiplexing in the network access protocols, time-varying delays are introduced in the control loop, which degrade the system dynamic performance and are a potential source of instability. The delayed control system is represented by a finite-dimensional, time-varying, discrete-time model which is less complex than the existing continuous-time models for time-varying delays; this approach allows for simpler schemes for analysis and simulation of the ICS.

Multiphase soft switched DC/DC converter and active control technique for fuel cell ripple current elimination

DOEpatents

Lai, Jih-Sheng; Liu, Changrong; Ridenour, Amy

2009-04-14

DC/DC converter has a transformer having primary coils connected to an input side and secondary coils connected to an output side. Each primary coil connects a full-bridge circuit comprising two switches on two legs, the primary coil being connected between the switches on each leg, each full-bridge circuit being connected in parallel wherein each leg is disposed parallel to one another, and the secondary coils connected to a rectifying circuit. An outer loop control circuit that reduces ripple in a voltage reference has a first resistor connected in series with a second resistor connected in series with a first capacitor which are connected in parallel with a second capacitor. An inner loop control circuit that reduces ripple in a current reference has a third resistor connected in series with a fourth resistor connected in series with a third capacitor which are connected in parallel with a fourth capacitor.

Another Nulling Hall-Effect Current-Measuring Circuit

NASA Technical Reports Server (NTRS)

Thibodeau, Phillip E.; Sullender, Craig C.

1993-01-01

Lightweight, low-power circuit provides noncontact measurement of alternating or direct current of many ampheres in main conductor. Advantages of circuit over other nulling Hall-effect current-measuring circuits is stability and accuracy increased by putting both analog-to-digital and digital-to-analog converters in nulling feedback loop. Converters and rest of circuit designed for operation at sampling rate of 100 kHz, but rate changed to alter time or frequency response of circuit.

Ultrahigh-speed clock recovery with optical phase lock loop based on four-wave-mixing in a semiconductor optical amplifier

NASA Astrophysics Data System (ADS)

Kim, Dong Hwan; Kim, Sang Hyuck; Jo, Jae Cheol; Choi, Sang Sam

2000-08-01

A new phase lock loop (PLL) is proposed and demonstrated for clock recovery from 40 Gbps time-division-multiplexed (TDM) optical signal using simple optical phase lock loop circuit. The proposed clock recovery scheme improves the jitter effect in PLL circuit from the clock pulse laser of harmonically-mode locked fiber laser. The cross-correlation component between the optical signal and an optical clock pulse train is detected as a four-wave-mixing (FWM) signal generated in SOA. The lock-in frequency range of the clock recovery is found to be within 10 KHz.

Experimental Verification of AUV (Autonomous Underwater Vehicle) Performance.

DTIC Science & Technology

1988-03-01

7 3 First Order Plant Model 10 4 Closed Loop System Block Diagram 11 5 RLP[Kpz=l,U=0.5] 13 6 RLP[Kpz=I,U=I] 147 RLP[Kpz=0.5,U-0.5] 15 8 RLP[Kpz=0.5,U...circuit. The control circuit would then generate a radio control signal to maneuver the vehicle. 6 *’%4 MUMNT -. %Am -W’ This takes the man out of the loop ...angle, the constant Ky is 0.14i_" IN’ ft-lbf/rad. Estimated values of J and B were determined. The closed loop transfer function Go could then be

Faster Hall-Effect Current-Measuring Circuit

NASA Technical Reports Server (NTRS)

Sullender, Craig C.; Johnson, Daniel D.; Walker, Daniel D.

1993-01-01

Current-measuring circuit operates on Hall-effect-sensing and magnetic-field-nulling principles similar to those described in article, "Nulling Hall-Effect Current-Measuring Circuit" (LEW-15023), but simpler and responds faster. Designed without feedback loop, and analog pulse-width-modulated output indicates measured current. Circuit measures current at frequency higher than bandwidth of its Hall-effect sensor.

Ferrite core coupled slapper detonator apparatus and method

DOEpatents

Boberg, Ralph E.; Lee, Ronald S.; Weingart, Richard C.

1989-01-01

Method and apparatus are provided for coupling a temporally short electric power pulse from a thick flat-conductor power cable into a thin flat-conductor slapper detonator circuit. A first planar and generally circular loop is formed from an end portion of the power cable. A second planar and generally circular loop, of similar diameter, is formed from all or part of the slapper detonator circuit. The two loops are placed together, within a ferrite housing that provides a ferrite path that magnetically couples the two loops. Slapper detonator parts may be incorporated within the ferrite housing. The ferrite housing may be made vacuum and water-tight, with the addition of a hermetic ceramic seal, and provided with an enclosure for protecting the power cable and parts related thereto.

Ferrite core coupled slapper detonator apparatus and method

DOEpatents

Boberg, R.E.; Lee, R.S.; Weingart, R.C.

1989-08-01

Method and apparatus are provided for coupling a temporally short electric power pulse from a thick flat-conductor power cable into a thin flat-conductor slapper detonator circuit. A first planar and generally circular loop is formed from an end portion of the power cable. A second planar and generally circular loop, of similar diameter, is formed from all or part of the slapper detonator circuit. The two loops are placed together, within a ferrite housing that provides a ferrite path that magnetically couples the two loops. Slapper detonator parts may be incorporated within the ferrite housing. The ferrite housing may be made vacuum and water-tight, with the addition of a hermetic ceramic seal, and provided with an enclosure for protecting the power cable and parts related thereto. 10 figs.

Closed-Loop and Activity-Guided Optogenetic Control

PubMed Central

Grosenick, Logan; Marshel, James H.; Deisseroth, Karl

2016-01-01

Advances in optical manipulation and observation of neural activity have set the stage for widespread implementation of closed-loop and activity-guided optical control of neural circuit dynamics. Closing the loop optogenetically (i.e., basing optogenetic stimulation on simultaneously observed dynamics in a principled way) is a powerful strategy for causal investigation of neural circuitry. In particular, observing and feeding back the effects of circuit interventions on physiologically relevant timescales is valuable for directly testing whether inferred models of dynamics, connectivity, and causation are accurate in vivo. Here we highlight technical and theoretical foundations as well as recent advances and opportunities in this area, and we review in detail the known caveats and limitations of optogenetic experimentation in the context of addressing these challenges with closed-loop optogenetic control in behaving animals. PMID:25856490

Noncoherent pseudonoise code tracking performance of spread spectrum receivers

NASA Technical Reports Server (NTRS)

Simon, M. K.

1977-01-01

The optimum design and performance of two noncoherent PN tracking loop configurations, namely, the delay-locked loop and tau-dither loop, are described. In particular, the bandlimiting effects of the bandpass arm filters are considered by demonstrating that for a fixed data rate and data signal-to-noise ratio, there exists an optimum filter bandwidth in the sense of minimizing the loop's tracking jitter. Both the linear and nonlinear loop analyses are presented, and the region of validity of the former relative to the latter is indicated. In addition, numerical results are given for several filter types. For example, assuming ideal bandpass arm filters, it is shown that the tau-dither loop requires approximately 1 dB more signal-to-noise ratio than the delay-locked loop for equal rms tracking jitters.

Base drive circuit

DOEpatents

Lange, Arnold C.

1995-01-01

An improved base drive circuit (10) having a level shifter (24) for providing bistable input signals to a pair of non-linear delays (30, 32). The non-linear delays (30, 32) provide gate control to a corresponding pair of field effect transistors (100, 106) through a corresponding pair of buffer components (88, 94). The non-linear delays (30, 32) provide delayed turn-on for each of the field effect transistors (100, 106) while an associated pair of transistors (72, 80) shunt the non-linear delays (30, 32) during turn-off of the associated field effect transistor (100, 106).

Adaptive control system for line-commutated inverters

NASA Technical Reports Server (NTRS)

Dolland, C. R.; Bailey, D. A. (Inventor)

1983-01-01

A control system for a permanent magnet motor driven by a multiphase line commutated inverter is provided with integration for integrating the back EMF of each phase of the motor. This is used in generating system control signals for an inverter gate logic using a sync and firing angle (alpha) control generator connected to the outputs of the integrators. A precision full wave rectifier provides a speed control feedback signal to a phase delay rectifier via a gain and loop compensation circuit and to the integrators for adaptive control of the attenuation of low frequencies by the integrators as a function of motor speed. As the motor speed increases, the attenuation of low frequency components by the integrators is increased to offset the gain of the integrators to spurious low frequencies.

Ultrahigh-speed phaselocked-loop type clock recovery circuit using a travelling-wave laser diode amplifier as a 50 GHz phase detector

NASA Astrophysics Data System (ADS)

Kawanishi, S.; Takara, H.; Saruwatari, M.; Kitoh, T.

1993-09-01

Successful operation of a phase-locked loop is demonstrated using a traveling-wave laser-diode amplifier as a 50 GHz phase detector. Optical gain modulation in the laser diode amplifier and an all-optical clock multiplication technique using a silica-based guided-wave optical circuit are used to achieve the extremely high-speed operation. Also discussed is the possibility of more than 100 GHz operation.

Oscillatory stimuli differentiate adapting circuit topologies

PubMed Central

Rahi, Sahand Jamal; Larsch, Johannes; Pecani, Kresti; Katsov, Alexander Y.; Mansouri, Nahal; Tsaneva-Atanasova, Krasimira; Sontag, Eduardo D.; Cross, Frederick R.

2017-01-01

Adapting pathways consist of negative feedback loops (NFLs) or incoherent feedforward loops (IFFLs), which we show can be differentiated using oscillatory stimulation: NFLs but not IFFLs generically show ‘refractory period stabilization’ or ‘period skipping’. Using these signatures and genetic rewiring we identified the circuit dominating cell cycle timing in yeast. In C. elegans AWA neurons we uncovered a Ca2+-NFL, diffcult to find by other means, especially in wild-type, intact animals. (70 words) PMID:28846089

Cortico-Striatal-Thalamic Loop Circuits of the Salience Network: A Central Pathway in Psychiatric Disease and Treatment.

PubMed

Peters, Sarah K; Dunlop, Katharine; Downar, Jonathan

2016-01-01

The salience network (SN) plays a central role in cognitive control by integrating sensory input to guide attention, attend to motivationally salient stimuli and recruit appropriate functional brain-behavior networks to modulate behavior. Mounting evidence suggests that disturbances in SN function underlie abnormalities in cognitive control and may be a common etiology underlying many psychiatric disorders. Such functional and anatomical abnormalities have been recently apparent in studies and meta-analyses of psychiatric illness using functional magnetic resonance imaging (fMRI) and voxel-based morphometry (VBM). Of particular importance, abnormal structure and function in major cortical nodes of the SN, the dorsal anterior cingulate cortex (dACC) and anterior insula (AI), have been observed as a common neurobiological substrate across a broad spectrum of psychiatric disorders. In addition to cortical nodes of the SN, the network's associated subcortical structures, including the dorsal striatum, mediodorsal thalamus and dopaminergic brainstem nuclei, comprise a discrete regulatory loop circuit. The SN's cortico-striato-thalamo-cortical loop increasingly appears to be central to mechanisms of cognitive control, as well as to a broad spectrum of psychiatric illnesses and their available treatments. Functional imbalances within the SN loop appear to impair cognitive control, and specifically may impair self-regulation of cognition, behavior and emotion, thereby leading to symptoms of psychiatric illness. Furthermore, treating such psychiatric illnesses using invasive or non-invasive brain stimulation techniques appears to modulate SN cortical-subcortical loop integrity, and these effects may be central to the therapeutic mechanisms of brain stimulation treatments in many psychiatric illnesses. Here, we review clinical and experimental evidence for abnormalities in SN cortico-striatal-thalamic loop circuits in major depression, substance use disorders (SUD), anxiety disorders, schizophrenia and eating disorders (ED). We also review emergent therapeutic evidence that novel invasive and non-invasive brain stimulation treatments may exert therapeutic effects by normalizing abnormalities in the SN loop, thereby restoring the capacity for cognitive control. Finally, we consider a series of promising directions for future investigations on the role of SN cortico-striatal-thalamic loop circuits in the pathophysiology and treatment of psychiatric disorders.

Cortico-Striatal-Thalamic Loop Circuits of the Salience Network: A Central Pathway in Psychiatric Disease and Treatment

PubMed Central

Peters, Sarah K.; Dunlop, Katharine; Downar, Jonathan

2016-01-01

The salience network (SN) plays a central role in cognitive control by integrating sensory input to guide attention, attend to motivationally salient stimuli and recruit appropriate functional brain-behavior networks to modulate behavior. Mounting evidence suggests that disturbances in SN function underlie abnormalities in cognitive control and may be a common etiology underlying many psychiatric disorders. Such functional and anatomical abnormalities have been recently apparent in studies and meta-analyses of psychiatric illness using functional magnetic resonance imaging (fMRI) and voxel-based morphometry (VBM). Of particular importance, abnormal structure and function in major cortical nodes of the SN, the dorsal anterior cingulate cortex (dACC) and anterior insula (AI), have been observed as a common neurobiological substrate across a broad spectrum of psychiatric disorders. In addition to cortical nodes of the SN, the network’s associated subcortical structures, including the dorsal striatum, mediodorsal thalamus and dopaminergic brainstem nuclei, comprise a discrete regulatory loop circuit. The SN’s cortico-striato-thalamo-cortical loop increasingly appears to be central to mechanisms of cognitive control, as well as to a broad spectrum of psychiatric illnesses and their available treatments. Functional imbalances within the SN loop appear to impair cognitive control, and specifically may impair self-regulation of cognition, behavior and emotion, thereby leading to symptoms of psychiatric illness. Furthermore, treating such psychiatric illnesses using invasive or non-invasive brain stimulation techniques appears to modulate SN cortical-subcortical loop integrity, and these effects may be central to the therapeutic mechanisms of brain stimulation treatments in many psychiatric illnesses. Here, we review clinical and experimental evidence for abnormalities in SN cortico-striatal-thalamic loop circuits in major depression, substance use disorders (SUD), anxiety disorders, schizophrenia and eating disorders (ED). We also review emergent therapeutic evidence that novel invasive and non-invasive brain stimulation treatments may exert therapeutic effects by normalizing abnormalities in the SN loop, thereby restoring the capacity for cognitive control. Finally, we consider a series of promising directions for future investigations on the role of SN cortico-striatal-thalamic loop circuits in the pathophysiology and treatment of psychiatric disorders. PMID:28082874

High resolution digital delay timer

DOEpatents

Martin, Albert D.

1988-01-01

Method and apparatus are provided for generating an output pulse following a trigger pulse at a time delay interval preset with a resolution which is high relative to a low resolution available from supplied clock pulses. A first lumped constant delay (20) provides a first output signal (24) at predetermined interpolation intervals corresponding to the desired high resolution time interval. Latching circuits (26, 28) latch the high resolution data (24) to form a first synchronizing data set (60). A selected time interval has been preset to internal counters (142, 146, 154) and corrected for circuit propagation delay times having the same order of magnitude as the desired high resolution. Internal system clock pulses (32, 34) count down the counters to generate an internal pulse delayed by an interval which is functionally related to the preset time interval. A second LCD (184) corrects the internal signal with the high resolution time delay. A second internal pulse is then applied to a third LCD (74) to generate a second set of synchronizing data (76) which is complementary with the first set of synchronizing data (60) for presentation to logic circuits (64). The logic circuits (64) further delay the internal output signal (72) to obtain a proper phase relationship of an output signal (80) with the internal pulses (32, 34). The final delayed output signal (80) thereafter enables the output pulse generator (82) to produce the desired output pulse (84) at the preset time delay interval following input of the trigger pulse (10, 12).

Phase-locked loops. [in analog and digital circuits communication system

NASA Technical Reports Server (NTRS)

Gupta, S. C.

1975-01-01

An attempt to systematically outline the work done in the area of phase-locked loops which are now used in modern communication system design is presented. The analog phase-locked loops are well documented in several books but discrete, analog-digital, and digital phase-locked loop work is scattered. Apart from discussing the various analysis, design, and application aspects of phase-locked loops, a number of references are given in the bibliography.

On the Origin of Tremor in Parkinson’s Disease

PubMed Central

Dovzhenok, Andrey; Rubchinsky, Leonid L.

2012-01-01

The exact origin of tremor in Parkinson’s disease remains unknown. We explain why the existing data converge on the basal ganglia-thalamo-cortical loop as a tremor generator and consider a conductance-based model of subthalamo-pallidal circuits embedded into a simplified representation of the basal ganglia-thalamo-cortical circuit to investigate the dynamics of this loop. We show how variation of the strength of dopamine-modulated connections in the basal ganglia-thalamo-cortical loop (representing the decreasing dopamine level in Parkinson’s disease) leads to the occurrence of tremor-like burst firing. These tremor-like oscillations are suppressed when the connections are modulated back to represent a higher dopamine level (as it would be the case in dopaminergic therapy), as well as when the basal ganglia-thalamo-cortical loop is broken (as would be the case for ablative anti-parkinsonian surgeries). Thus, the proposed model provides an explanation for the basal ganglia-thalamo-cortical loop mechanism of tremor generation. The strengthening of the loop leads to tremor oscillations, while the weakening or disconnection of the loop suppresses them. The loop origin of parkinsonian tremor also suggests that new tremor-suppression therapies may have anatomical targets in different cortical and subcortical areas as long as they are within the basal ganglia-thalamo-cortical loop. PMID:22848541

On inappropriately used neuronal circuits as a possible basis of the ``loop-swimming'' behaviour of fish under reduced gravity: a theoretical study

NASA Astrophysics Data System (ADS)

Anken, R. H.; Rahmann, H.

One hypothesis for the explanation of the so-called ``loop-swimming'' behaviour in fish when being subjected to reduced gravity assumes that the activities of the differently weighted otoliths of the two labyrinths are well compensated on ground but that a functional asymmetry is induced in weightlessness, resulting in a tonus asymmetry of the body and by this generating the ``loop-swimming'' behaviour. The basis of this abnormal behaviour has to be searched for in the central nervous system (cns), where the signal-transduction from the inner ear- related signal internalisation to the signal response takes place. Circuits within the CNS of fish, that could possibly generate the ``loop-swimming'', might be as follows: An asymmetric activation of vestibulospinal circuits would directly result in a tonus asymmetry of the body. An asymmetric activation of the oculomotor nucleus would generate an asymmetrical rotation of the eyes. This would cause in its turn asymmetric images on the two retinas, which were forwarded to the diencephalic accessory optic system (AOS). It is the task of the AOS to stabilize retinal images, thereby involving the cerebellum, which is the main integration center for sensory and motor modalities. With this, the cerebellar output would generate a tonus asymmetry of the body in order to make the body of the fish follow its eyes. Such movements (especially when assuming an open loop control) would end up in the aforementioned ``loop-swimming'' behaviour.

System Control for the Transitional DCS.

DTIC Science & Technology

1978-12-01

hour. The equipment destroyed includes the TTC-39 switch, all RF and multiplex equipment, emergency power equipment, distribution frames, antennal and...switch executes loop test to Rhein Main ULS, activating a local alarm at Donnersberg. Since restoral activity has not already been completed, alarm is...ITEM COMMENTS (BYTES) Loop ID Switch number and physical loop number 6 (BCD). Loop circuit CCSD 8 Telephone number 3 Location Physical location of

Digital phase-locked-loop speed sensor for accuracy improvement in analog speed controls. [feedback control and integrated circuits

NASA Technical Reports Server (NTRS)

Birchenough, A. G.

1975-01-01

A digital speed control that can be combined with a proportional analog controller is described. The stability and transient response of the analog controller were retained and combined with the long-term accuracy of a crystal-controlled integral controller. A relatively simple circuit was developed by using phase-locked-loop techniques and total error storage. The integral digital controller will maintain speed control accuracy equal to that of the crystal reference oscillator.

Comparison of in-situ delay monitors for use in Adaptive Voltage Scaling

NASA Astrophysics Data System (ADS)

Pour Aryan, N.; Heiß, L.; Schmitt-Landsiedel, D.; Georgakos, G.; Wirnshofer, M.

2012-09-01

In Adaptive Voltage Scaling (AVS) the supply voltage of digital circuits is tuned according to the circuit's actual operating condition, which enables dynamic compensation to PVTA variations. By exploiting the excessive safety margins added in state-of-the-art worst-case designs considerable power saving is achieved. In our approach, the operating condition of the circuit is monitored by in-situ delay monitors. This paper presents different designs to implement the in-situ delay monitors capable of detecting late but still non-erroneous transitions, called Pre-Errors. The developed Pre-Error monitors are integrated in a 16 bit multiplier test circuit and the resulting Pre-Error AVS system is modeled by a Markov chain in order to determine the power saving potential of each Pre-Error detection approach.

Multiplexing Readout of TES Microcalorimeters Based on Analog Baseband Feedback

DOE Office of Scientific and Technical Information (OSTI.GOV)

Takei, Y.; Yamasaki, N.Y; Mitsuda, K.

2009-12-16

A TES microcalorimeter array is a promising spectrometer with excellent energy resolution and a moderate imaging capability. To realize a large format array in space, multiplexing the TES signals at the low tempersture stage is mandatory. We are developing frequency division multiplexing (FDM) based on baseband feedback technique. In FDM, each TES is AC-biased with a different carrier frequency. Signals from several pixels are summed and then read out by one SQUID. The maximum number of multiplexed pixels are limited by the frequency band in which the SQUID can be operated in a flux-locked loop, which is {approx}1 MHz withmore » standard flux-locked loop circuit. In the baseband feedback, the signal ({approx}10 kHz band) from the TES is once demodulated. Then a reconstructed copy of the modulated signal with an appropriate phase is fed back to the SQUID input coil to maintain an approximately constant magnetic flux. This can be implemented even for large cable delays and automatically suppresses the carrier. We developed a prototype electronics for the baseband feedback based on an analog phase sensitive detector (PSD) and a multiplier. Combined with Seiko 80-SSA SQUID amp, open-loop gain of 8 has been obtained for 10 kHz baseband signal at 5 MHz carrier frequency, with a moderate noise contribution of 27pA/{radical}(Hz) at input.« less

Molecular genetic analysis of circadian timekeeping in Drosophila

PubMed Central

Hardin, Paul E.

2014-01-01

A genetic screen for mutants that alter circadian rhythms in Drosophila identified the first clock gene - the period (per) gene. The per gene is a central player within a transcriptional feedback loop that represents the core mechanism for keeping circadian time in Drosophila and other animals. The per feedback loop, or core loop, is interlocked with the Clock (Clk) feedback loop, but whether the Clk feedback loop contributes to circadian timekeeping is not known. A series of distinct molecular events are thought to control transcriptional feedback in the core loop. The time it takes to complete these events should take much less than 24h, thus delays must be imposed at different steps within the core loop. As new clock genes are identified, the molecular mechanisms responsible for these delays have been revealed in ever-increasing detail, and provide an in depth accounting of how transcriptional feedback loops keep circadian time. The phase of these feedback loops shift to maintain synchrony with environmental cycles, the most reliable of which is light. Although a great deal is known about cell-autonomous mechanisms of light-induced phase shifting by CRYPTOCHROME (CRY), much less is known about non-cell autonomous mechanisms. CRY mediates phase shifts through an uncharacterized mechanism in certain brain oscillator neurons, and carries out a dual role as a photoreceptor and transcription factor in other tissues. Here I will review how transcriptional feedback loops function to keep time in Drosophila, how they impose delays to maintain a 24h cycle, and how they maintain synchrony with environmental light:dark cycles. The transcriptional feedback loops that keep time in Drosophila are well conserved in other animals, thus what we learn about these loops in Drosophila should continue to provide insight into the operation of analogous transcriptional feedback loops in other animals. PMID:21924977

In-line Microwave Warmer for Blood and Intravenous Fluids.

DTIC Science & Technology

1989-12-14

circuit was designed and tested. This circuit uses a digitally controlled optically coupled Triac , a thyristor device, which acts as a switch to allow...three sites of the circuit : Inlet Port of Heating Chamber Interior Path of Heating Chamber Outlet Port of Heating Chamber 4) Feedback Control Mechanism...accomplished through use of a closed loop test circuit depicted in Figure 1-2. This test circuit can be used to heat iv fluids or blood on a continuous

The Performance of A Sampled Data Delay Lock Loop Implemented with a Kalman Loop Filter.

DTIC Science & Technology

1980-01-01

que for analysis is computer simulation. Other techniques include state variable techniques and z-transform methods. Since the Kalman filter is linear...LOGIC NOT SHOWN Figure 2. Block diagram of the sampled data delay lock loop (SDDLL) Es A/ A 3/A/ Figure 3. Sampled error voltage ( Es ) as a function of...from a sum of two components. The first component is the previous filtered es - timate advanced one step forward by the state transition matrix. The 8

A digital optical phase-locked loop for diode lasers based on field programmable gate array.

PubMed

Xu, Zhouxiang; Zhang, Xian; Huang, Kaikai; Lu, Xuanhui

2012-09-01

We have designed and implemented a highly digital optical phase-locked loop (OPLL) for diode lasers in atom interferometry. The three parts of controlling circuit in this OPLL, including phase and frequency detector (PFD), loop filter and proportional integral derivative (PID) controller, are implemented in a single field programmable gate array chip. A structure type compatible with the model MAX9382∕MCH12140 is chosen for PFD and pipeline and parallelism technology have been adapted in PID controller. Especially, high speed clock and twisted ring counter have been integrated in the most crucial part, the loop filter. This OPLL has the narrow beat note line width below 1 Hz, residual mean-square phase error of 0.14 rad(2) and transition time of 100 μs under 10 MHz frequency step. A main innovation of this design is the completely digitalization of the whole controlling circuit in OPLL for diode lasers.

A digital optical phase-locked loop for diode lasers based on field programmable gate array

NASA Astrophysics Data System (ADS)

Xu, Zhouxiang; Zhang, Xian; Huang, Kaikai; Lu, Xuanhui

2012-09-01

We have designed and implemented a highly digital optical phase-locked loop (OPLL) for diode lasers in atom interferometry. The three parts of controlling circuit in this OPLL, including phase and frequency detector (PFD), loop filter and proportional integral derivative (PID) controller, are implemented in a single field programmable gate array chip. A structure type compatible with the model MAX9382/MCH12140 is chosen for PFD and pipeline and parallelism technology have been adapted in PID controller. Especially, high speed clock and twisted ring counter have been integrated in the most crucial part, the loop filter. This OPLL has the narrow beat note line width below 1 Hz, residual mean-square phase error of 0.14 rad2 and transition time of 100 μs under 10 MHz frequency step. A main innovation of this design is the completely digitalization of the whole controlling circuit in OPLL for diode lasers.

Impact of Temporal Masking of Flip-Flop Upsets on Soft Error Rates of Sequential Circuits

NASA Astrophysics Data System (ADS)

Chen, R. M.; Mahatme, N. N.; Diggins, Z. J.; Wang, L.; Zhang, E. X.; Chen, Y. P.; Liu, Y. N.; Narasimham, B.; Witulski, A. F.; Bhuva, B. L.; Fleetwood, D. M.

2017-08-01

Reductions in single-event (SE) upset (SEU) rates for sequential circuits due to temporal masking effects are evaluated. The impacts of supply voltage, combinational-logic delay, flip-flop (FF) SEU performance, and particle linear energy transfer (LET) values are analyzed for SE cross sections of sequential circuits. Alpha particles and heavy ions with different LET values are used to characterize the circuits fabricated at the 40-nm bulk CMOS technology node. Experimental results show that increasing the delay of the logic circuit present between FFs and decreasing the supply voltage are two effective ways of reducing SE error rates for sequential circuits for particles with low LET values due to temporal masking. SEU-hardened FFs benefit less from temporal masking than conventional FFs. Circuit hardening implications for SEU-hardened and unhardened FFs are discussed.

Programmable Differential Delay Circuit With Fine Delay Adjustment

DOEpatents

DeRyckere, John F.; Jenkins, Philip Nord; Cornett, Frank Nolan

2002-07-09

Circuitry that provides additional delay to early arriving signals such that all data signals arrive at a receiving latch with same path delay. The delay of a forwarded clock reference is also controlled such that the capturing clock edge will be optimally positioned near quadrature (depending on latch setup/hold requirements). The circuitry continuously adapts to data and clock path delay changes and digital filtering of phase measurements reduce errors brought on by jittering data edges. The circuitry utilizes only the minimum amount of delay necessary to achieve objective thereby limiting any unintended jitter. Particularly, this programmable differential delay circuit with fine delay adjustment is designed to allow the skew between ASICS to be minimized. This includes skew between data bits, between data bits and clocks as well as minimizing the overall skew in a channel between ASICS.

A finite state machine read-out chip for integrated surface acoustic wave sensors

NASA Astrophysics Data System (ADS)

Rakshit, Sambarta; Iliadis, Agis A.

2015-01-01

A finite state machine based integrated sensor circuit suitable for the read-out module of a monolithically integrated SAW sensor on Si is reported. The primary sensor closed loop consists of a voltage controlled oscillator (VCO), a peak detecting comparator, a finite state machine (FSM), and a monolithically integrated SAW sensor device. The output of the system oscillates within a narrow voltage range that correlates with the SAW pass-band response. The period of oscillation is of the order of the SAW phase delay. We use timing information from the FSM to convert SAW phase delay to an on-chip 10 bit digital output operating on the principle of time to digital conversion (TDC). The control inputs of this digital conversion block are generated by a second finite state machine operating under a divided system clock. The average output varies with changes in SAW center frequency, thus tracking mass sensing events in real time. Based on measured VCO gain of 16 MHz/V our system will convert a 10 kHz SAW frequency shift to a corresponding mean voltage shift of 0.7 mV. A corresponding shift in phase delay is converted to a one or two bit shift in the TDC output code. The system can handle alternate SAW center frequencies and group delays simply by adjusting the VCO control and TDC delay control inputs. Because of frequency to voltage and phase to digital conversion, this topology does not require external frequency counter setups and is uniquely suitable for full monolithic integration of autonomous sensor systems and tags.

PARALYZER FOR PULSE HEIGHT DISTRIBUTION ANALYZER

DOEpatents

Fairstein, E.

1960-01-19

A paralyzer circuit is described for use with a pulseheight distribution analyzer to prevent the analyzer from counting overlapping pulses where they would serve to provide a false indication. The paralyzer circuit comprises a pair of cathode-coupled amplifiers for amplifying pulses of opposite polarity. Diodes are provided having their anodes coupled to the separate outputs of the amplifiers to produce only positive signals, and a trigger circuit is coupled to the diodes ior operation by input pulses of either polarity from the amplifiers. A delay network couples the output of the trigger circuit for delaying the pulses.

Integrated Circuit Wear out Prediction and Recycling Detection using Radio Frequency Distinct Native Attribute Features

DTIC Science & Technology

2016-12-22

105 A.1 Main Loop ... loop monitoring for preventative maintenance rather than early replacement based on statistical projections or replacement-after- failure schemes. IC...estimates, RF-DNA may provide a means to track an IC’s physical degradation during actual use. Monitoring an IC’s degradation in a closed loop fashion

Pulsatile desynchronizing delayed feedback for closed-loop deep brain stimulation

PubMed Central

Lysyansky, Borys; Rosenblum, Michael; Pikovsky, Arkady; Tass, Peter A.

2017-01-01

High-frequency (HF) deep brain stimulation (DBS) is the gold standard for the treatment of medically refractory movement disorders like Parkinson’s disease, essential tremor, and dystonia, with a significant potential for application to other neurological diseases. The standard setup of HF DBS utilizes an open-loop stimulation protocol, where a permanent HF electrical pulse train is administered to the brain target areas irrespectively of the ongoing neuronal dynamics. Recent experimental and clinical studies demonstrate that a closed-loop, adaptive DBS might be superior to the open-loop setup. We here combine the notion of the adaptive high-frequency stimulation approach, that aims at delivering stimulation adapted to the extent of appropriately detected biomarkers, with specifically desynchronizing stimulation protocols. To this end, we extend the delayed feedback stimulation methods, which are intrinsically closed-loop techniques and specifically designed to desynchronize abnormal neuronal synchronization, to pulsatile electrical brain stimulation. We show that permanent pulsatile high-frequency stimulation subjected to an amplitude modulation by linear or nonlinear delayed feedback methods can effectively and robustly desynchronize a STN-GPe network of model neurons and suggest this approach for desynchronizing closed-loop DBS. PMID:28273176

A Power Hardware-in-the-Loop Platform with Remote Distribution Circuit Cosimulation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Palmintier, Bryan; Lundstrom, Blake; Chakraborty, Sudipta

2015-04-01

This paper demonstrates the use of a novel cosimulation architecture that integrates hardware testing using Power Hardware-in-the-Loop (PHIL) with larger-scale electric grid models using off-the-shelf, non-PHIL software tools. This architecture enables utilities to study the impacts of emerging energy technologies on their system and manufacturers to explore the interactions of new devices with existing and emerging devices on the power system, both without the need to convert existing grid models to a new platform or to conduct in-field trials. The paper describes an implementation of this architecture for testing two residential-scale advanced solar inverters at separate points of common coupling.more » The same hardware setup is tested with two different distribution feeders (IEEE 123 and 8500 node test systems) modeled using GridLAB-D. In addition to simplifying testing with multiple feeders, the architecture demonstrates additional flexibility with hardware testing in one location linked via the Internet to software modeling in a remote location. In testing, inverter current, real and reactive power, and PCC voltage are well captured by the co-simulation platform. Testing of the inverter advanced control features is currently somewhat limited by the software model time step (1 sec) and tested communication latency (24 msec). Overshoot induced oscillations are observed with volt/VAR control delays of 0 and 1.5 sec, while 3.4 sec and 5.5 sec delays produced little or no oscillation. These limitations could be overcome using faster modeling and communication within the same co-simulation architecture.« less

Radiation Tolerant, Low Noise Phase Locked Loops in 65 nm CMOS Technology

NASA Astrophysics Data System (ADS)

Prinzie, Jeffrey; Christiansen, Jorgen; Moreira, Paulo; Steyaert, Michiel; Leroux, Paul

2018-04-01

This work presents an introduction to radiation hardened Phase Locked Loops (PLLs) for nuclear and high-energy physics application. An experimental circuit has been fabricated and irradiated with Xrays up to 600 Mrad. Heavy ions with an LET between 3.2 and 69.2 MeV.cm2/mg were used to verify the SEU cross section of the devices. A Two-photon Absorption (TPA) laser facility has been used to provide detailed results on the SEU sensitivity. The presented circuit employs TMR in the digital logic and an asynchronous phase-frequency detector (PFD) is presented. The PLL has a ringand LC-oscillator to be compared experimentally. The circuit has been fabricated in a 65 nm CMOS technology.

Corepressive interaction and clustering of degrade-and-fire oscillators

PubMed Central

Fernandez, Bastien; Tsimring, Lev S.

2016-01-01

Strongly nonlinear degrade-and-fire (DF) oscillations may emerge in genetic circuits having a delayed negative feedback loop as their core element. Here we study the synchronization of DF oscillators coupled through a common repressor field. For weak coupling, initially distinct oscillators remain desynchronized. For stronger coupling, oscillators can be forced to wait in the repressed state until the global repressor field is sufficiently degraded, and then they fire simultaneously forming a synchronized cluster. Our analytical theory provides necessary and sufficient conditions for clustering and specifies the maximum number of clusters that can be formed in the asymptotic regime. We find that in the thermodynamic limit a phase transition occurs at a certain coupling strength from the weakly clustered regime with only microscopic clusters to a strongly clustered regime where at least one giant cluster has to be present. PMID:22181453

The Electron Runaround: Understanding Electric Circuit Basics through a Classroom Activity

ERIC Educational Resources Information Center

Singh, Vandana

2010-01-01

Several misconceptions abound among college students taking their first general physics course, and to some extent pre-engineering physics students, regarding the physics and applications of electric circuits. Analogies used in textbooks, such as those that liken an electric circuit to a piped closed loop of water driven by a water pump, do not…

46 CFR 169.670 - Circuit breakers.

Code of Federal Regulations, 2010 CFR

2010-10-01

... Gross Tons § 169.670 Circuit breakers. Each circuit breaker must be of the manually reset type designed for— (a) Inverse time delay; (b) Instantaneous short circuit protection; and (c) Repeated opening of... 46 Shipping 7 2010-10-01 2010-10-01 false Circuit breakers. 169.670 Section 169.670 Shipping COAST...

A bipolar population counter using wave pipelining to achieve 2.5 x normal clock frequency

NASA Technical Reports Server (NTRS)

Wong, Derek C.; De Micheli, Giovanni; Flynn, Michael J.; Huston, Robert E.

1992-01-01

Wave pipelining is a technique for pipelining digital systems that can increase clock frequency in practical circuits without increasing the number of storage elements. In wave pipelining, multiple coherent waves of data are sent through a block of combinational logic by applying new inputs faster than the delay through the logic. The throughput of a 63-b CML population counter was increased from 97 to 250 MHz using wave pipelining. The internal circuit is flowthrough combinational logic. Novel CAD methods have balanced all input-to-output paths to about the same delay. This allows multiple data waves to propagate in sequence when the circuit is clocked faster than its propagation delay.

Low-common-mode differential amplifier

NASA Technical Reports Server (NTRS)

Morrison, S.

1980-01-01

Outputs of differential amplifier are excellently matched in phase and amplitude over wide range of frequencies. Common mode feedback loop offsets differences between two signal paths. Possible applications of circuit are in oscilloscopes, integrated circuit logic tester, and other self contained instruments.

Adaptive piezoelectric sensoriactuators for active structural acoustic control

NASA Astrophysics Data System (ADS)

Vipperman, Jeffrey Stuart

1997-09-01

A new transducer technology with application to active control systems, modal analysis, and autonomous system health monitoring, is brought to fruition in this work. It has the advantages of being lightweight, potentially cost-effective, self-tuning, has negligible dynamics, and most importantly (from a robustness perspective), it provides a colocated sensor/actuator pair. The transducer consists of a piezoceramic element which serves as both an actuator and a sensor and will be referred to in this work as a sensoriactuator. Simple, adaptive signal processing in conjunction with a voltage controlled amplifier, reference capacitor, and a common-mode rejection circuit extract the mechanical response from the total response of the piezoelectric sensoriactuator for sensing. The digital portion of the adaptive piezoelectric sensoriactuator merely serves to tune the circuit, avoiding the potentially destabilizing effects of introducing a digital delay in the signal path, when used for feedback control applications. Adaptive compensation of the sensoriactuator is necessary since the signal to noise ratio is typically greater than 40 dB, making it prohibitive to tune the circuit manually. In addition, the constitutive properties of piezoceramics vary with time and environment, necessitating that the circuit be periodically re-tuned. The analog portion of the hardware is based upon op-amp circuits and an AD632 analog multiplier chip, which serves as both a voltage controlled amplifier (VCA) and a common mode rejection (CMR) circuit. A single coefficient least-mean square (LMS) adaptive filter continuously adjusts the gain of the VCA circuit as necessary. Nonideal behavior of piezoceramics is discussed along with methods to counter the consequential deterioration in circuit performance. A multiple input multiple output (MIMO) implementation of the adaptive piezoelectric sensoriactuator is developed using orthogonal white noise training signals for each sensoriactuator. Two piezostructures were used to demonstrate and verify the adaptive piezoelectric sensoriactuator, a cantilevered beam and a simply-supported plate. The experimental open- loop results compare well with theory. A preliminary closed-loop rate controller applied to the cantilevered beam demonstrates simultaneous control and adaptation of the piezoelectric sensoriactuator. Lastly, [/cal H]2 optimal feedback Active Structural Acoustic Control (ASAC) is demonstrated using the adaptive piezoelectric sensoriactuators and the simply- supported plate test bed. A cost function is formulated based upon control effort and predicted radiated acoustic power. Radiation filters are created to predict acoustic power based on the self and mutual radiation efficiencies of the plate modes to be controlled. Both static output feedback and state-feedback compensation as well as dynamic (Linear Quadratic Gaussian) compensation are investigated and compared analytically. The importance of choosing an appropriate spatial aperture for the piezoceramic transducer for static compensation is discussed. Finally, multivariable Active Vibration Control (AVC) and ASAC are implemented experimentally on a simply-supported plate test bed using an array of four Adaptive Piezoelectric Sensoriactuators as the control sensors and actuators. Unfavorable high-frequency response from the given piezoceramic transducers required that dynamic, Linear Quadratic Gaussian (LQG) compensation be used to achieve good control performance.

Chaos in the fractional order logistic delay system: Circuit realization and synchronization

DOE Office of Scientific and Technical Information (OSTI.GOV)

Baskonus, Haci Mehmet; Hammouch, Zakia; Mekkaoui, Toufik

2016-06-08

In this paper, we present a numerical study and a circuit design to prove existence of chaos in the fractional order Logistic delay system. In addition, we investigate an active control synchronization scheme in this system. Numerical and cicruit simulations show the effectiveness and feasibility of this method.

Binary phase lock loops for simplified OMEGA receivers

NASA Technical Reports Server (NTRS)

Burhans, R. W.

1974-01-01

A sampled binary phase lock loop is proposed for periodically correcting OMEGA receiver internal clocks. The circuit is particularly simple to implement and provides a means of generating long range 3.4 KHz difference frequency lanes from simultaneous pair measurements.

Response of Nuclear Power Plant Instrumentation Cables Exposed to Fire Conditions.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Muna, Alice Baca; LaFleur, Chris Bensdotter; Brooks, Dusty Marie

This report presents the results of instrumentation cable tests sponsored by the US Nuclear Regulatory Commission (NRC) Office of Nuclear Regulatory Research and performed at Sandia National Laboratories (SNL). The goal of the tests was to assess thermal and electrical response behavior under fire-exposure conditions for instrumentation cables and circuits. The test objective was to assess how severe radiant heating conditions surrounding an instrumentation cable affect current or voltage signals in an instrumentation circuit. A total of thirty-nine small-scale tests were conducted. Ten different instrumentation cables were tested, ranging from one conductor to eight-twisted pairs. Because the focus of themore » tests was thermoset (TS) cables, only two of the ten cables had thermoplastic (TP) insulation and jacket material and the remaining eight cables were one of three different TS insulation and jacket material. Two instrumentation cables from previous cable fire testing were included, one TS and one TP. Three test circuits were used to simulate instrumentation circuits present in nuclear power plants: a 4–20 mA current loop, a 10–50 mA current loop and a 1–5 VDC voltage loop. A regression analysis was conducted to determine key variables affecting signal leakage time.« less

Cyclic voltammetry of apple fruits: Memristors in vivo.

PubMed

Volkov, Alexander G; Nyasani, Eunice K; Tuckett, Clayton; Blockmon, Avery L; Reedus, Jada; Volkova, Maya I

2016-12-01

A memristor is a resistor with memory that exhibits a pinched hysteretic relationship in cyclic voltammetry. Recently, we have found memristors in the electrical circuitry of plants and seeds. There are no publications in literature about the possible existence of memristors and electrical differentiators in fruits. Here we found that the electrostimulation of Golden Delicious or Arkansas Black apple fruits by bipolar periodic waves induces hysteresis loops with pinched points in cyclic voltammograms at low frequencies between 0.1MHz and 1MHz. At high frequencies of 1kHz, the pinched hysteresis loop transforms to a non-pinched hysteresis loop instead of a single line I=V/R for ideal memristors because the amplitude of electrical current depends on capacitance of a fruit's tissue and electrodes, frequency and direction of scanning. Electrostimulation of electrical circuits in apple fruits by periodic voltage waves also induces electrotonic potential propagation due to cell-to-cell electrical coupling with electrical differentiators. A differentiator is an electrical circuit in which the output of the circuit is approximately directly proportional to the rate of change of the input. The information gained from electrostimulation can be used to elucidate and to observe electrochemical and electrophysiological properties of electrical circuits in fruits. Copyright © 2016 Elsevier B.V. All rights reserved.

Management of the Post-Shuttle Extravehicular Mobility Unit (EMU) Water Circuits

NASA Technical Reports Server (NTRS)

Steele, John W.; Etter, David; Rector, Tony; Hill, Terry; Wells, Kevin

2011-01-01

The EMU incorporates two separate water circuits for the rejection of metabolic heat from the astronaut and the cooling of electrical components. The first (the Transport Water Loop) circulates in a semi-closed-loop manner and absorbs heat into a Liquid Coolant and Ventilation Garment (LCVG) warn by the astronaut. The second (the Feed Water Loop) provides water to a cooling device (Sublimator) with a porous plate, and that water subsequently sublimates to space vacuum. The cooling effect from the sublimation of this water translates to a cooling of the LCVG water that circulates through the Sublimator. Efforts are underway to streamline the use of a water processing kit (ALCLR) that is being used to periodically clean and disinfect the Transport Loop Water. Those efforts include a fine tuning of the duty cycle based on a review of prior performance data as well as an assessment of a fixed installation of this kit into the EMU backpack or within on-orbit EMU interface hardware. Furthermore, testing is being conducted to ensure compatibility between the International Space Station (ISS) Water Processor Assembly (WPA) effluent and the EMU Sublimator as a prelude to using the WPA effluent as influent to the EMU Feed Water loop. This work is undertaken to reduce the crew-time and logistics burdens for the EMU, while ensuring the long-term health of the EMU water circuits for a post-Shuttle 6-year service life.

Management of the Post-Shuttle Extravehicular Mobility Unit (EMU) Water Circuits

NASA Technical Reports Server (NTRS)

Steele, John W.; Etter, David; Rector, Tony; Hill, Terry; Wells, Kevin

2012-01-01

The EMU incorporates two separate water circuits for the rejection of metabolic heat from the astronaut and the cooling of electrical components. The first (the Transport Water Loop) circulates in a semi-closed-loop manner and absorbs heat into a Liquid Coolant and Ventilation Garment (LCVG) worn by the astronaut. The second (the Feed-water Loop) provides water to a cooling device (Sublimator) with a porous plate, and that water subsequently sublimates to space vacuum. The cooling effect from the sublimation of this water translates to a cooling of the LCVG water that circulates through the Sublimator. Efforts are underway to streamline the use of a water processing kit (ALCLR) that is being used to periodically clean and disinfect the Transport Loop Water. Those efforts include a fine tuning of the duty cycle based on a review of prior performance data as well as an assessment of a fixed installation of this kit into the EMU backpack, within on-orbit EMU interface hardware or as a stand-alone unit. Furthermore, testing is being conducted to ensure compatibility between the International Space Station (ISS) Water Processor Assembly (WPA) effluent and the EMU Sublimator as a prelude to using the WPA effluent as influent to the EMU Feed Water loop. This work is undertaken to reduce the crewtime and logistics burdens for the EMU, while ensuring the long-term health of the EMU water circuits for a 6-year service life.

Apparatus for and method of monitoring for breached fuel elements

DOEpatents

Gross, Kenny C.; Strain, Robert V.

1983-01-01

This invention teaches improved apparatus for the method of detecting a breach in cladded fuel used in a nuclear reactor. The detector apparatus uses a separate bypass loop for conveying part of the reactor coolant away from the core, and at least three separate delayed-neutron detectors mounted proximate this detector loop. The detectors are spaced apart so that the coolant flow time from the core to each detector is different, and these differences are known. The delayed-neutron activity at the detectors is a function of the dealy time after the reaction in the fuel until the coolant carrying the delayed-neutron emitter passes the respective detector. This time delay is broken down into separate components including an isotopic holdup time required for the emitter to move through the fuel from the reaction to the coolant at the breach, and two transit times required for the emitter now in the coolant to flow from the breach to the detector loop and then via the loop to the detector. At least two of these time components are determined during calibrated operation of the reactor. Thereafter during normal reactor operation, repeated comparisons are made by the method of regression approximation of the third time component for the best-fit line correlating measured delayed-neutron activity against activity that is approximated according to specific equations. The equations use these time-delay components and known parameter values of the fuel and of the part and emitting daughter isotopes.

A COLD FLARE WITH DELAYED HEATING

DOE Office of Scientific and Technical Information (OSTI.GOV)

Fleishman, Gregory D.; Pal'shin, Valentin D.; Lysenko, Alexandra L.

2016-05-10

Recently, a number of peculiar flares have been reported that demonstrate significant nonthermal particle signatures with low, if any, thermal emission, which implies a close association of the observed emission with the primary energy release/electron acceleration region. This paper presents a flare that appears “cold” at the impulsive phase, while displaying delayed heating later on. Using hard X-ray data from Konus- Wind , microwave observations by SSRT, RSTN, NoRH, and NoRP, context observations, and three-dimensional modeling, we study the energy release, particle acceleration, and transport, and the relationships between the nonthermal and thermal signatures. The flaring process is found tomore » involve the interaction between a small loop and a big loop with the accelerated particles divided roughly equally between them. Precipitation of the electrons from the small loop produced only a weak thermal response because the loop volume was small, while the electrons trapped in the big loop lost most of their energy in the coronal part of the loop, which resulted in coronal plasma heating but no or only weak chromospheric evaporation, and thus unusually weak soft X-ray emission. The energy losses of the fast electrons in the big tenuous loop were slow, which resulted in the observed delay of the plasma heating. We determined that the impulsively accelerated electron population had a beamed angular distribution in the direction of the electric force along the magnetic field of the small loop. The accelerated particle transport in the big loop was primarily mediated by turbulent waves, which is similar to other reported cold flares.« less

Basic Guidelines for Application of Performance Standards to Commissioning of DCS Digital Circuits

DTIC Science & Technology

1992-06-01

V6Z2J7 Canada Gustavo A. Cubas E. 1 Engineered Systems, Inc 2 Seccion De Transmission ATTN: Mr. David Gilfillan Direccion De Ingenieria Y Proyectos 14775...buffering, and and filter delay (for a voice circuit). Propagation delay is independent of data rate, while buffering delay is inversely proportional to...Complexe Des Jardins, 15th Fl. 171 N. Covington Drive 75 Rene Levesque West Bloomingdale, IL 60108 Montreal, PG H2Z Canada DISTRIBUTION LIST Department

Cryogen-free dilution refrigerators

NASA Astrophysics Data System (ADS)

Uhlig, K.

2012-12-01

We review briefly our first cryogen-free dilution refrigerator (CF-DR) which was precooled by a GM cryocooler. We then show how today's dry DRs with pulse tube precooling have developed. A few examples of commercial DRs are explained and noteworthy features pointed out. Thereby we describe the general advantages of cryogen-free DRs, but also show where improvements are still desirable. At present, our dry DR has a base temperature of 10 mK and a cooling capacity of 700 μW at a mixing chamber temperature of 100 mK. In our cryostat, in most recent work, an additional refrigeration loop was added to the dilution circuit. This 4He circuit has a lowest temperature of about 1 K and a refrigeration capacity of up to 100 mW at temperatures slightly above 1 K; the dilution circuit and the 4He circuit can be run separately or together. The purpose of this additional loop is to increase the cooling capacity for experiments where the cooling power of the still of the DR is not sufficient to cool cold amplifiers and cables, e.g. in studies on superconducting quantum circuits or astrophysical applications.

Gas turbine cooling system

DOEpatents

Bancalari, Eduardo E.

2001-01-01

A gas turbine engine (10) having a closed-loop cooling circuit (39) for transferring heat from the hot turbine section (16) to the compressed air (24) produced by the compressor section (12). The closed-loop cooling system (39) includes a heat exchanger (40) disposed in the flow path of the compressed air (24) between the outlet of the compressor section (12) and the inlet of the combustor (14). A cooling fluid (50) may be driven by a pump (52) located outside of the engine casing (53) or a pump (54) mounted on the rotor shaft (17). The cooling circuit (39) may include an orifice (60) for causing the cooling fluid (50) to change from a liquid state to a gaseous state, thereby increasing the heat transfer capacity of the cooling circuit (39).

Experimental diagnostics and modeling of inductive phenomena at low frequencies in impedance spectra of proton exchange membrane fuel cells

NASA Astrophysics Data System (ADS)

Pivac, Ivan; Šimić, Boris; Barbir, Frano

2017-10-01

Representation of fuel cell processes by equivalent circuit models, involving resistance and capacitance elements representing activation losses on both anode and cathode in series with resistance representing ohmic losses, cannot capture and explain the inductive loop that may show up at low frequencies in Nyquist diagram representation of the electrochemical impedance spectra. In an attempt to explain the cause of the low-frequency inductive loop and correlate it with the processes within the fuel cell electrodes, a novel equivalent circuit model of a Proton Exchange Membrane (PEM) fuel cell has been proposed and experimentally verified here in detail. The model takes into account both the anode and the cathode, and has an additional resonant loop on each side, comprising of a resistance, capacitance and inductance in parallel representing the processes within the catalyst layer. Using these additional circuit elements, more accurate and better fits to experimental impedance data in the wide frequency range at different current densities, cell temperatures, humidity of gases, air flow stoichiometries and backpressures were obtained.

A Magnetic Circuit Demonstration.

ERIC Educational Resources Information Center

Vanderkooy, John; Lowe, June

1995-01-01

Presents a demonstration designed to illustrate Faraday's, Ampere's, and Lenz's laws and to reinforce the concepts through the analysis of a two-loop magnetic circuit. Can be made dramatic and challenging for sophisticated students but is suitable for an introductory course in electricity and magnetism. (JRH)

Compensating measured intra-wafer ring oscillator stage delay with intra-wafer exposure dose corrections

NASA Astrophysics Data System (ADS)

Verhaegen, Staf; Nackaerts, Axel; Dusa, Mircea; Carpaij, Rene; Vandenberghe, Geert; Finders, Jo

2006-03-01

The purpose of this paper is to use measurements on real working devices to derive more information than typically measured by the classic line-width measurement techniques. The first part of the paper will discuss the principle of the measurements with a ring oscillator, a circuit used to measure the speed of elementary logic gates. These measurements contribute to the understanding of the exact timing dependencies in circuits, which is of utmost importance for the design and simulation of these circuits. When connecting an odd number of digital inverting stages in a ring, the circuit has no stable digital state but acts as an analog oscillator with the oscillation frequency dependent on the analog propagation delay of the signals through the stages. By varying some conditions during a litho step, the delay change caused by the process condition change can be measured very accurately. The response of the ring oscillator delay to exposure dose is measured and presented in this paper together with a comparison of measured line-width values of the poly gate lines. The second part of the paper will focus on improving the intra-wafer variation of the stage delay. A number of ring oscillators are put in a design at different slit and scan locations. 200mm wafers are processed with 48 full dies present. From the intra-wafer delay fingerprint and the dose sensitivity of the delay an intra-wafer dose correction, also called a dose recipe, is calculated. This dose recipe is used on the scanner to compensate for effects that are the root cause for the delay profile; including reticle and processing such as track, etch and annealing.

Cyber-Physical Test Platform for Microgrids: Combining Hardware, Hardware-in-the-Loop, and Network-Simulator-in-the-Loop

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nelson, Austin; Chakraborty, Sudipta; Wang, Dexin

This paper presents a cyber-physical testbed, developed to investigate the complex interactions between emerging microgrid technologies such as grid-interactive power sources, control systems, and a wide variety of communication platforms and bandwidths. The cyber-physical testbed consists of three major components for testing and validation: real time models of a distribution feeder model with microgrid assets that are integrated into the National Renewable Energy Laboratory's (NREL) power hardware-in-the-loop (PHIL) platform; real-time capable network-simulator-in-the-loop (NSIL) models; and physical hardware including inverters and a simple system controller. Several load profiles and microgrid configurations were tested to examine the effect on system performance withmore » increasing channel delays and router processing delays in the network simulator. Testing demonstrated that the controller's ability to maintain a target grid import power band was severely diminished with increasing network delays and laid the foundation for future testing of more complex cyber-physical systems.« less

Four-junction superconducting circuit

PubMed Central

Qiu, Yueyin; Xiong, Wei; He, Xiao-Ling; Li, Tie-Fu; You, J. Q.

2016-01-01

We develop a theory for the quantum circuit consisting of a superconducting loop interrupted by four Josephson junctions and pierced by a magnetic flux (either static or time-dependent). In addition to the similarity with the typical three-junction flux qubit in the double-well regime, we demonstrate the difference of the four-junction circuit from its three-junction analogue, including its advantages over the latter. Moreover, the four-junction circuit in the single-well regime is also investigated. Our theory provides a tool to explore the physical properties of this four-junction superconducting circuit. PMID:27356619

Design and characterization of a 20 Gbit/s clock recovery circuit

NASA Astrophysics Data System (ADS)

Monteiro, Paulo M.; Matos, J. N.; Gameiro, Atilio M. S.; da Rocha, Jose F.

1995-02-01

In this communication we report the design of a clock recovery circuit produced for the 20 Gbit/s demonstrator of the RACE 2011 project `TRAVEL' of the European Community. The clock recovery circuit is based on an open loop structure using a dielectric resonator narrow bandpass filter with a high quality factor. A detailed electrical characterization of the circuit and also its sensitivity to temperature and detuning variations are presented. The experimental results show that the circuit is a very attractive solution for the forthcoming STM-128 optical links.

Prediction-based control for LTI systems with uncertain time-varying delays and partial state knowledge

NASA Astrophysics Data System (ADS)

Léchappé, V.; Moulay, E.; Plestan, F.

2018-06-01

The stability of a prediction-based controller for linear time-invariant (LTI) systems is studied in the presence of time-varying input and output delays. The uncertain delay case is treated as well as the partial state knowledge case. The reduction method is used in order to prove the convergence of the closed-loop system including the state observer, the predictor and the plant. Explicit conditions that guarantee the closed-loop stability are given, thanks to a Lyapunov-Razumikhin analysis. Simulations illustrate the theoretical results.

Optical injection phase-lock loops

NASA Astrophysics Data System (ADS)

Bordonalli, Aldario Chrestani

Locking techniques have been widely applied for frequency synchronisation of semiconductor lasers used in coherent communication and microwave signal generation systems. Two main locking techniques, the optical phase-lock loop (OPLL) and optical injection locking (OIL) are analysed in this thesis. The principal limitations on OPLL performance result from the loop propagation delay, which makes difficult the implementation of high gain and wide bandwidth loops, leading to poor phase noise suppression performance and requiring the linewidths of the semiconductor laser sources to be less than a few megahertz for practical values of loop delay. The OIL phase noise suppression is controlled by the injected power. The principal limitations of the OIL implementation are the finite phase error under locked conditions and the narrow stable locking range the system provides at injected power levels required to reduce the phase noise output of semiconductor lasers significantly. This thesis demonstrates theoretically and experimentally that it is possible to overcome the limitations of OPLL and OIL systems by combining them, to form an optical injection phase-lock loop (OIPLL). The modelling of an OIPLL system is presented and compared with the equivalent OPLL and OIL results. Optical and electrical design of an homodyne OIPLL is detailed. Experimental results are given which verify the theoretical prediction that the OIPLL would keep the phase noise suppression as high as that of the OIL system over a much wider stable locking range, even with wide linewidth lasers and long loop delays. The experimental results for lasers with summed linewidth of 36 MHz and a loop delay of 15 ns showed measured phase error variances as low as 0.006 rad2 (500 MHz bandwidth) for locking bandwidths greater than 26 GHz, compared with the equivalent OPLL phase error variance of around 1 rad2 (500 MHz bandwidth) and the equivalent OIL locking bandwidth of less than 1.2 GHz.

Fixed-base simulator study of the effect of time delays in visual cues on pilot tracking performance

NASA Technical Reports Server (NTRS)

Queijo, M. J.; Riley, D. R.

1975-01-01

Factors were examined which determine the amount of time delay acceptable in the visual feedback loop in flight simulators. Acceptable time delays are defined as delays which significantly affect neither the results nor the manner in which the subject 'flies' the simulator. The subject tracked a target aircraft as it oscillated sinusoidally in a vertical plane only. The pursuing aircraft was permitted five degrees of freedom. Time delays of from 0.047 to 0.297 second were inserted in the visual feedback loop. A side task was employed to maintain the workload constant and to insure that the pilot was fully occupied during the experiment. Tracking results were obtained for 17 aircraft configurations having different longitudinal short-period characteristics. Results show a positive correlation between improved handling qualities and a longer acceptable time delay.

A digital optical phase-locked loop for diode lasers based on field programmable gate array

DOE Office of Scientific and Technical Information (OSTI.GOV)

Xu Zhouxiang; Zhang Xian; Huang Kaikai

2012-09-15

We have designed and implemented a highly digital optical phase-locked loop (OPLL) for diode lasers in atom interferometry. The three parts of controlling circuit in this OPLL, including phase and frequency detector (PFD), loop filter and proportional integral derivative (PID) controller, are implemented in a single field programmable gate array chip. A structure type compatible with the model MAX9382/MCH12140 is chosen for PFD and pipeline and parallelism technology have been adapted in PID controller. Especially, high speed clock and twisted ring counter have been integrated in the most crucial part, the loop filter. This OPLL has the narrow beat notemore » line width below 1 Hz, residual mean-square phase error of 0.14 rad{sup 2} and transition time of 100 {mu}s under 10 MHz frequency step. A main innovation of this design is the completely digitalization of the whole controlling circuit in OPLL for diode lasers.« less

Realisation of all 16 Boolean logic functions in a single magnetoresistance memory cell

NASA Astrophysics Data System (ADS)

Gao, Shuang; Yang, Guang; Cui, Bin; Wang, Shouguo; Zeng, Fei; Song, Cheng; Pan, Feng

2016-06-01

Stateful logic circuits based on next-generation nonvolatile memories, such as magnetoresistance random access memory (MRAM), promise to break the long-standing von Neumann bottleneck in state-of-the-art data processing devices. For the successful commercialisation of stateful logic circuits, a critical step is realizing the best use of a single memory cell to perform logic functions. In this work, we propose a method for implementing all 16 Boolean logic functions in a single MRAM cell, namely a magnetoresistance (MR) unit. Based on our experimental results, we conclude that this method is applicable to any MR unit with a double-hump-like hysteresis loop, especially pseudo-spin-valve magnetic tunnel junctions with a high MR ratio. Moreover, after simply reversing the correspondence between voltage signals and output logic values, this method could also be applicable to any MR unit with a double-pit-like hysteresis loop. These results may provide a helpful solution for the final commercialisation of MRAM-based stateful logic circuits in the near future.Stateful logic circuits based on next-generation nonvolatile memories, such as magnetoresistance random access memory (MRAM), promise to break the long-standing von Neumann bottleneck in state-of-the-art data processing devices. For the successful commercialisation of stateful logic circuits, a critical step is realizing the best use of a single memory cell to perform logic functions. In this work, we propose a method for implementing all 16 Boolean logic functions in a single MRAM cell, namely a magnetoresistance (MR) unit. Based on our experimental results, we conclude that this method is applicable to any MR unit with a double-hump-like hysteresis loop, especially pseudo-spin-valve magnetic tunnel junctions with a high MR ratio. Moreover, after simply reversing the correspondence between voltage signals and output logic values, this method could also be applicable to any MR unit with a double-pit-like hysteresis loop. These results may provide a helpful solution for the final commercialisation of MRAM-based stateful logic circuits in the near future. Electronic supplementary information (ESI) available. See DOI: 10.1039/c6nr03169b

Safe arming system for two-explosive munitions

DOEpatents

Jaroska, Miles F.; Niven, William A.; Morrison, Jasper J.

1978-01-01

A system for safely and positively detonating high-explosive munitions, including a source of electrical signals, a split-phase square-loop transformer responsive solely to a unique series of signals from the source for charging an energy storage circuit through a voltage doubling circuit, and a spark-gap trigger for initiating discharge of the energy in the storage circuit to actuate a detonator and thereby fire the munitions.

Cognitive-motor interactions of the basal ganglia in development

PubMed Central

Leisman, Gerry; Braun-Benjamin, Orit; Melillo, Robert

2014-01-01

Neural circuits linking activity in anatomically segregated populations of neurons in subcortical structures and the neocortex throughout the human brain regulate complex behaviors such as walking, talking, language comprehension, and other cognitive functions associated with frontal lobes. The basal ganglia, which regulate motor control, are also crucial elements in the circuits that confer human reasoning and adaptive function. The basal ganglia are key elements in the control of reward-based learning, sequencing, discrete elements that constitute a complete motor act, and cognitive function. Imaging studies of intact human subjects and electrophysiologic and tracer studies of the brains and behavior of other species confirm these findings. We know that the relation between the basal ganglia and the cerebral cortical region allows for connections organized into discrete circuits. Rather than serving as a means for widespread cortical areas to gain access to the motor system, these loops reciprocally interconnect a large and diverse set of cerebral cortical areas with the basal ganglia. Neuronal activity within the basal ganglia associated with motor areas of the cerebral cortex is highly correlated with parameters of movement. Neuronal activity within the basal ganglia and cerebellar loops associated with the prefrontal cortex is related to the aspects of cognitive function. Thus, individual loops appear to be involved in distinct behavioral functions. Damage to the basal ganglia of circuits with motor areas of the cortex leads to motor symptoms, whereas damage to the subcortical components of circuits with non-motor areas of the cortex causes higher-order deficits. In this report, we review some of the anatomic, physiologic, and behavioral findings that have contributed to a reappraisal of function concerning the basal ganglia and cerebellar loops with the cerebral cortex and apply it in clinical applications to attention deficit/hyperactivity disorder (ADHD) with biomechanics and a discussion of retention of primitive reflexes being highly associated with the condition. PMID:24592214

Fast, Low-Power, Hysteretic Level-Detector Circuit

NASA Technical Reports Server (NTRS)

Arditti, Mordechai

1993-01-01

Circuit for detection of preset levels of voltage or current intended to replace standard fast voltage comparator. Hysteretic analog/digital level detector operates at unusually low power with little sacrifice of speed. Comprises low-power analog circuit and complementary metal oxide/semiconductor (CMOS) digital circuit connected in overall closed feedback loop to decrease rise and fall times, provide hysteresis, and trip-level control. Contains multiple subloops combining linear and digital feedback. Levels of sensed signals and hysteresis level easily adjusted by selection of components to suit specific application.

Updating Procedures Can Reorganize the Neural Circuit Supporting a Fear Memory.

PubMed

Kwapis, Janine L; Jarome, Timothy J; Ferrara, Nicole C; Helmstetter, Fred J

2017-07-01

Established memories undergo a period of vulnerability following retrieval, a process termed 'reconsolidation.' Recent work has shown that the hypothetical process of reconsolidation is only triggered when new information is presented during retrieval, suggesting that this process may allow existing memories to be modified. Reconsolidation has received increasing attention as a possible therapeutic target for treating disorders that stem from traumatic memories, yet little is known about how this process changes the original memory. In particular, it is unknown whether reconsolidation can reorganize the neural circuit supporting an existing memory after that memory is modified with new information. Here, we show that trace fear memory undergoes a protein synthesis-dependent reconsolidation process following exposure to a single updating trial of delay conditioning. Further, this reconsolidation-dependent updating process appears to reorganize the neural circuit supporting the trace-trained memory, so that it better reflects the circuit supporting delay fear. Specifically, after a trace-to-delay update session, the amygdala is now required for extinction of the updated memory but the retrosplenial cortex is no longer required for retrieval. These results suggest that updating procedures could be used to force a complex, poorly defined memory circuit to rely on a better-defined neural circuit that may be more amenable to behavioral or pharmacological manipulation. This is the first evidence that exposure to new information can fundamentally reorganize the neural circuit supporting an existing memory.

Aging analysis of high performance FinFET flip-flop under Dynamic NBTI simulation configuration

NASA Astrophysics Data System (ADS)

Zainudin, M. F.; Hussin, H.; Halim, A. K.; Karim, J.

2018-03-01

A mechanism known as Negative-bias Temperature Instability (NBTI) degrades a main electrical parameters of a circuit especially in terms of performance. So far, the circuit design available at present are only focussed on high performance circuit without considering the circuit reliability and robustness. In this paper, the main circuit performances of high performance FinFET flip-flop such as delay time, and power were studied with the presence of the NBTI degradation. The aging analysis was verified using a 16nm High Performance Predictive Technology Model (PTM) based on different commands available at Synopsys HSPICE. The results shown that the circuit under the longer dynamic NBTI simulation produces the highest impact in the increasing of gate delay and decrease in the average power reduction from a fresh simulation until the aged stress time under a nominal condition. In addition, the circuit performance under a varied stress condition such as temperature and negative stress gate bias were also studied.

Phase-locked tracking loops for LORAN-C

NASA Technical Reports Server (NTRS)

Burhans, R. W.

1978-01-01

Portable battery operated LORAN-C receivers were fabricated to evaluate simple envelope detector methods with hybrid analog to digital phase locked loop sensor processors. The receivers are used to evaluate LORAN-C in general aviation applications. Complete circuit details are given for the experimental sensor and readout system.

Stability analysis and compensation of a boost regulator with two-loop control

NASA Technical Reports Server (NTRS)

Wester, G. W.

1974-01-01

A useful stability measure has been demonstrated by Wester (1973) for switching regulators with a single feedback loop by applying the Nyquist criterion to the approximate loop gain determined by a time-averaging technique. This approach is extended and applied to the characterization, stability analysis, and compensation design of a switching regulator with two-loop control. The role and relative significance of each control loop is clarified on the basis of a description of circuit operation, and the major and minor loops are identified. In view of the inapplicability of linear feedback theory, describing functions of the feedback loops and power stage are derived, using small-signal analysis. Several phenomena revealed from an analysis of the major loop gain are discussed.

Micro EEG/ECG signal’s chopper-stabilization amplifying chip for novel dry-contact electrode

NASA Astrophysics Data System (ADS)

Sun, Jianhui; Wang, Chunxing; Wang, Gongtang; Wang, Jinhui; Hua, Qing; Cheng, Chuanfu; Cai, Xinxia; Yin, Tao; Yu, Yang; Yang, Haigang; Li, Dengwang

2017-02-01

Facing the body’s EEG (electroencephalograph, 0.5–100 Hz, 5–100 μV) and ECG’s (electrocardiogram, < 100 {Hz}, 0.01–5 mV) micro signal detection requirement, this paper develops a pervasive application micro signal detection ASIC chip with the chopping modulation/demodulation method. The chopper-stabilization circuit with the RRL (ripple reduction loop) circuit is to suppress the ripple voltage, which locates at the single-stage amplifier’s outputting terminal. The single-stage chopping core’s noise has been suppressed too, and it is beneficial for suppressing noises of post-circuit. The chopping core circuit uses the PFB (positive feedback loop) to increase the inputting resistance, and the NFB (negative feedback loop) to stabilize the 40 dB intermediate frequency gain. The cascaded switch-capacitor sample/hold circuit has been used for deleting spike noises caused by non-ideal MOS switches, and the VGA/BPF (voltage gain amplifier/band pass filter) circuit is used to tune the chopper system’s gain/bandwidth digitally. Assisted with the designed novel dry-electrode, the real test result of the chopping amplifying circuit gives some critical parameters: 8.1 μW/channel, 0.8 μVrms (@band-width = 100 Hz), 4216–11220 times digitally tuning gain range, etc. The data capture system uses the NI CO’s data capturing DAQmx interface, and the captured micro EEG/ECG’s waves are real-time displayed with the PC-Labview. The proposed chopper system is a unified EEG/ECG signal’s detection instrument and has a critical real application value. Project supported by the National Natural Science Foundation of China (Nos. 61527815, 31500800, 61501426, 61471342), the National Key Basic Research Plan (No. 2014CB744600), the Beijing Science and Technology Plan (No. Z141100000214002), and the Chinese Academy of Sciences’ Key Project (No. KJZD-EW-L11-2).

Stability analysis of an autocatalytic protein model

NASA Astrophysics Data System (ADS)

Lee, Julian

2016-05-01

A self-regulatory genetic circuit, where a protein acts as a positive regulator of its own production, is known to be the simplest biological network with a positive feedback loop. Although at least three components—DNA, RNA, and the protein—are required to form such a circuit, stability analysis of the fixed points of this self-regulatory circuit has been performed only after reducing the system to a two-component system, either by assuming a fast equilibration of the DNA component or by removing the RNA component. Here, stability of the fixed points of the three-component positive feedback loop is analyzed by obtaining eigenvalues of the full three-dimensional Hessian matrix. In addition to rigorously identifying the stable fixed points and saddle points, detailed information about the system can be obtained, such as the existence of complex eigenvalues near a fixed point.

Design of a 9-loop quasi-exponential waveform generator

NASA Astrophysics Data System (ADS)

Banerjee, Partha; Shukla, Rohit; Shyam, Anurag

2015-12-01

We know in an under-damped L-C-R series circuit, current follows a damped sinusoidal waveform. But if a number of sinusoidal waveforms of decreasing time period, generated in an L-C-R circuit, be combined in first quarter cycle of time period, then a quasi-exponential nature of output current waveform can be achieved. In an L-C-R series circuit, quasi-exponential current waveform shows a rising current derivative and thereby finds many applications in pulsed power. Here, we have described design and experiment details of a 9-loop quasi-exponential waveform generator. In that, design details of magnetic switches have also been described. In the experiment, output current of 26 kA has been achieved. It has been shown that how well the experimentally obtained output current profile matches with the numerically computed output.

Design of a 9-loop quasi-exponential waveform generator.

PubMed

Banerjee, Partha; Shukla, Rohit; Shyam, Anurag

2015-12-01

We know in an under-damped L-C-R series circuit, current follows a damped sinusoidal waveform. But if a number of sinusoidal waveforms of decreasing time period, generated in an L-C-R circuit, be combined in first quarter cycle of time period, then a quasi-exponential nature of output current waveform can be achieved. In an L-C-R series circuit, quasi-exponential current waveform shows a rising current derivative and thereby finds many applications in pulsed power. Here, we have described design and experiment details of a 9-loop quasi-exponential waveform generator. In that, design details of magnetic switches have also been described. In the experiment, output current of 26 kA has been achieved. It has been shown that how well the experimentally obtained output current profile matches with the numerically computed output.

Simple system for locating ground loops.

PubMed

Bellan, P M

2007-06-01

A simple low-cost system for rapid identification of the cables causing ground loops in complex instrumentation configurations is described. The system consists of an exciter module that generates a 100 kHz ground loop current and a detector module that determines which cable conducts this test current. Both the exciter and detector are magnetically coupled to the ground circuit so there is no physical contact to the instrumentation system under test.

Is ultraviolet radiation on haemodialysis RO water beneficial?

PubMed

Stragier, A

2005-01-01

The quality of dialysis fluids has become increasingly important in the treatment of HD patients. Purified water represents over 95% of its volume. Bacterial and endotoxin content of Reverse Osmosis (RO) water is usually kept under control by bacterial filters, inserted in the distribution departure loop, and by monthly disinfection of the distribution circuit; the simpler the circuit, the better. This paper reports 12 years experience during which Ultraviolet Irradiation (UV) has replaced bacterial filters. To keep the bacterial growth under control in a complex RO water circuit (including a tank and multiple loops) a simple UV lamp was inserted in the departure line. It proved sufficient to keep bacterial count within AAMI norms. Failure of the UV lamp was associated with a rise of up to 500 cfu/ml in the last (fourth week) before routine disinfection. Normal levels were again obtained after replacement of the UV lamp. Six years later, a second UV lamp was added on the return loop. Bacterial counts and endotoxin levels in RO water promptly fell to <1 cfu/ml and <0.125 EU, till today. It is concluded that UV lamps should be favoured over bacterial filters in systems that are not disinfected daily, such as the RO water circuit. The principle of UV irradiation is explained and its advantage over bacterial filters is discussed. Future possible applications of UV are presented.

The constant current loop: A new paradigm for resistance signal conditioning

NASA Astrophysics Data System (ADS)

Anderson, Karl F.

1994-02-01

A practical single constant current loop circuit for the signal conditioning of variable-resistance transducers has been synthesized, analyzed, and demonstrated. The strain gage and the resistance temperature detector are examples of variable-resistance sensors. Lead wires connect variable-resistance sensors to remotely located signal-conditioning hardware. The presence of lead wires in the conventional Wheatstone bridge signal-conditioning circuit introduces undesired effects that reduce the quality of the data from the remote sensors. A practical approach is presented for suppressing essentially all lead wire resistance effects while indicating only the change in resistance value. Theoretical predictions supported by laboratory testing confirm the following features of the approach: (1) dc response; (2) the electrical output is unaffected by extremely large variation in the resistance of any or all lead wires; (3) the electrical output remains zero for no change in gage resistance; (4) the electrical output is inherently linear with respect to gage resistance change; (5) the sensitivity is double that of a Wheatstone bridge circuit; and (6) the same excitation wires can serve multiple independent gages. An adaptation of current loop circuit is presented that simultaneously provides an output signal voltage directly proportional to transducer resistance change and provides temperature information that is unaffected by transducer and lead wire resistance variations. These innovations are the subject of NASA patent applications.

The constant current loop: A new paradigm for resistance signal conditioning

NASA Astrophysics Data System (ADS)

Anderson, Karl F.

1992-10-01

A practical single constant current loop circuit for the signal conditioning of variable resistance transducers has been synthesized, analyzed, and demonstrated. The strain gage and the resistance temperature device are examples of variable resistance sensors. Lead wires connect variable resistance sensors to remotely located signal conditioning hardware. The presence of lead wires in the conventional Wheatstone bridge signal conditioning circuit introduces undesired effects that reduce the quality of the data from the remote sensors. A practical approach is presented for suppressing essentially all lead wire resistance effects while indicating only the change in resistance value. Theoretical predictions supported by laboratory testing confirm the following features of the approach: (1) dc response; (2) the electrical output is unaffected by extremely large variations in the resistance of any or all lead wires; (3) the electrical output remains zero for no change in gage resistance; (4) the electrical output is inherently linear with respect to gage resistance change; (5) the sensitivity is double that of a Wheatstone bridge circuit; and (6) the same excitation wires can serve multiple independent gages. An adaptation of current loop circuit is presented that simultaneously provides an output signal voltage directly proportional to transducer resistance change and provides temperature information that is unaffected by transducer and lead wire resistance variations. These innovations are the subject of NASA patent applications.

The constant current loop: A new paradigm for resistance signal conditioning

NASA Astrophysics Data System (ADS)

Anderson, Karl F.

A practical, single, constant-current loop circuit for the signal conditioning of variable-resistance transducers was synthesized, analyzed, and demonstrated. The strain gage and the resistance temperature device are examples of variable-resistance sensors. Lead wires connect variable-resistance sensors to remotely located signal-conditioning hardware. The presence of lead wires in the conventional Wheatstone bridge signal-conditioning circuit introduces undesired effects that reduce the quality of the data from the remote sensors. A practical approach is presented for suppressing essentially all lead wire resistance effects while indicating only the change in resistance value. Theoretical predictions supported by laboratory testing confirm the following features of the approach: (1) the dc response; (2) the electrical output is unaffected by extremely large variations in the resistance of any or all lead wires; (3) the electrical output remains zero for no change in gage resistance; (4) the electrical output is inherently linear with respect to gage resistance change; (5) the sensitivity is double that of a Wheatstone bridge circuit; and (6) the same excitation and sense wires can serve multiple independent gages. An adaptation of the current loop circuit is presented that simultaneously provides an output signal voltage directly proportional to transducer resistance change and provides temperature information that is unaffected by transducer and lead wire resistance variations. These innovations are the subject of NASA patent applications.

The constant current loop: A new paradigm for resistance signal conditioning

NASA Technical Reports Server (NTRS)

Anderson, Karl F.

1994-01-01

A practical single constant current loop circuit for the signal conditioning of variable-resistance transducers has been synthesized, analyzed, and demonstrated. The strain gage and the resistance temperature detector are examples of variable-resistance sensors. Lead wires connect variable-resistance sensors to remotely located signal-conditioning hardware. The presence of lead wires in the conventional Wheatstone bridge signal-conditioning circuit introduces undesired effects that reduce the quality of the data from the remote sensors. A practical approach is presented for suppressing essentially all lead wire resistance effects while indicating only the change in resistance value. Theoretical predictions supported by laboratory testing confirm the following features of the approach: (1) dc response; (2) the electrical output is unaffected by extremely large variation in the resistance of any or all lead wires; (3) the electrical output remains zero for no change in gage resistance; (4) the electrical output is inherently linear with respect to gage resistance change; (5) the sensitivity is double that of a Wheatstone bridge circuit; and (6) the same excitation wires can serve multiple independent gages. An adaptation of current loop circuit is presented that simultaneously provides an output signal voltage directly proportional to transducer resistance change and provides temperature information that is unaffected by transducer and lead wire resistance variations. These innovations are the subject of NASA patent applications.

The constant current loop: A new paradigm for resistance signal conditioning

NASA Technical Reports Server (NTRS)

Anderson, Karl F.

1993-01-01

A practical, single, constant-current loop circuit for the signal conditioning of variable-resistance transducers was synthesized, analyzed, and demonstrated. The strain gage and the resistance temperature device are examples of variable-resistance sensors. Lead wires connect variable-resistance sensors to remotely located signal-conditioning hardware. The presence of lead wires in the conventional Wheatstone bridge signal-conditioning circuit introduces undesired effects that reduce the quality of the data from the remote sensors. A practical approach is presented for suppressing essentially all lead wire resistance effects while indicating only the change in resistance value. Theoretical predictions supported by laboratory testing confirm the following features of the approach: (1) the dc response; (2) the electrical output is unaffected by extremely large variations in the resistance of any or all lead wires; (3) the electrical output remains zero for no change in gage resistance; (4) the electrical output is inherently linear with respect to gage resistance change; (5) the sensitivity is double that of a Wheatstone bridge circuit; and (6) the same excitation and sense wires can serve multiple independent gages. An adaptation of the current loop circuit is presented that simultaneously provides an output signal voltage directly proportional to transducer resistance change and provides temperature information that is unaffected by transducer and lead wire resistance variations. These innovations are the subject of NASA patent applications.

Design and experiment study of a semi-active energy-regenerative suspension system

NASA Astrophysics Data System (ADS)

Shi, Dehua; Chen, Long; Wang, Ruochen; Jiang, Haobin; Shen, Yujie

2015-01-01

A new kind of semi-active energy-regenerative suspension system is proposed to recover suspension vibration energy, as well as to reduce the suspension cost and demands for the motor-rated capacity. The system consists of an energy-regenerative damper and a DC-DC converter-based energy-regenerative circuit. The energy-regenerative damper is composed of an electromagnetic linear motor and an adjustable shock absorber with three regulating levels. The linear motor just works as the generator to harvest the suspension vibration energy. The circuit can be used to improve the system’s energy-regenerative performance and to continuously regulate the motor’s electromagnetic damping force. Therefore, although the motor works as a generator and damps the isolation without an external power source, the motor damping force is controllable. The damping characteristics of the system are studied based on a two degrees of freedom vehicle vibration model. By further analyzing the circuit operation characteristics under different working modes, the double-loop controller is designed to track the desired damping force. The external-loop is a fuzzy controller that offers the desired equivalent damping. The inner-loop controller, on one hand, is used to generate the pulse number and the frequency to control the angle and the rotational speed of the step motor; on the other hand, the inner-loop is used to offer the duty cycle of the energy-regenerative circuit. Simulations and experiments are conducted to validate such a new suspension system. The results show that the semi-active energy-regenerative suspension can improve vehicle ride comfort with the controllable damping characteristics of the linear motor. Meanwhile, it also ensures energy regeneration.

Asymmetric dual-loop feedback to suppress spurious tones and reduce timing jitter in self-mode-locked quantum-dash lasers emitting at 155 μm

NASA Astrophysics Data System (ADS)

Asghar, Haroon; McInerney, John G.

2017-09-01

We demonstrate an asymmetric dual-loop feedback scheme to suppress external cavity side-modes induced in self-mode-locked quantum-dash lasers with conventional single and dual-loop feedback. In this letter, we achieved optimal suppression of spurious tones by optimizing the length of second delay time. We observed that asymmetric dual-loop feedback, with large (~8x) disparity in cavity lengths, eliminates all external-cavity side-modes and produces flat RF spectra close to the main peak with low timing jitter compared to single-loop feedback. Significant reduction in RF linewidth and reduced timing jitter was also observed as a function of increased second feedback delay time. The experimental results based on this feedback configuration validate predictions of recently published numerical simulations. This interesting asymmetric dual-loop feedback scheme provides simplest, efficient and cost effective stabilization of side-band free optoelectronic oscillators based on mode-locked lasers.

Effect of metrology time delay on overlay APC

NASA Astrophysics Data System (ADS)

Carlson, Alan; DiBiase, Debra

2002-07-01

The run-to-run control strategy of lithography APC is primarily composed of a feedback loop as shown in the diagram below. It is known that the insertion of a time delay in a feedback loop can cause degradation in control performance and could even cause a stable system to become unstable, if the time delay becomes sufficiently large. Many proponents of integrated metrology methods have cited the damage caused by metrology time delays as the primary justification for moving from a stand-alone to integrated metrology. While there is little dispute over the qualitative form of this argument, there has been very light published about the quantitative effects under real fab conditions - precisely how much control is lost due to these time delays. Another issue regarding time delays is that the length of these delays is not typically fixed - they vary from lot to lot and in some cases this variance can be large - from one hour on the short side to over 32 hours on the long side. Concern has been expressed that the variability in metrology time delays can cause undesirable dynamics in feedback loops that make it difficult to optimize feedback filters and gains and at worst could drive a system unstable. By using data from numerous fabs, spanning many sizes and styles of operation, we have conducted a quantitative study of the time delay effect on overlay run- to-run control. Our analysis resulted in the following conclusions: (1) There is a significant and material relationship between metrology time delay and overlay control under a variety of real world production conditions. (2) The run-to-run controller can be configured to minimize sensitivity to time delay variations. (3) The value of moving to integrated metrology can be quantified.

Compensation for Lithography Induced Process Variations during Physical Design

NASA Astrophysics Data System (ADS)

Chin, Eric Yiow-Bing

This dissertation addresses the challenge of designing robust integrated circuits in the deep sub micron regime in the presence of lithography process variability. By extending and combining existing process and circuit analysis techniques, flexible software frameworks are developed to provide detailed studies of circuit performance in the presence of lithography variations such as focus and exposure. Applications of these software frameworks to select circuits demonstrate the electrical impact of these variations and provide insight into variability aware compact models that capture the process dependent circuit behavior. These variability aware timing models abstract lithography variability from the process level to the circuit level and are used to estimate path level circuit performance with high accuracy with very little overhead in runtime. The Interconnect Variability Characterization (IVC) framework maps lithography induced geometrical variations at the interconnect level to electrical delay variations. This framework is applied to one dimensional repeater circuits patterned with both 90nm single patterning and 32nm double patterning technologies, under the presence of focus, exposure, and overlay variability. Studies indicate that single and double patterning layouts generally exhibit small variations in delay (between 1--3%) due to self compensating RC effects associated with dense layouts and overlay errors for layouts without self-compensating RC effects. The delay response of each double patterned interconnect structure is fit with a second order polynomial model with focus, exposure, and misalignment parameters with 12 coefficients and residuals of less than 0.1ps. The IVC framework is also applied to a repeater circuit with cascaded interconnect structures to emulate more complex layout scenarios, and it is observed that the variations on each segment average out to reduce the overall delay variation. The Standard Cell Variability Characterization (SCVC) framework advances existing layout-level lithography aware circuit analysis by extending it to cell-level applications utilizing a physically accurate approach that integrates process simulation, compact transistor models, and circuit simulation to characterize electrical cell behavior. This framework is applied to combinational and sequential cells in the Nangate 45nm Open Cell Library, and the timing response of these cells to lithography focus and exposure variations demonstrate Bossung like behavior. This behavior permits the process parameter dependent response to be captured in a nine term variability aware compact model based on Bossung fitting equations. For a two input NAND gate, the variability aware compact model captures the simulated response to an accuracy of 0.3%. The SCVC framework is also applied to investigate advanced process effects including misalignment and layout proximity. The abstraction of process variability from the layout level to the cell level opens up an entire new realm of circuit analysis and optimization and provides a foundation for path level variability analysis without the computationally expensive costs associated with joint process and circuit simulation. The SCVC framework is used with slight modification to illustrate the speedup and accuracy tradeoffs of using compact models. With variability aware compact models, the process dependent performance of a three stage logic circuit can be estimated to an accuracy of 0.7% with a speedup of over 50,000. Path level variability analysis also provides an accurate estimate (within 1%) of ring oscillator period in well under a second. Another significant advantage of variability aware compact models is that they can be easily incorporated into existing design methodologies for design optimization. This is demonstrated by applying cell swapping on a logic circuit to reduce the overall delay variability along a circuit path. By including these variability aware compact models in cell characterization libraries, design metrics such as circuit timing, power, area, and delay variability can be quickly assessed to optimize for the correct balance of all design metrics, including delay variability. Deterministic lithography variations can be easily captured using the variability aware compact models described in this dissertation. However, another prominent source of variability is random dopant fluctuations, which affect transistor threshold voltage and in turn circuit performance. The SCVC framework is utilized to investigate the interactions between deterministic lithography variations and random dopant fluctuations. Monte Carlo studies show that the output delay distribution in the presence of random dopant fluctuations is dependent on lithography focus and exposure conditions, with a 3.6 ps change in standard deviation across the focus exposure process window. This indicates that the electrical impact of random variations is dependent on systematic lithography variations, and this dependency should be included for precise analysis.

Implementation of a Serial Delay Insertion Type Loop Communication for a Real Time Multitransputer System.

DTIC Science & Technology

1985-06-01

just pass the message WAIT NOW AFTER Rlock + timeo t -- if time is out write.screen( TIME IS OUT") MAIN PROGRAM* CHAN linki , link2, link3, link4...PAR D.I.Loop.Interface (link4, linkl,) D.I.Loop.Interface ( linki , link2, 2) D.I.Loop.Interface (link2, link3, 3) JD.I Loop.Interface (link3, link4, 4

Automatic Control of Silicon Melt Level

NASA Technical Reports Server (NTRS)

Duncan, C. S.; Stickel, W. B.

1982-01-01

A new circuit, when combined with melt-replenishment system and melt level sensor, offers continuous closed-loop automatic control of melt-level during web growth. Installed on silicon-web furnace, circuit controls melt-level to within 0.1 mm for as long as 8 hours. Circuit affords greater area growth rate and higher web quality, automatic melt-level control also allows semiautomatic growth of web over long periods which can greatly reduce costs.

Efficient/reliable dc-to-dc inverter circuit

NASA Technical Reports Server (NTRS)

Pasciutti, E. R.

1970-01-01

Feedback loop, which contains an inductor in series with a saturable reactor, is added to a standard inverter circuit to permit the inverter power transistors to be switched in a controlled and efficient manner. This inverter is applicable where the power source has either high or low impedance properties.

Active parallel redundancy for electronic integrator-type control circuits

NASA Technical Reports Server (NTRS)

Peterson, R. A.

1971-01-01

Circuit extends concept of redundant feedback control from type-0 to type-1 control systems. Inactive channels are slaves to the active channel, if latter fails, it is rejected and slave channel is activated. High reliability and elimination of single-component catastrophic failure are important in closed-loop control systems.

p53-repressed miRNAs are involved with E2F in a feed-forward loop promoting proliferation

PubMed Central

Brosh, Ran; Shalgi, Reut; Liran, Atar; Landan, Gilad; Korotayev, Katya; Nguyen, Giang Huong; Enerly, Espen; Johnsen, Hilde; Buganim, Yosef; Solomon, Hilla; Goldstein, Ido; Madar, Shalom; Goldfinger, Naomi; Børresen-Dale, Anne-Lise; Ginsberg, Doron; Harris, Curtis C; Pilpel, Yitzhak; Oren, Moshe; Rotter, Varda

2008-01-01

Normal cell growth is governed by a complicated biological system, featuring multiple levels of control, often deregulated in cancers. The role of microRNAs (miRNAs) in the control of gene expression is now increasingly appreciated, yet their involvement in controlling cell proliferation is still not well understood. Here we investigated the mammalian cell proliferation control network consisting of transcriptional regulators, E2F and p53, their targets and a family of 15 miRNAs. Indicative of their significance, expression of these miRNAs is downregulated in senescent cells and in breast cancers harboring wild-type p53. These miRNAs are repressed by p53 in an E2F1-mediated manner. Furthermore, we show that these miRNAs silence antiproliferative genes, which themselves are E2F1 targets. Thus, miRNAs and transcriptional regulators appear to cooperate in the framework of a multi-gene transcriptional and post-transcriptional feed-forward loop. Finally, we show that, similarly to p53 inactivation, overexpression of representative miRNAs promotes proliferation and delays senescence, manifesting the detrimental phenotypic consequence of perturbations in this circuit. Taken together, these findings position miRNAs as novel key players in the mammalian cellular proliferation network. PMID:19034270

A Triple-Loop Inductive Power Transmission System for Biomedical Applications.

PubMed

Lee, Byunghun; Kiani, Mehdi; Ghovanloo, Maysam

2016-02-01

A triple-loop wireless power transmission (WPT) system equipped with closed-loop global power control, adaptive transmitter (Tx) resonance compensation (TRC), and automatic receiver (Rx) resonance tuning (ART) is presented. This system not only opposes coupling and load variations but also compensates for changes in the environment surrounding the inductive link to enhance power transfer efficiency (PTE) in applications such as implantable medical devices (IMDs). The Tx was built around a commercial off-the-shelf (COTS) radio-frequency identification (RFID) reader, operating at 13.56 MHz. A local Tx loop finds the optimal capacitance in parallel with the Tx coil by adjusting a varactor. A global power control loop maintains the received power at a desired level in the presence of changes in coupling distance, coil misalignments, and loading. Moreover, a local Rx loop is implemented inside a power management integrated circuit (PMIC) to avoid PTE degradation due to the Rx coil surrounding environment and process variations. The PMIC was fabricated in a 0.35- μm 4M2P standard CMOS process with 2.54 mm(2) active area. Measurement results show that the proposed triple-loop system improves the overall PTE by up to 10.5% and 4.7% compared to a similar open- and single closed-loop system, respectively, at nominal coil distance of 2 cm. The added TRC and ART loops contribute 2.3% and 1.4% to the overall PTE of 13.5%, respectively. This is the first WPT system to include three loops to dynamically compensate for environment and circuit variations and improve the overall power efficiency all the way from the driver output in Tx to the load in Rx.

Foundry fabricated photonic integrated circuit optical phase lock loop.

PubMed

Bałakier, Katarzyna; Fice, Martyn J; Ponnampalam, Lalitha; Graham, Chris S; Wonfor, Adrian; Seeds, Alwyn J; Renaud, Cyril C

2017-07-24

This paper describes the first foundry-based InP photonic integrated circuit (PIC) designed to work within a heterodyne optical phase locked loop (OPLL). The PIC and an external electronic circuit were used to phase-lock a single-line semiconductor laser diode to an incoming reference laser, with tuneable frequency offset from 4 GHz to 12 GHz. The PIC contains 33 active and passive components monolithically integrated on a single chip, fully demonstrating the capability of a generic foundry PIC fabrication model. The electronic part of the OPLL consists of commercially available RF components. This semi-packaged system stabilizes the phase and frequency of the integrated laser so that an absolute frequency, high-purity heterodyne signal can be generated when the OPLL is in operation, with phase noise lower than -100 dBc/Hz at 10 kHz offset from the carrier. This is the lowest phase noise level ever demonstrated by monolithically integrated OPLLs.

Therapeutic synthetic gene networks.

PubMed

Karlsson, Maria; Weber, Wilfried

2012-10-01

The field of synthetic biology is rapidly expanding and has over the past years evolved from the development of simple gene networks to complex treatment-oriented circuits. The reprogramming of cell fate with open-loop or closed-loop synthetic control circuits along with biologically implemented logical functions have fostered applications spanning over a wide range of disciplines, including artificial insemination, personalized medicine and the treatment of cancer and metabolic disorders. In this review we describe several applications of interactive gene networks, a synthetic biology-based approach for future gene therapy, as well as the utilization of synthetic gene circuits as blueprints for the design of stimuli-responsive biohybrid materials. The recent progress in synthetic biology, including the rewiring of biosensing devices with the body's endogenous network as well as novel therapeutic approaches originating from interdisciplinary work, generates numerous opportunities for future biomedical applications. Copyright © 2012 Elsevier Ltd. All rights reserved.

Overload protection for switching regulators

NASA Technical Reports Server (NTRS)

Lachochi, E.

1980-01-01

Circuit protects all output lines of switching regulator against overloads without requiring current sensors on every line. If overload is sensed, device short circuits bias on switching transistor so that power is rapidly cut off from loads. Circuit also includes delay network to inhibit erroneous operation during startup.

Long period pseudo random number sequence generator

NASA Technical Reports Server (NTRS)

Wang, Charles C. (Inventor)

1989-01-01

A circuit for generating a sequence of pseudo random numbers, (A sub K). There is an exponentiator in GF(2 sup m) for the normal basis representation of elements in a finite field GF(2 sup m) each represented by m binary digits and having two inputs and an output from which the sequence (A sub K). Of pseudo random numbers is taken. One of the two inputs is connected to receive the outputs (E sub K) of maximal length shift register of n stages. There is a switch having a pair of inputs and an output. The switch outputs is connected to the other of the two inputs of the exponentiator. One of the switch inputs is connected for initially receiving a primitive element (A sub O) in GF(2 sup m). Finally, there is a delay circuit having an input and an output. The delay circuit output is connected to the other of the switch inputs and the delay circuit input is connected to the output of the exponentiator. Whereby after the exponentiator initially receives the primitive element (A sub O) in GF(2 sup m) through the switch, the switch can be switched to cause the exponentiator to receive as its input a delayed output A(K-1) from the exponentiator thereby generating (A sub K) continuously at the output of the exponentiator. The exponentiator in GF(2 sup m) is novel and comprises a cyclic-shift circuit; a Massey-Omura multiplier; and, a control logic circuit all operably connected together to perform the function U(sub i) = 92(sup i) (for n(sub i) = 1 or 1 (for n(subi) = 0).

CHEETAH: circuit-switched high-speed end-to-end transport architecture

NASA Astrophysics Data System (ADS)

Veeraraghavan, Malathi; Zheng, Xuan; Lee, Hyuk; Gardner, M.; Feng, Wuchun

2003-10-01

Leveraging the dominance of Ethernet in LANs and SONET/SDH in MANs and WANs, we propose a service called CHEETAH (Circuit-switched High-speed End-to-End Transport ArcHitecture). The service concept is to provide end hosts with high-speed, end-to-end circuit connectivity on a call-by-call shared basis, where a "circuit" consists of Ethernet segments at the ends that are mapped into Ethernet-over-SONET long-distance circuits. This paper focuses on the file-transfer application for such circuits. For this application, the CHEETAH service is proposed as an add-on to the primary Internet access service already in place for enterprise hosts. This allows an end host that is sending a file to first attempt setting up an end-to-end Ethernet/EoS circuit, and if rejected, fall back to the TCP/IP path. If the circuit setup is successful, the end host will enjoy a much shorter file-transfer delay than on the TCP/IP path. To determine the conditions under which an end host with access to the CHEETAH service should attempt circuit setup, we analyze mean file-transfer delays as a function of call blocking probability in the circuit-switched network, probability of packet loss in the IP network, round-trip times, link rates, and so on.

Postural control model interpretation of stabilogram diffusion analysis

NASA Technical Reports Server (NTRS)

Peterka, R. J.

2000-01-01

Collins and De Luca [Collins JJ. De Luca CJ (1993) Exp Brain Res 95: 308-318] introduced a new method known as stabilogram diffusion analysis that provides a quantitative statistical measure of the apparently random variations of center-of-pressure (COP) trajectories recorded during quiet upright stance in humans. This analysis generates a stabilogram diffusion function (SDF) that summarizes the mean square COP displacement as a function of the time interval between COP comparisons. SDFs have a characteristic two-part form that suggests the presence of two different control regimes: a short-term open-loop control behavior and a longer-term closed-loop behavior. This paper demonstrates that a very simple closed-loop control model of upright stance can generate realistic SDFs. The model consists of an inverted pendulum body with torque applied at the ankle joint. This torque includes a random disturbance torque and a control torque. The control torque is a function of the deviation (error signal) between the desired upright body position and the actual body position, and is generated in proportion to the error signal, the derivative of the error signal, and the integral of the error signal [i.e. a proportional, integral and derivative (PID) neural controller]. The control torque is applied with a time delay representing conduction, processing, and muscle activation delays. Variations in the PID parameters and the time delay generate variations in SDFs that mimic real experimental SDFs. This model analysis allows one to interpret experimentally observed changes in SDFs in terms of variations in neural controller and time delay parameters rather than in terms of open-loop versus closed-loop behavior.

A novel high performance ESD power clamp circuit with a small area

NASA Astrophysics Data System (ADS)

Zhaonian, Yang; Hongxia, Liu; Li, Li; Qingqing, Zhuo

2012-09-01

A MOSFET-based electrostatic discharge (ESD) power clamp circuit with only a 10 ns RC time constant for a 0.18-μm process is proposed. A diode-connected NMOSFET is used to maintain a long delay time and save area. The special structure overcomes other shortcomings in this clamp circuit. Under fast power-up events, the gate voltage of the clamp MOSFET does not rise as quickly as under ESD events, the special structure can keep the clamp MOSFET thoroughly off. Under a falsely triggered event, the special structure can turn off the clamp MOSFET in a short time. The clamp circuit can also reject the power supply noise effectively. Simulation results show that the clamp circuit avoids fast false triggering events such as a 30 ns/1.8 V power-up, maintains a 1.2 μs delay time and a 2.14 μs turn-off time, and reduces to about 70% of the RC time constant. It is believed that the proposed clamp circuit can be widely used in high-speed integrated circuits.

A closed-loop system for frequency tracking of piezoresistive cantilever sensors

NASA Astrophysics Data System (ADS)

Wasisto, Hutomo Suryo; Zhang, Qing; Merzsch, Stephan; Waag, Andreas; Peiner, Erwin

2013-05-01

A closed loop circuit capable of tracking resonant frequencies for MEMS-based piezoresistive cantilever resonators is developed in this work. The proposed closed-loop system is mainly based on a phase locked loop (PLL) circuit. In order to lock onto the resonant frequency of the resonator, an actuation signal generated from a voltage-controlled oscillator (VCO) is locked to the phase of the input reference signal of the cantilever sensor. In addition to the PLL component, an instrumentation amplifier and an active low pass filter (LPF) are connected to the system for gaining the amplitude and reducing the noise of the cantilever output signals. The LPF can transform a rectangular signal into a sinusoidal signal with voltage amplitudes ranging from 5 to 10 V which are sufficient for a piezoactuator input (i.e., maintaining a large output signal of the cantilever sensor). To demonstrate the functionality of the system, a self-sensing silicon cantilever resonator with a built-in piezoresistive Wheatstone bridge is fabricated and integrated with the circuit. A piezoactuator is utilized for actuating the cantilever into resonance. Implementation of this closed loop system is used to track the resonant frequency of a silicon cantilever-based sensor resonating at 9.4 kHz under a cross-sensitivity test of ambient temperature. The changes of the resonant frequency are interpreted using a frequency counter connected to the system. From the experimental results, the temperature sensitivity and coefficient of the employed sensor are 0.3 Hz/°C and 32.8 ppm/°C, respectively. The frequency stability of the system can reach up to 0.08 Hz. The development of this system will enable real-time nanoparticle monitoring systems and provide a miniaturization of the instrumentation modules for cantilever-based nanoparticle detectors.

Predictive lethal proarrhythmic risk evaluation using a closed-loop-circuit cell network with human induced pluripotent stem cells derived cardiomyocytes

NASA Astrophysics Data System (ADS)

Nomura, Fumimasa; Hattori, Akihiro; Terazono, Hideyuki; Kim, Hyonchol; Odaka, Masao; Sugio, Yoshihiro; Yasuda, Kenji

2016-06-01

For the prediction of lethal arrhythmia occurrence caused by abnormality of cell-to-cell conduction, we have developed a next-generation in vitro cell-to-cell conduction assay, i.e., a quasi in vivo assay, in which the change in spatial cell-to-cell conduction is quantitatively evaluated from the change in waveforms of the convoluted electrophysiological signals from lined-up cardiomyocytes on a single closed loop of a microelectrode of 1 mm diameter and 20 µm width in a cultivation chip. To evaluate the importance of the closed-loop arrangement of cardiomyocytes for prediction, we compared the change in waveforms of convoluted signals of the responses in the closed-loop circuit arrangement with that of the response of cardiomyocyte clusters using a typical human ether a go-go related gene (hERG) ion channel blocker, E-4031. The results showed that (1) waveform prolongation and fluctuation both in the closed loops and clusters increased depending on the E-4031 concentration increase. However, (2) only the waveform signals in closed loops showed an apparent temporal change in waveforms from ventricular tachycardia (VT) to ventricular fibrillation (VF), which is similar to the most typical cell-to-cell conductance abnormality. The results indicated the usefulness of convoluted waveform signals of a closed-loop cell network for acquiring reproducible results acquisition and more detailed temporal information on cell-to-cell conduction.

Impedance matched, high-power, rf antenna for ion cyclotron resonance heating of a plasma

DOEpatents

Baity, Jr., Frederick W.; Hoffman, Daniel J.; Owens, Thomas L.

1988-01-01

A resonant double loop radio frequency (rf) antenna for radiating high-power rf energy into a magnetically confined plasma. An inductive element in the form of a large current strap, forming the radiating element, is connected between two variable capacitors to form a resonant circuit. A real input impedance results from tapping into the resonant circuit along the inductive element, generally near the midpoint thereof. The impedance can be matched to the source impedance by adjusting the separate capacitors for a given tap arrangement or by keeping the two capacitances fixed and adjustng the tap position. This results in a substantial reduction in the voltage and current in the transmission system to the antenna compared to unmatched antennas. Because the complete circuit loop consisting of the two capacitors and the inductive element is resonant, current flows in the same direction along the entire length of the radiating element and is approximately equal in each branch of the circuit. Unidirectional current flow permits excitation of low order poloidal modes which penetrate more deeply into the plasma.

A closed-loop compressive-sensing-based neural recording system.

PubMed

Zhang, Jie; Mitra, Srinjoy; Suo, Yuanming; Cheng, Andrew; Xiong, Tao; Michon, Frederic; Welkenhuysen, Marleen; Kloosterman, Fabian; Chin, Peter S; Hsiao, Steven; Tran, Trac D; Yazicioglu, Firat; Etienne-Cummings, Ralph

2015-06-01

This paper describes a low power closed-loop compressive sensing (CS) based neural recording system. This system provides an efficient method to reduce data transmission bandwidth for implantable neural recording devices. By doing so, this technique reduces a majority of system power consumption which is dissipated at data readout interface. The design of the system is scalable and is a viable option for large scale integration of electrodes or recording sites onto a single device. The entire system consists of an application-specific integrated circuit (ASIC) with 4 recording readout channels with CS circuits, a real time off-chip CS recovery block and a recovery quality evaluation block that provides a closed feedback to adaptively adjust compression rate. Since CS performance is strongly signal dependent, the ASIC has been tested in vivo and with standard public neural databases. Implemented using efficient digital circuit, this system is able to achieve >10 times data compression on the entire neural spike band (500-6KHz) while consuming only 0.83uW (0.53 V voltage supply) additional digital power per electrode. When only the spikes are desired, the system is able to further compress the detected spikes by around 16 times. Unlike other similar systems, the characteristic spikes and inter-spike data can both be recovered which guarantes a >95% spike classification success rate. The compression circuit occupied 0.11mm(2)/electrode in a 180nm CMOS process. The complete signal processing circuit consumes <16uW/electrode. Power and area efficiency demonstrated by the system make it an ideal candidate for integration into large recording arrays containing thousands of electrode. Closed-loop recording and reconstruction performance evaluation further improves the robustness of the compression method, thus making the system more practical for long term recording.

Design strategies for dynamic closed-loop optogenetic neurocontrol in vivo

NASA Astrophysics Data System (ADS)

Bolus, M. F.; Willats, A. A.; Whitmire, C. J.; Rozell, C. J.; Stanley, G. B.

2018-04-01

Objective. Controlling neural activity enables the possibility of manipulating sensory perception, cognitive processes, and body movement, in addition to providing a powerful framework for functionally disentangling the neural circuits that underlie these complex phenomena. Over the last decade, optogenetic stimulation has become an increasingly important and powerful tool for understanding neural circuit function, owing to the ability to target specific cell types and bidirectionally modulate neural activity. To date, most stimulation has been provided in open-loop or in an on/off closed-loop fashion, where previously-determined stimulation is triggered by an event. Here, we describe and demonstrate a design approach for precise optogenetic control of neuronal firing rate modulation using feedback to guide stimulation continuously. Approach. Using the rodent somatosensory thalamus as an experimental testbed for realizing desired time-varying patterns of firing rate modulation, we utilized a moving average exponential filter to estimate firing rate online from single-unit spiking measured extracellularly. This estimate of instantaneous rate served as feedback for a proportional integral (PI) controller, which was designed during the experiment based on a linear-nonlinear Poisson (LNP) model of the neuronal response to light. Main results. The LNP model fit during the experiment enabled robust closed-loop control, resulting in good tracking of sinusoidal and non-sinusoidal targets, and rejection of unmeasured disturbances. Closed-loop control also enabled manipulation of trial-to-trial variability. Significance. Because neuroscientists are faced with the challenge of dissecting the functions of circuit components, the ability to maintain control of a region of interest in spite of changes in ongoing neural activity will be important for disambiguating function within networks. Closed-loop stimulation strategies are ideal for control that is robust to such changes, and the employment of continuous feedback to adjust stimulation in real-time can improve the quality of data collected using optogenetic manipulation.

UWB delay and multiply receiver

DOEpatents

Dallum, Gregory E.; Pratt, Garth C.; Haugen, Peter C.; Romero, Carlos E.

2013-09-10

An ultra-wideband (UWB) delay and multiply receiver is formed of a receive antenna; a variable gain attenuator connected to the receive antenna; a signal splitter connected to the variable gain attenuator; a multiplier having one input connected to an undelayed signal from the signal splitter and another input connected to a delayed signal from the signal splitter, the delay between the splitter signals being equal to the spacing between pulses from a transmitter whose pulses are being received by the receive antenna; a peak detection circuit connected to the output of the multiplier and connected to the variable gain attenuator to control the variable gain attenuator to maintain a constant amplitude output from the multiplier; and a digital output circuit connected to the output of the multiplier.

Divergence compensation for hardware-in-the-loop simulation of stiffness-varying discrete contact in space

NASA Astrophysics Data System (ADS)

Qi, Chenkun; Zhao, Xianchao; Gao, Feng; Ren, Anye; Hu, Yan

2016-11-01

The hardware-in-the-loop (HIL) contact simulation for flying objects in space is challenging due to the divergence caused by the time delay. In this study, a divergence compensation approach is proposed for the stiffness-varying discrete contact. The dynamic response delay of the motion simulator and the force measurement delay are considered. For the force measurement delay, a phase lead based force compensation approach is used. For the dynamic response delay of the motion simulator, a response error based force compensation approach is used, where the compensation force is obtained from the real-time identified contact stiffness and real-time measured position response error. The dynamic response model of the motion simulator is not required. The simulations and experiments show that the simulation divergence can be compensated effectively and satisfactorily by using the proposed approach.

Circuit breaker lock out assembly

DOEpatents

Gordy, W.T.

1983-05-18

A lock out assembly for a circuit breaker which consists of a generally step-shaped unitary base with an aperture in the small portion of the step-shaped base and a roughly S shaped retaining pin which loops through the large portion of the step-shaped base. The lock out assembly is adapted to fit over a circuit breaker with the handle switch projecting through the aperture, and the retaining pin projecting into an opening of the handle switch, preventing removal.

Circuit breaker lock out assembly

DOEpatents

Gordy, Wade T.

1984-01-01

A lock out assembly for a circuit breaker which consists of a generally step-shaped unitary base with an aperture in the small portion of the step-shaped base and a roughly "S" shaped retaining pin which loops through the large portion of the step-shaped base. The lock out assembly is adapted to fit over a circuit breaker with the handle switch projecting through the aperture, and the retaining pin projecting into an opening of the handle switch, preventing removal.

Complex dynamics of memristive circuits: Analytical results and universal slow relaxation

NASA Astrophysics Data System (ADS)

Caravelli, F.; Traversa, F. L.; Di Ventra, M.

2017-02-01

Networks with memristive elements (resistors with memory) are being explored for a variety of applications ranging from unconventional computing to models of the brain. However, analytical results that highlight the role of the graph connectivity on the memory dynamics are still few, thus limiting our understanding of these important dynamical systems. In this paper, we derive an exact matrix equation of motion that takes into account all the network constraints of a purely memristive circuit, and we employ it to derive analytical results regarding its relaxation properties. We are able to describe the memory evolution in terms of orthogonal projection operators onto the subspace of fundamental loop space of the underlying circuit. This orthogonal projection explicitly reveals the coupling between the spatial and temporal sectors of the memristive circuits and compactly describes the circuit topology. For the case of disordered graphs, we are able to explain the emergence of a power-law relaxation as a superposition of exponential relaxation times with a broad range of scales using random matrices. This power law is also universal, namely independent of the topology of the underlying graph but dependent only on the density of loops. In the case of circuits subject to alternating voltage instead, we are able to obtain an approximate solution of the dynamics, which is tested against a specific network topology. These results suggest a much richer dynamics of memristive networks than previously considered.

Arbitrary digital pulse sequence generator with delay-loop timing

NASA Astrophysics Data System (ADS)

Hošák, Radim; Ježek, Miroslav

2018-04-01

We propose an idea of an electronic multi-channel arbitrary digital sequence generator with temporal granularity equal to two clock cycles. We implement the generator with 32 channels using a low-cost ARM microcontroller and demonstrate its capability to produce temporal delays ranging from tens of nanoseconds to hundreds of seconds, with 24 ns timing granularity and linear scaling of delay with respect to the number of delay loop iterations. The generator is optionally synchronized with an external clock source to provide 100 ps jitter and overall sequence repeatability within the whole temporal range. The generator is fully programmable and able to produce digital sequences of high complexity. The concept of the generator can be implemented using different microcontrollers and applied for controlling of various optical, atomic, and nuclear physics measurement setups.

VERNIER CHRONOTRON UTILIZING AT LEAST TWO SHORTED DELAY LINES

DOEpatents

Rufer, R.P.

1964-02-25

An improved vernier chronotron featuring pulse-forming circuits of a ringing'' or back and forth'' oscillatory type is described. A delay line shorted at both ends together with transistor circuitry to introduce a pulse into that line and also to provide reinforcement of the pulse as it oscillates between the pulse-reflective extremities is provided. A transistorized coincidence circuit is also provided. Enhanced measurement of time intervals in the nanosecond range is afforded. (AEC)

An analog integrated circuit beamformer for high-frequency medical ultrasound imaging.

PubMed

Gurun, Gokce; Zahorian, Jaime S; Sisman, Alper; Karaman, Mustafa; Hasler, Paul E; Degertekin, F Levent

2012-10-01

We designed and fabricated a dynamic receive beamformer integrated circuit (IC) in 0.35-μm CMOS technology. This beamformer IC is suitable for integration with an annular array transducer for high-frequency (30-50 MHz) intravascular ultrasound (IVUS) imaging. The beamformer IC consists of receive preamplifiers, an analog dynamic delay-and-sum beamformer, and buffers for 8 receive channels. To form an analog dynamic delay line we designed an analog delay cell based on the current-mode first-order all-pass filter topology, as the basic building block. To increase the bandwidth of the delay cell, we explored an enhancement technique on the current mirrors. This technique improved the overall bandwidth of the delay line by a factor of 6. Each delay cell consumes 2.1-mW of power and is capable of generating a tunable time delay between 1.75 ns to 2.5 ns. We successfully integrated the fabricated beamformer IC with an 8-element annular array. Experimental test results demonstrated the desired buffering, preamplification and delaying capabilities of the beamformer.

Clock recovery for high-speed optical communication

NASA Astrophysics Data System (ADS)

Pedrotti, Kenneth D.

1996-01-01

This paper reviews recent results for clock recovery circuits operating at speeds in excess of 1 Gbit/sec or realized as multichannel arrays. The emphasis is on synchronous optical network (SONET) type systems, their requirements, and the effect of the clock recovery circuits on system performance. Clock recovery approaches include filter based, phase-locked-loops, and all-optical methods.

Clock recovery for high-speed optical communication

NASA Astrophysics Data System (ADS)

Pedrotti, Ken

1996-01-01

This paper reviews recent results for clock recovery circuits operating at speeds in excess of 1 Gbit/sec or realized as multichannel arrays. The emphasis is on Synchronous Optical NETwork (SONET) type systems, their requirements, and the effect of the clock recovery circuits on system performance. Clock recovery approaches include filter based, phase-lockcd-loops, and all-optical methods.

Teaching Electric Fences: The Physics behind the Brainiac Video

ERIC Educational Resources Information Center

Vollmer, Michael

2016-01-01

In many states, electric fences are used to prevent animals from leaving a designated area, for example for grazing. They are quite well known by most students and can therefore serve as daily-life examples of electric circuits. Besides helping to grasp the ideas of Kirchhoff's laws for voltages and currents in circuits according to loop and…

Torque control for electric motors

NASA Technical Reports Server (NTRS)

Bernard, C. A.

1980-01-01

Method for adjusting electric-motor torque output to accomodate various loads utilizes phase-lock loop to control relay connected to starting circuit. As load is imposed, motor slows down, and phase lock is lost. Phase-lock signal triggers relay to power starting coil and generate additional torque. Once phase lock is recoverd, relay restores starting circuit to its normal operating mode.

Spectral Structure Of Phase-Induced Intensity Noise In Recirculating Delay Lines

NASA Astrophysics Data System (ADS)

Tur, M.; Moslehi, B.; Bowers, J. E.; Newton, S. A.; Jackson, K. P.; Goodman, J. W.; Cutler, C. C.; Shaw, H. J.

1983-09-01

The dynamic range of fiber optic signal processors driven by relatively incoherent multimode semiconductor lasers is shown to be severely limited by laser phase-induced noise. It is experimentally demonstrated that while the noise power spectrum of differential length fiber filters is approximately flat, processors with recirculating loops exhibit noise with a periodically structured power spectrum with notches at zero frequency as well as at all other multiples of 1/(loop delay). The experimental results are aug-mented by a theoretical analysis.

46 CFR 169.683 - Overcurrent protection, general.

Code of Federal Regulations, 2013 CFR

2013-10-01

... time delay; (2) Instantaneous short circuit protection; and (3) Repeated opening of the circuit in... above the full-load rating for continuous rated machines or the overload rating for special rated machines. ...

46 CFR 169.683 - Overcurrent protection, general.

Code of Federal Regulations, 2014 CFR

2014-10-01

... time delay; (2) Instantaneous short circuit protection; and (3) Repeated opening of the circuit in... above the full-load rating for continuous rated machines or the overload rating for special rated machines. ...

46 CFR 169.683 - Overcurrent protection, general.

Code of Federal Regulations, 2012 CFR

2012-10-01

... time delay; (2) Instantaneous short circuit protection; and (3) Repeated opening of the circuit in... above the full-load rating for continuous rated machines or the overload rating for special rated machines. ...

Emission control apparatus for internal combustion engines with a controllably disabled clamping circuit

DOE Office of Scientific and Technical Information (OSTI.GOV)

Asano, M.

1979-08-28

The invention discloses an emission control apparatus for internal combustion engine includes an exhaust composition sensor to sense the mixture ratio, a circuit for clamping the mixture ratio to a predetermined constant value to prevent the mixture from becoming too rich or too lean when a failure should occur in the control loop, for example, in the exhaust composition sensor failure and a circuit for interrupting the clamping circuit when the engine operating condition is such that the sensor is caused to produce low voltage signals although the sensor is functioning properly.

Constant-current control method of multi-function electromagnetic transmitter.

PubMed

Xue, Kaichang; Zhou, Fengdao; Wang, Shuang; Lin, Jun

2015-02-01

Based on the requirements of controlled source audio-frequency magnetotelluric, DC resistivity, and induced polarization, a constant-current control method is proposed. Using the required current waveforms in prospecting as a standard, the causes of current waveform distortion and current waveform distortion's effects on prospecting are analyzed. A cascaded topology is adopted to achieve 40 kW constant-current transmitter. The responsive speed and precision are analyzed. According to the power circuit of the transmitting system, the circuit structure of the pulse width modulation (PWM) constant-current controller is designed. After establishing the power circuit model of the transmitting system and the PWM constant-current controller model, analyzing the influence of ripple current, and designing an open-loop transfer function according to the amplitude-frequency characteristic curves, the parameters of the PWM constant-current controller are determined. The open-loop transfer function indicates that the loop gain is no less than 28 dB below 160 Hz, which assures the responsive speed of the transmitting system; the phase margin is 45°, which assures the stabilization of the transmitting system. Experimental results verify that the proposed constant-current control method can keep the control error below 4% and can effectively suppress load change caused by the capacitance of earth load.

Constant-current control method of multi-function electromagnetic transmitter

NASA Astrophysics Data System (ADS)

Xue, Kaichang; Zhou, Fengdao; Wang, Shuang; Lin, Jun

2015-02-01

Based on the requirements of controlled source audio-frequency magnetotelluric, DC resistivity, and induced polarization, a constant-current control method is proposed. Using the required current waveforms in prospecting as a standard, the causes of current waveform distortion and current waveform distortion's effects on prospecting are analyzed. A cascaded topology is adopted to achieve 40 kW constant-current transmitter. The responsive speed and precision are analyzed. According to the power circuit of the transmitting system, the circuit structure of the pulse width modulation (PWM) constant-current controller is designed. After establishing the power circuit model of the transmitting system and the PWM constant-current controller model, analyzing the influence of ripple current, and designing an open-loop transfer function according to the amplitude-frequency characteristic curves, the parameters of the PWM constant-current controller are determined. The open-loop transfer function indicates that the loop gain is no less than 28 dB below 160 Hz, which assures the responsive speed of the transmitting system; the phase margin is 45°, which assures the stabilization of the transmitting system. Experimental results verify that the proposed constant-current control method can keep the control error below 4% and can effectively suppress load change caused by the capacitance of earth load.

Bidirectional amplifier

DOEpatents

Wright, James T.

1986-01-01

A bilateral circuit is operable for transmitting signals in two directions without generation of ringing due to feedback caused by the insertion of the circuit. The circuit may include gain for each of the signals to provide a bidirectional amplifier. The signals are passed through two separate paths, with a unidirectional amplifier in each path. A controlled sampling device is provided in each path for sampling the two signals. Any feedback loop between the two signals is disrupted by providing a phase displacement between the control signals for the two sampling devices.

Bidirectional amplifier

DOEpatents

Wright, J.T.

1984-02-02

A bilateral circuit is operable for transmitting signals in two directions without generation of ringing due to feedback caused by the insertion of the circuit. The circuit may include gain for each of the signals to provide a bidirectional amplifier. The signals are passed through two separate paths, with a unidirectional amplifier in each path. A controlled sampling device is provided in each path for sampling the two signals. Any feedback loop between the two signals is disrupted by providing a phase displacement between the control signals for the two sampling devices.

Multi-objective optimization of MOSFETs channel widths and supply voltage in the proposed dual edge-triggered static D flip-flop with minimum average power and delay by using fuzzy non-dominated sorting genetic algorithm-II.

PubMed

Keivanian, Farshid; Mehrshad, Nasser; Bijari, Abolfazl

2016-01-01

D Flip-Flop as a digital circuit can be used as a timing element in many sophisticated circuits. Therefore the optimum performance with the lowest power consumption and acceptable delay time will be critical issue in electronics circuits. The newly proposed Dual-Edge Triggered Static D Flip-Flop circuit layout is defined as a multi-objective optimization problem. For this, an optimum fuzzy inference system with fuzzy rules is proposed to enhance the performance and convergence of non-dominated sorting Genetic Algorithm-II by adaptive control of the exploration and exploitation parameters. By using proposed Fuzzy NSGA-II algorithm, the more optimum values for MOSFET channel widths and power supply are discovered in search space than ordinary NSGA types. What is more, the design parameters involving NMOS and PMOS channel widths and power supply voltage and the performance parameters including average power consumption and propagation delay time are linked. To do this, the required mathematical backgrounds are presented in this study. The optimum values for the design parameters of MOSFETs channel widths and power supply are discovered. Based on them the power delay product quantity (PDP) is 6.32 PJ at 125 MHz Clock Frequency, L = 0.18 µm, and T = 27 °C.

Fill-in binary loop pulse-torque quantizer

NASA Technical Reports Server (NTRS)

Lory, C. B.

1975-01-01

Fill-in binary (FIB) loop provides constant heating of torque generator, an advantage of binary current switching. At the same time, it avoids mode-related dead zone and data delay of binary, an advantage of ternary quantization.

ELECTRONIC PHASE CONTROL CIRCUIT

DOEpatents

Salisbury, J.D.; Klein, W.W.; Hansen, C.F.

1959-04-21

An electronic circuit is described for controlling the phase of radio frequency energy applied to a multicavity linear accelerator. In one application of the circuit two cavities are excited from a single radio frequency source, with one cavity directly coupled to the source and the other cavity coupled through a delay line of special construction. A phase detector provides a bipolar d-c output signal proportional to the difference in phase between the voltage in the two cavities. This d-c signal controls a bias supply which provides a d-c output for varying the capacitnce of voltage sensitive capacitors in the delay line. The over-all operation of the circuit is completely electronic, overcoming the time response limitations of the electromechanical control systems, and the relative phase relationship of the radio frequency voltages in the two caviiies is continuously controlled to effect particle acceleration.

Mixed logic style adder circuit designed and fabricated using SOI substrate for irradiation-hardened experiment

NASA Astrophysics Data System (ADS)

Yuan, Shoucai; Liu, Yamei

2016-08-01

This paper proposed a rail to rail swing, mixed logic style 28-transistor 1-bit full adder circuit which is designed and fabricated using silicon-on-insulator (SOI) substrate with 90 nm gate length technology. The main goal of our design is space application where circuits may be damaged by outer space radiation; so the irradiation-hardened technique such as SOI structure should be used. The circuit's delay, power and power-delay product (PDP) of our proposed gate diffusion input (GDI)-based adder are HSPICE simulated and compared with other reported high-performance 1-bit adder. The GDI-based 1-bit adder has 21.61% improvement in delay and 18.85% improvement in PDP, over the reported 1-bit adder. However, its power dissipation is larger than that reported with 3.56% increased but is still comparable. The worst case performance of proposed 1-bit adder circuit is also seen to be less sensitive to variations in power supply voltage (VDD) and capacitance load (CL), over a wide range from 0.6 to 1.8 V and 0 to 200 fF, respectively. The proposed and reported 1-bit full adders are all layout designed and wafer fabricated with other circuits/systems together on one chip. The chip measurement and analysis has been done at VDD = 1.2 V, CL = 20 fF, and 200 MHz maximum input signal frequency with temperature of 300 K.

The Role of the Medial Prefrontal Cortex in Trace Fear Extinction

ERIC Educational Resources Information Center

Kwapis, Janine L.; Jarome, Timothy J.; Helmstetter, Fred J.

2015-01-01

The extinction of delay fear conditioning relies on a neural circuit that has received much attention and is relatively well defined. Whether this established circuit also supports the extinction of more complex associations, however, is unclear. Trace fear conditioning is a better model of complex relational learning, yet the circuit that…

An advanced SEU tolerant latch based on error detection

NASA Astrophysics Data System (ADS)

Xu, Hui; Zhu, Jianwei; Lu, Xiaoping; Li, Jingzhao

2018-05-01

This paper proposes a latch that can mitigate SEUs via an error detection circuit. The error detection circuit is hardened by a C-element and a stacked PMOS. In the hold state, a particle strikes the latch or the error detection circuit may cause a fault logic state of the circuit. The error detection circuit can detect the upset node in the latch and the fault output will be corrected. The upset node in the error detection circuit can be corrected by the C-element. The power dissipation and propagation delay of the proposed latch are analyzed by HSPICE simulations. The proposed latch consumes about 77.5% less energy and 33.1% less propagation delay than the triple modular redundancy (TMR) latch. Simulation results demonstrate that the proposed latch can mitigate SEU effectively. Project supported by the National Natural Science Foundation of China (Nos. 61404001, 61306046), the Anhui Province University Natural Science Research Major Project (No. KJ2014ZD12), the Huainan Science and Technology Program (No. 2013A4011), and the National Natural Science Foundation of China (No. 61371025).

Power converter having improved fluid cooling

DOEpatents

Meyer, Andreas A.; Radosevich, Lawrence D.; Beihoff, Bruce C.; Kehl, Dennis L.; Kannenberg, Daniel G.

2007-03-06

A thermal support may receive one or more power electronic circuits. The support may aid in removing heat from the circuits through fluid circulating through the support, which may be controlled in a closed-loop manner. Interfacing between circuits, circuit mounting structure, and the support provide for greatly enhanced cooling. The support may form a shield from both external EMI/RFI and from interference generated by operation of the power electronic circuits. Features may be provided to permit and enhance connection of the circuitry to external circuitry, such as improved terminal configurations. Modular units may be assembled that may be coupled to electronic circuitry via plug-in arrangements or through interface with a backplane or similar mounting and interconnecting structures.

Response characteristic of high-speed on/off valve with double voltage driving circuit

NASA Astrophysics Data System (ADS)

Li, P. X.; Su, M.; Zhang, D. B.

2017-07-01

High-speed on/off valve, an important part of turbocharging system, its quick response has a direct impact on the turbocharger pressure cycle. The methods of improving the response characteristic of high speed on/off valve include increasing the magnetic force of armature and the voltage, decreasing the mass and current of coil. The less coil number of turns, the solenoid force is smaller. The special armature structure and the magnetic material will raise cost. In this paper a new scheme of double voltage driving circuit is investigated, in which the original driving circuit of high-speed on/off valve is replaced by double voltage driving circuit. The detailed theoretical analysis and simulations were carried out on the double voltage driving circuit, it showed that the switching time and delay time of the valve respectively are 3.3ms, 5.3ms, 1.9ms and 1.8ms. When it is driven by the double voltage driving circuit, the switching time and delay time of this valve are reduced, optimizing its response characteristic. By the comparison related factors (such as duty cycle or working frequency) about influences on response characteristic, the superior of double voltage driving circuit has been further confirmed.

Circuit for Driving Piezoelectric Transducers

NASA Technical Reports Server (NTRS)

Randall, David P.; Chapsky, Jacob

2009-01-01

The figure schematically depicts an oscillator circuit for driving a piezoelectric transducer to excite vibrations in a mechanical structure. The circuit was designed and built to satisfy application-specific requirements to drive a selected one of 16 such transducers at a regulated amplitude and frequency chosen to optimize the amount of work performed by the transducer and to compensate for both (1) temporal variations of the resonance frequency and damping time of each transducer and (2) initially unknown differences among the resonance frequencies and damping times of different transducers. In other words, the circuit is designed to adjust itself to optimize the performance of whichever transducer is selected at any given time. The basic design concept may be adaptable to other applications that involve the use of piezoelectric transducers in ultrasonic cleaners and other apparatuses in which high-frequency mechanical drives are utilized. This circuit includes three resistor-capacitor networks that, together with the selected piezoelectric transducer, constitute a band-pass filter having a peak response at a frequency of about 2 kHz, which is approximately the resonance frequency of the piezoelectric transducers. Gain for generating oscillations is provided by a power hybrid operational amplifier (U1). A junction field-effect transistor (Q1) in combination with a resistor (R4) is used as a voltage-variable resistor to control the magnitude of the oscillation. The voltage-variable resistor is part of a feedback control loop: Part of the output of the oscillator is rectified and filtered for use as a slow negative feedback to the gate of Q1 to keep the output amplitude constant. The response of this control loop is much slower than 2 kHz and, therefore, does not introduce significant distortion of the oscillator output, which is a fairly clean sine wave. The positive AC feedback needed to sustain oscillations is derived from sampling the current through the piezoelectric transducer. This positive AC feedback, in combination with the slow feedback to the voltage-variable resistors, causes the overall loop gain to be just large enough to keep the oscillator running. The positive feedback loop includes two 16-channel multiplexers, which are not shown in the figure. One multiplexer is used to select the desired piezoelectric transducer. The other multiplexer, which is provided for use in the event that there are significant differences among the damping times of the 16 piezoelectric transducers, facilitates changing the value of one of the resistors in the positive-feedback loop to accommodate the damping time of the selected transducer.

ELECTRICAL PULSE COUNTER APPARATUS

DOEpatents

Kaufman, W.M.; Jeeves, T.A.

1962-09-01

A progressive electrical pulse counter circuit rs designed for the counting of a chain of input pulses. The circuit employs a series of direct connected bistable counting stages simultaneously pulsed by each input pulse and a delay means connected between each of the stages. Each bistable stage has two d-c operative states, which stage, when in its initial state, prevents the next succeeding stage from changing its condition when the latter stage is pulsed. Since the delay circuits between the stages prevents the immediate decay of the d-c state of each stage when the stages are pulsed, only one stage will change its state for each input pulse, thereby providing progressive stage-by-stage counting. (AEC)

Understanding the Hysteresis Loop Conundrum in Pharmacokinetic / Pharmacodynamic Relationships

PubMed Central

Louizos, Christopher; Yáñez, Jaime A.; Forrest, Laird; Davies, Neal M.

2015-01-01

Hysteresis loops are phenomena that sometimes are encountered in the analysis of pharmacokinetic and pharmacodynamic relationships spanning from pre-clinical to clinical studies. When hysteresis occurs it provides insight into the complexity of drug action and disposition that can be encountered. Hysteresis loops suggest that the relationship between drug concentration and the effect being measured is not a simple direct relationship, but may have an inherent time delay and disequilibrium, which may be the result of metabolites, the consequence of changes in pharmacodynamics or the use of a non-specific assay or may involve an indirect relationship. Counter-clockwise hysteresis has been generally defined as the process in which effect can increase with time for a given drug concentration, while in the case of clockwise hysteresis the measured effect decreases with time for a given drug concentration. Hysteresis loops can occur as a consequence of a number of different pharmacokinetic and pharmacodynamic mechanisms including tolerance, distributional delay, feedback regulation, input and output rate changes, agonistic or antagonistic active metabolites, uptake into active site, slow receptor kinetics, delayed or modified activity, time-dependent protein binding and the use of racemic drugs among other factors. In this review, each of these various causes of hysteresis loops are discussed, with incorporation of relevant examples of drugs demonstrating these relationships for illustrative purposes. Furthermore, the effect that pharmaceutical formulation has on the occurrence and potential change in direction of the hysteresis loop, and the major pharmacokinetic / pharmacodynamic modeling approaches utilized to collapse and model hysteresis are detailed. PMID:24735761

A clocking discipline for two-phase digital integrated circuits

NASA Astrophysics Data System (ADS)

Noice, D. C.

1983-09-01

Sooner or later a designer of digital circuits must face the problem of timing verification so he can avoid errors caused by clock skew, critical races, and hazards. Unlike previous verification methods, such as timing simulation and timing analysis, the approach presented here guarantees correct operation despite uncertainty about delays in the circuit. The result is a clocking discipline that deals with timing abstractions only. It is not based on delay calculations; it is only concerned with the correct, synchronous operation at some clock rate. Accordingly, it may be used earlier in the design cycle, which is particularly important to integrated circuit designs. The clocking discipline consists of a notation of clocking types, and composition rules for using the types. Together, the notation and rules define a formal theory of two phase clocking. The notation defines the names and exact characteristics for different signals that are used in a two phase digital system. The notation makes it possible to develop rules for propagating the clocking types through particular circuits.

Delayed Maturation of Fast-Spiking Interneurons Is Rectified by Activation of the TrkB Receptor in the Mouse Model of Fragile X Syndrome

PubMed Central

Nomura, Toshihiro; Zhu, Yiwen; Remmers, Christine L.; Xu, Jian; Nicholson, Daniel A.

2017-01-01

Fragile X syndrome (FXS) is a neurodevelopmental disorder that is a leading cause of inherited intellectual disability, and the most common known cause of autism spectrum disorder. FXS is broadly characterized by sensory hypersensitivity and several developmental alterations in synaptic and circuit function have been uncovered in the sensory cortex of the mouse model of FXS (Fmr1 KO). GABA-mediated neurotransmission and fast-spiking (FS) GABAergic interneurons are central to cortical circuit development in the neonate. Here we demonstrate that there is a delay in the maturation of the intrinsic properties of FS interneurons in the sensory cortex, and a deficit in the formation of excitatory synaptic inputs on to these neurons in neonatal Fmr1 KO mice. Both these delays in neuronal and synaptic maturation were rectified by chronic administration of a TrkB receptor agonist. These results demonstrate that the maturation of the GABAergic circuit in the sensory cortex is altered during a critical developmental period due in part to a perturbation in BDNF-TrkB signaling, and could contribute to the alterations in cortical development underlying the sensory pathophysiology of FXS. SIGNIFICANCE STATEMENT Fragile X (FXS) individuals have a range of sensory related phenotypes, and there is growing evidence of alterations in neuronal circuits in the sensory cortex of the mouse model of FXS (Fmr1 KO). GABAergic interneurons are central to the correct formation of circuits during cortical critical periods. Here we demonstrate a delay in the maturation of the properties and synaptic connectivity of interneurons in Fmr1 KO mice during a critical period of cortical development. The delays both in cellular and synaptic maturation were rectified by administration of a TrkB receptor agonist, suggesting reduced BDNF-TrkB signaling as a contributing factor. These results provide evidence that the function of fast-spiking interneurons is disrupted due to a deficiency in neurotrophin signaling during early development in FXS. PMID:29038238

Closed-loop analysis and control of a non-inverting buck-boost converter

NASA Astrophysics Data System (ADS)

Chen, Zengshi; Hu, Jiangang; Gao, Wenzhong

2010-11-01

In this article, a cascade controller is designed and analysed for a non-inverting buck-boost converter. The fast inner current loop uses sliding mode control. The slow outer voltage loop uses the proportional-integral (PI) control. Stability analysis and selection of PI gains are based on the nonlinear closed-loop error dynamics incorporating both the inner and outer loop controllers. The closed-loop system is proven to have a nonminimum phase structure. The voltage transient due to step changes of input voltage or resistance is predictable. The operating range of the reference voltage is discussed. The controller is validated by a simulation circuit. The simulation results show that the reference output voltage is well-tracked under system uncertainties or disturbances, confirming the validity of the proposed controller.

THE "MUD VOLCANO," A STINKY THERMAL FEATURE ON THE GRAND ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

THE "MUD VOLCANO," A STINKY THERMAL FEATURE ON THE GRAND LOOP ROAD. ACIDIC HOT SPRINGS HAVE REDUCED THE UNDERLYING LAVA TO A FINE CLAY, PRODUCING AN AREA OF BOILING MUD. THE ODOR OF ROTTEN EGGS IS FROM HYDROGEN SULFIDE GAS. - Grand Loop Road, Forming circuit between Mammoth Hot Springs, Norris Junction, Madison Junction, Old Faithful, Mammoth, Park County, WY

A digitally controlled AGC loop circuitry for GNSS receiver chip with a binary weighted accurate dB-linear PGA

NASA Astrophysics Data System (ADS)

Gang, Jin; Yiqi, Zhuang; Yue, Yin; Miao, Cui

2015-03-01

A novel digitally controlled automatic gain control (AGC) loop circuitry for the global navigation satellite system (GNSS) receiver chip is presented. The entire AGC loop contains a programmable gain amplifier (PGA), an AGC circuit and an analog-to-digital converter (ADC), which is implemented in a 0.18 μm complementary metal-oxide-semiconductor (CMOS) process and measured. A binary-weighted approach is proposed in the PGA to achieve wide dB-linear gain control with small gain error. With binary-weighted cascaded amplifiers for coarse gain control, and parallel binary-weighted trans-conductance amplifier array for fine gain control, the PGA can provide a 64 dB dynamic range from -4 to 60 dB in 1.14 dB gain steps with a less than 0.15 dB gain error. Based on the Gaussian noise statistic characteristic of the GNSS signal, a digital AGC circuit is also proposed with low area and fast settling. The feed-backward AGC loop occupies an area of 0.27 mm2 and settles within less than 165 μs while consuming an average current of 1.92 mA at 1.8 V.

Vortex spin-torque oscillator stabilized by phase locked loop using integrated circuits

NASA Astrophysics Data System (ADS)

Kreissig, Martin; Lebrun, R.; Protze, F.; Merazzo-Jaimes, K.; Hem, J.; Vila, L.; Ferreira, R.; Cyrille, M.-C.; Ellinger, F.; Cros, V.; Ebels, U.; Bortolotti, P.

2017-05-01

Spin-torque nano-oscillators (STO) are candidates for the next technological implementation of spintronic devices in commercial electronic systems. For use in microwave applications, improving the noise figures by efficient control of their phase dynamics is a mandatory requirement. In order to achieve this, we developed a compact phase locked loop (PLL) based on custom integrated circuits (ICs) and demonstrate that it represents an efficient way to reduce the phase noise level of a vortex based STO. The advantage of our approach to phase stabilize STOs is that our compact system is highly reconfigurable e.g. in terms of the frequency divider ratio N, RF gain and loop gain. This makes it robust against device to device variations and at the same time compatible with a large range of STOs. Moreover, by taking advantage of the natural highly non-isochronous nature of the STO, the STO frequency can be easily controlled by e.g. changing the divider ratio N.

Bidirectional control system for energy flow in solar powered flywheel

NASA Technical Reports Server (NTRS)

Nola, Frank J. (Inventor)

1987-01-01

An energy storage system for a spacecraft is provided which employs a solar powered flywheel arrangement including a motor/generator which, in different operating modes, drives the flywheel and is driven thereby. A control circuit, including a threshold comparator, senses the output of a solar energy converter, and when a threshold voltage is exceeded thereby indicating the availability of solar power for the spacecraft loads, activates a speed control loop including the motor/generator so as to accelerate the flywheel to a constant speed and thereby store mechanical energy, while also supplying energy from the solar converter to the loads. Under circumstances where solar energy is not available and thus the threshold voltage is not exceeded, the control circuit deactivates the speed control loop and activates a voltage control loop that provides for operation of the motor as a generator so that mechanical energy from the flywheel is converted into electrical energy for supply to the spacecraft loads.

Varying self-inductance and energy storage in a sheared force-free arcade. [of coronal loops

NASA Technical Reports Server (NTRS)

Zuccarello, F.; Burm, H.; Kuperus, M.; Raadu, M.; Spicer, D. S.

1987-01-01

An electric circuit analogy is used to model the build-up and storage of magnetic energy in the coronal loops known to exist in the atmosphere of the sun. The present parameterization of magnetic energy storage in an electric circuit analog uses a bulk current I flowing in the circuit and a self-inductance L. Because the self-inductance is determined by the geometry of the magnetic configuration any change in its dimensions will change L. If L is increased, the amount of magnetic energy stored and the rate at which magnetic energy is stored are both increased. One way of increasing L is to shear the magnetic field lines and increase their effective geometrical length. Using the force-free field approximation for a magnetic arcade whose field lines are sheared by photospheric motions, it is demonstrated that the increase of magnetic energy is initially due to the increase of the current intensity I and later mainly due to the increase of the self-inductance.

A portable expression resource for engineering cross-species genetic circuits and pathways

PubMed Central

Kushwaha, Manish; Salis, Howard M.

2015-01-01

Genetic circuits and metabolic pathways can be reengineered to allow organisms to process signals and manufacture useful chemicals. However, their functions currently rely on organism-specific regulatory parts, fragmenting synthetic biology and metabolic engineering into host-specific domains. To unify efforts, here we have engineered a cross-species expression resource that enables circuits and pathways to reuse the same genetic parts, while functioning similarly across diverse organisms. Our engineered system combines mixed feedback control loops and cross-species translation signals to autonomously self-regulate expression of an orthogonal polymerase without host-specific promoters, achieving nontoxic and tuneable gene expression in diverse Gram-positive and Gram-negative bacteria. Combining 50 characterized system variants with mechanistic modelling, we show how the cross-species expression resource's dynamics, capacity and toxicity are controlled by the control loops' architecture and feedback strengths. We also demonstrate one application of the resource by reusing the same genetic parts to express a biosynthesis pathway in both model and non-model hosts. PMID:26184393

Realisation of all 16 Boolean logic functions in a single magnetoresistance memory cell.

PubMed

Gao, Shuang; Yang, Guang; Cui, Bin; Wang, Shouguo; Zeng, Fei; Song, Cheng; Pan, Feng

2016-07-07

Stateful logic circuits based on next-generation nonvolatile memories, such as magnetoresistance random access memory (MRAM), promise to break the long-standing von Neumann bottleneck in state-of-the-art data processing devices. For the successful commercialisation of stateful logic circuits, a critical step is realizing the best use of a single memory cell to perform logic functions. In this work, we propose a method for implementing all 16 Boolean logic functions in a single MRAM cell, namely a magnetoresistance (MR) unit. Based on our experimental results, we conclude that this method is applicable to any MR unit with a double-hump-like hysteresis loop, especially pseudo-spin-valve magnetic tunnel junctions with a high MR ratio. Moreover, after simply reversing the correspondence between voltage signals and output logic values, this method could also be applicable to any MR unit with a double-pit-like hysteresis loop. These results may provide a helpful solution for the final commercialisation of MRAM-based stateful logic circuits in the near future.

Inhibitory Control in the Cortico-Basal Ganglia-Thalamocortical Loop: Complex Regulation and Interplay with Memory and Decision Processes.

PubMed

Wei, Wei; Wang, Xiao-Jing

2016-12-07

We developed a circuit model of spiking neurons that includes multiple pathways in the basal ganglia (BG) and is endowed with feedback mechanisms at three levels: cortical microcircuit, corticothalamic loop, and cortico-BG-thalamocortical system. We focused on executive control in a stop signal task, which is known to depend on BG across species. The model reproduces a range of experimental observations and shows that the newly discovered feedback projection from external globus pallidus to striatum is crucial for inhibitory control. Moreover, stopping process is enhanced by the cortico-subcortical reverberatory dynamics underlying persistent activity, establishing interdependence between working memory and inhibitory control. Surprisingly, the stop signal reaction time (SSRT) can be adjusted by weights of certain connections but is insensitive to other connections in this complex circuit, suggesting novel circuit-based intervention for inhibitory control deficits associated with mental illness. Our model provides a unified framework for inhibitory control, decision making, and working memory. Copyright © 2016 Elsevier Inc. All rights reserved.

Development and Analysis of Cold Trap for Use in Fission Surface Power-Primary Test Circuit

NASA Technical Reports Server (NTRS)

Wolfe, T. M.; Dervan, C. A.; Pearson, J. B.; Godfroy, T. J.

2012-01-01

The design and analysis of a cold trap proposed for use in the purification of circulated eutectic sodium potassium (NaK-78) loops is presented. The cold trap is designed to be incorporated into the Fission Surface Power-Primary Test Circuit (FSP-PTC), which incorporates a pumped NaK loop to simulate in-space nuclear reactor-based technology using non-nuclear test methodology as developed by the Early Flight Fission-Test Facility. The FSP-PTC provides a test circuit for the development of fission surface power technology. This system operates at temperatures that would be similar to those found in a reactor (500-800 K). By dropping the operating temperature of a specified percentage of NaK flow through a bypass containing a forced circulation cold trap, the NaK purity level can be increased by precipitating oxides from the NaK and capturing them within the cold trap. This would prevent recirculation of these oxides back through the system, which may help prevent corrosion.

The impact of command signal power distribution, processing delays, and speed scaling on neurally-controlled devices.

PubMed

Marathe, A R; Taylor, D M

2015-08-01

Decoding algorithms for brain-machine interfacing (BMI) are typically only optimized to reduce the magnitude of decoding errors. Our goal was to systematically quantify how four characteristics of BMI command signals impact closed-loop performance: (1) error magnitude, (2) distribution of different frequency components in the decoding errors, (3) processing delays, and (4) command gain. To systematically evaluate these different command features and their interactions, we used a closed-loop BMI simulator where human subjects used their own wrist movements to command the motion of a cursor to targets on a computer screen. Random noise with three different power distributions and four different relative magnitudes was added to the ongoing cursor motion in real time to simulate imperfect decoding. These error characteristics were tested with four different visual feedback delays and two velocity gains. Participants had significantly more trouble correcting for errors with a larger proportion of low-frequency, slow-time-varying components than they did with jittery, higher-frequency errors, even when the error magnitudes were equivalent. When errors were present, a movement delay often increased the time needed to complete the movement by an order of magnitude more than the delay itself. Scaling down the overall speed of the velocity command can actually speed up target acquisition time when low-frequency errors and delays are present. This study is the first to systematically evaluate how the combination of these four key command signal features (including the relatively-unexplored error power distribution) and their interactions impact closed-loop performance independent of any specific decoding method. The equations we derive relating closed-loop movement performance to these command characteristics can provide guidance on how best to balance these different factors when designing BMI systems. The equations reported here also provide an efficient way to compare a diverse range of decoding options offline.

The impact of command signal power distribution, processing delays, and speed scaling on neurally-controlled devices

NASA Astrophysics Data System (ADS)

Marathe, A. R.; Taylor, D. M.

2015-08-01

Objective. Decoding algorithms for brain-machine interfacing (BMI) are typically only optimized to reduce the magnitude of decoding errors. Our goal was to systematically quantify how four characteristics of BMI command signals impact closed-loop performance: (1) error magnitude, (2) distribution of different frequency components in the decoding errors, (3) processing delays, and (4) command gain. Approach. To systematically evaluate these different command features and their interactions, we used a closed-loop BMI simulator where human subjects used their own wrist movements to command the motion of a cursor to targets on a computer screen. Random noise with three different power distributions and four different relative magnitudes was added to the ongoing cursor motion in real time to simulate imperfect decoding. These error characteristics were tested with four different visual feedback delays and two velocity gains. Main results. Participants had significantly more trouble correcting for errors with a larger proportion of low-frequency, slow-time-varying components than they did with jittery, higher-frequency errors, even when the error magnitudes were equivalent. When errors were present, a movement delay often increased the time needed to complete the movement by an order of magnitude more than the delay itself. Scaling down the overall speed of the velocity command can actually speed up target acquisition time when low-frequency errors and delays are present. Significance. This study is the first to systematically evaluate how the combination of these four key command signal features (including the relatively-unexplored error power distribution) and their interactions impact closed-loop performance independent of any specific decoding method. The equations we derive relating closed-loop movement performance to these command characteristics can provide guidance on how best to balance these different factors when designing BMI systems. The equations reported here also provide an efficient way to compare a diverse range of decoding options offline.

Arcjet power supply and start circuit

NASA Technical Reports Server (NTRS)

Gruber, Robert P. (Inventor)

1988-01-01

A dc power supply for spacecraft arcjet thrusters has an integral automatic starting circuit and an output averaging inductor. The output averaging inductor, in series with the load, provides instantaneous current control, and ignition pulse and an isolated signal proportional to the arc voltage. A pulse width modulated converter, close loop configured, is also incorporated to give fast response output current control.

Origin of bistability underlying mammalian cell cycle entry

PubMed Central

Yao, Guang; Tan, Cheemeng; West, Mike; Nevins, Joseph R; You, Lingchong

2011-01-01

Precise control of cell proliferation is fundamental to tissue homeostasis and differentiation. Mammalian cells commit to proliferation at the restriction point (R-point). It has long been recognized that the R-point is tightly regulated by the Rb–E2F signaling pathway. Our recent work has further demonstrated that this regulation is mediated by a bistable switch mechanism. Nevertheless, the essential regulatory features in the Rb–E2F pathway that create this switching property have not been defined. Here we analyzed a library of gene circuits comprising all possible link combinations in a simplified Rb–E2F network. We identified a minimal circuit that is able to generate robust, resettable bistability. This minimal circuit contains a feed-forward loop coupled with a mutual-inhibition feedback loop, which forms an AND-gate control of the E2F activation. Underscoring its importance, experimental disruption of this circuit abolishes maintenance of the activated E2F state, supporting its importance for the bistability of the Rb–E2F system. Our findings suggested basic design principles for the robust control of the bistable cell cycle entry at the R-point. PMID:21525871

A systems analysis of the erythropoietic responses to weightlessness. Volume 2: Description of the model of erythropoiesis regulation. Part A: Model for regulation of erythropoiesis. Part B: Detailed description of the model for regulation of erythropoiesis

NASA Technical Reports Server (NTRS)

Leonard, J. I.

1985-01-01

A mathematical model of the erythropoiesis on total red blood cell mass is presented. The loss of red cell mass has been a consistent finding during space flight. Computer simulation of this phenomenon required a model that could account for oxygen transport, red cell production, and red cell destruction. The elements incorporated into the feedback regulation loop of the model are based on the accepted concept that erythrocyte production is governed by the balance between oxygen supply and demand in the body. The mechanisms and pathways of the control circuit include oxygenation of hemoglobin and oxygenation of tissues by blood transport and diffusional processes. Other features of the model include a variable oxygen-hemoglobin affinity, and time delays which represent time for erythropoietin (erythrocyte-stimulating hormone) distribution in plasma, and time for maturation of the erythrocytes in bone marrow.

MicroRNA filters Hox temporal transcription noise to confer boundary formation in the spinal cord

NASA Astrophysics Data System (ADS)

Li, Chung-Jung; Hong, Tian; Tung, Ying-Tsen; Yen, Ya-Ping; Hsu, Ho-Chiang; Lu, Ya-Lin; Chang, Mien; Nie, Qing; Chen, Jun-An

2017-03-01

The initial rostrocaudal patterning of the neural tube leads to differential expression of Hox genes that contribute to the specification of motor neuron (MN) subtype identity. Although several 3' Hox mRNAs are expressed in progenitors in a noisy manner, these Hox proteins are not expressed in the progenitors and only become detectable in postmitotic MNs. MicroRNA biogenesis impairment leads to precocious expression and propagates the noise of Hoxa5 at the protein level, resulting in an imprecise Hoxa5-Hoxc8 boundary. Here we uncover, using in silico simulation, two feed-forward Hox-miRNA loops accounting for the precocious and noisy Hoxa5 expression, as well as an ill-defined boundary phenotype in Dicer mutants. Finally, we identify mir-27 as a major regulator coordinating the temporal delay and spatial boundary of Hox protein expression. Our results provide a novel trans Hox-miRNA circuit filtering transcription noise and controlling the timing of protein expression to confer robust individual MN identity.

A Conversion of Wheatstone Bridge to Current-Loop Signal Conditioning for Strain Gages

NASA Technical Reports Server (NTRS)

Anderson, Karl F.

1995-01-01

Current loop circuitry replaced Wheatstone bridge circuitry to signal-condition strain gage transducers in more than 350 data channels for two different test programs at NASA Dryden Flight Research Center. The uncorrected test data from current loop circuitry had a lower noise level than data from comparable Wheatstone bridge circuitry, were linear with respect to gage-resistance change, and were uninfluenced by varying lead-wire resistance. The current loop channels were easier for the technicians to set up, verify, and operate than equivalent Wheatstone bridge channels. Design choices and circuit details are presented in this paper in addition to operational experience.

Method for reworkable packaging of high speed, low electrical parasitic power electronics modules through gate drive integration

DOEpatents

Passmore, Brandon; Cole, Zach; Whitaker, Bret; Barkley, Adam; McNutt, Ty; Lostetter, Alexander

2016-08-02

A multichip power module directly connecting the busboard to a printed-circuit board that is attached to the power substrate enabling extremely low loop inductance for extreme environments such as high temperature operation. Wire bond interconnections are taught from the power die directly to the busboard further enabling enable low parasitic interconnections. Integration of on-board high frequency bus capacitors provide extremely low loop inductance. An extreme environment gate driver board allows close physical proximity of gate driver and power stage to reduce overall volume and reduce impedance in the control circuit. Parallel spring-loaded pin gate driver PCB connections allows a reliable and reworkable power module to gate driver interconnections.

Wireless Power Transfer for Space Applications

NASA Technical Reports Server (NTRS)

Ramos, Gabriel Vazquez; Yuan, Jiann-Shiun

2011-01-01

This paper introduces an implementation for magnetic resonance wireless power transfer for space applications. The analysis includes an equivalent impedance study, loop material characterization, source/load resonance coupling technique, and system response behavior due to loads variability. System characterization is accomplished by executing circuit design from analytical equations and simulations using Matlab and SPICE. The theory was validated by a combination of different experiments that includes loop material consideration, resonance coupling circuits considerations, electric loads considerations and a small scale proof-of-concept prototype. Experiment results shows successful wireless power transfer for all the cases studied. The prototype provided about 4.5 W of power to the load at a separation of -5 cm from the source using a power amplifier rated for 7 W.

Analysis of virtual passive controllers for flexible space structures

NASA Technical Reports Server (NTRS)

Williams, Trevor W.

1992-01-01

The dynamics of flexible spacecraft are not usually well known before launch. This makes it important to develop controllers for such systems that can never be destabilized by perturbations in the structural model. Virtual passive controllers, or active vibration absorbers, possess this guaranteed stability property; they mimic a fictitious flexible structure attached to the true physical one. This report analyzes the properties of such controllers, and shows that disturbance absorption behavior can be naturally described in terms of a set of virtual zeros that they introduce into the closed-loop dynamics of the system. Based on this analysis, techniques are then derived for selecting the active vibration absorber internal parameters, i.e., the gain matrices of such controllers, so as to achieve specified control objectives. Finally, the effects on closed-loop stability of small delays in the feedback loop are investigated. Such delays would typically be introduced by a digital implementation of an active vibration absorber. It is shown that these delays only affect the real parts of the eigenvalues of a lightly-damped structure. Furthermore, it is only the high-frequency modes that are destabilized by delays; low-frequency modes are actually made more heavily damped. Eigenvalue perturbation methods are used to obtain accurate predictions of the critical delay at which a given system will become unstable; these methods also determine which mode is critical.

Pulse advancement and delay in an integrated-optical two-port ring-resonator circuit: direct experimental observations.

PubMed

Uranus, H P; Zhuang, L; Roeloffzen, C G H; Hoekstra, H J W M

2007-09-01

We report experimental observations of the negative-group-velocity (v(g)) phenomenon in an integrated-optical two-port ring-resonator circuit. We demonstrate that when the v(g) is negative, the (main) peak of output pulse appears earlier than the peak of a reference pulse, while for a positive v(g), the situation is the other way around. We observed that a pulse splitting phenomenon occurs in the neighborhood of the critical-coupling point. This pulse splitting limits the maximum achievable delay and advancement of a single device as well as facilitating a smooth transition from highly advanced to highly delayed pulse, and vice versa, across the critical-coupling point.

CK1/Doubletime activity delays transcription activation in the circadian clock

PubMed Central

O'Neil, Jenna L; Merz, Gregory E; Dusad, Kritika; Crane, Brian R; Young, Michael W

2018-01-01

In the Drosophila circadian clock, Period (PER) and Timeless (TIM) proteins inhibit Clock-mediated transcription of per and tim genes until PER is degraded by Doubletime/CK1 (DBT)-mediated phosphorylation, establishing a negative feedback loop. Multiple regulatory delays within this feedback loop ensure ~24 hr periodicity. Of these delays, the mechanisms that regulate delayed PER degradation (and Clock reactivation) remain unclear. Here we show that phosphorylation of certain DBT target sites within a central region of PER affect PER inhibition of Clock and the stability of the PER/TIM complex. Our results indicate that phosphorylation of PER residue S589 stabilizes and activates PER inhibitory function in the presence of TIM, but promotes PER degradation in its absence. The role of DBT in regulating PER activity, stabilization and degradation ensures that these events are chronologically and biochemically linked, and contributes to the timing of an essential delay that influences the period of the circadian clock. PMID:29611807

The design and hardware implementation of a low-power real-time seizure detection algorithm

NASA Astrophysics Data System (ADS)

Raghunathan, Shriram; Gupta, Sumeet K.; Ward, Matthew P.; Worth, Robert M.; Roy, Kaushik; Irazoqui, Pedro P.

2009-10-01

Epilepsy affects more than 1% of the world's population. Responsive neurostimulation is emerging as an alternative therapy for the 30% of the epileptic patient population that does not benefit from pharmacological treatment. Efficient seizure detection algorithms will enable closed-loop epilepsy prostheses by stimulating the epileptogenic focus within an early onset window. Critically, this is expected to reduce neuronal desensitization over time and lead to longer-term device efficacy. This work presents a novel event-based seizure detection algorithm along with a low-power digital circuit implementation. Hippocampal depth-electrode recordings from six kainate-treated rats are used to validate the algorithm and hardware performance in this preliminary study. The design process illustrates crucial trade-offs in translating mathematical models into hardware implementations and validates statistical optimizations made with empirical data analyses on results obtained using a real-time functioning hardware prototype. Using quantitatively predicted thresholds from the depth-electrode recordings, the auto-updating algorithm performs with an average sensitivity and selectivity of 95.3 ± 0.02% and 88.9 ± 0.01% (mean ± SEα = 0.05), respectively, on untrained data with a detection delay of 8.5 s [5.97, 11.04] from electrographic onset. The hardware implementation is shown feasible using CMOS circuits consuming under 350 nW of power from a 250 mV supply voltage from simulations on the MIT 180 nm SOI process.

An Electromagnetically Actuated Vacuum Circuit Breaker Developed by Electromagnetic Analysis Coupled with Motion

NASA Astrophysics Data System (ADS)

Takeuchi, Toshie; Nakagawa, Takafumi; Tsukima, Mitsuru; Koyama, Kenichi; Tohya, Nobumoto; Yano, Tomotaka

A new electromagnetically actuated vacuum circuit breaker (VCB) has been designed and developed on the basis of the transient electromagnetic analysis coupled with motion. The VCB has three advanced bi-stable electromagnetic actuators, which control each phase independently. The VCB serves as a synchronous circuit breaker as well as a standard circuit breaker. In this work, the flux delay due to the eddy current is analytically formulated using the delay time constant of the actuator coil current, thereby leading to accurate driving behavior. With this analytical method, the electromagnetic mechanism for a 24kV rated VCB has been optimized; and as a result, the driving energy is reduced to one fifth of that of a conventional VCB employing spring mechanism, and the number of parts is significantly decreased. Therefore, the developed VCB becomes compact, highly reliable and highly durable.

An observer-based compensator for distributed delays

NASA Technical Reports Server (NTRS)

Luck, Rogelio; Ray, Asok

1990-01-01

This paper presents an algorithm for compensating delays that are distributed between the sensor(s), controller and actuator(s) within a control loop. This observer-based algorithm is specially suited to compensation of network-induced delays in integrated communication and control systems. The robustness of the algorithm relative to plant model uncertainties has been examined.

System and method for assaying a radionuclide

DOEpatents

Cadieux, James R; King, III, George S; Fugate, Glenn A

2014-12-23

A system for assaying a radionuclide includes a liquid scintillation detector, an analyzer connected to the liquid scintillation detector, and a delay circuit connected to the analyzer. A gamma detector and a multi-channel analyzer are connected to the delay circuit and the gamma detector. The multi-channel analyzer produces a signal reflective of the radionuclide in the sample. A method for assaying a radionuclide includes selecting a sample, detecting alpha or beta emissions from the sample with a liquid scintillation detector, producing a first signal reflective of the alpha or beta emissions, and delaying the first signal a predetermined time. The method further includes detecting gamma emissions from the sample, producing a second signal reflective of the gamma emissions, and combining the delayed first signal with the second signal to produce a third signal reflective of the radionuclide.

Magnetic field homogeneity of a conical coaxial coil pair.

PubMed

Salazar, F J; Nieves, F J; Bayón, A; Gascón, F

2017-09-01

An analytical study of the magnetic field created by a double-conical conducting sheet is presented. The analysis is based on the expansion of the magnetic field in terms of Legendre polynomials. It is demonstrated analytically that the angle of the conical surface that produces a nearly homogeneous magnetic field coincides with that of a pair of loops that fulfills the Helmholtz condition. From the results obtained, we propose an electric circuit formed by pairs of isolated conducting loops tightly wound around a pair of conical surfaces, calculating numerically the magnetic field produced by this system and its heterogeneity. An experimental setup of the proposed circuit was constructed and its magnetic field was measured. The results were compared with those obtained by numerical calculation, finding a good agreement. The numerical results demonstrate a significant improvement in homogeneity in the field of the proposed pair of conical coils compared with that achieved with a simple pair of Helmholtz loops or with a double solenoid. Moreover, a new design of a double pair of conical coils based on Braunbek's four loops is also proposed to achieve greater homogeneity. Regarding homogeneity, the rating of the analyzed configurations from best to worst is as follows: (1) double pair of conical coils, (2) pair of conical coils, (3) Braunbek's four loops, (4) Helmholtz pair, and (5) solenoid pair.

Magnetic field homogeneity of a conical coaxial coil pair

NASA Astrophysics Data System (ADS)

Salazar, F. J.; Nieves, F. J.; Bayón, A.; Gascón, F.

2017-09-01

An analytical study of the magnetic field created by a double-conical conducting sheet is presented. The analysis is based on the expansion of the magnetic field in terms of Legendre polynomials. It is demonstrated analytically that the angle of the conical surface that produces a nearly homogeneous magnetic field coincides with that of a pair of loops that fulfills the Helmholtz condition. From the results obtained, we propose an electric circuit formed by pairs of isolated conducting loops tightly wound around a pair of conical surfaces, calculating numerically the magnetic field produced by this system and its heterogeneity. An experimental setup of the proposed circuit was constructed and its magnetic field was measured. The results were compared with those obtained by numerical calculation, finding a good agreement. The numerical results demonstrate a significant improvement in homogeneity in the field of the proposed pair of conical coils compared with that achieved with a simple pair of Helmholtz loops or with a double solenoid. Moreover, a new design of a double pair of conical coils based on Braunbek's four loops is also proposed to achieve greater homogeneity. Regarding homogeneity, the rating of the analyzed configurations from best to worst is as follows: (1) double pair of conical coils, (2) pair of conical coils, (3) Braunbek's four loops, (4) Helmholtz pair, and (5) solenoid pair.

Circuit for echo and noise suppression of accoustic signals transmitted through a drill string

DOEpatents

Drumheller, Douglas S.; Scott, Douglas D.

1993-01-01

An electronic circuit for digitally processing analog electrical signals produced by at least one acoustic transducer is presented. In a preferred embodiment of the present invention, a novel digital time delay circuit is utilized which employs an array of First-in-First-out (FiFo) microchips. Also, a bandpass filter is used at the input to this circuit for isolating drill string noise and eliminating high frequency output.

The Basal Ganglia and Adaptive Motor Control

NASA Astrophysics Data System (ADS)

Graybiel, Ann M.; Aosaki, Toshihiko; Flaherty, Alice W.; Kimura, Minoru

1994-09-01

The basal ganglia are neural structures within the motor and cognitive control circuits in the mammalian forebrain and are interconnected with the neocortex by multiple loops. Dysfunction in these parallel loops caused by damage to the striatum results in major defects in voluntary movement, exemplified in Parkinson's disease and Huntington's disease. These parallel loops have a distributed modular architecture resembling local expert architectures of computational learning models. During sensorimotor learning, such distributed networks may be coordinated by widely spaced striatal interneurons that acquire response properties on the basis of experienced reward.

Experiments with arbitrary networks in time-multiplexed delay systems

NASA Astrophysics Data System (ADS)

Hart, Joseph D.; Schmadel, Don C.; Murphy, Thomas E.; Roy, Rajarshi

2017-12-01

We report a new experimental approach using an optoelectronic feedback loop to investigate the dynamics of oscillators coupled on large complex networks with arbitrary topology. Our implementation is based on a single optoelectronic feedback loop with time delays. We use the space-time interpretation of systems with time delay to create large networks of coupled maps. Others have performed similar experiments using high-pass filters to implement the coupling; this restricts the network topology to the coupling of only a few nearest neighbors. In our experiment, the time delays and coupling are implemented on a field-programmable gate array, allowing the creation of networks with arbitrary coupling topology. This system has many advantages: the network nodes are truly identical, the network is easily reconfigurable, and the network dynamics occur at high speeds. We use this system to study cluster synchronization and chimera states in both small and large networks of different topologies.

Relative position coordinated control for spacecraft formation flying with communication delays

NASA Astrophysics Data System (ADS)

Ran, Dechao; Chen, Xiaoqian; Misra, Arun K.; Xiao, Bing

2017-08-01

This study addresses a relative position coordinated control problem for spacecraft formation flying subject to directed communication topology. Two different kinds of communication delay cases, including time-varying delays and arbitrarily bounded delays are investigated. Using the backstepping control technique, two virtual velocity control inputs are firstly designed to achieve coordinated position tracking for the kinematic subsystem. Furthermore, a hyperbolic tangent function is introduced to guarantee the boundedness of the virtual controller. Then, a finite-time control algorithm is designed for the dynamic subsystem. It can guarantee that the virtual velocity can be followed by the real velocity after finite time. It is theoretically proved that the proposed control scheme can asymptotically stabilize the closed-loop system. Numerical simulations are further presented that not only highlight closed-loop performance benefiting from the proposed control scheme, but also illustrate its superiority in comparison with conventional formation control schemes.

Triple inverter pierce oscillator circuit suitable for CMOS

DOEpatents

Wessendorf,; Kurt, O [Albuquerque, NM

2007-02-27

An oscillator circuit is disclosed which can be formed using discrete field-effect transistors (FETs), or as a complementary metal-oxide-semiconductor (CMOS) integrated circuit. The oscillator circuit utilizes a Pierce oscillator design with three inverter stages connected in series. A feedback resistor provided in a feedback loop about a second inverter stage provides an almost ideal inverting transconductance thereby allowing high-Q operation at the resonator-controlled frequency while suppressing a parasitic oscillation frequency that is inherent in a Pierce configuration using a "standard" triple inverter for the sustaining amplifier. The oscillator circuit, which operates in a range of 10 50 MHz, has applications for use as a clock in a microprocessor and can also be used for sensor applications.

Compact vehicle drive module having improved thermal control

DOEpatents

Meyer, Andreas A.; Radosevich, Lawrence D.; Beihoff, Bruce C.; Kehl, Dennis L.; Kannenberg, Daniel G.

2006-01-03

An electric vehicle drive includes a thermal support may receive one or more power electronic circuits. The support may aid in removing heat from the circuits through fluid circulating through the support, which may be controlled in a closed-loop manner. Interfacing between circuits, circuit mounting structure, and the support provide for greatly enhanced cooling. The support may form a shield from both external EMI/RFI and from interference generated by operation of the power electronic circuits. Features may be provided to permit and enhance connection of the circuitry to external circuitry, such as improved terminal configurations. Modular units may be assembled that may be coupled to electronic circuitry via plug-in arrangements or through interface with a backplane or similar mounting and interconnecting structures.

Use of the quartz crystal microbalance to determine the monomeric friction coefficient of polyimides

NASA Technical Reports Server (NTRS)

Bechtold, Mary M.

1995-01-01

When a thin film of polymer is coated on to a quartz crystal microbalance (QCM), the QCM can be used to detect the rate of increase in weight of the polymer film as the volatile penetrant diffuses into the polymer. From this rate information the diffusion coefficient of the penetrant into the polymer can be computed. Calculations requiring this diffusion coefficient lead to values which approximate the monomeric friction coefficient of the polymer. This project has been concerned with the trial of crystal oscillating circuits suitable for driving polymer coated crystals in an atmosphere of penetrant. For these studies done at room temperature, natural rubber was used as an easily applied polymer that is readily penetrated by toluene vapors, qualities anticipated with polyimides when they are tested at T(g) in the presence of toluene. Three quartz crystal oscillator circuits were tested. The simplest circuit used +/- 5 volt dc and had a transistor to transistor logic (TTL) inverter chip that provides a 180 deg phase shift via a feed back loop. This oscillator circuit was stable but would not drive the crystal when the crystal was coated with polymer and subjected to toluene vapors. Removal of a variable resistor from this circuit increased stability but did not otherwise increase performance. Another driver circuit tested contained a two stage differential input, differential output, wide band video amplifier and also contain a feed back loop. The circuit voltage could not be varied and operated at +/- 5 volts dc; this circuit was also stable but failed to oscillate the polymer coated crystal in an atmosphere saturated with toluene vapors. The third oscillator circuit was of similar construction and relied on the same video amplifier but allowed operation with variable voltage. This circuit would drive the crystal when the crystal was submerged in liquid toluene and when the crystal was coated with polymer and immersed in toluene vapors. The frequency readings obtained when using this oscillating circuit are highly variable. This circuit requires further modification to stabilize frequency readings before its use in studies to determine the diffusion coefficient of penetrant molecules into a polymer film coated on a QCM.

Increased long-latency reflex activity as a sufficient explanation for childhood hypertonic dystonia: a neuromorphic emulation study

NASA Astrophysics Data System (ADS)

Sohn, Won J.; Niu, Chuanxin M.; Sanger, Terence D.

2015-06-01

Objective. Childhood dystonia is a movement disorder that interferes with daily movements and can have a devastating effect on quality of life for children and their families. Although injury to basal ganglia is associated with dystonia, the neurophysiological mechanisms leading to the clinical manifestations of dystonia are not understood. Previous work suggested that long-latency stretch reflex (LLSR) is hyperactive in children with hypertonia due to secondary dystonia. We hypothesize that abnormal activity in motor cortices may cause an increase in the LLSR leading to hypertonia. Approach. We modeled two possibilities of hyperactive LLSR by either creating a tonic involuntary drive to cortex, or increasing the synaptic gain in cortical neurons. Both models are emulated using programmable very-large-scale-integrated-circuit hardware to test their sufficiency for producing dystonic symptoms. The emulation includes a joint with two Hill-type muscles, realistic muscle spindles, and 2,304 Izhikevich-type spiking neurons. The muscles are regulated by a monosynaptic spinal pathway with 32 ms delay and a long-latency pathway with 64 ms loop-delay representing transcortical/supra-spinal connections. Main results. When the limb is passively stretched, both models produce involuntary resistance with increased antagonist EMG responses similar to human data; also the muscle relaxation is delayed similar to human data. Both models predict reduced range of motion in voluntary movements. Significance. Although our model is a highly simplified and limited representation of reflex pathways, it shows that increased activity of the LLSR is by itself sufficient to cause many of the features of hypertonic dystonia.

REVIEWS OF TOPICAL PROBLEMS: Coronal magnetic loops

NASA Astrophysics Data System (ADS)

Zaitsev, Valerii V.; Stepanov, Alexander V.

2008-11-01

The goal of this review is to outline some new ideas in the physics of coronal magnetic loops, the fundamental structural elements of the atmospheres of the Sun and flaring stars, which are involved in phenomena such as stellar coronal heating, flare energy release, charged particle acceleration, and the modulation of optical, radio, and X-ray emissions. The Alfvén-Carlqvist view of a coronal loop as an equivalent electric circuit allows a good physical understanding of loop processes. Describing coronal loops as MHD-resonators explains various ways in which flaring emissions from the Sun and stars are modulated, whereas modeling them by magnetic mirror traps allows one to describe the dynamics and emission of high-energy particles. Based on these approaches, loop plasma and fast particle parameters are obtained and models for flare energy release and stellar corona heating are developed.

Neural Networks For Demodulation Of Phase-Modulated Signals

NASA Technical Reports Server (NTRS)

Altes, Richard A.

1995-01-01

Hopfield neural networks proposed for demodulating quadrature phase-shift-keyed (QPSK) signals carrying digital information. Networks solve nonlinear integral equations prior demodulation circuits cannot solve. Consists of set of N operational amplifiers connected in parallel, with weighted feedback from output terminal of each amplifier to input terminals of other amplifiers. Used to solve signal processing problems. Implemented as analog very-large-scale integrated circuit that achieves rapid convergence. Alternatively, implemented as digital simulation of such circuit. Also used to improve phase estimation performance over that of phase-locked loop.

[Study on a wireless energy transmission system for the noninvasive examination micro system inside alimentary tracts].

PubMed

He, Xiu; Yan, Guo-Zheng; Wang, Fu-Min

2008-01-01

A wireless energy transmission system for the MEMS system inside alimentary tracts is reported here in the paper. It consists of an automatic frequency tracking circuit of phase lock loop and phase shift PWM control circuit. Experimental results show that the energy transmission system is capable of automatic frequency-tracking and transmission power-adjusting and has stable received energy.

Topical Meeting of Broadband Analog and Digital Optoelectronics

DTIC Science & Technology

1992-01-01

effects [2]. Laser nonlinearitics can be minimised by careful design of the device to maximise the relaxation oscillation resonance frequency [2...feedback loop ultimately limits the stability of the circuit and determines the maximum frequency of operation. With hybrid circuit constructioi. this...range and number of accessible frequency channels), the tuning lever, and the filter selectivity (which determines the side-mode suppression ratio (SMSR

Proceedings of the Electronics Manufacturing Seminar (14th Annual) Held in China Lake, California on 21-22 February 1990

DTIC Science & Technology

1990-02-01

Aging effects Aging of metalic surfaces Aqueous cleaning Circuit- card assembly Cleanability Closed-loop soldering Conformal coating Defect...5 Standard Electronic Circuit Card Assembly System ....................................... 7 Douglas Green Lockheed-Sanders Corp. Nashua, New...Facility Naval Weapons Center NAVIRSA Detachment 5 NWC TP 7066 EMPF TR 0010 STANDARD ELECTRONIC CIRCUTT CARD ASSEMBLY SYSTEM (SECAS PROJECT) by Douglas

Closed Loop Deep Brain Stimulation for PTSD, Addiction, and Disorders of Affective Facial Interpretation: Review and Discussion of Potential Biomarkers and Stimulation Paradigms

PubMed Central

Bina, Robert W.; Langevin, Jean-Phillipe

2018-01-01

The treatment of psychiatric diseases with Deep Brain Stimulation (DBS) is becoming more of a reality as studies proliferate the indications and targets for therapies. Opinions on the initial failures of DBS trials for some psychiatric diseases point to a certain lack of finesse in using an Open Loop DBS (OLDBS) system in these dynamic, cyclical pathologies. OLDBS delivers monomorphic input into dysfunctional brain circuits with modulation of that input via human interface at discrete time points with no interim modulation or adaptation to the changing circuit dynamics. Closed Loop DBS (CLDBS) promises dynamic, intrinsic circuit modulation based on individual physiologic biomarkers of dysfunction. Discussed here are several psychiatric diseases which may be amenable to CLDBS paradigms as the neurophysiologic dysfunction is stochastic and not static. Post-Traumatic Stress Disorder (PTSD) has several peripheral and central physiologic and neurologic changes preceding stereotyped hyper-activation behavioral responses. Biomarkers for CLDBS potentially include skin conductance changes indicating changes in the sympathetic nervous system, changes in serum and central neurotransmitter concentrations, and limbic circuit activation. Chemical dependency and addiction have been demonstrated to be improved with both ablation and DBS of the Nucleus Accumbens and as a serendipitous side effect of movement disorder treatment. Potential peripheral biomarkers are similar to those proposed for PTSD with possible use of environmental and geolocation based cues, peripheral signs of physiologic arousal, and individual changes in central circuit patterns. Non-substance addiction disorders have also been serendipitously treated in patients with OLDBS for movement disorders. As more is learned about these behavioral addictions, DBS targets and effectors will be identified. Finally, discussed is the use of facial recognition software to modulate activation of inappropriate responses for psychiatric diseases in which misinterpretation of social cues feature prominently. These include Autism Spectrum Disorder, PTSD, and Schizophrenia—all of which have a common feature of dysfunctional interpretation of facial affective clues. Technological advances and improvements in circuit-based, individual-specific, real-time adaptable modulation, forecast functional neurosurgery treatments for heretofore treatment-resistant behavioral diseases. PMID:29780303

Localizing Circuits of Atrial Macro-Reentry Using ECG Planes of Coherent Atrial Activation

PubMed Central

Kahn, Andrew M.; Krummen, David E.; Feld, Gregory K.; Narayan, Sanjiv M.

2007-01-01

Background The complexity of ablation for atrial macro-reentry (AFL) varies significantly depending upon the circuit location. Presently, surface ECG analysis poorly separates left from right atypical AFL and from some cases of typical AFL, delaying diagnosis until invasive study. Objective To differentiate and localize the intra-atrial circuits of left atypical AFL, right atypical, and typical AFL using quantitative ECG analysis. Methods We studied 66 patients (54 M, age 59±14 years) with typical (n=35), reverse typical (n=4) and atypical (n=27) AFL. For each, we generated filtered atrial waveforms from ECG leads V5 (X-axis), aVF (Y) and V1 (Z) by correlating a 120 ms F-wave sample to successive ECG regions. Atrial spatial loops were plotted for 3 orthogonal planes (frontal, XY=V5/aVF; sagittal, YZ=aVF/V1; axial, XZ=V5/V1), then cross-correlated to measure spatial regularity (‘coherence’: range −1 to 1). Results Mean coherence was greatest in the XY plane (p<10−3 vs XZ or YZ). Atypical AFL showed lower coherence than typical AFL in XY (p<10−3), YZ (p<10−6) and XZ (p<10−5) planes. Atypical left AFL could be separated from atypical right AFL by lower XY coherence (p=0.02); for this plane coherence < 0.69 detected atypical left AFL with 84% specificity and 75% sensitivity. F-wave amplitude did not separate typical, atypical right or atypical left AFL (p=NS). Conclusions Atypical AFL shows lower spatial coherence than typical AFL, particularly in sagittal and axial planes. Coherence in the Cartesian frontal plane separated left and right atypical AFL. Such analyses may be used to plan ablation strategy from the bedside. PMID:17399632

Wide tracking range, auto ranging, low jitter phase lock loop for swept and fixed frequency systems

DOEpatents

Kerner, Thomas M.

2001-01-01

The present invention provides a wide tracking range phase locked loop (PLL) circuit that achieves minimal jitter in a recovered clock signal, regardless of the source of the jitter (i.e. whether it is in the source or the transmission media). The present invention PLL has automatic harmonic lockout detection circuitry via a novel lock and seek control logic in electrical communication with a programmable frequency discriminator and a code balance detector. (The frequency discriminator enables preset of a frequency window of upper and lower frequency limits to derive a programmable range within which signal acquisition is effected. The discriminator works in combination with the code balance detector circuit to minimize the sensitivity of the PLL circuit to random data in the data stream). In addition, the combination of a differential loop integrator with the lock and seek control logic obviates a code preamble and guarantees signal acquisition without harmonic lockup. An adaptive cable equalizer is desirably used in combination with the present invention PLL to recover encoded transmissions containing a clock and/or data. The equalizer automatically adapts to equalize short haul cable lengths of coaxial and twisted pair cables or wires and provides superior jitter performance itself. The combination of the equalizer with the present invention PLL is desirable in that such combination permits the use of short haul wires without significant jitter.

Dynamic impedance compensation for wireless power transfer using conjugate power

NASA Astrophysics Data System (ADS)

Liu, Suqi; Tan, Jianping; Wen, Xue

2018-02-01

Wireless power transfer (WPT) via coupled magnetic resonances has been in development for over a decade. However, the frequency splitting phenomenon occurs in the over-coupled region. Thus, the output power of the two-coil system achieves the maximum output power at the two splitting angular frequencies, and not at the natural resonant angular frequency. According to the maximum power transfer theorem, the impedance compensation method was adopted in many WPT projects. However, it remains a challenge to achieve the maximum output power and transmission efficiency in a fixed-frequency mode. In this study, dynamic impedance compensation for WPT was presented by utilizing the compensator within a virtual three-coil WPT system. First, the circuit model was established and transfer characteristics of a system were studied by utilizing circuit theories. Second, the power superposition of the WPT system was carefully researched. When a pair of compensating coils was inserted into the transmitter loop, the conjugate power of the compensator loop was created via magnetic coupling of the two compensating coils that insert into the transmitter loop. The mechanism for dynamic impedance compensation for wireless power transfer was then provided by investigating a virtual three-coil WPT system. Finally, the experimental circuit of a virtual three-coil WPT system was designed, and experimental results are consistent with the theoretical analysis, which achieves the maximum output power and transmission efficiency.

78 FR 8675 - Self-Regulatory Organizations; International Securities Exchange, LLC; Notice of Filing and...

Federal Register 2010, 2011, 2012, 2013, 2014

2013-02-06

... Proposed Rule Change to Amend ISE Rule 2102 to Extend the Market-Wide Circuit Breaker Pilot Program January...- wide circuit breaker on a pilot basis for a period that corresponds to the pilot period for the LULD... delay the operative date of the market-wide circuit breaker pilot to April 8, 2013 in order for the...

78 FR 8666 - Self-Regulatory Organizations; The NASDAQ Stock Market LLC; Notice of Filing and Immediate...

Federal Register 2010, 2011, 2012, 2013, 2014

2013-02-06

... adopted the proposed changes to the market-wide circuit breakers on a pilot basis for a period that... to April 8, 2013. The proposal would delay the operative date of the market-wide circuit breaker pilot to April 8, 2013 in order for the implementation date for the market-wide circuit breaker pilot...

Triggerable electro-optic amplitude modulator bias stabilizer for integrated optical devices

DOEpatents

Conder, A.D.; Haigh, R.E.; Hugenberg, K.F.

1995-09-26

An improved Mach-Zehnder integrated optical electro-optic modulator is achieved by application and incorporation of a DC bias box containing a laser synchronized trigger circuit, a DC ramp and hold circuit, a modulator transfer function negative peak detector circuit, and an adjustable delay circuit. The DC bias box ramps the DC bias along the transfer function curve to any desired phase or point of operation at which point the RF modulation takes place. 7 figs.

Triggerable electro-optic amplitude modulator bias stabilizer for integrated optical devices

DOEpatents

Conder, Alan D.; Haigh, Ronald E.; Hugenberg, Keith F.

1995-01-01

An improved Mach-Zehnder integrated optical electro-optic modulator is achieved by application and incorporation of a DC bias box containing a laser synchronized trigger circuit, a DC ramp and hold circuit, a modulator transfer function negative peak detector circuit, and an adjustable delay circuit. The DC bias box ramps the DC bias along the transfer function curve to any desired phase or point of operation at which point the RF modulation takes place.

Circuit for echo and noise suppression of acoustic signals transmitted through a drill string

DOEpatents

Drumheller, D.S.; Scott, D.D.

1993-12-28

An electronic circuit for digitally processing analog electrical signals produced by at least one acoustic transducer is presented. In a preferred embodiment of the present invention, a novel digital time delay circuit is utilized which employs an array of First-in-First-out (FiFo) microchips. Also, a bandpass filter is used at the input to this circuit for isolating drill string noise and eliminating high frequency output. 20 figures.

Scaling up digital circuit computation with DNA strand displacement cascades.

PubMed

Qian, Lulu; Winfree, Erik

2011-06-03

To construct sophisticated biochemical circuits from scratch, one needs to understand how simple the building blocks can be and how robustly such circuits can scale up. Using a simple DNA reaction mechanism based on a reversible strand displacement process, we experimentally demonstrated several digital logic circuits, culminating in a four-bit square-root circuit that comprises 130 DNA strands. These multilayer circuits include thresholding and catalysis within every logical operation to perform digital signal restoration, which enables fast and reliable function in large circuits with roughly constant switching time and linear signal propagation delays. The design naturally incorporates other crucial elements for large-scale circuitry, such as general debugging tools, parallel circuit preparation, and an abstraction hierarchy supported by an automated circuit compiler.

High accuracy digital aging monitor based on PLL-VCO circuit

NASA Astrophysics Data System (ADS)

Yuejun, Zhang; Zhidi, Jiang; Pengjun, Wang; Xuelong, Zhang

2015-01-01

As the manufacturing process is scaled down to the nanoscale, the aging phenomenon significantly affects the reliability and lifetime of integrated circuits. Consequently, the precise measurement of digital CMOS aging is a key aspect of nanoscale aging tolerant circuit design. This paper proposes a high accuracy digital aging monitor using phase-locked loop and voltage-controlled oscillator (PLL-VCO) circuit. The proposed monitor eliminates the circuit self-aging effect for the characteristic of PLL, whose frequency has no relationship with circuit aging phenomenon. The PLL-VCO monitor is implemented in TSMC low power 65 nm CMOS technology, and its area occupies 303.28 × 298.94 μm2. After accelerating aging tests, the experimental results show that PLL-VCO monitor improves accuracy about high temperature by 2.4% and high voltage by 18.7%.

Mechanically-reattachable liquid-cooled cooling apparatus

DOEpatents

Arney, Susanne; Cheng, Jen-Hau; Kolodner, Paul R; Kota-Venkata, Krishna-Murty; Scofield, William; Salamon, Todd R; Simon, Maria E

2013-09-24

An apparatus comprising a rack having a row of shelves, each shelf supporting an electronics circuit board, each one of the circuit boards being manually removable from the shelve supporting the one of the circuit boards and having a local heat source thereon. The apparatus also comprises a cooler attached to the rack and being able to circulate a cooling fluid around a channel forming a closed loop. The apparatus further comprises a plurality of heat conduits, each heat conduit being located over a corresponding one of the circuit boards and forming a path to transport heat from the local heat source of the corresponding one of the circuit boards to the cooler. Each heat conduit is configured to be manually detachable from the cooler or the circuit board, without breaking a circulation pathway of the fluid through the cooler.

A low jitter PLL clock used for phase change memory

NASA Astrophysics Data System (ADS)

Xiao, Hong; Houpeng, Chen; Zhitang, Song; Daolin, Cai; Xi, Li

2013-02-01

A fully integrated low-jitter, precise frequency CMOS phase-locked loop (PLL) clock for the phase change memory (PCM) drive circuit is presented. The design consists of a dynamic dual-reset phase frequency detector (PFD) with high frequency acquisition, a novel low jitter charge pump, a CMOS ring oscillator based voltage-controlled oscillator (VCO), a 2nd order passive loop filter, and a digital frequency divider. The design is fabricated in 0.35 μm CMOS technology and consumes 20 mW from a supply voltage of 5 V. In terms of the PCM's program operation requirement, the output frequency range is from 1 to 140 MHz. For the 140 MHz output frequency, the circuit features a cycle-to-cycle jitter of 28 ps RMS and 250 ps peak-to-peak.

Digital-only PLL with adaptive search step

NASA Astrophysics Data System (ADS)

Lin, Ming-Lang; Huang, Shu-Chuan; Liu, Jie-Cherng

2014-06-01

In this paper, an all-digital phase-locked loop (PLL) with adaptively controlled up/down counter serves as the loop filter is presented, and it is implemented on a field-programmable gate array. The detailed circuit of the adaptive up/down counter implementing the adaptive search algorithm is also given, in which the search step for frequency acquisition is adaptively scaled down in half until it is reduced to zero. The phase jitter of the proposed PLL can be lowered, yet keeping with fast lock-in time. Thus, the dilemma between the low phase jitter and fast lock-in time of the traditional PLL can be resolved. Simulation results and circuit implementation show that the locked count, phase jitter and lock-in time of the proposed PLL are consistent with the theoretical predictions.

An efficient current-based logic cell model for crosstalk delay analysis

NASA Astrophysics Data System (ADS)

Nazarian, Shahin; Das, Debasish

2013-04-01

Logic cell modelling is an important component in the analysis and design of CMOS integrated circuits, mostly due to nonlinear behaviour of CMOS cells with respect to the voltage signal at their input and output pins. A current-based model for CMOS logic cells is presented, which can be used for effective crosstalk noise and delta delay analysis in CMOS VLSI circuits. Existing current source models are expensive and need a new set of Spice-based characterisation, which is not compatible with typical EDA tools. In this article we present Imodel, a simple nonlinear logic cell model that can be derived from the typical cell libraries such as NLDM, with accuracy much higher than NLDM-based cell delay models. In fact, our experiments show an average error of 3% compared to Spice. This level of accuracy comes with a maximum runtime penalty of 19% compared to NLDM-based cell delay models on medium-sized industrial designs.

Compensation of distributed delays in integrated communication and control systems

NASA Technical Reports Server (NTRS)

Ray, Asok; Luck, Rogelio

1991-01-01

The concept, analysis, implementation, and verification of a method for compensating delays that are distributed between the sensors, controller, and actuators within a control loop are discussed. With the objective of mitigating the detrimental effects of these network induced delays, a predictor-controller algorithm was formulated and analyzed. Robustness of the delay compensation algorithm was investigated relative to parametric uncertainties in plant modeling. The delay compensator was experimentally verified on an IEEE 802.4 network testbed for velocity control of a DC servomotor.

Hawaiian Electric Advanced Inverter Test Plan - Result Summary

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hoke, Anderson; Nelson, Austin; Prabakar, Kumaraguru

This presentation is intended to share the results of lab testing of five PV inverters with the Hawaiian Electric Companies and other stakeholders and interested parties. The tests included baseline testing of advanced inverter grid support functions, as well as distribution circuit-level tests to examine the impact of the PV inverters on simulated distribution feeders using power hardware-in-the-loop (PHIL) techniques. hardware-in-the-loop (PHIL) techniques.

PRESSURE SYSTEM CONTROL

DOEpatents

Esselman, W.H.; Kaplan, G.M.

1961-06-20

The control of pressure in pressurized liquid systems, especially a pressurized liquid reactor system, may be achieved by providing a bias circuit or loop across a closed loop having a flow restriction means in the form of an orifice, a storage tank, and a pump connected in series. The subject invention is advantageously utilized where control of a reactor can be achieved by response to the temperature and pressure of the primary cooling system.

STABILIZED OSCILLATOR

DOEpatents

Jessen, P.L.; Price, H.J.

1958-03-18

This patent relates to sine-wave generators and in particular describes a generator with a novel feedback circuit resulting in improved frequency stability. The generator comprises two triodes having a common cathode circuit connected to oscillate at a frequency and amplitude at which the loop galn of the circutt ls unity, and another pair of triodes having a common cathode circuit arranged as a conventional amplifier. A signal is conducted from the osciliator through a frequency selective network to the amplifier and fed back to the osciliator. The unique feature of the feedback circuit is the amplifier operates in the nonlinear portion of its tube characteristics thereby providing a relatively constant feedback voltage to the oscillator irrespective of the amplitude of its input signal.

Wide-beam sensors for controlling dual-delay systems

NASA Astrophysics Data System (ADS)

Edwards, J. B.; Twemlow, J. K.

1982-09-01

A class of dual delay feedback systems of open loop transfer function G(s) = k exp(-Xs)/l - exp(-Ws) is shown to be unstable if ratio X/W is noninteger. By means of z-transform techniques it is shown that, by using a feedback transducer that senses over a substantial distance either side of its central axis, closed-loop stability may be restored. Such transducers, termed widebeam sensors, include transmission, backscatter and natural radiation types as well as electromechanical conveyor belt weighers. Designing transducers for very narrow beams may not be desirable from the overall system viewpoint.

Analog circuit for the measurement of phase difference between two noisy sine-wave signals

NASA Technical Reports Server (NTRS)

Shakkottai, P.; Kwack, E. Y.; Back, L. H.

1989-01-01

A simple circuit was designed to measure the phase difference between two noisy sine waves. It locks over a wide range of frequencies and produces an output proportional to the phase difference of rapidly varying signals. A square wave locked in frequency and phase to the first signal is produced by a phase-locked loop and is amplified by an operational amplifier.

A class of optimum digital phase locked loops

NASA Technical Reports Server (NTRS)

Kumar, R.; Hurd, W. J.

1986-01-01

This paper presents a class of optimum digital filters for digital phase locked loops, for the important case in which the maximum update rate of the loop filter and numerically controlled oscillator (NCO) is limited. This case is typical when the loop filter is implemented in a microprocessor. In these situations, pure delay is encountered in the loop transfer function and thus the stability and gain margin of the loop are of crucial interest. The optimum filters designed for such situations are evaluated in terms of their gain margin for stability, dynamic error, and steady-state error performance. For situations involving considerably high phase dynamics an adaptive and programmable implementation is also proposed to obtain an overall optimum strategy.

Delayed in vitro development of Up states but normal network plasticity in Fragile X circuits.

PubMed

Motanis, Helen; Buonomano, Dean

2015-09-01

A broad range of neurophysiological phenotypes have been reported since the generation of the first mouse model of Fragile X syndrome (FXS). However, it remains unclear which phenotypes are causally related to the cognitive deficits associated with FXS. Indeed, because many of these phenotypes are known to be modulated by experience, a confounding factor in the interpretation of many studies is whether some phenotypes are an indirect consequence of abnormal development and experience. To help diminish this confound we first conducted an in vitro developmental study of spontaneous neural dynamics in cortical organotypic cultures. A significant developmental increase in network activity and Up states was observed in both wild-type and Fmr1(-/y) circuits, along with a specific developmental delay in the emergence of Up states in knockout circuits. To determine whether Up state regulation is generally impaired in FXS circuits, we examined Up state plasticity using chronic optogenetic stimulation. Wild-type and Fmr1(-/y) stimulated circuits exhibited a significant decrease in overall spontaneous activity including Up state frequency; however, no significant effect of genotype was observed. These results demonstrate that developmental delays characteristic of FXS are recapitulated during in vitro development, and that Up state abnormalities are probably a direct consequence of the disease, and not an indirect consequence of abnormal experience. However, the fact that Fmr1(-/y) circuits exhibited normal homeostatic modulation of Up states suggests that these plasticity mechanisms are largely intact, and that some of the previously reported plasticity deficits could reflect abnormal experience or the engagement of compensatory mechanisms. © 2015 Federation of European Neuroscience Societies and John Wiley & Sons Ltd.

Delayed Maturation of Fast-Spiking Interneurons Is Rectified by Activation of the TrkB Receptor in the Mouse Model of Fragile X Syndrome.

PubMed

Nomura, Toshihiro; Musial, Timothy F; Marshall, John J; Zhu, Yiwen; Remmers, Christine L; Xu, Jian; Nicholson, Daniel A; Contractor, Anis

2017-11-22

Fragile X syndrome (FXS) is a neurodevelopmental disorder that is a leading cause of inherited intellectual disability, and the most common known cause of autism spectrum disorder. FXS is broadly characterized by sensory hypersensitivity and several developmental alterations in synaptic and circuit function have been uncovered in the sensory cortex of the mouse model of FXS ( Fmr1 KO). GABA-mediated neurotransmission and fast-spiking (FS) GABAergic interneurons are central to cortical circuit development in the neonate. Here we demonstrate that there is a delay in the maturation of the intrinsic properties of FS interneurons in the sensory cortex, and a deficit in the formation of excitatory synaptic inputs on to these neurons in neonatal Fmr1 KO mice. Both these delays in neuronal and synaptic maturation were rectified by chronic administration of a TrkB receptor agonist. These results demonstrate that the maturation of the GABAergic circuit in the sensory cortex is altered during a critical developmental period due in part to a perturbation in BDNF-TrkB signaling, and could contribute to the alterations in cortical development underlying the sensory pathophysiology of FXS. SIGNIFICANCE STATEMENT Fragile X (FXS) individuals have a range of sensory related phenotypes, and there is growing evidence of alterations in neuronal circuits in the sensory cortex of the mouse model of FXS ( Fmr1 KO). GABAergic interneurons are central to the correct formation of circuits during cortical critical periods. Here we demonstrate a delay in the maturation of the properties and synaptic connectivity of interneurons in Fmr1 KO mice during a critical period of cortical development. The delays both in cellular and synaptic maturation were rectified by administration of a TrkB receptor agonist, suggesting reduced BDNF-TrkB signaling as a contributing factor. These results provide evidence that the function of fast-spiking interneurons is disrupted due to a deficiency in neurotrophin signaling during early development in FXS. Copyright © 2017 the authors 0270-6474/17/3711298-13$15.00/0.

An observer-based compensator for distributed delays in integrated control systems

NASA Technical Reports Server (NTRS)

Luck, Rogelio; Ray, Asok

1989-01-01

This paper presents an algorithm for compensation of delays that are distributed within a control loop. The observer-based algorithm is especially suitable for compensating network-induced delays that are likely to occur in integrated control systems of the future generation aircraft. The robustness of the algorithm relative to uncertainties in the plant model have been examined.

Electronic Combat Hardware-in-the-Loop Testing in an Open Air Environment

DTIC Science & Technology

1994-09-01

APQ- 126 (F-111) Gun Dish Squat Eye ANAWG-9 (F-14) Grill Pan Straight Flush I-Hawk Hawk Screech Sun Visor Head Light Tall King High Fix Team Work High...the required delay to the IF, the SPCs contain a Teledyne Microwave Bulk Acoustic Wave (BAW) delay line as well as a Coherent Variable Delay Unit

Behaviour of F82H mod. stainless steel in lead-bismuth under temperature gradient

NASA Astrophysics Data System (ADS)

Gómez Briceño, D.; Martín Muñoz, F. J.; Soler Crespo, L.; Esteban, F.; Torres, C.

2001-07-01

Austenitic steels can be used in a hybrid system in contact with liquid lead-bismuth eutectic if the region of operating temperatures is not beyond 400°C. For higher temperatures, martensitic steels are recommended. However, at long times, the interaction between the structural material and the eutectic leads to the dissolution of some elements of the steel (Ni, Cr and Fe, mainly) in the liquid metal. In a non-isothermal lead-bismuth loop, the material dissolution takes place at the hot leg of the circuit and, due to the mass transfer, deposition occurs at the cold leg. One of the possible ways to improve the performance of structural materials in lead-bismuth is the creation of an oxide layer. Tests have been performed in a small natural convection loop built of austenitic steel (316L) that has been operating for 3000 h. This loop contains a test area in which several samples of F82Hmod. martensitic steel have been tested at different times. A gas with an oxygen content of 10 ppm was bubbled in the hot area of the circuit during the operation time. The obtained results show that an oxide layer is formed on the samples introduced in the loop at the beginning of the operation and this layer increases with time. However, the samples introduced at different times during the loop operation, are not protected by oxide layers and present material dissolution in some cases.

Experimental Apparatus to Observe Dynamical Manifestations of Hamiltonian Monodromy

NASA Astrophysics Data System (ADS)

Nerem, M. Perry; Salmon, Danial; Delos, John; Aubin, Seth

An experiment to observe a topological change in a classical system with nontrivial monodromy is presented. Monodromy is the study of the topological behavior of a system as it evolves along a closed path. If the system does not return to the initial topological state at the end of the circuit, that system exhibits nontrivial monodromy. Such a topological change has been predicted in certain mechanical systems, but has not yet been observed experimentally. One such system is a family of paths in a cylindrically symmetric champagne-bottle potential, with a classically forbidden region centered at the origin. We constructed this system with a long spherically symmetric pendulum and a permanent magnet attached at the end. Magnetic fields from coils are used to create the potential barrier and the external forces to drive the pendulum about a monodromy circuit. A loop of initial conditions, that is initially on one side of the forbidden region, is driven smoothly about this circuit such that it continuously evolves into a loop that surrounds the forbidden region. We will display this phenomena through numerical simulations and hopefully experimental measurement.

Closed-loop neuromodulation of spinal sensorimotor circuits controls refined locomotion after complete spinal cord injury.

PubMed

Wenger, Nikolaus; Moraud, Eduardo Martin; Raspopovic, Stanisa; Bonizzato, Marco; DiGiovanna, Jack; Musienko, Pavel; Morari, Manfred; Micera, Silvestro; Courtine, Grégoire

2014-09-24

Neuromodulation of spinal sensorimotor circuits improves motor control in animal models and humans with spinal cord injury. With common neuromodulation devices, electrical stimulation parameters are tuned manually and remain constant during movement. We developed a mechanistic framework to optimize neuromodulation in real time to achieve high-fidelity control of leg kinematics during locomotion in rats. We first uncovered relationships between neuromodulation parameters and recruitment of distinct sensorimotor circuits, resulting in predictive adjustments of leg kinematics. Second, we established a technological platform with embedded control policies that integrated robust movement feedback and feed-forward control loops in real time. These developments allowed us to conceive a neuroprosthetic system that controlled a broad range of foot trajectories during continuous locomotion in paralyzed rats. Animals with complete spinal cord injury performed more than 1000 successive steps without failure, and were able to climb staircases of various heights and lengths with precision and fluidity. Beyond therapeutic potential, these findings provide a conceptual and technical framework to personalize neuromodulation treatments for other neurological disorders. Copyright © 2014, American Association for the Advancement of Science.

A SERIES OF SUPPRESSIVE SIGNALS WITHIN THE DROSOPHILA CIRCADIAN NEURAL CIRCUIT GENERATES SEQUENTIAL DAILY OUTPUTS

PubMed Central

Liang, Xitong; Holy, Timothy E; Taghert, Paul H

2017-01-01

Summary We studied the Drosophila circadian neural circuit using whole brain imaging in vivo. Five major groups of pacemaker neurons display synchronized molecular clocks, yet each exhibits a distinct phase of daily Ca2+ activation. Light and neuropeptide PDF from morning cells (s-LNv) together delay the phase of the evening (LNd) group by ~12 h; PDF alone delays the phase of the DN3 group, by ~17 h. Neuropeptide sNPF, released from s-LNv and LNd pacemakers, produces latenight Ca2+ activation in the DN1 group. The circuit also features negative feedback by PDF to truncate the s-LNv Ca2+ wave and terminate PDF release. Both PDF and sNPF suppress basal Ca2+ levels in target pacemakers with long durations by cell autonomous actions. Thus, light and neuropeptides act dynamically at distinct hubs of the circuit to produce multiple suppressive events that create the proper tempo and sequence of circadian pacemaker neuronal activities. PMID:28552314

A novel high-speed CMOS circuit based on a gang of capacitors

NASA Astrophysics Data System (ADS)

Sharroush, Sherif M.

2017-08-01

There is no doubt that complementary metal-oxide semiconductor (CMOS) circuits with wide fan-in suffers from the relatively sluggish operation. In this paper, a circuit that contains a gang of capacitors sharing their charge with each other is proposed as an alternative to long N-channel MOS and P-channel MOS stacks. The proposed scheme is investigated quantitatively and verified by simulation using the 45-nm CMOS technology with VDD = 1 V. The time delay, area and power consumption of the proposed scheme are investigated and compared with the conventional static CMOS logic circuit. It is verified that the proposed scheme achieves 52% saving in the average propagation delay for eight inputs and that it has a smaller area compared to the conventional CMOS logic when the number of inputs exceeds three and a smaller power consumption for a number of inputs exceeding two. The impacts of process variations, component mismatches and technology scaling on the proposed scheme are also investigated.

Bidirectional automatic release of reserve for low voltage network made with low capacity PLCs

NASA Astrophysics Data System (ADS)

Popa, I.; Popa, G. N.; Diniş, C. M.; Deaconu, S. I.

2018-01-01

The article presents the design of a bidirectional automatic release of reserve made on two types low capacity programmable logic controllers: PS-3 from Klöckner-Moeller and Zelio from Schneider. It analyses the electronic timing circuits that can be used for making the bidirectional automatic release of reserve: time-on delay circuit and time-off delay circuit (two types). In the paper are present the sequences code for timing performed on the PS-3 PLC, the logical functions for the bidirectional automatic release of reserve, the classical control electrical diagram (with contacts, relays, and time relays), the electronic control diagram (with logical gates and timing circuits), the code (in IL language) made for the PS-3 PLC, and the code (in FBD language) made for Zelio PLC. A comparative analysis will be carried out on the use of the two types of PLC and will be present the advantages of using PLCs.

A Current-Mode Common-Mode Feedback Circuit (CMFB) with Rail-to-Rail Operation

NASA Astrophysics Data System (ADS)

Suadet, Apirak; Kasemsuwan, Varakorn

2011-03-01

This paper presents a current-mode common-mode feedback (CMFB) circuit with rail-to-rail operation. The CMFB is a stand-alone circuit, which can be connected to any low voltage transconductor without changing or upsetting the existing circuit. The proposed CMFB employs current mirrors, operating as common-mode detector and current amplifier to enhance the loop gain of the CMFB. The circuit employs positive feedback to enhance the output impedance and gain. The circuit has been designed using a 0.18 μm CMOS technology under 1V supply and analyzed using HSPICE with BSIM3V3 device models. A pseudo-differential amplifier using two common sources and the proposed CMFB shows rail to rail output swing (± 0.7 V) with low common-mode gain (-36 dB) and power dissipation of 390 μW.

Analysis of adaptive algorithms for an integrated communication network

NASA Technical Reports Server (NTRS)

Reed, Daniel A.; Barr, Matthew; Chong-Kwon, Kim

1985-01-01

Techniques were examined that trade communication bandwidth for decreased transmission delays. When the network is lightly used, these schemes attempt to use additional network resources to decrease communication delays. As the network utilization rises, the schemes degrade gracefully, still providing service but with minimal use of the network. Because the schemes use a combination of circuit and packet switching, they should respond to variations in the types and amounts of network traffic. Also, a combination of circuit and packet switching to support the widely varying traffic demands imposed on an integrated network was investigated. The packet switched component is best suited to bursty traffic where some delays in delivery are acceptable. The circuit switched component is reserved for traffic that must meet real time constraints. Selected packet routing algorithms that might be used in an integrated network were simulated. An integrated traffic places widely varying workload demands on a network. Adaptive algorithms were identified, ones that respond to both the transient and evolutionary changes that arise in integrated networks. A new algorithm was developed, hybrid weighted routing, that adapts to workload changes.

LMI designmethod for networked-based PID control

NASA Astrophysics Data System (ADS)

Souza, Fernando de Oliveira; Mozelli, Leonardo Amaral; de Oliveira, Maurício Carvalho; Palhares, Reinaldo Martinez

2016-10-01

In this paper, we propose a methodology for the design of networked PID controllers for second-order delayed processes using linear matrix inequalities. The proposed procedure takes into account time-varying delay on the plant, time-varying delays induced by the network and packed dropouts. The design is carried on entirely using a continuous-time model of the closed-loop system where time-varying delays are used to represent sampling and holding occurring in a discrete-time digital PID controller.

Contact stiffness and damping identification for hardware-in-the-loop contact simulator with measurement delay compensation

NASA Astrophysics Data System (ADS)

Qi, Chenkun; Zhao, Xianchao; Gao, Feng; Ren, Anye; Sun, Qiao

2016-06-01

The hardware-in-the-loop (HIL) contact simulator is to simulate the contact process of two flying objects in space. The contact stiffness and damping are important parameters used for the process monitoring, compliant contact control and force compensation control. In this study, a contact stiffness and damping identification approach is proposed for the HIL contact simulation with the force measurement delay. The actual relative position of two flying objects can be accurately measured. However, the force measurement delay needs to be compensated because it will lead to incorrect stiffness and damping identification. Here, the phase lead compensation is used to reconstruct the actual contact force from the delayed force measurement. From the force and position data, the contact stiffness and damping are identified in real time using the recursive least squares (RLS) method. The simulations and experiments are used to verify that the proposed stiffness and damping identification approach is effective.

Frequency stabilization of an Er-doped fiber laser with a collinear 2f-to-3f self-referencing interferometer

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hitachi, K., E-mail: hitachi.kenichi@lab.ntt.co.jp; Ishizawa, A.; Mashiko, H.

2015-06-08

We report the stabilization of the carrier-envelope offset (CEO) frequency of an Er-doped fiber laser with a collinear 2f-to-3f self-referencing interferometer. The interferometer is implemented by a dual-pitch periodically poled lithium niobate ridge waveguide with two different quasi-phase matching pitch sizes. We obtain a 52-dB signal-to-noise ratio in the 100-kHz resolution bandwidth of a heterodyne beat signal, which is sufficient for frequency stabilization. We also demonstrate that the collinear geometry is robust against environmental perturbation by comparing in-loop and out-of-loop Allan deviations when the in-loop CEO frequency is stabilized with a phase-locked loop circuit.

Stable photosensor amplifiers

NASA Technical Reports Server (NTRS)

Fujimoto, H.

1972-01-01

Minimization of common mode effects in differential amplifier arrangement which processes signals from two high impedance photosensors is achieved by connecting one photosensor in feedback loop of amplifier and using field effect transistors in the input circuit.

Voltage regulator/amplifier is self-regulated

NASA Technical Reports Server (NTRS)

Day, W. E.; Phillips, D. E.

1967-01-01

Signal modulated, self-regulating voltage regulator/amplifier controls the output b-plus voltage in modulated regulator systems. It uses self-oscillation with feedback to a control circuit with a discontinuous amplitude action feedback loop.

Concentric transmon qubit featuring fast tunability and an anisotropic magnetic dipole moment

NASA Astrophysics Data System (ADS)

Braumüller, Jochen; Sandberg, Martin; Vissers, Michael R.; Schneider, Andre; Schlör, Steffen; Grünhaupt, Lukas; Rotzinger, Hannes; Marthaler, Michael; Lukashenko, Alexander; Dieter, Amadeus; Ustinov, Alexey V.; Weides, Martin; Pappas, David P.

2016-01-01

We present a planar qubit design based on a superconducting circuit that we call concentric transmon. While employing a straightforward fabrication process using Al evaporation and lift-off lithography, we observe qubit lifetimes and coherence times in the order of 10 μ s . We systematically characterize loss channels such as incoherent dielectric loss, Purcell decay and radiative losses. The implementation of a gradiometric SQUID loop allows for a fast tuning of the qubit transition frequency and therefore for full tomographic control of the quantum circuit. Due to the large loop size, the presented qubit architecture features a strongly increased magnetic dipole moment as compared to conventional transmon designs. This renders the concentric transmon a promising candidate to establish a site-selective passive direct Z ̂ coupling between neighboring qubits, being a pending quest in the field of quantum simulation.

Chaotic oscillations and noise transformations in a simple dissipative system with delayed feedback

NASA Astrophysics Data System (ADS)

Zverev, V. V.; Rubinstein, B. Ya.

1991-04-01

We analyze the statistical behavior of signals in nonlinear circuits with delayed feedback in the presence of external Markovian noise. For the special class of circuits with intense phase mixing we develop an approach for the computation of the probability distributions and multitime correlation functions based on the random phase approximation. Both Gaussian and Kubo-Andersen models of external noise statistics are analyzed and the existence of the stationary (asymptotic) random process in the long-time limit is shown. We demonstrate that a nonlinear system with chaotic behavior becomes a noise amplifier with specific statistical transformation properties.

Minimalist-design, high-functionality, micro-ring resonator-based optical filter with narrow linewidth and low group delay using Looped Back Over- and Under-coupled Resonator (LOBOUR)

NASA Astrophysics Data System (ADS)

Ye, Bo; Dingel, Benjamin B.; Cui, Weili

2013-01-01

We present a minimalist design but high functionality micro-ring resonator based optical filter with narrow linewidth and low group delay using a novel design we called LOBOUR for LOoped-Back Over- and Under- Coupled Resonator (LOBOUR). The characteristics of both narrow linewidth and low group delay (low chromatic dispersion) generally do not come together especially when using a single ring resonator. The Cascaded Over- and Under-Coupled Resonator (COUR) design was able to achieve this goal but introduced many practical fabrication issues. Here, we present an alternative design to COUR which uses only one ring resonator and without fabrication and manufacturing issues. It can achieve 50 dB extinction ratio and tens of ps performance. We also present important parameter selection mapping for LOBOUR.

On-line estimation and compensation of measurement delay in GPS/SINS integration

NASA Astrophysics Data System (ADS)

Yang, Tao; Wang, Wei

2008-10-01

The chief aim of this paper is to propose a simple on-line estimation and compensation method of GPS/SINS measurement delay. The causes of time delay for GPS/SINS integration are analyzed in this paper. New Kalman filter state equations augmented by measurement delay and modified measurement equations are derived. Based on an open-loop Kalman filter, several simulations are run, results of which show that by the proposed method, the estimation and compensation error of measurement delay is below 0.1s.

A twofold quantum delayed-choice experiment in a superconducting circuit

PubMed Central

Liu, Ke; Xu, Yuan; Wang, Weiting; Zheng, Shi-Biao; Roy, Tanay; Kundu, Suman; Chand, Madhavi; Ranadive, Arpit; Vijay, Rajamani; Song, Yipu; Duan, Luming; Sun, Luyan

2017-01-01

Wave-particle complementarity lies at the heart of quantum mechanics. To illustrate this mysterious feature, Wheeler proposed the delayed-choice experiment, where a quantum system manifests the wave- or particle-like attribute, depending on the experimental arrangement, which is made after the system has entered the interferometer. In recent quantum delayed-choice experiments, these two complementary behaviors were simultaneously observed with a quantum interferometer in a superposition of being closed and open. We suggest and implement a conceptually different quantum delayed-choice experiment by introducing a which-path detector (WPD) that can simultaneously record and neglect the system’s path information, but where the interferometer itself is classical. Our experiment is realized with a superconducting circuit, where a cavity acts as the WPD for an interfering qubit. Using this setup, we implement the first twofold delayed-choice experiment, which demonstrates that the system’s behavior depends not only on the measuring device’s configuration that can be chosen even after the system has been detected but also on whether we a posteriori erase or mark the which-path information, the latter of which cannot be revealed by previous quantum delayed-choice experiments. Our results represent the first demonstration of both counterintuitive features with the same experimental setup, significantly extending the concept of quantum delayed-choice experiment. PMID:28508079

A twofold quantum delayed-choice experiment in a superconducting circuit.

PubMed

Liu, Ke; Xu, Yuan; Wang, Weiting; Zheng, Shi-Biao; Roy, Tanay; Kundu, Suman; Chand, Madhavi; Ranadive, Arpit; Vijay, Rajamani; Song, Yipu; Duan, Luming; Sun, Luyan

2017-05-01

Wave-particle complementarity lies at the heart of quantum mechanics. To illustrate this mysterious feature, Wheeler proposed the delayed-choice experiment, where a quantum system manifests the wave- or particle-like attribute, depending on the experimental arrangement, which is made after the system has entered the interferometer. In recent quantum delayed-choice experiments, these two complementary behaviors were simultaneously observed with a quantum interferometer in a superposition of being closed and open. We suggest and implement a conceptually different quantum delayed-choice experiment by introducing a which-path detector (WPD) that can simultaneously record and neglect the system's path information, but where the interferometer itself is classical. Our experiment is realized with a superconducting circuit, where a cavity acts as the WPD for an interfering qubit. Using this setup, we implement the first twofold delayed-choice experiment, which demonstrates that the system's behavior depends not only on the measuring device's configuration that can be chosen even after the system has been detected but also on whether we a posteriori erase or mark the which-path information, the latter of which cannot be revealed by previous quantum delayed-choice experiments. Our results represent the first demonstration of both counterintuitive features with the same experimental setup, significantly extending the concept of quantum delayed-choice experiment.

Multi-piecewise quadratic nonlinearity memristor and its 2N-scroll and 2N + 1-scroll chaotic attractors system.

PubMed

Wang, Chunhua; Liu, Xiaoming; Xia, Hu

2017-03-01

In this paper, two kinds of novel ideal active flux-controlled smooth multi-piecewise quadratic nonlinearity memristors with multi-piecewise continuous memductance function are presented. The pinched hysteresis loop characteristics of the two memristor models are verified by building a memristor emulator circuit. Using the two memristor models establish a new memristive multi-scroll Chua's circuit, which can generate 2N-scroll and 2N+1-scroll chaotic attractors without any other ordinary nonlinear function. Furthermore, coexisting multi-scroll chaotic attractors are found in the proposed memristive multi-scroll Chua's circuit. Phase portraits, Lyapunov exponents, bifurcation diagrams, and equilibrium point analysis have been used to research the basic dynamics of the memristive multi-scroll Chua's circuit. The consistency of circuit implementation and numerical simulation verifies the effectiveness of the system design.

A novel architecture of recovered data comparison for high speed clock and data recovery

NASA Astrophysics Data System (ADS)

Gao, Susan; Li, Fei; Wang, Zhigong; Cui, Hongliang

2005-05-01

A clock and data recovery (CDR) circuit is one of the crucial blocks in high-speed serial link communication systems. The data received in these systems are asynchronous and noisy, requiring that a clock be extracted to allow synchronous operations. Furthermore, the data must be "retimed" so that the jitter accumulated during transmission is removed. This paper presents a novel architecture of CDR, which is very tolerant to long sequences of serial ones or zeros and also robust to occasional long absence of transitions. The design is based on the fact that a basic clock recovery having a clock recovery circuit (CRC) and a data decision circuit separately would generate a high jitter clock when the received non-return-to-zero (NRZ) data with long sequences of ones or zeros. To eliminate this drawback, the proposed architecture incorporates a data circuit decision circuit within the phase-locked loop (PLL) CRC. Other than this, a new phase detector (PD) is also proposed, which was easy to accomplish and robust at high speed. This PD is functional with a random input and automatically turns to disable during both the locked state and long absence of transitions. The voltage-controlled oscillator (VCO) is also designed delicately to suppress the jitter. Due to the high stability, the jitter is highly reduced when the loop is locked. The simulation results of such CDR working at 1.25Gb/s particularly for 1000BASE-X Gigabit Ethernet by using TSMC 0.25μm technology are presented to prove the feasibility of this architecture. One more CDR based on edge detection architecture is also built in the circuit for performance comparisons.

Influence of Time-Pickoff Circuit Parameters on LiDAR Range Precision

PubMed Central

Wang, Hongming; Yang, Bingwei; Huyan, Jiayue; Xu, Lijun

2017-01-01

A pulsed time-of-flight (TOF) measurement-based Light Detection and Ranging (LiDAR) system is more effective for medium-long range distances. As a key ranging unit, a time-pickoff circuit based on automatic gain control (AGC) and constant fraction discriminator (CFD) is designed to reduce the walk error and the timing jitter for obtaining the accurate time interval. Compared with Cramer–Rao lower bound (CRLB) and the estimation of the timing jitter, four parameters-based Monte Carlo simulations are established to show how the range precision is influenced by the parameters, including pulse amplitude, pulse width, attenuation fraction and delay time of the CFD. Experiments were carried out to verify the relationship between the range precision and three of the parameters, exclusing pulse width. It can be concluded that two parameters of the ranging circuit (attenuation fraction and delay time) were selected according to the ranging performance of the minimum pulse amplitude. The attenuation fraction should be selected in the range from 0.2 to 0.6 to achieve high range precision. The selection criterion of the time-pickoff circuit parameters is helpful for the ranging circuit design of TOF LiDAR system. PMID:29039772

Dynamic response of a fiber-optic ring resonator: Analysis with influences of light-source parameters

NASA Astrophysics Data System (ADS)

Seraji, Faramarz E.

2009-03-01

In practice, dynamic behavior of fiber-optic ring resonator (FORR) appears as a detrimental factor to influence the transmission response of the FORR. This paper presents dynamic response analysis of the FORR by considering phase modulation of the FORR loop and sinewave modulation of input signal applied to the FORR from a laser diode. The analysis investigates the influences of modulation frequency and amplitude modulation index of laser diode, loop delay time of the FORR, phase angle between FM and AM response of laser diode, and laser diode line-width on dynamic response of the FORR. The analysis shows that the transient response of the FORR strongly depends on the product of modulation frequency and loop delay time, coupling and transmission coefficients of the FORR. The analyses presented here may have applications in optical systems employing an FORR with a laser diode source.

Efficient laser noise reduction method via actively stabilized optical delay line.

PubMed

Li, Dawei; Qian, Cheng; Li, Ye; Zhao, Jianye

2017-04-17

We report a fiber laser noise reduction method by locking it to an actively stabilized optical delay line, specifically a fiber-based Mach-Zehnder interferometer with a 10 km optical fiber spool. The fiber spool is used to achieve large arm imbalance. The heterodyne signal of the two arms converts the laser noise from the optical domain to several megahertz, and it is used in laser noise reduction by a phase-locked loop. An additional phase-locked loop is induced in the system to compensate the phase noise due to environmentally induced length fluctuations of the optical fiber spool. A major advantage of this structure is the efficient reduction of out-of-loop frequency noise, particularly at low Fourier frequency. The frequency noise reaches -30 dBc/Hz at 1 Hz, which is reduced by more than 90 dB compared with that of the laser in its free-running state.

Fast 4-2 Compressor of Booth Multiplier Circuits for High-Speed RISC Processor

NASA Astrophysics Data System (ADS)

Yuan, S. C.

2008-11-01

We use different XOR circuits to optimize the XOR structure 4-2 compressor, and design the transmission gates(TG) 4-2 compressor use single to dual rail circuit configurations. The maximum propagation delay, the power consumption and the layout area of the designed 4-2 compressors are simulated with 0.35μm and 0.25μm CMOS process parameters and compared with results of the synthesized 4-2 circuits, and show that the designed 4-2 compressors are faster and area smaller than the synthesized one.

Dynamic PID loop control

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pei, L.; Klebaner, A.; Theilacker, J.

2011-06-01

The Horizontal Test Stand (HTS) SRF Cavity and Cryomodule 1 (CM1) of eight 9-cell, 1.3GHz SRF cavities are operating at Fermilab. For the cryogenic control system, how to hold liquid level constant in the cryostat by regulation of its Joule-Thompson JT-valve is very important after cryostat cool down to 2.0 K. The 72-cell cryostat liquid level response generally takes a long time delay after regulating its JT-valve; therefore, typical PID control loop should result in some cryostat parameter oscillations. This paper presents a type of PID parameter self-optimal and Time-Delay control method used to reduce cryogenic system parameters oscillation.

Magnonic Crystal as a Delay Line for Low-Noise Auto-Oscillator

DTIC Science & Technology

2015-05-12

Magnonic crystal as a delay line for low-noise auto-oscillator Elena Bankowski and Thomas Meitzler U.S. Army TARDEC, Warren, Michigan 48397, USA...authors propose to use the magnonic crystal patterned on the YIG magnetic film as an efficient delay line in the feedback loop of tunable auto-oscillator...increasing the thickness of such delay line as compare to the YIG film with no pattern. In turn, use of this magnonic crystal opens a way to improve

Space shuttle main engine controller assembly, phase C-D. [with lagging system design and analysis

NASA Technical Reports Server (NTRS)

1973-01-01

System design and system analysis and simulation are slightly behind schedule, while design verification testing has improved. Input/output circuit design has improved, but digital computer unit (DCU) and mechanical design continue to lag. Part procurement was impacted by delays in printed circuit board, assembly drawing releases. These are the result of problems in generating suitable printed circuit artwork for the very complex and high density multilayer boards.

UWB transmitter

DOEpatents

Dallum, Gregory E.; Pratt, Garth C.; Haugen, Peter C.; Romero, Carlos E.

2013-01-15

An ultra-wideband (UWB) dual impulse transmitter is made up of a trigger edge selection circuit actuated by a single trigger input pulse; a first step recovery diode (SRD) based pulser connected to the trigger edge selection circuit to generate a first impulse output; and a second step recovery diode (SRD) based pulser connected to the trigger edge selection circuit in parallel to the first pulser to generate a second impulse output having a selected delay from the first impulse output.

Modeling of the Near Field Coupling Between an External Loop and an Implantable Spiral Chip Antennas in Biosensor Systems

NASA Technical Reports Server (NTRS)

Simons, Rainee N.; Miranda, Felix A.

2006-01-01

In this paper, the near field coupling between an external hand-held loop antenna and an implantable miniature (1x1 mm) printed square spiral chip antenna used in bio-MEMS sensors for contact-less powering and RF telemetry is investigated. The loop and the spiral are inductively coupled and effectively form a transformer. The numerical results include the quasi-stationary magnetic field pattern of the implanted antenna, near zone wave impedance as a function of the radial distance and the values of the lumped elements in the equivalent circuit model for the transformer.

DC superconducting quantum interference device usable in nuclear quadrupole resonance and zero field nuclear magnetic spectrometers

DOEpatents

Fan, N.Q.; Clarke, J.

1993-10-19

A spectrometer for measuring the nuclear quadrupole resonance spectra or the zero-field nuclear magnetic resonance spectra generated by a sample is disclosed. The spectrometer uses an amplifier having a dc SQUID operating in a flux-locked loop for generating an amplified output as a function of the intensity of the signal generated by the sample. The flux-locked loop circuit includes an integrator. The amplifier also includes means for preventing the integrator from being driven into saturation. As a result, the time for the flux-locked loop to recover from the excitation pulses generated by the spectrometer is reduced. 7 figures.

DC superconducting quantum interference device usable in nuclear quadrupole resonance and zero field nuclear magnetic spectrometers

DOEpatents

Fan, Non Q.; Clarke, John

1993-01-01

A spectrometer for measuring the nuclear quadrupole resonance spectra or the zero-field nuclear magnetic resonance spectra generated by a sample is disclosed. The spectrometer uses an amplifier having a dc SQUID operating in a flux-locked loop for generating an amplified output as a function of the intensity of the signal generated by the sample. The flux-locked loop circuit includes an integrator. The amplifier also includes means for preventing the integrator from being driven into saturation. As a result, the time for the flux-locked loop to recover from the excitation pulses generated by the spectrometer is reduced.

A single chip 2 Gbit/s clock recovery subsystem for digital communications

NASA Astrophysics Data System (ADS)

Hickling, Ronald M.

A self-contained clock recovery/data resynchronizer phase locked loop (PLL) for use in microwave and fiber optic digital communications has been fabricated using GaAs integrated circuit technology. The IC contains the analog and digital components for the PLL: an edge-triggered phase detector based on a 1.2 GHz phase/frequency comparator, an op amp for creating the loop filter, and a VCO based on a differential source-coupled pair amplifier.

Autonomous Power: From War to Peace in the I-Robot Millennium

DTIC Science & Technology

2015-02-25

Elon Musk , 2014) “I chose to believe that I was a person, that I had the potential to become more than a collection of circuits and sub...performed without human interaction. At this level, a human could still enter the loop in an emergency or change the goals, although in practice there...enable orders of magnitude increases in the speed of the decision loop by autonomously processing massive volumes of data on the operational

Extended Range Passive Wireless Tag System and Method

NASA Technical Reports Server (NTRS)

Fink, Patrick W. (Inventor); Lin, Gregory Y. (Inventor); Kennedy, Timothy F. (Inventor)

2013-01-01

A passive wireless tag assembly comprises a plurality of antennas and transmission lines interconnected with circuitry and constructed and arranged in a Van Atta array or configuration to reflect an interrogator signal in the direction from where it came. The circuitry may comprise at least one surface acoustic wave (SAW)-based circuit that functions as a signal reflector and is operatively connected with an information circuit. In another embodiment, at least one delay circuit and/or at least one passive modulation circuit(s) are utilized. In yet another embodiment, antennas connected to SAW-based devices are mounted to at least one of the orthogonal surfaces of a corner reflector.

The performance of a sampled data delay lock loop implemented with a Kalman loop filter

NASA Astrophysics Data System (ADS)

Eilts, H. S.

1980-01-01

The purpose of this study is to evaluate the steady-state and transient (lock-up) performance of a tracking loop implemented with a Kalman filter. Steady-state performance criteria are errors due to measurement noise (jitter) and Doppler errors due to motion of the tracking loop. Trade-offs exist between the two criteria such that increasing performance with respect to either one will cause performance decrease with respect to the other. It is shown that by carefully selecting filter parameters reasonable performance can be obtained for both criteria simultaneously. It is also shown that lock-up performance for the loop is acceptable when these parameters are used.

Atomistic Simulation of Interstitial Dislocation Loop Evolution under Applied Stresses in BCC Iron

DOE Office of Scientific and Technical Information (OSTI.GOV)

Long, Xue Hao; Wang, Dong; Setyawan, Wahyu

Evolution of an interstitial 1/2⟨111⟩ dislocation loop under tensile, shear, and torsion stresses is studied with molecular statics method. Under a tensile stress, the dependence of ultimate tensile strength on size of loop is calculated. The formation of small shear loops around the initial prismatic loop is confirmed as an intermediate state to form the final dislocation network. Under a shear stress, the rotation of a loop is observed not only by a change of the habit plane but also through a transformation between a shear and a prismatic loop. Under torsion, a perfect BCC crystal may undergo a BCCmore » to FCC or BCC to HCP transformation. The present work indicates that a 1/2⟨111⟩ loop can delay these transformations, resulting in the formation of micro-crack on the surface.« less

Improved On-Chip Measurement of Delay in an FPGA or ASIC

NASA Technical Reports Server (NTRS)

Chen, Yuan; Burke, Gary; Sheldon, Douglas

2007-01-01

An improved design has been devised for on-chip-circuitry for measuring the delay through a chain of combinational logic elements in a field-programmable gate array (FPGA) or application-specific integrated circuit (ASIC). In the improved design, the delay chain does not include input and output buffers and is not configured as an oscillator. Instead, the delay chain is made part of the signal chain of an on-chip pulse generator. The duration of the pulse is measured on-chip and taken to equal the delay.

Reconstructions of parameters of radiophysical chaotic generator with delayed feedback from short time series

NASA Astrophysics Data System (ADS)

Ishbulatov, Yu. M.; Karavaev, A. S.; Kiselev, A. R.; Semyachkina-Glushkovskaya, O. V.; Postnov, D. E.; Bezruchko, B. P.

2018-04-01

A method for the reconstruction of time-delayed feedback system is investigated, which is based on the detection of synchronous response of a slave time-delay system with respect to the driving from the master system under study. The structure of the driven system is similar to the structure of the studied time-delay system, but the feedback circuit is broken in the driven system. The method efficiency is tested using short and noisy data gained from an electronic chaotic oscillator with time-delayed feedback.

Stability of the Baseline Holder in Readout Circuits For Radiation Detectors

PubMed Central

Chen, Y.; Cui, Y.; O’Connor, P.; Seo, Y.; Camarda, G. S.; Hossain, A.; Roy, U.; Yang, G.; James, R. B.

2016-01-01

Baseline holder (BLH) circuits are used widely to stabilize the analog output of application-specific integrated circuits (ASICs) for high-count-rate applications. The careful design of BLH circuits is vital to the overall stability of the analog-signal-processing chain in ASICs. Recently, we observed self-triggered fluctuations in an ASIC in which the shaping circuits have a BLH circuit in the feedback loop. In fact, further investigations showed that methods of enhancing small-signal stabilities cause an even worse situation. To resolve this problem, we used large-signal analyses to study the circuit’s stability. We found that a relatively small gain for the error amplifier and a small current in the non-linear stage of the BLH are required to enhance stability in large-signal analysis, which will compromise the properties of the BLH. These findings were verified by SPICE simulations. In this paper, we present our detailed analysis of the BLH circuits, and propose an improved version of them that have only minimal self-triggered fluctuations. We summarize the design considerations both for the stability and the properties of the BLH circuits. PMID:27182081

Architecture-Dependent Robustness and Bistability in a Class of Genetic Circuits

PubMed Central

Zhang, Jiajun; Yuan, Zhanjiang; Li, Han-Xiong; Zhou, Tianshou

2010-01-01

Understanding the relationship between genotype and phenotype is a challenge in systems biology. An interesting yet related issue is why a particular circuit topology is present in a cell when the same function can supposedly be obtained from an alternative architecture. Here we analyzed two topologically equivalent genetic circuits of coupled positive and negative feedback loops, named NAT and ALT circuits, respectively. The computational search for the oscillation volume of the entire biologically reasonable parameter region through large-scale random samplings shows that the NAT circuit exhibits a distinctly larger fraction of the oscillatory region than the ALT circuit. Such a global robustness difference between two circuits is supplemented by analyzing local robustness, including robustness to parameter perturbations and to molecular noise. In addition, detailed dynamical analysis shows that the molecular noise of both circuits can induce transient switching of the different mechanism between a stable steady state and a stable limit cycle. Our investigation on robustness and dynamics through examples provides insights into the relationship between network architecture and its function. PMID:20712986

Architecture and settings optimization procedure of a TES frequency domain multiplexed readout firmware

NASA Astrophysics Data System (ADS)

Clenet, A.; Ravera, L.; Bertrand, B.; den Hartog, R.; Jackson, B.; van Leeuwen, B.-J.; van Loon, D.; Parot, Y.; Pointecouteau, E.; Sournac, A.

2014-11-01

IRAP is developing the readout electronics of the SPICA-SAFARI's TES bolometer arrays. Based on the frequency domain multiplexing technique the readout electronics provides the AC-signals to voltage-bias the detectors; it demodulates the data; and it computes a feedback to linearize the detection chain. The feedback is computed with a specific technique, so called baseband feedback (BBFB) which ensures that the loop is stable even with long propagation and processing delays (i.e. several μ s) and with fast signals (i.e. frequency carriers of the order of 5 MHz). To optimize the power consumption we took advantage of the reduced science signal bandwidth to decouple the signal sampling frequency and the data processing rate. This technique allowed a reduction of the power consumption of the circuit by a factor of 10. Beyond the firmware architecture the optimization of the instrument concerns the characterization routines and the definition of the optimal parameters. Indeed, to operate an array TES one has to properly define about 21000 parameters. We defined a set of procedures to automatically characterize these parameters and find out the optimal settings.

Designing a Ring-VCO for RFID Transponders in 0.18 μm CMOS Process

PubMed Central

Jalil, Jubayer; Reaz, Mamun Bin Ibne; Bhuiyan, Mohammad Arif Sobhan; Rahman, Labonnah Farzana; Chang, Tae Gyu

2014-01-01

In radio frequency identification (RFID) systems, performance degradation of phase locked loops (PLLs) mainly occurs due to high phase noise of voltage-controlled oscillators (VCOs). This paper proposes a low power, low phase noise ring-VCO developed for 2.42 GHz operated active RFID transponders compatible with IEEE 802.11 b/g, Bluetooth, and Zigbee protocols. For ease of integration and implementation of the module in tiny die area, a novel pseudodifferential delay cell based 3-stage ring oscillator has been introduced to fabricate the ring-VCO. In CMOS technology, 0.18 μm process is adopted for designing the circuit with 1.5 V power supply. The postlayout simulated results show that the proposed oscillator works in the tuning range of 0.5–2.54 GHz and dissipates 2.47 mW of power. It exhibits a phase noise of −126.62 dBc/Hz at 25 MHz offset from 2.42 GHz carrier frequency. PMID:24587731

Intrinsic modulation of pulse-coupled integrate-and-fire neurons

NASA Astrophysics Data System (ADS)

Coombes, S.; Lord, G. J.

1997-11-01

Intrinsic neuromodulation is observed in sensory and neuromuscular circuits and in biological central pattern generators. We model a simple neuronal circuit with a system of two pulse-coupled integrate-and-fire neurons and explore the parameter regimes for periodic firing behavior. The inclusion of biologically realistic features shows that the speed and onset of neuronal response plays a crucial role in determining the firing phase for periodic rhythms. We explore the neurophysiological function of distributed delays arising from both the synaptic transmission process and dendritic structure as well as discrete delays associated with axonal communication delays. Bifurcation and stability diagrams are constructed with a mixture of simple analysis, numerical continuation and the Kuramoto phase-reduction technique. Moreover, we show that, for asynchronous behavior, the strength of electrical synapses can control the firing rate of the system.

Effects of adding Braun jejunojejunostomy to standard Whipple procedure on reduction of afferent loop syndrome - a randomized clinical trial.

PubMed

Kakaei, Farzad; Beheshtirouy, Samad; Nejatollahi, Seyed Moahammad Reza; Rashidi, Iqbal; Asvadi, Touraj; Habibzadeh, Afshin; Oliaei-Motlagh, Mohammad

2015-12-01

Whipple surgery (pancreaticodeudenectomy) has a high complication rate. We aimed to evaluate whether adding Braun jejunojejunostomy (side-to-side anastomosis of afferent and efferent loops distal to the gastrojejunostomy site) to a standard Whipple procedure would reduce postoperative complications. We conducted a randomized clinical trial comparing patients who underwent standard Whipple surgery (standard group) and patients who underwent standard Whipple surgery with Braun jejunojejunostomy (Braun group). Patients were followed for 1 month after the procedure and postoperative complications were recorded. Our study included 30 patients: 15 in the Braun and 15 in the standard group. In the Braun group, 4 (26.7%) patients experienced 6 complications, whereas in the standard group, 7 (46.7%) patients experienced 11 complications (p = 0.14). Complications in the Braun group were gastrointestinal bleeding and wound infection (n = 1 each) and delayed gastric emptying and pulmonary infection (n = 2 each). Complications in the standard group were death, pancreatic anastomosis leak and biliary anastomosis leak (n = 1 each); gastrointestinal bleeding (n = 2); and afferent loop syndrome and delayed gastric emptying (n = 3 each). There was no significant difference between groups in the subtypes of complications. Our results showed that adding Braun jejunojejunostomy to standard Whipple procedure was associated with lower rates of afferent loop syndrome and delayed gastric emptying. However, more studies are needed to define the role of Braun jejunojejunostomy in this regard. IRCT2014020316473N1 (www.irct.ir).

Integrated P-channel MOS gyrator

NASA Technical Reports Server (NTRS)

Hochmair, E. S. (Inventor)

1974-01-01

A gyrator circuit is described which is of the conventional configuration of two amplifiers in a circular loop, one producing zero phase shift and the other producing 180 phase reversal, in a circuit having medium Q composed of all field effect transistors of the same conductivity type. The current source to each gyrator amplifier comprises an amplifier which responds to changes in current, with the amplified signals feed back so as to limit current. The feedback amplifier has a large capacitor connected to bypass high frequency components, thereby stabilizing the output. The design makes possible fabrication of circuits with transistors of only one conductivity type, providing economies in manufacture and use.

Portable battery-free charger for radiation dosimeters

DOEpatents

Manning, Frank W.

1984-01-01

This invention is a novel portable charger for dosimeters of the electrometer type. The charger does not require batteries or piezoelectric crystals and is of rugged construction. In a preferred embodiment, the charge includes a housing which carries means for mounting a dosimeter to be charged. The housing also includes contact means for impressing a charging voltage across the mounted dosimeter. Also, the housing carries a trigger for operating a charging system mounted in the housing. The charging system includes a magnetic loop including a permanent magnet for establishing a magnetic field through the loop. A segment of the loop is coupled to the trigger for movement thereby to positions opening and closing the loop. A coil inductively coupled with the loop generates coil-generated voltage pulses when the trigger is operated to open and close the loop. The charging system includes an electrical circuit for impressing voltage pulses from the coil across a capacitor for integrating the pulses and applying the resulting integrated voltage across the above-mentioned contact means for charging the dosimeter.

FPGA implementation of self organizing map with digital phase locked loops.

PubMed

Hikawa, Hiroomi

2005-01-01

The self-organizing map (SOM) has found applicability in a wide range of application areas. Recently new SOM hardware with phase modulated pulse signal and digital phase-locked loops (DPLLs) has been proposed (Hikawa, 2005). The system uses the DPLL as a computing element since the operation of the DPLL is very similar to that of SOM's computation. The system also uses square waveform phase to hold the value of the each input vector element. This paper discuss the hardware implementation of the DPLL SOM architecture. For effective hardware implementation, some components are redesigned to reduce the circuit size. The proposed SOM architecture is described in VHDL and implemented on field programmable gate array (FPGA). Its feasibility is verified by experiments. Results show that the proposed SOM implemented on the FPGA has a good quantization capability, and its circuit size very small.

Powerful timing generator using mono-chip timers: An application to pulsed nuclear magnetic resonance

NASA Astrophysics Data System (ADS)

Saint-Jalmes, Hervé; Barjhoux, Yves

1982-01-01

We present a 10 line-7 MHz timing generator built on a single board around two LSI timer chips interfaced to a 16-bit microcomputer. Once programmed from the host computer, this device is able to generate elaborate logic sequences on its 10 output lines without further interventions from the CPU. Powerful architecture introduces new possibilities over conventional memory-based timing simulators and word generators. Loop control on a given sequence of events, loop nesting, and various logic combinations can easily be implemented through a software interface, using a symbolic command language. Typical applications of such a device range from development, emulation, and test of integrated circuits, circuit boards, and communication systems to pulse-controlled instrumentation (radar, ultrasonic systems). A particular application to a pulsed Nuclear Magnetic Resonance (NMR) spectrometer is presented, along with customization of the device for generating four-channel radio-frequency pulses and the necessary sequence for subsequent data acquisition.

Nuclear reactor with internal thimble-type delayed neutron detection system

DOEpatents

Gross, Kenny C.; Poloncsik, John; Lambert, John D. B.

1990-01-01

This invention teaches improved apparatus for the method of detecting a breach in cladded fuel used in a nuclear reactor. The detector apparatus is located in the primary heat exchanger which conveys part of the reactor coolant past at least three separate delayed-neutron detectors mounted in this heat exchanger. The detectors are spaced apart such that the coolant flow time from the core to each detector is different, and these differences are known. The delayed-neutron activity at the detectors is a function of the delay time after the reaction in the fuel until the coolant carrying the delayed-neutron emitter passes the respective detector. This time delay is broken down into separate components including an isotopic holdup time required for the emitter to move through the fuel from the reaction to the coolant at the breach, and two transit times required for the emitter now in the coolant to flow from the breach to the detector loop and then via the loop to the detector. At least two of these time components are determined during calibrated operation of the reactor. Thereafter during normal reactor operation, repeated comparisons are made by the method of regression approximation of the third time component for the best-fit line correlating measured delayed-neutron activity against activity that is approximated according to specific equations. The equations use these time-delay components and known parameter values of the fuel and of the part and emitting daughter isotopes.

Auxiliary quasi-resonant dc tank electrical power converter

DOEpatents

Peng, Fang Z.

2006-10-24

An auxiliary quasi-resonant dc tank (AQRDCT) power converter with fast current charging, voltage balancing (or charging), and voltage clamping circuits is provided for achieving soft-switched power conversion. The present invention is an improvement of the invention taught in U.S. Pat. No. 6,111,770, herein incorporated by reference. The present invention provides faster current charging to the resonant inductor, thus minimizing delay time of the pulse width modulation (PWM) due to the soft-switching process. The new AQRDCT converter includes three tank capacitors or power supplies to achieve the faster current charging and minimize the soft-switching time delay. The new AQRDCT converter further includes a voltage balancing circuit to charge and discharge the three tank capacitors so that additional isolated power supplies from the utility line are not needed. A voltage clamping circuit is also included for clamping voltage surge due to the reverse recovery of diodes.

Tunable electromagnetically induced transparency in integrated silicon photonics circuit.

PubMed

Li, Ang; Bogaerts, Wim

2017-12-11

We comprehensively simulate and experimentally demonstrate a novel approach to generate tunable electromagnetically induced transparency (EIT) in a fully integrated silicon photonics circuit. It can also generate tunable fast and slow light. The circuit is a single ring resonator with two integrated tunable reflectors inside, which form an embedded Fabry-Perot (FP) cavity inside the ring cavity. The mode of the FP cavity can be controlled by tuning the reflections using integrated thermo-optic tuners. Under correct tuning conditions, the interaction of the FP mode and the ring resonance mode will generate a Fano resonance and an EIT response. The extinction ratio and bandwidth of the EIT can be tuned by controlling the reflectors. Measured group delay proves that both fast light and slow light can be generated under different tuning conditions. A maximum group delay of 1100 ps is observed because of EIT. Pulse advance around 1200 ps is also demonstrated.

Burner ignition system

DOEpatents

Carignan, Forest J.

1986-01-21

An electronic ignition system for a gas burner is battery operated. The battery voltage is applied through a DC-DC chopper to a step-up transformer to charge a capacitor which provides the ignition spark. The step-up transformer has a significant leakage reactance in order to limit current flow from the battery during initial charging of the capacitor. A tank circuit at the input of the transformer returns magnetizing current resulting from the leakage reactance to the primary in succeeding cycles. An SCR in the output circuit is gated through a voltage divider which senses current flow through a flame. Once the flame is sensed, further sparks are precluded. The same flame sensor enables a thermopile driven main valve actuating circuit. A safety valve in series with the main gas valve responds to a control pressure thermostatically applied through a diaphragm. The valve closes after a predetermined delay determined by a time delay orifice if the pilot gas is not ignited.

Multi-lead heat sink

DOEpatents

Roose, L.D.

1984-07-03

The disclosure relates to a heat sink used to protect integrated circuits from the heat resulting from soldering them to circuit boards. A tubular housing contains a slidable member which engages somewhat inwardly extending connecting rods, each of which is rotatably attached at one end to the bottom of the housing. The other end of each rod is fastened to an expandable coil spring loop. As the member is pushed downward in the housing, its bottom edge engages and forces outward the connecting rods, thereby expanding the spring so that it will fit over an integrated circuit. After the device is in place, the member is slid upward and the spring contracts about the leads of the integrated circuit. Soldering is now conducted and the spring absorbs excess heat therefrom to protect the integrated circuit. The placement steps are repeated in reverse order to remove the heat sink for use again. 4 figs.

Multi-lead heat sink

DOEpatents

Roose, Lars D.

1984-01-01

The disclosure relates to a heat sink used to protect integrated circuits from the heat resulting from soldering them to circuit boards. A tubular housing contains a slidable member which engages somewhat inwardly extending connecting rods, each of which is rotatably attached at one end to the bottom of the housing. The other end of each rod is fastened to an expandable coil spring loop. As the member is pushed downward in the housing, its bottom edge engages and forces outward the connecting rods, thereby expanding the spring so that it will fit over an integrated circuit. After the device is in place, the member is slid upward and the spring contracts about the leads of the integrated circuit. Soldering is now conducted and the spring absorbs excess heat therefrom to protect the integrated circuit. The placement steps are repeated in reverse order to remove the heat sink for use again.

Multi-lead heat sink

DOEpatents

Roose, L.D.

1982-08-25

The disclosure relates to a heat sink used to protect integrated circuits from the heat resulting from soldering them to circuit boards. A tubular housing contains a slidable member which engages somewhat inwardly extending connecting rods, each of which is rotatably attached at one end to the bottom of the housing. The other end of each rod is fastened to an expandable coil spring loop. As the member is pushed downward in the housing, its bottom edge engages and forces outward the connecting rods, thereby expanding the spring so that it will fit over an integrated circuit. After the device is in place, the member is slid upward and the spring contracts about the leads of the integrated circuit. Soldering is now conducted and the spring absorbs excess heat therefrom to protect the integrated circuit. The placement steps are repeated in reverse order to remove the heat sink for use again.

Analysis and modeling of a family of two-transistor parallel inverters

NASA Technical Reports Server (NTRS)

Lee, F. C. Y.; Wilson, T. G.

1973-01-01

A family of five static dc-to-square-wave inverters, each employing a square-loop magnetic core in conjunction with two switching transistors, is analyzed using piecewise-linear models for the nonlinear characteristics of the transistors, diodes, and saturable-core devices. Four of the inverters are analyzed in detail for the first time. These analyses show that, by proper choice of a frame of reference, each of the five quite differently appearing inverter circuits can be described by a common equivalent circuit. This equivalent circuit consists of a five-segment nonlinear resistor, a nonlinear saturable reactor, and a linear capacitor. Thus, by proper interpretation and identification of the parameters in the different circuits, the results of a detailed solution for one of the inverter circuits provide similar information and insight into the local and global behavior of each inverter in the family.

A fluidic diode, valves, and a sequential-loading circuit fabricated on layered paper.

PubMed

Chen, Hong; Cogswell, Jeremy; Anagnostopoulos, Constantine; Faghri, Mohammad

2012-08-21

Current microfluidic paper-based devices lack crucial components for fluid manipulation. We created a fluidic diode fabricated entirely on a single layer of paper to control the wicking of fluids. The fluidic diode is a two-terminal component that promotes or stops wicking along a paper channel. We further constructed a trigger and a delay valve based on the fluidic diode. Furthermore, we demonstrated a high-level functional circuit, consisting of a diode and a delay valve, to manipulate two fluids in a sequential manner. Our study provides new, transformative tools to manipulate fluid in microfluidic paper-based devices.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chertkov, Michael; Turitsyn, Konstantin; Sulc, Petr

The anticipated increase in the number of plug-in electric vehicles (EV) will put additional strain on electrical distribution circuits. Many control schemes have been proposed to control EV charging. Here, we develop control algorithms based on randomized EV charging start times and simple one-way broadcast communication allowing for a time delay between communication events. Using arguments from queuing theory and statistical analysis, we seek to maximize the utilization of excess distribution circuit capacity while keeping the probability of a circuit overload negligible.

Spacecraft stability and control using new techniques for periodic and time-delayed systems

NASA Astrophysics Data System (ADS)

NAzari, Morad

This dissertation addresses various problems in spacecraft stability and control using specialized theoretical and numerical techniques for time-periodic and time-delayed systems. First, the effects of energy dissipation are considered in the dual-spin spacecraft, where the damper masses in the platform (?) and the rotor (?) cause energy loss in the system. Floquet theory is employed to obtain stability charts for different relative spin rates of the subsystem [special characters omitted] with respect to the subsystem [special characters omitted]. Further, the stability and bifurcation of delayed feedback spin stabilization of a rigid spacecraft is investigated. The spin is stabilized about the principal axis of the intermediate moment of inertia using a simple delayed feedback control law. In particular, linear stability is analyzed via the exponential-polynomial characteristic equations and then the method of multiple scales is used to obtain the normal form of the Hopf bifurcation. Next, the dynamics of a rigid spacecraft with nonlinear delayed multi-actuator feedback control are studied, where a nonlinear feedback controller using an inverse dynamics approach is sought for the controlled system to have the desired linear delayed closed-loop dynamics (CLD). Later, three linear state feedback control strategies based on Chebyshev spectral collocation and the Lyapunov Floquet transformation (LFT) are explored for regulation control of linear periodic time delayed systems. First , a delayed feedback control law with discrete delay is implemented and the stability of the closed-loop response is investigated in the parameter space of available control gains using infinite-dimensional Floquet theory. Second, the delay differential equation (DDE) is discretized into a large set of ordinary differential equations (ODEs) using the Chebyshev spectral continuous time approximation (CSCTA) and delayed feedback with distributed delay is applied. The third strategy involves use of both CSCTA and the reduced Lyapunov Floquet transformation (RLFT) in order to design a non-delayed feedback control law. The delayed Mathieu equation is used as an illustrative example in which the closed-loop response and control effort are compared for all three control strategies. Finally, three example applications of control of time-periodic astrodynamic systems, i.e. formation flying control for an elliptic Keplerian chief orbit, body-fixed hovering control over a tumbling asteroid, and stationkeeping in Earth-Moon L1 halo orbits, are shown using versions of the control strategies introduced above. These applications employ a mixture of feedforward and non-delayed periodic-gain state feedback for tracking control of natural and non-natural motions in these systems. A major conclusion is that control effort is minimized by employing periodic-gain (rather than constant-gain) feedback control in such systems.

A Brain for Speech. Evolutionary Continuity in Primate and Human Auditory-Vocal Processing

PubMed Central

Aboitiz, Francisco

2018-01-01

In this review article, I propose a continuous evolution from the auditory-vocal apparatus and its mechanisms of neural control in non-human primates, to the peripheral organs and the neural control of human speech. Although there is an overall conservatism both in peripheral systems and in central neural circuits, a few changes were critical for the expansion of vocal plasticity and the elaboration of proto-speech in early humans. Two of the most relevant changes were the acquisition of direct cortical control of the vocal fold musculature and the consolidation of an auditory-vocal articulatory circuit, encompassing auditory areas in the temporoparietal junction and prefrontal and motor areas in the frontal cortex. This articulatory loop, also referred to as the phonological loop, enhanced vocal working memory capacity, enabling early humans to learn increasingly complex utterances. The auditory-vocal circuit became progressively coupled to multimodal systems conveying information about objects and events, which gradually led to the acquisition of modern speech. Gestural communication accompanies the development of vocal communication since very early in human evolution, and although both systems co-evolved tightly in the beginning, at some point speech became the main channel of communication. PMID:29636657

Flexible and evolutionary optical access networks

NASA Astrophysics Data System (ADS)

Hsueh, Yu-Li

Passive optical networks (PONs) are promising solutions that will open the first-mile bottleneck. Current PONs employ time division multiplexing (TDM) to share bandwidth among users, leading to low cost but limited capacity. In the future, wavelength division multiplexing (WDM) technologies will be deployed to achieve high performance. This dissertation describes several advanced technologies to enhance PON systems. A spectral shaping line coding scheme is developed to allow a simple and cost-effective overlay of high data-rate services in existing PONs, leaving field-deployed fibers and existing services untouched. Spectral shapes of coded signals can be manipulated to adapt to different systems. For a specific tolerable interference level, the optimal line code can be found which maximizes the data throughput. Experiments are conducted to demonstrate and compare several optimized line codes. A novel PON employing dynamic wavelength allocation to provide bandwidth sharing across multiple physical PONs is designed and experimentally demonstrated. Tunable lasers, arrayed waveguide gratings, and coarse/fine filtering combine to create a flexible optical access solution. The network's excellent scalability can bridge the gap between conventional TDM PONs and WDM PONs. Scheduling algorithms with quality of service support are also investigated. Simulation results show that the proposed architecture exhibits significant performance gain over conventional PON systems. Streaming video transmission is demonstrated on the prototype experimental testbed. The powerful architecture is a promising candidate for next-generation optical access networks. A new CDR circuit for receiving the bursty traffic in PONs is designed and analyzed. It detects data transition edges upon arrival of the data burst and quickly selects the best clock phase by a control logic circuit. Then, an analog delay-locked loop (DLL) keeps track of data transitions and removes phase errors throughout the burst. The combination of the fast phase detection mechanism and a feedback loop based on DLL allows both fast response and manageable jitter performance in the burst-mode application. A new efficient numerical algorithm is developed to analyze holey optical fibers. The algorithm has been verified against experimental data, and is exploited to design holey optical fibers optimized for the discrete Raman amplification.

Acceleration and Storage of Energetic Electrons in Magnetic Loops in the Course of Electric Current Oscillations

NASA Astrophysics Data System (ADS)

Zaitsev, V. V.; Stepanov, A. V.

2017-10-01

A mechanism of electron acceleration and storage of energetic particles in solar and stellar coronal magnetic loops, based on oscillations of the electric current, is considered. The magnetic loop is presented as an electric circuit with the electric current generated by convective motions in the photosphere. Eigenoscillations of the electric current in a loop induce an electric field directed along the loop axis. It is shown that the sudden reductions that occur in the course of type IV continuum and pulsating type III observed in various frequency bands (25 - 180 MHz, 110 - 600 MHz, 0.7 - 3.0 GHz) in solar flares provide evidence for acceleration and storage of the energetic electrons in coronal magnetic loops. We estimate the energization rate and the energy of accelerated electrons and present examples of the storage of energetic electrons in loops in the course of flares on the Sun or on ultracool stars. We also discuss the efficiency of the suggested mechanism as compared with the electron acceleration during the five-minute photospheric oscillations and with the acceleration driven by the magnetic Rayleigh-Taylor instability.

RELAP5-3D Modeling of Heat Transfer Components (Intermediate Heat Exchanger and Helical-Coil Steam Generator) for NGNP Application

DOE Office of Scientific and Technical Information (OSTI.GOV)

N. A. Anderson; P. Sabharwall

2014-01-01

The Next Generation Nuclear Plant project is aimed at the research and development of a helium-cooled high-temperature gas reactor that could generate both electricity and process heat for the production of hydrogen. The heat from the high-temperature primary loop must be transferred via an intermediate heat exchanger to a secondary loop. Using RELAP5-3D, a model was developed for two of the heat exchanger options a printed-circuit heat exchanger and a helical-coil steam generator. The RELAP5-3D models were used to simulate an exponential decrease in pressure over a 20 second period. The results of this loss of coolant analysis indicate thatmore » heat is initially transferred from the primary loop to the secondary loop, but after the decrease in pressure in the primary loop the heat is transferred from the secondary loop to the primary loop. A high-temperature gas reactor model should be developed and connected to the heat transfer component to simulate other transients.« less

Phase-locked loops and their application

NASA Technical Reports Server (NTRS)

Lindsey, W. C. (Editor); Simon, M. K.

1978-01-01

A collection of papers is presented on the characteristics and capabilities of phase-locked loops (PLLs), along with some applications of interest. The discussion covers basic theory (linear and nonlinear); acquisition; threshold; stability; frequency demodulation and detection; tracking; cycle slipping and loss of lock; phase-locked oscillators; operation and performance in the presence of noise; AGC, AFC, and APC circuits and systems; digital PLL; and applications and miscellaneous. With the rapid development of IC technology, PLLs are expected to be used widely in consumer electronics.

Experimental Observation of Classical Dynamical Monodromy

NASA Astrophysics Data System (ADS)

Nerem, M. P.; Salmon, D.; Aubin, S.; Delos, J. B.

2018-03-01

A Hamiltonian system is said to have nontrivial monodromy if its fundamental action-angle loops do not return to their initial topological state at the end of a closed circuit in angular momentum-energy space. This process has been predicted to have consequences which can be seen in dynamical systems, called dynamical monodromy. Using an apparatus consisting of a spherical pendulum subject to magnetic potentials and torques, we observe nontrivial monodromy by the associated topological change in the evolution of a loop of trajectories.

A Measurable Difference: Bridge Versus Loop

NASA Technical Reports Server (NTRS)

1998-01-01

Trig-Tek, Inc.'s Model 251A ACL-8 Anderson Current Loop (ACL) Conditioner is an eight channel device designed to condition variable-resistant sensor signals from Strain Gage and RTD's (Resistance Temperature Device)s. It uses NASA's patented ACL technology instead of the classic wheatstone bridge. The electronic measurement circuit delivers accuracy far beyond previous methods and prevents errors caused by variation in the wires that connect sensors to data collection equipment. This is the first license to market a NASA Dryden Flight Research Center patent.

Microfluidic Serial Dilution Circuit

PubMed Central

Paegel, Brian M.; Grover, William H.; Skelley, Alison M.; Mathies, Richard A.; Joyce, Gerald F.

2008-01-01

In vitro evolution of RNA molecules requires a method for executing many consecutive serial dilutions. To solve this problem, a microfluidic circuit has been fabricated in a three-layer glass-PDMS-glass device. The 400-nL serial dilution circuit contains five integrated membrane valves: three two-way valves arranged in a loop to drive cyclic mixing of the diluent and carryover, and two bus valves to control fluidic access to the circuit through input and output channels. By varying the valve placement in the circuit, carryover fractions from 0.04 to 0.2 were obtained. Each dilution process, which is comprised of a diluent flush cycle followed by a mixing cycle, is carried out with no pipeting, and a sample volume of 400 nL is sufficient for conducting an arbitrary number of serial dilutions. Mixing is precisely controlled by changing the cyclic pumping rate, with a minimum mixing time of 22 s. This microfluidic circuit is generally applicable for integrating automated serial dilution and sample preparation in almost any microfluidic architecture. PMID:17073422

Plug-and-Play Multicellular Circuits with Time-Dependent Dynamic Responses.

PubMed

Urrios, Arturo; Gonzalez-Flo, Eva; Canadell, David; de Nadal, Eulàlia; Macia, Javier; Posas, Francesc

2018-04-20

Synthetic biology studies aim to develop cellular devices for biomedical applications. These devices, based on living instead of electronic or electromechanic technology, might provide alternative treatments for a wide range of diseases. However, the feasibility of these devices depends, in many cases, on complex genetic circuits that must fulfill physiological requirements. In this work, we explored the potential of multicellular architectures to act as an alternative to complex circuits for implementation of new devices. As a proof of concept, we developed specific circuits for insulin or glucagon production in response to different glucose levels. Here, we show that fundamental features, such as circuit's affinity or sensitivity, are dependent on the specific configuration of the multicellular consortia, providing a method for tuning these properties without genetic engineering. As an example, we have designed and built circuits with an incoherent feed-forward loop architecture (FFL) that can be easily adjusted to generate single pulse responses. Our results might serve as a blueprint for future development of cellular devices for glycemia regulation in diabetic patients.

Distortion cancellation performance of miniature delay filters for feed-forward linear power amplifiers.

PubMed

Roy, Manas K

2002-11-01

The technique of feed-forward amplitude control has been widely used in the linearization of power amplifiers for wireless communication systems. In this technique, an error signal due to third order intermodulation distortion (IMD) is extracted, amplified, and used to correct the delayed main line distorted signal. For example, a miniature prototype base station for the Global System for Mobile Communications/Code Division Multiple Access (GSM/CDMA) cellular system uses feed-forward amplifiers with bulky and expensive coaxial cables, about 20 feet in length, to provide about 25 ns of delay. This paper shows alternate space-saving approaches of achieving these delays using three different types of delay filters: electromagnetic interdigital/lumped (<2.5"), ceramic (<1.8"), and ladder-type surface acoustic wave (SAW) (0.15"). The delay lines introduce phase and amplitude imbalance and delay mismatch in the linearization loop due to fabrication tolerances. These adversely affect the IMD cancellation. Using an RF system simulation tool, this paper critically compares the IMD cancellation performance achieved using the three technologies. Simulation results show that the optimization of delay mismatch can achieve the desired cancellation more easily than other parameters. It is shown that, if the critical system parameter (phase deviation from linearity), is maintained at <2.5 degrees peak-to-peak over a 20 MHz bandwidth in the frequency range 855 MHz to 875 MHz, one can achieve 25 dB of IMD cancellation performance. This paper concludes with the suggestion of a set of realistic specifications for a miniature delay filter for the low power loop of the feed-forward amplifier.

Extinguishing trace fear engages the retrosplenial cortex rather than the amygdala

PubMed Central

Kwapis, Janine L.; Jarome, Timothy J.; Lee, Jonathan L.; Gilmartin, Marieke R.; Helmstetter, Fred J.

2013-01-01

Extinction learning underlies the treatment for a variety of anxiety disorders. Most of what is known about the neurobiology of extinction is based on standard “delay” fear conditioning, in which awareness is not required for learning. Little is known about how complex, explicit associations extinguish, however. “Trace” conditioning is considered to be a rodent model of explicit fear because it relies on both the cortex and hippocampus and requires explicit contingency awareness in humans. Here, we explore the neural circuit supporting trace fear extinction in order to better understand how complex memories extinguish. We first show that the amygdala is selectively involved in delay fear extinction; blocking intra-amygdala glutamate receptors disrupted delay, but not trace extinction. Further, ERK phosphorylation was increased in the amygdala after delay, but not trace extinction. We then identify the retrosplenial cortex (RSC) as a key structure supporting trace extinction. ERK phosphorylation was selectively increased in the RSC following trace extinction and blocking intra-RSC NMDA receptors impaired trace, but not delay extinction. These findings indicate that delay and trace extinction require different neural circuits; delay extinction requires plasticity in the amygdala whereas trace extinction requires the RSC. Anxiety disorders linked to explicit memory may therefore depend on cortical processes that have not been traditionally targeted by extinction studies based on delay fear. PMID:24055593

Sensitivity of bandpass filters using recirculating delay-line structures

NASA Astrophysics Data System (ADS)

Heyde, Eric C.

1996-12-01

Recirculating delay lines have value notably as sensors and optical signal processors. Most useful applications depend on a high-finesse response from a network. A proof that, with given response parameters, more complex systems can produce behavior that is more stable to the effects of nonidealities than a single recirculating loop is presented.

Distributed meandering waveguides (DMWs) for novel photonic circuits (Conference Presentation)

NASA Astrophysics Data System (ADS)

Dag, Ceren B.; Anil, Mehmet Ali; Serpengüzel, Ali

2017-05-01

Meandering waveguide distributed feedback structures are novel integrated photonic lightwave and microwave circuit elements. Meandering waveguide distributed feedback structures with a variety of spectral responses can be designed for a variety of lightwave and microwave circuit element functions. Distributed meandering waveguide (DMW) structures [1] show a variety of spectral behaviors with respect to the number of meandering loop mirrors (MLMs) [2] used in their composition as well as their internal coupling constants (Cs). DMW spectral behaviors include Fano resonances, coupled resonator induced transparency (CRIT), notch, add-drop, comb, and hitless filters. What makes the DMW special is the self-coupling property intrinsic to the DMW's nature. The basic example of DMW's nature is motivated through the analogy between the so-called symmetric meandering resonator (SMR), which consists of two coupled MLMs, and the resonator enhanced Mach-Zehnder interferometer (REMZI) [3]. A SMR shows the same spectral characteristics of Fano resonances with its self-coupling property, similar to the single, distributed and binary self coupled optical waveguide (SCOW) resonators [4]. So far DMWs have been studied for their electric field intensity, phase [5] and phasor responses [6]. The spectral analysis is performed using the coupled electric field analysis and the generalization of single meandering loop mirrors to multiple meandering distributed feedback structures is performed with the transfer matrix method. The building block of the meandering waveguide structures, the meandering loop mirror (MLM), is the integrated analogue of the fiber optic loop mirrors. The meandering resonator (MR) is composed of two uncoupled MLM's. The meandering distributed feedback (MDFB) structure is the DFB of the MLM. The symmetric MR (SMR) is composed of two coupled MLM's, and has the characteristics of a Fano resonator in the general case, and tunable power divider or tunable hitless filter in special cases. The antisymmetric MR (AMR) is composed of two coupled MLM's. The AMR has the characteristics of an add-drop filter in the general case, and coupled resonator induced transparency (CRIT) filter in a special case. The symmetric MDFB (SMDFB) is composed of multiple coupled MLM's. The antisymmetric MDFB (AMDFB) is composed of multiple coupled MLM's. The SMDFB and AMDFB can be utilized as band-pass, Fano, or Lorentzian filters, or Rabi splitters. Distributed meandering waveguide elements with extremely rich spectral and phase responses can be designed with creative combinations of distributed meandering waveguides structures for various novel photonic circuits. References [1 ] C. B. Dağ, M. A. Anıl, and A. Serpengüzel, "Meandering Waveguide Distributed Feedback Lightwave Circuits," J. Lightwave Technol, vol. 33, no. 9, pp. 1691-1702, May 2015. [2] N. J. Doran and D. Wood, "Nonlinear-optical loop mirror," Opt. Lett. vol. 13, no. 1, pp. 56-58, Jan. 1988. [3] L. Zhou and A. W. Poon, "Fano resonance-based electrically reconfigurable add-drop filters in silicon microring resonator-coupled Mach-Zehnder interferometers," Opt. Lett. vol. 32, no. 7, pp. 781-783, Apr. 2007. [4] Z. Zou, L. Zhou, X. Sun, J. Xie, H. Zhu, L. Lu, X. Li, and J. Chen, "Tunable two-stage self-coupled optical waveguide resonators," Opt. Lett. vol. 38, no. 8, pp. 1215-1217, Apr. 2013. [5] C. B. Dağ, M. A. Anıl, and A. Serpengüzel, "Novel distributed feedback lightwave circuit elements," in Proc. SPIE, San Francisco, 2015, vol. 9366, p. 93660A. [6] C. B. Dağ, M. A. Anıl, and A. Serpengüzel, "Meandering Waveguide Distributed Feedback Lightwave Elements: Phasor Diagram Analysis," in Proc. PIERS, Prague, 1986-1990 (2015).

Bio-isolated dc operational amplifier. [for bioelectric measurements

NASA Technical Reports Server (NTRS)

Lee, R. D. (Inventor)

1974-01-01

A bio-isolated dc operational amplifier is described for use in making bioelectrical measurements of a patient while providing isolation of the patient from electrical shocks. The circuit contains a first operational amplifier coupled to the patient with its output coupled in a forward loop through a first optic coupler to a second operational amplifier. The output of the second operational amplifier is coupled to suitable monitoring circuitry via a feedback circuit including a second optic coupler to the input of the first operational amplifier.

Hardware implementation of Lorenz circuit systems for secure chaotic communication applications.

PubMed

Chen, Hsin-Chieh; Liau, Ben-Yi; Hou, Yi-You

2013-02-18

This paper presents the synchronization between the master and slave Lorenz chaotic systems by slide mode controller (SMC)-based technique. A proportional-integral (PI) switching surface is proposed to simplify the task of assigning the performance of the closed-loop error system in sliding mode. Then, extending the concept of equivalent control and using some basic electronic components, a secure communication system is constructed. Experimental results show the feasibility of synchronizing two Lorenz circuits via the proposed SMC. 

Experimentation and Evaluation of Advanced Integrated System Concepts.

DTIC Science & Technology

1980-09-26

ART). (b) Selects one of four trunk circuits from each trunk (m) Dual Modem and Loop Interface (DMLI) card. circuit card. (n) Dictation and paging...Arbitrator L Bus - Modems ET _Modems Modems Figure 4-1 Certain Telenet Processor models (see Section 4.3 for details) can be equipped with redundancy to...JMemory Bank B Memory Bank A ArbittrAto Arbitrator A t a i Interface U a Modems $ Figure 4-2 In a system with common logic redundancy all centrally

Optical feedback technique extends frequency response of photoconductors

NASA Technical Reports Server (NTRS)

Katzberg, S. J.

1975-01-01

Feedback circuit consists of high-gain light-to-voltage converter with frequency-limited nonlinear photoconductor inside feedback loop. Feedback element is visible light-emitting diode with light-out versus current-in characteristic that is linear over several decades.

Time Delay in the Kuramoto Model of Coupled Oscillators

NASA Astrophysics Data System (ADS)

Yeung, M. K. Stephen; Strogatz, Steven H.

1999-01-01

We generalize the Kuramoto model of coupled oscillators to allow time-delayed interactions. New phenomena include bistability between synchronized and incoherent states, and unsteady solutions with time-dependent order parameters. We derive exact formulas for the stability boundaries of the incoherent and synchronized states, as a function of the delay, in the special case where the oscillators are identical. The experimental implications of the model are discussed for populations of chirping crickets, where the finite speed of sound causes communication delays, and for physical systems such as coupled phase-locked loops or lasers.

Optically-switched submillimeter-wave oscillator and radiator having a switch-to-switch propagation delay

NASA Technical Reports Server (NTRS)

Spencer, Michael G. (Inventor); Maserjian, Joseph (Inventor)

1995-01-01

A submillimeter wave-generating integrated circuit includes an array of N photoconductive switches biased across a common voltage source and an optical path difference from a common optical pulse of repetition rate f sub 0 providing a different optical delay to each of the switches. In one embodiment, each incoming pulse is applied to successive ones of the N switches with successive delays. The N switches are spaced apart with a suitable switch-to-switch spacing so as to generate at the output load or antenna radiation of a submillimeter wave frequency f on the order of N f sub 0. Preferably, the optical pulse has a repetition rate of at least 10 GHz and N is of the order of 100, so that the circuit generates radiation of frequency of the order of or greater than 1 Terahertz.

SHORT PULSE STRETCHER

DOEpatents

Branum, D.R.; Cummins, W.F.

1962-12-01

>A short pulse stretching circuit capable of stretching a short puise to enable it to be displayed on a relatively slow sweeping oscilloscope is described. Moreover, the duration of the pulse is increased by charging a capacitor through a diode and thereafter discharging the capacitor at such time as is desired. In the circuit the trigger pulse alone passes through a delay line, whereas the main signal passes through the diode only, and results in over-all circuit losses which are proportional to the low losses of the diode only. (AEC)

Damping Resonant Current in a Spark-Gap Trigger Circuit to Reduce Noise

DTIC Science & Technology

2009-06-01

DAMPING RESONANT CURRENT IN A SPARK- GAP TRIGGER CIRCUIT TO REDUCE NOISE E. L. Ruden Air Force Research Laboratory, Directed Energy Directorate, AFRL...REPORT TYPE N/A 3. DATES COVERED - 4. TITLE AND SUBTITLE Damping Resonant Current In A Spark- Gap Trigger Circuit To Reduce Noise 5a...thereby triggering 2 after delay 0, is 1. Each of the two rail- gaps (represented by 2) is trig- gered to close after the spark- gap (1) in the

Flexible, High-Speed CdSe Nanocrystal Integrated Circuits.

PubMed

Stinner, F Scott; Lai, Yuming; Straus, Daniel B; Diroll, Benjamin T; Kim, David K; Murray, Christopher B; Kagan, Cherie R

2015-10-14

We report large-area, flexible, high-speed analog and digital colloidal CdSe nanocrystal integrated circuits operating at low voltages. Using photolithography and a newly developed process to fabricate vertical interconnect access holes, we scale down device dimensions, reducing parasitic capacitances and increasing the frequency of circuit operation, and scale up device fabrication over 4 in. flexible substrates. We demonstrate amplifiers with ∼7 kHz bandwidth, ring oscillators with <10 μs stage delays, and NAND and NOR logic gates.

Highly integrated optical heterodyne phase-locked loop with phase/frequency detection.

PubMed

Lu, Mingzhi; Park, Hyunchul; Bloch, Eli; Sivananthan, Abirami; Bhardwaj, Ashish; Griffith, Zach; Johansson, Leif A; Rodwell, Mark J; Coldren, Larry A

2012-04-23

A highly-integrated optical phase-locked loop with a phase/frequency detector and a single-sideband mixer (SSBM) has been proposed and demonstrated for the first time. A photonic integrated circuit (PIC) has been designed, fabricated and tested, together with an electronic IC (EIC). The PIC integrates a widely-tunable sampled-grating distributed-Bragg-reflector laser, an optical 90 degree hybrid and four high-speed photodetectors on the InGaAsP/InP platform. The EIC adds a single-sideband mixer, and a digital phase/frequency detector, to provide single-sideband heterodyne locking from -9 GHz to 7.5 GHz. The loop bandwith is 400 MHz. © 2012 Optical Society of America

A high-speed, tunable silicon photonic ring modulator integrated with ultra-efficient active wavelength control.

PubMed

Zheng, Xuezhe; Chang, Eric; Amberg, Philip; Shubin, Ivan; Lexau, Jon; Liu, Frankie; Thacker, Hiren; Djordjevic, Stevan S; Lin, Shiyun; Luo, Ying; Yao, Jin; Lee, Jin-Hyoung; Raj, Kannan; Ho, Ron; Cunningham, John E; Krishnamoorthy, Ashok V

2014-05-19

We report the first complete 10G silicon photonic ring modulator with integrated ultra-efficient CMOS driver and closed-loop wavelength control. A selective substrate removal technique was used to improve the ring tuning efficiency. Limited by the thermal tuner driver output power, a maximum open-loop tuning range of about 4.5nm was measured with about 14mW of total tuning power including the heater driver circuit power consumption. Stable wavelength locking was achieved with a low-power mixed-signal closed-loop wavelength controller. An active wavelength tracking range of > 500GHz was demonstrated with controller energy cost of only 20fJ/bit.

Digital compensation techniques for the effects of time lag in closed-loop simulation using the 6 DOF motion system

NASA Technical Reports Server (NTRS)

Brown, R.

1982-01-01

Efforts are continued to develop digital filter compensation schemes for the correction of momentum gains observed in the closed loop simulation of the docking of two satellites using the 6 DOF motion system. Several filters that work well for small delays ( .100ms) and a non-preloaded probe are discussed.

Speed synchronization control for integrated automotive motor-transmission powertrain system with random delays

NASA Astrophysics Data System (ADS)

Zhu, Xiaoyuan; Zhang, Hui; Fang, Zongde

2015-12-01

This paper presents a robust speed synchronization controller design for an integrated motor-transmission powertrain system in which the driving motor and multi-gearbox are directly coupled. As the controller area network (CAN) is commonly used in the vehicle powertrain system, the possible network-induced random delays in both feedback and forward channel are considered and modeled by using two Markov chains in the controller design process. For the application perspective, the control law adopted here is a generalized proportional-integral (PI) control. By employing the system-augmentation technique, a delay-free stochastic closed-loop system is obtained and the generalized PI controller design problem is converted to a static output feedback (SOF) controller design problem. Since there are external disturbances involved in the closed-loop system, the energy-to-peak performance is considered to guarantee the robustness of the controller. And the controlled output is chosen as the speed synchronization error. To further improve the transient response of the closed-loop system, the pole placement is also employed in the energy-to-peak performance based speed synchronization control. The mode-dependent control gains are obtained by using an iterative linear matrix inequality (LMI) algorithm. Simulation results show the effectiveness of the proposed control approach.

Digital phase shifter synchronizes local oscillators

NASA Technical Reports Server (NTRS)

Ali, S. M.

1978-01-01

Digital phase-shifting network is used as synchronous frequency multiplier for applications such as phase-locking two signals that may differ in frequency. Circuit has various phase-shift capability. Possible applications include data-communication systems and hybrid digital/analog phase-locked loops.

TRIAC/SCR proportional control circuit

DOEpatents

Hughes, Wallace J.

1999-01-01

A power controller device which uses a voltage-to-frequency converter in conjunction with a zero crossing detector to linearly and proportionally control AC power being supplied to a load. The output of the voltage-to frequency converter controls the "reset" input of a R-S flip flop, while an "0" crossing detector controls the "set" input. The output of the flip flop triggers a monostable multivibrator controlling the SCR or TRIAC firing circuit connected to the load. Logic gates prevent the direct triggering of the multivibrator in the rare instance where the "reset" and "set" inputs of the flip flop are in coincidence. The control circuit can be supplemented with a control loop, providing compensation for line voltage variations.

Simple two-electrode biosignal amplifier.

PubMed

Dobrev, D; Neycheva, T; Mudrov, N

2005-11-01

A simple, cost effective circuit for a two-electrode non-differential biopotential amplifier is proposed. It uses a 'virtual ground' transimpedance amplifier and a parallel RC network for input common mode current equalisation, while the signal input impedance preserves its high value. With this innovative interface circuit, a simple non-inverting amplifier fully emulates high CMRR differential. The amplifier equivalent CMRR (typical range from 70-100 dB) is equal to the open loop gain of the operational amplifier used in the transimpedance interface stage. The circuit has very simple structure and utilises a small number of popular components. The amplifier is intended for use in various two-electrode applications, such as Holter-type monitors, defibrillators, ECG monitors, biotelemetry devices etc.

Design of a Closed-Loop, Bidirectional Brain Machine Interface System With Energy Efficient Neural Feature Extraction and PID Control.

PubMed

Liu, Xilin; Zhang, Milin; Richardson, Andrew G; Lucas, Timothy H; Van der Spiegel, Jan

2017-08-01

This paper presents a bidirectional brain machine interface (BMI) microsystem designed for closed-loop neuroscience research, especially experiments in freely behaving animals. The system-on-chip (SoC) consists of 16-channel neural recording front-ends, neural feature extraction units, 16-channel programmable neural stimulator back-ends, in-channel programmable closed-loop controllers, global analog-digital converters (ADC), and peripheral circuits. The proposed neural feature extraction units includes 1) an ultra low-power neural energy extraction unit enabling a 64-step natural logarithmic domain frequency tuning, and 2) a current-mode action potential (AP) detection unit with time-amplitude window discriminator. A programmable proportional-integral-derivative (PID) controller has been integrated in each channel enabling a various of closed-loop operations. The implemented ADCs include a 10-bit voltage-mode successive approximation register (SAR) ADC for the digitization of the neural feature outputs and/or local field potential (LFP) outputs, and an 8-bit current-mode SAR ADC for the digitization of the action potential outputs. The multi-mode stimulator can be programmed to perform monopolar or bipolar, symmetrical or asymmetrical charge balanced stimulation with a maximum current of 4 mA in an arbitrary channel configuration. The chip has been fabricated in 0.18 μ m CMOS technology, occupying a silicon area of 3.7 mm 2 . The chip dissipates 56 μW/ch on average. General purpose low-power microcontroller with Bluetooth module are integrated in the system to provide wireless link and SoC configuration. Methods, circuit techniques and system topology proposed in this work can be used in a wide range of relevant neurophysiology research, especially closed-loop BMI experiments.

Nanoscale superconducting memory based on the kinetic inductance of asymmetric nanowire loops

NASA Astrophysics Data System (ADS)

Murphy, Andrew; Averin, Dmitri V.; Bezryadin, Alexey

2017-06-01

The demand for low-dissipation nanoscale memory devices is as strong as ever. As Moore’s law is staggering, and the demand for a low-power-consuming supercomputer is high, the goal of making information processing circuits out of superconductors is one of the central goals of modern technology and physics. So far, digital superconducting circuits could not demonstrate their immense potential. One important reason for this is that a dense superconducting memory technology is not yet available. Miniaturization of traditional superconducting quantum interference devices is difficult below a few micrometers because their operation relies on the geometric inductance of the superconducting loop. Magnetic memories do allow nanometer-scale miniaturization, but they are not purely superconducting (Baek et al 2014 Nat. Commun. 5 3888). Our approach is to make nanometer scale memory cells based on the kinetic inductance (and not geometric inductance) of superconducting nanowire loops, which have already shown many fascinating properties (Aprili 2006 Nat. Nanotechnol. 1 15; Hopkins et al 2005 Science 308 1762). This allows much smaller devices and naturally eliminates magnetic-field cross-talk. We demonstrate that the vorticity, i.e., the winding number of the order parameter, of a closed superconducting loop can be used for realizing a nanoscale nonvolatile memory device. We demonstrate how to alter the vorticity in a controlled fashion by applying calibrated current pulses. A reliable read-out of the memory is also demonstrated. We present arguments that such memory can be developed to operate without energy dissipation.

Clocking and Synchronization Circuits in Multiprocessor Systems

DTIC Science & Technology

1989-04-01

18 3.4 Inter -chip Clocking Strategies...may occur when two or more of the switches make transitions at different times during the inter - val during which those inputs are being processed...increased without any fruitful computation. The sources of the inter -chip clock skew are the electromagnetic propagation delay, the buffer delay within

The effect of visual-motion time-delays on pilot performance in a simulated pursuit tracking task

NASA Technical Reports Server (NTRS)

Miller, G. K., Jr.; Riley, D. R.

1977-01-01

An experimental study was made to determine the effect on pilot performance of time delays in the visual and motion feedback loops of a simulated pursuit tracking task. Three major interrelated factors were identified: task difficulty either in the form of airplane handling qualities or target frequency, the amount and type of motion cues, and time delay itself. In general, the greater the task difficulty, the smaller the time delay that could exist without degrading pilot performance. Conversely, the greater the motion fidelity, the greater the time delay that could be tolerated. The effect of motion was, however, pilot dependent.

Photonic integrated circuits unveil crisis-induced intermittency.

PubMed

Karsaklian Dal Bosco, Andreas; Akizawa, Yasuhiro; Kanno, Kazutaka; Uchida, Atsushi; Harayama, Takahisa; Yoshimura, Kazuyuki

2016-09-19

We experimentally investigate an intermittent route to chaos in a photonic integrated circuit consisting of a semiconductor laser with time-delayed optical feedback from a short external cavity. The transition from a period-doubling dynamics to a fully-developed chaos reveals a stage intermittently exhibiting these two dynamics. We unveil the bifurcation mechanism underlying this route to chaos by using the Lang-Kobayashi model and demonstrate that the process is based on a phenomenon of attractor expansion initiated by a particular distribution of the local Lyapunov exponents. We emphasize on the crucial importance of the distribution of the steady-state solutions introduced by the time-delayed feedback on the existence of this intermittent dynamics.

Post-KR Delay Intervals and Mental Practice: A Test of Adams' Closed Loop Theory

ERIC Educational Resources Information Center

Bole, Ronald

1976-01-01

The present study suggests that post-KR delay interval time or activity in the interval has little to do with learning on a self-paced positioning task, not ruling out that on ballistic tasks or more complex nonballistic tasks that a learner could make use of additional time or strategy. (MB)

Global output feedback stabilisation of stochastic high-order feedforward nonlinear systems with time-delay

NASA Astrophysics Data System (ADS)

Zhang, Kemei; Zhao, Cong-Ran; Xie, Xue-Jun

2015-12-01

This paper considers the problem of output feedback stabilisation for stochastic high-order feedforward nonlinear systems with time-varying delay. By using the homogeneous domination theory and solving several troublesome obstacles in the design and analysis, an output feedback controller is constructed to drive the closed-loop system globally asymptotically stable in probability.

Controlled initialization of superconducting π-phaseshifters and possible applications

NASA Astrophysics Data System (ADS)

Mielke, Olaf; Ortlepp, Thomas; Kunert, Juergen; Meyer, Hans-Georg; Toepfer, Hannes

2010-05-01

The rapid single-flux quantum electronics (RSFQ) is a superconducting, naturally digital circuit family which is currently close to being commercially applied. RSFQ is outstanding because of its very low switching energy resulting in very low power consumption. This advantage causes, however, a significant influence of thermal noise. For industrial applications, a certain noise immunity is required which is still a challenge, especially for circuits of higher complexity. Integrating phase-shifting elements is a new concept for further improvements concerning stability against the influence of thermal noise. We have already shown that the implementation of phase-shifting elements significantly reduces the influence of thermal noise on circuit behavior by experimentally analyzing the bit-error rate (Mielke et al 2009 IEEE Trans. Appl. Supercond. 19 621-5). Concepts which are easily implementable in standard niobium technology are especially promising. The π-phaseshifter consists of a superconducting loop which is able to store a single flux quantum. The loop current related to the stored flux creates a well-defined phase shift. To achieve the correct functionality of complex circuits it is essential to store exactly one flux quantum in each π-phaseshifter during the cooling down of the chip. Thus, for studying the feasibility of this new approach, the initialization reliability of the π-phaseshifter needs to be verified. We present an experimental investigation of this reliability to obtain a general assessment for the application of the π-phaseshifter in niobium technology. Furthermore, we compare the configuration shielded by a solid ground plane with a configuration with a ground-plane hole below the π-phaseshifter. Justified by the experimental results we suggest programmable RSFQ circuits based on π-phaseshifters. The characteristics of these devices can be influenced by a controlled initialization of the π-phaseshifter. The fabrication was performed by FLUXONICS Foundry.

Research on design feasibility of high-power light-weight dc-to-dc converters for space power applications

NASA Technical Reports Server (NTRS)

Wilson, T. G.

1981-01-01

Utilizing knowledge gained from past experience with experimental current-or-voltage step-up dc-to-dc converter power stages operating at output powers up to and in excess of 2 kW, a new experimental current-or-voltage step-up power stage using paralleled bipolar junction transistors (BJTs) as the controlled power switch, was constructed during the current reporting period. The major motivation behind the construction of this new experimental power stage was to improve the circuit layout so as to reduce the effects of stray circuit parasitic inductances resulting from excess circuit lead lengths and circuit loops, and to take advantage of the layout improvements which could be made when some recently-available power components, particularly power diodes and polypropylene filter capacitors, were incorporated into the design.

Implementation of Basic and Universal Gates In a single Circuit Based On Quantum-dot Cellular Automata Using Multi-Layer Crossbar Wire

NASA Astrophysics Data System (ADS)

Bhowmik, Dhrubajyoti; Saha, Apu Kr; Dutta, Paramartha; Nandi, Supratim

2017-08-01

Quantum-dot Cellular Automata (QCA) is one of the most substitutes developing nanotechnologies for electronic circuits, as a result of lower force utilization, higher speed and smaller size in correlation with CMOS innovation. The essential devices, a Quantum-dot cell can be utilized to logic gates and wires. As it is the key building block on nanotechnology circuits. By applying simple gates, the hardware requirements for a QCA circuit can be decreased and circuits can be less complex as far as level, delay and cell check. This article exhibits an unobtrusive methodology for actualizing novel upgraded simple and universal gates, which can be connected to outline numerous variations of complex QCA circuits. Proposed gates are straightforward in structure and capable as far as implementing any digital circuits. The main aim is to build all basic and universal gates in a simple circuit with and without crossbar-wire. Simulation results and physical relations affirm its handiness in actualizing each advanced circuit.

Optoelectronic frequency discriminated phase tuning technology and its applications

NASA Astrophysics Data System (ADS)

Lin, Gong-Ru; Chang, Yung-Cheng

2000-07-01

By using a phase-tunable optoelectronic phase-locked loop, we are able to continuously change the phase as well as the delay-time of optically distributed microwave clock signals or optical pulse train. The advantages of the proposed technique include such as wide-band operation up to 20GHz, wide-range tuning up to 640 degrees, high tuning resolution of <6x10-2 degree/mV, ultra-low short-term phase fluctuation and drive of 4.7x10-2 degree and 3.4x10- 3 degree/min, good linearity with acceptable deviations, and frequency-independent transferred function with slope of nearly 90 degrees/volt, etc. The novel optoelectronic phase shifter is performed by using a DC-voltage controlled, optoelectronic-mixer-based, frequency-down-converted digital phase-locked-loop. The maximum delay-time is continuously tunable up to 3.9 ns for optical pulses repeated at 500 MHz from a gain-switched laser diode. This corresponds to a delay responsivity of about 0.54 ps/mV. The using of the OEPS as being an optoelectronic delay-time controller for optical pulses is demonstrated with temporal resolution of <0.2 ps. Electro-optic sampling of high-frequency microwave signals by using the in-situ delay-time-tunable pulsed laser as a novel optical probe is primarily reported.

BLOCKING OSCILLATOR DOUBLE PULSE GENERATOR CIRCUIT

DOEpatents

Haase, J.A.

1961-01-24

A double-pulse generator, particuiarly a double-pulse generator comprising a blocking oscillator utilizing a feedback circuit to provide means for producing a second pulse within the recovery time of the blocking oscillator, is described. The invention utilized a passive network which permits adjustment of the spacing between the original pulses derived from the blocking oscillator and further utilizes the original pulses to trigger a circuit from which other pulses are initiated. These other pulses are delayed and then applied to the input of the blocking oscillator, with the result that the output from the oscillator circuit contains twice the number of pulses originally initiated by the blocking oscillator itself.

Ultra Low Energy Binary Decision Diagram Circuits Using Few Electron Transistors

NASA Astrophysics Data System (ADS)

Saripalli, Vinay; Narayanan, Vijay; Datta, Suman

Novel medical applications involving embedded sensors, require ultra low energy dissipation with low-to-moderate performance (10kHz-100MHz) driving the conventional MOSFETs into sub-threshold operation regime. In this paper, we present an alternate ultra-low power computing architecture using Binary Decision Diagram based logic circuits implemented using Single Electron Transistors (SETs) operating in the Coulomb blockade regime with very low supply voltages. We evaluate the energy - performance tradeoff metrics of such BDD circuits using time domain Monte Carlo simulations and compare them with the energy-optimized CMOS logic circuits. Simulation results show that the proposed approach achieves better energy-delay characteristics than CMOS realizations.

Multiplier less high-speed squaring circuit for binary numbers

NASA Astrophysics Data System (ADS)

Sethi, Kabiraj; Panda, Rutuparna

2015-03-01

The squaring operation is important in many applications in signal processing, cryptography etc. In general, squaring circuits reported in the literature use fast multipliers. A novel idea of a squaring circuit without using multipliers is proposed in this paper. Ancient Indian method used for squaring decimal numbers is extended here for binary numbers. The key to our success is that no multiplier is used. Instead, one squaring circuit is used. The hardware architecture of the proposed squaring circuit is presented. The design is coded in VHDL and synthesised and simulated in Xilinx ISE Design Suite 10.1 (Xilinx Inc., San Jose, CA, USA). It is implemented in Xilinx Vertex 4vls15sf363-12 device (Xilinx Inc.). The results in terms of time delay and area is compared with both modified Booth's algorithm and squaring circuit using Vedic multipliers. Our proposed squaring circuit seems to have better performance in terms of both speed and area.

Analog circuit for controlling acoustic transducer arrays

DOEpatents

Drumheller, Douglas S.

1991-01-01

A simplified ananlog circuit is presented for controlling electromechanical transducer pairs in an acoustic telemetry system. The analog circuit of this invention comprises a single electrical resistor which replaces all of the digital components in a known digital circuit. In accordance with this invention, a first transducer in a transducer pair of array is driven in series with the resistor. The voltage drop across this resistor is then amplified and used to drive the second transducer. The voltage drop across the resistor is proportional and in phase with the current to the transducer. This current is approximately 90 degrees out of phase with the driving voltage to the transducer. This phase shift replaces the digital delay required by the digital control circuit of the prior art.

An RFID-Based Closed-Loop Wireless Power Transmission System for Biomedical Applications.

PubMed

Kiani, Mehdi; Ghovanloo, Maysam

2010-04-01

This brief presents a standalone closed-loop wireless power transmission system that is built around a commercial off-the-shelf (COTS) radio-frequency identification (RFID) reader (TRF7960) operating at 13.56 MHz. It can be used for inductively powering implantable biomedical devices in a closed loop. Any changes in the distance and misalignment between transmitter and receiver coils in near-field wireless power transmission can cause a significant change in the received power, which can cause either a malfunction or excessive heat dissipation. RFID circuits are often used in an open loop. However, their back telemetry capability can be utilized to stabilize the received voltage on the implant. Our measurements showed that the delivered power to the transponder was maintained at 11.2 mW over a range of 0.5 to 2 cm, while the transmitter power consumption changed from 78 mW to 1.1 W. The closed-loop system can also oppose voltage variations as a result of sudden changes in the load current.

High resolution angular sensor. [reducing ring laser gyro output quantization using phase locked loops

NASA Technical Reports Server (NTRS)

Gneses, M. I.; Berg, D. S.

1981-01-01

Specifications for the pointing stabilization system of the large space telescope were used in an investigation of the feasibility of reducing ring laser gyro output quantization to the sub-arc-second level by the use of phase locked loops and associated electronics. Systems analysis procedures are discussed and a multioscillator laser gyro model is presented along with data on the oscillator noise. It is shown that a second order closed loop can meet the measurement noise requirements when the loop gain and time constant of the loop filter are appropriately chosen. The preliminary electrical design is discussed from the standpoint of circuit tradeoff considerations. Analog, digital, and hybrid designs are given and their applicability to the high resolution sensor is examined. the electrical design choice of a system configuration is detailed. The design and operation of the various modules is considered and system block diagrams are included. Phase 1 and 2 test results using the multioscillator laser gyro are included.

Human in the Loop Simulation Measures of Pilot Response Delay in a Self-Separation Concept of Operations

NASA Technical Reports Server (NTRS)

Consiglio, Maria C.; Wilson, Sara R.; Sturdy, James; Murdoch, Jennifer L.; Wing, David J.

2010-01-01

A human-in-the-loop (HITL) simulation experiment was conducted by the National Aeronautics and Space Administration (NASA) to assess airline transport pilots performance and reported acceptance of the use of procedures relying on airborne separation assistance and trajectory management tools. This study was part of a larger effort involving two NASA centers that includes multiple HITL experiments planned over the next few years to evaluate the use of automated separation assurance (SA) tools by both air traffic controllers and pilots. This paper presents results of measured pilot response delay that subject pilots incurred when interacting with cockpit tools for SA and discusses possible implications for future concept and procedures design.

Case Study: Influences of Uncertainties and Traffic Scenario Difficulties in a Human-in-the-Loop Simulation

NASA Technical Reports Server (NTRS)

Bienert, Nancy; Mercer, Joey; Homola, Jeffrey; Morey, Susan; Prevot, Thomas

2014-01-01

This paper presents a case study of how factors such as wind prediction errors and metering delays can influence controller performance and workload in Human-In-The-Loop simulations. Retired air traffic controllers worked two arrival sectors adjacent to the terminal area. The main tasks were to provide safe air traffic operations and deliver the aircraft to the metering fix within +/- 25 seconds of the scheduled arrival time with the help of provided decision support tools. Analyses explore the potential impact of metering delays and system uncertainties on controller workload and performance. The results suggest that trajectory prediction uncertainties impact safety performance, while metering fix accuracy and workload appear subject to the scenario difficulty.

Implementation of Nonlinear Control Laws for an Optical Delay Line

NASA Technical Reports Server (NTRS)

Hench, John J.; Lurie, Boris; Grogan, Robert; Johnson, Richard

2000-01-01

This paper discusses the implementation of a globally stable nonlinear controller algorithm for the Real-Time Interferometer Control System Testbed (RICST) brassboard optical delay line (ODL) developed for the Interferometry Technology Program at the Jet Propulsion Laboratory. The control methodology essentially employs loop shaping to implement linear control laws. while utilizing nonlinear elements as means of ameliorating the effects of actuator saturation in its coarse, main, and vernier stages. The linear controllers were implemented as high-order digital filters and were designed using Bode integral techniques to determine the loop shape. The nonlinear techniques encompass the areas of exact linearization, anti-windup control, nonlinear rate limiting and modal control. Details of the design procedure are given as well as data from the actual mechanism.

Note: Large active area solid state photon counter with 20 ps timing resolution and 60 fs detection delay stability

NASA Astrophysics Data System (ADS)

Prochazka, Ivan; Kodet, Jan; Eckl, Johann; Blazej, Josef

2017-10-01

We are reporting on the design, construction, and performance of a photon counting detector system, which is based on single photon avalanche diode detector technology. This photon counting device has been optimized for very high timing resolution and stability of its detection delay. The foreseen application of this detector is laser ranging of space objects, laser time transfer ground to space and fundamental metrology. The single photon avalanche diode structure, manufactured on silicon using K14 technology, is used as a sensor. The active area of the sensor is circular with 200 μm diameter. Its photon detection probability exceeds 40% in the wavelength range spanning from 500 to 800 nm. The sensor is operated in active quenching and gating mode. A new control circuit was optimized to maintain high timing resolution and detection delay stability. In connection to this circuit, timing resolution of the detector is reaching 20 ps FWHM. In addition, the temperature change of the detection delay is as low as 70 fs/K. As a result, the detection delay stability of the device is exceptional: expressed in the form of time deviation, detection delay stability of better than 60 fs has been achieved. Considering the large active area aperture of the detector, this is, to our knowledge, the best timing performance reported for a solid state photon counting detector so far.

Seeking a unified framework for cerebellar function and dysfunction: from circuit operations to cognition

PubMed Central

D'Angelo, Egidio; Casali, Stefano

2013-01-01

Following the fundamental recognition of its involvement in sensory-motor coordination and learning, the cerebellum is now also believed to take part in the processing of cognition and emotion. This hypothesis is recurrent in numerous papers reporting anatomical and functional observations, and it requires an explanation. We argue that a similar circuit structure in all cerebellar areas may carry out various operations using a common computational scheme. On the basis of a broad review of anatomical data, it is conceivable that the different roles of the cerebellum lie in the specific connectivity of the cerebellar modules, with motor, cognitive, and emotional functions (at least partially) segregated into different cerebro-cerebellar loops. We here develop a conceptual and operational framework based on multiple interconnected levels (a meta-levels hypothesis): from cellular/molecular to network mechanisms leading to generation of computational primitives, thence to high-level cognitive/emotional processing, and finally to the sphere of mental function and dysfunction. The main concept explored is that of intimate interplay between timing and learning (reminiscent of the “timing and learning machine” capabilities long attributed to the cerebellum), which reverberates from cellular to circuit mechanisms. Subsequently, integration within large-scale brain loops could generate the disparate cognitive/emotional and mental functions in which the cerebellum has been implicated. We propose, therefore, that the cerebellum operates as a general-purpose co-processor, whose effects depend on the specific brain centers to which individual modules are connected. Abnormal functioning in these loops could eventually contribute to the pathogenesis of major brain pathologies including not just ataxia but also dyslexia, autism, schizophrenia, and depression. PMID:23335884

High-speed clock recovery with phase-locked-loop-based on LiNbO3 modulators

NASA Astrophysics Data System (ADS)

Zhu, Guanghao; Chen, Hongmin; Wang, Qiang; Dutta, Niloy K.

2003-08-01

In this paper, we present a scheme for recovering 10 GHz clock from 40 Gb/s and 80 Gb/s time division multiplexed (TDM) return to zero (RZ) data stream. The proposed clock recovery is successfully demonstrated using an electrical phase locked loop (PLL). The jitter of the recovered clock is estimated to be around 50 fs. The key part in the proposed clock recovery circuit is a LiNbO3 Mach-Zehnder modulator which is shown to be highly effective in optical to electrical down conversion.

Digital Baseband Architecture For Transponder

NASA Technical Reports Server (NTRS)

Nguyen, Tien M.; Yeh, Hen-Geul

1995-01-01

Proposed advanced transponder for long-distance radio communication system with turnaround ranging contains carrier-signal-tracking loop including baseband digital "front end." For reduced cost, transponder includes analog intermediate-frequency (IF) section and analog automatic gain control (AGC) loop at first of two IF mixers. However, second IF mixer redesigned to ease digitization of baseband functions. To conserve power and provide for simpler and smaller transponder hardware, baseband digital signal-processing circuits designed to implement undersampling scheme. Furthermore, sampling scheme and sampling frequency chosen so redesign involves minimum modification of command-detector unit (CDU).

Fiber-To-The-Home: Current Issues And Strategies For A Bell Operating Company

NASA Astrophysics Data System (ADS)

Engel, Joel

1990-01-01

This decade has seen extensive use of fiber in the telephone network. Fiber is already pervasive in interoffice facilities, and is now being introduced into the local loop, which represents 90% of telephone circuit miles. In the feeder portion of the loop, the connection between the central office and remote terminals, fiber has already made significant inroads. In fact, Ameritech has more route miles of fiber in each of its five states than is in the entire network of the interexchange carrier whose advertisements stress their use of fiber.

Hybrid Smith predictor and phase lead based divergence compensation for hardware-in-the-loop contact simulation with measurement delay

NASA Astrophysics Data System (ADS)

Qi, Chenkun; Gao, Feng; Zhao, Xianchao; Wang, Qian; Ren, Anye

2018-06-01

On the ground the hardware-in-the-loop (HIL) simulation is a good approach to test the contact dynamics of spacecraft docking process in space. Unfortunately, due to the time delay in the system the HIL contact simulation becomes divergent. However, the traditional first-order phase lead compensation approach still result in a small divergence for the pure time delay. The serial Smith predictor and phase lead compensation approach proposed by the authors recently will lead to an over-compensation and an obvious convergence. In this study, a hybrid Smith predictor and phase lead compensation approach is proposed. The hybrid Smith predictor and phase lead compensation can achieve a higher simulation fidelity with a little convergence. The phase angle of the compensator is analyzed and the stability condition of the HIL simulation system is given. The effectiveness of the proposed compensation approach is tested by simulations on an undamped elastic contact process.

The Effectiveness of TAG or Guard-Gates in SET Suppression Using Delay and Dual-Rail Configurations at 0.35 microns

NASA Technical Reports Server (NTRS)

Shuler, Robert L.; Balasubramanian, Anupama; Narasimham, Balaji; Bhuva, Bharat; O'Neill, Patrick M.; Kouba, Coy

2006-01-01

Design options for decreasing the susceptibility of integrated circuits to Single Event Upset (SEU) fall into two categories: (1) increasing the critical charge to cause an upset at a particular node, and (2) employing redundancy to mask or correct errors. With decreasing device sizes on an Integrated Circuit (IC), the amount of charge required to represent a logic state has steadily reduced. Critical charge methods such as increasing drive strength or increasing the time required to change state as in capacitive or resistive hardening or delay based approaches extract a steadily increasing penalty as a percentage of device resources and performance. Dual redundancy is commonly assumed only to provide error detection with Triple Modular Redundancy (TMR) required for correction, but less well known methods employ dual redundancy to achieve full error correction by voting two inputs with a prior state to resolve ambiguity. This requires special circuits such as the Whitaker latch [1], or the guard-gate [2] which some of us have called a Transition AND Gate (TAG) [3]. A 2-input guard gate is shown in Figure 1. It is similar to a Muller Completion Element [4] and relies on capacitance at node "out" to retain the prior state when inputs disagree, while eliminating any output buffer which would be susceptible to radiation strikes. This paper experimentally compares delay based and dual rail flip-flop designs wherein both types of circuits employ guard-gates to optimize layout and performance, and draws conclusions about design criteria and suitability of each option. In both cases a design goal is protection against Single Event Transients (SET) in combinational logic as well as SEU in the storage elements. For the delay based design, it is also a goal to allow asynchronous clear or preset inputs on the storage elements, which are often not available in radiation tolerant designs.

From Anxious to Reckless: A Control Systems Approach Unifies Prefrontal-Limbic Regulation Across the Spectrum of Threat Detection.

PubMed

Mujica-Parodi, Lilianne R; Cha, Jiook; Gao, Jonathan

2017-01-01

Here we provide an integrative review of basic control circuits, and introduce techniques by which their regulation can be quantitatively measured using human neuroimaging. We illustrate the utility of the control systems approach using four human neuroimaging threat detection studies ( N = 226), to which we applied circuit-wide analyses in order to identify the key mechanism underlying individual variation. In so doing, we build upon the canonical prefrontal-limbic control system to integrate circuit-wide influence from the inferior frontal gyrus (IFG). These were incorporated into a computational control systems model constrained by neuroanatomy and designed to replicate our experimental data. In this model, the IFG acts as an informational set point, gating signals between the primary prefrontal-limbic negative feedback loop and its cortical information-gathering loop. Along the cortical route, if the sensory cortex provides sufficient information to make a threat assessment, the signal passes to the ventromedial prefrontal cortex (vmPFC), whose threat-detection threshold subsequently modulates amygdala outputs. However, if signal outputs from the sensory cortex do not provide sufficient information during the first pass, the signal loops back to the sensory cortex, with each cycle providing increasingly fine-grained processing of sensory data. Simulations replicate IFG (chaotic) dynamics experimentally observed at both ends at the threat-detection spectrum. As such, they identify distinct types of IFG disconnection from the circuit, with associated clinical outcomes. If IFG thresholds are too high, the IFG and sensory cortex cycle for too long; in the meantime the coarse-grained (excitatory) pathway will dominate, biasing ambiguous stimuli as false positives. On the other hand, if cortical IFG thresholds are too low, the inhibitory pathway will suppress the amygdala without cycling back to the sensory cortex for much-needed fine-grained sensory cortical data, biasing ambiguous stimuli as false negatives. Thus, the control systems model provides a consistent mechanism for IFG regulation, capable of producing results consistent with our data for the full spectrum of threat-detection: from fearful to optimal to reckless. More generally, it illustrates how quantitative characterization of circuit dynamics can be used to unify a fundamental dimension across psychiatric affective symptoms, with implications for populations that range from anxiety disorders to addiction.

An area and power-efficient analog li-ion battery charger circuit.

PubMed

Do Valle, Bruno; Wentz, Christian T; Sarpeshkar, Rahul

2011-04-01

The demand for greater battery life in low-power consumer electronics and implantable medical devices presents a need for improved energy efficiency in the management of small rechargeable cells. This paper describes an ultra-compact analog lithium-ion (Li-ion) battery charger with high energy efficiency. The charger presented here utilizes the tanh basis function of a subthreshold operational transconductance amplifier to smoothly transition between constant-current and constant-voltage charging regimes without the need for additional area- and power-consuming control circuitry. Current-domain circuitry for end-of-charge detection negates the need for precision-sense resistors in either the charging path or control loop. We show theoretically and experimentally that the low-frequency pole-zero nature of most battery impedances leads to inherent stability of the analog control loop. The circuit was fabricated in an AMI 0.5-μm complementary metal-oxide semiconductor process, and achieves 89.7% average power efficiency and an end voltage accuracy of 99.9% relative to the desired target 4.2 V, while consuming 0.16 mm(2) of chip area. To date and to the best of our knowledge, this design represents the most area-efficient and most energy-efficient battery charger circuit reported in the literature.

An ultra low-power CMOS automatic action potential detector.

PubMed

Gosselin, Benoit; Sawan, Mohamad

2009-08-01

We present a low-power complementary metal-oxide semiconductor (CMOS) analog integrated biopotential detector intended for neural recording in wireless multichannel implants. The proposed detector can achieve accurate automatic discrimination of action potential (APs) from the background activity by means of an energy-based preprocessor and a linear delay element. This strategy improves detected waveforms integrity and prompts for better performance in neural prostheses. The delay element is implemented with a low-power continuous-time filter using a ninth-order equiripple allpass transfer function. All circuit building blocks use subthreshold OTAs employing dedicated circuit techniques for achieving ultra low-power and high dynamic range. The proposed circuit function in the submicrowatt range as the implemented CMOS 0.18- microm chip dissipates 780 nW, and it features a size of 0.07 mm(2). So it is suitable for massive integration in a multichannel device with modest overhead. The fabricated detector succeeds to automatically detect APs from underlying background activity. Testbench validation results obtained with synthetic neural waveforms are presented.

An Optimized Three-Level Design of Decoder Based on Nanoscale Quantum-Dot Cellular Automata

NASA Astrophysics Data System (ADS)

Seyedi, Saeid; Navimipour, Nima Jafari

2018-03-01

Quantum-dot Cellular Automata (QCA) has been potentially considered as a supersede to Complementary Metal-Oxide-Semiconductor (CMOS) because of its inherent advantages. Many QCA-based logic circuits with smaller feature size, improved operating frequency, and lower power consumption than CMOS have been offered. This technology works based on electron relations inside quantum-dots. Due to the importance of designing an optimized decoder in any digital circuit, in this paper, we design, implement and simulate a new 2-to-4 decoder based on QCA with low delay, area, and complexity. The logic functionality of the 2-to-4 decoder is verified using the QCADesigner tool. The results have shown that the proposed QCA-based decoder has high performance in terms of a number of cells, covered area, and time delay. Due to the lower clock pulse frequency, the proposed 2-to-4 decoder is helpful for building QCA-based sequential digital circuits with high performance.

Spiral Chip Implantable Radiator and Printed Loop External Receptor for RF Telemetry in Bio-Sensor Systems

NASA Technical Reports Server (NTRS)

Simons, Rainee N.; Hall, David G.; Miranda, Felix A.

2004-01-01

The paper describes the operation of a patented wireless RF telemetry system, consisting of a bio-MEMS implantable sensor and an external hand held unit, operating over the frequency range of few hundreds of MHz. A MEMS capacitive pressure sensor integrated with a miniature inductor/antenna together constitute the implantable sensor. Signal processing circuits collocated with a printed loop antenna together form the hand held unit, capable of inductively powering and also receiving the telemetry signals from the sensor. The paper in addition, demonstrates a technique to enhance the quality factor and inductance of the inductor in the presence of a lower ground plane and also presents the radiation characteristics of the loop antenna.

Advanced Space Suit PLSS 2.0 Cooling Loop Evaluation and PLSS 2.5 Recommendations

NASA Technical Reports Server (NTRS)

Steele, John; Quinn, Greg; Campbell, Colin; Makinen, Janice; Watts, Carly; Westheimer, David

2016-01-01

From 2012 to 2015 The NASA/JSC AdvSS (Advanced Space Suit) PLSS (Portable Life Support Subsystem) team, with support from UTC Aerospace Systems, performed the build-up, packaging and testing of PLSS 2.0. One aspect of that testing was the evaluation of the long-term health of the water cooling circuit and the interfacing components. Periodic and end-of-test water, residue and hardware analyses provided valuable information on the status of the water cooling circuit, and the approaches that would be necessary to enhance water cooling circuit health in the future. The evaluated data has been consolidated, interpreted and woven into an action plan for the maintenance of water cooling circuit health for the planned FY (fiscal year) 2016 through FY 2018 PLSS 2.5 testing. This paper provides an overview of the PLSS 2.0 water cooling circuit findings and the associated steps to be taken in that regard for the PLSS 2.5.

Improving dynamic performances of PWM-driven servo-pneumatic systems via a novel pneumatic circuit.

PubMed

Taghizadeh, Mostafa; Ghaffari, Ali; Najafi, Farid

2009-10-01

In this paper, the effect of pneumatic circuit design on the input-output behavior of PWM-driven servo-pneumatic systems is investigated and their control performances are improved using linear controllers instead of complex and costly nonlinear ones. Generally, servo-pneumatic systems are well known for their nonlinear behavior. However, PWM-driven servo-pneumatic systems have the advantage of flexibility in the design of pneumatic circuits which affects the input-output linearity of the whole system. A simple pneumatic circuit with only one fast switching valve is designed which leads to a quasi-linear input-output relation. The quasi-linear behavior of the proposed circuit is verified both experimentally and by simulations. Closed loop position control experiments are then carried out using linear P- and PD-controllers. Since the output position is noisy and cannot be directly differentiated, a Kalman filter is designed to estimate the velocity of the cylinder. Highly improved tracking performances are obtained using these linear controllers, compared to previous works with nonlinear controllers.

Test Bench for Coupling and Shielding Magnetic Fields

NASA Astrophysics Data System (ADS)

Jordan, J.; Esteve, V.; Dede, E.; Sanchis, E.; Maset, E.; Ferreres, A.; Ejea, J. B.; Cases, C.

2016-05-01

This paper describes a test bench for training purposes, which uses a magnetic field generator to couple this magnetic field to a victim circuit. It can be very useful to test for magnetic susceptibility as well. The magnetic field generator consists of a board, which generates a variable current that flows into a printed circuit board with spiral tracks (noise generator). The victim circuit consists of a coaxial cable concentric with the spiral tracks and its generated magnetic field. The coaxial cable is part of a circuit which conducts a signal produced by a signal generator and a resistive load. In the paper three cases are studied. First, the transmitted signal from the signal generator uses the central conductor of the coaxial cable and the shield is floating. Second, the shield is short circuited at its ends (and thus forming a loop). Third, when connecting the shield in series with the inner conductor and therefore having the current flowing into the coax via the inner conductor and returning via the shield.

Advanced Space Suit PLSS 2.0 Cooling Loop Evaluation and PLSS 2.5 Recommendations

NASA Technical Reports Server (NTRS)

Steele, John; Quinn, Greg; Campbell, Colin; Makinen, Janice; Watts, Carly; Westheimer, Dave

2016-01-01

From 2012 to 2015 The NASA/JSC AdvSS (Advanced Space Suit) PLSS (Primary Life Support Subsystem) team, with support from UTC Aerospace Systems, performed the build-up, packaging and testing of PLSS 2.0. A key aspect of that testing was the evaluation of the long-term health of the water cooling circuit and the interfacing components. Intermittent and end-of-test water, residue and hardware analyses provided valuable information on the status of the water cooling circuit, and the approaches that would be necessary to enhance water cooling circuit health in the future. The evaluated data has been consolidated, interpreted and woven into an action plan for the maintenance of water cooling circuit health for the planned FY (fiscal year) 2016 through FY 2018 PLSS 2.5 testing. This paper provides an overview of the PLSS 2.0 water cooling circuit findings and the associated steps to be taken in that regard for the PLSS 2.5 testing.

The base pairing RNA Spot 42 participates in a multi-output feedforward loop to help enact catabolite repression in Escherichia coli

PubMed Central

Beisel, Chase L.; Storz, Gisela

2011-01-01

SUMMARY Bacteria selectively consume some carbon sources over others through a regulatory mechanism termed catabolite repression. Here, we show that the base pairing RNA Spot 42 plays a broad role in catabolite repression in Escherichia coli by directly repressing genes involved in central and secondary metabolism, redox balancing, and the consumption of diverse non-preferred carbon sources. Many of the genes repressed by Spot 42 are transcriptionally activated by the global regulator CRP. Since CRP represses Spot 42, these regulators participate in a specific regulatory circuit called a multi-output feedforward loop. We found that this loop can reduce leaky expression of target genes in the presence of glucose and can maintain repression of target genes under changing nutrient conditions. Our results suggest that base pairing RNAs in feedforward loops can help shape the steady-state levels and dynamics of gene expression. PMID:21292161

Study of IEMP Effects on IC Operational Amplifier Circuits

DTIC Science & Technology

1975-12-10

plasma focus to study their IEMP responses with and without superposition of TREE responses. The 30-kJ plasma focus device produced photons primarily in the 8- to 100-keV range with pulse widths typically in the range of 10 to 15 nsec. Pulses of electrons were also deposited on the external leads of the operational amplifiers to determine the characteristic responses. These units were operated in circuits with closed-loop gains ranging from 5 to 100. During direct irradiation of the operational amplifiers, it was found that the IEMP responses (caused

Robust stability bounds for multi-delay networked control systems

NASA Astrophysics Data System (ADS)

Seitz, Timothy; Yedavalli, Rama K.; Behbahani, Alireza

2018-04-01

In this paper, the robust stability of a perturbed linear continuous-time system is examined when controlled using a sampled-data networked control system (NCS) framework. Three new robust stability bounds on the time-invariant perturbations to the original continuous-time plant matrix are presented guaranteeing stability for the corresponding discrete closed-loop augmented delay-free system (ADFS) with multiple time-varying sensor and actuator delays. The bounds are differentiated from previous work by accounting for the sampled-data nature of the NCS and for separate communication delays for each sensor and actuator, not a single delay. Therefore, this paper expands the knowledge base in multiple inputs multiple outputs (MIMO) sampled-data time delay systems. Bounds are presented for unstructured, semi-structured, and structured perturbations.

Transient-Switch-Signal Suppressor

NASA Technical Reports Server (NTRS)

Bozeman, Richard J., Jr.

1995-01-01

Circuit delays transmission of switch-opening or switch-closing signal until after preset suppression time. Used to prevent transmission of undesired momentary switch signal. Basic mode of operation simple. Beginning of switch signal initiates timing sequence. If switch signal persists after preset suppression time, circuit transmits switch signal to external circuitry. If switch signal no longer present after suppression time, switch signal deemed transient, and circuit does not pass signal on to external circuitry, as though no transient switch signal. Suppression time preset at value large enough to allow for damping of underlying pressure wave or other mechanical transient.

Software for a GPS-Reflection Remote-Sensing System

NASA Technical Reports Server (NTRS)

Lowe, Stephen

2003-01-01

A special-purpose software Global Positioning System (GPS) receiver designed for remote sensing with reflected GPS signals is described in Delay/Doppler-Mapping GPS-Reflection Remote-Sensing System (NPO-30385), which appears elsewhere in this issue of NASA Tech Briefs. The input accepted by this program comprises raw (open-loop) digitized GPS signals sampled at a rate of about 20 MHz. The program processes the data samples to perform the following functions: detection of signals; tracking of phases and delays; mapping of delay, Doppler, and delay/Doppler waveforms; dual-frequency processing; coherent integrations as short as 125 s; decoding of navigation messages; and precise time tagging of observable quantities. The software can perform these functions on all detectable satellite signals without dead time. Open-loop data collected over water, land, or ice and processed by this software can be further processed to extract geophysical information. Possible examples include mean sea height, wind speed and direction, and significant wave height (for observations over the ocean); bistatic-radar terrain images and measures of soil moisture and biomass (for observations over land); and estimates of ice age, thickness, and surface density (for observations over ice).

Tuning algorithms for fractional order internal model controllers for time delay processes

NASA Astrophysics Data System (ADS)

Muresan, Cristina I.; Dutta, Abhishek; Dulf, Eva H.; Pinar, Zehra; Maxim, Anca; Ionescu, Clara M.

2016-03-01

This paper presents two tuning algorithms for fractional-order internal model control (IMC) controllers for time delay processes. The two tuning algorithms are based on two specific closed-loop control configurations: the IMC control structure and the Smith predictor structure. In the latter, the equivalency between IMC and Smith predictor control structures is used to tune a fractional-order IMC controller as the primary controller of the Smith predictor structure. Fractional-order IMC controllers are designed in both cases in order to enhance the closed-loop performance and robustness of classical integer order IMC controllers. The tuning procedures are exemplified for both single-input-single-output as well as multivariable processes, described by first-order and second-order transfer functions with time delays. Different numerical examples are provided, including a general multivariable time delay process. Integer order IMC controllers are designed in each case, as well as fractional-order IMC controllers. The simulation results show that the proposed fractional-order IMC controller ensures an increased robustness to modelling uncertainties. Experimental results are also provided, for the design of a multivariable fractional-order IMC controller in a Smith predictor structure for a quadruple-tank system.

A Phase-Locked Loop Epilepsy Network Emulator.

PubMed

Watson, P D; Horecka, K M; Cohen, N J; Ratnam, R

2016-10-15

Most seizure forecasting employs statistical learning techniques that lack a representation of the network interactions that give rise to seizures. We present an epilepsy network emulator (ENE) that uses a network of interconnected phase-locked loops (PLLs) to model synchronous, circuit-level oscillations between electrocorticography (ECoG) electrodes. Using ECoG data from a canine-epilepsy model (Davis et al. 2011) and a physiological entropy measure (approximate entropy or ApEn, Pincus 1995), we demonstrate the entropy of the emulator phases increases dramatically during ictal periods across all ECoG recording sites and across all animals in the sample. Further, this increase precedes the observable voltage spikes that characterize seizure activity in the ECoG data. These results suggest that the ENE is sensitive to phase-domain information in the neural circuits measured by ECoG and that an increase in the entropy of this measure coincides with increasing likelihood of seizure activity. Understanding this unpredictable phase-domain electrical activity present in ECoG recordings may provide a target for seizure detection and feedback control.

Accidental degeneracy in k-space, geometrical phase, and the perturbation of π by spin-orbit interactions

NASA Astrophysics Data System (ADS)

Allen, Philip B.; Pickett, Warren E.

2018-06-01

Since closed lines of accidental electronic degeneracies were demonstrated to be possible, even frequent, by Herring in 1937, no further developments arose for eight decades. The earliest report of such a nodal loop in a real material - aluminum - is recounted and elaborated on. Nodal loop semimetals have become a focus of recent activity, with emphasis on other issues. Band degeneracies are, after all, the origin of topological phases in crystalline materials. Spin-orbit interaction lifts accidental band degeneracies, with the resulting spectrum being provided here. The geometric phase γ(C) = ± π for circuits C surrounding a line of such degeneracy cannot survive completely unchanged. The change depends on how the spin is fixed during adiabatic evolution. For spin fixed along the internal spin-orbit field, γ(C) decreases to zero as the circuit collapses around the line of lifted degeneracy. For spin fixed along a perpendicular axis, the conical intersection persists and γ(C) = ± π is unchanged.

Basal ganglia circuit loops, dopamine and motivation: A review and enquiry

PubMed Central

Ikemoto, Satoshi; Yang, Chen; Tan, Aaron

2015-01-01

Dopamine neurons located in the midbrain play a role in motivation that regulates approach behavior (approach motivation). In addition, activation and inactivation of dopamine neurons regulate mood and induce reward and aversion, respectively. Accumulating evidence suggests that such motivational role of dopamine neurons is not limited to those located in the ventral tegmental area, but also in the substantia nigra. The present paper reviews previous rodent work concerning dopamine’s role in approach motivation and the connectivity of dopamine neurons, and proposes two working models: One concerns the relationship between extracellular dopamine concentration and approach motivation. High, moderate and low concentrations of extracellular dopamine induce euphoric, seeking and aversive states, respectively. The other concerns circuit loops involving the cerebral cortex, basal ganglia, thalamus, epithalamus, and midbrain through which dopaminergic activity alters approach motivation. These models should help to generate hypothesis-driven research and provide insights for understanding altered states associated with drugs of abuse and affective disorders. PMID:25907747

About problematic peculiarities of Fault Tolerance digital regulation organization

NASA Astrophysics Data System (ADS)

Rakov, V. I.; Zakharova, O. V.

2018-05-01

The solution of problems concerning estimation of working capacity of regulation chains and possibilities of preventing situations of its violation in three directions are offered. The first direction is working out (creating) the methods of representing the regulation loop (circuit) by means of uniting (combining) diffuse components and forming algorithmic tooling for building predicates of serviceability assessment separately for the components and the for regulation loops (circuits, contours) in general. The second direction is creating methods of Fault Tolerance redundancy in the process of complex assessment of current values of control actions, closure errors and their regulated parameters. The third direction is creating methods of comparing the processes of alteration (change) of control actions, errors of closure and regulating parameters with their standard models or their surroundings. This direction allows one to develop methods and algorithmic tool means, aimed at preventing loss of serviceability and effectiveness of not only a separate digital regulator, but also the whole complex of Fault Tolerance regulation.

Electron emission controller with pulsed heating of filament

NASA Astrophysics Data System (ADS)

Durakiewicz, Tomasz

1996-11-01

A novel circuit has been invented for the versatile and safe stabilization of the electron emission current (Ie) produced by a hot filament in mass spectrometers or in ionization gauges. The voltage signal, which is directly proportional to Ie, is provided to the inverting input of a comparator, whereas the noninverting input is connected to the reference voltage. In addition to the commonly used negative feedback loop, a positive feedback loop was introduced by siting a resistor between the noninverting input and the output of the comparator, which results in a pulsation of the filament voltage. The pulses are rectangular, so that the power dissipated by the transistor in the filament power supply circuit is radically reduced. To refine the switching action of the transistor, the output of the comparator is connected through a capacitor to the transistor gate. A concise discussion of the phase shift between Ie, the filament temperature Tf, and the filament voltage Vf, including time constants for different modes of power dissipation, is included.

Effect of a Diagram on Primary Students' Understanding About Electric Circuits

NASA Astrophysics Data System (ADS)

Preston, Christine Margaret

2017-09-01

This article reports on the effect of using a diagram to develop primary students' conceptual understanding about electric circuits. Diagrammatic representations of electric circuits are used for teaching and assessment despite the absence of research on their pedagogical effectiveness with young learners. Individual interviews were used to closely analyse Years 3 and 5 (8-11-year-old) students' explanations about electric circuits. Data was collected from 20 students in the same school providing pre-, post- and delayed post-test dialogue. Students' thinking about electric circuits and changes in their explanations provide insights into the role of diagrams in understanding science concepts. Findings indicate that diagram interaction positively enhanced understanding, challenged non-scientific views and promoted scientific models of electric circuits. Differences in students' understanding about electric circuits were influenced by prior knowledge, meta-conceptual awareness and diagram conventions including a stylistic feature of the diagram used. A significant finding that students' conceptual models of electric circuits were energy rather than current based has implications for electricity instruction at the primary level.

Method and apparatus for transfer function simulator for testing complex systems

NASA Technical Reports Server (NTRS)

Kavaya, M. J. (Inventor)

1985-01-01

A method and apparatus for testing the operation of a complex stabilization circuit in a closed loop system is presented. The method is comprised of a programmed analog or digital computing system for implementing the transfer function of a load thereby providing a predictable load. The digital computing system employs a table stored in a microprocessor in which precomputed values of the load transfer function are stored for values of input signal from the stabilization circuit over the range of interest. This technique may be used not only for isolating faults in the stabilization circuit, but also for analyzing a fault in a faulty load by so varying parameters of the computing system as to simulate operation of the actual load with the fault.

TRIAC/SCR proportional control circuit

DOEpatents

Hughes, W.J.

1999-04-06

A power controller device is disclosed which uses a voltage-to-frequency converter in conjunction with a zero crossing detector to linearly and proportionally control AC power being supplied to a load. The output of the voltage-to frequency converter controls the ``reset`` input of a R-S flip flop, while an ``0`` crossing detector controls the ``set`` input. The output of the flip flop triggers a monostable multivibrator controlling the SCR or TRIAC firing circuit connected to the load. Logic gates prevent the direct triggering of the multivibrator in the rare instance where the ``reset`` and ``set`` inputs of the flip flop are in coincidence. The control circuit can be supplemented with a control loop, providing compensation for line voltage variations. 9 figs.

Design and validation of a high-voltage levitation circuit for electrostatic accelerometers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Li, G.; Wu, S. C.; Zhou, Z. B.

2013-12-15

A simple high-voltage circuit with a voltage range of 0 to 900 V and an open-loop bandwidth of 11 kHz is realized by using an operational amplifier and a MOSFET combination. The circuit is used for the levitation of a test mass of 71 g, suspended below the top-electrodes with a gap distance of 57 μm, so that the performance of an electrostatic accelerometer can be tested on the ground. The translation noise of the accelerometer, limited by seismic noise, is about 4 × 10{sup −8} m/s{sup 2}/Hz{sup 1/2} at 0.1 Hz, while the high-voltage coupling noise is one-order ofmore » magnitude lower.« less

Computation of magnetic suspension of maglev systems using dynamic circuit theory

NASA Technical Reports Server (NTRS)

He, J. L.; Rote, D. M.; Coffey, H. T.

1992-01-01

Dynamic circuit theory is applied to several magnetic suspensions associated with maglev systems. These suspension systems are the loop-shaped coil guideway, the figure-eight-shaped null-flux coil guideway, and the continuous sheet guideway. Mathematical models, which can be used for the development of computer codes, are provided for each of these suspension systems. The differences and similarities of the models in using dynamic circuit theory are discussed in the paper. The paper emphasizes the transient and dynamic analysis and computer simulation of maglev systems. In general, the method discussed here can be applied to many electrodynamic suspension system design concepts. It is also suited for the computation of the performance of maglev propulsion systems. Numerical examples are presented in the paper.

Determining distance to lightning strokes from a single station

NASA Technical Reports Server (NTRS)

Ruhnke, L. H. (Inventor)

1973-01-01

Apparatus is described for determining the distance to lightning strokes from a single station. The apparatus includes a first loop antenna system for sensing the magnetic field produced by the lightning which is filtered, square rooted, and fed into a peak voltage holding circuit. A second antenna is provided for sensing the electric field produced by the lightning which is fed into a filter, an absolute value meter, and to a peak voltage holding circuit. A multivibrator gates the magnetic and electric signals through the peak holding circuits to a ratio meter which produces a signal corresponding to the ratio between the magnetic component and the electric component. The amplitude of this signal is proportional to the distance from the apparatus to the lightning stroke.

Effects of time delay and pitch control sensitivity in the flared landing

NASA Technical Reports Server (NTRS)

Berthe, C. J.; Chalk, C. R.; Wingarten, N. C.; Grantham, W.

1986-01-01

Between December 1985 and January 1986, a flared landing program was conducted, using the USAF Total In-Flight simulator airplane, to examine time delay effects in a formal manner. Results show that as pitch sensitivity is increased, tolerance to time delay decreases. With the proper selection of pitch sensitivity, Level I performance was maintained with time delays ranging from 150 milliseconds to greater than 300 milliseconds. With higher sensitivity, configurations with Level I performance at 150 milliseconds degraded to level 2 at 200 milliseconds. When metrics of time delay and pitch sensitivity effects are applied to enhance previously developed predictive criteria, the result is an improved prediction technique which accounts for significant closed loop items.

Fluctuation relations and Maxwell's demon in a circuit QED setup

NASA Astrophysics Data System (ADS)

Nakamura, Yasunobu

The recent progress in information thermodynamics has resolved the paradox of Maxwell's demon and clarified the relationship between the information and the entropy. Its extension to quantum mechanical systems has also attracted much interest, and experimental demonstrations are awaited. Circuit QED systems offer the following tools suitable for investigating the properties of a quantum system coupled with a controlled environment: (i) a well-controlled qubit with a long coherence time, (ii) dispersive readout allowing high-fidelity quantum nondemolition measurement, and (iii) fast feedback control. We first apply the so-called two-measurement protocol (TMP) to a superconducting transmon qubit in a microwave cavity and study how the decoherence affects the nonequilibrium thermodynamic relations. Next, we implement Maxwell's demon in the circuit QED system by introducing a feedback loop and confirm the fluctuation relation including the effect of the information obtained in the feedback process. These results constitute a first step towards quantum thermodynamics in circuit QED systems.

A lumped parameter mathematical model for simulation of subsonic wind tunnels

NASA Technical Reports Server (NTRS)

Krosel, S. M.; Cole, G. L.; Bruton, W. M.; Szuch, J. R.

1986-01-01

Equations for a lumped parameter mathematical model of a subsonic wind tunnel circuit are presented. The equation state variables are internal energy, density, and mass flow rate. The circuit model is structured to allow for integration and analysis of tunnel subsystem models which provide functions such as control of altitude pressure and temperature. Thus the model provides a useful tool for investigating the transient behavior of the tunnel and control requirements. The model was applied to the proposed NASA Lewis Altitude Wind Tunnel (AWT) circuit and included transfer function representations of the tunnel supply/exhaust air and refrigeration subsystems. Both steady state and frequency response data are presented for the circuit model indicating the type of results and accuracy that can be expected from the model. Transient data for closed loop control of the tunnel and its subsystems are also presented, demonstrating the model's use as a control analysis tool.

Observation of the Topological Change Associated with the Dynamical Monodromy

NASA Astrophysics Data System (ADS)

Salmon, Daniel; Nerem, Matthew; Aubin, Seth; Delos, John

2017-04-01

Classical mechanics is an old theory and new phenomena do not often appear. A recently predicted phenomenon is called ``Dynamical Monodromy.'' Monodromy is the study of the behavior of a system as it evolves ``once around a closed circuit''. Systems that do not return to their original state after forming a closed circuit in some space are said to exhibit ``nontrivial monodromy.'' One such system is a collection of non-interacting particles moving in a ``champagne bottle'' potential. A loop of trajectories of this system exhibits a topological change when each of the particles traverse a monodromy circuit in Energy-Angular Momentum space (any closed path that encloses the singular point at the origin). This system has been realized using a rigid spherical pendulum, with a permanent magnet at its end. Magnetic fields generated by coils are used to create the champagne-bottle potential, as well as drive the pendulum through the monodromy circuit.

The Drosophila Circadian Pacemaker Circuit: Pas de Deux or Tarantella?

PubMed Central

Sheeba, Vasu; Kaneko, Maki; Sharma, Vijay Kumar; Holmes, Todd C.

2008-01-01

Molecular genetic analysis of the fruit fly Drosophila melanogaster has revolutionized our understanding of the transcription/translation loop mechanisms underlying the circadian molecular oscillator. More recently, Drosophila has been used to understand how different neuronal groups within the circadian pacemaker circuit interact to regulate the overall behavior of the fly in response to daily cyclic environmental cues as well as seasonal changes. Our present understanding of circadian timekeeping at the molecular and circuit level is discussed with a critical evaluation of the strengths and weaknesses of present models. Two models for circadian neural circuits are compared: one that posits that two anatomically distinct oscillators control the synchronization to the two major daily morning and evening transitions, versus a distributed network model that posits that many cell-autonomous oscillators are coordinated in a complex fashion and respond via plastic mechanisms to changes in environmental cues. PMID:18307108

Solid State Research

DTIC Science & Technology

1985-08-15

Hz. The high-speed performance is consis- tent with the low stage delay observed in the ring-oscillator measurements , and the low - frequency ...Phase-Locked Loop 41 5-10 Phase-Locked-Loop Output Spectrum . Note that a 10-kHz Measure - ment Bandwidth Is Used. 42 5-11 Phase Error Response to an...the niobium. Reflections of bulk acoustic waves from optically generated holograms in Fe-doped LiNb03 have been observed and measured . Holographic

Effects of channel tap spacing on delay-lock tracking

NASA Astrophysics Data System (ADS)

Dana, Roger A.; Milner, Brian R.; Bogusch, Robert L.

1995-12-01

High fidelity simulations of communication links operating through frequency selective fading channels require both accurate channel models and faithful reproduction of the received signal. In modern radio receivers, processing beyond the analog-to-digital converter (A/D) is done digitally, so a high fidelity simulation is actually an emulation of this digital signal processing. The 'simulation' occurs in constructing the output of the A/D. One approach to constructing the A/D output is to convolve the channel impulse response function with the combined impulse response of the transmitted modulation and the A/D. For both link simulations and hardware channel simulators, the channel impulse response function is then generated with a finite number of samples per chip, and the convolution is implemented in a tapped delay line. In this paper we discuss the effects of the channel model tap spacing on the performance of delay locked loops (DLLs) in both direct sequence and frequency hopped spread spectrum systems. A frequency selective fading channel is considered, and the channel impulse response function is constructed with an integer number of taps per modulation symbol or chip. The tracking loop time delay is computed theoretically for this tapped delay line channel model and is compared to the results of high fidelity simulations of actual DLLs. A surprising result is obtained. The performance of the DLL depends strongly on the number of taps per chip. As this number increases the DLL delay approaches the theoretical limit.

Analysis and design of a 3rd order velocity-controlled closed-loop for MEMS vibratory gyroscopes.

PubMed

Wu, Huan-ming; Yang, Hai-gang; Yin, Tao; Jiao, Ji-wei

2013-09-18

The time-average method currently available is limited to analyzing the specific performance of the automatic gain control-proportional and integral (AGC-PI) based velocity-controlled closed-loop in a micro-electro-mechanical systems (MEMS) vibratory gyroscope, since it is hard to solve nonlinear functions in the time domain when the control loop reaches to 3rd order. In this paper, we propose a linearization design approach to overcome this limitation by establishing a 3rd order linear model of the control loop and transferring the analysis to the frequency domain. Order reduction is applied on the built linear model's transfer function by constructing a zero-pole doublet, and therefore mathematical expression of each control loop's performance specification is obtained. Then an optimization methodology is summarized, which reveals that a robust, stable and swift control loop can be achieved by carefully selecting the system parameters following a priority order. Closed-loop drive circuits are designed and implemented using 0.35 μm complementary metal oxide semiconductor (CMOS) process, and experiments carried out on a gyroscope prototype verify the optimization methodology that an optimized stability of the control loop can be achieved by constructing the zero-pole doublet, and disturbance rejection capability (D.R.C) of the control loop can be improved by increasing the integral term.

Efficient high-performance ultrasound beamforming using oversampling

NASA Astrophysics Data System (ADS)

Freeman, Steven R.; Quick, Marshall K.; Morin, Marc A.; Anderson, R. C.; Desilets, Charles S.; Linnenbrink, Thomas E.; O'Donnell, Matthew

1998-05-01

High-performance and efficient beamforming circuitry is very important in large channel count clinical ultrasound systems. Current state-of-the-art digital systems using multi-bit analog to digital converters (A/Ds) have matured to provide exquisite image quality with moderate levels of integration. A simplified oversampling beamforming architecture has been proposed that may a low integration of delta-sigma A/Ds onto the same chip as digital delay and processing circuitry to form a monolithic ultrasound beamformer. Such a beamformer may enable low-power handheld scanners for high-end systems with very large channel count arrays. This paper presents an oversampling beamformer architecture that generates high-quality images using very simple; digitization, delay, and summing circuits. Additional performance may be obtained with this oversampled system for narrow bandwidth excitations by mixing the RF signal down in frequency to a range where the electronic signal to nose ratio of the delta-sigma A/D is optimized. An oversampled transmit beamformer uses the same delay circuits as receive and eliminates the need for separate transmit function generators.

A mixed-signal implementation of a polychronous spiking neural network with delay adaptation

PubMed Central

Wang, Runchun M.; Hamilton, Tara J.; Tapson, Jonathan C.; van Schaik, André

2014-01-01

We present a mixed-signal implementation of a re-configurable polychronous spiking neural network capable of storing and recalling spatio-temporal patterns. The proposed neural network contains one neuron array and one axon array. Spike Timing Dependent Delay Plasticity is used to fine-tune delays and add dynamics to the network. In our mixed-signal implementation, the neurons and axons have been implemented as both analog and digital circuits. The system thus consists of one FPGA, containing the digital neuron array and the digital axon array, and one analog IC containing the analog neuron array and the analog axon array. The system can be easily configured to use different combinations of each. We present and discuss the experimental results of all combinations of the analog and digital axon arrays and the analog and digital neuron arrays. The test results show that the proposed neural network is capable of successfully recalling more than 85% of stored patterns using both analog and digital circuits. PMID:24672422

A mixed-signal implementation of a polychronous spiking neural network with delay adaptation.

PubMed

Wang, Runchun M; Hamilton, Tara J; Tapson, Jonathan C; van Schaik, André

2014-01-01

We present a mixed-signal implementation of a re-configurable polychronous spiking neural network capable of storing and recalling spatio-temporal patterns. The proposed neural network contains one neuron array and one axon array. Spike Timing Dependent Delay Plasticity is used to fine-tune delays and add dynamics to the network. In our mixed-signal implementation, the neurons and axons have been implemented as both analog and digital circuits. The system thus consists of one FPGA, containing the digital neuron array and the digital axon array, and one analog IC containing the analog neuron array and the analog axon array. The system can be easily configured to use different combinations of each. We present and discuss the experimental results of all combinations of the analog and digital axon arrays and the analog and digital neuron arrays. The test results show that the proposed neural network is capable of successfully recalling more than 85% of stored patterns using both analog and digital circuits.

7 CFR 1755.405 - Voiceband data transmission measurements.

Code of Federal Regulations, 2010 CFR

2010-01-01

... 7 Agriculture 11 2010-01-01 2010-01-01 false Voiceband data transmission measurements. 1755.405..., AND STANDARD CONTRACT FORMS § 1755.405 Voiceband data transmission measurements. (a) The data... nonloaded subscriber loop circuits for data modem transmission. (b) Signal-to-C notched noise (S/CNN...

Retaining the equilibrium point hypothesis as an abstract description of the neuromuscular system.

PubMed

Tresilian, J R

1999-01-01

The lambda version of the equilibrium point (EP) hypothesis for motor control is examined in light of recent criticisms of its various instantiations. Four important assumptions that have formed the basis for recent criticism are analyzed: First, the assumption that intact muscles possess invariant force-length characteristics (ICs). Second, that these ICs are of the same form in agonist-antagonist pairs. Third, that muscle control is monoparametric and that the control parameter, lambda, can be given a neurophysiological interpretation. Fourth, that reflex loop time delays and the known, asymmetric, nonlinear mechanical properties of muscles can be ignored. Mechanical and neurophysiological investigations of the neuromuscular system suggests that none of these assumptions is likely to be correct. This has been taken to mean that the EP hypothesis is oversimplified and a new approach is needed. It is argued that such an approach can be provided without rejecting the EP hypothesis, rather to regard it as an input-output description of muscle and associated segmental circuits. The operation of the segmental circuitry can be interpreted as having the function, at least in part, of compensating for a variety of nonlinearities and asymmetries such that the overall system implements the lambda-EP model equations.

Digital phase-lock loop

NASA Technical Reports Server (NTRS)

Thomas, Jr., Jess B. (Inventor)

1991-01-01

An improved digital phase lock loop incorporates several distinctive features that attain better performance at high loop gain and better phase accuracy. These features include: phase feedback to a number-controlled oscillator in addition to phase rate; analytical tracking of phase (both integer and fractional cycles); an amplitude-insensitive phase extractor; a more accurate method for extracting measured phase; a method for changing loop gain during a track without loss of lock; and a method for avoiding loss of sampled data during computation delay, while maintaining excellent tracking performance. The advantages of using phase and phase-rate feedback are demonstrated by comparing performance with that of rate-only feedback. Extraction of phase by the method of modeling provides accurate phase measurements even when the number-controlled oscillator phase is discontinuously updated.

Carotid chemoreceptors tune breathing via multipath routing: reticular chain and loop operations supported by parallel spike train correlations.

PubMed

Morris, Kendall F; Nuding, Sarah C; Segers, Lauren S; Iceman, Kimberly E; O'Connor, Russell; Dean, Jay B; Ott, Mackenzie M; Alencar, Pierina A; Shuman, Dale; Horton, Kofi-Kermit; Taylor-Clark, Thomas E; Bolser, Donald C; Lindsey, Bruce G

2018-02-01

We tested the hypothesis that carotid chemoreceptors tune breathing through parallel circuit paths that target distinct elements of an inspiratory neuron chain in the ventral respiratory column (VRC). Microelectrode arrays were used to monitor neuronal spike trains simultaneously in the VRC, peri-nucleus tractus solitarius (p-NTS)-medial medulla, the dorsal parafacial region of the lateral tegmental field (FTL-pF), and medullary raphe nuclei together with phrenic nerve activity during selective stimulation of carotid chemoreceptors or transient hypoxia in 19 decerebrate, neuromuscularly blocked, and artificially ventilated cats. Of 994 neurons tested, 56% had a significant change in firing rate. A total of 33,422 cell pairs were evaluated for signs of functional interaction; 63% of chemoresponsive neurons were elements of at least one pair with correlational signatures indicative of paucisynaptic relationships. We detected evidence for postinspiratory neuron inhibition of rostral VRC I-Driver (pre-Bötzinger) neurons, an interaction predicted to modulate breathing frequency, and for reciprocal excitation between chemoresponsive p-NTS neurons and more downstream VRC inspiratory neurons for control of breathing depth. Chemoresponsive pericolumnar tonic expiratory neurons, proposed to amplify inspiratory drive by disinhibition, were correlationally linked to afferent and efferent "chains" of chemoresponsive neurons extending to all monitored regions. The chains included coordinated clusters of chemoresponsive FTL-pF neurons with functional links to widespread medullary sites involved in the control of breathing. The results support long-standing concepts on brain stem network architecture and a circuit model for peripheral chemoreceptor modulation of breathing with multiple circuit loops and chains tuned by tegmental field neurons with quasi-periodic discharge patterns. NEW & NOTEWORTHY We tested the long-standing hypothesis that carotid chemoreceptors tune the frequency and depth of breathing through parallel circuit operations targeting the ventral respiratory column. Responses to stimulation of the chemoreceptors and identified functional connectivity support differential tuning of inspiratory neuron burst duration and firing rate and a model of brain stem network architecture incorporating tonic expiratory "hub" neurons regulated by convergent neuronal chains and loops through rostral lateral tegmental field neurons with quasi-periodic discharge patterns.

Circadian pacemaking in cells and circuits of the suprachiasmatic nucleus.

PubMed

Hastings, M H; Brancaccio, M; Maywood, E S

2014-01-01

The suprachiasmatic nucleus (SCN) of the hypothalamus is the principal circadian pacemaker of the brain. It co-ordinates the daily rhythms of sleep and wakefulness, as well as physiology and behaviour, that set the tempo to our lives. Disturbance of this daily pattern, most acutely with jet-lag but more insidiously with rotational shift-work, can have severely deleterious effects for mental function and long-term health. The present review considers recent developments in our understanding of the properties of the SCN that make it a robust circadian time-keeper. It first focuses on the intracellular transcriptional/ translational feedback loops (TTFL) that constitute the cellular clockwork of the SCN neurone. Daily timing by these loops pivots around the negative regulation of the Period (Per) and Cryptochrome (Cry) genes by their protein products. The period of the circadian cycle is set by the relative stability of Per and Cry proteins, and this can be controlled by both genetic and pharmacological interventions. It then considers the function of these feedback loops in the context of cytosolic signalling by cAMP and intracellular calcium ([Ca(2+) ]i ), which are both outputs from, and inputs to, the TTFL, as well as the critical role of vasoactive intestinal peptide (VIP) signalling in synchronising cellular clocks across the SCN. Synchronisation by VIP in the SCN is paracrine, operating over an unconventionally long time frame (i.e. 24 h) and wide spatial domain, mediated via the cytosolic pathways upstream of the TTFL. Finally, we show how intersectional pharmacogenetics can be used to control G-protein-coupled signalling in individual SCN neurones, and how manipulation of Gq/[Ca(2+) ]i -signalling in VIP neurones can re-programme the circuit-level encoding of circadian time. Circadian pacemaking in the SCN therefore provides an unrivalled context in which to understand how a complex, adaptive behaviour can be organised by the dynamic activity of a relatively few gene products, operating in a clearly defined neuronal circuit, with both cell-autonomous and emergent, circuit-level properties. © 2014 The Authors. Journal of Neuroendocrinology published by John Wiley & Sons Ltd on behalf of The British Society for Neuroendocrinology.

NSTX Electrical Power Systems

DOE Office of Scientific and Technical Information (OSTI.GOV)

A. Ilic; E. Baker; R. Hatcher

The National Spherical Torus Experiment (NSTX) has been designed and installed in the existing facilities at Princeton Plasma Physic Laboratory (PPPL). Most of the hardware, plant facilities, auxiliary sub-systems, and power systems originally used for the Tokamak Fusion Test Reactor (TFTR) have been used with suitable modifications to reflect NSTX needs. The design of the NSTX electrical power system was tailored to suit the available infrastructure and electrical equipment on site. Components were analyzed to verify their suitability for use in NSTX. The total number of circuits and the location of the NSTX device drove the major changes in themore » Power system hardware. The NSTX has eleven (11) circuits to be fed as compared to the basic three power loops for TFTR. This required changes in cabling to insure that each cable tray system has the positive and negative leg of cables in the same tray. Also additional power cabling had to be installed to the new location. The hardware had to b e modified to address the need for eleven power loops. Power converters had to be reconnected and controlled in anti-parallel mode for the Ohmic heating and two of the Poloidal Field circuits. The circuit for the Coaxial Helicity Injection (CHI) System had to be carefully developed to meet this special application. Additional Protection devices were designed and installed for the magnet coils and the CHI. The thrust was to making the changes in the most cost-effective manner without compromising technical requirements. This paper describes the changes and addition to the Electrical Power System components for the NSTX magnet systems.« less

Logarithmic and power law input-output relations in sensory systems with fold-change detection.

PubMed

Adler, Miri; Mayo, Avi; Alon, Uri

2014-08-01

Two central biophysical laws describe sensory responses to input signals. One is a logarithmic relationship between input and output, and the other is a power law relationship. These laws are sometimes called the Weber-Fechner law and the Stevens power law, respectively. The two laws are found in a wide variety of human sensory systems including hearing, vision, taste, and weight perception; they also occur in the responses of cells to stimuli. However the mechanistic origin of these laws is not fully understood. To address this, we consider a class of biological circuits exhibiting a property called fold-change detection (FCD). In these circuits the response dynamics depend only on the relative change in input signal and not its absolute level, a property which applies to many physiological and cellular sensory systems. We show analytically that by changing a single parameter in the FCD circuits, both logarithmic and power-law relationships emerge; these laws are modified versions of the Weber-Fechner and Stevens laws. The parameter that determines which law is found is the steepness (effective Hill coefficient) of the effect of the internal variable on the output. This finding applies to major circuit architectures found in biological systems, including the incoherent feed-forward loop and nonlinear integral feedback loops. Therefore, if one measures the response to different fold changes in input signal and observes a logarithmic or power law, the present theory can be used to rule out certain FCD mechanisms, and to predict their cooperativity parameter. We demonstrate this approach using data from eukaryotic chemotaxis signaling.

Coordinated three-dimensional motion of the head and torso by dynamic neural networks.

PubMed

Kim, J; Hemami, H

1998-01-01

The problem of trajectory tracking control of a three dimensional (3D) model of the human upper torso and head is considered. The torso and the head are modeled as two rigid bodies connected at one point, and the Newton-Euler method is used to derive the nonlinear differential equations that govern the motion of the system. The two-link system is driven by six pairs of muscle like actuators that possess physiologically inspired alpha like and gamma like inputs, and spindle like and Golgi tendon organ like outputs. These outputs are utilized as reflex feedback for stability and stiffness control, in a long loop feedback for the purpose of estimating the state of the system (somesthesis), and as part of the input to the controller. Ideal delays of different duration are included in the feedforward and feedback paths of the system to emulate such delays encountered in physiological systems. Dynamical neural networks are trained to learn effective control of the desired maneuvers of the system. The feasibility of the controller is demonstrated by computer simulation of the successful execution of the desired maneuvers. This work demonstrates the capabilities of neural circuits in controlling highly nonlinear systems with multidelays in their feedforward and feedback paths. The ultimate long range goal of this research is toward understanding the working of the central nervous system in controlling movement. It is an interdisciplinary effort relying on mechanics, biomechanics, neuroscience, system theory, physiology and anatomy, and its short range relevance to rehabilitation must be noted.

Compensating Unknown Time-Varying Delay in Opto-Electronic Platform Tracking Servo System.

PubMed

Xie, Ruihong; Zhang, Tao; Li, Jiaquan; Dai, Ming

2017-05-09

This paper investigates the problem of compensating miss-distance delay in opto-electronic platform tracking servo system. According to the characteristic of LOS (light-of-sight) motion, we setup the Markovian process model and compensate this unknown time-varying delay by feed-forward forecasting controller based on robust H∞ control. Finally, simulation based on double closed-loop PI (Proportion Integration) control system indicates that the proposed method is effective for compensating unknown time-varying delay. Tracking experiments on the opto-electronic platform indicate that RMS (root-mean-square) error is 1.253 mrad when tracking 10° 0.2 Hz signal.

New Predictive Filters for Compensating the Transport Delay on a Flight Simulator

NASA Technical Reports Server (NTRS)

Guo, Liwen; Cardullo, Frank M.; Houck, Jacob A.; Kelly, Lon C.; Wolters, Thomas E.

2004-01-01

The problems of transport delay in a flight simulator, such as its sources and effects, are reviewed. Then their effects on a pilot-in-the-loop control system are investigated with simulations. Three current prominent delay compensators the lead/lag filter, McFarland filter, and the Sobiski/Cardullo filter were analyzed and compared. This paper introduces two novel delay compensation techniques an adaptive predictor using the Kalman estimator and a state space predictive filter using a reference aerodynamic model. Applications of these two new compensators on recorded data from the NASA Langley Research Center Visual Motion Simulator show that they achieve better compensation over the current ones.

SARDA HITL Simulations: System Performance Results

NASA Technical Reports Server (NTRS)

Gupta, Gautam

2012-01-01

This presentation gives an overview of the 2012 SARDA human-in-the-loop simulation, and presents a summary of system performance results from the simulation, including delay, throughput and fuel consumption

A flow-control mechanism for distributed systems

NASA Technical Reports Server (NTRS)

Maitan, J.

1991-01-01

A new approach to the rate-based flow control in store-and-forward networks is evaluated. Existing methods display oscillations in the presence of transport delays. The proposed scheme is based on the explicit use of an embedded dynamic model of a store-and-forward buffer in a controller's feedback loop. It is shown that the use of the model eliminates the oscillations caused by the transport delays. The paper presents simulation examples and assesses the applicability of the scheme in the new generation of high-speed photonic networks where transport delays must be considered.

Recirculating cross-correlation detector

DOEpatents

Andrews, W.H. Jr.; Roberts, M.J.

1985-01-18

A digital cross-correlation detector is provided in which two time-varying signals are correlated by repetitively comparing data samples stored in digital form to detect correlation between the two signals. The signals are sampled at a selected rate converted to digital form, and stored in separate locations in separate memories. When the memories are filled, the data samples from each memory are first fed word-by-word through a multiplier and summing circuit and each result is compared to the last in a peak memory circuit and if larger than the last is retained in the peak memory. Then the address line to leading signal memory is offset by one byte to affect one sample period delay of a known amount in that memory and the data in the two memories are then multiplied word-by-word once again and summed. If a new result is larger than a former sum, it is saved in the peak memory together with the time delay. The recirculating process continues with the address of the one memory being offset one additional byte each cycle until the address is shifted through the length of the memory. The correlation between the two signals is indicated by the peak signal stored in the peak memory together with the delay time at which the peak occurred. The circuit is faster and considerably less expensive than comparable accuracy correlation detectors.

47 CFR 36.621 - Study area total unseparated loop cost.

Code of Federal Regulations, 2011 CFR

2011-10-01

... investment and Exchange Line CO Circuit Equipment Category 4.13 investment. This amount is calculated by deducting the accumulated depreciation and noncurrent deferred Federal income taxes attributable to C&WF...) Maintenance expense attributable to C&WF subcategory 1.3 investment, and CO Category 4.13 investment as...

47 CFR 36.621 - Study area total unseparated loop cost.

Code of Federal Regulations, 2012 CFR

2012-10-01

... investment and Exchange Line CO Circuit Equipment Category 4.13 investment. This amount is calculated by deducting the accumulated depreciation and noncurrent deferred Federal income taxes attributable to C&WF...) Maintenance expense attributable to C&WF subcategory 1.3 investment, and CO Category 4.13 investment as...

47 CFR 36.621 - Study area total unseparated loop cost.

Code of Federal Regulations, 2013 CFR

2013-10-01

... investment and Exchange Line CO Circuit Equipment Category 4.13 investment. This amount is calculated by deducting the accumulated depreciation and noncurrent deferred Federal income taxes attributable to C&WF...) Maintenance expense attributable to C&WF subcategory 1.3 investment, and CO Category 4.13 investment as...

47 CFR 54.1308 - Study Area Total Unseparated Loop Cost.

Code of Federal Regulations, 2014 CFR

2014-10-01

... C&WF subcategory 1.3 investment and Exchange Line CO Circuit Equipment Category 4.13 investment. This amount is calculated by deducting the accumulated depreciation and noncurrent deferred Federal... investment as reported in § 54.1305(c). (3) Maintenance expense attributable to C&WF Subcategory 1.3...

Alternating-Current Motor Drive for Electric Vehicles

NASA Technical Reports Server (NTRS)

Krauthamer, S.; Rippel, W. E.

1982-01-01

New electric drive controls speed of a polyphase as motor by varying frequency of inverter output. Closed-loop current-sensing circuit automatically adjusts frequency of voltage-controlled oscillator that controls inverter frequency, to limit starting and accelerating surges. Efficient inverter and ac motor would give electric vehicles extra miles per battery charge.

Self-Paced Physics, Segments 28-31.

ERIC Educational Resources Information Center

New York Inst. of Tech., Old Westbury.

Four study segments of the Self-Paced Physics Course materials are presented in this sixth problems and solutions book used as a part of student course work. The subject matter is related to electric currents, current densities, resistances, Ohm's law, voltages, Joule heating, electromotive forces, single loop circuits, series and parallel…

Characterization, Sources and Sinks of Colored Detrital Matter in the Ocean

DTIC Science & Technology

1999-09-30

herbivores we have studied to date, i.e., diverse protozoans, the copepod Calanus pacificus, the euphausid Euphausia sp. and salps . Results of...significantly to export fluxes in this environment. It is likely that the microbial loop is ’short-circuited’ in this environment by salps . Tests with