An integrated framework for high level design of high performance signal processing circuits on FPGAs

NASA Astrophysics Data System (ADS)

Benkrid, K.; Belkacemi, S.; Sukhsawas, S.

2005-06-01

This paper proposes an integrated framework for the high level design of high performance signal processing algorithms' implementations on FPGAs. The framework emerged from a constant need to rapidly implement increasingly complicated algorithms on FPGAs while maintaining the high performance needed in many real time digital signal processing applications. This is particularly important for application developers who often rely on iterative and interactive development methodologies. The central idea behind the proposed framework is to dynamically integrate high performance structural hardware description languages with higher level hardware languages in other to help satisfy the dual requirement of high level design and high performance implementation. The paper illustrates this by integrating two environments: Celoxica's Handel-C language, and HIDE, a structural hardware environment developed at the Queen's University of Belfast. On the one hand, Handel-C has been proven to be very useful in the rapid design and prototyping of FPGA circuits, especially control intensive ones. On the other hand, HIDE, has been used extensively, and successfully, in the generation of highly optimised parameterisable FPGA cores. In this paper, this is illustrated in the construction of a scalable and fully parameterisable core for image algebra's five core neighbourhood operations, where fully floorplanned efficient FPGA configurations, in the form of EDIF netlists, are generated automatically for instances of the core. In the proposed combined framework, highly optimised data paths are invoked dynamically from within Handel-C, and are synthesized using HIDE. Although the idea might seem simple prima facie, it could have serious implications on the design of future generations of hardware description languages.

Toward Evolvable Hardware Chips: Experiments with a Programmable Transistor Array

NASA Technical Reports Server (NTRS)

Stoica, Adrian

1998-01-01

Evolvable Hardware is reconfigurable hardware that self-configures under the control of an evolutionary algorithm. We search for a hardware configuration can be performed using software models or, faster and more accurate, directly in reconfigurable hardware. Several experiments have demonstrated the possibility to automatically synthesize both digital and analog circuits. The paper introduces an approach to automated synthesis of CMOS circuits, based on evolution on a Programmable Transistor Array (PTA). The approach is illustrated with a software experiment showing evolutionary synthesis of a circuit with a desired DC characteristic. A hardware implementation of a test PTA chip is then described, and the same evolutionary experiment is performed on the chip demonstrating circuit synthesis/self-configuration directly in hardware.

Design and Implementation of a Motor Incremental Shaft Encoder

DTIC Science & Technology

2008-09-01

SDC Student Design Center VHDL Verilog Hardware Description Language VSC Voltage Source Converters ZCE Zero Crossing Event xiii EXECUTIVE...student to make accurate predictions of voltage source converters ( VSC ) behavior via software simulation; these simulated results could also be... VSC ), and several other off-the-shelf components, a circuit board interface between FPGA and the power source, and a desktop computer [1]. Now, the

FPGA Boot Loader and Scrubber

NASA Technical Reports Server (NTRS)

Wade, Randall S.; Jones, Bailey

2009-01-01

A computer program loads configuration code into a Xilinx field-programmable gate array (FPGA), reads back and verifies that code, reloads the code if an error is detected, and monitors the performance of the FPGA for errors in the presence of radiation. The program consists mainly of a set of VHDL files (wherein "VHDL" signifies "VHSIC Hardware Description Language" and "VHSIC" signifies "very-high-speed integrated circuit").

Formal development of a clock synchronization circuit

NASA Technical Reports Server (NTRS)

Miner, Paul S.

1995-01-01

This talk presents the latest stage in formal development of a fault-tolerant clock synchronization circuit. The development spans from a high level specification of the required properties to a circuit realizing the core function of the system. An abstract description of an algorithm has been verified to satisfy the high-level properties using the mechanical verification system EHDM. This abstract description is recast as a behavioral specification input to the Digital Design Derivation system (DDD) developed at Indiana University. DDD provides a formal design algebra for developing correct digital hardware. Using DDD as the principle design environment, a core circuit implementing the clock synchronization algorithm was developed. The design process consisted of standard DDD transformations augmented with an ad hoc refinement justified using the Prototype Verification System (PVS) from SRI International. Subsequent to the above development, Wilfredo Torres-Pomales discovered an area-efficient realization of the same function. Establishing correctness of this optimization requires reasoning in arithmetic, so a general verification is outside the domain of both DDD transformations and model-checking techniques. DDD represents digital hardware by systems of mutually recursive stream equations. A collection of PVS theories was developed to aid in reasoning about DDD-style streams. These theories include a combinator for defining streams that satisfy stream equations, and a means for proving stream equivalence by exhibiting a stream bisimulation. DDD was used to isolate the sub-system involved in Torres-Pomales' optimization. The equivalence between the original design and the optimized verified was verified in PVS by exhibiting a suitable bisimulation. The verification depended upon type constraints on the input streams and made extensive use of the PVS type system. The dependent types in PVS provided a useful mechanism for defining an appropriate bisimulation.

Engineering studies of vectorcardiographs in blood pressure measuring systems, appendix 1

NASA Technical Reports Server (NTRS)

Mark, R. G.

1975-01-01

A small, portable, relatively inexpensive computer system was developed for on-line use in clinical or laboratory situations. The system features an integrated hardware-software package that permits use of all peripherals, such as analog-to-digital converter, oscilloscope, plotter, digital bus, with an interpreter constructed around the BASIC programming language. The system is conceptually similar to the LINC system developed in 1962, but is more compact and powerful due to intervening advances in integrated circuit technology. A description of the hardware of the system was given. A reference manual, user manual, and programming guides were also presented. Finally, a stereo display system for vectorcardiograms was described.

Hardware Prototyping of Neural Network based Fetal Electrocardiogram Extraction

NASA Astrophysics Data System (ADS)

Hasan, M. A.; Reaz, M. B. I.

2012-01-01

The aim of this paper is to model the algorithm for Fetal ECG (FECG) extraction from composite abdominal ECG (AECG) using VHDL (Very High Speed Integrated Circuit Hardware Description Language) for FPGA (Field Programmable Gate Array) implementation. Artificial Neural Network that provides efficient and effective ways of separating FECG signal from composite AECG signal has been designed. The proposed method gives an accuracy of 93.7% for R-peak detection in FHR monitoring. The designed VHDL model is synthesized and fitted into Altera's Stratix II EP2S15F484C3 using the Quartus II version 8.0 Web Edition for FPGA implementation.

VHDL Descriptions for the FPGA Implementation of PWL-Function-Based Multi-Scroll Chaotic Oscillators

PubMed Central

2016-01-01

Nowadays, chaos generators are an attractive field for research and the challenge is their realization for the development of engineering applications. From more than three decades ago, chaotic oscillators have been designed using discrete electronic devices, very few with integrated circuit technology, and in this work we propose the use of field-programmable gate arrays (FPGAs) for fast prototyping. FPGA-based applications require that one be expert on programming with very-high-speed integrated circuits hardware description language (VHDL). In this manner, we detail the VHDL descriptions of chaos generators for fast prototyping from high-level programming using Python. The cases of study are three kinds of chaos generators based on piecewise-linear (PWL) functions that can be systematically augmented to generate even and odd number of scrolls. We introduce new algorithms for the VHDL description of PWL functions like saturated functions series, negative slopes and sawtooth. The generated VHDL-code is portable, reusable and open source to be synthesized in an FPGA. Finally, we show experimental results for observing 2, 10 and 30-scroll attractors. PMID:27997930

VHDL Descriptions for the FPGA Implementation of PWL-Function-Based Multi-Scroll Chaotic Oscillators.

PubMed

Tlelo-Cuautle, Esteban; Quintas-Valles, Antonio de Jesus; de la Fraga, Luis Gerardo; Rangel-Magdaleno, Jose de Jesus

2016-01-01

Nowadays, chaos generators are an attractive field for research and the challenge is their realization for the development of engineering applications. From more than three decades ago, chaotic oscillators have been designed using discrete electronic devices, very few with integrated circuit technology, and in this work we propose the use of field-programmable gate arrays (FPGAs) for fast prototyping. FPGA-based applications require that one be expert on programming with very-high-speed integrated circuits hardware description language (VHDL). In this manner, we detail the VHDL descriptions of chaos generators for fast prototyping from high-level programming using Python. The cases of study are three kinds of chaos generators based on piecewise-linear (PWL) functions that can be systematically augmented to generate even and odd number of scrolls. We introduce new algorithms for the VHDL description of PWL functions like saturated functions series, negative slopes and sawtooth. The generated VHDL-code is portable, reusable and open source to be synthesized in an FPGA. Finally, we show experimental results for observing 2, 10 and 30-scroll attractors.

Fault-Tolerant Sequencer Using FPGA-Based Logic Designs for Space Applications

DTIC Science & Technology

2013-12-01

Prototype Board SBU single bit upset SDK software development kit SDRAM synchronous dynamic random-access memory SEB single-event burnout ...current VHDL VHSIC hardware description language VHSIC very-high-speed integrated circuits VLSI very-large- scale integration VQFP very...transient pulse, called a single-event transient (SET), or even cause permanent damage to the device in the form of a burnout or gate rupture. The SEE

Modular implementation of a digital hardware design automation system

NASA Astrophysics Data System (ADS)

Masud, M.

An automation system based on AHPL (A Hardware Programming Language) was developed. The project may be divided into three distinct phases: (1) Upgrading of AHPL to make it more universally applicable; (2) Implementation of a compiler for the language; and (3) illustration of how the compiler may be used to support several phases of design activities. Several new features were added to AHPL. These include: application-dependent parameters, mutliple clocks, asynchronous results, functional registers and primitive functions. The new language, called Universal AHPL, has been defined rigorously. The compiler design is modular. The parsing is done by an automatic parser generated from the SLR(1)BNF grammar of the language. The compiler produces two data bases from the AHPL description of a circuit. The first one is a tabular representation of the circuit, and the second one is a detailed interconnection linked list. The two data bases provide a means to interface the compiler to application-dependent CAD systems.

Extended behavioural device modelling and circuit simulation with Qucs-S

NASA Astrophysics Data System (ADS)

Brinson, M. E.; Kuznetsov, V.

2018-03-01

Current trends in circuit simulation suggest a growing interest in open source software that allows access to more than one simulation engine while simultaneously supporting schematic drawing tools, behavioural Verilog-A and XSPICE component modelling, and output data post-processing. This article introduces a number of new features recently implemented in the 'Quite universal circuit simulator - SPICE variant' (Qucs-S), including structure and fundamental schematic capture algorithms, at the same time highlighting their use in behavioural semiconductor device modelling. Particular importance is placed on the interaction between Qucs-S schematics, equation-defined devices, SPICE B behavioural sources and hardware description language (HDL) scripts. The multi-simulator version of Qucs is a freely available tool that offers extended modelling and simulation features compared to those provided by legacy circuit simulators. The performance of a number of Qucs-S modelling extensions are demonstrated with a GaN HEMT compact device model and data obtained from tests using the Qucs-S/Ngspice/Xyce ©/SPICE OPUS multi-engine circuit simulator.

Practical applications of digital integrated circuits. Part 2: Minimization techniques, code conversion, flip-flops, and asynchronous circuits

NASA Technical Reports Server (NTRS)

1972-01-01

Here, the 7400 line of transistor to transistor logic (TTL) devices is emphasized almost exclusively where hardware is concerned. However, it should be pointed out that the logic theory contained herein applies to all hardware. Binary numbers, simplification of logic circuits, code conversion circuits, basic flip-flop theory, details about series 54/7400, and asynchronous circuits are discussed.

EHW Approach to Temperature Compensation of Electronics

NASA Technical Reports Server (NTRS)

Stoica, Adrian

2004-01-01

Efforts are under way to apply the concept of evolvable hardware (EHW) to compensate for variations, with temperature, in the operational characteristics of electronic circuits. To maintain the required functionality of a given circuit at a temperature above or below the nominal operating temperature for which the circuit was originally designed, a new circuit would be evolved; moreover, to obtain the required functionality over a very wide temperature range, there would be evolved a number of circuits, each of which would satisfy the performance requirements over a small part of the total temperature range. The basic concepts and some specific implementations of EHW were described in a number of previous NASA Tech Briefs articles, namely, "Reconfigurable Arrays of Transistors for Evolvable Hardware" (NPO-20078), Vol. 25, No. 2 (February 2001), page 36; Evolutionary Automated Synthesis of Electronic Circuits (NPO- 20535), Vol. 26, No. 7 (July 2002), page 37; "Designing Reconfigurable Antennas Through Hardware Evolution" (NPO-20666), Vol. 26, No. 7 (July 2002), page 38; "Morphing in Evolutionary Synthesis of Electronic Circuits" (NPO-20837), Vol. 26, No. 8 (August 2002), page 31; "Mixtrinsic Evolutionary Synthesis of Electronic Circuits" (NPO-20773) Vol. 26, No. 8 (August 2002), page 32; and "Synthesis of Fuzzy-Logic Circuits in Evolvable Hardware" (NPO-21095) Vol. 26, No. 11 (November 2002), page 38. To recapitulate from the cited prior articles: EHW is characterized as evolutionary in a quasi-genetic sense. The essence of EHW is to construct and test a sequence of populations of circuits that function as incrementally better solutions of a given design problem through the selective, repetitive connection and/or disconnection of capacitors, transistors, amplifiers, inverters, and/or other circuit building blocks. The connection and disconnection can be effected by use of field-programmable transistor arrays (FPTAs). The evolution is guided by a search-andoptimization algorithm (in particular, a genetic algorithm) that operates in the space of possible circuits to find a circuit that exhibits an acceptably close approximation of the desired functionality. The evolved circuits can be tested by mathematical modeling (that is, computational simulation) only, tested in real hardware, or tested in combinations of computational simulation and real hardware.

Hardware architecture for projective model calculation and false match refining using random sample consensus algorithm

NASA Astrophysics Data System (ADS)

Azimi, Ehsan; Behrad, Alireza; Ghaznavi-Ghoushchi, Mohammad Bagher; Shanbehzadeh, Jamshid

2016-11-01

The projective model is an important mapping function for the calculation of global transformation between two images. However, its hardware implementation is challenging because of a large number of coefficients with different required precisions for fixed point representation. A VLSI hardware architecture is proposed for the calculation of a global projective model between input and reference images and refining false matches using random sample consensus (RANSAC) algorithm. To make the hardware implementation feasible, it is proved that the calculation of the projective model can be divided into four submodels comprising two translations, an affine model and a simpler projective mapping. This approach makes the hardware implementation feasible and considerably reduces the required number of bits for fixed point representation of model coefficients and intermediate variables. The proposed hardware architecture for the calculation of a global projective model using the RANSAC algorithm was implemented using Verilog hardware description language and the functionality of the design was validated through several experiments. The proposed architecture was synthesized by using an application-specific integrated circuit digital design flow utilizing 180-nm CMOS technology as well as a Virtex-6 field programmable gate array. Experimental results confirm the efficiency of the proposed hardware architecture in comparison with software implementation.

A SOPC-BASED Evaluation of AES for 2.4 GHz Wireless Network

NASA Astrophysics Data System (ADS)

Ken, Cai; Xiaoying, Liang

In modern systems, data security is needed more than ever before and many cryptographic algorithms are utilized for security services. Wireless Sensor Networks (WSN) is an example of such technologies. In this paper an innovative SOPC-based approach for the security services evaluation in WSN is proposed that addresses the issues of scalability, flexible performance, and silicon efficiency for the hardware acceleration of encryption system. The design includes a Nios II processor together with custom designed modules for the Advanced Encryption Standard (AES) which has become the default choice for various security services in numerous applications. The objective of this mechanism is to present an efficient hardware realization of AES using very high speed integrated circuit hardware description language (Verilog HDL) and expand the usability for various applications. As compared to traditional customize processor design, the mechanism provides a very broad range of cost/performance points.

Formal hardware verification of digital circuits

NASA Technical Reports Server (NTRS)

Joyce, J.; Seger, C.-J.

1991-01-01

The use of formal methods to verify the correctness of digital circuits is less constrained by the growing complexity of digital circuits than conventional methods based on exhaustive simulation. This paper briefly outlines three main approaches to formal hardware verification: symbolic simulation, state machine analysis, and theorem-proving.

Transistor Level Circuit Experiments using Evolvable Hardware

NASA Technical Reports Server (NTRS)

Stoica, A.; Zebulum, R. S.; Keymeulen, D.; Ferguson, M. I.; Daud, Taher; Thakoor, A.

2005-01-01

The Jet Propulsion Laboratory (JPL) performs research in fault tolerant, long life, and space survivable electronics for the National Aeronautics and Space Administration (NASA). With that focus, JPL has been involved in Evolvable Hardware (EHW) technology research for the past several years. We have advanced the technology not only by simulation and evolution experiments, but also by designing, fabricating, and evolving a variety of transistor-based analog and digital circuits at the chip level. EHW refers to self-configuration of electronic hardware by evolutionary/genetic search mechanisms, thereby maintaining existing functionality in the presence of degradations due to aging, temperature, and radiation. In addition, EHW has the capability to reconfigure itself for new functionality when required for mission changes or encountered opportunities. Evolution experiments are performed using a genetic algorithm running on a DSP as the reconfiguration mechanism and controlling the evolvable hardware mounted on a self-contained circuit board. Rapid reconfiguration allows convergence to circuit solutions in the order of seconds. The paper illustrates hardware evolution results of electronic circuits and their ability to perform under 230 C temperature as well as radiations of up to 250 kRad.

An Efficient Hardware Circuit for Spike Sorting Based on Competitive Learning Networks.

PubMed

Chen, Huan-Yuan; Chen, Chih-Chang; Hwang, Wen-Jyi

2017-09-28

This study aims to present an effective VLSI circuit for multi-channel spike sorting. The circuit supports the spike detection, feature extraction and classification operations. The detection circuit is implemented in accordance with the nonlinear energy operator algorithm. Both the peak detection and area computation operations are adopted for the realization of the hardware architecture for feature extraction. The resulting feature vectors are classified by a circuit for competitive learning (CL) neural networks. The CL circuit supports both online training and classification. In the proposed architecture, all the channels share the same detection, feature extraction, learning and classification circuits for a low area cost hardware implementation. The clock-gating technique is also employed for reducing the power dissipation. To evaluate the performance of the architecture, an application-specific integrated circuit (ASIC) implementation is presented. Experimental results demonstrate that the proposed circuit exhibits the advantages of a low chip area, a low power dissipation and a high classification success rate for spike sorting.

An Efficient Hardware Circuit for Spike Sorting Based on Competitive Learning Networks

PubMed Central

Chen, Huan-Yuan; Chen, Chih-Chang

2017-01-01

This study aims to present an effective VLSI circuit for multi-channel spike sorting. The circuit supports the spike detection, feature extraction and classification operations. The detection circuit is implemented in accordance with the nonlinear energy operator algorithm. Both the peak detection and area computation operations are adopted for the realization of the hardware architecture for feature extraction. The resulting feature vectors are classified by a circuit for competitive learning (CL) neural networks. The CL circuit supports both online training and classification. In the proposed architecture, all the channels share the same detection, feature extraction, learning and classification circuits for a low area cost hardware implementation. The clock-gating technique is also employed for reducing the power dissipation. To evaluate the performance of the architecture, an application-specific integrated circuit (ASIC) implementation is presented. Experimental results demonstrate that the proposed circuit exhibits the advantages of a low chip area, a low power dissipation and a high classification success rate for spike sorting. PMID:28956859

Commercial Capaciflector

NASA Technical Reports Server (NTRS)

Vranish, John M.

1991-01-01

A capacitive proximity/tactile sensor with unique performance capabilities ('capaciflector' or capacitive reflector) is being developed by NASA/Goddard Space Flight Center (GSFC) for use on robots and payloads in space in the interests of safety, efficiency, and ease of operation. Specifically, this sensor will permit robots and their attached payloads to avoid collisions in space with humans and other objects and to dock these payloads in a cluttered environment. The sensor is simple, robust, and inexpensive to manufacture with obvious and recognized commercial possibilities. Accordingly, NASA/GSFC, in conjunction with industry, is embarking on an effort to 'spin' this technology off into the private sector. This effort includes prototypes aimed at commercial applications. The principles of operation of these prototypes are described along with hardware, software, modelling, and test results. The hardware description includes both the physical sensor in terms of a flexible printed circuit board and the electronic circuitry. The software description will include filtering and detection techniques. The modelling will involve finite element electric field analysis and will underline techniques used for design optimization.

Remote reset circuit

DOEpatents

Gritzo, R.E.

1985-09-12

A remote reset circuit acts as a stand-along monitor and controller by clocking in each character sent by a terminal to a computer and comparing it to a given reference character. When a match occurs, the remote reset circuit activates the system's hardware reset line. The remote reset circuit is hardware based centered around monostable multivibrators and is unaffected by system crashes, partial serial transmissions, or power supply transients. 4 figs.

Remote reset circuit

DOEpatents

Gritzo, Russell E.

1987-01-01

A remote reset circuit acts as a stand-alone monitor and controller by clocking in each character sent by a terminal to a computer and comparing it to a given reference character. When a match occurs, the remote reset circuit activates the system's hardware reset line. The remote reset circuit is hardware based centered around monostable multivibrators and is unaffected by system crashes, partial serial transmissions, or power supply transients.

A Circuit-Based Neural Network with Hybrid Learning of Backpropagation and Random Weight Change Algorithms

PubMed Central

Yang, Changju; Kim, Hyongsuk; Adhikari, Shyam Prasad; Chua, Leon O.

2016-01-01

A hybrid learning method of a software-based backpropagation learning and a hardware-based RWC learning is proposed for the development of circuit-based neural networks. The backpropagation is known as one of the most efficient learning algorithms. A weak point is that its hardware implementation is extremely difficult. The RWC algorithm, which is very easy to implement with respect to its hardware circuits, takes too many iterations for learning. The proposed learning algorithm is a hybrid one of these two. The main learning is performed with a software version of the BP algorithm, firstly, and then, learned weights are transplanted on a hardware version of a neural circuit. At the time of the weight transplantation, a significant amount of output error would occur due to the characteristic difference between the software and the hardware. In the proposed method, such error is reduced via a complementary learning of the RWC algorithm, which is implemented in a simple hardware. The usefulness of the proposed hybrid learning system is verified via simulations upon several classical learning problems. PMID:28025566

Hardware efficient monitoring of input/output signals

NASA Technical Reports Server (NTRS)

Driscoll, Kevin R. (Inventor); Hall, Brendan (Inventor); Paulitsch, Michael (Inventor)

2012-01-01

A communication device comprises first and second circuits to implement a plurality of ports via which the communicative device is operable to communicate over a plurality of communication channels. For each of the plurality of ports, the communication device comprises: command hardware that includes a first transmitter to transmit data over a respective one of the plurality of channels and a first receiver to receive data from the respective one of the plurality of channels; and monitor hardware that includes a second receiver coupled to the first transmitter and a third receiver coupled to the respective one of the plurality of channels. The first circuit comprises the command hardware for a first subset of the plurality of ports. The second circuit comprises the monitor hardware for the first subset of the plurality of ports and the command hardware for a second subset of the plurality of ports.

Temporal Planning for Compilation of Quantum Approximate Optimization Algorithm Circuits

NASA Technical Reports Server (NTRS)

Venturelli, Davide; Do, Minh Binh; Rieffel, Eleanor Gilbert; Frank, Jeremy David

2017-01-01

We investigate the application of temporal planners to the problem of compiling quantum circuits to newly emerging quantum hardware. While our approach is general, we focus our initial experiments on Quantum Approximate Optimization Algorithm (QAOA) circuits that have few ordering constraints and allow highly parallel plans. We report on experiments using several temporal planners to compile circuits of various sizes to a realistic hardware. This early empirical evaluation suggests that temporal planning is a viable approach to quantum circuit compilation.

Multispectral image fusion using neural networks

NASA Technical Reports Server (NTRS)

Kagel, J. H.; Platt, C. A.; Donaven, T. W.; Samstad, E. A.

1990-01-01

A prototype system is being developed to demonstrate the use of neural network hardware to fuse multispectral imagery. This system consists of a neural network IC on a motherboard, a circuit card assembly, and a set of software routines hosted by a PC-class computer. Research in support of this consists of neural network simulations fusing 4 to 7 bands of Landsat imagery and fusing (separately) multiple bands of synthetic imagery. The simulations, results, and a description of the prototype system are presented.

Standard high-reliability integrated circuit logic packaging. [for deep space tracking stations

NASA Technical Reports Server (NTRS)

Slaughter, D. W.

1977-01-01

A family of standard, high-reliability hardware used for packaging digital integrated circuits is described. The design transition from early prototypes to production hardware is covered and future plans are discussed. Interconnections techniques are described as well as connectors and related hardware available at both the microcircuit packaging and main-frame level. General applications information is also provided.

Hardware Design and Implementation of Fixed-Width Standard and Truncated 4×4, 6×6, 8×8 and 12×12-BIT Multipliers Using Fpga

NASA Astrophysics Data System (ADS)

Rais, Muhammad H.

2010-06-01

This paper presents Field Programmable Gate Array (FPGA) implementation of standard and truncated multipliers using Very High Speed Integrated Circuit Hardware Description Language (VHDL). Truncated multiplier is a good candidate for digital signal processing (DSP) applications such as finite impulse response (FIR) and discrete cosine transform (DCT). Remarkable reduction in FPGA resources, delay, and power can be achieved using truncated multipliers instead of standard parallel multipliers when the full precision of the standard multiplier is not required. The truncated multipliers show significant improvement as compared to standard multipliers. Results show that the anomaly in Spartan-3 AN average connection and maximum pin delay have been efficiently reduced in Virtex-4 device.

Towards Evolving Electronic Circuits for Autonomous Space Applications

NASA Technical Reports Server (NTRS)

Lohn, Jason D.; Haith, Gary L.; Colombano, Silvano P.; Stassinopoulos, Dimitris

2000-01-01

The relatively new field of Evolvable Hardware studies how simulated evolution can reconfigure, adapt, and design hardware structures in an automated manner. Space applications, especially those requiring autonomy, are potential beneficiaries of evolvable hardware. For example, robotic drilling from a mobile platform requires high-bandwidth controller circuits that are difficult to design. In this paper, we present automated design techniques based on evolutionary search that could potentially be used in such applications. First, we present a method of automatically generating analog circuit designs using evolutionary search and a circuit construction language. Our system allows circuit size (number of devices), circuit topology, and device values to be evolved. Using a parallel genetic algorithm, we present experimental results for five design tasks. Second, we investigate the use of coevolution in automated circuit design. We examine fitness evaluation by comparing the effectiveness of four fitness schedules. The results indicate that solution quality is highest with static and co-evolving fitness schedules as compared to the other two dynamic schedules. We discuss these results and offer two possible explanations for the observed behavior: retention of useful information, and alignment of problem difficulty with circuit proficiency.

Hardware Interface Description for the Integrated Power, Avionics, and Software (iPAS) Space Telecommunications Radio Ssystem (STRS) Radio

NASA Technical Reports Server (NTRS)

Shalkhauser, Mary Jo W.; Roche, Rigoberto

2017-01-01

The Space Telecommunications Radio System (STRS) provides a common, consistent framework for software defined radios (SDRs) to abstract the application software from the radio platform hardware. The STRS standard aims to reduce the cost and risk of using complex, configurable and reprogrammable radio systems across NASA missions. To promote the use of the STRS architecture for future NASA advanced exploration missions, NASA Glenn Research Center (GRC) developed an STRS-compliant SDR on a radio platform used by the Advance Exploration System program at the Johnson Space Center (JSC) in their Integrated Power, Avionics, and Software (iPAS) laboratory. The iPAS STRS Radio was implemented on the Reconfigurable, Intelligently-Adaptive Communication System (RIACS) platform, currently being used for radio development at JSC. The platform consists of a Xilinx ML605 Virtex-6 FPGA board, an Analog Devices FMCOMMS1-EBZ RF transceiver board, and an Embedded PC (Axiomtek eBox 620-110-FL) running the Ubuntu 12.4 operating system. Figure 1 shows the RIACS platform hardware. The result of this development is a very low cost STRS compliant platform that can be used for waveform developments for multiple applications.The purpose of this document is to describe how to develop a new waveform using the RIACS platform and the Very High Speed Integrated Circuits (VHSIC) Hardware Description Language (VHDL) FPGA wrapper code and the STRS implementation on the Axiomtek processor.

Cancellation Circuit for Transmit-Receive Isolation

DTIC Science & Technology

2010-09-01

non -ideal hardware, and the performance of the circuit is limited. One of the major problems is the leakage from the circulator. The leakage disrupts...cancellation circuit was investigated by a series of simulations using Agilent ADS (Agilent Advanced Design System), and hardware tests were conducted to...developed in the WDDPA application, allowing coherent processing of the data from all elements. There are limitations encountered due to non -ideal

Safety-related requirements for photovoltaic modules and arrays

NASA Technical Reports Server (NTRS)

Levins, A.; Smoot, A.; Wagner, R.

1984-01-01

Safety requirements for photovoltaic module and panel designs and configurations for residential, intermediate, and large scale applications are investigated. Concepts for safety systems, where each system is a collection of subsystems which together address the total anticipated hazard situation, are described. Descriptions of hardware, and system usefulness and viability are included. A comparison of these systems, as against the provisions of the 1984 National Electrical Code covering photovoltaic systems is made. A discussion of the Underwriters Laboratory UL investigation of the photovoltaic module evaluated to the provisions of the proposed UL standard for plat plate photovoltaic modules and panels is included. Grounding systems, their basis and nature, and the advantages and disadvantages of each are described. The meaning of frame grounding, circuit groundings, and the type of circuit ground are covered.

VHDL simulation with access to transistor models

NASA Technical Reports Server (NTRS)

Gibson, J.

1991-01-01

Hardware description languages such as VHDL have evolved to aid in the design of systems with large numbers of elements and a wide range of electronic and logical abstractions. For high performance circuits, behavioral models may not be able to efficiently include enough detail to give designers confidence in a simulation's accuracy. One option is to provide a link between the VHDL environment and a transistor level simulation environment. The coupling of the Vantage Analysis Systems VHDL simulator and the NOVA simulator provides the combination of VHDL modeling and transistor modeling.

Application specific serial arithmetic arrays

NASA Technical Reports Server (NTRS)

Winters, K.; Mathews, D.; Thompson, T.

1990-01-01

High performance systolic arrays of serial-parallel multiplier elements may be rapidly constructed for specific applications by applying hardware description language techniques to a library of full-custom CMOS building blocks. Single clock pre-charged circuits have been implemented for these arrays at clock rates in excess of 100 Mhz using economical 2-micron (minimum feature size) CMOS processes, which may be quickly configured for a variety of applications. A number of application-specific arrays are presented, including a 2-D convolver for image processing, an integer polynomial solver, and a finite-field polynomial solver.

Design verification tests for an axial gap permanent magnet compressor motor

NASA Astrophysics Data System (ADS)

Hawsey, R. A.; Bailey, J. M.

1987-07-01

A 30-hp, direct-drive, permanent magnet motor (PMM) has been constructed. The motor is to operate at 15,000 rpm and is designed to drive a Worthington compressor at the US DOE-owned gaseous diffusion plants. The PMM prevents traditional dynamometer testing, including locked rotor current, voltage, and torque measurements. A test plan is presented for data acquisition on the dynamometer test stand in order to calculate the equivalent circuit for the motor. A description of the hardware required for these measurements is included in the plan.

Design, Modeling, and Fabrication of Chemical Vapor Deposition Grown MoS2 Circuits with E-Mode FETs for Large-Area Electronics.

PubMed

Yu, Lili; El-Damak, Dina; Radhakrishna, Ujwal; Ling, Xi; Zubair, Ahmad; Lin, Yuxuan; Zhang, Yuhao; Chuang, Meng-Hsi; Lee, Yi-Hsien; Antoniadis, Dimitri; Kong, Jing; Chandrakasan, Anantha; Palacios, Tomas

2016-10-12

Two-dimensional electronics based on single-layer (SL) MoS 2 offers significant advantages for realizing large-scale flexible systems owing to its ultrathin nature, good transport properties, and stable crystalline structure. In this work, we utilize a gate first process technology for the fabrication of highly uniform enhancement mode FETs with large mobility and excellent subthreshold swing. To enable large-scale MoS 2 circuit, we also develop Verilog-A compact models that accurately predict the performance of the fabricated MoS 2 FETs as well as a parametrized layout cell for the FET to facilitate the design and layout process using computer-aided design (CAD) tools. Using this CAD flow, we designed combinational logic gates and sequential circuits (AND, OR, NAND, NOR, XNOR, latch, edge-triggered register) as well as switched capacitor dc-dc converter, which were then fabricated using the proposed flow showing excellent performance. The fabricated integrated circuits constitute the basis of a standard cell digital library that is crucial for electronic circuit design using hardware description languages. The proposed design flow provides a platform for the co-optimization of the device fabrication technology and circuits design for future ubiquitous flexible and transparent electronics using two-dimensional materials.

Interface Circuits for Self-Checking Microprocessors

NASA Technical Reports Server (NTRS)

Rennels, D. A.; Chandramouli, R.

1986-01-01

Fault-tolerant-microcomputer concept based on enhancing "simple" computer with redundancy and self-checking logic circuits detect hardware faults. Interface and checking logic and redundant processors confer on 16-bit microcomputer ability to check itself for hardware faults. Checking circuitry also checks itself. Concept of self-checking complementary pairs (SCCP's) employed throughout ICL unit.

RRAM-based hardware implementations of artificial neural networks: progress update and challenges ahead

NASA Astrophysics Data System (ADS)

Prezioso, M.; Merrikh-Bayat, F.; Chakrabarti, B.; Strukov, D.

2016-02-01

Artificial neural networks have been receiving increasing attention due to their superior performance in many information processing tasks. Typically, scaling up the size of the network results in better performance and richer functionality. However, large neural networks are challenging to implement in software and customized hardware are generally required for their practical implementations. In this work, we will discuss our group's recent efforts on the development of such custom hardware circuits, based on hybrid CMOS/memristor circuits, in particular of CMOL variety. We will start by reviewing the basics of memristive devices and of CMOL circuits. We will then discuss our recent progress towards demonstration of hybrid circuits, focusing on the experimental and theoretical results for artificial neural networks based on crossbarintegrated metal oxide memristors. We will conclude presentation with the discussion of the remaining challenges and the most pressing research needs.

Gas Sensors Characterization and Multilayer Perceptron (MLP) Hardware Implementation for Gas Identification Using a Field Programmable Gate Array (FPGA)

PubMed Central

Benrekia, Fayçal; Attari, Mokhtar; Bouhedda, Mounir

2013-01-01

This paper develops a primitive gas recognition system for discriminating between industrial gas species. The system under investigation consists of an array of eight micro-hotplate-based SnO2 thin film gas sensors with different selectivity patterns. The output signals are processed through a signal conditioning and analyzing system. These signals feed a decision-making classifier, which is obtained via a Field Programmable Gate Array (FPGA) with Very High-Speed Integrated Circuit Hardware Description Language. The classifier relies on a multilayer neural network based on a back propagation algorithm with one hidden layer of four neurons and eight neurons at the input and five neurons at the output. The neural network designed after implementation consists of twenty thousand gates. The achieved experimental results seem to show the effectiveness of the proposed classifier, which can discriminate between five industrial gases. PMID:23529119

Towards a visual modeling approach to designing microelectromechanical system transducers

NASA Astrophysics Data System (ADS)

Dewey, Allen; Srinivasan, Vijay; Icoz, Evrim

1999-12-01

In this paper, we address initial design capture and system conceptualization of microelectromechanical system transducers based on visual modeling and design. Visual modeling frames the task of generating hardware description language (analog and digital) component models in a manner similar to the task of generating software programming language applications. A structured topological design strategy is employed, whereby microelectromechanical foundry cell libraries are utilized to facilitate the design process of exploring candidate cells (topologies), varying key aspects of the transduction for each topology, and determining which topology best satisfies design requirements. Coupled-energy microelectromechanical system characterizations at a circuit level of abstraction are presented that are based on branch constitutive relations and an overall system of simultaneous differential and algebraic equations. The resulting design methodology is called visual integrated-microelectromechanical VHDL-AMS interactive design (VHDL-AMS is visual hardware design language for analog and mixed signal).

A control system based on field programmable gate array for papermaking sewage treatment

NASA Astrophysics Data System (ADS)

Zhang, Zi Sheng; Xie, Chang; Qing Xiong, Yan; Liu, Zhi Qiang; Li, Qing

2013-03-01

A sewage treatment control system is designed to improve the efficiency of papermaking wastewater treatment system. The automation control system is based on Field Programmable Gate Array (FPGA), coded with Very-High-Speed Integrate Circuit Hardware Description Language (VHDL), compiled and simulated with Quartus. In order to ensure the stability of the data used in FPGA, the data is collected through temperature sensors, water level sensor and online PH measurement system. The automatic control system is more sensitive, and both the treatment efficiency and processing power are increased. This work provides a new method for sewage treatment control.

Methods for the design and analysis of power optimized finite-state machines using clock gating

NASA Astrophysics Data System (ADS)

Chodorowski, Piotr

2017-11-01

The paper discusses two methods of design of power optimized FSMs. Both methods use clock gating techniques. The main objective of the research was to write a program capable of generating automatic hardware description of finite-state machines in VHDL and testbenches to help power analysis. The creation of relevant output files is detailed step by step. The program was tested using the LGSynth91 FSM benchmark package. An analysis of the generated circuits shows that the second method presented in this paper leads to significant reduction of power consumption.

Novel Designs of Quantum Reversible Counters

NASA Astrophysics Data System (ADS)

Qi, Xuemei; Zhu, Haihong; Chen, Fulong; Zhu, Junru; Zhang, Ziyang

2016-11-01

Reversible logic, as an interesting and important issue, has been widely used in designing combinational and sequential circuits for low-power and high-speed computation. Though a significant number of works have been done on reversible combinational logic, the realization of reversible sequential circuit is still at premature stage. Reversible counter is not only an important part of the sequential circuit but also an essential part of the quantum circuit system. In this paper, we designed two kinds of novel reversible counters. In order to construct counter, the innovative reversible T Flip-flop Gate (TFG), T Flip-flop block (T_FF) and JK flip-flop block (JK_FF) are proposed. Based on the above blocks and some existing reversible gates, the 4-bit binary-coded decimal (BCD) counter and controlled Up/Down synchronous counter are designed. With the help of Verilog hardware description language (Verilog HDL), these counters above have been modeled and confirmed. According to the simulation results, our circuits' logic structures are validated. Compared to the existing ones in terms of quantum cost (QC), delay (DL) and garbage outputs (GBO), it can be concluded that our designs perform better than the others. There is no doubt that they can be used as a kind of important storage components to be applied in future low-power computing systems.

Neural Networks Based Approach to Enhance Space Hardware Reliability

NASA Technical Reports Server (NTRS)

Zebulum, Ricardo S.; Thakoor, Anilkumar; Lu, Thomas; Franco, Lauro; Lin, Tsung Han; McClure, S. S.

2011-01-01

This paper demonstrates the use of Neural Networks as a device modeling tool to increase the reliability analysis accuracy of circuits targeted for space applications. The paper tackles a number of case studies of relevance to the design of Flight hardware. The results show that the proposed technique generates more accurate models than the ones regularly used to model circuits.

Modeling cortical circuits.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Rohrer, Brandon Robinson; Rothganger, Fredrick H.; Verzi, Stephen J.

2010-09-01

The neocortex is perhaps the highest region of the human brain, where audio and visual perception takes place along with many important cognitive functions. An important research goal is to describe the mechanisms implemented by the neocortex. There is an apparent regularity in the structure of the neocortex [Brodmann 1909, Mountcastle 1957] which may help simplify this task. The work reported here addresses the problem of how to describe the putative repeated units ('cortical circuits') in a manner that is easily understood and manipulated, with the long-term goal of developing a mathematical and algorithmic description of their function. The approachmore » is to reduce each algorithm to an enhanced perceptron-like structure and describe its computation using difference equations. We organize this algorithmic processing into larger structures based on physiological observations, and implement key modeling concepts in software which runs on parallel computing hardware.« less

Using Modern Design Tools for Digital Avionics Development

NASA Technical Reports Server (NTRS)

Hyde, David W.; Lakin, David R., II; Asquith, Thomas E.

2000-01-01

Using Modem Design Tools for Digital Avionics Development Shrinking development time and increased complexity of new avionics forces the designer to use modem tools and methods during hardware development. Engineers at the Marshall Space Flight Center have successfully upgraded their design flow and used it to develop a Mongoose V based radiation tolerant processor board for the International Space Station's Water Recovery System. The design flow, based on hardware description languages, simulation, synthesis, hardware models, and full functional software model libraries, allowed designers to fully simulate the processor board from reset, through initialization before any boards were built. The fidelity of a digital simulation is limited to the accuracy of the models used and how realistically the designer drives the circuit's inputs during simulation. By using the actual silicon during simulation, device modeling errors are reduced. Numerous design flaws were discovered early in the design phase when they could be easily fixed. The use of hardware models and actual MIPS software loaded into full functional memory models also provided checkout of the software development environment. This paper will describe the design flow used to develop the processor board and give examples of errors that were found using the tools. An overview of the processor board firmware will also be covered.

Artificial Neural Network with Hardware Training and Hardware Refresh

NASA Technical Reports Server (NTRS)

Duong, Tuan A. (Inventor)

2003-01-01

A neural network circuit is provided having a plurality of circuits capable of charge storage. Also provided is a plurality of circuits each coupled to at least one of the plurality of charge storage circuits and constructed to generate an output in accordance with a neuron transfer function. Each of a plurality of circuits is coupled to one of the plurality of neuron transfer function circuits and constructed to generate a derivative of the output. A weight update circuit updates the charge storage circuits based upon output from the plurality of transfer function circuits and output from the plurality of derivative circuits. In preferred embodiments, separate training and validation networks share the same set of charge storage circuits and may operate concurrently. The validation network has a separate transfer function circuits each being coupled to the charge storage circuits so as to replicate the training network s coupling of the plurality of charge storage to the plurality of transfer function circuits. The plurality of transfer function circuits may be constructed each having a transconductance amplifier providing differential currents combined to provide an output in accordance with a transfer function. The derivative circuits may have a circuit constructed to generate a biased differential currents combined so as to provide the derivative of the transfer function.

Formal semantics for a subset of VHDL and its use in analysis of the FTPP scoreboard circuit

NASA Technical Reports Server (NTRS)

Bickford, Mark

1994-01-01

In the first part of the report, we give a detailed description of an operational semantics for a large subset of VHDL, the VHSIC Hardware Description Language. The semantics is written in the functional language Caliban, similar to Haskell, used by the theorem prover Clio. We also describe a translator from VHDL into Caliban semantics and give some examples of its use. In the second part of the report, we describe our experience in using the VHDL semantics to try to verify a large VHDL design. We were not able to complete the verification due to certain complexities of VHDL which we discuss. We propose a VHDL verification method that addresses the problems we encountered but which builds on the operational semantics described in the first part of the report.

Microprocessors as a Vehicle for Teaching Circuit Analysis.

ERIC Educational Resources Information Center

Neu, Emil C.

1982-01-01

Based on the premise that most engineering students will own their own microcomputers, discusses the teaching of circuit analysis, possible directions to be taken in hardware analysis, and impact on the mathematics related to circuit analysis. (SK)

Polymorphic Electronic Circuits

NASA Technical Reports Server (NTRS)

Stoica, Adrian

2004-01-01

Polymorphic electronics is a nascent technological discipline that involves, among other things, designing the same circuit to perform different analog and/or digital functions under different conditions. For example, a circuit can be designed to function as an OR gate or an AND gate, depending on the temperature (see figure). Polymorphic electronics can also be considered a subset of polytronics, which is a broader technological discipline in which optical and possibly other information- processing systems could also be designed to perform multiple functions. Polytronics is an outgrowth of evolvable hardware (EHW). The basic concepts and some specific implementations of EHW were described in a number of previous NASA Tech Briefs articles. To recapitulate: The essence of EHW is to design, construct, and test a sequence of populations of circuits that function as incrementally better solutions of a given design problem through the selective, repetitive connection and/or disconnection of capacitors, transistors, amplifiers, inverters, and/or other circuit building blocks. The evolution is guided by a search-and-optimization algorithm (in particular, a genetic algorithm) that operates in the space of possible circuits to find a circuit that exhibits an acceptably close approximation of the desired functionality. The evolved circuits can be tested by computational simulation (in which case the evolution is said to be extrinsic), tested in real hardware (in which case the evolution is said to be intrinsic), or tested in random sequences of computational simulation and real hardware (in which case the evolution is said to be mixtrinsic).

3D Printed Fluidic Hardware for DNA Assembly

DTIC Science & Technology

2015-04-10

A3909 stepper motor driver, were soldered onto the milled circuit board (Supplementary Figure 8). Custom Arduino - based firmware was written to take...initiatives such as the FabLab Foundation10. Access to digital fabrication tools and open electronics, such as Arduino and Raspberry Pi, enables access to...hardware for assembly of DNA- based genetic circuits. Solid-phase DNA synthesis has declined in price, enabling researchers to routinely design and

The digital compensation technology system for automotive pressure sensor

NASA Astrophysics Data System (ADS)

Guo, Bin; Li, Quanling; Lu, Yi; Luo, Zai

2011-05-01

Piezoresistive pressure sensor be made of semiconductor silicon based on Piezoresistive phenomenon, has many characteristics. But since the temperature effect of semiconductor, the performance of silicon sensor is also changed by temperature, and the pressure sensor without temperature drift can not be produced at present. This paper briefly describe the principles of sensors, the function of pressure sensor and the various types of compensation method, design the detailed digital compensation program for automotive pressure sensor. Simulation-Digital mixed signal conditioning is used in this dissertation, adopt signal conditioning chip MAX1452. AVR singlechip ATMEGA128 and other apparatus; fulfill the design of digital pressure sensor hardware circuit and singlechip hardware circuit; simultaneously design the singlechip software; Digital pressure sensor hardware circuit is used to implementing the correction and compensation of sensor; singlechip hardware circuit is used to implementing to controll the correction and compensation of pressure sensor; singlechip software is used to implementing to fulfill compensation arithmetic. In the end, it implement to measure the output of sensor, and contrast to the data of non-compensation, the outcome indicates that the compensation precision of compensated sensor output is obviously better than non-compensation sensor, not only improving the compensation precision but also increasing the stabilization of pressure sensor.

Pratt and Whitney Overview and Advanced Health Management Program

NASA Technical Reports Server (NTRS)

Inabinett, Calvin

2008-01-01

Hardware Development Activity: Design and Test Custom Multi-layer Circuit Boards for use in the Fault Emulation Unit; Logic design performed using VHDL; Layout power system for lab hardware; Work lab issues with software developers and software testers; Interface with Engine Systems personnel with performance of Engine hardware components; Perform off nominal testing with new engine hardware.

Rapid evolution of analog circuits configured on a field programmable transistor array

NASA Technical Reports Server (NTRS)

Stoica, A.; Ferguson, M. I.; Zebulum, R. S.; Keymeulen, D.; Duong, V.; Daud, T.

2002-01-01

The purpose of this paper is to illustrate evolution of analog circuits on a stand-alone board-level evolvable system (SABLES). SABLES is part of an effort to achieve integrated evolvable systems. SABLES provides autonomous, fast (tens to hundreds of seconds), on-chip circuit evolution involving about 100,000 circuit evaluations. Its main components are a JPL Field Programmable Transistor Array (FPTA) chip used as transistor-level reconfigurable hardware, and a TI DSP that implements the evolutionary algorithm controlling the FPTA reconfiguration. The paper details an example of evolution on SABLES and points out to certain transient and memory effects that affect the stability of solutions obtained reusing the same piece of hardware for rapid testing of individuals during evolution.

Autonomous power system brassboard

NASA Technical Reports Server (NTRS)

Merolla, Anthony

1992-01-01

The Autonomous Power System (APS) brassboard is a 20 kHz power distribution system which has been developed at NASA Lewis Research Center, Cleveland, Ohio. The brassboard exists to provide a realistic hardware platform capable of testing artificially intelligent (AI) software. The brassboard's power circuit topology is based upon a Power Distribution Control Unit (PDCU), which is a subset of an advanced development 20 kHz electrical power system (EPS) testbed, originally designed for Space Station Freedom (SSF). The APS program is designed to demonstrate the application of intelligent software as a fault detection, isolation, and recovery methodology for space power systems. This report discusses both the hardware and software elements used to construct the present configuration of the brassboard. The brassboard power components are described. These include the solid-state switches (herein referred to as switchgear), transformers, sources, and loads. Closely linked to this power portion of the brassboard is the first level of embedded control. Hardware used to implement this control and its associated software is discussed. An Ada software program, developed by Lewis Research Center's Space Station Freedom Directorate for their 20 kHz testbed, is used to control the brassboard's switchgear, as well as monitor key brassboard parameters through sensors located within these switches. The Ada code is downloaded from a PC/AT, and is resident within the 8086 microprocessor-based embedded controllers. The PC/AT is also used for smart terminal emulation, capable of controlling the switchgear as well as displaying data from them. Intelligent control is provided through use of a T1 Explorer and the Autonomous Power Expert (APEX) LISP software. Real-time load scheduling is implemented through use of a 'C' program-based scheduling engine. The methods of communication between these computers and the brassboard are explored. In order to evaluate the features of both the brassboard hardware and intelligent controlling software, fault circuits have been developed and integrated as part of the brassboard. A description of these fault circuits and their function is included. The brassboard has become an extremely useful test facility, promoting artificial intelligence (AI) applications for power distribution systems. However, there are elements of the brassboard which could be enhanced, thus improving system performance. Modifications and enhancements to improve the brassboard's operation are discussed.

Tinker's Toys: Lessons from Bank Street: Hardware.

ERIC Educational Resources Information Center

Tinker, Robert

1985-01-01

Bank Street Laboratory (a set of hardware/software tools for measuring temperature, light, and sound) consists of a board that plugs into Apple microcomputers, cabling, software, and six probes. Discusses the laboratory's hardware, including the analog-to-digital converter, multiplier chip, and modular connectors. Circuit diagrams of components…

Hardware acceleration and verification of systems designed with hardware description languages (HDL)

NASA Astrophysics Data System (ADS)

Wisniewski, Remigiusz; Wegrzyn, Marek

2005-02-01

Hardware description languages (HDLs) allow creating bigger and bigger designs nowadays. The size of prototyped systems very often exceeds million gates. Therefore verification process of the designs takes several hours or even days. The solution for this problem can be solved by hardware acceleration of simulation.

Design and experiment of vehicular charger AC/DC system based on predictive control algorithm

NASA Astrophysics Data System (ADS)

He, Guangbi; Quan, Shuhai; Lu, Yuzhang

2018-06-01

For the car charging stage rectifier uncontrollable system, this paper proposes a predictive control algorithm of DC/DC converter based on the prediction model, established by the state space average method and its prediction model, obtained by the optimal mathematical description of mathematical calculation, to analysis prediction algorithm by Simulink simulation. The design of the structure of the car charging, at the request of the rated output power and output voltage adjustable control circuit, the first stage is the three-phase uncontrolled rectifier DC voltage Ud through the filter capacitor, after by using double-phase interleaved buck-boost circuit with wide range output voltage required value, analyzing its working principle and the the parameters for the design and selection of components. The analysis of current ripple shows that the double staggered parallel connection has the advantages of reducing the output current ripple and reducing the loss. The simulation experiment of the whole charging circuit is carried out by software, and the result is in line with the design requirements of the system. Finally combining the soft with hardware circuit to achieve charging of the system according to the requirements, experimental platform proved the feasibility and effectiveness of the proposed predictive control algorithm based on the car charging of the system, which is consistent with the simulation results.

Reset Tree-Based Optical Fault Detection

PubMed Central

Lee, Dong-Geon; Choi, Dooho; Seo, Jungtaek; Kim, Howon

2013-01-01

In this paper, we present a new reset tree-based scheme to protect cryptographic hardware against optical fault injection attacks. As one of the most powerful invasive attacks on cryptographic hardware, optical fault attacks cause semiconductors to misbehave by injecting high-energy light into a decapped integrated circuit. The contaminated result from the affected chip is then used to reveal secret information, such as a key, from the cryptographic hardware. Since the advent of such attacks, various countermeasures have been proposed. Although most of these countermeasures are strong, there is still the possibility of attack. In this paper, we present a novel optical fault detection scheme that utilizes the buffers on a circuit's reset signal tree as a fault detection sensor. To evaluate our proposal, we model radiation-induced currents into circuit components and perform a SPICE simulation. The proposed scheme is expected to be used as a supplemental security tool. PMID:23698267

Power Efficient Hardware Architecture of SHA-1 Algorithm for Trusted Mobile Computing

NASA Astrophysics Data System (ADS)

Kim, Mooseop; Ryou, Jaecheol

The Trusted Mobile Platform (TMP) is developed and promoted by the Trusted Computing Group (TCG), which is an industry standard body to enhance the security of the mobile computing environment. The built-in SHA-1 engine in TMP is one of the most important circuit blocks and contributes the performance of the whole platform because it is used as key primitives supporting platform integrity and command authentication. Mobile platforms have very stringent limitations with respect to available power, physical circuit area, and cost. Therefore special architecture and design methods for low power SHA-1 circuit are required. In this paper, we present a novel and efficient hardware architecture of low power SHA-1 design for TMP. Our low power SHA-1 hardware can compute 512-bit data block using less than 7,000 gates and has a power consumption about 1.1 mA on a 0.25μm CMOS process.

Trustworthy data collection from implantable medical devices via high-speed security implementation based on IEEE 1363.

PubMed

Hu, Fei; Hao, Qi; Lukowiak, Marcin; Sun, Qingquan; Wilhelm, Kyle; Radziszowski, Stanisław; Wu, Yao

2010-11-01

Implantable medical devices (IMDs) have played an important role in many medical fields. Any failure in IMDs operations could cause serious consequences and it is important to protect the IMDs access from unauthenticated access. This study investigates secure IMD data collection within a telehealthcare [mobile health (m-health)] network. We use medical sensors carried by patients to securely access IMD data and perform secure sensor-to-sensor communications between patients to relay the IMD data to a remote doctor's server. To meet the requirements on low computational complexity, we choose N-th degree truncated polynomial ring (NTRU)-based encryption/decryption to secure IMD-sensor and sensor-sensor communications. An extended matryoshkas model is developed to estimate direct/indirect trust relationship among sensors. An NTRU hardware implementation in very large integrated circuit hardware description language is studied based on industry Standard IEEE 1363 to increase the speed of key generation. The performance analysis results demonstrate the security robustness of the proposed IMD data access trust model.

Description and Simulation of a Fast Packet Switch Architecture for Communication Satellites

NASA Technical Reports Server (NTRS)

Quintana, Jorge A.; Lizanich, Paul J.

1995-01-01

The NASA Lewis Research Center has been developing the architecture for a multichannel communications signal processing satellite (MCSPS) as part of a flexible, low-cost meshed-VSAT (very small aperture terminal) network. The MCSPS architecture is based on a multifrequency, time-division-multiple-access (MF-TDMA) uplink and a time-division multiplex (TDM) downlink. There are eight uplink MF-TDMA beams, and eight downlink TDM beams, with eight downlink dwells per beam. The information-switching processor, which decodes, stores, and transmits each packet of user data to the appropriate downlink dwell onboard the satellite, has been fully described by using VHSIC (Very High Speed Integrated-Circuit) Hardware Description Language (VHDL). This VHDL code, which was developed in-house to simulate the information switching processor, showed that the architecture is both feasible and viable. This paper describes a shared-memory-per-beam architecture, its VHDL implementation, and the simulation efforts.

Assessment of Systematic Measurement Errors for Acoustic Travel-Time Tomography of the Atmosphere

DTIC Science & Technology

2013-01-01

measurements include assess- ment of the time delays in electronic circuits and mechanical hardware (e.g., drivers and microphones) of a tomography array ...hardware and electronic circuits of the tomography array and errors in synchronization of the transmitted and recorded signals. For example, if...coordinates can be as large as 30 cm. These errors are equivalent to the systematic errors in the travel times of 0.9 ms. Third, loudspeakers which are used

Deterrence of device counterfeiting, cloning, and subversion by substitution using hardware fingerprinting

DOEpatents

Hamlet, Jason R; Bauer, Todd M; Pierson, Lyndon G

2014-09-30

Deterrence of device subversion by substitution may be achieved by including a cryptographic fingerprint unit within a computing device for authenticating a hardware platform of the computing device. The cryptographic fingerprint unit includes a physically unclonable function ("PUF") circuit disposed in or on the hardware platform. The PUF circuit is used to generate a PUF value. A key generator is coupled to generate a private key and a public key based on the PUF value while a decryptor is coupled to receive an authentication challenge posed to the computing device and encrypted with the public key and coupled to output a response to the authentication challenge decrypted with the private key.

A hardware experimental platform for neural circuits in the auditory cortex

NASA Astrophysics Data System (ADS)

Rodellar-Biarge, Victoria; García-Dominguez, Pablo; Ruiz-Rizaldos, Yago; Gómez-Vilda, Pedro

2011-05-01

Speech processing in the human brain is a very complex process far from being fully understood although much progress has been done recently. Neuromorphic Speech Processing is a new research orientation in bio-inspired systems approach to find solutions to automatic treatment of specific problems (recognition, synthesis, segmentation, diarization, etc) which can not be adequately solved using classical algorithms. In this paper a neuromorphic speech processing architecture is presented. The systematic bottom-up synthesis of layered structures reproduce the dynamic feature detection of speech related to plausible neural circuits which work as interpretation centres located in the Auditory Cortex. The elementary model is based on Hebbian neuron-like units. For the computation of the architecture a flexible framework is proposed in the environment of Matlab®/Simulink®/HDL, which allows building models in different description styles, complexity and implementation levels. It provides a flexible platform for experimenting on the influence of the number of neurons and interconnections, in the precision of the results and in performance evaluation. The experimentation with different architecture configurations may help both in better understanding how neural circuits may work in the brain as well as in how speech processing can benefit from this understanding.

Parameterized hardware description as object oriented hardware model implementation

NASA Astrophysics Data System (ADS)

Drabik, Pawel K.

2010-09-01

The paper introduces novel model for design, visualization and management of complex, highly adaptive hardware systems. The model settles component oriented environment for both hardware modules and software application. It is developed on parameterized hardware description research. Establishment of stable link between hardware and software, as a purpose of designed and realized work, is presented. Novel programming framework model for the environment, named Graphic-Functional-Components is presented. The purpose of the paper is to present object oriented hardware modeling with mentioned features. Possible model implementation in FPGA chips and its management by object oriented software in Java is described.

Hardware accuracy counters for application precision and quality feedback

DOE Office of Scientific and Technical Information (OSTI.GOV)

de Paula Rosa Piga, Leonardo; Majumdar, Abhinandan; Paul, Indrani

Methods, devices, and systems for capturing an accuracy of an instruction executing on a processor. An instruction may be executed on the processor, and the accuracy of the instruction may be captured using a hardware counter circuit. The accuracy of the instruction may be captured by analyzing bits of at least one value of the instruction to determine a minimum or maximum precision datatype for representing the field, and determining whether to adjust a value of the hardware counter circuit accordingly. The representation may be output to a debugger or logfile for use by a developer, or may be outputmore » to a runtime or virtual machine to automatically adjust instruction precision or gating of portions of the processor datapath.« less

Rapid prototyping of update algorithm of discrete Fourier transform for real-time signal processing

NASA Astrophysics Data System (ADS)

Kakad, Yogendra P.; Sherlock, Barry G.; Chatapuram, Krishnan V.; Bishop, Stephen

2001-10-01

An algorithm is developed in the companion paper, to update the existing DFT to represent the new data series that results when a new signal point is received. Updating the DFT in this way uses less computation than directly evaluating the DFT using the FFT algorithm, This reduces the computational order by a factor of log2 N. The algorithm is able to work in the presence of data window function, for use with rectangular window, the split triangular, Hanning, Hamming, and Blackman windows. In this paper, a hardware implementation of this algorithm, using FPGA technology, is outlined. Unlike traditional fully customized VLSI circuits, FPGAs represent a technical break through in the corresponding industry. The FPGA implements thousands of gates of logic in a single IC chip and it can be programmed by users at their site in a few seconds or less depending on the type of device used. The risk is low and the development time is short. The advantages have made FPGAs very popular for rapid prototyping of algorithms in the area of digital communication, digital signal processing, and image processing. Our paper addresses the related issues of implementation using hardware descriptive language in the development of the design and the subsequent downloading on the programmable hardware chip.

EHWPACK: An evolvable hardware environment using the SPICE simulator and the Field Programmable Transistor Array

NASA Technical Reports Server (NTRS)

Keymeulen, D.; Klimeck, G.; Zebulum, R.; Stoica, A.; Jin, Y.; Lazaro, C.

2000-01-01

This paper describes the EHW development system, a tool that performs the evolutionary synthesis of electronic circuits, using the SPICE simulator and the Field Programmable Transistor Array hardware (FPTA) developed at JPL.

Computer hardware description languages - A tutorial

NASA Technical Reports Server (NTRS)

Shiva, S. G.

1979-01-01

The paper introduces hardware description languages (HDL) as useful tools for hardware design and documentation. The capabilities and limitations of HDLs are discussed along with the guidelines needed in selecting an appropriate HDL. The directions for future work are provided and attention is given to the implementation of HDLs in microcomputers.

A behavioral-level HDL description of SFQ logic circuits for quantitative performance analysis of large-scale SFQ digital systems

NASA Astrophysics Data System (ADS)

Matsuzaki, F.; Yoshikawa, N.; Tanaka, M.; Fujimaki, A.; Takai, Y.

2003-10-01

Recently many single flux quantum (SFQ) logic circuits containing several thousands of Josephson junctions have been designed successfully by using digital domain simulation based on the hard ware description language (HDL). In the present HDL-based design of SFQ circuits, a structure-level HDL description has been used, where circuits are made up of basic gate cells. However, in order to analyze large-scale SFQ digital systems, such as a microprocessor, more higher-level circuit abstraction is necessary to reduce the circuit simulation time. In this paper we have investigated the way to describe functionality of the large-scale SFQ digital circuits by a behavior-level HDL description. In this method, the functionality and the timing of the circuit block is defined directly by describing their behavior by the HDL. Using this method, we can dramatically reduce the simulation time of large-scale SFQ digital circuits.

Design and Development of Multi-Purpose CCD Camera System with Thermoelectric Cooling: Hardware

NASA Astrophysics Data System (ADS)

Kang, Y.-W.; Byun, Y. I.; Rhee, J. H.; Oh, S. H.; Kim, D. K.

2007-12-01

We designed and developed a multi-purpose CCD camera system for three kinds of CCDs; KAF-0401E(768×512), KAF-1602E(1536×1024), KAF-3200E(2184×1472) made by KODAK Co.. The system supports fast USB port as well as parallel port for data I/O and control signal. The packing is based on two stage circuit boards for size reduction and contains built-in filter wheel. Basic hardware components include clock pattern circuit, A/D conversion circuit, CCD data flow control circuit, and CCD temperature control unit. The CCD temperature can be controlled with accuracy of approximately 0.4° C in the max. range of temperature, Δ 33° C. This CCD camera system has with readout noise 6 e^{-}, and system gain 5 e^{-}/ADU. A total of 10 CCD camera systems were produced and our tests show that all of them show passable performance.

Global synchronization of parallel processors using clock pulse width modulation

DOEpatents

Chen, Dong; Ellavsky, Matthew R.; Franke, Ross L.; Gara, Alan; Gooding, Thomas M.; Haring, Rudolf A.; Jeanson, Mark J.; Kopcsay, Gerard V.; Liebsch, Thomas A.; Littrell, Daniel; Ohmacht, Martin; Reed, Don D.; Schenck, Brandon E.; Swetz, Richard A.

2013-04-02

A circuit generates a global clock signal with a pulse width modification to synchronize processors in a parallel computing system. The circuit may include a hardware module and a clock splitter. The hardware module may generate a clock signal and performs a pulse width modification on the clock signal. The pulse width modification changes a pulse width within a clock period in the clock signal. The clock splitter may distribute the pulse width modified clock signal to a plurality of processors in the parallel computing system.

On two new trends in evolvable hardware: employment of HDL-based structuring, and design of multi-functional circuits

NASA Technical Reports Server (NTRS)

Stoica, A.; Keymeulen, D.; Zebulum, R. S.; Ferguson, M. I.; Guo, X.

2002-01-01

This paper comments on some directions of growth for evolvable hardware, proposes research directions that address the scalability problem and gives examples of results in novel areas approached by EHW.

Super-Resolution in Plenoptic Cameras Using FPGAs

PubMed Central

Pérez, Joel; Magdaleno, Eduardo; Pérez, Fernando; Rodríguez, Manuel; Hernández, David; Corrales, Jaime

2014-01-01

Plenoptic cameras are a new type of sensor that extend the possibilities of current commercial cameras allowing 3D refocusing or the capture of 3D depths. One of the limitations of plenoptic cameras is their limited spatial resolution. In this paper we describe a fast, specialized hardware implementation of a super-resolution algorithm for plenoptic cameras. The algorithm has been designed for field programmable graphic array (FPGA) devices using VHDL (very high speed integrated circuit (VHSIC) hardware description language). With this technology, we obtain an acceleration of several orders of magnitude using its extremely high-performance signal processing capability through parallelism and pipeline architecture. The system has been developed using generics of the VHDL language. This allows a very versatile and parameterizable system. The system user can easily modify parameters such as data width, number of microlenses of the plenoptic camera, their size and shape, and the super-resolution factor. The speed of the algorithm in FPGA has been successfully compared with the execution using a conventional computer for several image sizes and different 3D refocusing planes. PMID:24841246

Embedded Hyperchaotic Generators: A Comparative Analysis

NASA Astrophysics Data System (ADS)

Sadoudi, Said; Tanougast, Camel; Azzaz, Mohamad Salah; Dandache, Abbas

In this paper, we present a comparative analysis of FPGA implementation performances, in terms of throughput and resources cost, of five well known autonomous continuous hyperchaotic systems. The goal of this analysis is to identify the embedded hyperchaotic generator which leads to designs with small logic area cost, satisfactory throughput rates, low power consumption and low latency required for embedded applications such as secure digital communications between embedded systems. To implement the four-dimensional (4D) chaotic systems, we use a new structural hardware architecture based on direct VHDL description of the forth order Runge-Kutta method (RK-4). The comparative analysis shows that the hyperchaotic Lorenz generator provides attractive performances compared to that of others. In fact, its hardware implementation requires only 2067 CLB-slices, 36 multipliers and no block RAMs, and achieves a throughput rate of 101.6 Mbps, at the output of the FPGA circuit, at a clock frequency of 25.315 MHz with a low latency time of 316 ns. Consequently, these good implementation performances offer to the embedded hyperchaotic Lorenz generator the advantage of being the best candidate for embedded communications applications.

Super-resolution in plenoptic cameras using FPGAs.

PubMed

Pérez, Joel; Magdaleno, Eduardo; Pérez, Fernando; Rodríguez, Manuel; Hernández, David; Corrales, Jaime

2014-05-16

Plenoptic cameras are a new type of sensor that extend the possibilities of current commercial cameras allowing 3D refocusing or the capture of 3D depths. One of the limitations of plenoptic cameras is their limited spatial resolution. In this paper we describe a fast, specialized hardware implementation of a super-resolution algorithm for plenoptic cameras. The algorithm has been designed for field programmable graphic array (FPGA) devices using VHDL (very high speed integrated circuit (VHSIC) hardware description language). With this technology, we obtain an acceleration of several orders of magnitude using its extremely high-performance signal processing capability through parallelism and pipeline architecture. The system has been developed using generics of the VHDL language. This allows a very versatile and parameterizable system. The system user can easily modify parameters such as data width, number of microlenses of the plenoptic camera, their size and shape, and the super-resolution factor. The speed of the algorithm in FPGA has been successfully compared with the execution using a conventional computer for several image sizes and different 3D refocusing planes.

Interchange of electronic design through VHDL and EIS

NASA Technical Reports Server (NTRS)

Wallace, Richard M.

1987-01-01

The need for both robust and unambiguous electronic designs is a direct requirement of the astonishing growth in design and manufacturing capability during recent years. In order to manage the plethora of designs, and have the design data both interchangeable and interoperable, the Very High Speed Integrated Circuits (VHSIC) program is developing two major standards for the electronic design community. The VHSIC Hardware Description Language (VHDL) is designed to be the lingua franca for transmission of design data between designers and their environments. The Engineering Information System (EIS) is designed to ease the integration of data betweeen diverse design automation systems. This paper describes the rationale for the necessity for these two standards and how they provide a synergistic expressive capability across the macrocosm of design environments.

Single Event Effect Hardware Trojans with Remote Activation

DTIC Science & Technology

2017-03-01

kinetically as in the SDI approach. These high-energy directed energy weapons have been studied and developed largely for the purpose remote sensing and...Single Event Effect Hardware Trojans with Remote Activation Paul A. Quintana; John McCollum; William A. Hill Microsemi Corporation, San Jose...space qualified semiconductors the use of SEE sensitive circuits may represents a latent and remotely -triggered hardware Trojan which would be

Hardware Evolution of Closed-Loop Controller Designs

NASA Technical Reports Server (NTRS)

Gwaltney, David; Ferguson, Ian

2002-01-01

Poster presentation will outline on-going efforts at NASA, MSFC to employ various Evolvable Hardware experimental platforms in the evolution of digital and analog circuitry for application to automatic control. Included will be information concerning the application of commercially available hardware and software along with the use of the JPL developed FPTA2 integrated circuit and supporting JPL developed software. Results to date will be presented.

Hardening Logic Encryption against Key Extraction Attacks with Circuit Camouflage

DTIC Science & Technology

2017-03-01

camouflage; obfuscation; SAT; key extraction; reverse engineering; security; trusted electronics Introduction Integrated Circuit (IC) designs are...Encryption Algorithms”, Hardware Oriented Security and Trust , 2015. 3. Rajendran J., Pino, Y., Sinanoglu, O., Karri, R., “Security Analysis of Logic

Long life assurance study for manned spacecraft long life hardware. Volume 2: Long life assurance studies of EEE parts and packaging

NASA Technical Reports Server (NTRS)

1972-01-01

Guidelines for the design, development, and fabrication of electronic components and circuits for use in spacecraft construction are presented. The subjects discussed involve quality control procedures and test methodology for the following subjects: (1) monolithic integrated circuits, (2) hybrid integrated circuits, (3) transistors, (4) diodes, (5) tantalum capacitors, (6) electromechanical relays, (7) switches and circuit breakers, and (8) electronic packaging.

Fault Detection, Isolation and Recovery (FDIR) Portable Liquid Oxygen Hardware Demonstrator

NASA Technical Reports Server (NTRS)

Oostdyk, Rebecca L.; Perotti, Jose M.

2011-01-01

The Fault Detection, Isolation and Recovery (FDIR) hardware demonstration will highlight the effort being conducted by Constellation's Ground Operations (GO) to provide the Launch Control System (LCS) with system-level health management during vehicle processing and countdown activities. A proof-of-concept demonstration of the FDIR prototype established the capability of the software to provide real-time fault detection and isolation using generated Liquid Hydrogen data. The FDIR portable testbed unit (presented here) aims to enhance FDIR by providing a dynamic simulation of Constellation subsystems that feed the FDIR software live data based on Liquid Oxygen system properties. The LO2 cryogenic ground system has key properties that are analogous to the properties of an electronic circuit. The LO2 system is modeled using electrical components and an equivalent circuit is designed on a printed circuit board to simulate the live data. The portable testbed is also be equipped with data acquisition and communication hardware to relay the measurements to the FDIR application running on a PC. This portable testbed is an ideal capability to perform FDIR software testing, troubleshooting, training among others.

A soft decoding algorithm and hardware implementation for the visual prosthesis based on high order soft demodulation.

PubMed

Yang, Yuan; Quan, Nannan; Bu, Jingjing; Li, Xueping; Yu, Ningmei

2016-09-26

High order modulation and demodulation technology can solve the frequency requirement between the wireless energy transmission and data communication. In order to achieve reliable wireless data communication based on high order modulation technology for visual prosthesis, this work proposed a Reed-Solomon (RS) error correcting code (ECC) circuit on the basis of differential amplitude and phase shift keying (DAPSK) soft demodulation. Firstly, recognizing the weakness of the traditional DAPSK soft demodulation algorithm based on division that is complex for hardware implementation, an improved phase soft demodulation algorithm for visual prosthesis to reduce the hardware complexity is put forward. Based on this new algorithm, an improved RS soft decoding method is hence proposed. In this new decoding method, the combination of Chase algorithm and hard decoding algorithms is used to achieve soft decoding. In order to meet the requirements of implantable visual prosthesis, the method to calculate reliability of symbol-level based on multiplication of bit reliability is derived, which reduces the testing vectors number of Chase algorithm. The proposed algorithms are verified by MATLAB simulation and FPGA experimental results. During MATLAB simulation, the biological channel attenuation property model is added into the ECC circuit. The data rate is 8 Mbps in the MATLAB simulation and FPGA experiments. MATLAB simulation results show that the improved phase soft demodulation algorithm proposed in this paper saves hardware resources without losing bit error rate (BER) performance. Compared with the traditional demodulation circuit, the coding gain of the ECC circuit has been improved by about 3 dB under the same BER of [Formula: see text]. The FPGA experimental results show that under the condition of data demodulation error with wireless coils 3 cm away, the system can correct it. The greater the distance, the higher the BER. Then we use a bit error rate analyzer to measure BER of the demodulation circuit and the RS ECC circuit with different distance of two coils. And the experimental results show that the RS ECC circuit has about an order of magnitude lower BER than the demodulation circuit when under the same coils distance. Therefore, the RS ECC circuit has more higher reliability of the communication in the system. The improved phase soft demodulation algorithm and soft decoding algorithm proposed in this paper enables data communication that is more reliable than other demodulation system, which also provide a significant reference for further study to the visual prosthesis system.

Comparison between Frame-Constrained Fix-Pixel-Value and Frame-Free Spiking-Dynamic-Pixel ConvNets for Visual Processing

PubMed Central

Farabet, Clément; Paz, Rafael; Pérez-Carrasco, Jose; Zamarreño-Ramos, Carlos; Linares-Barranco, Alejandro; LeCun, Yann; Culurciello, Eugenio; Serrano-Gotarredona, Teresa; Linares-Barranco, Bernabe

2012-01-01

Most scene segmentation and categorization architectures for the extraction of features in images and patches make exhaustive use of 2D convolution operations for template matching, template search, and denoising. Convolutional Neural Networks (ConvNets) are one example of such architectures that can implement general-purpose bio-inspired vision systems. In standard digital computers 2D convolutions are usually expensive in terms of resource consumption and impose severe limitations for efficient real-time applications. Nevertheless, neuro-cortex inspired solutions, like dedicated Frame-Based or Frame-Free Spiking ConvNet Convolution Processors, are advancing real-time visual processing. These two approaches share the neural inspiration, but each of them solves the problem in different ways. Frame-Based ConvNets process frame by frame video information in a very robust and fast way that requires to use and share the available hardware resources (such as: multipliers, adders). Hardware resources are fixed- and time-multiplexed by fetching data in and out. Thus memory bandwidth and size is important for good performance. On the other hand, spike-based convolution processors are a frame-free alternative that is able to perform convolution of a spike-based source of visual information with very low latency, which makes ideal for very high-speed applications. However, hardware resources need to be available all the time and cannot be time-multiplexed. Thus, hardware should be modular, reconfigurable, and expansible. Hardware implementations in both VLSI custom integrated circuits (digital and analog) and FPGA have been already used to demonstrate the performance of these systems. In this paper we present a comparison study of these two neuro-inspired solutions. A brief description of both systems is presented and also discussions about their differences, pros and cons. PMID:22518097

Comparison between Frame-Constrained Fix-Pixel-Value and Frame-Free Spiking-Dynamic-Pixel ConvNets for Visual Processing.

PubMed

Farabet, Clément; Paz, Rafael; Pérez-Carrasco, Jose; Zamarreño-Ramos, Carlos; Linares-Barranco, Alejandro; Lecun, Yann; Culurciello, Eugenio; Serrano-Gotarredona, Teresa; Linares-Barranco, Bernabe

2012-01-01

Most scene segmentation and categorization architectures for the extraction of features in images and patches make exhaustive use of 2D convolution operations for template matching, template search, and denoising. Convolutional Neural Networks (ConvNets) are one example of such architectures that can implement general-purpose bio-inspired vision systems. In standard digital computers 2D convolutions are usually expensive in terms of resource consumption and impose severe limitations for efficient real-time applications. Nevertheless, neuro-cortex inspired solutions, like dedicated Frame-Based or Frame-Free Spiking ConvNet Convolution Processors, are advancing real-time visual processing. These two approaches share the neural inspiration, but each of them solves the problem in different ways. Frame-Based ConvNets process frame by frame video information in a very robust and fast way that requires to use and share the available hardware resources (such as: multipliers, adders). Hardware resources are fixed- and time-multiplexed by fetching data in and out. Thus memory bandwidth and size is important for good performance. On the other hand, spike-based convolution processors are a frame-free alternative that is able to perform convolution of a spike-based source of visual information with very low latency, which makes ideal for very high-speed applications. However, hardware resources need to be available all the time and cannot be time-multiplexed. Thus, hardware should be modular, reconfigurable, and expansible. Hardware implementations in both VLSI custom integrated circuits (digital and analog) and FPGA have been already used to demonstrate the performance of these systems. In this paper we present a comparison study of these two neuro-inspired solutions. A brief description of both systems is presented and also discussions about their differences, pros and cons.

Analog hardware for delta-backpropagation neural networks

NASA Technical Reports Server (NTRS)

Eberhardt, Silvio P. (Inventor)

1992-01-01

This is a fully parallel analog backpropagation learning processor which comprises a plurality of programmable resistive memory elements serving as synapse connections whose values can be weighted during learning with buffer amplifiers, summing circuits, and sample-and-hold circuits arranged in a plurality of neuron layers in accordance with delta-backpropagation algorithms modified so as to control weight changes due to circuit drift.

Controlling system for smart hyper-spectral imaging array based on liquid-crystal Fabry-Perot device

NASA Astrophysics Data System (ADS)

Jiang, Xue; Chen, Xin; Rong, Xin; Liu, Kan; Zhang, Xinyu; Ji, An; Xie, Changsheng

2011-11-01

A research for developing a kind of smart spectral imaging detection technique based on the electrically tunable liquidcrystal (LC) FP structure is launched. It has some advantages of low cost, highly compact integration, perfuming wavelength selection without moving any micro-mirror of FP device, and the higher reliability and stability. The controlling system for hyper-spectral imaging array based on LC-FP device includes mainly a MSP430F5438 as its core. Considering the characteristics of LC-FP device, the controlling system can provide a driving signal of 1-10 kHz and 0- 30Vrms for the device in a static driving mode. This paper introduces the hardware designing of the control system in detail. It presents an overall hardware solutions including: (1) the MSP430 controlling circuit, and (2) the operational amplifier circuit, and (3) the power supply circuit, and (4) the AD conversion circuit. The techniques for the realization of special high speed digital circuits, which is necessary for the PCB employed, is also discussed.

An educational laboratory virtual instrumentation suite assisted experiment for studying fundamentals of series resistance-inductance-capacitance circuit

NASA Astrophysics Data System (ADS)

Rana, K. P. S.; Kumar, Vineet; Mendiratta, Jatin

2017-11-01

One of the most elementary concepts in freshmen Electrical Engineering subject comprises the Resistance-Inductance-Capacitance (RLC) circuit fundamentals, that is, their time and frequency domain responses. For a beginner, generally, it is difficult to understand and appreciate the step and the frequency responses, particularly the resonance. This paper proposes a student-friendly teaching and learning approach by inculcating the multifaceted versatile software LabVIEWTM along with the educational laboratory virtual instrumentation suite hardware, for studying the RLC circuit time and frequency domain responses. The proposed approach has offered an interactive laboratory experiment where students can model circuits in simulation and hardware circuits on prototype board, and then compare their performances. The theoretical simulations and the obtained experimental data are found to be in very close agreement, thereby enhancing the conviction of students. Finally, the proposed methodology was also subjected to the assessment of learning outcomes based on student feedback, and an average score of 8.05 out of 10 with a standard deviation of 0.471 was received, indicating the overall satisfaction of the students.

Strange non-chaotic attractors in a state controlled-cellular neural network-based quasiperiodically forced MLC circuit

NASA Astrophysics Data System (ADS)

Ezhilarasu, P. Megavarna; Inbavalli, M.; Murali, K.; Thamilmaran, K.

2018-07-01

In this paper, we report the dynamical transitions to strange non-chaotic attractors in a quasiperiodically forced state controlled-cellular neural network (SC-CNN)-based MLC circuit via two different mechanisms, namely the Heagy-Hammel route and the gradual fractalisation route. These transitions were observed through numerical simulations and hardware experiments and confirmed using statistical tools, such as maximal Lyapunov exponent spectrum and its variance and singular continuous spectral analysis. We find that there is a remarkable agreement of the results from both numerical simulations as well as from hardware experiments.

Department of the Air Force Information Technology Program FY 95 President’s Budget

DTIC Science & Technology

1994-03-01

2095 2200 552 900 1032 Description: Contractor hardware maintenan support, systems analyst support software development and maintenance, and off -the...hardware maintenance support, systems analyst support, operations support, configuration management, test support, and off -the-shelf software license...2419 2505 2594 Description: Contractor hardware maintenance support, systems analyst support, operations support, and off -the-shelf software license

Control theory meets synthetic biology

PubMed Central

2016-01-01

The past several years have witnessed an increased presence of control theoretic concepts in synthetic biology. This review presents an organized summary of how these control design concepts have been applied to tackle a variety of problems faced when building synthetic biomolecular circuits in living cells. In particular, we describe success stories that demonstrate how simple or more elaborate control design methods can be used to make the behaviour of synthetic genetic circuits within a single cell or across a cell population more reliable, predictable and robust to perturbations. The description especially highlights technical challenges that uniquely arise from the need to implement control designs within a new hardware setting, along with implemented or proposed solutions. Some engineering solutions employing complex feedback control schemes are also described, which, however, still require a deeper theoretical analysis of stability, performance and robustness properties. Overall, this paper should help synthetic biologists become familiar with feedback control concepts as they can be used in their application area. At the same time, it should provide some domain knowledge to control theorists who wish to enter the rising and exciting field of synthetic biology. PMID:27440256

Control theory meets synthetic biology.

PubMed

Del Vecchio, Domitilla; Dy, Aaron J; Qian, Yili

2016-07-01

The past several years have witnessed an increased presence of control theoretic concepts in synthetic biology. This review presents an organized summary of how these control design concepts have been applied to tackle a variety of problems faced when building synthetic biomolecular circuits in living cells. In particular, we describe success stories that demonstrate how simple or more elaborate control design methods can be used to make the behaviour of synthetic genetic circuits within a single cell or across a cell population more reliable, predictable and robust to perturbations. The description especially highlights technical challenges that uniquely arise from the need to implement control designs within a new hardware setting, along with implemented or proposed solutions. Some engineering solutions employing complex feedback control schemes are also described, which, however, still require a deeper theoretical analysis of stability, performance and robustness properties. Overall, this paper should help synthetic biologists become familiar with feedback control concepts as they can be used in their application area. At the same time, it should provide some domain knowledge to control theorists who wish to enter the rising and exciting field of synthetic biology. © 2016 The Author(s).

Hardware Evolution of Analog Speed Controllers for a DC Motor

NASA Technical Reports Server (NTRS)

Gwaltney, David A.; Ferguson, Michael I.

2003-01-01

Evolvable hardware provides the capability to evolve analog circuits to produce amplifier and filter functions. Conventional analog controller designs employ these same functions. Analog controllers for the control of the shaft speed of a DC motor are evolved on an evolvable hardware platform utilizing a Field Programmable Transistor Array (FPTA). The performance of these evolved controllers is compared to that of a conventional proportional-integral (PI) controller.

Design of a signal conditioner for the Fermilab Magnet Test Facility

DOE Office of Scientific and Technical Information (OSTI.GOV)

Giannelli, Pietro

2012-01-01

This thesis describes the design of a remotely-programmable signal conditioner for the harmonic measurement of accelerator magnets. A 10-channel signal conditioning circuit featuring bucking capabilities was designed from scratch and implemented to the level of the printed circuit board layout. Other system components were chosen from those available on the market. Software design was started with the definition of routine procedures. This thesis is part of an upgrade project for replacing obsolescent automated test equipment belonging to the Fermilab Magnet Test Facility. The design started with a given set of requirements. Using a top-down approach, all the circuits were designedmore » and their expected performances were theoretically predicted and simulated. A limited prototyping phase followed. The printed circuit boards were laid out and routed using a CAD software and focusing the design on maximum electromagnetic interference immunity. An embedded board was selected for controlling and interfacing the signal conditioning circuitry with the instrumentation network. Basic low level routines for hardware access were defined. This work covered the entire design process of the signal conditioner, resulting in a project ready for manufacturing. The expected performances are in line with the requirements and, in the cases where this was not possible, approval of trade-offs was sought and received from the end users. Part I deals with the global structure of the signal conditioner and the subdivision in functional macro-blocks. Part II treats the hardware design phase in detail, covering the analog and digital circuits, the printed circuit layouts, the embedded controller and the power supply selection. Part III deals with the basic hardware-related routines to be implemented in the final software.« less

DATAS Hardware Diagnostic Tests

DOT National Transportation Integrated Search

1990-10-01

This document is reference material for personnel using the Data Link and : Analysis System (DATAS) for hardware diagnostic testing. Included in this : document is a brief overall description of the DATAS, and a thorough : description of how to opera...

Accelerating artificial intelligence with reconfigurable computing

NASA Astrophysics Data System (ADS)

Cieszewski, Radoslaw

Reconfigurable computing is emerging as an important area of research in computer architectures and software systems. Many algorithms can be greatly accelerated by placing the computationally intense portions of an algorithm into reconfigurable hardware. Reconfigurable computing combines many benefits of both software and ASIC implementations. Like software, the mapped circuit is flexible, and can be changed over the lifetime of the system. Similar to an ASIC, reconfigurable systems provide a method to map circuits into hardware. Reconfigurable systems therefore have the potential to achieve far greater performance than software as a result of bypassing the fetch-decode-execute operations of traditional processors, and possibly exploiting a greater level of parallelism. Such a field, where there is many different algorithms which can be accelerated, is an artificial intelligence. This paper presents example hardware implementations of Artificial Neural Networks, Genetic Algorithms and Expert Systems.

Supervised Learning Using Spike-Timing-Dependent Plasticity of Memristive Synapses.

PubMed

Nishitani, Yu; Kaneko, Yukihiro; Ueda, Michihito

2015-12-01

We propose a supervised learning model that enables error backpropagation for spiking neural network hardware. The method is modeled by modifying an existing model to suit the hardware implementation. An example of a network circuit for the model is also presented. In this circuit, a three-terminal ferroelectric memristor (3T-FeMEM), which is a field-effect transistor with a gate insulator composed of ferroelectric materials, is used as an electric synapse device to store the analog synaptic weight. Our model can be implemented by reflecting the network error to the write voltage of the 3T-FeMEMs and introducing a spike-timing-dependent learning function to the device. An XOR problem was successfully demonstrated as a benchmark learning by numerical simulations using the circuit properties to estimate the learning performance. In principle, the learning time per step of this supervised learning model and the circuit is independent of the number of neurons in each layer, promising a high-speed and low-power calculation in large-scale neural networks.

Efficient architecture for spike sorting in reconfigurable hardware.

PubMed

Hwang, Wen-Jyi; Lee, Wei-Hao; Lin, Shiow-Jyu; Lai, Sheng-Ying

2013-11-01

This paper presents a novel hardware architecture for fast spike sorting. The architecture is able to perform both the feature extraction and clustering in hardware. The generalized Hebbian algorithm (GHA) and fuzzy C-means (FCM) algorithm are used for feature extraction and clustering, respectively. The employment of GHA allows efficient computation of principal components for subsequent clustering operations. The FCM is able to achieve near optimal clustering for spike sorting. Its performance is insensitive to the selection of initial cluster centers. The hardware implementations of GHA and FCM feature low area costs and high throughput. In the GHA architecture, the computation of different weight vectors share the same circuit for lowering the area costs. Moreover, in the FCM hardware implementation, the usual iterative operations for updating the membership matrix and cluster centroid are merged into one single updating process to evade the large storage requirement. To show the effectiveness of the circuit, the proposed architecture is physically implemented by field programmable gate array (FPGA). It is embedded in a System-on-Chip (SOC) platform for performance measurement. Experimental results show that the proposed architecture is an efficient spike sorting design for attaining high classification correct rate and high speed computation.

Flywheel-Powered Mobile X-Ray Generator.

DTIC Science & Technology

1983-03-18

38 Circuit Description .. . . . . . . . .. 40 0. Digital Tachometer Purpose . . . . . . . . . . . . . . . 47 Operation...47 Circuit Description . . . . . . . . o 47 E. High Tension Transfoner Purpose . . . . . . . . . . . . . . . 51 Operation... Circuit Purpose . . . . . . . . . . . . . . . 54 Operation . . . . . . . . . . . . . . 54 G. Tube Rotor Control Purpose ........ . 57 Operation of Timer

A software framework for pipelined arithmetic algorithms in field programmable gate arrays

NASA Astrophysics Data System (ADS)

Kim, J. B.; Won, E.

2018-03-01

Pipelined algorithms implemented in field programmable gate arrays are extensively used for hardware triggers in the modern experimental high energy physics field and the complexity of such algorithms increases rapidly. For development of such hardware triggers, algorithms are developed in C++, ported to hardware description language for synthesizing firmware, and then ported back to C++ for simulating the firmware response down to the single bit level. We present a C++ software framework which automatically simulates and generates hardware description language code for pipelined arithmetic algorithms.

Automatic Digital Hardware Synthesis

DTIC Science & Technology

1990-09-01

VHDL to PALASM, a hardware synthesis language. The PALASM description is then directly implemented into a field programmable gate array (FPGAI using...process of translating VHDL to PALASM, a hardware synthesis language. The PALASM description is then directly implemented into a field programmable gate...allows the engineer to use VHDL to create and validate a design, and then to implement it in a gate array. The development of software o translate VHDL

Electronics design of the airborne stabilized platform attitude acquisition module

NASA Astrophysics Data System (ADS)

Xu, Jiang; Wei, Guiling; Cheng, Yong; Li, Baolin; Bu, Hongyi; Wang, Hao; Zhang, Zhanwei; Li, Xingni

2014-02-01

We present an attitude acquisition module electronics design for the airborne stabilized platform. The design scheme, which is based on Integrated MEMS sensor ADIS16405, develops the attitude information processing algorithms and the hardware circuit. The hardware circuits with a small volume of only 44.9 x 43.6 x 24.6 mm3, has the characteristics of lightweight, modularization and digitalization. The interface design of the PC software uses the combination plane chart with track line to receive the attitude information and display. Attitude calculation uses the Kalman filtering algorithm to improve the measurement accuracy of the module in the dynamic environment.

Circuit Design Optimization Using Genetic Algorithm with Parameterized Uniform Crossover

NASA Astrophysics Data System (ADS)

Bao, Zhiguo; Watanabe, Takahiro

Evolvable hardware (EHW) is a new research field about the use of Evolutionary Algorithms (EAs) to construct electronic systems. EHW refers in a narrow sense to use evolutionary mechanisms as the algorithmic drivers for system design, while in a general sense to the capability of the hardware system to develop and to improve itself. Genetic Algorithm (GA) is one of typical EAs. We propose optimal circuit design by using GA with parameterized uniform crossover (GApuc) and with fitness function composed of circuit complexity, power, and signal delay. Parameterized uniform crossover is much more likely to distribute its disruptive trials in an unbiased manner over larger portions of the space, then it has more exploratory power than one and two-point crossover, so we have more chances of finding better solutions. Its effectiveness is shown by experiments. From the results, we can see that the best elite fitness, the average value of fitness of the correct circuits and the number of the correct circuits of GApuc are better than that of GA with one-point crossover or two-point crossover. The best case of optimal circuits generated by GApuc is 10.18% and 6.08% better in evaluating value than that by GA with one-point crossover and two-point crossover, respectively.

Efficacy of a Virtual Teaching Assistant in an Open Laboratory Environment for Electric Circuits

ERIC Educational Resources Information Center

Saleheen, Firdous; Wang, Zicong; Picone, Joseph; Butz, Brian P.; Won, Chang-Hee

2018-01-01

In order to provide an on-demand, open electrical engineering laboratory, we developed an innovative software-based Virtual Open Laboratory Teaching Assistant (VOLTA). This web-based virtual assistant provides laboratory instructions, equipment usage videos, circuit simulation assistance, and hardware implementation diagnostics. VOLTA allows…

FPGA implementation of self organizing map with digital phase locked loops.

PubMed

Hikawa, Hiroomi

2005-01-01

The self-organizing map (SOM) has found applicability in a wide range of application areas. Recently new SOM hardware with phase modulated pulse signal and digital phase-locked loops (DPLLs) has been proposed (Hikawa, 2005). The system uses the DPLL as a computing element since the operation of the DPLL is very similar to that of SOM's computation. The system also uses square waveform phase to hold the value of the each input vector element. This paper discuss the hardware implementation of the DPLL SOM architecture. For effective hardware implementation, some components are redesigned to reduce the circuit size. The proposed SOM architecture is described in VHDL and implemented on field programmable gate array (FPGA). Its feasibility is verified by experiments. Results show that the proposed SOM implemented on the FPGA has a good quantization capability, and its circuit size very small.

Functional test generation for digital circuits described with a declarative language: LUSTRE

NASA Astrophysics Data System (ADS)

Almahrous, Mazen

1990-08-01

A functional approach to the test generation problem starting from a high level description is proposed. The circuit tested is modeled, using the LUSTRE high level data flow description language. The different LUSTRE primitives are translated to a SATAN format graph in order to evaluate the testability of the circuit and to generate test sequences. Another method of testing the complex circuits comprising an operative part and a control part is defined. It consists of checking experiments for the control part observed through the operative part. It was applied to the automata generated from a LUSTRE description of the circuit.

Mechanically verified hardware implementing an 8-bit parallel IO Byzantine agreement processor

NASA Technical Reports Server (NTRS)

Moore, J. Strother

1992-01-01

Consider a network of four processors that use the Oral Messages (Byzantine Generals) Algorithm of Pease, Shostak, and Lamport to achieve agreement in the presence of faults. Bevier and Young have published a functional description of a single processor that, when interconnected appropriately with three identical others, implements this network under the assumption that the four processors step in synchrony. By formalizing the original Pease, et al work, Bevier and Young mechanically proved that such a network achieves fault tolerance. We develop, formalize, and discuss a hardware design that has been mechanically proven to implement their processor. In particular, we formally define mapping functions from the abstract state space of the Bevier-Young processor to a concrete state space of a hardware module and state a theorem that expresses the claim that the hardware correctly implements the processor. We briefly discuss the Brock-Hunt Formal Hardware Description Language which permits designs both to be proved correct with the Boyer-Moore theorem prover and to be expressed in a commercially supported hardware description language for additional electrical analysis and layout. We briefly describe our implementation.

Open-circuit respirometry: real-time, laboratory-based systems.

PubMed

Ward, Susan A

2018-05-04

This review explores the conceptual and technological factors integral to the development of laboratory-based, automated real-time open-circuit mixing-chamber and breath-by-breath (B × B) gas-exchange systems, together with considerations of assumptions and limitations. Advances in sensor technology, signal analysis, and digital computation led to the emergence of these technologies in the mid-20th century, at a time when investigators were beginning to recognise the interpretational advantages of nonsteady-state physiological-system interrogation in understanding the aetiology of exercise (in)tolerance in health, sport, and disease. Key milestones include the 'Auchincloss' description of an off-line system to estimate alveolar O 2 uptake B × B during exercise. This was followed by the first descriptions of real-time automated O 2 uptake and CO 2 output B × B measurement by Beaver and colleagues and by Linnarsson and Lindborg, and mixing-chamber measurement by Wilmore and colleagues. Challenges to both approaches soon emerged: e.g., the influence of mixing-chamber washout kinetics on mixed-expired gas concentration determination, and B × B alignment of gas-concentration signals with respired flow. The challenging algorithmic and technical refinements required for gas-exchange estimation at the alveolar level have also been extensively explored. In conclusion, while the technology (both hardware and software) underpinning real-time automated gas-exchange measurement has progressively advanced, there are still concerns regarding accuracy especially under the challenging conditions of changing metabolic rate.

Parallel reduced-instruction-set-computer architecture for real-time symbolic pattern matching

NASA Astrophysics Data System (ADS)

Parson, Dale E.

1991-03-01

This report discusses ongoing work on a parallel reduced-instruction- set-computer (RISC) architecture for automatic production matching. The PRIOPS compiler takes advantage of the memoryless character of automatic processing by translating a program's collection of automatic production tests into an equivalent combinational circuit-a digital circuit without memory, whose outputs are immediate functions of its inputs. The circuit provides a highly parallel, fine-grain model of automatic matching. The compiler then maps the combinational circuit onto RISC hardware. The heart of the processor is an array of comparators capable of testing production conditions in parallel, Each comparator attaches to private memory that contains virtual circuit nodes-records of the current state of nodes and busses in the combinational circuit. All comparator memories hold identical information, allowing simultaneous update for a single changing circuit node and simultaneous retrieval of different circuit nodes by different comparators. Along with the comparator-based logic unit is a sequencer that determines the current combination of production-derived comparisons to try, based on the combined success and failure of previous combinations of comparisons. The memoryless nature of automatic matching allows the compiler to designate invariant memory addresses for virtual circuit nodes, and to generate the most effective sequences of comparison test combinations. The result is maximal utilization of parallel hardware, indicating speed increases and scalability beyond that found for course-grain, multiprocessor approaches to concurrent Rete matching. Future work will consider application of this RISC architecture to the standard (controlled) Rete algorithm, where search through memory dominates portions of matching.

Integrated testing system FiTest for diagnosis of PCBA

NASA Astrophysics Data System (ADS)

Bogdan, Arkadiusz; Lesniak, Adam

2016-12-01

This article presents the innovative integrated testing system FiTest for automatic, quick inspection of printed circuit board assemblies (PCBA) manufactured in Surface Mount Technology (SMT). Integration of Automatic Optical Inspection (AOI), In-Circuit Tests (ICT) and Functional Circuit Tests (FCT) resulted in universal hardware platform for testing variety of electronic circuits. The platform provides increased test coverage, decreased level of false calls and optimization of test duration. The platform is equipped with powerful algorithms performing tests in a stable and repetitive way and providing effective management of diagnosis.

Hardware device binding and mutual authentication

DOEpatents

Hamlet, Jason R; Pierson, Lyndon G

2014-03-04

Detection and deterrence of device tampering and subversion by substitution may be achieved by including a cryptographic unit within a computing device for binding multiple hardware devices and mutually authenticating the devices. The cryptographic unit includes a physically unclonable function ("PUF") circuit disposed in or on the hardware device, which generates a binding PUF value. The cryptographic unit uses the binding PUF value during an enrollment phase and subsequent authentication phases. During a subsequent authentication phase, the cryptographic unit uses the binding PUF values of the multiple hardware devices to generate a challenge to send to the other device, and to verify a challenge received from the other device to mutually authenticate the hardware devices.

Testing Services

NASA Technical Reports Server (NTRS)

1993-01-01

Trace Laboratories is an independent testing laboratory specializing in testing printed circuit boards, automotive products and military hardware. Technical information from NASA Tech Briefs and two subsequent JPL Technical Support packages have assisted Trace in testing surface insulation resistance on printed circuit board materials. Testing time was reduced and customer service was improved because of Jet Propulsion Laboratory technical support packages.

Battery voltage-balancing applications of disk-type radial mode Pb(Zr • Ti)O3 ceramic resonator

NASA Astrophysics Data System (ADS)

Thenathayalan, Daniel; Lee, Chun-gu; Park, Joung-hu

2017-10-01

In this paper, we propose a novel technique to build a charge-balancing circuit for series-connected battery strings using various kinds of disk-type ceramic Pb(Zr • Ti)O3 piezoelectric resonators (PRs). The use of PRs replaces the whole external battery voltage-balancer circuit, which consists mainly of a bulky magnetic element. The proposed technique is validated using different ceramic PRs and the results are analyzed in terms of their physical properties. A series-connected battery string with a voltage rating of 61.5 V is set as a hardware prototype under test, then the power transfer efficiency of the system is measured at different imbalance voltages. The performance of the proposed battery voltage-balancer circuit employed with a PR is also validated through hardware implementation. Furthermore, the temperature distribution image of the PR is obtained to compare power transfer efficiency and thermal stress under different operating conditions. The test results show that the battery voltage-balancer circuit can be successfully implemented using PRs with the maximum power conversion efficiency of over 96% for energy storage systems.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chinthavali, Madhu Sudhan; Campbell, Steven L

This paper presents an analytical model for wireless power transfer system used in electric vehicle application. The equivalent circuit model for each major component of the system is described, including the input voltage source, resonant network, transformer, nonlinear diode rectifier load, etc. Based on the circuit model, the primary side compensation capacitance, equivalent input impedance, active / reactive power are calculated, which provides a guideline for parameter selection. Moreover, the voltage gain curve from dc output to dc input is derived as well. A hardware prototype with series-parallel resonant stage is built to verify the developed model. The experimental resultsmore » from the hardware are compared with the model predicted results to show the validity of the model.« less

Measuring the RC time constant with Arduino

NASA Astrophysics Data System (ADS)

Pereira, N. S. A.

2016-11-01

In this work we use the Arduino UNO R3 open source hardware platform to assemble an experimental apparatus for the measurement of the time constant of an RC circuit. With adequate programming, the Arduino is used as a signal generator, a data acquisition system and a basic signal visualisation tool. Theoretical calculations are compared with direct observations from an analogue oscilloscope. Data processing and curve fitting is performed on a spreadsheet. The results obtained for the six RC test circuits are within the expected interval of values defined by the tolerance of the components. The hardware and software prove to be adequate to the proposed measurements and therefore adaptable to a laboratorial teaching and learning context.

Hardware Design and Implementation of a Wavelet De-Noising Procedure for Medical Signal Preprocessing

PubMed Central

Chen, Szi-Wen; Chen, Yuan-Ho

2015-01-01

In this paper, a discrete wavelet transform (DWT) based de-noising with its applications into the noise reduction for medical signal preprocessing is introduced. This work focuses on the hardware realization of a real-time wavelet de-noising procedure. The proposed de-noising circuit mainly consists of three modules: a DWT, a thresholding, and an inverse DWT (IDWT) modular circuits. We also proposed a novel adaptive thresholding scheme and incorporated it into our wavelet de-noising procedure. Performance was then evaluated on both the architectural designs of the software and. In addition, the de-noising circuit was also implemented by downloading the Verilog codes to a field programmable gate array (FPGA) based platform so that its ability in noise reduction may be further validated in actual practice. Simulation experiment results produced by applying a set of simulated noise-contaminated electrocardiogram (ECG) signals into the de-noising circuit showed that the circuit could not only desirably meet the requirement of real-time processing, but also achieve satisfactory performance for noise reduction, while the sharp features of the ECG signals can be well preserved. The proposed de-noising circuit was further synthesized using the Synopsys Design Compiler with an Artisan Taiwan Semiconductor Manufacturing Company (TSMC, Hsinchu, Taiwan) 40 nm standard cell library. The integrated circuit (IC) synthesis simulation results showed that the proposed design can achieve a clock frequency of 200 MHz and the power consumption was only 17.4 mW, when operated at 200 MHz. PMID:26501290

Hardware design and implementation of a wavelet de-noising procedure for medical signal preprocessing.

PubMed

Chen, Szi-Wen; Chen, Yuan-Ho

2015-10-16

In this paper, a discrete wavelet transform (DWT) based de-noising with its applications into the noise reduction for medical signal preprocessing is introduced. This work focuses on the hardware realization of a real-time wavelet de-noising procedure. The proposed de-noising circuit mainly consists of three modules: a DWT, a thresholding, and an inverse DWT (IDWT) modular circuits. We also proposed a novel adaptive thresholding scheme and incorporated it into our wavelet de-noising procedure. Performance was then evaluated on both the architectural designs of the software and. In addition, the de-noising circuit was also implemented by downloading the Verilog codes to a field programmable gate array (FPGA) based platform so that its ability in noise reduction may be further validated in actual practice. Simulation experiment results produced by applying a set of simulated noise-contaminated electrocardiogram (ECG) signals into the de-noising circuit showed that the circuit could not only desirably meet the requirement of real-time processing, but also achieve satisfactory performance for noise reduction, while the sharp features of the ECG signals can be well preserved. The proposed de-noising circuit was further synthesized using the Synopsys Design Compiler with an Artisan Taiwan Semiconductor Manufacturing Company (TSMC, Hsinchu, Taiwan) 40 nm standard cell library. The integrated circuit (IC) synthesis simulation results showed that the proposed design can achieve a clock frequency of 200 MHz and the power consumption was only 17.4 mW, when operated at 200 MHz.

Hardware implementation of an adaptive resonance theory (ART) neural network using compensated operational amplifiers

NASA Astrophysics Data System (ADS)

Ho, Ching S.; Liou, Juin J.; Georgiopoulos, Michael; Christodoulou, Christos G.

1994-03-01

This paper presents an analog circuit design and implementation for an adaptive resonance theory neural network architecture called the augmented ART1 neural network (AART1-NN). Practical monolithic operational amplifiers (Op-Amps) LM741 and LM318 are selected to implement the circuit, and a simple compensation scheme is developed to adjust the Op-Amp electrical characteristics to meet the design requirement. A 7-node prototype circuit has been designed and verified using the Pspice circuit simulator run on a Sun workstation. Results simulated from the AART1-NN circuit using the LM741, LM318, and ideal Op-Amps are presented and compared.

Direct Digital Boiler Control Systems for the Navy Small Boiler Equipment.

DTIC Science & Technology

1983-02-01

Hardware. Each full-size ACU a 6 caculation modules 30 arrme, modufes sation for dead time lag contains input/output circuit a 16 control mo uies a...along with lather modules of the DCS-1000 family. ’The complete instrument consists of plug-in circuit boards that allow easy Teplacement of a...Maintenance-Most systems indicate trouble areas with diagnostic routines or integral LED indicators so that circuit boards can be replaced to correct

Design Methodology of an Equalizer for Unipolar Non Return to Zero Binary Signals in the Presence of Additive White Gaussian Noise Using a Time Delay Neural Network on a Field Programmable Gate Array

PubMed Central

Pérez Suárez, Santiago T.; Travieso González, Carlos M.; Alonso Hernández, Jesús B.

2013-01-01

This article presents a design methodology for designing an artificial neural network as an equalizer for a binary signal. Firstly, the system is modelled in floating point format using Matlab. Afterward, the design is described for a Field Programmable Gate Array (FPGA) using fixed point format. The FPGA design is based on the System Generator from Xilinx, which is a design tool over Simulink of Matlab. System Generator allows one to design in a fast and flexible way. It uses low level details of the circuits and the functionality of the system can be fully tested. System Generator can be used to check the architecture and to analyse the effect of the number of bits on the system performance. Finally the System Generator design is compiled for the Xilinx Integrated System Environment (ISE) and the system is described using a hardware description language. In ISE the circuits are managed with high level details and physical performances are obtained. In the Conclusions section, some modifications are proposed to improve the methodology and to ensure portability across FPGA manufacturers.

Requirements analysis for a hardware, discrete-event, simulation engine accelerator

NASA Astrophysics Data System (ADS)

Taylor, Paul J., Jr.

1991-12-01

An analysis of a general Discrete Event Simulation (DES), executing on the distributed architecture of an eight mode Intel PSC/2 hypercube, was performed. The most time consuming portions of the general DES algorithm were determined to be the functions associated with message passing of required simulation data between processing nodes of the hypercube architecture. A behavioral description, using the IEEE standard VHSIC Hardware Description and Design Language (VHDL), for a general DES hardware accelerator is presented. The behavioral description specifies the operational requirements for a DES coprocessor to augment the hypercube's execution of DES simulations. The DES coprocessor design implements the functions necessary to perform distributed discrete event simulations using a conservative time synchronization protocol.

Hardware Fault Simulator for Microprocessors

NASA Technical Reports Server (NTRS)

Hess, L. M.; Timoc, C. C.

1983-01-01

Breadboarded circuit is faster and more thorough than software simulator. Elementary fault simulator for AND gate uses three gates and shaft register to simulate stuck-at-one or stuck-at-zero conditions at inputs and output. Experimental results showed hardware fault simulator for microprocessor gave faster results than software simulator, by two orders of magnitude, with one test being applied every 4 microseconds.

Obstacle Avoidance and Target Acquisition for Robot Navigation Using a Mixed Signal Analog/Digital Neuromorphic Processing System

PubMed Central

Milde, Moritz B.; Blum, Hermann; Dietmüller, Alexander; Sumislawska, Dora; Conradt, Jörg; Indiveri, Giacomo; Sandamirskaya, Yulia

2017-01-01

Neuromorphic hardware emulates dynamics of biological neural networks in electronic circuits offering an alternative to the von Neumann computing architecture that is low-power, inherently parallel, and event-driven. This hardware allows to implement neural-network based robotic controllers in an energy-efficient way with low latency, but requires solving the problem of device variability, characteristic for analog electronic circuits. In this work, we interfaced a mixed-signal analog-digital neuromorphic processor ROLLS to a neuromorphic dynamic vision sensor (DVS) mounted on a robotic vehicle and developed an autonomous neuromorphic agent that is able to perform neurally inspired obstacle-avoidance and target acquisition. We developed a neural network architecture that can cope with device variability and verified its robustness in different environmental situations, e.g., moving obstacles, moving target, clutter, and poor light conditions. We demonstrate how this network, combined with the properties of the DVS, allows the robot to avoid obstacles using a simple biologically-inspired dynamics. We also show how a Dynamic Neural Field for target acquisition can be implemented in spiking neuromorphic hardware. This work demonstrates an implementation of working obstacle avoidance and target acquisition using mixed signal analog/digital neuromorphic hardware. PMID:28747883

Obstacle Avoidance and Target Acquisition for Robot Navigation Using a Mixed Signal Analog/Digital Neuromorphic Processing System.

PubMed

Milde, Moritz B; Blum, Hermann; Dietmüller, Alexander; Sumislawska, Dora; Conradt, Jörg; Indiveri, Giacomo; Sandamirskaya, Yulia

2017-01-01

Neuromorphic hardware emulates dynamics of biological neural networks in electronic circuits offering an alternative to the von Neumann computing architecture that is low-power, inherently parallel, and event-driven. This hardware allows to implement neural-network based robotic controllers in an energy-efficient way with low latency, but requires solving the problem of device variability, characteristic for analog electronic circuits. In this work, we interfaced a mixed-signal analog-digital neuromorphic processor ROLLS to a neuromorphic dynamic vision sensor (DVS) mounted on a robotic vehicle and developed an autonomous neuromorphic agent that is able to perform neurally inspired obstacle-avoidance and target acquisition. We developed a neural network architecture that can cope with device variability and verified its robustness in different environmental situations, e.g., moving obstacles, moving target, clutter, and poor light conditions. We demonstrate how this network, combined with the properties of the DVS, allows the robot to avoid obstacles using a simple biologically-inspired dynamics. We also show how a Dynamic Neural Field for target acquisition can be implemented in spiking neuromorphic hardware. This work demonstrates an implementation of working obstacle avoidance and target acquisition using mixed signal analog/digital neuromorphic hardware.

Hardware device to physical structure binding and authentication

DOEpatents

Hamlet, Jason R.; Stein, David J.; Bauer, Todd M.

2013-08-20

Detection and deterrence of device tampering and subversion may be achieved by including a cryptographic fingerprint unit within a hardware device for authenticating a binding of the hardware device and a physical structure. The cryptographic fingerprint unit includes an internal physically unclonable function ("PUF") circuit disposed in or on the hardware device, which generate an internal PUF value. Binding logic is coupled to receive the internal PUF value, as well as an external PUF value associated with the physical structure, and generates a binding PUF value, which represents the binding of the hardware device and the physical structure. The cryptographic fingerprint unit also includes a cryptographic unit that uses the binding PUF value to allow a challenger to authenticate the binding.

Microprocessor Design Using Hardware Description Language

ERIC Educational Resources Information Center

Mita, Rosario; Palumbo, Gaetano

2008-01-01

The following paper has been conceived to deal with the contents of some lectures aimed at enhancing courses on digital electronic, microelectronic or VLSI systems. Those lectures show how to use a hardware description language (HDL), such as the VHDL, to specify, design and verify a custom microprocessor. The general goal of this work is to teach…

Micromachined integrated quantum circuit containing a superconducting qubit

NASA Astrophysics Data System (ADS)

Brecht, Teresa; Chu, Yiwen; Axline, Christopher; Pfaff, Wolfgang; Blumoff, Jacob; Chou, Kevin; Krayzman, Lev; Frunzio, Luigi; Schoelkopf, Robert

We demonstrate a functional multilayer microwave integrated quantum circuit (MMIQC). This novel hardware architecture combines the high coherence and isolation of three-dimensional structures with the advantages of integrated circuits made with lithographic techniques. We present fabrication and measurement of a two-cavity/one-qubit prototype, including a transmon coupled to a three-dimensional microwave cavity micromachined in a silicon wafer. It comprises a simple MMIQC with competitive lifetimes and the ability to perform circuit QED operations in the strong dispersive regime. Furthermore, the design and fabrication techniques that we have developed are extensible to more complex quantum information processing devices.

NSTX Electrical Power Systems

DOE Office of Scientific and Technical Information (OSTI.GOV)

A. Ilic; E. Baker; R. Hatcher

The National Spherical Torus Experiment (NSTX) has been designed and installed in the existing facilities at Princeton Plasma Physic Laboratory (PPPL). Most of the hardware, plant facilities, auxiliary sub-systems, and power systems originally used for the Tokamak Fusion Test Reactor (TFTR) have been used with suitable modifications to reflect NSTX needs. The design of the NSTX electrical power system was tailored to suit the available infrastructure and electrical equipment on site. Components were analyzed to verify their suitability for use in NSTX. The total number of circuits and the location of the NSTX device drove the major changes in themore » Power system hardware. The NSTX has eleven (11) circuits to be fed as compared to the basic three power loops for TFTR. This required changes in cabling to insure that each cable tray system has the positive and negative leg of cables in the same tray. Also additional power cabling had to be installed to the new location. The hardware had to b e modified to address the need for eleven power loops. Power converters had to be reconnected and controlled in anti-parallel mode for the Ohmic heating and two of the Poloidal Field circuits. The circuit for the Coaxial Helicity Injection (CHI) System had to be carefully developed to meet this special application. Additional Protection devices were designed and installed for the magnet coils and the CHI. The thrust was to making the changes in the most cost-effective manner without compromising technical requirements. This paper describes the changes and addition to the Electrical Power System components for the NSTX magnet systems.« less

The design and hardware implementation of a low-power real-time seizure detection algorithm

NASA Astrophysics Data System (ADS)

Raghunathan, Shriram; Gupta, Sumeet K.; Ward, Matthew P.; Worth, Robert M.; Roy, Kaushik; Irazoqui, Pedro P.

2009-10-01

Epilepsy affects more than 1% of the world's population. Responsive neurostimulation is emerging as an alternative therapy for the 30% of the epileptic patient population that does not benefit from pharmacological treatment. Efficient seizure detection algorithms will enable closed-loop epilepsy prostheses by stimulating the epileptogenic focus within an early onset window. Critically, this is expected to reduce neuronal desensitization over time and lead to longer-term device efficacy. This work presents a novel event-based seizure detection algorithm along with a low-power digital circuit implementation. Hippocampal depth-electrode recordings from six kainate-treated rats are used to validate the algorithm and hardware performance in this preliminary study. The design process illustrates crucial trade-offs in translating mathematical models into hardware implementations and validates statistical optimizations made with empirical data analyses on results obtained using a real-time functioning hardware prototype. Using quantitatively predicted thresholds from the depth-electrode recordings, the auto-updating algorithm performs with an average sensitivity and selectivity of 95.3 ± 0.02% and 88.9 ± 0.01% (mean ± SEα = 0.05), respectively, on untrained data with a detection delay of 8.5 s [5.97, 11.04] from electrographic onset. The hardware implementation is shown feasible using CMOS circuits consuming under 350 nW of power from a 250 mV supply voltage from simulations on the MIT 180 nm SOI process.

BETA: Behavioral testability analyzer and its application to high-level test generation and synthesis for testability. Ph.D. Thesis

NASA Technical Reports Server (NTRS)

Chen, Chung-Hsing

1992-01-01

In this thesis, a behavioral-level testability analysis approach is presented. This approach is based on analyzing the circuit behavioral description (similar to a C program) to estimate its testability by identifying controllable and observable circuit nodes. This information can be used by a test generator to gain better access to internal circuit nodes and to reduce its search space. The results of the testability analyzer can also be used to select test points or partial scan flip-flops in the early design phase. Based on selection criteria, a novel Synthesis for Testability approach call Test Statement Insertion (TSI) is proposed, which modifies the circuit behavioral description directly. Test Statement Insertion can also be used to modify circuit structural description to improve its testability. As a result, Synthesis for Testability methodology can be combined with an existing behavioral synthesis tool to produce more testable circuits.

Four-terminal circuit element with photonic core

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sampayan, Stephen

A four-terminal circuit element is described that includes a photonic core inside of the circuit element that uses a wide bandgap semiconductor material that exhibits photoconductivity and allows current flow through the material in response to the light that is incident on the wide bandgap material. The four-terminal circuit element can be configured based on various hardware structures using a single piece or multiple pieces or layers of a wide bandgap semiconductor material to achieve various designed electrical properties such as high switching voltages by using the photoconductive feature beyond the breakdown voltages of semiconductor devices or circuits operated basedmore » on electrical bias or control designs. The photonic core aspect of the four-terminal circuit element provides unique features that enable versatile circuit applications to either replace the semiconductor transistor-based circuit elements or semiconductor diode-based circuit elements.« less

Limits on fundamental limits to computation.

PubMed

Markov, Igor L

2014-08-14

An indispensable part of our personal and working lives, computing has also become essential to industries and governments. Steady improvements in computer hardware have been supported by periodic doubling of transistor densities in integrated circuits over the past fifty years. Such Moore scaling now requires ever-increasing efforts, stimulating research in alternative hardware and stirring controversy. To help evaluate emerging technologies and increase our understanding of integrated-circuit scaling, here I review fundamental limits to computation in the areas of manufacturing, energy, physical space, design and verification effort, and algorithms. To outline what is achievable in principle and in practice, I recapitulate how some limits were circumvented, and compare loose and tight limits. Engineering difficulties encountered by emerging technologies may indicate yet unknown limits.

Multistage switching hardware and software implementations for student experiment purpose

NASA Astrophysics Data System (ADS)

Sani, A.; Suherman

2018-02-01

Current communication and internet networks are underpinned by the switching technologies that interconnect one network to the others. Students’ understanding on networks rely on how they conver the theories. However, understanding theories without touching the reality may exert spots in the overall knowledge. This paper reports the progress of the multistage switching design and implementation for student laboratory activities. The hardware and software designs are based on three stages clos switching architecture with modular 2x2 switches, controlled by an arduino microcontroller. The designed modules can also be extended for batcher and bayan switch, and working on circuit and packet switching systems. The circuit analysis and simulation show that the blocking probability for each switch combinations can be obtained by generating random or patterned traffics. The mathematic model and simulation analysis shows 16.4% blocking probability differences as the traffic generation is uniform. The circuits design components and interfacing solution have been identified to allow next step implementation.

Failure Mode/Mechanism Distributions

DTIC Science & Technology

1991-09-01

circuits , hybrids, discrete semiconductors, microwave devices, optoelectronics and nonelectronic parts employed in military, space, industrial and...FMEA may be performed as a hardware analysis, a functional analysis, or a combination analysis and is ideally initiated at the part, circuit or...by a single replaceable module , a separate FMEA could be performed on the internal functions of the module , viewing the module as a system. The level

Quadrature demodulation based circuit implementation of pulse stream for ultrasonic signal FRI sparse sampling

NASA Astrophysics Data System (ADS)

Shoupeng, Song; Zhou, Jiang

2017-03-01

Converting ultrasonic signal to ultrasonic pulse stream is the key step of finite rate of innovation (FRI) sparse sampling. At present, ultrasonic pulse-stream-forming techniques are mainly based on digital algorithms. No hardware circuit that can achieve it has been reported. This paper proposes a new quadrature demodulation (QD) based circuit implementation method for forming an ultrasonic pulse stream. Elaborating on FRI sparse sampling theory, the process of ultrasonic signal is explained, followed by a discussion and analysis of ultrasonic pulse-stream-forming methods. In contrast to ultrasonic signal envelope extracting techniques, a quadrature demodulation method (QDM) is proposed. Simulation experiments were performed to determine its performance at various signal-to-noise ratios (SNRs). The circuit was then designed, with mixing module, oscillator, low pass filter (LPF), and root of square sum module. Finally, application experiments were carried out on pipeline sample ultrasonic flaw testing. The experimental results indicate that the QDM can accurately convert ultrasonic signal to ultrasonic pulse stream, and reverse the original signal information, such as pulse width, amplitude, and time of arrival. This technique lays the foundation for ultrasonic signal FRI sparse sampling directly with hardware circuitry.

Gyroscope relativity experiment

NASA Technical Reports Server (NTRS)

Decher, R.

1971-01-01

A gyroscope test of general relativity theory is proposed. The basic ideas and hardware concepts conceived by the investigators to implement the experiment are discussed. The goal is to measure the extremely small relativistic precession of gyroscopes in an earth-orbiting satellite. The experiment hardware (cryogenic gyroscopes, a telescope and superconducting circuits) is enclosed in a liquid helium dewar. The experiment will operate in orbit for about one year.

The Hermod Behavioral Synthesis System

DTIC Science & Technology

1988-06-08

LDescription 1 lib tech-independent Transformation & Parser Optimization lib Hardware • g - utSynhesze Generator li Datapath lb Hardware liCotllb...Proc. 22nd Design Automation Conference, ACM/IEEE, June 1985, pp. 475-481. [7] G . De Micheli, "Synthesis of Control Systems", in Design Systems for...VLSI Circuits: Logic Synthesis and Silicon Compilation, G . De Micheli, A. Sangiovanni-Vincentelli, and P. Antognetti, (editor), Martinus Nijhoff

The 30/20 GHz flight experiment system, phase 2. Volume 2: Experiment system description

NASA Technical Reports Server (NTRS)

Bronstein, L.; Kawamoto, Y.; Ribarich, J. J.; Scope, J. R.; Forman, B. J.; Bergman, S. G.; Reisenfeld, S.

1981-01-01

A detailed technical description of the 30/20 GHz flight experiment system is presented. The overall communication system is described with performance analyses, communication operations, and experiment plans. Hardware descriptions of the payload are given with the tradeoff studies that led to the final design. The spacecraft bus which carries the payload is discussed and its interface with the launch vehicle system is described. Finally, the hardwares and the operations of the terrestrial segment are presented.

FPGA Based Reconfigurable ATM Switch Test Bed

NASA Technical Reports Server (NTRS)

Chu, Pong P.; Jones, Robert E.

1998-01-01

Various issues associated with "FPGA Based Reconfigurable ATM Switch Test Bed" are presented in viewgraph form. Specific topics include: 1) Network performance evaluation; 2) traditional approaches; 3) software simulation; 4) hardware emulation; 5) test bed highlights; 6) design environment; 7) test bed architecture; 8) abstract sheared-memory switch; 9) detailed switch diagram; 10) traffic generator; 11) data collection circuit and user interface; 12) initial results; and 13) the following conclusions: Advances in FPGA make hardware emulation feasible for performance evaluation, hardware emulation can provide several orders of magnitude speed-up over software simulation; due to the complexity of hardware synthesis process, development in emulation is much more difficult than simulation and requires knowledge in both networks and digital design.

Electrical circuit modeling and analysis of microwave acoustic interaction with biological tissues.

PubMed

Gao, Fei; Zheng, Qian; Zheng, Yuanjin

2014-05-01

Numerical study of microwave imaging and microwave-induced thermoacoustic imaging utilizes finite difference time domain (FDTD) analysis for simulation of microwave and acoustic interaction with biological tissues, which is time consuming due to complex grid-segmentation and numerous calculations, not straightforward due to no analytical solution and physical explanation, and incompatible with hardware development requiring circuit simulator such as SPICE. In this paper, instead of conventional FDTD numerical simulation, an equivalent electrical circuit model is proposed to model the microwave acoustic interaction with biological tissues for fast simulation and quantitative analysis in both one and two dimensions (2D). The equivalent circuit of ideal point-like tissue for microwave-acoustic interaction is proposed including transmission line, voltage-controlled current source, envelop detector, and resistor-inductor-capacitor (RLC) network, to model the microwave scattering, thermal expansion, and acoustic generation. Based on which, two-port network of the point-like tissue is built and characterized using pseudo S-parameters and transducer gain. Two dimensional circuit network including acoustic scatterer and acoustic channel is also constructed to model the 2D spatial information and acoustic scattering effect in heterogeneous medium. Both FDTD simulation, circuit simulation, and experimental measurement are performed to compare the results in terms of time domain, frequency domain, and pseudo S-parameters characterization. 2D circuit network simulation is also performed under different scenarios including different sizes of tumors and the effect of acoustic scatterer. The proposed circuit model of microwave acoustic interaction with biological tissue could give good agreement with FDTD simulated and experimental measured results. The pseudo S-parameters and characteristic gain could globally evaluate the performance of tumor detection. The 2D circuit network enables the potential to combine the quasi-numerical simulation and circuit simulation in a uniform simulator for codesign and simulation of a microwave acoustic imaging system, bridging bioeffect study and hardware development seamlessly.

Optimization of the Multi-Spectral Euclidean Distance Calculation for FPGA-based Spaceborne Systems

NASA Technical Reports Server (NTRS)

Cristo, Alejandro; Fisher, Kevin; Perez, Rosa M.; Martinez, Pablo; Gualtieri, Anthony J.

2012-01-01

Due to the high quantity of operations that spaceborne processing systems must carry out in space, new methodologies and techniques are being presented as good alternatives in order to free the main processor from work and improve the overall performance. These include the development of ancillary dedicated hardware circuits that carry out the more redundant and computationally expensive operations in a faster way, leaving the main processor free to carry out other tasks while waiting for the result. One of these devices is SpaceCube, a FPGA-based system designed by NASA. The opportunity to use FPGA reconfigurable architectures in space allows not only the optimization of the mission operations with hardware-level solutions, but also the ability to create new and improved versions of the circuits, including error corrections, once the satellite is already in orbit. In this work, we propose the optimization of a common operation in remote sensing: the Multi-Spectral Euclidean Distance calculation. For that, two different hardware architectures have been designed and implemented in a Xilinx Virtex-5 FPGA, the same model of FPGAs used by SpaceCube. Previous results have shown that the communications between the embedded processor and the circuit create a bottleneck that affects the overall performance in a negative way. In order to avoid this, advanced methods including memory sharing, Native Port Interface (NPI) connections and Data Burst Transfers have been used.

Coexistence of Multiple Attractors in an Active Diode Pair Based Chua’s Circuit

NASA Astrophysics Data System (ADS)

Bao, Bocheng; Wu, Huagan; Xu, Li; Chen, Mo; Hu, Wen

This paper focuses on the coexistence of multiple attractors in an active diode pair based Chua’s circuit with smooth nonlinearity. With dimensionless equations, dynamical properties, including boundness of system orbits and stability distributions of two nonzero equilibrium points, are investigated, and complex coexisting behaviors of multiple kinds of disconnected attractors of stable point attractors, limit cycles and chaotic attractors are numerically revealed. The results show that unlike the classical Chua’s circuit, the proposed circuit has two stable nonzero node-foci for the specified circuit parameters, thereby resulting in the emergence of multistability phenomenon. Based on two general impedance converters, the active diode pair based Chua’s circuit with an adjustable inductor and an adjustable capacitor is made in hardware, from which coexisting multiple attractors are conveniently captured.

DRFM Cordic Processor and Sea Clutter Modeling for Enhancing Structured False Target Synthesis

DTIC Science & Technology

2017-09-01

was implemented using the Verilog hardware description language. The second investigation concerns generating sea clutter to impose on the false target...to achieve accuracy at 5.625o. The resulting design was implemented using the Verilog hardware description language. The second investigation...33 3. Initialization of the Angle Accumulator ....................................34 4. Design Methodology for I/Q Phase

A Low-Complexity Circuit for On-Sensor Concurrent A/D Conversion and Compression

NASA Technical Reports Server (NTRS)

Leon-Salas, Walter D.; Balkir, Sina; Sayood, Khalid; Schemm, Nathan; Hoffman, Michael W.

2007-01-01

A low-complexity circuit for on-sensor compression is presented. The proposed circuit achieves complexity savings by combining a single-slope analog-to-digital converter with a Golomb-Rice entropy encoder and by implementing a low-complexity adaptation rule. The adaptation rule monitors the output codewords and minimizes their length by incrementing or decrementing the value of the Golomb-Rice coding parameter k. Its hardware implementation is one order of magnitude lower than existing adaptive algorithms. The compression circuit has been fabricated using a 0.35 micrometers CMOS technology and occupies an area of 0.0918 mm2. Test measurements confirm the validity of the design

DDL:Digital systems design language

NASA Technical Reports Server (NTRS)

Shival, S. G.

1980-01-01

Hardware description languages are valuable tools in such applications as hardware design, system documentation, and logic design training. DDL is convenient medium for inputting design details into hardware-design automation system. It is suitable for describing digital systems at gate, register transfer, and major combinational block level.

The effect of structural design parameters on FPGA-based feed-forward space-time trellis coding-orthogonal frequency division multiplexing channel encoders

NASA Astrophysics Data System (ADS)

Passas, Georgios; Freear, Steven; Fawcett, Darren

2010-08-01

Orthogonal frequency division multiplexing (OFDM)-based feed-forward space-time trellis code (FFSTTC) encoders can be synthesised as very high speed integrated circuit hardware description language (VHDL) designs. Evaluation of their FPGA implementation can lead to conclusions that help a designer to decide the optimum implementation, given the encoder structural parameters. VLSI architectures based on 1-bit multipliers and look-up tables (LUTs) are compared in terms of FPGA slices and block RAMs (area), as well as in terms of minimum clock period (speed). Area and speed graphs versus encoder memory order are provided for quadrature phase shift keying (QPSK) and 8 phase shift keying (8-PSK) modulation and two transmit antennas, revealing best implementation under these conditions. The effect of number of modulation bits and transmit antennas on the encoder implementation complexity is also investigated.

DRS: Derivational Reasoning System

NASA Technical Reports Server (NTRS)

Bose, Bhaskar

1995-01-01

The high reliability requirements for airborne systems requires fault-tolerant architectures to address failures in the presence of physical faults, and the elimination of design flaws during the specification and validation phase of the design cycle. Although much progress has been made in developing methods to address physical faults, design flaws remain a serious problem. Formal methods provides a mathematical basis for removing design flaws from digital systems. DRS (Derivational Reasoning System) is a formal design tool based on advanced research in mathematical modeling and formal synthesis. The system implements a basic design algebra for synthesizing digital circuit descriptions from high level functional specifications. DRS incorporates an executable specification language, a set of correctness preserving transformations, verification interface, and a logic synthesis interface, making it a powerful tool for realizing hardware from abstract specifications. DRS integrates recent advances in transformational reasoning, automated theorem proving and high-level CAD synthesis systems in order to provide enhanced reliability in designs with reduced time and cost.

CHeCS: International Space Station Medical Hardware Catalog

NASA Technical Reports Server (NTRS)

2008-01-01

The purpose of this catalog is to provide a detailed description of each piece of hardware in the Crew Health Care System (CHeCS), including subpacks associated with the hardware, and to briefly describe the interfaces between the hardware and the ISS. The primary user of this document is the Space Medicine/Medical Operations ISS Biomedical Flight Controllers (ISS BMEs).

Reliability Evaluation of Computer Systems.

DTIC Science & Technology

1981-01-01

algorithms in hardware is not restricted by the designs of particular circuits. Applications could be made in new computer architectures; one candidate...pp. 137-148, IEEE, Chicago, Illinois, September 1963. (With J.F. Wakerly ) "Design of Low-Cost General-Purpose Self- Diagnosing Computers," Proc...34 Proc., IEEE Int’l Solid-State Circuits Conference, Philadelphia, Pennsylvania, February 16-18, 1977. (With J.F. Wakerly ) "Microcomputers in the

An Automated Safe-to-Mate (ASTM) Tester

NASA Technical Reports Server (NTRS)

Nguyen, Phuc; Scott, Michelle; Leung, Alan; Lin, Michael; Johnson, Thomas

2013-01-01

Safe-to-mate testing is a common hardware safety practice where impedance measurements are made on unpowered hardware to verify isolation, continuity, or impedance between pins of an interface connector. A computer-based instrumentation solution has been developed to resolve issues. The ASTM is connected to the circuit under test, and can then quickly, safely, and reliably safe-to-mate the entire connector, or even multiple connectors, at the same time.

Hawaiian Electric Advanced Inverter Test Plan - Result Summary

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hoke, Anderson; Nelson, Austin; Prabakar, Kumaraguru

This presentation is intended to share the results of lab testing of five PV inverters with the Hawaiian Electric Companies and other stakeholders and interested parties. The tests included baseline testing of advanced inverter grid support functions, as well as distribution circuit-level tests to examine the impact of the PV inverters on simulated distribution feeders using power hardware-in-the-loop (PHIL) techniques. hardware-in-the-loop (PHIL) techniques.

PC based graphic display real-time particle beam uniformity

NASA Technical Reports Server (NTRS)

Huebner, M. A.; Malone, C. J.; Smith, L. S.; Soli, G. A.

1989-01-01

A technique has been developed to support the study of the effects of cosmic rays on integrated circuits. The system is designed to determine the particle distribution across the surface of an integrated circuit accurately while the circuit is bombarded by a particle beam. The system uses photomultiplier tubes, an octal discriminator, a computer-controlled NIM quad counter, and an IBM PC. It provides real-time operator feedback for fast beam tuning and monitors momentary fluctuations in the particle beam. The hardware, software, and system performance are described.

NASA Tech Briefs, June 1996. Volume 20, No. 6

NASA Technical Reports Server (NTRS)

1996-01-01

Topics: New Computer Hardware; Electronic Components and Circuits; Electronic Systems; Physical Sciences; Materials; Computer Programs; Mechanics; Machinery/Automation; Manufacturing/Fabrication; Mathematics and Information Sciences;Books and Reports.

Mini-O, simple Omega receiver hardware for user education

NASA Technical Reports Server (NTRS)

Burhans, R. W.

1976-01-01

A problem with the Omega system is a lack of suitable low cost hardware for the small user community. A collection of do it yourself circuit modules are under development intended for use by educational institutions, small boat owners, aviation enthusiasts, and others who have some skills in fabricating their own electronic equipment. Applications of the hardware to time frequency standards measurements, signal propagation monitoring, and navigation experiments are presented. A family of Mini-O systems have been constructed varying from the simplest RF preamplifiers and narrowband filters front-ends, to sophisticated microcomputer interface adapters.

Coexistence of multiple bifurcation modes in memristive diode-bridge-based canonical Chua's circuit

NASA Astrophysics Data System (ADS)

Bao, Bocheng; Xu, Li; Wu, Zhimin; Chen, Mo; Wu, Huagan

2018-07-01

Based on a memristive diode bridge cascaded with series resistor and inductor filter, a modified memristive canonical Chua's circuit is presented in this paper. With the modelling of the memristive circuit, a normalised system model is built. Stability analyses of the equilibrium points are performed and bifurcation behaviours are investigated by numerical simulations and hardware experiments. Most extraordinary in the memristive circuit is that within a parameter region, coexisting phenomenon of multiple bifurcation modes is emerged under six sets of different initial values, resulting in the coexistence of four sets of topologically different and disconnected attractors. These coexisting attractors are easily captured by repeatedly switching on and off the circuit power supplies, which well verify the numerical simulations.

Hardware synthesis from DDL. [Digital Design Language for computer aided design and test of LSI

NASA Technical Reports Server (NTRS)

Shah, A. M.; Shiva, S. G.

1981-01-01

The details of the digital systems can be conveniently input into the design automation system by means of Hardware Description Languages (HDL). The Computer Aided Design and Test (CADAT) system at NASA MSFC is used for the LSI design. The Digital Design Language (DDL) has been selected as HDL for the CADAT System. DDL translator output can be used for the hardware implementation of the digital design. This paper addresses problems of selecting the standard cells from the CADAT standard cell library to realize the logic implied by the DDL description of the system.

Computer hardware for radiologists: Part I

PubMed Central

Indrajit, IK; Alam, A

2010-01-01

Computers are an integral part of modern radiology practice. They are used in different radiology modalities to acquire, process, and postprocess imaging data. They have had a dramatic influence on contemporary radiology practice. Their impact has extended further with the emergence of Digital Imaging and Communications in Medicine (DICOM), Picture Archiving and Communication System (PACS), Radiology information system (RIS) technology, and Teleradiology. A basic overview of computer hardware relevant to radiology practice is presented here. The key hardware components in a computer are the motherboard, central processor unit (CPU), the chipset, the random access memory (RAM), the memory modules, bus, storage drives, and ports. The personnel computer (PC) has a rectangular case that contains important components called hardware, many of which are integrated circuits (ICs). The fiberglass motherboard is the main printed circuit board and has a variety of important hardware mounted on it, which are connected by electrical pathways called “buses”. The CPU is the largest IC on the motherboard and contains millions of transistors. Its principal function is to execute “programs”. A Pentium® 4 CPU has transistors that execute a billion instructions per second. The chipset is completely different from the CPU in design and function; it controls data and interaction of buses between the motherboard and the CPU. Memory (RAM) is fundamentally semiconductor chips storing data and instructions for access by a CPU. RAM is classified by storage capacity, access speed, data rate, and configuration. PMID:21042437

An Open Hardware seismic data recorder - a solid basis for citizen science

NASA Astrophysics Data System (ADS)

Mertl, Stefan

2015-04-01

"Ruwai" is a 24-Bit Open Hardware seismic data recorder. It is built up of four stackable printed circuit boards fitting the Arduino Mega 2560 microcontroller prototyping platform. An interface to the BeagleBone Black single-board computer enables extensive data storage, -processing and networking capabilities. The four printed circuit boards provide a uBlox Lea-6T GPS module and real-time clock (GPS Timing shield), an Texas Instruments ADS1274 24-Bit analog to digital converter (ADC main shield), an analog input section with a Texas Instruments PGA281 programmable gain amplifier and an analog anti-aliasing filter (ADC analog interface pga) and the power conditioning based on 9-36V DC input (power supply shield). The Arduino Mega 2560 is used for controlling the hardware components, timestamping sampled data using the GPS timing information and transmitting the data to the BeagleBone Black single-board computer. The BeagleBone Black provides local data storage, wireless mesh networking using the optimized link state routing daemon and differential GNSS positioning using the RTKLIB software. The complete hardware and software is published under free software - or open hardware licenses and only free software (e.g. KiCad) was used for the development to facilitate the reusability of the design and increases the sustainability of the project. "Ruwai" was developed within the framework of the "Community Environmental Observation Network (CEON)" (http://www.mertl-research.at/ceon/) which was supported by the Internet Foundation Austria (IPA) within the NetIdee 2013 call.

Multichannel temperature control for solar heating

NASA Technical Reports Server (NTRS)

Currie, J. R.

1978-01-01

Multiplexer/amplifier circuit monitors temperatures and temperature differences. Although primarily designed for cycle control in solar-heating systems, it can also measure temperatures in motors, ovens, electronic hardware, and other equipment.

Area-delay trade-offs of texture decompressors for a graphics processing unit

NASA Astrophysics Data System (ADS)

Novoa Súñer, Emilio; Ituero, Pablo; López-Vallejo, Marisa

2011-05-01

Graphics Processing Units have become a booster for the microelectronics industry. However, due to intellectual property issues, there is a serious lack of information on implementation details of the hardware architecture that is behind GPUs. For instance, the way texture is handled and decompressed in a GPU to reduce bandwidth usage has never been dealt with in depth from a hardware point of view. This work addresses a comparative study on the hardware implementation of different texture decompression algorithms for both conventional (PCs and video game consoles) and mobile platforms. Circuit synthesis is performed targeting both a reconfigurable hardware platform and a 90nm standard cell library. Area-delay trade-offs have been extensively analyzed, which allows us to compare the complexity of decompressors and thus determine suitability of algorithms for systems with limited hardware resources.

Intrinsic Hardware Evolution for the Design and Reconfiguration of Analog Speed Controllers for a DC Motor

NASA Technical Reports Server (NTRS)

Gwaltney, David A.; Ferguson, Michael I.

2003-01-01

Evolvable hardware provides the capability to evolve analog circuits to produce amplifier and filter functions. Conventional analog controller designs employ these same functions. Analog controllers for the control of the shaft speed of a DC motor are evolved on an evolvable hardware platform utilizing a second generation Field Programmable Transistor Array (FPTA2). The performance of an evolved controller is compared to that of a conventional proportional-integral (PI) controller. It is shown that hardware evolution is able to create a compact design that provides good performance, while using considerably less functional electronic components than the conventional design. Additionally, the use of hardware evolution to provide fault tolerance by reconfiguring the design is explored. Experimental results are presented showing that significant recovery of capability can be made in the face of damaging induced faults.

The NASA Langley 16-Foot Transonic Tunnel: Historical Overview, Facility Description, Calibration, Flow Characteristics, and Test Capabilities

NASA Technical Reports Server (NTRS)

Capone, Francis J.; Bangert, Linda S.; Asbury, Scott C.; Mills, Charles T. L.; Bare, E. Ann

1995-01-01

The Langley 16-Foot Transonic Tunnel is a closed-circuit single-return atmospheric wind tunnel that has a slotted octagonal test section with continuous air exchange. The wind tunnel speed can be varied continuously over a Mach number range from 0.1 to 1.3. Test-section plenum suction is used for speeds above a Mach number of 1.05. Over a period of some 40 years, the wind tunnel has undergone many modifications. During the modifications completed in 1990, a new model support system that increased blockage, new fan blades, a catcher screen for the first set of turning vanes, and process controllers for tunnel speed, model attitude, and jet flow for powered models were installed. This report presents a complete description of the Langley 16-Foot Transonic Tunnel and auxiliary equipment, the calibration procedures, and the results of the 1977 and the 1990 wind tunnel calibration with test section air removal. Comparisons with previous calibrations showed that the modifications made to the wind tunnel had little or no effect on the aerodynamic characteristics of the tunnel. Information required for planning experimental investigations and the use of test hardware and model support systems is also provided.

Multiplier less high-speed squaring circuit for binary numbers

NASA Astrophysics Data System (ADS)

Sethi, Kabiraj; Panda, Rutuparna

2015-03-01

The squaring operation is important in many applications in signal processing, cryptography etc. In general, squaring circuits reported in the literature use fast multipliers. A novel idea of a squaring circuit without using multipliers is proposed in this paper. Ancient Indian method used for squaring decimal numbers is extended here for binary numbers. The key to our success is that no multiplier is used. Instead, one squaring circuit is used. The hardware architecture of the proposed squaring circuit is presented. The design is coded in VHDL and synthesised and simulated in Xilinx ISE Design Suite 10.1 (Xilinx Inc., San Jose, CA, USA). It is implemented in Xilinx Vertex 4vls15sf363-12 device (Xilinx Inc.). The results in terms of time delay and area is compared with both modified Booth's algorithm and squaring circuit using Vedic multipliers. Our proposed squaring circuit seems to have better performance in terms of both speed and area.

VLSI circuits implementing computational models of neocortical circuits.

PubMed

Wijekoon, Jayawan H B; Dudek, Piotr

2012-09-15

This paper overviews the design and implementation of three neuromorphic integrated circuits developed for the COLAMN ("Novel Computing Architecture for Cognitive Systems based on the Laminar Microcircuitry of the Neocortex") project. The circuits are implemented in a standard 0.35 μm CMOS technology and include spiking and bursting neuron models, and synapses with short-term (facilitating/depressing) and long-term (STDP and dopamine-modulated STDP) dynamics. They enable execution of complex nonlinear models in accelerated-time, as compared with biology, and with low power consumption. The neural dynamics are implemented using analogue circuit techniques, with digital asynchronous event-based input and output. The circuits provide configurable hardware blocks that can be used to simulate a variety of neural networks. The paper presents experimental results obtained from the fabricated devices, and discusses the advantages and disadvantages of the analogue circuit approach to computational neural modelling. Copyright © 2012 Elsevier B.V. All rights reserved.

Integrated neuron circuit for implementing neuromorphic system with synaptic device

NASA Astrophysics Data System (ADS)

Lee, Jeong-Jun; Park, Jungjin; Kwon, Min-Woo; Hwang, Sungmin; Kim, Hyungjin; Park, Byung-Gook

2018-02-01

In this paper, we propose and fabricate Integrate & Fire neuron circuit for implementing neuromorphic system. Overall operation of the circuit is verified by measuring discrete devices and the output characteristics of the circuit. Since the neuron circuit shows asymmetric output characteristic that can drive synaptic device with Spike-Timing-Dependent-Plasticity (STDP) characteristic, the autonomous weight update process is also verified by connecting the synaptic device and the neuron circuit. The timing difference of the pre-neuron and the post-neuron induce autonomous weight change of the synaptic device. Unlike 2-terminal devices, which is frequently used to implement neuromorphic system, proposed scheme of the system enables autonomous weight update and simple configuration by using 4-terminal synapse device and appropriate neuron circuit. Weight update process in the multi-layer neuron-synapse connection ensures implementation of the hardware-based artificial intelligence, based on Spiking-Neural- Network (SNN).

Implementation of Basic and Universal Gates In a single Circuit Based On Quantum-dot Cellular Automata Using Multi-Layer Crossbar Wire

NASA Astrophysics Data System (ADS)

Bhowmik, Dhrubajyoti; Saha, Apu Kr; Dutta, Paramartha; Nandi, Supratim

2017-08-01

Quantum-dot Cellular Automata (QCA) is one of the most substitutes developing nanotechnologies for electronic circuits, as a result of lower force utilization, higher speed and smaller size in correlation with CMOS innovation. The essential devices, a Quantum-dot cell can be utilized to logic gates and wires. As it is the key building block on nanotechnology circuits. By applying simple gates, the hardware requirements for a QCA circuit can be decreased and circuits can be less complex as far as level, delay and cell check. This article exhibits an unobtrusive methodology for actualizing novel upgraded simple and universal gates, which can be connected to outline numerous variations of complex QCA circuits. Proposed gates are straightforward in structure and capable as far as implementing any digital circuits. The main aim is to build all basic and universal gates in a simple circuit with and without crossbar-wire. Simulation results and physical relations affirm its handiness in actualizing each advanced circuit.

GRC-2013-C-02448

NASA Image and Video Library

2009-06-23

Environmental Portrait, Electrical Power Systems Employee, hardware for the High Power 300-Volt Power Processing Unit (PPU). The Printed Circuit Boards (PCBs) are the Discharge Module Inverter and the Pulse Width Modulation (PWM) Controller

NASA Tech Briefs, August 1994. Volume 18, No. 8

NASA Technical Reports Server (NTRS)

1994-01-01

Topics covered include: Computer Hardware; Electronic Components and Circuits; Electronic Systems; Physical Sciences; Materials; Computer Programs; Mechanics; Machinery; Fabrication Technology; Mathematics and Information Sciences; Life Sciences; Books and Reports.

NASA Tech Briefs, June 1997. Volume 21, No. 6

NASA Technical Reports Server (NTRS)

1997-01-01

Topics include: Computer Hardware and Peripherals; Electronic Components and Circuits; Electronic Systems; Physical Sciences; Materials; Computer Programs; Mechanics; Machinery/Automation; Manufacturing/Fabrication; Mathematics and Information Sciences; Books and Reports.

Advanced High-Definition Video Cameras

NASA Technical Reports Server (NTRS)

Glenn, William

2007-01-01

A product line of high-definition color video cameras, now under development, offers a superior combination of desirable characteristics, including high frame rates, high resolutions, low power consumption, and compactness. Several of the cameras feature a 3,840 2,160-pixel format with progressive scanning at 30 frames per second. The power consumption of one of these cameras is about 25 W. The size of the camera, excluding the lens assembly, is 2 by 5 by 7 in. (about 5.1 by 12.7 by 17.8 cm). The aforementioned desirable characteristics are attained at relatively low cost, largely by utilizing digital processing in advanced field-programmable gate arrays (FPGAs) to perform all of the many functions (for example, color balance and contrast adjustments) of a professional color video camera. The processing is programmed in VHDL so that application-specific integrated circuits (ASICs) can be fabricated directly from the program. ["VHDL" signifies VHSIC Hardware Description Language C, a computing language used by the United States Department of Defense for describing, designing, and simulating very-high-speed integrated circuits (VHSICs).] The image-sensor and FPGA clock frequencies in these cameras have generally been much higher than those used in video cameras designed and manufactured elsewhere. Frequently, the outputs of these cameras are converted to other video-camera formats by use of pre- and post-filters.

Programmable logic devices

NASA Astrophysics Data System (ADS)

Jacobs, J. L.

1993-04-01

Erasable programmable logic devices (EPLD's) were investigated to determine their advantages and/or disadvantages in Test Equipment Engineering applications. It was found that EPLD's performed as well as or better than identical circuits using standard transistor transistor logic (TTL). The chip count in these circuits was reduced, saving printed circuit board space and shortening fabrication and prove-in time. Troubleshooting circuits of EPLD's was also easier with 10 to 100 times fewer wires needed. The reduced number of integrated circuits (IC's) contributed to faster system speeds and an overall lower power consumption. In some cases changes to the circuit became software changes using EPLD's instead of hardware changes for standard logic. Using EPLD's was fairly easy; however, as with any new technology, a learning curve must be overcome before EPLD's can be used efficiently. The many benefits of EPLD's outweighed this initial inconvenience.

Flight Hardware Packaging Design for Stringent EMC Radiated Emission Requirements

NASA Technical Reports Server (NTRS)

Lortz, Charlene L.; Huang, Chi-Chien N.; Ravich, Joshua A.; Steiner, Carl N.

2013-01-01

This packaging design approach can help heritage hardware meet a flight project's stringent EMC radiated emissions requirement. The approach requires only minor modifications to a hardware's chassis and mainly concentrates on its connector interfaces. The solution is to raise the surface area where the connector is mounted by a few millimeters using a pedestal, and then wrapping with conductive tape from the cable backshell down to the surface-mounted connector. This design approach has been applied to JPL flight project subsystems. The EMC radiated emissions requirements for flight projects can vary from benign to mission critical. If the project's EMC requirements are stringent, the best approach to meet EMC requirements would be to design an EMC control program for the project early on and implement EMC design techniques starting with the circuit board layout. This is the ideal scenario for hardware that is built from scratch. Implementation of EMC radiated emissions mitigation techniques can mature as the design progresses, with minimal impact to the design cycle. The real challenge exists for hardware that is planned to be flown following a built-to-print approach, in which heritage hardware from a past project with a different set of requirements is expected to perform satisfactorily for a new project. With acceptance of heritage, the design would already be established (circuit board layout and components have already been pre-determined), and hence any radiated emissions mitigation techniques would only be applicable at the packaging level. The key is to take a heritage design with its known radiated emissions spectrum and repackage, or modify its chassis design so that it would have a better chance of meeting the new project s radiated emissions requirements.

Expedition 18 Station Development Test Objectives (STDO) Session 1

NASA Image and Video Library

2009-02-19

ISS018-E-033816 (19 Feb. 2009) --- Astronaut Michael Fincke, Expedition 18 commander, removes, cleans and replaces electronic test components on a single test card using Component Repair Equipment (CRE-1) hardware in a portable glovebox facility in the Harmony node of the International Space Station. Fincke unsoldered 1 1/2 components from an integrated circuit board and re-soldered new components including an integrated circuit chip.

Expedition 18 Station Development Test Objectives (STDO) Session 1

NASA Image and Video Library

2009-02-19

ISS018-E-033818 (19 Feb. 2009) --- Astronaut Michael Fincke, Expedition 18 commander, removes, cleans and replaces electronic test components on a single test card using Component Repair Equipment (CRE-1) hardware in a portable glovebox facility in the Harmony node of the International Space Station. Fincke unsoldered 1 1/2 components from an integrated circuit board and re-soldered new components including an integrated circuit chip.

Generalized reconfigurable memristive dynamical system (MDS) for neuromorphic applications

PubMed Central

Bavandpour, Mohammad; Soleimani, Hamid; Linares-Barranco, Bernabé; Abbott, Derek; Chua, Leon O.

2015-01-01

This study firstly presents (i) a novel general cellular mapping scheme for two dimensional neuromorphic dynamical systems such as bio-inspired neuron models, and (ii) an efficient mixed analog-digital circuit, which can be conveniently implemented on a hybrid memristor-crossbar/CMOS platform, for hardware implementation of the scheme. This approach employs 4n memristors and no switch for implementing an n-cell system in comparison with 2n2 memristors and 2n switches of a Cellular Memristive Dynamical System (CMDS). Moreover, this approach allows for dynamical variables with both analog and one-hot digital values opening a wide range of choices for interconnections and networking schemes. Dynamical response analyses show that this circuit exhibits various responses based on the underlying bifurcation scenarios which determine the main characteristics of the neuromorphic dynamical systems. Due to high programmability of the circuit, it can be applied to a variety of learning systems, real-time applications, and analytically indescribable dynamical systems. We simulate the FitzHugh-Nagumo (FHN), Adaptive Exponential (AdEx) integrate and fire, and Izhikevich neuron models on our platform, and investigate the dynamical behaviors of these circuits as case studies. Moreover, error analysis shows that our approach is suitably accurate. We also develop a simple hardware prototype for experimental demonstration of our approach. PMID:26578867

Generalized reconfigurable memristive dynamical system (MDS) for neuromorphic applications.

PubMed

Bavandpour, Mohammad; Soleimani, Hamid; Linares-Barranco, Bernabé; Abbott, Derek; Chua, Leon O

2015-01-01

This study firstly presents (i) a novel general cellular mapping scheme for two dimensional neuromorphic dynamical systems such as bio-inspired neuron models, and (ii) an efficient mixed analog-digital circuit, which can be conveniently implemented on a hybrid memristor-crossbar/CMOS platform, for hardware implementation of the scheme. This approach employs 4n memristors and no switch for implementing an n-cell system in comparison with 2n (2) memristors and 2n switches of a Cellular Memristive Dynamical System (CMDS). Moreover, this approach allows for dynamical variables with both analog and one-hot digital values opening a wide range of choices for interconnections and networking schemes. Dynamical response analyses show that this circuit exhibits various responses based on the underlying bifurcation scenarios which determine the main characteristics of the neuromorphic dynamical systems. Due to high programmability of the circuit, it can be applied to a variety of learning systems, real-time applications, and analytically indescribable dynamical systems. We simulate the FitzHugh-Nagumo (FHN), Adaptive Exponential (AdEx) integrate and fire, and Izhikevich neuron models on our platform, and investigate the dynamical behaviors of these circuits as case studies. Moreover, error analysis shows that our approach is suitably accurate. We also develop a simple hardware prototype for experimental demonstration of our approach.

CHeCS (Crew Health Care Systems): International Space Station (ISS) Medical Hardware Catalog. Version 10.0

NASA Technical Reports Server (NTRS)

2011-01-01

The purpose of this catalog is to provide a detailed description of each piece of hardware in the Crew Health Care System (CHeCS), including subpacks associated with the hardware, and to briefly describe the interfaces between the hardware and the ISS. The primary user of this document is the Space Medicine/Medical Operations ISS Biomedical Flight Controllers (ISS BMEs).

Phase-lock-loop application for fiber optic receiver

NASA Astrophysics Data System (ADS)

Ruggles, Stephen L.; Wills, Robert W.

1991-02-01

Phase-locked loop circuits are frequently employed in communication systems. In recent years, digital phase-locked loop circuits were utilized in optical communications systems. In an optical transceiver system, the digital phase-locked loop circuit is connected to the output of the receiver to extract a clock signal from the received coded data (NRZ, Bi-Phase, or Manchester). The clock signal is then used to reconstruct or recover the original data from the coded data. A theoretical approach to the design of a digital phase-locked loop circuit operation at 1 and 50 MHz is described. Hardware implementation of a breadboard design to function at 1 MHz and a printed-circuit board designed to function at 50 MHz were assembled using emitter coupled logic (ECL) to verify experimentally the theoretical design.

A Readout Integrated Circuit (ROIC) employing self-adaptive background current compensation technique for Infrared Focal Plane Array (IRFPA)

NASA Astrophysics Data System (ADS)

Zhou, Tong; Zhao, Jian; He, Yong; Jiang, Bo; Su, Yan

2018-05-01

A novel self-adaptive background current compensation circuit applied to infrared focal plane array is proposed in this paper, which can compensate the background current generated in different conditions. Designed double-threshold detection strategy is to estimate and eliminate the background currents, which could significantly reduce the hardware overhead and improve the uniformity among different pixels. In addition, the circuit is well compatible to various categories of infrared thermo-sensitive materials. The testing results of a 4 × 4 experimental chip showed that the proposed circuit achieves high precision, wide application and high intelligence. Tape-out of the 320 × 240 readout circuit, as well as the bonding, encapsulation and imaging verification of uncooled infrared focal plane array, have also been completed.

Phase-lock-loop application for fiber optic receiver

NASA Technical Reports Server (NTRS)

Ruggles, Stephen L.; Wills, Robert W.

1991-01-01

Phase-locked loop circuits are frequently employed in communication systems. In recent years, digital phase-locked loop circuits were utilized in optical communications systems. In an optical transceiver system, the digital phase-locked loop circuit is connected to the output of the receiver to extract a clock signal from the received coded data (NRZ, Bi-Phase, or Manchester). The clock signal is then used to reconstruct or recover the original data from the coded data. A theoretical approach to the design of a digital phase-locked loop circuit operation at 1 and 50 MHz is described. Hardware implementation of a breadboard design to function at 1 MHz and a printed-circuit board designed to function at 50 MHz were assembled using emitter coupled logic (ECL) to verify experimentally the theoretical design.

Evolution of Analog Circuits on Field Programmable Transistor Arrays

NASA Technical Reports Server (NTRS)

Stoica, A.; Keymeulen, D.; Zebulum, R.; Thakoor, A.; Daud, T.; Klimeck, G.; Jin, Y.; Tawel, R.; Duong, V.

2000-01-01

Evolvable Hardware (EHW) refers to HW design and self-reconfiguration using evolutionary/genetic mechanisms. The paper presents an overview of some key concepts of EHW, describing also a set of selected applications.

Compressive Sensing Based Bio-Inspired Shape Feature Detection CMOS Imager

NASA Technical Reports Server (NTRS)

Duong, Tuan A. (Inventor)

2015-01-01

A CMOS imager integrated circuit using compressive sensing and bio-inspired detection is presented which integrates novel functions and algorithms within a novel hardware architecture enabling efficient on-chip implementation.

Space Station Freedom biomedical monitoring and countermeasures: Biomedical facility hardware catalog

NASA Technical Reports Server (NTRS)

1990-01-01

This hardware catalog covers that hardware proposed under the Biomedical Monitoring and Countermeasures Development Program supported by the Johnson Space Center. The hardware items are listed separately by item, and are in alphabetical order. Each hardware item specification consists of four pages. The first page describes background information with an illustration, definition and a history/design status. The second page identifies the general specifications, performance, rack interface requirements, problems, issues, concerns, physical description, and functional description. The level of hardware design reliability is also identified under the maintainability and reliability category. The third page specifies the mechanical design guidelines and assumptions. Described are the material types and weights, modules, and construction methods. Also described is an estimation of percentage of construction which utilizes a particular method, and the percentage of required new mechanical design is documented. The fourth page analyzes the electronics, the scope of design effort, and the software requirements. Electronics are described by percentages of component types and new design. The design effort, as well as, the software requirements are identified and categorized.

40 CFR 413.80 - Applicability: Description of the printed circuit board subcategory.

Code of Federal Regulations, 2010 CFR

2010-07-01

... 40 Protection of Environment 28 2010-07-01 2010-07-01 true Applicability: Description of the printed circuit board subcategory. 413.80 Section 413.80 Protection of Environment ENVIRONMENTAL PROTECTION AGENCY (CONTINUED) EFFLUENT GUIDELINES AND STANDARDS ELECTROPLATING POINT SOURCE CATEGORY Printed...

Adult Competency Education Kit. Basic Skills in Speaking, Math, and Reading for Employment. Part P: ACE Competency Based Job Descriptions: #77--Secretary; #78--Keypunch Operator; Assembly Worker Core Job Description; #82--Electronics Assembler; #83--Printed Circuit Assembler; #84--Micro Electronics Assembler; #85--Chassis Assembler; #87--Machinist Apprentice.

ERIC Educational Resources Information Center

San Mateo County Office of Education, Redwood City, CA. Career Preparation Centers.

This thirteenth of fifteen sets of Adult Competency Education (ACE) Competency Based Job Descriptions in the ACE kit contains job descriptions for Secretary, Keypunch Operator, Electronics Assembler, Printed Circuit Assembler, Micro Electronincs Assembler, Chassis Assembler, and Machinist Apprentice. Each begins with a fact sheet that includes…

Space Telecommunications Radio Systems (STRS) Hardware Architecture Standard: Release 1.0 Hardware Section

NASA Technical Reports Server (NTRS)

Reinhart, Richard C.; Kacpura, Thomas J.; Smith, Carl R.; Liebetreu, John; Hill, Gary; Mortensen, Dale J.; Andro, Monty; Scardelletti, Maximilian C.; Farrington, Allen

2008-01-01

This report defines a hardware architecture approach for software-defined radios to enable commonality among NASA space missions. The architecture accommodates a range of reconfigurable processing technologies including general-purpose processors, digital signal processors, field programmable gate arrays, and application-specific integrated circuits (ASICs) in addition to flexible and tunable radiofrequency front ends to satisfy varying mission requirements. The hardware architecture consists of modules, radio functions, and interfaces. The modules are a logical division of common radio functions that compose a typical communication radio. This report describes the architecture details, the module definitions, the typical functions on each module, and the module interfaces. Tradeoffs between component-based, custom architecture and a functional-based, open architecture are described. The architecture does not specify a physical implementation internally on each module, nor does the architecture mandate the standards or ratings of the hardware used to construct the radios.

Evaluation of hardware costs of implementing PSK signal detection circuit based on "system on chip"

NASA Astrophysics Data System (ADS)

Sokolovskiy, A. V.; Dmitriev, D. D.; Veisov, E. A.; Gladyshev, A. B.

2018-05-01

The article deals with the choice of the architecture of digital signal processing units for implementing the PSK signal detection scheme. As an assessment of the effectiveness of architectures, the required number of shift registers and computational processes are used when implementing the "system on a chip" on the chip. A statistical estimation of the normalized code sequence offset in the signal synchronization scheme for various hardware block architectures is used.

Analog Integrated Circuit Design for Spike Time Dependent Encoder and Reservoir in Reservoir Computing Processors

DTIC Science & Technology

2018-01-01

14. ABSTRACT The objective of this effort was to: (a) develop novel and fundamental methodologies for data representation using hardware-based spike...Distribution Unlimited. 1 1.0 SUMMARY This effort is a critical part of an overall program to develop novel and fundamental methodologies for data...to fabrication a dynamic-reservoir circuit that utilizes sensory encoding methodologies similar to those employed in biological brains. Inspired

Bridging the Hardware-Software Gap: A Proof Carrying Approach for Computer Systems Trust Evaluation (5.3.5)

DTIC Science & Technology

2017-08-22

has significantly lowered the design cost and shortened the time-to- market (TTM) of Integrated Circuits (ICs) in the electronic industry. Over the...semiconductor companies have focused on high-profit phases such as design, marketing , and sales and have outsourced chip manufacturing, wafer fabrication...supply chain has significantly lowered the design cost and shortened the time- to- market (TTM) of integrated circuits (ICs) in the electronic

Multi-factor authentication

DOEpatents

Hamlet, Jason R; Pierson, Lyndon G

2014-10-21

Detection and deterrence of spoofing of user authentication may be achieved by including a cryptographic fingerprint unit within a hardware device for authenticating a user of the hardware device. The cryptographic fingerprint unit includes an internal physically unclonable function ("PUF") circuit disposed in or on the hardware device, which generates a PUF value. Combining logic is coupled to receive the PUF value, combines the PUF value with one or more other authentication factors to generate a multi-factor authentication value. A key generator is coupled to generate a private key and a public key based on the multi-factor authentication value while a decryptor is coupled to receive an authentication challenge posed to the hardware device and encrypted with the public key and coupled to output a response to the authentication challenge decrypted with the private key.

Hierarchical MFMO Circuit Modules for an Energy-Efficient SDR DBF

NASA Astrophysics Data System (ADS)

Mar, Jeich; Kuo, Chi-Cheng; Wu, Shin-Ru; Lin, You-Rong

The hierarchical multi-function matrix operation (MFMO) circuit modules are designed using coordinate rotations digital computer (CORDIC) algorithm for realizing the intensive computation of matrix operations. The paper emphasizes that the designed hierarchical MFMO circuit modules can be used to develop a power-efficient software-defined radio (SDR) digital beamformer (DBF). The formulas of the processing time for the scalable MFMO circuit modules implemented in field programmable gate array (FPGA) are derived to allocate the proper logic resources for the hardware reconfiguration. The hierarchical MFMO circuit modules are scalable to the changing number of array branches employed for the SDR DBF to achieve the purpose of power saving. The efficient reuse of the common MFMO circuit modules in the SDR DBF can also lead to energy reduction. Finally, the power dissipation and reconfiguration function in the different modes of the SDR DBF are observed from the experiment results.

Novel Quaternary Quantum Decoder, Multiplexer and Demultiplexer Circuits

NASA Astrophysics Data System (ADS)

Haghparast, Majid; Monfared, Asma Taheri

2017-05-01

Multiple valued logic is a promising approach to reduce the width of the reversible or quantum circuits, moreover, quaternary logic is considered as being a good choice for future quantum computing technology hence it is very suitable for the encoded realization of binary logic functions through its grouping of 2-bits together into quaternary values. The Quaternary decoder, multiplexer, and demultiplexer are essential units of quaternary digital systems. In this paper, we have initially designed a quantum realization of the quaternary decoder circuit using quaternary 1-qudit gates and quaternary Muthukrishnan-Stroud gates. Then we have presented quantum realization of quaternary multiplexer and demultiplexer circuits using the constructed quaternary decoder circuit and quaternary controlled Feynman gates. The suggested circuits in this paper have a lower quantum cost and hardware complexity than the existing designs that are currently used in quaternary digital systems. All the scales applied in this paper are based on Nanometric area.

Designing Novel Quaternary Quantum Reversible Subtractor Circuits

NASA Astrophysics Data System (ADS)

Haghparast, Majid; Monfared, Asma Taheri

2018-01-01

Reversible logic synthesis is an important area of current research because of its ability to reduce energy dissipation. In recent years, multiple valued logic has received great attention due to its ability to reduce the width of the reversible circuit which is a main requirement in quantum technology. Subtractor circuits are between major components used in quantum computers. In this paper, we will discuss the design of a quaternary quantum reversible half subtractor circuit using quaternary 1-qudit, 2-qudit Muthukrishnan-Stroud and 3-qudit controlled gates and a 2-qudit Generalized quaternary gate. Then a design of a quaternary quantum reversible full subtractor circuit based on the quaternary half subtractor will be presenting. The designs shall then be evaluated in terms of quantum cost, constant input, garbage output, and hardware complexity. The proposed quaternary quantum reversible circuits are the first attempt in the designing of the aforementioned subtractor.

QUARTERLY TECHNICAL PROGRESS REPORT, JULY, AUGUST, SEPTEMBER 1967.

DTIC Science & Technology

Contents: Circuit research program; Hardware systems research; Computer system software research; Illinois pattern recognition computer: ILLIAC II... service , use, and program development; IBM 7094/1401 service , use, and program development; Problem specifications; General laboratory information.

Demonstration Advanced Avionics System (DAAS), Phase 1

NASA Technical Reports Server (NTRS)

Bailey, A. J.; Bailey, D. G.; Gaabo, R. J.; Lahn, T. G.; Larson, J. C.; Peterson, E. M.; Schuck, J. W.; Rodgers, D. L.; Wroblewski, K. A.

1981-01-01

Demonstration advanced anionics system (DAAS) function description, hardware description, operational evaluation, and failure mode and effects analysis (FMEA) are provided. Projected advanced avionics system (PAAS) description, reliability analysis, cost analysis, maintainability analysis, and modularity analysis are discussed.

[Development and test of a wheat chlorophyll, nitrogen and water content meter].

PubMed

Yu, Bo; Sun, Ming; Han, Shu-Qing; Xia, Jin-Wen

2011-08-01

A portable meter was developed which can detect chlorophyll, nitrogen and moisture content of wheat leaf simultaneously, and can supply enough data for guiding fertilization and irrigation. This meter is composed of light path and electronic circuit. And this meter uses 660, 940 and 1450 nm LED together with narrow band filters as the active light source. The hardware circuit consists of micro-controller, LED drive circuit, detector, communication circuit, keyboard and LCD circuit. The meter was tested in the field and performed well with good repeatability and accuracy. The relative errors of chlorophyll and nitrogen test were about 10%, relative error for water content was 4%. The coefficients of variation of the three indices were all below 1.5%. All of these prove that the meter can be applied under the field condition to guide the wheat production.

Area, speed and power measurements of FPGA-based complex orthogonal space-time block code channel encoders

NASA Astrophysics Data System (ADS)

Passas, Georgios; Freear, Steven; Fawcett, Darren

2010-01-01

Space-time coding (STC) is an important milestone in modern wireless communications. In this technique, more copies of the same signal are transmitted through different antennas (space) and different symbol periods (time), to improve the robustness of a wireless system by increasing its diversity gain. STCs are channel coding algorithms that can be readily implemented on a field programmable gate array (FPGA) device. This work provides some figures for the amount of required FPGA hardware resources, the speed that the algorithms can operate and the power consumption requirements of a space-time block code (STBC) encoder. Seven encoder very high-speed integrated circuit hardware description language (VHDL) designs have been coded, synthesised and tested. Each design realises a complex orthogonal space-time block code with a different transmission matrix. All VHDL designs are parameterisable in terms of sample precision. Precisions ranging from 4 bits to 32 bits have been synthesised. Alamouti's STBC encoder design [Alamouti, S.M. (1998), 'A Simple Transmit Diversity Technique for Wireless Communications', IEEE Journal on Selected Areas in Communications, 16:55-108.] proved to be the best trade-off, since it is on average 3.2 times smaller, 1.5 times faster and requires slightly less power than the next best trade-off in the comparison, which is a 3/4-rate full-diversity 3Tx-antenna STBC.

Design and Development of a CPCI-Based Electronics Package for Space Station Experiments

NASA Technical Reports Server (NTRS)

Kolacz, John S.; Clapper, Randy S.; Wade, Raymond P.

2006-01-01

The NASA John H. Glenn Research Center is developing a Compact-PCI (CPCI) based electronics package for controlling space experiment hardware on the International Space Station. Goals of this effort include an easily modified, modular design that allows for changes in experiment requirements. Unique aspects of the experiment package include a flexible circuit used for internal interconnections and a separate enclosure (box in a box) for controlling 1 kW of power for experiment fuel heating requirements. This electronics package was developed as part of the FEANICS (Flow Enclosure Accommodating Novel Investigations in Combustion of Solids) mini-facility which is part of the Fluids and Combustion Facility s Combustion Integrated Rack (CIR). The CIR will be the platform for future microgravity combustion experiments and will reside on the Destiny Module of the International Space Station (ISS). The FEANICS mini-facility will be the primary means for conducting solid fuel combustion experiments in the CIR on ISS. The main focus of many of these solid combustion experiments will be to conduct applied scientific investigations in fire-safety to support NASA s future space missions. A description of the electronics package and the results of functional testing are the subjects of this report. The report concludes that the use of innovative packaging methods combined with readily available COTS hardware can provide a modular electronics package which is easily modified for changing experiment requirements.

Waveform Developer's Guide for the Integrated Power, Avionics, and Software (iPAS) Space Telecommunications Radio System (STRS) Radio

NASA Technical Reports Server (NTRS)

Shalkhauser, Mary Jo W.; Roche, Rigoberto

2017-01-01

The Space Telecommunications Radio System (STRS) provides a common, consistent framework for software defined radios (SDRs) to abstract the application software from the radio platform hardware. The STRS standard aims to reduce the cost and risk of using complex, configurable and reprogrammable radio systems across NASA missions. To promote the use of the STRS architecture for future NASA advanced exploration missions, NASA Glenn Research Center (GRC) developed an STRS-compliant SDR on a radio platform used by the Advance Exploration System program at the Johnson Space Center (JSC) in their Integrated Power, Avionics, and Software (iPAS) laboratory. The iPAS STRS Radio was implemented on the Reconfigurable, Intelligently-Adaptive Communication System (RIACS) platform, currently being used for radio development at JSC. The platform consists of a Xilinx(Trademark) ML605 Virtex(Trademark)-6 FPGA board, an Analog Devices FMCOMMS1-EBZ RF transceiver board, and an Embedded PC (Axiomtek(Trademark) eBox 620-110-FL) running the Ubuntu 12.4 operating system. The result of this development is a very low cost STRS compliant platform that can be used for waveform developments for multiple applications. The purpose of this document is to describe how to develop a new waveform using the RIACS platform and the Very High Speed Integrated Circuits (VHSIC) Hardware Description Language (VHDL) FPGA wrapper code and the STRS implementation on the Axiomtek processor.

Autonomous Lawnmower using FPGA implementation.

NASA Astrophysics Data System (ADS)

Ahmad, Nabihah; Lokman, Nabill bin; Helmy Abd Wahab, Mohd

2016-11-01

Nowadays, there are various types of robot have been invented for multiple purposes. The robots have the special characteristic that surpass the human ability and could operate in extreme environment which human cannot endure. In this paper, an autonomous robot is built to imitate the characteristic of a human cutting grass. A Field Programmable Gate Array (FPGA) is used to control the movements where all data and information would be processed. Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) is used to describe the hardware using Quartus II software. This robot has the ability of avoiding obstacle using ultrasonic sensor. This robot used two DC motors for its movement. It could include moving forward, backward, and turning left and right. The movement or the path of the automatic lawn mower is based on a path planning technique. Four Global Positioning System (GPS) plot are set to create a boundary. This to ensure that the lawn mower operates within the area given by user. Every action of the lawn mower is controlled by the FPGA DE' Board Cyclone II with the help of the sensor. Furthermore, Sketch Up software was used to design the structure of the lawn mower. The autonomous lawn mower was able to operate efficiently and smoothly return to coordinated paths after passing the obstacle. It uses 25% of total pins available on the board and 31% of total Digital Signal Processing (DSP) blocks.

Analog Ranging Modem Code Processor and Generator

DOT National Transportation Integrated Search

1974-05-01

The report details technical development efforts to implement an analog ranging modem using recently developed linear integrated circuits where possible. The breadboard hardware is capable of acquiring frequency and phase of a weak signal in a high n...

Optical Multiple Access Network (OMAN) for advanced processing satellite applications

NASA Technical Reports Server (NTRS)

Mendez, Antonio J.; Gagliardi, Robert M.; Park, Eugene; Ivancic, William D.; Sherman, Bradley D.

1991-01-01

An OMAN breadboard for exploring advanced processing satellite circuit switch applications is introduced. Network architecture, hardware trade offs, and multiple user interference issues are presented. The breadboard test set up and experimental results are discussed.

Learning and optimization with cascaded VLSI neural network building-block chips

NASA Technical Reports Server (NTRS)

Duong, T.; Eberhardt, S. P.; Tran, M.; Daud, T.; Thakoor, A. P.

1992-01-01

To demonstrate the versatility of the building-block approach, two neural network applications were implemented on cascaded analog VLSI chips. Weights were implemented using 7-b multiplying digital-to-analog converter (MDAC) synapse circuits, with 31 x 32 and 32 x 32 synapses per chip. A novel learning algorithm compatible with analog VLSI was applied to the two-input parity problem. The algorithm combines dynamically evolving architecture with limited gradient-descent backpropagation for efficient and versatile supervised learning. To implement the learning algorithm in hardware, synapse circuits were paralleled for additional quantization levels. The hardware-in-the-loop learning system allocated 2-5 hidden neurons for parity problems. Also, a 7 x 7 assignment problem was mapped onto a cascaded 64-neuron fully connected feedback network. In 100 randomly selected problems, the network found optimal or good solutions in most cases, with settling times in the range of 7-100 microseconds.

Hardware/software codesign for embedded RISC core

NASA Astrophysics Data System (ADS)

Liu, Peng

2001-12-01

This paper describes hardware/software codesign method of the extendible embedded RISC core VIRGO, which based on MIPS-I instruction set architecture. VIRGO is described by Verilog hardware description language that has five-stage pipeline with shared 32-bit cache/memory interface, and it is controlled by distributed control scheme. Every pipeline stage has one small controller, which controls the pipeline stage status and cooperation among the pipeline phase. Since description use high level language and structure is distributed, VIRGO core has highly extension that can meet the requirements of application. We take look at the high-definition television MPEG2 MPHL decoder chip, constructed the hardware/software codesign virtual prototyping machine that can research on VIRGO core instruction set architecture, and system on chip memory size requirements, and system on chip software, etc. We also can evaluate the system on chip design and RISC instruction set based on the virtual prototyping machine platform.

A Computer Scientist’s Evaluation of Publically Available Hardware Trojan Benchmarks

DTIC Science & Technology

2015-09-01

in the Verilog file round.v. This module represents the tenth round of the AES encryption process. This round is similar to previous rounds. It...the round keys used during the AES encryption process. Note that the last two round keys are not leaked, but we assume that the attacker either...undermine the effectiveness of a 128-bit AES encryption circuit. These circuits are labelled AES -T100 through AES -T2100. The naming convention

Development and characteristics of the hardware for Skylab experiment S015

NASA Technical Reports Server (NTRS)

Thirolf, R. G.

1975-01-01

Details are given regarding the hardware for the Skylab S015 experiment, which was designed to detect the effects of zero gravity on cell growth rates. Experience gained in hardware-related considerations is presented for use of researchers concerned with future research of this type and further study of the S015 results. Brief descriptions are given of the experiment hardware, the hardware configuration for the critical design review, the major configuration changes, the final configuration, and the postflight review and analysis. An appendix describes pertinent documentation, film, and hardware that are available to qualified researchers; sources for additional or special information are given.

Hardware and software status of QCDOC

NASA Astrophysics Data System (ADS)

Boyle, P. A.; Chen, D.; Christ, N. H.; Clark, M.; Cohen, S. D.; Cristian, C.; Dong, Z.; Gara, A.; Joó, B.; Jung, C.; Kim, C.; Levkova, L.; Liao, X.; Liu, G.; Mawhinney, R. D.; Ohta, S.; Petrov, K.; Wettig, T.; Yamaguchi, A.

2004-03-01

QCDOC is a massively parallel supercomputer whose processing nodes are based on an application-specific integrated circuit (ASIC). This ASIC was custom-designed so that crucial lattice QCD kernels achieve an overall sustained performance of 50% on machines with several 10,000 nodes. This strong scalability, together with low power consumption and a price/performance ratio of $1 per sustained MFlops, enable QCDOC to attack the most demanding lattice QCD problems. The first ASICs became available in June of 2003, and the testing performed so far has shown all systems functioning according to specification. We review the hardware and software status of QCDOC and present performance figures obtained in real hardware as well as in simulation.

Logic design for dynamic and interactive recovery.

NASA Technical Reports Server (NTRS)

Carter, W. C.; Jessep, D. C.; Wadia, A. B.; Schneider, P. R.; Bouricius, W. G.

1971-01-01

Recovery in a fault-tolerant computer means the continuation of system operation with data integrity after an error occurs. This paper delineates two parallel concepts embodied in the hardware and software functions required for recovery; detection, diagnosis, and reconfiguration for hardware, data integrity, checkpointing, and restart for the software. The hardware relies on the recovery variable set, checking circuits, and diagnostics, and the software relies on the recovery information set, audit, and reconstruct routines, to characterize the system state and assist in recovery when required. Of particular utility is a handware unit, the recovery control unit, which serves as an interface between error detection and software recovery programs in the supervisor and provides dynamic interactive recovery.

A low-cost universal cumulative gating circuit for small and large animal clinical imaging

NASA Astrophysics Data System (ADS)

Gioux, Sylvain; Frangioni, John V.

2008-02-01

Image-assisted diagnosis and therapy is becoming more commonplace in medicine. However, most imaging techniques suffer from voluntary or involuntary motion artifacts, especially cardiac and respiratory motions, which degrade image quality. Current software solutions either induce computational overhead or reject out-of-focus images after acquisition. In this study we demonstrate a hardware-only gating circuit that accepts multiple, pseudo-periodic signals and produces a single TTL (0-5 V) imaging window of accurate phase and period. The electronic circuit Gerber files described in this article and the list of components are available online at www.frangionilab.org.

Recycling Flight Hardware Components and Systems to Reduce Next Generation Research Costs

NASA Technical Reports Server (NTRS)

Turner, Wlat

2011-01-01

With the recent 'new direction' put forth by President Obama identifying NASA's new focus in research rather than continuing on a path to return to the Moon and Mars, the focus of work at Kennedy Space Center (KSC) may be changing dramatically. Research opportunities within the micro-gravity community potentially stands at the threshold of resurgence when the new direction of the agency takes hold for the next generation of experimenters. This presentation defines a strategy for recycling flight experiment components or part numbers, in order to reduce research project costs, not just in component selection and fabrication, but in expediting qualification of hardware for flight. A key component of the strategy is effective communication of relevant flight hardware information and available flight hardware components to researchers, with the goal of 'short circuiting' the design process for flight experiments

Optimization and development of solar power system under diffused sunlight condition in rural areas with supercapacitor integration

NASA Astrophysics Data System (ADS)

Castelino, Roystan V.; Jana, Suman; Kumhar, Rajesh; Singh, Niraj K.

2018-04-01

The simulation and hardware based experiment in this presented paper shows a possibility of increasing the reliability of solar power under diffused condition by using super capacitor module. This experimental setup can be used in those areas where the sun light is intermittent and under the diffused radiation condition. Due to diffused radiation, solar PV cells operate very poorly, but by using this setup the power efficiency can be increased greatly. Sometimes dependent numerical models are used to measure the voltage and current response of the hardware setup in MATLAB Simulink based environment. To convert the scattered solar radiation to electricity using the conventional solar PV module, batteries have to be linked with the rapid charging or discharging device like super capacitor module. The conventional method consists of a charging circuit, which dumps the power if the voltage is below certain voltage level, but this circuit utilizes the entire power even if the voltage is low under diffused sun light conditions. There is no power dumped in this circuit. The efficiency and viability of this labscale experimental setup can be examined with further experiment and industrial model.

Study and design on USB wireless laser communication system

NASA Astrophysics Data System (ADS)

Wang, Aihua; Zheng, Jiansheng; Ai, Yong

2004-04-01

We give the definition of USB wireless laser communication system (WLCS) and the brief introduction to the protocol of USB, the standard of hardware is also given. The paper analyses the hardware and software of USB WLCS. Wireless laser communication part and USB interface circuit part are discussed in detail. We also give the periphery design of the chip AN2131Q, the control circuit to realize the transformation from parallel port to serial bus, and the circuit of laser sending and receiving of laser communication part, which are simply, cheap and workable. And then the four part of software are analyzed as followed. We have consummated the ISR in the firmware frame to develop the periphery device of USB. We have debugged and consummated the 'ezload,' and the GPD of the drivers. Windows application performs functions and schedules the corresponding API functions to let the interface practical and beautiful. The system can realize USB wireless laser communication between computers, which distance is farther than 50 meters, and top speed can be bigger than 8 Mbps. The system is of great practical sense to resolve the issues of high-speed communication among increasing districts without fiber trunk network.

Building Security into Schools.

ERIC Educational Resources Information Center

Kosar, John E.; Ahmed, Faruq

2000-01-01

Offers tips for redesigning safer school sites; installing and implementing security technologies (closed-circuit television cameras, door security hardware, electronic security panels, identification cards, metal detectors, and panic buttons); educating students and staff about security functions; and minimizing costs via a comprehensive campus…

Historical Perspective on Technology and Music.

ERIC Educational Resources Information Center

Webster, Peter

2002-01-01

Explores the historical developments in technology that affected music education. Describes the developments in hardware, such as gears and levers, electricity, vacuum tubes, transistors, and integrated circuits. Discusses the changes in computer software from the 1950s to the present. (CMK)

Instrumentation Hardware Abstraction Language (IHAL) Handbook

DTIC Science & Technology

2017-01-01

1-1 1.1 The Range Commanders Council (RCC) and IHAL ....................................................... 1-1 1.2 Problem Description ...1-5 1.3.1 IHAL as a Description Language...Figure 2-6. Generic IHAL Device Schema Diagram ............................................................. 2-7 Figure 2-7. Device Description Schema

Vehicle infrastructure integration proof of concept : technical description--vehicle : final report

DOT National Transportation Integrated Search

2009-05-19

This report provides the technical description of the VII system developed for the Cooperative Agreement VII Program between the USDOT and the VII Consortium. The basic architectural elements are summarized and detailed descriptions of the hardware a...

Printed wiring board system programmer's manual

NASA Technical Reports Server (NTRS)

Brinkerhoff, C. D.

1973-01-01

The printed wiring board system provides automated techniques for the design of printed circuit boards and hybrid circuit boards. The system consists of four programs: (1) the preprocessor program combines user supplied data and pre-defined library data to produce the detailed circuit description data; (2) the placement program assigns circuit components to specific areas of the board in a manner that optimizes the total interconnection length of the circuit; (3) the organizer program assigns pin interconnections to specific board levels and determines the optimal order in which the router program should attempt to layout the paths connecting the pins; and (4) the router program determines the wire paths which are to be used to connect each input pin pair on the circuit board. This document is intended to serve as a programmer's reference manual for the printed wiring board system. A detailed description of the internal logic and flow of the printed wiring board programs is included.

Safety-related requirements for photovoltaic modules and arrays. Final report

DOE Office of Scientific and Technical Information (OSTI.GOV)

Levins, A.

1984-03-01

Underwriters Laboratories has conducted a study to identify and develop safety requirements for photovoltaic module and panel designs and configurations for residential, intermediate, and large scale applications. Concepts for safety systems, where each system is a collection of subsystems which together address the total anticipated hazard situation, are described. Descriptions of hardware, and system usefulness and viability are included. This discussion of safety systems recognizes that there is little history on which to base the expected safety related performance of a photovoltaic system. A comparison of these systems, as against the provisions of the 1984 National Electrical Code covering photovoltaicmore » systems is made. A discussion of the UL investigation of the photovoltaic module evaluated to the provisions of the Proposed UL Standard for Flat-Plate Photovoltaic Modules and Panels is included. Grounding systems, their basis and nature, and the advantages and disadvantages of each are described. The meaning of frame grounding, circuit grounding, and the type of circuit ground are covered. The development of the Standard for Flat-Plate Photovoltaic Modules and Panels has continued, and with both industry comment and a product submittal and listing, the Standard has been refined to a viable document allowing an objective safety review of photovoltaic modules and panels. How this document, and other UL documents would cover investigations of certain other photovoltaic system components is described.« less

Hardware implementation of Lorenz circuit systems for secure chaotic communication applications.

PubMed

Chen, Hsin-Chieh; Liau, Ben-Yi; Hou, Yi-You

2013-02-18

This paper presents the synchronization between the master and slave Lorenz chaotic systems by slide mode controller (SMC)-based technique. A proportional-integral (PI) switching surface is proposed to simplify the task of assigning the performance of the closed-loop error system in sliding mode. Then, extending the concept of equivalent control and using some basic electronic components, a secure communication system is constructed. Experimental results show the feasibility of synchronizing two Lorenz circuits via the proposed SMC. 

Harnessing vision for computation.

PubMed

Changizi, Mark

2008-01-01

Might it be possible to harness the visual system to carry out artificial computations, somewhat akin to how DNA has been harnessed to carry out computation? I provide the beginnings of a research programme attempting to do this. In particular, new techniques are described for building 'visual circuits' (or 'visual software') using wire, NOT, OR, and AND gates in a visual 6modality such that our visual system acts as 'visual hardware' computing the circuit, and generating a resultant perception which is the output.

Magnetophoretic circuits for digital control of single particles and cells

NASA Astrophysics Data System (ADS)

Lim, Byeonghwa; Reddy, Venu; Hu, Xinghao; Kim, Kunwoo; Jadhav, Mital; Abedini-Nassab, Roozbeh; Noh, Young-Woock; Lim, Yong Taik; Yellen, Benjamin B.; Kim, Cheolgi

2014-05-01

The ability to manipulate small fluid droplets, colloidal particles and single cells with the precision and parallelization of modern-day computer hardware has profound applications for biochemical detection, gene sequencing, chemical synthesis and highly parallel analysis of single cells. Drawing inspiration from general circuit theory and magnetic bubble technology, here we demonstrate a class of integrated circuits for executing sequential and parallel, timed operations on an ensemble of single particles and cells. The integrated circuits are constructed from lithographically defined, overlaid patterns of magnetic film and current lines. The magnetic patterns passively control particles similar to electrical conductors, diodes and capacitors. The current lines actively switch particles between different tracks similar to gated electrical transistors. When combined into arrays and driven by a rotating magnetic field clock, these integrated circuits have general multiplexing properties and enable the precise control of magnetizable objects.

Servo Platform Circuit Design of Pendulous Gyroscope Based on DSP

NASA Astrophysics Data System (ADS)

Tan, Lilong; Wang, Pengcheng; Zhong, Qiyuan; Zhang, Cui; Liu, Yunfei

2018-03-01

In order to solve the problem when a certain type of pendulous gyroscope in the initial installation deviation more than 40 degrees, that the servo platform can not be up to the speed of the gyroscope in the rough north seeking phase. This paper takes the digital signal processor TMS320F28027 as the core, uses incremental digital PID algorithm, carries out the circuit design of the servo platform. Firstly, the hardware circuit is divided into three parts: DSP minimum system, motor driving circuit and signal processing circuit, then the mathematical model of incremental digital PID algorithm is established, based on the model, writes the PID control program in CCS3.3, finally, the servo motor tracking control experiment is carried out, it shows that the design can significantly improve the tracking ability of the servo platform, and the design has good engineering practice.

Atomic memory access hardware implementations

DOEpatents

Ahn, Jung Ho; Erez, Mattan; Dally, William J

2015-02-17

Atomic memory access requests are handled using a variety of systems and methods. According to one example method, a data-processing circuit having an address-request generator that issues requests to a common memory implements a method of processing the requests using a memory-access intervention circuit coupled between the generator and the common memory. The method identifies a current atomic-memory access request from a plurality of memory access requests. A data set is stored that corresponds to the current atomic-memory access request in a data storage circuit within the intervention circuit. It is determined whether the current atomic-memory access request corresponds to at least one previously-stored atomic-memory access request. In response to determining correspondence, the current request is implemented by retrieving data from the common memory. The data is modified in response to the current request and at least one other access request in the memory-access intervention circuit.

Faster Evolution of More Multifunctional Logic Circuits

NASA Technical Reports Server (NTRS)

Stoica, Adrian; Zebulum, Ricardo

2005-01-01

A modification in a method of automated evolutionary synthesis of voltage-controlled multifunctional logic circuits makes it possible to synthesize more circuits in less time. Prior to the modification, the computations for synthesizing a four-function logic circuit by this method took about 10 hours. Using the method as modified, it is possible to synthesize a six-function circuit in less than half an hour. The concepts of automated evolutionary synthesis and voltage-controlled multifunctional logic circuits were described in a number of prior NASA Tech Briefs articles. To recapitulate: A circuit is designed to perform one of several different logic functions, depending on the value of an applied control voltage. The circuit design is synthesized following an automated evolutionary approach that is so named because it is modeled partly after the repetitive trial-and-error process of biological evolution. In this process, random populations of integer strings that encode electronic circuits play a role analogous to that of chromosomes. An evolved circuit is tested by computational simulation (prior to testing in real hardware to verify a final design). Then, in a fitness-evaluation step, responses of the circuit are compared with specifications of target responses and circuits are ranked according to how close they come to satisfying specifications. The results of the evaluation provide guidance for refining designs through further iteration.

Recent trends in hardware security exploiting hybrid CMOS-resistive memory circuits

NASA Astrophysics Data System (ADS)

Sahay, Shubham; Suri, Manan

2017-12-01

This paper provides a comprehensive review and insight of recent trends in the field of random number generator (RNG) and physically unclonable function (PUF) circuits implemented using different types of emerging resistive non-volatile (NVM) memory devices. We present a detailed review of hybrid RNG/PUF implementations based on the use of (i) Spin-Transfer Torque (STT-MRAM), and (ii) metal-oxide based (OxRAM), NVM devices. Various approaches on Hybrid CMOS-NVM RNG/PUF circuits are considered, followed by a discussion on different nanoscale device phenomena. Certain nanoscale device phenomena (variability/stochasticity etc), which are otherwise undesirable for reliable memory and storage applications, form the basis for low power and highly scalable RNG/PUF circuits. Detailed qualitative comparison and benchmarking of all implementations is performed.

Exploration and design of smart home circuit based on ZigBee

NASA Astrophysics Data System (ADS)

Luo, Huirong

2018-05-01

To apply ZigBee technique in smart home circuit design, in the hardware design link of ZigBee node, TI Company's ZigBee wireless communication chip CC2530 was used to complete the design of ZigBee RF module circuit and peripheral circuit. In addition, the function demand and the overall scheme of the intelligent system based on smart home furnishing were proposed. Finally, the smart home system was built by combining ZigBee network and intelligent gateway. The function realization, reliability and power consumption of ZigBee network were tested. The results showed that ZigBee technology was applied to smart home system, making it have some advantages in terms of flexibility, scalability, power consumption and indoor aesthetics. To sum up, the system has high application value.

Lithium Circuit Test Section Design and Fabrication

NASA Technical Reports Server (NTRS)

Godfroy, Thomas; Garber, Anne

2006-01-01

The Early Flight Fission - Test Facilities (EFF-TF) team has designed and built an actively pumped lithium flow circuit. Modifications were made to a circuit originally designed for NaK to enable the use of lithium that included application specific instrumentation and hardware. Component scale freeze/thaw tests were conducted to both gain experience with handling and behavior of lithium in solid and liquid form and to supply anchor data for a Generalized Fluid System Simulation Program (GFSSP) model that was modified to include the physics for freeze/thaw transitions. Void formation was investigated. The basic circuit components include: reactor segment, lithium to gas heat exchanger, electromagnetic (EM) liquid metal pump, load/drain reservoir, expansion reservoir, instrumentation, and trace heaters. This paper will discuss the overall system design and build and the component testing findings.

Lithium Circuit Test Section Design and Fabrication

NASA Astrophysics Data System (ADS)

Godfroy, Thomas; Garber, Anne; Martin, James

2006-01-01

The Early Flight Fission - Test Facilities (EFF-TF) team has designed and built an actively pumped lithium flow circuit. Modifications were made to a circuit originally designed for NaK to enable the use of lithium that included application specific instrumentation and hardware. Component scale freeze/thaw tests were conducted to both gain experience with handling and behavior of lithium in solid and liquid form and to supply anchor data for a Generalized Fluid System Simulation Program (GFSSP) model that was modified to include the physics for freeze/thaw transitions. Void formation was investigated. The basic circuit components include: reactor segment, lithium to gas heat exchanger, electromagnetic (EM) liquid metal pump, load/drain reservoir, expansion reservoir, instrumentation, and trace heaters. This paper discusses the overall system design and build and the component testing findings.

The dc power circuits: A compilation

NASA Technical Reports Server (NTRS)

1972-01-01

A compilation of reports concerning power circuits is presented for the dissemination of aerospace information to the general public as part of the NASA Technology Utilization Program. The descriptions for the electronic circuits are grouped as follows: dc power supplies, power converters, current-voltage power supply regulators, overload protection circuits, and dc constant current power supplies.

Fundamentals of Hardware. Curriculum Improvement Project. Region II.

ERIC Educational Resources Information Center

Onabajo, Femi

This course curriculum is intended for use by community college instructors and administrators in implementing a fundamentals in hardware course. A student's course syllabus provides this information: credit hours, catalog description, prerequisites, required text, instructional process, objectives, student evaluation, and class schedule. A…

Hardware Architecture Study for NASA's Space Software Defined Radios

NASA Technical Reports Server (NTRS)

Reinhart, Richard C.; Scardelletti, Maximilian C.; Mortensen, Dale J.; Kacpura, Thomas J.; Andro, Monty; Smith, Carl; Liebetreu, John

2008-01-01

This study defines a hardware architecture approach for software defined radios to enable commonality among NASA space missions. The architecture accommodates a range of reconfigurable processing technologies including general purpose processors, digital signal processors, field programmable gate arrays (FPGAs), and application-specific integrated circuits (ASICs) in addition to flexible and tunable radio frequency (RF) front-ends to satisfy varying mission requirements. The hardware architecture consists of modules, radio functions, and and interfaces. The modules are a logical division of common radio functions that comprise a typical communication radio. This paper describes the architecture details, module definitions, and the typical functions on each module as well as the module interfaces. Trade-offs between component-based, custom architecture and a functional-based, open architecture are described. The architecture does not specify the internal physical implementation within each module, nor does the architecture mandate the standards or ratings of the hardware used to construct the radios.

Error protection capability of space shuttle data bus designs

NASA Technical Reports Server (NTRS)

Proch, G. E.

1974-01-01

Error protection assurance in the reliability of digital data communications is discussed. The need for error protection on the space shuttle data bus system has been recognized and specified as a hardware requirement. The error protection techniques of particular concern are those designed into the Shuttle Main Engine Interface (MEI) and the Orbiter Multiplex Interface Adapter (MIA). The techniques and circuit design details proposed for these hardware are analyzed in this report to determine their error protection capability. The capability is calculated in terms of the probability of an undetected word error. Calculated results are reported for a noise environment that ranges from the nominal noise level stated in the hardware specifications to burst levels which may occur in extreme or anomalous conditions.

Electronic neural networks for global optimization

NASA Technical Reports Server (NTRS)

Thakoor, A. P.; Moopenn, A. W.; Eberhardt, S.

1990-01-01

An electronic neural network with feedback architecture, implemented in analog custom VLSI is described. Its application to problems of global optimization for dynamic assignment is discussed. The convergence properties of the neural network hardware are compared with computer simulation results. The neural network's ability to provide optimal or near optimal solutions within only a few neuron time constants, a speed enhancement of several orders of magnitude over conventional search methods, is demonstrated. The effect of noise on the circuit dynamics and the convergence behavior of the neural network hardware is also examined.

Simplifying the circuit of Josephson parametric converters

NASA Astrophysics Data System (ADS)

Abdo, Baleegh; Brink, Markus; Chavez-Garcia, Jose; Keefe, George

Josephson parametric converters (JPCs) are quantum-limited three-wave mixing devices that can play various important roles in quantum information processing in the microwave domain, including amplification of quantum signals, transduction of quantum information, remote entanglement of qubits, nonreciprocal amplification, and circulation of signals. However, the input-output and biasing circuit of a state-of-the-art JPC consists of bulky components, i.e. two commercial off-chip broadband 180-degree hybrids, four phase-matched short coax cables, and one superconducting magnetic coil. Such bulky hardware significantly hinders the integration of JPCs in scalable quantum computing architectures. In my talk, I will present ideas on how to simplify the JPC circuit and show preliminary experimental results

QUARTERLY TECHNICAL PROGRESS REPORT, JULY, AUGUST, SEPTEMBER 1966.

DTIC Science & Technology

Contents: Circuit research program; Hardware systems research; Software systems research program; Numerical methods, computer arithmetic and...artificial languages; Library automation; Illiac II service , use, and program development; IBM service , use, and program development; Problem specifications; Switching theory and logical design; General laboratory information.

Optimizations of a Hardware Decoder for Deep-Space Optical Communications

NASA Technical Reports Server (NTRS)

Cheng, Michael K.; Nakashima, Michael A.; Moision, Bruce E.; Hamkins, Jon

2007-01-01

The National Aeronautics and Space Administration has developed a capacity approaching modulation and coding scheme that comprises a serial concatenation of an inner accumulate pulse-position modulation (PPM) and an outer convolutional code [or serially concatenated PPM (SCPPM)] for deep-space optical communications. Decoding of this code uses the turbo principle. However, due to the nonbinary property of SCPPM, a straightforward application of classical turbo decoding is very inefficient. Here, we present various optimizations applicable in hardware implementation of the SCPPM decoder. More specifically, we feature a Super Gamma computation to efficiently handle parallel trellis edges, a pipeline-friendly 'maxstar top-2' circuit that reduces the max-only approximation penalty, a low-latency cyclic redundancy check circuit for window-based decoders, and a high-speed algorithmic polynomial interleaver that leads to memory savings. Using the featured optimizations, we implement a 6.72 megabits-per-second (Mbps) SCPPM decoder on a single field-programmable gate array (FPGA). Compared to the current data rate of 256 kilobits per second from Mars, the SCPPM coded scheme represents a throughput increase of more than twenty-six fold. Extension to a 50-Mbps decoder on a board with multiple FPGAs follows naturally. We show through hardware simulations that the SCPPM coded system can operate within 1 dB of the Shannon capacity at nominal operating conditions.

Using MaxCompiler for the high level synthesis of trigger algorithms

NASA Astrophysics Data System (ADS)

Summers, S.; Rose, A.; Sanders, P.

2017-02-01

Firmware for FPGA trigger applications at the CMS experiment is conventionally written using hardware description languages such as Verilog and VHDL. MaxCompiler is an alternative, Java based, tool for developing FPGA applications which uses a higher level of abstraction from the hardware than a hardware description language. An implementation of the jet and energy sum algorithms for the CMS Level-1 calorimeter trigger has been written using MaxCompiler to benchmark against the VHDL implementation in terms of accuracy, latency, resource usage, and code size. A Kalman Filter track fitting algorithm has been developed using MaxCompiler for a proposed CMS Level-1 track trigger for the High-Luminosity LHC upgrade. The design achieves a low resource usage, and has a latency of 187.5 ns per iteration.

The Application of the EIS in Li-ion Batteries Measurement

NASA Astrophysics Data System (ADS)

Zhai, N. S.; Li, M. W.; Wang, W. L.; Zhang, D. L.; Xu, D. G.

2006-10-01

The measurement and determination of the lithium ion battery's electrochemical impedance spectroscopy (EIS) and the application of EIS to battery classification are researched in this paper. The lithium ion battery gets extensive applications due to its inherent advantages over other batteries. For proper and sustainable performance, it is very necessary to check the uniformity of the lithium ion batteries. In this paper, the equivalent circuit of the lithium ion battery is analyzed; the design of hardware circuit based on DSP and software that calculates the EIS of the lithium ion battery is critically done and evaluated. The parameters of the lithium ion equivalent circuit are determined, the parameter values of li-ion equivalent circuit are achieved by least square method, and the application of Principal Component Analysis (CPA) to the battery classification is analyzed.

Remote Memory Access Protocol Target Node Intellectual Property

NASA Technical Reports Server (NTRS)

Haddad, Omar

2013-01-01

The MagnetoSpheric Multiscale (MMS) mission had a requirement to use the Remote Memory Access Protocol (RMAP) over its SpaceWire network. At the time, no known intellectual property (IP) cores were available for purchase. Additionally, MMS preferred to implement the RMAP functionality with control over the low-level details of the design. For example, not all the RMAP standard functionality was needed, and it was desired to implement only the portions of the RMAP protocol that were needed. RMAP functionality had been previously implemented in commercial off-the-shelf (COTS) products, but the IP core was not available for purchase. The RMAP Target IP core is a VHDL (VHSIC Hardware Description Language description of a digital logic design suitable for implementation in an FPGA (field-programmable gate array) or ASIC (application-specific integrated circuit) that parses SpaceWire packets that conform to the RMAP standard. The RMAP packet protocol allows a network host to access and control a target device using address mapping. This capability allows SpaceWire devices to be managed in a standardized way that simplifies the hardware design of the device, as well as the development of the software that controls the device. The RMAP Target IP core has some features that are unique and not specified in the RMAP standard. One such feature is the ability to automatically abort transactions if the back-end logic does not respond to read/write requests within a predefined time. When a request times out, the RMAP Target IP core automatically retracts the request and returns a command response with an appropriate status in the response packet s header. Another such feature is the ability to control the SpaceWire node or router using RMAP transactions in the extended address range. This allows the SpaceWire network host to manage the SpaceWire network elements using RMAP packets, which reduces the number of protocols that the network host needs to support.

15 CFR Supplement No. 6 to Part 742 - Technical Questionnaire for Encryption Items

Code of Federal Regulations, 2012 CFR

2012-01-01

... software, provide the following information: (1) Description of all the symmetric and asymmetric encryption... third-party hardware or software encryption components (if any). Identify the manufacturers of the hardware or software components, including specific part numbers and version information as needed to...

15 CFR Supplement No. 6 to Part 742 - Technical Questionnaire for Encryption Items

Code of Federal Regulations, 2013 CFR

2013-01-01

... software, provide the following information: (1) Description of all the symmetric and asymmetric encryption... third-party hardware or software encryption components (if any). Identify the manufacturers of the hardware or software components, including specific part numbers and version information as needed to...

15 CFR Supplement No. 6 to Part 742 - Technical Questionnaire for Encryption Items

Code of Federal Regulations, 2014 CFR

2014-01-01

... software, provide the following information: (1) Description of all the symmetric and asymmetric encryption... third-party hardware or software encryption components (if any). Identify the manufacturers of the hardware or software components, including specific part numbers and version information as needed to...

Hardware Algorithm Implementation for Mission Specific Processing

DTIC Science & Technology

2008-03-01

knowledge about the VLSI technology and understands VHDL, scripting, and intergrating the script in Cadencersoftware pro- gram or Modelsimr. The main...possible to have a trade off between parallel and serial logic design for the circuit. Power can be saved by using parallization, pipelining, or a

Hardware Trust Implications of 3-D Integration

DTIC Science & Technology

2010-12-01

between two points of the combined circuit, allowing more transistors to be placed closer to each other. The reduced global interconnect length, and the...Scandiuzzo, S. Cani, L. Perugini, E. Franchi , R. Canegallo, and R. Guerrieri. Chip-to-chip communication based on capacitive coupling. In Proceedings

Discharge Chamber Primary Electron Modeling Activities in Three-Dimensions

NASA Technical Reports Server (NTRS)

Steuber, Thomas J.

2004-01-01

Designing discharge chambers for ion thrusters involves many geometric configuration decisions. Various decisions will impact discharge chamber performance with respect to propellant utilization efficiency, ion production costs, and grid lifetime. These hardware design decisions can benefit from the assistance of computational modeling. Computational modeling for discharge chambers has been limited to two-dimensional codes that leveraged symmetry for interpretation into three-dimensional analysis. This paper presents model development activities towards a three-dimensional discharge chamber simulation to aid discharge chamber design decisions. Specifically, of the many geometric configuration decisions toward attainment of a worthy discharge chamber, this paper focuses on addressing magnetic circuit considerations with a three-dimensional discharge chamber simulation as a tool. With this tool, candidate discharge chamber magnetic circuit designs can be analyzed computationally to gain insight into factors that may influence discharge chamber performance such as: primary electron loss width in magnetic cusps, cathode tip position with respect to the low magnetic field volume, definition of a low magnetic field region, and maintenance of a low magnetic field region across the grid span. Corroborating experimental data will be obtained from mockup hardware tests. Initially, simulated candidate magnetic circuit designs will resemble previous successful thruster designs. To provide opportunity to improve beyond previous performance benchmarks, off-design modifications will be simulated and experimentally tested.

A Low Cost VLSI Architecture for Spike Sorting Based on Feature Extraction with Peak Search.

PubMed

Chang, Yuan-Jyun; Hwang, Wen-Jyi; Chen, Chih-Chang

2016-12-07

The goal of this paper is to present a novel VLSI architecture for spike sorting with high classification accuracy, low area costs and low power consumption. A novel feature extraction algorithm with low computational complexities is proposed for the design of the architecture. In the feature extraction algorithm, a spike is separated into two portions based on its peak value. The area of each portion is then used as a feature. The algorithm is simple to implement and less susceptible to noise interference. Based on the algorithm, a novel architecture capable of identifying peak values and computing spike areas concurrently is proposed. To further accelerate the computation, a spike can be divided into a number of segments for the local feature computation. The local features are subsequently merged with the global ones by a simple hardware circuit. The architecture can also be easily operated in conjunction with the circuits for commonly-used spike detection algorithms, such as the Non-linear Energy Operator (NEO). The architecture has been implemented by an Application-Specific Integrated Circuit (ASIC) with 90-nm technology. Comparisons to the existing works show that the proposed architecture is well suited for real-time multi-channel spike detection and feature extraction requiring low hardware area costs, low power consumption and high classification accuracy.

Energy efficiency of task allocation for embedded JPEG systems.

PubMed

Fan, Yang-Hsin; Wu, Jan-Ou; Wang, San-Fu

2014-01-01

Embedded system works everywhere for repeatedly performing a few particular functionalities. Well-known products include consumer electronics, smart home applications, and telematics device, and so forth. Recently, developing methodology of embedded systems is applied to conduct the design of cloud embedded system resulting in the applications of embedded system being more diverse. However, the more energy consumes result from the more embedded system works. This study presents hyperrectangle technology (HT) to embedded system for obtaining energy saving. The HT adopts drift effect to construct embedded systems with more hardware circuits than software components or vice versa. It can fast construct embedded system with a set of hardware circuits and software components. Moreover, it has a great benefit to fast explore energy consumption for various embedded systems. The effects are presented by assessing a JPEG benchmarks. Experimental results demonstrate that the HT, respectively, achieves the energy saving by 29.84%, 2.07%, and 68.80% on average to GA, GHO, and Lin.

Software-Reconfigurable Processors for Spacecraft

NASA Technical Reports Server (NTRS)

Farrington, Allen; Gray, Andrew; Bell, Bryan; Stanton, Valerie; Chong, Yong; Peters, Kenneth; Lee, Clement; Srinivasan, Jeffrey

2005-01-01

A report presents an overview of an architecture for a software-reconfigurable network data processor for a spacecraft engaged in scientific exploration. When executed on suitable electronic hardware, the software performs the functions of a physical layer (in effect, acts as a software radio in that it performs modulation, demodulation, pulse-shaping, error correction, coding, and decoding), a data-link layer, a network layer, a transport layer, and application-layer processing of scientific data. The software-reconfigurable network processor is undergoing development to enable rapid prototyping and rapid implementation of communication, navigation, and scientific signal-processing functions; to provide a long-lived communication infrastructure; and to provide greatly improved scientific-instrumentation and scientific-data-processing functions by enabling science-driven in-flight reconfiguration of computing resources devoted to these functions. This development is an extension of terrestrial radio and network developments (e.g., in the cellular-telephone industry) implemented in software running on such hardware as field-programmable gate arrays, digital signal processors, traditional digital circuits, and mixed-signal application-specific integrated circuits (ASICs).

Energy Efficiency of Task Allocation for Embedded JPEG Systems

PubMed Central

2014-01-01

Embedded system works everywhere for repeatedly performing a few particular functionalities. Well-known products include consumer electronics, smart home applications, and telematics device, and so forth. Recently, developing methodology of embedded systems is applied to conduct the design of cloud embedded system resulting in the applications of embedded system being more diverse. However, the more energy consumes result from the more embedded system works. This study presents hyperrectangle technology (HT) to embedded system for obtaining energy saving. The HT adopts drift effect to construct embedded systems with more hardware circuits than software components or vice versa. It can fast construct embedded system with a set of hardware circuits and software components. Moreover, it has a great benefit to fast explore energy consumption for various embedded systems. The effects are presented by assessing a JPEG benchmarks. Experimental results demonstrate that the HT, respectively, achieves the energy saving by 29.84%, 2.07%, and 68.80% on average to GA, GHO, and Lin. PMID:24982983

Module generation for self-testing integrated systems

NASA Astrophysics Data System (ADS)

Vanriessen, Ronald Pieter

Hardware used for self test in VLSI (Very Large Scale Integrated) systems is reviewed, and an architecture to control the test hardware in an integrated system is presented. Because of the increase of test times, the use of self test techniques has become practically and economically viable for VLSI systems. Beside the reduction in test times and costs, self test also provides testing at operational speeds. Therefore, a suitable combination of scan path and macrospecific (self) tests is required to reduce test times and costs. An expert system that can be used in a silicon compilation environment is presented. The approach requires a minimum of testability knowledge from a system designer. A user friendly interface was described for specifying and modifying testability requirements by a testability expert. A reason directed backtracking mechanism is used to solve selection failures. Both the hierarchical testable architecture and the design for testability expert system are used in a self test compiler. The definition of a self test compiler was given. A self test compiler is a software tool that selects an appropriate test method for every macro in a design. The hardware to control a macro test will be included in the design automatically. As an example, the integration of the self-test compiler in a silicon compilation system PIRAMID was described. The design of a demonstrator circuit by self test compiler is described. This circuit consists of two self testable macros. Control of the self test hardware is carried out via the test access port of the boundary scan standard.

An introduction to the BANNING design automation system for shuttle microelectronic hardware development

NASA Technical Reports Server (NTRS)

Mcgrady, W. J.

1979-01-01

The BANNING MOS design system is presented. It complements rather than supplant the normal design activities associated with the design and fabrication of low-power digital electronic equipment. BANNING is user-oriented and requires no programming experience to use effectively. It provides the user a simulation capability to aid in his circuit design and it eliminates most of the manual operations involved in the layout and artwork generation of integrated circuits. An example of its operation is given and some additional background reading is provided.

Note: Circuit design for direct current and alternating current electrochemical etching of scanning probe microscopy tips.

PubMed

Jobbins, Matthew M; Raigoza, Annette F; Kandel, S Alex

2012-03-01

We present control circuits designed for electrochemically etching, reproducibly sharp STM probes. The design uses an Arduino UNO microcontroller to allow for both ac and dc operation, as well as a comparator driven shut-off that allows for etching to be stopped in 0.5-1 μs. The Arduino allows the instrument to be customized to suit a wide variety of potential applications without significant changes to hardware. Data is presented for coarse chemical etching of 80:20 platinum-iridium, tungsten, and nickel tips.

Inexpensive robots used to teach dc circuits and electronics

NASA Astrophysics Data System (ADS)

Sidebottom, David L.

2017-05-01

This article describes inexpensive, autonomous robots, built without microprocessors, used in a college-level introductory physics laboratory course to motivate student learning of dc circuits. Detailed circuit descriptions are provided as well as a week-by-week course plan that can guide students from elementary dc circuits, through Kirchhoff's laws, and into simple analog integrated circuits with the motivational incentive of building an autonomous robot that can compete with others in a public arena.

Dedicated hardware processor and corresponding system-on-chip design for real-time laser speckle imaging.

PubMed

Jiang, Chao; Zhang, Hongyan; Wang, Jia; Wang, Yaru; He, Heng; Liu, Rui; Zhou, Fangyuan; Deng, Jialiang; Li, Pengcheng; Luo, Qingming

2011-11-01

Laser speckle imaging (LSI) is a noninvasive and full-field optical imaging technique which produces two-dimensional blood flow maps of tissues from the raw laser speckle images captured by a CCD camera without scanning. We present a hardware-friendly algorithm for the real-time processing of laser speckle imaging. The algorithm is developed and optimized specifically for LSI processing in the field programmable gate array (FPGA). Based on this algorithm, we designed a dedicated hardware processor for real-time LSI in FPGA. The pipeline processing scheme and parallel computing architecture are introduced into the design of this LSI hardware processor. When the LSI hardware processor is implemented in the FPGA running at the maximum frequency of 130 MHz, up to 85 raw images with the resolution of 640×480 pixels can be processed per second. Meanwhile, we also present a system on chip (SOC) solution for LSI processing by integrating the CCD controller, memory controller, LSI hardware processor, and LCD display controller into a single FPGA chip. This SOC solution also can be used to produce an application specific integrated circuit for LSI processing.

Independent Orbiter Assessment (IOA): Analysis of the guidance, navigation, and control subsystem

NASA Technical Reports Server (NTRS)

Trahan, W. H.; Odonnell, R. A.; Pietz, K. C.; Hiott, J. M.

1986-01-01

The results of the Independent Orbiter Assessment (IOA) of the Failure Modes and Effects Analysis (FMEA) and Critical Items List (CIL) is presented. The IOA approach features a top-down analysis of the hardware to determine failure modes, criticality, and potential critical items. To preserve independence, this analysis was accomplished without reliance upon the results contained within the NASA FMEA/CIL documentation. The independent analysis results corresponding to the Orbiter Guidance, Navigation, and Control (GNC) Subsystem hardware are documented. The function of the GNC hardware is to respond to guidance, navigation, and control software commands to effect vehicle control and to provide sensor and controller data to GNC software. Some of the GNC hardware for which failure modes analysis was performed includes: hand controllers; Rudder Pedal Transducer Assembly (RPTA); Speed Brake Thrust Controller (SBTC); Inertial Measurement Unit (IMU); Star Tracker (ST); Crew Optical Alignment Site (COAS); Air Data Transducer Assembly (ADTA); Rate Gyro Assemblies; Accelerometer Assembly (AA); Aerosurface Servo Amplifier (ASA); and Ascent Thrust Vector Control (ATVC). The IOA analysis process utilized available GNC hardware drawings, workbooks, specifications, schematics, and systems briefs for defining hardware assemblies, components, and circuits. Each hardware item was evaluated and analyzed for possible failure modes and effects. Criticality was assigned based upon the severity of the effect for each failure mode.

VLSI 'smart' I/O module development

NASA Astrophysics Data System (ADS)

Kirk, Dan

The developmental history, design, and operation of the MIL-STD-1553A/B discrete and serial module (DSM) for the U.S. Navy AN/AYK-14(V) avionics computer are described and illustrated with diagrams. The ongoing preplanned product improvement for the AN/AYK-14(V) includes five dual-redundant MIL-STD-1553 channels based on DSMs. The DSM is a front-end processor for transferring data to and from a common memory, sharing memory with a host processor to provide improved 'smart' input/output performance. Each DSM comprises three hardware sections: three VLSI-6000 semicustomized CMOS arrays, memory units to support the arrays, and buffers and resynchronization circuits. The DSM hardware module design, VLSI-6000 design tools, controlware and test software, and checkout procedures (using a hardware simulator) are characterized in detail.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Shepard, Kenneth L.; Sturcken, Noah Andrew

Power controller includes an output terminal having an output voltage, at least one clock generator to generate a plurality of clock signals and a plurality of hardware phases. Each hardware phase is coupled to the at least one clock generator and the output terminal and includes a comparator. Each hardware phase is configured to receive a corresponding one of the plurality of clock signals and a reference voltage, combine the corresponding clock signal and the reference voltage to produce a reference input, generate a feedback voltage based on the output voltage, compare the reference input and the feedback voltage usingmore » the comparator and provide a comparator output to the output terminal, whereby the comparator output determines a duty cycle of the power controller. An integrated circuit including the power controller is also provided.« less

NASA Tech Briefs, June 1998. Volume 22, No. 6

NASA Technical Reports Server (NTRS)

1998-01-01

Topics include: special coverage on computer hardware and peripherals, electronic components and circuits, electronic systems, software, materials, mechanics, machinery/automation, manufacturing, physical sciences, information sciences, book and reports, and a special section of Photonics Tech Briefs. and a second special section of Motion Control Tech Briefs

Demonstration Advanced Avionics System (DAAS) functional description. [Cessna 402B aircraft

NASA Technical Reports Server (NTRS)

1980-01-01

A comprehensive set of general aviation avionics were defined for integration into an advanced hardware mechanization for demonstration in a Cessna 402B aircraft. Block diagrams are shown and system and computer architecture as well as significant hardware elements are described. The multifunction integrated data control center and electronic horizontal situation indicator are discussed. The functions that the DAAS will perform are examined. This function definition is the basis for the DAAS hardware and software design.

Advanced Space Suit PLSS 2.0 Cooling Loop Evaluation and PLSS 2.5 Recommendations

NASA Technical Reports Server (NTRS)

Steele, John; Quinn, Greg; Campbell, Colin; Makinen, Janice; Watts, Carly; Westheimer, David

2016-01-01

From 2012 to 2015 The NASA/JSC AdvSS (Advanced Space Suit) PLSS (Portable Life Support Subsystem) team, with support from UTC Aerospace Systems, performed the build-up, packaging and testing of PLSS 2.0. One aspect of that testing was the evaluation of the long-term health of the water cooling circuit and the interfacing components. Periodic and end-of-test water, residue and hardware analyses provided valuable information on the status of the water cooling circuit, and the approaches that would be necessary to enhance water cooling circuit health in the future. The evaluated data has been consolidated, interpreted and woven into an action plan for the maintenance of water cooling circuit health for the planned FY (fiscal year) 2016 through FY 2018 PLSS 2.5 testing. This paper provides an overview of the PLSS 2.0 water cooling circuit findings and the associated steps to be taken in that regard for the PLSS 2.5.

A programmable CCD driver circuit for multiphase CCD operation

NASA Technical Reports Server (NTRS)

Ewin, Audrey J.; Reed, Kenneth V.

1989-01-01

A programmable CCD (charge-coupled device) driver circuit was designed to drive CCDs in multiphased modes. The purpose of the drive electronics is to operate developmental CCD imaging arrays for NASA's tiltable moderate resolution imaging spectrometer (MODIS-T). Five objectives for the driver were considered during its design: (1) the circuit drives CCD electrode voltages between 0 V and +30 V to produce reasonable potential wells, (2) the driving sequence is started with one input signal, (3) the driving sequence is started with one input signal, (4) the circuit allows programming of frame sequences required by arrays of any size, (5) it produces interfacing signals for the CCD and the DTF (detector test facility). Simulation of the driver verified its function with the master clock running up to 10 MHz. This suggests a maximum rate of 400,000 pixels/s. Timing and packaging parameters were verified. The design uses 54 TTL (transistor-transistor logic) chips. Two versions of hardware were fabricated: wirewrap and printed circuit board. Both were verified functionally with a logic analyzer.

Advanced Space Suit PLSS 2.0 Cooling Loop Evaluation and PLSS 2.5 Recommendations

NASA Technical Reports Server (NTRS)

Steele, John; Quinn, Greg; Campbell, Colin; Makinen, Janice; Watts, Carly; Westheimer, Dave

2016-01-01

From 2012 to 2015 The NASA/JSC AdvSS (Advanced Space Suit) PLSS (Primary Life Support Subsystem) team, with support from UTC Aerospace Systems, performed the build-up, packaging and testing of PLSS 2.0. A key aspect of that testing was the evaluation of the long-term health of the water cooling circuit and the interfacing components. Intermittent and end-of-test water, residue and hardware analyses provided valuable information on the status of the water cooling circuit, and the approaches that would be necessary to enhance water cooling circuit health in the future. The evaluated data has been consolidated, interpreted and woven into an action plan for the maintenance of water cooling circuit health for the planned FY (fiscal year) 2016 through FY 2018 PLSS 2.5 testing. This paper provides an overview of the PLSS 2.0 water cooling circuit findings and the associated steps to be taken in that regard for the PLSS 2.5 testing.

Design and Hardware Implementation of a New Chaotic Secure Communication Technique

PubMed Central

Xiong, Li; Lu, Yan-Jun; Zhang, Yong-Fang; Zhang, Xin-Guo; Gupta, Parag

2016-01-01

In this paper, a scheme for chaotic modulation secure communication is proposed based on chaotic synchronization of an improved Lorenz system. For the first time, the intensity limit and stability of the transmitted signal, the characteristics of broadband and the requirements for accuracy of electronic components are presented by Multisim simulation. In addition, some improvements are made on the measurement method and the proposed experimental circuit in order to facilitate the experiments of chaotic synchronization, chaotic non-synchronization, experiment without signal and experiment with signal. To illustrate the effectiveness of the proposed scheme, some numerical simulations are presented. Then, the proposed chaotic secure communication circuit is implemented through analog electronic circuit, which is characterized by its high accuracy and good robustness. PMID:27548385

Design and Hardware Implementation of a New Chaotic Secure Communication Technique.

PubMed

Xiong, Li; Lu, Yan-Jun; Zhang, Yong-Fang; Zhang, Xin-Guo; Gupta, Parag

2016-01-01

In this paper, a scheme for chaotic modulation secure communication is proposed based on chaotic synchronization of an improved Lorenz system. For the first time, the intensity limit and stability of the transmitted signal, the characteristics of broadband and the requirements for accuracy of electronic components are presented by Multisim simulation. In addition, some improvements are made on the measurement method and the proposed experimental circuit in order to facilitate the experiments of chaotic synchronization, chaotic non-synchronization, experiment without signal and experiment with signal. To illustrate the effectiveness of the proposed scheme, some numerical simulations are presented. Then, the proposed chaotic secure communication circuit is implemented through analog electronic circuit, which is characterized by its high accuracy and good robustness.

An extensible circuit QED architecture for quantum computation

NASA Astrophysics Data System (ADS)

Dicarlo, Leo

Realizing a logical qubit robust to single errors in its constituent physical elements is an immediate challenge for quantum information processing platforms. A longer-term challenge will be achieving quantum fault tolerance, i.e., improving logical qubit resilience by increasing redundancy in the underlying quantum error correction code (QEC). In QuTech, we target these challenges in collaboration with industrial and academic partners. I will present the circuit QED quantum hardware, room-temperature control electronics, and software components of the complete architecture. I will show the extensibility of each component to the Surface-17 and -49 circuits needed to reach the objectives with surface-code QEC, and provide an overview of latest developments. Research funded by IARPA and Intel Corporation.

JEN-1 Reactor Control System; SISTEMA DE CONTROL DEL REACTOR JEN-1

DOE Office of Scientific and Technical Information (OSTI.GOV)

Cantillo, M.F.; Nuno, C.M.; Andreu, J.L.M.

1963-01-01

ABS>The JEN-1 3Mw power swimming pool reactor electrical control circuits are described. Start-up, power generation in the core, and shutdown are controlled by the reactor control system. This control system guarantees in each moment the safety conditions during reactor operation. Each circuit was represented by a scheme, complemented with a description of its function, components, and operation theory. Components described include: scram circuit; fission counter control circuit; servo control circuit; control circuit of safety sheets; control circuits of primary, secondary, and clean-up pump motors and tower fan motor; primary valve motor circuit; center cubicle alarm circuit; and process alarm circuit.more » (auth)« less

Implementation of a system to provide mobile satellite services in North America

NASA Technical Reports Server (NTRS)

Johanson, Gary A.; Davies, N. George; Tisdale, William R. H.

1993-01-01

This paper describes the implementation of the ground network to support Mobile Satellite Services (MSS). The system is designed to take advantage of a powerful new satellite series and provides significant improvements in capacity and throughput over systems in service today. The system is described in terms of the services provided and the system architecture being implemented to deliver those services. The system operation is described including examples of a circuit switched and packet switched call placement. The physical architecture is presented showing the major hardware components and software functionality placement within the hardware.

Photovoltaic array space power plus diagnostics experiment

NASA Technical Reports Server (NTRS)

Burger, D. R.

1990-01-01

The objective is to summarize the five years of hardware development and fabrication represented by the Photovoltaic Array Space Power Plus Diagnostics (PASP Plus) Instrument. The original PASP Experiment requirements and background is presented along with the modifications which were requested to transform the PASP Experiment into the PASP Plus Instrument. The PASP Plus hardware and software is described. Test results for components and subsystems are given as well as final system tests. Also included are appendices which describe the major subsystems and present supporting documentation such as block diagrams, schematics, circuit board artwork, drawings, test procedures and test reports.

The VLSI design of the sub-band filterbank in MP3 decoding

NASA Astrophysics Data System (ADS)

Liu, Jia-Xin; Luo, Li

2018-03-01

The sub-band filterbank is one of the most important modules which has the largest amount of calculation in MP3 decoding. In order to save CPU resources and integrate the sub-band filterbank part into MP3 IP core, the hardware circuit of the sub-band filterbank module is designed in this paper. A fast algorithm suit for hardware implementation is proposed and achieved on FPGA development board. The results show that the sub-band filterbank function is correct in the case of using very few registers and the amount of calculation and ROM resources are reduced greatly.

Application of M-JPEG compression hardware to dynamic stimulus production.

PubMed

Mulligan, J B

1997-01-01

Inexpensive circuit boards have appeared on the market which transform a normal micro-computer's disk drive into a video disk capable of playing extended video sequences in real time. This technology enables the performance of experiments which were previously impossible, or at least prohibitively expensive. The new technology achieves this capability using special-purpose hardware to compress and decompress individual video frames, enabling a video stream to be transferred over relatively low-bandwidth disk interfaces. This paper will describe the use of such devices for visual psychophysics and present the technical issues that must be considered when evaluating individual products.

The Extravehicular Mobility Unit (EMU): Proven hardware for Satellite Servicing

NASA Technical Reports Server (NTRS)

1982-01-01

A general technical description of the extravehicular mobility unit (EMU) is given. The description provides a basis for understanding EMU mobility capabilities and the environments a payload is exposed to in the vicinity of an EMU.

Design of an FPGA-based electronic flow regulator (EFR) for spacecraft propulsion system

NASA Astrophysics Data System (ADS)

Manikandan, J.; Jayaraman, M.; Jayachandran, M.

2011-02-01

This paper describes a scheme for electronically regulating the flow of propellant to the thruster from a high-pressure storage tank used in spacecraft application. Precise flow delivery of propellant to thrusters ensures propulsion system operation at best efficiency by maximizing the propellant and power utilization for the mission. The proposed field programmable gate array (FPGA) based electronic flow regulator (EFR) is used to ensure precise flow of propellant to the thrusters from a high-pressure storage tank used in spacecraft application. This paper presents hardware and software design of electronic flow regulator and implementation of the regulation logic onto an FPGA.Motivation for proposed FPGA-based electronic flow regulation is on the disadvantages of conventional approach of using analog circuits. Digital flow regulation overcomes the analog equivalent as digital circuits are highly flexible, are not much affected due to noise, accurate performance is repeatable, interface is easier to computers, storing facilities are possible and finally failure rate of digital circuits is less. FPGA has certain advantages over ASIC and microprocessor/micro-controller that motivated us to opt for FPGA-based electronic flow regulator. Also the control algorithm being software, it is well modifiable without changing the hardware. This scheme is simple enough to adopt for a wide range of applications, where the flow is to be regulated for efficient operation.The proposed scheme is based on a space-qualified re-configurable field programmable gate arrays (FPGA) and hybrid micro circuit (HMC). A graphical user interface (GUI) based application software is also developed for debugging, monitoring and controlling the electronic flow regulator from PC COM port.

Advances in integrated photonic circuits for packet-switched interconnection

NASA Astrophysics Data System (ADS)

Williams, Kevin A.; Stabile, Ripalta

2014-03-01

Sustained increases in capacity and connectivity are needed to overcome congestion in a range of broadband communication network nodes. Packet routing and switching in the electronic domain are leading to unsustainable energy- and bandwidth-densities, motivating research into hybrid solutions: optical switching engines are introduced for massive-bandwidth data transport while the electronic domain is clocked at more modest GHz rates to manage routing. Commercially-deployed optical switching engines using MEMS technologies are unwieldy and too slow to reconfigure for future packet-based networking. Optoelectronic packet-compliant switch technologies have been demonstrated as laboratory prototypes, but they have so far mostly used discretely pigtailed components, which are impractical for control plane development and product assembly. Integrated photonics has long held the promise of reduced hardware complexity and may be the critical step towards packet-compliant optical switching engines. Recently a number of laboratories world-wide have prototyped optical switching circuits using monolithic integration technology with up to several hundreds of integrated optical components per chip. Our own work has focused on multi-input to multi-output switching matrices. Recently we have demonstrated 8×8×8λ space and wavelength selective switches using gated cyclic routers and 16×16 broadband switching chips using monolithic multi-stage networks. We now operate these advanced circuits with custom control planes implemented with FPGAs to explore real time packet routing in multi-wavelength, multi-port test-beds. We review our contributions in the context of state of the art photonic integrated circuit technology and packet optical switching hardware demonstrations.

Establishing a Novel Modeling Tool: A Python-Based Interface for a Neuromorphic Hardware System

PubMed Central

Brüderle, Daniel; Müller, Eric; Davison, Andrew; Muller, Eilif; Schemmel, Johannes; Meier, Karlheinz

2008-01-01

Neuromorphic hardware systems provide new possibilities for the neuroscience modeling community. Due to the intrinsic parallelism of the micro-electronic emulation of neural computation, such models are highly scalable without a loss of speed. However, the communities of software simulator users and neuromorphic engineering in neuroscience are rather disjoint. We present a software concept that provides the possibility to establish such hardware devices as valuable modeling tools. It is based on the integration of the hardware interface into a simulator-independent language which allows for unified experiment descriptions that can be run on various simulation platforms without modification, implying experiment portability and a huge simplification of the quantitative comparison of hardware and simulator results. We introduce an accelerated neuromorphic hardware device and describe the implementation of the proposed concept for this system. An example setup and results acquired by utilizing both the hardware system and a software simulator are demonstrated. PMID:19562085

Establishing a novel modeling tool: a python-based interface for a neuromorphic hardware system.

PubMed

Brüderle, Daniel; Müller, Eric; Davison, Andrew; Muller, Eilif; Schemmel, Johannes; Meier, Karlheinz

2009-01-01

Neuromorphic hardware systems provide new possibilities for the neuroscience modeling community. Due to the intrinsic parallelism of the micro-electronic emulation of neural computation, such models are highly scalable without a loss of speed. However, the communities of software simulator users and neuromorphic engineering in neuroscience are rather disjoint. We present a software concept that provides the possibility to establish such hardware devices as valuable modeling tools. It is based on the integration of the hardware interface into a simulator-independent language which allows for unified experiment descriptions that can be run on various simulation platforms without modification, implying experiment portability and a huge simplification of the quantitative comparison of hardware and simulator results. We introduce an accelerated neuromorphic hardware device and describe the implementation of the proposed concept for this system. An example setup and results acquired by utilizing both the hardware system and a software simulator are demonstrated.

Using Cable Television for Library Data Transmission.

ERIC Educational Resources Information Center

Whitaker, Douglas A.

1985-01-01

Discusses information gained from a test of cable data circuits on a Geac bibliographic control system at the Wayne Oakland Library Federation (WOLF) (Michigan). Highlights include an introduction to cable, hardware profile, the WOLF experience, and key questions that will affect the future use of cable for data transmission. (EJS)

In-line task 57: Component evaluation. [of circuit breakers, panel switches, etc. for space shuttle

NASA Technical Reports Server (NTRS)

Boykin, J. C.

1974-01-01

Design analysis tests were performed on selected power switching components to determine the possible applicability of off-the-shelf hardware to space shuttles. Various characteristics were also evaluated in those devices to determine the most desirable properties for the space shuttle.

Dynamic partial reconfiguration of logic controllers implemented in FPGAs

NASA Astrophysics Data System (ADS)

Bazydło, Grzegorz; Wiśniewski, Remigiusz

2016-09-01

Technological progress in recent years benefits in digital circuits containing millions of logic gates with the capability for reprogramming and reconfiguring. On the one hand it provides the unprecedented computational power, but on the other hand the modelled systems are becoming increasingly complex, hierarchical and concurrent. Therefore, abstract modelling supported by the Computer Aided Design tools becomes a very important task. Even the higher consumption of the basic electronic components seems to be acceptable because chip manufacturing costs tend to fall over the time. The paper presents a modelling approach for logic controllers with the use of Unified Modelling Language (UML). Thanks to the Model Driven Development approach, starting with a UML state machine model, through the construction of an intermediate Hierarchical Concurrent Finite State Machine model, a collection of Verilog files is created. The system description generated in hardware description language can be synthesized and implemented in reconfigurable devices, such as FPGAs. Modular specification of the prototyped controller permits for further dynamic partial reconfiguration of the prototyped system. The idea bases on the exchanging of the functionality of the already implemented controller without stopping of the FPGA device. It means, that a part (for example a single module) of the logic controller is replaced by other version (called context), while the rest of the system is still running. The method is illustrated by a practical example by an exemplary Home Area Network system.

HSCT Sector Combustor Hardware Modifications for Improved Combustor Design

NASA Technical Reports Server (NTRS)

Greenfield, Stuart C.; Heberling, Paul V.; Moertle, George E.

2005-01-01

An alternative to the stepped-dome design for the lean premixed prevaporized (LPP) combustor has been developed. The new design uses the same premixer types as the stepped-dome design: integrated mixer flameholder (IMFH) tubes and a cyclone swirler pilot. The IMFH fuel system has been taken to a new level of development. Although the IMFH fuel system design developed in this Task is not intended to be engine-like hardware, it does have certain characteristics of engine hardware, including separate fuel circuits for each of the fuel stages. The four main stage fuel circuits are integrated into a single system which can be withdrawn from the combustor as a unit. Additionally, two new types of liner cooling have been designed. The resulting lean blowout data was found to correlate well with the Lefebvre parameter. As expected, CO and unburned hydrocarbons emissions were shown to have an approximately linear relationship, even though some scatter was present in the data, and the CO versus flame temperature data showed the typical cupped shape. Finally, the NOx emissions data was shown to agree well with a previously developed correlation based on emissions data from Configuration 3 tests performed at GEAE. The design variations of the cyclone swirler pilot that were investigated in this study did not significantly change the NOx emissions from the baseline design (GEAE Configuration 3) at supersonic cruise conditions.

Shuttle mission simulator baseline definition report, volume 1

NASA Technical Reports Server (NTRS)

Burke, J. F.; Small, D. E.

1973-01-01

A baseline definition of the space shuttle mission simulator is presented. The subjects discussed are: (1) physical arrangement of the complete simulator system in the appropriate facility, with a definition of the required facility modifications, (2) functional descriptions of all hardware units, including the operational features, data demands, and facility interfaces, (3) hardware features necessary to integrate the items into a baseline simulator system to include the rationale for selecting the chosen implementation, and (4) operating, maintenance, and configuration updating characteristics of the simulator hardware.

MSFC Skylab structures and mechanical systems mission evaluation

NASA Technical Reports Server (NTRS)

1974-01-01

A performance analysis for structural and mechanical major hardware systems and components is presented. Development background testing, modifications, and requirement adjustments are included. Functional narratives are provided for comparison purposes as are predicted design performance criterion. Each item is evaluated on an individual basis: that is, (1) history (requirements, design, manufacture, and test); (2) in-orbit performance (description and analysis); and (3) conclusions and recommendations regarding future space hardware application. Overall, the structural and mechanical performance of the Skylab hardware was outstanding.

Operation and Maintenance Manual, TECS 18.

DTIC Science & Technology

1978-11-01

width modulated variable output voltage and frequency using a three-phase transistor bridge circuit . Reduced power line electromagnetic interference...Description 3-1 Section II. Circuit Fundamentals 3-1 Section III. System Description 3-2 CHAPTER 4. Protection and Maintenance 4-1 Section I. Internal...Number I-la TECS 18 Electronic Module Location-Evaporator Side 1-3 1-lb TECS 18 Electronic Module Location-Condenser Side 1-4 1-2 Remote Control Panel 1-5

1.06 Micrometer Avalanche Photodiode Detector

DTIC Science & Technology

1977-04-01

for Gigabit Nd-YAG Laser Communication ............. 30 2.1.6 Influence of Modulator Extinction Ration on Communication Performance with Different...GAASFET Preamps ............ 157 4.2.1.1 Circuit Description for GAASFET Preamps #4 and #5 157 4.2.1.2 Performance Results for GAASFET Preamp #5...163 4.2.1.3 Performance Results for GAASFET Preamp #4 ...... 169 4.2.2 Results for Mark II GAASFET Preamp ............. 173 4.2.2.1 Circuit Description

Digital systems design language

NASA Technical Reports Server (NTRS)

Shiva, S. G.

1979-01-01

Digital Systems Design Language (DDL) is implemented on the SEL-32 Computer Systems. The detaileds of the language, the translator, and the simulator, and the smulator programs are given. Several example descriptions and a tutorial on hardware description languages are provided, to guide the user.

An Open-Source Hardware and Software System for Acquisition and Real-Time Processing of Electrophysiology during High Field MRI

PubMed Central

Purdon, Patrick L.; Millan, Hernan; Fuller, Peter L.; Bonmassar, Giorgio

2008-01-01

Simultaneous recording of electrophysiology and functional magnetic resonance imaging (fMRI) is a technique of growing importance in neuroscience. Rapidly evolving clinical and scientific requirements have created a need for hardware and software that can be customized for specific applications. Hardware may require customization to enable a variety of recording types (e.g., electroencephalogram, local field potentials, or multi-unit activity) while meeting the stringent and costly requirements of MRI safety and compatibility. Real-time signal processing tools are an enabling technology for studies of learning, attention, sleep, epilepsy, neurofeedback, and neuropharmacology, yet real-time signal processing tools are difficult to develop. We describe an open source system for simultaneous electrophysiology and fMRI featuring low-noise (< 0.6 uV p-p input noise), electromagnetic compatibility for MRI (tested up to 7 Tesla), and user-programmable real-time signal processing. The hardware distribution provides the complete specifications required to build an MRI-compatible electrophysiological data acquisition system, including circuit schematics, print circuit board (PCB) layouts, Gerber files for PCB fabrication and robotic assembly, a bill of materials with part numbers, data sheets, and vendor information, and test procedures. The software facilitates rapid implementation of real-time signal processing algorithms. This system has used in human EEG/fMRI studies at 3 and 7 Tesla examining the auditory system, visual system, sleep physiology, and anesthesia, as well as in intracranial electrophysiological studies of the non-human primate visual system during 3 Tesla fMRI, and in human hyperbaric physiology studies at depths of up to 300 feet below sea level. PMID:18761038

An open-source hardware and software system for acquisition and real-time processing of electrophysiology during high field MRI.

PubMed

Purdon, Patrick L; Millan, Hernan; Fuller, Peter L; Bonmassar, Giorgio

2008-11-15

Simultaneous recording of electrophysiology and functional magnetic resonance imaging (fMRI) is a technique of growing importance in neuroscience. Rapidly evolving clinical and scientific requirements have created a need for hardware and software that can be customized for specific applications. Hardware may require customization to enable a variety of recording types (e.g., electroencephalogram, local field potentials, or multi-unit activity) while meeting the stringent and costly requirements of MRI safety and compatibility. Real-time signal processing tools are an enabling technology for studies of learning, attention, sleep, epilepsy, neurofeedback, and neuropharmacology, yet real-time signal processing tools are difficult to develop. We describe an open-source system for simultaneous electrophysiology and fMRI featuring low-noise (<0.6microV p-p input noise), electromagnetic compatibility for MRI (tested up to 7T), and user-programmable real-time signal processing. The hardware distribution provides the complete specifications required to build an MRI-compatible electrophysiological data acquisition system, including circuit schematics, print circuit board (PCB) layouts, Gerber files for PCB fabrication and robotic assembly, a bill of materials with part numbers, data sheets, and vendor information, and test procedures. The software facilitates rapid implementation of real-time signal processing algorithms. This system has been used in human EEG/fMRI studies at 3 and 7T examining the auditory system, visual system, sleep physiology, and anesthesia, as well as in intracranial electrophysiological studies of the non-human primate visual system during 3T fMRI, and in human hyperbaric physiology studies at depths of up to 300 feet below sea level.

Applying a Genetic Algorithm to Reconfigurable Hardware

NASA Technical Reports Server (NTRS)

Wells, B. Earl; Weir, John; Trevino, Luis; Patrick, Clint; Steincamp, Jim

2004-01-01

This paper investigates the feasibility of applying genetic algorithms to solve optimization problems that are implemented entirely in reconfgurable hardware. The paper highlights the pe$ormance/design space trade-offs that must be understood to effectively implement a standard genetic algorithm within a modem Field Programmable Gate Array, FPGA, reconfgurable hardware environment and presents a case-study where this stochastic search technique is applied to standard test-case problems taken from the technical literature. In this research, the targeted FPGA-based platform and high-level design environment was the Starbridge Hypercomputing platform, which incorporates multiple Xilinx Virtex II FPGAs, and the Viva TM graphical hardware description language.

An analog neural hardware implementation using charge-injection multipliers and neutron-specific gain control.

PubMed

Massengill, L W; Mundie, D B

1992-01-01

A neural network IC based on a dynamic charge injection is described. The hardware design is space and power efficient, and achieves massive parallelism of analog inner products via charge-based multipliers and spatially distributed summing buses. Basic synaptic cells are constructed of exponential pulse-decay modulation (EPDM) dynamic injection multipliers operating sequentially on propagating signal vectors and locally stored analog weights. Individually adjustable gain controls on each neutron reduce the effects of limited weight dynamic range. A hardware simulator/trainer has been developed which incorporates the physical (nonideal) characteristics of actual circuit components into the training process, thus absorbing nonlinearities and parametric deviations into the macroscopic performance of the network. Results show that charge-based techniques may achieve a high degree of neural density and throughput using standard CMOS processes.

Electrically reconfigurable logic array

NASA Technical Reports Server (NTRS)

Agarwal, R. K.

1982-01-01

To compose the complicated systems using algorithmically specialized logic circuits or processors, one solution is to perform relational computations such as union, division and intersection directly on hardware. These relations can be pipelined efficiently on a network of processors having an array configuration. These processors can be designed and implemented with a few simple cells. In order to determine the state-of-the-art in Electrically Reconfigurable Logic Array (ERLA), a survey of the available programmable logic array (PLA) and the logic circuit elements used in such arrays was conducted. Based on this survey some recommendations are made for ERLA devices.

Sensor Authentication: Embedded Processor Code

DOE Office of Scientific and Technical Information (OSTI.GOV)

Svoboda, John

2012-09-25

Described is the c code running on the embedded Microchip 32bit PIC32MX575F256H located on the INL developed noise analysis circuit board. The code performs the following functions: Controls the noise analysis circuit board preamplifier voltage gains of 1, 10, 100, 000 Initializes the analog to digital conversion hardware, input channel selection, Fast Fourier Transform (FFT) function, USB communications interface, and internal memory allocations Initiates high resolution 4096 point 200 kHz data acquisition Computes complex 2048 point FFT and FFT magnitude. Services Host command set Transfers raw data to Host Transfers FFT result to host Communication error checking

Intelligent FPGA Data Acquisition Framework

NASA Astrophysics Data System (ADS)

Bai, Yunpeng; Gaisbauer, Dominic; Huber, Stefan; Konorov, Igor; Levit, Dmytro; Steffen, Dominik; Paul, Stephan

2017-06-01

In this paper, we present the field programmable gate arrays (FPGA)-based framework intelligent FPGA data acquisition (IFDAQ), which is used for the development of DAQ systems for detectors in high-energy physics. The framework supports Xilinx FPGA and provides a collection of IP cores written in very high speed integrated circuit hardware description language, which use the common interconnect interface. The IP core library offers functionality required for the development of the full DAQ chain. The library consists of Serializer/Deserializer (SERDES)-based time-to-digital conversion channels, an interface to a multichannel 80-MS/s 10-b analog-digital conversion, data transmission, and synchronization protocol between FPGAs, event builder, and slow control. The functionality is distributed among FPGA modules built in the AMC form factor: front end and data concentrator. This modular design also helps to scale and adapt the DAQ system to the needs of the particular experiment. The first application of the IFDAQ framework is the upgrade of the read-out electronics for the drift chambers and the electromagnetic calorimeters (ECALs) of the COMPASS experiment at CERN. The framework will be presented and discussed in the context of this paper.

Maglev Train Signal Processing Architecture Based on Nonlinear Discrete Tracking Differentiator.

PubMed

Wang, Zhiqiang; Li, Xiaolong; Xie, Yunde; Long, Zhiqiang

2018-05-24

In a maglev train levitation system, signal processing plays an important role for the reason that some sensor signals are prone to be corrupted by noise due to the harsh installation and operation environment of sensors and some signals cannot be acquired directly via sensors. Based on these concerns, an architecture based on a new type of nonlinear second-order discrete tracking differentiator is proposed. The function of this signal processing architecture includes filtering signal noise and acquiring needed signals for levitation purposes. The proposed tracking differentiator possesses the advantages of quick convergence, no fluttering, and simple calculation. Tracking differentiator's frequency characteristics at different parameter values are studied in this paper. The performance of this new type of tracking differentiator is tested in a MATLAB simulation and this tracking-differentiator is implemented in Very-High-Speed Integrated Circuit Hardware Description Language (VHDL). In the end, experiments are conducted separately on a test board and a maglev train model. Simulation and experiment results show that the performance of this novel signal processing architecture can fulfill the real system requirement.

A CMOS ASIC Design for SiPM Arrays

PubMed Central

Dey, Samrat; Banks, Lushon; Chen, Shaw-Pin; Xu, Wenbin; Lewellen, Thomas K.; Miyaoka, Robert S.; Rudell, Jacques C.

2012-01-01

Our lab has previously reported on novel board-level readout electronics for an 8×8 silicon photomultiplier (SiPM) array featuring row/column summation technique to reduce the hardware requirements for signal processing. We are taking the next step by implementing a monolithic CMOS chip which is based on the row-column architecture. In addition, this paper explores the option of using diagonal summation as well as calibration to compensate for temperature and process variations. Further description of a timing pickoff signal which aligns all of the positioning (spatial channels) pulses in the array is described. The ASIC design is targeted to be scalable with the detector size and flexible to accommodate detectors from different vendors. This paper focuses on circuit implementation issues associated with the design of the ASIC to interface our Phase II MiCES FPGA board with a SiPM array. Moreover, a discussion is provided for strategies to eventually integrate all the analog and mixed-signal electronics with the SiPM, on either a single-silicon substrate or multi-chip module (MCM). PMID:24825923

The Langley 14- by 22-Foot Subsonic Tunnel: Description, Flow Characteristics, and Guide for Users

NASA Technical Reports Server (NTRS)

Gentry, Garl L., Jr.; Quinto, P. Frank; Gatlin, Gregory M.; Applin, Zachary T.

1990-01-01

The Langley 14- by 22-foot Subsonic Tunnel is a closed circuit, single-return atmospheric wind tunnel with a test section that can be operated in a variety of configurations (closed, slotted, partially open, and open). The closed test section configuration is 14.5 ft high by 21.75 ft wide and 50 ft long with a maximum speed of about 338 ft/sec. The open test section configuration has a maximum speed of about 270 ft/sec, and is formed by raising the ceiling and walls, to form a floor-only configuration. The tunnel may be configured with a moving-belt ground plane and a floor boundary-layer removal system at the entrance to the test section for ground effect testing. In addition, the tunnel had a two-component laser velocimeter, a frequency modulated (FM) tape system for dynamic data acquisition, flow visualization equipment, and acoustic testing capabilities. Users of the 14- by 22-foot Subsonic Tunnel are provided with information required for planning of experimental investigations including test hardware and model support systems.

Development of Electronics for Low-Temperature Space Missions

NASA Technical Reports Server (NTRS)

Patterson, Richard L.; Hammoud, Ahmad; Dickman, John E.; Gerber, Scott S.; Overton, Eric

2001-01-01

Electronic systems that are capable of operating at cryogenic temperatures will be needed for many future NASA space missions, including deep space probes and spacecraft for planetary surface exploration. In addition to being able to survive the harsh deep space environment, low-temperature electronics would help improve circuit performance, increase system efficiency, and reduce payload development and launch costs. Terrestrial applications where components and systems must operate in low-temperature environments include cryogenic instrumentation, superconducting magnetic energy storage, magnetic levitation transportation systems, and arctic exploration. An ongoing research and development project for the design, fabrication, and characterization of low-temperature electronics and supporting technologies at NASA Glenn Research Center focuses on efficient power systems capable of surviving in and exploiting the advantages of low-temperature environments. Supporting technologies include dielectric and insulating materials, semiconductor devices, passive power components, optoelectronic devices, and packaging and integration of the developed components into prototype flight hardware. An overview of the project is presented, including a description of the test facilities, a discussion of selected data from component testing, and a presentation of ongoing research activities being performed in collaboration with various organizations.

Active vibration control of a full scale aircraft wing using a reconfigurable controller

NASA Astrophysics Data System (ADS)

Prakash, Shashikala; Renjith Kumar, T. G.; Raja, S.; Dwarakanathan, D.; Subramani, H.; Karthikeyan, C.

2016-01-01

This work highlights the design of a Reconfigurable Active Vibration Control (AVC) System for aircraft structures using adaptive techniques. The AVC system with a multichannel capability is realized using Filtered-X Least Mean Square algorithm (FxLMS) on Xilinx Virtex-4 Field Programmable Gate Array (FPGA) platform in Very High Speed Integrated Circuits Hardware Description Language, (VHDL). The HDL design is made based on Finite State Machine (FSM) model with Floating point Intellectual Property (IP) cores for arithmetic operations. The use of FPGA facilitates to modify the system parameters even during runtime depending on the changes in user's requirements. The locations of the control actuators are optimized based on dynamic modal strain approach using genetic algorithm (GA). The developed system has been successfully deployed for the AVC testing of the full-scale wing of an all composite two seater transport aircraft. Several closed loop configurations like single channel and multi-channel control have been tested. The experimental results from the studies presented here are very encouraging. They demonstrate the usefulness of the system's reconfigurability for real time applications.

Arithmetic Circuit Verification Based on Symbolic Computer Algebra

NASA Astrophysics Data System (ADS)

Watanabe, Yuki; Homma, Naofumi; Aoki, Takafumi; Higuchi, Tatsuo

This paper presents a formal approach to verify arithmetic circuits using symbolic computer algebra. Our method describes arithmetic circuits directly with high-level mathematical objects based on weighted number systems and arithmetic formulae. Such circuit description can be effectively verified by polynomial reduction techniques using Gröbner Bases. In this paper, we describe how the symbolic computer algebra can be used to describe and verify arithmetic circuits. The advantageous effects of the proposed approach are demonstrated through experimental verification of some arithmetic circuits such as multiply-accumulator and FIR filter. The result shows that the proposed approach has a definite possibility of verifying practical arithmetic circuits.

ATLAS from Data Research Associates: A Fully Integrated Automation System.

ERIC Educational Resources Information Center

Mellinger, Michael J.

1987-01-01

This detailed description of a fully integrated, turnkey library system includes a complete profile of the system (functions, operational characteristics, hardware, operating system, minimum memory and pricing); history of the technologies involved; and descriptions of customer services and availability. (CLB)

Digital systems design language. Design synthesis of digital systems

NASA Technical Reports Server (NTRS)

Shiva, S. G.

1979-01-01

The Digital Systems Design Language (DDL) is implemented on the SEL-32 computer systems. The details of the language, translator and simulator programs are included. Several example descriptions and a tutorial on hardware description languages are provided, to guide the user.

Weather satellite picture receiving stations, APT digital scan converter

NASA Technical Reports Server (NTRS)

Vermillion, C. H.; Kamowski, J. C.

1975-01-01

The automatic picture transmission digital scan converter is used at ground stations to convert signals received from scanning radiometers to data compatible with ground equipment designed to receive signals from vidicons aboard operational meteorological satellites. Information necessary to understand the circuit theory, functional operation, general construction and calibration of the converter is provided. Brief and detailed descriptions of each of the individual circuits are included, accompanied by a schematic diagram contained at the end of each circuit description. Listings of integral parts and testing equipment required as well as an overall wiring diagram are included. This unit will enable the user to readily accept and process weather photographs from the operational meteorological satellites.

Neuromorphic Silicon Neuron Circuits

PubMed Central

Indiveri, Giacomo; Linares-Barranco, Bernabé; Hamilton, Tara Julia; van Schaik, André; Etienne-Cummings, Ralph; Delbruck, Tobi; Liu, Shih-Chii; Dudek, Piotr; Häfliger, Philipp; Renaud, Sylvie; Schemmel, Johannes; Cauwenberghs, Gert; Arthur, John; Hynna, Kai; Folowosele, Fopefolu; Saighi, Sylvain; Serrano-Gotarredona, Teresa; Wijekoon, Jayawan; Wang, Yingxue; Boahen, Kwabena

2011-01-01

Hardware implementations of spiking neurons can be extremely useful for a large variety of applications, ranging from high-speed modeling of large-scale neural systems to real-time behaving systems, to bidirectional brain–machine interfaces. The specific circuit solutions used to implement silicon neurons depend on the application requirements. In this paper we describe the most common building blocks and techniques used to implement these circuits, and present an overview of a wide range of neuromorphic silicon neurons, which implement different computational models, ranging from biophysically realistic and conductance-based Hodgkin–Huxley models to bi-dimensional generalized adaptive integrate and fire models. We compare the different design methodologies used for each silicon neuron design described, and demonstrate their features with experimental results, measured from a wide range of fabricated VLSI chips. PMID:21747754

Educational-research laboratory "electric circuits" on the base of digital technologies

NASA Astrophysics Data System (ADS)

Koroteyev, V. I.; Florentsev, V. V.; Florentseva, N. I.

2017-01-01

The problem of research activity of trainees' activation in the educational-research laboratory "Electric Circuits" using innovative methodological solutions and digital technologies is considered. The main task is in creation of the unified experimental research information-educational environment "Electrical Engineering". The problems arising during the developing and application of the modern software and hardware, experimental and research stands and digital control and measuring systems are presented. This paper presents the main stages of development and creation of educational-research laboratory "Electrical Circuits" at the Department of Electrical Engineering of NRNU MEPhI. The authors also consider the analogues of the described research complex offered by various educational institutions and companies. The analysis of their strengths and weaknesses, on which the advantages of the proposed solution are based, is held.

The constant current loop - A new paradigm for resistance signal conditioning

NASA Astrophysics Data System (ADS)

Anderson, Karl F.

A practical single constant current loop circuit for the signal conditioning of variable-resistance transducers has been synthesized, analyzed, and demonstrated. The strain gage and the resistance temperature device are examples of variable-resistance sensors. Lead wires connect variable-resistance sensors to remotely located signal-conditioning hardware. The presence of lead wires in the conventional Wheatstone bridge signal-conditioning circuit introduces undesired effects that reduce the quality of the data from the remote sensors. A practical approach is presented for suppressing essentially all lead wire resistance effects while indicating only the change in resistance value. An adaptation of the current loop circuit is presented that simultaneously provides an output signal voltage directly proportional to transducer resistance change and provides temperature information that is unaffected by transducer and lead wire resistance variations.

A verified design of a fault-tolerant clock synchronization circuit: Preliminary investigations

NASA Technical Reports Server (NTRS)

Miner, Paul S.

1992-01-01

Schneider demonstrates that many fault tolerant clock synchronization algorithms can be represented as refinements of a single proven correct paradigm. Shankar provides mechanical proof that Schneider's schema achieves Byzantine fault tolerant clock synchronization provided that 11 constraints are satisfied. Some of the constraints are assumptions about physical properties of the system and cannot be established formally. Proofs are given that the fault tolerant midpoint convergence function satisfies three of the constraints. A hardware design is presented, implementing the fault tolerant midpoint function, which is shown to satisfy the remaining constraints. The synchronization circuit will recover completely from transient faults provided the maximum fault assumption is not violated. The initialization protocol for the circuit also provides a recovery mechanism from total system failure caused by correlated transient faults.

The constant current loop - A new paradigm for resistance signal conditioning

NASA Technical Reports Server (NTRS)

Anderson, Karl F.

1993-01-01

A practical single constant current loop circuit for the signal conditioning of variable-resistance transducers has been synthesized, analyzed, and demonstrated. The strain gage and the resistance temperature device are examples of variable-resistance sensors. Lead wires connect variable-resistance sensors to remotely located signal-conditioning hardware. The presence of lead wires in the conventional Wheatstone bridge signal-conditioning circuit introduces undesired effects that reduce the quality of the data from the remote sensors. A practical approach is presented for suppressing essentially all lead wire resistance effects while indicating only the change in resistance value. An adaptation of the current loop circuit is presented that simultaneously provides an output signal voltage directly proportional to transducer resistance change and provides temperature information that is unaffected by transducer and lead wire resistance variations.

A generalized analog implementation of piecewise linear neuron models using CCII building blocks.

PubMed

Soleimani, Hamid; Ahmadi, Arash; Bavandpour, Mohammad; Sharifipoor, Ozra

2014-03-01

This paper presents a set of reconfigurable analog implementations of piecewise linear spiking neuron models using second generation current conveyor (CCII) building blocks. With the same topology and circuit elements, without W/L modification which is impossible after circuit fabrication, these circuits can produce different behaviors, similar to the biological neurons, both for a single neuron as well as a network of neurons just by tuning reference current and voltage sources. The models are investigated, in terms of analog implementation feasibility and costs, targeting large scale hardware implementations. Results show that, in order to gain the best performance, area and accuracy; these models can be compromised. Simulation results are presented for different neuron behaviors with CMOS 350 nm technology. Copyright © 2013 Elsevier Ltd. All rights reserved.

Engineering support activities for the Apollo 17 Surface Electrical Properties Experiment.

NASA Technical Reports Server (NTRS)

Cubley, H. D.

1972-01-01

Description of the engineering support activities which were required to ensure fulfillment of objectives specified for the Apollo 17 SEP (Surface Electrical Properties) Experiment. Attention is given to procedural steps involving verification of hardware acceptability to the astronauts, computer simulation of the experiment hardware, field trials, receiver antenna pattern measurements, and the qualification test program.

Special Report on the Data Collection Programs for the Ground Based Nitrogen Washout Experiment. Volume 2 - Detailed Program Descriptions, Listings, Examples and Hardware Specifications

NASA Technical Reports Server (NTRS)

1982-01-01

Personal data input, decompression data, nitrogen washout, nitrogen data, and update computer programs are described. Input data and formats; program output, reports, and data; program flowcharts; program listings; sample runs with input and output pages; hardware operation; and engineering data are provided.

Cammp Team

NASA Technical Reports Server (NTRS)

Evertt, Shonn F.; Collins, Michael; Hahn, William

2008-01-01

The International Space Station (ISS) Configuration Analysis Modeling and Mass Properties (CAMMP) Team is presenting a demo of certain CAMMP capabilities at a Booz Allen Hamilton conference in San Antonio. The team will be showing pictures of low fidelity, simplified ISS models, but no dimensions or technical data. The presentation will include a brief description of the contract and task, description and picture of the Topology, description of Generic Ground Rules and Constraints (GGR&C), description of Stage Analysis with constraints applied, and wrap up with description of other tasks such as Special Studies, Cable Routing, etc. The models include conceptual Crew Exploration Vehicle (CEV) and Lunar Lander images and animations created for promotional purposes, which are based entirely on public domain conceptual images from public NASA web sites and publicly available magazine articles and are not based on any actual designs, measurements, or 3D models. Conceptual Mars rover and lander are completely conceptual and are not based on any NASA designs or data. The demonstration includes High Fidelity Computer Aided Design (CAD) models of ISS provided by the ISS 3D CAD Team which will be used in a visual display to demonstrate the capabilities of the Teamcenter Visualization software. The demonstration will include 3D views of the CAD models including random measurements that will be taken to demonstrate the measurement tool. A 3D PDF file will be demonstrated of the Blue Book fidelity assembly complete model with no vehicles attached. The 3D zoom and rotation will be displayed as well as random measurements from the measurement tool. The External Configuration Analysis and Tracking Tool (ExCATT) Microsoft Access Database will be demonstrated to show its capabilities to organize and track hardware on ISS. The data included will be part numbers, serial numbers, historical, current, and future locations, of external hardware components on station. It includes dates of all external ISS events and flights and the associated hardware changes for each event. The hardware location information does not always reveal the exact location of the hardware, only the general location. In some cases the location is a module or carrier, in other cases it is a WIF socket, handrail, or attach point. Only small portions of the data will be displayed for demonstration purposes.

Design, testing, and delivery of an interactive graphics display subsystem

NASA Technical Reports Server (NTRS)

Holmes, B.

1973-01-01

An interactive graphics display system was designed to be used in locating components on a printed circuit card and outputting data concerning their thermal values. The manner in which this was accomplished in terms of both hardware and software is described. An analysis of the accuracy of this approach is also included.

Forgotten Hardware: How to Urinate in a Spacesuit

ERIC Educational Resources Information Center

Hollins, Hunter

2013-01-01

On May 5, 1961, astronaut Alan Shepard became the first American to fly in space. Although National Aeronautics and Space Administration (NASA) had discounted the need for him to urinate, Shepard did, in his spacesuit, short circuiting his electronic biosensors. With the development of the pressure suit needed for high-altitude and space flight…

Design and performance test of NIRS-based spinal cord lesion detector

NASA Astrophysics Data System (ADS)

Li, Nanxi; Li, Ting

2018-02-01

Spinal cord lesions can cause a series of severe complications, which can even lead to paralysis with high mortality. However, the traditional diagnosis of spinal cord lesion relies on complicated imaging modalities and other invasive and dangerous methods. Here, we have designed a small monitor based on NIRS technology for noninvasive monitoring for spinal cord lesions. The development of the instrument system includes the design of hardware circuits and the program of software. In terms of hardware, OPT1011 is selected as the light detector, and the appropriate probe distribution structure is selected according to the simulation result of Monte Carlo Simulation. At the same time, the powerful controller is selected as our system's central processing chip for the circuit design, and the data is transmitted by serial port to the host computer for post processing. Finally, we verify the stability and feasibility of the instrument system. It is found that the spinal signal could be obviously detected in the system, which indicates that our monitor based on NIRS technology has the potential to monitor the spinal lesion.

Hardware-efficient fermionic simulation with a cavity-QED system

NASA Astrophysics Data System (ADS)

Zhu, Guanyu; Subaşı, Yiǧit; Whitfield, James D.; Hafezi, Mohammad

2018-03-01

In digital quantum simulation of fermionic models with qubits, non-local maps for encoding are often encountered. Such maps require linear or logarithmic overhead in circuit depth which could render the simulation useless, for a given decoherence time. Here we show how one can use a cavity-QED system to perform digital quantum simulation of fermionic models. In particular, we show that highly nonlocal Jordan-Wigner or Bravyi-Kitaev transformations can be efficiently implemented through a hardware approach. The key idea is using ancilla cavity modes, which are dispersively coupled to a qubit string, to collectively manipulate and measure qubit states. Our scheme reduces the circuit depth in each Trotter step of the Jordan-Wigner encoding by a factor of N2, comparing to the scheme for a device with only local connectivity, where N is the number of orbitals for a generic two-body Hamiltonian. Additional analysis for the Fermi-Hubbard model on an N × N square lattice results in a similar reduction. We also discuss a detailed implementation of our scheme with superconducting qubits and cavities.

Design of single phase inverter using microcontroller assisted by data processing applications software

NASA Astrophysics Data System (ADS)

Ismail, K.; Muharam, A.; Amin; Widodo Budi, S.

2015-12-01

Inverter is widely used for industrial, office, and residential purposes. Inverter supports the development of alternative energy such as solar cells, wind turbines and fuel cells by converting dc voltage to ac voltage. Inverter has been made with a variety of hardware and software combinations, such as the use of pure analog circuit and various types of microcontroller as controller. When using pure analog circuit, modification would be difficult because it will change the entire hardware components. In inverter with microcontroller based design (with software), calculations to generate AC modulation is done in the microcontroller. This increases programming complexity and amount of coding downloaded to the microcontroller chip (capacity flash memory in the microcontroller is limited). This paper discusses the design of a single phase inverter using unipolar modulation of sine wave and triangular wave, which is done outside the microcontroller using data processing software application (Microsoft Excel), result shows that complexity programming was reduce and resolution sampling data is very influence to THD. Resolution sampling must taking ½ A degree to get best THD (15.8%).

Scalability, Timing, and System Design Issues for Intrinsic Evolvable Hardware

NASA Technical Reports Server (NTRS)

Hereford, James; Gwaltney, David

2004-01-01

In this paper we address several issues pertinent to intrinsic evolvable hardware (EHW). The first issue is scalability; namely, how the design space scales as the programming string for the programmable device gets longer. We develop a model for population size and the number of generations as a function of the programming string length, L, and show that the number of circuit evaluations is an O(L2) process. We compare our model to several successful intrinsic EHW experiments and discuss the many implications of our model. The second issue that we address is the timing of intrinsic EHW experiments. We show that the processing time is a small part of the overall time to derive or evolve a circuit and that major improvements in processor speed alone will have only a minimal impact on improving the scalability of intrinsic EHW. The third issue we consider is the system-level design of intrinsic EHW experiments. We review what other researchers have done to break the scalability barrier and contend that the type of reconfigurable platform and the evolutionary algorithm are tied together and impose limits on each other.

Improving Design Efficiency for Large-Scale Heterogeneous Circuits

NASA Astrophysics Data System (ADS)

Gregerson, Anthony

Despite increases in logic density, many Big Data applications must still be partitioned across multiple computing devices in order to meet their strict performance requirements. Among the most demanding of these applications is high-energy physics (HEP), which uses complex computing systems consisting of thousands of FPGAs and ASICs to process the sensor data created by experiments at particles accelerators such as the Large Hadron Collider (LHC). Designing such computing systems is challenging due to the scale of the systems, the exceptionally high-throughput and low-latency performance constraints that necessitate application-specific hardware implementations, the requirement that algorithms are efficiently partitioned across many devices, and the possible need to update the implemented algorithms during the lifetime of the system. In this work, we describe our research to develop flexible architectures for implementing such large-scale circuits on FPGAs. In particular, this work is motivated by (but not limited in scope to) high-energy physics algorithms for the Compact Muon Solenoid (CMS) experiment at the LHC. To make efficient use of logic resources in multi-FPGA systems, we introduce Multi-Personality Partitioning, a novel form of the graph partitioning problem, and present partitioning algorithms that can significantly improve resource utilization on heterogeneous devices while also reducing inter-chip connections. To reduce the high communication costs of Big Data applications, we also introduce Information-Aware Partitioning, a partitioning method that analyzes the data content of application-specific circuits, characterizes their entropy, and selects circuit partitions that enable efficient compression of data between chips. We employ our information-aware partitioning method to improve the performance of the hardware validation platform for evaluating new algorithms for the CMS experiment. Together, these research efforts help to improve the efficiency and decrease the cost of the developing large-scale, heterogeneous circuits needed to enable large-scale application in high-energy physics and other important areas.

Solid-State Lighting Module (SSLM)

NASA Technical Reports Server (NTRS)

2008-01-01

The project's goal was to build a light-emitting-diode (LED)-based light fixture that is identical in fit, form, and function to the existing International Space Station (ISS) General Luminaire Assembly (GLA) light fixture and fly it on the ISS in early FY 2008 as a Station Detailed Test Objective (SDTO). Our design offers the following strengths: proven component hardware: Our design uses components flown in other KSC-developed hardware; heat path thermal pad: LED array heat is transferred from the circuit board by silicon pad, negating the need for a cooling fan; variable colorimetry: The output light color can be changed by inserting different LED combinations.

Hardware proofs using EHDM and the RSRE verification methodology

NASA Technical Reports Server (NTRS)

Butler, Ricky W.; Sjogren, Jon A.

1988-01-01

Examined is a methodology for hardware verification developed by Royal Signals and Radar Establishment (RSRE) in the context of the SRI International's Enhanced Hierarchical Design Methodology (EHDM) specification/verification system. The methodology utilizes a four-level specification hierarchy with the following levels: functional level, finite automata model, block model, and circuit level. The properties of a level are proved as theorems in the level below it. This methodology is applied to a 6-bit counter problem and is critically examined. The specifications are written in EHDM's specification language, Extended Special, and the proofs are improving both the RSRE methodology and the EHDM system.

Elementary Keyboarding Software Product Reports.

ERIC Educational Resources Information Center

Northwest Regional Educational Lab., Portland, OR.

This report provides detailed product descriptions of 45 software programs designed to teach or improve the keyboarding skills of elementary school students that were identified by the MicroSIFT (Microcomputer Information and Software for Teachers) staff. The descriptions include program titles, producer names, costs, grade levels, hardware,…

Utilizing the Digital Fingerprint Methodology for Secure Key Generation

DTIC Science & Technology

2010-03-01

circuits. 2.2.2. Arbiter PUF 2.2.1 Arbiter PUF Description Figure 3 represents the arbiter PUF circuitry designed by Suh and Devadas [4]. The D latch...Reliability The results of Suh and Devadas ‟s experiments on the arbiter PUF circuit showed that when the arbiter circuit output was measured for the...and Devada pointed out that this low percentage was the result of not laying out their circuit symmetrically as it appears in the idealized

Modular and Reusable Power System Design for the BRRISON Balloon Telescope

NASA Astrophysics Data System (ADS)

Truesdale, Nicholas A.

High altitude balloons are emerging as low-cost alternatives to orbital satellites in the field of telescopic observation. The near-space environment of balloons allows optics to perform near their diffraction limit. In practice, this implies that a telescope similar to the Hubble Space Telescope could be flown for a cost of tens of millions as opposed to billions. While highly feasible, the design of a balloon telescope to rival Hubble is limited by funding. Until a prototype is proven and more support for balloon science is gained, projects remain limited in both hardware costs and man hours. Thus, to effectively create and support balloon payloads, engineering designs must be efficient, modular, and if possible reusable. This thesis focuses specifically on a modular power system design for the BRRISON comet-observing balloon telescope. Time- and cost-saving techniques are developed that can be used for future missions. A modular design process is achieved through the development of individual circuit elements that span a wide range of capabilities. Circuits for power conversion, switching and sensing are designed to be combined in any configuration. These include DC-DC regulators, MOSFET drivers for switching, isolated switches, current sensors and voltage sensing ADCs. Emphasis is also given to commercially available hardware. Pre-fabricated DC-DC converters and an Arduino microcontroller simplify the design process and offer proven, cost-effective performance. The design of the BRRISON power system is developed from these low-level circuits elements. A board for main power distribution supports the majority of flight electronics, and is extensible to additional hardware in future applications. An ATX computer power supply is developed, allowing the use of a commercial ATX motherboard as the flight computer. The addition of new capabilities is explored in the form of a heater control board. Finally, the power system as a whole is described, and its overall performance analyzed. The success of the BRRISON power system during testing and flight proves its utility, both for BRRISON and for future balloon telescopes.

Design of two-channel oscilloscope and basic circuit simulations in LabView

NASA Astrophysics Data System (ADS)

Balzhiev, Plamen; Makal, Jaroslaw

2008-01-01

The project is realized as a diploma thesis in Bialystok Technical University, Poland). The main aim is to develop a useful educational tool which presents the time and frequency characteristics in basic electrical circuits. It is designed as a helpful instrument for lectures and laboratory classes. The predominant audience will be students of electrical engineering from first semester of the higher education. Therefore the level of knowledge at this stage of education is not high enough and different techniques are necessary to increase the students' interest and the efficiency of teaching process. This educational instrument provides the needed knowledge concerning the basic circuits and its parameters. Graphics and animations of the general processes in the electrical circuits make the problems more interesting, comprehensive and easier to understand. For designing such an instrument the National Instruments' programming environment LabView is used. It is preferred to the other simulation software because of its simplicity flexibility and also availability (the free demo version is sufficient to make a simple virtual instrument). LabView uses graphical programming language and has powerful mathematical functions for analysis and simulations. The useful visualization tools for presenting different diagrams are worth recommending, too. It is also specialized in measurement and control and it supports a wide variety of hardware. Therefore this software is suitable for laboratory classes to present the dependencies between the simulated characteristics in basic electrical circuits and the real one measured with the hardware device. For this purpose a two-channel oscilloscope is designed as part of the described project. The main purpose of this instrument as part of the educational process is to present the desired characteristics of the electrical circuits and to become familiar with the general functions of the oscilloscope. This project combines several important features appropriate for teaching purposes: well presented information with graphics, easy to operate with and giving the necessary knowledge. This method of teaching is more interesting and attractive to the audience. Also the information is assimilated more quickly, with less effort.

On Polymorphic Circuits and Their Design Using Evolutionary Algorithms

NASA Technical Reports Server (NTRS)

Stoica, Adrian; Zebulum, Ricardo; Keymeulen, Didier; Lohn, Jason; Clancy, Daniel (Technical Monitor)

2002-01-01

This paper introduces the concept of polymorphic electronics (polytronics) - referring to electronics with superimposed built-in functionality. A function change does not require switches/reconfiguration as in traditional approaches. Instead the change comes from modifications in the characteristics of devices involved in the circuit, in response to controls such as temperature, power supply voltage (VDD), control signals, light, etc. The paper illustrates polytronic circuits in which the control is done by temperature, morphing signals, and VDD respectively. Polytronic circuits are obtained by evolutionary design/evolvable hardware techniques. These techniques are ideal for the polytronics design, a new area that lacks design guidelines, know-how,- yet the requirements/objectives are easy to specify and test. The circuits are evolved/synthesized in two different modes. The first mode explores an unstructured space, in which transistors can be interconnected freely in any arrangement (in simulations only). The second mode uses a Field Programmable Transistor Array (FPTA) model, and the circuit topology is sought as a mapping onto a programmable architecture (these experiments are performed both in simulations and on FPTA chips). The experiments demonstrated the synthesis. of polytronic circuits by evolution. The capacity of storing/hiding "extra" functions provides for watermark/invisible functionality, thus polytronics may find uses in intelligence/security applications.

Three Axis Acoustic Current Meter.

DTIC Science & Technology

1979-05-10

ofNaval Research co N~~~L4-75~C~~~~~~ ’~1i The report con a a brief description of the history of the contract work undertaken , together with reprints of...4V titanium allo y . All external hardware is also titani um, resulting in high stren gth and freedom from corrosion. (j The hardware is electricall y

A CCD experimental platform for large telescope in Antarctica based on FPGA

NASA Astrophysics Data System (ADS)

Zhu, Yuhua; Qi, Yongjun

2014-07-01

The CCD , as a detector , is one of the important components of astronomical telescopes. For a large telescope in Antarctica, a set of CCD detector system with large size, high sensitivity and low noise is indispensable. Because of the extremely low temperatures and unattended, system maintenance and software and hardware upgrade become hard problems. This paper introduces a general CCD controller experiment platform, using Field programmable gate array FPGA, which is, in fact, a large-scale field reconfigurable array. Taking the advantage of convenience to modify the system, construction of driving circuit, digital signal processing module, network communication interface, control algorithm validation, and remote reconfigurable module may realize. With the concept of integrated hardware and software, the paper discusses the key technology of building scientific CCD system suitable for the special work environment in Antarctica, focusing on the method of remote reconfiguration for controller via network and then offering a feasible hardware and software solution.

Performance evaluation of heart sound cancellation in FPGA hardware implementation for electronic stethoscope.

PubMed

Chao, Chun-Tang; Maneetien, Nopadon; Wang, Chi-Jo; Chiou, Juing-Shian

2014-01-01

This paper presents the design and evaluation of the hardware circuit for electronic stethoscopes with heart sound cancellation capabilities using field programmable gate arrays (FPGAs). The adaptive line enhancer (ALE) was adopted as the filtering methodology to reduce heart sound attributes from the breath sounds obtained via the electronic stethoscope pickup. FPGAs were utilized to implement the ALE functions in hardware to achieve near real-time breath sound processing. We believe that such an implementation is unprecedented and crucial toward a truly useful, standalone medical device in outpatient clinic settings. The implementation evaluation with one Altera cyclone II-EP2C70F89 shows that the proposed ALE used 45% resources of the chip. Experiments with the proposed prototype were made using DE2-70 emulation board with recorded body signals obtained from online medical archives. Clear suppressions were observed in our experiments from both the frequency domain and time domain perspectives.

Ka-Band Wide-Bandgap Solid-State Power Amplifier: Hardware Validation

NASA Technical Reports Server (NTRS)

Epp, L.; Khan, P.; Silva, A.

2005-01-01

Motivated by recent advances in wide-bandgap (WBG) gallium nitride (GaN) semiconductor technology, there is considerable interest in developing efficient solid-state power amplifiers (SSPAs) as an alternative to the traveling-wave tube amplifier (TWTA) for space applications. This article documents proof-of-concept hardware used to validate power-combining technologies that may enable a 120-W, 40 percent power-added efficiency (PAE) SSPA. Results in previous articles [1-3] indicate that architectures based on at least three power combiner designs are likely to enable the target SSPA. Previous architecture performance analyses and estimates indicate that the proposed architectures can power combine 16 to 32 individual monolithic microwave integrated circuits (MMICs) with >80 percent combining efficiency. This combining efficiency would correspond to MMIC requirements of 5- to 10-W output power and >48 percent PAE. In order to validate the performance estimates of the three proposed architectures, measurements of proof-of-concept hardware are reported here.

CIRCAL-2 - General-purpose on-line circuit design.

NASA Technical Reports Server (NTRS)

Dertouzos, M. L.; Jessel, G. P.; Stinger, J. R.

1972-01-01

CIRCAL-2 is a second-generation general-purpose on-line circuit-design program with the following main features: (1) multiple-analysis capability; (2) uniform and general data structures for handling text editing, network representations, and output results, regardless of analysis; (3) special techniques and structures for minimizing and controlling user-program interaction; (4) use of functionals for the description of hysteresis and heat effects; and (5) ability to define optimization procedures that 'replace' the user. The paper discusses the organization of CIRCAL-2, the aforementioned main features, and their consequences, such as a set of network elements and models general enough for most analyses and a set of functions tailored to circuit-design requirements. The presentation is descriptive, concentrating on conceptual rather than on program implementation details.

Neuropeptide Signaling Networks and Brain Circuit Plasticity.

PubMed

McClard, Cynthia K; Arenkiel, Benjamin R

2018-01-01

The brain is a remarkable network of circuits dedicated to sensory integration, perception, and response. The computational power of the brain is estimated to dwarf that of most modern supercomputers, but perhaps its most fascinating capability is to structurally refine itself in response to experience. In the language of computers, the brain is loaded with programs that encode when and how to alter its own hardware. This programmed "plasticity" is a critical mechanism by which the brain shapes behavior to adapt to changing environments. The expansive array of molecular commands that help execute this programming is beginning to emerge. Notably, several neuropeptide transmitters, previously best characterized for their roles in hypothalamic endocrine regulation, have increasingly been recognized for mediating activity-dependent refinement of local brain circuits. Here, we discuss recent discoveries that reveal how local signaling by corticotropin-releasing hormone reshapes mouse olfactory bulb circuits in response to activity and further explore how other local neuropeptide networks may function toward similar ends.

The 30/20 GHz mixed user architecture development study: Executive summary

NASA Technical Reports Server (NTRS)

1979-01-01

The baseline 30/30 GHz satellite communication system, designed for cost-effective communications in the years 1990 to 2000, incorporates on-board satellite demodulation and routing of individual 64 kbps digital voice-grade circuits. This level of routing flexibility is necessary to provide efficient communications to the large number of direct-to-user terminals (DTU) projected. The circuit interfacing hardware is distributed among all the DTU and master control stations. The switching circuitry which provides full interconnectivity between 30 to 45 thousand circuits is in the satellite. The DTU terminal cost, perhaps the largest element in the system cost, represents the largest economic value element of the system because it avoids using terrestrial signal distribution and routing and the charges associated with these functions. Satellite baseline design and power requirements for the system are examined.

A study of ignition and simulation circuits for arcjet thrusters, part 1. M.S. Thesis Final Report

NASA Technical Reports Server (NTRS)

Stuart, Thomas A.; King, Roger J.; Altenburger, Gene P.

1991-01-01

A 1 kW electronic load was programmed to simulate the nonlinear i-v (volt-ampere) characteristics of an arcjet, both ignited and unignited. The simulator was tested and found to closely resemble an arcjet both for large transients and small perturbances up to about 40 kHz. No attempt was made to simulate the ignition process itself. The dynamic behavior of the arcjet (and the simulator) was shown to differ significantly from that of a resistor bank. Previous research led to the design and construction of a 1 kW arcjet power supply. A high voltage ignition circuit was added to this hardware, and tests on a 1 kW arcjet were performed at NASA-Lewis. All tests were successful and no ignition failures were observed. Circuit documentation and test results are included.

Conic section function neural network circuitry for offline signature recognition.

PubMed

Erkmen, Burcu; Kahraman, Nihan; Vural, Revna A; Yildirim, Tulay

2010-04-01

In this brief, conic section function neural network (CSFNN) circuitry was designed for offline signature recognition. CSFNN is a unified framework for multilayer perceptron (MLP) and radial basis function (RBF) networks to make simultaneous use of advantages of both. The CSFNN circuitry architecture was developed using a mixed mode circuit implementation. The designed circuit system is problem independent. Hence, the general purpose neural network circuit system could be applied to various pattern recognition problems with different network sizes on condition with the maximum network size of 16-16-8. In this brief, CSFNN circuitry system has been applied to two different signature recognition problems. CSFNN circuitry was trained with chip-in-the-loop learning technique in order to compensate typical analog process variations. CSFNN hardware achieved highly comparable computational performances with CSFNN software for nonlinear signature recognition problems.

Design of a magnetic-tunnel-junction-oriented nonvolatile lookup table circuit with write-operation-minimized data shifting

NASA Astrophysics Data System (ADS)

Suzuki, Daisuke; Hanyu, Takahiro

2018-04-01

A magnetic-tunnel-junction (MTJ)-oriented nonvolatile lookup table (LUT) circuit, in which a low-power data-shift function is performed by minimizing the number of write operations in MTJ devices is proposed. The permutation of the configuration memory cell for read/write access is performed as opposed to conventional direct data shifting to minimize the number of write operations, which results in significant write energy savings in the data-shift function. Moreover, the hardware cost of the proposed LUT circuit is small since the selector is shared between read access and write access. In fact, the power consumption in the data-shift function and the transistor count are reduced by 82 and 52%, respectively, compared with those in a conventional static random-access memory-based implementation using a 90 nm CMOS technology.

Sensor Networks, Dataloggers, and Other Handy Gadgets Using Open-Source Electronics for the Christina River Basin CZO

NASA Astrophysics Data System (ADS)

Hicks, S. D.; Aufdenkampe, A. K.; Montgomery, D. S.

2011-12-01

The search for biogeochemical "hot spots" and "hot moments" that control ecosystem-level processes requires a rethinking of how we observe the environment. Extensive multi-sensor/measurement arrays are required to realize 2D, 3D, or 4D maps of environmental properties with sufficient spatial and temporal resolution to find and understand hot spots and hot moments. To date, the cost of the data logging and communication infrastructure has been a major limitation to large-scale sensor deployment, especially for near-real-time (NRT) wireless networks. A low-cost, user-friendly alternative is needed so that resources can be prioritized toward sensor hardware rather than data acquisition and communication hardware. A flexible development platform would also allow for easy creation of other useful devices in addition to the already apparent need for economical dataloggers. The recent proliferation of open-source electronics platforms offers an opportunity for environmental observatories to deploy sensors at large scales by reducing data logging and communications costs by more than an order of magnitude. Leading the open-source electronics revolution is the Arduino project, designed to make the process of using electronics in multidisciplinary projects more accessible to hobbyists and professionals alike. A large user community has developed and shared hundreds of practical applications for projects that interface with a variety of sensors and use embedded logic to control external hardware. Likewise, dozens of companies and individuals sell low-cost Arduino-compatible boards that can connect together in a modular framework, allowing the user to quickly create devices for a wide range of applications. Based on these open-source technologies and products, we are designing and building a variety of circuit devices for use in our research watersheds. One Arduino-based device is a multi-channel datalogger that can be used with a variety of analog and digital sensors, such as pressure transducers, conductivity sensors, soil moisture and temperature probes, and redox probes. Radio modules can be added to the loggers to create a self-meshing wireless network for streaming live sensor data. A variation of the logger circuit is a smaller handheld unit with a text display that can be used when testing sensors in the field. Another useful custom device is a remote streamwater sampling system, made up of an Arduino circuit and a prepaid cell phone, allowing a user to remotely control multiple pumps by following interactive voice menus and hearing live sensor value readouts. In the lab, an Arduino circuit is used in a multi-chamber CO2 respiration experiment where it is controlling dozens of solenoid valves and logging the data from the analytical instruments. One of the biggest benefits of open source hardware is the low cost of the components. Each of the devices we have built costs less than $100 and can be assembled in a few hours. These circuits could easily be adapted to other applications or interfaced with other sensors in a variety of configurations, making the Arduino platform an incredibly useful tool for researchers.

Standalone engine simulator (SAES), Engine Dynamics simulator (EDS) Xerox Sigma 5 interface hardware manual

NASA Technical Reports Server (NTRS)

Kirshten, P. M.; Black, S.; Pearson, R.

1979-01-01

The ESS-EDS and EDS-Sigma interfaces within the standalone engine simulator are described. The operation of these interfaces, including the definition and use of special function signals and data flow paths within them during data transfers, is presented along with detailed schematics and circuit layouts of the described equipment.

Florida specific NTCIP MIB development for actuated signal controller (ASC), closed-circuit television (CCTV), and center-to-center (C2C) communications with SunGuideSM software and ITS device test procedure development : summary of final report.

DOT National Transportation Integrated Search

2009-06-01

To provide hardware, software, network, systems research, and testing for multi-million dollar traffic : operations, Intelligent Transportation Systems (ITS), and statewide communications investments, the : Traffic Engineering and Operations Office h...

Florida specific NTCIP MIB development for actuated signal controller (ASC), closed-circuit television (CCTV), and center-to-center (C2C) communications with SunGuideSM software and ITS device test procedure development : executive summary.

DOT National Transportation Integrated Search

2009-06-01

To provide hardware, software, network, systems research, and testing for multi-million : dollar traffic operations, Intelligent Transportation Systems (ITS), and statewide : communications investments, the Traffic Engineering and Operations Office h...

Automatic chemical vapor deposition

NASA Technical Reports Server (NTRS)

Kennedy, B. W.

1981-01-01

Report reviews chemical vapor deposition (CVD) for processing integrated circuits and describes fully automatic machine for CVD. CVD proceeds at relatively low temperature, allows wide choice of film compositions (including graded or abruptly changing compositions), and deposits uniform films of controllable thickness at fairly high growth rate. Report gives overview of hardware, reactants, and temperature ranges used with CVD machine.

Electrolysis Performance Improvement and Validation Experiment

NASA Technical Reports Server (NTRS)

Schubert, Franz H.

1992-01-01

Viewgraphs on electrolysis performance improvement and validation experiment are presented. Topics covered include: water electrolysis: an ever increasing need/role for space missions; static feed electrolysis (SFE) technology: a concept developed for space applications; experiment objectives: why test in microgravity environment; and experiment description: approach, hardware description, test sequence and schedule.

Computer-Aided Authoring of Programmed Instruction for Teaching Symbol Recognition. Final Report.

ERIC Educational Resources Information Center

Braby, Richard; And Others

This description of AUTHOR, a computer program for the automated authoring of programmed texts designed to teach symbol recognition, includes discussions of the learning strategies incorporated in the design of the instructional materials, hardware description and the algorithm for the software, and current and future developments. Appendices…

Development of structural model of adaptive training complex in ergatic systems for professional use

NASA Astrophysics Data System (ADS)

Obukhov, A. D.; Dedov, D. L.; Arkhipov, A. E.

2018-03-01

The article considers the structural model of the adaptive training complex (ATC), which reflects the interrelations between the hardware, software and mathematical model of ATC and describes the processes in this subject area. The description of the main components of software and hardware complex, their interaction and functioning within the common system are given. Also the article scrutinizers a brief description of mathematical models of personnel activity, a technical system and influences, the interactions of which formalize the regularities of ATC functioning. The studies of main objects of training complexes and connections between them will make it possible to realize practical implementation of ATC in ergatic systems for professional use.

Description, characteristics and testing of the NASA airborne radar

NASA Technical Reports Server (NTRS)

Jones, W. R.; Altiz, O.; Schaffner, P.; Schrader, J. H.; Blume, H. J. C.

1991-01-01

Presented here is a description of a coherent radar scattermeter and its associated signal processing hardware, which have been specifically designed to detect microbursts and record their radar characteristics. Radar parameters, signal processing techniques and detection algorithms, all under computer control, combine to sense and process reflectivity, clutter, and microburst data. Also presented is the system's high density, high data rate recording system. This digital system is capable of recording many minutes of the in-phase and quadrature components and corresponding receiver gains of the scattered returns for selected spatial regions, as well as other aircraft and hardware related parameters of interest for post-flight analysis. Information is given in viewgraph form.

Construction and testing of a Scanning Laser Radar (SLR), phase 2

NASA Technical Reports Server (NTRS)

Flom, T.; Coombes, H. D.

1971-01-01

The scanning laser radar overall system is described. Block diagrams and photographs of the hardware are included with the system description. Detailed descriptions of all the subsystems that make up the scanning laser radar system are included. Block diagrams, photographs, and detailed optical and electronic schematics are used to help describe such subsystem hardware as the laser, beam steerer, receiver optics and detector, control and processing electronics, visual data displays, and the equipment used on the target. Tests were performed on the scanning laser radar to determine its acquisition and tracking performance and to determine its range and angle accuracies while tracking a moving target. The tests and test results are described.

Launch Deployment Assembly Extravehicular Activity Neutral Buoyancy Development Test Report

NASA Technical Reports Server (NTRS)

Loughead, T.

1996-01-01

This test evaluated the Launch Deployment Assembly (LDA) design for Extravehicular Activity (EVA) work sites (setup, igress, egress), reach and visual access, and translation required for cargo item removal. As part of the LDA design, this document describes the method and results of the LDA EVA Neutral Buoyancy Development Test to ensure that the LDA hardware support the deployment of the cargo items from the pallet. This document includes the test objectives, flight and mockup hardware description, descriptions of procedures and data collection used in the testing, and the results of the development test at the National Aeronautics and Space Administrations (NASA) Marshall Space Flight Center (MSFC) Neutral Buoyancy Simulator (NBS).

Integration of multi-interface conversion channel using FPGA for modular photonic network

NASA Astrophysics Data System (ADS)

Janicki, Tomasz; Pozniak, Krzysztof T.; Romaniuk, Ryszard S.

2010-09-01

The article discusses the integration of different types of interfaces with FPGA circuits using a reconfigurable communication platform. The solution has been implemented in practice in a single node of a distributed measurement system. Construction of communication platform has been presented with its selected hardware modules, described in VHDL and implemented in FPGA circuits. The graphical user interface (GUI) has been described that allows a user to control the operation of the system. In the final part of the article selected practical solutions have been introduced. The whole measurement system resides on multi-gigabit optical network. The optical network construction is highly modular, reconfigurable and scalable.

Multiplexing Superconducting Qubit Circuit for Single Microwave Photon Generation

NASA Astrophysics Data System (ADS)

George, R. E.; Senior, J.; Saira, O.-P.; Pekola, J. P.; de Graaf, S. E.; Lindström, T.; Pashkin, Yu A.

2017-10-01

We report on a device that integrates eight superconducting transmon qubits in λ /4 superconducting coplanar waveguide resonators fed from a common feedline. Using this multiplexing architecture, each resonator and qubit can be addressed individually, thus reducing the required hardware resources and allowing their individual characterisation by spectroscopic methods. The measured device parameters agree with the designed values, and the resonators and qubits exhibit excellent coherence properties and strong coupling, with the qubit relaxation rate dominated by the Purcell effect when brought in resonance with the resonator. Our analysis shows that the circuit is suitable for generation of single microwave photons on demand with an efficiency exceeding 80%.

Radiation-Tolerant Intelligent Memory Stack - RTIMS

NASA Technical Reports Server (NTRS)

Ng, Tak-kwong; Herath, Jeffrey A.

2011-01-01

This innovation provides reconfigurable circuitry and 2-Gb of error-corrected or 1-Gb of triple-redundant digital memory in a small package. RTIMS uses circuit stacking of heterogeneous components and radiation shielding technologies. A reprogrammable field-programmable gate array (FPGA), six synchronous dynamic random access memories, linear regulator, and the radiation mitigation circuits are stacked into a module of 42.7 42.7 13 mm. Triple module redundancy, current limiting, configuration scrubbing, and single- event function interrupt detection are employed to mitigate radiation effects. The novel self-scrubbing and single event functional interrupt (SEFI) detection allows a relatively soft FPGA to become radiation tolerant without external scrubbing and monitoring hardware

C to VHDL compiler

NASA Astrophysics Data System (ADS)

Berdychowski, Piotr P.; Zabolotny, Wojciech M.

2010-09-01

The main goal of C to VHDL compiler project is to make FPGA platform more accessible for scientists and software developers. FPGA platform offers unique ability to configure the hardware to implement virtually any dedicated architecture, and modern devices provide sufficient number of hardware resources to implement parallel execution platforms with complex processing units. All this makes the FPGA platform very attractive for those looking for efficient heterogeneous, computing environment. Current industry standard in development of digital systems on FPGA platform is based on HDLs. Although very effective and expressive in hands of hardware development specialists, these languages require specific knowledge and experience, unreachable for most scientists and software programmers. C to VHDL compiler project attempts to remedy that by creating an application, that derives initial VHDL description of a digital system (for further compilation and synthesis), from purely algorithmic description in C programming language. This idea itself is not new, and the C to VHDL compiler combines the best approaches from existing solutions developed over many previous years, with the introduction of some new unique improvements.

TERSSE: Definition of the Total Earth Resources System for the Shuttle Era. Volume 2: An Assessment of the Current State-of-the-Art

NASA Technical Reports Server (NTRS)

1974-01-01

Results of a state-of-the-art assessment of technology areas which affect the Earth Resources Program are presented along with a functional description of the basic earth resources system. Major areas discussed include: spacecraft flight hardware, remote sensors, data processing techniques and hardware, user models, user interfaces, and operations technology.

Florida-specific NTCIP management information base (MIB) for closed-circuit television (CCTV) camera : final draft.

DOT National Transportation Integrated Search

2009-01-01

Description: This following MIB has been developed for use by FDOT. This : proposed Florida-Specific NTCIP Management Information Base (MIB) For : Closed-Circuit Television (CCTV) Camera MIB is based on the following : documentations: : NTCIP 120...

Artwork Interactive Design System (AIDS) program description

NASA Technical Reports Server (NTRS)

Johnson, B. T.; Taylor, J. F.

1976-01-01

An artwork interactive design system is described which provides the microelectronic circuit designer/engineer a tool to perform circuit design, automatic layout modification, standard cell design, and artwork verification at a graphics computer terminal using a graphics tablet at the designer/computer interface.

Real-time demonstration hardware for enhanced DPCM video compression algorithm

NASA Technical Reports Server (NTRS)

Bizon, Thomas P.; Whyte, Wayne A., Jr.; Marcopoli, Vincent R.

1992-01-01

The lack of available wideband digital links as well as the complexity of implementation of bandwidth efficient digital video CODECs (encoder/decoder) has worked to keep the cost of digital television transmission too high to compete with analog methods. Terrestrial and satellite video service providers, however, are now recognizing the potential gains that digital video compression offers and are proposing to incorporate compression systems to increase the number of available program channels. NASA is similarly recognizing the benefits of and trend toward digital video compression techniques for transmission of high quality video from space and therefore, has developed a digital television bandwidth compression algorithm to process standard National Television Systems Committee (NTSC) composite color television signals. The algorithm is based on differential pulse code modulation (DPCM), but additionally utilizes a non-adaptive predictor, non-uniform quantizer and multilevel Huffman coder to reduce the data rate substantially below that achievable with straight DPCM. The non-adaptive predictor and multilevel Huffman coder combine to set this technique apart from other DPCM encoding algorithms. All processing is done on a intra-field basis to prevent motion degradation and minimize hardware complexity. Computer simulations have shown the algorithm will produce broadcast quality reconstructed video at an average transmission rate of 1.8 bits/pixel. Hardware implementation of the DPCM circuit, non-adaptive predictor and non-uniform quantizer has been completed, providing realtime demonstration of the image quality at full video rates. Video sampling/reconstruction circuits have also been constructed to accomplish the analog video processing necessary for the real-time demonstration. Performance results for the completed hardware compare favorably with simulation results. Hardware implementation of the multilevel Huffman encoder/decoder is currently under development along with implementation of a buffer control algorithm to accommodate the variable data rate output of the multilevel Huffman encoder. A video CODEC of this type could be used to compress NTSC color television signals where high quality reconstruction is desirable (e.g., Space Station video transmission, transmission direct-to-the-home via direct broadcast satellite systems or cable television distribution to system headends and direct-to-the-home).

Crew Quarters (CQ) and Electromagnetic Interference (EMI) Measurement Facility Combined Impedance Study

NASA Technical Reports Server (NTRS)

Scully, Robert C.

2011-01-01

This report documents an investigation into observed failures associated with conducted susceptibility testing of Crew Quarters (CQ) hardware in the Johnson Space Center (JSC) Electromagnetic Interference (EMI) Measurement Facility, and the work accomplished to identify the source of the observed behavior. Investigation led to the conclusion that the hardware power input impedance was interacting with the facility power impedance leading to instability at the observed frequencies of susceptibility. Testing performed in other facilities did not show this same behavior, pointing back to the EMI Measurement Facility power as the potential root cause. A LISN emulating the Station power bus impedance was inserted into the power circuit, and the susceptibility was eliminated from the measurements.

303 CD-ROMs To Use in Your Library: Descriptions, Evaluations, and Practical Advice.

ERIC Educational Resources Information Center

Dewey, Patrick R.

This book provides descriptions of approximately 270 CD-ROM packages and series, and references to dozens of others, all which are especially suitable for libraries. Organized by subject, entries include the vendor price (when available), platform and hardware requirements, and availability of network versions. In addition, evaluative comments…

The Induction of Chaos in Electronic Circuits Final Report-October 1, 2001

DOE Office of Scientific and Technical Information (OSTI.GOV)

R.M.Wheat, Jr.

2003-04-01

This project, now known by the name ''Chaos in Electronic Circuits,'' was originally tasked as a two-year project to examine various ''fault'' or ''non-normal'' operational states of common electronic circuits with some focus on determining the feasibility of exploiting these states. Efforts over the two-year duration of this project have been dominated by the study of the chaotic behavior of electronic circuits. These efforts have included setting up laboratory space and hardware for conducting laboratory tests and experiments, acquiring and developing computer simulation and analysis capabilities, conducting literature surveys, developing test circuitry and computer models to exercise and test ourmore » capabilities, and experimenting with and studying the use of RF injection as a means of inducing chaotic behavior in electronics. An extensive array of nonlinear time series analysis tools have been developed and integrated into a package named ''After Acquisition'' (AA), including capabilities such as Delayed Coordinate Embedding Mapping (DCEM), Time Resolved (3-D) Fourier Transform, and several other phase space re-creation methods. Many computer models have been developed for Spice and for the ATP (Alternative Transients Program), modeling the several working circuits that have been developed for use in the laboratory. And finally, methods of induction of chaos in electronic circuits have been explored.« less

[Hardware Implementation of Numerical Simulation Function of Hodgkin-Huxley Model Neurons Action Potential Based on Field Programmable Gate Array].

PubMed

Wang, Jinlong; Lu, Mai; Hu, Yanwen; Chen, Xiaoqiang; Pan, Qiangqiang

2015-12-01

Neuron is the basic unit of the biological neural system. The Hodgkin-Huxley (HH) model is one of the most realistic neuron models on the electrophysiological characteristic description of neuron. Hardware implementation of neuron could provide new research ideas to clinical treatment of spinal cord injury, bionics and artificial intelligence. Based on the HH model neuron and the DSP Builder technology, in the present study, a single HH model neuron hardware implementation was completed in Field Programmable Gate Array (FPGA). The neuron implemented in FPGA was stimulated by different types of current, the action potential response characteristics were analyzed, and the correlation coefficient between numerical simulation result and hardware implementation result were calculated. The results showed that neuronal action potential response of FPGA was highly consistent with numerical simulation result. This work lays the foundation for hardware implementation of neural network.

Optical Neural Interfaces

PubMed Central

Warden, Melissa R.; Cardin, Jessica A.; Deisseroth, Karl

2014-01-01

Genetically encoded optical actuators and indicators have changed the landscape of neuroscience, enabling targetable control and readout of specific components of intact neural circuits in behaving animals. Here, we review the development of optical neural interfaces, focusing on hardware designed for optical control of neural activity, integrated optical control and electrical readout, and optical readout of population and single-cell neural activity in freely moving mammals. PMID:25014785

Fault-Tolerant Computing: An Overview

DTIC Science & Technology

1991-06-01

Addison Wesley:, Reading, MA) 1984. [8] J. Wakerly , Error Detecting Codes, Self-Checking Circuits and Applications , (Elsevier North Holland, Inc.- New York... applicable to bit-sliced organi- zations of hardware. In the first time step, the normal computation is performed on the operands and the results...for error detection and fault tolerance in parallel processor systems while perform- ing specific computation-intensive applications [111. Contrary to

Modified timing module for Loran-C receiver

NASA Technical Reports Server (NTRS)

Lilley, R. W.

1983-01-01

Full hardware documentation is provided for the circuit card implementing the Loran-C timing loop, and the receiver event-mark and re-track functions. This documentation is to be combined with overall receiver drawings to form the as-built record for this device. Computer software to support this module is integrated with the remainder of the receiver software, in the LORPROM program.

CheapStat: an open-source, "do-it-yourself" potentiostat for analytical and educational applications.

PubMed

Rowe, Aaron A; Bonham, Andrew J; White, Ryan J; Zimmer, Michael P; Yadgar, Ramsin J; Hobza, Tony M; Honea, Jim W; Ben-Yaacov, Ilan; Plaxco, Kevin W

2011-01-01

Although potentiostats are the foundation of modern electrochemical research, they have seen relatively little application in resource poor settings, such as undergraduate laboratory courses and the developing world. One reason for the low penetration of potentiostats is their cost, as even the least expensive commercially available laboratory potentiostats sell for more than one thousand dollars. An inexpensive electrochemical workstation could thus prove useful in educational labs, and increase access to electrochemistry-based analytical techniques for food, drug and environmental monitoring. With these motivations in mind, we describe here the CheapStat, an inexpensive (<$80), open-source (software and hardware), hand-held potentiostat that can be constructed by anyone who is proficient at assembling circuits. This device supports a number of potential waveforms necessary to perform cyclic, square wave, linear sweep and anodic stripping voltammetry. As we demonstrate, it is suitable for a wide range of applications ranging from food- and drug-quality testing to environmental monitoring, rapid DNA detection, and educational exercises. The device's schematics, parts lists, circuit board layout files, sample experiments, and detailed assembly instructions are available in the supporting information and are released under an open hardware license.

The Impact of 3D Stacking and Technology Scaling on the Power and Area of Stereo Matching Processors.

PubMed

Ok, Seung-Ho; Lee, Yong-Hwan; Shim, Jae Hoon; Lim, Sung Kyu; Moon, Byungin

2017-02-22

Recently, stereo matching processors have been adopted in real-time embedded systems such as intelligent robots and autonomous vehicles, which require minimal hardware resources and low power consumption. Meanwhile, thanks to the through-silicon via (TSV), three-dimensional (3D) stacking technology has emerged as a practical solution to achieving the desired requirements of a high-performance circuit. In this paper, we present the benefits of 3D stacking and process technology scaling on stereo matching processors. We implemented 2-tier 3D-stacked stereo matching processors with GlobalFoundries 130-nm and Nangate 45-nm process design kits and compare them with their two-dimensional (2D) counterparts to identify comprehensive design benefits. In addition, we examine the findings from various analyses to identify the power benefits of 3D-stacked integrated circuit (IC) and device technology advancements. From experiments, we observe that the proposed 3D-stacked ICs, compared to their 2D IC counterparts, obtain 43% area, 13% power, and 14% wire length reductions. In addition, we present a logic partitioning method suitable for a pipeline-based hardware architecture that minimizes the use of TSVs.

The Impact of 3D Stacking and Technology Scaling on the Power and Area of Stereo Matching Processors

PubMed Central

Ok, Seung-Ho; Lee, Yong-Hwan; Shim, Jae Hoon; Lim, Sung Kyu; Moon, Byungin

2017-01-01

Recently, stereo matching processors have been adopted in real-time embedded systems such as intelligent robots and autonomous vehicles, which require minimal hardware resources and low power consumption. Meanwhile, thanks to the through-silicon via (TSV), three-dimensional (3D) stacking technology has emerged as a practical solution to achieving the desired requirements of a high-performance circuit. In this paper, we present the benefits of 3D stacking and process technology scaling on stereo matching processors. We implemented 2-tier 3D-stacked stereo matching processors with GlobalFoundries 130-nm and Nangate 45-nm process design kits and compare them with their two-dimensional (2D) counterparts to identify comprehensive design benefits. In addition, we examine the findings from various analyses to identify the power benefits of 3D-stacked integrated circuit (IC) and device technology advancements. From experiments, we observe that the proposed 3D-stacked ICs, compared to their 2D IC counterparts, obtain 43% area, 13% power, and 14% wire length reductions. In addition, we present a logic partitioning method suitable for a pipeline-based hardware architecture that minimizes the use of TSVs. PMID:28241437

CheapStat: An Open-Source, “Do-It-Yourself” Potentiostat for Analytical and Educational Applications

PubMed Central

Rowe, Aaron A.; Bonham, Andrew J.; White, Ryan J.; Zimmer, Michael P.; Yadgar, Ramsin J.; Hobza, Tony M.; Honea, Jim W.; Ben-Yaacov, Ilan; Plaxco, Kevin W.

2011-01-01

Although potentiostats are the foundation of modern electrochemical research, they have seen relatively little application in resource poor settings, such as undergraduate laboratory courses and the developing world. One reason for the low penetration of potentiostats is their cost, as even the least expensive commercially available laboratory potentiostats sell for more than one thousand dollars. An inexpensive electrochemical workstation could thus prove useful in educational labs, and increase access to electrochemistry-based analytical techniques for food, drug and environmental monitoring. With these motivations in mind, we describe here the CheapStat, an inexpensive (<$80), open-source (software and hardware), hand-held potentiostat that can be constructed by anyone who is proficient at assembling circuits. This device supports a number of potential waveforms necessary to perform cyclic, square wave, linear sweep and anodic stripping voltammetry. As we demonstrate, it is suitable for a wide range of applications ranging from food- and drug-quality testing to environmental monitoring, rapid DNA detection, and educational exercises. The device's schematics, parts lists, circuit board layout files, sample experiments, and detailed assembly instructions are available in the supporting information and are released under an open hardware license. PMID:21931613

Orbit Transfer Rocket Engine Technology Program. Task C.5. Enhanced Heat Transfer Combustor Technology

DTIC Science & Technology

1991-12-01

December, 1991 i--" NASA-Lewis Research Center Cleveland, Ohio 44135 94-08573 Contract No. NAS3-23773 .0l•!ill~• 111 l94 3 16 09V PISULATIXI NOTICI... 3 3.1 Test Hardware and Facility Description...V - Drawings and Layouts of Calorimeter Insert and Related Hardware .... 133 - Ui - FIGURES NUMBER PIALE GE 3 -1 Integrated Component Evaluator (I.C.E

High-fidelity real-time maritime scene rendering

NASA Astrophysics Data System (ADS)

Shyu, Hawjye; Taczak, Thomas M.; Cox, Kevin; Gover, Robert; Maraviglia, Carlos; Cahill, Colin

2011-06-01

The ability to simulate authentic engagements using real-world hardware is an increasingly important tool. For rendering maritime environments, scene generators must be capable of rendering radiometrically accurate scenes with correct temporal and spatial characteristics. When the simulation is used as input to real-world hardware or human observers, the scene generator must operate in real-time. This paper introduces a novel, real-time scene generation capability for rendering radiometrically accurate scenes of backgrounds and targets in maritime environments. The new model is an optimized and parallelized version of the US Navy CRUISE_Missiles rendering engine. It was designed to accept environmental descriptions and engagement geometry data from external sources, render a scene, transform the radiometric scene using the electro-optical response functions of a sensor under test, and output the resulting signal to real-world hardware. This paper reviews components of the scene rendering algorithm, and details the modifications required to run this code in real-time. A description of the simulation architecture and interfaces to external hardware and models is presented. Performance assessments of the frame rate and radiometric accuracy of the new code are summarized. This work was completed in FY10 under Office of Secretary of Defense (OSD) Central Test and Evaluation Investment Program (CTEIP) funding and will undergo a validation process in FY11.

Packaging printed circuit boards: A production application of interactive graphics

NASA Technical Reports Server (NTRS)

Perrill, W. A.

1975-01-01

The structure and use of an Interactive Graphics Packaging Program (IGPP), conceived to apply computer graphics to the design of packaging electronic circuits onto printed circuit boards (PCB), were described. The intent was to combine the data storage and manipulative power of the computer with the imaginative, intuitive power of a human designer. The hardware includes a CDC 6400 computer and two CDC 777 terminals with CRT screens, light pens, and keyboards. The program is written in FORTRAN 4 extended with the exception of a few functions coded in COMPASS (assembly language). The IGPP performs four major functions for the designer: (1) data input and display, (2) component placement (automatic or manual), (3) conductor path routing (automatic or manual), and (4) data output. The most complex PCB packaged to date measured 16.5 cm by 19 cm and contained 380 components, two layers of ground planes and four layers of conductors mixed with ground planes.

A visually guided collision warning system with a neuromorphic architecture.

PubMed

Okuno, Hirotsugu; Yagi, Tetsuya

2008-12-01

We have designed a visually guided collision warning system with a neuromorphic architecture, employing an algorithm inspired by the visual nervous system of locusts. The system was implemented with mixed analog-digital integrated circuits consisting of an analog resistive network and field-programmable gate array (FPGA) circuits. The resistive network processes the interaction between the laterally spreading excitatory and inhibitory signals instantaneously, which is essential for real-time computation of collision avoidance with a low power consumption and a compact hardware. The system responded selectively to approaching objects of simulated movie images at close range. The system was, however, confronted with serious noise problems due to the vibratory ego-motion, when it was installed in a mobile miniature car. To overcome this problem, we developed the algorithm, which is also installable in FPGA circuits, in order for the system to respond robustly during the ego-motion.

Modeling selective attention using a neuromorphic analog VLSI device.

PubMed

Indiveri, G

2000-12-01

Attentional mechanisms are required to overcome the problem of flooding a limited processing capacity system with information. They are present in biological sensory systems and can be a useful engineering tool for artificial visual systems. In this article we present a hardware model of a selective attention mechanism implemented on a very large-scale integration (VLSI) chip, using analog neuromorphic circuits. The chip exploits a spike-based representation to receive, process, and transmit signals. It can be used as a transceiver module for building multichip neuromorphic vision systems. We describe the circuits that carry out the main processing stages of the selective attention mechanism and provide experimental data for each circuit. We demonstrate the expected behavior of the model at the system level by stimulating the chip with both artificially generated control signals and signals obtained from a saliency map, computed from an image containing several salient features.

Stretchable electronics based on Ag-PDMS composites

PubMed Central

Larmagnac, Alexandre; Eggenberger, Samuel; Janossy, Hanna; Vörös, Janos

2014-01-01

Patterned structures of flexible, stretchable, electrically conductive materials on soft substrates could lead to novel electronic devices with unique mechanical properties allowing them to bend, fold, stretch or conform to their environment. For the last decade, research on improving the stretchability of circuits on elastomeric substrates has made significant progresses but designing printed circuit assemblies on elastomers remains challenging. Here we present a simple, cost-effective, cleanroom-free process to produce large scale soft electronic hardware where standard surface-mounted electrical components were directly bonded onto all-elastomeric printed circuit boards, or soft PCBs. Ag-PDMS tracks were stencil printed onto a PDMS substrate and soft PCBs were made by bonding the top and bottom layers together and filling punched holes with Ag-PDMS to create vias. Silver epoxy was used to bond commercial electrical components and no mechanical failure was observed after hundreds of stretching cycles. We also demonstrate the fabrication of a stretchable clock generator. PMID:25434843

The evolvability of programmable hardware.

PubMed

Raman, Karthik; Wagner, Andreas

2011-02-06

In biological systems, individual phenotypes are typically adopted by multiple genotypes. Examples include protein structure phenotypes, where each structure can be adopted by a myriad individual amino acid sequence genotypes. These genotypes form vast connected 'neutral networks' in genotype space. The size of such neutral networks endows biological systems not only with robustness to genetic change, but also with the ability to evolve a vast number of novel phenotypes that occur near any one neutral network. Whether technological systems can be designed to have similar properties is poorly understood. Here we ask this question for a class of programmable electronic circuits that compute digital logic functions. The functional flexibility of such circuits is important in many applications, including applications of evolutionary principles to circuit design. The functions they compute are at the heart of all digital computation. We explore a vast space of 10(45) logic circuits ('genotypes') and 10(19) logic functions ('phenotypes'). We demonstrate that circuits that compute the same logic function are connected in large neutral networks that span circuit space. Their robustness or fault-tolerance varies very widely. The vicinity of each neutral network contains circuits with a broad range of novel functions. Two circuits computing different functions can usually be converted into one another via few changes in their architecture. These observations show that properties important for the evolvability of biological systems exist in a commercially important class of electronic circuitry. They also point to generic ways to generate fault-tolerant, adaptable and evolvable electronic circuitry.

The evolvability of programmable hardware

PubMed Central

Raman, Karthik; Wagner, Andreas

2011-01-01

In biological systems, individual phenotypes are typically adopted by multiple genotypes. Examples include protein structure phenotypes, where each structure can be adopted by a myriad individual amino acid sequence genotypes. These genotypes form vast connected ‘neutral networks’ in genotype space. The size of such neutral networks endows biological systems not only with robustness to genetic change, but also with the ability to evolve a vast number of novel phenotypes that occur near any one neutral network. Whether technological systems can be designed to have similar properties is poorly understood. Here we ask this question for a class of programmable electronic circuits that compute digital logic functions. The functional flexibility of such circuits is important in many applications, including applications of evolutionary principles to circuit design. The functions they compute are at the heart of all digital computation. We explore a vast space of 1045 logic circuits (‘genotypes’) and 1019 logic functions (‘phenotypes’). We demonstrate that circuits that compute the same logic function are connected in large neutral networks that span circuit space. Their robustness or fault-tolerance varies very widely. The vicinity of each neutral network contains circuits with a broad range of novel functions. Two circuits computing different functions can usually be converted into one another via few changes in their architecture. These observations show that properties important for the evolvability of biological systems exist in a commercially important class of electronic circuitry. They also point to generic ways to generate fault-tolerant, adaptable and evolvable electronic circuitry. PMID:20534598

Summary of Closed Circuit Television Activities in Medical Education.

ERIC Educational Resources Information Center

London Univ. (England). Inst. of Education.

This 1967 summary of closed circuit television (CCTV) activities in medical education presents descriptive information on 35 different medical institutions in Great Britain. Specific data on CCTV are offered by institution, equipment, and uses under each medical field: anatomy, anaesthetics, geriatrics, medicine, obstretrics and gynaecology,…

Space station ECLSS simplified integrated test

NASA Technical Reports Server (NTRS)

Schunk, Richard G.; Bagdigian, Robert M.; Carrasquillo, Robyn L.; Ogle, Kathyrn Y.; Wieland, Paul O.

1989-01-01

A discussion of the Space Station Simplified Integrated Test (SIT) was conducted. The first in a series of three integrated Environmental Control and Life Support (ECLS) system tests, the primary objectives of the SIT were to verify proper operation of ECLS subsystems functioning in an integrated fashion as well as to gather preliminary performance data for the partial ECLS system used in the test. A description of the SIT configuration, a summary of events, a discussion of anomalies that occurred during the test, and detailed results and analysis from individual measurements and water and gas samples taken during the test are included. The preprototype ECLS hardware used in the test is reported providing an overall process description and theory of operation for each hardware item.

Demonstration Advanced Avionics System (DAAS) function description

NASA Technical Reports Server (NTRS)

Bailey, A. J.; Bailey, D. G.; Gaabo, R. J.; Lahn, T. G.; Larson, J. C.; Peterson, E. M.; Schuck, J. W.; Rodgers, D. L.; Wroblewski, K. A.

1982-01-01

The Demonstration Advanced Avionics System, DAAS, is an integrated avionics system utilizing microprocessor technologies, data busing, and shared displays for demonstrating the potential of these technologies in improving the safety and utility of general aviation operations in the late 1980's and beyond. Major hardware elements of the DAAS include a functionally distributed microcomputer complex, an integrated data control center, an electronic horizontal situation indicator, and a radio adaptor unit. All processing and display resources are interconnected by an IEEE-488 bus in order to enhance the overall system effectiveness, reliability, modularity and maintainability. A detail description of the DAAS architecture, the DAAS hardware, and the DAAS functions is presented. The system is designed for installation and flight test in a NASA Cessna 402-B aircraft.

Back-Propagation Operation for Analog Neural Network Hardware with Synapse Components Having Hysteresis Characteristics

PubMed Central

Ueda, Michihito; Nishitani, Yu; Kaneko, Yukihiro; Omote, Atsushi

2014-01-01

To realize an analog artificial neural network hardware, the circuit element for synapse function is important because the number of synapse elements is much larger than that of neuron elements. One of the candidates for this synapse element is a ferroelectric memristor. This device functions as a voltage controllable variable resistor, which can be applied to a synapse weight. However, its conductance shows hysteresis characteristics and dispersion to the input voltage. Therefore, the conductance values vary according to the history of the height and the width of the applied pulse voltage. Due to the difficulty of controlling the accurate conductance, it is not easy to apply the back-propagation learning algorithm to the neural network hardware having memristor synapses. To solve this problem, we proposed and simulated a learning operation procedure as follows. Employing a weight perturbation technique, we derived the error change. When the error reduced, the next pulse voltage was updated according to the back-propagation learning algorithm. If the error increased the amplitude of the next voltage pulse was set in such way as to cause similar memristor conductance but in the opposite voltage scanning direction. By this operation, we could eliminate the hysteresis and confirmed that the simulation of the learning operation converged. We also adopted conductance dispersion numerically in the simulation. We examined the probability that the error decreased to a designated value within a predetermined loop number. The ferroelectric has the characteristics that the magnitude of polarization does not become smaller when voltages having the same polarity are applied. These characteristics greatly improved the probability even if the learning rate was small, if the magnitude of the dispersion is adequate. Because the dispersion of analog circuit elements is inevitable, this learning operation procedure is useful for analog neural network hardware. PMID:25393715

PANDA: A distributed multiprocessor operating system

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chubb, P.

1989-01-01

PANDA is a design for a distributed multiprocessor and an operating system. PANDA is designed to allow easy expansion of both hardware and software. As such, the PANDA kernel provides only message passing and memory and process management. The other features needed for the system (device drivers, secondary storage management, etc.) are provided as replaceable user tasks. The thesis presents PANDA's design and implementation, both hardware and software. PANDA uses multiple 68010 processors sharing memory on a VME bus, each such node potentially connected to others via a high speed network. The machine is completely homogeneous: there are no differencesmore » between processors that are detectable by programs running on the machine. A single two-processor node has been constructed. Each processor contains memory management circuits designed to allow processors to share page tables safely. PANDA presents a programmers' model similar to the hardware model: a job is divided into multiple tasks, each having its own address space. Within each task, multiple processes share code and data. Tasks can send messages to each other, and set up virtual circuits between themselves. Peripheral devices such as disc drives are represented within PANDA by tasks. PANDA divides secondary storage into volumes, each volume being accessed by a volume access task, or VAT. All knowledge about the way that data is stored on a disc is kept in its volume's VAT. The design is such that PANDA should provide a useful testbed for file systems and device drivers, as these can be installed without recompiling PANDA itself, and without rebooting the machine.« less

Design of Refractory Metal Heat Pipe Life Test Environment Chamber, Cooling System, and Radio Frequency Heating System

NASA Technical Reports Server (NTRS)

Martin, J. J.; Bragg-Sitton, S. M.; Reid, R. S.; Stewart, E. T.; Davis, J. D.

2011-01-01

A series of 16 Mo-44.5%Re alloy/sodium heat pipes will be experimentally tested to examine heat pipe aging. To support this evaluation, an environmental test chamber and a number of auxiliary subsystems are required. These subsystems include radio frequency (RF) power supplies/inductive coils, recirculation water coolant loops, and chamber gas conditioning. The heat pipes will be grouped, based on like power and gas mixture requirements, into three clusters of five units each, configured in a pentagonal arrangement. The highest powered heat pipe will be tested separately. Test chamber atmospheric purity is targeted at <0.3 ppb oxygen at an approximate operating pressure of 76 torr (.1.5 psia), maintained by active purification (oxygen level is comparable to a 10(exp -6) torr environment). Treated water will be used in two independent cooling circuits to remove .85 kW. One circuit will service the RF hardware while the other will maintain the heat pipe calorimetry. Initial procedures for the startup and operation of support systems have been identified. Each of these subsystems is outfitted with a variety of instrumentation, integrated with distributed real-time controllers and computers. A local area network provides communication between all devices. This data and control network continuously monitors the health of the test hardware, providing warning indicators followed by automatic shutdown should potentially damaging conditions develop. During hardware construction, a number of checkout tests.many making use of stainless steel prototype heat pipes that are already fabricated.will be required to verify operation.

Space-Based Reconfigurable Software Defined Radio Test Bed Aboard International Space Station

NASA Technical Reports Server (NTRS)

Reinhart, Richard C.; Lux, James P.

2014-01-01

The National Aeronautical and Space Administration (NASA) recently launched a new software defined radio research test bed to the International Space Station. The test bed, sponsored by the Space Communications and Navigation (SCaN) Office within NASA is referred to as the SCaN Testbed. The SCaN Testbed is a highly capable communications system, composed of three software defined radios, integrated into a flight system, and mounted to the truss of the International Space Station. Software defined radios offer the future promise of in-flight reconfigurability, autonomy, and eventually cognitive operation. The adoption of software defined radios offers space missions a new way to develop and operate space transceivers for communications and navigation. Reconfigurable or software defined radios with communications and navigation functions implemented in software or VHDL (Very High Speed Hardware Description Language) provide the capability to change the functionality of the radio during development or after launch. The ability to change the operating characteristics of a radio through software once deployed to space offers the flexibility to adapt to new science opportunities, recover from anomalies within the science payload or communication system, and potentially reduce development cost and risk by adapting generic space platforms to meet specific mission requirements. The software defined radios on the SCaN Testbed are each compliant to NASA's Space Telecommunications Radio System (STRS) Architecture. The STRS Architecture is an open, non-proprietary architecture that defines interfaces for the connections between radio components. It provides an operating environment to abstract the communication waveform application from the underlying platform specific hardware such as digital-to-analog converters, analog-to-digital converters, oscillators, RF attenuators, automatic gain control circuits, FPGAs, general-purpose processors, etc. and the interconnections among different radio components.

A self-resetting spiking phase-change neuron

NASA Astrophysics Data System (ADS)

Cobley, R. A.; Hayat, H.; Wright, C. D.

2018-05-01

Neuromorphic, or brain-inspired, computing applications of phase-change devices have to date concentrated primarily on the implementation of phase-change synapses. However, the so-called accumulation mode of operation inherent in phase-change materials and devices can also be used to mimic the integrative properties of a biological neuron. Here we demonstrate, using physical modelling of nanoscale devices and SPICE modelling of associated circuits, that a single phase-change memory cell integrated into a comparator type circuit can deliver a basic hardware mimic of an integrate-and-fire spiking neuron with self-resetting capabilities. Such phase-change neurons, in combination with phase-change synapses, can potentially open a new route for the realisation of all-phase-change neuromorphic computing.

Flexible implementation of front-end bioelectric signal amplifier using FPAA for telemedicine system.

PubMed

Chan, U Fai; Chan, Wai Wong; Pun, Sio Hang; Vai, Mang I; Mak, Peng Un

2007-01-01

Traditional/Current electronic circuits for Telemedicine have significant performance on certain bioelectric signal detection. However, it is rarely seen that can handle multiple signals without changing of hardware. This paper introduces a general front-end amplifier for various bioelectric signals based on Field Programmable Analogy Array (FPAA) Technology. Employing FPAA technology, the implemented amplifier can be adapted for various bioelectric signals without alternating the circuitry while its compact size (core parts < 2 cm2) provides an alternative solution for miniaturized Telemedicine system and Wearable Devices. The proposed design implementation has demonstrated, through successfully ECG and EMG signal extractions, a quick way to miniaturize analog biomedical circuit in a convenient and cost effective way.

A new 4D chaotic system with hidden attractor and its engineering applications: Analog circuit design and field programmable gate array implementation

NASA Astrophysics Data System (ADS)

Abdolmohammadi, Hamid Reza; Khalaf, Abdul Jalil M.; Panahi, Shirin; Rajagopal, Karthikeyan; Pham, Viet-Thanh; Jafari, Sajad

2018-06-01

Nowadays, designing chaotic systems with hidden attractor is one of the most interesting topics in nonlinear dynamics and chaos. In this paper, a new 4D chaotic system is proposed. This new chaotic system has no equilibria, and so it belongs to the category of systems with hidden attractors. Dynamical features of this system are investigated with the help of its state-space portraits, bifurcation diagram, Lyapunov exponents diagram, and basin of attraction. Also a hardware realisation of this system is proposed by using field programmable gate arrays (FPGA). In addition, an electronic circuit design for the chaotic system is introduced.

High Efficiency Single Output ZVS-ZCS Voltage Doubled Flyback Converter

NASA Astrophysics Data System (ADS)

Kaliyaperumal, Deepa; Saju, Hridya Merin; Kumar, M. Vijaya

2016-06-01

A switch operating at high switching frequency increases the switching losses of the converter resulting in lesser efficiency. Hence this paper proposes a new topology which has resonant switches [zero voltage switching (ZVS)] in the primary circuit to eliminate the above said disadvantages, and voltage doubler zero current switching (ZCS) circuit in the secondary to double the output voltage, and hence the output power, power density and efficiency. The design aspects of the proposed topology for a single output of 5 V at 50 kHz, its simulation and hardware results are discussed in detail. The analysis of the results obtained from a 2.5 W converter reveals the superiority of the proposed converter.

Automated processing of dynamic properties of intraventricular pressure by computer program and electronic circuit.

PubMed

Adler, D; Mahler, Y

1980-04-01

A procedure for automatic detection and digital processing of the maximum first derivative of the intraventricular pressure (dp/dtmax), time to dp/dtmax(t - dp/dt) and beat-to-beat intervals have been developed. The procedure integrates simple electronic circuits with a short program using a simple algorithm for the detection of the points of interest. The tasks of differentiating the pressure signal and detecting the onset of contraction were done by electronics, while the tasks of finding the values of dp/dtmax, t - dp/dt, beat-to-beat intervals and all computations needed were done by software. Software/hardware 'trade off' considerations and the accuracy and reliability of the system are discussed.

A self-resetting spiking phase-change neuron.

PubMed

Cobley, R A; Hayat, H; Wright, C D

2018-05-11

Neuromorphic, or brain-inspired, computing applications of phase-change devices have to date concentrated primarily on the implementation of phase-change synapses. However, the so-called accumulation mode of operation inherent in phase-change materials and devices can also be used to mimic the integrative properties of a biological neuron. Here we demonstrate, using physical modelling of nanoscale devices and SPICE modelling of associated circuits, that a single phase-change memory cell integrated into a comparator type circuit can deliver a basic hardware mimic of an integrate-and-fire spiking neuron with self-resetting capabilities. Such phase-change neurons, in combination with phase-change synapses, can potentially open a new route for the realisation of all-phase-change neuromorphic computing.

Circuit Riding: A Method for Providing Reference Services.

ERIC Educational Resources Information Center

Plunket, Linda; And Others

1983-01-01

Discussion of the design and implementation of the Circuit Rider Librarian Program, a shared services project for delivering reference services to eight hospitals in Maine, includes a cost analysis of services and description of user evaluation survey. Five references, composite results of the survey, and postgrant options proposal are appended.…

HDL Based FPGA Interface Library for Data Acquisition and Multipurpose Real Time Algorithms

NASA Astrophysics Data System (ADS)

Fernandes, Ana M.; Pereira, R. C.; Sousa, J.; Batista, A. J. N.; Combo, A.; Carvalho, B. B.; Correia, C. M. B. A.; Varandas, C. A. F.

2011-08-01

The inherent parallelism of the logic resources, the flexibility in its configuration and the performance at high processing frequencies makes the field programmable gate array (FPGA) the most suitable device to be used both for real time algorithm processing and data transfer in instrumentation modules. Moreover, the reconfigurability of these FPGA based modules enables exploiting different applications on the same module. When using a reconfigurable module for various applications, the availability of a common interface library for easier implementation of the algorithms on the FPGA leads to more efficient development. The FPGA configuration is usually specified in a hardware description language (HDL) or other higher level descriptive language. The critical paths, such as the management of internal hardware clocks that require deep knowledge of the module behavior shall be implemented in HDL to optimize the timing constraints. The common interface library should include these critical paths, freeing the application designer from hardware complexity and able to choose any of the available high-level abstraction languages for the algorithm implementation. With this purpose a modular Verilog code was developed for the Virtex 4 FPGA of the in-house Transient Recorder and Processor (TRP) hardware module, based on the Advanced Telecommunications Computing Architecture (ATCA), with eight channels sampling at up to 400 MSamples/s (MSPS). The TRP was designed to perform real time Pulse Height Analysis (PHA), Pulse Shape Discrimination (PSD) and Pile-Up Rejection (PUR) algorithms at a high count rate (few Mevent/s). A brief description of this modular code is presented and examples of its use as an interface with end user algorithms, including a PHA with PUR, are described.

AES Cardless Automatic Teller Machine (ATM) Biometric Security System Design Using FPGA Implementation

NASA Astrophysics Data System (ADS)

Ahmad, Nabihah; Rifen, A. Aminurdin M.; Helmy Abd Wahab, Mohd

2016-11-01

Automated Teller Machine (ATM) is an electronic banking outlet that allows bank customers to complete a banking transactions without the aid of any bank official or teller. Several problems are associated with the use of ATM card such card cloning, card damaging, card expiring, cast skimming, cost of issuance and maintenance and accessing customer account by third parties. The aim of this project is to give a freedom to the user by changing the card to biometric security system to access the bank account using Advanced Encryption Standard (AES) algorithm. The project is implemented using Field Programmable Gate Array (FPGA) DE2-115 board with Cyclone IV device, fingerprint scanner, and Multi-Touch Liquid Crystal Display (LCD) Second Edition (MTL2) using Very High Speed Integrated Circuit Hardware (VHSIC) Description Language (VHDL). This project used 128-bits AES for recommend the device with the throughput around 19.016Gbps and utilized around 520 slices. This design offers a secure banking transaction with a low rea and high performance and very suited for restricted space environments for small amounts of RAM or ROM where either encryption or decryption is performed.

NeuroFlow: A General Purpose Spiking Neural Network Simulation Platform using Customizable Processors.

PubMed

Cheung, Kit; Schultz, Simon R; Luk, Wayne

2015-01-01

NeuroFlow is a scalable spiking neural network simulation platform for off-the-shelf high performance computing systems using customizable hardware processors such as Field-Programmable Gate Arrays (FPGAs). Unlike multi-core processors and application-specific integrated circuits, the processor architecture of NeuroFlow can be redesigned and reconfigured to suit a particular simulation to deliver optimized performance, such as the degree of parallelism to employ. The compilation process supports using PyNN, a simulator-independent neural network description language, to configure the processor. NeuroFlow supports a number of commonly used current or conductance based neuronal models such as integrate-and-fire and Izhikevich models, and the spike-timing-dependent plasticity (STDP) rule for learning. A 6-FPGA system can simulate a network of up to ~600,000 neurons and can achieve a real-time performance of 400,000 neurons. Using one FPGA, NeuroFlow delivers a speedup of up to 33.6 times the speed of an 8-core processor, or 2.83 times the speed of GPU-based platforms. With high flexibility and throughput, NeuroFlow provides a viable environment for large-scale neural network simulation.

20-GFLOPS QR processor on a Xilinx Virtex-E FPGA

NASA Astrophysics Data System (ADS)

Walke, Richard L.; Smith, Robert W. M.; Lightbody, Gaye

2000-11-01

Adaptive beamforming can play an important role in sensor array systems in countering directional interference. In high-sample rate systems, such as radar and comms, the calculation of adaptive weights is a very computational task that requires highly parallel solutions. For systems where low power consumption and volume are important the only viable implementation is as an Application Specific Integrated Circuit (ASIC). However, the rapid advancement of Field Programmable Gate Array (FPGA) technology is enabling highly credible re-programmable solutions. In this paper we present the implementation of a scalable linear array processor for weight calculation using QR decomposition. We employ floating-point arithmetic with mantissa size optimized to the target application to minimize component size, and implement them as relationally placed macros (RPMs) on Xilinx Virtex FPGAs to achieve predictable dense layout and high-speed operation. We present results that show that 20GFLOPS of sustained computation on a single XCV3200E-8 Virtex-E FPGA is possible. We also describe the parameterized implementation of the floating-point operators and QR-processor, and the design methodology that enables us to rapidly generate complex FPGA implementations using the industry standard hardware description language VHDL.

Replication of Space-Shuttle Computers in FPGAs and ASICs

NASA Technical Reports Server (NTRS)

Ferguson, Roscoe C.

2008-01-01

A document discusses the replication of the functionality of the onboard space-shuttle general-purpose computers (GPCs) in field-programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs). The purpose of the replication effort is to enable utilization of proven space-shuttle flight software and software-development facilities to the extent possible during development of software for flight computers for a new generation of launch vehicles derived from the space shuttles. The replication involves specifying the instruction set of the central processing unit and the input/output processor (IOP) of the space-shuttle GPC in a hardware description language (HDL). The HDL is synthesized to form a "core" processor in an FPGA or, less preferably, in an ASIC. The core processor can be used to create a flight-control card to be inserted into a new avionics computer. The IOP of the GPC as implemented in the core processor could be designed to support data-bus protocols other than that of a multiplexer interface adapter (MIA) used in the space shuttle. Hence, a computer containing the core processor could be tailored to communicate via the space-shuttle GPC bus and/or one or more other buses.

NeuroFlow: A General Purpose Spiking Neural Network Simulation Platform using Customizable Processors

PubMed Central

Cheung, Kit; Schultz, Simon R.; Luk, Wayne

2016-01-01

NeuroFlow is a scalable spiking neural network simulation platform for off-the-shelf high performance computing systems using customizable hardware processors such as Field-Programmable Gate Arrays (FPGAs). Unlike multi-core processors and application-specific integrated circuits, the processor architecture of NeuroFlow can be redesigned and reconfigured to suit a particular simulation to deliver optimized performance, such as the degree of parallelism to employ. The compilation process supports using PyNN, a simulator-independent neural network description language, to configure the processor. NeuroFlow supports a number of commonly used current or conductance based neuronal models such as integrate-and-fire and Izhikevich models, and the spike-timing-dependent plasticity (STDP) rule for learning. A 6-FPGA system can simulate a network of up to ~600,000 neurons and can achieve a real-time performance of 400,000 neurons. Using one FPGA, NeuroFlow delivers a speedup of up to 33.6 times the speed of an 8-core processor, or 2.83 times the speed of GPU-based platforms. With high flexibility and throughput, NeuroFlow provides a viable environment for large-scale neural network simulation. PMID:26834542

Energy efficient engine low-pressure compressor component test hardware detailed design report

NASA Technical Reports Server (NTRS)

Michael, C. J.; Halle, J. E.

1981-01-01

The aerodynamic and mechanical design description of the low pressure compressor component of the Energy Efficient Engine were used. The component was designed to meet the requirements of the Flight Propulsion System while maintaining a low cost approach in providing a low pressure compressor design for the Integrated Core/Low Spool test required in the Energy Efficient Engine Program. The resulting low pressure compressor component design meets or exceeds all design goals with the exception of surge margin. In addition, the expense of hardware fabrication for the Integrated Core/Low Spool test has been minimized through the use of existing minor part hardware.

Adopting Industry Standards for Control Systems Within Advanced Life Support

NASA Technical Reports Server (NTRS)

Young, James Scott; Boulanger, Richard

2002-01-01

This paper gives a description of OPC (Object Linking and Embedding for Process Control) standards for process control and outlines the experiences at JSC with using these standards to interface with I/O hardware from three independent vendors. The I/O hardware was integrated with a commercially available SCADA/HMI software package to make up the control and monitoring system for the Environmental Systems Test Stand (ESTS). OPC standards were utilized for communicating with I/O hardware and the software was used for implementing monitoring, PC-based distributed control, and redundant data storage over an Ethernet physical layer using an embedded din-rail mounted PC.

Arrays of Miniature Microphones for Aeroacoustic Testing

NASA Technical Reports Server (NTRS)

Shams, Qamar A.; Humphreys, William M.; Sealey, Bradley S.; Bartram, Scott M.; Zuckewar, Allan J.; Comeaux, Toby; Adams, James K.

2007-01-01

A phased-array system comprised of custom-made and commercially available microelectromechanical system (MEMS) silicon microphones and custom ancillary hardware has been developed for use in aeroacoustic testing in hard-walled and acoustically treated wind tunnels. Recent advances in the areas of multi-channel signal processing and beam forming have driven the construction of phased arrays containing ever-greater numbers of microphones. Traditional obstacles to this trend have been posed by (1) the high costs of conventional condenser microphones, associated cabling, and support electronics and (2) the difficulty of mounting conventional microphones in the precise locations required for high-density arrays. The present development overcomes these obstacles. One of the hallmarks of the new system is a series of fabricated platforms on which multiple microphones can be mounted. These mounting platforms, consisting of flexible polyimide circuit-board material (see left side of figure), include all the necessary microphone power and signal interconnects. A single bus line connects all microphones to a common power supply, while the signal lines terminate in one or more data buses on the sides of the circuit board. To minimize cross talk between array channels, ground lines are interposed as shields between all the data bus signal lines. The MEMS microphones are electrically connected to the boards via solder pads that are built into the printed wiring. These flexible circuit boards share many characteristics with their traditional rigid counterparts, but can be manufactured much thinner, as small as 0.1 millimeter, and much lighter with boards weighing as much as 75 percent less than traditional rigid ones. For a typical hard-walled wind-tunnel installation, the flexible printed-circuit board is bonded to the tunnel wall and covered with a face sheet that contains precise cutouts for the microphones. Once the face sheet is mounted, a smooth surface is established over the entire array due to the flush mounting of all microphones (see right side of figure). The face sheet is made from a continuous glass-woven-fabric base impregnated with an epoxy resin binder. This material offers a combination of high mechanical strength and low dielectric loss, making it suitable for withstanding the harsh test section environment present in many wind tunnels, while at the same time protecting the underlying polyimide board. Customized signal-conditioning hardware consisting of line drivers and antialiasing filters are coupled with the array. The line drivers are constructed using low-supply-current, high-gain-bandwidth operational amplifiers designed to transmit the microphone signals several dozen feet from the array to external acquisition hardware. The anti-alias filters consist of individual Chebyshev low-pass filters (one for each microphone channel) housed on small printed-circuit boards mounted on one or more motherboards. The mother/daughter board design results in a modular system, which is easy to debug and service and which enables the filter characteristics to be changed by swapping daughter boards with ones containing different filter parameters. The filter outputs are passed to commercially- available acquisition hardware to digitize and store the conditioned microphone signals. Wind-tunnel testing of the new MEMS microphone polyimide mounting system shows that the array performance is comparable to that of traditional arrays, but with significantly less cost of construction.

Programmable data collection platform study

NASA Technical Reports Server (NTRS)

1976-01-01

The results of a feasibility study incorporating microprocessors in data collection platforms in described. An introduction to microcomputer hardware and software concepts is provided. The influence of microprocessor technology on the design of programmable data collection platform hardware is discussed. A standard modular PDCP design capable of meeting the design goals is proposed, and the process of developing PDCP programs is examined. A description of design and construction of the UT PDCP development system is given.

Guidelines for Applying Video Simulation Technology to Training Land Design

DTIC Science & Technology

1993-02-01

Training Land Design for Realism." The technical monitor was Dr. Victor Diersing, CEHSC-FN. This study was performed by the Environmental Resources...technology to their land management activities. 5 Objective The objective of this study was to provide a general overview of the use of video simulation...4). A market study of currently available hardware and software provided the basis for descriptions of hardware and software systems, and their

Hardware system of X-wave generator with simple driving pulses

NASA Astrophysics Data System (ADS)

Li, Xu; Li, Yaqin; Xiao, Feng; Ding, Mingyue; Yuchi, Ming

2013-03-01

The limited diffraction beams such as X-wave have the properties of larger depth of field. Thus, it has the potential to generate ultra-high frame rate ultrasound images. However, in practice, the real-time generation of X-wave ultrasonic field requires complex and high-cost system, especially the precise and specific voltage time distribution part for the excitation of each distinct array element. In order to simplify the hardware realization of X-wave, based on the previous works, X-wave excitation signals were decomposed and expressed as the superposition of a group of simple driving pulses, such as rectangular and triangular waves. The hardware system for the X-wave generator was also designed. The generator consists of a computer for communication with the circuit, universal serial bus (USB) based micro-controller unit (MCU) for data transmission, field programmable gate array (FPGA) based Direct Digital Synthesizer(DDS), 12-bit digital-to-analog (D/A) converter and a two stage amplifier.The hardware simulation results show that the designed system can generate the waveforms at different radius approximating the theoretical X-wave excitations with a maximum error of 0.49% triggered by the quantification of amplitude data.

Digitally balanced detection for optical tomography.

PubMed

Hafiz, Rehan; Ozanyan, Krikor B

2007-10-01

Analog balanced Photodetection has found extensive usage for sensing of a weak absorption signal buried in laser intensity noise. This paper proposes schemes for compact, affordable, and flexible digital implementation of the already established analog balanced detection, as part of a multichannel digital tomography system. Variants of digitally balanced detection (DBD) schemes, suitable for weak signals on a largely varying background or weakly varying envelopes of high frequency carrier waves, are introduced analytically and elaborated in terms of algorithmic and hardware flow. The DBD algorithms are implemented on a low-cost general purpose reconfigurable hardware (field-programmable gate array), utilizing less than half of its resources. The performance of the DBD schemes compare favorably with their analog counterpart: A common mode rejection ratio of 50 dB was observed over a bandwidth of 300 kHz, limited mainly by the host digital hardware. The close relationship between the DBD outputs and those of known analog balancing circuits is discussed in principle and shown experimentally in the example case of propane gas detection.

Performance Evaluation of Heart Sound Cancellation in FPGA Hardware Implementation for Electronic Stethoscope

PubMed Central

Chao, Chun-Tang

2014-01-01

This paper presents the design and evaluation of the hardware circuit for electronic stethoscopes with heart sound cancellation capabilities using field programmable gate arrays (FPGAs). The adaptive line enhancer (ALE) was adopted as the filtering methodology to reduce heart sound attributes from the breath sounds obtained via the electronic stethoscope pickup. FPGAs were utilized to implement the ALE functions in hardware to achieve near real-time breath sound processing. We believe that such an implementation is unprecedented and crucial toward a truly useful, standalone medical device in outpatient clinic settings. The implementation evaluation with one Altera cyclone II–EP2C70F89 shows that the proposed ALE used 45% resources of the chip. Experiments with the proposed prototype were made using DE2-70 emulation board with recorded body signals obtained from online medical archives. Clear suppressions were observed in our experiments from both the frequency domain and time domain perspectives. PMID:24790573

Test and evaluation of load converter topologies used in the Space Station Freedom Power Management and distribution DC test bed

NASA Technical Reports Server (NTRS)

Lebron, Ramon C.; Oliver, Angela C.; Bodi, Robert F.

1991-01-01

Power components hardware in support of the Space Station Freedom dc Electrical Power System were tested. One type of breadboard hardware tested is the dc Load Converter Unit, which constitutes the power interface between the electric power system and the actual load. These units are dc to dc converters that provide the final system regulation before power is delivered to the load. Three load converters were tested: a series resonant converter, a series inductor switchmode converter, and a switching full-bridge forward converter. The topology, operation principles, and tests results are described, in general. A comparative analysis of the three units is given with respect to efficiency, regulation, short circuit behavior (protection), and transient characteristics.

Design of an Incubator for Premature Infant Based on LabVIEW.

PubMed

Zhang, Lina; Zhou, Runjing

2005-01-01

This paper introduces the system structure, hardware circuits, control algorithms, and software program of the incubator for premature infant based on LabVIEW. The main advantages of this device are that preheating is less time than others, the capability of meeting of emergency is provided, control track of temperature and humidity are visible, operation is easy to clinical practice, and maintainability is possessed.

Advanced Shutter Control for a Molecular Beam Epitaxy Reactor

DTIC Science & Technology

An open-source hardware and software-based shutter controller solution was developed that communicates over Ethernet with our original equipment...manufacturer (OEM) molecular beam epitaxy (MBE) reactor control software. An Arduino Mega microcontroller is the used for the brain of the shutter... controller , while a custom-designed circuit board distributes 24-V power to each of the 16 shutter solenoids available on the MBE. Using Ethernet

AER synthetic generation in hardware for bio-inspired spiking systems

NASA Astrophysics Data System (ADS)

Linares-Barranco, Alejandro; Linares-Barranco, Bernabe; Jimenez-Moreno, Gabriel; Civit-Balcells, Anton

2005-06-01

Address Event Representation (AER) is an emergent neuromorphic interchip communication protocol that allows for real-time virtual massive connectivity between huge number neurons located on different chips. By exploiting high speed digital communication circuits (with nano-seconds timings), synaptic neural connections can be time multiplexed, while neural activity signals (with mili-seconds timings) are sampled at low frequencies. Also, neurons generate 'events' according to their activity levels. More active neurons generate more events per unit time, and access the interchip communication channel more frequently, while neurons with low activity consume less communication bandwidth. When building multi-chip muti-layered AER systems it is absolutely necessary to have a computer interface that allows (a) to read AER interchip traffic into the computer and visualize it on screen, and (b) convert conventional frame-based video stream in the computer into AER and inject it at some point of the AER structure. This is necessary for test and debugging of complex AER systems. This paper addresses the problem of converting, in a computer, a conventional frame-based video stream into the spike event based representation AER. There exist several proposed software methods for synthetic generation of AER for bio-inspired systems. This paper presents a hardware implementation for one method, which is based on Linear-Feedback-Shift-Register (LFSR) pseudo-random number generation. The sequence of events generated by this hardware, which follows a Poisson distribution like a biological neuron, has been reconstructed using two AER integrator cells. The error of reconstruction for a set of images that produces different traffic loads of event in the AER bus is used as evaluation criteria. A VHDL description of the method, that includes the Xilinx PCI Core, has been implemented and tested using a general purpose PCI-AER board. This PCI-AER board has been developed by authors, and uses a Spartan II 200 FPGA. This system for AER Synthetic Generation is capable of transforming frames of 64x64 pixels, received through a standard computer PCI bus, at a frame rate of 25 frames per second, producing spike events at a peak rate of 107 events per second.

Architecture Framework for Trapped-Ion Quantum Computer based on Performance Simulation Tool

NASA Astrophysics Data System (ADS)

Ahsan, Muhammad

The challenge of building scalable quantum computer lies in striking appropriate balance between designing a reliable system architecture from large number of faulty computational resources and improving the physical quality of system components. The detailed investigation of performance variation with physics of the components and the system architecture requires adequate performance simulation tool. In this thesis we demonstrate a software tool capable of (1) mapping and scheduling the quantum circuit on a realistic quantum hardware architecture with physical resource constraints, (2) evaluating the performance metrics such as the execution time and the success probability of the algorithm execution, and (3) analyzing the constituents of these metrics and visualizing resource utilization to identify system components which crucially define the overall performance. Using this versatile tool, we explore vast design space for modular quantum computer architecture based on trapped ions. We find that while success probability is uniformly determined by the fidelity of physical quantum operation, the execution time is a function of system resources invested at various layers of design hierarchy. At physical level, the number of lasers performing quantum gates, impact the latency of the fault-tolerant circuit blocks execution. When these blocks are used to construct meaningful arithmetic circuit such as quantum adders, the number of ancilla qubits for complicated non-clifford gates and entanglement resources to establish long-distance communication channels, become major performance limiting factors. Next, in order to factorize large integers, these adders are assembled into modular exponentiation circuit comprising bulk of Shor's algorithm. At this stage, the overall scaling of resource-constraint performance with the size of problem, describes the effectiveness of chosen design. By matching the resource investment with the pace of advancement in hardware technology, we find optimal designs for different types of quantum adders. Conclusively, we show that 2,048-bit Shor's algorithm can be reliably executed within the resource budget of 1.5 million qubits.

AUTOMOTIVE DIESEL MAINTENANCE 2. UNIT IX, AUTOMATIC TRANSMISSIONS--HYDRAULIC SYSTEM (PART I).

ERIC Educational Resources Information Center

Human Engineering Inst., Cleveland, OH.

THIS MODULE OF A 25-MODULE COURSE IS DESIGNED TO DEVELOP AN UNDERSTANDING OF THE OIL FLOW WITHIN HYDRAULIC TRANSMISSIONS USED ON DIESEL POWERED VEHICLES. TOPICS ARE GENERAL DESCRIPTION, HYDRAULIC CIRCUITS, AND BRAKE HYDRAULIC CIRCUIT AND OPERATION. THE MODULE CONSISTS OF A SELF-INSTRUCTIONAL PROGRAMED TRAINING FILM "LEARNING ABOUT THE ALLISON…

An optimized implementation of a fault-tolerant clock synchronization circuit

NASA Technical Reports Server (NTRS)

Torres-Pomales, Wilfredo

1995-01-01

A fault-tolerant clock synchronization circuit was designed and tested. A comparison to a previous design and the procedure followed to achieve the current optimization are included. The report also includes a description of the system and the results of tests performed to study the synchronization and fault-tolerant characteristics of the implementation.

FPGA-Based, Self-Checking, Fault-Tolerant Computers

NASA Technical Reports Server (NTRS)

Some, Raphael; Rennels, David

2004-01-01

A proposed computer architecture would exploit the capabilities of commercially available field-programmable gate arrays (FPGAs) to enable computers to detect and recover from bit errors. The main purpose of the proposed architecture is to enable fault-tolerant computing in the presence of single-event upsets (SEUs). [An SEU is a spurious bit flip (also called a soft error) caused by a single impact of ionizing radiation.] The architecture would also enable recovery from some soft errors caused by electrical transients and, to some extent, from intermittent and permanent (hard) errors caused by aging of electronic components. A typical FPGA of the current generation contains one or more complete processor cores, memories, and highspeed serial input/output (I/O) channels, making it possible to shrink a board-level processor node to a single integrated-circuit chip. Custom, highly efficient microcontrollers, general-purpose computers, custom I/O processors, and signal processors can be rapidly and efficiently implemented by use of FPGAs. Unfortunately, FPGAs are susceptible to SEUs. Prior efforts to mitigate the effects of SEUs have yielded solutions that degrade performance of the system and require support from external hardware and software. In comparison with other fault-tolerant- computing architectures (e.g., triple modular redundancy), the proposed architecture could be implemented with less circuitry and lower power demand. Moreover, the fault-tolerant computing functions would require only minimal support from circuitry outside the central processing units (CPUs) of computers, would not require any software support, and would be largely transparent to software and to other computer hardware. There would be two types of modules: a self-checking processor module and a memory system (see figure). The self-checking processor module would be implemented on a single FPGA and would be capable of detecting its own internal errors. It would contain two CPUs executing identical programs in lock step, with comparison of their outputs to detect errors. It would also contain various cache local memory circuits, communication circuits, and configurable special-purpose processors that would use self-checking checkers. (The basic principle of the self-checking checker method is to utilize logic circuitry that generates error signals whenever there is an error in either the checker or the circuit being checked.) The memory system would comprise a main memory and a hardware-controlled check-pointing system (CPS) based on a buffer memory denoted the recovery cache. The main memory would contain random-access memory (RAM) chips and FPGAs that would, in addition to everything else, implement double-error-detecting and single-error-correcting memory functions to enable recovery from single-bit errors.

The DYNES Instrument: A Description and Overview

NASA Astrophysics Data System (ADS)

Zurawski, Jason; Ball, Robert; Barczyk, Artur; Binkley, Mathew; Boote, Jeff; Boyd, Eric; Brown, Aaron; Brown, Robert; Lehman, Tom; McKee, Shawn; Meekhof, Benjeman; Mughal, Azher; Newman, Harvey; Rozsa, Sandor; Sheldon, Paul; Tackett, Alan; Voicu, Ramiro; Wolff, Stephen; Yang, Xi

2012-12-01

Scientific innovation continues to increase requirements for the computing and networking infrastructures of the world. Collaborative partners, instrumentation, storage, and processing facilities are often geographically and topologically separated, as is the case with LHC virtual organizations. These separations challenge the technology used to interconnect available resources, often delivered by Research and Education (R&E) networking providers, and leads to complications in the overall process of end-to-end data management. Capacity and traffic management are key concerns of R&E network operators; a delicate balance is required to serve both long-lived, high capacity network flows, as well as more traditional end-user activities. The advent of dynamic circuit services, a technology that enables the creation of variable duration, guaranteed bandwidth networking channels, allows for the efficient use of common network infrastructures. These gains are seen particularly in locations where overall capacity is scarce compared to the (sustained peak) needs of user communities. Related efforts, including those of the LHCOPN [3] operations group and the emerging LHCONE [4] project, may take advantage of available resources by designating specific network activities as a “high priority”, allowing reservation of dedicated bandwidth or optimizing for deadline scheduling and predicable delivery patterns. This paper presents the DYNES instrument, an NSF funded cyberinfrastructure project designed to facilitate end-to-end dynamic circuit services [2]. This combination of hardware and software innovation is being deployed across R&E networks in the United States at selected end-sites located on University Campuses. DYNES is peering with international efforts in other countries using similar solutions, and is increasing the reach of this emerging technology. This global data movement solution could be integrated into computing paradigms such as cloud and grid computing platforms, and through the use of APIs can be integrated into existing data movement software.

Viking 75 project: Viking lander system primary mission performance report

NASA Technical Reports Server (NTRS)

Cooley, C. G.

1977-01-01

Viking Lander hardware performance during launch, interplanetary cruise, Mars orbit insertion, preseparation, separation through landing, and the primary landed mission, with primary emphasis on Lander engineering and science hardware operations, the as-flown mission are described with respect to Lander system performance and anomalies during the various mission phases. The extended mission and predicted Lander performance is discussed along with a summary of Viking goals, mission plans, and description of the Lander, and its subsystem definitions.

Computer-aided design and computer science technology

NASA Technical Reports Server (NTRS)

Fulton, R. E.; Voigt, S. J.

1976-01-01

A description is presented of computer-aided design requirements and the resulting computer science advances needed to support aerospace design. The aerospace design environment is examined, taking into account problems of data handling and aspects of computer hardware and software. The interactive terminal is normally the primary interface between the computer system and the engineering designer. Attention is given to user aids, interactive design, interactive computations, the characteristics of design information, data management requirements, hardware advancements, and computer science developments.

Dissecting the COW

DOE Office of Scientific and Technical Information (OSTI.GOV)

Linstadt, E.

1985-10-01

The COW, or Console On Wheels, is the primary operator interface to the SLC accelerator control system. A hardware and software description of the COW, a microcomputer based system with a color graphics display output and touchpanel and knob inputs, is given. The ease of development and expandability, due to both the modular nature of the hardware and the multitasking, interrupt driven software running in the COW, are described. Integration of the COW into the SLCNET communications network and SLC Control system is detailed.

Laboratory process control using natural language commands from a personal computer

NASA Technical Reports Server (NTRS)

Will, Herbert A.; Mackin, Michael A.

1989-01-01

PC software is described which provides flexible natural language process control capability with an IBM PC or compatible machine. Hardware requirements include the PC, and suitable hardware interfaces to all controlled devices. Software required includes the Microsoft Disk Operating System (MS-DOS) operating system, a PC-based FORTRAN-77 compiler, and user-written device drivers. Instructions for use of the software are given as well as a description of an application of the system.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kumar, Dinesh; Thapliyal, Himanshu; Mohammad, Azhar

Differential Power Analysis (DPA) attack is considered to be a main threat while designing cryptographic processors. In cryptographic algorithms like DES and AES, S-Box is used to indeterminate the relationship between the keys and the cipher texts. However, S-box is prone to DPA attack due to its high power consumption. In this paper, we are implementing an energy-efficient 8-bit S-Box circuit using our proposed Symmetric Pass Gate Adiabatic Logic (SPGAL). SPGAL is energy-efficient as compared to the existing DPAresistant adiabatic and non-adiabatic logic families. SPGAL is energy-efficient due to reduction of non-adiabatic loss during the evaluate phase of the outputs.more » Further, the S-Box circuit implemented using SPGAL is resistant to DPA attacks. The results are verified through SPICE simulations in 180nm technology. SPICE simulations show that the SPGAL based S-Box circuit saves upto 92% and 67% of energy as compared to the conventional CMOS and Secured Quasi-Adiabatic Logic (SQAL) based S-Box circuit. From the simulation results, it is evident that the SPGAL based circuits are energy-efficient as compared to the existing DPAresistant adiabatic and non-adiabatic logic families. In nutshell, SPGAL based gates can be used to build secure hardware for lowpower portable electronic devices and Internet-of-Things (IoT) based electronic devices.« less

Implementation of the 2-D Wavelet Transform into FPGA for Image

NASA Astrophysics Data System (ADS)

León, M.; Barba, L.; Vargas, L.; Torres, C. O.

2011-01-01

This paper presents a hardware system implementation of the of discrete wavelet transform algoritm in two dimensions for FPGA, using the Daubechies filter family of order 2 (db2). The decomposition algorithm of this transform is designed and simulated with the Hardware Description Language VHDL and is implemented in a programmable logic device (FPGA) XC3S1200E reference, Spartan IIIE family, by Xilinx, take advantage the parallels properties of these gives us and speeds processing that can reach them. The architecture is evaluated using images input of different sizes. This implementation is done with the aim of developing a future images encryption hardware system using wavelet transform for security information.

Effects of AEA Cell-Bypass-Switch Closure on Charged EOS-Aqua NiH2 Cell

NASA Technical Reports Server (NTRS)

Keys, Denney; Rao, Gopalakrishna M.; Sullivan, David; Wannemacher, Harry

2001-01-01

The nominal performance of AEA CBPD under simulated EOS-Aqua/Aura flight hardware configuration has been demonstrated. There is no evidence of cell rupture or excessive heat production during or after CBPD switch activation under simulated high cell impedance (open-circuit cell failure mode). Inadvertent CBPD switch activation with a charged cell (low impedance path) intermittently closes and opens up the switch, therefore the device may or may not provide protection against future open-circuit cell failure. Further testing with switches F01 and F02 may provide clarification. The formation of a continuous low impedance path (a homogeneous low melting point alloy), has been confirmed - which is the expected mode of operation.

Loopback Tester: a synchronous communications circuit diagnostic device

DOE Office of Scientific and Technical Information (OSTI.GOV)

Maestas, J.H.

1986-07-01

The Loopback Tester is an Intel SBC 86/12A Single Board Computer and an Intel SBC 534 Communications Expansion Board configured and programmed to perform various basic or less. These tests include: (1) Data Communications Equipment (DCE) transmit timing detection (2) data rate measurement (3) instantaneous loopback indication and (4) bit error rate testing. It requires no initial setup after plug in, and can be used to locate the source of communications loss in a circuit. It can also be used to determine when crypto variable mismatch problems are the source of communications loss. This report discusses the functionality of themore » Loopback Tester as a diagnostic device. It also discusses the hardware and software which implements this simple yet reliable device.« less

High frequency, high time resolution time-to-digital converter employing passive resonating circuits.

PubMed

Ripamonti, Giancarlo; Abba, Andrea; Geraci, Angelo

2010-05-01

A method for measuring time intervals accurate to the picosecond range is based on phase measurements of oscillating waveforms synchronous with their beginning and/or end. The oscillation is generated by triggering an LC resonant circuit, whose capacitance is precharged. By using high Q resonators and a final active quenching of the oscillation, it is possible to conjugate high time resolution and a small measurement time, which allows a high measurement rate. Methods for fast analysis of the data are considered and discussed with reference to computing resource requirements, speed, and accuracy. Experimental tests show the feasibility of the method and a time accuracy better than 4 ps rms. Methods aimed at further reducing hardware resources are finally discussed.

Floating-Point Units and Algorithms for field-programmable gate arrays

DOE Office of Scientific and Technical Information (OSTI.GOV)

Underwood, Keith D.; Hemmert, K. Scott

2005-11-01

The software that we are attempting to copyright is a package of floating-point unit descriptions and example algorithm implementations using those units for use in FPGAs. The floating point units are best-in-class implementations of add, multiply, divide, and square root floating-point operations. The algorithm implementations are sample (not highly flexible) implementations of FFT, matrix multiply, matrix vector multiply, and dot product. Together, one could think of the collection as an implementation of parts of the BLAS library or something similar to the FFTW packages (without the flexibility) for FPGAs. Results from this work has been published multiple times and wemore » are working on a publication to discuss the techniques we use to implement the floating-point units, For some more background, FPGAS are programmable hardware. "Programs" for this hardware are typically created using a hardware description language (examples include Verilog, VHDL, and JHDL). Our floating-point unit descriptions are written in JHDL, which allows them to include placement constraints that make them highly optimized relative to some other implementations of floating-point units. Many vendors (Nallatech from the UK, SRC Computers in the US) have similar implementations, but our implementations seem to be somewhat higher performance. Our algorithm implementations are written in VHDL and models of the floating-point units are provided in VHDL as well. FPGA "programs" make multiple "calls" (hardware instantiations) to libraries of intellectual property (IP), such as the floating-point unit library described here. These programs are then compiled using a tool called a synthesizer (such as a tool from Synplicity, Inc.). The compiled file is a netlist of gates and flip-flops. This netlist is then mapped to a particular type of FPGA by a mapper and then a place- and-route tool. These tools assign the gates in the netlist to specific locations on the specific type of FPGA chip used and constructs the required routes between them. The result is a "bitstream" that is analogous to a compiled binary. The bitstream is loaded into the FPGA to create a specific hardware configuration.« less

Lightweight Payload for High Altitude Balloons

DTIC Science & Technology

1991-05-21

common at microwave frequencies. Examples of such transponders are DSCS-fl, DSCS-Ill, NATO- III, Nato-IV, and Skynet-4.I Rx Translation Tx Wideband BPF ...Narrowband Limiter BPF Bank BankI Figure 2.4-2. Channelized Transponder ArchitectureI The disadvantage of channelization is the hardware complexity. We...excessive electromagnetic interference (EMI), either conducted or radiated, from one part of the circuit to another. There are three major guidelines

Evolvable Hardware for Space Applications

NASA Technical Reports Server (NTRS)

Lohn, Jason; Globus, Al; Hornby, Gregory; Larchev, Gregory; Kraus, William

2004-01-01

This article surveys the research of the Evolvable Systems Group at NASA Ames Research Center. Over the past few years, our group has developed the ability to use evolutionary algorithms in a variety of NASA applications ranging from spacecraft antenna design, fault tolerance for programmable logic chips, atomic force field parameter fitting, analog circuit design, and earth observing satellite scheduling. In some of these applications, evolutionary algorithms match or improve on human performance.

Evaluation of SSME test data reduction methods

NASA Technical Reports Server (NTRS)

Santi, L. Michael

1994-01-01

Accurate prediction of hardware and flow characteristics within the Space Shuttle Main Engine (SSME) during transient and main-stage operation requires a significant integration of ground test data, flight experience, and computational models. The process of integrating SSME test measurements with physical model predictions is commonly referred to as data reduction. Uncertainties within both test measurements and simplified models of the SSME flow environment compound the data integration problem. The first objective of this effort was to establish an acceptability criterion for data reduction solutions. The second objective of this effort was to investigate the data reduction potential of the ROCETS (Rocket Engine Transient Simulation) simulation platform. A simplified ROCETS model of the SSME was obtained from the MSFC Performance Analysis Branch . This model was examined and tested for physical consistency. Two modules were constructed and added to the ROCETS library to independently check the mass and energy balances of selected engine subsystems including the low pressure fuel turbopump, the high pressure fuel turbopump, the low pressure oxidizer turbopump, the high pressure oxidizer turbopump, the fuel preburner, the oxidizer preburner, the main combustion chamber coolant circuit, and the nozzle coolant circuit. A sensitivity study was then conducted to determine the individual influences of forty-two hardware characteristics on fourteen high pressure region prediction variables as returned by the SSME ROCETS model.

Synthesizing cognition in neuromorphic electronic systems

PubMed Central

Neftci, Emre; Binas, Jonathan; Rutishauser, Ueli; Chicca, Elisabetta; Indiveri, Giacomo; Douglas, Rodney J.

2013-01-01

The quest to implement intelligent processing in electronic neuromorphic systems lacks methods for achieving reliable behavioral dynamics on substrates of inherently imprecise and noisy neurons. Here we report a solution to this problem that involves first mapping an unreliable hardware layer of spiking silicon neurons into an abstract computational layer composed of generic reliable subnetworks of model neurons and then composing the target behavioral dynamics as a “soft state machine” running on these reliable subnets. In the first step, the neural networks of the abstract layer are realized on the hardware substrate by mapping the neuron circuit bias voltages to the model parameters. This mapping is obtained by an automatic method in which the electronic circuit biases are calibrated against the model parameters by a series of population activity measurements. The abstract computational layer is formed by configuring neural networks as generic soft winner-take-all subnetworks that provide reliable processing by virtue of their active gain, signal restoration, and multistability. The necessary states and transitions of the desired high-level behavior are then easily embedded in the computational layer by introducing only sparse connections between some neurons of the various subnets. We demonstrate this synthesis method for a neuromorphic sensory agent that performs real-time context-dependent classification of motion patterns observed by a silicon retina. PMID:23878215

Analog quantum simulation of the Rabi model in the ultra-strong coupling regime.

PubMed

Braumüller, Jochen; Marthaler, Michael; Schneider, Andre; Stehli, Alexander; Rotzinger, Hannes; Weides, Martin; Ustinov, Alexey V

2017-10-03

The quantum Rabi model describes the fundamental mechanism of light-matter interaction. It consists of a two-level atom or qubit coupled to a quantized harmonic mode via a transversal interaction. In the weak coupling regime, it reduces to the well-known Jaynes-Cummings model by applying a rotating wave approximation. The rotating wave approximation breaks down in the ultra-strong coupling regime, where the effective coupling strength g is comparable to the energy ω of the bosonic mode, and remarkable features in the system dynamics are revealed. Here we demonstrate an analog quantum simulation of an effective quantum Rabi model in the ultra-strong coupling regime, achieving a relative coupling ratio of g/ω ~ 0.6. The quantum hardware of the simulator is a superconducting circuit embedded in a cQED setup. We observe fast and periodic quantum state collapses and revivals of the initial qubit state, being the most distinct signature of the synthesized model.An analog quantum simulation scheme has been explored with a quantum hardware based on a superconducting circuit. Here the authors investigate the time evolution of the quantum Rabi model at ultra-strong coupling conditions, which is synthesized by slowing down the system dynamics in an effective frame.

Josephson junction in the quantum mesoscopic electric circuits with charge discreteness

NASA Astrophysics Data System (ADS)

Pahlavani, H.

2018-04-01

A quantum mesoscopic electrical LC-circuit with charge discreteness including a Josephson junction is considered and a nonlinear Hamiltonian that describing the dynamic of such circuit is introduced. The quantum dynamical behavior (persistent current probability) is studied in the charge and phase regimes by numerical solution approaches. The time evolution of charge and current, number-difference and the bosonic phase and also the energy spectrum of a quantum mesoscopic electric LC-circuit with charge discreteness that coupled with a Josephson junction device are investigated. We show the role of the coupling energy and the electrostatic Coulomb energy of the Josephson junction in description of the quantum behavior and the spectral properties of a quantum mesoscopic electrical LC-circuits with charge discreteness.

Dissecting the COW

DOE Office of Scientific and Technical Information (OSTI.GOV)

Linstadt, E.

1985-04-01

The COW, or Console On Wheels, is the primary operator interface to the SLC accelerator control system. A hardware and software description of the COW, a microcomputer based system with a color graphics display output and touch-panel and knob inputs, is given. The ease of development and expandability, due to both the modular nature of the hardware and the multitasking, interrupt driven software running in the COW, are described. Integration of the COW into the SLCNET communications network and SLC Control system is detailed.

Efficient and self-adaptive in-situ learning in multilayer memristor neural networks.

PubMed

Li, Can; Belkin, Daniel; Li, Yunning; Yan, Peng; Hu, Miao; Ge, Ning; Jiang, Hao; Montgomery, Eric; Lin, Peng; Wang, Zhongrui; Song, Wenhao; Strachan, John Paul; Barnell, Mark; Wu, Qing; Williams, R Stanley; Yang, J Joshua; Xia, Qiangfei

2018-06-19

Memristors with tunable resistance states are emerging building blocks of artificial neural networks. However, in situ learning on a large-scale multiple-layer memristor network has yet to be demonstrated because of challenges in device property engineering and circuit integration. Here we monolithically integrate hafnium oxide-based memristors with a foundry-made transistor array into a multiple-layer neural network. We experimentally demonstrate in situ learning capability and achieve competitive classification accuracy on a standard machine learning dataset, which further confirms that the training algorithm allows the network to adapt to hardware imperfections. Our simulation using the experimental parameters suggests that a larger network would further increase the classification accuracy. The memristor neural network is a promising hardware platform for artificial intelligence with high speed-energy efficiency.

[The design of a cardiac monitoring and analysing system with low power consumption].

PubMed

Chen, Zhen-cheng; Ni, Li-li; Zhu, Yan-gao; Wang, Hong-yan; Ma, Yan

2002-07-01

The paper deals with a portable analyzing monitor system with liquid crystal display (LCD), which is low in power consumption and suitable for China's specific conditions. Apart from the development of the overall scheme of the system, the paper introduces the design of the hardware and the software. The 80196 single chip microcomputer is used as the central microprocessor to process and real-time electrocardiac signal data. The system have the following functions: five types of arrhythmia analysis, alarm, freeze, and record of automatic paperfeeding. The portable system can be operated by alternate-current (AC) or direct-current (DC). Its hardware circuit is simplified and its software structure is optimized. Multiple low power consumption and LCD unit are adopted in its modular designs.

Test and evaluation of load converter topologies used in the Space Station Freedom power management and distribution dc test bed

NASA Technical Reports Server (NTRS)

Lebron, Ramon C.; Oliver, Angela C.; Bodi, Robert F.

1991-01-01

Power components hardware in support of the Space Station freedom dc Electric Power System were tested. One type of breadboard hardware tested is the dc Load Converter Unit, which constitutes the power interface between the electric power system and the actual load. These units are dc to dc converters that provide the final system regulation before power is delivered to the load. Three load converters were tested: a series resonant converter, a series inductor switch-mode converter, and a switching full-bridge forward converter. The topology, operation principles, and test results are described, in general. A comparative analysis of the three units is given with respect to efficiency, regulation, short circuit behavior (protection), and transient characteristics.

Merlin - Massively parallel heterogeneous computing

NASA Technical Reports Server (NTRS)

Wittie, Larry; Maples, Creve

1989-01-01

Hardware and software for Merlin, a new kind of massively parallel computing system, are described. Eight computers are linked as a 300-MIPS prototype to develop system software for a larger Merlin network with 16 to 64 nodes, totaling 600 to 3000 MIPS. These working prototypes help refine a mapped reflective memory technique that offers a new, very general way of linking many types of computer to form supercomputers. Processors share data selectively and rapidly on a word-by-word basis. Fast firmware virtual circuits are reconfigured to match topological needs of individual application programs. Merlin's low-latency memory-sharing interfaces solve many problems in the design of high-performance computing systems. The Merlin prototypes are intended to run parallel programs for scientific applications and to determine hardware and software needs for a future Teraflops Merlin network.

A methodology of SiP testing based on boundary scan

NASA Astrophysics Data System (ADS)

Qin, He; Quan, Haiyang; Han, Yifei; Zhu, Tianrui; Zheng, Tuo

2017-10-01

System in Package (SiP) play an important role in portable, aerospace and military electronic with the microminiaturization, light weight, high density, and high reliability. At present, SiP system test has encountered the problem on system complexity and malfunction location with the system scale exponentially increase. For SiP system, this paper proposed a testing methodology and testing process based on the boundary scan technology. Combining the character of SiP system and referencing the boundary scan theory of PCB circuit and embedded core test, the specific testing methodology and process has been proposed. The hardware requirement of the under test SiP system has been provided, and the hardware platform of the testing has been constructed. The testing methodology has the character of high test efficiency and accurate malfunction location.

Multipurpose silicon photonics signal processor core.

PubMed

Pérez, Daniel; Gasulla, Ivana; Crudgington, Lee; Thomson, David J; Khokhar, Ali Z; Li, Ke; Cao, Wei; Mashanovich, Goran Z; Capmany, José

2017-09-21

Integrated photonics changes the scaling laws of information and communication systems offering architectural choices that combine photonics with electronics to optimize performance, power, footprint, and cost. Application-specific photonic integrated circuits, where particular circuits/chips are designed to optimally perform particular functionalities, require a considerable number of design and fabrication iterations leading to long development times. A different approach inspired by electronic Field Programmable Gate Arrays is the programmable photonic processor, where a common hardware implemented by a two-dimensional photonic waveguide mesh realizes different functionalities through programming. Here, we report the demonstration of such reconfigurable waveguide mesh in silicon. We demonstrate over 20 different functionalities with a simple seven hexagonal cell structure, which can be applied to different fields including communications, chemical and biomedical sensing, signal processing, multiprocessor networks, and quantum information systems. Our work is an important step toward this paradigm.Integrated optical circuits today are typically designed for a few special functionalities and require complex design and development procedures. Here, the authors demonstrate a reconfigurable but simple silicon waveguide mesh with different functionalities.

An Efficient VLSI Architecture for Multi-Channel Spike Sorting Using a Generalized Hebbian Algorithm

PubMed Central

Chen, Ying-Lun; Hwang, Wen-Jyi; Ke, Chi-En

2015-01-01

A novel VLSI architecture for multi-channel online spike sorting is presented in this paper. In the architecture, the spike detection is based on nonlinear energy operator (NEO), and the feature extraction is carried out by the generalized Hebbian algorithm (GHA). To lower the power consumption and area costs of the circuits, all of the channels share the same core for spike detection and feature extraction operations. Each channel has dedicated buffers for storing the detected spikes and the principal components of that channel. The proposed circuit also contains a clock gating system supplying the clock to only the buffers of channels currently using the computation core to further reduce the power consumption. The architecture has been implemented by an application-specific integrated circuit (ASIC) with 90-nm technology. Comparisons to the existing works show that the proposed architecture has lower power consumption and hardware area costs for real-time multi-channel spike detection and feature extraction. PMID:26287193

An Efficient VLSI Architecture for Multi-Channel Spike Sorting Using a Generalized Hebbian Algorithm.

PubMed

Chen, Ying-Lun; Hwang, Wen-Jyi; Ke, Chi-En

2015-08-13

A novel VLSI architecture for multi-channel online spike sorting is presented in this paper. In the architecture, the spike detection is based on nonlinear energy operator (NEO), and the feature extraction is carried out by the generalized Hebbian algorithm (GHA). To lower the power consumption and area costs of the circuits, all of the channels share the same core for spike detection and feature extraction operations. Each channel has dedicated buffers for storing the detected spikes and the principal components of that channel. The proposed circuit also contains a clock gating system supplying the clock to only the buffers of channels currently using the computation core to further reduce the power consumption. The architecture has been implemented by an application-specific integrated circuit (ASIC) with 90-nm technology. Comparisons to the existing works show that the proposed architecture has lower power consumption and hardware area costs for real-time multi-channel spike detection and feature extraction.

Initial SVS Integrated Technology Evaluation Flight Test Requirements and Hardware Architecture

NASA Technical Reports Server (NTRS)

Harrison, Stella V.; Kramer, Lynda J.; Bailey, Randall E.; Jones, Denise R.; Young, Steven D.; Harrah, Steven D.; Arthur, Jarvis J.; Parrish, Russell V.

2003-01-01

This document presents the flight test requirements for the Initial Synthetic Vision Systems Integrated Technology Evaluation flight Test to be flown aboard NASA Langley's ARIES aircraft and the final hardware architecture implemented to meet these requirements. Part I of this document contains the hardware, software, simulator, and flight operations requirements for this light test as they were defined in August 2002. The contents of this section are the actual requirements document that was signed for this flight test. Part II of this document contains information pertaining to the hardware architecture that was realized to meet these requirements as presented to and approved by a Critical Design Review Panel prior to installation on the B-757 Airborne Research Integrated Experiments Systems (ARIES) airplane. This information includes a description of the equipment, block diagrams of the architecture, layouts of the workstations, and pictures of the actual installations.

Effect of Joule heating and current crowding on electromigration in mobile technology

NASA Astrophysics Data System (ADS)

Tu, K. N.; Liu, Yingxia; Li, Menglu

2017-03-01

In the present era of big data and internet of things, the use of microelectronic products in all aspects of our life is manifested by the ubiquitous presence of mobile devices as i-phones and wearable i-products. These devices are facing the need for higher power and greater functionality applications such as in i-health, yet they are limited by physical size. At the moment, software (Apps) is much ahead of hardware in mobile technology. To advance hardware, the end of Moore's law in two-dimensional integrated circuits can be extended by three-dimensional integrated circuits (3D ICs). The concept of 3D ICs has been with us for more than ten years. The challenge in 3D IC technology is dense packing by using both vertical and horizontal interconnections. Mass production of 3D IC devices is behind schedule due to cost because of low yield and uncertain reliability. Joule heating is serious in a dense structure because of heat generation and dissipation. A change of reliability paradigm has advanced from failure at a specific circuit component to failure at a system level weak-link. Currently, the electronic industry is introducing 3D IC devices in mainframe computers, where cost is not an issue, for the purpose of collecting field data of failure, especially the effect of Joule heating and current crowding on electromigration. This review will concentrate on the positive feedback between Joule heating and electromigration, resulting in an accelerated system level weak-link failure. A new driving force of electromigration, the electric potential gradient force due to current crowding, will be reviewed critically. The induced failure tends to occur in the low current density region.

Design of a Low-Power, Small-Area AEC-Q100-Compliant SENT Transmitter in Signal Conditioning IC for Automotive Pressure and Temperature Complex Sensors in 180 Nm CMOS Technology.

PubMed

Ali, Imran; Rikhan, Behnam Samadpoor; Kim, Dong-Gyu; Lee, Dong-Soo; Rehman, Muhammad Riaz Ur; Abbasizadeh, Hamed; Asif, Muhammad; Lee, Minjae; Hwang, Keum Cheol; Yang, Youngoo; Lee, Kang-Yoon

2018-05-14

In this paper, a low-power and small-area Single Edge Nibble Transmission (SENT) transmitter design is proposed for automotive pressure and temperature complex sensor applications. To reduce the cost and size of the hardware, the pressure and temperature information is processed with a single integrated circuit (IC) and transmitted at the same time to the electronic control unit (ECU) through SENT. Due to its digital nature, it is immune to noise, has reduced sensitivity to electromagnetic interference (EMI), and generates low EMI. It requires only one PAD for its connectivity with ECU, and thus reduces the pin requirements, simplifies the connectivity, and minimizes the printed circuit board (PCB) complexity. The design is fully synthesizable, and independent of technology. The finite state machine-based approach is employed for area efficient implementation, and to translate the proposed architecture into hardware. The IC is fabricated in 1P6M 180 nm CMOS process with an area of (116 μm × 116 μm) and 4.314 K gates. The current consumption is 50 μA from a 1.8 V supply with a total 90 μW power. For compliance with AEC-Q100 for automotive reliability, a reverse and over voltage protection circuit is also implemented with human body model (HBM) electro-static discharge (ESD) of +6 kV, reverse voltage of -16 V to 0 V, over voltage of 8.2 V to 16 V, and fabricated area of 330 μm × 680 μm. The extensive testing, measurement, and simulation results prove that the design is fully compliant with SAE J2716 standard.

Design of a Low-Power, Small-Area AEC-Q100-Compliant SENT Transmitter in Signal Conditioning IC for Automotive Pressure and Temperature Complex Sensors in 180 Nm CMOS Technology

PubMed Central

Rikhan, Behnam Samadpoor; Kim, Dong-Gyu; Lee, Dong-Soo; Rehman, Muhammad Riaz Ur; Abbasizadeh, Hamed; Asif, Muhammad; Lee, Minjae; Yang, Youngoo; Lee, Kang-Yoon

2018-01-01

In this paper, a low-power and small-area Single Edge Nibble Transmission (SENT) transmitter design is proposed for automotive pressure and temperature complex sensor applications. To reduce the cost and size of the hardware, the pressure and temperature information is processed with a single integrated circuit (IC) and transmitted at the same time to the electronic control unit (ECU) through SENT. Due to its digital nature, it is immune to noise, has reduced sensitivity to electromagnetic interference (EMI), and generates low EMI. It requires only one PAD for its connectivity with ECU, and thus reduces the pin requirements, simplifies the connectivity, and minimizes the printed circuit board (PCB) complexity. The design is fully synthesizable, and independent of technology. The finite state machine-based approach is employed for area efficient implementation, and to translate the proposed architecture into hardware. The IC is fabricated in 1P6M 180 nm CMOS process with an area of (116 μm × 116 μm) and 4.314 K gates. The current consumption is 50 μA from a 1.8 V supply with a total 90 μW power. For compliance with AEC-Q100 for automotive reliability, a reverse and over voltage protection circuit is also implemented with human body model (HBM) electro-static discharge (ESD) of +6 kV, reverse voltage of −16 V to 0 V, over voltage of 8.2 V to 16 V, and fabricated area of 330 μm × 680 μm. The extensive testing, measurement, and simulation results prove that the design is fully compliant with SAE J2716 standard. PMID:29757996

Superconducting Optoelectronic Circuits for Neuromorphic Computing

NASA Astrophysics Data System (ADS)

Shainline, Jeffrey M.; Buckley, Sonia M.; Mirin, Richard P.; Nam, Sae Woo

2017-03-01

Neural networks have proven effective for solving many difficult computational problems, yet implementing complex neural networks in software is computationally expensive. To explore the limits of information processing, it is necessary to implement new hardware platforms with large numbers of neurons, each with a large number of connections to other neurons. Here we propose a hybrid semiconductor-superconductor hardware platform for the implementation of neural networks and large-scale neuromorphic computing. The platform combines semiconducting few-photon light-emitting diodes with superconducting-nanowire single-photon detectors to behave as spiking neurons. These processing units are connected via a network of optical waveguides, and variable weights of connection can be implemented using several approaches. The use of light as a signaling mechanism overcomes fanout and parasitic constraints on electrical signals while simultaneously introducing physical degrees of freedom which can be employed for computation. The use of supercurrents achieves the low power density (1 mW /cm2 at 20-MHz firing rate) necessary to scale to systems with enormous entropy. Estimates comparing the proposed hardware platform to a human brain show that with the same number of neurons (1 011) and 700 independent connections per neuron, the hardware presented here may achieve an order of magnitude improvement in synaptic events per second per watt.

Dynamic Recrystallization Model for Whisker and Hillock Growth

DOE Office of Scientific and Technical Information (OSTI.GOV)

Vianco, Paul T.; Neilsen, Michael K.

2015-07-01

Tin (Sn) whiskers are not a recent development. Studies in the late 1930’s investigated thin filaments that grew spontaneously from Sn coatings used for the corrosion protection of electronic hardware. It was soon recognized that these Sn filaments,or whiskers, could create short circuits in the same electronic equipment. Figure 1a illustrates whisker growth in the hole of a printed circuit board having an immersion Sn surface finish. The engineering solution was to contaminate the Sn with > 3wt.% of lead (Pb). The result was that whisker growth was replaced with hillock formation (Fig. 1b) that posed a minimal reliability concerntomore » electrical circuits. Today, Pb-containing finishes are being replaced with pure Sn coatings to meet environmental restrictions on Pb use. The same short-circuit concerns have been raised, once again, with respect to Sn whiskers. The present authors have taken the approach that, in order to develop more widely applicable, first-principles strategies to mitigate Sn whisker formation, it is necessary to understand the fundamental mechanism(s) and rate kinetics underlying their development. Numerous mechanisms have been proposed by other authors to describe whisker growth, including static recrystallization by Boguslavsky and Bush.« less

A procedural method for the efficient implementation of full-custom VLSI designs

NASA Technical Reports Server (NTRS)

Belk, P.; Hickey, N.

1987-01-01

An imbedded language system for the layout of very large scale integration (VLSI) circuits is examined. It is shown that through the judicious use of this system, a large variety of circuits can be designed with circuit density and performance comparable to traditional full-custom design methods, but with design costs more comparable to semi-custom design methods. The high performance of this methodology is attributable to the flexibility of procedural descriptions of VLSI layouts and to a number of automatic and semi-automatic tools within the system.

Component-Level Electronic-Assembly Repair (CLEAR) Synthetic Instrument Capabilities Assessment and Test Report

NASA Technical Reports Server (NTRS)

Oeftering, Richard C.; Bradish, Martin A.

2011-01-01

The role of synthetic instruments (SIs) for Component-Level Electronic-Assembly Repair (CLEAR) is to provide an external lower-level diagnostic and functional test capability beyond the built-in-test capabilities of spacecraft electronics. Built-in diagnostics can report faults and symptoms, but isolating the root cause and performing corrective action requires specialized instruments. Often a fault can be revealed by emulating the operation of external hardware. This implies complex hardware that is too massive to be accommodated in spacecraft. The SI strategy is aimed at minimizing complexity and mass by employing highly reconfigurable instruments that perform diagnostics and emulate external functions. In effect, SI can synthesize an instrument on demand. The SI architecture section of this document summarizes the result of a recent program diagnostic and test needs assessment based on the International Space Station. The SI architecture addresses operational issues such as minimizing crew time and crew skill level, and the SI data transactions between the crew and supporting ground engineering searching for the root cause and formulating corrective actions. SI technology is described within a teleoperations framework. The remaining sections describe a lab demonstration intended to show that a single SI circuit could synthesize an instrument in hardware and subsequently clear the hardware and synthesize a completely different instrument on demand. An analysis of the capabilities and limitations of commercially available SI hardware and programming tools is included. Future work in SI technology is also described.

STICAP: A linear circuit analysis program with stiff systems capability. Volume 1: Theory manual. [network analysis

NASA Technical Reports Server (NTRS)

Cooke, C. H.

1975-01-01

STICAP (Stiff Circuit Analysis Program) is a FORTRAN 4 computer program written for the CDC-6400-6600 computer series and SCOPE 3.0 operating system. It provides the circuit analyst a tool for automatically computing the transient responses and frequency responses of large linear time invariant networks, both stiff and nonstiff (algorithms and numerical integration techniques are described). The circuit description and user's program input language is engineer-oriented, making simple the task of using the program. Engineering theories underlying STICAP are examined. A user's manual is included which explains user interaction with the program and gives results of typical circuit design applications. Also, the program structure from a systems programmer's viewpoint is depicted and flow charts and other software documentation are given.

Fault detection in digital and analog circuits using an i(DD) temporal analysis technique

NASA Technical Reports Server (NTRS)

Beasley, J.; Magallanes, D.; Vridhagiri, A.; Ramamurthy, Hema; Deyong, Mark

1993-01-01

An i(sub DD) temporal analysis technique which is used to detect defects (faults) and fabrication variations in both digital and analog IC's by pulsing the power supply rails and analyzing the temporal data obtained from the resulting transient rail currents is presented. A simple bias voltage is required for all the inputs, to excite the defects. Data from hardware tests supporting this technique are presented.

Can EDA Combat the Rise of Electronic Counterfeiting?

DTIC Science & Technology

2012-06-01

Categories and Subject Descriptors B .7 [Hardware]: Integrated Circuits General Terms Design, Security Keywords Counterfeiting; Reliability; Device and...1199-1/12/06 ...$10.00. SIA at $7.5 B . Very recently, EE Times estimated that IC counterfeiting losses are as high as $ 169 B annually. There- fore, the...PERSON a. REPORT unclassified b . ABSTRACT unclassified c. THIS PAGE unclassified Standard Form 298 (Rev. 8-98) Prescribed by ANSI Std Z39-18

Defense Healthcare Information Assurance Program

DTIC Science & Technology

1999-11-01

56k Modem • Cisco 1OS 12.0 operation at the MTFs, the Team • Cisco 3640 Router Configuration Fileo 24- 56k Modems recommended the Cisco 3600 series...temporarily substituted by the vendor pending availability of ordered components (e.g., the modem circuit board for the router). " Each site created a...control for software / hardware modifications and upgrades? 3.5 Is there a process for introducing new equipment (such as hosts, printers, or modems

Comparison of Analytical Predictions and Experimental Results for a Dual Brayton Power System (Discussion on Test Hardware and Computer Model for a Dual Brayton System)

NASA Technical Reports Server (NTRS)

Johnson, Paul K.

2007-01-01

NASA Glenn Research Center (GRC) contracted Barber-Nichols, Arvada, CO to construct a dual Brayton power conversion system for use as a hardware proof of concept and to validate results from a computational code known as the Closed Cycle System Simulation (CCSS). Initial checkout tests were performed at Barber- Nichols to ready the system for delivery to GRC. This presentation describes the system hardware components and lists the types of checkout tests performed along with a couple issues encountered while conducting the tests. A description of the CCSS model is also presented. The checkout tests did not focus on generating data, therefore, no test data or model analyses are presented.

Skylab materials processing facility experiment developer's report

NASA Technical Reports Server (NTRS)

Parks, P. G.

1975-01-01

The development of the Skylab M512 Materials Processing Facility is traced from the design of a portable, self-contained electron beam welding system for terrestrial applications to the highly complex experiment system ultimately developed for three Skylab missions. The M512 experiment facility was designed to support six in-space experiments intended to explore the advantages of manufacturing materials in the near-zero-gravity environment of Earth orbit. Detailed descriptions of the M512 facility and related experiment hardware are provided, with discussions of hardware verification and man-machine interfaces included. An analysis of the operation of the facility and experiments during the three Skylab missions is presented, including discussions of the hardware performance, anomalies, and data returned to earth.

Novel structures for Discrete Hartley Transform based on first-order moments

NASA Astrophysics Data System (ADS)

Xiong, Jun; Zheng, Wenjuan; Wang, Hao; Liu, Jianguo

2018-03-01

Discrete Hartley Transform (DHT) is an important tool in digital signal processing. In the present paper, the DHT is firstly transformed into the first-order moments-based form, then a new fast algorithm is proposed to calculate the first-order moments without multiplication. Based on the algorithm theory, the corresponding hardware architecture for DHT is proposed, which only contains shift operations and additions with no need for multipliers and large memory. To verify the availability and effectiveness, the proposed design is implemented with hardware description language and synthesized by Synopsys Design Compiler with 0.18-μm SMIC library. A series of experiments have proved that the proposed architecture has better performance in terms of the product of the hardware consumption and computation time.

Design guidelines for robotically serviceable hardware

NASA Technical Reports Server (NTRS)

Gordon, Scott A.

1988-01-01

Research being conducted at the Goddard Space Flight Center into the development of guidelines for the design of robotically serviceable spaceflight hardware is described. A mock-up was built based on an existing spaceflight system demonstrating how these guidelines can be applied to actual hardware. The report examines the basic servicing philosophy being studied and how this philosophy is reflected in the formulation of design guidelines for robotic servicing. A description of the mock-up is presented with emphasis on the design features that make it robot friendly. Three robotic servicing schemes fulfilling the design guidelines were developed for the mock-up. These servicing schemes are examined as to how their implementation was affected by the constraints of the spacecraft system on which the mock-up is based.

Apollo experience report: Television system

NASA Technical Reports Server (NTRS)

Coan, P. P.

1973-01-01

The progress of the Apollo television systems from the early definition of requirements through the development and inflight use of color television hardware is presented. Television systems that have been used during the Apollo Program are discussed, beginning with a description of the specifications for each system. The document describes the technical approach taken for the development of each system and discusses the prototype and engineering hardware built to test the system itself and to perform the testing to verify compatibility with the spacecraft systems. Problems that occurred during the design and development phase are described. Finally, the flight hardware, operational characteristics, and performance during several Apollo missions are described, and specific recommendations for the remaining Apollo flights and future space missions are made.

Hardware implementation of fuzzy Petri net as a controller.

PubMed

Gniewek, Lesław; Kluska, Jacek

2004-06-01

The paper presents a new approach to fuzzy Petri net (FPN) and its hardware implementation. The authors' motivation is as follows. Complex industrial processes can be often decomposed into many parallelly working subprocesses, which can, in turn, be modeled using Petri nets. If all the process variables (or events) are assumed to be two-valued signals, then it is possible to obtain a hardware or software control device, which works according to the algorithm described by conventional Petri net. However, the values of real signals are contained in some bounded interval and can be interpreted as events which are not only true or false, but rather true in some degree from the interval [0, 1]. Such a natural interpretation from multivalued logic (fuzzy logic) point of view, concerns sensor outputs, control signals, time expiration, etc. It leads to the idea of FPN as a controller, which one can rather simply obtain, and which would be able to process both analog, and binary signals. In the paper both graphical, and algebraic representations of the proposed FPN are given. The conditions under which transitions can be fired are described. The algebraic description of the net and a theorem which enables computation of new marking in the net, based on current marking, are formulated. Hardware implementation of the FPN, which uses fuzzy JK flip-flops and fuzzy gates, are proposed. An example illustrating usefulness of the proposed FPN for control algorithm description and its synthesis as a controller device for the concrete production process are presented.

A preferential design approach for energy-efficient and robust implantable neural signal processing hardware.

PubMed

Narasimhan, Seetharam; Chiel, Hillel J; Bhunia, Swarup

2009-01-01

For implantable neural interface applications, it is important to compress data and analyze spike patterns across multiple channels in real time. Such a computational task for online neural data processing requires an innovative circuit-architecture level design approach for low-power, robust and area-efficient hardware implementation. Conventional microprocessor or Digital Signal Processing (DSP) chips would dissipate too much power and are too large in size for an implantable system. In this paper, we propose a novel hardware design approach, referred to as "Preferential Design" that exploits the nature of the neural signal processing algorithm to achieve a low-voltage, robust and area-efficient implementation using nanoscale process technology. The basic idea is to isolate the critical components with respect to system performance and design them more conservatively compared to the noncritical ones. This allows aggressive voltage scaling for low power operation while ensuring robustness and area efficiency. We have applied the proposed approach to a neural signal processing algorithm using the Discrete Wavelet Transform (DWT) and observed significant improvement in power and robustness over conventional design.

An AES chip with DPA resistance using hardware-based random order execution

NASA Astrophysics Data System (ADS)

Bo, Yu; Xiangyu, Li; Cong, Chen; Yihe, Sun; Liji, Wu; Xiangmin, Zhang

2012-06-01

This paper presents an AES (advanced encryption standard) chip that combats differential power analysis (DPA) side-channel attack through hardware-based random order execution. Both decryption and encryption procedures of an AES are implemented on the chip. A fine-grained dataflow architecture is proposed, which dynamically exploits intrinsic byte-level independence in the algorithm. A novel circuit called an HMF (Hold-Match-Fetch) unit is proposed for random control, which randomly sets execution orders for concurrent operations. The AES chip was manufactured in SMIC 0.18 μm technology. The average energy for encrypting one group of plain texts (128 bits secrete keys) is 19 nJ. The core area is 0.43 mm2. A sophisticated experimental setup was built to test the DPA resistance. Measurement-based experimental results show that one byte of a secret key cannot be disclosed from our chip under random mode after 64000 power traces were used in the DPA attack. Compared with the corresponding fixed order execution, the hardware based random order execution is improved by at least 21 times the DPA resistance.

A research of a high precision multichannel data acquisition system

NASA Astrophysics Data System (ADS)

Zhong, Ling-na; Tang, Xiao-ping; Yan, Wei

2013-08-01

The output signals of the focusing system in lithography are analog. To convert the analog signals into digital ones which are more flexible and stable to process, a desirable data acquisition system is required. The resolution of data acquisition, to some extent, affects the accuracy of focusing. In this article, we first compared performance between the various kinds of analog-to-digital converters (ADC) available on the market at the moment. Combined with the specific requirements (sampling frequency, converting accuracy, numbers of channels etc) and the characteristics (polarization, amplitude range etc) of the analog signals, the model of the ADC to be used as the core chip in our hardware design was determined. On this basis, we chose other chips needed in the hardware circuit that would well match with ADC, then the overall hardware design was obtained. Validation of our data acquisition system was verified through experiments and it can be demonstrated that the system can effectively realize the high resolution conversion of the multi-channel analog signals and give the accurate focusing information in lithography.

Standard cell-based implementation of a digital optoelectronic neural-network hardware.

PubMed

Maier, K D; Beckstein, C; Blickhan, R; Erhard, W

2001-03-10

A standard cell-based implementation of a digital optoelectronic neural-network architecture is presented. The overall structure of the multilayer perceptron network that was used, the optoelectronic interconnection system between the layers, and all components required in each layer are defined. The design process from VHDL-based modeling from synthesis and partly automatic placing and routing to the final editing of one layer of the circuit of the multilayer perceptrons are described. A suitable approach for the standard cell-based design of optoelectronic systems is presented, and shortcomings of the design tool that was used are pointed out. The layout for the microelectronic circuit of one layer in a multilayer perceptron neural network with a performance potential 1 magnitude higher than neural networks that are purely electronic based has been successfully designed.

Digital coincidence counting

NASA Astrophysics Data System (ADS)

Buckman, S. M.; Ius, D.

1996-02-01

This paper reports on the development of a digital coincidence-counting system which comprises a custom-built data acquisition card and associated PC software. The system has been designed to digitise the pulse-trains from two radiation detectors at a rate of 20 MSamples/s with 12-bit resolution. Through hardware compression of the data, the system can continuously record both individual pulse-shapes and the time intervals between pulses. Software-based circuits are used to process the stored pulse trains. These circuits are constructed simply by linking together icons representing various components such as coincidence mixers, time delays, single-channel analysers, deadtimes and scalers. This system enables a pair of pulse trains to be processed repeatedly using any number of different methods. Some preliminary results are presented in order to demonstrate the versatility and efficiency of this new method.

FPGA Implementation of Generalized Hebbian Algorithm for Texture Classification

PubMed Central

Lin, Shiow-Jyu; Hwang, Wen-Jyi; Lee, Wei-Hao

2012-01-01

This paper presents a novel hardware architecture for principal component analysis. The architecture is based on the Generalized Hebbian Algorithm (GHA) because of its simplicity and effectiveness. The architecture is separated into three portions: the weight vector updating unit, the principal computation unit and the memory unit. In the weight vector updating unit, the computation of different synaptic weight vectors shares the same circuit for reducing the area costs. To show the effectiveness of the circuit, a texture classification system based on the proposed architecture is physically implemented by Field Programmable Gate Array (FPGA). It is embedded in a System-On-Programmable-Chip (SOPC) platform for performance measurement. Experimental results show that the proposed architecture is an efficient design for attaining both high speed performance and low area costs. PMID:22778640

Vectorized program architectures for supercomputer-aided circuit design

DOE Office of Scientific and Technical Information (OSTI.GOV)

Rizzoli, V.; Ferlito, M.; Neri, A.

1986-01-01

Vector processors (supercomputers) can be effectively employed in MIC or MMIC applications to solve problems of large numerical size such as broad-band nonlinear design or statistical design (yield optimization). In order to fully exploit the capabilities of a vector hardware, any program architecture must be structured accordingly. This paper presents a possible approach to the ''semantic'' vectorization of microwave circuit design software. Speed-up factors of the order of 50 can be obtained on a typical vector processor (Cray X-MP), with respect to the most powerful scaler computers (CDC 7600), with cost reductions of more than one order of magnitude. Thismore » could broaden the horizon of microwave CAD techniques to include problems that are practically out of the reach of conventional systems.« less

An approach for fixed coefficient RNS-based FIR filter

NASA Astrophysics Data System (ADS)

Srinivasa Reddy, Kotha; Sahoo, Subhendu Kumar

2017-08-01

In this work, an efficient new modular multiplication method for {2k-1, 2k, 2k+1-1} moduli set is proposed to implement a residue number system (RNS)-based fixed coefficient finite impulse response filter. The new multiplication approach reduces the number of partial products by using pre-loaded product block. The reduction in partial products with the proposed modular multiplication improves the clock frequency and reduces the area and power as compared with the conventional modular multiplication. Further, the present approach eliminates a binary number to residue number converter circuit, which is usually needed at the front end of RNS-based system. In this work, two fixed coefficient filter architectures with the new modular multiplication approach are proposed. The filters are implemented using Verilog hardware description language. The United Microelectronics Corporation 90 nm technology library has been used for synthesis and the results area, power and delay are obtained with the help of Cadence register transfer level compiler. The power delay product (PDP) is also considered for performance comparison among the proposed filters. One of the proposed architecture is found to improve PDP gain by 60.83% as compared with the filter implemented with conventional modular multiplier. The filters functionality is validated with the help of Altera DSP Builder.

Computer Series, 17: Bits and Pieces, 5.

ERIC Educational Resources Information Center

Moore, John W., Ed.

1981-01-01

Contains short descriptions of computer programs or hardware that simulate laboratory instruments or results of kinetics experiments, including ones that include experiment error, numerical simulation, first-order kinetic mechanisms, a game for decisionmaking, and simulated mass spectrophotometers. (CS)

SeaBIRD: A Flexible and Intuitive Planetary Datamining Infrastructure

NASA Astrophysics Data System (ADS)

Politi, R.; Capaccioni, F.; Giardino, M.; Fonte, S.; Capria, M. T.; Turrini, D.; De Sanctis, M. C.; Piccioni, G.

2018-04-01

Description of SeaBIRD (Searchable and Browsable Infrastructure for Repository of Data), a software and hardware infrastructure for multi-mission planetary datamining, with web-based GUI and API set for the integration in users' software.

International Space Station (ISS) Carbon Dioxide Removal Assembly (CDRA) Desiccant/Adsorbent Bed (DAB) Orbital Replacement Unit (ORU) Redesign

NASA Technical Reports Server (NTRS)

Reysa, Richard P.; Lumpkin, John P.; Sherif, Dian El; Kay, Robert; Williams, David E.

2007-01-01

The Carbon Dioxide Removal Assembly (CDRA) is a part of the International Space Station (ISS) Environmental Control and Life Support (ECLS) system. The CDRA provides carbon dioxide (CO2) removal from the ISS on-orbit modules. Currently, the CDRA is the secondary removal system on the ISS, with the primary system being the Russian Vozdukh. Within the CDRA are two desiccant/adsorbent beds (DAB), which perform the carbon dioxide removal function. The DAB adsorbent containment approach required improvements with respect to adsorbent containment. These improvements were implemented through a redesign program and have been implemented on units returning from orbit. This paper presents a DAB design modification implementation description, a hardware performance comparison between the unmodified and modified DAB configurations, and a description of the modified DAB hardware implementation into the on-orbit CDRA.

SIRU utilization. Volume 2: Software description and program documentation

NASA Technical Reports Server (NTRS)

Oehrle, J.; Whittredge, R.

1973-01-01

A complete description of the additional analysis, development and evaluation provided for the SIRU system as identified in the requirements for the SIRU utilization program is presented. The SIRU configuration is a modular inertial subsystem with hardware and software features that achieve fault tolerant operational capabilities. The SIRU redundant hardware design is formulated about a six gyro and six accelerometer instrument module package. The modules are mounted in this package so that their measurement input axes form a unique symmetrical pattern that corresponds to the array of perpendiculars to the faces of a regular dodecahedron. This six axes array provides redundant independent sensing and the symmetry enables the formulation of an optimal software redundant data processing structure with self-contained fault detection and isolation (FDI) capabilities. Documentation of the additional software and software modifications required to implement the utilization capabilities includes assembly listings and flow charts

Space Station CMIF extended duration metabolic control test

NASA Technical Reports Server (NTRS)

Schunk, Richard G.; Bagdigian, Robert M.; Carrasquillo, Robyn L.; Ogle, Kathryn Y.; Wieland, Paul O.

1989-01-01

The Space Station Extended Duration Metabolic Control Test (EMCT) was conducted at the MSFC Core Module Integration Facility. The primary objective of the EMCT was to gather performance data from a partially-closed regenerative Environmental Control and Life Support (ECLS) system functioning under steady-state conditions. Included is a description of the EMCT configuration, a summary of events, a discussion of anomalies that occurred during the test, and detailed results and analysis from individual measurements of water and gas samples taken during the test. A comparison of the physical, chemical, and microbiological methods used in the post test laboratory analyses of the water samples is included. The preprototype ECLS hardware used in the test, providing an overall process description and theory of operation for each hardware item. Analytical results pertaining to a system level mass balance and selected system power estimates are also included.

Real-time skin feature identification in a time-sequential video stream

NASA Astrophysics Data System (ADS)

Kramberger, Iztok

2005-04-01

Skin color can be an important feature when tracking skin-colored objects. Particularly this is the case for computer-vision-based human-computer interfaces (HCI). Humans have a highly developed feeling of space and, therefore, it is reasonable to support this within intelligent HCI, where the importance of augmented reality can be foreseen. Joining human-like interaction techniques within multimodal HCI could, or will, gain a feature for modern mobile telecommunication devices. On the other hand, real-time processing plays an important role in achieving more natural and physically intuitive ways of human-machine interaction. The main scope of this work is the development of a stereoscopic computer-vision hardware-accelerated framework for real-time skin feature identification in the sense of a single-pass image segmentation process. The hardware-accelerated preprocessing stage is presented with the purpose of color and spatial filtering, where the skin color model within the hue-saturation-value (HSV) color space is given with a polyhedron of threshold values representing the basis of the filter model. An adaptive filter management unit is suggested to achieve better segmentation results. This enables the adoption of filter parameters to the current scene conditions in an adaptive way. Implementation of the suggested hardware structure is given at the level of filed programmable system level integrated circuit (FPSLIC) devices using an embedded microcontroller as their main feature. A stereoscopic clue is achieved using a time-sequential video stream, but this shows no difference for real-time processing requirements in terms of hardware complexity. The experimental results for the hardware-accelerated preprocessing stage are given by efficiency estimation of the presented hardware structure using a simple motion-detection algorithm based on a binary function.

An adaptable neuromorphic model of orientation selectivity based on floating gate dynamics

PubMed Central

Gupta, Priti; Markan, C. M.

2014-01-01

The biggest challenge that the neuromorphic community faces today is to build systems that can be considered truly cognitive. Adaptation and self-organization are the two basic principles that underlie any cognitive function that the brain performs. If we can replicate this behavior in hardware, we move a step closer to our goal of having cognitive neuromorphic systems. Adaptive feature selectivity is a mechanism by which nature optimizes resources so as to have greater acuity for more abundant features. Developing neuromorphic feature maps can help design generic machines that can emulate this adaptive behavior. Most neuromorphic models that have attempted to build self-organizing systems, follow the approach of modeling abstract theoretical frameworks in hardware. While this is good from a modeling and analysis perspective, it may not lead to the most efficient hardware. On the other hand, exploiting hardware dynamics to build adaptive systems rather than forcing the hardware to behave like mathematical equations, seems to be a more robust methodology when it comes to developing actual hardware for real world applications. In this paper we use a novel time-staggered Winner Take All circuit, that exploits the adaptation dynamics of floating gate transistors, to model an adaptive cortical cell that demonstrates Orientation Selectivity, a well-known biological phenomenon observed in the visual cortex. The cell performs competitive learning, refining its weights in response to input patterns resembling different oriented bars, becoming selective to a particular oriented pattern. Different analysis performed on the cell such as orientation tuning, application of abnormal inputs, response to spatial frequency and periodic patterns reveal close similarity between our cell and its biological counterpart. Embedded in a RC grid, these cells interact diffusively exhibiting cluster formation, making way for adaptively building orientation selective maps in silicon. PMID:24765062

High-Speed Isolation Board for Flight Hardware Testing

NASA Technical Reports Server (NTRS)

Yamamoto, Clifford K.; Goodpasture, Richard L.

2011-01-01

There is a need to provide a portable and cost-effective galvanic isolation between ground support equipment and flight hardware such that any unforeseen voltage differential between ground and power supplies is eliminated. An interface board was designed for use between the ground support equipment and the flight hardware that electrically isolates all input and output signals and faithfully reproduces them on each side of the interface. It utilizes highly integrated multi-channel isolating devices to minimize size and reduce assembly time. This single-board solution provides appropriate connector hardware and breakout of required flight signals to individual connectors as needed for various ground support equipment. The board utilizes multi-channel integrated circuits that contain transformer coupling, thereby allowing input and output signals to be isolated from one another while still providing high-fidelity reproduction of the signal up to 90 MHz. The board also takes in a single-voltage power supply input from the ground support equipment and in turn provides a transformer-derived isolated voltage supply to power the portion of the circuitry that is electrically connected to the flight hardware. Prior designs used expensive opto-isolated couplers that were required for each signal to isolate and were time-consuming to assemble. In addition, these earlier designs were bulky and required a 2U rack-mount enclosure. The new design is smaller than a piece of 8.5 11-in. (.22 28-mm) paper and can be easily hand-carried where needed. The flight hardware in question is based on a lineage of existing software-defined radios (SDRs) that utilize a common interface connector with many similar input-output signals present. There are currently four to five variations of this SDR, and more upcoming versions are planned based on the more recent design.

AEA Cell-Bypass-Switch Activation: An Update

NASA Technical Reports Server (NTRS)

Keys, Denney; Rao, Gopalakrishna M.; Wannemacher, Harry

2002-01-01

The objectives of this project included the following: (1) verify the performance of AEA cell bypass protection device (CBPD) under simulated EOS-Aqua/Aura flight hardware configuration; (2) assess the safety of the hardware under an inadvertent firing of CBPD switch, as well as the closing of CBPD; and (3) confirm that the mode of operation of CBPD switch is the formation of a continuous low impedance path (a homogeneous low melting point alloy). The nominal performance of AEA CBPD under flight operating conditions (vacuum except zero-G, and high impedance cell) has been demonstrated. There is no evidence of cell rupture or excessive heat production during or after CBPD switch activation under simulated high cell impedance (open-circuit cell failure mode). The formation of a continuous low impedance path (a homogeneous low melting point alloy) has been confirmed.

Field Programmable Gate Array Failure Rate Estimation Guidelines for Launch Vehicle Fault Tree Models

NASA Technical Reports Server (NTRS)

Al Hassan, Mohammad; Novack, Steven D.; Hatfield, Glen S.; Britton, Paul

2017-01-01

Today's launch vehicles complex electronic and avionic systems heavily utilize the Field Programmable Gate Array (FPGA) integrated circuit (IC). FPGAs are prevalent ICs in communication protocols such as MIL-STD-1553B, and in control signal commands such as in solenoid/servo valves actuations. This paper will demonstrate guidelines to estimate FPGA failure rates for a launch vehicle, the guidelines will account for hardware, firmware, and radiation induced failures. The hardware contribution of the approach accounts for physical failures of the IC, FPGA memory and clock. The firmware portion will provide guidelines on the high level FPGA programming language and ways to account for software/code reliability growth. The radiation portion will provide guidelines on environment susceptibility as well as guidelines on tailoring other launch vehicle programs historical data to a specific launch vehicle.

Radiation Mitigation and Power Optimization Design Tools for Reconfigurable Hardware in Orbit

NASA Technical Reports Server (NTRS)

French, Matthew; Graham, Paul; Wirthlin, Michael; Wang, Li; Larchev, Gregory

2005-01-01

The Reconfigurable Hardware in Orbit (RHinO)project is focused on creating a set of design tools that facilitate and automate design techniques for reconfigurable computing in space, using SRAM-based field-programmable-gate-array (FPGA) technology. In the second year of the project, design tools that leverage an established FPGA design environment have been created to visualize and analyze an FPGA circuit for radiation weaknesses and power inefficiencies. For radiation, a single event Upset (SEU) emulator, persistence analysis tool, and a half-latch removal tool for Xilinx/Virtex-II devices have been created. Research is underway on a persistence mitigation tool and multiple bit upsets (MBU) studies. For power, synthesis level dynamic power visualization and analysis tools have been completed. Power optimization tools are under development and preliminary test results are positive.

STS-57 Pilot Duffy uses TDS soldering tool in SPACEHAB-01 aboard OV-105

NASA Technical Reports Server (NTRS)

1993-01-01

STS-57 Pilot Brian J. Duffy, at a SPACEHAB-01 (Commercial Middeck Augmentation Module (CMAM)) work bench, handles a soldering tool onboard the Earth-orbiting Endeavour, Orbiter Vehicle (OV) 105. Duffy is conducting a soldering experiment (SE) which is part of the Tools and Diagnostic Systems (TDS) project. He is soldering on a printed circuit board, positioned in a specially designed holder, containing 45 connection points and will later de-solder 35 points on a similar board. TDS' sponsor is the Flight Crew Support Division, Space and Life Sciences Directorate, JSC. It represents a group of equipment selected from tools and diagnostic hardware to be supported by the Space Station program. TDS was designed to demonstrate the maintenance of experiment hardware on-orbit and to evaluate the adequacy of its design and the crew interface.

Proceedings of the European Seminar on Industrial Software Engineering (2nd) Held in Freiburg (Germany, F.R.) on 9-10 May 1985,

DTIC Science & Technology

1985-05-10

synchronisation , 8% cache bus monitoring ). 6. Conclusions Since the 1950’s, fault tolerance has been used to improve the reliability of hardware systems ...description. The operation may use other operations supplied with the system , here e.g. HIRE EMPLOYEE, ENTER MGR SAL etc . HIRE MRNAGR (X:PERSOW) nsot ACTOR (X...hardware design and in the operating systems software and they have developed a number of products which are of a commercial standard and of wide

VHDL Simulation of the Implementation of a Costfunction Circuit.

DTIC Science & Technology

1990-09-01

the characteristic delays for each component. At this point in time, it is not necessary for the VHDL code to implement the exact hardware...NAVAL POSTGRADUATE SCHOOL Monterey, California AD-A240 430 ,DSTATv, OTIC"b El FCTE 9% SEP 16 1991 ru m D THESIS VHDL Simulation of the Implementation ...partition algorithm is used here as an example to test the VHDL design methodology. Subroutines or statements in the software can be implemented into

Method and apparatus for detecting timing errors in a system oscillator

DOEpatents

Gliebe, Ronald J.; Kramer, William R.

1993-01-01

A method of detecting timing errors in a system oscillator for an electronic device, such as a power supply, includes the step of comparing a system oscillator signal with a delayed generated signal and generating a signal representative of the timing error when the system oscillator signal is not identical to the delayed signal. An LED indicates to an operator that a timing error has occurred. A hardware circuit implements the above-identified method.

Interfacial Properties of Germanium Nitride Dielectric Layers in Germanium.

DTIC Science & Technology

1986-01-01

operating information are discussed, INTRODUCTION sible way to construct a circuit for adjusting the power out- A type of apparatus being used with...described as an empirical art at best and by the unot considered a good way to modulate the power output usually greater cost of the microwave power...continuously adjusted. A com- input to the cathode dc supply, and miscellaneous hardware. mon method for the modulation of microwave power to a Figure 1

Exer-Genie(Registered Trademark) Exercise Device Hardware Evaluation

NASA Technical Reports Server (NTRS)

Schaffner, Grant; Sharp,Carwyn; Stroud, Leah

2008-01-01

An engineering evaluation was performed on the ExerGenie(r) exercise device to quantify its capabilities and limitations to address questions from the Constellation Program. Three subjects performed rowing and circuit training sessions to assess the suitability of the device for aerobic exercise. Three subjects performed a resistive exercise session to assess the suitability of the device for resistive exercise. Since 1 subject performed both aerobic and resistive exercise sessions, a total of 5 subjects participated.

Analog hardware implementation of neocognitron networks

NASA Astrophysics Data System (ADS)

Inigo, Rafael M.; Bonde, Allen, Jr.; Holcombe, Bradford

1990-08-01

This paper deals with the analog implementation of neocognitron based neural networks. All of Fukushima''s and related work on the neocognitron is based on digital computer simulations. To fully take advantage of the power of this network paradigm an analog electronic approach is proposed. We first implemented a 6-by-6 sensor network with discrete analog components and fixed weights. The network was given weight values to recognize the characters U L and F. These characters are recognized regardless of their location on the sensor and with various levels of distortion and noise. The network performance has also shown an excellent correlation with software simulation results. Next we implemented a variable weight network which can be trained to recognize simple patterns by means of self-organization. The adaptable weights were implemented with PETs configured as voltage-controlled resistors. To implement a variable weight there must be some type of " memory" to store the weight value and hold it while the value is reinforced or incremented. Two methods were evaluated: an analog sample-hold circuit and a digital storage scheme using binary counters. The latter is preferable for VLSI implementation because it uses standard components and does not require the use of capacitors. The analog design and implementation of these small-scale networks demonstrates the feasibility of implementing more complicated ANNs in electronic hardware. The circuits developed can also be designed for VLSI implementation. 1.

MRI and (31)P magnetic resonance spectroscopy hardware for axillary lymph node investigation at 7T.

PubMed

Rivera, Debra S; Wijnen, Jannie P; van der Kemp, Wybe J M; Raaijmakers, Alexander J; Luijten, Peter R; Klomp, Dennis W J

2015-05-01

Neoadjuvant treatment response in lymph nodes predicts patient outcome, but existing methods do not track response during therapy accurately. In this study, specialized hardware was used to adapt high-field (7T) (31) P magnetic resonance spectroscopy (MRS), which has been shown to track treatment response in small breast tumors, to monitor axillary lymph nodes. A dual-tuned quadrature coil that is a (31) P (120 MHz) transceiver and a (1) H (300 MHz) receiver was designed using a novel detune circuit. The transceiver/receiver coil in the axilla is used with a fractionated dipole antenna on the back of the subject and the conventional breast coil for transmit. The novel circuit detuned the (1) H resonance without disturbing the (31) P resonance. In vivo demonstrations included: >80% homogeneous B1 (+) for (1) H over the axilla, identification of a small (3-mm diameter) lymph node, and (31) P MR spectra from a single healthy lymph node. The setup can detect <2 millimolar concentrations of metabolites from a 2-mL voxel. The first (31) P MR spectrum from an in vivo lymph node indicates that the presented design may be sufficiently sensitive to detect metabolic response to neoadjuvant therapy. Multinuclei MRS of the lymph nodes at 7T is possible through combining lightweight antenna elements with dual-tuned transceiver/receive-only coils. © 2014 Wiley Periodicals, Inc.