Functional role for suppression of the insular-striatal circuit in modulating interoceptive effects of alcohol.

PubMed

Jaramillo, Anel A; Agan, Verda E; Makhijani, Viren H; Pedroza, Stephen; McElligott, Zoe A; Besheer, Joyce

2017-09-27

The insular cortex (IC) is a region proposed to modulate, in part, interoceptive states and motivated behavior. Interestingly, IC dysfunction and deficits in interoceptive processing are often found among individuals with substance-use disorders. Furthermore, the IC projects to the nucleus accumbens core (AcbC), a region known to modulate the discriminative stimulus/interoceptive effects of alcohol and other drug-related behaviors. Therefore, the goal of the present work was to investigate the possible role of the IC ➔ AcbC circuit in modulating the interoceptive effects of alcohol. Thus, we utilized a chemogenetic technique (hM4D i designer receptor activation by designer drugs) to silence neuronal activity in the IC of rats trained to discriminate alcohol (1 g/kg, IG) versus water using an operant or Pavlovian alcohol discrimination procedure. Chemogenetic silencing of the IC or IC ➔ AcbC neuronal projections resulted in potentiated sensitivity to the interoceptive effects of alcohol in both the operant and Pavlovian tasks. Together, these data provide critical evidence for the nature of the complex IC circuitry and, specifically, suppression of the insular-striatal circuit in modulating behavior under a drug stimulus control. © 2017 Society for the Study of Addiction.

Behavioral modeling of VCSELs for high-speed optical interconnects

NASA Astrophysics Data System (ADS)

Szczerba, Krzysztof; Kocot, Chris

2018-02-01

Transition from on-off keying to 4-level pulse amplitude modulation (PAM) in VCSEL based optical interconnects allows for an increase of data rates, at the cost of 4.8 dB sensitivity penalty. The resulting strained link budget creates a need for accurate VCSEL models for driver integrated circuit (IC) design and system level simulations. Rate equation based equivalent circuit models are convenient for the IC design, but system level analysis requires computationally efficient closed form behavioral models based Volterra series and neural networks. In this paper we present and compare these models.

First-Order SPICE Modeling of Extreme-Temperature 4H-SiC JFET Integrated Circuits

NASA Technical Reports Server (NTRS)

Neudeck, Philip G.; Spry, David J.; Chen, Liang-Yu

2016-01-01

A separate submission to this conference reports that 4H-SiC Junction Field Effect Transistor (JFET) digital and analog Integrated Circuits (ICs) with two levels of metal interconnect have reproducibly demonstrated electrical operation at 500 C in excess of 1000 hours. While this progress expands the complexity and durability envelope of high temperature ICs, one important area for further technology maturation is the development of reasonably accurate and accessible computer-aided modeling and simulation tools for circuit design of these ICs. Towards this end, we report on development and verification of 25 C to 500 C SPICE simulation models of first order accuracy for this extreme-temperature durable 4H-SiC JFET IC technology. For maximum availability, the JFET IC modeling is implemented using the baseline-version SPICE NMOS LEVEL 1 model that is common to other variations of SPICE software and importantly includes the body-bias effect. The first-order accuracy of these device models is verified by direct comparison with measured experimental device characteristics.

Area efficient layout design of CMOS circuit for high-density ICs

NASA Astrophysics Data System (ADS)

Mishra, Vimal Kumar; Chauhan, R. K.

2018-01-01

Efficient layouts have been an active area of research to accommodate the greater number of devices fabricated on a given chip area. In this work a new layout of CMOS circuit is proposed, with an aim to improve its electrical performance and reduce the chip area consumed. The study shows that the design of CMOS circuit and SRAM cells comprising tapered body reduced source fully depleted silicon on insulator (TBRS FD-SOI)-based n- and p-type MOS devices. The proposed TBRS FD-SOI n- and p-MOSFET exhibits lower sub-threshold slope and higher Ion to Ioff ratio when compared with FD-SOI MOSFET and FinFET technology. Other parameters like power dissipation, delay time and signal-to-noise margin of CMOS inverter circuits show improvement when compared with available inverter designs. The above device design is used in 6-T SRAM cell so as to see the effect of proposed layout on high density integrated circuits (ICs). The SNM obtained from the proposed SRAM cell is 565 mV which is much better than any other SRAM cell designed at 50 nm gate length MOS device. The Sentaurus TCAD device simulator is used to design the proposed MOS structure.

An Integrated-Circuit Temperature Sensor for Calorimetry and Differential Temperature Measurement

NASA Astrophysics Data System (ADS)

Muyskens, Mark

1997-07-01

Our application of an integrated-circuit (IC) temperature sensor which is easy-to-use, inexpensive, rugged, easily computer-interfacable and has good precision is described. The design, based on the National Semiconductor LM35 IC chip, avoids some of the difficulties associated with conventional sensors (thermocouples, thermistors, and platinum resistance thermometers) and a previously described IC sensor. The sensor can be used with a variety of data-acquisition systems. Applications range from general chemistry to physical chemistry, particularly where computer interfaced, digital temperature measurement is desired. Included is a detailed description of our current design with suggestions for improvement and a performance evaluation of the precision in differential measurement and the time constant for responding to temperature change.

Using Tablet PCs and Interactive Software in IC Design Courses to Improve Learning

ERIC Educational Resources Information Center

Simoni, M.

2011-01-01

This paper describes an initial study of using tablet PCs and interactive course software in integrated circuit (IC) design courses. A rapidly growing community is demonstrating how this technology can improve learning and retention of material by facilitating interaction between faculty and students via cognitive exercises during lectures. While…

Assessment of Durable SiC JFET Technology for +600 C to -125 C Integrated Circuit Operation

NASA Technical Reports Server (NTRS)

Neudeck, P. G.; Krasowski, M. J.; Prokop, N. F.

2011-01-01

Electrical characteristics and circuit design considerations for prototype 6H-SiC JFET integrated circuits (ICs) operating over the broad temperature range of -125 C to +600 C are described. Strategic implementation of circuits with transistors and resistors in the same 6H-SiC n-channel layer enabled ICs with nearly temperature-independent functionality to be achieved. The frequency performance of the circuits declined at temperatures increasingly below or above room temperature, roughly corresponding to the change in 6H-SiC n-channel resistance arising from incomplete carrier ionization at low temperature and decreased electron mobility at high temperature. In addition to very broad temperature functionality, these simple digital and analog demonstration integrated circuits successfully operated with little change in functional characteristics over the course of thousands of hours at 500 C before experiencing interconnect-related failures. With appropriate further development, these initial results establish a new technology foundation for realizing durable 500 C ICs for combustion engine sensing and control, deep-well drilling, and other harsh-environment applications.

Automated Design Tools for Integrated Mixed-Signal Microsystems (NeoCAD)

DTIC Science & Technology

2005-02-01

method, Model Order Reduction (MOR) tools, system-level, mixed-signal circuit synthesis and optimization tools, and parsitic extraction tools. A unique...Mission Area: Command and Control mixed signal circuit simulation parasitic extraction time-domain simulation IC design flow model order reduction... Extraction 1.2 Overall Program Milestones CHAPTER 2 FAST TIME DOMAIN MIXED-SIGNAL CIRCUIT SIMULATION 2.1 HAARSPICE Algorithms 2.1.1 Mathematical Background

Thermally-induced voltage alteration for integrated circuit analysis

DOEpatents

Cole, Jr., Edward I.

2000-01-01

A thermally-induced voltage alteration (TIVA) apparatus and method are disclosed for analyzing an integrated circuit (IC) either from a device side of the IC or through the IC substrate to locate any open-circuit or short-circuit defects therein. The TIVA apparatus uses constant-current biasing of the IC while scanning a focused laser beam over electrical conductors (i.e. a patterned metallization) in the IC to produce localized heating of the conductors. This localized heating produces a thermoelectric potential due to the Seebeck effect in any conductors with open-circuit defects and a resistance change in any conductors with short-circuit defects, both of which alter the power demand by the IC and thereby change the voltage of a source or power supply providing the constant-current biasing. By measuring the change in the supply voltage and the position of the focused and scanned laser beam over time, any open-circuit or short-circuit defects in the IC can be located and imaged. The TIVA apparatus can be formed in part from a scanning optical microscope, and has applications for qualification testing or failure analysis of ICs.

An Integrated-Circuit Temperature Sensor for Calorimetry and Differential Temperature Measurement.

ERIC Educational Resources Information Center

Muyskens, Mark A.

1997-01-01

Describes the application of an integrated-circuit (IC) chip which provides an easy-to-use, inexpensive, rugged, computer-interfaceable temperature sensor for calorimetry and differential temperature measurement. Discusses its design and advantages. (JRH)

Integrated circuit failure analysis by low-energy charge-induced voltage alteration

DOEpatents

Cole, E.I. Jr.

1996-06-04

A scanning electron microscope apparatus and method are described for detecting and imaging open-circuit defects in an integrated circuit (IC). The invention uses a low-energy high-current focused electron beam that is scanned over a device surface of the IC to generate a charge-induced voltage alteration (CIVA) signal at the location of any open-circuit defects. The low-energy CIVA signal may be used to generate an image of the IC showing the location of any open-circuit defects. A low electron beam energy is used to prevent electrical breakdown in any passivation layers in the IC and to minimize radiation damage to the IC. The invention has uses for IC failure analysis, for production-line inspection of ICs, and for qualification of ICs. 5 figs.

Integrated circuit failure analysis by low-energy charge-induced voltage alteration

DOEpatents

Cole, Jr., Edward I.

1996-01-01

A scanning electron microscope apparatus and method are described for detecting and imaging open-circuit defects in an integrated circuit (IC). The invention uses a low-energy high-current focused electron beam that is scanned over a device surface of the IC to generate a charge-induced voltage alteration (CIVA) signal at the location of any open-circuit defects. The low-energy CIVA signal may be used to generate an image of the IC showing the location of any open-circuit defects. A low electron beam energy is used to prevent electrical breakdown in any passivation layers in the IC and to minimize radiation damage to the IC. The invention has uses for IC failure analysis, for production-line inspection of ICs, and for qualification of ICs.

Prototyping and implementing flight qualifiable semicustom CMOS P-well bulk integrated circuits in the JPL environment

NASA Technical Reports Server (NTRS)

Olson, E. M.

1986-01-01

Presently, there are many difficulties associated with implementing application specific custom or semi-custom (standard cell based) integrated circuits (ICs) into JPL flight projects. One of the primary difficulties is developing prototype semi-custom integrated circuits for use and evaluation in engineering prototype flight hardware. The prototype semi-custom ICs must be extremely cost-effective and yet still representative of flight qualifiable versions of the design. A second difficulty is encountered in the transport of the design from engineering prototype quality to flight quality. Normally, flight quality integrated circuits have stringent quality standards, must be radiation resistant and should consume minimal power. It is often not necessary or cost effective, however, to impose such stringent quality standards on engineering models developed for systems analysis in controlled lab environments. This article presents work originally initiated for ground based applications that also addresses these two problems. Furthermore, this article suggests a method that has been shown successful in prototyping flight quality semi-custom ICs through the Metal Oxide Semiconductor Implementation Service (MOSIS) program run by the University of Southern California's Information Sciences Institute. The method has been used successfully to design and fabricate through the MOSIS three different semi-custom prototype CMOS p-well chips. The three designs make use of the work presented and were designed consistent with design techniques and structures that are flight qualifiable, allowing one hour transfer of the design from engineering model status to flight qualifiable foundry-ready status through methods outlined in this article.

The Design and Assessment of a Hypermedia Course on Semiconductor Manufacturing.

ERIC Educational Resources Information Center

Schank, Patrick K.; Rowe, Lawrence A.

1993-01-01

Describes the design and evaluation of a multimedia course on integrated circuit manufacturing that was developed at the University of California at Berkeley using IC-HIP (Integrated Circuit-Hypermedia in PICASSO), a hypermedia-based instructional system. Learning effects based on prior knowledge, methods of navigation, and other factors are…

Commercialisation of CMOS integrated circuit technology in multi-electrode arrays for neuroscience and cell-based biosensors.

PubMed

Graham, Anthony H D; Robbins, Jon; Bowen, Chris R; Taylor, John

2011-01-01

The adaptation of standard integrated circuit (IC) technology as a transducer in cell-based biosensors in drug discovery pharmacology, neural interface systems and electrophysiology requires electrodes that are electrochemically stable, biocompatible and affordable. Unfortunately, the ubiquitous Complementary Metal Oxide Semiconductor (CMOS) IC technology does not meet the first of these requirements. For devices intended only for research, modification of CMOS by post-processing using cleanroom facilities has been achieved. However, to enable adoption of CMOS as a basis for commercial biosensors, the economies of scale of CMOS fabrication must be maintained by using only low-cost post-processing techniques. This review highlights the methodologies employed in cell-based biosensor design where CMOS-based integrated circuits (ICs) form an integral part of the transducer system. Particular emphasis will be placed on the application of multi-electrode arrays for in vitro neuroscience applications. Identifying suitable IC packaging methods presents further significant challenges when considering specific applications. The various challenges and difficulties are reviewed and some potential solutions are presented.

Laboratory experiments in integrated circuit fabrication

NASA Technical Reports Server (NTRS)

Jenkins, Thomas J.; Kolesar, Edward S.

1993-01-01

The objectives of the experiment are fourfold: to provide practical experience implementing the fundamental processes and technology associated with the science and art of integrated circuit (IC) fabrication; to afford the opportunity for the student to apply the theory associated with IC fabrication and semiconductor device operation; to motivate the student to exercise engineering decisions associated with fabricating integrated circuits; and to complement the theory of n-channel MOS and diffused devices that are presented in the classroom by actually fabricating and testing them. Therefore, a balance between theory and practice can be realized in the education of young engineers, whose education is often criticized as lacking sufficient design and practical content.

[An integral chip for the multiphase pulse-duration modulation used for voltage changer in biomedical microprocessor systems].

PubMed

Balashov, A M; Selishchev, S V

2004-01-01

An integral chip (IC) was designed for controlling the step-down pulse voltage converter, which is based on the multiphase pulse-duration modulation, for use in biomedical microprocessor systems. The CMOS technology was an optimal basis for the IC designing. An additional feedback circuit diminishes the output voltage dispersion at dynamically changing loads.

Hardening Logic Encryption against Key Extraction Attacks with Circuit Camouflage

DTIC Science & Technology

2017-03-01

camouflage; obfuscation; SAT; key extraction; reverse engineering; security; trusted electronics Introduction Integrated Circuit (IC) designs are...Encryption Algorithms”, Hardware Oriented Security and Trust , 2015. 3. Rajendran J., Pino, Y., Sinanoglu, O., Karri, R., “Security Analysis of Logic

Single Circuit Board Implementation of a Digitally Compensated SAW Oscillator (DCSO).

DTIC Science & Technology

1983-12-01

Through this project a design for a Digitally Compensated SAW Oscillator (DCSO) was developed and implemented on a single circuit board. The AFIT IC, which...is the heart of the design , did not function properly. Therefore, my work was halted after testing several of the subcircuits and assembling the...o.... -7 Standards ........ o..o....... -8 Approach-9 Sequence of Presentation .................. -10 II, Design

Computer aided design of monolithic microwave and millimeter wave integrated circuits and subsystems

NASA Astrophysics Data System (ADS)

Ku, Walter H.

1989-05-01

The objectives of this research are to develop analytical and computer aided design techniques for monolithic microwave and millimeter wave integrated circuits (MMIC and MIMIC) and subsystems and to design and fabricate those ICs. Emphasis was placed on heterojunction-based devices, especially the High Electron Mobility Transition (HEMT), for both low noise and medium power microwave and millimeter wave applications. Circuits to be considered include monolithic low noise amplifiers, power amplifiers, and distributed and feedback amplifiers. Interactive computer aided design programs were developed, which include large signal models of InP MISFETs and InGaAs HEMTs. Further, a new unconstrained optimization algorithm POSM was developed and implemented in the general Analysis and Design program for Integrated Circuit (ADIC) for assistance in the design of largesignal nonlinear circuits.

Innovative Magnetic-Field Array Probe for TRUST Integrated Circuits

DTIC Science & Technology

2017-03-01

real-time an IC device. This non-invasive solution is cost effective, with a small form factor. Keywords: Electromagnetic radiation; Near-Field...solicitation was to design, develop and fabricate a low cost electromagnetic probe array for ICs counterfeit. The probe array should operate in the near...Our overall effort was focus on modeling, designing, fabricating, and utilizing novel electromagnetic probes for the analysis, characterization

Functional Laser Trimming Of Thin Film Resistors On Silicon ICs

NASA Astrophysics Data System (ADS)

Mueller, Michael J.; Mickanin, Wes

1986-07-01

Modern Laser Wafer Trimming (LWT) technology achieves exceptional analog circuit performance and precision while maintain-ing the advantages of high production throughput and yield. Microprocessor-driven instrumentation has both emphasized the role of data conversion circuits and demanded sophisticated signal conditioning functions. Advanced analog semiconductor circuits with bandwidths over 1 GHz, and high precision, trimmable, thin-film resistors meet many of todays emerging circuit requirements. Critical to meeting these requirements are optimum choices of laser characteristics, proper materials, trimming process control, accurate modeling of trimmed resistor performance, and appropriate circuit design. Once limited exclusively to hand-crafted, custom integrated circuits, designs are now available in semi-custom circuit configurations. These are similar to those provided for digital designs and supported by computer-aided design (CAD) tools. Integrated with fully automated measurement and trimming systems, these quality circuits can now be produced in quantity to meet the requirements of communications, instrumentation, and signal processing markets.

4H-SiC JFET Multilayer Integrated Circuit Technologies Tested Up to 1000 K

NASA Technical Reports Server (NTRS)

Spry, D. J.; Neudeck, P. G.; Chen, L.; Chang, C. W.; Lukco, D.; Beheim, G. M.

2015-01-01

Testing of semiconductor electronics at temperatures above their designed operating envelope is recognized as vital to qualification and lifetime prediction of circuits. This work describes the high temperature electrical testing of prototype 4H silicon carbide (SiC) junction field effect transistor (JFET) integrated circuits (ICs) technology implemented with multilayer interconnects; these ICs are intended for prolonged operation at temperatures up to 773K (500 C). A 50 mm diameter sapphire wafer was used in place of the standard NASA packaging for this experiment. Testing was carried out between 300K (27 C) and 1150K (877 C) with successful electrical operation of all devices observed up to 1000K (727 C).

Coplanar monolithic integrated circuits for low-noise communication and radar systems

NASA Astrophysics Data System (ADS)

Bessemoulin, Alexandre; Verweyen, Ludger; Marsetz, Waldemar; Massler, Hermann; Neumann, Markus; Hulsmann, Axel; Schlechtweg, Michael

1999-12-01

This paper presents coplanar millimeter-wave monolithic integrated circuits with high performance and small size for use in low noise communication and radar system applications. Technology and modeling issues with respect to active and passive elements are discussed first. In a second step, the potential of coplanar waveguides to realize compact ICs is illustrated through various design examples, such as low noise amplifiers, mixers and power amplifiers. The performance of multifunctional ICs is also presented by comparing simulated and measured results for a complete 77 GHz Transceive MMIC.

Commercialisation of CMOS Integrated Circuit Technology in Multi-Electrode Arrays for Neuroscience and Cell-Based Biosensors

PubMed Central

Graham, Anthony H. D.; Robbins, Jon; Bowen, Chris R.; Taylor, John

2011-01-01

The adaptation of standard integrated circuit (IC) technology as a transducer in cell-based biosensors in drug discovery pharmacology, neural interface systems and electrophysiology requires electrodes that are electrochemically stable, biocompatible and affordable. Unfortunately, the ubiquitous Complementary Metal Oxide Semiconductor (CMOS) IC technology does not meet the first of these requirements. For devices intended only for research, modification of CMOS by post-processing using cleanroom facilities has been achieved. However, to enable adoption of CMOS as a basis for commercial biosensors, the economies of scale of CMOS fabrication must be maintained by using only low-cost post-processing techniques. This review highlights the methodologies employed in cell-based biosensor design where CMOS-based integrated circuits (ICs) form an integral part of the transducer system. Particular emphasis will be placed on the application of multi-electrode arrays for in vitro neuroscience applications. Identifying suitable IC packaging methods presents further significant challenges when considering specific applications. The various challenges and difficulties are reviewed and some potential solutions are presented. PMID:22163884

Protective Socket For Integrated Circuits

NASA Technical Reports Server (NTRS)

Wilkinson, Chris; Henegar, Greg

1988-01-01

Socket for intergrated circuits (IC's) protects from excessive voltages and currents or from application of voltages and currents in wrong sequence during insertion or removal. Contains built-in switch that opens as IC removed, disconnecting leads from signals and power. Also protects other components on circuit board from transients produced by insertion and removal of IC. Makes unnecessary to turn off power to entire circuit board so other circuits on board continue to function.

Nonlinear system analysis in bipolar integrated circuits

NASA Astrophysics Data System (ADS)

Fang, T. F.; Whalen, J. J.

1980-01-01

Since analog bipolar integrated circuits (IC's) have become important components in modern communication systems, the study of the Radio Frequency Interference (RFI) effects in bipolar IC amplifiers is an important subject for electromagnetic compatibility (EMC) engineering. The investigation has focused on using the nonlinear circuit analysis program (NCAP) to predict RF demodulation effects in broadband bipolar IC amplifiers. The audio frequency (AF) voltage at the IC amplifier output terminal caused by an amplitude modulated (AM) RF signal at the IC amplifier input terminal was calculated and compared to measured values. Two broadband IC amplifiers were investigated: (1) a cascode circuit using a CA3026 dual differential pair; (2) a unity gain voltage follower circuit using a micro A741 operational amplifier (op amp). Before using NCAP for RFI analysis, the model parameters for each bipolar junction transistor (BJT) in the integrated circuit were determined. Probe measurement techniques, manufacturer's data, and other researcher's data were used to obtain the required NCAP BJT model parameter values. An important contribution included in this effort is a complete set of NCAP BJT model parameters for most of the transistor types used in linear IC's.

An analog integrated circuit beamformer for high-frequency medical ultrasound imaging.

PubMed

Gurun, Gokce; Zahorian, Jaime S; Sisman, Alper; Karaman, Mustafa; Hasler, Paul E; Degertekin, F Levent

2012-10-01

We designed and fabricated a dynamic receive beamformer integrated circuit (IC) in 0.35-μm CMOS technology. This beamformer IC is suitable for integration with an annular array transducer for high-frequency (30-50 MHz) intravascular ultrasound (IVUS) imaging. The beamformer IC consists of receive preamplifiers, an analog dynamic delay-and-sum beamformer, and buffers for 8 receive channels. To form an analog dynamic delay line we designed an analog delay cell based on the current-mode first-order all-pass filter topology, as the basic building block. To increase the bandwidth of the delay cell, we explored an enhancement technique on the current mirrors. This technique improved the overall bandwidth of the delay line by a factor of 6. Each delay cell consumes 2.1-mW of power and is capable of generating a tunable time delay between 1.75 ns to 2.5 ns. We successfully integrated the fabricated beamformer IC with an 8-element annular array. Experimental test results demonstrated the desired buffering, preamplification and delaying capabilities of the beamformer.

Defense Industrial Base Assessment: U.S. Integrated Circuit Design and Fabrication Capability

DTIC Science & Technology

2009-05-01

in the U.S for the period 2003-2006, with projections to 2011.6 The resulting draft OTE survey was field tested for accuracy and usability with a...custom application specific integrated circuits (ASICs) to field programmable gate arrays (FPGAs). Companies of all sizes can manufacture these IC...able to design one-time Electronically Programmable Gate Arrays (EPGAs) while nine are able to design Field Programmable Gate Arrays (FPGAs). Eight

Interface design for CMOS-integrated Electrochemical Impedance Spectroscopy (EIS) biosensors.

PubMed

Manickam, Arun; Johnson, Christopher Andrew; Kavusi, Sam; Hassibi, Arjang

2012-10-29

Electrochemical Impedance Spectroscopy (EIS) is a powerful electrochemical technique to detect biomolecules. EIS has the potential of carrying out label-free and real-time detection, and in addition, can be easily implemented using electronic integrated circuits (ICs) that are built through standard semiconductor fabrication processes. This paper focuses on the various design and optimization aspects of EIS ICs, particularly the bio-to-semiconductor interface design. We discuss, in detail, considerations such as the choice of the electrode surface in view of IC manufacturing, surface linkers, and development of optimal bio-molecular detection protocols. We also report experimental results, using both macro- and micro-electrodes to demonstrate the design trade-offs and ultimately validate our optimization procedures.

Implantable neurotechnologies: a review of integrated circuit neural amplifiers.

PubMed

Ng, Kian Ann; Greenwald, Elliot; Xu, Yong Ping; Thakor, Nitish V

2016-01-01

Neural signal recording is critical in modern day neuroscience research and emerging neural prosthesis programs. Neural recording requires the use of precise, low-noise amplifier systems to acquire and condition the weak neural signals that are transduced through electrode interfaces. Neural amplifiers and amplifier-based systems are available commercially or can be designed in-house and fabricated using integrated circuit (IC) technologies, resulting in very large-scale integration or application-specific integrated circuit solutions. IC-based neural amplifiers are now used to acquire untethered/portable neural recordings, as they meet the requirements of a miniaturized form factor, light weight and low power consumption. Furthermore, such miniaturized and low-power IC neural amplifiers are now being used in emerging implantable neural prosthesis technologies. This review focuses on neural amplifier-based devices and is presented in two interrelated parts. First, neural signal recording is reviewed, and practical challenges are highlighted. Current amplifier designs with increased functionality and performance and without penalties in chip size and power are featured. Second, applications of IC-based neural amplifiers in basic science experiments (e.g., cortical studies using animal models), neural prostheses (e.g., brain/nerve machine interfaces) and treatment of neuronal diseases (e.g., DBS for treatment of epilepsy) are highlighted. The review concludes with future outlooks of this technology and important challenges with regard to neural signal amplification.

Implantable neurotechnologies: a review of integrated circuit neural amplifiers

PubMed Central

Greenwald, Elliot; Xu, Yong Ping; Thakor, Nitish V.

2016-01-01

Neural signal recording is critical in modern day neuroscience research and emerging neural prosthesis programs. Neural recording requires the use of precise, low-noise amplifier systems to acquire and condition the weak neural signals that are transduced through electrode interfaces. Neural amplifiers and amplifier-based systems are available commercially or can be designed in-house and fabricated using integrated circuit (IC) technologies, resulting in very large-scale integration or application-specific integrated circuit solutions. IC-based neural amplifiers are now used to acquire untethered/portable neural recordings, as they meet the requirements of a miniaturized form factor, light weight and low power consumption. Furthermore, such miniaturized and low-power IC neural amplifiers are now being used in emerging implantable neural prosthesis technologies. This review focuses on neural amplifier-based devices and is presented in two interrelated parts. First, neural signal recording is reviewed, and practical challenges are highlighted. Current amplifier designs with increased functionality and performance and without penalties in chip size and power are featured. Second, applications of IC-based neural amplifiers in basic science experiments (e.g., cortical studies using animal models), neural prostheses (e.g., brain/nerve machine interfaces) and treatment of neuronal diseases (e.g., DBS for treatment of epilepsy) are highlighted. The review concludes with future outlooks of this technology and important challenges with regard to neural signal amplification. PMID:26798055

Automated Visual Inspection Of Integrated Circuits

NASA Astrophysics Data System (ADS)

Noppen, G.; Oosterlinck, Andre J.

1989-07-01

One of the major application fields of image processing techniques is the 'visual inspection'. For a number of rea-sons, the automated visual inspection of Integrated Circuits (IC's) has drawn a lot of attention. : Their very strict design makes them very suitable for an automated inspection. : There is already a lot of experience in the comparable Printed Circuit Board (PCB) and mask inspection. : The mechanical handling of wafers and dice is already an established technology. : Military and medical IC's should be a 100 % failproof. : IC inspection gives a high and allinost immediate payback. In this paper we wil try to give an outline of the problems involved in IC inspection, and the algorithms and methods used to overcome these problems. We will not go into de-tail, but we will try to give a general understanding. Our attention will go to the following topics. : An overview of the inspection process, with an emphasis on the second visual inspection. : The problems encountered in IC inspection, as opposed to the comparable PCB and mask inspection. : The image acquisition devices that can be used to obtain 'inspectable' images. : A general overview of the algorithms that can be used. : A short description of the algorithms developed at the ESAT-MI2 division of the katholieke Universiteit Leuven.

Design and performance of clock-recovery GaAs ICs for high-speed optical communication systems

NASA Astrophysics Data System (ADS)

Imai, Yuhki; Sano, Eiichi; Nakamura, Makoto; Ishihara, Noboru; Kikuchi, Hiroyuki; Ono, Takashi

1993-05-01

Design and performance of clock-recovery GaAs ICs are presented. Four kinds of ICs were developed: a limiting amplifier, a tuning amplifier, a rectifier, and a differentiator. The cascaded limiting amplifier together with a tuning amplifier achieved a 58-dB gain and a 10-degree phase deviation with 20-dB input dynamic range at 10 GHz. A clock-recovery circuit successfully extracts a low-jitter 10-GHz clock signal of 1-dBm constant power from 10-Gb/s NRZ pseudorandom bit streams using a pulse pattern generator.

Electrical Characterization of 4H-SiC JFET Wafer: DC Parameter Variations for Extreme Temperature IC Design

NASA Technical Reports Server (NTRS)

Neudeck, Philip G.; Chen, Liangyu; Spry, David J.; Beheim, Glenn M.; Chang, Carl W.

2014-01-01

This work reports DC electrical characterization of a 76 mm diameter 4H-SiC JFET test wafer fabricated as part of NASA's on-going efforts to realize medium-scale ICs with prolonged and stable circuit operation at temperatures as high as 500 degC. In particular, these measurements provide quantitative parameter ranges for use in JFET IC design and simulation. Larger than expected parameter variations were observed both as a function of position across the wafer as well as a function of ambient testing temperature from 23 degC to 500 degC.

Integrated readout electronics for Belle II pixel detector

NASA Astrophysics Data System (ADS)

Blanco, R.; Leys, R.; Perić, I.

2018-03-01

This paper describes the readout components for Belle II that have been designed as integrated circuits. The ICs are connected to DEPFET sensor by bump bonding. Three types of ICs have been developed: SWITCHER for pixel matrix control, DCD for readout and digitizing of sensor signals and DHP for digital data processing. The ICs are radiation tolerant and use several novel features, such as the multiple-input differential amplifiers and the fast and radiation hard high-voltage drivers. SWITCHER and DCD have been developed at University of Heidelberg, Karlsruhe Institute of Technology (KIT) and DHP at Bonn University. The IC-development started in 2009 and was accomplished in 2016 with the submissions of final designs. The final ICs for Belle II pixel detector and the related measurement results will be presented in this contribution.

R&D100: IC ID

ScienceCinema

Hamlet, Jason; Pierson, Lyndon; Bauer, Todd

2018-06-25

Supply chain security to detect, deter, and prevent the counterfeiting of networked and stand-alone integrated circuits (ICs) is critical to cyber security. Sandia National Laboratory researchers have developed IC ID to leverage Physically Unclonable Functions (PUFs) and strong cryptographic authentication to create a unique fingerprint for each integrated circuit. IC ID assures the authenticity of ICs to prevent tampering or malicious substitution.

Fabrication process of superconducting integrated circuits with submicron Nb/AlOx/Nb junctions using electron-beam direct writing technique

NASA Astrophysics Data System (ADS)

Aoyagi, Masahiro; Nakagawa, Hiroshi

1997-07-01

For enhancing operating speed of a superconducting integrated circuit (IC), the device size must be reduced into the submicron level. For this purpose, we have introduced electron beam (EB) direct writing technique into the fabrication process of a Nb/AlOx/Nb Josephson IC. A two-layer (PMMA/(alpha) M-CMS) resist method called the portable conformable mask (PCM) method was utilized for having a high aspect ratio. The electron cyclotron resonance (ECR) plasma etching technique was utilized. We have fabricated micron or submicron-size Nb/AlOx/Nb Josephson junctions, where the size of the junction was varied from 2 micrometer to 0.5 micrometer at 0.1 micrometer intervals. These junctions were designed for evaluating the spread of the junction critical current. We achieved minimum-to-maximum Ic spread of plus or minus 13% for 0.81-micrometer-square (plus or minus 16% for 0.67-micrometer-square) 100 junctions spreading in 130- micrometer-square area. The size deviation of 0.05 micrometer was estimated from the spread values. We have successfully demonstrated a small-scale logic IC with 0.9-micrometer-square junctions having a 50 4JL OR-gate chain, where 4JL means four junctions logic family. The circuit was designed for measuring the gate delay. We obtained a preliminary result of the OR- gate logic delay, where the minimum delay was 8.6 ps/gate.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hamlet, Jason; Pierson, Lyndon; Bauer, Todd

Supply chain security to detect, deter, and prevent the counterfeiting of networked and stand-alone integrated circuits (ICs) is critical to cyber security. Sandia National Laboratory researchers have developed IC ID to leverage Physically Unclonable Functions (PUFs) and strong cryptographic authentication to create a unique fingerprint for each integrated circuit. IC ID assures the authenticity of ICs to prevent tampering or malicious substitution.

An electron-beam dose deposition experiment: TIGER 1-D simulation code versus thermoluminescent dosimetry

NASA Astrophysics Data System (ADS)

Murrill, Steven R.; Tipton, Charles W.; Self, Charles T.

1991-03-01

The dose absorbed in an integrated circuit (IC) die exposed to a pulse of low-energy electrons is a strong function of both electron energy and surrounding packaging materials. This report describes an experiment designed to measure how well the Integrated TIGER Series one-dimensional (1-D) electron transport simulation program predicts dose correction factors for a state-of-the-art IC package and package/printed circuit board (PCB) combination. These derived factors are compared with data obtained experimentally using thermoluminescent dosimeters (TLD's) and the FX-45 flash x-ray machine (operated in electron-beam (e-beam) mode). The results of this experiment show that the TIGER 1-D simulation code can be used to accurately predict FX-45 e-beam dose deposition correction factors for reasonably complex IC packaging configurations.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Britton, C.L.; Jagadish, U.; Bryan, W.L.

An Integrated Circuit (IC) readout chip with four channels arranged so as to receive input charge from the corners of the chip was designed for use with 5- to 7-mm pixel detectors. This Application Specific IC (ASIC) can be used for cold neutron imaging, for study of structural order in materials using cold neutron scattering or for particle physics experiments. The ASIC is fabricated in a 0.5-{micro}m n-well AMI process. The design of the ASIC and the test measurements made is reported. Noise measurements are also reported.

Light-induced voltage alteration for integrated circuit analysis

DOEpatents

Cole, Jr., Edward I.; Soden, Jerry M.

1995-01-01

An apparatus and method are described for analyzing an integrated circuit (IC), The invention uses a focused light beam that is scanned over a surface of the IC to generate a light-induced voltage alteration (LIVA) signal for analysis of the IC, The LIVA signal may be used to generate an image of the IC showing the location of any defects in the IC; and it may be further used to image and control the logic states of the IC. The invention has uses for IC failure analysis, for the development of ICs, for production-line inspection of ICs, and for qualification of ICs.

Light-induced voltage alteration for integrated circuit analysis

DOEpatents

Cole, E.I. Jr.; Soden, J.M.

1995-07-04

An apparatus and method are described for analyzing an integrated circuit (IC). The invention uses a focused light beam that is scanned over a surface of the IC to generate a light-induced voltage alteration (LIVA) signal for analysis of the IC. The LIVA signal may be used to generate an image of the IC showing the location of any defects in the IC; and it may be further used to image and control the logic states of the IC. The invention has uses for IC failure analysis, for the development of ICs, for production-line inspection of ICs, and for qualification of ICs. 18 figs.

Using NCAP to predict RFI effects in linear bipolar integrated circuits

NASA Astrophysics Data System (ADS)

Fang, T.-F.; Whalen, J. J.; Chen, G. K. C.

1980-11-01

Applications of the Nonlinear Circuit Analysis Program (NCAP) to calculate RFI effects in electronic circuits containing discrete semiconductor devices have been reported upon previously. The objective of this paper is to demonstrate that the computer program NCAP also can be used to calcuate RFI effects in linear bipolar integrated circuits (IC's). The IC's reported upon are the microA741 operational amplifier (op amp) which is one of the most widely used IC's, and a differential pair which is a basic building block in many linear IC's. The microA741 op amp was used as the active component in a unity-gain buffer amplifier. The differential pair was used in a broad-band cascode amplifier circuit. The computer program NCAP was used to predict how amplitude-modulated RF signals are demodulated in the IC's to cause undesired low-frequency responses. The predicted and measured results for radio frequencies in the 0.050-60-MHz range are in good agreement.

Modular integration of electronics and microfluidic systems using flexible printed circuit boards.

PubMed

Wu, Amy; Wang, Lisen; Jensen, Erik; Mathies, Richard; Boser, Bernhard

2010-02-21

Microfluidic systems offer an attractive alternative to conventional wet chemical methods with benefits including reduced sample and reagent volumes, shorter reaction times, high-throughput, automation, and low cost. However, most present microfluidic systems rely on external means to analyze reaction products. This substantially adds to the size, complexity, and cost of the overall system. Electronic detection based on sub-millimetre size integrated circuits (ICs) has been demonstrated for a wide range of targets including nucleic and amino acids, but deployment of this technology to date has been limited due to the lack of a flexible process to integrate these chips within microfluidic devices. This paper presents a modular and inexpensive process to integrate ICs with microfluidic systems based on standard printed circuit board (PCB) technology to assemble the independently designed microfluidic and electronic components. The integrated system can accommodate multiple chips of different sizes bonded to glass or PDMS microfluidic systems. Since IC chips and flex PCB manufacturing and assembly are industry standards with low cost, the integrated system is economical for both laboratory and point-of-care settings.

Low power, compact charge coupled device signal processing system

NASA Technical Reports Server (NTRS)

Bosshart, P. W.; Buss, D. D.; Eversole, W. L.; Hewes, C. R.; Mayer, D. J.

1980-01-01

A variety of charged coupled devices (CCDs) for performing programmable correlation for preprocessing environmental sensor data preparatory to its transmission to the ground were developed. A total of two separate ICs were developed and a third was evaluated. The first IC was a CCD chirp z transform IC capable of performing a 32 point DFT at frequencies to 1 MHz. All on chip circuitry operated as designed with the exception of the limited dynamic range caused by a fixed pattern noise due to interactions between the digital and analog circuits. The second IC developed was a 64 stage CCD analog/analog correlator for performing time domain correlation. Multiplier errors were found to be less than 1 percent at designed signal levels and less than 0.3 percent at the measured smaller levels. A prototype IC for performing time domain correlation was also evaluated.

Nanoscale x-ray imaging of circuit features without wafer etching.

PubMed

Deng, Junjing; Hong, Young Pyo; Chen, Si; Nashed, Youssef S G; Peterka, Tom; Levi, Anthony J F; Damoulakis, John; Saha, Sayan; Eiles, Travis; Jacobsen, Chris

2017-03-01

Modern integrated circuits (ICs) employ a myriad of materials organized at nanoscale dimensions, and certain critical tolerances must be met for them to function. To understand departures from intended functionality, it is essential to examine ICs as manufactured so as to adjust design rules, ideally in a non-destructive way so that imaged structures can be correlated with electrical performance. Electron microscopes can do this on thin regions, or on exposed surfaces, but the required processing alters or even destroys functionality. Microscopy with multi-keV x-rays provides an alternative approach with greater penetration, but the spatial resolution of x-ray imaging lenses has not allowed one to see the required detail in the latest generation of ICs. X-ray ptychography provides a way to obtain images of ICs without lens-imposed resolution limits, with past work delivering 20-40 nm resolution on thinned ICs. We describe a simple model for estimating the required exposure, and use it to estimate the future potential for this technique. Here we show for the first time that this approach can be used to image circuit detail through an unprocessed 300 μ m thick silicon wafer, with sub-20 nm detail clearly resolved after mechanical polishing to 240 μ m thickness was used to eliminate image contrast caused by Si wafer surface scratches. By using continuous x-ray scanning, massively parallel computation, and a new generation of synchrotron light sources, this should enable entire non-etched ICs to be imaged to 10 nm resolution or better while maintaining their ability to function in electrical tests.

Nanoscale x-ray imaging of circuit features without wafer etching

DOE PAGES

Deng, Junjing; Hong, Young Pyo; Chen, Si; ...

2017-03-24

Modern integrated circuits (ICs) employ a myriad of materials organized at nanoscale dimensions, and certain critical tolerances must be met for them to function. To understand departures from intended functionality, it is essential to examine ICs as manufactured so as to adjust design rules ideally in a nondestructive way so that imaged structures can be correlated with electrical performance. Electron microscopes can do this on thin regions or on exposed surfaces, but the required processing alters or even destroys functionality. Microscopy with multi-keV x-rays provides an alternative approach with greater penetration, but the spatial resolution of x-ray imaging lenses hasmore » not allowed one to see the required detail in the latest generation of ICs. X-ray ptychography provides a way to obtain images of ICs without lens-imposed resolution limits with past work delivering 20–40-nm resolution on thinned ICs. We describe a simple model for estimating the required exposure and use it to estimate the future potential for this technique. Here we show that this approach can be used to image circuit detail through an unprocessed 300-μm-thick silicon wafer with sub-20-nm detail clearly resolved after mechanical polishing to 240-μm thickness was used to eliminate image contrast caused by Si wafer surface scratches. Here, by using continuous x-ray scanning, massively parallel computation, and a new generation of synchrotron light sources, this should enable entire nonetched ICs to be imaged to 10-nm resolution or better while maintaining their ability to function in electrical tests.« less

Nanoscale x-ray imaging of circuit features without wafer etching

NASA Astrophysics Data System (ADS)

Deng, Junjing; Hong, Young Pyo; Chen, Si; Nashed, Youssef S. G.; Peterka, Tom; Levi, Anthony J. F.; Damoulakis, John; Saha, Sayan; Eiles, Travis; Jacobsen, Chris

2017-03-01

Modern integrated circuits (ICs) employ a myriad of materials organized at nanoscale dimensions, and certain critical tolerances must be met for them to function. To understand departures from intended functionality, it is essential to examine ICs as manufactured so as to adjust design rules ideally in a nondestructive way so that imaged structures can be correlated with electrical performance. Electron microscopes can do this on thin regions or on exposed surfaces, but the required processing alters or even destroys functionality. Microscopy with multi-keV x rays provides an alternative approach with greater penetration, but the spatial resolution of x-ray imaging lenses has not allowed one to see the required detail in the latest generation of ICs. X-ray ptychography provides a way to obtain images of ICs without lens-imposed resolution limits with past work delivering 20-40-nm resolution on thinned ICs. We describe a simple model for estimating the required exposure and use it to estimate the future potential for this technique. Here we show that this approach can be used to image circuit detail through an unprocessed 300 -μ m -thick silicon wafer with sub-20-nm detail clearly resolved after mechanical polishing to 240 -μ m thickness was used to eliminate image contrast caused by Si wafer surface scratches. By using continuous x-ray scanning, massively parallel computation, and a new generation of synchrotron light sources, this should enable entire nonetched ICs to be imaged to 10-nm resolution or better while maintaining their ability to function in electrical tests.

A high-speed trapezoid image sensor design for continuous traffic monitoring at signalized intersection approaches.

DOT National Transportation Integrated Search

2014-10-01

The goal of this project is to monitor traffic flow continuously with an innovative camera system composed of a custom : designed image sensor integrated circuit (IC) containing trapezoid pixel array and camera system that is capable of : intelligent...

The design of radiation-hardened ICs for space - A compendium of approaches

NASA Technical Reports Server (NTRS)

Kerns, Sherra E.; Shafer, B. D; Rockett, L. R., Jr.; Pridmore, J. S.; Berndt, D. F.

1988-01-01

Several technologies, including bulk and epi CMOS, CMOS/SOI-SOS (silicon-on-insulator-silicon-on-sapphire), CML (current-mode logic), ECL (emitter-coupled logic), analog bipolar (JI, single-poly DI, and SOI) and GaAs E/D (enhancement/depletion) heterojunction MESFET, are discussed. The discussion includes the direct effects of space radiation on microelectronic materials and devices, how these effects are evidenced in circuit and device design parameter variations, the particular effects of most significance to each functional class of circuit, specific techniques for hardening high-speed circuits, design examples for integrated systems, including operational amplifiers and A/D (analog/digital) converters, and the computer simulation of radiation effects on microelectronic ISs.

Heart-Rate and Breath-Rate Monitor

NASA Technical Reports Server (NTRS)

Cooper, T. G.

1983-01-01

Circuit requiring only four integrated circuits (IC's) measures both heart rate and breath rate. Phase-locked loops lock on heart-rate and respiration-rate input signals. Each loop IC contains two phase comparators. Positive-edge-triggered circuit used in making monitors insensitive to dutycycle variations.

On-Die Sensors for Transient Events

NASA Astrophysics Data System (ADS)

Suchak, Mihir Vimal

Failures caused by transient electromagnetic events like Electrostatic Discharge (ESD) are a major concern for embedded systems. The component often failing is an integrated circuit (IC). Determining which IC is affected in a multi-device system is a challenging task. Debugging errors often requires sophisticated lab setups which require intentionally disturbing and probing various parts of the system which might not be easily accessible. Opening the system and adding probes may change its response to the transient event, which further compounds the problem. On-die transient event sensors were developed that require relatively little area on die, making them inexpensive, they consume negligible static current, and do not interfere with normal operation of the IC. These circuits can be used to determine the pin involved and the level of the event in the event of a transient event affecting the IC, thus allowing the user to debug system-level transient events without modifying the system. The circuit and detection scheme design has been completed and verified in simulations with Cadence Virtuoso environment. Simulations accounted for the impact of the ESD protection circuits, parasitics from the I/O pin, package and I/O ring, and included a model of an ESD gun to test the circuit's response to an ESD pulse as specified in IEC 61000-4-2. Multiple detection schemes are proposed. The final detection scheme consists of an event detector and a level sensor. The event detector latches on the presence of an event at a pad, to determine on which pin an event occurred. The level sensor generates current proportional to the level of the event. This current is converted to a voltage and digitized at the A/D converter to be read by the microprocessor. Detection scheme shows good performance in simulations when checked against process variations and different kind of events.

Apparatus and methods for packaging integrated circuit chips with antenna modules providing closed electromagnetic environment for integrated antennas

NASA Technical Reports Server (NTRS)

Gaucher, Brian P. (Inventor); Grzyb, Janusz (Inventor); Liu, Duixian (Inventor); Pfeiffer, Ullrich R. (Inventor)

2008-01-01

Apparatus and methods are provided for packaging IC chips together with integrated antenna modules designed to provide a closed EM (electromagnetic) environment for antenna radiators, thereby allowing antennas to be designed independent from the packaging technology.

Healing Voids In Interconnections In Integrated Circuits

NASA Technical Reports Server (NTRS)

Cuddihy, Edward F.; Lawton, Russell A.; Gavin, Thomas

1989-01-01

Unusual heat treatment heals voids in aluminum interconnections on integrated circuits (IC's). Treatment consists of heating IC to temperature between 200 degrees C and 400 degrees C, holding it at that temperature, and then plunging IC immediately into liquid nitrogen. Typical holding time at evaluated temperature is 30 minutes.

JPRS Report: Science & Technology - Europe.

DTIC Science & Technology

1992-12-21

in the aero- nautical industry—through the use of hybrids, ASICs [application-specific integrated circuits ], etc. "The system will also have an... Module ], the cylinder-shaped pressurized cabin that can be firmly attached to the international space station), which is to be launched in 1999...34] [Excerpt] Two hundred scientists and $1 billion to design the chip of the future, an integrated circuit (IC) giving microcomputers power

Drive and protection circuit for converter module of cascaded H-bridge STATCOM

NASA Astrophysics Data System (ADS)

Wang, Xuan; Yuan, Hongliang; Wang, Xiaoxing; Wang, Shuai; Fu, Yongsheng

2018-04-01

Drive and protection circuit is an important part of power electronics, which is related to safe and stable operation issues in the power electronics. The drive and protection circuit is designed for the cascaded H-bridge STATCOM. This circuit can realize flexible dead-time setting, operation status self-detection, fault priority protection and detailed fault status uploading. It can help to improve the reliability of STATCOM's operation. Finally, the proposed circuit is tested and analyzed by power electronic simulation software PSPICE (Simulation Program with IC Emphasis) and a series of experiments. Further studies showed that the proposed circuit can realize drive and control of H-bridge circuit, meanwhile it also can realize fast processing faults and have advantage of high reliability.

Design of a Low-Power, Small-Area AEC-Q100-Compliant SENT Transmitter in Signal Conditioning IC for Automotive Pressure and Temperature Complex Sensors in 180 Nm CMOS Technology.

PubMed

Ali, Imran; Rikhan, Behnam Samadpoor; Kim, Dong-Gyu; Lee, Dong-Soo; Rehman, Muhammad Riaz Ur; Abbasizadeh, Hamed; Asif, Muhammad; Lee, Minjae; Hwang, Keum Cheol; Yang, Youngoo; Lee, Kang-Yoon

2018-05-14

In this paper, a low-power and small-area Single Edge Nibble Transmission (SENT) transmitter design is proposed for automotive pressure and temperature complex sensor applications. To reduce the cost and size of the hardware, the pressure and temperature information is processed with a single integrated circuit (IC) and transmitted at the same time to the electronic control unit (ECU) through SENT. Due to its digital nature, it is immune to noise, has reduced sensitivity to electromagnetic interference (EMI), and generates low EMI. It requires only one PAD for its connectivity with ECU, and thus reduces the pin requirements, simplifies the connectivity, and minimizes the printed circuit board (PCB) complexity. The design is fully synthesizable, and independent of technology. The finite state machine-based approach is employed for area efficient implementation, and to translate the proposed architecture into hardware. The IC is fabricated in 1P6M 180 nm CMOS process with an area of (116 μm × 116 μm) and 4.314 K gates. The current consumption is 50 μA from a 1.8 V supply with a total 90 μW power. For compliance with AEC-Q100 for automotive reliability, a reverse and over voltage protection circuit is also implemented with human body model (HBM) electro-static discharge (ESD) of +6 kV, reverse voltage of -16 V to 0 V, over voltage of 8.2 V to 16 V, and fabricated area of 330 μm × 680 μm. The extensive testing, measurement, and simulation results prove that the design is fully compliant with SAE J2716 standard.

Design of a Low-Power, Small-Area AEC-Q100-Compliant SENT Transmitter in Signal Conditioning IC for Automotive Pressure and Temperature Complex Sensors in 180 Nm CMOS Technology

PubMed Central

Rikhan, Behnam Samadpoor; Kim, Dong-Gyu; Lee, Dong-Soo; Rehman, Muhammad Riaz Ur; Abbasizadeh, Hamed; Asif, Muhammad; Lee, Minjae; Yang, Youngoo; Lee, Kang-Yoon

2018-01-01

In this paper, a low-power and small-area Single Edge Nibble Transmission (SENT) transmitter design is proposed for automotive pressure and temperature complex sensor applications. To reduce the cost and size of the hardware, the pressure and temperature information is processed with a single integrated circuit (IC) and transmitted at the same time to the electronic control unit (ECU) through SENT. Due to its digital nature, it is immune to noise, has reduced sensitivity to electromagnetic interference (EMI), and generates low EMI. It requires only one PAD for its connectivity with ECU, and thus reduces the pin requirements, simplifies the connectivity, and minimizes the printed circuit board (PCB) complexity. The design is fully synthesizable, and independent of technology. The finite state machine-based approach is employed for area efficient implementation, and to translate the proposed architecture into hardware. The IC is fabricated in 1P6M 180 nm CMOS process with an area of (116 μm × 116 μm) and 4.314 K gates. The current consumption is 50 μA from a 1.8 V supply with a total 90 μW power. For compliance with AEC-Q100 for automotive reliability, a reverse and over voltage protection circuit is also implemented with human body model (HBM) electro-static discharge (ESD) of +6 kV, reverse voltage of −16 V to 0 V, over voltage of 8.2 V to 16 V, and fabricated area of 330 μm × 680 μm. The extensive testing, measurement, and simulation results prove that the design is fully compliant with SAE J2716 standard. PMID:29757996

Ion-beam apparatus and method for analyzing and controlling integrated circuits

DOEpatents

Campbell, A.N.; Soden, J.M.

1998-12-01

An ion-beam apparatus and method for analyzing and controlling integrated circuits are disclosed. The ion-beam apparatus comprises a stage for holding one or more integrated circuits (ICs); a source means for producing a focused ion beam; and a beam-directing means for directing the focused ion beam to irradiate a predetermined portion of the IC for sufficient time to provide an ion-beam-generated electrical input signal to a predetermined element of the IC. The apparatus and method have applications to failure analysis and developmental analysis of ICs and permit an alteration, control, or programming of logic states or device parameters within the IC either separate from or in combination with applied electrical stimulus to the IC for analysis thereof. Preferred embodiments of the present invention including a secondary particle detector and an electron floodgun further permit imaging of the IC by secondary ions or electrons, and allow at least a partial removal or erasure of the ion-beam-generated electrical input signal. 4 figs.

Ion-beam apparatus and method for analyzing and controlling integrated circuits

DOEpatents

Campbell, Ann N.; Soden, Jerry M.

1998-01-01

An ion-beam apparatus and method for analyzing and controlling integrated circuits. The ion-beam apparatus comprises a stage for holding one or more integrated circuits (ICs); a source means for producing a focused ion beam; and a beam-directing means for directing the focused ion beam to irradiate a predetermined portion of the IC for sufficient time to provide an ion-beam-generated electrical input signal to a predetermined element of the IC. The apparatus and method have applications to failure analysis and developmental analysis of ICs and permit an alteration, control, or programming of logic states or device parameters within the IC either separate from or in combination with applied electrical stimulus to the IC for analysis thereof. Preferred embodiments of the present invention including a secondary particle detector and an electron floodgun further permit imaging of the IC by secondary ions or electrons, and allow at least a partial removal or erasure of the ion-beam-generated electrical input signal.

Improved Signal Chains for Readout of CMOS Imagers

NASA Technical Reports Server (NTRS)

Pain, Bedabrata; Hancock, Bruce; Cunningham, Thomas

2009-01-01

An improved generic design has been devised for implementing signal chains involved in readout from complementary metal oxide/semiconductor (CMOS) image sensors and for other readout integrated circuits (ICs) that perform equivalent functions. The design applies to any such IC in which output signal charges from the pixels in a given row are transferred simultaneously into sampling capacitors at the bottoms of the columns, then voltages representing individual pixel charges are read out in sequence by sequentially turning on column-selecting field-effect transistors (FETs) in synchronism with source-follower- or operational-amplifier-based amplifier circuits. The improved design affords the best features of prior source-follower-and operational- amplifier-based designs while overcoming the major limitations of those designs. The limitations can be summarized as follows: a) For a source-follower-based signal chain, the ohmic voltage drop associated with DC bias current flowing through the column-selection FET causes unacceptable voltage offset, nonlinearity, and reduced small-signal gain. b) For an operational-amplifier-based signal chain, the required bias current and the output noise increase superlinearly with size of the pixel array because of a corresponding increase in the effective capacitance of the row bus used to couple the sampled column charges to the operational amplifier. The effect of the bus capacitance is to simultaneously slow down the readout circuit and increase noise through the Miller effect.

High-frequency output characteristics of AlGaAs/GaAs heterojunction bipolar transistors for large-signal applications

NASA Astrophysics Data System (ADS)

Chen, J.; Gao, G. B.; Ünlü, M. S.; Morkoç, H.

1991-11-01

High-frequency ic- vce output characteristics of bipolar transistors, derived from calculated device cutoff frequencies, are reported. The generation of high-frequency output characteristics from device design specifications represents a novel bridge between microwave circuit design and device design: the microwave performance of simulated device structures can be analyzed, or tailored transistor device structures can be designed to fit specific circuit applications. The details of our compact transistor model are presented, highlighting the high-current base-widening (Kirk) effect. The derivation of the output characteristics from the modeled cutoff frequencies are then presented, and the computed characteristics of an AlGaAs/GaAs heterojunction bipolar transistor operating at 10 GHz are analyzed. Applying the derived output characteristics to microwave circuit design, we examine large-signal class A and class B amplification.

Picosecond imaging of signal propagation in integrated circuits

NASA Astrophysics Data System (ADS)

Frohmann, Sven; Dietz, Enrico; Dittrich, Helmar; Hübers, Heinz-Wilhelm

2017-04-01

Optical analysis of integrated circuits (IC) is a powerful tool for analyzing security functions that are implemented in an IC. We present a photon emission microscope for picosecond imaging of hot carrier luminescence in ICs in the near-infrared spectral range from 900 to 1700 nm. It allows for a semi-invasive signal tracking in fully operational ICs on the gate or transistor level with a timing precision of approximately 6 ps. The capabilities of the microscope are demonstrated by imaging the operation of two ICs made by 180 and 60 nm process technology.

High operating temperature interband cascade focal plane arrays

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tian, Z.-B.; Godoy, S. E.; Kim, H. S.

2014-08-04

In this paper, we report the initial demonstration of mid-infrared interband cascade (IC) photodetector focal plane arrays with multiple-stage/junction design. The merits of IC photodetectors include low noise and efficient photocarrier extraction, even for zero-bias operation. By adopting enhanced electron barrier design and a total absorber thickness of 0.7 μm, the 5-stage IC detectors show very low dark current (1.10 × 10{sup −7} A/cm{sup 2} at −5 mV and 150 K). Even with un-optimized fabrication and standard commercial (mis-matched) read-out circuit technology, infrared images are obtained by the 320 × 256 IC focal plane array up to 180 K with f/2.3 optics. The minimum noise equivalent temperature differencemore » of 28 mK is obtained at 120 K. These initial results indicate great potential of IC photodetectors, particularly for high operating temperature applications.« less

FAST: a framework for simulation and analysis of large-scale protein-silicon biosensor circuits.

PubMed

Gu, Ming; Chakrabartty, Shantanu

2013-08-01

This paper presents a computer aided design (CAD) framework for verification and reliability analysis of protein-silicon hybrid circuits used in biosensors. It is envisioned that similar to integrated circuit (IC) CAD design tools, the proposed framework will be useful for system level optimization of biosensors and for discovery of new sensing modalities without resorting to laborious fabrication and experimental procedures. The framework referred to as FAST analyzes protein-based circuits by solving inverse problems involving stochastic functional elements that admit non-linear relationships between different circuit variables. In this regard, FAST uses a factor-graph netlist as a user interface and solving the inverse problem entails passing messages/signals between the internal nodes of the netlist. Stochastic analysis techniques like density evolution are used to understand the dynamics of the circuit and estimate the reliability of the solution. As an example, we present a complete design flow using FAST for synthesis, analysis and verification of our previously reported conductometric immunoassay that uses antibody-based circuits to implement forward error-correction (FEC).

Integrated circuit authentication using photon-limited x-ray microscopy.

PubMed

Markman, Adam; Javidi, Bahram

2016-07-15

A counterfeit integrated circuit (IC) may contain subtle changes to its circuit configuration. These changes may be observed when imaged using an x-ray; however, the energy from the x-ray can potentially damage the IC. We have investigated a technique to authenticate ICs under photon-limited x-ray imaging. We modeled an x-ray image with lower energy by generating a photon-limited image from a real x-ray image using a weighted photon-counting method. We performed feature extraction on the image using the speeded-up robust features (SURF) algorithm. We then authenticated the IC by comparing the SURF features to a database of SURF features from authentic and counterfeit ICs. Our experimental results with real and counterfeit ICs using an x-ray microscope demonstrate that we can correctly authenticate an IC image captured using orders of magnitude lower energy x-rays. To the best of our knowledge, this Letter is the first one on using a photon-counting x-ray imaging model and relevant algorithms to authenticate ICs to prevent potential damage.

Survey of key technologies on millimeter-wave CMOS integrated circuits

NASA Astrophysics Data System (ADS)

Yu, Fei; Gao, Lei; Li, Lixiang; Cai, Shuo; Wang, Wei; Wang, Chunhua

2018-05-01

In order to provide guidance for the development of high performance millimeter-wave complementary metal oxide semiconductor (MMW-CMOS) integrated circuits (IC), this paper provides a survey of key technologies on MMW-CMOS IC. Technical background of MMW wireless communications is described. Then the recent development of the critical technologies of the MMW-CMOS IC are introduced in detail and compared. A summarization is given, and the development prospects on MMW-CMOS IC are also discussed.

I/O impedance controller

DOEpatents

Ruesch, Rodney; Jenkins, Philip N.; Ma, Nan

2004-03-09

There is disclosed apparatus and apparatus for impedance control to provide for controlling the impedance of a communication circuit using an all-digital impedance control circuit wherein one or more control bits are used to tune the output impedance. In one example embodiment, the impedance control circuit is fabricated using circuit components found in a standard macro library of a computer aided design system. According to another example embodiment, there is provided a control for an output driver on an integrated circuit ("IC") device to provide for forming a resistor divider network with the output driver and a resistor off the IC device so that the divider network produces an output voltage, comparing the output voltage of the divider network with a reference voltage, and adjusting the output impedance of the output driver to attempt to match the output voltage of the divider network and the reference voltage. Also disclosed is over-sampling the divider network voltage, storing the results of the over sampling, repeating the over-sampling and storing, averaging the results of multiple over sampling operations, controlling the impedance with a plurality of bits forming a word, and updating the value of the word by only one least significant bit at a time.

The Impact of 3D Stacking and Technology Scaling on the Power and Area of Stereo Matching Processors.

PubMed

Ok, Seung-Ho; Lee, Yong-Hwan; Shim, Jae Hoon; Lim, Sung Kyu; Moon, Byungin

2017-02-22

Recently, stereo matching processors have been adopted in real-time embedded systems such as intelligent robots and autonomous vehicles, which require minimal hardware resources and low power consumption. Meanwhile, thanks to the through-silicon via (TSV), three-dimensional (3D) stacking technology has emerged as a practical solution to achieving the desired requirements of a high-performance circuit. In this paper, we present the benefits of 3D stacking and process technology scaling on stereo matching processors. We implemented 2-tier 3D-stacked stereo matching processors with GlobalFoundries 130-nm and Nangate 45-nm process design kits and compare them with their two-dimensional (2D) counterparts to identify comprehensive design benefits. In addition, we examine the findings from various analyses to identify the power benefits of 3D-stacked integrated circuit (IC) and device technology advancements. From experiments, we observe that the proposed 3D-stacked ICs, compared to their 2D IC counterparts, obtain 43% area, 13% power, and 14% wire length reductions. In addition, we present a logic partitioning method suitable for a pipeline-based hardware architecture that minimizes the use of TSVs.

The Impact of 3D Stacking and Technology Scaling on the Power and Area of Stereo Matching Processors

PubMed Central

Ok, Seung-Ho; Lee, Yong-Hwan; Shim, Jae Hoon; Lim, Sung Kyu; Moon, Byungin

2017-01-01

Recently, stereo matching processors have been adopted in real-time embedded systems such as intelligent robots and autonomous vehicles, which require minimal hardware resources and low power consumption. Meanwhile, thanks to the through-silicon via (TSV), three-dimensional (3D) stacking technology has emerged as a practical solution to achieving the desired requirements of a high-performance circuit. In this paper, we present the benefits of 3D stacking and process technology scaling on stereo matching processors. We implemented 2-tier 3D-stacked stereo matching processors with GlobalFoundries 130-nm and Nangate 45-nm process design kits and compare them with their two-dimensional (2D) counterparts to identify comprehensive design benefits. In addition, we examine the findings from various analyses to identify the power benefits of 3D-stacked integrated circuit (IC) and device technology advancements. From experiments, we observe that the proposed 3D-stacked ICs, compared to their 2D IC counterparts, obtain 43% area, 13% power, and 14% wire length reductions. In addition, we present a logic partitioning method suitable for a pipeline-based hardware architecture that minimizes the use of TSVs. PMID:28241437

System and method for interfacing large-area electronics with integrated circuit devices

DOEpatents

Verma, Naveen; Glisic, Branko; Sturm, James; Wagner, Sigurd

2016-07-12

A system and method for interfacing large-area electronics with integrated circuit devices is provided. The system may be implemented in an electronic device including a large area electronic (LAE) device disposed on a substrate. An integrated circuit IC is disposed on the substrate. A non-contact interface is disposed on the substrate and coupled between the LAE device and the IC. The non-contact interface is configured to provide at least one of a data acquisition path or control path between the LAE device and the IC.

A multifactor regulatory circuit involving H-NS, VirF and an antisense RNA modulates transcription of the virulence gene icsA of Shigella flexneri.

PubMed

Tran, Chi Nhan; Giangrossi, Mara; Prosseda, Gianni; Brandi, Anna; Di Martino, Maria Letizia; Colonna, Bianca; Falconi, Maurizio

2011-10-01

The icsA gene of Shigella encodes a structural protein involved in colonization of the intestinal mucosa by bacteria. This gene is expressed upon invasion of the host and is controlled by a complex regulatory circuit involving the nucleoid protein H-NS, the AraC-like transcriptional activator VirF, and a 450 nt antisense RNA (RnaG) acting as transcriptional attenuator. We investigated on the interplay of these factors at the molecular level. DNase I footprints reveal that both H-NS and VirF bind to a region including the icsA and RnaG promoters. H-NS is shown to repress icsA transcription at 30°C but not at 37°C, suggesting a significant involvement of this protein in the temperature-regulated expression of icsA. We also demonstrate that VirF directly stimulates icsA transcription and is able to alleviate H-NS repression in vitro. According to these results, icsA expression is derepressed in hns- background and overexpressed when VirF is provided in trans. Moreover, we find that RnaG-mediated transcription attenuation depends on 80 nt at its 5'-end, a stretch carrying the antisense region. Bases engaged in the initial contact leading to sense-antisense pairing have been identified using synthetic RNA and DNA oligonucleotides designed to rebuild and mutagenize the two stem-loop motifs of the antisense region.

Stitch-bond parallel-gap welding for IC circuits

NASA Technical Reports Server (NTRS)

Chvostal, P.; Tuttle, J.; Vanderpool, R.

1980-01-01

Stitch-bonded flatpacks are superior to soldered dual-in-lines where size, weight, and reliability are important. Results should interest designers of packaging for complex high-reliability electronics, such as that used in security systems, industrial process control, and vehicle electronics.

Radiation-hardened transistor and integrated circuit

DOEpatents

Ma, Kwok K.

2007-11-20

A composite transistor is disclosed for use in radiation hardening a CMOS IC formed on an SOI or bulk semiconductor substrate. The composite transistor has a circuit transistor and a blocking transistor connected in series with a common gate connection. A body terminal of the blocking transistor is connected only to a source terminal thereof, and to no other connection point. The blocking transistor acts to prevent a single-event transient (SET) occurring in the circuit transistor from being coupled outside the composite transistor. Similarly, when a SET occurs in the blocking transistor, the circuit transistor prevents the SET from being coupled outside the composite transistor. N-type and P-type composite transistors can be used for each and every transistor in the CMOS IC to radiation harden the IC, and can be used to form inverters and transmission gates which are the building blocks of CMOS ICs.

A Physics-Based Approach for Power Integrity in Multi-Layered PCBs

NASA Astrophysics Data System (ADS)

Zhao, Biyao

Developing a power distribution network (PDN) for ASICs and ICs to achieve the low-voltage ripple specifications for current digital designs is challenging with the high-speed and low-voltage ICs. Present methods are typically guided by best engineering practices for low impedance looking into the PDN from the IC. A pre-layout design methodology for power integrity in multi-layered PCB PDN geometry is proposed in the thesis. The PCB PDN geometry is segmented into four parts and every part is modelled using different methods based on the geometry details of the part. Physics-based circuit models are built for every part and the four parts are re-assembled into one model. The influence of geometry details is clearly revealed in this methodology. Based on the physics-based circuit mode, the procedures of using the pre-layout design methodology as a guideline during the PDN design is illustrated. Some common used geometries are used to build design space, and the design curves with the geometry details are provided to be a look up library for engineering use. The pre-layout methodology is based on the resonant cavity model of parallel planes for the cavity structures, and parallel-plane PEEC (PPP) for the irregular shaped plane inductance, and PEEC for the decoupling capacitor connection above the top most or bottom most power-return planes. PCB PDN is analyzed based on the input impedance looking into the PCB from the IC. The pre-layout design methodology can be used to obtain the best possible PCB PDN design. With the switching current profile, the target impedance can be selected to evaluate the PDN performance, and the frequency domain PDN input impedance can be used to obtain the voltage ripple in the time domain to give intuitive insight of the geometry impact on the voltage ripple.

Apparatus and method for defect testing of integrated circuits

DOEpatents

Cole, Jr., Edward I.; Soden, Jerry M.

2000-01-01

An apparatus and method for defect and failure-mechanism testing of integrated circuits (ICs) is disclosed. The apparatus provides an operating voltage, V.sub.DD, to an IC under test and measures a transient voltage component, V.sub.DDT, signal that is produced in response to switching transients that occur as test vectors are provided as inputs to the IC. The amplitude or time delay of the V.sub.DDT signal can be used to distinguish between defective and defect-free (i.e. known good) ICs. The V.sub.DDT signal is measured with a transient digitizer, a digital oscilloscope, or with an IC tester that is also used to input the test vectors to the IC. The present invention has applications for IC process development, for the testing of ICs during manufacture, and for qualifying ICs for reliability.

Thermally-isolated silicon-based integrated circuits and related methods

DOEpatents

Wojciechowski, Kenneth; Olsson, Roy H.; Clews, Peggy J.; Bauer, Todd

2017-05-09

Thermally isolated devices may be formed by performing a series of etches on a silicon-based substrate. As a result of the series of etches, silicon material may be removed from underneath a region of an integrated circuit (IC). The removal of the silicon material from underneath the IC forms a gap between remaining substrate and the integrated circuit, though the integrated circuit remains connected to the substrate via a support bar arrangement that suspends the integrated circuit over the substrate. The creation of this gap functions to release the device from the substrate and create a thermally-isolated integrated circuit.

Experimental and theoretical analysis of integrated circuit (IC) chips on flexible substrates subjected to bending

NASA Astrophysics Data System (ADS)

Chen, Ying; Yuan, Jianghong; Zhang, Yingchao; Huang, Yonggang; Feng, Xue

2017-10-01

The interfacial failure of integrated circuit (IC) chips integrated on flexible substrates under bending deformation has been studied theoretically and experimentally. A compressive buckling test is used to impose the bending deformation onto the interface between the IC chip and the flexible substrate quantitatively, after which the failed interface is investigated using scanning electron microscopy. A theoretical model is established based on the beam theory and a bi-layer interface model, from which an analytical expression of the critical curvature in relation to the interfacial failure is obtained. The relationships between the critical curvature, the material, and the geometric parameters of the device are discussed in detail, providing guidance for future optimization flexible circuits based on IC chips.

6H-SiC Transistor Integrated Circuits Demonstrating Prolonged Operation at 500 C

NASA Technical Reports Server (NTRS)

Neudeck, Philip G.; Spry, David J.; Chen, Liang-Yu; Chang, Carl W.; Beheim, Glenn M.; Okojie, Robert S.; Evans, Laura J.; Meredith, Roger; Ferrier, Terry; Krasowski, Michael J.;

Simulation of materials processing: Fantasy or reality?

NASA Technical Reports Server (NTRS)

Jenkins, Thomas J.; Bright, Victor M.

1994-01-01

This experiment introduces students to the application of computer-aided design (CAD) and analysis of materials processing in the context of integrated circuit (IC) fabrication. The fabrication of modern IC's is a complex process which consists of several sequential steps. These steps involve the precise control of processing variables such as temperature, humidity, and ambient gas composition. In essence, the particular process employed during the fabrication becomes a 'recipe'. Due to economic and other considerations, CAD is becoming an indispensable part of the development of new recipes for IC fabrication. In particular, this experiment permits the students to explore the CAD of the thermal oxidation of silicon.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wojciechowski, Kenneth; Olsson, Roy; Clews, Peggy J.

Thermally isolated devices may be formed by performing a series of etches on a silicon-based substrate. As a result of the series of etches, silicon material may be removed from underneath a region of an integrated circuit (IC). The removal of the silicon material from underneath the IC forms a gap between remaining substrate and the integrated circuit, though the integrated circuit remains connected to the substrate via a support bar arrangement that suspends the integrated circuit over the substrate. The creation of this gap functions to release the device from the substrate and create a thermally-isolated integrated circuit.

An Integrated Circuit for Simultaneous Extracellular Electrophysiology Recording and Optogenetic Neural Manipulation.

PubMed

Chen, Chang Hao; McCullagh, Elizabeth A; Pun, Sio Hang; Mak, Peng Un; Vai, Mang I; Mak, Pui In; Klug, Achim; Lei, Tim C

2017-03-01

The ability to record and to control action potential firing in neuronal circuits is critical to understand how the brain functions. The objective of this study is to develop a monolithic integrated circuit (IC) to record action potentials and simultaneously control action potential firing using optogenetics. A low-noise and high input impedance (or low input capacitance) neural recording amplifier is combined with a high current laser/light-emitting diode (LED) driver in a single IC. The low input capacitance of the amplifier (9.7 pF) was achieved by adding a dedicated unity gain stage optimized for high impedance metal electrodes. The input referred noise of the amplifier is [Formula: see text], which is lower than the estimated thermal noise of the metal electrode. Thus, the action potentials originating from a single neuron can be recorded with a signal-to-noise ratio of at least 6.6. The LED/laser current driver delivers a maximum current of 330 mA, which is adequate for optogenetic control. The functionality of the IC was tested with an anesthetized Mongolian gerbil and auditory stimulated action potentials were recorded from the inferior colliculus. Spontaneous firings of fifth (trigeminal) nerve fibers were also inhibited using the optogenetic protein Halorhodopsin. Moreover, a noise model of the system was derived to guide the design. A single IC to measure and control action potentials using optogenetic proteins is realized so that more complicated behavioral neuroscience research and the translational neural disorder treatments become possible in the future.

Experimental Durability Testing of 4H SiC JFET Integrated Circuit Technology at 727 C

NASA Technical Reports Server (NTRS)

Spry, David; Neudeck, Phil; Chen, Liangyu; Chang, Carl; Lukco, Dorothy; Beheim, Glenn M

2016-01-01

We have reported SiC integrated circuits (IC's) with two levels of metal interconnect that have demonstrated prolonged operation for thousands of hours at their intended peak ambient operational temperature of 500 C [1, 2]. However, it is recognized that testing of semiconductor microelectronics at temperatures above their designed operating envelope is vital to qualification. Towards this end, we previously reported operation of a 4H-SiC JFET IC ring oscillator on an initial fast thermal ramp test through 727 C [3]. However, this thermal ramp was not ended until a peak temperature of 880 C (well beyond failure) was attained. Further experiments are necessary to better understand failure mechanisms and upper temperature limit of this extreme-temperature capable 4H-SiC IC technology. Here we report on additional experimental testing of custom-packaged 4H-SiC JFET IC devices at temperatures above 500 C. In one test, the temperature was ramped and then held at 727 C, and the devices were periodically measured until electrical failure was observed. A 4H-SiC JFET on this chip electrically functioned with little change for around 25 hours at 727 C before rapid increases in device resistance caused failure. In a second test, devices from our next generation 4H-SiC JFET ICs were ramped up and then held at 700 C (which is below the maximum deposition temperature of the dielectrics). Three ring oscillators functioned for 8 hours at this temperature before degradation. In a third experiment, an alternative die attach of gold paste and package lid was used, and logic circuit operation was demonstrated for 143.5 hours at 700 C.

Experimental Durability Testing of 4H SiC JFET Integrated Circuit Technology at 727 Degrees Centigrade

NASA Technical Reports Server (NTRS)

Spry, David J.; Neudeck, Philip G.; Chen, Liangyu; Chang, Carl W.; Lukco, Dorothy; Beheim, Glenn M.

2016-01-01

We have reported SiC integrated circuits (ICs) with two levels of metal interconnect that have demonstrated prolonged operation for thousands of hours at their intended peak ambient operational temperature of 500 degrees Centigrade. However, it is recognized that testing of semiconductor microelectronics at temperatures above their designed operating envelope is vital to qualification. Towards this end, we previously reported operation of a 4H-SiC JFET IC ring oscillator on an initial fast thermal ramp test through 727 degrees Centigrade. However, this thermal ramp was not ended until a peak temperature of 880 degrees Centigrade (well beyond failure) was attained. Further experiments are necessary to better understand failure mechanisms and upper temperature limit of this extreme-temperature capable 4H-SiC IC technology.Here we report on additional experimental testing of custom-packaged 4H-SiC JFET IC devices at temperatures above 500 degrees Centigrade. In one test, the temperature was ramped and then held at 727 degrees Centigrade, and the devices were periodically measured until electrical failure was observed. A 4H-SiC JFET on this chip electrically functioned with little change for around 25 hours at 727 degrees Centigrade before rapid increases in device resistance caused failure. In a second test, devices from our next generation 4H-SiC JFET ICs were ramped up and then held at 700 degrees Centigrade (which is below the maximum deposition temperature of the dielectrics). Three ring oscillators functioned for 8 hours at this temperature before degradation. In a third experiment, an alternative die attach of gold paste and package lid was used, and logic circuit operation was demonstrated for 143.5 hours at 700 degrees Centigrade.

The use of hybrid integrated circuit techniques in biotelemetry applications

NASA Technical Reports Server (NTRS)

Fryer, T. B.

1977-01-01

A review is presented of some features of hybrid integrated circuits that make their use advantageous in miniature biotelemetry applications. The various techniques for fabricating resistors, capacitors and interconnections by both thin film and thick film technology are discussed. The use of chip capacitors, resistors, and especially standard IC chips on substrates with fired-on interconnection patterns is emphasized. The review is designed primarily to acquaint biotelemetry users and designers with an overview of this fabrication technique so that they can better communicate their needs with an understanding of its limitations and advantages to facilities specializing in hybrid construction.

Accelerating functional verification of an integrated circuit

DOEpatents

Deindl, Michael; Ruedinger, Jeffrey Joseph; Zoellin, Christian G.

2015-10-27

Illustrative embodiments include a method, system, and computer program product for accelerating functional verification in simulation testing of an integrated circuit (IC). Using a processor and a memory, a serial operation is replaced with a direct register access operation, wherein the serial operation is configured to perform bit shifting operation using a register in a simulation of the IC. The serial operation is blocked from manipulating the register in the simulation of the IC. Using the register in the simulation of the IC, the direct register access operation is performed in place of the serial operation.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Deng, Junjing; Hong, Young Pyo; Chen, Si

Modern integrated circuits (ICs) employ a myriad of materials organized at nanoscale dimensions, and certain critical tolerances must be met for them to function. To understand departures from intended functionality, it is essential to examine ICs as manufactured so as to adjust design rules ideally in a nondestructive way so that imaged structures can be correlated with electrical performance. Electron microscopes can do this on thin regions or on exposed surfaces, but the required processing alters or even destroys functionality. Microscopy with multi-keV x-rays provides an alternative approach with greater penetration, but the spatial resolution of x-ray imaging lenses hasmore » not allowed one to see the required detail in the latest generation of ICs. X-ray ptychography provides a way to obtain images of ICs without lens-imposed resolution limits with past work delivering 20–40-nm resolution on thinned ICs. We describe a simple model for estimating the required exposure and use it to estimate the future potential for this technique. Here we show that this approach can be used to image circuit detail through an unprocessed 300-μm-thick silicon wafer with sub-20-nm detail clearly resolved after mechanical polishing to 240-μm thickness was used to eliminate image contrast caused by Si wafer surface scratches. Here, by using continuous x-ray scanning, massively parallel computation, and a new generation of synchrotron light sources, this should enable entire nonetched ICs to be imaged to 10-nm resolution or better while maintaining their ability to function in electrical tests.« less

Optical waveguide circuit board with a surface-mounted optical receiver array

NASA Astrophysics Data System (ADS)

Thomson, J. E.; Levesque, Harold; Savov, Emil; Horwitz, Fred; Booth, Bruce L.; Marchegiano, Joseph E.

1994-03-01

A photonic circuit board is fabricated for potential application to interchip and interboard parallel optical links. The board comprises photolithographically patterned polymer optical waveguides on a conventional glass-epoxy electrical circuit board and a surface-mounted integrated circuit (IC) package that optically and electrically couples to an optoelectronic IC. The waveguide circuits include eight-channel arrays of straights, cross-throughs, curves, self- aligning interconnects to multi-fiber ribbon, and out-of-plane turning mirrors. A coherent, fused bundle of optical fibers couples light between 45-deg waveguide mirrors and a GaAs receiver array in the IC package. The fiber bundle is easily aligned to the mirrors and the receivers and is amenable to surface mounting and hermetic sealing. The waveguide-receiver- array board achieved error-free data rates up to 1.25 Gbits/s per channel, and modal noise was shown to be negligible.

Novel Low Loss Wide-Band Multi-Port Integrated Circuit Technology for RF/Microwave Applications

NASA Technical Reports Server (NTRS)

Simons, Rainee N.; Goverdhanam, Kavita; Katehi, Linda P. B.; Burke, Thomas P. (Technical Monitor)

2001-01-01

In this paper, novel low loss, wide-band coplanar stripline technology for radio frequency (RF)/microwave integrated circuits is demonstrated on high resistivity silicon wafer. In particular, the fabrication process for the deposition of spin-on-glass (SOG) as a dielectric layer, the etching of microvias for the vertical interconnects, the design methodology for the multiport circuits and their measured/simulated characteristics are graphically illustrated. The study shows that circuits with very low loss, large bandwidth, and compact size are feasible using this technology. This multilayer planar technology has potential to significantly enhance RF/microwave IC performance when combined with semi-conductor devices and microelectromechanical systems (MEMS).

Radiation-Hardened Electronics for Advanced Communications Systems

NASA Technical Reports Server (NTRS)

Whitaker, Sterling

2015-01-01

Novel approach enables high-speed special-purpose processors Advanced reconfigurable and reprogrammable communication systems will require sub-130-nanometer electronics. Legacy single event upset (SEU) radiation-tolerant circuits are ineffective at speeds greater than 125 megahertz. In Phase I of this project, ICs, LLC, demonstrated new base-level logic circuits that provide SEU immunity for sub-130-nanometer high-speed circuits. In Phase II, the company developed an innovative self-restoring logic (SRL) circuit and a system approach that provides high-speed, SEU-tolerant solutions that are effective for sub-130-nanometer electronics scalable to at least 22-nanometer processes. The SRL system can be used in the design of NASA's next-generation special-purpose processors, especially reconfigurable communication processors.

Semiconductor/High-Tc-Superconductor Hybrid ICs

NASA Technical Reports Server (NTRS)

Burns, Michael J.

1995-01-01

Hybrid integrated circuits (ICs) containing both Si-based semiconducting and YBa(2)Cu(3)O(7-x) superconducting circuit elements on sapphire substrates developed. Help to prevent diffusion of Cu from superconductors into semiconductors. These hybrid ICs combine superconducting and semiconducting features unavailable in superconducting or semiconducting circuitry alone. For example, complementary metal oxide/semiconductor (CMOS) readout and memory devices integrated with fast-switching Josephson-junction super-conducting logic devices and zero-resistance interconnections.

A bipolar analog front-end integrated circuit for the SDC silicon tracker

NASA Astrophysics Data System (ADS)

Kipnis, I.; Spieler, H.; Collins, T.

1993-11-01

A low noise, low power, high bandwidth, radiation hard, silicon bipolar transistor full-custom integrated circuit (IC) containing 64 channels of analog signal processing has been developed for the SDC silicon tracker. The IC was designed and tested at LBL and was fabricated using CBIC-U2, 4 GHz f(sub T) complementary bipolar technology. Each channel contains the following functions: low noise preamplification, pulse shaping, and threshold discrimination. This is the first iteration of the production analog IC for the SDC silicon tracker. The IC is laid out to directly match the 50 micron pitch double-sided silicon strip detector. The chip measures 6.8 mm by 3.1 mm and contains 3,600 transistors. Three stages of amplification provide 180 mV/fC of gain with a 35 nsec peaking time at the comparator input. For a 14 pF detector capacitance, the equivalent noise charge is 1300 el. rms at a power consumption of 1 mW/channel from a single 3.5 V supply. With the discriminator threshold set to four times the noise level, a 16 nsec time-walk for 1.25 to 10 fC signals is achieved using a time-walk compensation network. Irradiation tests at TRIUMF to a Phi = 10(exp 14) protons/sq cm have been performed on the IC, demonstrating the radiation hardness of the complementary bipolar process.

Encapsulate-and-peel: fabricating carbon nanotube CMOS integrated circuits in a flexible ultra-thin plastic film.

PubMed

Gao, Pingqi; Zhang, Qing

2014-02-14

Fabrication of single-walled carbon nanotube thin film (SWNT-TF) based integrated circuits (ICs) on soft substrates has been challenging due to several processing-related obstacles, such as printed/transferred SWNT-TF pattern and electrode alignment, electrical pad/channel material/dielectric layer flatness, adherence of the circuits onto the soft substrates etc. Here, we report a new approach that circumvents these challenges by encapsulating pre-formed SWNT-TF-ICs on hard substrates into polyimide (PI) and peeling them off to form flexible ICs on a large scale. The flexible SWNT-TF-ICs show promising performance comparable to those circuits formed on hard substrates. The flexible p- and n-type SWNT-TF transistors have an average mobility of around 60 cm(2) V(-1) s(-1), a subthreshold slope as low as 150 mV dec(-1), operating gate voltages less than 2 V, on/off ratios larger than 10(4) and a switching speed of several kilohertz. The post-transfer technique described here is not only a simple and cost-effective pathway to realize scalable flexible ICs, but also a feasible method to fabricate flexible displays, sensors and solar cells etc.

Nonlinear relaxation algorithms for circuit simulation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Saleh, R.A.

Circuit simulation is an important Computer-Aided Design (CAD) tool in the design of Integrated Circuits (IC). However, the standard techniques used in programs such as SPICE result in very long computer-run times when applied to large problems. In order to reduce the overall run time, a number of new approaches to circuit simulation were developed and are described. These methods are based on nonlinear relaxation techniques and exploit the relative inactivity of large circuits. Simple waveform-processing techniques are described to determine the maximum possible speed improvement that can be obtained by exploiting this property of large circuits. Three simulation algorithmsmore » are described, two of which are based on the Iterated Timing Analysis (ITA) method and a third based on the Waveform-Relaxation Newton (WRN) method. New programs that incorporate these techniques were developed and used to simulate a variety of industrial circuits. The results from these simulations are provided. The techniques are shown to be much faster than the standard approach. In addition, a number of parallel aspects of these algorithms are described, and a general space-time model of parallel-task scheduling is developed.« less

A Integrated Circuit for a Biomedical Capacitive Pressure Transducer

NASA Astrophysics Data System (ADS)

Smith, Michael John Sebastian

Medical research has an urgent need for a small, accurate, stable, low-power, biocompatible and inexpensive pressure sensor with a zero to full-scale range of 0-300 mmHg. An integrated circuit (IC) for use with a capacitive pressure transducer was designed, built and tested. The random pressure measurement error due to resolution and non-linearity is (+OR-)0.4 mmHg (at mid-range with a full -scale of 300 mmHg). The long-term systematic error due to falling battery voltage is (+OR-)0.6 mmHg. These figures were calculated from measurements of temperature, supply dependence and non-linearity on completed integrated circuits. The sensor IC allows measurement of temperature to (+OR-)0.1(DEGREES)C to allow for temperature compensation of the transducer. Novel micropower circuit design of the system components enabled these levels of accuracy to be reached. Capacitance is measured by a new ratiometric scheme employing an on -chip reference capacitor. This method greatly reduces the effects of voltage supply, temperature and manufacturing variations on the sensor circuit performance. The limits on performance of the bandgap reference circuit fabricated with a standard bipolar process using ion-implanted resistors were determined. Measurements confirm the limits of temperature stability as approximately (+OR-)300 ppm/(DEGREES)C. An exact analytical expression for the period of the Schmitt trigger oscillator, accounting for non-constant capacitor charging current, was formulated. Experiments to test agreement with theory showed that prediction of the oscillator period was very accurate. The interaction of fundamental and practical limits on the scaling of the transducer size was investigated including a correction to previous theoretical analysis of jitter in an RC oscillator. An areal reduction of 4 times should be achievable.

Technology CAD for integrated circuit fabrication technology development and technology transfer

NASA Astrophysics Data System (ADS)

Saha, Samar

2003-07-01

In this paper systematic simulation-based methodologies for integrated circuit (IC) manufacturing technology development and technology transfer are presented. In technology development, technology computer-aided design (TCAD) tools are used to optimize the device and process parameters to develop a new generation of IC manufacturing technology by reverse engineering from the target product specifications. While in technology transfer to manufacturing co-location, TCAD is used for process centering with respect to high-volume manufacturing equipment of the target manufacturing equipment of the target manufacturing facility. A quantitative model is developed to demonstrate the potential benefits of the simulation-based methodology in reducing the cycle time and cost of typical technology development and technology transfer projects over the traditional practices. The strategy for predictive simulation to improve the effectiveness of a TCAD-based project, is also discussed.

Very High Speed Integrated Circuits (VHSIC).

DTIC Science & Technology

1987-12-31

types with minor modification. The module has been designed both in the SEM-E format and the 3/4 Air Transport Regulation (ATR) format for new...a step that ensures that VHSIC designs ’ ’, documented in the VHDL will be readily transportable throughout the commercial and military IC design...maintain high reliability specifications in a standardized, transportable , andI:compiter-accessible format and to automatically generate test programs. This

Data encryption standard ASIC design and development report.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Robertson, Perry J.; Pierson, Lyndon George; Witzke, Edward L.

2003-10-01

This document describes the design, fabrication, and testing of the SNL Data Encryption Standard (DES) ASIC. This device was fabricated in Sandia's Microelectronics Development Laboratory using 0.6 {micro}m CMOS technology. The SNL DES ASIC was modeled using VHDL, then simulated, and synthesized using Synopsys, Inc. software and finally IC layout was performed using Compass Design Automation's CAE tools. IC testing was performed by Sandia's Microelectronic Validation Department using a HP 82000 computer aided test system. The device is a single integrated circuit, pipelined realization of DES encryption and decryption capable of throughputs greater than 6.5 Gb/s. Several enhancements accommodate ATMmore » or IP network operation and performance scaling. This design is the latest step in the evolution of DES modules.« less

Determination of thermal properties of commercial Ni-MH cells

NASA Astrophysics Data System (ADS)

Darcy, Eric C.

1994-02-01

The test objectives were to evaluate the electrical and thermal performance of commercial Ni-MH cells, evaluate the effectiveness of commercial charge control circuits, assess the abuse tolerance of these cells, and correlate performance and abuse tolerances to cell design via disassembly. Design objectives were to determine which cell designs are most suitable for scale-up and to guide the design of future shuttle and space station based battery chargers. Results, displayed in viewgraph format, include: reflex charging with ICS circuit resulted in premature charge termination; Ni-MH cells appear very tolerant to overcharge at low rates; Enstore's charger is more electrically and thermally efficient at high rates; and Ni-MH cycles much more efficiently than Ni-Cd with the delta-V/delta-t termination.

Determination of thermal properties of commercial Ni-MH cells

NASA Technical Reports Server (NTRS)

Darcy, Eric C.

1994-01-01

The test objectives were to evaluate the electrical and thermal performance of commercial Ni-MH cells, evaluate the effectiveness of commercial charge control circuits, assess the abuse tolerance of these cells, and correlate performance and abuse tolerances to cell design via disassembly. Design objectives were to determine which cell designs are most suitable for scale-up and to guide the design of future shuttle and space station based battery chargers. Results, displayed in viewgraph format, include: reflex charging with ICS circuit resulted in premature charge termination; Ni-MH cells appear very tolerant to overcharge at low rates; Enstore's charger is more electrically and thermally efficient at high rates; and Ni-MH cycles much more efficiently than Ni-Cd with the delta-V/delta-t termination.

Novel Vertical Interconnects With 180 Degree Phase Shift for Amplifiers, Filters, and Integrated Antennas

NASA Technical Reports Server (NTRS)

Goverdhanam, Kavita; Simons, Rainee N.; Katehi, Linda P. B.; Burke, Thomas P. (Technical Monitor)

2001-01-01

In this paper, novel low loss, wide-band coplanar stripline technology for RF/microwave integrated circuits is demonstrated on high resistivity silicon wafer. In particular, the fabrication process for the deposition of spin-on-glass (SOG) as a dielectric layer, the etching of microvias for the vertical interconnects, the design methodology for the multiport circuits and their measured/simulated characteristics are graphically illustrated. The study shows that circuits with very low loss, large bandwidth and compact size are feasible using this technology. This multilayer planar technology has potential to significantly enhance RF/microwave IC performance when combined with semiconductor devices and microelectromechanical systems (MEMS).

The National Si-Soft Project

NASA Astrophysics Data System (ADS)

Chang, Chun-Yen; Trappey, Charles V.

2003-06-01

Taiwan's electronics industry emerged in the 1960s with the creation of a small but well planned integrated circuit (IC) packaging industry. This industry investment led to bolder investments in research, laboratories, and the island's first semiconductor foundries in the 1980s. Following the success of the emerging IC manufacturers and design houses, hundreds of service firms and related industries (software, legal services, substrate, chemical, and test firms among others) opened for business and completed Taiwan's IC manufacturing supply chain. The challenge for Taiwan's electronics industry is to take the lead in the design, manufacture, and marketing of name brand electronic products. This paper introduces the Si-Soft (silicon software) Project, a national initiative that builds on Taiwan's achievements in manufacturing (referred to as Si-Hard or silicon hardware) to launch a new wave of companies. These firms will contribute to the core underlying technology (intellectual property) used in the creation of electronic products.

System-on-Chip Considerations for Heterogeneous Integration of CMOS and Fluidic Bio-Interfaces.

PubMed

Datta-Chaudhuri, Timir; Smela, Elisabeth; Abshire, Pamela A

2016-12-01

CMOS chips are increasingly used for direct sensing and interfacing with fluidic and biological systems. While many biosensing systems have successfully combined CMOS chips for readout and signal processing with passive sensing arrays, systems that co-locate sensing with active circuits on a single chip offer significant advantages in size and performance but increase the complexity of multi-domain design and heterogeneous integration. This emerging class of lab-on-CMOS systems also poses distinct and vexing technical challenges that arise from the disparate requirements of biosensors and integrated circuits (ICs). Modeling these systems must address not only circuit design, but also the behavior of biological components on the surface of the IC and any physical structures. Existing tools do not support the cross-domain simulation of heterogeneous lab-on-CMOS systems, so we recommend a two-step modeling approach: using circuit simulation to inform physics-based simulation, and vice versa. We review the primary lab-on-CMOS implementation challenges and discuss practical approaches to overcome them. Issues include new versions of classical challenges in system-on-chip integration, such as thermal effects, floor-planning, and signal coupling, as well as new challenges that are specifically attributable to biological and fluidic domains, such as electrochemical effects, non-standard packaging, surface treatments, sterilization, microfabrication of surface structures, and microfluidic integration. We describe these concerns as they arise in lab-on-CMOS systems and discuss solutions that have been experimentally demonstrated.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Shah, Kedar G.; Pannu, Satinderpall S.

An integrated circuit system having an integrated circuit (IC) component which is able to have its functionality destroyed upon receiving a command signal. The system may involve a substrate with the IC component being supported on the substrate. A module may be disposed in proximity to the IC component. The module may have a cavity and a dissolving compound in a solid form disposed in the cavity. A heater component may be configured to heat the dissolving compound to a point of sublimation where the dissolving compound changes from a solid to a gaseous dissolving compound. A triggering mechanism maymore » be used for initiating a dissolution process whereby the gaseous dissolving compound is allowed to attack the IC component and destroy a functionality of the IC component.« less

An analog front-end bipolar-transistor integrated circuit for the SDC silicon tracker

NASA Astrophysics Data System (ADS)

Kipnis, I.; Spieler, H.; Collins, T.

1994-08-01

A low-noise, low-power, high-bandwidth, radiation hard, silicon bipolar-transistor full-custom integrated circuit (IC) containing 64 channels of analog signal processing has been developed for the SDC silicon tracker The IC was designed and tested at LBL and was fabricated using AT&T's CBIC-U2, 4 GHz f/sub /spl tau// complementary bipolar technology. Each channel contains the following functions: low-noise preamplification, pulse shaping and threshold discrimination. This is the first iteration of the production analog IC for the SDC silicon tracker. The IC is laid out to directly match the 50 /spl mu/m pitch double-sided silicon strip detector. The chip measures 6.8 mm/spl times/3.1 mm and contains 3,600 transistors. Three stages of amplification provide 180 mV/fC of gain with a 35 nsec peaking time at the comparator input. For a 14 pF detector capacitance, the equivalent noise charge is 1300 el. RMS at a power consumption of 1 mW/channel from a single 3.5 V supply. With the discriminator threshold set to 4 times the noise level, a 16 nsec time-walk for 1.25 to 10 fC signals is achieved using a time-walk compensation network. Irradiation tests at TRIUMF to a /spl Phi/=10/sup 14/ protons/cm/sup 2/ have been performed on the IC, demonstrating the radiation hardness of the complementary bipolar process.

SEM probe of IC radiation sensitivity

NASA Technical Reports Server (NTRS)

Gauthier, M. K.; Stanley, A. G.

1979-01-01

Scanning Electron Microscope (SEM) used to irradiate single integrated circuit (IC) subcomponent to test for radiation sensitivity can localize area of IC less than .03 by .03 mm for determination of exact location of radiation sensitive section.

Evidence of Processing Non-Idealities in 4H-SiC Integrated Circuits Fabricated with Two Levels of Metal Interconnect

NASA Technical Reports Server (NTRS)

Spry, David J.; Neudeck, Philip G.; Liangyu, Chen; Evans, Laura J.; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.

2015-01-01

The fabrication and prolonged 500 C electrical testing of 4H-SiC junction field effect transistor (JFET) integrated circuits (ICs) with two levels of metal interconnect is reported in another submission to this conference proceedings. While some circuits functioned more than 1000 hours at 500 C, the majority of packaged ICs from this wafer electrically failed after less than 200 hours of operation in the same test conditions. This work examines the root physical degradation and failure mechanisms believed responsible for observed large discrepancies in 500 C operating time. Evidence is presented for four distinct issues that significantly impacted 500 C IC operational yield and lifetime for this wafer.

Evidence of Processing Non-Idealities in 4H-SiC Integrated Circuits Fabricated With Two Levels of Metal Interconnect

NASA Technical Reports Server (NTRS)

Spry, David J.; Neudeck, Philip G.; Chen, Liangyu; Evans, Laura J.; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.

2015-01-01

The fabrication and prolonged 500 C electrical testing of 4H-SiC junction field effect transistor (JFET) integrated circuits (ICs) with two levels of metal interconnect is reported in another submission to this conference proceedings. While some circuits functioned more than 3000 hours at 500 C, the majority of packaged ICs from this wafer electrically failed after less than 200 hours of operation in the same test conditions. This work examines the root physical degradation and failure mechanisms believed responsible for observed large discrepancies in 500 C operating time. Evidence is presented for four distinct issues that significantly impacted 500 C IC operational yield and lifetime for this wafer.

Nano-engineered Multiwall Carbon Nanotube-copper Composite Thermal Interface Material for Efficient Heat Conduction

NASA Technical Reports Server (NTRS)

Ngo, Quoc; Cruden, Brett A.; Cassell, Alan M.; Sims, Gerard; Li, Jun; Meyyappa, M.; Yang, Cary Y.

2005-01-01

Efforts in integrated circuit (IC) packaging technologies have recently been focused on management of increasing heat density associated with high frequency and high density circuit designs. While current flip-chip package designs can accommodate relatively high amounts of heat density, new materials need to be developed to manage thermal effects of next-generation integrated circuits. Multiwall carbon nanotubes (MWNT) have been shown to significantly enhance thermal conduction in the axial direction and thus can be considered to be a candidate for future thermal interface materials by facilitating efficient thermal transport. This work focuses on fabrication and characterization of a robust MWNT-copper composite material as an element in IC package designs. We show that using vertically aligned MWNT arrays reduces interfacial thermal resistance by increasing conduction surface area, and furthermore, the embedded copper acts as a lateral heat spreader to efficiently disperse heat, a necessary function for packaging materials. In addition, we demonstrate reusability of the material, and the absence of residue on the contacting material, both novel features of the MWNT-copper composite that are not found in most state-of-the-art thermal interface materials. Electrochemical methods such as metal deposition and etch are discussed for the creation of the MWNT-Cu composite, detailing issues and observations with using such methods. We show that precise engineering of the composite surface affects the ability of this material to act as an efficient thermal interface material. A thermal contact resistance measurement has been designed to obtain a value of thermal contact resistance for a variety of different thermal contact materials.

The basic circuit of the IC: tectothalamic neurons with different patterns of synaptic organization send different messages to the thalamus

PubMed Central

Ito, Tetsufumi; Oliver, Douglas L.

2012-01-01

The inferior colliculus (IC) in the midbrain of the auditory system uses a unique basic circuit to organize the inputs from virtually all of the lower auditory brainstem and transmit this information to the medial geniculate body (MGB) in the thalamus. Here, we review the basic circuit of the IC, the neuronal types, the organization of their inputs and outputs. We specifically discuss the large GABAergic (LG) neurons and how they differ from the small GABAergic (SG) and the more numerous glutamatergic neurons. The somata and dendrites of LG neurons are identified by axosomatic glutamatergic synapses that are lacking in the other cell types and exclusively contain the glutamate transporter VGLUT2. Although LG neurons are most numerous in the central nucleus of the IC (ICC), an analysis of their distribution suggests that they are not specifically associated with one set of ascending inputs. The inputs to ICC may be organized into functional zones with different subsets of brainstem inputs, but each zone may contain the same three neuron types. However, the sources of VGLUT2 axosomatic terminals on the LG neuron are not known. Neurons in the dorsal cochlear nucleus, superior olivary complex, intermediate nucleus of the lateral lemniscus, and IC itself that express the gene for VGLUT2 only are the likely origin of the dense VGLUT2 axosomatic terminals on LG tectothalamic neurons. The IC is unique since LG neurons are GABAergic tectothalamic neurons in addition to the numerous glutamatergic tectothalamic neurons. SG neurons evidently target other auditory structures. The basic circuit of the IC and the LG neurons in particular, has implications for the transmission of information about sound through the midbrain to the MGB. PMID:22855671

High-Performance Complementary Transistors and Medium-Scale Integrated Circuits Based on Carbon Nanotube Thin Films.

PubMed

Yang, Yingjun; Ding, Li; Han, Jie; Zhang, Zhiyong; Peng, Lian-Mao

2017-04-25

Solution-derived carbon nanotube (CNT) network films with high semiconducting purity are suitable materials for the wafer-scale fabrication of field-effect transistors (FETs) and integrated circuits (ICs). However, it is challenging to realize high-performance complementary metal-oxide semiconductor (CMOS) FETs with high yield and stability on such CNT network films, and this difficulty hinders the development of CNT-film-based ICs. In this work, we developed a doping-free process for the fabrication of CMOS FETs based on solution-processed CNT network films, in which the polarity of the FETs was controlled using Sc or Pd as the source/drain contacts to selectively inject carriers into the channels. The fabricated top-gated CMOS FETs showed high symmetry between the characteristics of n- and p-type devices and exhibited high-performance uniformity and excellent scalability down to a gate length of 1 μm. Many common types of CMOS ICs, including typical logic gates, sequential circuits, and arithmetic units, were constructed based on CNT films, and the fabricated ICs exhibited rail-to-rail outputs because of the high noise margin of CMOS circuits. In particular, 4-bit full adders consisting of 132 CMOS FETs were realized with 100% yield, thereby demonstrating that this CMOS technology shows the potential to advance the development of medium-scale CNT-network-film-based ICs.

Guidelines for Design and Test of a Built-In Self Test (BIST) Circuit For Space Radiation Studies of High-Speed IC Technologies

NASA Technical Reports Server (NTRS)

Carts, M. A.; Marshall, P. W.; Reed, R.; Curie, S.; Randall, B.; LaBel, K.; Gilbert, B.; Daniel, E.

2006-01-01

Serial Bit Error Rate Testing under radiation to characterize single particle induced errors in high-speed IC technologies generally involves specialized test equipment common to the telecommunications industry. As bit rates increase, testing is complicated by the rapidly increasing cost of equipment able to test at-speed. Furthermore as rates extend into the tens of billions of bits per second test equipment ceases to be broadband, a distinct disadvantage for exploring SEE mechanisms in the target technologies. In this presentation the authors detail the testing accomplished in the CREST project and apply the knowledge gained to establish a set of guidelines suitable for designing arbitrarily high speed radiation effects tests.

A multi-scale PDMS fabrication strategy to bridge the size mismatch between integrated circuits and microfluidics†

PubMed Central

Muluneh, Melaku

2015-01-01

In recent years there has been great progress harnessing the small-feature size and programmability of integrated circuits (ICs) for biological applications, by building microfluidics directly on top of ICs. However, a major hurdle to the further development of this technology is the inherent size-mismatch between ICs (~mm) and microfluidic chips (~cm). Increasing the area of the ICs to match the size of the microfluidic chip, as has often been done in previous studies, leads to a waste of valuable space on the IC and an increase in fabrication cost (>100×). To address this challenge, we have developed a three dimensional PDMS chip that can straddle multiple length scales of hybrid IC/microfluidic chips. This approach allows millimeter-scale ICs, with no post-processing, to be integrated into a centimeter-sized PDMS chip. To fabricate this PDMS chip we use a combination of soft-lithography and laser micromachining. Soft lithography was used to define micrometer-scale fluid channels directly on the surface of the IC, allowing fluid to be controlled with high accuracy and brought into close proximity to sensors for highly sensitive measurements. Laser micromachining was used to create ~50 μm vias to connect these molded PDMS channels to a larger PDMS chip, which can connect multiple ICs and house fluid connections to the outside world. To demonstrate the utility of this approach, we built and demonstrated an in-flow magnetic cytometer that consisted of a 5 × 5 cm2 microfluidic chip that incorporated a commercial 565 × 1145 μm2 IC with a GMR sensing circuit. We additionally demonstrated the modularity of this approach by building a chip that incorporated two of these GMR chips connected in series. PMID:25284502

A multi-scale PDMS fabrication strategy to bridge the size mismatch between integrated circuits and microfluidics.

PubMed

Muluneh, Melaku; Issadore, David

2014-12-07

In recent years there has been great progress harnessing the small-feature size and programmability of integrated circuits (ICs) for biological applications, by building microfluidics directly on top of ICs. However, a major hurdle to the further development of this technology is the inherent size-mismatch between ICs (~mm) and microfluidic chips (~cm). Increasing the area of the ICs to match the size of the microfluidic chip, as has often been done in previous studies, leads to a waste of valuable space on the IC and an increase in fabrication cost (>100×). To address this challenge, we have developed a three dimensional PDMS chip that can straddle multiple length scales of hybrid IC/microfluidic chips. This approach allows millimeter-scale ICs, with no post-processing, to be integrated into a centimeter-sized PDMS chip. To fabricate this PDMS chip we use a combination of soft-lithography and laser micromachining. Soft lithography was used to define micrometer-scale fluid channels directly on the surface of the IC, allowing fluid to be controlled with high accuracy and brought into close proximity to sensors for highly sensitive measurements. Laser micromachining was used to create ~50 μm vias to connect these molded PDMS channels to a larger PDMS chip, which can connect multiple ICs and house fluid connections to the outside world. To demonstrate the utility of this approach, we built and demonstrated an in-flow magnetic cytometer that consisted of a 5 × 5 cm(2) microfluidic chip that incorporated a commercial 565 × 1145 μm(2) IC with a GMR sensing circuit. We additionally demonstrated the modularity of this approach by building a chip that incorporated two of these GMR chips connected in series.

A low-power CMOS operational amplifier IC for a heterogeneous paper-based potentiostat

NASA Astrophysics Data System (ADS)

Bezuidenhout, P.; Land, K.; Joubert, T.-H.

2016-02-01

Electrochemical biosensing is used to detect specific analytes in fluids, such as bacterial and chemical contaminants. A common implementation of an electrochemical readout is a potentiostat, which usually includes potentiometric, amperometric, and impedimetric detection. Recently several researchers have developed small, low-cost, single-chip silicon-based potentiostats. With the advances in heterogeneous integration technology, low-power potentiostats can be implemented on paper and similar low cost substrates. This paper deals with the design of a low-power paper-based amperometric front-end for a low-cost and rapid detection environment. In amperometric detection a voltage signal is provided to a sensor system, while a small current value generated by an electrochemical redox reaction in the system is measured. In order to measure low current values, the noise of the circuit must be minimized, which is accomplished with a pre-amplification front-end stage, typically designed around an operational amplifier core. An appropriate circuit design for a low-power and low-cost amperometric front-end is identified, taking the heterogeneous integration of various components into account. The operational amplifier core is on a bare custom CMOS chip, which will be integrated onto the paper substrate alongside commercial off-the-shelf electronic components. A general-purpose low-power two-stage CMOS amplifier circuit is designed and simulated for the ams 350 nm 5 V process. After the layout design and verification, the IC was submitted for a multi-project wafer manufacturing run. The simulated results are a bandwidth of 2.4 MHz, a common-mode rejection ratio of 70.04 dB, and power dissipation of 0.154 mW, which are comparable with the analytical values.

Designing skin response meter for psycho galvanic reflex

NASA Astrophysics Data System (ADS)

Dhokalia, Dhruv M.; Atreya, Parul; Kumar, Arun

2011-12-01

Human skin offers some resistance to current and voltage. This resistance changes with the emotional state of the body. The circuit proposed here measures changes in our skin resistance following changes in our mental state. In the relaxed state, the resistance offered by the skin is as high as 2 mega-ohms or more, which reduces to 500 kilo-ohms or less when the emotional stress is too high. The reduction in skin resistance is related to increased blood flow and permeability followed by the physiological changes during high stress. This increases the electrical conductivity of the skin. This circuit is useful to monitor the skin's response to relaxation techniques. It is very sensitive and shows response during a sudden moment of stress. Even a deep sigh will give response in the circuit. The circuit uses a sensitive amplifier to sense variations in the skin resistance. IC CA3140 is designed as a resistance- to-voltage converter that outputs varying voltage based on the skin's conductivity.

Low-Power Analog Processing for Sensing Applications: Low-Frequency Harmonic Signal Classification

PubMed Central

White, Daniel J.; William, Peter E.; Hoffman, Michael W.; Balkir, Sina

2013-01-01

A low-power analog sensor front-end is described that reduces the energy required to extract environmental sensing spectral features without using Fast Fouriér Transform (FFT) or wavelet transforms. An Analog Harmonic Transform (AHT) allows selection of only the features needed by the back-end, in contrast to the FFT, where all coefficients must be calculated simultaneously. We also show that the FFT coefficients can be easily calculated from the AHT results by a simple back-substitution. The scheme is tailored for low-power, parallel analog implementation in an integrated circuit (IC). Two different applications are tested with an ideal front-end model and compared to existing studies with the same data sets. Results from the military vehicle classification and identification of machine-bearing fault applications shows that the front-end suits a wide range of harmonic signal sources. Analog-related errors are modeled to evaluate the feasibility of and to set design parameters for an IC implementation to maintain good system-level performance. Design of a preliminary transistor-level integrator circuit in a 0.13 μm complementary metal-oxide-silicon (CMOS) integrated circuit process showed the ability to use online self-calibration to reduce fabrication errors to a sufficiently low level. Estimated power dissipation is about three orders of magnitude less than similar vehicle classification systems that use commercially available FFT spectral extraction. PMID:23892765

Processing and Characterization of Thousand-Hour 500 C Durable 4H-SiC JFET Integrated Circuits

NASA Technical Reports Server (NTRS)

Spry, David J.; Neudeck, Philip G.; Chen, Liangyu; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.; Krasowski, Michael J.; Prokop, Norman F.

2016-01-01

This work reports fabrication and testing of integrated circuits (ICs) with two levels of interconnect that consistently achieve greater than 1000 hours of stable electrical operation at 500 C in air ambient. These ICs are based on 4H-SiC junction field effect transistor (JFET) technology that integrates hafnium ohmic contacts with TaSi2 interconnects and SiO2 and Si3N4 dielectric layers over 1-m scale vertical topology. Following initial burn-in, important circuit parameters remain stable for more than 1000 hours of 500 C operational testing. These results advance the technology foundation for realizing long-term durable 500 C ICs with increased functional capability for sensing and control combustion engine, planetary, deep-well drilling, and other harsh-environment applications.

Processing and Characterization of Thousand-Hour 500 C Durable 4H-SiC JFET Integrated Circuits

NASA Technical Reports Server (NTRS)

Spry, David J.; Neudeck, Philip G.; Chen, Liang-Yu; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.; Krasowski, Michael J.; Prokop, Norman F.

2016-01-01

This work reports fabrication and testing of integrated circuits (ICs) with two levels of interconnect that consistently achieve greater than 1000 hours of stable electrical operation at 500 C in air ambient. These ICs are based on 4H-SiC junction field effect transistor (JFET) technology that integrates hafnium ohmic contacts with TaSi2 interconnects and SiO2 and Si3N4 dielectric layers over approximately 1-micrometer scale vertical topology. Following initial burn-in, important circuit parameters remain stable for more than 1000 hours of 500 C operational testing. These results advance the technology foundation for realizing long-term durable 500 C ICs with increased functional capability for sensing and control combustion engine, planetary, deep-well drilling, and other harsh-environment applications.

Graphene/Si CMOS Hybrid Hall Integrated Circuits

PubMed Central

Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

2014-01-01

Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18 um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process. PMID:24998222

Graphene/Si CMOS hybrid hall integrated circuits.

PubMed

Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

2014-07-07

Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18 um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process.

Hardware Design and Implementation of a Wavelet De-Noising Procedure for Medical Signal Preprocessing

PubMed Central

Chen, Szi-Wen; Chen, Yuan-Ho

2015-01-01

In this paper, a discrete wavelet transform (DWT) based de-noising with its applications into the noise reduction for medical signal preprocessing is introduced. This work focuses on the hardware realization of a real-time wavelet de-noising procedure. The proposed de-noising circuit mainly consists of three modules: a DWT, a thresholding, and an inverse DWT (IDWT) modular circuits. We also proposed a novel adaptive thresholding scheme and incorporated it into our wavelet de-noising procedure. Performance was then evaluated on both the architectural designs of the software and. In addition, the de-noising circuit was also implemented by downloading the Verilog codes to a field programmable gate array (FPGA) based platform so that its ability in noise reduction may be further validated in actual practice. Simulation experiment results produced by applying a set of simulated noise-contaminated electrocardiogram (ECG) signals into the de-noising circuit showed that the circuit could not only desirably meet the requirement of real-time processing, but also achieve satisfactory performance for noise reduction, while the sharp features of the ECG signals can be well preserved. The proposed de-noising circuit was further synthesized using the Synopsys Design Compiler with an Artisan Taiwan Semiconductor Manufacturing Company (TSMC, Hsinchu, Taiwan) 40 nm standard cell library. The integrated circuit (IC) synthesis simulation results showed that the proposed design can achieve a clock frequency of 200 MHz and the power consumption was only 17.4 mW, when operated at 200 MHz. PMID:26501290

Hardware design and implementation of a wavelet de-noising procedure for medical signal preprocessing.

PubMed

Chen, Szi-Wen; Chen, Yuan-Ho

2015-10-16

In this paper, a discrete wavelet transform (DWT) based de-noising with its applications into the noise reduction for medical signal preprocessing is introduced. This work focuses on the hardware realization of a real-time wavelet de-noising procedure. The proposed de-noising circuit mainly consists of three modules: a DWT, a thresholding, and an inverse DWT (IDWT) modular circuits. We also proposed a novel adaptive thresholding scheme and incorporated it into our wavelet de-noising procedure. Performance was then evaluated on both the architectural designs of the software and. In addition, the de-noising circuit was also implemented by downloading the Verilog codes to a field programmable gate array (FPGA) based platform so that its ability in noise reduction may be further validated in actual practice. Simulation experiment results produced by applying a set of simulated noise-contaminated electrocardiogram (ECG) signals into the de-noising circuit showed that the circuit could not only desirably meet the requirement of real-time processing, but also achieve satisfactory performance for noise reduction, while the sharp features of the ECG signals can be well preserved. The proposed de-noising circuit was further synthesized using the Synopsys Design Compiler with an Artisan Taiwan Semiconductor Manufacturing Company (TSMC, Hsinchu, Taiwan) 40 nm standard cell library. The integrated circuit (IC) synthesis simulation results showed that the proposed design can achieve a clock frequency of 200 MHz and the power consumption was only 17.4 mW, when operated at 200 MHz.

Method and apparatus to debug an integrated circuit chip via synchronous clock stop and scan

DOEpatents

Bellofatto, Ralph E [Ridgefield, CT; Ellavsky, Matthew R [Rochester, MN; Gara, Alan G [Mount Kisco, NY; Giampapa, Mark E [Irvington, NY; Gooding, Thomas M [Rochester, MN; Haring, Rudolf A [Cortlandt Manor, NY; Hehenberger, Lance G [Leander, TX; Ohmacht, Martin [Yorktown Heights, NY

2012-03-20

An apparatus and method for evaluating a state of an electronic or integrated circuit (IC), each IC including one or more processor elements for controlling operations of IC sub-units, and each the IC supporting multiple frequency clock domains. The method comprises: generating a synchronized set of enable signals in correspondence with one or more IC sub-units for starting operation of one or more IC sub-units according to a determined timing configuration; counting, in response to one signal of the synchronized set of enable signals, a number of main processor IC clock cycles; and, upon attaining a desired clock cycle number, generating a stop signal for each unique frequency clock domain to synchronously stop a functional clock for each respective frequency clock domain; and, upon synchronously stopping all on-chip functional clocks on all frequency clock domains in a deterministic fashion, scanning out data values at a desired IC chip state. The apparatus and methodology enables construction of a cycle-by-cycle view of any part of the state of a running IC chip, using a combination of on-chip circuitry and software.

Toward printed integrated circuits based on unipolar or ambipolar polymer semiconductors.

PubMed

Baeg, Kang-Jun; Caironi, Mario; Noh, Yong-Young

2013-08-21

For at least the past ten years printed electronics has promised to revolutionize our daily life by making cost-effective electronic circuits and sensors available through mass production techniques, for their ubiquitous applications in wearable components, rollable and conformable devices, and point-of-care applications. While passive components, such as conductors, resistors and capacitors, had already been fabricated by printing techniques at industrial scale, printing processes have been struggling to meet the requirements for mass-produced electronics and optoelectronics applications despite their great potential. In the case of logic integrated circuits (ICs), which constitute the focus of this Progress Report, the main limitations have been represented by the need of suitable functional inks, mainly high-mobility printable semiconductors and low sintering temperature conducting inks, and evoluted printing tools capable of higher resolution, registration and uniformity than needed in the conventional graphic arts printing sector. Solution-processable polymeric semiconductors are the best candidates to fulfill the requirements for printed logic ICs on flexible substrates, due to their superior processability, ease of tuning of their rheology parameters, and mechanical properties. One of the strongest limitations has been mainly represented by the low charge carrier mobility (μ) achievable with polymeric, organic field-effect transistors (OFETs). However, recently unprecedented values of μ ∼ 10 cm(2) /Vs have been achieved with solution-processed polymer based OFETs, a value competing with mobilities reported in organic single-crystals and exceeding the performances enabled by amorphous silicon (a-Si). Interestingly these values were achieved thanks to the design and synthesis of donor-acceptor copolymers, showing limited degree of order when processed in thin films and therefore fostering further studies on the reason leading to such improved charge transport properties. Among this class of materials, various polymers can show well balanced electrons and holes mobility, therefore being indicated as ambipolar semiconductors, good environmental stability, and a small band-gap, which simplifies the tuning of charge injection. This opened up the possibility of taking advantage of the superior performances offered by complementary "CMOS-like" logic for the design of digital ICs, easing the scaling down of critical geometrical features, and achieving higher complexity from robust single gates (e.g., inverters) and test circuits (e.g., ring oscillators) to more complete circuits. Here, we review the recent progress in the development of printed ICs based on polymeric semiconductors suitable for large-volume micro- and nano-electronics applications. Particular attention is paid to the strategies proposed in the literature to design and synthesize high mobility polymers and to develop suitable printing tools and techniques to allow for improved patterning capability required for the down-scaling of devices in order to achieve the operation frequencies needed for applications, such as flexible radio-frequency identification (RFID) tags, near-field communication (NFC) devices, ambient electronics, and portable flexible displays. Copyright © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

FInal Technical Repot of the Project: Design and Implementation of Low-Power 10Gb/s/channel Laser/Silicon Photonics Modulator Drivers with SEU Tolerance for HL-LHC

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gui, Ping

During the funding period of this award from May 1, 2014 through March 30, 2016, we have accomplished the design, implementation and measurement results of two laser driver chips: LpGBLD10+ which is a low-power single-channel 10Gb/s laser driver IC, and LDQ10P, which is a 4x10Gb/s driver array chip for High Energy Physics (HEP) applications. With new circuit techniques, the driver consumes a record-low power consumption, 31 mW @10Gb/s/channel and occupies a small area of 400 µm × 1750 µm for the single-channel driver IC and 1900umx1700um for the LDQ10P chip. These characteristics allow for both the LpGBLD10+ ICs and LDQ10P suitable candidatemore » for the Versatile Link PLUS (VL+) project, offering flexibility in configuring multiple Transmitters and receivers.« less

Sensor readout detector circuit

DOEpatents

Chu, Dahlon D.; Thelen, Jr., Donald C.

1998-01-01

A sensor readout detector circuit is disclosed that is capable of detecting sensor signals down to a few nanoamperes or less in a high (microampere) background noise level. The circuit operates at a very low standby power level and is triggerable by a sensor event signal that is above a predetermined threshold level. A plurality of sensor readout detector circuits can be formed on a substrate as an integrated circuit (IC). These circuits can operate to process data from an array of sensors in parallel, with only data from active sensors being processed for digitization and analysis. This allows the IC to operate at a low power level with a high data throughput for the active sensors. The circuit may be used with many different types of sensors, including photodetectors, capacitance sensors, chemically-sensitive sensors or combinations thereof to provide a capability for recording transient events or for recording data for a predetermined period of time following an event trigger. The sensor readout detector circuit has applications for portable or satellite-based sensor systems.

Sensor readout detector circuit

DOEpatents

Chu, D.D.; Thelen, D.C. Jr.

1998-08-11

A sensor readout detector circuit is disclosed that is capable of detecting sensor signals down to a few nanoamperes or less in a high (microampere) background noise level. The circuit operates at a very low standby power level and is triggerable by a sensor event signal that is above a predetermined threshold level. A plurality of sensor readout detector circuits can be formed on a substrate as an integrated circuit (IC). These circuits can operate to process data from an array of sensors in parallel, with only data from active sensors being processed for digitization and analysis. This allows the IC to operate at a low power level with a high data throughput for the active sensors. The circuit may be used with many different types of sensors, including photodetectors, capacitance sensors, chemically-sensitive sensors or combinations thereof to provide a capability for recording transient events or for recording data for a predetermined period of time following an event trigger. The sensor readout detector circuit has applications for portable or satellite-based sensor systems. 6 figs.

Recent progress in low-temperature-process monolithic three dimension technology

NASA Astrophysics Data System (ADS)

Yang, Chih-Chao; Hsieh, Tung-Ying; Huang, Wen-Hsien; Shen, Chang-Hong; Shieh, Jia-Min; Yeh, Wen-Kuan; Wu, Meng-Chyi

2018-04-01

Monolithic three-dimension (3D) integration is an ultimate alternative method of fabricating high density, high performance, and multi-functional integrated circuits. It offers the promise of being a new approach to increase system performance. How to manage the thermal impact of multi-tiered processes, such as dopant activation, source/drain silicidation, and channel formation, and to prevent the degradation of pre-existing devices/circuits become key challenges. In this paper, we provide updates on several important monolithic 3D works, particularly in sequentially stackable channels, and our recent achievements in monolithic 3D integrated circuit (3D-IC). These results indicate that the advanced 3D architecture with novel design tools enables ultrahigh-density stackable circuits to have superior performance and low power consumption for future artificial intelligence (AI) and internet of things (IoTs) application.

Self-Patterning of Silica/Epoxy Nanocomposite Underfill by Tailored Hydrophilic-Superhydrophobic Surfaces for 3D Integrated Circuit (IC) Stacking.

PubMed

Tuan, Chia-Chi; James, Nathan Pataki; Lin, Ziyin; Chen, Yun; Liu, Yan; Moon, Kyoung-Sik; Li, Zhuo; Wong, C P

2017-03-15

As microelectronics are trending toward smaller packages and integrated circuit (IC) stacks nowadays, underfill, the polymer composite filled in between the IC chip and the substrate, becomes increasingly important for interconnection reliability. However, traditional underfills cannot meet the requirements for low-profile and fine pitch in high density IC stacking packages. Post-applied underfills have difficulties in flowing into the small gaps between the chip and the substrate, while pre-applied underfills face filler entrapment at bond pads. In this report, we present a self-patterning underfilling technology that uses selective wetting of underfill on Cu bond pads and Si 3 N 4 passivation via surface energy engineering. This novel process, fully compatible with the conventional underfilling process, eliminates the issue of filler entrapment in typical pre-applied underfilling process, enabling high density and fine pitch IC die bonding.

A Microcomputer-Based Program for Printing Check Plots of Integrated Circuits Specified in Caltech Intermediate Form.

DTIC Science & Technology

1984-12-01

only four transistors[5]. Each year since that time, the semiconductor industry has con- sistently improved the quality of the fabrication tech- niques...rarely took place at universities and was almost exclusively confined to industry . IC design techniques were developed, tested, and taught only in the...community, it is not uncommon for industry to borrow ideas and even particular programs from these university designed tools. The Very Large Scale Integration

Missile Defense Information Technology Small Business Conference

DTIC Science & Technology

2009-09-01

NetOps Survivability 4 • Supported User Base • Number of Workstations • Number of Servers • Number of Special Circuits • Number of Sites • Number...Contracts, MDIOC • Ground Test (DTC) • MDSEC (SS) • Infrastructure (IC) • BMDS Support (BCT) • JTAAS – SETA • Mod & Sim ( DES ) • Analysis (GML) • Tenants...AUG 09) 4 MDA DOCE Engineering Functions • Design Engineers – Develop detailed design artifacts based on architectural specifications – Coordinate

Assessment of SOI Devices and Circuits at Extreme Temperatures

NASA Technical Reports Server (NTRS)

Elbuluk, Malik; Hammoud, Ahmad; Patterson, Richard L.

2007-01-01

Electronics designed for use in future NASA space exploration missions are expected to encounter extreme temperatures and wide thermal swings. Such missions include planetary surface exploration, bases, rovers, landers, orbiters, and satellites. Electronics designed for such applications must, therefore, be able to withstand exposure to extreme temperatures and to perform properly for the duration of mission. The Low Temperature Electronics Program at the NASA Glenn Research Center focuses on research and development of electrical devices, circuits, and systems suitable for applications in deep space exploration missions and aerospace environment. Silicon-On-Insulator (SOI) technology has been under active consideration in the electronics industry for many years due to the advantages that it can provide in integrated circuit (IC) chips and computer processors. Faster switching, less power, radiationtolerance, reduced leakage, and high temp-erature capability are some of the benefits that are offered by using SOI-based devices. A few SOI circuits are available commercially. However, there is a noticeable interest in SOI technology for different applications. Very little data, however, exist on the performance of such circuits under cryogenic temperatures. In this work, the performance of SOI integrated circuits, evaluated under low temperature and thermal cycling, are reported. In particular, three examples of SOI circuits that have been tested for operation at low at temperatures are given. These circuits are SOI operational amplifiers, timers and power MOSFET drivers. The investigations were carried out to establish a baseline on the functionality and to determine suitability of these circuits for use in space exploration missions at cryogenic temperatures. The findings are useful to mission planners and circuit designers so that proper selection of electronic parts can be made, and risk assessment can be established for such circuits for use in space missions.

50 Years of ``Scaling'' Jack Kilby's Invention

NASA Astrophysics Data System (ADS)

Doering, Robert

2008-03-01

This year is the 50th anniversary of Jack Kilby's 1958 invention of the integrated circuit (IC), for which he won the 2000 Nobel Prize in Physics. Since that invention in a laboratory at Texas Instruments, IC components have been continuously miniaturized, which has resulted in exponential improvement trends in their performance, energy efficiency, and cost per function. These improvements have created a semiconductor industry that has grown to over 250B in annual sales. The process of reducing integrated-circuit component size and associated parameters in a coordinated fashion is traditionally called ``feature-size scaling.'' Kilby's original circuit had active (transistor) and passive (resistor, capacitor) components with dimensions of a few millimeters. Today, the minimum feature sizes on integrated circuits are less than 30 nanometers for patterned line widths and down to about one nanometer for film thicknesses. Thus, we have achieved about five orders of magnitude in linear-dimension scaling over the past fifty years, which has resulted in about ten orders of magnitude increase in the density of IC components, a representation of ``Moore's Law.'' As IC features are approaching atomic dimensions, increasing emphasis is now being given to the parallel effort of further diversifying the types of components in integrated circuits. This is called ``functional scaling'' and ``more then Moore.'' Of course, the enablers for both types of scaling have been developed at many laboratories around the world. This talk will review a few of the highlights in scaling and its applications from R&D projects at Texas Instruments.

Emergency OSL/TL dosimetry with integrated circuits from mobile phones

NASA Astrophysics Data System (ADS)

Sholom, S.; McKeever, S. W. S.

2014-09-01

Integrated circuits (ICs) from several mobile phones were studied as possible emergency dosimeters using optically stimulated luminescence (OSL) and thermoluminescence (TL) techniques. Measurement protocols were developed for ICs that take into consideration the effect of sensitization of the samples with increasing dose as well as fading of the signals after sample exposure. It was found that the OSL technique has a higher sensitivity with ICs when compared to TL, while the TL signals were characterized by better stability with time after exposure. Values of minimum measurable doses were found to be in the range between a few tens of mGy and several tens of mGy for the tested samples. It was concluded that ICs from mobile phones could be used for emergency dose reconstruction.

Scaling of graphene integrated circuits.

PubMed

Bianchi, Massimiliano; Guerriero, Erica; Fiocco, Marco; Alberti, Ruggero; Polloni, Laura; Behnam, Ashkan; Carrion, Enrique A; Pop, Eric; Sordan, Roman

2015-05-07

The influence of transistor size reduction (scaling) on the speed of realistic multi-stage integrated circuits (ICs) represents the main performance metric of a given transistor technology. Despite extensive interest in graphene electronics, scaling efforts have so far focused on individual transistors rather than multi-stage ICs. Here we study the scaling of graphene ICs based on transistors from 3.3 to 0.5 μm gate lengths and with different channel widths, access lengths, and lead thicknesses. The shortest gate delay of 31 ps per stage was obtained in sub-micron graphene ROs oscillating at 4.3 GHz, which is the highest oscillation frequency obtained in any strictly low-dimensional material to date. We also derived the fundamental Johnson limit, showing that scaled graphene ICs could be used at high frequencies in applications with small voltage swing.

A reuse-based framework for the design of analog and mixed-signal ICs

NASA Astrophysics Data System (ADS)

Castro-Lopez, Rafael; Fernandez, Francisco V.; Rodriguez Vazquez, Angel

2005-06-01

Despite the spectacular breakthroughs of the semiconductor industry, the ability to design integrated circuits (ICs) under stringent time-to-market (TTM) requirements is lagging behind integration capacity, so far keeping pace with still valid Moore"s Law. The resulting gap is threatening with slowing down such a phenomenal growth. The design community believes that it is only by means of powerful CAD tools and design methodologies - and, possibly, a design paradigm shift - that this design gap can be bridged. In this sense, reuse-based design is seen as a promising solution, and concepts such as IP Block, Virtual Component, and Design Reuse have become commonplace thanks to the significant advances in the digital arena. Unfortunately, the very nature of analog and mixed-signal (AMS) design has hindered a similar level of consensus and development. This paper presents a framework for the reuse-based design of AMS circuits. The framework is founded on three key elements: (1) a CAD-supported hierarchical design flow that facilitates the incorporation of AMS reusable blocks, reduces the overall design time, and expedites the management of increasing AMS design complexity; (2) a complete, clear definition of the AMS reusable block, structured into three separate facets or views: the behavioral, structural, and layout facets, the two first for top-down electrical synthesis and bottom-up verification, the latter used during bottom-up physical synthesis; (3) the design for reusability set of tools, methods, and guidelines that, relying on intensive parameterization as well as on design knowledge capture and encapsulation, allows to produce fully reusable AMS blocks. A case study and a functional silicon prototype demonstrate the validity of the paper"s proposals.

Field Programmable Gate Array Reliability Analysis Guidelines for Launch Vehicle Reliability Block Diagrams

NASA Technical Reports Server (NTRS)

Al Hassan, Mohammad; Britton, Paul; Hatfield, Glen Spencer; Novack, Steven D.

2017-01-01

Field Programmable Gate Arrays (FPGAs) integrated circuits (IC) are one of the key electronic components in today's sophisticated launch and space vehicle complex avionic systems, largely due to their superb reprogrammable and reconfigurable capabilities combined with relatively low non-recurring engineering costs (NRE) and short design cycle. Consequently, FPGAs are prevalent ICs in communication protocols and control signal commands. This paper will identify reliability concerns and high level guidelines to estimate FPGA total failure rates in a launch vehicle application. The paper will discuss hardware, hardware description language, and radiation induced failures. The hardware contribution of the approach accounts for physical failures of the IC. The hardware description language portion will discuss the high level FPGA programming languages and software/code reliability growth. The radiation portion will discuss FPGA susceptibility to space environment radiation.

Prolonged 500 C Operation of 100+ Transistor Silicon Carbide Integrated Circuits

NASA Technical Reports Server (NTRS)

Spry, David J.; Neudeck, Philip G.; Lukco, Dorothy; Chen, Liangyu; Krasowski, Michael J.; Prokop, Norman F.; Chang, Carl W.; Beheim, Glenn M.

2017-01-01

This report describes more than 5000 hours of successful 500 C operation of semiconductor integrated circuits (ICs) with more than 100 transistors. Multiple packaged chips with two different 4H-SiC junction field effect transistor (JFET) technology demonstrator circuits have surpassed thousands of hours of oven-testing at 500 C. After 100 hours of 500 C burn-in, the circuits (except for 2 failures) exhibit less than 10% change in output characteristics for the remainder of 500 C testing. We also describe the observation of important differences in IC materials durability when subjected to the first nine constituents of Venus-surface atmosphere at 9.4 MPa and 460 C in comparison to what is observed for Earth-atmosphere oven testing at 500 C.

Prolonged 500 C Operation of 100+ Transistor Silicon Carbide Integrated Circuits

NASA Technical Reports Server (NTRS)

Spry, David J.; Neudeck, Philip G.; Lukco, Dorothy; Chen, Liangyu; Krasowski, Michael J.; Prokop, Norman F.; Chang, Carl W.; Beheim, Glenn M.

2017-01-01

This report describes more than 5000 hours of successful 500 C operation of semiconductor integrated circuits (ICs) with more than 100 transistors. Multiple packaged chips with two different 4H-SiC junction field effect transistor (JFET) technology demonstrator circuits have surpassed thousands of hours of oven-testing at 500 C. After 100 hours of 500 C burn-in, the circuits (except for 2 failures) exhibit less than 10 change in output characteristics for the remainder of 500C testing. We also describe the observation of important differences in IC materials durability when subjected to the first nine constituents of Venus-surface atmosphere at 9.4 MPa and 460C in comparison to what is observed for Earth-atmosphere oven testing at 500 C.

Modularized construction of general integrated circuits on individual carbon nanotubes.

PubMed

Pei, Tian; Zhang, Panpan; Zhang, Zhiyong; Qiu, Chenguang; Liang, Shibo; Yang, Yingjun; Wang, Sheng; Peng, Lian-Mao

2014-06-11

While constructing general integrated circuits (ICs) with field-effect transistors (FETs) built on individual CNTs is among few viable ways to build ICs with small dimension and high performance that can be compared with that of state-of-the-art Si based ICs, this has not been demonstrated owing to the absence of valid and well-tolerant fabrication method. Here we demonstrate a modularized method for constructing general ICs on individual CNTs with different electric properties. A pass-transistor-logic style 8-transistor (8-T) unit is built, demonstrated as a multifunctional function generator with good tolerance to inhomogeneity in the CNTs used and used as a building block for constructing general ICs. As an example, an 8-bits BUS system that is widely used to transfer data between different systems in a computer is constructed. This is the most complicated IC fabricated on individual CNTs to date, containing 46 FETs built on six individual semiconducting CNTs. The 8-T unit provides a good basis for constructing complex ICs to explore the potential and limits of CNT ICs given the current imperfection in available CNT materials and may also be developed into a universal and efficient way for constructing general ICs on ideal CNT materials in the future.

III-V-on-Silicon Photonic Integrated Circuits for Spectroscopic Sensing in the 2-4 μm Wavelength Range.

PubMed

Wang, Ruijun; Vasiliev, Anton; Muneeb, Muhammad; Malik, Aditya; Sprengel, Stephan; Boehm, Gerhard; Amann, Markus-Christian; Šimonytė, Ieva; Vizbaras, Augustinas; Vizbaras, Kristijonas; Baets, Roel; Roelkens, Gunther

2017-08-04

The availability of silicon photonic integrated circuits (ICs) in the 2-4 μm wavelength range enables miniature optical sensors for trace gas and bio-molecule detection. In this paper, we review our recent work on III-V-on-silicon waveguide circuits for spectroscopic sensing in this wavelength range. We first present results on the heterogeneous integration of 2.3 μm wavelength III-V laser sources and photodetectors on silicon photonic ICs for fully integrated optical sensors. Then a compact 2 μm wavelength widely tunable external cavity laser using a silicon photonic IC for the wavelength selective feedback is shown. High-performance silicon arrayed waveguide grating spectrometers are also presented. Further we show an on-chip photothermal transducer using a suspended silicon-on-insulator microring resonator used for mid-infrared photothermal spectroscopy.

III–V-on-Silicon Photonic Integrated Circuits for Spectroscopic Sensing in the 2–4 μm Wavelength Range

PubMed Central

Wang, Ruijun; Vasiliev, Anton; Muneeb, Muhammad; Malik, Aditya; Sprengel, Stephan; Boehm, Gerhard; Amann, Markus-Christian; Šimonytė, Ieva; Vizbaras, Augustinas; Vizbaras, Kristijonas; Baets, Roel; Roelkens, Gunther

2017-01-01

The availability of silicon photonic integrated circuits (ICs) in the 2–4 μm wavelength range enables miniature optical sensors for trace gas and bio-molecule detection. In this paper, we review our recent work on III–V-on-silicon waveguide circuits for spectroscopic sensing in this wavelength range. We first present results on the heterogeneous integration of 2.3 μm wavelength III–V laser sources and photodetectors on silicon photonic ICs for fully integrated optical sensors. Then a compact 2 μm wavelength widely tunable external cavity laser using a silicon photonic IC for the wavelength selective feedback is shown. High-performance silicon arrayed waveguide grating spectrometers are also presented. Further we show an on-chip photothermal transducer using a suspended silicon-on-insulator microring resonator used for mid-infrared photothermal spectroscopy. PMID:28777291

Tailoring femtosecond 1.5-μm Bessel beams for manufacturing high-aspect-ratio through-silicon vias

NASA Astrophysics Data System (ADS)

He, Fei; Yu, Junjie; Tan, Yuanxin; Chu, Wei; Zhou, Changhe; Cheng, Ya; Sugioka, Koji

2017-01-01

Three-dimensional integrated circuits (3D ICs) are an attractive replacement for conventional 2D ICs as high-performance, low-power-consumption, and small-footprint microelectronic devices. However, one of the major remaining challenges is the manufacture of high-aspect-ratio through-silicon vias (TSVs), which is a crucial technology for the assembly of 3D Si ICs. Here, we present the fabrication of high-quality TSVs using a femtosecond (fs) 1.5-μm Bessel beam. To eliminate the severe ablation caused by the sidelobes of a conventional Bessel beam, a fs Bessel beam is tailored using a specially designed binary phase plate. We demonstrate that the tailored fs Bessel beam can be used to fabricate a 2D array of approximately ∅10-μm TSVs on a 100-μm-thick Si substrate without any sidelobe damage, suggesting potential application in the 3D assembly of 3D Si ICs.

Tailoring femtosecond 1.5-μm Bessel beams for manufacturing high-aspect-ratio through-silicon vias.

PubMed

He, Fei; Yu, Junjie; Tan, Yuanxin; Chu, Wei; Zhou, Changhe; Cheng, Ya; Sugioka, Koji

2017-01-18

Three-dimensional integrated circuits (3D ICs) are an attractive replacement for conventional 2D ICs as high-performance, low-power-consumption, and small-footprint microelectronic devices. However, one of the major remaining challenges is the manufacture of high-aspect-ratio through-silicon vias (TSVs), which is a crucial technology for the assembly of 3D Si ICs. Here, we present the fabrication of high-quality TSVs using a femtosecond (fs) 1.5-μm Bessel beam. To eliminate the severe ablation caused by the sidelobes of a conventional Bessel beam, a fs Bessel beam is tailored using a specially designed binary phase plate. We demonstrate that the tailored fs Bessel beam can be used to fabricate a 2D array of approximately ∅10-μm TSVs on a 100-μm-thick Si substrate without any sidelobe damage, suggesting potential application in the 3D assembly of 3D Si ICs.

CMOS Imaging of Pin-Printed Xerogel-Based Luminescent Sensor Microarrays.

PubMed

Yao, Lei; Yung, Ka Yi; Khan, Rifat; Chodavarapu, Vamsy P; Bright, Frank V

2010-12-01

We present the design and implementation of a luminescence-based miniaturized multisensor system using pin-printed xerogel materials which act as host media for chemical recognition elements. We developed a CMOS imager integrated circuit (IC) to image the luminescence response of the xerogel-based sensor array. The imager IC uses a 26 × 20 (520 elements) array of active pixel sensors and each active pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. The imager includes a correlated double sampling circuit and pixel address/digital control circuit; the image data is read-out as coded serial signal. The sensor system uses a light-emitting diode (LED) to excite the target analyte responsive luminophores doped within discrete xerogel-based sensor elements. As a prototype, we developed a 4 × 4 (16 elements) array of oxygen (O 2 ) sensors. Each group of 4 sensor elements in the array (arranged in a row) is designed to provide a different and specific sensitivity to the target gaseous O 2 concentration. This property of multiple sensitivities is achieved by using a strategic mix of two oxygen sensitive luminophores ([Ru(dpp) 3 ] 2+ and ([Ru(bpy) 3 ] 2+ ) in each pin-printed xerogel sensor element. The CMOS imager consumes an average power of 8 mW operating at 1 kHz sampling frequency driven at 5 V. The developed prototype system demonstrates a low cost and miniaturized luminescence multisensor system.

Layout-aware simulation of soft errors in sub-100 nm integrated circuits

NASA Astrophysics Data System (ADS)

Balbekov, A.; Gorbunov, M.; Bobkov, S.

2016-12-01

Single Event Transient (SET) caused by charged particle traveling through the sensitive volume of integral circuit (IC) may lead to different errors in digital circuits in some cases. In technologies below 180 nm, a single particle can affect multiple devices causing multiple SET. This fact adds the complexity to fault tolerant devices design, because the schematic design techniques become useless without their layout consideration. The most common layout mitigation technique is a spatial separation of sensitive nodes of hardened circuits. Spatial separation decreases the circuit performance and increases power consumption. Spacing should thus be reasonable and its scaling follows the device dimensions' scaling trend. This paper presents the development of the SET simulation approach comprised of SPICE simulation with "double exponent" current source as SET model. The technique uses layout in GDSII format to locate nearby devices that can be affected by a single particle and that can share the generated charge. The developed software tool automatizes multiple simulations and gathers the produced data to present it as the sensitivity map. The examples of conducted simulations of fault tolerant cells and their sensitivity maps are presented in this paper.

How thin barrier metal can be used to prevent Co diffusion in the modern integrated circuits?

NASA Astrophysics Data System (ADS)

Dixit, Hemant; Konar, Aniruddha; Pandey, Rajan; Ethirajan, Tamilmani

2017-11-01

In modern integrated circuits (ICs), billions of transistors are connected to each other via thin metal layers (e.g. copper, cobalt, etc) known as interconnects. At elevated process temperatures, inter-diffusion of atomic species can occur among these metal layers, causing sub-optimal performance of interconnects, which may lead to the failure of an IC. Thus, typically a thin barrier metal layer is used to prevent the inter-diffusion of atomic species within interconnects. For ICs with sub-10 nm transistors (10 nm technology node), the design rule (thickness scaling) demands the thinnest possible barrier layer. Therefore, here we investigate the critical thickness of a titanium-nitride (TiN) barrier that can prevent the cobalt diffusion using multi-scale modeling and simulations. First, we compute the Co diffusion barrier in crystalline and amorphous TiN with the nudged elastic band method within first-principles density functional theory simulations. Later, using the calculated activation energy barriers, we quantify the Co diffusion length in the TiN metal layer with the help of kinetic Monte Carlo simulations. Such a multi-scale modelling approach yields an exact critical thickness of the metal layer sufficient to prevent the Co diffusion in IC interconnects. We obtain a diffusion length of a maximum of 2 nm for a typical process of thermal annealing at 400 °C for 30 min. Our study thus provides useful physical insights for the Co diffusion in the TiN layer and further quantifies the critical thickness (~2 nm) to which the metal barrier layer can be thinned down for sub-10 nm ICs.

Initiative in Concurrent Engineering (DICE). Phase 1.

DTIC Science & Technology

1990-02-09

and power of commercial and military electronics systems. The continual evolution of HDE technology offers far greater flexibility in circuit design... powerful magnetic field of the permanent magnets in the sawyer motors. This makes it possible to have multiple robots in the workcell and to have them...Controller. The Adept IC was chosen because of its extensive processing power , integrated grayscale vision, standard 28 industrial I/O control

Eddy current measurement of the thickness of top Cu film of the multilayer interconnects in the integrated circuit (IC) manufacturing process

NASA Astrophysics Data System (ADS)

Qu, Zilian; Meng, Yonggang; Zhao, Qian

2015-03-01

This paper proposes a new eddy current method, named equivalent unit method (EUM), for the thickness measurement of the top copper film of multilayer interconnects in the chemical mechanical polishing (CMP) process, which is an important step in the integrated circuit (IC) manufacturing. The influence of the underneath circuit layers on the eddy current is modeled and treated as an equivalent film thickness. By subtracting this equivalent film component, the accuracy of the thickness measurement of the top copper layer with an eddy current sensor is improved and the absolute error is 3 nm for sampler measurement.

TDR method for determine IC's parameters

NASA Astrophysics Data System (ADS)

Timoshenkov, V.; Rodionov, D.; Khlybov, A.

2016-12-01

Frequency domain simulation is a widely used approach for determine integrated circuits parameters. This approach can be found in most of software tools used in IC industry. Time domain simulation approach shows intensive usage last years due to some advantages. In particular it applicable for analysis of nonlinear and nonstationary systems where frequency domain is inapplicable. Resolution of time domain systems allow see heterogeneities on distance 1mm, determine it parameters and properties. Authors used approach based on detecting reflected signals from heterogeneities - time domain reflectometry (TDR). Field effect transistor technology scaling up to 30-60nm gate length and 10nm gate dielectric, heterojunction bi-polar transistors with 10-30nm base width allows fabricate digital IC's with 20GHz clock frequency and RF-IC's with tens GHz bandwidth. Such devices and operation speed suppose transit signal by use microwave lines. There are local heterogeneities can be found inside of the signal path due to connections between different parts of signal lines (stripe line-RF-connector pin, stripe line - IC package pin). These heterogeneities distort signals that cause bandwidth decrease for RF-devices. Time domain research methods of transmission and reflected signals give the opportunities to determine heterogeneities, it properties, parameters and built up equivalent circuits. Experimental results are provided and show possibility for inductance and capacitance measurement up to 25GHz. Measurements contains result of signal path research on IC and printed circuit board (PCB) used for 12GHz RF chips. Also dielectric constant versus frequency was measured up to 35GHz.

All optical programmable logic array (PLA)

NASA Astrophysics Data System (ADS)

Hiluf, Dawit

2018-03-01

A programmable logic array (PLA) is an integrated circuit (IC) logic device that can be reconfigured to implement various kinds of combinational logic circuits. The device has a number of AND and OR gates which are linked together to give output or further combined with more gates or logic circuits. This work presents the realization of PLAs via the physics of a three level system interacting with light. A programmable logic array is designed such that a number of different logical functions can be combined as a sum-of-product or product-of-sum form. We present an all optical PLAs with the aid of laser light and observables of quantum systems, where encoded information can be considered as memory chip. The dynamics of the physical system is investigated using Lie algebra approach.

A Solder Based Self Assembly Project in an Introductory IC Fabrication Course

ERIC Educational Resources Information Center

Rao, Madhav; Lusth, John C.; Burkett, Susan L.

2015-01-01

Integrated circuit (IC) fabrication principles is an elective course in a senior undergraduate and early graduate student's curriculum. Over the years, the semiconductor industry relies heavily on students with developed expertise in the area of fabrication techniques, learned in an IC fabrication theory and laboratory course. The theory course…

Elevated voltage level I{sub DDQ} failure testing of integrated circuits

DOEpatents

Righter, A.W.

1996-05-21

Burn in testing of static CMOS IC`s is eliminated by I{sub DDQ} testing at elevated voltage levels. These voltage levels are at least 25% higher than the normal operating voltage for the IC but are below voltage levels that would cause damage to the chip. 4 figs.

An adiabatic quantum flux parametron as an ultra-low-power logic device

NASA Astrophysics Data System (ADS)

Takeuchi, Naoki; Ozawa, Dan; Yamanashi, Yuki; Yoshikawa, Nobuyuki

2013-03-01

Ultra-low-power adiabatic quantum flux parametron (QFP) logic is investigated since it has the potential to reduce the bit energy per operation to the order of the thermal energy. In this approach, nonhysteretic QFPs are operated slowly to prevent nonadiabatic energy dissipation occurring during switching events. The designed adiabatic QFP gate is estimated to have a dynamic energy dissipation of 12% of IcΦ0 for a rise/fall time of 1000 ps. It can be further reduced by reducing circuit inductances. Three stages of adiabatic QFP NOT gates were fabricated using a Nb Josephson integrated circuit process and their correct operation was confirmed.

Flip-flop resolving time test circuit

NASA Technical Reports Server (NTRS)

Rosenberger, F.; Chaney, T. J.

1982-01-01

Integrated circuit (IC) flip-flop resolving time parameters are measured by wafer probing, without need of dicing or bonding, throught the incorporation of test structures on an IC together with the flip-flop to be measured. Several delays that are fabricated as part of the test circuit, including a voltage-controlled delay with a resolution of a few picosecs, are calibrated as part of the test procedure by integrating them into, and out of, the delay path of a ring oscillator. Each of the delay values is calculated by subtracting the period of the ring oscillator with the delay omitted from the period with the delay included. The delay measurement technique is sufficiently general for other applications. The technique is illustrated for the case of the flip-flop parameters of a 5-micron feature size NMOS circuit.

Stable Electrical Operation of 6H-SiC JFETs and ICs for Thousands of Hours at 500 C

NASA Technical Reports Server (NTRS)

Neudeck, Philip G.; Spry, David J.; Chen, Liang-Yu; Beheim, Glenn M.; Okojie, Robert S.; Chang, Carl W.; Meredith, Roger D.; Ferrier, Terry L.; Evans, Laura J.; Krasowski, Michael J.;

Single-Event Transient Testing of Low Dropout PNP Series Linear Voltage Regulators

NASA Technical Reports Server (NTRS)

Adell, Philippe; Allen, Gregory

2013-01-01

As demand for high-speed, on-board, digital-processing integrated circuits on spacecraft increases (field-programmable gate arrays and digital signal processors in particular), the need for the next generation point-of-load (POL) regulator becomes a prominent design issue. Shrinking process nodes have resulted in core rails dropping to values close to 1.0 V, drastically reducing margin to standard switching converters or regulators that power digital ICs. The goal of this task is to perform SET characterization of several commercial POL converters, and provide a discussion of the impact of these results to state-of-the-art digital processing IC through laser and heavy ion testing

Simulation and experimental design of a new advanced variable step size Incremental Conductance MPPT algorithm for PV systems.

PubMed

Loukriz, Abdelhamid; Haddadi, Mourad; Messalti, Sabir

2016-05-01

Improvement of the efficiency of photovoltaic system based on new maximum power point tracking (MPPT) algorithms is the most promising solution due to its low cost and its easy implementation without equipment updating. Many MPPT methods with fixed step size have been developed. However, when atmospheric conditions change rapidly , the performance of conventional algorithms is reduced. In this paper, a new variable step size Incremental Conductance IC MPPT algorithm has been proposed. Modeling and simulation of different operational conditions of conventional Incremental Conductance IC and proposed methods are presented. The proposed method was developed and tested successfully on a photovoltaic system based on Flyback converter and control circuit using dsPIC30F4011. Both, simulation and experimental design are provided in several aspects. A comparative study between the proposed variable step size and fixed step size IC MPPT method under similar operating conditions is presented. The obtained results demonstrate the efficiency of the proposed MPPT algorithm in terms of speed in MPP tracking and accuracy. Copyright © 2015 ISA. Published by Elsevier Ltd. All rights reserved.

Integrated circuit detector technology in abdominal CT: added value in obese patients.

PubMed

Morsbach, Fabian; Bickelhaupt, Sebastian; Rätzer, Susan; Schmidt, Bernhard; Alkadhi, Hatem

2014-02-01

The purpose of this article was to assess the effect of an integrated circuit (IC) detector for abdominal CT on image quality. In the first study part, an abdominal phantom was scanned with various extension rings using a CT scanner equipped with a conventional discrete circuit (DC) detector and on the same scanner with an IC detector (120 kVp, 150 effective mAs, and 75 effective mAs). In the second study part, 20 patients were included who underwent abdominal CT both with the IC detector and previously at similar protocol parameters (120 kVp tube current-time product and 150 reference mAs using automated tube current modulation) with the DC detector. Images were reconstructed with filtered back projection. Image quality in the phantom was higher for images acquired with the IC compared with the DC detector. There was a gradually increasing noise reduction with increasing phantom sizes, with the highest (37% in the largest phantom) at 75 effective mAs (p < 0.001). In patients, noise was overall significantly (p = 0.025) reduced by 6.4% using the IC detector. Similar to the phantom, there was a gradual increase in noise reduction to 7.9% in patients with a body mass index of 25 kg/m(2) or lower (p = 0.008). Significant correlation was found in patients between noise and abdominal diameter in DC detector images (r = 0.604, p = 0.005), whereas no such correlation was found for the IC detector (r = 0.427, p = 0.060). Use of an IC detector in abdominal CT improves image quality and reduces image noise, particularly in overweight and obese patients. This noise reduction has the potential for dose reduction in abdominal CT.

Smart substrates: Making multi-chip modules smarter

NASA Astrophysics Data System (ADS)

Wunsch, T. F.; Treece, R. K.

1995-05-01

A novel multi-chip module (MCM) design and manufacturing methodology which utilizes active CMOS circuits in what is normally a passive substrate realizes the 'smart substrate' for use in highly testable, high reliability MCMS. The active devices are used to test the bare substrate, diagnose assembly errors or integrated circuit (IC) failures that require rework, and improve the testability of the final MCM assembly. A static random access memory (SRAM) MCM has been designed and fabricated in Sandia Microelectronics Development Laboratory in order to demonstrate the technical feasibility of this concept and to examine design and manufacturing issues which will ultimately determine the economic viability of this approach. The smart substrate memory MCM represents a first in MCM packaging. At the time the first modules were fabricated, no other company or MCM vendor had incorporated active devices in the substrate to improve manufacturability and testability, and thereby improve MCM reliability and reduce cost.

Industry-Oriented Laboratory Development for Mixed-Signal IC Test Education

ERIC Educational Resources Information Center

Hu, J.; Haffner, M.; Yoder, S.; Scott, M.; Reehal, G.; Ismail, M.

2010-01-01

The semiconductor industry is lacking qualified integrated circuit (IC) test engineers to serve in the field of mixed-signal electronics. The absence of mixed-signal IC test education at the collegiate level is cited as one of the main sources for this problem. In response to this situation, the Department of Electrical and Computer Engineering at…

An Integrated Circuit for Radio Astronomy Correlators Supporting Large Arrays of Antennas

NASA Technical Reports Server (NTRS)

D'Addario, Larry R.; Wang, Douglas

2016-01-01

Radio telescopes that employ arrays of many antennas are in operation, and ever larger ones are being designed and proposed. Signals from the antennas are combined by cross-correlation. While the cost of most components of the telescope is proportional to the number of antennas N, the cost and power consumption of cross-correlationare proportional to N2 and dominate at sufficiently large N. Here we report the design of an integrated circuit (IC) that performs digital cross-correlations for arbitrarily many antennas in a power-efficient way. It uses an intrinsically low-power architecture in which the movement of data between devices is minimized. In a large system, each IC performs correlations for all pairs of antennas but for a portion of the telescope's bandwidth (the so-called "FX" structure). In our design, the correlations are performed in an array of 4096 complex multiply-accumulate (CMAC) units. This is sufficient to perform all correlations in parallel for 64 signals (N=32 antennas with 2 opposite-polarization signals per antenna). When N is larger, the input data are buffered in an on-chipmemory and the CMACs are re-used as many times as needed to compute all correlations. The design has been synthesized and simulated so as to obtain accurate estimates of the IC's size and power consumption. It isintended for fabrication in a 32 nm silicon-on-insulator process, where it will require less than 12mm2 of silicon area and achieve an energy efficiency of 1.76 to 3.3 pJ per CMAC operation, depending on the number of antennas. Operation has been analyzed in detail up to N = 4096. The system-level energy efficiency, including board-levelI/O, power supplies, and controls, is expected to be 5 to 7 pJ per CMAC operation. Existing correlators for the JVLA (N = 32) and ALMA (N = 64) telescopes achieve about 5000 pJ and 1000 pJ respectively usingapplication-specific ICs in older technologies. To our knowledge, the largest-N existing correlator is LEDA atN = 256; it uses GPUs built in 28 nm technology and achieves about 1000 pJ. Correlators being designed for the SKA telescopes (N = 128 and N = 512) using FPGAs in 16nm technology are predicted to achieve about 100 pJ.

Processing and Prolonged 500 C Testing of 4H-SiC JFET Integrated Circuits with Two Levels of Metal Interconnect

NASA Technical Reports Server (NTRS)

Spry, David J.; Neudeck, Philip G.; Chen, Liangyu; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.; Krasowski, Michael J.; Prokop, Norman F.

2015-01-01

Complex integrated circuit (IC) chips rely on more than one level of interconnect metallization for routing of electrical power and signals. This work reports the processing and testing of 4H-SiC junction field effect transistor (JFET) prototype ICs with two levels of metal interconnect capable of prolonged operation at 500 C. Packaged functional circuits including 3-and 11-stage ring oscillators, a 4-bit digital to analog converter, and a 4-bit address decoder and random access memory cell have been demonstrated at 500 C. A 3-stage oscillator functioned for over 3000 hours at 500 C in air ambient.

A flexible surface wetness sensor using a RFID technique.

PubMed

Yang, Cheng-Hao; Chien, Jui-Hung; Wang, Bo-Yan; Chen, Ping-Hei; Lee, Da-Sheng

2008-02-01

This paper presents a flexible wetness sensor whose detection signal, converted to a binary code, is transmitted through radio-frequency (RF) waves from a radio-frequency identification integrated circuit (RFID IC) to a remote reader. The flexible sensor, with a fixed operating frequency of 13.56 MHz, contains a RFID IC and a sensor circuit that is fabricated on a flexible printed circuit board (FPCB) using a Micro-Electro-Mechanical-System (MEMS) process. The sensor circuit contains a comb-shaped sensing area surrounded by an octagonal antenna with a width of 2.7 cm. The binary code transmitted from the RFIC to the reader changes if the surface conditions of the detector surface changes from dry to wet. This variation in the binary code can be observed on a digital oscilloscope connected to the reader.

Assessment of image quality and low-contrast detectability in abdominal CT of obese patients: comparison of a novel integrated circuit with a conventional discrete circuit detector at different tube voltages.

PubMed

Euler, A; Heye, T; Kekelidze, M; Bongartz, G; Szucs-Farkas, Z; Sommer, C; Schmidt, B; Schindera, Sebastian T

2015-03-01

To compare image quality and low-contrast detectability of an integrated circuit (IC) detector in abdominal CT of obese patients with conventional detector technology at low tube voltages. A liver phantom with 45 lesions was placed in a water container to mimic an obese patient and examined on two different CT systems at 80, 100 and 120 kVp. The systems were equipped with either the IC or conventional detector. Image noise was measured, and the contrast-to-noise-ratio (CNR) was calculated. Low-contrast detectability was assessed independently by three radiologists. Radiation dose was estimated by the volume CT dose index (CTDIvol). The image noise was significantly lower, and the CNR was significantly higher with the IC detector at 80, 100 and 120 kVp, respectively (P = 0.023). The IC detector resulted in an increased lesion detection rate at 80 kVp (38.1 % vs. 17.2 %) and 100 kVp (57.0 % vs. 41.0 %). There was no difference in the detection rate between the IC detector at 100 kVp and the conventional detector at 120 kVp (57.0 % vs. 62.2 %). The CTDIvol at 80, 100 and 120 kVp measured 4.5-5.2, 7.3-7.9 and 9.8-10.2 mGy, respectively. The IC detector at 100 kVp resulted in similar low-contrast detectability compared to the conventional detector with a 120-kVp protocol at a radiation dose reduction of 37 %.

Reliability Assessment of Critical Electronic Components

DTIC Science & Technology

1992-07-01

Failures FLHP - Full Horse Power FSN - Federal Stock Number I Current IC - Integrated Circuit IPB - Illustrated Parts Breakdown K - Boltzmans Constant L...Classified P - Power PC - Printed Circuit PCB - Printed Circuit Board PGA - Pin Grid Array PPM - Parts Per Million PWB - Printed Wiring Board 0...4-59 4.4.3.2.3 Circuit Brcakers ......................................................... 4-59 4.4.3.2.4 Thermal

Present, future of automotive hybrid IC applications discussed

NASA Astrophysics Data System (ADS)

Matsuda, Nobuyoshi; Fukuoka, Atuhisa

1987-09-01

Hybrid ICs are presently utilized in various fields such as commercial televisions, VTRs, and audio devices, industrial usage of communication equipment, computers, terminals, and automobiles. Its applications and environments are various and diverse. The functions required for hybrid ICs vary from simple high density mounting for a system to the realization of high mechanisms with the application of function timing. The functions are properly used depending upon the system with its hybrid ICs and its circuit composition. Considering structure and reliability requirements for automotive hybrid ICs, an application example for hybrid ICs which use the package (COMPACT), will be discussed.

Active C4 Electrodes for Local Field Potential Recording Applications

PubMed Central

Wang, Lu; Freedman, David; Sahin, Mesut; Ünlü, M. Selim; Knepper, Ronald

2016-01-01

Extracellular neural recording, with multi-electrode arrays (MEAs), is a powerful method used to study neural function at the network level. However, in a high density array, it can be costly and time consuming to integrate the active circuit with the expensive electrodes. In this paper, we present a 4 mm × 4 mm neural recording integrated circuit (IC) chip, utilizing IBM C4 bumps as recording electrodes, which enable a seamless active chip and electrode integration. The IC chip was designed and fabricated in a 0.13 μm BiCMOS process for both in vitro and in vivo applications. It has an input-referred noise of 4.6 μVrms for the bandwidth of 10 Hz to 10 kHz and a power dissipation of 11.25 mW at 2.5 V, or 43.9 μW per input channel. This prototype is scalable for implementing larger number and higher density electrode arrays. To validate the functionality of the chip, electrical testing results and acute in vivo recordings from a rat barrel cortex are presented. PMID:26861324

Biosignal integrated circuit with simultaneous acquisition of ECG and PPG for wearable healthcare applications.

PubMed

Kim, Hyungseup; Park, Yunjong; Ko, Youngwoon; Mun, Yeongjin; Lee, Sangmin; Ko, Hyoungho

2018-01-01

Wearable healthcare systems require measurements from electrocardiograms (ECGs) and photoplethysmograms (PPGs), and the blood pressure of the user. The pulse transit time (PTT) can be calculated by measuring the ECG and PPG simultaneously. Continuous-time blood pressure without using an air cuff can be estimated by using the PTT. This paper presents a biosignal acquisition integrated circuit (IC) that can simultaneously measure the ECG and PPG for wearable healthcare applications. Included in this biosignal acquisition circuit are a voltage mode instrumentation amplifier (IA) for ECG acquisition and a current mode transimpedance amplifier for PPG acquisition. The analog outputs from the ECG and PPG channels are muxed and converted to digital signals using 12-bit successive approximation register (SAR) analog-to-digital converter (ADC). The proposed IC is fabricated by using a standard 0.18 μm CMOS process with an active area of 14.44 mm2. The total current consumption for the multichannel IC is 327 μA with a 3.3 V supply. The measured input referred noise of ECG readout channel is 1.3 μVRMS with a bandwidth of 0.5 Hz to 100 Hz. And the measured input referred current noise of the PPG readout channel is 0.122 nA/√Hz with a bandwidth of 0.5 Hz to 100 Hz. The proposed IC, which is implemented using various circuit techniques, can measure ECG and PPG signals simultaneously to calculate the PTT for wearable healthcare applications.

Integrated Cryogenic Electronics Testbed (ICE-T) for Evaluation of Superconductor and Cryo-Semiconductor Integrated Circuits

NASA Astrophysics Data System (ADS)

Dotsenko, V. V.; Sahu, A.; Chonigman, B.; Tang, J.; Lehmann, A. E.; Gupta, V.; Talalevskii, A.; Ruotolo, S.; Sarwana, S.; Webber, R. J.; Gupta, D.

2017-02-01

Research and development of cryogenic application-specific integrated circuits (ASICs), such as high-frequency (tens of GHz) semiconductor and superconductor mixed-signal circuits and large-scale (>10,000 Josephson Junctions) superconductor digital circuits, have long been hindered by the absence of specialized cryogenic test apparatus. During their iterative development phase, most ASICs require many additional input-output lines for applying independent bias controls, injecting test signals, and monitoring outputs of different sub-circuits. We are developing a full suite of modular test apparatus based on cryocoolers that do not consume liquid helium, and support extensive electrical interfaces to standard and custom test equipment. Our design separates the cryogenics from electrical connections, allowing even inexperienced users to conduct testing by simply mounting their ASIC on a removable electrical insert. Thermal connections between the cold stages and the inserts are made with robust thermal links. ICE-T accommodates two independent electrical inserts at the same time. We have designed various inserts, such as universal ones with all 40 or 80 coaxial cables and those with customized wiring and temperature-controlled stages. ICE-T features fast thermal cycling for rapid testing, enables detailed testing over long periods (days to months, if necessary), and even supports automated testing of digital ICs with modular additions.

Monolithic integrated circuit charge amplifier and comparator for MAMA readout

NASA Technical Reports Server (NTRS)

Cole, Edward H.; Smeins, Larry G.

1991-01-01

Prototype ICs for the Solar Heliospheric Observatory's Multi-Anode Microchannel Array (MAMA) have been developed; these ICs' charge-amplifier and comparator components were then tested with a view to pulse response and noise performance. All model performance predictions have been exceeded. Electrostatic discharge protection has been included on all IC connections; device operation over temperature has been consistent with model predictions.

Radiation Hard 0.13 Micron CMOS Library at IHP

NASA Astrophysics Data System (ADS)

Jagdhold, U.

2013-08-01

To support space applications we have developed an 0.13 micron CMOS library which should be radiation hard up to 200 krad. The article describes the concept to come to a radiation hard digital circuit and was introduces in 2010 [1]. By introducing new radiation hard design rules we will minimize IC-level leakage and single event latch-up (SEL). To reduce single event upset (SEU) we add two p-MOS transistors to all flip flops. For reliability reasons we use double contacts in all library elements. The additional rules and the library elements are integrated in our Cadence mixed signal design kit, “Virtuoso” IC6.1 [2]. A test chip is produced with our in house 0.13 micron BiCMOS technology, see Ref. [3]. As next step we will doing radiation tests according the european space agency (ESA) specifications, see Ref. [4], [5].

Scanning fluorescent microthermal imaging apparatus and method

DOEpatents

Barton, Daniel L.; Tangyunyong, Paiboon

1998-01-01

A scanning fluorescent microthermal imaging (FMI) apparatus and method is disclosed, useful for integrated circuit (IC) failure analysis, that uses a scanned and focused beam from a laser to excite a thin fluorescent film disposed over the surface of the IC. By collecting fluorescent radiation from the film, and performing point-by-point data collection with a single-point photodetector, a thermal map of the IC is formed to measure any localized heating associated with defects in the IC.

A way to improve dose rate laser simulation adequacy

DOE Office of Scientific and Technical Information (OSTI.GOV)

Skorobogatov, P.K.; Nikiforov, A.Y.; Demidov, A.A.

1998-12-01

A method for improving laser simulation of dose rate radiation in silicon IC`s (Integrated Circuit) is analyzed based on the application of noncoherent laser radiation. Experimental validation was performed using test structures with up to 90% surface metallization coverage.

In situ high-resolution thermal microscopy on integrated circuits.

PubMed

Zhuo, Guan-Yu; Su, Hai-Ching; Wang, Hsien-Yi; Chan, Ming-Che

2017-09-04

The miniaturization of metal tracks in integrated circuits (ICs) can cause abnormal heat dissipation, resulting in electrostatic discharge, overvoltage breakdown, and other unwanted issues. Unfortunately, locating areas of abnormal heat dissipation is limited either by the spatial resolution or imaging acquisition speed of current thermal analytical techniques. A rapid, non-contact approach to the thermal imaging of ICs with sub-μm resolution could help to alleviate this issue. In this work, based on the intensity of the temperature-dependent two-photon fluorescence (TPF) of Rhodamine 6G (R6G) material, we developed a novel fast and non-invasive thermal microscopy with a sub-μm resolution. Its application to the location of hotspots that may evolve into thermally induced defects in ICs was also demonstrated. To the best of our knowledge, this is the first study to present high-resolution 2D thermal microscopic images of ICs, showing the generation, propagation, and distribution of heat during its operation. According to the demonstrated results, this scheme has considerable potential for future in situ hotspot analysis during the optimization stage of IC development.

Reconfigurable, Bi-Directional Flexfet Level Shifter for Low-Power, Rad-Hard Integration

NASA Technical Reports Server (NTRS)

DeGregorio, Kelly; Wilson, Dale G.

2009-01-01

Two prototype Reconfigurable, Bi-directional Flexfet Level Shifters (ReBiLS) have been developed, where one version is a stand-alone component designed to interface between external low voltage and high voltage, and the other version is an embedded integrated circuit (IC) for interface between internal low-voltage logic and external high-voltage components. Targeting stand-alone and embedded circuits separately allows optimization for these distinct applications. Both ReBiLS designs use the commercially available 180-nm Flex fet Independently Double-Gated (IDG) SOI CMOS (silicon on insulator, complementary metal oxide semiconductor) technology. Embedded ReBiLS circuits were integrated with a Reed-Solomon (RS) encoder using CMOS Ultra-Low-Power Radiation Tolerant (CULPRiT) double-gated digital logic circuits. The scope of the project includes: creation of a new high-voltage process, development of ReBiLS circuit designs, and adjustment of the designs to maximize performance through simulation, layout, and manufacture of prototypes. The primary technical objectives were to develop a high-voltage, thick oxide option for the 180-nm Flexfet process, and to develop a stand-alone ReBiLS IC with two 8-channel I/O busses, 1.8 2.5 I/O on the low-voltage pins, 5.0-V-tolerant input and 3.3-V output I/O on the high-voltage pins, and 100-MHz minimum operation with 10-pF external loads. Another objective was to develop an embedded, rad-hard ReBiLS I/O cell with 0.5-V low-voltage operation for interface with core logic, 5.0-V-tolerant input and 3.3-V output I/O pins, and 100-MHz minimum operation with 10- pF external loads. A third objective was to develop a 0.5- V Reed-Solomon Encoder with embedded ReBilS I/O: Transfer the existing CULPRiT RS encoder from a 0.35-micron bulk-CMOS process to the ASI 180-nm Flexfet, rad-hard SOI Process. 0.5-V low-voltage core logic. 5.0-V-tolerant input and 3.3-V output I/O pins. 100-MHz minimum operation with 10- pF external loads. The stand-alone ReBiLS chip will allow system designers to provide efficient bi-directional communication between components operating at different voltages. Embedding the ReBiLS cells into the proven Reed-Solomon encoder will demonstrate the ability to support new product development in a commercially viable, rad-hard, scalable 180-nm SOI CMOS process.

Can EDA Combat the Rise of Electronic Counterfeiting?

DTIC Science & Technology

2012-06-01

Categories and Subject Descriptors B .7 [Hardware]: Integrated Circuits General Terms Design, Security Keywords Counterfeiting; Reliability; Device and...1199-1/12/06 ...$10.00. SIA at $7.5 B . Very recently, EE Times estimated that IC counterfeiting losses are as high as $ 169 B annually. There- fore, the...PERSON a. REPORT unclassified b . ABSTRACT unclassified c. THIS PAGE unclassified Standard Form 298 (Rev. 8-98) Prescribed by ANSI Std Z39-18

Processing and Prolonged 500 C Testing of 4H-SiC JFET Integrated Circuits with Two Levels of Metal Interconnect

NASA Technical Reports Server (NTRS)

Spry, David J.; Neudeck, Philip G.; Chen, Liangyu; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.; Krasowski, Michael J.; Prokop, Norman F.

2015-01-01

Complex integrated circuit (IC) chips rely on more than one level of interconnect metallization for routing of electrical power and signals. This work reports the processing and testing of 4H-SiC junction field effect transistor (JFET) prototype IC's with two levels of metal interconnect capable of prolonged operation at 500 C. Packaged functional circuits including 3- and 11-stage ring oscillators, a 4-bit digital to analog converter, and a 4-bit address decoder and random access memory cell have been demonstrated at 500 C. A 3-stage oscillator functioned for over 3000 hours at 500 C in air ambient. Improved reproducibility remains to be accomplished.

Heavy-ion induced single-event upset in integrated circuits

NASA Technical Reports Server (NTRS)

Zoutendyk, J. A.

1991-01-01

The cosmic ray environment in space can affect the operation of Integrated Circuit (IC) devices via the phenomenon of Single Event Upset (SEU). In particular, heavy ions passing through an IC can induce sufficient integrated current (charge) to alter the state of a bistable circuit, for example a memory cell. The SEU effect is studied in great detail in both static and dynamic memory devices, as well as microprocessors fabricated from bipolar, Complementary Metal Oxide Semiconductor (CMOS) and N channel Metal Oxide Semiconductor (NMOS) technologies. Each device/process reflects its individual characteristics (minimum scale geometry/process parameters) via a unique response to the direct ionization of electron hole pairs by heavy ion tracks. A summary of these analytical and experimental SEU investigations is presented.

Neural CMOS-integrated circuit and its application to data classification.

PubMed

Göknar, Izzet Cem; Yildiz, Merih; Minaei, Shahram; Deniz, Engin

2012-05-01

Implementation and new applications of a tunable complementary metal-oxide-semiconductor-integrated circuit (CMOS-IC) of a recently proposed classifier core-cell (CC) are presented and tested with two different datasets. With two algorithms-one based on Fisher's linear discriminant analysis and the other based on perceptron learning, used to obtain CCs' tunable parameters-the Haberman and Iris datasets are classified. The parameters so obtained are used for hard-classification of datasets with a neural network structured circuit. Classification performance and coefficient calculation times for both algorithms are given. The CC has 6-ns response time and 1.8-mW power consumption. The fabrication parameters used for the IC are taken from CMOS AMS 0.35-μm technology.

Digital correlator with fewer IC's

NASA Technical Reports Server (NTRS)

Apple, G. G.; Rubin, L.

1979-01-01

Digital correlator requires only few integrated circuits to determine synchronization of two 24-bit digital words. Circuit is easily reduced or expanded to accommodate shorter or longer words and can be utilized in industrial and commercial data processing and telecommunications.

An assessment of the impact of the Department of Defense very high speed integrated circuit program

NASA Astrophysics Data System (ADS)

1982-01-01

The technical and economic effects of the Department of Defense's (DoD) development program for very-high-speed integrated circuits (VHSIC) are examined. The probable effects of this program on the domestic aspects and international position of the integrated-circuit (IC) industry as they relate to the interests of the general public and the DoD are considered. The report presents a review of the unique DoD needs that motivate VHSIC research and development; an estimate of the degree of which these needs are likely to be met by the VHSIC program; a discussion of the effects of the program's demands for manpower, materials, and design and processing technologies; the problems connected with the program's technology export controls; and an assessment of the impact of the program on the structure of the U.S. integrated-circuit industry, its continued development and production of civilian consumer products, and its international competitive position.

Scanning fluorescent microthermal imaging apparatus and method

DOEpatents

Barton, D.L.; Tangyunyong, P.

1998-01-06

A scanning fluorescent microthermal imaging (FMI) apparatus and method is disclosed, useful for integrated circuit (IC) failure analysis, that uses a scanned and focused beam from a laser to excite a thin fluorescent film disposed over the surface of the IC. By collecting fluorescent radiation from the film, and performing point-by-point data collection with a single-point photodetector, a thermal map of the IC is formed to measure any localized heating associated with defects in the IC. 1 fig.

SPROC: A multiple-processor DSP IC

NASA Technical Reports Server (NTRS)

Davis, R.

1991-01-01

A large, single-chip, multiple-processor, digital signal processing (DSP) integrated circuit (IC) fabricated in HP-Cmos34 is presented. The innovative architecture is best suited for analog and real-time systems characterized by both parallel signal data flows and concurrent logic processing. The IC is supported by a powerful development system that transforms graphical signal flow graphs into production-ready systems in minutes. Automatic compiler partitioning of tasks among four on-chip processors gives the IC the signal processing power of several conventional DSP chips.

Integrated circuit-based instrumentation for microchip capillary electrophoresis.

PubMed

Behnam, M; Kaigala, G V; Khorasani, M; Martel, S; Elliott, D G; Backhouse, C J

2010-09-01

Although electrophoresis with laser-induced fluorescence (LIF) detection has tremendous potential in lab on chip-based point-of-care disease diagnostics, the wider use of microchip electrophoresis has been limited by the size and cost of the instrumentation. To address this challenge, the authors designed an integrated circuit (IC, i.e. a microelectronic chip, with total silicon area of <0.25 cm2, less than 5 mmx5 mm, and power consumption of 28 mW), which, with a minimal additional infrastructure, can perform microchip electrophoresis with LIF detection. The present work enables extremely compact and inexpensive portable systems consisting of one or more complementary metal-oxide-semiconductor (CMOS) chips and several other low-cost components. There are, to the authors' knowledge, no other reports of a CMOS-based LIF capillary electrophoresis instrument (i.e. high voltage generation, switching, control and interface circuit combined with LIF detection). This instrument is powered and controlled using a universal serial bus (USB) interface to a laptop computer. The authors demonstrate this IC in various configurations and can readily analyse the DNA produced by a standard medical diagnostic protocol (end-labelled polymerase chain reaction (PCR) product) with a limit of detection of approximately 1 ng/microl (approximately 1 ng of total DNA). The authors believe that this approach may ultimately enable lab-on-a-chip-based electrophoretic instruments that cost on the order of several dollars.

Reducing image noise in computed tomography (CT) colonography: effect of an integrated circuit CT detector.

PubMed

Liu, Yu; Leng, Shuai; Michalak, Gregory J; Vrieze, Thomas J; Duan, Xinhui; Qu, Mingliang; Shiung, Maria M; McCollough, Cynthia H; Fletcher, Joel G

2014-01-01

To investigate whether the integrated circuit (IC) detector results in reduced noise in computed tomography (CT) colonography (CTC). Three hundred sixty-six consecutive patients underwent clinically indicated CTC using the same CT scanner system, except for a difference in CT detectors (IC or conventional). Image noise, patient size, and scanner radiation output (volume CT dose index) were quantitatively compared between patient cohorts using each detector system, with separate comparisons for the abdomen and pelvis. For the abdomen and pelvis, despite significantly larger patient sizes in the IC detector cohort (both P < 0.001), image noise was significantly lower (both P < 0.001), whereas volume CT dose index was unchanged (both P > 0.18). Based on the observed image noise reduction, radiation dose could alternatively be reduced by approximately 20% to result in similar levels of image noise. Computed tomography colonography images acquired using the IC detector had significantly lower noise than images acquired using the conventional detector. This noise reduction can permit further radiation dose reduction in CTC.

An integrated control and readout circuit for implantable multi-target electrochemical biosensing.

PubMed

Ghoreishizadeh, Sara S; Baj-Rossi, Camilla; Cavallini, Andrea; Carrara, Sandro; De Micheli, Giovanni

2014-12-01

We describe an integrated biosensor capable of sensing multiple molecular targets using both cyclic voltammetry (CV) and chronoamperometry (CA). In particular, we present our custom IC to realize voltage control and current readout of the biosensors. A mixed-signal circuit block generates sub-Hertz triangular waveform for the biosensors by means of a direct-digital-synthesizer to control CV. A current to pulse-width converter is realized to output the data for CA measurement. The IC is fabricated in 0.18 μm technology. It consumes 220 μW from 1.8 V supply voltage, making it suitable for remotely-powered applications. Electrical measurements show excellent linearity in sub- μA current range. Electrochemical measurements including CA measurements of glucose and lactate and CV measurements of the anti-cancer drug Etoposide have been acquired with the fabricated IC and compared with a commercial equipment. The results obtained with the fabricated IC are in good agreement with those of the commercial equipment for both CV and CA measurements.

Flexible packaging of solid-state integrated circuit chips with elastomeric microfluidics

PubMed Central

Zhang, Bowei; Dong, Quan; Korman, Can E.; Li, Zhenyu; Zaghloul, Mona E.

2013-01-01

A flexible technology is proposed to integrate smart electronics and microfluidics all embedded in an elastomer package. The microfluidic channels are used to deliver both liquid samples and liquid metals to the integrated circuits (ICs). The liquid metals are used to realize electrical interconnects to the IC chip. This avoids the traditional IC packaging challenges, such as wire-bonding and flip-chip bonding, which are not compatible with current microfluidic technologies. As a demonstration we integrated a CMOS magnetic sensor chip and associate microfluidic channels on a polydimethylsiloxane (PDMS) substrate that allows precise delivery of small liquid samples to the sensor. Furthermore, the packaged system is fully functional under bending curvature radius of one centimetre and uniaxial strain of 15%. The flexible integration of solid-state ICs with microfluidics enables compact flexible electronic and lab-on-a-chip systems, which hold great potential for wearable health monitoring, point-of-care diagnostics and environmental sensing among many other applications.

Pyrolysis characteristics of integrated circuit boards at various particle sizes and temperatures.

PubMed

Chiang, Hung-Lung; Lin, Kuo-Hsiung; Lai, Mei-Hsiu; Chen, Ting-Chien; Ma, Sen-Yi

2007-10-01

A pyrolysis method was employed to recycle the metals and brominated compounds blended into printed circuit boards. This research investigated the effect of particle size and process temperature on the element composition of IC boards and pyrolytic residues, liquid products, and water-soluble ionic species in the exhaust, with the overall goal being to identify the pyrolysis conditions that will have the least impact on the environment. Integrated circuit (IC) boards were crushed into 5-40 mesh (0.71-4.4mm), and the crushed particles were pyrolyzed at temperatures ranging from 200 to 500 degrees C. The thermal decomposition kinetics were measured by a thermogravimetric (TG) analyzer. The composition of pyrolytic residues was analyzed by Energy Dispersive X-ray Spectrometer (EDS), Inductively Coupled Plasma Atomic Emission Spectrometer (ICP-AES) and Inductively Coupled Plasma-Mass Spectrometry (ICP-MS). In addition, the element compositions of liquid products were analyzed by ICP-AES and ICP-MS. Pyrolytic exhaust was collected by a water-absorption system in an ice-bath cooler, and IC analysis showed that the absorbed solution comprised 11 ionic species. Based on the pyrolytic kinetic parameters of TG analysis and pyrolytic residues at various temperatures for 30 min, the effect of particle size was insignificant in this study, and temperature was the key factor for the IC board pyrolysis. Two stages of decomposition were found for IC board pyrolysis under nitrogen atmosphere. The activation energy was 38-47 kcal/mol for the first-stage reaction and 5.2-9.4 kcal/mol for the second-stage reaction. Metal content was low in the liquid by-product of the IC board pyrolysis process, which is an advantage in that the liquid product could be used as a fuel. Brominate and ammonium were the main water-soluble ionic species of the pyrolytic exhaust. A plan for their safe and effective disposal must be developed if the pyrolytic recycling process is to be applied to IC boards.

Integration of Low-Power ASIC and MEMS Sensors for Monitoring Gastrointestinal Tract Using a Wireless Capsule System.

PubMed

Arefin, Md Shamsul; Redoute, Jean-Michel; Yuce, Mehmet Rasit

2018-01-01

This paper presents a wireless capsule microsystem to detect and monitor the pH, pressure, and temperature of the gastrointestinal tract in real time. This research contributes to the integration of sensors (microfabricated capacitive pH, capacitive pressure, and resistive temperature sensors), frequency modulation and pulse width modulation based interface IC circuits, microcontroller, and transceiver with meandered conformal antenna for the development of a capsule system. The challenges associated with the system miniaturization, higher sensitivity and resolution of sensors, and lower power consumption of interface circuits are addressed. The layout, PCB design, and packaging of a miniaturized wireless capsule, having diameter of 13 mm and length of 28 mm, have successfully been implemented. A data receiver and recorder system is also designed to receive physiological data from the wireless capsule and to send it to a computer for real-time display and recording. Experiments are performed in vitro using a stomach model and minced pork as tissue simulating material. The real-time measurements also validate the suitability of sensors, interface circuits, and meandered antenna for wireless capsule applications.

Heterostructure-based high-speed/high-frequency electronic circuit applications

NASA Astrophysics Data System (ADS)

Zampardi, P. J.; Runge, K.; Pierson, R. L.; Higgins, J. A.; Yu, R.; McDermott, B. T.; Pan, N.

1999-08-01

With the growth of wireless and lightwave technologies, heterostructure electronic devices are commodity items in the commercial marketplace [Browne J. Power-amplifier MMICs drive commercial circuits. Microwaves & RF, 1998. p. 116-24.]. In particular, HBTs are an attractive device for handset power amplifiers at 900 MHz and 1.9 GHz for CDMA applications [Lum E. GaAs technology rides the wireless wave. Proceedings of the 1997 GaAs IC Symposium, 1997. p. 11-13; "Rockwell Ramps Up". Compound Semiconductor, May/June 1997.]. At higher frequencies, both HBTs and p-HEMTs are expected to dominate the marketplace. For high-speed lightwave circuit applications, heterostructure based products on the market for OC-48 (2.5 Gb/s) and OC-192 (10 Gb/s) are emerging [http://www.nb.rockwell.com/platforms/network_access/nahome.html#5.; http://www.nortel.com/technology/opto/receivers/ptav2.html.]. Chips that operate at 40 Gb/ have been demonstrated in a number of research laboratories [Zampardi PJ, Pierson RL, Runge K, Yu R, Beccue SM, Yu J, Wang KC. hybrid digital/microwave HBTs for >30 Gb/s optical communications. IEDM Technical Digest, 1995. p. 803-6; Swahn T, Lewin T, Mokhtari M, Tenhunen H, Walden R, Stanchina W. 40 Gb/s 3 Volt InP HBT ICs for a fiber optic demonstrator system. Proceedings of the 1996 GaAs IC Symposium, 1996. p. 125-8; Suzuki H, Watanabe K, Ishikawa K, Masuda H, Ouchi K, Tanoue T, Takeyari R. InP/InGaAs HBT ICs for 40 Gbit/s optical transmission systems. Proceedings of the 1997 GaAs IC Symposium, 1997. p. 215-8]. In addition to these two markets, another area where heterostructure devices are having significant impact is for data conversion [Walden RH. Analog-to digital convertor technology comparison. Proceedings of the 1994 GaAs IC Symposium, 1994. p. 217-9; Poulton K, Knudsen K, Corcoran J, Wang KC, Nubling RB, Chang M-CF, Asbeck PM, Huang RT. A 6-b, 4 GSa/s GaAs HBT ADC. IEEE J Solid-State Circuits 1995;30:1109-18; Nary K, Nubling R, Beccue S, Colleran W, Penney J, Wang KC. An 8-bit, 2 gigasample per second analog to digital converter. Proceedings of the 1995 GaAs IC Symposium, 1995. p. 303-6.]. In this paper, we will discuss the present and future trends of heterostructure device applications to these areas.

An integrated circuit with transmit beamforming flip-chip bonded to a 2-D CMUT array for 3-D ultrasound imaging.

PubMed

Wygant, Ira O; Jamal, Nafis S; Lee, Hyunjoo J; Nikoozadeh, Amin; Oralkan, Omer; Karaman, Mustafa; Khuri-Yakub, Butrus T

2009-10-01

State-of-the-art 3-D medical ultrasound imaging requires transmitting and receiving ultrasound using a 2-D array of ultrasound transducers with hundreds or thousands of elements. A tight combination of the transducer array with integrated circuitry eliminates bulky cables connecting the elements of the transducer array to a separate system of electronics. Furthermore, preamplifiers located close to the array can lead to improved receive sensitivity. A combined IC and transducer array can lead to a portable, high-performance, and inexpensive 3-D ultrasound imaging system. This paper presents an IC flip-chip bonded to a 16 x 16-element capacitive micromachined ultrasonic transducer (CMUT) array for 3-D ultrasound imaging. The IC includes a transmit beamformer that generates 25-V unipolar pulses with programmable focusing delays to 224 of the 256 transducer elements. One-shot circuits allow adjustment of the pulse widths for different ultrasound transducer center frequencies. For receiving reflected ultrasound signals, the IC uses the 32-elements along the array diagonals. The IC provides each receiving element with a low-noise 25-MHz-bandwidth transimpedance amplifier. Using a field-programmable gate array (FPGA) clocked at 100 MHz to operate the IC, the IC generated properly timed transmit pulses with 5-ns accuracy. With the IC flip-chip bonded to a CMUT array, we show that the IC can produce steered and focused ultrasound beams. We present 2-D and 3-D images of a wire phantom and 2-D orthogonal cross-sectional images (Bscans) of a latex heart phantom.

System architecture of a gallium arsenide one-gigahertz digital IC tester

NASA Technical Reports Server (NTRS)

Fouts, Douglas J.; Johnson, John M.; Butner, Steven E.; Long, Stephen I.

1987-01-01

The design for a 1-GHz digital integrated circuit tester for the evaluation of custom GaAs chips and subsystems is discussed. Technology-related problems affecting the design of a GaAs computer are discussed, with emphasis on the problems introduced by long printed-circuit-board interconnect. High-speed interface modules provide a link between the low-speed microprocessor and the chip under test. Memory-multiplexer and memory-shift register architectures for the storage of test vectors are described in addition to an architecture for local data storage consisting of a long chain of GaAs shift registers. The tester is constructed around a VME system card cage and backplane, and very little high-speed interconnect exists between boards. The tester has a three part self-test consisting of a CPU board confidence test, a main memory confidence test, and a high-speed interface module functional test.

Transforming Ordinary Buildings into Smart Buildings via Low-Cost, Self-Powering Wireless Sensors & Sensor Networks

DOE Office of Scientific and Technical Information (OSTI.GOV)

Feng, Philip

The research objective of this project is to design and demonstrate a low-cost, compact, easy-to-deploy, maintenance-free sensor node technology, and a network of such sensors, which enable the monitoring of multiphysical parameters and can transform today’s ordinary buildings into smart buildings with environmental awareness. We develop the sensor node and network via engineering and integration of existing technologies, including high-efficiency mechanical energy harvesting, and ultralow-power integrated circuits (ICs) for sensing and wireless communication. Through integration and innovative power management via specifically designed low-power control circuits for wireless sensing applications, and tailoring energy-harvesting components to indoor applications, the target products willmore » have smaller volume, higher efficiency, and much lower cost (in both manufacturing and maintenance) than the baseline technology. Our development and commercialization objective is to create prototypes for our target products under the CWRU-Intwine collaboration.« less

DOE Office of Scientific and Technical Information (OSTI.GOV)

Radojcic, Riko; Nowak, Matt; Nakamoto, Mark

The status of the development of a Design-for-Stress simulation flow that captures the stress effects in packaged 3D-stacked Si products like integrated circuits (ICs) using advanced via-middle Through Si Via technology is outlined. The next set of challenges required to proliferate the methodology and to deploy it for making and dispositioning real Si product decisions are described here. These include the adoption and support of a Process Design Kit (PDK) that includes the relevant material properties, the development of stress simulation methodologies that operate at higher levels of abstraction in a design flow, and the development and adoption of suitablemore » models required to make real product reliability decisions.« less

Network interactions within the canine intrinsic cardiac nervous system: implications for reflex control of regional cardiac function

PubMed Central

Beaumont, Eric; Salavatian, Siamak; Southerland, E Marie; Vinet, Alain; Jacquemet, Vincent; Armour, J Andrew; Ardell, Jeffrey L

2013-01-01

The aims of the study were to determine how aggregates of intrinsic cardiac (IC) neurons transduce the cardiovascular milieu versus responding to changes in central neuronal drive and to determine IC network interactions subsequent to induced neural imbalances in the genesis of atrial fibrillation (AF). Activity from multiple IC neurons in the right atrial ganglionated plexus was recorded in eight anaesthetized canines using a 16-channel linear microelectrode array. Induced changes in IC neuronal activity were evaluated in response to: (1) focal cardiac mechanical distortion; (2) electrical activation of cervical vagi or stellate ganglia; (3) occlusion of the inferior vena cava or thoracic aorta; (4) transient ventricular ischaemia, and (5) neurally induced AF. Low level activity (ranging from 0 to 2.7 Hz) generated by 92 neurons was identified in basal states, activities that displayed functional interconnectivity. The majority (56%) of IC neurons so identified received indirect central inputs (vagus alone: 25%; stellate ganglion alone: 27%; both: 48%). Fifty per cent transduced the cardiac milieu responding to multimodal stressors applied to the great vessels or heart. Fifty per cent of IC neurons exhibited cardiac cycle periodicity, with activity occurring primarily in late diastole into isovolumetric contraction. Cardiac-related activity in IC neurons was primarily related to direct cardiac mechano-sensory inputs and indirect autonomic efferent inputs. In response to mediastinal nerve stimulation, most IC neurons became excessively activated; such network behaviour preceded and persisted throughout AF. It was concluded that stochastic interactions occur among IC local circuit neuronal populations in the control of regional cardiac function. Modulation of IC local circuit neuronal recruitment may represent a novel approach for the treatment of cardiac disease, including atrial arrhythmias. PMID:23818689

Path programmable logic: A structured design method for digital and/or mixed analog integrated circuits

NASA Technical Reports Server (NTRS)

Taylor, B.

1990-01-01

The design of Integrated Circuits has evolved past the black art practiced by a few semiconductor companies to a world wide community of users. This was basically accomplished by the development of computer aided design tools which were made available to this community. As the tools matured into different components of the design task they were accepted into the community at large. However, the next step in this evolution is being ignored by the large tool vendors hindering the continuation of this process. With system level definition and simulation through the logic specification well understood, why is the physical generation so blatantly ignored. This portion of the development is still treated as an isolated task with information being passed from the designer to the layout function. Some form of result given back but it severely lacks full definition of what has transpired. The level of integration in I.C.'s for tomorrow, whether through new processes or applications will require higher speeds, increased transistor density, and non-digital performance which can only be achieved through attention to the physical implementation.

Monolithic integration of GMR sensors for standard CMOS-IC current sensing

NASA Astrophysics Data System (ADS)

De Marcellis, A.; Reig, C.; Cubells-Beltrán, M.-D.; Madrenas, J.; Santos, J. D.; Cardoso, S.; Freitas, P. P.

2017-09-01

In this work we report on the development of Giant Magnetoresistive (GMR) sensors for off-line current measurements in standard integrated circuits. An ASIC has been specifically designed and fabricated in the well-known AMS-0.35 μm CMOS technology, including the electronic circuitry for sensor interfacing. It implements an oscillating circuit performing a voltage-to-frequency conversion. Subsequently, a fully CMOS-compatible low temperature post-process has been applied for depositing the GMR sensing devices in a full-bridge configuration onto the buried current straps. Sensitivity and resolution of these sensors have been investigated achieving experimental results that show a detection sensitivity of about 100 Hz/mA, with a resolution of about 5 μA.

Improving depiction of temporal bone anatomy with low-radiation dose CT by an integrated circuit detector in pediatric patients: a preliminary study.

PubMed

He, Jingzhen; Zu, Yuliang; Wang, Qing; Ma, Xiangxing

2014-12-01

The purpose of this study was to determine the performance of low-dose computed tomography (CT) scanning with integrated circuit (IC) detector in defining fine structures of temporal bone in children by comparing with the conventional detector. The study was performed with the approval of our institutional review board and the patients' anonymity was maintained. A total of 86 children<3 years of age underwent imaging of temporal bone with low-dose CT (80 kV/150 mAs) equipped with either IC detector or conventional discrete circuit (DC) detector. The image noise was measured for quantitative analysis. Thirty-five structures of temporal bone were further assessed and rated by 2 radiologists for qualitative analysis. κ Statistics were performed to determine the agreement reached between the 2 radiologists on each image. Mann-Whitney U test was used to determine the difference in image quality between the 2 detector systems. Objective analysis showed that the image noise was significantly lower (P<0.001) with the IC detector than with the DC detector. The κ values for qualitative assessment of the 35 fine anatomical structures revealed high interobserver agreement. The delineation for 30 of the 35 landmarks (86%) with the IC detector was superior to that with the conventional DC detector (P<0.05) although there were no differences in the delineation of the remaining 5 structures (P>0.05). The low-dose CT images acquired with the IC detector provide better depiction of fine osseous structures of temporal bone than that with the conventional DC detector.

Cryogenic ultra-low power dissipation operational amplifiers with GaAs JFETs

NASA Astrophysics Data System (ADS)

Hibi, Yasunori; Matsuo, Hiroshi; Ikeda, Hirokazu; Fujiwara, Mikio; Kang, Lin; Chen, Jian; Wu, Peiheng

2016-01-01

To realize a multipixel camera for astronomical observation, we developed cryogenic multi-channel readout systems using gallium arsenide junction field-effect transistor (GaAs JFET) integrated circuits (ICs). Based on our experience with these cryogenic ICs, we designed, manufactured, and demonstrated operational amplifiers requiring four power supplies and two voltage sources. The amplifiers operate at 4.2 K with an open-loop gain of 2000. The gain-bandwidth product can expect 400 kHz at a power dissipation of 6 μW. In performance evaluations, the input-referred voltage noise was 4 μVrms/Hz0.5 at 1 Hz and 30 nVrms/Hz0.5 at 10 kHz, respectively. The noise power spectrum density was of type 1/f and extended to 10 kHz.

CCD correlation techniques

NASA Technical Reports Server (NTRS)

Hewes, C. R.; Bosshart, P. W.; Eversole, W. L.; Dewit, M.; Buss, D. D.

1976-01-01

Two CCD techniques were discussed for performing an N-point sampled data correlation between an input signal and an electronically programmable reference function. The design and experimental performance of an implementation of the direct time correlator utilizing two analog CCDs and MOS multipliers on a single IC were evaluated. The performance of a CCD implementation of the chirp z transform was described, and the design of a new CCD integrated circuit for performing correlation by multiplication in the frequency domain was presented. This chip provides a discrete Fourier transform (DFT) or inverse DFT, multipliers, and complete support circuitry for the CCD CZT. The two correlation techniques are compared.

The use of light emission in failure analysis of CMOS ICs

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hawkins, C.F.; Soden, J.M.; Cole, E.I. Jr.

1990-01-01

The use of photon emission for analyzing failure mechanisms and defects in CMOS ICs is presented. Techniques are given for accurate identification and spatial localization of failure mechanisms and physical defects, including defects such as short and open circuits which do not themselves emit photons.

Elevated voltage level I.sub.DDQ failure testing of integrated circuits

DOEpatents

Righter, Alan W.

1996-01-01

Burn in testing of static CMOS IC's is eliminated by I.sub.DDQ testing at elevated voltage levels. These voltage levels are at least 25% higher than the normal operating voltage for the IC but are below voltage levels that would cause damage to the chip.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Rodenbeck, Christopher T; Girardi, Michael

Internal nodes of a constituent integrated circuit (IC) package of a multichip module (MCM) are protected from excessive charge during plasma cleaning of the MCM. The protected nodes are coupled to an internal common node of the IC package by respectively associated discharge paths. The common node is connected to a bond pad of the IC package. During MCM assembly, and before plasma cleaning, this bond pad receives a wire bond to a ground bond pad on the MCM substrate.

Improving yield and reliability of FIB modifications using electrical testing

NASA Astrophysics Data System (ADS)

Desplats, Romain; Benbrik, Jamel; Benteo, Bruno; Perdu, Philippe

1998-08-01

Focused Ion Beam technology has two main areas of application for ICs: modification and preparation for technological analysis. The most solicited area is modification. This involves physically modifying a circuit by cutting lines and creating new ones in order to change the electrical function of the circuit. IC planar technologies have an increasing number of metal interconnections making FIB modifications more complex and decreasing their changes of success. The yield of FIB operations on ICs reflects a downward trend that imposes a greater number of circuits to be modified in order to successfully correct a small number of them. This requires extended duration, which is not compatible with production line turn around times. To respond to this problem, two solutions can be defined: either, reducing the duration of each FIB operation or increasing the success rate of FIB modifications. Since reducing the time depends mainly on FIB operator experience, insuring a higher success rate represents a more crucial aspect as both experienced and novice operators could benefit from this improvement. In order to insure successful modifications, it is necessary to control each step of a FIB operation. To do this, we have developed a new method using in situ electrical testing which has a direct impact on the yield of FIB modifications. We will present this innovative development through a real case study of a CMOS ASIC for high-speed communications. Monitoring the electrical behavior at each step in a FIB operation makes it possible to reduce the number of circuits to be modified and consequently reduces system costs thanks to better yield control. Knowing the internal electrical behavior also gives us indications about the impact on reliability of FIB modified circuits. Finally, this approach can be applied to failure analysis and FIB operations on flip chip circuits.

A MEMS Interface IC With Low-Power and Wide-Range Frequency-to-Voltage Converter for Biomedical Applications.

PubMed

Arefin, Md Shamsul; Redouté, Jean-Michel; Yuce, Mehmet Rasit

2016-04-01

This paper presents an interface circuit for capacitive and inductive MEMS biosensors using an oscillator and a charge pump based frequency-to-voltage converter. Frequency modulation using a differential crossed coupled oscillator is adopted to sense capacitive and inductive changes. The frequency-to-voltage converter is designed with a negative feedback system and external controlling parameters to adjust the sensitivity, dynamic range, and nominal point for the measurement. The sensitivity of the frequency-to-voltage converter is from 13.28 to 35.96 mV/MHz depending on external voltage and charging current. The sensitivity ranges of the capacitive and inductive interface circuit are 17.08 to 54.4 mV/pF and 32.11 to 82.88 mV/mH, respectively. A capacitive MEMS based pH sensor is also connected with the interface circuit to measure the high acidic gastric acid throughout the digestive tract. The sensitivity for pH from 1 to 3 is 191.4 mV/pH with 550 μV(pp) noise. The readout circuit is designed and fabricated using the UMC 0.18 μm CMOS technology. It occupies an area of 0.18 mm (2) and consumes 11.8 mW.

A 32 kb 9T near-threshold SRAM with enhanced read ability at ultra-low voltage operation

NASA Astrophysics Data System (ADS)

Kim, Tony Tae-Hyoung; Lee, Zhao Chuan; Do, Anh Tuan

2018-01-01

Ultra-low voltage SRAMs are highly sought-after in energy-limited systems such as battery-powered and self-harvested SoCs. However, ultra-low voltage operation diminishes SRAM read bitline (RBL) sensing margin significantly. This paper tackles this issue by presenting a novel 9T cell with data-independent RBL leakage in combination with an RBL boosting technique for enhancing the sensing margin. The proposed technique automatically tracks process, temperature and voltage (PVT) variations for robust sensing margin enhancement. A test chip fabricated in 65 nm CMOS technology shows that the proposed scheme significantly enlarges the sensing margin compared to the conventional bitline sensing scheme. It also achieves the minimum operating voltage of 0.18 V and the minimum energy consumption of 0.92 J/access at 0.4 V. He received 2016 International Low Power Design Contest Award from ISLPED, a best paper award at 2014 and 2011 ISOCC, 2008 AMD/CICC Student Scholarship Award, 2008 Departmental Research Fellowship from Univ. of Minnesota, 2008 DAC/ISSCC Student Design Contest Award, 2008, 2001, and 1999 Samsung Humantec Thesis Award and, 2005 ETRI Journal Paper of the Year Award. He is an author/co-author of +100 journal and conference papers and has 17 US and Korean patents registered. His current research interests include low power and high performance digital, mixed- mode, and memory circuit design, ultra-low voltage circuits and systems design, variation and aging tolerant circuits and systems, and circuit techniques for 3D ICs. He serves as an associate editor of IEEE Transactions on VLSI Systems. He is an IEEE senior member and the Chair of IEEE Solid-State Circuits Society Singapore Chapter. He has served numerous conferences as a committee member.

Recovery of the Space Shuttle Columbia Avionics

NASA Technical Reports Server (NTRS)

Hames, Kevin L.

2003-01-01

Lessons Learned: a) Avionics data can playa critical role in the investigation of a "close call" or accident. b) Avionics designers should think about the role their systems might play in an investigation. c) Know your data, down to the bit level. d) Know your spacecraft - follow the data. e) Internal placement of circuit cards can affect their survivability. f) Think about how to reconstruct nonvolatile memory (e.g. serialize IC's, etc.) g) Use of external assets can aid in extracting data from avionics.

Asymmetric Multilevel Outphasing (AMO): A New Architecture for All-Silicon mm-Wave Transmitter ICs

DTIC Science & Technology

2015-06-12

power-amplifiers for mobile basestation infrastructure and handsets. NanoSemi Inc. designs linearization solutions for analog front-ends such as...ward flexible, multi-standard radio chips, increases the need for high-precision, high-throughput and energy-efficient backend processing. The desire...peak PAE is affected by less than 1% (46 mW/(46 mW 1.8 W/0.4)) by this 64-QAM capable AMO SCS backend . 378 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48

An Integrated Circuit for Simultaneous Extracellular Electrophysiology Recording and Optogenetic Neural Manipulation

PubMed Central

Chen, Chang Hao; McCullagh, Elizabeth A.; Pun, Sio Hang; Mak, Peng Un; Vai, Mang I; Mak, Pui In; Klug, Achim; Lei, Tim C.

2017-01-01

The ability to record and to control action potential firing in neuronal circuits of the brain is critical to understand how the brain functions on the cellular and network levels. Recent development of optogenetic proteins allows direct stimulation or inhibition of action potential firing of neurons upon optical illumination. In this paper, we combined a low-noise and high input impedance (or low input capacitance) neural recording amplifier, and a high current laser/LED driver in a monolithic integrated circuit (IC) for simultaneous neural recording and optogenetic neural control. The low input capacitance of the amplifier (9.7 pF) was achieved through adding a dedicated unity gain input stage optimized for high impedance metal electrodes. The input referred noise of the amplifier was measured to be 4.57 µVrms, which is lower than the estimated thermal noise of the metal electrode. Thus, action potentials originating from a single neuron can be recorded with a signal-to-noise ratio of ~6.6. The LED/laser current driver delivers a maximum current of 330 mA to generate adequate light for optogenetic control. We experimentally tested the functionality of the IC with an anesthetized Mongolian gerbil and recorded auditory stimulated action potentials from the inferior colliculus. Furthermore, we showed that spontaneous firing of 5th (trigeminal) nerve fibers was inhibited using the optogenetic protein Halorhodopsin. A noise model was also derived including the equivalent electronic components of the metal electrode and the high current driver to guide the design. PMID:28221990

Auditory cortex controls sound-driven innate defense behaviour through corticofugal projections to inferior colliculus.

PubMed

Xiong, Xiaorui R; Liang, Feixue; Zingg, Brian; Ji, Xu-ying; Ibrahim, Leena A; Tao, Huizhong W; Zhang, Li I

2015-06-11

Defense against environmental threats is essential for animal survival. However, the neural circuits responsible for transforming unconditioned sensory stimuli and generating defensive behaviours remain largely unclear. Here, we show that corticofugal neurons in the auditory cortex (ACx) targeting the inferior colliculus (IC) mediate an innate, sound-induced flight behaviour. Optogenetic activation of these neurons, or their projection terminals in the IC, is sufficient for initiating flight responses, while the inhibition of these projections reduces sound-induced flight responses. Corticocollicular axons monosynaptically innervate neurons in the cortex of the IC (ICx), and optogenetic activation of the projections from the ICx to the dorsal periaqueductal gray is sufficient for provoking flight behaviours. Our results suggest that ACx can both amplify innate acoustic-motor responses and directly drive flight behaviours in the absence of sound input through corticocollicular projections to ICx. Such corticofugal control may be a general feature of innate defense circuits across sensory modalities.

A study on the recycling of scrap integrated circuits by leaching.

PubMed

Lee, Ching-Hwa; Tang, Li-Wen; Popuri, Srinivasa R

2011-07-01

In order to minimize the problem of pollution and to conserve limited natural resources, a method to recover the valuable metals such as gold, silver and copper) present in the scrap integrated circuits (ICs) was developed in the present study. Roasting, grinding, screening, magnetic separation, melting and leaching were adopted to investigate the efficiency of recovery of gold, silver and copper from scrap ICs. The collected scrap IC samples were roasted at 850 °C to destroy their plastic resin sealing material, followed by screening and magnetic separation to separate the metals from the resin residue. The non-ferrous materials (0.840 mm) were mainly composed of copper and could be melted into a copper alloy. Non-ferrous materials containing gold (860.05 ppm), silver (1323.12 ppm) and copper (37259.7 ppm) (size less than 50 mesh) were recovered 100% by a leaching process and thiourea was used as a leaching reagent.

INTEGRATED CIRCUITS FROM MOBILE PHONES AS POSSIBLE EMERGENCY OSL/TL DOSIMETERS.

PubMed

Sholom, S; McKeever, S W S

2016-09-01

In this article, optically stimulated luminescence (OSL) data are presented from integrated circuits (ICs) extracted from mobile phones. The purpose is to evaluate the potential of using OSL from components in personal electronic devices such as smart phones as a means of emergency dosimetry in the event of a large-scale radiological incident. ICs were extracted from five different makes and models of mobile phone. Sample preparation procedures are described, and OSL from the IC samples following irradiation using a (90)Sr/(90)Y source is presented. Repeatability, sensitivity, dose responses, minimum measureable doses, stability and fading data were examined and are described. A protocol for measuring absorbed dose is presented, and it was concluded that OSL from these components is a viable method for assessing dose in the days following a radiological incident. © The Author 2015. Published by Oxford University Press. All rights reserved. For Permissions, please email: journals.permissions@oup.com.

Effecting aging time of epoxy molding compound to molding process for integrated circuit packaging

NASA Astrophysics Data System (ADS)

Tachapitunsuk, Jirayu; Ugsornrat, Kessararat; Srisuwitthanon, Warayoot; Thonglor, Panakamon

2017-09-01

This research studied about effecting aging time of epoxy molding compound (EMC) that effect to reliability performance of integrated circuit (IC) package in molding process. Molding process is so important of IC packaging process for protecting IC chip (or die) from temperature and humidity environment using encapsulated EMC. For general molding process, EMC are stored in the frozen at 5°C and left at room temperature at 25 °C for aging time on self before molding of die onto lead frame is 24 hours. The aging time effect to reliability performance of IC package due to different temperature and humidity inside the package. In experiment, aging time of EMC were varied from 0 to 24 hours for molding process of SOIC-8L packages. For analysis, these packages were tested by x-ray and scanning acoustic microscope to analyze properties of EMC with an aging time and also analyzed delamination, internal void, and wire sweep inside the packages with different aging time. The results revealed that different aging time of EMC effect to properties and reliability performance of molding process.

Three-Dimensional, Inkjet-Printed Organic Transistors and Integrated Circuits with 100% Yield, High Uniformity, and Long-Term Stability.

PubMed

Kwon, Jimin; Takeda, Yasunori; Fukuda, Kenjiro; Cho, Kilwon; Tokito, Shizuo; Jung, Sungjune

2016-11-22

In this paper, we demonstrate three-dimensional (3D) integrated circuits (ICs) based on a 3D complementary organic field-effect transistor (3D-COFET). The transistor-on-transistor structure was achieved by vertically stacking a p-type OFET over an n-type OFET with a shared gate joining the two transistors, effectively halving the footprint of printed transistors. All the functional layers including organic semiconductors, source/drain/gate electrodes, and interconnection paths were fully inkjet-printed except a parylene dielectric which was deposited by chemical vapor deposition. An array of printed 3D-COFETs and their inverter logic gates comprising over 100 transistors showed 100% yield, and the uniformity and long-term stability of the device were also investigated. A full-adder circuit, the most basic computing unit, has been successfully demonstrated using nine NAND gates based on the 3D structure. The present study fulfills the essential requirements for the fabrication of organic printed complex ICs (increased transistor density, 100% yield, high uniformity, and long-term stability), and the findings can be applied to realize more complex digital/analogue ICs and intelligent devices.

Ion chromatography in the manufacture of multilayer circuit boards

NASA Astrophysics Data System (ADS)

Smith, R. E.

1987-10-01

Ion chromatography (IC) has proven useful in analyzing chemical solutions used in the manufacture of multilayer circuit boards. IC provides results on ions not expected in the production solutions. Thus, solution contamination and breakdown products can be monitored in every phase of the circuit board manufacturing. During the first phase, epoxy laminates experience an etchback, first in chromic acid, which can be analyzed for trace chloride and sulfate, then in ammonium bifluoride/HCl, which can be analyzed for fluoride and chloride. Following a wet blasting to roughen up the surface, 20 mu in. of copper are deposited using an electroless bath. Again, IC is applicable for monitoring formate, tartarate, and sulfate levels. Next, an acid copper bath is used to electroplate the through holes with 0.001 in. of ductile copper. This bath is analyzed for trace chloride. Photoimaging is then performed, and the organic solvents used can be assayed for trace ionic chloride. Finally, a fluoroboric acid-based tin-lead bath is used to deposit a solderable alloy. This bath is analyzed for total fluoroborate, tin, and lead. In addition, mobile phase ion chromatography (MPIC) is used to monitor the nonionic organic brighteners in the baths.

Ion chromatography in the manufacture of multilayer circuit boards

NASA Astrophysics Data System (ADS)

Smith, Robert E.

1990-01-01

Ion chromatography (IC) has proven useful in analyzing chemical solutions used in the manufacture of multilayer circuit boards. Unlike other chemical quantification techniques, IC provides results on ions not expected in the production solutions. Thus, solution contamination and break-down products can be monitored in every phase of the circuit board manufacturing. During the first phase, epoxy laminates experience an etchback, first in chromic acid, which can be analyzed for trace chloride and sulfate, then in ammonium bifluoride/HCl, which can be analyzed for fluoride and chloride. Following a wet-blasting to roughen up the surface, 20 microinches of copper are deposited using an electroless bath. Again, IC is applicable for monitoring formate, tartarate, and sulfate levels. Next, an acid copper bath is used to electroplate the through holes with 0.001 inches of ductile copper. This bath is analyzed for trace chloride. Photoimaging is then performed, and the organic solvents used can be assayed for trace ionic chloride. Finally, a fluoroboric acid-based tin-lead bath is used to deposit a solderable alloy. This bath is analyzed for fluoroborate, tin, and lead. In addition, mobile phase ion chromatography (MPIC) is used to monitor the nonionic organic brighteners in the baths.

Correlation of the ionisation response at selected points of IC sensitive regions with SEE sensitivity parameters under pulsed laser irradiation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gordienko, A V; Mavritskii, O B; Egorov, A N

2014-12-31

The statistics of the ionisation response amplitude measured at selected points and their surroundings within sensitive regions of integrated circuits (ICs) under focused femtosecond laser irradiation is obtained for samples chosen from large batches of two types of ICs. A correlation between these data and the results of full-chip scanning is found for each type. The criteria for express validation of IC single-event effect (SEE) hardness based on ionisation response measurements at selected points are discussed. (laser applications and other topics in quantum electronics)

Integrated circuit layer image segmentation

NASA Astrophysics Data System (ADS)

Masalskis, Giedrius; Petrauskas, Romas

2010-09-01

In this paper we present IC layer image segmentation techniques which are specifically created for precise metal layer feature extraction. During our research we used many samples of real-life de-processed IC metal layer images which were obtained using optical light microscope. We have created sequence of various image processing filters which provides segmentation results of good enough precision for our application. Filter sequences were fine tuned to provide best possible results depending on properties of IC manufacturing process and imaging technology. Proposed IC image segmentation filter sequences were experimentally tested and compared with conventional direct segmentation algorithms.

Effect of Joule heating and current crowding on electromigration in mobile technology

NASA Astrophysics Data System (ADS)

Tu, K. N.; Liu, Yingxia; Li, Menglu

2017-03-01

In the present era of big data and internet of things, the use of microelectronic products in all aspects of our life is manifested by the ubiquitous presence of mobile devices as i-phones and wearable i-products. These devices are facing the need for higher power and greater functionality applications such as in i-health, yet they are limited by physical size. At the moment, software (Apps) is much ahead of hardware in mobile technology. To advance hardware, the end of Moore's law in two-dimensional integrated circuits can be extended by three-dimensional integrated circuits (3D ICs). The concept of 3D ICs has been with us for more than ten years. The challenge in 3D IC technology is dense packing by using both vertical and horizontal interconnections. Mass production of 3D IC devices is behind schedule due to cost because of low yield and uncertain reliability. Joule heating is serious in a dense structure because of heat generation and dissipation. A change of reliability paradigm has advanced from failure at a specific circuit component to failure at a system level weak-link. Currently, the electronic industry is introducing 3D IC devices in mainframe computers, where cost is not an issue, for the purpose of collecting field data of failure, especially the effect of Joule heating and current crowding on electromigration. This review will concentrate on the positive feedback between Joule heating and electromigration, resulting in an accelerated system level weak-link failure. A new driving force of electromigration, the electric potential gradient force due to current crowding, will be reviewed critically. The induced failure tends to occur in the low current density region.

The research of digital circuit system for high accuracy CCD of portable Raman spectrometer

NASA Astrophysics Data System (ADS)

Yin, Yu; Cui, Yongsheng; Zhang, Xiuda; Yan, Huimin

2013-08-01

The Raman spectrum technology is widely used for it can identify various types of molecular structure and material. The portable Raman spectrometer has become a hot direction of the spectrometer development nowadays for its convenience in handheld operation and real-time detection which is superior to traditional Raman spectrometer with heavy weight and bulky size. But there is still a gap for its measurement sensitivity between portable and traditional devices. However, portable Raman Spectrometer with Shell-Isolated Nanoparticle-Enhanced Raman Spectroscopy (SHINERS) technology can enhance the Raman signal significantly by several orders of magnitude, giving consideration in both measurement sensitivity and mobility. This paper proposed a design and implementation of driver and digital circuit for high accuracy CCD sensor, which is core part of portable spectrometer. The main target of the whole design is to reduce the dark current generation rate and increase signal sensitivity during the long integration time, and in the weak signal environment. In this case, we use back-thinned CCD image sensor from Hamamatsu Corporation with high sensitivity, low noise and large dynamic range. In order to maximize this CCD sensor's performance and minimize the whole size of the device simultaneously to achieve the project indicators, we delicately designed a peripheral circuit for the CCD sensor. The design is mainly composed with multi-voltage circuit, sequential generation circuit, driving circuit and A/D transition parts. As the most important power supply circuit, the multi-voltage circuits with 12 independent voltages are designed with reference power supply IC and set to specified voltage value by the amplifier making up the low-pass filter, which allows the user to obtain a highly stable and accurate voltage with low noise. What's more, to make our design easy to debug, CPLD is selected to generate sequential signal. The A/D converter chip consists of a correlated double sampler; a digitally controlled variable gain amplifier and a 16-bit A/D converter which can help improve the data quality. And the acquired digital signals are transmitted into the computer via USB 2.0 data port. Our spectrometer with SHINERS technology can acquire the Raman spectrum signals efficiently in long time integration and weak signal environment, and the size of our system is well controlled for portable application.

Temperature-Adaptive Circuits on Reconfigurable Analog Arrays

NASA Technical Reports Server (NTRS)

Stoica, Adrian; Zebulum, Ricardo S.; Keymeulen, Didier; Ramesham, Rajeshuni; Neff, Joseph; Katkoori, Srinivas

2006-01-01

Demonstration of a self-reconfigurable Integrated Circuit (IC) that would operate under extreme temperature (-180 C and 120 C) and radiation (300krad), without the protection of thermal controls and radiation shields. Self-Reconfigurable Electronics platform: a) Evolutionary Processor (EP) to run reconfiguration mechanism; b) Reconfigurable chip (FPGA, FPAA, etc).

Image Noise, CNR, and Detectability of Low-Contrast, Low-Attenuation Liver Lesions in a Phantom: Effects of Radiation Exposure, Phantom Size, Integrated Circuit Detector, and Iterative Reconstruction.

PubMed

Goenka, Ajit H; Herts, Brian R; Dong, Frank; Obuchowski, Nancy A; Primak, Andrew N; Karim, Wadih; Baker, Mark E

2016-08-01

Purpose To assess image noise, contrast-to-noise ratio (CNR) and detectability of low-contrast, low-attenuation liver lesions in a semianthropomorphic phantom by using either a discrete circuit (DC) detector and filtered back projection (FBP) or an integrated circuit (IC) detector and iterative reconstruction (IR) with changes in radiation exposure and phantom size. Materials and Methods An anthropomorphic phantom without or with a 5-cm-thick fat-mimicking ring (widths, 30 and 40 cm) containing liver inserts with four spherical lesions was scanned with five exposure settings on each of two computed tomography scanners, one equipped with a DC detector and the other with an IC detector. Images from the DC and IC detector scanners were reconstructed with FBP and IR, respectively. Image noise and lesion CNR were measured. Four radiologists evaluated lesion presence on a five-point diagnostic confidence scale. Data analyses included receiver operating characteristic (ROC) curve analysis and noninferiority analysis. Results The combination of IC and IR significantly reduced image noise (P < .001) (with the greatest reduction in the 40-cm phantom and at lower exposures) and improved lesion CNR (P < .001). There was no significant difference in area under the ROC curve between detector-reconstruction combinations at fixed exposure for either phantom. Reader accuracy with IC-IR was noninferior at 50% (100 mAs [effective]) and 25% (300 mAs [effective]) exposure reduction for the 30- and 40-cm phantoms, respectively (adjusted P < .001 and .04 respectively). IC-IR improved readers' confidence in the presence of a lesion (P = .029) independent of phantom size or exposure level. Conclusion IC-IR improved objective image quality and lesion detection confidence but did not result in superior diagnostic accuracy when compared with DC-FBP. Moderate exposure reductions maintained comparable diagnostic accuracy for both detector-reconstruction combinations. Lesion detection in the 40-cm phantom was inferior at smaller exposure reduction than in the 30-cm phantom. (©) RSNA, 2016 Online supplemental material is available for this article.

Radiation Testing and Evaluation Issues for Modern Integrated Circuits

NASA Technical Reports Server (NTRS)

LaBel, Kenneth A.; Cohn, Lew M.

2005-01-01

Abstract. Changes in modern integrated circuit (IC) technologies have modified the way we approach and conduct radiation tolerance and testing of electronics. These changes include scaling of geometries, new materials, new packaging technologies, and overall speed and device complexity challenges. In this short course section, we will identify and discuss these issues as they impact radiation testing, modeling, and effects mitigation of modern integrated circuits. The focus will be on CMOS-based technologies, however, other high performance technologies will be discussed where appropriate. The effects of concern will be: Single-Event Effects (SEE) and steady state total ionizing dose (TID) IC response. However, due to the growing use of opto-electronics in space systems issues concerning displacement damage testing will also be considered. This short course section is not intended to provide detailed "how-to-test" information, but simply provide a snapshot of current challenges and some of the approaches being considered.

60 V tolerance full symmetrical switch for battery monitor IC

NASA Astrophysics Data System (ADS)

Zhang, Qidong; Yang, Yintang; Chai, Changchun

2017-06-01

For stacked battery monitoring IC high speed and high precision voltage acquisition requirements, this paper introduces a kind of symmetrical type high voltage switch circuit. This kind of switch circuit uses the voltage following structure, which eliminates the leakage path of input signals. At the same time, this circuit adopts a high speed charge pump structure, in any case the input signal voltage is higher than the supply voltage, it can fast and accurately turn on high voltage MOS devices, and convert the battery voltage to an analog to digital converter. The proposed high voltage full symmetry switch has been implemented in a 0.18 μm BCD process; simulated and measured results show that the proposed switch can always work properly regardless of the polarity of the voltage difference between the input signal ports and an input signal higher than the power supply. Project supported by the National Natural Science Foundation of China (No. 61334003).

A review on high-resolution CMOS delay lines: towards sub-picosecond jitter performance.

PubMed

Abdulrazzaq, Bilal I; Abdul Halin, Izhal; Kawahito, Shoji; Sidek, Roslina M; Shafie, Suhaidi; Yunus, Nurul Amziah Md

2016-01-01

A review on CMOS delay lines with a focus on the most frequently used techniques for high-resolution delay step is presented. The primary types, specifications, delay circuits, and operating principles are presented. The delay circuits reported in this paper are used for delaying digital inputs and clock signals. The most common analog and digitally-controlled delay elements topologies are presented, focusing on the main delay-tuning strategies. IC variables, namely, process, supply voltage, temperature, and noise sources that affect delay resolution through timing jitter are discussed. The design specifications of these delay elements are also discussed and compared for the common delay line circuits. As a result, the main findings of this paper are highlighting and discussing the followings: the most efficient high-resolution delay line techniques, the trade-off challenge found between CMOS delay lines designed using either analog or digitally-controlled delay elements, the trade-off challenge between delay resolution and delay range and the proposed solutions for this challenge, and how CMOS technology scaling can affect the performance of CMOS delay lines. Moreover, the current trends and efforts used in order to generate output delayed signal with low jitter in the sub-picosecond range are presented.

Advanced Ultra-Violet (UV) Aircraft Fire Detection System. Volume 2. System Hardware Design, Software Design, and Test

DTIC Science & Technology

1982-08-01

REPORT SHT",, -ENGLAND A W*nson Match Company Saftey and Protion Division ISSUE " 3 (contd) HEADS 1 2 3 4 5 6 7 8 ,7 0 BITS iii ii The 832 tm inspection...input data buffering and output data buffering. 2.2.2.3.1. Power up, Reset Circuit To ensure correct system operation when power is first applied the...act in conjunction with R2, R3 and two buffer sections of IC2. When power is first applied , Cl is discharged, Via the pot chain divider of R2 and R3 the

Ultra-precision engineering in lithographic exposure equipment for the semiconductor industry.

PubMed

Schmidt, Robert-H Munnig

2012-08-28

The developments in lithographic tools for the production of an integrated circuit (IC) are ruled by 'Moore's Law': the density of components on an IC doubles in about every two years. The corresponding size reduction of the smallest detail in an IC entails several technological breakthroughs. The wafer scanner, the exposure system that defines those details, is the determining factor in these developments. This review deals with those aspects of the positioning systems inside these wafer scanners that enable the extension of Moore's Law into the future. The design of these systems is increasingly difficult because of the accuracy levels in the sub-nanometre range coupled with motion velocities of several metres per second. In addition to the use of feedback control for the reduction of errors, high-precision model-based feed-forward control is required with an almost ideally reproducible motion-system behaviour and a strict limitation of random disturbing events. The full mastering of this behaviour even includes material drift on an atomic scale and is decisive for the future success of these machines.

Addressing On-Chip Power Converstion and Dissipation Issues in Many-Core System-on-a-Chip Based on Conventional Silicon and Emerging Nanotechnologies

NASA Astrophysics Data System (ADS)

Ashenafi, Emeshaw

Integrated circuits (ICs) are moving towards system-on-a-chip (SOC) designs. SOC allows various small and large electronic systems to be implemented in a single chip. This approach enables the miniaturization of design blocks that leads to high density transistor integration, faster response time, and lower fabrication costs. To reap the benefits of SOC and uphold the miniaturization of transistors, innovative power delivery and power dissipation management schemes are paramount. This dissertation focuses on on-chip integration of power delivery systems and managing power dissipation to increase the lifetime of energy storage elements. We explore this problem from two different angels: On-chip voltage regulators and power gating techniques. On-chip voltage regulators reduce parasitic effects, and allow faster and efficient power delivery for microprocessors. Power gating techniques, on the other hand, reduce the power loss incurred by circuit blocks during standby mode. Power dissipation (Ptotal = Pstatic and Pdynamic) in a complementary metal-oxide semiconductor (CMOS) circuit comes from two sources: static and dynamic. A quadratic dependency on the dynamic switching power and a more than linear dependency on static power as a form of gate leakage (subthreshold current) exist. To reduce dynamic power loss, the supply power should be reduced. A significant reduction in power dissipation occurs when portions of a microprocessor operate at a lower voltage level. This reduction in supply voltage is achieved via voltage regulators or converters. Voltage regulators are used to provide a stable power supply to the microprocessor. The conventional off-chip switching voltage regulator contains a passive floating inductor, which is difficult to be implemented inside the chip due to excessive power dissipation and parasitic effects. Additionally, the inductor takes a very large chip area while hampering the scaling process. These limitations make passive inductor based on-chip regulator design very unattractive for SOC integration and multi-/many-core environments. To circumvent the challenges, three alternative techniques based on active circuit elements to replace the passive LC filter of the buck convertor are developed. The first inductorless on-chip switching voltage regulator architecture is based on a cascaded 2nd order multiple feedback (MFB) low-pass filter (LPF). This design has the ability to modulate to multiple voltage settings via pulse-with modulation (PWM). The second approach is a supplementary design utilizing a hybrid low drop-out scheme to lower the output ripple of the switching regulator over a wider frequency range. The third design approach allows the integration of an entire power management system within a single chipset by combining a highly efficient switching regulator with an intermittently efficient linear regulator (area efficient), for robust and highly efficient on-chip regulation. The static power (Pstatic) or subthreshold leakage power (Pleak) increases with technology scaling. To mitigate static power dissipation, power gating techniques are implemented. Power gating is one of the popular methods to manage leakage power during standby periods in low-power high-speed IC design. It works by using transistor based switches to shut down part of the circuit block and put them in the idle mode. The efficiency of a power gating scheme involves minimum Ioff and high Ion for the sleep transistor. A conventional sleep transistor circuit design requires an additional header, footer, or both switches to turn off the logic block. This additional transistor causes signal delay and increases the chip area. We propose two innovative designs for next generation sleep transistor designs. For an above threshold operation, we present a sleep transistor design based on fully depleted silicon-on-insulator (FDSOI) device. For a subthreshold circuit operation, we implement a sleep transistor utilizing the newly developed silicon-on-ferroelectric-insulator field effect transistor (SOFFET). In both of the designs, the ability to control the threshold voltage via bias voltage at the back gate makes both devices more flexible for sleep transistors design than a bulk MOSFET. The proposed approaches simplify the design complexity, reduce the chip area, eliminate the voltage drop by sleep transistor, and improve power dissipation. In addition, the design provides a dynamically controlled Vt for times when the circuit needs to be in a sleep or switching mode.

Two-Wire to Four-Wire Audio Converter

NASA Technical Reports Server (NTRS)

Talley, G. L., Jr; Seale, B. L.

1983-01-01

Simple circuit provides interface between normally incompatible voicecommunication lines. Circuit maintains 40 dB of isolation between input and output halves of four-wire line permitting two-wire line to be connected. Balancing potentiometer, Rg, adjusts gain of IC2 to null feed through from input to output. Adjustment is done on workbench just after assembly.

Scanning capacitance microscope as a tool for the characterization of integrated circuits

NASA Astrophysics Data System (ADS)

Born, A.; Wiesendanger, R.

With the decreasing size of integrated circuits (ICs), there is an increasing demand for the measurement of doping profiles with high spatial resolution. The scanning capacitance microscope (SCM) offers the possibility of measuring 2D dopant profiles with spatial resolution of less than 20 nm. A great problem of the SCM technique is the influence of previous measurements on subsequent ones. We have observed hysteresis in the SCM images and measured low-frequency C-V curves with high-frequency equipment. A theoretical model was developed to understand this phenomenon. We are now undertaking the first steps using the SCM as a standard device for the characterization of ICs.

Test aspects of the JPL Viterbi decoder

NASA Technical Reports Server (NTRS)

Breuer, M. A.

1989-01-01

The generation of test vectors and design-for-test aspects of the Jet Propulsion Laboratory (JPL) Very Large Scale Integration (VLSI) Viterbi decoder chip is discussed. Each processor integrated circuit (IC) contains over 20,000 gates. To achieve a high degree of testability, a scan architecture is employed. The logic has been partitioned so that very few test vectors are required to test the entire chip. In addition, since several blocks of logic are replicated numerous times on this chip, test vectors need only be generated for each block, rather than for the entire circuit. These unique blocks of logic have been identified and test sets generated for them. The approach employed for testing was to use pseudo-exhaustive test vectors whenever feasible. That is, each cone of logid is tested exhaustively. Using this approach, no detailed logic design or fault model is required. All faults which modify the function of a block of combinational logic are detected, such as all irredundant single and multiple stuck-at faults.

EROIC: a BiCMOS pseudo-gaussian shaping amplifier for high-resolution X-ray spectroscopy

NASA Astrophysics Data System (ADS)

Buzzetti, Siro; Guazzoni, Chiara; Longoni, Antonio

2003-10-01

We present the design and complete characterization of a fifth-order pseudo-gaussian shaping amplifier with 1 μs shaping time. The circuit is optimized for the read-out of signals coming from Silicon Drift Detectors for high-resolution X-ray spectroscopy. The novelty of the designed chip stands in the use of a current feedback loop to place the poles in the desired position on the s-plane. The amplifier has been designed in 0.8 μm BiCMOS technology and fully tested. The EROIC chip comprises also the peak stretcher, the peak detector, the output buffer to drive the external ADC and the pile-up rejection system. The circuit needs a single +5 V power supply and the dissipated power is 5 mW per channel. The digital outputs can be directly coupled to standard digital CMOS ICs. The measured integral-non-linearity of the whole chip is below 0.05% and the achieved energy resolution at the Mn Kα line detected by a 5 mm 2 Peltier-cooled Silicon Drift Detector is 167 eV FWHM.

Quantum-engineered interband cascade photovoltaic devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Razeghi, Manijeh; Tournié, Eric; Brown, Gail J.

2013-12-18

Quantum-engineered multiple stage photovoltaic (PV) devices are explored based on InAs/GaSb/AlSb interband cascade (IC) structures. These ICPV devices employ multiple discrete absorbers that are connected in series by widebandgap unipolar barriers using type-II heterostructure interfaces for facilitating carrier transport between cascade stages similar to IC lasers. The discrete architecture is beneficial for improving the collection efficiency and for spectral splitting by utilizing absorbers with different bandgaps. As such, the photo-voltages from each individual cascade stage in an ICPV device add together, creating a high overall open-circuit voltage, similar to conventional multi-junction tandem solar cells. Furthermore, photo-generated carriers can be collectedmore » with nearly 100% efficiency in each stage. This is because the carriers travel over only a single cascade stage, designed to be shorter than a typical diffusion length. The approach is of significant importance for operation at high temperatures where the diffusion length is reduced. Here, we will present our recent progress in the study of ICPV devices, which includes the demonstration of ICPV devices at room temperature and above with narrow bandgaps (e.g. 0.23 eV) and high open-circuit voltages. © (2013) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.« less

Driver-receiver combined optical transceiver modules for bidirectional optical interconnection

NASA Astrophysics Data System (ADS)

Park, Hyo-Hoon; Kang, Sae-Kyoung; Kim, Do-Won; Nga, Nguyen T. H.; Hwang, Sung-Hwan; Lee, Tae-Woo

2008-02-01

We review a bidirectional optical link scheme for memory-interface applications. A driver-receiver combined optical transceiver (TRx) modules was demonstrated on an optical printed-circuit board (OPCB) platform. To select the bidirectional electric input/output signals, a driver-receiver combined TRx IC with a switching function was designed in 0.18-μm CMOS technology. The TRx IC was integrated with VCSEL/PD chips for optical link in the TRx module. The optical TRx module was assembled on a fiber-embedded OPCB, employing a 90°-bent fiber connector for 90° deflection of light beams between the TRx module and the OPCB. The TRx module and the 90° connector were passively assembled on the OPCB, using ferrule-type guide pins/ holes. Employing these constituent components, the bidirectional optical link between a pair of TRx modules has been successfully demonstrated up to 1.25 Gb/s on the OPCB.

Experimental investigation on the thermal performance of Si micro-heat pipe with different cross-sections

NASA Astrophysics Data System (ADS)

Hamidnia, Mohammad; Luo, Yi; Wang, Xiaodong; Li, Congming

2017-10-01

Increasing component densities of the integrated circuit (IC) and packaging levels has led to thermal management problems. Si substrates with embedded micro-heat pipes (MHPs) couple good thermal characteristics and cost savings associated with IC batch processing. The thermal performance of MHP is intimately related to the cross-sectional geometry. Different cross-sections are designed in order to enhance the backflow of working fluid. In this experimental study, three different Si MHPs with same hydraulic diameter and various cross-sections are fabricated by micro-fabrication methods and tested under different conditions of fluid charge ratios. The results show that the trapezoidal MHP associated with rectangular artery which is charged with 40% of vapor chamber’s volume has the best thermal performance. This silicon-based MHP is a passive approach for thermal management, which could widen applications in the commercial electronics industry and LED lightings.

VCSEL-based optical transceiver module operating at 25 Gb/s and using a single CMOS IC

NASA Astrophysics Data System (ADS)

Afriat, Gil; Horwitz, Lior; Lazar, Dror; Issachar, Assaf; Pogrebinsky, Alexander; Ran, Adee; Shoor, Ehud; Bar, Roi; Saba, Rushdy

2012-01-01

We present here a low cost, small form factor, optical transceiver module composed of a CMOS IC transceiver, 850 nm emission wavelength VCSEL modulated at 25 Gb/s, and an InGaAs/InP PIN Photo Diode (PD). The transceiver IC is fabricated in a standard 28 nm CMOS process and integrates the analog circuits interfacing the VCSEL and PD, namely the VCSEL driver and Transimpedance Amplifier (TIA), as well as all other required transmitter and receiver circuits like Phase Locked Loop (PLL), Post Amplifier and Clock & Data Recovery (CDR). The transceiver module couples into a 62.5/125 um multi-mode (OM1) TX/RX fiber pair via a low cost plastic cover realizing the transmitter and receiver lens systems and demonstrates BER < 10-12 at the 25 Gb/s data rate over a distance of 3 meters. Using a 50/125 um laser optimized multi-mode fiber (OM3), the same performance was achieved over a distance of 30 meters.

Auditory cortex controls sound-driven innate defense behaviour through corticofugal projections to inferior colliculus

PubMed Central

Xiong, Xiaorui R.; Liang, Feixue; Zingg, Brian; Ji, Xu-ying; Ibrahim, Leena A.; Tao, Huizhong W.; Zhang, Li I.

2015-01-01

Defense against environmental threats is essential for animal survival. However, the neural circuits responsible for transforming unconditioned sensory stimuli and generating defensive behaviours remain largely unclear. Here, we show that corticofugal neurons in the auditory cortex (ACx) targeting the inferior colliculus (IC) mediate an innate, sound-induced flight behaviour. Optogenetic activation of these neurons, or their projection terminals in the IC, is sufficient for initiating flight responses, while the inhibition of these projections reduces sound-induced flight responses. Corticocollicular axons monosynaptically innervate neurons in the cortex of the IC (ICx), and optogenetic activation of the projections from the ICx to the dorsal periaqueductal gray is sufficient for provoking flight behaviours. Our results suggest that ACx can both amplify innate acoustic-motor responses and directly drive flight behaviours in the absence of sound input through corticocollicular projections to ICx. Such corticofugal control may be a general feature of innate defense circuits across sensory modalities. PMID:26068082

A microarchitecture for resource-limited superscalar microprocessors

NASA Astrophysics Data System (ADS)

Basso, Todd David

1999-11-01

Microelectronic components in space and satellite systems must be resistant to total dose radiation, single-even upset, and latchup in order to accomplish their missions. The demand for inexpensive, high-volume, radiation hardened (rad-hard) integrated circuits (ICs) is expected to increase dramatically as the communication market continues to expand. Motorola's Complementary Gallium Arsenide (CGaAsTM) technology offers superior radiation tolerance compared to traditional CMOS processes, while being more economical than dedicated rad-hard CMOS processes. The goals of this dissertation are to optimize a superscalar microarchitecture suitable for CGaAsTM microprocessors, develop circuit techniques for such applications, and evaluate the potential of CGaAsTM for the development of digital VLSI circuits. Motorola's 0.5 mum CGaAsTM process is summarized and circuit techniques applicable to digital CGaAsTM are developed. Direct coupled FET, complementary, and domino logic circuits are compared based on speed, power, area, and noise margins. These circuit techniques are employed in the design of a 600 MHz PowerPCTM arithmetic logic unit. The dissertation emphasizes CGaASTM-specific design considerations, specifically, low integration level. A baseline superscalar microarchitecture is defined and SPEC95 integer benchmark simulations are used to evaluate the applicability of advanced architectural features to microprocessors having low integration levels. The performance simulations center around the optimization of a simple superscalar core, small-scale branch prediction, instruction prefetching, and an off-chip primary data cache. The simulation results are used to develop a superscalar microarchitecture capable of outperforming a comparable sequential pipeline, while using only 500,000 transistors. The architecture, running at 200 MHz, is capable of achieving an estimated 153 MIPS, translating to a 27% performance increase over a comparable traditional pipelined microprocessor. The proposed microarchitecture is process independent and can be applied to low-cost, or transistor-limited applications. The proposed microarchitecture is implemented in the design of a 0.35 mum CMOS microprocessor, and the design of a 0.5 mum CGaAsTM micro-processor. The two technologies and designs are compared to ascertain the state of CGaAsTM for digital VLSI applications.

Attachment method for stacked integrated circuit (IC) chips

DOEpatents

Bernhardt, Anthony F.; Malba, Vincent

1999-01-01

An attachment method for stacked integrated circuit (IC) chips. The method involves connecting stacked chips, such as DRAM memory chips, to each other and/or to a circuit board. Pads on the individual chips are rerouted to form pads on the side of the chip, after which the chips are stacked on top of each other whereby desired interconnections to other chips or a circuit board can be accomplished via the side-located pads. The pads on the side of a chip are connected to metal lines on a flexible plastic tape (flex) by anisotropically conductive adhesive (ACA). Metal lines on the flex are likewise connected to other pads on chips and/or to pads on a circuit board. In the case of a stack of DRAM chips, pads to corresponding address lines on the various chips may be connected to the same metal line on the flex to form an address bus. This method has the advantage of reducing the number of connections required to be made to the circuit board due to bussing; the flex can accommodate dimensional variation in the alignment of chips in the stack; bonding of the ACA is accomplished at low temperature and is otherwise simpler and less expensive than solder bonding; chips can be bonded to the ACA all at once if the sides of the chips are substantially coplanar, as in the case for stacks of identical chips, such as DRAM.

Optical printed circuit board (O-PCB) and VLSI photonic integrated circuits: visions, challenges, and progresses

NASA Astrophysics Data System (ADS)

Lee, El-Hang; Lee, S. G.; O, B. H.; Park, S. G.; Noh, H. S.; Kim, K. H.; Song, S. H.

2006-09-01

A collective overview and review is presented on the original work conducted on the theory, design, fabrication, and in-tegration of micro/nano-scale optical wires and photonic devices for applications in a newly-conceived photonic systems called "optical printed circuit board" (O-PCBs) and "VLSI photonic integrated circuits" (VLSI-PIC). These are aimed for compact, high-speed, multi-functional, intelligent, light-weight, low-energy and environmentally friendly, low-cost, and high-volume applications to complement or surpass the capabilities of electrical PCBs (E-PCBs) and/or VLSI electronic integrated circuit (VLSI-IC) systems. These consist of 2-dimensional or 3-dimensional planar arrays of micro/nano-optical wires and circuits to perform the functions of all-optical sensing, storing, transporting, processing, switching, routing and distributing optical signals on flat modular boards or substrates. The integrated optical devices include micro/nano-scale waveguides, lasers, detectors, switches, sensors, directional couplers, multi-mode interference devices, ring-resonators, photonic crystal devices, plasmonic devices, and quantum devices, made of polymer, silicon and other semiconductor materials. For VLSI photonic integration, photonic crystals and plasmonic structures have been used. Scientific and technological issues concerning the processes of miniaturization, interconnection and integration of these systems as applicable to board-to-board, chip-to-chip, and intra-chip integration, are discussed along with applications for future computers, telecommunications, and sensor-systems. Visions and challenges toward these goals are also discussed.

Switched-capacitor realization of presynaptic short-term-plasticity and stop-learning synapses in 28 nm CMOS.

PubMed

Noack, Marko; Partzsch, Johannes; Mayr, Christian G; Hänzsche, Stefan; Scholze, Stefan; Höppner, Sebastian; Ellguth, Georg; Schüffny, Rene

2015-01-01

Synaptic dynamics, such as long- and short-term plasticity, play an important role in the complexity and biological realism achievable when running neural networks on a neuromorphic IC. For example, they endow the IC with an ability to adapt and learn from its environment. In order to achieve the millisecond to second time constants required for these synaptic dynamics, analog subthreshold circuits are usually employed. However, due to process variation and leakage problems, it is almost impossible to port these types of circuits to modern sub-100nm technologies. In contrast, we present a neuromorphic system in a 28 nm CMOS process that employs switched capacitor (SC) circuits to implement 128 short term plasticity presynapses as well as 8192 stop-learning synapses. The neuromorphic system consumes an area of 0.36 mm(2) and runs at a power consumption of 1.9 mW. The circuit makes use of a technique for minimizing leakage effects allowing for real-time operation with time constants up to several seconds. Since we rely on SC techniques for all calculations, the system is composed of only generic mixed-signal building blocks. These generic building blocks make the system easy to port between technologies and the large digital circuit part inherent in an SC system benefits fully from technology scaling.

A neural circuit transforming temporal periodicity information into a rate-based representation in the mammalian auditory system.

PubMed

Dicke, Ulrike; Ewert, Stephan D; Dau, Torsten; Kollmeier, Birger

2007-01-01

Periodic amplitude modulations (AMs) of an acoustic stimulus are presumed to be encoded in temporal activity patterns of neurons in the cochlear nucleus. Physiological recordings indicate that this temporal AM code is transformed into a rate-based periodicity code along the ascending auditory pathway. The present study suggests a neural circuit for the transformation from the temporal to the rate-based code. Due to the neural connectivity of the circuit, bandpass shaped rate modulation transfer functions are obtained that correspond to recorded functions of inferior colliculus (IC) neurons. In contrast to previous modeling studies, the present circuit does not employ a continuously changing temporal parameter to obtain different best modulation frequencies (BMFs) of the IC bandpass units. Instead, different BMFs are yielded from varying the number of input units projecting onto different bandpass units. In order to investigate the compatibility of the neural circuit with a linear modulation filterbank analysis as proposed in psychophysical studies, complex stimuli such as tones modulated by the sum of two sinusoids, narrowband noise, and iterated rippled noise were processed by the model. The model accounts for the encoding of AM depth over a large dynamic range and for modulation frequency selective processing of complex sounds.

Half-dose non-contrast CT in the investigation of urolithiasis: image quality improvement with third-generation integrated circuit CT detectors.

PubMed

Wang, Jun; Kang, Tony; Arepalli, Chesnal; Barrett, Sarah; O'Connell, Tim; Louis, Luck; Nicolaou, Savvakis; McLaughlin, Patrick

2015-06-01

The objective of this study is to establish the effect of third-generation integrated circuit (IC) CT detector on objective image quality in full- and half-dose non-contrast CT of the urinary tract. 51 consecutive patients with acute renal colic underwent non-contrast CT of the urinary tract using a 128-slice dual-source CT before (n = 24) and after (n = 27) the installation of third-generation IC detectors. Half-dose images were generated using projections from detector A using the dual-source RAW data. Objective image noise in the liver, spleen, right renal cortex, and right psoas muscle was compared between DC and IC cohorts for full-dose and half-dose images reconstructed with FBP and IR algorithms using 1 cm(2) regions of interest. Presence and size of obstructing ureteric calculi were also compared for full-dose and half-dose reconstructions using DC and IC detectors. No statistical difference in age and lateral body size was found between patients in the IC and DC cohorts. Radiation dose, as measured by size-specific dose estimates, did not differ significantly either between the two cohorts (10.02 ± 4.54 mGy IC vs. 12.28 ± 7.03 mGy DC). At full dose, objective image noise was not significantly lower in the IC cohort as compared to the DC cohort for the liver, spleen, and right psoas muscle. At half dose, objective image noise was lower in the IC cohort as compared to DC cohort at the liver (21.32 IC vs. 24.99 DC, 14.7% decrease, p < 0.001), spleen (19.33 IC vs. 20.83 DC, 7.20% decrease, p = 0.02), and right renal cortex (20.28 IC vs. 22.98 DC, 11.7% decrease, p = 0.005). Mean obstructing ureteric calculi size was not significantly different when comparison was made between full-dose and half-dose images, regardless of detector type (p > 0.05 for all comparisons). Third-generation IC detectors result in lower objective image noise at full- and half-radiation dose levels as compared with traditional DC detectors. The magnitude of noise reduction was greater at half-radiation dose indicating that the benefits of using novel IC detectors are greater in low and ultra-low-dose CT imaging.

Night-day-night sleep-wakefulness monitoring by ambulatory integrated circuit memories.

PubMed

Yamamoto, M; Nakao, M; Katayama, N; Waku, M; Suzuki, K; Irokawa, K; Abe, M; Ueno, T

1999-04-01

A medium-sized portable digital recorder with fully integrated circuit (IC) memories for sleep monitoring has been developed. It has five amplifiers for EEG, EMG, EOG, ECG, and a signal of body acceleration or respiration sound, four event markers, an 8 ch A/D converter, a digital signal processor (DSP), 192 Mbytes IC flash memories, and batteries. The whole system weighs 1200 g including batteries and is put into a small bag worn on the subject's waist or carried in their hand. The sampling rate for each input channel is programmable through the DSP. This apparatus is valuable for continuously monitoring the states of sleep-wakefulness over 24 h, making a night-day-night recording possible in a hospital, home, or car.

MEDUSA-32: A low noise, low power silicon strip detector front-end electronics, for space applications

NASA Astrophysics Data System (ADS)

Cicuttin, Andres; Colavita, Alberto; Cerdeira, Alberto; Fratnik, Fabio; Vacchi, Andrea

1997-02-01

In this report we describe a mixed analog-digital integrated circuit (IC) designed as the front-end electronics for silicon strip-detectors for space applications. In space power consumption, compactness and robustness become critical constraints for a pre-amplifier design. The IC is a prototype with 32 complete channels, and it is intended for a large area particle tracker of a new generation of gamma ray telescopes. Each channel contains a charge sensitive amplifier, a pulse shaper, a discriminator and two digital buffers. The reference trip point of the discriminator is adjustable. This chip also has a custom PMOSFET transistor per channel, included in order to provide the high dynamic resistance needed to reverse-bias the strip diode. The digital part of the chip is used to store and serially shift out the state of the channels. There is also a storage buffer that allows the disabling of non-functioning channels if it is required by the data acquisition system. An input capacitance of 30 pF introduced at the input of the front-end produces less than 1000 electrons of RMS equivalent noise charge (ENC), for a total power dissipation of only 60 μW per channel. The chip was made using Orbit's 1.2 μm double poly, double metal n-well low noise CMOS process. The dimensions of the IC are 2400 μm × 8840 μm.

Design of remote control alarm system by microwave detection

NASA Astrophysics Data System (ADS)

Wang, Junli

2018-04-01

A microwave detection remote control alarm system is designed, which is composed of a Microwave detectors, a radio receiving/transmitting module and a digital encoding/decoding IC. When some objects move into the surveillance area, microwave detectors will generate a control signal to start transmitting system. A radio control signal will be spread by the transmitting module, once the signal can be received, and it will be disposed by some circuits, arousing some voices that awake the watching people. The whole device is a modular configuration, it not only has some advantage of frequency stable, but also reliable and adjustment-free, and it is suitable for many kinds of demands within the distance of 100m.

Analysis of a Statistical Relationship Between Dose and Error Tallies in Semiconductor Digital Integrated Circuits for Application to Radiation Monitoring Over a Wireless Sensor Network

NASA Astrophysics Data System (ADS)

Colins, Karen; Li, Liqian; Liu, Yu

2017-05-01

Mass production of widely used semiconductor digital integrated circuits (ICs) has lowered unit costs to the level of ordinary daily consumables of a few dollars. It is therefore reasonable to contemplate the idea of an engineered system that consumes unshielded low-cost ICs for the purpose of measuring gamma radiation dose. Underlying the idea is the premise of a measurable correlation between an observable property of ICs and radiation dose. Accumulation of radiation-damage-induced state changes or error events is such a property. If correct, the premise could make possible low-cost wide-area radiation dose measurement systems, instantiated as wireless sensor networks (WSNs) with unshielded consumable ICs as nodes, communicating error events to a remote base station. The premise has been investigated quantitatively for the first time in laboratory experiments and related analyses performed at the Canadian Nuclear Laboratories. State changes or error events were recorded in real time during irradiation of samples of ICs of different types in a 60Co gamma cell. From the error-event sequences, empirical distribution functions of dose were generated. The distribution functions were inverted and probabilities scaled by total error events, to yield plots of the relationship between dose and error tallies. Positive correlation was observed, and discrete functional dependence of dose quantiles on error tallies was measured, demonstrating the correctness of the premise. The idea of an engineered system that consumes unshielded low-cost ICs in a WSN, for the purpose of measuring gamma radiation dose over wide areas, is therefore tenable.

Four-Channel PC/104 MIL-STD-1553 Circuit Board

NASA Technical Reports Server (NTRS)

Cox, Gary L.

2004-01-01

The mini bus interface card (miniBIC) is the first four-channel electronic circuit board that conforms to MIL-STD-1553 and to the electrical-footprint portion of PC/104. [MIL-STD-1553 is a military standard that encompasses a method of communication and electrical- interface requirements for digital electronic subsystems connected to a data bus. PC/104 is an industry standard for compact, stackable modules that are fully compatible (in architecture, hardware, and software) with personal-computer data- and power-bus circuitry.] Prior to the development of the miniBIC, only one- and two-channel PC/104 MIL-STD-1553 boards were available. To obtain four channels, it was necessary to include at least two boards in a PC/104 stack. In comparison with such a two-board stack, the miniBIC takes up less space, consumes less power, and is more reliable. In addition, the miniBIC includes 32 digital input/output channels. The miniBIC (see figure) contains four MIL-STD-1553B hybrid integrated circuits (ICs), four transformers, a field-programmable gate array (FPGA), and an Industry Standard Architecture (ISA) interface. Each hybrid IC includes a MILSTD-1553 dual transceiver, memory-management circuitry, processor interface logic circuitry, and 64Kx16 bits of shared static random access memory. The memory is used to configure message and data blocks. In addition, 23 16-bit registers are available for (1) configuring the hybrid IC for, and starting it in, various modes of operation; (2) reading the status of the functionality of the hybrid IC; and (3) resetting the hybrid IC to a known state. The miniBIC can operate as a remote terminal, bus controller, or bus monitor. The FPGA provides the chip-select and data-strobe signals needed for operation of the hybrid ICs. The FPGA also receives interruption signals and forwards them to the ISA bus. The ISA interface connects the address, data, and control interfaces of the hybrid ICs to the ISA backplane. Each channel is, in effect, a MIL-STD-1553 interface that can operate either independently of the others or else as a redundant version of one of the others. The transformer in each channel provides electrical isolation between the rest of the miniBIC circuitry and the bus to which that channel is connected.

Design and fabrication of vertically-integrated CMOS image sensors.

PubMed

Skorka, Orit; Joseph, Dileepan

2011-01-01

Technologies to fabricate integrated circuits (IC) with 3D structures are an emerging trend in IC design. They are based on vertical stacking of active components to form heterogeneous microsystems. Electronic image sensors will benefit from these technologies because they allow increased pixel-level data processing and device optimization. This paper covers general principles in the design of vertically-integrated (VI) CMOS image sensors that are fabricated by flip-chip bonding. These sensors are composed of a CMOS die and a photodetector die. As a specific example, the paper presents a VI-CMOS image sensor that was designed at the University of Alberta, and fabricated with the help of CMC Microsystems and Micralyne Inc. To realize prototypes, CMOS dies with logarithmic active pixels were prepared in a commercial process, and photodetector dies with metal-semiconductor-metal devices were prepared in a custom process using hydrogenated amorphous silicon. The paper also describes a digital camera that was developed to test the prototype. In this camera, scenes captured by the image sensor are read using an FPGA board, and sent in real time to a PC over USB for data processing and display. Experimental results show that the VI-CMOS prototype has a higher dynamic range and a lower dark limit than conventional electronic image sensors.

Design and Fabrication of Vertically-Integrated CMOS Image Sensors

PubMed Central

Skorka, Orit; Joseph, Dileepan

2011-01-01

Technologies to fabricate integrated circuits (IC) with 3D structures are an emerging trend in IC design. They are based on vertical stacking of active components to form heterogeneous microsystems. Electronic image sensors will benefit from these technologies because they allow increased pixel-level data processing and device optimization. This paper covers general principles in the design of vertically-integrated (VI) CMOS image sensors that are fabricated by flip-chip bonding. These sensors are composed of a CMOS die and a photodetector die. As a specific example, the paper presents a VI-CMOS image sensor that was designed at the University of Alberta, and fabricated with the help of CMC Microsystems and Micralyne Inc. To realize prototypes, CMOS dies with logarithmic active pixels were prepared in a commercial process, and photodetector dies with metal-semiconductor-metal devices were prepared in a custom process using hydrogenated amorphous silicon. The paper also describes a digital camera that was developed to test the prototype. In this camera, scenes captured by the image sensor are read using an FPGA board, and sent in real time to a PC over USB for data processing and display. Experimental results show that the VI-CMOS prototype has a higher dynamic range and a lower dark limit than conventional electronic image sensors. PMID:22163860

SPICE Modeling of Body Bias Effect in 4H-SiC Integrated Circuit Resistors

NASA Technical Reports Server (NTRS)

Neudeck, Philip G.

2017-01-01

The DC electrical behavior of n-type 4H-SiC resistors used for realizing 500C durable integrated circuits (ICs) is studied as a function of substrate bias and temperature. Improved fidelity electrical simulation is described using SPICE NMOS model to simulate resistor substrate body bias effect that is absent from the SPICE semiconductor resistor model.

Ambient temperature cadmium zinc telluride radiation detector and amplifier circuit

DOEpatents

McQuaid, James H.; Lavietes, Anthony D.

1998-05-29

A low noise, low power consumption, compact, ambient temperature signal amplifier for a Cadmium Zinc Telluride (CZT) radiation detector. The amplifier can be used within a larger system (e.g., including a multi-channel analyzer) to allow isotopic analysis of radionuclides in the field. In one embodiment, the circuit stages of the low power, low noise amplifier are constructed using integrated circuit (IC) amplifiers , rather than discrete components, and include a very low noise, high gain, high bandwidth dual part preamplification stage, an amplification stage, and an filter stage. The low noise, low power consumption, compact, ambient temperature amplifier enables the CZT detector to achieve both the efficiency required to determine the presence of radio nuclides and the resolution necessary to perform isotopic analysis to perform nuclear material identification. The present low noise, low power, compact, ambient temperature amplifier enables a CZT detector to achieve resolution of less than 3% full width at half maximum at 122 keV for a Cobalt-57 isotope source. By using IC circuits and using only a single 12 volt supply and ground, the novel amplifier provides significant power savings and is well suited for prolonged portable in-field use and does not require heavy, bulky power supply components.

NASA Tech Briefs, July 1999. Volume 23, No. 7

NASA Technical Reports Server (NTRS)

1999-01-01

Topics: Test and Measurement; Electronic Components and Circuits; Electronic Systems; Physical Sciences; Materials; Computer Software; Mechanics; Machinery/Automation; Bio-Medical; Books and Reports; Semiconductors/ICs.

The Effectiveness of TAG or Guard-Gates in SET Suppression Using Delay and Dual-Rail Configurations at 0.35 microns

NASA Technical Reports Server (NTRS)

Shuler, Robert L.; Balasubramanian, Anupama; Narasimham, Balaji; Bhuva, Bharat; O'Neill, Patrick M.; Kouba, Coy

2006-01-01

Design options for decreasing the susceptibility of integrated circuits to Single Event Upset (SEU) fall into two categories: (1) increasing the critical charge to cause an upset at a particular node, and (2) employing redundancy to mask or correct errors. With decreasing device sizes on an Integrated Circuit (IC), the amount of charge required to represent a logic state has steadily reduced. Critical charge methods such as increasing drive strength or increasing the time required to change state as in capacitive or resistive hardening or delay based approaches extract a steadily increasing penalty as a percentage of device resources and performance. Dual redundancy is commonly assumed only to provide error detection with Triple Modular Redundancy (TMR) required for correction, but less well known methods employ dual redundancy to achieve full error correction by voting two inputs with a prior state to resolve ambiguity. This requires special circuits such as the Whitaker latch [1], or the guard-gate [2] which some of us have called a Transition AND Gate (TAG) [3]. A 2-input guard gate is shown in Figure 1. It is similar to a Muller Completion Element [4] and relies on capacitance at node "out" to retain the prior state when inputs disagree, while eliminating any output buffer which would be susceptible to radiation strikes. This paper experimentally compares delay based and dual rail flip-flop designs wherein both types of circuits employ guard-gates to optimize layout and performance, and draws conclusions about design criteria and suitability of each option. In both cases a design goal is protection against Single Event Transients (SET) in combinational logic as well as SEU in the storage elements. For the delay based design, it is also a goal to allow asynchronous clear or preset inputs on the storage elements, which are often not available in radiation tolerant designs.

Electromigration failures under bidirectional current stress

NASA Astrophysics Data System (ADS)

Tao, Jiang; Cheung, Nathan W.; Hu, Chenming

1998-01-01

Electromigration failure under DC stress has been studied for more than 30 years, and the methodologies for accelerated DC testing and design rules have been well established in the IC industry. However, the electromigration behavior and design rules under time-varying current stress are still unclear. In CMOS circuits, as many interconnects carry pulsed-DC (local VCC and VSS lines) and bidirectional AC current (clock and signal lines), it is essential to assess the reliability of metallization systems under these conditions. Failure mechanisms of different metallization systems (Al-Si, Al-Cu, Cu, TiN/Al-alloy/TiN, etc.) and different metallization structures (via, plug and interconnect) under AC current stress in a wide frequency range (from mHz to 500 MHz) has been study in this paper. Based on these experimental results, a damage healing model is developed, and electromigration design rules are proposed. It shows that in the circuit operating frequency range, the "design-rule current" is the time-average current. The pure AC component of the current only contributes to self-heating, while the average (DC component) current contributes to electromigration. To ensure longer thermal-migration lifetime under high frequency AC stress, an additional design rule is proposed to limit the temperature rise due to self-joule heating.

Experimentally Observed Electrical Durability of 4H-SiC JFET ICs Operating from 500 C to 700 C

NASA Technical Reports Server (NTRS)

Neudeck, Philip G.; Spry, David J.; Chen, Liangyu; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.

2016-01-01

Prolonged 500 degrees Celsius to 700 degrees Celsius electrical testing data from 4H-SiC junction field effect transistor (JFET) integrated circuits (ICs) are combined with post-testing microscopic studies in order to gain more comprehensive understanding of the durability limits of the present version of NASA Glenn's extreme temperature microelectronics technology. The results of this study support the hypothesis that T = 500 degrees Celsius durability-limiting IC failure initiates with thermal-stress-related crack formation where dielectric passivation layers overcoat micron-scale vertical features including patterned metal traces.

Development of high-performance printed organic field-effect transistors and integrated circuits.

PubMed

Xu, Yong; Liu, Chuan; Khim, Dongyoon; Noh, Yong-Young

2015-10-28

Organic electronics is regarded as an important branch of future microelectronics especially suited for large-area, flexible, transparent, and green devices, with their low cost being a key benefit. Organic field-effect transistors (OFETs), the primary building blocks of numerous expected applications, have been intensively studied, and considerable progress has recently been made. However, there are still a number of challenges to the realization of high-performance OFETs and integrated circuits (ICs) using printing technologies. Therefore, in this perspective article, we investigate the main issues concerning developing high-performance printed OFETs and ICs and seek strategies for further improvement. Unlike many other studies in the literature that deal with organic semiconductors (OSCs), printing technology, and device physics, our study commences with a detailed examination of OFET performance parameters (e.g., carrier mobility, threshold voltage, and contact resistance) by which the related challenges and potential solutions to performance development are inspected. While keeping this complete understanding of device performance in mind, we check the printed OFETs' components one by one and explore the possibility of performance improvement regarding device physics, material engineering, processing procedure, and printing technology. Finally, we analyze the performance of various organic ICs and discuss ways to optimize OFET characteristics and thus develop high-performance printed ICs for broad practical applications.

Low-power analog integrated circuits for wireless ECG acquisition systems.

PubMed

Tsai, Tsung-Heng; Hong, Jia-Hua; Wang, Liang-Hung; Lee, Shuenn-Yuh

2012-09-01

This paper presents low-power analog ICs for wireless ECG acquisition systems. Considering the power-efficient communication in the body sensor network, the required low-power analog ICs are developed for a healthcare system through miniaturization and system integration. To acquire the ECG signal, a low-power analog front-end system, including an ECG signal acquisition board, an on-chip low-pass filter, and an on-chip successive-approximation analog-to-digital converter for portable ECG detection devices is presented. A quadrature CMOS voltage-controlled oscillator and a 2.4 GHz direct-conversion transmitter with a power amplifier and upconversion mixer are also developed to transmit the ECG signal through wireless communication. In the receiver, a 2.4 GHz fully integrated CMOS RF front end with a low-noise amplifier, differential power splitter, and quadrature mixer based on current-reused folded architecture is proposed. The circuits have been implemented to meet the specifications of the IEEE 802.15.4 2.4 GHz standard. The low-power ICs of the wireless ECG acquisition systems have been fabricated using a 0.18 μm Taiwan Semiconductor Manufacturing Company (TSMC) CMOS standard process. The measured results on the human body reveal that ECG signals can be acquired effectively by the proposed low-power analog front-end ICs.

Design and Evaluation of a Clock Multiplexing Circuit for the SSRL Booster Accelerator Timing System - Oral Presentation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Araya, Million

2015-08-25

SPEAR3 is a 234 m circular storage ring at SLAC’s synchrotron radiation facility (SSRL) in which a 3 GeV electron beam is stored for user access. Typically the electron beam decays with a time constant of approximately 10hr due to electron lose. In order to replenish the lost electrons, a booster synchrotron is used to accelerate fresh electrons up to 3GeV for injection into SPEAR3. In order to maintain a constant electron beam current of 500mA, the injection process occurs at 5 minute intervals. At these times the booster synchrotron accelerates electrons for injection at a 10Hz rate. A 10Hzmore » 'injection ready' clock pulse train is generated when the booster synchrotron is operating. Between injection intervalswhere the booster is not running and hence the 10 Hz ‘injection ready’ signal is not present-a 10Hz clock is derived from the power line supplied by Pacific Gas and Electric (PG&E) to keep track of the injection timing. For this project I constructed a multiplexing circuit to 'switch' between the booster synchrotron 'injection ready' clock signal and PG&E based clock signal. The circuit uses digital IC components and is capable of making glitch-free transitions between the two clocks. This report details construction of a prototype multiplexing circuit including test results and suggests improvement opportunities for the final design.« less

Design and Evaluation of a Clock Multiplexing Circuit for the SSRL Booster Accelerator Timing System - Final Paper

DOE Office of Scientific and Technical Information (OSTI.GOV)

Araya, Million

2015-08-21

SPEAR3 is a 234 m circular storage ring at SLAC’s synchrotron radiation facility (SSRL) in which a 3 GeV electron beam is stored for user access. Typically the electron beam decays with a time constant of approximately 10hr due to electron lose. In order to replenish the lost electrons, a booster synchrotron is used to accelerate fresh electrons up to 3GeV for injection into SPEAR3. In order to maintain a constant electron beam current of 500mA, the injection process occurs at 5 minute intervals. At these times the booster synchrotron accelerates electrons for injection at a 10Hz rate. A 10Hzmore » 'injection ready' clock pulse train is generated when the booster synchrotron is operating. Between injection intervals-where the booster is not running and hence the 10 Hz ‘injection ready’ signal is not present-a 10Hz clock is derived from the power line supplied by Pacific Gas and Electric (PG&E) to keep track of the injection timing. For this project I constructed a multiplexing circuit to 'switch' between the booster synchrotron 'injection ready' clock signal and PG&E based clock signal. The circuit uses digital IC components and is capable of making glitch-free transitions between the two clocks. This report details construction of a prototype multiplexing circuit including test results and suggests improvement opportunities for the final design.« less

Attachment method for stacked integrated circuit (IC) chips

DOEpatents

Bernhardt, A.F.; Malba, V.

1999-08-03

An attachment method for stacked integrated circuit (IC) chips is disclosed. The method involves connecting stacked chips, such as DRAM memory chips, to each other and/or to a circuit board. Pads on the individual chips are rerouted to form pads on the side of the chip, after which the chips are stacked on top of each other whereby desired interconnections to other chips or a circuit board can be accomplished via the side-located pads. The pads on the side of a chip are connected to metal lines on a flexible plastic tape (flex) by anisotropically conductive adhesive (ACA). Metal lines on the flex are likewise connected to other pads on chips and/or to pads on a circuit board. In the case of a stack of DRAM chips, pads to corresponding address lines on the various chips may be connected to the same metal line on the flex to form an address bus. This method has the advantage of reducing the number of connections required to be made to the circuit board due to bussing; the flex can accommodate dimensional variation in the alignment of chips in the stack; bonding of the ACA is accomplished at low temperature and is otherwise simpler and less expensive than solder bonding; chips can be bonded to the ACA all at once if the sides of the chips are substantially coplanar, as in the case for stacks of identical chips, such as DRAM. 12 figs.

Surface-micromachined and high-aspect ratio electrostatic actuators for aeronautic and space applications: design and lifetime considerations

NASA Astrophysics Data System (ADS)

Vescovo, P.; Joseph, E.; Bourbon, G.; Le Moal, P.; Minotti, P.; Hibert, C.; Pont, G.

2003-09-01

This paper focuses on recent advances in the field of MEMS-based actuators and distributed microelectromechanical systems (MEMS). IC-processed actuators (e.g. actuators that are machined using integrated circuit batch processes) are expected to open a wide range of industrial applications on the near term. The most promising investigations deal with high-aspect ratio electric field driven microactuators suitable for use in numerous technical fields such as aeronautics and space industry. Because the silicon micromachining technology have the potential to integrate both mechanical components and control circuits within a single process, MEMS-based active control of microscopic and macroscopic structures appears to be one of the most promising challenges for the next decade. As a first step towards new generations of MEMS-based smart structures, recent investigations dealing with silicon mechanisms involving MEMS-based actuators are briefly discussed in this paper.

The Insula and Taste Learning

PubMed Central

Yiannakas, Adonis; Rosenblum, Kobi

2017-01-01

The sense of taste is a key component of the sensory machinery, enabling the evaluation of both the safety as well as forming associations regarding the nutritional value of ingestible substances. Indicative of the salience of the modality, taste conditioning can be achieved in rodents upon a single pairing of a tastant with a chemical stimulus inducing malaise. This robust associative learning paradigm has been heavily linked with activity within the insular cortex (IC), among other regions, such as the amygdala and medial prefrontal cortex. A number of studies have demonstrated taste memory formation to be dependent on protein synthesis at the IC and to correlate with the induction of signaling cascades involved in synaptic plasticity. Taste learning has been shown to require the differential involvement of dopaminergic GABAergic, glutamatergic, muscarinic neurotransmission across an extended taste learning circuit. The subsequent activation of downstream protein kinases (ERK, CaMKII), transcription factors (CREB, Elk-1) and immediate early genes (c-fos, Arc), has been implicated in the regulation of the different phases of taste learning. This review discusses the relevant neurotransmission, molecular signaling pathways and genetic markers involved in novel and aversive taste learning, with a particular focus on the IC. Imaging and other studies in humans have implicated the IC in the pathophysiology of a number of cognitive disorders. We conclude that the IC participates in circuit-wide computations that modulate the interception and encoding of sensory information, as well as the formation of subjective internal representations that control the expression of motivated behaviors. PMID:29163022

NASA Tech Briefs, September 2000. Volume 24, No. 9

NASA Technical Reports Server (NTRS)

2000-01-01

Topics include: Sensors; Test and Measurement; Electronic Components and Circuits; Electronic Systems; Physical Sciences; Materials; Computer Programs; Mechanics; Machinery/Automation; Bio-Medical; semiconductors/ICs; Books and Reports.

Intermetallic compounds in 3D integrated circuits technology: a brief review

NASA Astrophysics Data System (ADS)

Annuar, Syahira; Mahmoodian, Reza; Hamdi, Mohd; Tu, King-Ning

2017-12-01

The high performance and downsizing technology of three-dimensional integrated circuits (3D-ICs) for mobile consumer electronic products have gained much attention in the microelectronics industry. This has been driven by the utilization of chip stacking by through-Si-via and solder microbumps. Pb-free solder microbumps are intended to replace conventional Pb-containing solder joints due to the rising awareness of environmental preservation. The use of low-volume solder microbumps has led to crucial constraints that cause several reliability issues, including excessive intermetallic compounds (IMCs) formation and solder microbump embrittlement due to IMCs growth. This article reviews technologies related to 3D-ICs, IMCs formation mechanisms and reliability issues concerning IMCs with Pb-free solder microbumps. Finally, future outlook on the potential growth of research in this area is discussed.

Intermetallic compounds in 3D integrated circuits technology: a brief review.

PubMed

Annuar, Syahira; Mahmoodian, Reza; Hamdi, Mohd; Tu, King-Ning

2017-01-01

The high performance and downsizing technology of three-dimensional integrated circuits (3D-ICs) for mobile consumer electronic products have gained much attention in the microelectronics industry. This has been driven by the utilization of chip stacking by through-Si-via and solder microbumps. Pb-free solder microbumps are intended to replace conventional Pb-containing solder joints due to the rising awareness of environmental preservation. The use of low-volume solder microbumps has led to crucial constraints that cause several reliability issues, including excessive intermetallic compounds (IMCs) formation and solder microbump embrittlement due to IMCs growth. This article reviews technologies related to 3D-ICs, IMCs formation mechanisms and reliability issues concerning IMCs with Pb-free solder microbumps. Finally, future outlook on the potential growth of research in this area is discussed.

Device-level and module-level three-dimensional integrated circuits created using oblique processing

NASA Astrophysics Data System (ADS)

Burckel, D. Bruce

2016-07-01

This paper demonstrates that another class of three-dimensional integrated circuits (3-D-ICs) exists, distinct from through-silicon-via-centric and monolithic 3-D-ICs. Furthermore, it is possible to create devices that are 3-D "at the device level" (i.e., with active channels oriented in each of the three coordinate axes), by performing standard CMOS fabrication operations at an angle with respect to the wafer surface into high aspect ratio silicon substrates using membrane projection lithography (MPL). MPL requires only minimal fixturing changes to standard CMOS equipment, and no change to current state-of-the-art lithography. Eliminating the constraint of two-dimensional planar device architecture enables a wide range of interconnect topologies which could help reduce interconnect resistance/capacitance, and potentially improve performance.

Non-invasive current and voltage imaging techniques for integrated circuits using scanning probe microscopy. Final report, LDRD Project FY93 and FY94

DOE Office of Scientific and Technical Information (OSTI.GOV)

Campbell, A.N.; Cole, E.I. Jr.; Tangyunyong, Paiboon

This report describes the first practical, non-invasive technique for detecting and imaging currents internal to operating integrated circuits (ICs). This technique is based on magnetic force microscopy and was developed under Sandia National Laboratories` LDRD (Laboratory Directed Research and Development) program during FY 93 and FY 94. LDRD funds were also used to explore a related technique, charge force microscopy, for voltage probing of ICs. This report describes the technical work performed under this LDRD as well as the outcomes of the project in terms of publications and awards, intellectual property and licensing, synergistic work, potential future work, hiring ofmore » additional permanent staff, and benefits to DOE`s defense programs (DP).« less

Integrated mixed signal control IC for 500-kHz switching frequency buck regulator

NASA Astrophysics Data System (ADS)

Chen, Keng; Zhang, Hong

2015-12-01

The main purpose for this work is to study the challenges of designing a digital buck regulator using pipelined analog to digital converter (ADC). Although pipelined ADC can achieve high sampling speed, it will introduce additional phase lag to the buck circuit. Along with the latency brought by processing time of additional digital circuits, as well as the time delay associated with the switching frequency, the closed loop will be unstable; moreover, raw ADC outputs have low signal-to-noise ratio, which usually need back-end calibration. In order to compensate these phase lag and make control loop unconditional stable, as well as boost up signal-to-noise ratio of the ADC block with cost-efficient design, a finite impulse response filter followed by digital proportional-integral-derivative blocks were designed. All these digital function blocks were optimised with processing speed. In the system simulation, it can be found that this controller achieved output regulation within 10% of nominal 5 V output voltage under 1 A/µs load transient condition; moreover, with the soft-start method, there is no turn-on overshooting. The die size of this controller is controlled within 3 mm2 by using 180 nm CMOS technology.

Switched-capacitor realization of presynaptic short-term-plasticity and stop-learning synapses in 28 nm CMOS

PubMed Central

Noack, Marko; Partzsch, Johannes; Mayr, Christian G.; Hänzsche, Stefan; Scholze, Stefan; Höppner, Sebastian; Ellguth, Georg; Schüffny, Rene

2015-01-01

Synaptic dynamics, such as long- and short-term plasticity, play an important role in the complexity and biological realism achievable when running neural networks on a neuromorphic IC. For example, they endow the IC with an ability to adapt and learn from its environment. In order to achieve the millisecond to second time constants required for these synaptic dynamics, analog subthreshold circuits are usually employed. However, due to process variation and leakage problems, it is almost impossible to port these types of circuits to modern sub-100nm technologies. In contrast, we present a neuromorphic system in a 28 nm CMOS process that employs switched capacitor (SC) circuits to implement 128 short term plasticity presynapses as well as 8192 stop-learning synapses. The neuromorphic system consumes an area of 0.36 mm2 and runs at a power consumption of 1.9 mW. The circuit makes use of a technique for minimizing leakage effects allowing for real-time operation with time constants up to several seconds. Since we rely on SC techniques for all calculations, the system is composed of only generic mixed-signal building blocks. These generic building blocks make the system easy to port between technologies and the large digital circuit part inherent in an SC system benefits fully from technology scaling. PMID:25698914

Massively Parallel, Molecular Analysis Platform Developed Using a CMOS Integrated Circuit With Biological Nanopores

PubMed Central

Roever, Stefan

2012-01-01

A massively parallel, low cost molecular analysis platform will dramatically change the nature of protein, molecular and genomics research, DNA sequencing, and ultimately, molecular diagnostics. An integrated circuit (IC) with 264 sensors was fabricated using standard CMOS semiconductor processing technology. Each of these sensors is individually controlled with precision analog circuitry and is capable of single molecule measurements. Under electronic and software control, the IC was used to demonstrate the feasibility of creating and detecting lipid bilayers and biological nanopores using wild type α-hemolysin. The ability to dynamically create bilayers over each of the sensors will greatly accelerate pore development and pore mutation analysis. In addition, the noise performance of the IC was measured to be 30fA(rms). With this noise performance, single base detection of DNA was demonstrated using α-hemolysin. The data shows that a single molecule, electrical detection platform using biological nanopores can be operationalized and can ultimately scale to millions of sensors. Such a massively parallel platform will revolutionize molecular analysis and will completely change the field of molecular diagnostics in the future.

SiC Integrated Circuits for Power Device Drivers Able to Operate in Harsh Environments

NASA Astrophysics Data System (ADS)

Godignon, P.; Alexandru, M.; Banu, V.; Montserrat, J.; Jorda, X.; Vellvehi, M.; Schmidt, B.; Michel, P.; Millan, J.

2014-08-01

The currently developed SiC electronic devices are more robust to high temperature operation and radiation exposure damage than correspondingly rated Si ones. In order to integrate the existent SiC high power and high temperature electronics into more complex systems, a SiC integrated circuit (IC) technology capable of operation at temperatures substantially above the conventional ones is required. Therefore, this paper is a step towards the development of ICs-control electronics that have to attend the harsh environment power applications. Concretely, we present the development of SiC MESFET-based digital circuitry, able to integrate gate driver for SiC power devices. Furthermore, a planar lateral power MESFET is developed with the aim of its co-integration on the same chip with the previously mentioned SiC digital ICs technology. And finally, experimental results on SiC Schottky-gated devices irradiated with protons and electrons are presented. This development is based on the Tungsten-Schottky interface technology used for the fabrication of stable SiC Schottky diodes for the European Space Agency Mission BepiColombo.

Inclusion of Body Bias Effect in SPICE Modeling of 4H-SiC Integrated Circuit Resistors

NASA Technical Reports Server (NTRS)

Neudeck, Philip G.

2017-01-01

The DC electrical behavior of n-type 4H-SiC resistors used for realizing 500 degrees Celsius durable integrated circuits (ICs) is studied as a function of substrate bias and temperature. Improved fidelity electrical simulation is described using SPICE NMOS model to simulate resistor substrate body bias effect that is absent from the SPICE semiconductor resistor model.

Inclusion of Body-Bias Effect in SPICE Modeling of 4H-SiC Integrated Circuit Resistors

NASA Technical Reports Server (NTRS)

Neudeck, Philip G.

2017-01-01

The DC electrical behavior of n-type 4H-SiC resistors used for realizing 500 C durable integrated circuits (ICs) is studied as a function of substrate bias and temperature. Improved fidelity electrical simulation is described using SPICE NMOS model to simulate resistor substrate body bias effect that is absent from the SPICE semiconductor resistor model.

Spacer engineered Trigate SOI TFET: An investigation towards harsh temperature environment applications

NASA Astrophysics Data System (ADS)

Mallikarjunarao; Ranjan, Rajeev; Pradhan, K. P.; Artola, L.; Sahu, P. K.

2016-09-01

In this paper, a novel N-channel Tunnel Field Effect Transistor (TFET) i.e., Trigate Silicon-ON-Insulator (SOI) N-TFET with high-k spacer is proposed for better Sub-threshold swing (SS) and OFF-state current (IOFF) by keeping in mind the sensitivity towards temperature. The proposed model can achieve a Sub-threshold swing less than 35 mV/decade at various temperatures, which is desirable for designing low power CTFET for digital circuit applications. In N-TFET source doping has a significant effect on the ON-state current (ION) level; therefore more electrons will tunnel from source to channel region. High-k Spacer i.e., HfO2 is used to enhance the device performance and also it avoids overlapping of transistors in an integrated circuits (IC's). We have designed a reliable device by performing the temperature analysis on Transfer characteristics, Drain characteristics and also on various performance metrics like ON-state current (ION), OFF-state current (IOFF), ION/IOFF, Trans-conductance (gm), Trans-conductance Generation Factor (TGF), Sub-threshold Swing (SS) to observe the applications towards harsh temperature environment.

Circuit Design Approaches for Implementation of a Subtrellis IC for a Reed-Muller Subcode

NASA Technical Reports Server (NTRS)

Lin, Shu; Uehara, Gregory T.; Nakamura, Eric B.; Chu, Cecilia W. P.

1996-01-01

In his research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RM subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second(Mbps). The combination of a large number of states and a high data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high- speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these subtrellises.

Circuit Design Approaches for Implementation of a Subtrellis IC for a Reed-Muller Subcode

NASA Technical Reports Server (NTRS)

Lin, Shu; Uehara, Gregory T.; Nakamura, Eric B.; Chu, Cecilia W. P.

1996-01-01

In this research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RM subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second (Mbps). The combination of a large number of states and a high data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high-speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these subtrellises.

Fine-Tuning of Molecular Packing and Energy Level through Methyl Substitution Enabling Excellent Small Molecule Acceptors for Nonfullerene Polymer Solar Cells with Efficiency up to 12.54.

PubMed

Luo, Zhenghui; Bin, Haijun; Liu, Tao; Zhang, Zhi-Guo; Yang, Yankang; Zhong, Cheng; Qiu, Beibei; Li, Guanghao; Gao, Wei; Xie, Dongjun; Wu, Kailong; Sun, Yanming; Liu, Feng; Li, Yongfang; Yang, Chuluo

2018-03-01

A novel small molecule acceptor MeIC with a methylated end-capping group is developed. Compared to unmethylated counterparts (ITCPTC), MeIC exhibits a higher lowest unoccupied molecular orbital (LUMO) level value, tighter molecular packing, better crystallites quality, and stronger absorption in the range of 520-740 nm. The MeIC-based polymer solar cells (PSCs) with J71 as donor, achieve high power conversion efficiency (PCE), up to 12.54% with a short-circuit current (J SC ) of 18.41 mA cm -2 , significantly higher than that of the device based on J71:ITCPTC (11.63% with a J SC of 17.52 mA cm -2 ). The higher J SC of the PSC based on J71:MeIC can be attributed to more balanced μ h /μ e , higher charge dissociation and charge collection efficiency, better molecular packing, and more proper phase separation features as indicated by grazing incident X-ray diffraction and resonant soft X-ray scattering results. It is worth mentioning that the as-cast PSCs based on MeIC also yield a high PCE of 11.26%, which is among the highest value for the as-cast nonfullerene PSCs so far. Such a small modification that leads to so significant an improvement of the photovoltaic performance is a quite exciting finding, shining a light on the molecular design of the nonfullerene acceptors. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Self-Adaptive System based on Field Programmable Gate Array for Extreme Temperature Electronics

NASA Technical Reports Server (NTRS)

Keymeulen, Didier; Zebulum, Ricardo; Rajeshuni, Ramesham; Stoica, Adrian; Katkoori, Srinivas; Graves, Sharon; Novak, Frank; Antill, Charles

2006-01-01

In this work, we report the implementation of a self-adaptive system using a field programmable gate array (FPGA) and data converters. The self-adaptive system can autonomously recover the lost functionality of a reconfigurable analog array (RAA) integrated circuit (IC) [3]. Both the RAA IC and the self-adaptive system are operating in extreme temperatures (from 120 C down to -180 C). The RAA IC consists of reconfigurable analog blocks interconnected by several switches and programmable by bias voltages. It implements filters/amplifiers with bandwidth up to 20 MHz. The self-adaptive system controls the RAA IC and is realized on Commercial-Off-The-Shelf (COTS) parts. It implements a basic compensation algorithm that corrects a RAA IC in less than a few milliseconds. Experimental results for the cold temperature environment (down to -180 C) demonstrate the feasibility of this approach.

Elements configuration of the open lead test circuit

DOE Office of Scientific and Technical Information (OSTI.GOV)

Fukuzaki, Yumi, E-mail: 14514@sr.kagawa-nct.ac.jp; Ono, Akira

In the field of electronics, small electronic devices are widely utilized because they are easy to carry. The devices have various functions by user’s request. Therefore, the lead’s pitch or the ball’s pitch have been narrowed and high-density printed circuit board has been used in the devices. Use of the ICs which have narrow lead pitch makes normal connection difficult. When logic circuits in the devices are fabricated with the state-of-the-art technology, some faults have occurred more frequently. It can be divided into types of open faults and short faults. We have proposed a new test method using a testmore » circuit in the past. This paper propose elements configuration of the test circuit.« less

A proposed holistic approach to on-chip, off-chip, test, and package interconnections

NASA Astrophysics Data System (ADS)

Bartelink, Dirk J.

1998-11-01

The term interconnection has traditionally implied a `robust' connection from a transistor or a group of transistors in an IC to the outside world, usually a PC board. Optimum system utilization is done from outside the IC. As an alternative, this paper addresses `unimpeded' transistor-to-transistor interconnection aimed at reaching the high circuit densities and computational capabilities of neighboring IC's. In this view, interconnections are not made to some human-centric place outside the IC world requiring robustness—except for system input and output connections. This unimpeded interconnect style is currently available only through intra-chip signal traces in `system-on-a-chip' implementations, as exemplified by embedded DRAMs. Because the traditional off-chip penalty in performance and wiring density is so large, a merging of complex process technologies is the only option today. It is suggested that, for system integration to move forward, the traditional robustness requirement inherited from conventional packaging interconnect and IC manufacturing test must be discarded. Traditional system assembly from vendor parts requires robustness under shipping, inspection and assembly. The trend toward systems on a chip signifies willingness by semiconductor companies to design and fabricate whole systems in house, so that `in-house' chip-to-chip assembly is not beyond reach. In this scenario, bare chips never leave the controlled environment of the IC fabricator while the two major contributors to off-chip signal penalty, ESD protection and the need to source a 50-ohm test head, are avoided. With in-house assembly, ESD protection can be eliminated with the precautions already familiar in plasma etching. Test interconnection impacts the fundamentals of IC manufacturing, particularly with clock speeds approaching 1GHz, and cannot be an afterthought. It should be an integral part of the chip-to-chip interconnection bandwidth optimization, because—as we must recognize—test is also performed using IC's. A system interconnection is proposed using multiple chips fabricated with conventional silicon processes, including MEMS technology. The system resembles an MCM that can be joined without committing to final assembly to perform at-speed testing. 50-Ohm test probes never load the circuit; only intended neighboring chips are ever connected. A `back-plane' chip provides the connection layers for both inter- and intra-chip signals and also serves as the probe card, in analogy with membrane probes now used for single-chip testing. Intra-chip connections, which require complicated connections during test that exactly match the product, are then properly made and all waveforms and loading conditions under test will be identical to those of the product. The major benefit is that all front-end chip technologies can be merged—logic, memory, RF, even passives. ESD protection is required only on external system connections. Manufacturing test information will accurately characterize process faults and thus avoid the Known-Good-Die problem that has slowed the arrival of conventional MCM's.

Panel discussion summary: do we need a revolution in design and process integration to enable sub-100-nm technology nodes?

NASA Astrophysics Data System (ADS)

Grobman, Warren D.

2002-07-01

Dramatically increasing mask set costs, long-loop design-fabrication iterations, and lithography of unprecedented complexity and cost threaten to disrupt time-accepted IC industry progression as described by Moore"s Law. Practical and cost-effective IC manufacturing below the 100nm technology node presents significant and unique new challenges spanning multiple disciplines and overlapping traditionally separable components of the design-through-chip manufacturing flow. Lithographic and other process complexity is compounded by design, mask, and infrastructure technologies, which do not sufficiently account for increasingly stringent and complex manufacturing issues. Deep subwavelength and atomic-scale process and device physics effects increasingly invade and impact the design flow strongly at a time when the pressures for increased design productivity are escalating at a superlinear rate. Productivity gaps, both upstream in design and downstream in fabrication, are anticipated by many to increase due to dramatic increases in inherent complexity of the design-to-chip equation. Furthermore, the cost of lithographic equipment is increasing at an aggressive compound growth rate so large that we can no longer economically derive the benefit of the increased number of circuits per unit area unless we extend the life of lithographic equipment for more generations, and deeper into the subwavelength regime. Do these trends unambiguously lead to the conclusion that we need a revolution in design and design-process integration to enable the sub-100nm nodes? Or is such a premise similar to other well-known predictions of technology brick walls that never came true?

Neural Implants, Packaging for Biocompatible Implants, and Improving Fabricated Capacitors

NASA Astrophysics Data System (ADS)

Agger, Elizabeth Rose

We have completed the circuit design and packaging procedure for an NIH-funded neural implant, called a MOTE (Microscale Optoelectronically Transduced Electrode). Neural recording implants for mice have greatly advanced neuroscience, but they are often damaging and limited in their recording location. This project will result in free-floating implants that cause less damage, provide rapid electronic recording, and increase range of recording across the cortex. A low-power silicon IC containing amplification and digitization sub-circuits is powered by a dual-function gallium arsenide photovoltaic and LED. Through thin film deposition, photolithography, and chemical and physical etching, the Molnar Group and the McEuen Group (Applied and Engineering Physics department) will package the IC and LED into a biocompatible implant approximately 100microm3. The IC and LED are complete and we have begun refining this packaging procedure in the Cornell NanoScale Science & Technology Facility. ICs with 3D time-resolved imaging capabilities can image microorganisms and other biological samples given proper packaging. A portable, flat, easily manufactured package would enable scientists to place biological samples on slides directly above the Molnar group's imaging chip. We have developed a packaging procedure using laser cutting, photolithography, epoxies, and metal deposition. Using a flip-chip method, we verified the process by aligning and adhering a sample chip to a holder wafer. In the CNF, we have worked on a long-term metal-insulator-metal (MIM) capacitor characterization project. Former Fellow and continuing CNF user Kwame Amponsah developed the original procedure for the capacitor fabrication, and another former fellow, Jonilyn Longenecker, revised the procedure and began the arduous process of characterization. MIM caps are useful to clean room users as testing devices to verify electronic characteristics of their active circuitry. This project's objective is to determine differences in current-voltage (IV) and capacitor-voltage (CV) relationships across variations in capacitor size and dielectric type. This effort requires an approximately 20-step process repeated for two-to-six varieties (dependent on temperature and thermal versus plasma options) of the following dielectrics: HfO2, SiO2, Al2O3, TaOx, and TiO2.

Maximum permissible voltage of YBCO coated conductors

NASA Astrophysics Data System (ADS)

Wen, J.; Lin, B.; Sheng, J.; Xu, J.; Jin, Z.; Hong, Z.; Wang, D.; Zhou, H.; Shen, X.; Shen, C.

2014-06-01

Superconducting fault current limiter (SFCL) could reduce short circuit currents in electrical power system. One of the most important thing in developing SFCL is to find out the maximum permissible voltage of each limiting element. The maximum permissible voltage is defined as the maximum voltage per unit length at which the YBCO coated conductors (CC) do not suffer from critical current (Ic) degradation or burnout. In this research, the time of quenching process is changed and voltage is raised until the Ic degradation or burnout happens. YBCO coated conductors test in the experiment are from American superconductor (AMSC) and Shanghai Jiao Tong University (SJTU). Along with the quenching duration increasing, the maximum permissible voltage of CC decreases. When quenching duration is 100 ms, the maximum permissible of SJTU CC, 12 mm AMSC CC and 4 mm AMSC CC are 0.72 V/cm, 0.52 V/cm and 1.2 V/cm respectively. Based on the results of samples, the whole length of CCs used in the design of a SFCL can be determined.

High-density Schottky barrier IRCCD sensors for remote sensing applications

NASA Astrophysics Data System (ADS)

Elabd, H.; Tower, J. R.; McCarthy, B. M.

1983-01-01

It is pointed out that the ambitious goals envisaged for the next generation of space-borne sensors challenge the state-of-the-art in solid-state imaging technology. Studies are being conducted with the aim to provide focal plane array technology suitable for use in future Multispectral Linear Array (MLA) earth resource instruments. An important new technology for IR-image sensors involves the use of monolithic Schottky barrier infrared charge-coupled device arrays. This technology is suitable for earth sensing applications in which moderate quantum efficiency and intermediate operating temperatures are required. This IR sensor can be fabricated by using standard integrated circuit (IC) processing techniques, and it is possible to employ commercial IC grade silicon. For this reason, it is feasible to construct Schottky barrier area and line arrays with large numbers of elements and high-density designs. A Pd2Si Schottky barrier sensor for multispectral imaging in the 1 to 3.5 micron band is under development.

Ambient temperature cadmium zinc telluride radiation detector and amplifier circuit

DOEpatents

McQuaid, J.H.; Lavietes, A.D.

1998-05-26

A low noise, low power consumption, compact, ambient temperature signal amplifier for a Cadmium Zinc Telluride (CZT) radiation detector is disclosed. The amplifier can be used within a larger system (e.g., including a multi-channel analyzer) to allow isotopic analysis of radionuclides in the field. In one embodiment, the circuit stages of the low power, low noise amplifier are constructed using integrated circuit (IC) amplifiers , rather than discrete components, and include a very low noise, high gain, high bandwidth dual part preamplification stage, an amplification stage, and an filter stage. The low noise, low power consumption, compact, ambient temperature amplifier enables the CZT detector to achieve both the efficiency required to determine the presence of radionuclides and the resolution necessary to perform isotopic analysis to perform nuclear material identification. The present low noise, low power, compact, ambient temperature amplifier enables a CZT detector to achieve resolution of less than 3% full width at half maximum at 122 keV for a Cobalt-57 isotope source. By using IC circuits and using only a single 12 volt supply and ground, the novel amplifier provides significant power savings and is well suited for prolonged portable in-field use and does not require heavy, bulky power supply components. 9 figs.

Continuous adjustment of threshold voltage in carbon nanotube field-effect transistors through gate engineering

NASA Astrophysics Data System (ADS)

Zhong, Donglai; Zhao, Chenyi; Liu, Lijun; Zhang, Zhiyong; Peng, Lian-Mao

2018-04-01

In this letter, we report a gate engineering method to adjust threshold voltage of carbon nanotube (CNT) based field-effect transistors (FETs) continuously in a wide range, which makes the application of CNT FETs especially in digital integrated circuits (ICs) easier. Top-gated FETs are fabricated using solution-processed CNT network films with stacking Pd and Sc films as gate electrodes. By decreasing the thickness of the lower layer metal (Pd) from 20 nm to zero, the effective work function of the gate decreases, thus tuning the threshold voltage (Vt) of CNT FETs from -1.0 V to 0.2 V. The continuous adjustment of threshold voltage through gate engineering lays a solid foundation for multi-threshold technology in CNT based ICs, which then can simultaneously provide high performance and low power circuit modules on one chip.

Intermetallic compounds in 3D integrated circuits technology: a brief review

PubMed Central

Annuar, Syahira; Mahmoodian, Reza; Hamdi, Mohd; Tu, King-Ning

2017-01-01

Abstract The high performance and downsizing technology of three-dimensional integrated circuits (3D-ICs) for mobile consumer electronic products have gained much attention in the microelectronics industry. This has been driven by the utilization of chip stacking by through-Si-via and solder microbumps. Pb-free solder microbumps are intended to replace conventional Pb-containing solder joints due to the rising awareness of environmental preservation. The use of low-volume solder microbumps has led to crucial constraints that cause several reliability issues, including excessive intermetallic compounds (IMCs) formation and solder microbump embrittlement due to IMCs growth. This article reviews technologies related to 3D-ICs, IMCs formation mechanisms and reliability issues concerning IMCs with Pb-free solder microbumps. Finally, future outlook on the potential growth of research in this area is discussed. PMID:29057024

3D Printing of Ball Grid Arrays

NASA Astrophysics Data System (ADS)

Sinha, Shayandev; Hines, Daniel; Dasgupta, Abhijit; Das, Siddhartha

Ball grid arrays (BGA) are interconnects between an integrated circuit (IC) and a printed circuit board (PCB), that are used for surface mounting electronic components. Typically, lead free alloys are used to make solder balls which, after a reflow process, establish a mechanical and electrical connection between the IC and the PCB. High temperature processing is required for most of these alloys leading to thermal shock causing damage to ICs. For producing flexible circuits on a polymer substrate, there is a requirement for low temperature processing capabilities (around 150 C) and for reducing strain from mechanical stresses. Additive manufacturing techniques can provide an alternative methodology for fabricating BGAs as a direct replacement for standard solder bumped BGAs. We have developed aerosol jet (AJ) printing methods to fabricate a polymer bumped BGA. As a demonstration of the process developed, a daisy chain test chip was polymer bumped using an AJ printed ultra violet (UV) curable polymer ink that was then coated with an AJ printed silver nanoparticle laden ink as a conducting layer printed over the polymer bump. The structure for the balls were achieved by printing the polymer ink using a specific toolpath coupled with in-situ UV curing of the polymer which provided good control over the shape, resulting in well-formed spherical bumps on the order of 200 um wide by 200 um tall for this initial demonstration. A detailed discussion of the AJ printing method and results from accelerated life-time testing will be presented

Digital Platform for Wafer-Level MEMS Testing and Characterization Using Electrical Response

PubMed Central

Brito, Nuno; Ferreira, Carlos; Alves, Filipe; Cabral, Jorge; Gaspar, João; Monteiro, João; Rocha, Luís

2016-01-01

The uniqueness of microelectromechanical system (MEMS) devices, with their multiphysics characteristics, presents some limitations to the borrowed test methods from traditional integrated circuits (IC) manufacturing. Although some improvements have been performed, this specific area still lags behind when compared to the design and manufacturing competencies developed over the last decades by the IC industry. A complete digital solution for fast testing and characterization of inertial sensors with built-in actuation mechanisms is presented in this paper, with a fast, full-wafer test as a leading ambition. The full electrical approach and flexibility of modern hardware design technologies allow a fast adaptation for other physical domains with minimum effort. The digital system encloses a processor and the tailored signal acquisition, processing, control, and actuation hardware control modules, capable of the structure position and response analysis when subjected to controlled actuation signals in real time. The hardware performance, together with the simplicity of the sequential programming on a processor, results in a flexible and powerful tool to evaluate the newest and fastest control algorithms. The system enables measurement of resonant frequency (Fr), quality factor (Q), and pull-in voltage (Vpi) within 1.5 s with repeatability better than 5 ppt (parts per thousand). A full-wafer with 420 devices under test (DUTs) has been evaluated detecting the faulty devices and providing important design specification feedback to the designers. PMID:27657087

Digital Platform for Wafer-Level MEMS Testing and Characterization Using Electrical Response.

PubMed

Brito, Nuno; Ferreira, Carlos; Alves, Filipe; Cabral, Jorge; Gaspar, João; Monteiro, João; Rocha, Luís

2016-09-21

The uniqueness of microelectromechanical system (MEMS) devices, with their multiphysics characteristics, presents some limitations to the borrowed test methods from traditional integrated circuits (IC) manufacturing. Although some improvements have been performed, this specific area still lags behind when compared to the design and manufacturing competencies developed over the last decades by the IC industry. A complete digital solution for fast testing and characterization of inertial sensors with built-in actuation mechanisms is presented in this paper, with a fast, full-wafer test as a leading ambition. The full electrical approach and flexibility of modern hardware design technologies allow a fast adaptation for other physical domains with minimum effort. The digital system encloses a processor and the tailored signal acquisition, processing, control, and actuation hardware control modules, capable of the structure position and response analysis when subjected to controlled actuation signals in real time. The hardware performance, together with the simplicity of the sequential programming on a processor, results in a flexible and powerful tool to evaluate the newest and fastest control algorithms. The system enables measurement of resonant frequency (Fr), quality factor (Q), and pull-in voltage (Vpi) within 1.5 s with repeatability better than 5 ppt (parts per thousand). A full-wafer with 420 devices under test (DUTs) has been evaluated detecting the faulty devices and providing important design specification feedback to the designers.

Good Trellises for IC Implementation of Viterbi Decoders for Linear Block Codes

NASA Technical Reports Server (NTRS)

Moorthy, Hari T.; Lin, Shu; Uehara, Gregory T.

1997-01-01

This paper investigates trellis structures of linear block codes for the integrated circuit (IC) implementation of Viterbi decoders capable of achieving high decoding speed while satisfying a constraint on the structural complexity of the trellis in terms of the maximum number of states at any particular depth. Only uniform sectionalizations of the code trellis diagram are considered. An upper-bound on the number of parallel and structurally identical (or isomorphic) subtrellises in a proper trellis for a code without exceeding the maximum state complexity of the minimal trellis of the code is first derived. Parallel structures of trellises with various section lengths for binary BCH and Reed-Muller (RM) codes of lengths 32 and 64 are analyzed. Next, the complexity of IC implementation of a Viterbi decoder based on an L-section trellis diagram for a code is investigated. A structural property of a Viterbi decoder called add-compare-select (ACS)-connectivity which is related to state connectivity is introduced. This parameter affects the complexity of wire-routing (interconnections within the IC). The effect of five parameters namely: (1) effective computational complexity; (2) complexity of the ACS-circuit; (3) traceback complexity; (4) ACS-connectivity; and (5) branch complexity of a trellis diagram on the very large scale integration (VISI) complexity of a Viterbi decoder is investigated. It is shown that an IC implementation of a Viterbi decoder based on a nonminimal trellis requires less area and is capable of operation at higher speed than one based on the minimal trellis when the commonly used ACS-array architecture is considered.

Good trellises for IC implementation of viterbi decoders for linear block codes

NASA Technical Reports Server (NTRS)

Lin, Shu; Moorthy, Hari T.; Uehara, Gregory T.

1996-01-01

This paper investigates trellis structures of linear block codes for the IC (integrated circuit) implementation of Viterbi decoders capable of achieving high decoding speed while satisfying a constraint on the structural complexity of the trellis in terms of the maximum number of states at any particular depth. Only uniform sectionalizations of the code trellis diagram are considered. An upper bound on the number of parallel and structurally identical (or isomorphic) subtrellises in a proper trellis for a code without exceeding the maximum state complexity of the minimal trellis of the code is first derived. Parallel structures of trellises with various section lengths for binary BCH and Reed-Muller (RM) codes of lengths 32 and 64 are analyzed. Next, the complexity of IC implementation of a Viterbi decoder based on an L-section trellis diagram for a code is investigated. A structural property of a Viterbi decoder called ACS-connectivity which is related to state connectivity is introduced. This parameter affects the complexity of wire-routing (interconnections within the IC). The effect of five parameters namely: (1) effective computational complexity; (2) complexity of the ACS-circuit; (3) traceback complexity; (4) ACS-connectivity; and (5) branch complexity of a trellis diagram on the VLSI complexity of a Viterbi decoder is investigated. It is shown that an IC implementation of a Viterbi decoder based on a non-minimal trellis requires less area and is capable of operation at higher speed than one based on the minimal trellis when the commonly used ACS-array architecture is considered.

Programmable logic devices

NASA Astrophysics Data System (ADS)

Jacobs, J. L.

1993-04-01

Erasable programmable logic devices (EPLD's) were investigated to determine their advantages and/or disadvantages in Test Equipment Engineering applications. It was found that EPLD's performed as well as or better than identical circuits using standard transistor transistor logic (TTL). The chip count in these circuits was reduced, saving printed circuit board space and shortening fabrication and prove-in time. Troubleshooting circuits of EPLD's was also easier with 10 to 100 times fewer wires needed. The reduced number of integrated circuits (IC's) contributed to faster system speeds and an overall lower power consumption. In some cases changes to the circuit became software changes using EPLD's instead of hardware changes for standard logic. Using EPLD's was fairly easy; however, as with any new technology, a learning curve must be overcome before EPLD's can be used efficiently. The many benefits of EPLD's outweighed this initial inconvenience.

Affordable MMICs for Air Force systems

NASA Astrophysics Data System (ADS)

Kemerley, Robert T.; Fayette, Daniel F.

1991-05-01

The paper deals with a program directed at demonstrating affordable MMIC chips - the microwave/mm-wave monolithic integrated circuit (MIMIC) program. Focus is placed on experiments involving the growth and characterization of III-V materials, and the design, fabrication, and evaluation of ICs in the 1 to 60 GHz frequency range, as well as efforts related to the reliability testing, failure analysis, and generation of qualified manufacture's list procedures for GaAs MMICs and modules. Attributes associated with GaAs-technology devices, quality, reliability, and performance in select environments are discussed, including the dependence of these structures over temperature ranges, electrostatic discharge sensitivity, and susceptibility to environmental stresses.

GBLD10+: a compact low-power 10 Gb/s VCSEL driver

DOE PAGES

Zhang, T.; Kulis, S.; Gui, P.; ...

2016-01-13

We report the design and implementation of the GBLD10+, a low-power 10 Gb/s VCSEL driver for High Energy Physics (HEP) applications. With new circuit techniques, the driver consumes only 31 mW and occupies a small area of 400 μm × 1750 μm including the IO PADs and sealrings. These characteristics allow for multiple GBLD10+ ICs to be assembled side by side in a compact module, with each one directly wire bonded to one VCSEL diode. Finally, this makes the GBLD10+ a suitable candidate for the Versatile Link PLUS (VL +) project, offering flexibility in configuring multiple transmitters and receivers.

GaAs digital dynamic IC's for applications up to 10 GHz

NASA Astrophysics Data System (ADS)

Rocchi, M.; Gabillard, B.

1983-06-01

To evaluate the potentiality of GaAs MESFET's as transmitting gates, dynamic TT-bar flip-flops have been fabricated using a self-aligned planar process. The maximum operating frequency is 10.2 GHz, which is the best speed performance ever reported for a digital circuit. The performance of the transmitting gates within the circuits are discussed in detail. Speed improvement and topological simplification of fully static LSI subsystems are investigated.

Broadband millimeter-wave GaAs transmitters and receivers using planar bow-tie antennas

NASA Technical Reports Server (NTRS)

Konishi, Y.; Kamegawa, M.; Case, M.; Yu, R.; Rodwell, M. J. W.; York, R. A.; Rutledge, D. B.

1992-01-01

We report broadband monolithic transmitters and receivers IC's for mm-wave electromagnetic measurements. The IC's use nonlinear transmission lines (NLTL) and sampling circuits as picosecond pulse generators and detectors. The pulses are radiated and received by planar monolithic bow-tie antennas, collimated with silicon substrate lenses and off-axis parabolic reflectors. Through Fourier transformation of the received pulse, 30-250 GHz free space gain-frequency measurements are demonstrated with an accuracy approximately = 0.17 dB, RMS.

Novel Manufacturing Technologies for GHZ/THz Integrated Circuits on Synthetic Diamond Substrates

DTIC Science & Technology

2010-11-15

silicon form palladium silicide Pd2Si at a temperature of 400 ºС, thus ensuring high reliability of the contacts. All the above metallization layers were...indicate possibility of realization of ICs on diamond substrates. In the course of our studies it was found that the Ti-Pd-Au metallization system...thickness of 2-3 um) can be applied when forming the topology of IC elements on synthetic diamond layers, while the Cr–Cu–Ni–Au metallization system with

Silicon photonic IC embedded optical-PCB for high-speed interconnect application

NASA Astrophysics Data System (ADS)

Kallega, Rakshitha; Nambiar, Siddharth; Kumar, Abhai; Ranganath, Praveen; Selvaraja, Shankar Kumar

2018-02-01

Optical-Printed Circuit Board (PCB) is an emerging optical interconnect technology to bridge the gap between the board edge and the processing module. The technology so far has been used as a broadband transmitter using polymer waveguides in the PCB. In this paper, we report a Silicon Nitride based photonic IC embedded in the PCB along with the polymers as waveguides in the PCB. The motivation for such integration is to bring routing capability and to reduce the power loss due to broadcasting mode.

GaAs integrated circuits and heterojunction devices

NASA Astrophysics Data System (ADS)

Fowlis, Colin

1986-06-01

The state of the art of GaAs technology in the U.S. as it applies to digital and analog integrated circuits is examined. In a market projection, it is noted that whereas analog ICs now largely dominate the market, in 1994 they will amount to only 39 percent vs. 57 percent for digital ICs. The military segment of the market will remain the largest (42 percent in 1994 vs. 70 percent today). ICs using depletion-mode-only FETs can be constructed in various forms, the closest to production being BFL or buffered FET logic. Schottky diode FET logic - a lower power approach - can reach higher complexities and strong efforts are being made in this direction. Enhancement type devices appear essential to reach LSI and VLSI complexity, but process control is still very difficult; strong efforts are under way, both in the U.S. and in Japan. Heterojunction devices appear very promising, although structures are fairly complex, and special fabrication techniques, such as molecular beam epitaxy and MOCVD, are necessary. High-electron-mobility-transistor (HEMT) devices show significant performance advantages over MESFETs at low temperatures. Initial results of heterojunction bipolar transistor devices show promise for high speed A/D converter applications.

Computer hardware for radiologists: Part I

PubMed Central

Indrajit, IK; Alam, A

2010-01-01

Computers are an integral part of modern radiology practice. They are used in different radiology modalities to acquire, process, and postprocess imaging data. They have had a dramatic influence on contemporary radiology practice. Their impact has extended further with the emergence of Digital Imaging and Communications in Medicine (DICOM), Picture Archiving and Communication System (PACS), Radiology information system (RIS) technology, and Teleradiology. A basic overview of computer hardware relevant to radiology practice is presented here. The key hardware components in a computer are the motherboard, central processor unit (CPU), the chipset, the random access memory (RAM), the memory modules, bus, storage drives, and ports. The personnel computer (PC) has a rectangular case that contains important components called hardware, many of which are integrated circuits (ICs). The fiberglass motherboard is the main printed circuit board and has a variety of important hardware mounted on it, which are connected by electrical pathways called “buses”. The CPU is the largest IC on the motherboard and contains millions of transistors. Its principal function is to execute “programs”. A Pentium® 4 CPU has transistors that execute a billion instructions per second. The chipset is completely different from the CPU in design and function; it controls data and interaction of buses between the motherboard and the CPU. Memory (RAM) is fundamentally semiconductor chips storing data and instructions for access by a CPU. RAM is classified by storage capacity, access speed, data rate, and configuration. PMID:21042437

A Fully Integrated Dual-Channel On-Coil CMOS Receiver for Array Coils in 1.5-10.5 T MRI.

PubMed

Sporrer, Benjamin; Wu, Lianbo; Bettini, Luca; Vogt, Christian; Reber, Jonas; Marjanovic, Josip; Burger, Thomas; Brunner, David O; Pruessmann, Klaas P; Troster, Gerhard; Huang, Qiuting

2017-12-01

Magnetic resonance imaging (MRI) is among the most important medical imaging modalities. Coil arrays and receivers with high channel counts (16 and more) have to be deployed to obtain the image quality and acquisition speed required by modern clinical protocols. In this paper, we report the theoretical analysis, the system-level design, and the circuit implementation of the first receiver IC (RXIC) for clinical MRI fully integrated in a modern CMOS technology. The dual-channel RXIC sits directly on the sensor coil, thus eliminating any RF cable otherwise required to transport the information out of the magnetic field. The first stage LNA was implemented using a noise-canceling architecture providing a highly reflective input used to decouple the individual channels of the array. Digitization is performed directly on-chip at base-band by means of a delta-sigma modulator, allowing the subsequent optical transmission of data. The presented receiver, implemented in a CMOS technology, is compatible with MRI scanners up to . It reaches sub- noise figure for MRI units and features a dynamic range up to at a power consumption below per channel, with an area occupation of . Mounted on a small-sized printed circuit board (PCB), the receiver IC has been employed in a commercial MRI scanner to acquire in-vivo images matching the quality of traditional systems, demonstrating the first step toward multichannel wearable MRI array coils.

Merging parallel optics packaging and surface mount technologies

NASA Astrophysics Data System (ADS)

Kopp, Christophe; Volpert, Marion; Routin, Julien; Bernabé, Stéphane; Rossat, Cyrille; Tournaire, Myriam; Hamelin, Régis

2008-02-01

Optical links are well known to present significant advantages over electrical links for very high-speed data rate at 10Gpbs and above per channel. However, the transition towards optical interconnects solutions for short and very short reach applications requires the development of innovative packaging solutions that would deal with very high volume production capability and very low cost per unit. Moreover, the optoelectronic transceiver components must be able to move from the edge to anywhere on the printed circuit board, for instance close to integrated circuits with high speed IO. In this paper, we present an original packaging design to manufacture parallel optic transceivers that are surface mount devices. The package combines highly integrated Multi-Chip-Module on glass and usual IC ceramics packaging. The use of ceramic and the development of sealing technologies achieve hermetic requirements. Moreover, thanks to a chip scale package approach the final device exhibits a much minimized footprint. One of the main advantages of the package is its flexibility to be soldered or plugged anywhere on the printed circuit board as any other electronic device. As a demonstrator we present a 2 by 4 10Gbps transceiver operating at 850nm.

Visible light laser voltage probing on thinned substrates

DOEpatents

Beutler, Joshua; Clement, John Joseph; Miller, Mary A.; Stevens, Jeffrey; Cole, Jr., Edward I.

2017-03-21

The various technologies presented herein relate to utilizing visible light in conjunction with a thinned structure to enable characterization of operation of one or more features included in an integrated circuit (IC). Short wavelength illumination (e.g., visible light) is applied to thinned samples (e.g., ultra-thinned samples) to achieve a spatial resolution for laser voltage probing (LVP) analysis to be performed on smaller technology node silicon-on-insulator (SOI) and bulk devices. Thinning of a semiconductor material included in the IC (e.g., backside material) can be controlled such that the thinned semiconductor material has sufficient thickness to enable operation of one or more features comprising the IC during LVP investigation.

Automating analog design: Taming the shrew

NASA Technical Reports Server (NTRS)

Barlow, A.

1990-01-01

The pace of progress in the design of integrated circuits continues to amaze observers inside and outside of the industry. Three decades ago, a 50 transistor chip was a technological wonder. Fifteen year later, a 5000 transistor device would 'wow' the crowds. Today, 50,000 transistor chips will earn a 'not too bad' assessment, but it takes 500,000 to really leave an impression. In 1975 a typical ASIC device had 1000 transistors, took one year to first samples (and two years to production) and sold for about 5 cents per transistor. Today's 50,000 transistor gate array takes about 4 months from spec to silicon, works the first time, and sells for about 0.02 cents per transistor. Fifteen years ago, the single most laborious and error prone step in IC design was the physical layout. Today, most IC's never see the hand of a layout designer: and automatic place and route tool converts the engineer's computer captured schematic to a complete physical design using a gate array or a library of standard cells also created by software rather than by designers. CAD has also been a generous benefactor to the digital design process. The architect of today's digital systems creates the design using an RTL or other high level simulator. Then the designer pushes a button to invoke the logic synthesizer-optimizer tool. A fault analyzer checks the result for testability and suggests where scan based cells will improve test coverage. One obstinate holdout amidst this parade of progress is the automation of analog design and its reduction to semi-custom techniques. This paper investigates the application of CAD techniques to analog design.

Equivalent radiation source of 3D package for electromagnetic characteristics analysis

NASA Astrophysics Data System (ADS)

Li, Jun; Wei, Xingchang; Shu, Yufei

2017-10-01

An equivalent radiation source method is proposed to characterize electromagnetic emission and interference of complex three dimensional integrated circuits (IC) in this paper. The method utilizes amplitude-only near-field scanning data to reconstruct an equivalent magnetic dipole array, and the differential evolution optimization algorithm is proposed to extract the locations, orientation and moments of those dipoles. By importing the equivalent dipoles model into a 3D full-wave simulator together with the victim circuit model, the electromagnetic interference issues in mixed RF/digital systems can be well predicted. A commercial IC is used to validate the accuracy and efficiency of this proposed method. The coupled power at the victim antenna port calculated by the equivalent radiation source is compared with the measured data. Good consistency is obtained which confirms the validity and efficiency of the method. Project supported by the National Nature Science Foundation of China (No. 61274110).

Novel AlInN/GaN integrated circuits operating up to 500 °C

NASA Astrophysics Data System (ADS)

Gaska, R.; Gaevski, M.; Jain, R.; Deng, J.; Islam, M.; Simin, G.; Shur, M.

2015-11-01

High electron concentration in 2DEG channel of AlInN/GaN devices is remarkably stable over a broad temperature range, enabling device operation above 500 °C. The developed IC technology is based on three key elements: (1) exceptional quality AlInN/GaN heterostructure with very high carrier concentration and mobility enables IC fast operation in a broad temperature range; (2) heterostructure field effect transistor approach t provides fully planar IC structure which is easy to scale and to combine with the other high temperature electronic components; (3) fabrication advancements including novel metallization scheme and high-K passivation/gate dielectrics enable high temperature operation. The feasibility of the developed technology was confirmed by fabrication and testing of the high temperature inverter and differential amplifier ICs using AlInN/GaN heterostructures. The developed ICs showed stable performance with unit-gain bandwidth above 1 MHz and internal response time 45 ns at temperatures as high as 500 °C.

High-voltage integrated active quenching circuit for single photon count rate up to 80 Mcounts/s.

PubMed

Acconcia, Giulia; Rech, Ivan; Gulinatti, Angelo; Ghioni, Massimo

2016-08-08

Single photon avalanche diodes (SPADs) have been subject to a fast improvement in recent years. In particular, custom technologies specifically developed to fabricate SPAD devices give the designer the freedom to pursue the best detector performance required by applications. A significant breakthrough in this field is represented by the recent introduction of a red enhanced SPAD (RE-SPAD) technology, capable of attaining a good photon detection efficiency in the near infrared range (e.g. 40% at a wavelength of 800 nm) while maintaining a remarkable timing resolution of about 100ps full width at half maximum. Being planar, the RE-SPAD custom technology opened the way to the development of SPAD arrays particularly suited for demanding applications in the field of life sciences. However, to achieve such excellent performance custom SPAD detectors must be operated with an external active quenching circuit (AQC) designed on purpose. Next steps toward the development of compact and practical multichannel systems will require a new generation of monolithically integrated AQC arrays. In this paper we present a new, fully integrated AQC fabricated in a high-voltage 0.18 µm CMOS technology able to provide quenching pulses up to 50 Volts with fast leading and trailing edges. Although specifically designed for optimal operation of RE-SPAD devices, the new AQC is quite versatile: it can be used with any SPAD detector, regardless its fabrication technology, reaching remarkable count rates up to 80 Mcounts/s and generating a photon detection pulse with a timing jitter as low as 119 ps full width at half maximum. The compact design of our circuit has been specifically laid out to make this IC a suitable building block for monolithically integrated AQC arrays.

Imbalanced spontaneous brain activity in orbitofrontal-insular circuits in individuals with cognitive vulnerability to depression.

PubMed

Zhang, Xiaocui; Di, Xin; Lei, Hui; Yang, Juan; Xiao, Jing; Wang, Xiang; Yao, Shuqiao; Rao, Hengyi

2016-07-01

The hopelessness theory of depression posits that individuals with negative cognitive styles are at risk of developing depression following negative life events. The purpose of this work was to examine whether individuals with cognitive vulnerability to depression (CVD) exhibit similar spontaneous brain activity patterns as compared to patients with major depressive disorder (MDD). Subjects with CVD (N=32), drug-naïve first-episode patients with major depressive disorder (N=32), and sex-, age- and education-matched healthy controls (HCs; N=35) were subjected to resting state functional magnetic resonance imaging (RS-fMRI) and amplitudes of low-frequency fluctuation (ALFF) was compared between the groups. Pearson correlation analysis was performed between regional ALFFs and psychometric scores, namely the Cognitive Style Questionnaire (CSQ) and the Center for Epidemiologic Studies Depression (CES-D) scale scores. Significant group differences in ALFF values were observed bilaterally in the orbitofrontal cortex (OFC) and insular cortex (IC), and in the left fusiform gyrus (FFG). Compared to HCs, CVD subjects had reduced ALFFs in the bilateral OFC and increased ALFF in the bilateral IC and the left FFG, which were similar to the differences observed between the HCs and MDD patients. Compared to MDD patients, CVD subjects showed significant reduced ALFF values in right IC. Additionally, CSQ scores for the CVD group correlated with ALFF values in the left IC. We did not conduct a longitudinal study. Our findings were limited in cross-sectional analysis. A hypoactive OFC and hyperactive IC in a resting-state may underlie an imbalance in the spontaneous brain activity in orbitofrontal-insular circuits, and these differences may represent a trait-related marker of vulnerability to depression. Copyright © 2016 Elsevier B.V. All rights reserved.

Postinhibitory rebound neurons and networks are disrupted in retrovirus-induced spongiform neurodegeneration

PubMed Central

Li, Ying; Davey, Robert A.; Lynch, William P.

2014-01-01

Certain retroviruses induce progressive spongiform motor neuron disease with features resembling prion diseases and amyotrophic lateral sclerosis. With the neurovirulent murine leukemia virus (MLV) FrCasE, Env protein expression within glia leads to postsynaptic vacuolation, cellular effacement, and neuronal loss in the absence of neuroinflammation. To understand the physiological changes associated with MLV-induced spongiosis, and its neuronal specificity, we employed patch-clamp recordings and voltage-sensitive dye imaging in brain slices of the mouse inferior colliculus (IC), a midbrain nucleus that undergoes extensive spongiosis. IC neurons characterized by postinhibitory rebound firing (PIR) were selectively affected in FrCasE-infected mice. Coincident with Env expression in microglia and in glia characterized by NG2 proteoglycan expression (NG2 cells), rebound neurons (RNs) lost PIR, became hyperexcitable, and were reduced in number. PIR loss and hyperexcitability were reversed by raising internal calcium buffer concentrations in RNs. PIR-initiated rhythmic circuits were disrupted, and spontaneous synchronized bursting and prolonged depolarizations were widespread. Other IC neuron cell types and circuits within the same degenerative environment were unaffected. Antagonists of NMDA and/or AMPA receptors reduced burst firing in the IC but did not affect prolonged depolarizations. Antagonists of L-type calcium channels abolished both bursts and slow depolarizations. IC infection by the nonneurovirulent isogenic virus Friend 57E (Fr57E), whose Env protein is structurally similar to FrCasE, showed no RN hyperactivity or cell loss; however, PIR latency increased. These findings suggest that spongiform neurodegeneration arises from the unique excitability of RNs, their local regulation by glia, and the disruption of this relationship by glial expression of abnormal protein. PMID:25252336

A three-channel LED driver with single line transportation technique

NASA Astrophysics Data System (ADS)

Yu, Caideng; Du, Yiying; Jiang, Qiao; Zhou, Yun; Lv, Jian

2012-10-01

Designed a three-channel LED driver, realized the single-wire transmission of cascade signal between the drive IC of LED. Including the MCU digital interface, date register, clock synchronization, PWM grayscale adjustment circuit, as well as high voltage driver circuit for LED, etc… The driver control LED displaying 256 gray. Chip will generate synchronous sampling clock signals according to the received serial signals, when 24 bits dates have been received, the output pin begins to transport the dates followed-up which are automotive shaped to the input of the next chip. When the date receiving becomes low level that represent RESET, the red, green and blue channels will export different signals based on different input dates. Through the external MCU, it is realized the Separate luminance, and by connecting chips in series it achieved the control of outdoor big screen' colorful display. The automatic shaping forward technique makes the number of chips cascading immune to the limitations of signal transmission, but only limited by the refresh speed.

Configurable analog-digital conversion using the neural engineering framework

PubMed Central

Mayr, Christian G.; Partzsch, Johannes; Noack, Marko; Schüffny, Rene

2014-01-01

Efficient Analog-Digital Converters (ADC) are one of the mainstays of mixed-signal integrated circuit design. Besides the conventional ADCs used in mainstream ICs, there have been various attempts in the past to utilize neuromorphic networks to accomplish an efficient crossing between analog and digital domains, i.e., to build neurally inspired ADCs. Generally, these have suffered from the same problems as conventional ADCs, that is they require high-precision, handcrafted analog circuits and are thus not technology portable. In this paper, we present an ADC based on the Neural Engineering Framework (NEF). It carries out a large fraction of the overall ADC process in the digital domain, i.e., it is easily portable across technologies. The analog-digital conversion takes full advantage of the high degree of parallelism inherent in neuromorphic networks, making for a very scalable ADC. In addition, it has a number of features not commonly found in conventional ADCs, such as a runtime reconfigurability of the ADC sampling rate, resolution and transfer characteristic. PMID:25100933

Out Flying the Eagle: China’s Drive for Domestic Economic Innovation and Its Impact on U.S.-China Relations

DTIC Science & Technology

2014-03-01

wind turbines from General Electric. China recognizes the issues with IPR but it is something that will take time to fix. It will be a significant...Large aircraft  Large-scale oil and gas exploration  Manned space, including lunar exploration  Next-generation broadband wireless ...circuits, and building an innovation system for China’s integrated circuit (IC) manufacturing industry. 3. New generation broadband wireless mobile

Non-Contact Circuit for Real-Time Electric and Magnetic Field Measurements

DTIC Science & Technology

2015-10-01

addresses these needs, and additionally has “smart” features that adjust integrated circuits ( ICs ) on the sensor during start-up based upon the...Hall effect sensors, the datasheet information on the MLX91205 gives a dynamic range of 66 to 96 dB for frequencies of 10 Hz and 10 kHz, respectively...Electric Field Sensors. 18 August 2009. 4. Melexis. IMC-Hall Current Sensor, MLX91205 Datasheet . June. 2012 5. Vinci SJ, Hull DM. Electrostatic

Silicon ball grid array chip carrier

DOEpatents

Palmer, David W.; Gassman, Richard A.; Chu, Dahwey

2000-01-01

A ball-grid-array integrated circuit (IC) chip carrier formed from a silicon substrate is disclosed. The silicon ball-grid-array chip carrier is of particular use with ICs having peripheral bond pads which can be reconfigured to a ball-grid-array. The use of a semiconductor substrate such as silicon for forming the ball-grid-array chip carrier allows the chip carrier to be fabricated on an IC process line with, at least in part, standard IC processes. Additionally, the silicon chip carrier can include components such as transistors, resistors, capacitors, inductors and sensors to form a "smart" chip carrier which can provide added functionality and testability to one or more ICs mounted on the chip carrier. Types of functionality that can be provided on the "smart" chip carrier include boundary-scan cells, built-in test structures, signal conditioning circuitry, power conditioning circuitry, and a reconfiguration capability. The "smart" chip carrier can also be used to form specialized or application-specific ICs (ASICs) from conventional ICs. Types of sensors that can be included on the silicon ball-grid-array chip carrier include temperature sensors, pressure sensors, stress sensors, inertia or acceleration sensors, and/or chemical sensors. These sensors can be fabricated by IC processes and can include microelectromechanical (MEM) devices.

A Study of Direct Digital Manufactured RF/Microwave Packaging

NASA Astrophysics Data System (ADS)

Stratton, John W. I.

Various facets of direct digital manufactured (DDM) microwave packages are studied. The rippled surface inherent in fused deposition modeling (FDM) fabricated geometries is modeled in Ansoft HFSS, and its effect on the performance of microstrip transmission lines is assessed via simulation and measurement. The thermal response of DDM microstrip transmission lines is analyzed over a range of RF input powers, and linearity is confirmed over that range. Two IC packages are embedded into DDM printed circuit boards, and their performance is analyzed. The first is a low power RF switch, and the second is an RF front end device that includes a low noise amplifier (LNA) and a power amplifier (PA). The RF switch is shown to perform well, as compared to a layout designed for a Rogers 4003C microwave laminate substrate. The LNA performs within datasheet specifications. The power amplifier generates substantial heat, so a thermal management attempt is described. Finally, a capacitively loaded 6dB Wilkinson power divider is designed and fabricated using DDM techniques and materials. Its performance is analyzed and compared to simulation. The device is shown to compare favorably to a similar device fabricated on a Rogers 4003C microwave laminate using traditional printed circuit board techniques.

A Subthreshold Digital Library Using a Dynamic-Threshold Metal-Oxide Semiconductor (DTMOS) and Transmission Gate Logic

DTIC Science & Technology

2014-09-01

electrocardiography (ECG), electromyography (EMG), and electroencephalography (EEG) applications that operate using thermoelectrically generated energy...semiconductor ECG electrocardiography EEG electroencephalography EMG electromyography FY15 fiscal year 2015 IC integrated circuit MOSFETs

Fully Integrated Biopotential Acquisition Analog Front-End IC

PubMed Central

Song, Haryong; Park, Yunjong; Kim, Hyungseup; Ko, Hyoungho

2015-01-01

A biopotential acquisition analog front-end (AFE) integrated circuit (IC) is presented. The biopotential AFE includes a capacitively coupled chopper instrumentation amplifier (CCIA) to achieve low input referred noise (IRN) and to block unwanted DC potential signals. A DC servo loop (DSL) is designed to minimize the offset voltage in the chopper amplifier and low frequency respiration artifacts. An AC coupled ripple rejection loop (RRL) is employed to reduce ripple due to chopper stabilization. A capacitive impedance boosting loop (CIBL) is designed to enhance the input impedance and common mode rejection ratio (CMRR) without additional power consumption, even under an external electrode mismatch. The AFE IC consists of two-stage CCIA that include three compensation loops (DSL, RRL, and CIBL) at each CCIA stage. The biopotential AFE is fabricated using a 0.18 µm one polysilicon and six metal layers (1P6M) complementary metal oxide semiconductor (CMOS) process. The core chip size of the AFE without input/output (I/O) pads is 10.5 mm2. A fourth-order band-pass filter (BPF) with a pass-band in the band-width from 1 Hz to 100 Hz was integrated to attenuate unwanted signal and noise. The overall gain and band-width are reconfigurable by using programmable capacitors. The IRN is measured to be 0.94 µVRMS in the pass band. The maximum amplifying gain of the pass-band was measured as 71.9 dB. The CIBL enhances the CMRR from 57.9 dB to 67 dB at 60 Hz under electrode mismatch conditions. PMID:26437404

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kisner, Roger A; Melin, Alexander M; Burress, Timothy A

The overall project objective is to demonstrate improved reliability and increased performance made possible by deeply embedding instrumentation and controls (I&C) in nuclear power plant components. The project is employing a highly instrumented canned rotor, magnetic bearing, fluoride salt pump as its I&C technology demonstration vehicle. The project s focus is not primarily on pump design, but instead is on methods to deeply embed I&C within a pump system. However, because the I&C is intimately part of the basic millisecond-by-millisecond functioning of the pump, the I&C design cannot proceed in isolation from the other aspects of the pump. The pumpmore » will not function if the characteristics of the I&C are not embedded within the design because the I&C enables performance of the basic function rather than merely monitoring quasi-stable performance. Traditionally, I&C has been incorporated in nuclear power plant (NPP) components after their design is nearly complete; adequate performance was obtained through over-design. This report describes the progress and status of the project and provides a conceptual design overview for the embedded I&C pump.« less

An RFID-based on-lens sensor system for long-term IOP monitoring.

PubMed

Hsu, Shun-Hsi; Chiou, Jin-Chern; Liao, Yu-Te; Yang, Tzu-Sen; Kuei, Cheng-Kai; Wu, Tsung-Wei; Huang, Yu-Chieh

2015-01-01

In this paper, an RFID-based on-lens sensor system is proposed for noninvasive long-term intraocular pressure monitoring. The proposed sensor IC, fabricated in a 0.18um CMOS process, consists of capacitive sensor readout circuitry, RFID communication circuits, and digital processing units. The sensor IC is integrated with electroplating capacitive sensors and a receiving antenna on the contact lens. The sensor IC can be wirelessly powered, communicate with RFID compatible equipment, and perform IOP measurement using on-lens capacitive sensor continuously from a 2cm distance while the incident power from an RFID reader is 20 dBm. The proposed system is compatible to Gen2 RFID protocol, extending the flexibility and reducing the self-developed firmware efforts.

3D-ICs created using oblique processing

NASA Astrophysics Data System (ADS)

Burckel, D. Bruce

2016-03-01

This paper demonstrates that another class of three-dimensional integrated circuits (3D-ICs) exists, distinct from through silicon via centric and monolithic 3D-ICs. Furthermore, it is possible to create devices that are 3D at the device level (i.e. with active channels oriented in each of the three coordinate axes), by performing standard CMOS fabrication operations at an angle with respect to the wafer surface into high aspect ratio silicon substrates using membrane projection lithography (MPL). MPL requires only minimal fixturing changes to standard CMOS equipment, and no change to current state-of-the-art lithography. Eliminating the constraint of 2D planar device architecture enables a wide range of new interconnect topologies which could help reduce interconnect resistance/capacitance, and potentially improve performance.

Counterfeit Electronics Detection Using Image Processing and Machine Learning

NASA Astrophysics Data System (ADS)

Asadizanjani, Navid; Tehranipoor, Mark; Forte, Domenic

2017-01-01

Counterfeiting is an increasing concern for businesses and governments as greater numbers of counterfeit integrated circuits (IC) infiltrate the global market. There is an ongoing effort in experimental and national labs inside the United States to detect and prevent such counterfeits in the most efficient time period. However, there is still a missing piece to automatically detect and properly keep record of detected counterfeit ICs. Here, we introduce a web application database that allows users to share previous examples of counterfeits through an online database and to obtain statistics regarding the prevalence of known defects. We also investigate automated techniques based on image processing and machine learning to detect different physical defects and to determine whether or not an IC is counterfeit.

Dynamical Competition of IC-Industry Clustering from Taiwan to China

NASA Astrophysics Data System (ADS)

Tsai, Bi-Huei; Tsai, Kuo-Hui

2009-08-01

Most studies employ qualitative approach to explore the industrial clusters; however, few research has objectively quantified the evolutions of industry clustering. The purpose of this paper is to quantitatively analyze clustering among IC design, IC manufacturing as well as IC packaging and testing industries by using the foreign direct investment (FDI) data. The Lotka-Volterra system equations are first adopted here to capture the competition or cooperation among such three industries, thus explaining their clustering inclinations. The results indicate that the evolution of FDI into China for IC design industry significantly inspire the subsequent FDI of IC manufacturing as well as IC packaging and testing industries. Since IC design industry lie in the upstream stage of IC production, the middle-stream IC manufacturing and downstream IC packing and testing enterprises tend to cluster together with IC design firms, in order to sustain a steady business. Finally, Taiwan IC industry's FDI amount into China is predicted to cumulatively increase, which supports the industrial clustering tendency for Taiwan IC industry. Particularly, the FDI prediction of Lotka-Volterra model performs superior to that of the conventional Bass model after the forecast accuracy of these two models are compared. The prediction ability is dramatically improved as the industrial mutualism among each IC production stage is taken into account.

Fast time- and frequency-domain finite-element methods for electromagnetic analysis

NASA Astrophysics Data System (ADS)

Lee, Woochan

Fast electromagnetic analysis in time and frequency domain is of critical importance to the design of integrated circuits (IC) and other advanced engineering products and systems. Many IC structures constitute a very large scale problem in modeling and simulation, the size of which also continuously grows with the advancement of the processing technology. This results in numerical problems beyond the reach of existing most powerful computational resources. Different from many other engineering problems, the structure of most ICs is special in the sense that its geometry is of Manhattan type and its dielectrics are layered. Hence, it is important to develop structure-aware algorithms that take advantage of the structure specialties to speed up the computation. In addition, among existing time-domain methods, explicit methods can avoid solving a matrix equation. However, their time step is traditionally restricted by the space step for ensuring the stability of a time-domain simulation. Therefore, making explicit time-domain methods unconditionally stable is important to accelerate the computation. In addition to time-domain methods, frequency-domain methods have suffered from an indefinite system that makes an iterative solution difficult to converge fast. The first contribution of this work is a fast time-domain finite-element algorithm for the analysis and design of very large-scale on-chip circuits. The structure specialty of on-chip circuits such as Manhattan geometry and layered permittivity is preserved in the proposed algorithm. As a result, the large-scale matrix solution encountered in the 3-D circuit analysis is turned into a simple scaling of the solution of a small 1-D matrix, which can be obtained in linear (optimal) complexity with negligible cost. Furthermore, the time step size is not sacrificed, and the total number of time steps to be simulated is also significantly reduced, thus achieving a total cost reduction in CPU time. The second contribution is a new method for making an explicit time-domain finite-element method (TDFEM) unconditionally stable for general electromagnetic analysis. In this method, for a given time step, we find the unstable modes that are the root cause of instability, and deduct them directly from the system matrix resulting from a TDFEM based analysis. As a result, an explicit TDFEM simulation is made stable for an arbitrarily large time step irrespective of the space step. The third contribution is a new method for full-wave applications from low to very high frequencies in a TDFEM based on matrix exponential. In this method, we directly deduct the eigenmodes having large eigenvalues from the system matrix, thus achieving a significantly increased time step in the matrix exponential based TDFEM. The fourth contribution is a new method for transforming the indefinite system matrix of a frequency-domain FEM to a symmetric positive definite one. We deduct non-positive definite component directly from the system matrix resulting from a frequency-domain FEM-based analysis. The resulting new representation of the finite-element operator ensures an iterative solution to converge in a small number of iterations. We then add back the non-positive definite component to synthesize the original solution with negligible cost.

CMOS Imaging of Temperature Effects on Pin-Printed Xerogel Sensor Microarrays.

PubMed

Lei Yao; Ka Yi Yung; Chodavarapu, Vamsy P; Bright, Frank V

2011-04-01

In this paper, we study the effect of temperature on the operation and performance of a xerogel-based sensor microarrays coupled to a complementary metal-oxide semiconductor (CMOS) imager integrated circuit (IC) that images the photoluminescence response from the sensor microarray. The CMOS imager uses a 32 × 32 (1024 elements) array of active pixel sensors and each pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. A correlated double sampling circuit and pixel address/digital control/signal integration circuit are also implemented on-chip. The CMOS imager data are read out as a serial coded signal. The sensor system uses a light-emitting diode to excite target analyte responsive organometallic luminophores doped within discrete xerogel-based sensor elements. As a proto type, we developed a 3 × 3 (9 elements) array of oxygen (O2) sensors. Each group of three sensor elements in the array (arranged in a column) is designed to provide a different and specific sensitivity to the target gaseous O2 concentration. This property of multiple sensitivities is achieved by using a mix of two O2 sensitive luminophores in each pin-printed xerogel sensor element. The CMOS imager is designed to be low noise and consumes a static power of 320.4 μW and an average dynamic power of 624.6 μW when operating at 100-Hz sampling frequency and 1.8-V dc power supply.

Long-term reproducibility of relative sensitivity factors obtained with CAMECA Wf

NASA Astrophysics Data System (ADS)

Gui, D.; Xing, Z. X.; Huang, Y. H.; Mo, Z. Q.; Hua, Y. N.; Zhao, S. P.; Cha, L. Z.

2008-12-01

As the wafer size continues to increase and the feature size of the integrated circuits (IC) continues to shrink, process control of IC manufacturing becomes ever more important to reduce the cost of failures caused by the drift of processes or equipments. Characterization tools with high precision and reproducibility are required to capture any abnormality of the process. Although Secondary ion mass spectrometry (SIMS) has been widely used in dopant profile control, it was reported that magnetic sector SIMS, compared to quadrupole SIMS, has lower short-term repeatability and long-term reproducibility due to the high extraction field applied between sample and extraction lens. In this paper, we demonstrate that CAMECA Wf can deliver high long-term reproducibility because of its high-level automation and improved design of immersion lens. The relative standard deviation (R.S.D.) of the relative sensitivity factors (RSF) of three typical elements, i.e., boron (B), phosphorous (P) and nitrogen (N), over 3 years are 3.7%, 5.5% and 4.1%, respectively. The high reproducibility results have a practical implication that deviation can be estimated without testing the standards.

Highly integrated optical heterodyne phase-locked loop with phase/frequency detection.

PubMed

Lu, Mingzhi; Park, Hyunchul; Bloch, Eli; Sivananthan, Abirami; Bhardwaj, Ashish; Griffith, Zach; Johansson, Leif A; Rodwell, Mark J; Coldren, Larry A

2012-04-23

A highly-integrated optical phase-locked loop with a phase/frequency detector and a single-sideband mixer (SSBM) has been proposed and demonstrated for the first time. A photonic integrated circuit (PIC) has been designed, fabricated and tested, together with an electronic IC (EIC). The PIC integrates a widely-tunable sampled-grating distributed-Bragg-reflector laser, an optical 90 degree hybrid and four high-speed photodetectors on the InGaAsP/InP platform. The EIC adds a single-sideband mixer, and a digital phase/frequency detector, to provide single-sideband heterodyne locking from -9 GHz to 7.5 GHz. The loop bandwith is 400 MHz. © 2012 Optical Society of America

DOE Office of Scientific and Technical Information (OSTI.GOV)

Li, Menglu; Tu, K. N., E-mail: kntu@ucla.edu; Kim, Dong Wook

Thermal-crosstalk induced thermomigration failure in un-powered microbumps has been found in 2.5D integrated circuit (IC) circuit. In 2.5D IC, a Si interposer was used between a polymer substrate and a device chip which has transistors. The interposer has no transistors. If transistors are added to the interposer chip, it becomes 3D IC. In our test structure, there are two Si chips placed horizontally on a Si interposer. The vertical connections between the interposer and the Si chips are through microbumps. We powered one daisy chain of the microbumps under one Si chip; however, the un-powered microbumps in the neighboring chipmore » are failed with big holes in the solder layer. We find that Joule heating from the powered microbumps is transferred horizontally to the bottom of the neighboring un-powered microbumps, and creates a large temperature gradient, in the order of 1000 °C/cm, through the un-powered microbumps in the neighboring chip, so the latter failed by thermomigration. In addition, we used synchrotron radiation tomography to compare three sets of microbumps in the test structure: microbumps under electromigration, microbumps under thermomigration, and microbumps under a constant temperature thermal annealing. The results show that the microbumps under thermomigration have the largest damage. Furthermore, simulation of temperature distribution in the test structure supports the finding of thermomigration.« less

A battery-free multichannel digital neural/EMG telemetry system for flying insects.

PubMed

Thomas, Stewart J; Harrison, Reid R; Leonardo, Anthony; Reynolds, Matthew S

2012-10-01

This paper presents a digital neural/EMG telemetry system small enough and lightweight enough to permit recording from insects in flight. It has a measured flight package mass of only 38 mg. This system includes a single-chip telemetry integrated circuit (IC) employing RF power harvesting for battery-free operation, with communication via modulated backscatter in the UHF (902-928 MHz) band. An on-chip 11-bit ADC digitizes 10 neural channels with a sampling rate of 26.1 kSps and 4 EMG channels at 1.63 kSps, and telemeters this data wirelessly to a base station. The companion base station transceiver includes an RF transmitter of +36 dBm (4 W) output power to wirelessly power the telemetry IC, and a digital receiver with a sensitivity of -70 dBm for 10⁻⁵ BER at 5.0 Mbps to receive the data stream from the telemetry IC. The telemetry chip was fabricated in a commercial 0.35 μ m 4M1P (4 metal, 1 poly) CMOS process. The die measures 2.36 × 1.88 mm, is 250 μm thick, and is wire bonded into a flex circuit assembly measuring 4.6 × 6.8 mm.

Design and Experiment of Electrooculogram (EOG) System and Its Application to Control Mobile Robot

NASA Astrophysics Data System (ADS)

Sanjaya, W. S. M.; Anggraeni, D.; Multajam, R.; Subkhi, M. N.; Muttaqien, I.

2017-03-01

In this paper, we design and investigate a biological signal detection of eye movements (Electrooculogram). To detect a signal of Electrooculogram (EOG) used 4 instrument amplifier process; differential instrumentation amplifier, High Pass Filter (HPF) with 3 stage filters, Low Pass Filter (LPF) with 3 stage filters and Level Shifter circuit. The total of amplifying is 1000 times of gain, with frequency range 0.5-30 Hz. IC OP-Amp OP07 was used for all amplifying process. EOG signal will be read as analog input for Arduino microprocessor, and will interfaced with serial communication to PC Monitor using Processing® software. The result of this research show a differences value of eye movements. Differences signal of EOG have been applied to navigation control of the mobile robot. In this research, all communication process using Bluetooth HC-05.

Resonant Rectifier ICs for Piezoelectric Energy Harvesting Using Low-Voltage Drop Diode Equivalents

PubMed Central

Din, Amad Ud; Chandrathna, Seneke Chamith; Lee, Jong-Wook

2017-01-01

Herein, we present the design technique of a resonant rectifier for piezoelectric (PE) energy harvesting. We propose two diode equivalents to reduce the voltage drop in the rectifier operation, a minuscule-drop-diode equivalent (MDDE) and a low-drop-diode equivalent (LDDE). The diode equivalents are embedded in resonant rectifier integrated circuits (ICs), which use symmetric bias-flip to reduce the power used for charging and discharging the internal capacitance of a PE transducer. The self-startup function is supported by synchronously generating control pulses for the bias-flip from the PE transducer. Two resonant rectifier ICs, using both MDDE and LDDE, are fabricated in a 0.18 μm CMOS process and their performances are characterized under external and self-power conditions. Under the external-power condition, the rectifier using LDDE delivers an output power POUT of 564 μW and a rectifier output voltage VRECT of 3.36 V with a power transfer efficiency of 68.1%. Under self-power conditions, the rectifier using MDDE delivers a POUT of 288 μW and a VRECT of 2.4 V with a corresponding efficiency of 78.4%. Using the proposed bias-flip technique, the power extraction capability of the proposed rectifier is 5.9 and 3.0 times higher than that of a conventional full-bridge rectifier. PMID:28422085

Resonant Rectifier ICs for Piezoelectric Energy Harvesting Using Low-Voltage Drop Diode Equivalents.

PubMed

Din, Amad Ud; Chandrathna, Seneke Chamith; Lee, Jong-Wook

2017-04-19

Herein, we present the design technique of a resonant rectifier for piezoelectric (PE) energy harvesting. We propose two diode equivalents to reduce the voltage drop in the rectifier operation, a minuscule-drop-diode equivalent (MDDE) and a low-drop-diode equivalent (LDDE). The diode equivalents are embedded in resonant rectifier integrated circuits (ICs), which use symmetric bias-flip to reduce the power used for charging and discharging the internal capacitance of a PE transducer. The self-startup function is supported by synchronously generating control pulses for the bias-flip from the PE transducer. Two resonant rectifier ICs, using both MDDE and LDDE, are fabricated in a 0.18 μm CMOS process and their performances are characterized under external and self-power conditions. Under the external-power condition, the rectifier using LDDE delivers an output power P OUT of 564 μW and a rectifier output voltage V RECT of 3.36 V with a power transfer efficiency of 68.1%. Under self-power conditions, the rectifier using MDDE delivers a P OUT of 288 μW and a V RECT of 2.4 V with a corresponding efficiency of 78.4%. Using the proposed bias-flip technique, the power extraction capability of the proposed rectifier is 5.9 and 3.0 times higher than that of a conventional full-bridge rectifier.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kisner, R.; Melin, A.; Burress, T.

The objective of this project is to demonstrate improved reliability and increased performance made possible by deeply embedding instrumentation and controls (I&C) in nuclear power plant (NPP) components and systems. The project is employing a highly instrumented canned rotor, magnetic bearing, fluoride salt pump as its I&C technology demonstration platform. I&C is intimately part of the basic millisecond-by-millisecond functioning of the system; treating I&C as an integral part of the system design is innovative and will allow significant improvement in capabilities and performance. As systems become more complex and greater performance is required, traditional I&C design techniques become inadequate andmore » more advanced I&C needs to be applied. New I&C techniques enable optimal and reliable performance and tolerance of noise and uncertainties in the system rather than merely monitoring quasistable performance. Traditionally, I&C has been incorporated in NPP components after the design is nearly complete; adequate performance was obtained through over-design. By incorporating I&C at the beginning of the design phase, the control system can provide superior performance and reliability and enable designs that are otherwise impossible. This report describes the progress and status of the project and provides a conceptual design overview for the platform to demonstrate the performance and reliability improvements enabled by advanced embedded I&C.« less

An improved instantaneous frequency meter for use with a multi-trace CRO: re-examination of the principles involved.

PubMed

Obara, S; Nagai, T

1983-01-01

The instantaneous frequency display of single unit discharges provides a useful measure of neuronal activities. Such a device must produce voltage outputs proportional to the reciprocal of each inter-spike interval by on-line computation of the hyperbola of V = a/t. Segment approximation of the required hyperbola can be made by a series of exponential functions which increase in time constants by a factor of m. Numerical analysis of a normalized function indicates possible error maxima of 3.4, 2.4 and 1.1% for m of 2, 1.8 and 1.5, respectively. This prediction is fully confirmed by the actual performance where m of 1.5 is adopted. The test circuit combines only readily available ICs and other components, to give a linear F-V conversion over a dynamic range of 4-600 Hz with error maxima of approximately 1%. The outputs are square pulses of approximately 1.5 ms in duration through the use of a flexible sample-hold circuit. Compared with that of earlier models, this display mode gives better photographic records with the base-line in simultaneous multi-trace display. Simple and systematic methods are described for designing a circuit to one's own specifications, and also for compensating for component variations.

Field Programmable Gate Array Failure Rate Estimation Guidelines for Launch Vehicle Fault Tree Models

NASA Technical Reports Server (NTRS)

Al Hassan, Mohammad; Britton, Paul; Hatfield, Glen Spencer; Novack, Steven D.

2017-01-01

Today's launch vehicles complex electronic and avionics systems heavily utilize Field Programmable Gate Array (FPGA) integrated circuits (IC) for their superb speed and reconfiguration capabilities. Consequently, FPGAs are prevalent ICs in communication protocols such as MILSTD- 1553B and in control signal commands such as in solenoid valve actuations. This paper will identify reliability concerns and high level guidelines to estimate FPGA total failure rates in a launch vehicle application. The paper will discuss hardware, hardware description language, and radiation induced failures. The hardware contribution of the approach accounts for physical failures of the IC. The hardware description language portion will discuss the high level FPGA programming languages and software/code reliability growth. The radiation portion will discuss FPGA susceptibility to space environment radiation.

On the use of new generation mobile phone (smart phone) for retrospective accident dosimetry

NASA Astrophysics Data System (ADS)

Lee, J. I.; Chang, I.; Pradhan, A. S.; Kim, J. L.; Kim, B. H.; Chung, K. S.

2015-11-01

Optically stimulated luminescence (OSL) characteristics of resistors, inductors and integrated-circuit (IC) chips, extracted from new generation smart phones, were investigated for the purpose of retrospective accident dosimetry. Inductor samples were found to exhibit OSL sensitivity about 5 times and 40 times higher than that of the resistors and the IC chips, respectively. On post-irradiation storage, the resistors exhibited a much higher OSL fading (about 80 % in 36 h as compared to the value 3 min after irradiation) than IC chips (about 20 % after 36 h) and inductors (about 50 % in 36 h). Higher OSL sensitivity, linear dose response (from 8.7 mGy up to 8.9 Gy) and acceptable fading make inductors more attractive for accident dosimetry than widely studied resistors.

HYMOSS signal processing for pushbroom spectral imaging

NASA Technical Reports Server (NTRS)

Ludwig, David E.

1991-01-01

The objective of the Pushbroom Spectral Imaging Program was to develop on-focal plane electronics which compensate for detector array non-uniformities. The approach taken was to implement a simple two point calibration algorithm on focal plane which allows for offset and linear gain correction. The key on focal plane features which made this technique feasible was the use of a high quality transimpedance amplifier (TIA) and an analog-to-digital converter for each detector channel. Gain compensation is accomplished by varying the feedback capacitance of the integrate and dump TIA. Offset correction is performed by storing offsets in a special on focal plane offset register and digitally subtracting the offsets from the readout data during the multiplexing operation. A custom integrated circuit was designed, fabricated, and tested on this program which proved that nonuniformity compensated, analog-to-digital converting circuits may be used to read out infrared detectors. Irvine Sensors Corporation (ISC) successfully demonstrated the following innovative on-focal-plane functions that allow for correction of detector non-uniformities. Most of the circuit functions demonstrated on this program are finding their way onto future IC's because of their impact on reduced downstream processing, increased focal plane performance, simplified focal plane control, reduced number of dewar connections, as well as the noise immunity of a digital interface dewar. The potential commercial applications for this integrated circuit are primarily in imaging systems. These imaging systems may be used for: security monitoring systems, manufacturing process monitoring, robotics, and for spectral imaging when used in analytical instrumentation.

HYMOSS signal processing for pushbroom spectral imaging

NASA Astrophysics Data System (ADS)

Ludwig, David E.

1991-06-01

The objective of the Pushbroom Spectral Imaging Program was to develop on-focal plane electronics which compensate for detector array non-uniformities. The approach taken was to implement a simple two point calibration algorithm on focal plane which allows for offset and linear gain correction. The key on focal plane features which made this technique feasible was the use of a high quality transimpedance amplifier (TIA) and an analog-to-digital converter for each detector channel. Gain compensation is accomplished by varying the feedback capacitance of the integrate and dump TIA. Offset correction is performed by storing offsets in a special on focal plane offset register and digitally subtracting the offsets from the readout data during the multiplexing operation. A custom integrated circuit was designed, fabricated, and tested on this program which proved that nonuniformity compensated, analog-to-digital converting circuits may be used to read out infrared detectors. Irvine Sensors Corporation (ISC) successfully demonstrated the following innovative on-focal-plane functions that allow for correction of detector non-uniformities. Most of the circuit functions demonstrated on this program are finding their way onto future IC's because of their impact on reduced downstream processing, increased focal plane performance, simplified focal plane control, reduced number of dewar connections, as well as the noise immunity of a digital interface dewar. The potential commercial applications for this integrated circuit are primarily in imaging systems. These imaging systems may be used for: security monitoring systems, manufacturing process monitoring, robotics, and for spectral imaging when used in analytical instrumentation.

Substrate noise coupling: a pain for mixed-signal systems (Keynote Address)

NASA Astrophysics Data System (ADS)

Wambacq, Piet; Van der Plas, Geert; Donnay, Stephane; Badaroglu, Mustafa; Soens, Charlotte

2005-06-01

Crosstalk from digital to analog in mixed-signal ICs is recognized as one of the major roadblocks for systems-on-chip (SoC) in future CMOS technologies. This crosstalk mainly happens via the semiconducting silicon substrate, which is usually treated as a ground node by analog and RF designers. The substrate noise coupling problem leads more and more to malfunctioning or extra design iterations. One of the reasons is that the phenomenon of substrate noise coupling is difficult to model and hence difficult to understand. It can be caused by the switching of thousands or millions of gates and depends on layout details. From the generation side (the digital domain), coping with the large amount of noise generators can be solved by macromodeling. On the other hand, the impact of substrate noise on the analog circuits requires careful modeling at the level of transistors and parasitics of layout, power supply, package, PCB, Comparison to measurements of macromodeling at the digital side and careful modeling at the analog side, shows that both the generation and the impact of substrate noise can be predicted with an accuracy of a few dB. In addition, this combination of macromodeling at the digital side and careful modeling at the analog side leads to an understanding of the problem, which can be used for digital low-noise design techniques to minimize the generation of noise, and substrate noise immune design of analog/RF circuits.

Study of IEMP Effects on IC Operational Amplifier Circuits

DTIC Science & Technology

1975-12-10

plasma focus to study their IEMP responses with and without superposition of TREE responses. The 30-kJ plasma focus device produced photons primarily in the 8- to 100-keV range with pulse widths typically in the range of 10 to 15 nsec. Pulses of electrons were also deposited on the external leads of the operational amplifiers to determine the characteristic responses. These units were operated in circuits with closed-loop gains ranging from 5 to 100. During direct irradiation of the operational amplifiers, it was found that the IEMP responses (caused

A highly linear fully integrated powerline filter for biopotential acquisition systems.

PubMed

Alzaher, Hussain A; Tasadduq, Noman; Mahnashi, Yaqub

2013-10-01

Powerline interference is one of the most dominant problems in detection and processing of biopotential signals. This work presents a new fully integrated notch filter exhibiting high linearity and low power consumption. High filter linearity is preserved utilizing active-RC approach while IC implementation is achieved through replacing passive resistors by R-2R ladders achieving area saving of approximately 120 times. The filter design is optimized for low power operation using an efficient circuit topology and an ultra-low power operational amplifier. Fully differential implementation of the proposed filter shows notch depth of 43 dB (78 dB for 4th-order) with THD of better than -70 dB while consuming about 150 nW from 1.5 V supply.

MEMS switches having non-metallic crossbeams

NASA Technical Reports Server (NTRS)

Scardelletti, Maximillian C (Inventor)

2009-01-01

A RF MEMS switch comprising a crossbeam of SiC, supported by at least one leg above a substrate and above a plurality of transmission lines forming a CPW. Bias is provided by at least one layer of metal disposed on a top surface of the SiC crossbeam, such as a layer of chromium followed by a layer of gold, and extending beyond the switch to a biasing pad on the substrate. The switch utilizes stress and conductivity-controlled non-metallic thin cantilevers or bridges, thereby improving the RF characteristics and operational reliability of the switch. The switch can be fabricated with conventional silicon integrated circuit (IC) processing techniques. The design of the switch is very versatile and can be implemented in many transmission line mediums.

High-NA EUV projection lens with central obscuration

NASA Astrophysics Data System (ADS)

Zhevlakov, A. P.; Seisyan, R. P.; Bespalov, V. G.; Elizarov, V. V.; Grishkanich, A. S.; Kascheev, S. V.; Bagdasarov, A. A.; Sidorov, I. S.

2016-03-01

The lenses with coaxial mirrors allow obtain NA values up to of 0.8 and demagnification β >=10. The larger β value leads to the mask cost reducing, as in this case, the elements of the IC pattern template can be made bigger and, therefore, with fewer defects. Coaxial schemes can engender a problem of the image plane shift beyond the projection lens element boundaries near the wafer. The projection lens consisting of four coaxial mirrors with NA= 0.485 and s = 12 combined with the "Vanguard" imaging subsystem have been designed. According to the computation the circuit features at 10 nm in center and 20 nm on the edge of 12.4 mm field of view can be imaged.

A multichannel implantable telemetry system for flow, pressure, and ECG measurements

NASA Technical Reports Server (NTRS)

Fryer, T. B.; Sandler, H.; Freund, W.; Mccutcheon, E. P.; Carlson, E. L.

1975-01-01

The design, principles of operation, and performance of an implantable miniaturized (48 cu cm in volume) multiplex telemetry system for simultaneous measurement of up to eight physiological parameters (including cardiovascular data) are described. Integrated circuits are used to reduce the size, complexity, and cost of fabrication. Power consumption is reduced using recently developed complementary MOS devices. PWM technique is selected as it is relatively easy to implement, lends itself to ICs, and provides an accurate means of transmitting data. The system is totally implantable within the chest of a test animal, with no wire penetrating through the skin. It is shown that the described system permits repeated measurement of the physiological effects of a variety of interventions in awake unanesthetized animals.

Make Your Own Digital Thermometer!

ERIC Educational Resources Information Center

Sorey, Timothy; Willard, Teri; Kim, Bom

2010-01-01

In the hands-on, guided-inquiry lesson presented in this article, high school students create, calibrate, and apply an affordable scientific-grade instrument (Lapp and Cyrus 2000). In just four class periods, they build a homemade integrated circuit (IC) digital thermometer, apply a math model to calibrate their instrument, and ask a researchable…

Printed stretchable circuit on soft elastic substrate for wearable application

NASA Astrophysics Data System (ADS)

Yuan, Wei; Wu, Xinzhou; Gu, Weibing; Lin, Jian; Cui, Zheng

2018-01-01

In this paper, a flexible and stretchable circuit has been fabricated by the printing method based on Ag NWs/PDMS composite. The randomly oriented Ag NWs were buried in PDMS to form a conductive and stretchable electrode. Stable conductivity was achieved with a large range of tensile strain (0-50%) after the initial stretching/releasing cycle. The stable electrical response is due to the buckling of the Ag NWs/PDMS composite layer. Furthermore, printed stretchable circuits integrated with commercial ICs have been demonstrated for wearable applications. Project supported by the National Program on Key Basic Research Project (No. 2015CB351901), the Strategic Priority Research Program of the Chinese Academy of Sciences (No. XDA09020201), and the National Science Foundation of China (Nos. 51603227, 51603228).

Charge Yield at Low Electric Fields: Considerations for Bipolar Integrated Circuits

NASA Technical Reports Server (NTRS)

Johnston, A. H.; Swimm, R. T.; Thorbourn, D. O.

2013-01-01

A significant reduction in total dose damage is observed when bipolar integrated circuits are irradiated at low temperature. This can be partially explained by the Onsager theory of recombination, which predicts a strong temperature dependence for charge yield under low-field conditions. Reduced damage occurs for biased as well as unbiased devices because the weak fringing field in thick bipolar oxides only affects charge yield near the Si/SiO2 interface, a relatively small fraction of the total oxide thickness. Lowering the temperature of bipolar ICs - either continuously, or for time periods when they are exposed to high radiation levels - provides an additional degree of freedom to improve total dose performance of bipolar circuits, particularly in space applications.

Field Programmable Gate Array Failure Rate Estimation Guidelines for Launch Vehicle Fault Tree Models

NASA Technical Reports Server (NTRS)

Al Hassan, Mohammad; Novack, Steven D.; Hatfield, Glen S.; Britton, Paul

2017-01-01

Today's launch vehicles complex electronic and avionic systems heavily utilize the Field Programmable Gate Array (FPGA) integrated circuit (IC). FPGAs are prevalent ICs in communication protocols such as MIL-STD-1553B, and in control signal commands such as in solenoid/servo valves actuations. This paper will demonstrate guidelines to estimate FPGA failure rates for a launch vehicle, the guidelines will account for hardware, firmware, and radiation induced failures. The hardware contribution of the approach accounts for physical failures of the IC, FPGA memory and clock. The firmware portion will provide guidelines on the high level FPGA programming language and ways to account for software/code reliability growth. The radiation portion will provide guidelines on environment susceptibility as well as guidelines on tailoring other launch vehicle programs historical data to a specific launch vehicle.

A 25μm pitch LWIR focal plane array with pixel-level 15-bit ADC providing high well capacity and targeting 2mK NETD

NASA Astrophysics Data System (ADS)

Guellec, Fabrice; Peizerat, Arnaud; Tchagaspanian, Michael; de Borniol, Eric; Bisotto, Sylvette; Mollard, Laurent; Castelein, Pierre; Zanatta, Jean-Paul; Maillart, Patrick; Zecri, Michel; Peyrard, Jean-Christophe

2010-04-01

CEA Leti has recently developed a new readout IC (ROIC) with pixel-level ADC for cooled infrared focal plane arrays (FPAs). It operates at 50Hz frame rate in a snapshot Integrate-While-Read (IWR) mode. It targets applications that provide a large amount of integrated charge thanks to a long integration time. The pixel-level analog-to-digital conversion is based on charge packets counting. This technique offers a large well capacity that paves the way for a breakthrough in NETD performances. The 15 bits ADC resolution preserves the excellent detector SNR at full well (3Ge-). These characteristics are essential for LWIR FPAs as broad intra-scene dynamic range imaging requires high sensitivity. The ROIC, featuring a 320x256 array with 25μm pixel pitch, has been designed in a standard 0.18μm CMOS technology. The main design challenges for this digital pixel array (SNR, power consumption and layout density) are discussed. The IC has been hybridized to a LWIR detector fabricated using our in-house HgCdTe process. The first electro-optical test results of the detector dewar assembly are presented. They validate both the pixel-level ADC concept and its circuit implementation. Finally, the benefit of this LWIR FPA in terms of NETD performance is demonstrated.

Uncooled IR imager with 5-mK NEDT

NASA Astrophysics Data System (ADS)

Amantea, Robert; Knoedler, C. M.; Pantuso, Francis P.; Patel, Vipulkumar; Sauer, Donald J.; Tower, John R.

1997-08-01

The bi-material concept for room-temperature infrared imaging has the potential of reaching an NE(Delta) T approaching the theoretical limit because of its high responsivity and low noise. The approach, which is 100% compatible with silicon IC foundry processing, utilizes a novel combination of surface micromachining and conventional integrated circuits to produce a bimaterial thermally sensitive element that controls the position of a capacitive plate coupled to the input of a low noise MOS amplifier. This approach can achieve the high sensitivity, the low weight, and the low cost necessary for equipment such as helmet mounted IR viewers and IR rifle sights. The pixel design has the following benefits: (1) an order of magnitude improvement in NE(Delta) T due to extremely high sensitivity and low noise, (2) low cost due to 100% silicon IC compatibility, (3) high image quality and increased yield due to ability to do offset and sensitivity corrections on the imager, pixel-by-pixel; (4) no cryogenic cooler and no high vacuum processing; and (5) commercial applications such as law enforcement, home security, and transportation safety. Two designs are presented. One is a 50 micrometer pixel using silicon nitride as the thermal isolation element that can achieve 5 mK NE(Delta) T; the other is a 29 micrometer pixel using silicon carbide that provides much higher thermal isolation and can achieve 10 mK NE(Delta) T.

Binning and filtering: the six-color solution

NASA Astrophysics Data System (ADS)

Ashdown, Ian; Robinson, Shane; Salsbury, Marc

2006-08-01

The use of LED backlighting for LCD displays requires careful binning of red, green, and blue LEDs by dominant wavelength to maintain the color gamuts as specified by NTSC, SMPTE, and EBU/ITU standards. This problem also occurs to a lesser extent with RGB and RGBA assemblies for solid-state lighting, where color gamut consistency is required for color-changing luminaires. In this paper, we propose a "six-color solution," based on Grassman's laws, that does not require color binning, but nevertheless guarantees a fixed color gamut that subsumes the color gamuts of carefully-binned RGB assemblies. A further advantage of this solution is that it solves the problem of peak wavelength shifts with varying junction temperatures. The color gamut can thus remain fixed over the full range of LED intensities and ambient temperatures. A related problem occurs with integrated circuit (IC) colorimeters used for optical feedback with LED backlighting and RGB(A) solid-state lighting, wherein it can be difficult to distinguish between peak wavelength shifts and changes in LED intensity. We apply our six-color solution to the design of a novel colorimeter for LEDs that independently measures changes in peak wavelength and intensity. The design is compatible with current manufacturing techniques for tristimulus colorimeter ICs. Together, the six-color solution for LEDs and colorimeters enables less expensive LED backlighting and solid-state lighting systems with improved color stability.

Development of Equivalent Material Properties of Microbump for Simulating Chip Stacking Packaging

PubMed Central

Lee, Chang-Chun; Tzeng, Tzai-Liang; Huang, Pei-Chen

2015-01-01

A three-dimensional integrated circuit (3D-IC) structure with a significant scale mismatch causes difficulty in analytic model construction. This paper proposes a simulation technique to introduce an equivalent material composed of microbumps and their surrounding wafer level underfill (WLUF). The mechanical properties of this equivalent material, including Young’s modulus (E), Poisson’s ratio, shear modulus, and coefficient of thermal expansion (CTE), are directly obtained by applying either a tensile load or a constant displacement, and by increasing the temperature during simulations, respectively. Analytic results indicate that at least eight microbumps at the outermost region of the chip stacking structure need to be considered as an accurate stress/strain contour in the concerned region. In addition, a factorial experimental design with analysis of variance is proposed to optimize chip stacking structure reliability with four factors: chip thickness, substrate thickness, CTE, and E-value. Analytic results show that the most significant factor is CTE of WLUF. This factor affects microbump reliability and structural warpage under a temperature cycling load and high-temperature bonding process. WLUF with low CTE and high E-value are recommended to enhance the assembly reliability of the 3D-IC architecture. PMID:28793495

Advanced Data Acquisition Systems

NASA Technical Reports Server (NTRS)

Perotti, J.

2003-01-01

Current and future requirements of the aerospace sensors and transducers field make it necessary for the design and development of new data acquisition devices and instrumentation systems. New designs are sought to incorporate self-health, self-calibrating, self-repair capabilities, allowing greater measurement reliability and extended calibration cycles. With the addition of power management schemes, state-of-the-art data acquisition systems allow data to be processed and presented to the users with increased efficiency and accuracy. The design architecture presented in this paper displays an innovative approach to data acquisition systems. The design incorporates: electronic health self-check, device/system self-calibration, electronics and function self-repair, failure detection and prediction, and power management (reduced power consumption). These requirements are driven by the aerospace industry need to reduce operations and maintenance costs, to accelerate processing time and to provide reliable hardware with minimum costs. The project's design architecture incorporates some commercially available components identified during the market research investigation like: Field Programmable Gate Arrays (FPGA) Programmable Analog Integrated Circuits (PAC IC) and Field Programmable Analog Arrays (FPAA); Digital Signal Processing (DSP) electronic/system control and investigation of specific characteristics found in technologies like: Electronic Component Mean Time Between Failure (MTBF); and Radiation Hardened Component Availability. There are three main sections discussed in the design architecture presented in this document. They are the following: (a) Analog Signal Module Section, (b) Digital Signal/Control Module Section and (c) Power Management Module Section. These sections are discussed in detail in the following pages. This approach to data acquisition systems has resulted in the assignment of patent rights to Kennedy Space Center under U.S. patent # 6,462,684. Furthermore, NASA KSC commercialization office has issued licensing rights to Circuit Avenue Netrepreneurs, LLC , a minority-owned business founded in 1999 located in Camden, NJ.

Oxygen ion-beam microlithography

DOEpatents

Tsuo, Y.S.

1991-08-20

A method of providing and developing a resist on a substrate for constructing integrated circuit (IC) chips includes the following steps: of depositing a thin film of amorphous silicon or hydrogenated amorphous silicon on the substrate and exposing portions of the amorphous silicon to low-energy oxygen ion beams to oxidize the amorphous silicon at those selected portions. The nonoxidized portions are then removed by etching with RF-excited hydrogen plasma. Components of the IC chip can then be constructed through the removed portions of the resist. The entire process can be performed in an in-line vacuum production system having several vacuum chambers. Nitrogen or carbon ion beams can also be used. 5 figures.

Solar cell and I.C. aspects of ingot-to-slice mechanical processing

NASA Astrophysics Data System (ADS)

Dyer, L. D.

1985-08-01

Intensive efforts have been put into the growth of silicon crystals to suit today's solar cell and integrated circuit requirements. Each step of processing the crystal must also receive concentrated attention to preserve the grown-in perfection and to provide a suitable device-ready wafer at reasonable cost. A comparison is made between solar cell and I.C. requirements on the mechanical processing of silicon from ingot to wafer. Specific defects are described that can ruin the slice or can possibly lead to device degradation. These include grinding cracks, saw exit chips, crow's-foot fractures, edge cracks, and handling scratches.

Solar cell and I.C. aspects of ingot-to-slice mechanical processing

NASA Technical Reports Server (NTRS)

Dyer, L. D.

1985-01-01

Intensive efforts have been put into the growth of silicon crystals to suit today's solar cell and integrated circuit requirements. Each step of processing the crystal must also receive concentrated attention to preserve the grown-in perfection and to provide a suitable device-ready wafer at reasonable cost. A comparison is made between solar cell and I.C. requirements on the mechanical processing of silicon from ingot to wafer. Specific defects are described that can ruin the slice or can possibly lead to device degradation. These include grinding cracks, saw exit chips, crow's-foot fractures, edge cracks, and handling scratches.

Oxygen ion-beam microlithography

DOEpatents

Tsuo, Y. Simon

1991-01-01

A method of providing and developing a resist on a substrate for constructing integrated circuit (IC) chips includes the following steps: of depositing a thin film of amorphous silicon or hydrogenated amorphous silicon on the substrate and exposing portions of the amorphous silicon to low-energy oxygen ion beams to oxidize the amorphous silicon at those selected portions. The nonoxidized portions are then removed by etching with RF-excited hydrogen plasma. Components of the IC chip can then be constructed through the removed portions of the resist. The entire process can be performed in an in-line vacuum production system having several vacuum chambers. Nitrogen or carbon ion beams can also be used.

Dielectric Spectroscopic Detection of Early Failures in 3-D Integrated Circuits.

PubMed

Obeng, Yaw; Okoro, C A; Ahn, Jung-Joon; You, Lin; Kopanski, Joseph J

The commercial introduction of three dimensional integrated circuits (3D-ICs) has been hindered by reliability challenges, such as stress related failures, resistivity changes, and unexplained early failures. In this paper, we discuss a new RF-based metrology, based on dielectric spectroscopy, for detecting and characterizing electrically active defects in fully integrated 3D devices. These defects are traceable to the chemistry of the insolation dielectrics used in the through silicon via (TSV) construction. We show that these defects may be responsible for some of the unexplained early reliability failures observed in TSV enabled 3D devices.

Christmas Light Display

NASA Astrophysics Data System (ADS)

Ross, Arthur; Renfro, Timothy

2012-03-01

The Digital Electronics class at McMurry University created a Christmas light display that toggles the power of different strands of lights, according to what frequencies are played in a song, as an example of an analog to digital circuit. This was accomplished using a BA3830S IC six-band audio filter and six solid-state relays.

An Electrifying Quiz! Constructing a Printed-Circuit Board Quiz Game

ERIC Educational Resources Information Center

Calhoun, Michael J.

2005-01-01

Laptop computers, cell phones and the Apple iPod all contain transistors, IC chips, capacitors, and other electronic components. To the general public--and especially students in upper elementary and middle school grades--these components are most often very mysterious items. Yet, it is at elementary and middle school levels that scientists and…

Microwave evaluation of electromigration susceptibility in advanced interconnects

NASA Astrophysics Data System (ADS)

Sunday, Christopher E.; Veksler, Dmitry; Cheung, Kin C.; Obeng, Yaw S.

2017-11-01

Traditional metrology has been unable to adequately address the needs of the emerging integrated circuits (ICs) at the nano scale; thus, new metrology and techniques are needed. For example, the reliability challenges in fabrication need to be well understood and controlled to facilitate mass production of through-substrate-via (TSV) enabled three-dimensional integrated circuits (3D-ICs). This requires new approaches to the metrology. In this paper, we use the microwave propagation characteristics to study the reliability issues that precede the physical damage caused by electromigration in the Cu-filled TSVs. The pre-failure microwave insertion losses and group delay are dependent on both the device temperature and the amount of current forced through the devices-under-test. The microwave insertion losses increase with the increase in the test temperature, while the group delay increases with the increase in the forced direct current magnitude. The microwave insertion losses are attributed to the defect mobility at the Cu-TiN interface, and the group delay changes are due to resistive heating in the interconnects, which perturbs the dielectric properties of the cladding dielectrics of the copper fill in the TSVs.

A low-power RFID integrated circuits for intelligent healthcare systems.

PubMed

Lee, Shuenn-Yuh; Wang, Liang-Hung; Fang, Qiang

2010-11-01

This paper presents low-power radio-frequency identification (RFID) technology for intelligent healthcare systems. With attention to power-efficient communication in the body sensor network, RF power transfer was estimated and the required low-power ICs, which are important in the development of a healthcare system with miniaturization and system integration, are discussed based on the RFID platform. To analyze the power transformation, this paper adopts a 915-MHz industrial, scientific, and medical RF with a radiation power of 70 mW to estimate the power loss under the 1-m communication distance between an RFID reader (bioinformation node) and a transponder (biosignal acquisition nodes). The low-power ICs of the transponder will be implemented in the TSMC 0.18-μm CMOS process. The simulation result reveals that the transponder's IC can fit in with the link budget of the UHF RFID system.

Realization of MEMS-IC Vertical Integration Utilizing Smart Bumpless Bonding

NASA Astrophysics Data System (ADS)

Shiozaki, Masayoshi; Moriguchi, Makoto; Sasaki, Sho; Oba, Masatoshi

This paper reports fundamental technologies, properties, and new experimental results of SBB (Smart Bumpless Bonding) to realize MEMS-IC vertical integration. Although conventional bonding technologies have had difficulties integrating MEMS and its processing circuit because of their rough bonding surfaces, fragile structures, and thermal restriction, SBB technology realized the vertical integration without thermal treatment, any adhesive materials including bumps, and chemical mechanical polishing. The SBB technology bonds sealing parts for vacuum sealing and electrodes for electrical connection simultaneously as published in previous experimental study. The plasma CVD SiO2 is utilized to realize vacuum sealing as sealing material. And Au projection studs are formed on each electrode and connected electrically between two wafers by compressive plastic deformation and surface activation. In this paper, new experimental results including vacuum sealing properties, electrical improvement, IC bonding results on the described fundamental concept and properties are reported.

Logic Gates Made of N-Channel JFETs and Epitaxial Resistors

NASA Technical Reports Server (NTRS)

Krasowski, Michael J.

2008-01-01

Prototype logic gates made of n-channel junction field-effect transistors (JFETs) and epitaxial resistors have been demonstrated, with a view toward eventual implementation of digital logic devices and systems in silicon carbide (SiC) integrated circuits (ICs). This development is intended to exploit the inherent ability of SiC electronic devices to function at temperatures from 300 to somewhat above 500 C and withstand large doses of ionizing radiation. SiC-based digital logic devices and systems could enable operation of sensors and robots in nuclear reactors, in jet engines, near hydrothermal vents, and in other environments that are so hot or radioactive as to cause conventional silicon electronic devices to fail. At present, current needs for digital processing at high temperatures exceed SiC integrated circuit production capabilities, which do not allow for highly integrated circuits. Only single to small number component production of depletion mode n-channel JFETs and epitaxial resistors on a single substrate is possible. As a consequence, the fine matching of components is impossible, resulting in rather large direct-current parameter distributions within a group of transistors typically spanning multiples of 5 to 10. Add to this the lack of p-channel devices to complement the n-channel FETs, the lack of precise dropping diodes, and the lack of enhancement mode devices at these elevated temperatures and the use of conventional direct coupled and buffered direct coupled logic gate design techniques is impossible. The presented logic gate design is tolerant of device parameter distributions and is not hampered by the lack of complementary devices or dropping diodes. In addition to n-channel JFETs, these gates include level-shifting and load resistors (see figure). Instead of relying on precise matching of parameters among individual JFETS, these designs rely on choosing the values of these resistors and of supply potentials so as to make the circuits perform the desired functions throughout the ranges over which the parameters of the JFETs are distributed. The supply rails V(sub dd) and V(sub ss) and the resistors R are chosen as functions of the distribution of direct-current operating parameters of the group of transistors used.

A Novel Hybrid MADM Based Competence Set Expansions of a SOC Design Service Firm

NASA Astrophysics Data System (ADS)

Huang, Chi-Yo; Tzeng, Gwo-Hshiung; Lue, Yeou-Feng; Chuang, Hsiu-Tyan

As the IC (integrated circuit) industry migrates to the System-on-Chip (SOC) era, a novel business model, the SOC design service (DS), is emerging. However, how to expand a firm’s innovation competences while satisfying multiple objectives including highest quality, lowest cost, and fastest time to market as well as most revenues for economics of scale are always problems for a design service firm. Therefore, attempts to expand the innovation competences, and thus the competitiveness, of latecomers in the SOC DS industry have already become the most critical issue facing the top managers of SOC design service firms. In this paper, a novel multiple attribute decision making (MADM) analytic framework based on the concept of competence set expansion, as well as MADM methods consisting with DEMATEL, ANP and multiple objective decision making (MODM) will be proposed in order to define a path for expanding a late-coming SOC DS firm’s innovation capabilities. An empirical study on expanding innovation competence sets, of a late-coming Taiwanese DS firm then will be presented.

Light-controlled biphasic current stimulator IC using CMOS image sensors for high-resolution retinal prosthesis and in vitro experimental results with rd1 mouse.

PubMed

Oh, Sungjin; Ahn, Jae-Hyun; Lee, Sangmin; Ko, Hyoungho; Seo, Jong Mo; Goo, Yong-Sook; Cho, Dong-il Dan

2015-01-01

Retinal prosthetic devices stimulate retinal nerve cells with electrical signals proportional to the incident light intensities. For a high-resolution retinal prosthesis, it is necessary to reduce the size of the stimulator pixels as much as possible, because the retinal nerve cells are concentrated in a small area of approximately 5 mm × 5 mm. In this paper, a miniaturized biphasic current stimulator integrated circuit is developed for subretinal stimulation and tested in vitro. The stimulator pixel is miniaturized by using a complementary metal-oxide-semiconductor (CMOS) image sensor composed of three transistors. Compared to a pixel that uses a four-transistor CMOS image sensor, this new design reduces the pixel size by 8.3%. The pixel size is further reduced by simplifying the stimulation-current generating circuit, which provides a 43.9% size reduction when compared to the design reported to be the most advanced version to date for subretinal stimulation. The proposed design is fabricated using a 0.35 μm bipolar-CMOS-DMOS process. Each pixel is designed to fit in a 50 μ m × 55 μm area, which theoretically allows implementing more than 5000 pixels in the 5 mm × 5 mm area. Experimental results show that a biphasic current in the range of 0 to 300 μA at 12 V can be generated as a function of incident light intensities. Results from in vitro experiments with rd1 mice indicate that the proposed method can be effectively used for retinal prosthesis with a high resolution.

Porous Diblock Copolymer Thin Films in High-Performance Semiconductor Microelectronics

DOE Office of Scientific and Technical Information (OSTI.GOV)

Black, C.T.

2011-02-01

The engine fueling more than 40 years of performance improvements in semiconductor integrated circuits (ICs) has been industry's ability to pattern circuit elements at ever-higher resolution and with ever-greater precision. Steady advances in photolithography - the process wherein ultraviolet light chemically changes a photosensitive polymer resist material in order to create a latent image - have resulted in scaling of minimum printed feature sizes from tens of microns during the 1980s to sub-50 nanometer transistor gate lengths in today's state-of-the-art ICs. The history of semiconductor technology scaling as well as future technology requirements is documented in the International Technology Roadmapmore » for Semiconductors (ITRS). The progression of the semiconductor industry to the realm of nanometer-scale sizes has brought enormous challenges to device and circuit fabrication, rendering performance improvements by conventional scaling alone increasingly difficult. Most often this discussion is couched in terms of field effect transistor (FET) feature sizes such as the gate length or gate oxide thickness, however these challenges extend to many other aspects of the IC, including interconnect dimensions and pitch, device packing density, power consumption, and heat dissipation. The ITRS Technology Roadmap forecasts a difficult set of scientific and engineering challenges with no presently-known solutions. The primary focus of this chapter is the research performed at IBM on diblock copolymer films composed of polystyrene (PS) and poly(methyl-methacrylate) (PMMA) (PS-b-PMMA) with total molecular weights M{sub n} in the range of {approx}60K (g/mol) and polydispersities (PD) of {approx}1.1. These materials self assemble to form patterns having feature sizes in the range of 15-20nm. PS-b-PMMA was selected as a self-assembling patterning material due to its compatibility with the semiconductor microelectronics manufacturing infrastructure, as well as the significant body of existing research on understanding its material properties.« less

An NFC-Enabled CMOS IC for a Wireless Fully Implantable Glucose Sensor.

PubMed

DeHennis, Andrew; Getzlaff, Stefan; Grice, David; Mailand, Marko

2016-01-01

This paper presents an integrated circuit (IC) that merges integrated optical and temperature transducers, optical interface circuitry, and a near-field communication (NFC)-enabled digital, wireless readout for a fully passive implantable sensor platform to measure glucose in people with diabetes. A flip-chip mounted LED and monolithically integrated photodiodes serve as the transduction front-end to enable fluorescence readout. A wide-range programmable transimpedance amplifier adapts the sensor signals to the input of an 11-bit analog-to-digital converter digitizing the measurements. Measurement readout is enabled by means of wireless backscatter modulation to a remote NFC reader. The system is able to resolve current levels of less than 10 pA with a single fluorescent measurement energy consumption of less than 1 μJ. The wireless IC is fabricated in a 0.6-μm-CMOS process and utilizes a 13.56-MHz-based ISO15693 for passive wireless readout through a NFC interface. The IC is utilized as the core interface to a fluorescent, glucose transducer to enable a fully implantable sensor-based continuous glucose monitoring system.

The 30-GHz monolithic receive module

NASA Technical Reports Server (NTRS)

Bauhahn, P.; Geddes, J.; Sokolov, V.; Contolatis, T.

1988-01-01

The fourth year progress is described on a program to develop a 27.5 to 30 GHz GaAs monolithic receive module for spaceborne-communication antenna feed array applications, and to deliver submodules for experimental evaluation. Program goals include an overall receive module noise figure of 5 dB, a 30 dB RF to IF gain with six levels of intermediate gain control, a five bit phase shifter, and a maximum power consumption of 250 mW. Submicron gate length single and dual gate FETs are described and applied in the development of monolithic gain control amplifiers and low noise amplifiers. A two-stage monolithic gain control amplifier based on ion implanted dual gate MESFETs was designed and fabricated. The gain control amplifier has a gain of 12 dB at 29 GHz with a gain control range of over 13 dB. A two-stage monolithic low noise amplifier based on ion implanted MESFETs which provides 7 dB gain with 6.2 dB noise figure at 29 GHz was also developed. An interconnected receive module containing LNA, gain control, and phase shifter submodules was built using the LNA and gain control ICs as well as a monolithic phase shifter developed previously under this program. The design, fabrication, and evaluation of this interconnected receiver is presented. Progress in the development of an RF/IF submodule containing a unique ion implanted diode mixer diode and a broadband balanced mixer monolithic IC with on-chip IF amplifier and the initial design of circuits for the RF portion of a two submodule receiver are also discussed.

Study of complete interconnect reliability for a GaAs MMIC power amplifier

NASA Astrophysics Data System (ADS)

Lin, Qian; Wu, Haifeng; Chen, Shan-ji; Jia, Guoqing; Jiang, Wei; Chen, Chao

2018-05-01

By combining the finite element analysis (FEA) and artificial neural network (ANN) technique, the complete prediction of interconnect reliability for a monolithic microwave integrated circuit (MMIC) power amplifier (PA) at the both of direct current (DC) and alternating current (AC) operation conditions is achieved effectively in this article. As a example, a MMIC PA is modelled to study the electromigration failure of interconnect. This is the first time to study the interconnect reliability for an MMIC PA at the conditions of DC and AC operation simultaneously. By training the data from FEA, a high accuracy ANN model for PA reliability is constructed. Then, basing on the reliability database which is obtained from the ANN model, it can give important guidance for improving the reliability design for IC.

Architecture and implementation considerations of a high-speed Viterbi decoder for a Reed-Muller subcode

NASA Technical Reports Server (NTRS)

Lin, Shu (Principal Investigator); Uehara, Gregory T.; Nakamura, Eric; Chu, Cecilia W. P.

1996-01-01

The (64, 40, 8) subcode of the third-order Reed-Muller (RM) code for high-speed satellite communications is proposed. The RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. The progress made toward achieving the goal of implementing a decoder system based upon this code is summarized. The development of the integrated circuit prototype sub-trellis IC, particularly focusing on the design methodology, is addressed.

PDSOI and Radiation Effects: An Overview

NASA Technical Reports Server (NTRS)

Forgione, Joshua B.

2005-01-01

Bulk silicon substrates are a common characteristic of nearly all commercial, Complementary Metal-Oxide-Semiconductor (CMOS), integrated circuits. These devices operate well on Earth, but are not so well received in the space environment. An alternative to bulk CMOS is the Silicon-On-Insulator (SOI), in which a &electric isolates the device layer from the substrate. SO1 behavior in the space environment has certain inherent advantages over bulk, a primary factor in its long-time appeal to space-flight IC designers. The discussion will investigate the behavior of the Partially-Depleted SO1 (PDSOI) device with respect to some of the more common space radiation effects: Total Ionized Dose (TID), Single-Event Upsets (SEUs), and Single-Event Latchup (SEL). Test and simulation results from the literature, bulk and epitaxial comparisons facilitate reinforcement of PDSOI radiation characteristics.

Integrated Circuit Wear out Prediction and Recycling Detection using Radio Frequency Distinct Native Attribute Features

DTIC Science & Technology

2016-12-22

105 A.1 Main Loop ... loop monitoring for preventative maintenance rather than early replacement based on statistical projections or replacement-after- failure schemes. IC...estimates, RF-DNA may provide a means to track an IC’s physical degradation during actual use. Monitoring an IC’s degradation in a closed loop fashion

A new physical unclonable function architecture

NASA Astrophysics Data System (ADS)

Chuang, Bai; Xuecheng, Zou; Kui, Dai

2015-03-01

This paper describes a new silicon physical unclonable function (PUF) architecture that can be fabricated on a standard CMOS process. Our proposed architecture is built using process sensors, difference amplifier, comparator, voting mechanism and diffusion algorithm circuit. Multiple identical process sensors are fabricated on the same chip. Due to manufacturing process variations, each sensor produces slightly different physical characteristic values that can be compared in order to create a digital identification for the chip. The diffusion algorithm circuit ensures further that the PUF based on the proposed architecture is able to effectively identify a population of ICs. We also improve the stability of PUF design with respect to temporary environmental variations like temperature and supply voltage with the introduction of difference amplifier and voting mechanism. The PUF built on the proposed architecture is fabricated in 0.18 μm CMOS technology. Experimental results show that the PUF has a good output statistical characteristic of uniform distribution and a high stability of 98.1% with respect to temperature variation from -40 to 100 °C, and supply voltage variation from 1.7 to 1.9 V. Project supported by the National Natural Science Foundation of China (No. 61376031).

RF to millimeter wave integration and module technologies

NASA Astrophysics Data System (ADS)

Vähä-Heikkilä, T.

2015-04-01

Radio Frequency (RF) consumer applications have boosted silicon integrated circuits (IC) and corresponding technologies. More and more functions are integrated to ICs and their performance is also increasing. However, RF front-end modules with filters and switches as well as antennas still need other way of integration. This paper focuses to RF front-end module and antenna developments as well as to the integration of millimeter wave radios. VTT Technical Research Centre of Finland has developed both Low Temperature Co-fired Ceramics (LTCC) and Integrated Passive Devices (IPD) integration platforms for RF and millimeter wave integrated modules. In addition to in-house technologies, VTT is using module and component technologies from other commercial sources.

Off-line, built-in test techniques for VLSI circuits

NASA Technical Reports Server (NTRS)

Buehler, M. G.; Sievers, M. W.

1982-01-01

It is shown that the use of redundant on-chip circuitry improves the testability of an entire VLSI circuit. In the study described here, five techniques applied to a two-bit ripple carry adder are compared. The techniques considered are self-oscillation, self-comparison, partition, scan path, and built-in logic block observer. It is noted that both classical stuck-at faults and nonclassical faults, such as bridging faults (shorts), stuck-on x faults where x may be 0, 1, or vary between the two, and parasitic flip-flop faults occur in IC structures. To simplify the analysis of the testing techniques, however, a stuck-at fault model is assumed.

Faraday Cup Array Integrated with a Readout IC and Method for Manufacture Thereof

NASA Technical Reports Server (NTRS)

Temple, Dorota (Inventor); Bower, Christopher A. (Inventor); Hedgepath Gilchrist, Kristin (Inventor); Stoner, Brian R. (Inventor)

2014-01-01

A detector array and method for making the detector array. The array includes a substrate including a plurality of trenches formed therein, and includes a plurality of collectors electrically isolated from each other, formed on the walls of the trenches, and configured to collect charge particles incident on respective ones of the collectors and to output from said collectors signals indicative of charged particle collection. The array includes a plurality of readout circuits disposed on a side of the substrate opposite openings to the collectors. The readout circuits are configured to read charge collection signals from respective ones of the plurality of collectors.

Incentive memory: evidence the basolateral amygdala encodes and the insular cortex retrieves outcome values to guide choice between goal-directed actions.

PubMed

Parkes, Shauna L; Balleine, Bernard W

2013-05-15

Choice between goal-directed actions is determined by the relative value of their consequences. Such values are encoded during incentive learning and later retrieved to guide performance. Although the basolateral amygdala (BLA) and the gustatory region of insular cortex (IC) have been implicated in these processes, their relative contribution is still a matter of debate. Here we assessed whether these structures interact during incentive learning and retrieval to guide choice. In these experiments, rats were trained on two actions for distinct outcomes after which one of the two outcomes was devalued by specific satiety immediately before a choice extinction test. We first confirmed that, relative to appropriate controls, outcome devaluation recruited both the BLA and IC based on activation of the immediate early gene Arc; however, we found that infusion of the NMDAr antagonist ifenprodil into the BLA only abolished outcome devaluation when given before devaluation. In contrast, ifenprodil infusion into the IC was effective whether made before devaluation or test. We hypothesized that the BLA encodes and the IC retrieves incentive value for choice and, to test this, developed a novel sequential disconnection procedure. Blocking NMDAr activation unilaterally in the BLA before devaluation and then contralaterally in the IC before test abolished selective devaluation. In contrast, reversing the order of these infusions left devaluation intact. These results confirm that the BLA and IC form a circuit mediating the encoding and retrieval of outcome values, with the BLA encoding and the IC retrieving such values to guide choice.

Characterization of 6H-SiC JFET Integrated Circuits Over A Broad Temperature Range from -150 C to +500 C

NASA Technical Reports Server (NTRS)

Neudeck, Philip G.; Krasowski, Michael J.; Chen, Liang-Yu; Prokop, Norman F.

2009-01-01

The NASA Glenn Research Center has previously reported prolonged stable operation of simple prototype 6H-SiC JFET integrated circuits (logic gates and amplifier stages) for thousands of hours at +500 C. This paper experimentally investigates the ability of these 6H-SiC JFET devices and integrated circuits to also function at cold temperatures expected to arise in some envisioned applications. Prototype logic gate ICs experimentally demonstrated good functionality down to -125 C without changing circuit input voltages. Cascaded operation of gates at cold temperatures was verified by externally wiring gates together to form a 3-stage ring oscillator. While logic gate output voltages exhibited little change across the broad temperature range from -125 C to +500 C, the change in operating frequency and power consumption of these non-optimized logic gates as a function of temperature was much larger and tracked JFET channel conduction properties.

Minimally-Invasive Neural Interface for Distributed Wireless Electrocorticogram Recording Systems

PubMed Central

Chang, Sun-Il

2018-01-01

This paper presents a minimally-invasive neural interface for distributed wireless electrocorticogram (ECoG) recording systems. The proposed interface equips all necessary components for ECoG recording, such as the high performance front-end integrated circuits, a fabricated flexible microelectrode array, and wireless communication inside a miniaturized custom-made platform. The multiple units of the interface systems can be deployed to cover a broad range of the target brain region and transmit signals via a built-in intra-skin communication (ISCOM) module. The core integrated circuit (IC) consists of 16-channel, low-power push-pull double-gated preamplifiers, in-channel successive approximation register analog-to-digital converters (SAR ADC) with a single-clocked bootstrapping switch and a time-delayed control unit, an ISCOM module for wireless data transfer through the skin instead of a power-hungry RF wireless transmitter, and a monolithic voltage/current reference generator to support the aforementioned analog and mixed-signal circuit blocks. The IC was fabricated using 250 nm CMOS processes in an area of 3.2 × 0.9 mm2 and achieved the low-power operation of 2.5 µW per channel. Input-referred noise was measured as 5.62 µVrms for 10 Hz to 10 kHz and ENOB of 7.21 at 31.25 kS/s. The implemented system successfully recorded multi-channel neural activities in vivo from a primate and demonstrated modular expandability using the ISCOM with power consumption of 160 µW. PMID:29342103

Minimally-Invasive Neural Interface for Distributed Wireless Electrocorticogram Recording Systems.

PubMed

Chang, Sun-Il; Park, Sung-Yun; Yoon, Euisik

2018-01-17

This paper presents a minimally-invasive neural interface for distributed wireless electrocorticogram (ECoG) recording systems. The proposed interface equips all necessary components for ECoG recording, such as the high performance front-end integrated circuits, a fabricated flexible microelectrode array, and wireless communication inside a miniaturized custom-made platform. The multiple units of the interface systems can be deployed to cover a broad range of the target brain region and transmit signals via a built-in intra-skin communication (ISCOM) module. The core integrated circuit (IC) consists of 16-channel, low-power push-pull double-gated preamplifiers, in-channel successive approximation register analog-to-digital converters (SAR ADC) with a single-clocked bootstrapping switch and a time-delayed control unit, an ISCOM module for wireless data transfer through the skin instead of a power-hungry RF wireless transmitter, and a monolithic voltage/current reference generator to support the aforementioned analog and mixed-signal circuit blocks. The IC was fabricated using 250 nm CMOS processes in an area of 3.2 × 0.9 mm² and achieved the low-power operation of 2.5 µW per channel. Input-referred noise was measured as 5.62 µV rms for 10 Hz to 10 kHz and ENOB of 7.21 at 31.25 kS/s. The implemented system successfully recorded multi-channel neural activities in vivo from a primate and demonstrated modular expandability using the ISCOM with power consumption of 160 µW.

Forward-Looking Intracardiac Ultrasound Imaging Using a 1-D CMUT Array Integrated With Custom Front-End Electronics

PubMed Central

Nikoozadeh, Amin; Wygant, Ira O.; Lin, Der-Song; Oralkan, Ömer; Ergun, A. Sanlı; Stephens, Douglas N.; Thomenius, Kai E.; Dentinger, Aaron M.; Wildes, Douglas; Akopyan, Gina; Shivkumar, Kalyanam; Mahajan, Aman; Sahn, David J.; Khuri-Yakub, Butrus T.

2009-01-01

Minimally invasive catheter-based electrophysiological (EP) interventions are becoming a standard procedure in diagnosis and treatment of cardiac arrhythmias. As a result of technological advances that enable small feature sizes and a high level of integration, nonfluoroscopic intracardiac echocardiography (ICE) imaging catheters are attracting increasing attention. ICE catheters improve EP procedural guidance while reducing the undesirable use of fluoroscopy, which is currently the common catheter guidance method. Phased-array ICE catheters have been in use for several years now, although only for side-looking imaging. We are developing a forward-looking ICE catheter for improved visualization. In this effort, we fabricate a 24-element, fine-pitch 1-D array of capacitive micromachined ultrasonic transducers (CMUT), with a total footprint of 1.73 mm × 1.27 mm. We also design a custom integrated circuit (IC) composed of 24 identical blocks of transmit/receive circuitry, measuring 2.1 mm × 2.1 mm. The transmit circuitry is capable of delivering 25-V unipolar pulses, and the receive circuitry includes a transimpedance preamplifier followed by an output buffer. The CMUT array and the custom IC are designed to be mounted at the tip of a 10-Fr catheter for high-frame-rate forward-looking intracardiac imaging. Through-wafer vias incorporated in the CMUT array provide access to individual array elements from the back side of the array. We successfully flip-chip bond a CMUT array to the custom IC with 100% yield. We coat the device with a layer of polydimethylsiloxane (PDMS) to electrically isolate the device for imaging in water and tissue. The pulse-echo in water from a total plane reflector has a center frequency of 9.2 MHz with a 96% fractional bandwidth. Finally, we demonstrate the imaging capability of the integrated device on commercial phantoms and on a beating ex vivo rabbit heart (Langendorff model) using a commercial ultrasound imaging system. PMID:19126489

AIN-Based Packaging for SiC High-Temperature Electronics

NASA Technical Reports Server (NTRS)

Savrun, Ender

2004-01-01

Packaging made primarily of aluminum nitride has been developed to enclose silicon carbide-based integrated circuits (ICs), including circuits containing SiC-based power diodes, that are capable of operation under conditions more severe than can be withstood by silicon-based integrated circuits. A major objective of this development was to enable packaged SiC electronic circuits to operate continuously at temperatures up to 500 C. AlN-packaged SiC electronic circuits have commercial potential for incorporation into high-power electronic equipment and into sensors that must withstand high temperatures and/or high pressures in diverse applications that include exploration in outer space, well logging, and monitoring of nuclear power systems. This packaging embodies concepts drawn from flip-chip packaging of silicon-based integrated circuits. One or more SiC-based circuit chips are mounted on an aluminum nitride package substrate or sandwiched between two such substrates. Intimate electrical connections between metal conductors on the chip(s) and the metal conductors on external circuits are made by direct bonding to interconnections on the package substrate(s) and/or by use of holes through the package substrate(s). This approach eliminates the need for wire bonds, which have been the most vulnerable links in conventional electronic circuitry in hostile environments. Moreover, the elimination of wire bonds makes it possible to pack chips more densely than was previously possible.

One-power IC with MPPT design

NASA Astrophysics Data System (ADS)

Xu, Shengzhi; Chu, Ian; Zhao, Gengshen; Wang, Qingzhang

2008-03-01

When proceed photovoltaic power system design, engineer needs prepared model of PV cells to evaluate system response, capability performance, and stability, the DC model is not enough, but an accuracy AC model plays a big role. This paper talks first about the AC model of PV cells, and DC model is also introduced in simple. There is a PV controller example explaining the steps to do system simulation in this paper. Two equivalent circuit models are implemented with mixed-signal language verilog-a, one hardware language easy to use and having good speed and high accuracy. Both of two models include solar cell arrays, one buck switched mode DC-DC converter, and the maximum power point tracking algorithm. The difference between them is that Solar cell in one of two models is with ac small signal parameter, another is without. The simulation result is given in comparison. This paper's work shows that ac parameter plays large role in switch-mode PV power system, especially when the switch frequency is higher than 100kHz.

Possibilities for mixed mode chip manufacturing in EUROPRACTICE

NASA Astrophysics Data System (ADS)

Das, C.

1997-02-01

EUROPRACTICE is an EC initiative under the ESPRIT programme which aims to stimulate the wider exploitation of state-of-the-art microelectronics technologies by European industry and to enhance European industrial competitiveness in the global market-place. Through EUROPRACTICE, the EC has created a range of Basic Services that offer users a cost-effective and flexible means of accessing three main microelectronics-based technologies: Application Specific Integrated Circuit (ASICs), Multi-Chip Modules (MCMs) and Microsystems. EUROPRACTICE Basic Services reduce the cost and risk for companies wishing to begin using these technologies. EUROPRACTICE offers a fully supported, low cost route for companies to design and fabricate ASICs for their individual applications. Low cost is achieved by consolidating designs from many users onto a single semiconductor wafer (MPW: Multi Project Wafer). The EUROPRACTICE IC Manufacturing Service (ICMS) offers a broad range of fabrication technologies including CMOS, BiCMOS and GaAs. The Service extends from enabling users to produce prototype ASICs for testing and evaluation, through to low-volume production runs.

Yield modeling of acoustic charge transport transversal filters

NASA Technical Reports Server (NTRS)

Kenney, J. S.; May, G. S.; Hunt, W. D.

1995-01-01

This paper presents a yield model for acoustic charge transport transversal filters. This model differs from previous IC yield models in that it does not assume that individual failures of the nondestructive sensing taps necessarily cause a device failure. A redundancy in the number of taps included in the design is explained. Poisson statistics are used to describe the tap failures, weighted over a uniform defect density distribution. A representative design example is presented. The minimum number of taps needed to realize the filter is calculated, and tap weights for various numbers of redundant taps are calculated. The critical area for device failure is calculated for each level of redundancy. Yield is predicted for a range of defect densities and redundancies. To verify the model, a Monte Carlo simulation is performed on an equivalent circuit model of the device. The results of the yield model are then compared to the Monte Carlo simulation. Better than 95% agreement was obtained for the Poisson model with redundant taps ranging from 30% to 150% over the minimum.

Critical role of domain crystallinity, domain purity and domain interface sharpness for reduced bimolecular recombination in polymer solar cells

DOE PAGES

Venkatesan, Swaminathan; Chen, Jihua; Ngo, Evan C.; ...

2014-12-31

In this study, inverted bulk heterojunction solar cells were fabricated using poly(3-hexylthiophene) (P3HT) blended with two different fullerene derivatives namely phenyl-C61-butyric acid methyl ester (PC 60BM) and indene-C 60 bis-adduct (IC 60BA). The effects of annealing temperatures on the morphology, optical and structural properties were studied and correlated to differences in photovoltaic device performance. It was observed that annealing temperature significantly improved the performance of P3HT:IC 60BA solar cells while P3HT:PC 60BM cells showed relatively less improvement. The performance improvement is attributed to the extent of fullerene mixing with polymer domains. Energy filtered transmission electron microscopy (EFTEM) and x-ray diffractionmore » (XRD) results showed that ICBA mixes with disordered P3HT much more readily than PC 60BM which leads to lower short circuit current density and fill factor for P3HT:IC 60BA cells annealed below 120°C. Annealing above 120°C improves the crystallinity of P3HT in case of P3HT:IC 60BA whereas in P3HT:PC 60BM films, annealing above 80°C leads to negligible change in crystallinity. Crystallization of P3HT also leads to higher domain purity as seen EFTEM. Further it is seen that cells processed with additive nitrobenzene (NB) showed enhanced short circuit current density and power conversion efficiency regardless of the fullerene derivative used. Addition of NB led to nanoscale phase separation between purer polymer and fullerene domains. Kelvin probe force microscopy (KPFM) images showed that enhanced domain purity in additive casted films led to a sharper interface between polymer and fullerene. Lastly, enhanced domain purity and interfacial sharpness led to lower bimolecular recombination and higher mobility and charge carrier lifetime in NB modified devices.« less

PROGRESS IN DESIGN OF THE INSTRUMENTATION AND CONTROL OF THE TOKAMAK COOLING WATER SYSTEM

DOE Office of Scientific and Technical Information (OSTI.GOV)

Korsah, Kofi; DeVan, Bill; Ashburn, David

This paper discusses progress in the design of the control, interlock and safety systems of the Tokamak Cooling Water System (TCWS) for the ITER fusion reactor. The TCWS instrumentation and control (I&C) is one of approximately 200 separate plant I&C systems (e.g., vacuum system I&C, magnets system I&C) that interface to a common central I&C system through standardized networks. Several aspects of the I&C are similar to the I&C of fission-based power plants. However, some of the unique features of the ITER fusion reactor and the TCWS (e.g., high quasi-static magnetic field, need for baking and drying as well asmore » cooling operations), also demand some unique safety and qualification considerations. The paper compares the design strategy/guidelines of the TCWS I&C and the I&C of conventional nuclear power plants. Issues such as safety classifications, independence between control and safety systems, sensor sharing, redundancy, voting schemes, and qualification methodologies are discussed. It is concluded that independence and separation requirements are similar in both designs. However, the voting schemes for safety systems in nuclear power plants typically use 2oo4 (i.e., 4 divisions of safety I&C, any 2 of which is sufficient to trigger a safety action), while 2oo3 voting logic - within each of 2 independent trains - is used in the TCWS I&C. It is also noted that 2oo3 voting is also acceptable in nuclear power plants if adequate risk assessment and reliability is demonstrated. Finally, while qualification requirements provide similar guidance [e.g., both IEC 60780 (invoked in ITER-space), and IEEE 323 (invoked in fission power plant space) provide similar guidance], an important qualification consideration is the susceptibility of I&C to the magnetic fields of ITER. Also, the radiation environments are different. In the case of magnetic fields the paper discusses some options that are being considered.« less

High Voltage Dielectrophoretic and Magnetophoretic Hybrid Integrated Circuit / Microfluidic Chip

PubMed Central

Issadore, David; Franke, Thomas; Brown, Keith A.; Hunt, Thomas P.; Westervelt, Robert M.

2010-01-01

A hybrid integrated circuit (IC) / microfluidic chip is presented that independently and simultaneously traps and moves microscopic objects suspended in fluid using both electric and magnetic fields. This hybrid chip controls the location of dielectric objects, such as living cells and drops of fluid, on a 60 × 61 array of pixels that are 30 × 38 μm2 in size, each of which can be individually addressed with a 50 V peak-to-peak, DC to 10 MHz radio frequency voltage. These high voltage pixels produce electric fields above the chip’s surface with a magnitude , resulting in strong dielectrophoresis (DEP) forces . Underneath the array of DEP pixels there is a magnetic matrix that consists of two perpendicular sets of 60 metal wires running across the chip. Each wire can be sourced with 120 mA to trap and move magnetically susceptible objects using magnetophoresis (MP). The DEP pixel array and magnetic matrix can be used simultaneously to apply forces to microscopic objects, such as living cells or lipid vesicles, that are tagged with magnetic nanoparticles. The capabilities of the hybrid IC / microfluidic chip demonstrated in this paper provide important building blocks for a platform for biological and chemical applications. PMID:20625468

High Voltage Dielectrophoretic and Magnetophoretic Hybrid Integrated Circuit / Microfluidic Chip.

PubMed

Issadore, David; Franke, Thomas; Brown, Keith A; Hunt, Thomas P; Westervelt, Robert M

2009-12-01

A hybrid integrated circuit (IC) / microfluidic chip is presented that independently and simultaneously traps and moves microscopic objects suspended in fluid using both electric and magnetic fields. This hybrid chip controls the location of dielectric objects, such as living cells and drops of fluid, on a 60 × 61 array of pixels that are 30 × 38 μm(2) in size, each of which can be individually addressed with a 50 V peak-to-peak, DC to 10 MHz radio frequency voltage. These high voltage pixels produce electric fields above the chip's surface with a magnitude , resulting in strong dielectrophoresis (DEP) forces . Underneath the array of DEP pixels there is a magnetic matrix that consists of two perpendicular sets of 60 metal wires running across the chip. Each wire can be sourced with 120 mA to trap and move magnetically susceptible objects using magnetophoresis (MP). The DEP pixel array and magnetic matrix can be used simultaneously to apply forces to microscopic objects, such as living cells or lipid vesicles, that are tagged with magnetic nanoparticles. The capabilities of the hybrid IC / microfluidic chip demonstrated in this paper provide important building blocks for a platform for biological and chemical applications.

Microwave evaluation of electromigration susceptibility in advanced interconnects.

PubMed

Sunday, Christopher E; Veksler, Dmitry; Cheung, Kin C; Obeng, Yaw S

2017-11-07

Traditional metrology has been unable to adequately address the needs of the emerging integrated circuits (ICs) at the nano scale; thus, new metrology and techniques are needed. For example, the reliability challenges in fabrication need to be well understood and controlled to facilitate mass production of through-substrate-via (TSV) enabled three-dimensional integrated circuits (3D-ICs). This requires new approaches to the metrology. In this paper, we use the microwave propagation characteristics to study the reliability issues that precede the physical damage caused by electromigration in the Cu-filled TSVs. The pre-failure microwave insertion losses and group delay are dependent on both the device temperature and the amount of current forced through the devices-under-test. The microwave insertion losses increase with the increase in the test temperature, while the group delay increases with the increase in the forced direct current magnitude. The microwave insertion losses are attributed to the defect mobility at the Cu-TiN interface, and the group delay changes are due to resistive heating in the interconnects, which perturbs the dielectric properties of the cladding dielectrics of the copper fill in the TSVs. https://doi.org/10.1063/1.4992135.

Corrosion of silicon integrated circuits and lifetime predictions in implantable electronic devices.

PubMed

Vanhoestenberghe, A; Donaldson, N

2013-06-01

Corrosion is a prime concern for active implantable devices. In this paper we review the principles underlying the concepts of hermetic packages and encapsulation, used to protect implanted electronics, some of which remain widely overlooked. We discuss how technological advances have created a need to update the way we evaluate the suitability of both protection methods. We demonstrate how lifetime predictability is lost for very small hermetic packages and introduce a single parameter to compare different packages, with an equation to calculate the minimum sensitivity required from a test method to guarantee a given lifetime. In the second part of this paper, we review the literature on the corrosion of encapsulated integrated circuits (ICs) and, following a new analysis of published data, we propose an equation for the pre-corrosion lifetime of implanted ICs, and discuss the influence of the temperature, relative humidity, encapsulation and field-strength. As any new protection will be tested under accelerated conditions, we demonstrate the sensitivity of acceleration factors to some inaccurately known parameters. These results are relevant for any application of electronics working in a moist environment. Our comparison of encapsulation and hermetic packages suggests that both concepts may be suitable for future implants.

An externally head-mounted wireless neural recording device for laboratory animal research and possible human clinical use.

PubMed

Yin, Ming; Li, Hao; Bull, Christopher; Borton, David A; Aceros, Juan; Larson, Lawrence; Nurmikko, Arto V

2013-01-01

In this paper we present a new type of head-mounted wireless neural recording device in a highly compact package, dedicated for untethered laboratory animal research and designed for future mobile human clinical use. The device, which takes its input from an array of intracortical microelectrode arrays (MEA) has ninety-seven broadband parallel neural recording channels and was integrated on to two custom designed printed circuit boards. These house several low power, custom integrated circuits, including a preamplifier ASIC, a controller ASIC, plus two SAR ADCs, a 3-axis accelerometer, a 48MHz clock source, and a Manchester encoder. Another ultralow power RF chip supports an OOK transmitter with the center frequency tunable from 3GHz to 4GHz, mounted on a separate low loss dielectric board together with a 3V LDO, with output fed to a UWB chip antenna. The IC boards were interconnected and packaged in a polyether ether ketone (PEEK) enclosure which is compatible with both animal and human use (e.g. sterilizable). The entire system consumes 17mA from a 1.2Ahr 3.6V Li-SOCl2 1/2AA battery, which operates the device for more than 2 days. The overall system includes a custom RF receiver electronics which are designed to directly interface with any number of commercial (or custom) neural signal processors for multi-channel broadband neural recording. Bench-top measurements and in vivo testing of the device in rhesus macaques are presented to demonstrate the performance of the wireless neural interface.

An Integrated Multilevel Converter with Sigma Delta Control for LED Lighting

NASA Astrophysics Data System (ADS)

Gerber, Daniel L.

High brightness LEDs have become a mainstream lighting technology due to their efficiency, life span, and environmental benefits. As such, the lighting industry values LED drivers with low cost, small form factor, and long life span. Additional specifications that define a high quality LED driver are high efficiency, high power factor, wide-range dimming, minimal flicker, and a galvanically isolated output. The flyback LED driver is a popular topology that satisfies all these specifications, but it requires a bulky and costly flyback transformer. In addition, its passive methods for cancelling AC power ripple require electrolytic capacitors, which have been known to have life span issues. This dissertation details the design, construction, and verification of a novel LED driver that satisfies all the specifications. In addition, it does not require a flyback transformer or electrolytic capacitors, thus marking an improvement over the flyback driver on size, cost, and life span. This dissertation presents an integrated circuit (IC) LED driver, which features a pair of generalized multilevel converters that are controlled via sigma-delta modulation. The first is a multilevel rectifier responsible for power factor correction (PFC) and dimming. The PFC rectifier employs a second order sigma-delta loop to precisely control the input current harmonics and amplitude. The second is a bidirectional multilevel inverter used to cancel AC power ripple from the DC bus. This ripple-cancellation module transfers energy to and from a storage capacitor. It uses a first order sigma-delta loop with a preprogrammed waveform to swing the storage capacitor voltage. The system also contains an output stage that powers the LEDs with DC and provides for galvanic isolation. The output stage consists of an H-bridge stack that connects to the output through a small toroid transformer. The IC LED driver was simulated and prototyped on an ABCD silicon test chip. Testing and verification indicates functional performance for all the modules in the LED driver. The driver exhibits moderate efficiency at half voltage. Although the part was only testable to half voltage, loss models predict that its efficiency would be much higher at full voltage. The driver also meets specifications on the line current harmonics and ripple cancellation. This dissertation introduces multilevel circuit techniques to the IC and LED research space. The prototype's functional performance indicates that integrated multilevel converters are a viable topology for lighting and other similar applications.

Integrated circuits for volumetric ultrasound imaging with 2-D CMUT arrays.

PubMed

Bhuyan, Anshuman; Choe, Jung Woo; Lee, Byung Chul; Wygant, Ira O; Nikoozadeh, Amin; Oralkan, Ömer; Khuri-Yakub, Butrus T

2013-12-01

Real-time volumetric ultrasound imaging systems require transmit and receive circuitry to generate ultrasound beams and process received echo signals. The complexity of building such a system is high due to requirement of the front-end electronics needing to be very close to the transducer. A large number of elements also need to be interfaced to the back-end system and image processing of a large dataset could affect the imaging volume rate. In this work, we present a 3-D imaging system using capacitive micromachined ultrasonic transducer (CMUT) technology that addresses many of the challenges in building such a system. We demonstrate two approaches in integrating the transducer and the front-end electronics. The transducer is a 5-MHz CMUT array with an 8 mm × 8 mm aperture size. The aperture consists of 1024 elements (32 × 32) with an element pitch of 250 μm. An integrated circuit (IC) consists of a transmit beamformer and receive circuitry to improve the noise performance of the overall system. The assembly was interfaced with an FPGA and a back-end system (comprising of a data acquisition system and PC). The FPGA provided the digital I/O signals for the IC and the back-end system was used to process the received RF echo data (from the IC) and reconstruct the volume image using a phased array imaging approach. Imaging experiments were performed using wire and spring targets, a ventricle model and a human prostrate. Real-time volumetric images were captured at 5 volumes per second and are presented in this paper.

A hybrid approach to nanoelectronics

NASA Astrophysics Data System (ADS)

Cerofolini, G. F.; Arena, G.; Camalleri, C. M.; Galati, C.; Reina, S.; Renna, L.; Mascolo, D.

2005-08-01

The definition of features on the nanometre length scale (NLS) is impossible via conventional lithography, but can be done using extreme ultraviolet, synchrotron-radiation, or electron beam lithography. However, since these techniques are very expensive and still in their infancy, their exploitation in integrated circuit (IC) processing is still highly putative. Geometries on the NLS can however be produced with relative ease using the spacer patterning technique, i.e. transforming vertical features (like film thickness) in the vicinity of a step of a sacrificial layer into horizontal features. The ultimate length that can be produced in this way is controlled by the steepness of the step defining the sacrificial layer, the uniformity of the deposited or grown films, and the anisotropy of its etching. While useful for the preparation of a few devices with special needs, the above trick does not allow by itself the development of a nanotechnology where each layer useful for defining the circuit should be on the NLS and aligned on the underlying geometries with tolerances on the NLS. Setting up such a nanotechnology is a major problem which will involve the IC industry in the post-Roadmap era. Irrespective of the detailed structure of the basic constituents (molecules, supramolecular structures, clusters, etc), ICs with nanoscopic active elements can hardly be prepared without the ability to produce arrays of conductive strips with pitch on the NLS. This work is devoted to describing a scheme (essentially based on the existing microelectronic technology) for their production without the use of advanced lithography and how it can be arranged to host molecular devices.

Development and Operation of Dual-Mode Analyzers for Wireless Power Consortium/Power Matters Alliance Wireless Power Systems.

PubMed

Um, Keehong

2016-05-01

We have designed a protocol analyzer to be used in wireless power systems and analyzed the operation of wireless chargers defined by standards of Qi of Wireless Power Consortium (WPC) and Power Matters Alliance (PMA) protocols. The integrated circuit (IC, or microchip) developed so far for wireless power transmission is not easily adopted by chargers for specific purposes. A device for measuring the performance of test equipment currently available is required to transform and expand the types of protocol. Since a protocol analyzer with these functions is required, we have developed a device that can analyze the two protocols of WPC and PMA at the same time. As a result of our research, we present a dual-mode system that can analyze the protocols of both WPC and PMA.

A gallium-arsenide digital phase shifter for clock and control signal distribution in high-speed digital systems

NASA Technical Reports Server (NTRS)

Fouts, Douglas J.

1992-01-01

The design, implementation, testing, and applications of a gallium-arsenide digital phase shifter and fan-out buffer are described. The integrated circuit provides a method for adjusting the phase of high-speed clock and control signals in digital systems, without the need for pruning cables, multiplexing between cables of different lengths, delay lines, or similar techniques. The phase of signals distributed with the described chip can be dynamically adjusted in eight different steps of approximately 60 ps per step. The IC also serves as a fan-out buffer and provides 12 in-phase outputs. The chip is useful for distributing high-speed clock and control signals in synchronous digital systems, especially if components are distributed over a large physical area or if there is a large number of components.

5-Gb/s 0.18-μm CMOS 2:1 multiplexer with integrated clock extraction

NASA Astrophysics Data System (ADS)

Changchun, Zhang; Zhigong, Wang; Si, Shi; Peng, Miao; Ling, Tian

2009-09-01

A 5-Gb/s 2:1 MUX (multiplexer) with an on-chip integrated clock extraction circuit which possesses the function of automatic phase alignment (APA), has been designed and fabricated in SMIC's 0.18 μm CMOS technology. The chip area is 670 × 780 μm2. At a single supply voltage of 1.8 V, the total power consumption is 112 mW with an input sensitivity of less than 50 mV and an output single-ended swing of above 300 mV. The measurement results show that the IC can work reliably at any input data rate between 1.8 and 2.6 Gb/s with no need for external components, reference clock, or phase alignment between data and clock. It can be used in a parallel optic-fiber data interconnecting system.

An analog neural hardware implementation using charge-injection multipliers and neutron-specific gain control.

PubMed

Massengill, L W; Mundie, D B

1992-01-01

A neural network IC based on a dynamic charge injection is described. The hardware design is space and power efficient, and achieves massive parallelism of analog inner products via charge-based multipliers and spatially distributed summing buses. Basic synaptic cells are constructed of exponential pulse-decay modulation (EPDM) dynamic injection multipliers operating sequentially on propagating signal vectors and locally stored analog weights. Individually adjustable gain controls on each neutron reduce the effects of limited weight dynamic range. A hardware simulator/trainer has been developed which incorporates the physical (nonideal) characteristics of actual circuit components into the training process, thus absorbing nonlinearities and parametric deviations into the macroscopic performance of the network. Results show that charge-based techniques may achieve a high degree of neural density and throughput using standard CMOS processes.

Sex Differences in Gamma Band Functional Connectivity Between the Frontal Lobe and Cortical Areas During an Auditory Oddball Task, as Revealed by Imaginary Coherence Assessment.

PubMed

Fujimoto, Toshiro; Okumura, Eiichi; Kodabashi, Atsushi; Takeuchi, Kouzou; Otsubo, Toshiaki; Nakamura, Katsumi; Yatsushiro, Kazutaka; Sekine, Masaki; Kamiya, Shinichiro; Shimooki, Susumu; Tamura, Toshiyo

2016-01-01

We studied sex-related differences in gamma oscillation during an auditory oddball task, using magnetoencephalography and electroencephalography assessment of imaginary coherence (IC). We obtained a statistical source map of event-related desynchronization (ERD) / event-related synchronization (ERS), and compared females and males regarding ERD / ERS. Based on the results, we chose respectively seed regions for IC determinations in low (30-50 Hz), mid (50-100 Hz) and high gamma (100-150 Hz) bands. In males, ERD was increased in the left posterior cingulate cortex (CGp) at 500 ms in the low gamma band, and in the right caudal anterior cingulate cortex (cACC) at 125 ms in the mid-gamma band. ERS was increased in the left rostral anterior cingulate cortex (rACC) at 375 ms in the high gamma band. We chose the CGp, cACC and rACC as seeds, and examined IC between the seed and certain target regions using the IC map. IC changes depended on the height of the gamma frequency and the time window in the gamma band. Although IC in the mid and high gamma bands did not show sex-specific differences, IC at 30-50 Hz in males was increased between the left rACC and the frontal, orbitofrontal, inferior temporal and fusiform target regions. Increased IC in males suggested that males may acomplish the task constructively, analysingly, emotionally, and by perfoming analysis, and that information processing was more complicated in the cortico-cortical circuit. On the other hand, females showed few differences in IC. Females planned the task with general attention and economical well-balanced processing, which was explained by the higher overall functional cortical connectivity. CGp, cACC and rACC were involved in sex differences in information processing and were likely related to differences in neuroanatomy, hormones and neurotransmitter systems.

Gigascale Silicon Photonic Transmitters Integrating HBT-based Carrier-injection Electroabsorption Modulator Structures

NASA Astrophysics Data System (ADS)

Fu, Enjin

Demand for more bandwidth is rapidly increasing, which is driven by data intensive applications such as high-definition (HD) video streaming, cloud storage, and terascale computing applications. Next-generation high-performance computing systems require power efficient chip-to-chip and intra-chip interconnect yielding densities on the order of 1Tbps/cm2. The performance requirements of such system are the driving force behind the development of silicon integrated optical interconnect, providing a cost-effective solution for fully integrated optical interconnect systems on a single substrate. Compared to conventional electrical interconnect, optical interconnects have several advantages, including frequency independent insertion loss resulting in ultra wide bandwidth and link latency reduction. For high-speed optical transmitter modules, the optical modulator is a key component of the optical I/O channel. This thesis presents a silicon integrated optical transmitter module design based on a novel silicon HBT-based carrier injection electroabsorption modulator (EAM), which has the merits of wide optical bandwidth, high speed, low power, low drive voltage, small footprint, and high modulation efficiency. The structure, mechanism, and fabrication of the modulator structure will be discussed which is followed by the electrical modeling of the post-processed modulator device. The design and realization of a 10Gbps monolithic optical transmitter module integrating the driver circuit architecture and the HBT-based EAM device in a 130nm BiCMOS process is discussed. For high power efficiency, a 6Gbps ultra-low power driver IC implemented in a 130nm BiCMOS process is presented. The driver IC incorporates an integrated 27-1 pseudo-random bit sequence (PRBS) generator for reliable high-speed testing, and a driver circuit featuring digitally-tuned pre-emphasis signal strength. With outstanding drive capability, the driver module can be applied to a wide range of carrier injection modulators and light-emitting diodes (LED) with drive voltage requirements below 1.5V. Measurement results show an optical link based on a 70MHz red LED work well at 300Mbps by using the pre-emphasis driver module. A traveling wave electrode (TWE) modulator structure is presented, including a novel design methodology to address process limitations imposed by a commercial silicon fabrication technology. Results from 3D full wave EM simulation demonstrate the application of the design methodology to achieve specifications, including phase velocity matching, insertion loss, and impedance matching. Results show the HBT-based TWE-EAM system has the bandwidth higher than 60GHz.

Superconductive ADC Project Fabrication Package. Final Design Review Package (Briefing Charts)

DTIC Science & Technology

2010-09-07

Simulation Results Iin 1.45mV 2.5Ω 1pH 4pH 100fF 310uA 1fΩ Ic = 300uA Rn = 0.8Ω Cs = 0.32pF Ic = 300uA Rn = 0.8Ω Cs = 0.32pF Iin Vout Vout Ic = 500uA Rn...0.55Ω Cs = 0.32pF ONR Superconductive ADC CLIN/SLIN 0001AD September 2010, Brad Perranoski Pg. 17 Modulator Design Documentation Comparator Design...Comparator Design - Cadence Schematic & Simulation Comparator Testbench Simulation Results 1.45mV 2.5Ω 1pH 4pH 100fF 310uA 1fΩSine wave 100uApk Iin Ic

High performance MPEG-audio decoder IC

NASA Technical Reports Server (NTRS)

Thorn, M.; Benbassat, G.; Cyr, K.; Li, S.; Gill, M.; Kam, D.; Walker, K.; Look, P.; Eldridge, C.; Ng, P.

1993-01-01

The emerging digital audio and video compression technology brings both an opportunity and a new challenge to IC design. The pervasive application of compression technology to consumer electronics will require high volume, low cost IC's and fast time to market of the prototypes and production units. At the same time, the algorithms used in the compression technology result in complex VLSI IC's. The conflicting challenges of algorithm complexity, low cost, and fast time to market have an impact on device architecture and design methodology. The work presented in this paper is about the design of a dedicated, high precision, Motion Picture Expert Group (MPEG) audio decoder.

Millimeter-wave silicon-based ultra-wideband automotive radar transceivers

NASA Astrophysics Data System (ADS)

Jain, Vipul

Since the invention of the integrated circuit, the semiconductor industry has revolutionized the world in ways no one had ever anticipated. With the advent of silicon technologies, consumer electronics became light-weight and affordable and paved the way for an Information-Communication-Entertainment age. While silicon almost completely replaced compound semiconductors from these markets, it has been unable to compete in areas with more stringent requirements due to technology limitations. One of these areas is automotive radar sensors, which will enable next-generation collision-warning systems in automobiles. A low-cost implementation is absolutely essential for widespread use of these systems, which leads us to the subject of this dissertation---silicon-based solutions for automotive radars. This dissertation presents architectures and design techniques for mm-wave automotive radar transceivers. Several fully-integrated transceivers and receivers operating at 22-29 GHz and 77-81 GHz are demonstrated in both CMOS and SiGe BiCMOS technologies. Excellent performance is achieved indicating the suitability of silicon technologies for automotive radar sensors. The first CMOS 22-29-GHz pulse-radar receiver front-end for ultra-wideband radars is presented. The chip includes a low noise amplifier, I/Q mixers, quadrature voltage-controlled oscillators, pulse formers and variable-gain amplifiers. Fabricated in 0.18-mum CMOS, the receiver achieves a conversion gain of 35-38.1 dB and a noise figure of 5.5-7.4 dB. Integration of multi-mode multi-band transceivers on a single chip will enable next-generation low-cost automotive radar sensors. Two highly-integrated silicon ICs are designed in a 0.18-mum BiCMOS technology. These designs are also the first reported demonstrations of mm-wave circuits with high-speed digital circuits on the same chip. The first mm-wave dual-band frequency synthesizer and transceiver, operating in the 24-GHz and 77-GHz bands, are demonstrated. All circuits except the oscillators are shared between the two bands. A multi-functional injection-locked circuit is used after the oscillators to reconfigure the division ratio inside the phase-locked loop. The synthesizer is suitable for integration in automotive radar transceivers and heterodyne receivers for 94-GHz imaging applications. The transceiver chip includes a dual-band low noise amplifier, a shared downconversion chain, dual-band pulse formers, power amplifiers, a dual-band frequency synthesizer and a high-speed programmable baseband pulse generator. Radar functionality is demonstrated using loopback measurements.

Research on the exponential growth effect on network topology: Theoretical and empirical analysis

NASA Astrophysics Data System (ADS)

Li, Shouwei; You, Zongjun

Integrated circuit (IC) industry network has been built in Yangtze River Delta with the constant expansion of IC industry. The IC industry network grows exponentially with the establishment of new companies and the establishment of contacts with old firms. Based on preferential attachment and exponential growth, the paper presents the analytical results in which the vertices degree of scale-free network follows power-law distribution p(k)˜k‑γ (γ=2β+1) and parameter β satisfies 0.5≤β≤1. At the same time, we find that the preferential attachment takes place in a dynamic local world and the size of the dynamic local world is in direct proportion to the size of whole networks. The paper also gives the analytical results of no-preferential attachment and exponential growth on random networks. The computer simulated results of the model illustrate these analytical results. Through some investigations on the enterprises, this paper at first presents the distribution of IC industry, composition of industrial chain and service chain firstly. Then, the correlative network and its analysis of industrial chain and service chain are presented. The correlative analysis of the whole IC industry is also presented at the same time. Based on the theory of complex network, the analysis and comparison of industrial chain network and service chain network in Yangtze River Delta are provided in the paper.

Photo-Spectrometer Realized In A Standard Cmos Ic Process

DOEpatents

Simpson, Michael L.; Ericson, M. Nance; Dress, William B.; Jellison, Gerald E.; Sitter, Jr., David N.; Wintenberg, Alan L.

1999-10-12

A spectrometer, comprises: a semiconductor having a silicon substrate, the substrate having integrally formed thereon a plurality of layers forming photo diodes, each of the photo diodes having an independent spectral response to an input spectra within a spectral range of the semiconductor and each of the photo diodes formed only from at least one of the plurality of layers of the semiconductor above the substrate; and, a signal processing circuit for modifying signals from the photo diodes with respective weights, the weighted signals being representative of a specific spectral response. The photo diodes have different junction depths and different polycrystalline silicon and oxide coverings. The signal processing circuit applies the respective weights and sums the weighted signals. In a corresponding method, a spectrometer is manufactured by manipulating only the standard masks, materials and fabrication steps of standard semiconductor processing, and integrating the spectrometer with a signal processing circuit.

A portable pattern-based design technology co-optimization flow to reduce optical proximity correction run-time

NASA Astrophysics Data System (ADS)

Chen, Yi-Chieh; Li, Tsung-Han; Lin, Hung-Yu; Chen, Kao-Tun; Wu, Chun-Sheng; Lai, Ya-Chieh; Hurat, Philippe

2018-03-01

Along with process improvement and integrated circuit (IC) design complexity increased, failure rate caused by optical getting higher in the semiconductor manufacture. In order to enhance chip quality, optical proximity correction (OPC) plays an indispensable rule in the manufacture industry. However, OPC, includes model creation, correction, simulation and verification, is a bottleneck from design to manufacture due to the multiple iterations and advanced physical behavior description in math. Thus, this paper presented a pattern-based design technology co-optimization (PB-DTCO) flow in cooperation with OPC to find out patterns which will negatively affect the yield and fixed it automatically in advance to reduce the run-time in OPC operation. PB-DTCO flow can generate plenty of test patterns for model creation and yield gaining, classify candidate patterns systematically and furthermore build up bank includes pairs of match and optimization patterns quickly. Those banks can be used for hotspot fixing, layout optimization and also be referenced for the next technology node. Therefore, the combination of PB-DTCO flow with OPC not only benefits for reducing the time-to-market but also flexible and can be easily adapted to diversity OPC flow.

The Chiasmus of Design: Paradoxical Outcomes in the e-Government Reform of UK Children's Services

NASA Astrophysics Data System (ADS)

Wastell, David; White, Sue; Broadhurst, Karen

This paper describes a detailed ethnographic study of the design problems of a major national IT system in the UK- The Integrated Children’s System (ICS). The implementation of the ICS has disrupted social work practice and engendered growing professional resistance, prompting a fundamental review of its design. Marshall McLuhan’s concept of chiasmus is a central feature of our analysis of the vicissitudes of ICS. Chiasmus refers to the tendency of any system, when pushed too far, to produce unintended contradictory effects, and is an intrinsic feature of the behaviour of complex, socio-technical systems. The dysfunctions of the ICS provide a pertinent, large-scale example. The ICS constitutes an attempt, via technological means, to re-organize child welfare services in the UK. Whilst aimed at improving child safety, the ICS has had the opposite effect of increasing the potential for error. This chiasmus has been exposed through the multi-site ethnography reported here, which shows how rigidly designed processes, enforced by IT systems, force social work professionals into unsafe investigative and recording practices which increase the risk of errors. The paper ends by proposing an alternative approach to design, based on socio-technical precepts, emphasizing the principles of minimum critical specification, user-centeredness and local autonomy.

Wide-bandwidth high-resolution search for extraterrestrial intelligence

NASA Technical Reports Server (NTRS)

Horowitz, Paul

1993-01-01

A third antenna was added to the system. It is a terrestrial low-gain feed, to act as a veto for local interference. The 3-chip design for a 4 megapoint complex FFT was reduced to finished working hardware. The 4-Megachannel circuit board contains 36 MByte of DRAM, 5 CPLDs, the three large FFT ASICs, and 74 ICs in all. The Austek FDP-based Spectrometer/Power Accumulator (SPA) has now been implemented as a 4-layer printed circuit. A PC interface board has been designed and together with its associated user interface and control software allows an IBM compatible computer to control the SPA board, and facilitates the transfer of spectra to the PC for display, processing, and storage. The Feature Recognizer Array cards receive the stream of modulus words from the 4M FFT cards, and forward a greatly thinned set of reports to the PC's in whose backplane they reside. In particular, a powerful ROM-based state-machine architecture has been adopted, and DRAM has been added to permit integration modes when tracking or reobserving source candidates. The general purpose (GP) array consists of twenty '486 PC class computers, each of which receives and processes the data from a feature extractor/correlator board set. The array performs a first analysis on the provided 'features' and then passes this information on to the workstation. The core workstation software is now written. That is, the communication channels between the user interface, the backend monitor program and the PC's have working software.

A Parallel Genetic Algorithm for Automated Electronic Circuit Design

NASA Technical Reports Server (NTRS)

Lohn, Jason D.; Colombano, Silvano P.; Haith, Gary L.; Stassinopoulos, Dimitris; Norvig, Peter (Technical Monitor)

2000-01-01

We describe a parallel genetic algorithm (GA) that automatically generates circuit designs using evolutionary search. A circuit-construction programming language is introduced and we show how evolution can generate practical analog circuit designs. Our system allows circuit size (number of devices), circuit topology, and device values to be evolved. We present experimental results as applied to analog filter and amplifier design tasks.

Digital circuits using universal logic gates

NASA Technical Reports Server (NTRS)

Whitaker, Sterling R. (Inventor); Miles, Lowell H. (Inventor); Cameron, Eric G. (Inventor); Donohoe, Gregory W. (Inventor); Gambles, Jody W. (Inventor)

2004-01-01

According to the invention, a digital circuit design embodied in at least one of a structural netlist, a behavioral netlist, a hardware description language netlist, a full-custom ASIC, a semi-custom ASIC, an IP core, an integrated circuit, a hybrid of chips, one or more masks, a FPGA, and a circuit card assembly is disclosed. The digital circuit design includes first and second sub-circuits. The first sub-circuits comprise a first percentage of the digital circuit design and the second sub-circuits comprise a second percentage of the digital circuit design. Each of the second sub-circuits is substantially comprised of one or more kernel circuits. The kernel circuits are comprised of selection circuits. The second percentage is at least 5%. In various embodiments, the second percentage could be at least 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, or 95%.

A Sparsity-based Framework for Resolution Enhancement in Optical Fault Analysis of Integrated Circuits

DTIC Science & Technology

2015-01-01

for IC fault detection . This section provides background information on inversion methods. Conventional inversion techniques and their shortcomings are...physical techniques, electron beam imaging/analysis, ion beam techniques, scanning probe techniques. Electrical tests are used to detect faults in 13 an...hand, there is also the second harmonic technique through which duty cycle degradation faults are detected by collecting the magnitude and the phase of

S-MMICs: Sub-mm-Wave Transistors and Integrated Circuits

DTIC Science & Technology

2008-09-01

Research Lab BAA DAAD19-03-R-0017 Research area 2.35: RF devices—Dr. Alfred Hung Submitted by: Mark Rodwell, Department of Electrical and Computer ...MOTIVATION / APPLICATION 3 TECHNOLOGY STATUS 4 TRANSISTOR SCALING LAWS 5 256 NM GENERATION 6 HBT POWER AMPLIFIER DEVELOPMENT 7 DRY-ETCHED EMITTER...TECHNOLOGY: 256 NM GENERATION 9 SCALED EPITAXY 11 CONCLUSIONS 12 20081103013 Executive Summary Transistor and power amplifier IC technology was

Evaluation of the Tuberculosis Infection Control Training Center, Tajikistan, 2014–2015

PubMed Central

Scott, C.; Mangan, J.; Tillova, Z.; Jensen, P. A.; Ahmedov, S.; Ismoilova, J.; Trusov, A.

2017-01-01

SUMMARY SETTING Training center on tuberculosis (TB) infection control (IC) for health care workers in the Central Asian Republics region. OBJECTIVE To assess the effects of TB IC training courses conducted at the Tuberculosis Infection Control Training Center in Machiton, Tajikistan. DESIGN Participants who participated in training (n = 89) during the first year of operation (April 2014–February 2015) were invited to participate in a post-training interview. RESULTS Of the 89 participants, 84 (94%) completed the interview and expressed satisfaction with the training. Eighty (95%) participants reported meeting with workplace leadership to discuss the training. Of these, 69 (85%) reported discussing changes required to meet TB IC standards. Self-reported changes in TB IC practices at work facilities post training included the creation of TB IC committees, designation of a TB IC focal person, TB IC planning, policies to separate infectious patients in waiting rooms, provision of masks for infectious patients, development of cough etiquette policies, improved glove availability, hand hygiene programs, and TB IC posters in waiting rooms. CONCLUSIONS Participant satisfaction and reported changes in TB IC activities illustrate the potential of these training courses to improve TB IC in the region. Future training courses may be tailored to specific audiences using a structured conceptual framework to impact administration, budgeting, and facilities management of TB IC practices. PMID:28399974

Warpage of QFN Package in Post Mold Cure Process of integrated circuit packaging

NASA Astrophysics Data System (ADS)

Sriwithoon, Nattha; Ugsornrat, Kessararat; Srisuwitthanon, Warayoot; Thonglor, Panakamon

2017-09-01

This research studied about warpage of QFN package in post mold cure process of integrated circuit (IC) packages using pre-plated (PPF) leadframe. For IC package, epoxy molding compound (EMC) are molded by cross linking of compound stiffness but incomplete crosslinked network and leading the fully cured thermoset by post mold cure (PMC) process. The cure temperature of PMC can change microstructure of EMC in term of stress inside the package and effect to warpage of the package due to coefficient of thermal expansion (CTE) between EMC and leadframe. In experiment, cure temperatures were varied to check the effect of internal stress due to different cure temperature after completed post mold cure for TDFN 2×3 8L. The cure temperature were varied with 180 °C, 170 °C, 160 °C, and 150°C with cure time 4 and 6 hours, respectively. For analysis, the TDFN 2×3 8L packages were analyzed the warpage by thickness gauge and scanning acoustic microscope (SAM) after take the test samples out from the oven cure. The results confirmed that effect of different CTE between EMC and leadframe due to different cure temperature resulting to warpage of the TDFN 2×3 8L packages.

Quality control and authentication of packaged integrated circuits using enhanced-spatial-resolution terahertz time-domain spectroscopy and imaging

NASA Astrophysics Data System (ADS)

Ahi, Kiarash; Shahbazmohamadi, Sina; Asadizanjani, Navid

2018-05-01

In this paper, a comprehensive set of techniques for quality control and authentication of packaged integrated circuits (IC) using terahertz (THz) time-domain spectroscopy (TDS) is developed. By material characterization, the presence of unexpected materials in counterfeit components is revealed. Blacktopping layers are detected using THz time-of-flight tomography, and thickness of hidden layers is measured. Sanded and contaminated components are detected by THz reflection-mode imaging. Differences between inside structures of counterfeit and authentic components are revealed through developing THz transmission imaging. For enabling accurate measurement of features by THz transmission imaging, a novel resolution enhancement technique (RET) has been developed. This RET is based on deconvolution of the THz image and the THz point spread function (PSF). The THz PSF is mathematically modeled through incorporating the spectrum of the THz imaging system, the axis of propagation of the beam, and the intensity extinction coefficient of the object into a Gaussian beam distribution. As a result of implementing this RET, the accuracy of the measurements on THz images has been improved from 2.4 mm to 0.1 mm and bond wires as small as 550 μm inside the packaging of the ICs are imaged.

Separation and Detection of Toxic Gases with a Silicon Micromachined Gas Chromatography System

NASA Technical Reports Server (NTRS)

Kolesar, Edward S.; Reston, Rocky R.

1995-01-01

A miniature gas chromatography (GC) system was designed and fabricated using silicon micromachining and integrated circuit (IC) processing techniques. The silicon micromachined gas chromatography system (SMGCS) is composed of a miniature sample injector that incorporates a 10 microliter sample loop; a 0.9 meter long, rectangular shaped (300 micrometer width and 10 micrometer height) capillary column coated with a 0.2 micrometer thick copper phthalocyanine (CuPc) stationary phase; and a dual detector scheme based upon a CuPc-coated chemiresistor and a commercially available 125 micrometer diameter thermal conductivity detector (TCD) bead. Silicon micromachining was employed to fabricate the interface between the sample injector and the GC column, the column itself, and the dual detector cavity. A novel IC thin-film processing technique was developed to sublime the CuPc stationary phase coating on the column walls that were micromachined in the host silicon wafer substrate and Pyrex (r) cover plate, which were then electrostatically bonded together. The SMGCS can separate binary gas mixtures composed of parts-per-million (ppm) concentrations of ammonia (NH3) and nitrogen dioxide (NO2) when isothermally operated (55-80 degrees C). With a helium carrier gas and nitrogen diluent, a 10 microliter sample volume containing ammonia and nitrogen dioxide injected at 40 psi ((2.8 x 10(exp 5)Pa)) can be separated in less than 30 minutes.

Electronic circuits and systems: A compilation. [including integrated circuits, logic circuits, varactor diode circuits, low pass filters, and optical equipment circuits

NASA Technical Reports Server (NTRS)

1975-01-01

Technological information is presented electronic circuits and systems which have potential utility outside the aerospace community. Topics discussed include circuit components such as filters, converters, and integrators, circuits designed for use with specific equipment or systems, and circuits designed primarily for use with optical equipment or displays.

49 CFR 236.5 - Design of control circuits on closed circuit principle.

Code of Federal Regulations, 2014 CFR

2014-10-01

... 49 Transportation 4 2014-10-01 2014-10-01 false Design of control circuits on closed circuit... THE INSTALLATION, INSPECTION, MAINTENANCE, AND REPAIR OF SIGNAL AND TRAIN CONTROL SYSTEMS, DEVICES, AND APPLIANCES Rules and Instructions: All Systems General § 236.5 Design of control circuits on...

49 CFR 236.5 - Design of control circuits on closed circuit principle.

Code of Federal Regulations, 2011 CFR

2011-10-01

... 49 Transportation 4 2011-10-01 2011-10-01 false Design of control circuits on closed circuit... THE INSTALLATION, INSPECTION, MAINTENANCE, AND REPAIR OF SIGNAL AND TRAIN CONTROL SYSTEMS, DEVICES, AND APPLIANCES Rules and Instructions: All Systems General § 236.5 Design of control circuits on...

49 CFR 236.5 - Design of control circuits on closed circuit principle.

Code of Federal Regulations, 2012 CFR

2012-10-01

... 49 Transportation 4 2012-10-01 2012-10-01 false Design of control circuits on closed circuit... THE INSTALLATION, INSPECTION, MAINTENANCE, AND REPAIR OF SIGNAL AND TRAIN CONTROL SYSTEMS, DEVICES, AND APPLIANCES Rules and Instructions: All Systems General § 236.5 Design of control circuits on...

49 CFR 236.5 - Design of control circuits on closed circuit principle.

Code of Federal Regulations, 2010 CFR

2010-10-01

... 49 Transportation 4 2010-10-01 2010-10-01 false Design of control circuits on closed circuit... THE INSTALLATION, INSPECTION, MAINTENANCE, AND REPAIR OF SIGNAL AND TRAIN CONTROL SYSTEMS, DEVICES, AND APPLIANCES Rules and Instructions: All Systems General § 236.5 Design of control circuits on...

49 CFR 236.5 - Design of control circuits on closed circuit principle.

Code of Federal Regulations, 2013 CFR

2013-10-01

... 49 Transportation 4 2013-10-01 2013-10-01 false Design of control circuits on closed circuit... THE INSTALLATION, INSPECTION, MAINTENANCE, AND REPAIR OF SIGNAL AND TRAIN CONTROL SYSTEMS, DEVICES, AND APPLIANCES Rules and Instructions: All Systems General § 236.5 Design of control circuits on...

Vagal stimulation targets select populations of intrinsic cardiac neurons to control neurally induced atrial fibrillation

PubMed Central

Salavatian, Siamak; Beaumont, Eric; Longpré, Jean-Philippe; Armour, J. Andrew; Vinet, Alain; Jacquemet, Vincent; Shivkumar, Kalyanam

2016-01-01

Mediastinal nerve stimulation (MNS) reproducibly evokes atrial fibrillation (AF) by excessive and heterogeneous activation of intrinsic cardiac (IC) neurons. This study evaluated whether preemptive vagus nerve stimulation (VNS) impacts MNS-induced evoked changes in IC neural network activity to thereby alter susceptibility to AF. IC neuronal activity in the right atrial ganglionated plexus was directly recorded in anesthetized canines (n = 8) using a linear microelectrode array concomitant with right atrial electrical activity in response to: 1) epicardial touch or great vessel occlusion vs. 2) stellate or vagal stimulation. From these stressors, post hoc analysis (based on the Skellam distribution) defined IC neurons so recorded as afferent, efferent, or convergent (afferent and efferent inputs) local circuit neurons (LCN). The capacity of right-sided MNS to modify IC activity in the induction of AF was determined before and after preemptive right (RCV)- vs. left (LCV)-sided VNS (15 Hz, 500 μs; 1.2× bradycardia threshold). Neuronal (n = 89) activity at baseline (0.11 ± 0.29 Hz) increased during MNS-induced AF (0.51 ± 1.30 Hz; P < 0.001). Convergent LCNs were preferentially activated by MNS. Preemptive RCV reduced MNS-induced changes in LCN activity (by 70%) while mitigating MNS-induced AF (by 75%). Preemptive LCV reduced LCN activity by 60% while mitigating AF potential by 40%. IC neuronal synchrony increased during neurally induced AF, a local neural network response mitigated by preemptive VNS. These antiarrhythmic effects persisted post-VNS for, on average, 26 min. In conclusion, VNS preferentially targets convergent LCNs and their interactive coherence to mitigate the potential for neurally induced AF. The antiarrhythmic properties imposed by VNS exhibit memory. PMID:27591222

Embedded I&C for Extreme Environments

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kisner, Roger A.

2016-04-01

This project uses embedded instrumentation and control (I&C) technologies to demonstrate potential performance gains of nuclear power plant components in extreme environments. Extreme environments include high temperature, radiation, high pressure, high vibration, and high EMI conditions. For extreme environments, performance gains arise from moment-to-moment sensing of local variables and immediate application of local feedback control. Planning for embedding I&C during early system design phases contrasts with the traditional, serial design approach that incorporates minimal I&C after mechanical and electrical design is complete. The demonstration application involves the development and control of a novel, proof-of-concept motor/pump design. The motor and pumpmore » combination operate within the fluid environment, eliminating the need for rotating seals. Actively controlled magnetic bearings also replace failure-prone mechanical contact bearings that typically suspend rotating components. Such as design has the potential to significantly enhance the reliability and life of the pumping system and would not be possible without embedded I&C.« less

Automated Design of Quantum Circuits

NASA Technical Reports Server (NTRS)

Williams, Colin P.; Gray, Alexander G.

2000-01-01

In order to design a quantum circuit that performs a desired quantum computation, it is necessary to find a decomposition of the unitary matrix that represents that computation in terms of a sequence of quantum gate operations. To date, such designs have either been found by hand or by exhaustive enumeration of all possible circuit topologies. In this paper we propose an automated approach to quantum circuit design using search heuristics based on principles abstracted from evolutionary genetics, i.e. using a genetic programming algorithm adapted specially for this problem. We demonstrate the method on the task of discovering quantum circuit designs for quantum teleportation. We show that to find a given known circuit design (one which was hand-crafted by a human), the method considers roughly an order of magnitude fewer designs than naive enumeration. In addition, the method finds novel circuit designs superior to those previously known.

Capable Copper Electrodeposition Process for Integrated Circuit - substrate Packaging Manufacturing

NASA Astrophysics Data System (ADS)

Ghanbari, Nasrin

This work demonstrates a capable reverse pulse deposition methodology to influence gap fill behavior inside microvia along with a uniform deposit in the fine line patterned regions for substrate packaging applications. Interconnect circuitry in IC substrate packages comprises of stacked microvia that varies in depth from 20microm to 100microm with an aspect ratio of 0.5 to 1.5 and fine line patterns defined by photolithography. Photolithography defined pattern regions incorporate a wide variety of feature sizes including large circular pad structures with diameter of 20microm - 200microm, fine traces with varying widths of 3microm - 30microm and additional planar regions to define a IC substrate package. Electrodeposition of copper is performed to establish the desired circuit. Electrodeposition of copper in IC substrate applications holds certain unique challenges in that they require a low cost manufacturing process that enables a void-free gap fill inside the microvia along with uniform deposition of copper on exposed patterned regions. Deposition time scales to establish the desired metal thickness for such packages could range from several minutes to few hours. This work showcases a reverse pulse electrodeposition methodology that achieves void-free gap fill inside the microvia and uniform plating in FLS (Fine Lines and Spaces) regions with significantly higher deposition rates than traditional approaches. In order to achieve this capability, systematic experimental and simulation studies were performed. A strong correlation of independent parameters that govern the electrodeposition process such as bath temperature, reverse pulse plating parameters and the ratio of electrolyte concentrations is shown to the deposition kinetics and deposition uniformity in fine patterned regions and gap fill rate inside the microvia. Additionally, insight into the physics of via fill process is presented with secondary and tertiary current simulation efforts. Such efforts lead to show "smart" control of deposition rate at the top and bottom of via to avoid void formation. Finally, a parametric effect on grain size and the ensuing copper metallurgical characteristics of bulk copper is also shown to enable high reliability substrate packages for the IC packaging industry.

Risk of Pneumonia with Inhaled Corticosteroid versus Long-Acting Bronchodilator Regimens in Chronic Obstructive Pulmonary Disease: A New-User Cohort Study

PubMed Central

DiSantostefano, Rachael L.; Sampson, Tim; Le, Hoa Van; Hinds, David; Davis, Kourtney J.; Bakerly, Nawar Diar

2014-01-01

Introduction Observational studies using case-control designs have showed an increased risk of pneumonia associated with inhaled corticosteroid (ICS)-containing medications in patients with chronic obstructive pulmonary disease (COPD). New-user observational cohort designs may minimize biases associated with previous case-control designs. Objective To estimate the association between ICS and pneumonia among new users of ICS relative to inhaled long-acting bronchodilator (LABD) monotherapy. Methods Pneumonia events in COPD patients ≥45 years old were compared among new users of ICS medications (n = 11,555; ICS, ICS/long-acting β2-agonist [LABA] combination) and inhaled LABD monotherapies (n = 6,492; LABA, long-acting muscarinic antagonists) using Cox proportional hazards models, with propensity scores to adjust for confounding. Setting: United Kingdom electronic medical records with linked hospitalization and mortality data (2002–2010). New users were censored at earliest of: pneumonia event, death, changing/discontinuing treatment, or end of follow-up. Outcomes: severe pneumonia (primary) and any pneumonia (secondary). Results Following adjustment, new use of ICS-containing medications was associated with an increased risk of pneumonia hospitalization (n = 322 events; HR = 1.55, 95% CI: 1.14, 2.10) and any pneumonia (n = 702 events; HR = 1.49, 95% CI: 1.22, 1.83). Crude incidence rates of any pneumonia were 48.7 and 30.9 per 1000 person years among the ICS-containing and LABD cohorts, respectively. Excess risk of pneumonia with ICS was reduced when requiring ≥1 month or ≥ 6 months of new use. There was an apparent dose-related effect, with greater risk at higher daily doses of ICS. There was evidence of channeling bias, with more severe patients prescribed ICS, for which the analysis may not have completely adjusted. Conclusions The results of this new-user cohort study are consistent with published findings; ICS were associated with a 20–50% increased risk of pneumonia in COPD, which reduced with exposure time. This risk must be weighed against the benefits when prescribing ICS to patients with COPD. PMID:24878543

Fracture resistance of the implant-abutment connection in implants with internal hex and internal conical connections under oblique compressive loading: an in vitro study.

PubMed

Coppedê, Abílio Ricciardi; Bersani, Edmilson; de Mattos, Maria da Gloria Chiarello; Rodrigues, Renata Cristina Silveira; Sartori, Ivete Aparecida de Mattias; Ribeiro, Ricardo Faria

2009-01-01

The objective of this study was to verify if differences in the design of internal hex (IH) and internal conical (IC) connection implant systems influence fracture resistance under oblique compressive forces. Twenty implant-abutment assemblies were utilized: 10 with IH connections and 10 with IC connections. Maximum deformation force for IC implants (90.58 +/- 6.72 kgf) was statistically higher than that for IH implants (83.73 +/- 4.94 kgf) (P = .0182). Fracture force for the IH implants was 79.86 +/- 4.77 kgf. None of the IC implants fractured. The friction-locking mechanics and the solid design of the IC abutments provided greater resistance to deformation and fracture under oblique compressive loading when compared to the IH abutments.

PUZZLE - A program for computer-aided design of printed circuit artwork

NASA Technical Reports Server (NTRS)

Harrell, D. A. W.; Zane, R.

1971-01-01

Program assists in solving spacing problems encountered in printed circuit /PC/ design. It is intended to have maximum use for two-sided PC boards carrying integrated circuits, and also aids design of discrete component circuits.

An Electronics Course Emphasizing Circuit Design

ERIC Educational Resources Information Center

Bergeson, Haven E.

1975-01-01

Describes a one-quarter introductory electronics course in which the students use a variety of inexpensive integrated circuits to design and construct a large number of useful circuits. Presents the subject matter of the course in three parts: linear circuits, digital circuits, and more complex circuits. (GS)

CMOS compatible fabrication process of MEMS resonator for timing reference and sensing application

NASA Astrophysics Data System (ADS)

Huynh, Duc H.; Nguyen, Phuong D.; Nguyen, Thanh C.; Skafidas, Stan; Evans, Robin

2015-12-01

Frequency reference and timing control devices are ubiquitous in electronic applications. There is at least one resonator required for each of this device. Currently electromechanical resonators such as crystal resonator, ceramic resonator are the ultimate choices. This tendency will probably keep going for many more years. However, current market demands for small size, low power consumption, cheap and reliable products, has divulged many limitations of this type of resonators. They cannot be integrated into standard CMOS (Complement metaloxide- semiconductor) IC (Integrated Circuit) due to material and fabrication process incompatibility. Currently, these devices are off-chip and they require external circuitries to interface with the ICs. This configuration significantly increases the overall size and cost of the entire electronic system. In addition, extra external connection, especially at high frequency, will potentially create negative impacts on the performance of the entire system due to signal degradation and parasitic effects. Furthermore, due to off-chip packaging nature, these devices are quite expensive, particularly for high frequency and high quality factor devices. To address these issues, researchers have been intensively studying on an alternative for type of resonator by utilizing the new emerging MEMS (Micro-electro-mechanical systems) technology. Recent progress in this field has demonstrated a MEMS resonator with resonant frequency of 2.97 GHz and quality factor (measured in vacuum) of 42900. Despite this great achievement, this prototype is still far from being fully integrated into CMOS system due to incompatibility in fabrication process and its high series motional impedance. On the other hand, fully integrated MEMS resonator had been demonstrated but at lower frequency and quality factor. We propose a design and fabrication process for a low cost, high frequency and a high quality MEMS resonator, which can be integrated into a standard CMOS IC. This device is expected to operate in hundreds of Mhz frequency range; quality factor surpasses 10000 and series motional impedance low enough that could be matching into conventional system without enormous effort. This MEMS resonator can be used in the design of many blocks in wireless and RF (Radio Frequency) systems such as low phase noise oscillator, band pass filter, power amplifier and in many sensing application.

Fault detection in digital and analog circuits using an i(DD) temporal analysis technique

NASA Technical Reports Server (NTRS)

Beasley, J.; Magallanes, D.; Vridhagiri, A.; Ramamurthy, Hema; Deyong, Mark

1993-01-01

An i(sub DD) temporal analysis technique which is used to detect defects (faults) and fabrication variations in both digital and analog IC's by pulsing the power supply rails and analyzing the temporal data obtained from the resulting transient rail currents is presented. A simple bias voltage is required for all the inputs, to excite the defects. Data from hardware tests supporting this technique are presented.

Three-Dimensional Integrated Circuit (3D IC) Key Technology: Through-Silicon Via (TSV).

PubMed

Shen, Wen-Wei; Chen, Kuan-Neng

2017-12-01

3D integration with through-silicon via (TSV) is a promising candidate to perform system-level integration with smaller package size, higher interconnection density, and better performance. TSV fabrication is the key technology to permit communications between various strata of the 3D integration system. TSV fabrication steps, such as etching, isolation, metallization processes, and related failure modes, as well as other characterizations are discussed in this invited review paper.

Government-Imposed Barriers to the Use of Commercial Integrated Circuits in Military Systems.

DTIC Science & Technology

1996-02-01

Advanced Planning Briefing for Industry (undated). The FY94/FY95 research agenda of the Microprocessor Technology Utiliza- tion Program includes... planning and re- sults. As a model of how a private institute might operate, we suggest (without implying partiality) the Semiconductor Research...or incorporate lessons learned). Those IC suppliers passing the audit are listed on the QML. Products from QML-listed suppliers can be used with

Hybrid Technology Cost Reduction Improvement Study Program. Volume I. Results of Literature Search and Questionnaire Survey.

DTIC Science & Technology

1978-04-01

Rockwell Internat i . P.O. Box 10062 Elec tronic Devices Div . a ll a s. TX 7 520 7 Rockwell Internat ’l. P.O. Box 0192 Electronic Devices Div. Anaheim...H a n dl inc for -H ybrid ‘4icro- circuits , B. Rasmariis (ref. 3). 14. Therma l A g ing Characterist ics of In- Pb Solder Bonds to Gold , R. B

[Risk factors found in suicide attempters].

PubMed

Villa-Manzano, Alberto Iram; Robles-Romero, Miguel Angel; Gutiérrez-Román, Elsa Armida; Martínez-Arriaga, María Guadalupe; Valadez-Toscano, Francisco Javier; Cabrera-Pivaral, Carlos E

2009-01-01

A better understanding of risk factors for suicide in general population is crucial for the design of suicide prevention programs. Our objective was to identify personal and family risk factors in suicide attempters. Case-control design. We searched in patients with an acute intoxication, those subjects with and intoxication attributable to suicide attempt. These patients were matched with controls by gender and the date of intoxication. We use a structured questionnaire to identify personal characteristics, family features and network support. Odds ratio (OR) and 95 % confidence interval were obtained. 25 cases and 25 controls were evaluated. The risk factors associated with suicide attempt adjusted by age, were being a student and smoking habits. Family violence background showed OR = 3.8 (IC 95 % = 1.1-13), family disintegration a OR = 8.5 (IC 95 % = 2.1-35), critical events background OR = 8.8 (IC 95 % = 2.1-36), poor self-esteem OR = 8.2 (IC 95 % 2-35), depression OR = 22 (IC 95 % = 3-190), anxiety OR = 9 (IC 95 % = 2-47), family dysfunction OR = 25 (IC 95 % = 4-151). The principal risk factor for suicide attempt was family dysfunction and psychological traits.

Design of a Multi-Channel Front-End Readout ASIC With Low Noise and Large Dynamic Input Range for APD-Based PET Imaging

NASA Astrophysics Data System (ADS)

Fang, X. C.; Hu-Guo, Ch.; Ollivier-Henry, N.; Brasse, D.; Hu, Y.

2010-06-01

This paper represents the design of a low-noise, wide band multi-channel readout integrated circuit (IC) used as front end readout electronics of avalanche photo diodes (APD) dedicated to a small animal positron emission tomography (PET) system. The first ten-channel prototype chip (APD-Chip) of the analog parts has been designed and fabricated in a 0.35 μm CMOS process. Every channel of the APD_Chip includes a charge-sensitive preamplifier (CSA), a CR-(RC)2 shaper, and an analog buffer. In a channel, the CSA reads charge signals (10 bits dynamic range) from an APD array having 10 pF of capacitance per pixel. A linearized degenerated differential pair which ensures high linearity in all dynamical range is used as the high feedback resistor for preventing pile up of signals. The designed CSA has the capability of compensating automatically up to 200 nA leakage current from the detector. The CR-(RC)2 shaper filters and shapes the output signal of the CSA. An equivalent input noise charge obtained from test is 275 e -+ 10 e-/pF. In this paper the prototype is presented for both its theoretical analysis and its test results.

Expediting analog design retargeting by design knowledge re-use and circuit synthesis: a practical example on a Delta-Sigma modulator

NASA Astrophysics Data System (ADS)

Webb, Matthew; Tang, Hua

2016-08-01

In the past decade or two, due to constant and rapid technology changes, analog design re-use or design retargeting to newer technologies has been brought to the table in order to expedite the design process and improve time-to-market. If properly conducted, analog design retargeting could significantly cut down design cycle compared to designs starting from the scratch. In this article, we present an empirical and general method for efficient analog design retargeting by design knowledge re-use and circuit synthesis (CS). The method first identifies circuit blocks that compose the source system and extracts the performance parameter specifications of each circuit block. Then, for each circuit block, it scales the values of design variables (DV) from the source design to derive an initial design in the target technology. Depending on the performance of this initial target design, a design space is defined for synthesis. Subsequently, each circuit block is automatically synthesised using state-of-art analog synthesis tools based on a combination of global and local optimisation techniques to achieve comparable performance specifications to those extracted from the source system. Finally, the overall system is composed of those synthesised circuit blocks in the target technology. We illustrate the method using a practical example of a complex Delta-Sigma modulator (DSM) circuit.

Universal programmable quantum circuit schemes to emulate an operator

DOE Office of Scientific and Technical Information (OSTI.GOV)

Daskin, Anmer; Grama, Ananth; Kollias, Giorgos

Unlike fixed designs, programmable circuit designs support an infinite number of operators. The functionality of a programmable circuit can be altered by simply changing the angle values of the rotation gates in the circuit. Here, we present a new quantum circuit design technique resulting in two general programmable circuit schemes. The circuit schemes can be used to simulate any given operator by setting the angle values in the circuit. This provides a fixed circuit design whose angles are determined from the elements of the given matrix-which can be non-unitary-in an efficient way. We also give both the classical and quantummore » complexity analysis for these circuits and show that the circuits require a few classical computations. For the electronic structure simulation on a quantum computer, one has to perform the following steps: prepare the initial wave function of the system; present the evolution operator U=e{sup -iHt} for a given atomic and molecular Hamiltonian H in terms of quantum gates array and apply the phase estimation algorithm to find the energy eigenvalues. Thus, in the circuit model of quantum computing for quantum chemistry, a crucial step is presenting the evolution operator for the atomic and molecular Hamiltonians in terms of quantum gate arrays. Since the presented circuit designs are independent from the matrix decomposition techniques and the global optimization processes used to find quantum circuits for a given operator, high accuracy simulations can be done for the unitary propagators of molecular Hamiltonians on quantum computers. As an example, we show how to build the circuit design for the hydrogen molecule.« less

Compact modeling of total ionizing dose and aging effects in MOS technologies

DOE PAGES

Esqueda, Ivan S.; Barnaby, Hugh J.; King, Michael Patrick

2015-06-18

This paper presents a physics-based compact modeling approach that incorporates the impact of total ionizing dose (TID) and stress-induced defects into simulations of metal-oxide-semiconductor (MOS) devices and integrated circuits (ICs). This approach utilizes calculations of surface potential (ψs) to capture the charge contribution from oxide trapped charge and interface traps and to describe their impact on MOS electrostatics and device operating characteristics as a function of ionizing radiation exposure and aging effects. The modeling approach is demonstrated for bulk and silicon-on-insulator (SOI) MOS device. The formulation is verified using TCAD simulations and through the comparison of model calculations and experimentalmore » I-V characteristics from irradiated devices. The presented approach is suitable for modeling TID and aging effects in advanced MOS devices and ICs.« less

Ultra-compact coherent receiver with serial interface for pluggable transceiver.

PubMed

Itoh, Toshihiro; Nakajima, Fumito; Ohno, Tetsuichiro; Yamanaka, Shogo; Soma, Shunichi; Saida, Takashi; Nosaka, Hideyuki; Murata, Koichi

2014-09-22

An ultra-compact integrated coherent receiver with a volume of 1.3 cc using a quad-channel transimpedance amplifier (TIA)-IC chip with a serial peripheral interface (SPI) is demonstrated for the first time. The TIA with the SPI and photodiode (PD) bias circuits, a miniature dual polarization optical hybrid, an octal-PD and small optical coupling system enabled the realization of the compact receiver. Measured transmission performance with 32 Gbaud dual-polarization quadrature phase shift keying signal is equivalent to that of the conventional multi-source agreement-based integrated coherent receiver with dual channel TIA-ICs. By comparing the bit-error rate (BER) performance with that under continuous SPI access, we also confirmed that there is no BER degradation caused by SPI interface access. Such an ultra-compact receiver is promising for realizing a new generation of pluggable transceivers.

A Single Chip Automotive Control LSI Using SOI Bipolar Complimentary MOS Double-Diffused MOS

NASA Astrophysics Data System (ADS)

Kawamoto, Kazunori; Mizuno, Shoji; Abe, Hirofumi; Higuchi, Yasushi; Ishihara, Hideaki; Fukumoto, Harutsugu; Watanabe, Takamoto; Fujino, Seiji; Shirakawa, Isao

2001-04-01

Using the example of an air bag controller, a single chip solution for automotive sub-control systems is investigated, by using a technological combination of improved circuits, bipolar complimentary metal oxide silicon double-diffused metal oxide silicon (BiCDMOS) and thick silicon on insulator (SOI). For circuits, an automotive specific reduced instruction set computer (RISC) center processing unit (CPU), and a novel, all integrated system clock generator, dividing digital phase-locked loop (DDPLL) are proposed. For the device technologies, the authors use SOI-BiCDMOS with trench dielectric-isolation (TD) which enables integration of various devices in an integrated circuit (IC) while avoiding parasitic miss operations by ideal isolation. The structures of the SOI layer and TD, are optimized for obtaining desired device characteristics and high electromagnetic interference (EMI) immunity. While performing all the air bag system functions over a wide range of supply voltage, and ambient temperature, the resulting single chip reduces the electronic parts to about a half of those in the conventional air bags. The combination of single chip oriented circuits and thick SOI-BiCDMOS technologies offered in this work is valuable for size reduction and improved reliability of automotive electronic control units (ECUs).

Robust Design of Biological Circuits: Evolutionary Systems Biology Approach

PubMed Central

Chen, Bor-Sen; Hsu, Chih-Yuan; Liou, Jing-Jia

2011-01-01

Artificial gene circuits have been proposed to be embedded into microbial cells that function as switches, timers, oscillators, and the Boolean logic gates. Building more complex systems from these basic gene circuit components is one key advance for biologic circuit design and synthetic biology. However, the behavior of bioengineered gene circuits remains unstable and uncertain. In this study, a nonlinear stochastic system is proposed to model the biological systems with intrinsic parameter fluctuations and environmental molecular noise from the cellular context in the host cell. Based on evolutionary systems biology algorithm, the design parameters of target gene circuits can evolve to specific values in order to robustly track a desired biologic function in spite of intrinsic and environmental noise. The fitness function is selected to be inversely proportional to the tracking error so that the evolutionary biological circuit can achieve the optimal tracking mimicking the evolutionary process of a gene circuit. Finally, several design examples are given in silico with the Monte Carlo simulation to illustrate the design procedure and to confirm the robust performance of the proposed design method. The result shows that the designed gene circuits can robustly track desired behaviors with minimal errors even with nontrivial intrinsic and external noise. PMID:22187523

Robust design of biological circuits: evolutionary systems biology approach.

PubMed

Chen, Bor-Sen; Hsu, Chih-Yuan; Liou, Jing-Jia

2011-01-01

Artificial gene circuits have been proposed to be embedded into microbial cells that function as switches, timers, oscillators, and the Boolean logic gates. Building more complex systems from these basic gene circuit components is one key advance for biologic circuit design and synthetic biology. However, the behavior of bioengineered gene circuits remains unstable and uncertain. In this study, a nonlinear stochastic system is proposed to model the biological systems with intrinsic parameter fluctuations and environmental molecular noise from the cellular context in the host cell. Based on evolutionary systems biology algorithm, the design parameters of target gene circuits can evolve to specific values in order to robustly track a desired biologic function in spite of intrinsic and environmental noise. The fitness function is selected to be inversely proportional to the tracking error so that the evolutionary biological circuit can achieve the optimal tracking mimicking the evolutionary process of a gene circuit. Finally, several design examples are given in silico with the Monte Carlo simulation to illustrate the design procedure and to confirm the robust performance of the proposed design method. The result shows that the designed gene circuits can robustly track desired behaviors with minimal errors even with nontrivial intrinsic and external noise.

Genetic circuit design automation.

PubMed

Nielsen, Alec A K; Der, Bryan S; Shin, Jonghyeon; Vaidyanathan, Prashant; Paralanov, Vanya; Strychalski, Elizabeth A; Ross, David; Densmore, Douglas; Voigt, Christopher A

2016-04-01

Computation can be performed in living cells by DNA-encoded circuits that process sensory information and control biological functions. Their construction is time-intensive, requiring manual part assembly and balancing of regulator expression. We describe a design environment, Cello, in which a user writes Verilog code that is automatically transformed into a DNA sequence. Algorithms build a circuit diagram, assign and connect gates, and simulate performance. Reliable circuit design requires the insulation of gates from genetic context, so that they function identically when used in different circuits. We used Cello to design 60 circuits forEscherichia coli(880,000 base pairs of DNA), for which each DNA sequence was built as predicted by the software with no additional tuning. Of these, 45 circuits performed correctly in every output state (up to 10 regulators and 55 parts), and across all circuits 92% of the output states functioned as predicted. Design automation simplifies the incorporation of genetic circuits into biotechnology projects that require decision-making, control, sensing, or spatial organization. Copyright © 2016, American Association for the Advancement of Science.

Design and implementation of GaAs HBT circuits with ACME

NASA Technical Reports Server (NTRS)

Hutchings, Brad L.; Carter, Tony M.

1993-01-01

GaAs HBT circuits offer high performance (5-20 GHz) and radiation hardness (500 Mrad) that is attractive for space applications. ACME is a CAD tool specifically developed for HBT circuits. ACME implements a novel physical schematic-capture design technique where designers simultaneously view the structure and physical organization of a circuit. ACME's design interface is similar to schematic capture; however, unlike conventional schematic capture, designers can directly control the physical placement of both function and interconnect at the schematic level. In addition, ACME provides design-time parasitic extraction, complex wire models, and extensions to Multi-Chip Modules (MCM's). A GaAs HBT gate-array and semi-custom circuits have been developed with ACME; several circuits have been fabricated and found to be fully functional .

Educational Support System for Experiments Involving Construction of Sound Processing Circuits

ERIC Educational Resources Information Center

Takemura, Atsushi

2012-01-01

This paper proposes a novel educational support system for technical experiments involving the production of practical electronic circuits for sound processing. To support circuit design and production, each student uses a computer during the experiments, and can learn circuit design, virtual circuit making, and real circuit making. In the…

Nanotubes May Break Through "Chip Wall"

NASA Technical Reports Server (NTRS)

Laufenberg, Larry

2003-01-01

In 1965, just four years after the first planar integrated circuit (IC) was discovered, Cordon Moore observed that the number of transistors per integrated circuit had grown exponentially. He predicted that this would continue, and the media soon began to call his prophesy "Moore's Law" For nearly forty years, Moore's Law has been validated by the technological progress achieved in the semiconductor industry. Now, however, industry experts are warning of a "Red Brick Wall" that may soon block the continued scaling predicted by by Moore's Law. The "red bricks" in the wall are those areas of technical challenge for which no known manufacturable solution exists. One such "brick" is the challenge of finding a new material and processing technology to replace the metals used today to interconnect transistors on a chip.

Design of low loss helix circuits for interference fitted and brazed circuits

NASA Technical Reports Server (NTRS)

Jacquez, A.

1983-01-01

The RF loss properties and thermal capability of brazed helix circuits and interference fitted circuits were evaluated. The objective was to produce design circuits with minimum RF loss and maximum heat transfer. These circuits were to be designed to operate at 10 kV and at 20 GHz using a gamma a approximately equal to 1.0. This represents a circuit diameter of only 0.75 millimeters. The fabrication of this size circuit and the 0.48 millimeter high support rods required considerable refinements in the assembly techniques and fixtures used on lower frequency circuits. The transition from the helices to the waveguide was designed and the circuits were matched from 20 to 40 GHz since the helix design is a broad band circuit and at a gamma a of 1.0 will operate over this band. The loss measurement was a transmission measurement and therefore had two such transitions. This resulting double-ended match required tuning elements to achieve the broad band match and external E-H tuners at each end to optimize the match for each frequency where the loss measurement was made. The test method used was a substitution method where the test fixture was replaced by a calibrated attenuator.

The Effect of Epoxy Molding Compound Floor Life to Reliability Performance and mold ability for QFN Package

NASA Astrophysics Data System (ADS)

Peanpunga, Udom; Ugsornrat, Kessararat; Thorlor, Panakamol; Sumithpibul, Chalermsak

2017-09-01

This research studied about an epoxy molding compound (EMC) floor life to reliability performance of integrated circuit (IC) package. Molding is the process for protecting the die of IC package form mechanical and chemical reaction from external environment by shaping EMC. From normal manufacturing process, the EMC is stored in the frozen at 5oC and left at around room temperature for aging time or floor life before molding process. The EMC floor life effect to its properties and reliability performance of IC package. Therefore, this work interested in varied the floor life of EMC before molding process to analyze properties of EMC such as spiral flow length, gelation time, and viscosity. In experiment, the floor life of EMC was varied to check the effect of its property to reliability performance. The EMC floor life were varied from 0 hours to 60 hours with a step of 12 hours and observed wire sweep, incomplete EMC, and delamination inside the packages for 3x3, 5x5 and 8x8 mm2 of QFN packages. The evaluation showed about clearly effect of EMC floor life to IC packaging reliability. EMC floor life is not any concern for EMC property, moldabilty, and reliability from 0 hours to 48 hours for molding process of 3x3,5x5 and 8x8 mm2 QFN packaging manufacturing

30 CFR 75.907 - Design of trailing cables for medium-voltage circuits.

Code of Federal Regulations, 2010 CFR

2010-07-01

... 30 Mineral Resources 1 2010-07-01 2010-07-01 false Design of trailing cables for medium-voltage... Medium-Voltage Alternating Current Circuits § 75.907 Design of trailing cables for medium-voltage circuits. [Statutory Provisions] Trailing cables for medium-voltage circuits shall include grounding...

30 CFR 75.907 - Design of trailing cables for medium-voltage circuits.

Code of Federal Regulations, 2011 CFR

2011-07-01

... 30 Mineral Resources 1 2011-07-01 2011-07-01 false Design of trailing cables for medium-voltage... Medium-Voltage Alternating Current Circuits § 75.907 Design of trailing cables for medium-voltage circuits. [Statutory Provisions] Trailing cables for medium-voltage circuits shall include grounding...

30 CFR 75.907 - Design of trailing cables for medium-voltage circuits.

Code of Federal Regulations, 2013 CFR

2013-07-01

... 30 Mineral Resources 1 2013-07-01 2013-07-01 false Design of trailing cables for medium-voltage... Medium-Voltage Alternating Current Circuits § 75.907 Design of trailing cables for medium-voltage circuits. [Statutory Provisions] Trailing cables for medium-voltage circuits shall include grounding...

30 CFR 75.907 - Design of trailing cables for medium-voltage circuits.

Code of Federal Regulations, 2012 CFR

2012-07-01

... 30 Mineral Resources 1 2012-07-01 2012-07-01 false Design of trailing cables for medium-voltage... Medium-Voltage Alternating Current Circuits § 75.907 Design of trailing cables for medium-voltage circuits. [Statutory Provisions] Trailing cables for medium-voltage circuits shall include grounding...

30 CFR 75.907 - Design of trailing cables for medium-voltage circuits.

Code of Federal Regulations, 2014 CFR

2014-07-01

... 30 Mineral Resources 1 2014-07-01 2014-07-01 false Design of trailing cables for medium-voltage... Medium-Voltage Alternating Current Circuits § 75.907 Design of trailing cables for medium-voltage circuits. [Statutory Provisions] Trailing cables for medium-voltage circuits shall include grounding...

Power Management and SRAM for Energy-Autonomous and Low-Power Systems

NASA Astrophysics Data System (ADS)

Chen, Gregory K.

We demonstrate the two first-known, complete, self-powered millimeter-scale computer systems. These microsystems achieve zero-net-energy operation using solar energy harvesting and ultra-low-power circuits. A medical implant for monitoring intraocular pressure (IOP) is presented as part of a treatment for glaucoma. The 1.5mm3 IOP monitor is easily implantable because of its small size and measures IOP with 0.5mmHg accuracy. It wirelessly transmits data to an external wand while consuming 4.70nJ/bit. This provides rapid feedback about treatment efficacies to decrease physician response time and potentially prevent unnecessary vision loss. A nearly-perpetual temperature sensor is presented that processes data using a 2.1muW near-threshold ARMRTM Cortex-M3(TM) muP that provides a widely-used and trusted programming platform. Energy harvesting and power management techniques for these two microsystems enable energy-autonomous operation. The IOP monitor harvests 80nW of solar power while consuming only 5.3nW, extending lifetime indefinitely. This allows the device to provide medical information for extended periods of time, giving doctors time to converge upon the best glaucoma treatment. The temperature sensor uses on-demand power delivery to improve low-load dc-dc voltage conversion efficiency by 4.75x. It also performs linear regulation to deliver power with low noise, improved load regulation, and tight line regulation. Low-power high-throughput SRAM techniques help millimeter-scale microsystems meet stringent power budgets. VDD scaling in memory decreases energy per access, but also decreases stability margins. These margins can be improved using sizing, VTH selection, and assist circuits, as well as new bitcell designs. Adaptive Crosshairs modulation of SRAM power supplies fixes 70% of parametric failures. Half-differential SRAM design improves stability, reducing VMIN by 72mV. The circuit techniques for energy autonomy presented in this dissertation enable millimeter-scale microsystems for medical implants, such as blood pressure and glucose sensors, as well as non-medical applications, such as supply chain and infrastructure monitoring. These pervasive sensors represent the continuation of Bell's Law, which accurately traces the evolution of computers as they have become smaller, more numerous, and more powerful. The development of millimeter-scale massively-deployed ubiquitous computers ensures the continued expansion and profitability of the semiconductor industry. NanoWatt circuit techniques will allow us to meet this next frontier in IC design.

Documentation of Stainless Steel Lithium Circuit Test Section Design. Suppl

NASA Technical Reports Server (NTRS)

Godfroy, Thomas J. (Compiler); Martin, James J.

2010-01-01

The Early Flight Fission-Test Facilities (EFF-TF) team was tasked by Naval Reactors Prime Contract Team (NRPCT) to design, fabricate, and test an actively pumped lithium (Li) flow circuit. This Li circuit takes advantage of work in progress at the EFF TF on a stainless steel sodium/potassium (NaK) circuit. The effort involved modifying the original stainless steel NaK circuit such that it could be operated with Li in place of NaK. This new design considered freeze/thaw issues and required the addition of an expansion tank and expansion/extrusion volumes in the circuit plumbing. Instrumentation has been specified for Li and circuit heaters have been placed throughout the design to ensure adequate operational temperatures and no uncontrolled freezing of the Li. All major components have been designed and fabricated prior to circuit redesign for Li and were not modified. Basic circuit components include: reactor segment, Li to gas heat exchanger, electromagnetic liquid metal pump, load/drain reservoir, expansion reservoir, instrumentation, and trace heaters. The reactor segment, based on a Los Alamos National Laboratory 100-kW design study with 120 fuel pins, is the only prototypic component in the circuit. However, due to earlier funding constraints, a 37-pin partial-array of the core, including the central three rings of fuel pins (pin and flow path dimensions are the same as those in the full design), was selected for fabrication and test. This Technical Publication summarizes the design and integration of the pumped liquid metal Li flow circuit as of May 1, 2005. This supplement contains drawings, analysis, and calculations

Documentation of Stainless Steel Lithium Circuit Test Section Design

NASA Technical Reports Server (NTRS)

Godfroy, T. J.; Martin, J. J.; Stewart, E. T.; Rhys, N. O.

2010-01-01

The Early Flight Fission-Test Facilities (EFF-TF) team was tasked by Naval Reactors Prime Contract Team (NRPCT) to design, fabricate, and test an actively pumped lithium (Li) flow circuit. This Li circuit takes advantage of work in progress at the EFF TF on a stainless steel sodium/potassium (NaK) circuit. The effort involved modifying the original stainless steel NaK circuit such that it could be operated with Li in place of NaK. This new design considered freeze/thaw issues and required the addition of an expansion tank and expansion/extrusion volumes in the circuit plumbing. Instrumentation has been specified for Li and circuit heaters have been placed throughout the design to ensure adequate operational temperatures and no uncontrolled freezing of the Li. All major components have been designed and fabricated prior to circuit redesign for Li and were not modified. Basic circuit components include: reactor segment, Li to gas heat exchanger, electromagnetic liquid metal pump, load/drain reservoir, expansion reservoir, instrumentation, and trace heaters. The reactor segment, based on a Los Alamos National Laboratory 100-kW design study with 120 fuel pins, is the only prototypic component in the circuit. However, due to earlier funding constraints, a 37-pin partial-array of the core, including the central three rings of fuel pins (pin and flow path dimensions are the same as those in the full design), was selected for fabrication and test. This Technical Publication summarizes the design and integration of the pumped liquid metal Li flow circuit as of May 1, 2005.

A single chip 2 Gbit/s clock recovery subsystem for digital communications

NASA Astrophysics Data System (ADS)

Hickling, Ronald M.

A self-contained clock recovery/data resynchronizer phase locked loop (PLL) for use in microwave and fiber optic digital communications has been fabricated using GaAs integrated circuit technology. The IC contains the analog and digital components for the PLL: an edge-triggered phase detector based on a 1.2 GHz phase/frequency comparator, an op amp for creating the loop filter, and a VCO based on a differential source-coupled pair amplifier.

The Department of Defense Critical Technologies Plan for the Committees on Armed Services United States Congress

DTIC Science & Technology

1991-05-01

health monitoring , and detection avoidance. Similar to the im!proved ca abi!ities of electr,-.ics with the introduction of the integrated circuit...Sensors not needing to emit signals to detect targets, monitor the environment, or determine 1he status or condition of equipment. 9 Signal & Image... monitoring , and detection avoidance. Photonics R &D will significantly affect the high-speed computing defense iadustrial base through the development of

Direct Digital Demultiplexing of Analog TDM Signals for Cable Reduction in Ultrasound Imaging Catheters

PubMed Central

Carpenter, Thomas M.; Rashid, M. Wasequr; Ghovanloo, Maysam; Cowell, David M. J.; Freear, Steven; Degertekin, F. Levent

2016-01-01

In real-time catheter based 3D ultrasound imaging applications, gathering data from the transducer arrays is difficult as there is a restriction on cable count due to the diameter of the catheter. Although area and power hungry multiplexing circuits integrated at the catheter tip are used in some applications, these are unsuitable for use in small sized catheters for applications like intracardiac imaging. Furthermore, the length requirement for catheters and limited power available to on-chip cable drivers leads to limited signal strength at the receiver end. In this paper an alternative approach using Analog Time Division Multiplexing (TDM) is presented which addresses the cable restrictions of ultrasound catheters. A novel digital demultiplexing technique is also described which allows for a reduction in the number of analog signal processing stages required. The TDM and digital demultiplexing schemes are demonstrated for an intracardiac imaging system that would operate in the 4 MHz to 11 MHz range. A TDM integrated circuit (IC) with 8:1 multiplexer is interfaced with a fast ADC through a micro-coaxial catheter cable bundle, and processed with an FPGA RTL simulation. Input signals to the TDM IC are recovered with −40 dB crosstalk between channels on the same micro-coax, showing the feasibility of this system for ultrasound imaging applications. PMID:27116738

Irreducible incoherence and intelligent design: a look into the conceptual toolbox of a pseudoscience.

PubMed

Boudry, Maarten; Blancke, Stefaan; Braeckman, Johan

2010-12-01

The concept of Irreducible Complexity (IC) has played a pivotal role in the resurgence of the creationist movement over the past two decades. Evolutionary biologists and philosophers have unambiguously rejected the purported demonstration of "intelligent design" in nature, but there have been several, apparently contradictory, lines of criticism. We argue that this is in fact due to Michael Behe's own incoherent definition and use of IC. This paper offers an analysis of several equivocations inherent in the concept of Irreducible Complexity and discusses the way in which advocates of the Intelligent Design Creationism (IDC) have conveniently turned IC into a moving target. An analysis of these rhetorical strategies helps us to understand why IC has gained such prominence in the IDC movement, and why, despite its complete lack of scientific merits, it has even convinced some knowledgeable persons of the impending demise of evolutionary theory.

Automatic Design of Digital Synthetic Gene Circuits

PubMed Central

Marchisio, Mario A.; Stelling, Jörg

2011-01-01

De novo computational design of synthetic gene circuits that achieve well-defined target functions is a hard task. Existing, brute-force approaches run optimization algorithms on the structure and on the kinetic parameter values of the network. However, more direct rational methods for automatic circuit design are lacking. Focusing on digital synthetic gene circuits, we developed a methodology and a corresponding tool for in silico automatic design. For a given truth table that specifies a circuit's input–output relations, our algorithm generates and ranks several possible circuit schemes without the need for any optimization. Logic behavior is reproduced by the action of regulatory factors and chemicals on the promoters and on the ribosome binding sites of biological Boolean gates. Simulations of circuits with up to four inputs show a faithful and unequivocal truth table representation, even under parametric perturbations and stochastic noise. A comparison with already implemented circuits, in addition, reveals the potential for simpler designs with the same function. Therefore, we expect the method to help both in devising new circuits and in simplifying existing solutions. PMID:21399700

Towards Evolving Electronic Circuits for Autonomous Space Applications

NASA Technical Reports Server (NTRS)

Lohn, Jason D.; Haith, Gary L.; Colombano, Silvano P.; Stassinopoulos, Dimitris

2000-01-01

The relatively new field of Evolvable Hardware studies how simulated evolution can reconfigure, adapt, and design hardware structures in an automated manner. Space applications, especially those requiring autonomy, are potential beneficiaries of evolvable hardware. For example, robotic drilling from a mobile platform requires high-bandwidth controller circuits that are difficult to design. In this paper, we present automated design techniques based on evolutionary search that could potentially be used in such applications. First, we present a method of automatically generating analog circuit designs using evolutionary search and a circuit construction language. Our system allows circuit size (number of devices), circuit topology, and device values to be evolved. Using a parallel genetic algorithm, we present experimental results for five design tasks. Second, we investigate the use of coevolution in automated circuit design. We examine fitness evaluation by comparing the effectiveness of four fitness schedules. The results indicate that solution quality is highest with static and co-evolving fitness schedules as compared to the other two dynamic schedules. We discuss these results and offer two possible explanations for the observed behavior: retention of useful information, and alignment of problem difficulty with circuit proficiency.

Parameters Design of Series Resonant Inverter Circuit

NASA Astrophysics Data System (ADS)

Qi, Xingkun; Peng, Yonglong; Li, Yabin

This paper analyzes the main circuit structure of series resonant inverter, and designs the components parameters of the main circuit.That provides a theoretical method for the design of series resonant inverter.

Macromodels of digital integrated circuits for program packages of circuit engineering design

NASA Astrophysics Data System (ADS)

Petrenko, A. I.; Sliusar, P. B.; Timchenko, A. P.

1984-04-01

Various aspects of the generation of macromodels of digital integrated circuits are examined, and their effective application in program packages of circuit engineering design is considered. Three levels of macromodels are identified, and the application of such models to the simulation of circuit outputs is discussed.

Capacitive transducers

NASA Technical Reports Server (NTRS)

Lucifredi, A. L.

1970-01-01

The theory, applications, and possible structural designs of capacitive transducers are presented. Emphasis is placed on the circuits used in connection with the sensors, such as AM, FM, resonant circuits, mode circuits, direct current circuits, and special circuits. Some criteria for selection of a design or the purchase of a commercial device are given.

Petri-net-based 2D design of DNA walker circuits.

PubMed

Gilbert, David; Heiner, Monika; Rohr, Christian

2018-01-01

We consider localised DNA computation, where a DNA strand walks along a binary decision graph to compute a binary function. One of the challenges for the design of reliable walker circuits consists in leakage transitions, which occur when a walker jumps into another branch of the decision graph. We automatically identify leakage transitions, which allows for a detailed qualitative and quantitative assessment of circuit designs, design comparison, and design optimisation. The ability to identify leakage transitions is an important step in the process of optimising DNA circuit layouts where the aim is to minimise the computational error inherent in a circuit while minimising the area of the circuit. Our 2D modelling approach of DNA walker circuits relies on coloured stochastic Petri nets which enable functionality, topology and dimensionality all to be integrated in one two-dimensional model. Our modelling and analysis approach can be easily extended to 3-dimensional walker systems.

Computer-aided design of large-scale integrated circuits - A concept

NASA Technical Reports Server (NTRS)

Schansman, T. T.

1971-01-01

Circuit design and mask development sequence are improved by using general purpose computer with interactive graphics capability establishing efficient two way communications link between design engineer and system. Interactive graphics capability places design engineer in direct control of circuit development.

CMOS analogue amplifier circuits optimisation using hybrid backtracking search algorithm with differential evolution

NASA Astrophysics Data System (ADS)

Mallick, S.; Kar, R.; Mandal, D.; Ghoshal, S. P.

2016-07-01

This paper proposes a novel hybrid optimisation algorithm which combines the recently proposed evolutionary algorithm Backtracking Search Algorithm (BSA) with another widely accepted evolutionary algorithm, namely, Differential Evolution (DE). The proposed algorithm called BSA-DE is employed for the optimal designs of two commonly used analogue circuits, namely Complementary Metal Oxide Semiconductor (CMOS) differential amplifier circuit with current mirror load and CMOS two-stage operational amplifier (op-amp) circuit. BSA has a simple structure that is effective, fast and capable of solving multimodal problems. DE is a stochastic, population-based heuristic approach, having the capability to solve global optimisation problems. In this paper, the transistors' sizes are optimised using the proposed BSA-DE to minimise the areas occupied by the circuits and to improve the performances of the circuits. The simulation results justify the superiority of BSA-DE in global convergence properties and fine tuning ability, and prove it to be a promising candidate for the optimal design of the analogue CMOS amplifier circuits. The simulation results obtained for both the amplifier circuits prove the effectiveness of the proposed BSA-DE-based approach over DE, harmony search (HS), artificial bee colony (ABC) and PSO in terms of convergence speed, design specifications and design parameters of the optimal design of the analogue CMOS amplifier circuits. It is shown that BSA-DE-based design technique for each amplifier circuit yields the least MOS transistor area, and each designed circuit is shown to have the best performance parameters such as gain, power dissipation, etc., as compared with those of other recently reported literature.

Microelectromechanical pump utilizing porous silicon

DOEpatents

Lantz, Jeffrey W [Albuquerque, NM; Stalford, Harold L [Norman, OK

2011-07-19

A microelectromechanical (MEM) pump is disclosed which includes a porous silicon region sandwiched between an inlet chamber and an outlet chamber. The porous silicon region is formed in a silicon substrate and contains a number of pores extending between the inlet and outlet chambers, with each pore having a cross-section dimension about equal to or smaller than a mean free path of a gas being pumped. A thermal gradient is provided along the length of each pore by a heat source which can be an electrical resistance heater or an integrated circuit (IC). A channel can be formed through the silicon substrate so that inlet and outlet ports can be formed on the same side of the substrate, or so that multiple MEM pumps can be connected in series to form a multi-stage MEM pump. The MEM pump has applications for use in gas-phase MEM chemical analysis systems, and can also be used for passive cooling of ICs.

Llamas: Large-area microphone arrays and sensing systems

NASA Astrophysics Data System (ADS)

Sanz-Robinson, Josue

Large-area electronics (LAE) provides a platform to build sensing systems, based on distributing large numbers of densely spaced sensors over a physically-expansive space. Due to their flexible, "wallpaper-like" form factor, these systems can be seamlessly deployed in everyday spaces. They go beyond just supplying sensor readings, but rather they aim to transform the wealth of data from these sensors into actionable inferences about our physical environment. This requires vertically integrated systems that span the entirety of the signal processing chain, including transducers and devices, circuits, and signal processing algorithms. To this end we develop hybrid LAE / CMOS systems, which exploit the complementary strengths of LAE, enabling spatially distributed sensors, and CMOS ICs, providing computational capacity for signal processing. To explore the development of hybrid sensing systems, based on vertical integration across the signal processing chain, we focus on two main drivers: (1) thin-film diodes, and (2) microphone arrays for blind source separation: 1) Thin-film diodes are a key building block for many applications, such as RFID tags or power transfer over non-contact inductive links, which require rectifiers for AC-to-DC conversion. We developed hybrid amorphous / nanocrystalline silicon diodes, which are fabricated at low temperatures (<200 °C) to be compatible with processing on plastic, and have high current densities (5 A/cm2 at 1 V) and high frequency operation (cutoff frequency of 110 MHz). 2) We designed a system for separating the voices of multiple simultaneous speakers, which can ultimately be fed to a voice-command recognition engine for controlling electronic systems. On a device level, we developed flexible PVDF microphones, which were used to create a large-area microphone array. On a circuit level we developed localized a-Si TFT amplifiers, and a custom CMOS IC, for system control, sensor readout and digitization. On a signal processing level we developed an algorithm for blind source separation in a real, reverberant room, based on beamforming and binary masking. It requires no knowledge about the location of the speakers or microphones. Instead, it uses cluster analysis techniques to determine the time delays for beamforming; thus, adapting to the unique acoustic environment of the room.

HDL to verification logic translator

NASA Technical Reports Server (NTRS)

Gambles, J. W.; Windley, P. J.

1992-01-01

The increasingly higher number of transistors possible in VLSI circuits compounds the difficulty in insuring correct designs. As the number of possible test cases required to exhaustively simulate a circuit design explodes, a better method is required to confirm the absence of design faults. Formal verification methods provide a way to prove, using logic, that a circuit structure correctly implements its specification. Before verification is accepted by VLSI design engineers, the stand alone verification tools that are in use in the research community must be integrated with the CAD tools used by the designers. One problem facing the acceptance of formal verification into circuit design methodology is that the structural circuit descriptions used by the designers are not appropriate for verification work and those required for verification lack some of the features needed for design. We offer a solution to this dilemma: an automatic translation from the designers' HDL models into definitions for the higher-ordered logic (HOL) verification system. The translated definitions become the low level basis of circuit verification which in turn increases the designer's confidence in the correctness of higher level behavioral models.

DESIGN METHODOLOGIES AND TOOLS FOR SINGLE-FLUX QUANTUM LOGIC CIRCUITS

DTIC Science & Technology

2017-10-01

DESIGN METHODOLOGIES AND TOOLS FOR SINGLE-FLUX QUANTUM LOGIC CIRCUITS UNIVERSITY OF SOUTHERN CALIFORNIA OCTOBER 2017 FINAL...SUBTITLE DESIGN METHODOLOGIES AND TOOLS FOR SINGLE-FLUX QUANTUM LOGIC CIRCUITS 5a. CONTRACT NUMBER FA8750-15-C-0203 5b. GRANT NUMBER N/A 5c. PROGRAM...of this project was to investigate the state-of-the-art in design and optimization of single-flux quantum (SFQ) logic circuits, e.g., RSFQ and ERSFQ