Corrosion of silicon integrated circuits and lifetime predictions in implantable electronic devices.

PubMed

Vanhoestenberghe, A; Donaldson, N

2013-06-01

Corrosion is a prime concern for active implantable devices. In this paper we review the principles underlying the concepts of hermetic packages and encapsulation, used to protect implanted electronics, some of which remain widely overlooked. We discuss how technological advances have created a need to update the way we evaluate the suitability of both protection methods. We demonstrate how lifetime predictability is lost for very small hermetic packages and introduce a single parameter to compare different packages, with an equation to calculate the minimum sensitivity required from a test method to guarantee a given lifetime. In the second part of this paper, we review the literature on the corrosion of encapsulated integrated circuits (ICs) and, following a new analysis of published data, we propose an equation for the pre-corrosion lifetime of implanted ICs, and discuss the influence of the temperature, relative humidity, encapsulation and field-strength. As any new protection will be tested under accelerated conditions, we demonstrate the sensitivity of acceleration factors to some inaccurately known parameters. These results are relevant for any application of electronics working in a moist environment. Our comparison of encapsulation and hermetic packages suggests that both concepts may be suitable for future implants.

Processing and Prolonged 500 C Testing of 4H-SiC JFET Integrated Circuits with Two Levels of Metal Interconnect

NASA Technical Reports Server (NTRS)

Spry, David J.; Neudeck, Philip G.; Chen, Liangyu; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.; Krasowski, Michael J.; Prokop, Norman F.

2015-01-01

Complex integrated circuit (IC) chips rely on more than one level of interconnect metallization for routing of electrical power and signals. This work reports the processing and testing of 4H-SiC junction field effect transistor (JFET) prototype IC's with two levels of metal interconnect capable of prolonged operation at 500 C. Packaged functional circuits including 3- and 11-stage ring oscillators, a 4-bit digital to analog converter, and a 4-bit address decoder and random access memory cell have been demonstrated at 500 C. A 3-stage oscillator functioned for over 3000 hours at 500 C in air ambient. Improved reproducibility remains to be accomplished.

Commercialisation of CMOS Integrated Circuit Technology in Multi-Electrode Arrays for Neuroscience and Cell-Based Biosensors

PubMed Central

Graham, Anthony H. D.; Robbins, Jon; Bowen, Chris R.; Taylor, John

2011-01-01

The adaptation of standard integrated circuit (IC) technology as a transducer in cell-based biosensors in drug discovery pharmacology, neural interface systems and electrophysiology requires electrodes that are electrochemically stable, biocompatible and affordable. Unfortunately, the ubiquitous Complementary Metal Oxide Semiconductor (CMOS) IC technology does not meet the first of these requirements. For devices intended only for research, modification of CMOS by post-processing using cleanroom facilities has been achieved. However, to enable adoption of CMOS as a basis for commercial biosensors, the economies of scale of CMOS fabrication must be maintained by using only low-cost post-processing techniques. This review highlights the methodologies employed in cell-based biosensor design where CMOS-based integrated circuits (ICs) form an integral part of the transducer system. Particular emphasis will be placed on the application of multi-electrode arrays for in vitro neuroscience applications. Identifying suitable IC packaging methods presents further significant challenges when considering specific applications. The various challenges and difficulties are reviewed and some potential solutions are presented. PMID:22163884

Experimental Durability Testing of 4H SiC JFET Integrated Circuit Technology at 727 C

NASA Technical Reports Server (NTRS)

Spry, David; Neudeck, Phil; Chen, Liangyu; Chang, Carl; Lukco, Dorothy; Beheim, Glenn M

2016-01-01

We have reported SiC integrated circuits (IC's) with two levels of metal interconnect that have demonstrated prolonged operation for thousands of hours at their intended peak ambient operational temperature of 500 C [1, 2]. However, it is recognized that testing of semiconductor microelectronics at temperatures above their designed operating envelope is vital to qualification. Towards this end, we previously reported operation of a 4H-SiC JFET IC ring oscillator on an initial fast thermal ramp test through 727 C [3]. However, this thermal ramp was not ended until a peak temperature of 880 C (well beyond failure) was attained. Further experiments are necessary to better understand failure mechanisms and upper temperature limit of this extreme-temperature capable 4H-SiC IC technology. Here we report on additional experimental testing of custom-packaged 4H-SiC JFET IC devices at temperatures above 500 C. In one test, the temperature was ramped and then held at 727 C, and the devices were periodically measured until electrical failure was observed. A 4H-SiC JFET on this chip electrically functioned with little change for around 25 hours at 727 C before rapid increases in device resistance caused failure. In a second test, devices from our next generation 4H-SiC JFET ICs were ramped up and then held at 700 C (which is below the maximum deposition temperature of the dielectrics). Three ring oscillators functioned for 8 hours at this temperature before degradation. In a third experiment, an alternative die attach of gold paste and package lid was used, and logic circuit operation was demonstrated for 143.5 hours at 700 C.

Experimental Durability Testing of 4H SiC JFET Integrated Circuit Technology at 727 Degrees Centigrade

NASA Technical Reports Server (NTRS)

Spry, David J.; Neudeck, Philip G.; Chen, Liangyu; Chang, Carl W.; Lukco, Dorothy; Beheim, Glenn M.

2016-01-01

We have reported SiC integrated circuits (ICs) with two levels of metal interconnect that have demonstrated prolonged operation for thousands of hours at their intended peak ambient operational temperature of 500 degrees Centigrade. However, it is recognized that testing of semiconductor microelectronics at temperatures above their designed operating envelope is vital to qualification. Towards this end, we previously reported operation of a 4H-SiC JFET IC ring oscillator on an initial fast thermal ramp test through 727 degrees Centigrade. However, this thermal ramp was not ended until a peak temperature of 880 degrees Centigrade (well beyond failure) was attained. Further experiments are necessary to better understand failure mechanisms and upper temperature limit of this extreme-temperature capable 4H-SiC IC technology.Here we report on additional experimental testing of custom-packaged 4H-SiC JFET IC devices at temperatures above 500 degrees Centigrade. In one test, the temperature was ramped and then held at 727 degrees Centigrade, and the devices were periodically measured until electrical failure was observed. A 4H-SiC JFET on this chip electrically functioned with little change for around 25 hours at 727 degrees Centigrade before rapid increases in device resistance caused failure. In a second test, devices from our next generation 4H-SiC JFET ICs were ramped up and then held at 700 degrees Centigrade (which is below the maximum deposition temperature of the dielectrics). Three ring oscillators functioned for 8 hours at this temperature before degradation. In a third experiment, an alternative die attach of gold paste and package lid was used, and logic circuit operation was demonstrated for 143.5 hours at 700 degrees Centigrade.

Capable Copper Electrodeposition Process for Integrated Circuit - substrate Packaging Manufacturing

NASA Astrophysics Data System (ADS)

Ghanbari, Nasrin

This work demonstrates a capable reverse pulse deposition methodology to influence gap fill behavior inside microvia along with a uniform deposit in the fine line patterned regions for substrate packaging applications. Interconnect circuitry in IC substrate packages comprises of stacked microvia that varies in depth from 20microm to 100microm with an aspect ratio of 0.5 to 1.5 and fine line patterns defined by photolithography. Photolithography defined pattern regions incorporate a wide variety of feature sizes including large circular pad structures with diameter of 20microm - 200microm, fine traces with varying widths of 3microm - 30microm and additional planar regions to define a IC substrate package. Electrodeposition of copper is performed to establish the desired circuit. Electrodeposition of copper in IC substrate applications holds certain unique challenges in that they require a low cost manufacturing process that enables a void-free gap fill inside the microvia along with uniform deposition of copper on exposed patterned regions. Deposition time scales to establish the desired metal thickness for such packages could range from several minutes to few hours. This work showcases a reverse pulse electrodeposition methodology that achieves void-free gap fill inside the microvia and uniform plating in FLS (Fine Lines and Spaces) regions with significantly higher deposition rates than traditional approaches. In order to achieve this capability, systematic experimental and simulation studies were performed. A strong correlation of independent parameters that govern the electrodeposition process such as bath temperature, reverse pulse plating parameters and the ratio of electrolyte concentrations is shown to the deposition kinetics and deposition uniformity in fine patterned regions and gap fill rate inside the microvia. Additionally, insight into the physics of via fill process is presented with secondary and tertiary current simulation efforts. Such efforts lead to show "smart" control of deposition rate at the top and bottom of via to avoid void formation. Finally, a parametric effect on grain size and the ensuing copper metallurgical characteristics of bulk copper is also shown to enable high reliability substrate packages for the IC packaging industry.

Neural Implants, Packaging for Biocompatible Implants, and Improving Fabricated Capacitors

NASA Astrophysics Data System (ADS)

Agger, Elizabeth Rose

We have completed the circuit design and packaging procedure for an NIH-funded neural implant, called a MOTE (Microscale Optoelectronically Transduced Electrode). Neural recording implants for mice have greatly advanced neuroscience, but they are often damaging and limited in their recording location. This project will result in free-floating implants that cause less damage, provide rapid electronic recording, and increase range of recording across the cortex. A low-power silicon IC containing amplification and digitization sub-circuits is powered by a dual-function gallium arsenide photovoltaic and LED. Through thin film deposition, photolithography, and chemical and physical etching, the Molnar Group and the McEuen Group (Applied and Engineering Physics department) will package the IC and LED into a biocompatible implant approximately 100microm3. The IC and LED are complete and we have begun refining this packaging procedure in the Cornell NanoScale Science & Technology Facility. ICs with 3D time-resolved imaging capabilities can image microorganisms and other biological samples given proper packaging. A portable, flat, easily manufactured package would enable scientists to place biological samples on slides directly above the Molnar group's imaging chip. We have developed a packaging procedure using laser cutting, photolithography, epoxies, and metal deposition. Using a flip-chip method, we verified the process by aligning and adhering a sample chip to a holder wafer. In the CNF, we have worked on a long-term metal-insulator-metal (MIM) capacitor characterization project. Former Fellow and continuing CNF user Kwame Amponsah developed the original procedure for the capacitor fabrication, and another former fellow, Jonilyn Longenecker, revised the procedure and began the arduous process of characterization. MIM caps are useful to clean room users as testing devices to verify electronic characteristics of their active circuitry. This project's objective is to determine differences in current-voltage (IV) and capacitor-voltage (CV) relationships across variations in capacitor size and dielectric type. This effort requires an approximately 20-step process repeated for two-to-six varieties (dependent on temperature and thermal versus plasma options) of the following dielectrics: HfO2, SiO2, Al2O3, TaOx, and TiO2.

Merging parallel optics packaging and surface mount technologies

NASA Astrophysics Data System (ADS)

Kopp, Christophe; Volpert, Marion; Routin, Julien; Bernabé, Stéphane; Rossat, Cyrille; Tournaire, Myriam; Hamelin, Régis

2008-02-01

Optical links are well known to present significant advantages over electrical links for very high-speed data rate at 10Gpbs and above per channel. However, the transition towards optical interconnects solutions for short and very short reach applications requires the development of innovative packaging solutions that would deal with very high volume production capability and very low cost per unit. Moreover, the optoelectronic transceiver components must be able to move from the edge to anywhere on the printed circuit board, for instance close to integrated circuits with high speed IO. In this paper, we present an original packaging design to manufacture parallel optic transceivers that are surface mount devices. The package combines highly integrated Multi-Chip-Module on glass and usual IC ceramics packaging. The use of ceramic and the development of sealing technologies achieve hermetic requirements. Moreover, thanks to a chip scale package approach the final device exhibits a much minimized footprint. One of the main advantages of the package is its flexibility to be soldered or plugged anywhere on the printed circuit board as any other electronic device. As a demonstrator we present a 2 by 4 10Gbps transceiver operating at 850nm.

Stitch-bond parallel-gap welding for IC circuits

NASA Technical Reports Server (NTRS)

Chvostal, P.; Tuttle, J.; Vanderpool, R.

1980-01-01

Stitch-bonded flatpacks are superior to soldered dual-in-lines where size, weight, and reliability are important. Results should interest designers of packaging for complex high-reliability electronics, such as that used in security systems, industrial process control, and vehicle electronics.

Thin glass based packaging and photonic single-mode waveguide integration by ion-exchange technology on board and module level

NASA Astrophysics Data System (ADS)

Brusberg, Lars; Lang, Günter; Schröder, Henning

2011-01-01

The proposed novel packaging approach merges micro-system packaging and glass integrated optics. It provides 3D optical single-mode intra system links to bridge the gap between novel photonic integrated circuits and the glass fibers for inter system interconnects. We introduce our hybrid 3D photonic packaging approach based on thin glass substrates with planar integrated optical single-mode waveguides for fiber-to-chip and chip-to-chip links. Optical mirrors and lenses provide optical mode matching for photonic IC assemblies and optical fiber interconnects. Thin glass is commercially available in panel and wafer formats and characterizes excellent optical and high-frequency properties as reviewed in the paper. That makes it perfect for micro-system packaging. The adopted planar waveguide process based on ion-exchange technology is capable for high-volume manufacturing. This ion-exchange process and the optical propagation are described in detail for thin glass substrates. An extensive characterization of all basic circuit elements like straight and curved waveguides, couplers and crosses proves the low attenuation of the optical circuit elements.

Low temperature co-fired ceramic packaging of CMOS capacitive sensor chip towards cell viability monitoring.

PubMed

Halonen, Niina; Kilpijärvi, Joni; Sobocinski, Maciej; Datta-Chaudhuri, Timir; Hassinen, Antti; Prakash, Someshekar B; Möller, Peter; Abshire, Pamela; Kellokumpu, Sakari; Lloyd Spetz, Anita

2016-01-01

Cell viability monitoring is an important part of biosafety evaluation for the detection of toxic effects on cells caused by nanomaterials, preferably by label-free, noninvasive, fast, and cost effective methods. These requirements can be met by monitoring cell viability with a capacitance-sensing integrated circuit (IC) microchip. The capacitance provides a measurement of the surface attachment of adherent cells as an indication of their health status. However, the moist, warm, and corrosive biological environment requires reliable packaging of the sensor chip. In this work, a second generation of low temperature co-fired ceramic (LTCC) technology was combined with flip-chip bonding to provide a durable package compatible with cell culture. The LTCC-packaged sensor chip was integrated with a printed circuit board, data acquisition device, and measurement-controlling software. The packaged sensor chip functioned well in the presence of cell medium and cells, with output voltages depending on the medium above the capacitors. Moreover, the manufacturing of microfluidic channels in the LTCC package was demonstrated.

Nano-engineered Multiwall Carbon Nanotube-copper Composite Thermal Interface Material for Efficient Heat Conduction

NASA Technical Reports Server (NTRS)

Ngo, Quoc; Cruden, Brett A.; Cassell, Alan M.; Sims, Gerard; Li, Jun; Meyyappa, M.; Yang, Cary Y.

2005-01-01

Efforts in integrated circuit (IC) packaging technologies have recently been focused on management of increasing heat density associated with high frequency and high density circuit designs. While current flip-chip package designs can accommodate relatively high amounts of heat density, new materials need to be developed to manage thermal effects of next-generation integrated circuits. Multiwall carbon nanotubes (MWNT) have been shown to significantly enhance thermal conduction in the axial direction and thus can be considered to be a candidate for future thermal interface materials by facilitating efficient thermal transport. This work focuses on fabrication and characterization of a robust MWNT-copper composite material as an element in IC package designs. We show that using vertically aligned MWNT arrays reduces interfacial thermal resistance by increasing conduction surface area, and furthermore, the embedded copper acts as a lateral heat spreader to efficiently disperse heat, a necessary function for packaging materials. In addition, we demonstrate reusability of the material, and the absence of residue on the contacting material, both novel features of the MWNT-copper composite that are not found in most state-of-the-art thermal interface materials. Electrochemical methods such as metal deposition and etch are discussed for the creation of the MWNT-Cu composite, detailing issues and observations with using such methods. We show that precise engineering of the composite surface affects the ability of this material to act as an efficient thermal interface material. A thermal contact resistance measurement has been designed to obtain a value of thermal contact resistance for a variety of different thermal contact materials.

Standard semiconductor packaging for high-reliability low-cost MEMS applications

NASA Astrophysics Data System (ADS)

Harney, Kieran P.

2005-01-01

Microelectronic packaging technology has evolved over the years in response to the needs of IC technology. The fundamental purpose of the package is to provide protection for the silicon chip and to provide electrical connection to the circuit board. Major change has been witnessed in packaging and today wafer level packaging technology has further revolutionized the industry. MEMS (Micro Electro Mechanical Systems) technology has created new challenges for packaging that do not exist in standard ICs. However, the fundamental objective of MEMS packaging is the same as traditional ICs, the low cost and reliable presentation of the MEMS chip to the next level interconnect. Inertial MEMS is one of the best examples of the successful commercialization of MEMS technology. The adoption of MEMS accelerometers for automotive airbag applications has created a high volume market that demands the highest reliability at low cost. The suppliers to these markets have responded by exploiting standard semiconductor packaging infrastructures. However, there are special packaging needs for MEMS that cannot be ignored. New applications for inertial MEMS devices are emerging in the consumer space that adds the imperative of small size to the need for reliability and low cost. These trends are not unique to MEMS accelerometers. For any MEMS technology to be successful the packaging must provide the basic reliability and interconnection functions, adding the least possible cost to the product. This paper will discuss the evolution of MEMS packaging in the accelerometer industry and identify the main issues that needed to be addressed to enable the successful commercialization of the technology in the automotive and consumer markets.

Standard semiconductor packaging for high-reliability low-cost MEMS applications

NASA Astrophysics Data System (ADS)

Harney, Kieran P.

2004-12-01

Microelectronic packaging technology has evolved over the years in response to the needs of IC technology. The fundamental purpose of the package is to provide protection for the silicon chip and to provide electrical connection to the circuit board. Major change has been witnessed in packaging and today wafer level packaging technology has further revolutionized the industry. MEMS (Micro Electro Mechanical Systems) technology has created new challenges for packaging that do not exist in standard ICs. However, the fundamental objective of MEMS packaging is the same as traditional ICs, the low cost and reliable presentation of the MEMS chip to the next level interconnect. Inertial MEMS is one of the best examples of the successful commercialization of MEMS technology. The adoption of MEMS accelerometers for automotive airbag applications has created a high volume market that demands the highest reliability at low cost. The suppliers to these markets have responded by exploiting standard semiconductor packaging infrastructures. However, there are special packaging needs for MEMS that cannot be ignored. New applications for inertial MEMS devices are emerging in the consumer space that adds the imperative of small size to the need for reliability and low cost. These trends are not unique to MEMS accelerometers. For any MEMS technology to be successful the packaging must provide the basic reliability and interconnection functions, adding the least possible cost to the product. This paper will discuss the evolution of MEMS packaging in the accelerometer industry and identify the main issues that needed to be addressed to enable the successful commercialization of the technology in the automotive and consumer markets.

Radiation Testing and Evaluation Issues for Modern Integrated Circuits

NASA Technical Reports Server (NTRS)

LaBel, Kenneth A.; Cohn, Lew M.

2005-01-01

Abstract. Changes in modern integrated circuit (IC) technologies have modified the way we approach and conduct radiation tolerance and testing of electronics. These changes include scaling of geometries, new materials, new packaging technologies, and overall speed and device complexity challenges. In this short course section, we will identify and discuss these issues as they impact radiation testing, modeling, and effects mitigation of modern integrated circuits. The focus will be on CMOS-based technologies, however, other high performance technologies will be discussed where appropriate. The effects of concern will be: Single-Event Effects (SEE) and steady state total ionizing dose (TID) IC response. However, due to the growing use of opto-electronics in space systems issues concerning displacement damage testing will also be considered. This short course section is not intended to provide detailed "how-to-test" information, but simply provide a snapshot of current challenges and some of the approaches being considered.

TDR method for determine IC's parameters

NASA Astrophysics Data System (ADS)

Timoshenkov, V.; Rodionov, D.; Khlybov, A.

2016-12-01

Frequency domain simulation is a widely used approach for determine integrated circuits parameters. This approach can be found in most of software tools used in IC industry. Time domain simulation approach shows intensive usage last years due to some advantages. In particular it applicable for analysis of nonlinear and nonstationary systems where frequency domain is inapplicable. Resolution of time domain systems allow see heterogeneities on distance 1mm, determine it parameters and properties. Authors used approach based on detecting reflected signals from heterogeneities - time domain reflectometry (TDR). Field effect transistor technology scaling up to 30-60nm gate length and 10nm gate dielectric, heterojunction bi-polar transistors with 10-30nm base width allows fabricate digital IC's with 20GHz clock frequency and RF-IC's with tens GHz bandwidth. Such devices and operation speed suppose transit signal by use microwave lines. There are local heterogeneities can be found inside of the signal path due to connections between different parts of signal lines (stripe line-RF-connector pin, stripe line - IC package pin). These heterogeneities distort signals that cause bandwidth decrease for RF-devices. Time domain research methods of transmission and reflected signals give the opportunities to determine heterogeneities, it properties, parameters and built up equivalent circuits. Experimental results are provided and show possibility for inductance and capacitance measurement up to 25GHz. Measurements contains result of signal path research on IC and printed circuit board (PCB) used for 12GHz RF chips. Also dielectric constant versus frequency was measured up to 35GHz.

Quality control and authentication of packaged integrated circuits using enhanced-spatial-resolution terahertz time-domain spectroscopy and imaging

NASA Astrophysics Data System (ADS)

Ahi, Kiarash; Shahbazmohamadi, Sina; Asadizanjani, Navid

2018-05-01

In this paper, a comprehensive set of techniques for quality control and authentication of packaged integrated circuits (IC) using terahertz (THz) time-domain spectroscopy (TDS) is developed. By material characterization, the presence of unexpected materials in counterfeit components is revealed. Blacktopping layers are detected using THz time-of-flight tomography, and thickness of hidden layers is measured. Sanded and contaminated components are detected by THz reflection-mode imaging. Differences between inside structures of counterfeit and authentic components are revealed through developing THz transmission imaging. For enabling accurate measurement of features by THz transmission imaging, a novel resolution enhancement technique (RET) has been developed. This RET is based on deconvolution of the THz image and the THz point spread function (PSF). The THz PSF is mathematically modeled through incorporating the spectrum of the THz imaging system, the axis of propagation of the beam, and the intensity extinction coefficient of the object into a Gaussian beam distribution. As a result of implementing this RET, the accuracy of the measurements on THz images has been improved from 2.4 mm to 0.1 mm and bond wires as small as 550 μm inside the packaging of the ICs are imaged.

On-Die Sensors for Transient Events

NASA Astrophysics Data System (ADS)

Suchak, Mihir Vimal

Failures caused by transient electromagnetic events like Electrostatic Discharge (ESD) are a major concern for embedded systems. The component often failing is an integrated circuit (IC). Determining which IC is affected in a multi-device system is a challenging task. Debugging errors often requires sophisticated lab setups which require intentionally disturbing and probing various parts of the system which might not be easily accessible. Opening the system and adding probes may change its response to the transient event, which further compounds the problem. On-die transient event sensors were developed that require relatively little area on die, making them inexpensive, they consume negligible static current, and do not interfere with normal operation of the IC. These circuits can be used to determine the pin involved and the level of the event in the event of a transient event affecting the IC, thus allowing the user to debug system-level transient events without modifying the system. The circuit and detection scheme design has been completed and verified in simulations with Cadence Virtuoso environment. Simulations accounted for the impact of the ESD protection circuits, parasitics from the I/O pin, package and I/O ring, and included a model of an ESD gun to test the circuit's response to an ESD pulse as specified in IEC 61000-4-2. Multiple detection schemes are proposed. The final detection scheme consists of an event detector and a level sensor. The event detector latches on the presence of an event at a pad, to determine on which pin an event occurred. The level sensor generates current proportional to the level of the event. This current is converted to a voltage and digitized at the A/D converter to be read by the microprocessor. Detection scheme shows good performance in simulations when checked against process variations and different kind of events.

Wide-temperature integrated operational amplifier

NASA Technical Reports Server (NTRS)

Mojarradi, Mohammad (Inventor); Levanas, Greg (Inventor); Chen, Yuan (Inventor); Cozy, Raymond S. (Inventor); Greenwell, Robert (Inventor); Terry, Stephen (Inventor); Blalock, Benjamin J. (Inventor)

2009-01-01

The present invention relates to a reference current circuit. The reference circuit comprises a low-level current bias circuit, a voltage proportional-to-absolute temperature generator for creating a proportional-to-absolute temperature voltage (VPTAT), and a MOSFET-based constant-IC regulator circuit. The MOSFET-based constant-IC regulator circuit includes a constant-IC input and constant-IC output. The constant-IC input is electrically connected with the VPTAT generator such that the voltage proportional-to-absolute temperature is the input into the constant-IC regulator circuit. Thus the constant-IC output maintains the constant-IC ratio across any temperature range.

Equivalent radiation source of 3D package for electromagnetic characteristics analysis

NASA Astrophysics Data System (ADS)

Li, Jun; Wei, Xingchang; Shu, Yufei

2017-10-01

An equivalent radiation source method is proposed to characterize electromagnetic emission and interference of complex three dimensional integrated circuits (IC) in this paper. The method utilizes amplitude-only near-field scanning data to reconstruct an equivalent magnetic dipole array, and the differential evolution optimization algorithm is proposed to extract the locations, orientation and moments of those dipoles. By importing the equivalent dipoles model into a 3D full-wave simulator together with the victim circuit model, the electromagnetic interference issues in mixed RF/digital systems can be well predicted. A commercial IC is used to validate the accuracy and efficiency of this proposed method. The coupled power at the victim antenna port calculated by the equivalent radiation source is compared with the measured data. Good consistency is obtained which confirms the validity and efficiency of the method. Project supported by the National Nature Science Foundation of China (No. 61274110).

Electro-Microfluidic Packaging

NASA Astrophysics Data System (ADS)

Benavides, G. L.; Galambos, P. C.

2002-06-01

There are many examples of electro-microfluidic products that require cost effective packaging solutions. Industry has responded to a demand for products such as drop ejectors, chemical sensors, and biological sensors. Drop ejectors have consumer applications such as ink jet printing and scientific applications such as patterning self-assembled monolayers or ejecting picoliters of expensive analytes/reagents for chemical analysis. Drop ejectors can be used to perform chemical analysis, combinatorial chemistry, drug manufacture, drug discovery, drug delivery, and DNA sequencing. Chemical and biological micro-sensors can sniff the ambient environment for traces of dangerous materials such as explosives, toxins, or pathogens. Other biological sensors can be used to improve world health by providing timely diagnostics and applying corrective measures to the human body. Electro-microfluidic packaging can easily represent over fifty percent of the product cost and, as with Integrated Circuits (IC), the industry should evolve to standard packaging solutions. Standard packaging schemes will minimize cost and bring products to market sooner.

Thermally-induced voltage alteration for integrated circuit analysis

DOEpatents

Cole, Jr., Edward I.

2000-01-01

A thermally-induced voltage alteration (TIVA) apparatus and method are disclosed for analyzing an integrated circuit (IC) either from a device side of the IC or through the IC substrate to locate any open-circuit or short-circuit defects therein. The TIVA apparatus uses constant-current biasing of the IC while scanning a focused laser beam over electrical conductors (i.e. a patterned metallization) in the IC to produce localized heating of the conductors. This localized heating produces a thermoelectric potential due to the Seebeck effect in any conductors with open-circuit defects and a resistance change in any conductors with short-circuit defects, both of which alter the power demand by the IC and thereby change the voltage of a source or power supply providing the constant-current biasing. By measuring the change in the supply voltage and the position of the focused and scanned laser beam over time, any open-circuit or short-circuit defects in the IC can be located and imaged. The TIVA apparatus can be formed in part from a scanning optical microscope, and has applications for qualification testing or failure analysis of ICs.

Three-Dimensional Integrated Circuit (3D IC) Key Technology: Through-Silicon Via (TSV).

PubMed

Shen, Wen-Wei; Chen, Kuan-Neng

2017-12-01

3D integration with through-silicon via (TSV) is a promising candidate to perform system-level integration with smaller package size, higher interconnection density, and better performance. TSV fabrication is the key technology to permit communications between various strata of the 3D integration system. TSV fabrication steps, such as etching, isolation, metallization processes, and related failure modes, as well as other characterizations are discussed in this invited review paper.

Integrated circuit failure analysis by low-energy charge-induced voltage alteration

DOEpatents

Cole, E.I. Jr.

1996-06-04

A scanning electron microscope apparatus and method are described for detecting and imaging open-circuit defects in an integrated circuit (IC). The invention uses a low-energy high-current focused electron beam that is scanned over a device surface of the IC to generate a charge-induced voltage alteration (CIVA) signal at the location of any open-circuit defects. The low-energy CIVA signal may be used to generate an image of the IC showing the location of any open-circuit defects. A low electron beam energy is used to prevent electrical breakdown in any passivation layers in the IC and to minimize radiation damage to the IC. The invention has uses for IC failure analysis, for production-line inspection of ICs, and for qualification of ICs. 5 figs.

Integrated circuit failure analysis by low-energy charge-induced voltage alteration

DOEpatents

Cole, Jr., Edward I.

1996-01-01

A scanning electron microscope apparatus and method are described for detecting and imaging open-circuit defects in an integrated circuit (IC). The invention uses a low-energy high-current focused electron beam that is scanned over a device surface of the IC to generate a charge-induced voltage alteration (CIVA) signal at the location of any open-circuit defects. The low-energy CIVA signal may be used to generate an image of the IC showing the location of any open-circuit defects. A low electron beam energy is used to prevent electrical breakdown in any passivation layers in the IC and to minimize radiation damage to the IC. The invention has uses for IC failure analysis, for production-line inspection of ICs, and for qualification of ICs.

The National Si-Soft Project

NASA Astrophysics Data System (ADS)

Chang, Chun-Yen; Trappey, Charles V.

2003-06-01

Taiwan's electronics industry emerged in the 1960s with the creation of a small but well planned integrated circuit (IC) packaging industry. This industry investment led to bolder investments in research, laboratories, and the island's first semiconductor foundries in the 1980s. Following the success of the emerging IC manufacturers and design houses, hundreds of service firms and related industries (software, legal services, substrate, chemical, and test firms among others) opened for business and completed Taiwan's IC manufacturing supply chain. The challenge for Taiwan's electronics industry is to take the lead in the design, manufacture, and marketing of name brand electronic products. This paper introduces the Si-Soft (silicon software) Project, a national initiative that builds on Taiwan's achievements in manufacturing (referred to as Si-Hard or silicon hardware) to launch a new wave of companies. These firms will contribute to the core underlying technology (intellectual property) used in the creation of electronic products.

A Study of Direct Digital Manufactured RF/Microwave Packaging

NASA Astrophysics Data System (ADS)

Stratton, John W. I.

Various facets of direct digital manufactured (DDM) microwave packages are studied. The rippled surface inherent in fused deposition modeling (FDM) fabricated geometries is modeled in Ansoft HFSS, and its effect on the performance of microstrip transmission lines is assessed via simulation and measurement. The thermal response of DDM microstrip transmission lines is analyzed over a range of RF input powers, and linearity is confirmed over that range. Two IC packages are embedded into DDM printed circuit boards, and their performance is analyzed. The first is a low power RF switch, and the second is an RF front end device that includes a low noise amplifier (LNA) and a power amplifier (PA). The RF switch is shown to perform well, as compared to a layout designed for a Rogers 4003C microwave laminate substrate. The LNA performs within datasheet specifications. The power amplifier generates substantial heat, so a thermal management attempt is described. Finally, a capacitively loaded 6dB Wilkinson power divider is designed and fabricated using DDM techniques and materials. Its performance is analyzed and compared to simulation. The device is shown to compare favorably to a similar device fabricated on a Rogers 4003C microwave laminate using traditional printed circuit board techniques.

A battery-free multichannel digital neural/EMG telemetry system for flying insects.

PubMed

Thomas, Stewart J; Harrison, Reid R; Leonardo, Anthony; Reynolds, Matthew S

2012-10-01

This paper presents a digital neural/EMG telemetry system small enough and lightweight enough to permit recording from insects in flight. It has a measured flight package mass of only 38 mg. This system includes a single-chip telemetry integrated circuit (IC) employing RF power harvesting for battery-free operation, with communication via modulated backscatter in the UHF (902-928 MHz) band. An on-chip 11-bit ADC digitizes 10 neural channels with a sampling rate of 26.1 kSps and 4 EMG channels at 1.63 kSps, and telemeters this data wirelessly to a base station. The companion base station transceiver includes an RF transmitter of +36 dBm (4 W) output power to wirelessly power the telemetry IC, and a digital receiver with a sensitivity of -70 dBm for 10⁻⁵ BER at 5.0 Mbps to receive the data stream from the telemetry IC. The telemetry chip was fabricated in a commercial 0.35 μ m 4M1P (4 metal, 1 poly) CMOS process. The die measures 2.36 × 1.88 mm, is 250 μm thick, and is wire bonded into a flex circuit assembly measuring 4.6 × 6.8 mm.

Protective Socket For Integrated Circuits

NASA Technical Reports Server (NTRS)

Wilkinson, Chris; Henegar, Greg

1988-01-01

Socket for intergrated circuits (IC's) protects from excessive voltages and currents or from application of voltages and currents in wrong sequence during insertion or removal. Contains built-in switch that opens as IC removed, disconnecting leads from signals and power. Also protects other components on circuit board from transients produced by insertion and removal of IC. Makes unnecessary to turn off power to entire circuit board so other circuits on board continue to function.

Nonlinear system analysis in bipolar integrated circuits

NASA Astrophysics Data System (ADS)

Fang, T. F.; Whalen, J. J.

1980-01-01

Since analog bipolar integrated circuits (IC's) have become important components in modern communication systems, the study of the Radio Frequency Interference (RFI) effects in bipolar IC amplifiers is an important subject for electromagnetic compatibility (EMC) engineering. The investigation has focused on using the nonlinear circuit analysis program (NCAP) to predict RF demodulation effects in broadband bipolar IC amplifiers. The audio frequency (AF) voltage at the IC amplifier output terminal caused by an amplitude modulated (AM) RF signal at the IC amplifier input terminal was calculated and compared to measured values. Two broadband IC amplifiers were investigated: (1) a cascode circuit using a CA3026 dual differential pair; (2) a unity gain voltage follower circuit using a micro A741 operational amplifier (op amp). Before using NCAP for RFI analysis, the model parameters for each bipolar junction transistor (BJT) in the integrated circuit were determined. Probe measurement techniques, manufacturer's data, and other researcher's data were used to obtain the required NCAP BJT model parameter values. An important contribution included in this effort is a complete set of NCAP BJT model parameters for most of the transistor types used in linear IC's.

Use of optical technique for inspection of warpage of IC packages

NASA Astrophysics Data System (ADS)

Toh, Siew-Lok; Chau, Fook S.; Ong, Sim Heng

2001-06-01

The packaging of IC packages has changed over the years, form dual-in-line, wire-bond, and pin-through-hole in printed wiring board technologies in the 1970s to ball grid array, chip scale and surface mount technologies in the 1990s. Reliability has been a big problem for manufacturers for some moisture-sensitive packages. One of the potential problems in plastic IC packages is moisture-induced popcorn effect which can arise during the reflow process. Shearography is a non-destructive inspection technique that may be used to detect the delamination and warpage of IC packages. It is non-contacting and permits a full-field observation of surface displacement derivatives. Another advantage of this technique is that it is able to give the real-time formation of the fringes which indicate flaws in the IC package under real-time simulation condition of Surface Mount Technology (SMT) IR reflow profile. It is extremely fast and convenient to study the true behavior of the packaging deformation during the SMT process. It can be concluded that shearography has the potential for the real- time detection, in situ and non-destructive inspection of IC packages during the surface mount process.

System-on-Chip Considerations for Heterogeneous Integration of CMOS and Fluidic Bio-Interfaces.

PubMed

Datta-Chaudhuri, Timir; Smela, Elisabeth; Abshire, Pamela A

2016-12-01

CMOS chips are increasingly used for direct sensing and interfacing with fluidic and biological systems. While many biosensing systems have successfully combined CMOS chips for readout and signal processing with passive sensing arrays, systems that co-locate sensing with active circuits on a single chip offer significant advantages in size and performance but increase the complexity of multi-domain design and heterogeneous integration. This emerging class of lab-on-CMOS systems also poses distinct and vexing technical challenges that arise from the disparate requirements of biosensors and integrated circuits (ICs). Modeling these systems must address not only circuit design, but also the behavior of biological components on the surface of the IC and any physical structures. Existing tools do not support the cross-domain simulation of heterogeneous lab-on-CMOS systems, so we recommend a two-step modeling approach: using circuit simulation to inform physics-based simulation, and vice versa. We review the primary lab-on-CMOS implementation challenges and discuss practical approaches to overcome them. Issues include new versions of classical challenges in system-on-chip integration, such as thermal effects, floor-planning, and signal coupling, as well as new challenges that are specifically attributable to biological and fluidic domains, such as electrochemical effects, non-standard packaging, surface treatments, sterilization, microfabrication of surface structures, and microfluidic integration. We describe these concerns as they arise in lab-on-CMOS systems and discuss solutions that have been experimentally demonstrated.

R&D100: IC ID

ScienceCinema

Hamlet, Jason; Pierson, Lyndon; Bauer, Todd

2018-06-25

Supply chain security to detect, deter, and prevent the counterfeiting of networked and stand-alone integrated circuits (ICs) is critical to cyber security. Sandia National Laboratory researchers have developed IC ID to leverage Physically Unclonable Functions (PUFs) and strong cryptographic authentication to create a unique fingerprint for each integrated circuit. IC ID assures the authenticity of ICs to prevent tampering or malicious substitution.

Cost optimization in low volume VLSI circuits

NASA Technical Reports Server (NTRS)

Cook, K. B., Jr.; Kerns, D. V., Jr.

1982-01-01

The relationship of integrated circuit (IC) cost to electronic system cost is developed using models for integrated circuit cost which are based on design/fabrication approach. Emphasis is on understanding the relationship between cost and volume for custom circuits suitable for NASA applications. In this report, reliability is a major consideration in the models developed. Results are given for several typical IC designs using off the shelf, full custom, and semicustom IC's with single and double level metallization.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hamlet, Jason; Pierson, Lyndon; Bauer, Todd

Supply chain security to detect, deter, and prevent the counterfeiting of networked and stand-alone integrated circuits (ICs) is critical to cyber security. Sandia National Laboratory researchers have developed IC ID to leverage Physically Unclonable Functions (PUFs) and strong cryptographic authentication to create a unique fingerprint for each integrated circuit. IC ID assures the authenticity of ICs to prevent tampering or malicious substitution.

Light-induced voltage alteration for integrated circuit analysis

DOEpatents

Cole, Jr., Edward I.; Soden, Jerry M.

1995-01-01

An apparatus and method are described for analyzing an integrated circuit (IC), The invention uses a focused light beam that is scanned over a surface of the IC to generate a light-induced voltage alteration (LIVA) signal for analysis of the IC, The LIVA signal may be used to generate an image of the IC showing the location of any defects in the IC; and it may be further used to image and control the logic states of the IC. The invention has uses for IC failure analysis, for the development of ICs, for production-line inspection of ICs, and for qualification of ICs.

Light-induced voltage alteration for integrated circuit analysis

DOEpatents

Cole, E.I. Jr.; Soden, J.M.

1995-07-04

An apparatus and method are described for analyzing an integrated circuit (IC). The invention uses a focused light beam that is scanned over a surface of the IC to generate a light-induced voltage alteration (LIVA) signal for analysis of the IC. The LIVA signal may be used to generate an image of the IC showing the location of any defects in the IC; and it may be further used to image and control the logic states of the IC. The invention has uses for IC failure analysis, for the development of ICs, for production-line inspection of ICs, and for qualification of ICs. 18 figs.

Using NCAP to predict RFI effects in linear bipolar integrated circuits

NASA Astrophysics Data System (ADS)

Fang, T.-F.; Whalen, J. J.; Chen, G. K. C.

1980-11-01

Applications of the Nonlinear Circuit Analysis Program (NCAP) to calculate RFI effects in electronic circuits containing discrete semiconductor devices have been reported upon previously. The objective of this paper is to demonstrate that the computer program NCAP also can be used to calcuate RFI effects in linear bipolar integrated circuits (IC's). The IC's reported upon are the microA741 operational amplifier (op amp) which is one of the most widely used IC's, and a differential pair which is a basic building block in many linear IC's. The microA741 op amp was used as the active component in a unity-gain buffer amplifier. The differential pair was used in a broad-band cascode amplifier circuit. The computer program NCAP was used to predict how amplitude-modulated RF signals are demodulated in the IC's to cause undesired low-frequency responses. The predicted and measured results for radio frequencies in the 0.050-60-MHz range are in good agreement.

Heart-Rate and Breath-Rate Monitor

NASA Technical Reports Server (NTRS)

Cooper, T. G.

1983-01-01

Circuit requiring only four integrated circuits (IC's) measures both heart rate and breath rate. Phase-locked loops lock on heart-rate and respiration-rate input signals. Each loop IC contains two phase comparators. Positive-edge-triggered circuit used in making monitors insensitive to dutycycle variations.

A proposed holistic approach to on-chip, off-chip, test, and package interconnections

NASA Astrophysics Data System (ADS)

Bartelink, Dirk J.

1998-11-01

The term interconnection has traditionally implied a `robust' connection from a transistor or a group of transistors in an IC to the outside world, usually a PC board. Optimum system utilization is done from outside the IC. As an alternative, this paper addresses `unimpeded' transistor-to-transistor interconnection aimed at reaching the high circuit densities and computational capabilities of neighboring IC's. In this view, interconnections are not made to some human-centric place outside the IC world requiring robustness—except for system input and output connections. This unimpeded interconnect style is currently available only through intra-chip signal traces in `system-on-a-chip' implementations, as exemplified by embedded DRAMs. Because the traditional off-chip penalty in performance and wiring density is so large, a merging of complex process technologies is the only option today. It is suggested that, for system integration to move forward, the traditional robustness requirement inherited from conventional packaging interconnect and IC manufacturing test must be discarded. Traditional system assembly from vendor parts requires robustness under shipping, inspection and assembly. The trend toward systems on a chip signifies willingness by semiconductor companies to design and fabricate whole systems in house, so that `in-house' chip-to-chip assembly is not beyond reach. In this scenario, bare chips never leave the controlled environment of the IC fabricator while the two major contributors to off-chip signal penalty, ESD protection and the need to source a 50-ohm test head, are avoided. With in-house assembly, ESD protection can be eliminated with the precautions already familiar in plasma etching. Test interconnection impacts the fundamentals of IC manufacturing, particularly with clock speeds approaching 1GHz, and cannot be an afterthought. It should be an integral part of the chip-to-chip interconnection bandwidth optimization, because—as we must recognize—test is also performed using IC's. A system interconnection is proposed using multiple chips fabricated with conventional silicon processes, including MEMS technology. The system resembles an MCM that can be joined without committing to final assembly to perform at-speed testing. 50-Ohm test probes never load the circuit; only intended neighboring chips are ever connected. A `back-plane' chip provides the connection layers for both inter- and intra-chip signals and also serves as the probe card, in analogy with membrane probes now used for single-chip testing. Intra-chip connections, which require complicated connections during test that exactly match the product, are then properly made and all waveforms and loading conditions under test will be identical to those of the product. The major benefit is that all front-end chip technologies can be merged—logic, memory, RF, even passives. ESD protection is required only on external system connections. Manufacturing test information will accurately characterize process faults and thus avoid the Known-Good-Die problem that has slowed the arrival of conventional MCM's.

Experimental investigation on the thermal performance of Si micro-heat pipe with different cross-sections

NASA Astrophysics Data System (ADS)

Hamidnia, Mohammad; Luo, Yi; Wang, Xiaodong; Li, Congming

2017-10-01

Increasing component densities of the integrated circuit (IC) and packaging levels has led to thermal management problems. Si substrates with embedded micro-heat pipes (MHPs) couple good thermal characteristics and cost savings associated with IC batch processing. The thermal performance of MHP is intimately related to the cross-sectional geometry. Different cross-sections are designed in order to enhance the backflow of working fluid. In this experimental study, three different Si MHPs with same hydraulic diameter and various cross-sections are fabricated by micro-fabrication methods and tested under different conditions of fluid charge ratios. The results show that the trapezoidal MHP associated with rectangular artery which is charged with 40% of vapor chamber’s volume has the best thermal performance. This silicon-based MHP is a passive approach for thermal management, which could widen applications in the commercial electronics industry and LED lightings.

Healing Voids In Interconnections In Integrated Circuits

NASA Technical Reports Server (NTRS)

Cuddihy, Edward F.; Lawton, Russell A.; Gavin, Thomas

1989-01-01

Unusual heat treatment heals voids in aluminum interconnections on integrated circuits (IC's). Treatment consists of heating IC to temperature between 200 degrees C and 400 degrees C, holding it at that temperature, and then plunging IC immediately into liquid nitrogen. Typical holding time at evaluated temperature is 30 minutes.

Ion-beam apparatus and method for analyzing and controlling integrated circuits

DOEpatents

Campbell, A.N.; Soden, J.M.

1998-12-01

An ion-beam apparatus and method for analyzing and controlling integrated circuits are disclosed. The ion-beam apparatus comprises a stage for holding one or more integrated circuits (ICs); a source means for producing a focused ion beam; and a beam-directing means for directing the focused ion beam to irradiate a predetermined portion of the IC for sufficient time to provide an ion-beam-generated electrical input signal to a predetermined element of the IC. The apparatus and method have applications to failure analysis and developmental analysis of ICs and permit an alteration, control, or programming of logic states or device parameters within the IC either separate from or in combination with applied electrical stimulus to the IC for analysis thereof. Preferred embodiments of the present invention including a secondary particle detector and an electron floodgun further permit imaging of the IC by secondary ions or electrons, and allow at least a partial removal or erasure of the ion-beam-generated electrical input signal. 4 figs.

Ion-beam apparatus and method for analyzing and controlling integrated circuits

DOEpatents

Campbell, Ann N.; Soden, Jerry M.

1998-01-01

An ion-beam apparatus and method for analyzing and controlling integrated circuits. The ion-beam apparatus comprises a stage for holding one or more integrated circuits (ICs); a source means for producing a focused ion beam; and a beam-directing means for directing the focused ion beam to irradiate a predetermined portion of the IC for sufficient time to provide an ion-beam-generated electrical input signal to a predetermined element of the IC. The apparatus and method have applications to failure analysis and developmental analysis of ICs and permit an alteration, control, or programming of logic states or device parameters within the IC either separate from or in combination with applied electrical stimulus to the IC for analysis thereof. Preferred embodiments of the present invention including a secondary particle detector and an electron floodgun further permit imaging of the IC by secondary ions or electrons, and allow at least a partial removal or erasure of the ion-beam-generated electrical input signal.

Picosecond imaging of signal propagation in integrated circuits

NASA Astrophysics Data System (ADS)

Frohmann, Sven; Dietz, Enrico; Dittrich, Helmar; Hübers, Heinz-Wilhelm

2017-04-01

Optical analysis of integrated circuits (IC) is a powerful tool for analyzing security functions that are implemented in an IC. We present a photon emission microscope for picosecond imaging of hot carrier luminescence in ICs in the near-infrared spectral range from 900 to 1700 nm. It allows for a semi-invasive signal tracking in fully operational ICs on the gate or transistor level with a timing precision of approximately 6 ps. The capabilities of the microscope are demonstrated by imaging the operation of two ICs made by 180 and 60 nm process technology.

Smart substrates: Making multi-chip modules smarter

NASA Astrophysics Data System (ADS)

Wunsch, T. F.; Treece, R. K.

1995-05-01

A novel multi-chip module (MCM) design and manufacturing methodology which utilizes active CMOS circuits in what is normally a passive substrate realizes the 'smart substrate' for use in highly testable, high reliability MCMS. The active devices are used to test the bare substrate, diagnose assembly errors or integrated circuit (IC) failures that require rework, and improve the testability of the final MCM assembly. A static random access memory (SRAM) MCM has been designed and fabricated in Sandia Microelectronics Development Laboratory in order to demonstrate the technical feasibility of this concept and to examine design and manufacturing issues which will ultimately determine the economic viability of this approach. The smart substrate memory MCM represents a first in MCM packaging. At the time the first modules were fabricated, no other company or MCM vendor had incorporated active devices in the substrate to improve manufacturability and testability, and thereby improve MCM reliability and reduce cost.

Integrated circuit authentication using photon-limited x-ray microscopy.

PubMed

Markman, Adam; Javidi, Bahram

2016-07-15

A counterfeit integrated circuit (IC) may contain subtle changes to its circuit configuration. These changes may be observed when imaged using an x-ray; however, the energy from the x-ray can potentially damage the IC. We have investigated a technique to authenticate ICs under photon-limited x-ray imaging. We modeled an x-ray image with lower energy by generating a photon-limited image from a real x-ray image using a weighted photon-counting method. We performed feature extraction on the image using the speeded-up robust features (SURF) algorithm. We then authenticated the IC by comparing the SURF features to a database of SURF features from authentic and counterfeit ICs. Our experimental results with real and counterfeit ICs using an x-ray microscope demonstrate that we can correctly authenticate an IC image captured using orders of magnitude lower energy x-rays. To the best of our knowledge, this Letter is the first one on using a photon-counting x-ray imaging model and relevant algorithms to authenticate ICs to prevent potential damage.

Survey of key technologies on millimeter-wave CMOS integrated circuits

NASA Astrophysics Data System (ADS)

Yu, Fei; Gao, Lei; Li, Lixiang; Cai, Shuo; Wang, Wei; Wang, Chunhua

2018-05-01

In order to provide guidance for the development of high performance millimeter-wave complementary metal oxide semiconductor (MMW-CMOS) integrated circuits (IC), this paper provides a survey of key technologies on MMW-CMOS IC. Technical background of MMW wireless communications is described. Then the recent development of the critical technologies of the MMW-CMOS IC are introduced in detail and compared. A summarization is given, and the development prospects on MMW-CMOS IC are also discussed.

System and method for interfacing large-area electronics with integrated circuit devices

DOEpatents

Verma, Naveen; Glisic, Branko; Sturm, James; Wagner, Sigurd

2016-07-12

A system and method for interfacing large-area electronics with integrated circuit devices is provided. The system may be implemented in an electronic device including a large area electronic (LAE) device disposed on a substrate. An integrated circuit IC is disposed on the substrate. A non-contact interface is disposed on the substrate and coupled between the LAE device and the IC. The non-contact interface is configured to provide at least one of a data acquisition path or control path between the LAE device and the IC.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Radojcic, Riko; Nowak, Matt; Nakamoto, Mark

The status of the development of a Design-for-Stress simulation flow that captures the stress effects in packaged 3D-stacked Si products like integrated circuits (ICs) using advanced via-middle Through Si Via technology is outlined. The next set of challenges required to proliferate the methodology and to deploy it for making and dispositioning real Si product decisions are described here. These include the adoption and support of a Process Design Kit (PDK) that includes the relevant material properties, the development of stress simulation methodologies that operate at higher levels of abstraction in a design flow, and the development and adoption of suitablemore » models required to make real product reliability decisions.« less

Radiation-hardened transistor and integrated circuit

DOEpatents

Ma, Kwok K.

2007-11-20

A composite transistor is disclosed for use in radiation hardening a CMOS IC formed on an SOI or bulk semiconductor substrate. The composite transistor has a circuit transistor and a blocking transistor connected in series with a common gate connection. A body terminal of the blocking transistor is connected only to a source terminal thereof, and to no other connection point. The blocking transistor acts to prevent a single-event transient (SET) occurring in the circuit transistor from being coupled outside the composite transistor. Similarly, when a SET occurs in the blocking transistor, the circuit transistor prevents the SET from being coupled outside the composite transistor. N-type and P-type composite transistors can be used for each and every transistor in the CMOS IC to radiation harden the IC, and can be used to form inverters and transmission gates which are the building blocks of CMOS ICs.

Hermetic Packages For Millimeter-Wave Circuits

NASA Technical Reports Server (NTRS)

Herman, Martin I.; Lee, Karen A.; Lowry, Lynn E.; Carpenter, Alain; Wamhof, Paul

1994-01-01

Advanced hermetic packages developed to house electronic circuits operating at frequencies from 1 to 100 gigahertz and beyond. Signals coupled into and out of packages electromagnetically. Provides circuit packages small, lightweight, rugged, and inexpensive in mass production. Packages embedded in planar microstrip and coplanar waveguide circuits, in waveguide-to-planar and planar-to-waveguide circuitry, in waveguide-to-waveguide circuitry, between radiating (antenna) elements, and between planar transmission lines and radiating elements. Other applications in automotive, communication, radar, remote sensing, and biomedical electronic systems foreseen.

Package for integrated optic circuit and method

DOEpatents

Kravitz, Stanley H.; Hadley, G. Ronald; Warren, Mial E.; Carson, Richard F.; Armendariz, Marcelino G.

1998-01-01

A structure and method for packaging an integrated optic circuit. The package comprises a first wall having a plurality of microlenses formed therein to establish channels of optical communication with an integrated optic circuit within the package. A first registration pattern is provided on an inside surface of one of the walls of the package for alignment and attachment of the integrated optic circuit. The package in one embodiment may further comprise a fiber holder for aligning and attaching a plurality of optical fibers to the package and extending the channels of optical communication to the fibers outside the package. In another embodiment, a fiber holder may be used to hold the fibers and align the fibers to the package. The fiber holder may be detachably connected to the package.

Package for integrated optic circuit and method

DOEpatents

Kravitz, S.H.; Hadley, G.R.; Warren, M.E.; Carson, R.F.; Armendariz, M.G.

1998-08-04

A structure and method are disclosed for packaging an integrated optic circuit. The package comprises a first wall having a plurality of microlenses formed therein to establish channels of optical communication with an integrated optic circuit within the package. A first registration pattern is provided on an inside surface of one of the walls of the package for alignment and attachment of the integrated optic circuit. The package in one embodiment may further comprise a fiber holder for aligning and attaching a plurality of optical fibers to the package and extending the channels of optical communication to the fibers outside the package. In another embodiment, a fiber holder may be used to hold the fibers and align the fibers to the package. The fiber holder may be detachably connected to the package. 6 figs.

Single-mode glass waveguide technology for optical interchip communication on board level

NASA Astrophysics Data System (ADS)

Brusberg, Lars; Neitz, Marcel; Schröder, Henning

2012-01-01

The large bandwidth demand in long-distance telecom networks lead to single-mode fiber interconnects as result of low dispersion, low loss and dense wavelength multiplexing possibilities. In contrast, multi-mode interconnects are suitable for much shorter lengths up to 300 meters and are promising for optical links between racks and on board level. Active optical cables based on multi-mode fiber links are at the market and research in multi-mode waveguide integration on board level is still going on. Compared to multi-mode, a single-mode waveguide has much more integration potential because of core diameters of around 20% of a multi-mode waveguide by a much larger bandwidth. But light coupling in single-mode waveguides is much more challenging because of lower coupling tolerances. Together with the silicon photonics technology, a single-mode waveguide technology on board-level will be the straight forward development goal for chip-to-chip optical interconnects integration. Such a hybrid packaging platform providing 3D optical single-mode links bridges the gap between novel photonic integrated circuits and the glass fiber based long-distance telecom networks. Following we introduce our 3D photonic packaging approach based on thin glass substrates with planar integrated optical single-mode waveguides for fiber-to-chip and chip-to-chip interconnects. This novel packaging approach merges micro-system packaging and glass integrated optics. It consists of a thin glass substrate with planar integrated singlemode waveguide circuits, optical mirrors and lenses providing an integration platform for photonic IC assembly and optical fiber interconnect. Thin glass is commercially available in panel and wafer formats and characterizes excellent optical and high-frequency properties. That makes it perfect for microsystem packaging. The paper presents recent results in single-mode waveguide technology on wafer level and waveguide characterization. Furthermore the integration in a hybrid packaging process and design issues are discussed.

Apparatus and method for defect testing of integrated circuits

DOEpatents

Cole, Jr., Edward I.; Soden, Jerry M.

2000-01-01

An apparatus and method for defect and failure-mechanism testing of integrated circuits (ICs) is disclosed. The apparatus provides an operating voltage, V.sub.DD, to an IC under test and measures a transient voltage component, V.sub.DDT, signal that is produced in response to switching transients that occur as test vectors are provided as inputs to the IC. The amplitude or time delay of the V.sub.DDT signal can be used to distinguish between defective and defect-free (i.e. known good) ICs. The V.sub.DDT signal is measured with a transient digitizer, a digital oscilloscope, or with an IC tester that is also used to input the test vectors to the IC. The present invention has applications for IC process development, for the testing of ICs during manufacture, and for qualifying ICs for reliability.

Integration of Low-Power ASIC and MEMS Sensors for Monitoring Gastrointestinal Tract Using a Wireless Capsule System.

PubMed

Arefin, Md Shamsul; Redoute, Jean-Michel; Yuce, Mehmet Rasit

2018-01-01

This paper presents a wireless capsule microsystem to detect and monitor the pH, pressure, and temperature of the gastrointestinal tract in real time. This research contributes to the integration of sensors (microfabricated capacitive pH, capacitive pressure, and resistive temperature sensors), frequency modulation and pulse width modulation based interface IC circuits, microcontroller, and transceiver with meandered conformal antenna for the development of a capsule system. The challenges associated with the system miniaturization, higher sensitivity and resolution of sensors, and lower power consumption of interface circuits are addressed. The layout, PCB design, and packaging of a miniaturized wireless capsule, having diameter of 13 mm and length of 28 mm, have successfully been implemented. A data receiver and recorder system is also designed to receive physiological data from the wireless capsule and to send it to a computer for real-time display and recording. Experiments are performed in vitro using a stomach model and minced pork as tissue simulating material. The real-time measurements also validate the suitability of sensors, interface circuits, and meandered antenna for wireless capsule applications.

Thermally-isolated silicon-based integrated circuits and related methods

DOEpatents

Wojciechowski, Kenneth; Olsson, Roy H.; Clews, Peggy J.; Bauer, Todd

2017-05-09

Thermally isolated devices may be formed by performing a series of etches on a silicon-based substrate. As a result of the series of etches, silicon material may be removed from underneath a region of an integrated circuit (IC). The removal of the silicon material from underneath the IC forms a gap between remaining substrate and the integrated circuit, though the integrated circuit remains connected to the substrate via a support bar arrangement that suspends the integrated circuit over the substrate. The creation of this gap functions to release the device from the substrate and create a thermally-isolated integrated circuit.

Evaluation of a TB infection control implementation initiative in out-patient HIV clinics in Zambia and Botswana.

PubMed

Emerson, C; Lipke, V; Kapata, N; Mwananyambe, N; Mwinga, A; Garekwe, M; Lanje, S; Moshe, Y; Pals, S L; Nakashima, A K; Miller, B

2016-07-01

Out-patient human immunodeficiency virus (HIV) care and treatment clinics in Zambia and Botswana, countries with a high burden of HIV and TB infection. To develop a tuberculosis infection control (TB IC) training and implementation package and evaluate the implementation of TB IC activities in facilities implementing the package. Prospective program evaluation of a TB IC training and implementation package using a standardized facility risk assessment tool, qualitative interviews with facility health care workers and measures of pre- and post-test performance. A composite measure of facility performance in TB IC improved from 32% at baseline to 50% at 1 year among eight facilities in Zambia, and from 27% to 80% at 6 months among 10 facilities in Botswana. Although there was marked improvement in indicators of managerial, administrative and environmental controls, key ongoing challenges remained in ensuring access to personal protective equipment and implementing TB screening in health care workers. TB IC activities at out-patient HIV clinics in Zambia and Botswana improved after training using the implementation package. Continued infrastructure support, as well as monitoring and evaluation, are needed to support the scale-up and sustainability of TB IC programs in facilities in low-resource countries.

Experimental and theoretical analysis of integrated circuit (IC) chips on flexible substrates subjected to bending

NASA Astrophysics Data System (ADS)

Chen, Ying; Yuan, Jianghong; Zhang, Yingchao; Huang, Yonggang; Feng, Xue

2017-10-01

The interfacial failure of integrated circuit (IC) chips integrated on flexible substrates under bending deformation has been studied theoretically and experimentally. A compressive buckling test is used to impose the bending deformation onto the interface between the IC chip and the flexible substrate quantitatively, after which the failed interface is investigated using scanning electron microscopy. A theoretical model is established based on the beam theory and a bi-layer interface model, from which an analytical expression of the critical curvature in relation to the interfacial failure is obtained. The relationships between the critical curvature, the material, and the geometric parameters of the device are discussed in detail, providing guidance for future optimization flexible circuits based on IC chips.

6H-SiC Transistor Integrated Circuits Demonstrating Prolonged Operation at 500 C

NASA Technical Reports Server (NTRS)

Neudeck, Philip G.; Spry, David J.; Chen, Liang-Yu; Chang, Carl W.; Beheim, Glenn M.; Okojie, Robert S.; Evans, Laura J.; Meredith, Roger; Ferrier, Terry; Krasowski, Michael J.;

Symmetric miniaturized heating system for active microelectronic devices.

PubMed

McCracken, Michael; Mayer, Michael; Jourard, Isaac; Moon, Jeong-Tak; Persic, John

2010-07-01

To qualify interconnect technologies such as microelectronic fine wire bonds for mass production of integrated circuit (IC) packages, it is necessary to perform accelerated aging tests, e.g., to age a device at an elevated temperature or to subject the device to thermal cycling and measure the decrease of interconnect quality. There are downsides to using conventional ovens for this as they are relatively large and have relatively slow temperature change rates, and if electrical connections are required between monitoring equipment and the device being heated, they must be located inside the oven and may be aged by the high temperatures. Addressing these downsides, a miniaturized heating system (minioven) is presented, which can heat individual IC packages containing the interconnects to be tested. The core of this system is a piece of copper cut from a square shaped tube with high resistance heating wire looped around it. Ceramic dual in-line packages are clamped against either open end of the core. One package contains a Pt100 temperature sensor and the other package contains the device to be aged placed in symmetry to the temperature sensor. According to the temperature detected by the Pt100, a proportional-integral-derivative controller adjusts the power supplied to the heating wire. The system maintains a dynamic temperature balance with the core hot and the two symmetric sides with electrical connections to the device under test at a cooler temperature. Only the face of the package containing the device is heated, while the socket holding it remains below 75 degrees C when the oven operates at 200 degrees C. The minioven can heat packages from room temperature up to 200 degrees C in less than 5 min and maintain this temperature at 28 W power. During long term aging, a temperature of 200 degrees C was maintained for 1120 h with negligible resistance change of the heating wires after 900 h (heating wire resistance increased 0.2% over the final 220 h). The device is also subjected to 5700 thermal cycles between 55 and 195 degrees C, demonstrating reliability under thermal cycling.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wojciechowski, Kenneth; Olsson, Roy; Clews, Peggy J.

Thermally isolated devices may be formed by performing a series of etches on a silicon-based substrate. As a result of the series of etches, silicon material may be removed from underneath a region of an integrated circuit (IC). The removal of the silicon material from underneath the IC forms a gap between remaining substrate and the integrated circuit, though the integrated circuit remains connected to the substrate via a support bar arrangement that suspends the integrated circuit over the substrate. The creation of this gap functions to release the device from the substrate and create a thermally-isolated integrated circuit.

Accelerating functional verification of an integrated circuit

DOEpatents

Deindl, Michael; Ruedinger, Jeffrey Joseph; Zoellin, Christian G.

2015-10-27

Illustrative embodiments include a method, system, and computer program product for accelerating functional verification in simulation testing of an integrated circuit (IC). Using a processor and a memory, a serial operation is replaced with a direct register access operation, wherein the serial operation is configured to perform bit shifting operation using a register in a simulation of the IC. The serial operation is blocked from manipulating the register in the simulation of the IC. Using the register in the simulation of the IC, the direct register access operation is performed in place of the serial operation.

Semiconductor/High-Tc-Superconductor Hybrid ICs

NASA Technical Reports Server (NTRS)

Burns, Michael J.

1995-01-01

Hybrid integrated circuits (ICs) containing both Si-based semiconducting and YBa(2)Cu(3)O(7-x) superconducting circuit elements on sapphire substrates developed. Help to prevent diffusion of Cu from superconductors into semiconductors. These hybrid ICs combine superconducting and semiconducting features unavailable in superconducting or semiconducting circuitry alone. For example, complementary metal oxide/semiconductor (CMOS) readout and memory devices integrated with fast-switching Josephson-junction super-conducting logic devices and zero-resistance interconnections.

Swarm intelligence-based approach for optimal design of CMOS differential amplifier and comparator circuit using a hybrid salp swarm algorithm

NASA Astrophysics Data System (ADS)

Asaithambi, Sasikumar; Rajappa, Muthaiah

2018-05-01

In this paper, an automatic design method based on a swarm intelligence approach for CMOS analog integrated circuit (IC) design is presented. The hybrid meta-heuristics optimization technique, namely, the salp swarm algorithm (SSA), is applied to the optimal sizing of a CMOS differential amplifier and the comparator circuit. SSA is a nature-inspired optimization algorithm which mimics the navigating and hunting behavior of salp. The hybrid SSA is applied to optimize the circuit design parameters and to minimize the MOS transistor sizes. The proposed swarm intelligence approach was successfully implemented for an automatic design and optimization of CMOS analog ICs using Generic Process Design Kit (GPDK) 180 nm technology. The circuit design parameters and design specifications are validated through a simulation program for integrated circuit emphasis simulator. To investigate the efficiency of the proposed approach, comparisons have been carried out with other simulation-based circuit design methods. The performances of hybrid SSA based CMOS analog IC designs are better than the previously reported studies.

Swarm intelligence-based approach for optimal design of CMOS differential amplifier and comparator circuit using a hybrid salp swarm algorithm.

PubMed

Asaithambi, Sasikumar; Rajappa, Muthaiah

2018-05-01

In this paper, an automatic design method based on a swarm intelligence approach for CMOS analog integrated circuit (IC) design is presented. The hybrid meta-heuristics optimization technique, namely, the salp swarm algorithm (SSA), is applied to the optimal sizing of a CMOS differential amplifier and the comparator circuit. SSA is a nature-inspired optimization algorithm which mimics the navigating and hunting behavior of salp. The hybrid SSA is applied to optimize the circuit design parameters and to minimize the MOS transistor sizes. The proposed swarm intelligence approach was successfully implemented for an automatic design and optimization of CMOS analog ICs using Generic Process Design Kit (GPDK) 180 nm technology. The circuit design parameters and design specifications are validated through a simulation program for integrated circuit emphasis simulator. To investigate the efficiency of the proposed approach, comparisons have been carried out with other simulation-based circuit design methods. The performances of hybrid SSA based CMOS analog IC designs are better than the previously reported studies.

Encapsulate-and-peel: fabricating carbon nanotube CMOS integrated circuits in a flexible ultra-thin plastic film.

PubMed

Gao, Pingqi; Zhang, Qing

2014-02-14

Fabrication of single-walled carbon nanotube thin film (SWNT-TF) based integrated circuits (ICs) on soft substrates has been challenging due to several processing-related obstacles, such as printed/transferred SWNT-TF pattern and electrode alignment, electrical pad/channel material/dielectric layer flatness, adherence of the circuits onto the soft substrates etc. Here, we report a new approach that circumvents these challenges by encapsulating pre-formed SWNT-TF-ICs on hard substrates into polyimide (PI) and peeling them off to form flexible ICs on a large scale. The flexible SWNT-TF-ICs show promising performance comparable to those circuits formed on hard substrates. The flexible p- and n-type SWNT-TF transistors have an average mobility of around 60 cm(2) V(-1) s(-1), a subthreshold slope as low as 150 mV dec(-1), operating gate voltages less than 2 V, on/off ratios larger than 10(4) and a switching speed of several kilohertz. The post-transfer technique described here is not only a simple and cost-effective pathway to realize scalable flexible ICs, but also a feasible method to fabricate flexible displays, sensors and solar cells etc.

Pulsed laser ablation of IC packages for device failure analyses

NASA Astrophysics Data System (ADS)

Hong, Ming Hui; Mai, ZhiHong; Chen, G. X.; Thiam, Thomas; Song, Wen D.; Lu, Yongfeng; Soh, Chye E.; Chong, Tow Chong

2002-06-01

Pulsed laser ablation of mold compounds for IC packaging in air and with steam assistance is investigated. It is applied to decap IC packages and expose computer CPU dies for the device failure analyses. Compared with chemical decapping, the laser ablation has advantages of being fast speed, non- contact and dry processing. Laser ablation with the steam assistance results in higher ablation rate and wider ablated crater with much smoother surface morphology. It implies that the steam assisted laser ablation can achieve a faster and better quality laser processing. Audible acoustic wave and plasma optical signal diagnostics are also carried out to have a better understanding of the mechanisms behind. Light wavelength and laser fluence applied in the decapping are two important parameters. The 532 nm Nd:YAG laser decapping at a low laser fluence can achieve a large decapping area with a fine ablation profile. IC packages decapped by the laser ablation show good quality for the device failure analyses.

First-Order SPICE Modeling of Extreme-Temperature 4H-SiC JFET Integrated Circuits

NASA Technical Reports Server (NTRS)

Neudeck, Philip G.; Spry, David J.; Chen, Liang-Yu

2016-01-01

A separate submission to this conference reports that 4H-SiC Junction Field Effect Transistor (JFET) digital and analog Integrated Circuits (ICs) with two levels of metal interconnect have reproducibly demonstrated electrical operation at 500 C in excess of 1000 hours. While this progress expands the complexity and durability envelope of high temperature ICs, one important area for further technology maturation is the development of reasonably accurate and accessible computer-aided modeling and simulation tools for circuit design of these ICs. Towards this end, we report on development and verification of 25 C to 500 C SPICE simulation models of first order accuracy for this extreme-temperature durable 4H-SiC JFET IC technology. For maximum availability, the JFET IC modeling is implemented using the baseline-version SPICE NMOS LEVEL 1 model that is common to other variations of SPICE software and importantly includes the body-bias effect. The first-order accuracy of these device models is verified by direct comparison with measured experimental device characteristics.

Modular electronics packaging system

NASA Technical Reports Server (NTRS)

Hunter, Don J. (Inventor)

2001-01-01

A modular electronics packaging system includes multiple packaging slices that are mounted horizontally to a base structure. The slices interlock to provide added structural support. Each packaging slice includes a rigid and thermally conductive housing having four side walls that together form a cavity to house an electronic circuit. The chamber is enclosed on one end by an end wall, or web, that isolates the electronic circuit from a circuit in an adjacent packaging slice. The web also provides a thermal path between the electronic circuit and the base structure. Each slice also includes a mounting bracket that connects the packaging slice to the base structure. Four guide pins protrude from the slice into four corresponding receptacles in an adjacent slice. A locking element, such as a set screw, protrudes into each receptacle and interlocks with the corresponding guide pin. A conduit is formed in the slice to allow electrical connection to the electronic circuit.

77 FR 33486 - Certain Integrated Circuit Packages Provided With Multiple Heat-Conducting Paths and Products...

Federal Register 2010, 2011, 2012, 2013, 2014

2012-06-06

... INTERNATIONAL TRADE COMMISSION [Docket No. 2899] Certain Integrated Circuit Packages Provided With... complaint entitled Certain Integrated Circuit Packages Provided With Multiple Heat-Conducting Paths and..., telephone (202) 205-2000. The public version of the complaint can be accessed on the Commission's electronic...

Packaging system with cleaning channel and method of making the same

DOE Office of Scientific and Technical Information (OSTI.GOV)

Fang, Lu

A packaging structure and method for surface mount integrated circuits reduces electrochemical migration (ECM) problems by including one or more cleaning channels to effectively and efficiently remove flux residue that may otherwise remain lodged in gaps between the surface mount package and the printed circuit board. A cleaning channel may be formed along a bottom surface of the surface mount package (i.e., the surface facing the printed circuit board), or along a portion of a top surface of the printed circuit board. In either case, the inclusion of a cleaning channel enlarges the gap between the bottom surface of themore » surface mount package and the printed circuit board and creates a path for contaminants to be flushed out during a cleaning process.« less

Macromodels of digital integrated circuits for program packages of circuit engineering design

NASA Astrophysics Data System (ADS)

Petrenko, A. I.; Sliusar, P. B.; Timchenko, A. P.

1984-04-01

Various aspects of the generation of macromodels of digital integrated circuits are examined, and their effective application in program packages of circuit engineering design is considered. Three levels of macromodels are identified, and the application of such models to the simulation of circuit outputs is discussed.

Assessment of Durable SiC JFET Technology for +600 C to -125 C Integrated Circuit Operation

NASA Technical Reports Server (NTRS)

Neudeck, P. G.; Krasowski, M. J.; Prokop, N. F.

2011-01-01

Electrical characteristics and circuit design considerations for prototype 6H-SiC JFET integrated circuits (ICs) operating over the broad temperature range of -125 C to +600 C are described. Strategic implementation of circuits with transistors and resistors in the same 6H-SiC n-channel layer enabled ICs with nearly temperature-independent functionality to be achieved. The frequency performance of the circuits declined at temperatures increasingly below or above room temperature, roughly corresponding to the change in 6H-SiC n-channel resistance arising from incomplete carrier ionization at low temperature and decreased electron mobility at high temperature. In addition to very broad temperature functionality, these simple digital and analog demonstration integrated circuits successfully operated with little change in functional characteristics over the course of thousands of hours at 500 C before experiencing interconnect-related failures. With appropriate further development, these initial results establish a new technology foundation for realizing durable 500 C ICs for combustion engine sensing and control, deep-well drilling, and other harsh-environment applications.

Effective Teaching of the Physical Design of Integrated Circuits Using Educational Tools

ERIC Educational Resources Information Center

Aziz, Syed Mahfuzul; Sicard, Etienne; Ben Dhia, Sonia

2010-01-01

This paper presents the strategies used for effective teaching and skill development in integrated circuit (IC) design using project-based learning (PBL) methodologies. It presents the contexts in which these strategies are applied to IC design courses at the University of South Australia, Adelaide, Australia, and the National Institute of Applied…

DOE Office of Scientific and Technical Information (OSTI.GOV)

Shah, Kedar G.; Pannu, Satinderpall S.

An integrated circuit system having an integrated circuit (IC) component which is able to have its functionality destroyed upon receiving a command signal. The system may involve a substrate with the IC component being supported on the substrate. A module may be disposed in proximity to the IC component. The module may have a cavity and a dissolving compound in a solid form disposed in the cavity. A heater component may be configured to heat the dissolving compound to a point of sublimation where the dissolving compound changes from a solid to a gaseous dissolving compound. A triggering mechanism maymore » be used for initiating a dissolution process whereby the gaseous dissolving compound is allowed to attack the IC component and destroy a functionality of the IC component.« less

A Way to End the IC Designer Shortage.

ERIC Educational Resources Information Center

Robinson, Arthur L.

1980-01-01

Discusses the problem of the shortage of engineers capable of designing advanced integrated circuits (IC) and presents some suggestions for increasing the number of IC designers in universities and semiconductor companies. (HM)

High ESD Breakdown-Voltage InP HBT Transimpedance Amplifier IC for Optical Video Distribution Systems

NASA Astrophysics Data System (ADS)

Sano, Kimikazu; Nagatani, Munehiko; Mutoh, Miwa; Murata, Koichi

This paper is a report on a high ESD breakdown-voltage InP HBT transimpedance amplifier IC for optical video distribution systems. To make ESD breakdown-voltage higher, we designed ESD protection circuits integrated in the TIA IC using base-collector/base-emitter diodes of InP HBTs and resistors. These components for ESD protection circuits have already existed in the employed InP HBT IC process, so no process modifications were needed. Furthermore, to meet requirements for use in optical video distribution systems, we studied circuit design techniques to obtain a good input-output linearity and a low-noise characteristic. Fabricated InP HBT TIA IC exhibited high human-body-model ESD breakdown voltages (±1000V for power supply terminals, ±200V for high-speed input/output terminals), good input-output linearity (less than 2.9-% duty-cycle-distortion), and low noise characteristic (10.7pA/√Hz averaged input-referred noise current density) with a -3-dB-down higher frequency of 6.9GHz. To the best of our knowledge, this paper is the first literature describing InP ICs with high ESD-breakdown voltages.

SEM probe of IC radiation sensitivity

NASA Technical Reports Server (NTRS)

Gauthier, M. K.; Stanley, A. G.

1979-01-01

Scanning Electron Microscope (SEM) used to irradiate single integrated circuit (IC) subcomponent to test for radiation sensitivity can localize area of IC less than .03 by .03 mm for determination of exact location of radiation sensitive section.

Dynamical Competition of IC-Industry Clustering from Taiwan to China

NASA Astrophysics Data System (ADS)

Tsai, Bi-Huei; Tsai, Kuo-Hui

2009-08-01

Most studies employ qualitative approach to explore the industrial clusters; however, few research has objectively quantified the evolutions of industry clustering. The purpose of this paper is to quantitatively analyze clustering among IC design, IC manufacturing as well as IC packaging and testing industries by using the foreign direct investment (FDI) data. The Lotka-Volterra system equations are first adopted here to capture the competition or cooperation among such three industries, thus explaining their clustering inclinations. The results indicate that the evolution of FDI into China for IC design industry significantly inspire the subsequent FDI of IC manufacturing as well as IC packaging and testing industries. Since IC design industry lie in the upstream stage of IC production, the middle-stream IC manufacturing and downstream IC packing and testing enterprises tend to cluster together with IC design firms, in order to sustain a steady business. Finally, Taiwan IC industry's FDI amount into China is predicted to cumulatively increase, which supports the industrial clustering tendency for Taiwan IC industry. Particularly, the FDI prediction of Lotka-Volterra model performs superior to that of the conventional Bass model after the forecast accuracy of these two models are compared. The prediction ability is dramatically improved as the industrial mutualism among each IC production stage is taken into account.

Packaging Of Control Circuits In A Robot Arm

NASA Technical Reports Server (NTRS)

Kast, William

1994-01-01

Packaging system houses and connects control circuitry mounted on circuit boards within shoulder, upper section, and lower section of seven-degree-of-freedom robot arm. Has modular design that incorporates surface-mount technology, multilayer circuit boards, large-scale integrated circuits, and multi-layer flat cables between sections for compactness. Three sections of robot arm contain circuit modules in form of stardardized circuit boards. Each module contains two printed-circuit cards, one of each face.

Analog integrated circuits design for processing physiological signals.

PubMed

Li, Yan; Poon, Carmen C Y; Zhang, Yuan-Ting

2010-01-01

Analog integrated circuits (ICs) designed for processing physiological signals are important building blocks of wearable and implantable medical devices used for health monitoring or restoring lost body functions. Due to the nature of physiological signals and the corresponding application scenarios, the ICs designed for these applications should have low power consumption, low cutoff frequency, and low input-referred noise. In this paper, techniques for designing the analog front-end circuits with these three characteristics will be reviewed, including subthreshold circuits, bulk-driven MOSFETs, floating gate MOSFETs, and log-domain circuits to reduce power consumption; methods for designing fully integrated low cutoff frequency circuits; as well as chopper stabilization (CHS) and other techniques that can be used to achieve a high signal-to-noise performance. Novel applications using these techniques will also be discussed.

The basic circuit of the IC: tectothalamic neurons with different patterns of synaptic organization send different messages to the thalamus

PubMed Central

Ito, Tetsufumi; Oliver, Douglas L.

2012-01-01

The inferior colliculus (IC) in the midbrain of the auditory system uses a unique basic circuit to organize the inputs from virtually all of the lower auditory brainstem and transmit this information to the medial geniculate body (MGB) in the thalamus. Here, we review the basic circuit of the IC, the neuronal types, the organization of their inputs and outputs. We specifically discuss the large GABAergic (LG) neurons and how they differ from the small GABAergic (SG) and the more numerous glutamatergic neurons. The somata and dendrites of LG neurons are identified by axosomatic glutamatergic synapses that are lacking in the other cell types and exclusively contain the glutamate transporter VGLUT2. Although LG neurons are most numerous in the central nucleus of the IC (ICC), an analysis of their distribution suggests that they are not specifically associated with one set of ascending inputs. The inputs to ICC may be organized into functional zones with different subsets of brainstem inputs, but each zone may contain the same three neuron types. However, the sources of VGLUT2 axosomatic terminals on the LG neuron are not known. Neurons in the dorsal cochlear nucleus, superior olivary complex, intermediate nucleus of the lateral lemniscus, and IC itself that express the gene for VGLUT2 only are the likely origin of the dense VGLUT2 axosomatic terminals on LG tectothalamic neurons. The IC is unique since LG neurons are GABAergic tectothalamic neurons in addition to the numerous glutamatergic tectothalamic neurons. SG neurons evidently target other auditory structures. The basic circuit of the IC and the LG neurons in particular, has implications for the transmission of information about sound through the midbrain to the MGB. PMID:22855671

Continuous epitaxial growth of extremely strong Cu6Sn5 textures at liquid-Sn/(111)Cu interface under temperature gradient

NASA Astrophysics Data System (ADS)

Zhong, Y.; Zhao, N.; Liu, C. Y.; Dong, W.; Qiao, Y. Y.; Wang, Y. P.; Ma, H. T.

2017-11-01

As the diameter of solder interconnects in three-dimensional integrated circuits (3D ICs) downsizes to several microns, how to achieve a uniform microstructure with thousands of interconnects on stacking chips becomes a critical issue in 3D IC manufacturing. We report a promising way for fabricating fully intermetallic interconnects with a regular grain morphology and a strong texture feature by soldering single crystal (111) Cu/Sn/polycrystalline Cu interconnects under the temperature gradient. Continuous epitaxial growth of η-Cu6Sn5 at cold end liquid-Sn/(111)Cu interfaces has been demonstrated. The resultant η-Cu6Sn5 grains show faceted prism textures with an intersecting angle of 60° and highly preferred orientation with their ⟨ 11 2 ¯ 0 ⟩ directions nearly paralleling to the direction of the temperature gradient. These desirable textures are maintained even after soldering for 120 min. The results pave the way for controlling the morphology and orientation of interfacial intermetallics in 3D packaging technologies.

Advanced packaging for Integrated Micro-Instruments

NASA Technical Reports Server (NTRS)

Lyke, James L.

1995-01-01

The relationship between packaging, microelectronics, and micro-electrical-mechanical systems (MEMS) is an important one, particularly when the edges of performance boundaries are pressed, as in the case of miniaturized systems. Packaging is a sort of physical backbone that enables the maximum performance of these systems to be realized, and the penalties imposed by conventional packing approaches is particularly limiting for MEMS devices. As such, advanced packaging approaches, such as multi-chip modules (MCM's) have been touted as a true means of electronic 'enablement' for a variety of application domains. Realizing an optimum system of packaging, however, in not as simple as replacing a set of single chip packages with a substrate of interconnections. Research at Phillips Laboratory has turned up a number of integrating options in the two- and three-dimensional rending of miniature systems with physical interconnection structures with intrinsically high performance. Not only do these structures motivate the redesign of integrated circuits (IC's) for lower power, but they possess interesting features that provide a framework for the direct integration of MEMS devices. Cost remains a barrier to the application of MEMS devices, even in space systems. Several innovations are suggested that will result in lower cost and more rapid cycle time. First, the novelty of a 'constant floor plan' MCM which encapsulates a variety of commonly used components into a stockable, easily customized assembly is discussed. Next, the use of low-cost substrates is examined. The anticipated advent of ultra-high density interconnect (UHDI) is suggested as the limit argument of advanced packaging. Finally, the concept of a heterogeneous 3-D MCM system is outlined that allows for the combination of different compatible packaging approaches into a uniformly dense structure that could also include MEMS-based sensors.

High-Performance Complementary Transistors and Medium-Scale Integrated Circuits Based on Carbon Nanotube Thin Films.

PubMed

Yang, Yingjun; Ding, Li; Han, Jie; Zhang, Zhiyong; Peng, Lian-Mao

2017-04-25

Solution-derived carbon nanotube (CNT) network films with high semiconducting purity are suitable materials for the wafer-scale fabrication of field-effect transistors (FETs) and integrated circuits (ICs). However, it is challenging to realize high-performance complementary metal-oxide semiconductor (CMOS) FETs with high yield and stability on such CNT network films, and this difficulty hinders the development of CNT-film-based ICs. In this work, we developed a doping-free process for the fabrication of CMOS FETs based on solution-processed CNT network films, in which the polarity of the FETs was controlled using Sc or Pd as the source/drain contacts to selectively inject carriers into the channels. The fabricated top-gated CMOS FETs showed high symmetry between the characteristics of n- and p-type devices and exhibited high-performance uniformity and excellent scalability down to a gate length of 1 μm. Many common types of CMOS ICs, including typical logic gates, sequential circuits, and arithmetic units, were constructed based on CNT films, and the fabricated ICs exhibited rail-to-rail outputs because of the high noise margin of CMOS circuits. In particular, 4-bit full adders consisting of 132 CMOS FETs were realized with 100% yield, thereby demonstrating that this CMOS technology shows the potential to advance the development of medium-scale CNT-network-film-based ICs.

A multi-scale PDMS fabrication strategy to bridge the size mismatch between integrated circuits and microfluidics†

PubMed Central

Muluneh, Melaku

2015-01-01

In recent years there has been great progress harnessing the small-feature size and programmability of integrated circuits (ICs) for biological applications, by building microfluidics directly on top of ICs. However, a major hurdle to the further development of this technology is the inherent size-mismatch between ICs (~mm) and microfluidic chips (~cm). Increasing the area of the ICs to match the size of the microfluidic chip, as has often been done in previous studies, leads to a waste of valuable space on the IC and an increase in fabrication cost (>100×). To address this challenge, we have developed a three dimensional PDMS chip that can straddle multiple length scales of hybrid IC/microfluidic chips. This approach allows millimeter-scale ICs, with no post-processing, to be integrated into a centimeter-sized PDMS chip. To fabricate this PDMS chip we use a combination of soft-lithography and laser micromachining. Soft lithography was used to define micrometer-scale fluid channels directly on the surface of the IC, allowing fluid to be controlled with high accuracy and brought into close proximity to sensors for highly sensitive measurements. Laser micromachining was used to create ~50 μm vias to connect these molded PDMS channels to a larger PDMS chip, which can connect multiple ICs and house fluid connections to the outside world. To demonstrate the utility of this approach, we built and demonstrated an in-flow magnetic cytometer that consisted of a 5 × 5 cm2 microfluidic chip that incorporated a commercial 565 × 1145 μm2 IC with a GMR sensing circuit. We additionally demonstrated the modularity of this approach by building a chip that incorporated two of these GMR chips connected in series. PMID:25284502

A multi-scale PDMS fabrication strategy to bridge the size mismatch between integrated circuits and microfluidics.

PubMed

Muluneh, Melaku; Issadore, David

2014-12-07

In recent years there has been great progress harnessing the small-feature size and programmability of integrated circuits (ICs) for biological applications, by building microfluidics directly on top of ICs. However, a major hurdle to the further development of this technology is the inherent size-mismatch between ICs (~mm) and microfluidic chips (~cm). Increasing the area of the ICs to match the size of the microfluidic chip, as has often been done in previous studies, leads to a waste of valuable space on the IC and an increase in fabrication cost (>100×). To address this challenge, we have developed a three dimensional PDMS chip that can straddle multiple length scales of hybrid IC/microfluidic chips. This approach allows millimeter-scale ICs, with no post-processing, to be integrated into a centimeter-sized PDMS chip. To fabricate this PDMS chip we use a combination of soft-lithography and laser micromachining. Soft lithography was used to define micrometer-scale fluid channels directly on the surface of the IC, allowing fluid to be controlled with high accuracy and brought into close proximity to sensors for highly sensitive measurements. Laser micromachining was used to create ~50 μm vias to connect these molded PDMS channels to a larger PDMS chip, which can connect multiple ICs and house fluid connections to the outside world. To demonstrate the utility of this approach, we built and demonstrated an in-flow magnetic cytometer that consisted of a 5 × 5 cm(2) microfluidic chip that incorporated a commercial 565 × 1145 μm(2) IC with a GMR sensing circuit. We additionally demonstrated the modularity of this approach by building a chip that incorporated two of these GMR chips connected in series.

Functional role for suppression of the insular-striatal circuit in modulating interoceptive effects of alcohol.

PubMed

Jaramillo, Anel A; Agan, Verda E; Makhijani, Viren H; Pedroza, Stephen; McElligott, Zoe A; Besheer, Joyce

2017-09-27

The insular cortex (IC) is a region proposed to modulate, in part, interoceptive states and motivated behavior. Interestingly, IC dysfunction and deficits in interoceptive processing are often found among individuals with substance-use disorders. Furthermore, the IC projects to the nucleus accumbens core (AcbC), a region known to modulate the discriminative stimulus/interoceptive effects of alcohol and other drug-related behaviors. Therefore, the goal of the present work was to investigate the possible role of the IC ➔ AcbC circuit in modulating the interoceptive effects of alcohol. Thus, we utilized a chemogenetic technique (hM4D i designer receptor activation by designer drugs) to silence neuronal activity in the IC of rats trained to discriminate alcohol (1 g/kg, IG) versus water using an operant or Pavlovian alcohol discrimination procedure. Chemogenetic silencing of the IC or IC ➔ AcbC neuronal projections resulted in potentiated sensitivity to the interoceptive effects of alcohol in both the operant and Pavlovian tasks. Together, these data provide critical evidence for the nature of the complex IC circuitry and, specifically, suppression of the insular-striatal circuit in modulating behavior under a drug stimulus control. © 2017 Society for the Study of Addiction.

The rectenna design on contact lens for wireless powering of the active intraocular pressure monitoring system.

PubMed

Cheng, H W; Jeng, B M; Chen, C Y; Huang, H Y; Chiou, J C; Luo, C H

2013-01-01

This paper proposed a wireless power harvesting system with micro-electro-mechanical-systems (MEMS) fabrication for noninvasive intraocular pressure (IOP) measurement on soft contact lens substructure. The power harvesting IC consists of a loop antenna, an impedance matching network and a rectifier. The proposed IC has been designed and fabricated by CMOS 0.18 um process that operates at the ISM band of 5.8 GHz. The antenna and the power harvesting IC would be bonded together by using flip chip bonding technologies without extra wire interference. The circuit utilized an impedance transformation circuit to boost the input RF signal that improves the circuit performance. The proposed design achieves an RF-to-DC conversion efficiency of 35% at 5.8 GHz.

Processing and Characterization of Thousand-Hour 500 C Durable 4H-SiC JFET Integrated Circuits

NASA Technical Reports Server (NTRS)

Spry, David J.; Neudeck, Philip G.; Chen, Liangyu; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.; Krasowski, Michael J.; Prokop, Norman F.

2016-01-01

This work reports fabrication and testing of integrated circuits (ICs) with two levels of interconnect that consistently achieve greater than 1000 hours of stable electrical operation at 500 C in air ambient. These ICs are based on 4H-SiC junction field effect transistor (JFET) technology that integrates hafnium ohmic contacts with TaSi2 interconnects and SiO2 and Si3N4 dielectric layers over 1-m scale vertical topology. Following initial burn-in, important circuit parameters remain stable for more than 1000 hours of 500 C operational testing. These results advance the technology foundation for realizing long-term durable 500 C ICs with increased functional capability for sensing and control combustion engine, planetary, deep-well drilling, and other harsh-environment applications.

Processing and Characterization of Thousand-Hour 500 C Durable 4H-SiC JFET Integrated Circuits

NASA Technical Reports Server (NTRS)

Spry, David J.; Neudeck, Philip G.; Chen, Liang-Yu; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.; Krasowski, Michael J.; Prokop, Norman F.

2016-01-01

This work reports fabrication and testing of integrated circuits (ICs) with two levels of interconnect that consistently achieve greater than 1000 hours of stable electrical operation at 500 C in air ambient. These ICs are based on 4H-SiC junction field effect transistor (JFET) technology that integrates hafnium ohmic contacts with TaSi2 interconnects and SiO2 and Si3N4 dielectric layers over approximately 1-micrometer scale vertical topology. Following initial burn-in, important circuit parameters remain stable for more than 1000 hours of 500 C operational testing. These results advance the technology foundation for realizing long-term durable 500 C ICs with increased functional capability for sensing and control combustion engine, planetary, deep-well drilling, and other harsh-environment applications.

Graphene/Si CMOS Hybrid Hall Integrated Circuits

PubMed Central

Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

2014-01-01

Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18 um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process. PMID:24998222

Graphene/Si CMOS hybrid hall integrated circuits.

PubMed

Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

2014-07-07

Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18 um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process.

Ultra-Reliable Digital Avionics (URDA) processor

NASA Astrophysics Data System (ADS)

Branstetter, Reagan; Ruszczyk, William; Miville, Frank

1994-10-01

Texas Instruments Incorporated (TI) developed the URDA processor design under contract with the U.S. Air Force Wright Laboratory and the U.S. Army Night Vision and Electro-Sensors Directorate. TI's approach couples advanced packaging solutions with advanced integrated circuit (IC) technology to provide a high-performance (200 MIPS/800 MFLOPS) modular avionics processor module for a wide range of avionics applications. TI's processor design integrates two Ada-programmable, URDA basic processor modules (BPM's) with a JIAWG-compatible PiBus and TMBus on a single F-22 common integrated processor-compatible form-factor SEM-E avionics card. A separate, high-speed (25-MWord/second 32-bit word) input/output bus is provided for sensor data. Each BPM provides a peak throughput of 100 MIPS scalar concurrent with 400-MFLOPS vector processing in a removable multichip module (MCM) mounted to a liquid-flowthrough (LFT) core and interfacing to a processor interface module printed wiring board (PWB). Commercial RISC technology coupled with TI's advanced bipolar complementary metal oxide semiconductor (BiCMOS) application specific integrated circuit (ASIC) and silicon-on-silicon packaging technologies are used to achieve the high performance in a miniaturized package. A Mips R4000-family reduced instruction set computer (RISC) processor and a TI 100-MHz BiCMOS vector coprocessor (VCP) ASIC provide, respectively, the 100 MIPS of a scalar processor throughput and 400 MFLOPS of vector processing throughput for each BPM. The TI Aladdim ASIC chipset was developed on the TI Aladdin Program under contract with the U.S. Army Communications and Electronics Command and was sponsored by the Advanced Research Projects Agency with technical direction from the U.S. Army Night Vision and Electro-Sensors Directorate.

High Volume Manufacturing and Field Stability of MEMS Products

NASA Astrophysics Data System (ADS)

Martin, Jack

Low volume MEMS/NEMS production is practical when an attractive concept is implemented with business, manufacturing, packaging, and test support. Moving beyond this to high volume production adds requirements on design, process control, quality, product stability, market size, market maturity, capital investment, and business systems. In a broad sense, this chapter uses a case study approach: It describes and compares the silicon-based MEMS accelerometers, pressure sensors, image projection systems, and gyroscopes that are in high volume production. Although they serve several markets, these businesses have common characteristics. For example, the manufacturing lines use automated semiconductor equipment and standard material sets to make consistent products in large quantities. Standard, well controlled processes are sometimes modified for a MEMS product. However, novel processes that cannot run with standard equipment and material sets are avoided when possible. This reliance on semiconductor tools, as well as the organizational practices required to manufacture clean, particle-free products partially explains why the MEMS market leaders are integrated circuit manufacturers. There are other factors. MEMS and NEMS are enabling technologies, so it can take several years for high volume applications to develop. Indeed, market size is usually a strong function of price. This becomes a vicious circle, because low price requires low cost - a result that is normally achieved only after a product is in high volume production. During the early years, IC companies reduced cost and financial risk by using existing facilities for low volume MEMS production. As a result, product architectures are partially determined by capabilities developed for previous products. This chapter includes a discussion of MEMS product architecture with particular attention to the impact of electronic integration, packaging, and surfaces. Packaging and testing are critical, because they are significant factors in MEMS product cost. These devices have extremelyhigh surface/volume ratios, so performance and stability may depend on the control of surface characteristics after packaging. Looking into the future, the competitive advantage of IC suppliers will decrease as small companies learn to integrate MEMS/NEMS devices on CMOS foundry wafers. Packaging challenges still remain, because most MEMS/NEMS products must interact with the environment without degrading stability or reliability. Generic packaging solutions are unlikely. However, packaging subcontractors recognize that MEMS/NEMS is a growth opportunity. They will spread the overhead burden of high-capital-cost-facilities by developing flexible processes in order to package several types of moderate volume integrated MEMS/NEMS products on the same equipment.

High Volume Manufacturing and Field Stability of MEMS Products

NASA Astrophysics Data System (ADS)

Martin, Jack

Low volume MEMS/NEMS production is practical when an attractive concept is implemented with business, manufacturing, packaging, and test support. Moving beyond this to high volume production adds requirements on design, process control, quality, product stability, market size, market maturity, capital investment, and business systems. In a broad sense, this chapter uses a case study approach: It describes and compares the silicon-based MEMS accelerometers, pressure sensors, image projection systems, and gyroscopes that are in high volume production. Although they serve several markets, these businesses have common characteristics. For example, the manufacturing lines use automated semiconductor equipment and standard material sets to make consistent products in large quantities. Standard, well controlled processes are sometimes modified for a MEMS product. However, novel processes that cannot run with standard equipment and material sets are avoided when possible. This reliance on semiconductor tools, as well as the organizational practices required to manufacture clean, particle-free products partially explains why the MEMS market leaders are integrated circuit manufacturers. There are other factors. MEMS and NEMS are enabling technologies, so it can take several years for high volume applications to develop. Indeed, market size is usually a strong function of price. This becomes a vicious circle, because low price requires low cost - a result that is normally achieved only after a product is in high volume production. During the early years, IC companies reduced cost and financial risk by using existing facilities for low volume MEMS production. As a result, product architectures are partially determined by capabilities developed for previous products. This chapter includes a discussion of MEMS product architecture with particular attention to the impact of electronic integration, packaging, and surfaces. Packaging and testing are critical, because they are significant factors in MEMS product cost. These devices have extremely high surface/volume ratios, so performance and stability may depend on the control of surface characteristics after packaging. Looking into the future, the competitive advantage of IC suppliers will decrease as small companies learn to integrate MEMS/NEMS devices on CMOS foundry wafers. Packaging challenges still remain, because most MEMS/NEMS products must interact with the environment without degrading stability or reliability. Generic packaging solutions are unlikely. However, packaging subcontractors recognize that MEMS/NEMS is a growth opportunity. They will spread the overhead burden of high-capital-cost-facilities by developing flexible processes in order to package several types of moderate volume integrated MEMS/NEMS products on the same equipment.

Method and apparatus to debug an integrated circuit chip via synchronous clock stop and scan

DOEpatents

Bellofatto, Ralph E [Ridgefield, CT; Ellavsky, Matthew R [Rochester, MN; Gara, Alan G [Mount Kisco, NY; Giampapa, Mark E [Irvington, NY; Gooding, Thomas M [Rochester, MN; Haring, Rudolf A [Cortlandt Manor, NY; Hehenberger, Lance G [Leander, TX; Ohmacht, Martin [Yorktown Heights, NY

2012-03-20

An apparatus and method for evaluating a state of an electronic or integrated circuit (IC), each IC including one or more processor elements for controlling operations of IC sub-units, and each the IC supporting multiple frequency clock domains. The method comprises: generating a synchronized set of enable signals in correspondence with one or more IC sub-units for starting operation of one or more IC sub-units according to a determined timing configuration; counting, in response to one signal of the synchronized set of enable signals, a number of main processor IC clock cycles; and, upon attaining a desired clock cycle number, generating a stop signal for each unique frequency clock domain to synchronously stop a functional clock for each respective frequency clock domain; and, upon synchronously stopping all on-chip functional clocks on all frequency clock domains in a deterministic fashion, scanning out data values at a desired IC chip state. The apparatus and methodology enables construction of a cycle-by-cycle view of any part of the state of a running IC chip, using a combination of on-chip circuitry and software.

Electrical Performance of a High Temperature 32-I/O HTCC Alumina Package

NASA Technical Reports Server (NTRS)

Chen, Liang-Yu; Neudeck, Philip G.; Spry, David J.; Beheim, Glenn M.; Hunter, Gary W.

2016-01-01

A high temperature co-fired ceramic (HTCC) alumina material was previously electrically tested at temperatures up to 550 C, and demonstrated improved dielectric performance at high temperatures compared with the 96% alumina substrate that we used before, suggesting its potential use for high temperature packaging applications. This paper introduces a prototype 32-I/O (input/output) HTCC alumina package with platinum conductor for 500 C low-power silicon carbide (SiC) integrated circuits. The design and electrical performance of this package including parasitic capacitance and parallel conductance of neighboring I/Os from 100 Hz to 1 MHz in a temperature range from room temperature to 550 C are discussed in detail. The parasitic capacitance and parallel conductance of this package in the entire frequency and temperature ranges measured does not exceed 1.5 pF and 0.05 microsiemens, respectively. SiC integrated circuits using this package and compatible printed circuit board have been successfully tested at 500 C for over 3736 hours continuously, and at 700 C for over 140 hours. Some test examples of SiC integrated circuits with this packaging system are presented. This package is the key to prolonged T greater than or equal to 500 C operational testing of the new generation of SiC high temperature integrated circuits and other devices currently under development at NASA Glenn Research Center.

Sensor readout detector circuit

DOEpatents

Chu, Dahlon D.; Thelen, Jr., Donald C.

1998-01-01

A sensor readout detector circuit is disclosed that is capable of detecting sensor signals down to a few nanoamperes or less in a high (microampere) background noise level. The circuit operates at a very low standby power level and is triggerable by a sensor event signal that is above a predetermined threshold level. A plurality of sensor readout detector circuits can be formed on a substrate as an integrated circuit (IC). These circuits can operate to process data from an array of sensors in parallel, with only data from active sensors being processed for digitization and analysis. This allows the IC to operate at a low power level with a high data throughput for the active sensors. The circuit may be used with many different types of sensors, including photodetectors, capacitance sensors, chemically-sensitive sensors or combinations thereof to provide a capability for recording transient events or for recording data for a predetermined period of time following an event trigger. The sensor readout detector circuit has applications for portable or satellite-based sensor systems.

Sensor readout detector circuit

DOEpatents

Chu, D.D.; Thelen, D.C. Jr.

1998-08-11

A sensor readout detector circuit is disclosed that is capable of detecting sensor signals down to a few nanoamperes or less in a high (microampere) background noise level. The circuit operates at a very low standby power level and is triggerable by a sensor event signal that is above a predetermined threshold level. A plurality of sensor readout detector circuits can be formed on a substrate as an integrated circuit (IC). These circuits can operate to process data from an array of sensors in parallel, with only data from active sensors being processed for digitization and analysis. This allows the IC to operate at a low power level with a high data throughput for the active sensors. The circuit may be used with many different types of sensors, including photodetectors, capacitance sensors, chemically-sensitive sensors or combinations thereof to provide a capability for recording transient events or for recording data for a predetermined period of time following an event trigger. The sensor readout detector circuit has applications for portable or satellite-based sensor systems. 6 figs.

Silicon CMOS optical receiver circuits with integrated thin-film compound semiconductor detectors

NASA Astrophysics Data System (ADS)

Brooke, Martin A.; Lee, Myunghee; Jokerst, Nan Marie; Camperi-Ginestet, C.

1995-04-01

While many circuit designers have tackled the problem of CMOS digital communications receiver design, few have considered the problem of circuitry suitable for an all CMOS digital IC fabrication process. Faced with a high speed receiver design the circuit designer will soon conclude that a high speed analog-oriented fabrication process provides superior performance advantages to a digital CMOS process. However, for applications where there are overwhelming reasons to integrate the receivers on the same IC as large amounts of conventional digital circuitry, the low yield and high cost of the exotic analog-oriented fabrication is no longer an option. The issues that result from a requirement to use a digital CMOS IC process cut across all aspects of receiver design, and result in significant differences in circuit design philosophy and topology. Digital ICs are primarily designed to yield small, fast CMOS devices for digital logic gates, thus no effort is put into providing accurate or high speed resistances, or capacitors. This lack of any reliable resistance or capacitance has a significant impact on receiver design. Since resistance optimization is not a prerogative of the digital IC process engineer, the wisest option is thus to not use these elements, opting instead for active circuitry to replace the functions normally ascribed to resistance and capacitance. Depending on the application receiver noise may be a dominant design constraint. The noise performance of CMOS amplifiers is different than bipolar or GaAs MESFET circuits, shot noise is generally insignificant when compared to channel thermal noise. As a result the optimal input stage topology is significantly different for the different technologies. It is found that, at speeds of operation approaching the limits of the digital CMOS process, open loop designs have noise-power-gain-bandwidth tradeoff performance superior to feedback designs. Furthermore, the lack of good resisters and capacitors complicates the use of feedback circuits. Thus feedback is generally not used in the front-end of our digital process CMOS receivers.

Superconductive ADC Project Fabrication Package. Final Design Review Package (Briefing Charts)

DTIC Science & Technology

2010-09-07

Simulation Results Iin 1.45mV 2.5Ω 1pH 4pH 100fF 310uA 1fΩ Ic = 300uA Rn = 0.8Ω Cs = 0.32pF Ic = 300uA Rn = 0.8Ω Cs = 0.32pF Iin Vout Vout Ic = 500uA Rn...0.55Ω Cs = 0.32pF ONR Superconductive ADC CLIN/SLIN 0001AD September 2010, Brad Perranoski Pg. 17 Modulator Design Documentation Comparator Design...Comparator Design - Cadence Schematic & Simulation Comparator Testbench Simulation Results 1.45mV 2.5Ω 1pH 4pH 100fF 310uA 1fΩSine wave 100uApk Iin Ic

High-performance packaging for monolithic microwave and millimeter-wave integrated circuits

NASA Technical Reports Server (NTRS)

Shalkhauser, K. A.; Li, K.; Shih, Y. C.

1992-01-01

Packaging schemes are developed that provide low-loss, hermetic enclosure for enhanced monolithic microwave and millimeter-wave integrated circuits. These package schemes are based on a fused quartz substrate material offering improved RF performance through 44 GHz. The small size and weight of the packages make them useful for a number of applications, including phased array antenna systems. As part of the packaging effort, a test fixture was developed to interface the single chip packages to conventional laboratory instrumentation for characterization of the packaged devices.

50 Years of ``Scaling'' Jack Kilby's Invention

NASA Astrophysics Data System (ADS)

Doering, Robert

2008-03-01

This year is the 50th anniversary of Jack Kilby's 1958 invention of the integrated circuit (IC), for which he won the 2000 Nobel Prize in Physics. Since that invention in a laboratory at Texas Instruments, IC components have been continuously miniaturized, which has resulted in exponential improvement trends in their performance, energy efficiency, and cost per function. These improvements have created a semiconductor industry that has grown to over 250B in annual sales. The process of reducing integrated-circuit component size and associated parameters in a coordinated fashion is traditionally called ``feature-size scaling.'' Kilby's original circuit had active (transistor) and passive (resistor, capacitor) components with dimensions of a few millimeters. Today, the minimum feature sizes on integrated circuits are less than 30 nanometers for patterned line widths and down to about one nanometer for film thicknesses. Thus, we have achieved about five orders of magnitude in linear-dimension scaling over the past fifty years, which has resulted in about ten orders of magnitude increase in the density of IC components, a representation of ``Moore's Law.'' As IC features are approaching atomic dimensions, increasing emphasis is now being given to the parallel effort of further diversifying the types of components in integrated circuits. This is called ``functional scaling'' and ``more then Moore.'' Of course, the enablers for both types of scaling have been developed at many laboratories around the world. This talk will review a few of the highlights in scaling and its applications from R&D projects at Texas Instruments.

Silicon photonics devices for metro applications

NASA Astrophysics Data System (ADS)

Fukuda, H.; Kikuchi, K.; Jizodo, M.; Kawamura, Y.; Takeda, K.; Honda, K.

2017-01-01

Digital coherent technology is considered an attractive way of realizing both high-speed metro links and long distance transmissions. In metro areas, there is a strong demand for a smaller, faster transceiver module. This demand is mainly driven by the rapidly increasing data center interconnection traffic, where transmission capacity per faceplane is a key feature. Therefore, optical integration technology is desired. Since compensation in digital coherent technology is performed in the electrical or digital domain, users can deal with those optics performances that are not compensated for digitally. This means using a new material that cannot provide perfect characteristics but that is suitable for miniaturization and integration is possible. Silicon photonics (SiPh) is considered an attractive technology that would enable the significant miniaturization of optical circuits and be capable of optical integration with high manufacturability. While SiPh-based devices have begun to be deployed for very short or short reach links on the basis of direct detection technology, their digital coherent applications have recently been investigated in view of their integration capability. This paper describes recent progress on SiPh-based integrated optical devices for high-speed digital coherent transceivers targeting metro links. An optical modulator and receiver with related circuits have been integrated into a single SiPh chip. TEC-free operation under non-hermetic conditions and the direct attachment of optical fibers have both been realized. Very thin and small packaging with sufficient performance has been demonstrated by using the SiPh chip co-packaged with high-speed ICs.

Plastic-Sealed Hybrid Power Circuit Package

NASA Technical Reports Server (NTRS)

Miller, W. N.; Gray, O. E.

1983-01-01

Proposed design for hybrid high-voltage power-circuit package uses molded plastic for hermetic sealing instead of glass-to-metal seal. New package used to house high-voltage regulators and solid-state switches for applications in aircraft, electric automobiles, industrial equipment, satellites, solarcell arrays, and other equipment in extreme environments.

Emergency OSL/TL dosimetry with integrated circuits from mobile phones

NASA Astrophysics Data System (ADS)

Sholom, S.; McKeever, S. W. S.

2014-09-01

Integrated circuits (ICs) from several mobile phones were studied as possible emergency dosimeters using optically stimulated luminescence (OSL) and thermoluminescence (TL) techniques. Measurement protocols were developed for ICs that take into consideration the effect of sensitization of the samples with increasing dose as well as fading of the signals after sample exposure. It was found that the OSL technique has a higher sensitivity with ICs when compared to TL, while the TL signals were characterized by better stability with time after exposure. Values of minimum measurable doses were found to be in the range between a few tens of mGy and several tens of mGy for the tested samples. It was concluded that ICs from mobile phones could be used for emergency dose reconstruction.

Scaling of graphene integrated circuits.

PubMed

Bianchi, Massimiliano; Guerriero, Erica; Fiocco, Marco; Alberti, Ruggero; Polloni, Laura; Behnam, Ashkan; Carrion, Enrique A; Pop, Eric; Sordan, Roman

2015-05-07

The influence of transistor size reduction (scaling) on the speed of realistic multi-stage integrated circuits (ICs) represents the main performance metric of a given transistor technology. Despite extensive interest in graphene electronics, scaling efforts have so far focused on individual transistors rather than multi-stage ICs. Here we study the scaling of graphene ICs based on transistors from 3.3 to 0.5 μm gate lengths and with different channel widths, access lengths, and lead thicknesses. The shortest gate delay of 31 ps per stage was obtained in sub-micron graphene ROs oscillating at 4.3 GHz, which is the highest oscillation frequency obtained in any strictly low-dimensional material to date. We also derived the fundamental Johnson limit, showing that scaled graphene ICs could be used at high frequencies in applications with small voltage swing.

Methods of fabricating applique circuits

DOEpatents

Dimos, Duane B.; Garino, Terry J.

1999-09-14

Applique circuits suitable for advanced packaging applications are introduced. These structures are particularly suited for the simple integration of large amounts (many nanoFarads) of capacitance into conventional integrated circuit and multichip packaging technology. In operation, applique circuits are bonded to the integrated circuit or other appropriate structure at the point where the capacitance is required, thereby minimizing the effects of parasitic coupling. An immediate application is to problems of noise reduction and control in modern high-frequency circuitry.

Bridging the Hardware-Software Gap: A Proof Carrying Approach for Computer Systems Trust Evaluation (5.3.5)

DTIC Science & Technology

2017-08-22

has significantly lowered the design cost and shortened the time-to- market (TTM) of Integrated Circuits (ICs) in the electronic industry. Over the...semiconductor companies have focused on high-profit phases such as design, marketing , and sales and have outsourced chip manufacturing, wafer fabrication...supply chain has significantly lowered the design cost and shortened the time- to- market (TTM) of integrated circuits (ICs) in the electronic

Modularized construction of general integrated circuits on individual carbon nanotubes.

PubMed

Pei, Tian; Zhang, Panpan; Zhang, Zhiyong; Qiu, Chenguang; Liang, Shibo; Yang, Yingjun; Wang, Sheng; Peng, Lian-Mao

2014-06-11

While constructing general integrated circuits (ICs) with field-effect transistors (FETs) built on individual CNTs is among few viable ways to build ICs with small dimension and high performance that can be compared with that of state-of-the-art Si based ICs, this has not been demonstrated owing to the absence of valid and well-tolerant fabrication method. Here we demonstrate a modularized method for constructing general ICs on individual CNTs with different electric properties. A pass-transistor-logic style 8-transistor (8-T) unit is built, demonstrated as a multifunctional function generator with good tolerance to inhomogeneity in the CNTs used and used as a building block for constructing general ICs. As an example, an 8-bits BUS system that is widely used to transfer data between different systems in a computer is constructed. This is the most complicated IC fabricated on individual CNTs to date, containing 46 FETs built on six individual semiconducting CNTs. The 8-T unit provides a good basis for constructing complex ICs to explore the potential and limits of CNT ICs given the current imperfection in available CNT materials and may also be developed into a universal and efficient way for constructing general ICs on ideal CNT materials in the future.

III-V-on-Silicon Photonic Integrated Circuits for Spectroscopic Sensing in the 2-4 μm Wavelength Range.

PubMed

Wang, Ruijun; Vasiliev, Anton; Muneeb, Muhammad; Malik, Aditya; Sprengel, Stephan; Boehm, Gerhard; Amann, Markus-Christian; Šimonytė, Ieva; Vizbaras, Augustinas; Vizbaras, Kristijonas; Baets, Roel; Roelkens, Gunther

2017-08-04

The availability of silicon photonic integrated circuits (ICs) in the 2-4 μm wavelength range enables miniature optical sensors for trace gas and bio-molecule detection. In this paper, we review our recent work on III-V-on-silicon waveguide circuits for spectroscopic sensing in this wavelength range. We first present results on the heterogeneous integration of 2.3 μm wavelength III-V laser sources and photodetectors on silicon photonic ICs for fully integrated optical sensors. Then a compact 2 μm wavelength widely tunable external cavity laser using a silicon photonic IC for the wavelength selective feedback is shown. High-performance silicon arrayed waveguide grating spectrometers are also presented. Further we show an on-chip photothermal transducer using a suspended silicon-on-insulator microring resonator used for mid-infrared photothermal spectroscopy.

III–V-on-Silicon Photonic Integrated Circuits for Spectroscopic Sensing in the 2–4 μm Wavelength Range

PubMed Central

Wang, Ruijun; Vasiliev, Anton; Muneeb, Muhammad; Malik, Aditya; Sprengel, Stephan; Boehm, Gerhard; Amann, Markus-Christian; Šimonytė, Ieva; Vizbaras, Augustinas; Vizbaras, Kristijonas; Baets, Roel; Roelkens, Gunther

2017-01-01

The availability of silicon photonic integrated circuits (ICs) in the 2–4 μm wavelength range enables miniature optical sensors for trace gas and bio-molecule detection. In this paper, we review our recent work on III–V-on-silicon waveguide circuits for spectroscopic sensing in this wavelength range. We first present results on the heterogeneous integration of 2.3 μm wavelength III–V laser sources and photodetectors on silicon photonic ICs for fully integrated optical sensors. Then a compact 2 μm wavelength widely tunable external cavity laser using a silicon photonic IC for the wavelength selective feedback is shown. High-performance silicon arrayed waveguide grating spectrometers are also presented. Further we show an on-chip photothermal transducer using a suspended silicon-on-insulator microring resonator used for mid-infrared photothermal spectroscopy. PMID:28777291

Monolithic microwave integrated circuits: Interconnections and packaging considerations

NASA Astrophysics Data System (ADS)

Bhasin, K. B.; Downey, A. N.; Ponchak, G. E.; Romanofsky, R. R.; Anzic, G.; Connolly, D. J.

Monolithic microwave integrated circuits (MMIC's) above 18 GHz were developed because of important potential system benefits in cost reliability, reproducibility, and control of circuit parameters. The importance of interconnection and packaging techniques that do not compromise these MMIC virtues is emphasized. Currently available microwave transmission media are evaluated to determine their suitability for MMIC interconnections. An antipodal finline type of microstrip waveguide transition's performance is presented. Packaging requirements for MMIC's are discussed for thermal, mechanical, and electrical parameters for optimum desired performance.

Monolithic microwave integrated circuits: Interconnections and packaging considerations

NASA Technical Reports Server (NTRS)

Bhasin, K. B.; Downey, A. N.; Ponchak, G. E.; Romanofsky, R. R.; Anzic, G.; Connolly, D. J.

1984-01-01

Monolithic microwave integrated circuits (MMIC's) above 18 GHz were developed because of important potential system benefits in cost reliability, reproducibility, and control of circuit parameters. The importance of interconnection and packaging techniques that do not compromise these MMIC virtues is emphasized. Currently available microwave transmission media are evaluated to determine their suitability for MMIC interconnections. An antipodal finline type of microstrip waveguide transition's performance is presented. Packaging requirements for MMIC's are discussed for thermal, mechanical, and electrical parameters for optimum desired performance.

Automated Visual Inspection Of Integrated Circuits

NASA Astrophysics Data System (ADS)

Noppen, G.; Oosterlinck, Andre J.

1989-07-01

One of the major application fields of image processing techniques is the 'visual inspection'. For a number of rea-sons, the automated visual inspection of Integrated Circuits (IC's) has drawn a lot of attention. : Their very strict design makes them very suitable for an automated inspection. : There is already a lot of experience in the comparable Printed Circuit Board (PCB) and mask inspection. : The mechanical handling of wafers and dice is already an established technology. : Military and medical IC's should be a 100 % failproof. : IC inspection gives a high and allinost immediate payback. In this paper we wil try to give an outline of the problems involved in IC inspection, and the algorithms and methods used to overcome these problems. We will not go into de-tail, but we will try to give a general understanding. Our attention will go to the following topics. : An overview of the inspection process, with an emphasis on the second visual inspection. : The problems encountered in IC inspection, as opposed to the comparable PCB and mask inspection. : The image acquisition devices that can be used to obtain 'inspectable' images. : A general overview of the algorithms that can be used. : A short description of the algorithms developed at the ESAT-MI2 division of the katholieke Universiteit Leuven.

Silicon Carbide Integrated Circuit Chip

NASA Image and Video Library

2015-02-17

A multilevel interconnect silicon carbide integrated circuit chip with co-fired ceramic package and circuit board recently developed at the NASA GRC Smart Sensors and Electronics Systems Branch for high temperature applications. High temperature silicon carbide electronics and compatible packaging technologies are elements of instrumentation for aerospace engine control and long term inner-solar planet explorations.

A miniature batteryless health and usage monitoring system based on hybrid energy harvesting

NASA Astrophysics Data System (ADS)

Huang, Chenling; Chakrabartty, Shantanu

2011-04-01

The cost and size of the state-of-the-art health and usage monitoring systems (HUMS) are determined by capacity of on-board energy storage which limits their large scale deployment. In this paper, we present a miniature low-cost mechanical HUMS integrated circuit (IC) based on the concept of hybrid energy harvesting where continuous monitoring is achieved by self-powering, where as the programming, localization and communication with the sensor is achieved using remote RF powering. The self-powered component of the proposed HUMS is based on our previous result which used a controllable hot electron injection on floatinggate transistor as an ultra-low power signal processor. We show that the HUMS IC can seamlessly switch between different energy harvesting modes based on the availability of ambient RF power and that the configuration, programming and communication functions can be remotely performed without physically accessing the HUMS device. All the measured results presented in this paper have been obtained from prototypes fabricated in a 0.5 micron standard CMOS process and the entire system has been successfully integrated on a 1.5cm x 1.5cm package.

Development of Equivalent Material Properties of Microbump for Simulating Chip Stacking Packaging

PubMed Central

Lee, Chang-Chun; Tzeng, Tzai-Liang; Huang, Pei-Chen

2015-01-01

A three-dimensional integrated circuit (3D-IC) structure with a significant scale mismatch causes difficulty in analytic model construction. This paper proposes a simulation technique to introduce an equivalent material composed of microbumps and their surrounding wafer level underfill (WLUF). The mechanical properties of this equivalent material, including Young’s modulus (E), Poisson’s ratio, shear modulus, and coefficient of thermal expansion (CTE), are directly obtained by applying either a tensile load or a constant displacement, and by increasing the temperature during simulations, respectively. Analytic results indicate that at least eight microbumps at the outermost region of the chip stacking structure need to be considered as an accurate stress/strain contour in the concerned region. In addition, a factorial experimental design with analysis of variance is proposed to optimize chip stacking structure reliability with four factors: chip thickness, substrate thickness, CTE, and E-value. Analytic results show that the most significant factor is CTE of WLUF. This factor affects microbump reliability and structural warpage under a temperature cycling load and high-temperature bonding process. WLUF with low CTE and high E-value are recommended to enhance the assembly reliability of the 3D-IC architecture. PMID:28793495

Preparation and properties of sol-gel derived PZT thin films for decoupling capacitor applications

NASA Astrophysics Data System (ADS)

Schwartz, R. W.; Dimos, D.; Lockwood, S. J.; Torres, V. M.

The use of ceramic thin films as decoupling capacitors offers the possibility of capacitor integration within the integrated circuit (IC) package and, potentially, directly onto the IC itself. Since these configurations minimize series inductance, higher operational speeds are possible. In the present study, the authors have investigated the dielectric and leakage characteristics of sol-gel PZT films. For compositions near the morphotropic phase boundary, dielectric constants of 1000, and loss tangents of about 0.02, are observed. The current-voltage behavior of the capacitors is characterized by a non-linear response, and significant asymmetry in both the leakage and breakdown characteristics as a function of bias sign is observed. Breakdown fields for PZT 53/47 thin films are typically approximately 800 kV/cm at 25 C. The authors have also studied the effects of La and Nb dopant additions and alternate firing strategies on film leakage characteristics. Donor doping at 2 - 5 mol % lowers leakage currents by a factor of 10(exp 3). For films prepared by a multilayering approach, firing each layer to crystallization results in leakage currents that are a factor of 10(exp 2) lower than films prepared by the standard process.

Laboratory experiments in integrated circuit fabrication

NASA Technical Reports Server (NTRS)

Jenkins, Thomas J.; Kolesar, Edward S.

1993-01-01

The objectives of the experiment are fourfold: to provide practical experience implementing the fundamental processes and technology associated with the science and art of integrated circuit (IC) fabrication; to afford the opportunity for the student to apply the theory associated with IC fabrication and semiconductor device operation; to motivate the student to exercise engineering decisions associated with fabricating integrated circuits; and to complement the theory of n-channel MOS and diffused devices that are presented in the classroom by actually fabricating and testing them. Therefore, a balance between theory and practice can be realized in the education of young engineers, whose education is often criticized as lacking sufficient design and practical content.

Eddy current measurement of the thickness of top Cu film of the multilayer interconnects in the integrated circuit (IC) manufacturing process

NASA Astrophysics Data System (ADS)

Qu, Zilian; Meng, Yonggang; Zhao, Qian

2015-03-01

This paper proposes a new eddy current method, named equivalent unit method (EUM), for the thickness measurement of the top copper film of multilayer interconnects in the chemical mechanical polishing (CMP) process, which is an important step in the integrated circuit (IC) manufacturing. The influence of the underneath circuit layers on the eddy current is modeled and treated as an equivalent film thickness. By subtracting this equivalent film component, the accuracy of the thickness measurement of the top copper layer with an eddy current sensor is improved and the absolute error is 3 nm for sampler measurement.

Analog/digital pH meter system I.C.

NASA Technical Reports Server (NTRS)

Vincent, Paul; Park, Jea

1992-01-01

The project utilizes design automation software tools to design, simulate, and fabricate a pH meter integrated circuit (IC) system including a successive approximation type seven-bit analog to digital converter circuits using a 1.25 micron N-Well CMOS MOSIS process. The input voltage ranges from 0.5 to 1.0 V derived from a special type pH sensor, and the output is a three-digit decimal number display of pH with one decimal point.

Innovative Teaching of IC Design and Manufacture Using the Superchip Platform

ERIC Educational Resources Information Center

Wilson, P. R.; Wilcock, R.; McNally, I.; Swabey, M.

2010-01-01

This paper describes how an intelligent chip architecture has allowed a large cohort of undergraduate (UG) students to be given effective practical insight into integrated circuit (IC) design by designing and manufacturing their own ICs. To achieve this, an efficient chip architecture, the "Superchip," was developed, which allows multiple student…

A New Microelectronics Curriculum Created by Synopsys, Inc.

ERIC Educational Resources Information Center

Goldman, Rich; Bartleson, Karen; Wood, Troy; Melikyan, Vazgen; Wang, Zhi-hua; Chen, Lan

2009-01-01

Rapid changes in integrated circuits (IC) technology and constantly shrinking process geometries demand a new curriculum that meets the contemporary requirements for IC design. This is especially important for 90nm and below technologies and the use of state-of-the-art EDA design tools and advanced IC design techniques. The creation of new…

A Solder Based Self Assembly Project in an Introductory IC Fabrication Course

ERIC Educational Resources Information Center

Rao, Madhav; Lusth, John C.; Burkett, Susan L.

2015-01-01

Integrated circuit (IC) fabrication principles is an elective course in a senior undergraduate and early graduate student's curriculum. Over the years, the semiconductor industry relies heavily on students with developed expertise in the area of fabrication techniques, learned in an IC fabrication theory and laboratory course. The theory course…

Elevated voltage level I{sub DDQ} failure testing of integrated circuits

DOEpatents

Righter, A.W.

1996-05-21

Burn in testing of static CMOS IC`s is eliminated by I{sub DDQ} testing at elevated voltage levels. These voltage levels are at least 25% higher than the normal operating voltage for the IC but are below voltage levels that would cause damage to the chip. 4 figs.

Long life assurance study for manned spacecraft long life hardware. Volume 2: Long life assurance studies of EEE parts and packaging

NASA Technical Reports Server (NTRS)

1972-01-01

Guidelines for the design, development, and fabrication of electronic components and circuits for use in spacecraft construction are presented. The subjects discussed involve quality control procedures and test methodology for the following subjects: (1) monolithic integrated circuits, (2) hybrid integrated circuits, (3) transistors, (4) diodes, (5) tantalum capacitors, (6) electromechanical relays, (7) switches and circuit breakers, and (8) electronic packaging.

Flip-flop resolving time test circuit

NASA Technical Reports Server (NTRS)

Rosenberger, F.; Chaney, T. J.

1982-01-01

Integrated circuit (IC) flip-flop resolving time parameters are measured by wafer probing, without need of dicing or bonding, throught the incorporation of test structures on an IC together with the flip-flop to be measured. Several delays that are fabricated as part of the test circuit, including a voltage-controlled delay with a resolution of a few picosecs, are calibrated as part of the test procedure by integrating them into, and out of, the delay path of a ring oscillator. Each of the delay values is calculated by subtracting the period of the ring oscillator with the delay omitted from the period with the delay included. The delay measurement technique is sufficiently general for other applications. The technique is illustrated for the case of the flip-flop parameters of a 5-micron feature size NMOS circuit.

Integrated circuit detector technology in abdominal CT: added value in obese patients.

PubMed

Morsbach, Fabian; Bickelhaupt, Sebastian; Rätzer, Susan; Schmidt, Bernhard; Alkadhi, Hatem

2014-02-01

The purpose of this article was to assess the effect of an integrated circuit (IC) detector for abdominal CT on image quality. In the first study part, an abdominal phantom was scanned with various extension rings using a CT scanner equipped with a conventional discrete circuit (DC) detector and on the same scanner with an IC detector (120 kVp, 150 effective mAs, and 75 effective mAs). In the second study part, 20 patients were included who underwent abdominal CT both with the IC detector and previously at similar protocol parameters (120 kVp tube current-time product and 150 reference mAs using automated tube current modulation) with the DC detector. Images were reconstructed with filtered back projection. Image quality in the phantom was higher for images acquired with the IC compared with the DC detector. There was a gradually increasing noise reduction with increasing phantom sizes, with the highest (37% in the largest phantom) at 75 effective mAs (p < 0.001). In patients, noise was overall significantly (p = 0.025) reduced by 6.4% using the IC detector. Similar to the phantom, there was a gradual increase in noise reduction to 7.9% in patients with a body mass index of 25 kg/m(2) or lower (p = 0.008). Significant correlation was found in patients between noise and abdominal diameter in DC detector images (r = 0.604, p = 0.005), whereas no such correlation was found for the IC detector (r = 0.427, p = 0.060). Use of an IC detector in abdominal CT improves image quality and reduces image noise, particularly in overweight and obese patients. This noise reduction has the potential for dose reduction in abdominal CT.

Industry-Oriented Laboratory Development for Mixed-Signal IC Test Education

ERIC Educational Resources Information Center

Hu, J.; Haffner, M.; Yoder, S.; Scott, M.; Reehal, G.; Ismail, M.

2010-01-01

The semiconductor industry is lacking qualified integrated circuit (IC) test engineers to serve in the field of mixed-signal electronics. The absence of mixed-signal IC test education at the collegiate level is cited as one of the main sources for this problem. In response to this situation, the Department of Electrical and Computer Engineering at…

Standard high-reliability integrated circuit logic packaging. [for deep space tracking stations

NASA Technical Reports Server (NTRS)

Slaughter, D. W.

1977-01-01

A family of standard, high-reliability hardware used for packaging digital integrated circuits is described. The design transition from early prototypes to production hardware is covered and future plans are discussed. Interconnections techniques are described as well as connectors and related hardware available at both the microcircuit packaging and main-frame level. General applications information is also provided.

Package Holds Five Monolithic Microwave Integrated Circuits

NASA Technical Reports Server (NTRS)

Mysoor, Narayan R.; Decker, D. Richard; Olson, Hilding M.

1996-01-01

Packages protect and hold monolithic microwave integrated circuit (MMIC) chips while providing dc and radio-frequency (RF) electrical connections for chips undergoing development. Required to be compact, lightweight, and rugged. Designed to minimize undesired resonances, reflections, losses, and impedance mismatches.

An Ultra-Low-Power RFID/NFC Frontend IC Using 0.18 μm CMOS Technology for Passive Tag Applications.

PubMed

Bhattacharyya, Mayukh; Gruenwald, Waldemar; Jansen, Dirk; Reindl, Leonhard; Aghassi-Hagmann, Jasmin

2018-05-07

Battery-less passive sensor tags based on RFID or NFC technology have achieved much popularity in recent times. Passive tags are widely used for various applications like inventory control or in biotelemetry. In this paper, we present a new RFID/NFC frontend IC (integrated circuit) for 13.56 MHz passive tag applications. The design of the frontend IC is compatible with the standard ISO 15693/NFC 5. The paper discusses the analog design part in details with a brief overview of the digital interface and some of the critical measured parameters. A novel approach is adopted for the demodulator design, to demodulate the 10% ASK (amplitude shift keying) signal. The demodulator circuit consists of a comparator designed with a preset offset voltage. The comparator circuit design is discussed in detail. The power consumption of the bandgap reference circuit is used as the load for the envelope detection of the ASK modulated signal. The sub-threshold operation and low-supply-voltage are used extensively in the analog design—to keep the power consumption low. The IC was fabricated using 0.18 μ m CMOS technology in a die area of 1.5 mm × 1.5 mm and an effective area of 0.7 m m 2 . The minimum supply voltage desired is 1.2 V, for which the total power consumption is 107 μ W. The analog part of the design consumes only 36 μ W, which is low in comparison to other contemporary passive tags ICs. Eventually, a passive tag is developed using the frontend IC, a microcontroller, a temperature and a pressure sensor. A smart NFC device is used to readout the sensor data from the tag employing an Android-based application software. The measurement results demonstrate the full passive operational capability. The IC is suitable for low-power and low-cost industrial or biomedical battery-less sensor applications. A figure-of-merit (FOM) is proposed in this paper which is taken as a reference for comparison with other related state-of-the-art researches.

An Ultra-Low-Power RFID/NFC Frontend IC Using 0.18 μm CMOS Technology for Passive Tag Applications

PubMed Central

Gruenwald, Waldemar; Jansen, Dirk; Aghassi-Hagmann, Jasmin

2018-01-01

Battery-less passive sensor tags based on RFID or NFC technology have achieved much popularity in recent times. Passive tags are widely used for various applications like inventory control or in biotelemetry. In this paper, we present a new RFID/NFC frontend IC (integrated circuit) for 13.56 MHz passive tag applications. The design of the frontend IC is compatible with the standard ISO 15693/NFC 5. The paper discusses the analog design part in details with a brief overview of the digital interface and some of the critical measured parameters. A novel approach is adopted for the demodulator design, to demodulate the 10% ASK (amplitude shift keying) signal. The demodulator circuit consists of a comparator designed with a preset offset voltage. The comparator circuit design is discussed in detail. The power consumption of the bandgap reference circuit is used as the load for the envelope detection of the ASK modulated signal. The sub-threshold operation and low-supply-voltage are used extensively in the analog design—to keep the power consumption low. The IC was fabricated using 0.18 μm CMOS technology in a die area of 1.5 mm × 1.5 mm and an effective area of 0.7 mm2. The minimum supply voltage desired is 1.2 V, for which the total power consumption is 107 μW. The analog part of the design consumes only 36 μW, which is low in comparison to other contemporary passive tags ICs. Eventually, a passive tag is developed using the frontend IC, a microcontroller, a temperature and a pressure sensor. A smart NFC device is used to readout the sensor data from the tag employing an Android-based application software. The measurement results demonstrate the full passive operational capability. The IC is suitable for low-power and low-cost industrial or biomedical battery-less sensor applications. A figure-of-merit (FOM) is proposed in this paper which is taken as a reference for comparison with other related state-of-the-art researches. PMID:29735939

Design of high precision temperature control system for TO packaged LD

NASA Astrophysics Data System (ADS)

Liang, Enji; Luo, Baoke; Zhuang, Bin; He, Zhengquan

2017-10-01

Temperature is an important factor affecting the performance of TO package LD. In order to ensure the safe and stable operation of LD, a temperature control circuit for LD based on PID technology is designed. The MAX1978 and an external PID circuit are used to form a control circuit that drives the thermoelectric cooler (TEC) to achieve control of temperature and the external load can be changed. The system circuit has low power consumption, high integration and high precision,and the circuit can achieve precise control of the LD temperature. Experiment results show that the circuit can achieve effective and stable control of the laser temperature.

Fabrication of electrospun polylactic acid nanofilm incorporating cinnamon essential oil/β-cyclodextrin inclusion complex for antimicrobial packaging.

PubMed

Wen, Peng; Zhu, Ding-He; Feng, Kun; Liu, Fang-Jun; Lou, Wen-Yong; Li, Ning; Zong, Min-Hua; Wu, Hong

2016-04-01

A novel antimicrobial packaging material was obtained by incorporating cinnamon essential oil/β-cyclodextrin inclusion complex (CEO/β-CD-IC) into polylacticacid (PLA) nanofibers via electrospinning technique. The CEO/β-CD-IC was prepared by the co-precipitation method and SEM and FT-IR spectroscopy analysis indicated the successful formation of CEO/β-CD-IC, which improved the thermal stability of CEO. The CEO/β-CD-IC was then incorporated into PLA nanofibers by electrospinning and the resulting PLA/CEO/β-CD nanofilm showed better antimicrobial activity compared to PLA/CEO nanofilm. The minimum inhibitory concentration (MIC) of PLA/CEO/β-CD nanofilm against Escherichia coli and Staphylococcus aureus was approximately 1 mg/ml (corresponding CEO concentration 11.35 μg/ml) and minimum bactericidal concentration (MBC) was approximately 7 mg/ml (corresponding CEO concentration 79.45 μg/ml). Furthermore, compared with the casting method, the mild electrospinning process was more favorable for maintaining greater CEO in the obtained film. The PLA/CEO/β-CD nanofilm can effectively prolong the shelf life of pork, suggesting it has potential application in active food packaging. Copyright © 2015 Elsevier Ltd. All rights reserved.

A flexible surface wetness sensor using a RFID technique.

PubMed

Yang, Cheng-Hao; Chien, Jui-Hung; Wang, Bo-Yan; Chen, Ping-Hei; Lee, Da-Sheng

2008-02-01

This paper presents a flexible wetness sensor whose detection signal, converted to a binary code, is transmitted through radio-frequency (RF) waves from a radio-frequency identification integrated circuit (RFID IC) to a remote reader. The flexible sensor, with a fixed operating frequency of 13.56 MHz, contains a RFID IC and a sensor circuit that is fabricated on a flexible printed circuit board (FPCB) using a Micro-Electro-Mechanical-System (MEMS) process. The sensor circuit contains a comb-shaped sensing area surrounded by an octagonal antenna with a width of 2.7 cm. The binary code transmitted from the RFIC to the reader changes if the surface conditions of the detector surface changes from dry to wet. This variation in the binary code can be observed on a digital oscilloscope connected to the reader.

An externally head-mounted wireless neural recording device for laboratory animal research and possible human clinical use.

PubMed

Yin, Ming; Li, Hao; Bull, Christopher; Borton, David A; Aceros, Juan; Larson, Lawrence; Nurmikko, Arto V

2013-01-01

In this paper we present a new type of head-mounted wireless neural recording device in a highly compact package, dedicated for untethered laboratory animal research and designed for future mobile human clinical use. The device, which takes its input from an array of intracortical microelectrode arrays (MEA) has ninety-seven broadband parallel neural recording channels and was integrated on to two custom designed printed circuit boards. These house several low power, custom integrated circuits, including a preamplifier ASIC, a controller ASIC, plus two SAR ADCs, a 3-axis accelerometer, a 48MHz clock source, and a Manchester encoder. Another ultralow power RF chip supports an OOK transmitter with the center frequency tunable from 3GHz to 4GHz, mounted on a separate low loss dielectric board together with a 3V LDO, with output fed to a UWB chip antenna. The IC boards were interconnected and packaged in a polyether ether ketone (PEEK) enclosure which is compatible with both animal and human use (e.g. sterilizable). The entire system consumes 17mA from a 1.2Ahr 3.6V Li-SOCl2 1/2AA battery, which operates the device for more than 2 days. The overall system includes a custom RF receiver electronics which are designed to directly interface with any number of commercial (or custom) neural signal processors for multi-channel broadband neural recording. Bench-top measurements and in vivo testing of the device in rhesus macaques are presented to demonstrate the performance of the wireless neural interface.

Nanoscale x-ray imaging of circuit features without wafer etching.

PubMed

Deng, Junjing; Hong, Young Pyo; Chen, Si; Nashed, Youssef S G; Peterka, Tom; Levi, Anthony J F; Damoulakis, John; Saha, Sayan; Eiles, Travis; Jacobsen, Chris

2017-03-01

Modern integrated circuits (ICs) employ a myriad of materials organized at nanoscale dimensions, and certain critical tolerances must be met for them to function. To understand departures from intended functionality, it is essential to examine ICs as manufactured so as to adjust design rules, ideally in a non-destructive way so that imaged structures can be correlated with electrical performance. Electron microscopes can do this on thin regions, or on exposed surfaces, but the required processing alters or even destroys functionality. Microscopy with multi-keV x-rays provides an alternative approach with greater penetration, but the spatial resolution of x-ray imaging lenses has not allowed one to see the required detail in the latest generation of ICs. X-ray ptychography provides a way to obtain images of ICs without lens-imposed resolution limits, with past work delivering 20-40 nm resolution on thinned ICs. We describe a simple model for estimating the required exposure, and use it to estimate the future potential for this technique. Here we show for the first time that this approach can be used to image circuit detail through an unprocessed 300 μ m thick silicon wafer, with sub-20 nm detail clearly resolved after mechanical polishing to 240 μ m thickness was used to eliminate image contrast caused by Si wafer surface scratches. By using continuous x-ray scanning, massively parallel computation, and a new generation of synchrotron light sources, this should enable entire non-etched ICs to be imaged to 10 nm resolution or better while maintaining their ability to function in electrical tests.

Nanoscale x-ray imaging of circuit features without wafer etching

DOE PAGES

Deng, Junjing; Hong, Young Pyo; Chen, Si; ...

2017-03-24

Modern integrated circuits (ICs) employ a myriad of materials organized at nanoscale dimensions, and certain critical tolerances must be met for them to function. To understand departures from intended functionality, it is essential to examine ICs as manufactured so as to adjust design rules ideally in a nondestructive way so that imaged structures can be correlated with electrical performance. Electron microscopes can do this on thin regions or on exposed surfaces, but the required processing alters or even destroys functionality. Microscopy with multi-keV x-rays provides an alternative approach with greater penetration, but the spatial resolution of x-ray imaging lenses hasmore » not allowed one to see the required detail in the latest generation of ICs. X-ray ptychography provides a way to obtain images of ICs without lens-imposed resolution limits with past work delivering 20–40-nm resolution on thinned ICs. We describe a simple model for estimating the required exposure and use it to estimate the future potential for this technique. Here we show that this approach can be used to image circuit detail through an unprocessed 300-μm-thick silicon wafer with sub-20-nm detail clearly resolved after mechanical polishing to 240-μm thickness was used to eliminate image contrast caused by Si wafer surface scratches. Here, by using continuous x-ray scanning, massively parallel computation, and a new generation of synchrotron light sources, this should enable entire nonetched ICs to be imaged to 10-nm resolution or better while maintaining their ability to function in electrical tests.« less

Nanoscale x-ray imaging of circuit features without wafer etching

NASA Astrophysics Data System (ADS)

Deng, Junjing; Hong, Young Pyo; Chen, Si; Nashed, Youssef S. G.; Peterka, Tom; Levi, Anthony J. F.; Damoulakis, John; Saha, Sayan; Eiles, Travis; Jacobsen, Chris

2017-03-01

Modern integrated circuits (ICs) employ a myriad of materials organized at nanoscale dimensions, and certain critical tolerances must be met for them to function. To understand departures from intended functionality, it is essential to examine ICs as manufactured so as to adjust design rules ideally in a nondestructive way so that imaged structures can be correlated with electrical performance. Electron microscopes can do this on thin regions or on exposed surfaces, but the required processing alters or even destroys functionality. Microscopy with multi-keV x rays provides an alternative approach with greater penetration, but the spatial resolution of x-ray imaging lenses has not allowed one to see the required detail in the latest generation of ICs. X-ray ptychography provides a way to obtain images of ICs without lens-imposed resolution limits with past work delivering 20-40-nm resolution on thinned ICs. We describe a simple model for estimating the required exposure and use it to estimate the future potential for this technique. Here we show that this approach can be used to image circuit detail through an unprocessed 300 -μ m -thick silicon wafer with sub-20-nm detail clearly resolved after mechanical polishing to 240 -μ m thickness was used to eliminate image contrast caused by Si wafer surface scratches. By using continuous x-ray scanning, massively parallel computation, and a new generation of synchrotron light sources, this should enable entire nonetched ICs to be imaged to 10-nm resolution or better while maintaining their ability to function in electrical tests.

Assessment of image quality and low-contrast detectability in abdominal CT of obese patients: comparison of a novel integrated circuit with a conventional discrete circuit detector at different tube voltages.

PubMed

Euler, A; Heye, T; Kekelidze, M; Bongartz, G; Szucs-Farkas, Z; Sommer, C; Schmidt, B; Schindera, Sebastian T

2015-03-01

To compare image quality and low-contrast detectability of an integrated circuit (IC) detector in abdominal CT of obese patients with conventional detector technology at low tube voltages. A liver phantom with 45 lesions was placed in a water container to mimic an obese patient and examined on two different CT systems at 80, 100 and 120 kVp. The systems were equipped with either the IC or conventional detector. Image noise was measured, and the contrast-to-noise-ratio (CNR) was calculated. Low-contrast detectability was assessed independently by three radiologists. Radiation dose was estimated by the volume CT dose index (CTDIvol). The image noise was significantly lower, and the CNR was significantly higher with the IC detector at 80, 100 and 120 kVp, respectively (P = 0.023). The IC detector resulted in an increased lesion detection rate at 80 kVp (38.1 % vs. 17.2 %) and 100 kVp (57.0 % vs. 41.0 %). There was no difference in the detection rate between the IC detector at 100 kVp and the conventional detector at 120 kVp (57.0 % vs. 62.2 %). The CTDIvol at 80, 100 and 120 kVp measured 4.5-5.2, 7.3-7.9 and 9.8-10.2 mGy, respectively. The IC detector at 100 kVp resulted in similar low-contrast detectability compared to the conventional detector with a 120-kVp protocol at a radiation dose reduction of 37 %.

Reliability Assessment of Critical Electronic Components

DTIC Science & Technology

1992-07-01

Failures FLHP - Full Horse Power FSN - Federal Stock Number I Current IC - Integrated Circuit IPB - Illustrated Parts Breakdown K - Boltzmans Constant L...Classified P - Power PC - Printed Circuit PCB - Printed Circuit Board PGA - Pin Grid Array PPM - Parts Per Million PWB - Printed Wiring Board 0...4-59 4.4.3.2.3 Circuit Brcakers ......................................................... 4-59 4.4.3.2.4 Thermal

DIELECTROPHORESIS-BASED MICROFLUIDIC SEPARATION AND DETECTION SYSTEMS

PubMed Central

Yang, Jun; Vykoukal, Jody; Noshari, Jamileh; Becker, Frederick; Gascoyne, Peter; Krulevitch, Peter; Fuller, Chris; Ackler, Harold; Hamilton, Julie; Boser, Bernhard; Eldredge, Adam; Hitchens, Duncan; Andrews, Craig

2009-01-01

Diagnosis and treatment of human diseases frequently requires isolation and detection of certain cell types from a complex mixture. Compared with traditional separation and detection techniques, microfluidic approaches promise to yield easy-to-use diagnostic instruments tolerant of a wide range of operating environments and capable of accomplishing automated analyses. These approaches will enable diagnostic advances to be disseminated from sophisticated clinical laboratories to the point-of-care. Applications will include the separation and differential analysis of blood cell subpopulations for host-based detection of blood cell changes caused by disease, infection, or exposure to toxins, and the separation and analysis of surface-sensitized, custom dielectric beads for chemical, biological, and biomolecular targets. Here we report a new particle separation and analysis microsystem that uses dielectrophoretic field-flow fractionation (DEP-FFF). The system consists of a microfluidic chip with integrated sample injector, a DEP-FFF separator, and an AC impedance sensor. We show the design of a miniaturized impedance sensor integrated circuit (IC) with improved sensitivity, a new packaging approach for micro-flumes that features a slide-together compression package and novel microfluidic interconnects, and the design, control, integration and packaging of a fieldable prototype. Illustrative applications will be shown, including the separation of different sized beads and different cell types, blood cell differential analysis, and impedance sensing results for beads, spores and cells. PMID:22025905

An Integrated-Circuit Temperature Sensor for Calorimetry and Differential Temperature Measurement

NASA Astrophysics Data System (ADS)

Muyskens, Mark

1997-07-01

Our application of an integrated-circuit (IC) temperature sensor which is easy-to-use, inexpensive, rugged, easily computer-interfacable and has good precision is described. The design, based on the National Semiconductor LM35 IC chip, avoids some of the difficulties associated with conventional sensors (thermocouples, thermistors, and platinum resistance thermometers) and a previously described IC sensor. The sensor can be used with a variety of data-acquisition systems. Applications range from general chemistry to physical chemistry, particularly where computer interfaced, digital temperature measurement is desired. Included is a detailed description of our current design with suggestions for improvement and a performance evaluation of the precision in differential measurement and the time constant for responding to temperature change.

Biosignal integrated circuit with simultaneous acquisition of ECG and PPG for wearable healthcare applications.

PubMed

Kim, Hyungseup; Park, Yunjong; Ko, Youngwoon; Mun, Yeongjin; Lee, Sangmin; Ko, Hyoungho

2018-01-01

Wearable healthcare systems require measurements from electrocardiograms (ECGs) and photoplethysmograms (PPGs), and the blood pressure of the user. The pulse transit time (PTT) can be calculated by measuring the ECG and PPG simultaneously. Continuous-time blood pressure without using an air cuff can be estimated by using the PTT. This paper presents a biosignal acquisition integrated circuit (IC) that can simultaneously measure the ECG and PPG for wearable healthcare applications. Included in this biosignal acquisition circuit are a voltage mode instrumentation amplifier (IA) for ECG acquisition and a current mode transimpedance amplifier for PPG acquisition. The analog outputs from the ECG and PPG channels are muxed and converted to digital signals using 12-bit successive approximation register (SAR) analog-to-digital converter (ADC). The proposed IC is fabricated by using a standard 0.18 μm CMOS process with an active area of 14.44 mm2. The total current consumption for the multichannel IC is 327 μA with a 3.3 V supply. The measured input referred noise of ECG readout channel is 1.3 μVRMS with a bandwidth of 0.5 Hz to 100 Hz. And the measured input referred current noise of the PPG readout channel is 0.122 nA/√Hz with a bandwidth of 0.5 Hz to 100 Hz. The proposed IC, which is implemented using various circuit techniques, can measure ECG and PPG signals simultaneously to calculate the PTT for wearable healthcare applications.

Monolithic integrated circuit charge amplifier and comparator for MAMA readout

NASA Technical Reports Server (NTRS)

Cole, Edward H.; Smeins, Larry G.

1991-01-01

Prototype ICs for the Solar Heliospheric Observatory's Multi-Anode Microchannel Array (MAMA) have been developed; these ICs' charge-amplifier and comparator components were then tested with a view to pulse response and noise performance. All model performance predictions have been exceeded. Electrostatic discharge protection has been included on all IC connections; device operation over temperature has been consistent with model predictions.

Scanning fluorescent microthermal imaging apparatus and method

DOEpatents

Barton, Daniel L.; Tangyunyong, Paiboon

1998-01-01

A scanning fluorescent microthermal imaging (FMI) apparatus and method is disclosed, useful for integrated circuit (IC) failure analysis, that uses a scanned and focused beam from a laser to excite a thin fluorescent film disposed over the surface of the IC. By collecting fluorescent radiation from the film, and performing point-by-point data collection with a single-point photodetector, a thermal map of the IC is formed to measure any localized heating associated with defects in the IC.

A way to improve dose rate laser simulation adequacy

DOE Office of Scientific and Technical Information (OSTI.GOV)

Skorobogatov, P.K.; Nikiforov, A.Y.; Demidov, A.A.

1998-12-01

A method for improving laser simulation of dose rate radiation in silicon IC`s (Integrated Circuit) is analyzed based on the application of noncoherent laser radiation. Experimental validation was performed using test structures with up to 90% surface metallization coverage.

Packaging of electro-microfluidic devices

DOEpatents

Benavides, Gilbert L.; Galambos, Paul C.; Emerson, John A.; Peterson, Kenneth A.; Giunta, Rachel K.; Zamora, David Lee; Watson, Robert D.

2003-04-15

A new architecture for packaging surface micromachined electro-microfluidic devices is presented. This architecture relies on two scales of packaging to bring fluid to the device scale (picoliters) from the macro-scale (microliters). The architecture emulates and utilizes electronics packaging technology. The larger package consists of a circuit board with embedded fluidic channels and standard fluidic connectors (e.g. Fluidic Printed Wiring Board). The embedded channels connect to the smaller package, an Electro-Microfluidic Dual-Inline-Package (EMDIP) that takes fluid to the microfluidic integrated circuit (MIC). The fluidic connection is made to the back of the MIC through Bosch-etched holes that take fluid to surface micromachined channels on the front of the MIC. Electrical connection is made to bond pads on the front of the MIC.

Packaging of electro-microfluidic devices

DOEpatents

Benavides, Gilbert L.; Galambos, Paul C.; Emerson, John A.; Peterson, Kenneth A.; Giunta, Rachel K.; Watson, Robert D.

2002-01-01

A new architecture for packaging surface micromachined electro-microfluidic devices is presented. This architecture relies on two scales of packaging to bring fluid to the device scale (picoliters) from the macro-scale (microliters). The architecture emulates and utilizes electronics packaging technology. The larger package consists of a circuit board with embedded fluidic channels and standard fluidic connectors (e.g. Fluidic Printed Wiring Board). The embedded channels connect to the smaller package, an Electro-Microfluidic Dual-Inline-Package (EMDIP) that takes fluid to the microfluidic integrated circuit (MIC). The fluidic connection is made to the back of the MIC through Bosch-etched holes that take fluid to surface micromachined channels on the front of the MIC. Electrical connection is made to bond pads on the front of the MIC.

Flexible Packaging by Film-Assisted Molding for Microintegration of Inertia Sensors

PubMed Central

Hera, Daniel; Berndt, Armin; Günther, Thomas; Schmiel, Stephan; Harendt, Christine; Zimmermann, André

2017-01-01

Packaging represents an important part in the microintegration of sensors based on microelectromechanical system (MEMS). Besides miniaturization and integration density, functionality and reliability in combination with flexibility in packaging design at moderate costs and consequently high-mix, low-volume production are the main requirements for future solutions in packaging. This study investigates possibilities employing printed circuit board (PCB-)based assemblies to provide high flexibility for circuit designs together with film-assisted transfer molding (FAM) to package sensors. The feasibility of FAM in combination with PCB and MEMS as a packaging technology for highly sensitive inertia sensors is being demonstrated. The results prove the technology to be a viable method for damage-free packaging of stress- and pressure-sensitive MEMS. PMID:28653992

In situ high-resolution thermal microscopy on integrated circuits.

PubMed

Zhuo, Guan-Yu; Su, Hai-Ching; Wang, Hsien-Yi; Chan, Ming-Che

2017-09-04

The miniaturization of metal tracks in integrated circuits (ICs) can cause abnormal heat dissipation, resulting in electrostatic discharge, overvoltage breakdown, and other unwanted issues. Unfortunately, locating areas of abnormal heat dissipation is limited either by the spatial resolution or imaging acquisition speed of current thermal analytical techniques. A rapid, non-contact approach to the thermal imaging of ICs with sub-μm resolution could help to alleviate this issue. In this work, based on the intensity of the temperature-dependent two-photon fluorescence (TPF) of Rhodamine 6G (R6G) material, we developed a novel fast and non-invasive thermal microscopy with a sub-μm resolution. Its application to the location of hotspots that may evolve into thermally induced defects in ICs was also demonstrated. To the best of our knowledge, this is the first study to present high-resolution 2D thermal microscopic images of ICs, showing the generation, propagation, and distribution of heat during its operation. According to the demonstrated results, this scheme has considerable potential for future in situ hotspot analysis during the optimization stage of IC development.

Retractable pin dual in-line package test clip

DOEpatents

Bandzuch, Gregory S.; Kosslow, William J.

1996-01-01

This invention is a Dual In-Line Package (DIP) test clip for use when troubleshooting circuits containing DIP integrated circuits. This test clip is a significant improvement over existing DIP test clips in that it has retractable pins which will permit troubleshooting without risk of accidentally shorting adjacent pins together when moving probes to different pins on energized circuits or when the probe is accidentally bumped while taking measurements.

Alpha particle-induced soft errors in microelectronic devices. I

NASA Astrophysics Data System (ADS)

Redman, D. J.; Sega, R. M.; Joseph, R.

1980-03-01

The article provides a tutorial review and trend assessment of the problem of alpha particle-induced soft errors in VLSI memories. Attention is given to an analysis of the design evolution of modern ICs, and the characteristics of alpha particles and their origin in IC packaging are reviewed. Finally, the process of an alpha particle penetrating an IC is examined.

Ultra high speed image processing techniques. [electronic packaging techniques

NASA Technical Reports Server (NTRS)

Anthony, T.; Hoeschele, D. F.; Connery, R.; Ehland, J.; Billings, J.

1981-01-01

Packaging techniques for ultra high speed image processing were developed. These techniques involve the development of a signal feedthrough technique through LSI/VLSI sapphire substrates. This allows the stacking of LSI/VLSI circuit substrates in a 3 dimensional package with greatly reduced length of interconnecting lines between the LSI/VLSI circuits. The reduced parasitic capacitances results in higher LSI/VLSI computational speeds at significantly reduced power consumption levels.

Coplanar monolithic integrated circuits for low-noise communication and radar systems

NASA Astrophysics Data System (ADS)

Bessemoulin, Alexandre; Verweyen, Ludger; Marsetz, Waldemar; Massler, Hermann; Neumann, Markus; Hulsmann, Axel; Schlechtweg, Michael

1999-12-01

This paper presents coplanar millimeter-wave monolithic integrated circuits with high performance and small size for use in low noise communication and radar system applications. Technology and modeling issues with respect to active and passive elements are discussed first. In a second step, the potential of coplanar waveguides to realize compact ICs is illustrated through various design examples, such as low noise amplifiers, mixers and power amplifiers. The performance of multifunctional ICs is also presented by comparing simulated and measured results for a complete 77 GHz Transceive MMIC.

Behavioral modeling of VCSELs for high-speed optical interconnects

NASA Astrophysics Data System (ADS)

Szczerba, Krzysztof; Kocot, Chris

2018-02-01

Transition from on-off keying to 4-level pulse amplitude modulation (PAM) in VCSEL based optical interconnects allows for an increase of data rates, at the cost of 4.8 dB sensitivity penalty. The resulting strained link budget creates a need for accurate VCSEL models for driver integrated circuit (IC) design and system level simulations. Rate equation based equivalent circuit models are convenient for the IC design, but system level analysis requires computationally efficient closed form behavioral models based Volterra series and neural networks. In this paper we present and compare these models.

Design techniques for low-voltage analog integrated circuits

NASA Astrophysics Data System (ADS)

Rakús, Matej; Stopjaková, Viera; Arbet, Daniel

2017-08-01

In this paper, a review and analysis of different design techniques for (ultra) low-voltage integrated circuits (IC) are performed. This analysis shows that the most suitable design methods for low-voltage analog IC design in a standard CMOS process include techniques using bulk-driven MOS transistors, dynamic threshold MOS transistors and MOS transistors operating in weak or moderate inversion regions. The main advantage of such techniques is that there is no need for any modification of standard CMOS structure or process. Basic circuit building blocks like differential amplifiers or current mirrors designed using these approaches are able to operate with the power supply voltage of 600 mV (or even lower), which is the key feature towards integrated systems for modern portable applications.

Heavy-ion induced single-event upset in integrated circuits

NASA Technical Reports Server (NTRS)

Zoutendyk, J. A.

1991-01-01

The cosmic ray environment in space can affect the operation of Integrated Circuit (IC) devices via the phenomenon of Single Event Upset (SEU). In particular, heavy ions passing through an IC can induce sufficient integrated current (charge) to alter the state of a bistable circuit, for example a memory cell. The SEU effect is studied in great detail in both static and dynamic memory devices, as well as microprocessors fabricated from bipolar, Complementary Metal Oxide Semiconductor (CMOS) and N channel Metal Oxide Semiconductor (NMOS) technologies. Each device/process reflects its individual characteristics (minimum scale geometry/process parameters) via a unique response to the direct ionization of electron hole pairs by heavy ion tracks. A summary of these analytical and experimental SEU investigations is presented.

Neural CMOS-integrated circuit and its application to data classification.

PubMed

Göknar, Izzet Cem; Yildiz, Merih; Minaei, Shahram; Deniz, Engin

2012-05-01

Implementation and new applications of a tunable complementary metal-oxide-semiconductor-integrated circuit (CMOS-IC) of a recently proposed classifier core-cell (CC) are presented and tested with two different datasets. With two algorithms-one based on Fisher's linear discriminant analysis and the other based on perceptron learning, used to obtain CCs' tunable parameters-the Haberman and Iris datasets are classified. The parameters so obtained are used for hard-classification of datasets with a neural network structured circuit. Classification performance and coefficient calculation times for both algorithms are given. The CC has 6-ns response time and 1.8-mW power consumption. The fabrication parameters used for the IC are taken from CMOS AMS 0.35-μm technology.

An Integrated-Circuit Temperature Sensor for Calorimetry and Differential Temperature Measurement.

ERIC Educational Resources Information Center

Muyskens, Mark A.

1997-01-01

Describes the application of an integrated-circuit (IC) chip which provides an easy-to-use, inexpensive, rugged, computer-interfaceable temperature sensor for calorimetry and differential temperature measurement. Discusses its design and advantages. (JRH)

Digital correlator with fewer IC's

NASA Technical Reports Server (NTRS)

Apple, G. G.; Rubin, L.

1979-01-01

Digital correlator requires only few integrated circuits to determine synchronization of two 24-bit digital words. Circuit is easily reduced or expanded to accommodate shorter or longer words and can be utilized in industrial and commercial data processing and telecommunications.

Design of high-speed burst mode clock and data recovery IC for passive optical network

NASA Astrophysics Data System (ADS)

Yan, Minhui; Hong, Xiaobin; Huang, Wei-Ping; Hong, Jin

2005-09-01

Design of a high bit rate burst mode clock and data recovery (BMCDR) circuit for gigabit passive optical networks (GPON) is described. A top-down design flow is established and some of the key issues related to the behavioural level modeling are addressed in consideration for the complexity of the BMCDR integrated circuit (IC). Precise implementation of Simulink behavioural model accounting for the saturation of frequency control voltage is therefore developed for the BMCDR, and the parameters of the circuit blocks can be readily adjusted and optimized based on the behavioural model. The newly designed BMCDR utilizes the 0.18um standard CMOS technology and is shown to be capable of operating at bit rate of 2.5Gbps, as well as the recovery time of one bit period in our simulation. The developed behaviour model is verified by comparing with the detailed circuit simulation.

Scanning fluorescent microthermal imaging apparatus and method

DOEpatents

Barton, D.L.; Tangyunyong, P.

1998-01-06

A scanning fluorescent microthermal imaging (FMI) apparatus and method is disclosed, useful for integrated circuit (IC) failure analysis, that uses a scanned and focused beam from a laser to excite a thin fluorescent film disposed over the surface of the IC. By collecting fluorescent radiation from the film, and performing point-by-point data collection with a single-point photodetector, a thermal map of the IC is formed to measure any localized heating associated with defects in the IC. 1 fig.

SPROC: A multiple-processor DSP IC

NASA Technical Reports Server (NTRS)

Davis, R.

1991-01-01

A large, single-chip, multiple-processor, digital signal processing (DSP) integrated circuit (IC) fabricated in HP-Cmos34 is presented. The innovative architecture is best suited for analog and real-time systems characterized by both parallel signal data flows and concurrent logic processing. The IC is supported by a powerful development system that transforms graphical signal flow graphs into production-ready systems in minutes. Automatic compiler partitioning of tasks among four on-chip processors gives the IC the signal processing power of several conventional DSP chips.

Method Of Packaging And Assembling Electro-Microfluidic Devices

DOEpatents

Benavides, Gilbert L.; Galambos, Paul C.; Emerson, John A.; Peterson, Kenneth A.; Giunta, Rachel K.; Zamora, David Lee; Watson, Robert D.

2004-11-23

A new architecture for packaging surface micromachined electro-microfluidic devices is presented. This architecture relies on two scales of packaging to bring fluid to the device scale (picoliters) from the macro-scale (microliters). The architecture emulates and utilizes electronics packaging technology. The larger package consists of a circuit board with embedded fluidic channels and standard fluidic connectors (e.g. Fluidic Printed Wiring Board). The embedded channels connect to the smaller package, an Electro-Microfluidic Dual-Inline-Package (EMDIP) that takes fluid to the microfluidic integrated circuit (MIC). The fluidic connection is made to the back of the MIC through Bosch-etched holes that take fluid to surface micromachined channels on the front of the MIC. Electrical connection is made to bond pads on the front of the MIC.

Packaged die heater

DOEpatents

Spielberger, Richard; Ohme, Bruce Walker; Jensen, Ronald J.

2011-06-21

A heater for heating packaged die for burn-in and heat testing is described. The heater may be a ceramic-type heater with a metal filament. The heater may be incorporated into the integrated circuit package as an additional ceramic layer of the package, or may be an external heater placed in contact with the package to heat the die. Many different types of integrated circuit packages may be accommodated. The method provides increased energy efficiency for heating the die while reducing temperature stresses on testing equipment. The method allows the use of multiple heaters to heat die to different temperatures. Faulty die may be heated to weaken die attach material to facilitate removal of the die. The heater filament or a separate temperature thermistor located in the package may be used to accurately measure die temperature.

77 FR 74027 - Certain Integrated Circuit Packages Provided with Multiple Heat-Conducting Paths and Products...

Federal Register 2010, 2011, 2012, 2013, 2014

2012-12-12

... INTERNATIONAL TRADE COMMISSION [Investigation No. 337-TA-851] Certain Integrated Circuit Packages Provided with Multiple Heat- Conducting Paths and Products Containing Same; Commission Determination Not To... provided with multiple heat-conducting paths and products containing same by reason of infringement of...

A Novel Analog Integrated Circuit Design Course Covering Design, Layout, and Resulting Chip Measurement

ERIC Educational Resources Information Center

Lin, Wei-Liang; Cheng, Wang-Chuan; Wu, Chen-Hao; Wu, Hai-Ming; Wu, Chang-Yu; Ho, Kuan-Hsuan; Chan, Chueh-An

2010-01-01

This work describes a novel, first-year graduate-level analog integrated circuit (IC) design course. The course teaches students analog circuit design; an external manufacturer then produces their designs in three different silicon chips. The students, working in pairs, then test these chips to verify their success. All work is completed within…

Reducing image noise in computed tomography (CT) colonography: effect of an integrated circuit CT detector.

PubMed

Liu, Yu; Leng, Shuai; Michalak, Gregory J; Vrieze, Thomas J; Duan, Xinhui; Qu, Mingliang; Shiung, Maria M; McCollough, Cynthia H; Fletcher, Joel G

2014-01-01

To investigate whether the integrated circuit (IC) detector results in reduced noise in computed tomography (CT) colonography (CTC). Three hundred sixty-six consecutive patients underwent clinically indicated CTC using the same CT scanner system, except for a difference in CT detectors (IC or conventional). Image noise, patient size, and scanner radiation output (volume CT dose index) were quantitatively compared between patient cohorts using each detector system, with separate comparisons for the abdomen and pelvis. For the abdomen and pelvis, despite significantly larger patient sizes in the IC detector cohort (both P < 0.001), image noise was significantly lower (both P < 0.001), whereas volume CT dose index was unchanged (both P > 0.18). Based on the observed image noise reduction, radiation dose could alternatively be reduced by approximately 20% to result in similar levels of image noise. Computed tomography colonography images acquired using the IC detector had significantly lower noise than images acquired using the conventional detector. This noise reduction can permit further radiation dose reduction in CTC.

An integrated control and readout circuit for implantable multi-target electrochemical biosensing.

PubMed

Ghoreishizadeh, Sara S; Baj-Rossi, Camilla; Cavallini, Andrea; Carrara, Sandro; De Micheli, Giovanni

2014-12-01

We describe an integrated biosensor capable of sensing multiple molecular targets using both cyclic voltammetry (CV) and chronoamperometry (CA). In particular, we present our custom IC to realize voltage control and current readout of the biosensors. A mixed-signal circuit block generates sub-Hertz triangular waveform for the biosensors by means of a direct-digital-synthesizer to control CV. A current to pulse-width converter is realized to output the data for CA measurement. The IC is fabricated in 0.18 μm technology. It consumes 220 μW from 1.8 V supply voltage, making it suitable for remotely-powered applications. Electrical measurements show excellent linearity in sub- μA current range. Electrochemical measurements including CA measurements of glucose and lactate and CV measurements of the anti-cancer drug Etoposide have been acquired with the fabricated IC and compared with a commercial equipment. The results obtained with the fabricated IC are in good agreement with those of the commercial equipment for both CV and CA measurements.

500 C Electronic Packaging and Dielectric Materials for High Temperature Applications

NASA Technical Reports Server (NTRS)

Chen, Liang-yu; Neudeck, Philip G.; Spry, David J.; Beheim, Glenn M.; Hunter, Gary W.

2016-01-01

High-temperature environment operable sensors and electronics are required for exploring the inner solar planets and distributed control of next generation aeronautical engines. Various silicon carbide (SiC) high temperature sensors, actuators, and electronics have been demonstrated at and above 500C. A compatible packaging system is essential for long-term testing and application of high temperature electronics and sensors. High temperature passive components are also necessary for high temperature electronic systems. This talk will discuss ceramic packaging systems developed for high temperature electronics, and related testing results of SiC circuits at 500C and silicon-on-insulator (SOI) integrated circuits at temperatures beyond commercial limit facilitated by these high temperature packaging technologies. Dielectric materials for high temperature multilayers capacitors will also be discussed. High-temperature environment operable sensors and electronics are required for probing the inner solar planets and distributed control of next generation aeronautical engines. Various silicon carbide (SiC) high temperature sensors, actuators, and electronics have been demonstrated at and above 500C. A compatible packaging system is essential for long-term testing and eventual applications of high temperature electronics and sensors. High temperature passive components are also necessary for high temperature electronic systems. This talk will discuss ceramic packaging systems developed for high electronics and related testing results of SiC circuits at 500C and silicon-on-insulator (SOI) integrated circuits at temperatures beyond commercial limit facilitated by high temperature packaging technologies. Dielectric materials for high temperature multilayers capacitors will also be discussed.

Vibration analysis of printed circuit boards: Effect of boundary condition

NASA Astrophysics Data System (ADS)

Prashanth, M. D.

2018-04-01

A spacecraft consists of a number of electronic packages to meet the functional requirements. An electronic package is generally an assembly of printed circuit boards placed in a mechanical housing. A number of electronic components are mounted on the printed circuit board (PCB). A spacecraft experiences various types of loads during its launch such as vibration, acoustic and shock loads. Prediction of response for printed circuit boards due to vibration loads is important for mechanical design and reliability of electronic packages. The modeling and analysis of printed circuit boards is required for accurate prediction of response due to vibration loads. The response of PCB is highly dependent on the mounting configuration of PCB. In addition, anti-vibration mounts or stiffeners are used to reduce the PCB response. Vibration analysis of printed circuit boards is carried out using finite element method. The objective of this paper is to determine the dynamic characteristics of a printed circuit board. Modeling and analysis of PCB shall be carried out to study the effect of boundary conditions on the vibration response. The modeling of stiffeners or ribs shall also be considered in detail. The analysis results shall be validated using vibration tests of PCB.

Modular integration of electronics and microfluidic systems using flexible printed circuit boards.

PubMed

Wu, Amy; Wang, Lisen; Jensen, Erik; Mathies, Richard; Boser, Bernhard

2010-02-21

Microfluidic systems offer an attractive alternative to conventional wet chemical methods with benefits including reduced sample and reagent volumes, shorter reaction times, high-throughput, automation, and low cost. However, most present microfluidic systems rely on external means to analyze reaction products. This substantially adds to the size, complexity, and cost of the overall system. Electronic detection based on sub-millimetre size integrated circuits (ICs) has been demonstrated for a wide range of targets including nucleic and amino acids, but deployment of this technology to date has been limited due to the lack of a flexible process to integrate these chips within microfluidic devices. This paper presents a modular and inexpensive process to integrate ICs with microfluidic systems based on standard printed circuit board (PCB) technology to assemble the independently designed microfluidic and electronic components. The integrated system can accommodate multiple chips of different sizes bonded to glass or PDMS microfluidic systems. Since IC chips and flex PCB manufacturing and assembly are industry standards with low cost, the integrated system is economical for both laboratory and point-of-care settings.

Pyrolysis characteristics of integrated circuit boards at various particle sizes and temperatures.

PubMed

Chiang, Hung-Lung; Lin, Kuo-Hsiung; Lai, Mei-Hsiu; Chen, Ting-Chien; Ma, Sen-Yi

2007-10-01

A pyrolysis method was employed to recycle the metals and brominated compounds blended into printed circuit boards. This research investigated the effect of particle size and process temperature on the element composition of IC boards and pyrolytic residues, liquid products, and water-soluble ionic species in the exhaust, with the overall goal being to identify the pyrolysis conditions that will have the least impact on the environment. Integrated circuit (IC) boards were crushed into 5-40 mesh (0.71-4.4mm), and the crushed particles were pyrolyzed at temperatures ranging from 200 to 500 degrees C. The thermal decomposition kinetics were measured by a thermogravimetric (TG) analyzer. The composition of pyrolytic residues was analyzed by Energy Dispersive X-ray Spectrometer (EDS), Inductively Coupled Plasma Atomic Emission Spectrometer (ICP-AES) and Inductively Coupled Plasma-Mass Spectrometry (ICP-MS). In addition, the element compositions of liquid products were analyzed by ICP-AES and ICP-MS. Pyrolytic exhaust was collected by a water-absorption system in an ice-bath cooler, and IC analysis showed that the absorbed solution comprised 11 ionic species. Based on the pyrolytic kinetic parameters of TG analysis and pyrolytic residues at various temperatures for 30 min, the effect of particle size was insignificant in this study, and temperature was the key factor for the IC board pyrolysis. Two stages of decomposition were found for IC board pyrolysis under nitrogen atmosphere. The activation energy was 38-47 kcal/mol for the first-stage reaction and 5.2-9.4 kcal/mol for the second-stage reaction. Metal content was low in the liquid by-product of the IC board pyrolysis process, which is an advantage in that the liquid product could be used as a fuel. Brominate and ammonium were the main water-soluble ionic species of the pyrolytic exhaust. A plan for their safe and effective disposal must be developed if the pyrolytic recycling process is to be applied to IC boards.

Heterostructure-based high-speed/high-frequency electronic circuit applications

NASA Astrophysics Data System (ADS)

Zampardi, P. J.; Runge, K.; Pierson, R. L.; Higgins, J. A.; Yu, R.; McDermott, B. T.; Pan, N.

1999-08-01

With the growth of wireless and lightwave technologies, heterostructure electronic devices are commodity items in the commercial marketplace [Browne J. Power-amplifier MMICs drive commercial circuits. Microwaves & RF, 1998. p. 116-24.]. In particular, HBTs are an attractive device for handset power amplifiers at 900 MHz and 1.9 GHz for CDMA applications [Lum E. GaAs technology rides the wireless wave. Proceedings of the 1997 GaAs IC Symposium, 1997. p. 11-13; "Rockwell Ramps Up". Compound Semiconductor, May/June 1997.]. At higher frequencies, both HBTs and p-HEMTs are expected to dominate the marketplace. For high-speed lightwave circuit applications, heterostructure based products on the market for OC-48 (2.5 Gb/s) and OC-192 (10 Gb/s) are emerging [http://www.nb.rockwell.com/platforms/network_access/nahome.html#5.; http://www.nortel.com/technology/opto/receivers/ptav2.html.]. Chips that operate at 40 Gb/ have been demonstrated in a number of research laboratories [Zampardi PJ, Pierson RL, Runge K, Yu R, Beccue SM, Yu J, Wang KC. hybrid digital/microwave HBTs for >30 Gb/s optical communications. IEDM Technical Digest, 1995. p. 803-6; Swahn T, Lewin T, Mokhtari M, Tenhunen H, Walden R, Stanchina W. 40 Gb/s 3 Volt InP HBT ICs for a fiber optic demonstrator system. Proceedings of the 1996 GaAs IC Symposium, 1996. p. 125-8; Suzuki H, Watanabe K, Ishikawa K, Masuda H, Ouchi K, Tanoue T, Takeyari R. InP/InGaAs HBT ICs for 40 Gbit/s optical transmission systems. Proceedings of the 1997 GaAs IC Symposium, 1997. p. 215-8]. In addition to these two markets, another area where heterostructure devices are having significant impact is for data conversion [Walden RH. Analog-to digital convertor technology comparison. Proceedings of the 1994 GaAs IC Symposium, 1994. p. 217-9; Poulton K, Knudsen K, Corcoran J, Wang KC, Nubling RB, Chang M-CF, Asbeck PM, Huang RT. A 6-b, 4 GSa/s GaAs HBT ADC. IEEE J Solid-State Circuits 1995;30:1109-18; Nary K, Nubling R, Beccue S, Colleran W, Penney J, Wang KC. An 8-bit, 2 gigasample per second analog to digital converter. Proceedings of the 1995 GaAs IC Symposium, 1995. p. 303-6.]. In this paper, we will discuss the present and future trends of heterostructure device applications to these areas.

An integrated circuit with transmit beamforming flip-chip bonded to a 2-D CMUT array for 3-D ultrasound imaging.

PubMed

Wygant, Ira O; Jamal, Nafis S; Lee, Hyunjoo J; Nikoozadeh, Amin; Oralkan, Omer; Karaman, Mustafa; Khuri-Yakub, Butrus T

2009-10-01

State-of-the-art 3-D medical ultrasound imaging requires transmitting and receiving ultrasound using a 2-D array of ultrasound transducers with hundreds or thousands of elements. A tight combination of the transducer array with integrated circuitry eliminates bulky cables connecting the elements of the transducer array to a separate system of electronics. Furthermore, preamplifiers located close to the array can lead to improved receive sensitivity. A combined IC and transducer array can lead to a portable, high-performance, and inexpensive 3-D ultrasound imaging system. This paper presents an IC flip-chip bonded to a 16 x 16-element capacitive micromachined ultrasonic transducer (CMUT) array for 3-D ultrasound imaging. The IC includes a transmit beamformer that generates 25-V unipolar pulses with programmable focusing delays to 224 of the 256 transducer elements. One-shot circuits allow adjustment of the pulse widths for different ultrasound transducer center frequencies. For receiving reflected ultrasound signals, the IC uses the 32-elements along the array diagonals. The IC provides each receiving element with a low-noise 25-MHz-bandwidth transimpedance amplifier. Using a field-programmable gate array (FPGA) clocked at 100 MHz to operate the IC, the IC generated properly timed transmit pulses with 5-ns accuracy. With the IC flip-chip bonded to a CMUT array, we show that the IC can produce steered and focused ultrasound beams. We present 2-D and 3-D images of a wire phantom and 2-D orthogonal cross-sectional images (Bscans) of a latex heart phantom.

Hardening Logic Encryption against Key Extraction Attacks with Circuit Camouflage

DTIC Science & Technology

2017-03-01

camouflage; obfuscation; SAT; key extraction; reverse engineering; security; trusted electronics Introduction Integrated Circuit (IC) designs are...Encryption Algorithms”, Hardware Oriented Security and Trust , 2015. 3. Rajendran J., Pino, Y., Sinanoglu, O., Karri, R., “Security Analysis of Logic

Integrated circuit package with lead structure and method of preparing the same

NASA Technical Reports Server (NTRS)

Kennedy, B. W. (Inventor)

1973-01-01

A beam-lead integrated circuit package assembly including a beam-lead integrated circuit chip, a lead frame array bonded to projecting fingers of the chip, a rubber potting compound disposed around the chip, and an encapsulating molded plastic is described. The lead frame array is prepared by photographically printing a lead pattern on a base metal sheet, selectively etching to remove metal between leads, and plating with gold. Joining of the chip to the lead frame array is carried out by thermocompression bonding of mating goldplated surfaces. A small amount of silicone rubber is then applied to cover the chip and bonded joints, and the package is encapsulated with epoxy resin, applied by molding.

Network interactions within the canine intrinsic cardiac nervous system: implications for reflex control of regional cardiac function

PubMed Central

Beaumont, Eric; Salavatian, Siamak; Southerland, E Marie; Vinet, Alain; Jacquemet, Vincent; Armour, J Andrew; Ardell, Jeffrey L

2013-01-01

The aims of the study were to determine how aggregates of intrinsic cardiac (IC) neurons transduce the cardiovascular milieu versus responding to changes in central neuronal drive and to determine IC network interactions subsequent to induced neural imbalances in the genesis of atrial fibrillation (AF). Activity from multiple IC neurons in the right atrial ganglionated plexus was recorded in eight anaesthetized canines using a 16-channel linear microelectrode array. Induced changes in IC neuronal activity were evaluated in response to: (1) focal cardiac mechanical distortion; (2) electrical activation of cervical vagi or stellate ganglia; (3) occlusion of the inferior vena cava or thoracic aorta; (4) transient ventricular ischaemia, and (5) neurally induced AF. Low level activity (ranging from 0 to 2.7 Hz) generated by 92 neurons was identified in basal states, activities that displayed functional interconnectivity. The majority (56%) of IC neurons so identified received indirect central inputs (vagus alone: 25%; stellate ganglion alone: 27%; both: 48%). Fifty per cent transduced the cardiac milieu responding to multimodal stressors applied to the great vessels or heart. Fifty per cent of IC neurons exhibited cardiac cycle periodicity, with activity occurring primarily in late diastole into isovolumetric contraction. Cardiac-related activity in IC neurons was primarily related to direct cardiac mechano-sensory inputs and indirect autonomic efferent inputs. In response to mediastinal nerve stimulation, most IC neurons became excessively activated; such network behaviour preceded and persisted throughout AF. It was concluded that stochastic interactions occur among IC local circuit neuronal populations in the control of regional cardiac function. Modulation of IC local circuit neuronal recruitment may represent a novel approach for the treatment of cardiac disease, including atrial arrhythmias. PMID:23818689

Testing Services

NASA Technical Reports Server (NTRS)

1993-01-01

Trace Laboratories is an independent testing laboratory specializing in testing printed circuit boards, automotive products and military hardware. Technical information from NASA Tech Briefs and two subsequent JPL Technical Support packages have assisted Trace in testing surface insulation resistance on printed circuit board materials. Testing time was reduced and customer service was improved because of Jet Propulsion Laboratory technical support packages.

77 FR 39735 - Certain Integrated Circuit Packages Provided With Multiple Heat-Conducting Paths and Products...

Federal Register 2010, 2011, 2012, 2013, 2014

2012-07-05

... INTERNATIONAL TRADE COMMISSION [Investigation No. 337-TA-851] Certain Integrated Circuit Packages... AGENCY: U.S. International Trade Commission. ACTION: Notice. SUMMARY: Notice is hereby given that a complaint was filed with the U.S. International Trade Commission on May 31, 2012, under section 337 of the...

Improving depiction of temporal bone anatomy with low-radiation dose CT by an integrated circuit detector in pediatric patients: a preliminary study.

PubMed

He, Jingzhen; Zu, Yuliang; Wang, Qing; Ma, Xiangxing

2014-12-01

The purpose of this study was to determine the performance of low-dose computed tomography (CT) scanning with integrated circuit (IC) detector in defining fine structures of temporal bone in children by comparing with the conventional detector. The study was performed with the approval of our institutional review board and the patients' anonymity was maintained. A total of 86 children<3 years of age underwent imaging of temporal bone with low-dose CT (80 kV/150 mAs) equipped with either IC detector or conventional discrete circuit (DC) detector. The image noise was measured for quantitative analysis. Thirty-five structures of temporal bone were further assessed and rated by 2 radiologists for qualitative analysis. κ Statistics were performed to determine the agreement reached between the 2 radiologists on each image. Mann-Whitney U test was used to determine the difference in image quality between the 2 detector systems. Objective analysis showed that the image noise was significantly lower (P<0.001) with the IC detector than with the DC detector. The κ values for qualitative assessment of the 35 fine anatomical structures revealed high interobserver agreement. The delineation for 30 of the 35 landmarks (86%) with the IC detector was superior to that with the conventional DC detector (P<0.05) although there were no differences in the delineation of the remaining 5 structures (P>0.05). The low-dose CT images acquired with the IC detector provide better depiction of fine osseous structures of temporal bone than that with the conventional DC detector.

The use of light emission in failure analysis of CMOS ICs

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hawkins, C.F.; Soden, J.M.; Cole, E.I. Jr.

1990-01-01

The use of photon emission for analyzing failure mechanisms and defects in CMOS ICs is presented. Techniques are given for accurate identification and spatial localization of failure mechanisms and physical defects, including defects such as short and open circuits which do not themselves emit photons.

Elevated voltage level I.sub.DDQ failure testing of integrated circuits

DOEpatents

Righter, Alan W.

1996-01-01

Burn in testing of static CMOS IC's is eliminated by I.sub.DDQ testing at elevated voltage levels. These voltage levels are at least 25% higher than the normal operating voltage for the IC but are below voltage levels that would cause damage to the chip.

Implantable neurotechnologies: a review of integrated circuit neural amplifiers.

PubMed

Ng, Kian Ann; Greenwald, Elliot; Xu, Yong Ping; Thakor, Nitish V

2016-01-01

Neural signal recording is critical in modern day neuroscience research and emerging neural prosthesis programs. Neural recording requires the use of precise, low-noise amplifier systems to acquire and condition the weak neural signals that are transduced through electrode interfaces. Neural amplifiers and amplifier-based systems are available commercially or can be designed in-house and fabricated using integrated circuit (IC) technologies, resulting in very large-scale integration or application-specific integrated circuit solutions. IC-based neural amplifiers are now used to acquire untethered/portable neural recordings, as they meet the requirements of a miniaturized form factor, light weight and low power consumption. Furthermore, such miniaturized and low-power IC neural amplifiers are now being used in emerging implantable neural prosthesis technologies. This review focuses on neural amplifier-based devices and is presented in two interrelated parts. First, neural signal recording is reviewed, and practical challenges are highlighted. Current amplifier designs with increased functionality and performance and without penalties in chip size and power are featured. Second, applications of IC-based neural amplifiers in basic science experiments (e.g., cortical studies using animal models), neural prostheses (e.g., brain/nerve machine interfaces) and treatment of neuronal diseases (e.g., DBS for treatment of epilepsy) are highlighted. The review concludes with future outlooks of this technology and important challenges with regard to neural signal amplification.

Implantable neurotechnologies: a review of integrated circuit neural amplifiers

PubMed Central

Greenwald, Elliot; Xu, Yong Ping; Thakor, Nitish V.

2016-01-01

Neural signal recording is critical in modern day neuroscience research and emerging neural prosthesis programs. Neural recording requires the use of precise, low-noise amplifier systems to acquire and condition the weak neural signals that are transduced through electrode interfaces. Neural amplifiers and amplifier-based systems are available commercially or can be designed in-house and fabricated using integrated circuit (IC) technologies, resulting in very large-scale integration or application-specific integrated circuit solutions. IC-based neural amplifiers are now used to acquire untethered/portable neural recordings, as they meet the requirements of a miniaturized form factor, light weight and low power consumption. Furthermore, such miniaturized and low-power IC neural amplifiers are now being used in emerging implantable neural prosthesis technologies. This review focuses on neural amplifier-based devices and is presented in two interrelated parts. First, neural signal recording is reviewed, and practical challenges are highlighted. Current amplifier designs with increased functionality and performance and without penalties in chip size and power are featured. Second, applications of IC-based neural amplifiers in basic science experiments (e.g., cortical studies using animal models), neural prostheses (e.g., brain/nerve machine interfaces) and treatment of neuronal diseases (e.g., DBS for treatment of epilepsy) are highlighted. The review concludes with future outlooks of this technology and important challenges with regard to neural signal amplification. PMID:26798055

Packaging Technologies for High Temperature Electronics and Sensors

NASA Technical Reports Server (NTRS)

Chen, Liang-Yu; Hunter, Gary W.; Neudeck, Philip G.; Beheim, Glenn M.; Spry, David J.; Meredith, Roger D.

2013-01-01

This paper reviews ceramic substrates and thick-film metallization based packaging technologies in development for 500 C silicon carbide (SiC) electronics and sensors. Prototype high temperature ceramic chip-level packages and printed circuit boards (PCBs) based on ceramic substrates of aluminum oxide (Al2O3) and aluminum nitride (AlN) have been designed and fabricated. These ceramic substrate-based chip-level packages with gold (Au) thick-film metallization have been electrically characterized at temperatures up to 550 C. A 96% alumina based edge connector for a PCB level subsystem interconnection has also been demonstrated recently. The 96% alumina packaging system composed of chip-level packages and PCBs has been tested with high temperature SiC devices at 500 C for over 10,000 hours. In addition to tests in a laboratory environment, a SiC JFET with a packaging system composed of a 96% alumina chip-level package and an alumina printed circuit board mounted on a data acquisition circuit board was launched as a part of the MISSE-7 suite to the International Space Station via a Shuttle mission. This packaged SiC transistor was successfully tested in orbit for eighteen months. A spark-plug type sensor package designed for high temperature SiC capacitive pressure sensors was developed. This sensor package combines the high temperature interconnection system with a commercial high temperature high pressure stainless steel seal gland (electrical feed-through). Test results of a packaged high temperature capacitive pressure sensor at 500 C are also discussed. In addition to the pressure sensor package, efforts for packaging high temperature SiC diode-based gas chemical sensors are in process.

Packaging Technologies for High Temperature Electronics and Sensors

NASA Technical Reports Server (NTRS)

Chen, Liangyu; Hunter, Gary W.; Neudeck, Philip G.; Beheim, Glenn M.; Spry, David J.; Meredith, Roger D.

2013-01-01

This paper reviews ceramic substrates and thick-film metallization based packaging technologies in development for 500degC silicon carbide (SiC) electronics and sensors. Prototype high temperature ceramic chip-level packages and printed circuit boards (PCBs) based on ceramic substrates of aluminum oxide (Al2O3) and aluminum nitride (AlN) have been designed and fabricated. These ceramic substrate-based chiplevel packages with gold (Au) thick-film metallization have been electrically characterized at temperatures up to 550degC. A 96% alumina based edge connector for a PCB level subsystem interconnection has also been demonstrated recently. The 96% alumina packaging system composed of chip-level packages and PCBs has been tested with high temperature SiC devices at 500degC for over 10,000 hours. In addition to tests in a laboratory environment, a SiC JFET with a packaging system composed of a 96% alumina chip-level package and an alumina printed circuit board mounted on a data acquisition circuit board was launched as a part of the MISSE-7 suite to the International Space Station via a Shuttle mission. This packaged SiC transistor was successfully tested in orbit for eighteen months. A spark-plug type sensor package designed for high temperature SiC capacitive pressure sensors was developed. This sensor package combines the high temperature interconnection system with a commercial high temperature high pressure stainless steel seal gland (electrical feed-through). Test results of a packaged high temperature capacitive pressure sensor at 500degC are also discussed. In addition to the pressure sensor package, efforts for packaging high temperature SiC diode-based gas chemical sensors are in process.

Packaging printed circuit boards: A production application of interactive graphics

NASA Technical Reports Server (NTRS)

Perrill, W. A.

1975-01-01

The structure and use of an Interactive Graphics Packaging Program (IGPP), conceived to apply computer graphics to the design of packaging electronic circuits onto printed circuit boards (PCB), were described. The intent was to combine the data storage and manipulative power of the computer with the imaginative, intuitive power of a human designer. The hardware includes a CDC 6400 computer and two CDC 777 terminals with CRT screens, light pens, and keyboards. The program is written in FORTRAN 4 extended with the exception of a few functions coded in COMPASS (assembly language). The IGPP performs four major functions for the designer: (1) data input and display, (2) component placement (automatic or manual), (3) conductor path routing (automatic or manual), and (4) data output. The most complex PCB packaged to date measured 16.5 cm by 19 cm and contained 380 components, two layers of ground planes and four layers of conductors mixed with ground planes.

Implementation of interconnect simulation tools in spice

NASA Technical Reports Server (NTRS)

Satsangi, H.; Schutt-Aine, J. E.

1993-01-01

Accurate computer simulation of high speed digital computer circuits and communication circuits requires a multimode approach to simulate both the devices and the interconnects between devices. Classical circuit analysis algorithms (lumped parameter) are needed for circuit devices and the network formed by the interconnected devices. The interconnects, however, have to be modeled as transmission lines which incorporate electromagnetic field analysis. An approach to writing a multimode simulator is to take an existing software package which performs either lumped parameter analysis or field analysis and add the missing type of analysis routines to the package. In this work a traditionally lumped parameter simulator, SPICE, is modified so that it will perform lossy transmission line analysis using a different model approach. Modifying SPICE3E2 or any other large software package is not a trivial task. An understanding of the programming conventions used, simulation software, and simulation algorithms is required. This thesis was written to clarify the procedure for installing a device into SPICE3E2. The installation of three devices is documented and the installations of the first two provide a foundation for installation of the lossy line which is the third device. The details of discussions are specific to SPICE, but the concepts will be helpful when performing installations into other circuit analysis packages.

Application of GA package in functional packaging

NASA Astrophysics Data System (ADS)

Belousova, D. A.; Noskova, E. E.; Kapulin, D. V.

2018-05-01

The approach to application program for the task of configuration of the elements of the commutation circuit for design of the radio-electronic equipment on the basis of the genetic algorithm is offered. The efficiency of the used approach for commutation circuits with different characteristics for computer-aided design on radio-electronic manufacturing is shown. The prototype of the computer-aided design subsystem on the basis of a package GA for R with a set of the general functions for optimization of multivariate models is programmed.

Improving yield and reliability of FIB modifications using electrical testing

NASA Astrophysics Data System (ADS)

Desplats, Romain; Benbrik, Jamel; Benteo, Bruno; Perdu, Philippe

1998-08-01

Focused Ion Beam technology has two main areas of application for ICs: modification and preparation for technological analysis. The most solicited area is modification. This involves physically modifying a circuit by cutting lines and creating new ones in order to change the electrical function of the circuit. IC planar technologies have an increasing number of metal interconnections making FIB modifications more complex and decreasing their changes of success. The yield of FIB operations on ICs reflects a downward trend that imposes a greater number of circuits to be modified in order to successfully correct a small number of them. This requires extended duration, which is not compatible with production line turn around times. To respond to this problem, two solutions can be defined: either, reducing the duration of each FIB operation or increasing the success rate of FIB modifications. Since reducing the time depends mainly on FIB operator experience, insuring a higher success rate represents a more crucial aspect as both experienced and novice operators could benefit from this improvement. In order to insure successful modifications, it is necessary to control each step of a FIB operation. To do this, we have developed a new method using in situ electrical testing which has a direct impact on the yield of FIB modifications. We will present this innovative development through a real case study of a CMOS ASIC for high-speed communications. Monitoring the electrical behavior at each step in a FIB operation makes it possible to reduce the number of circuits to be modified and consequently reduces system costs thanks to better yield control. Knowing the internal electrical behavior also gives us indications about the impact on reliability of FIB modified circuits. Finally, this approach can be applied to failure analysis and FIB operations on flip chip circuits.

A multifactor regulatory circuit involving H-NS, VirF and an antisense RNA modulates transcription of the virulence gene icsA of Shigella flexneri.

PubMed

Tran, Chi Nhan; Giangrossi, Mara; Prosseda, Gianni; Brandi, Anna; Di Martino, Maria Letizia; Colonna, Bianca; Falconi, Maurizio

2011-10-01

The icsA gene of Shigella encodes a structural protein involved in colonization of the intestinal mucosa by bacteria. This gene is expressed upon invasion of the host and is controlled by a complex regulatory circuit involving the nucleoid protein H-NS, the AraC-like transcriptional activator VirF, and a 450 nt antisense RNA (RnaG) acting as transcriptional attenuator. We investigated on the interplay of these factors at the molecular level. DNase I footprints reveal that both H-NS and VirF bind to a region including the icsA and RnaG promoters. H-NS is shown to repress icsA transcription at 30°C but not at 37°C, suggesting a significant involvement of this protein in the temperature-regulated expression of icsA. We also demonstrate that VirF directly stimulates icsA transcription and is able to alleviate H-NS repression in vitro. According to these results, icsA expression is derepressed in hns- background and overexpressed when VirF is provided in trans. Moreover, we find that RnaG-mediated transcription attenuation depends on 80 nt at its 5'-end, a stretch carrying the antisense region. Bases engaged in the initial contact leading to sense-antisense pairing have been identified using synthetic RNA and DNA oligonucleotides designed to rebuild and mutagenize the two stem-loop motifs of the antisense region.

Automated Design Tools for Integrated Mixed-Signal Microsystems (NeoCAD)

DTIC Science & Technology

2005-02-01

method, Model Order Reduction (MOR) tools, system-level, mixed-signal circuit synthesis and optimization tools, and parsitic extraction tools. A unique...Mission Area: Command and Control mixed signal circuit simulation parasitic extraction time-domain simulation IC design flow model order reduction... Extraction 1.2 Overall Program Milestones CHAPTER 2 FAST TIME DOMAIN MIXED-SIGNAL CIRCUIT SIMULATION 2.1 HAARSPICE Algorithms 2.1.1 Mathematical Background

Alumina Based 500 C Electronic Packaging Systems and Future Development

NASA Technical Reports Server (NTRS)

Chen, Liang-Yu

2012-01-01

NASA space and aeronautical missions for probing the inner solar planets as well as for in situ monitoring and control of next-generation aeronautical engines require high-temperature environment operable sensors and electronics. A 96% aluminum oxide and Au thick-film metallization based packaging system including chip-level packages, printed circuit board, and edge-connector is in development for high temperature SiC electronics. An electronic packaging system based on this material system was successfully tested and demonstrated with SiC electronics at 500 C for over 10,000 hours in laboratory conditions previously. In addition to the tests in laboratory environments, this packaging system has more recently been tested with a SiC junction field effect transistor (JFET) on low earth orbit through the NASA Materials on the International Space Station Experiment 7 (MISSE7). A SiC JFET with a packaging system composed of a 96% alumina chip-level package and an alumina printed circuit board mounted on a data acquisition circuit board was launched as a part of the MISSE7 suite to International Space Station via a Shuttle mission and tested on the orbit for eighteen months. A summary of results of tests in both laboratory and space environments will be presented. The future development of alumina based high temperature packaging using co-fired material systems for improved performance at high temperature and more feasible mass production will also be discussed.

Auditory cortex controls sound-driven innate defense behaviour through corticofugal projections to inferior colliculus.

PubMed

Xiong, Xiaorui R; Liang, Feixue; Zingg, Brian; Ji, Xu-ying; Ibrahim, Leena A; Tao, Huizhong W; Zhang, Li I

2015-06-11

Defense against environmental threats is essential for animal survival. However, the neural circuits responsible for transforming unconditioned sensory stimuli and generating defensive behaviours remain largely unclear. Here, we show that corticofugal neurons in the auditory cortex (ACx) targeting the inferior colliculus (IC) mediate an innate, sound-induced flight behaviour. Optogenetic activation of these neurons, or their projection terminals in the IC, is sufficient for initiating flight responses, while the inhibition of these projections reduces sound-induced flight responses. Corticocollicular axons monosynaptically innervate neurons in the cortex of the IC (ICx), and optogenetic activation of the projections from the ICx to the dorsal periaqueductal gray is sufficient for provoking flight behaviours. Our results suggest that ACx can both amplify innate acoustic-motor responses and directly drive flight behaviours in the absence of sound input through corticocollicular projections to ICx. Such corticofugal control may be a general feature of innate defense circuits across sensory modalities.

A study on the recycling of scrap integrated circuits by leaching.

PubMed

Lee, Ching-Hwa; Tang, Li-Wen; Popuri, Srinivasa R

2011-07-01

In order to minimize the problem of pollution and to conserve limited natural resources, a method to recover the valuable metals such as gold, silver and copper) present in the scrap integrated circuits (ICs) was developed in the present study. Roasting, grinding, screening, magnetic separation, melting and leaching were adopted to investigate the efficiency of recovery of gold, silver and copper from scrap ICs. The collected scrap IC samples were roasted at 850 °C to destroy their plastic resin sealing material, followed by screening and magnetic separation to separate the metals from the resin residue. The non-ferrous materials (0.840 mm) were mainly composed of copper and could be melted into a copper alloy. Non-ferrous materials containing gold (860.05 ppm), silver (1323.12 ppm) and copper (37259.7 ppm) (size less than 50 mesh) were recovered 100% by a leaching process and thiourea was used as a leaching reagent.

INTEGRATED CIRCUITS FROM MOBILE PHONES AS POSSIBLE EMERGENCY OSL/TL DOSIMETERS.

PubMed

Sholom, S; McKeever, S W S

2016-09-01

In this article, optically stimulated luminescence (OSL) data are presented from integrated circuits (ICs) extracted from mobile phones. The purpose is to evaluate the potential of using OSL from components in personal electronic devices such as smart phones as a means of emergency dosimetry in the event of a large-scale radiological incident. ICs were extracted from five different makes and models of mobile phone. Sample preparation procedures are described, and OSL from the IC samples following irradiation using a (90)Sr/(90)Y source is presented. Repeatability, sensitivity, dose responses, minimum measureable doses, stability and fading data were examined and are described. A protocol for measuring absorbed dose is presented, and it was concluded that OSL from these components is a viable method for assessing dose in the days following a radiological incident. © The Author 2015. Published by Oxford University Press. All rights reserved. For Permissions, please email: journals.permissions@oup.com.

Using Tablet PCs and Interactive Software in IC Design Courses to Improve Learning

ERIC Educational Resources Information Center

Simoni, M.

2011-01-01

This paper describes an initial study of using tablet PCs and interactive course software in integrated circuit (IC) design courses. A rapidly growing community is demonstrating how this technology can improve learning and retention of material by facilitating interaction between faculty and students via cognitive exercises during lectures. While…

An analog integrated circuit beamformer for high-frequency medical ultrasound imaging.

PubMed

Gurun, Gokce; Zahorian, Jaime S; Sisman, Alper; Karaman, Mustafa; Hasler, Paul E; Degertekin, F Levent

2012-10-01

We designed and fabricated a dynamic receive beamformer integrated circuit (IC) in 0.35-μm CMOS technology. This beamformer IC is suitable for integration with an annular array transducer for high-frequency (30-50 MHz) intravascular ultrasound (IVUS) imaging. The beamformer IC consists of receive preamplifiers, an analog dynamic delay-and-sum beamformer, and buffers for 8 receive channels. To form an analog dynamic delay line we designed an analog delay cell based on the current-mode first-order all-pass filter topology, as the basic building block. To increase the bandwidth of the delay cell, we explored an enhancement technique on the current mirrors. This technique improved the overall bandwidth of the delay line by a factor of 6. Each delay cell consumes 2.1-mW of power and is capable of generating a tunable time delay between 1.75 ns to 2.5 ns. We successfully integrated the fabricated beamformer IC with an 8-element annular array. Experimental test results demonstrated the desired buffering, preamplification and delaying capabilities of the beamformer.

Quartz/fused silica chip carriers

NASA Technical Reports Server (NTRS)

1992-01-01

The primary objective of this research and development effort was to develop monolithic microwave integrated circuit (MMIC) packaging which will operate efficiently at millimeter-wave frequencies. The packages incorporated fused silica as the substrate material which was selected due to its favorable electrical properties and potential performance improvement over more conventional materials for Ka-band operation. The first step towards meeting this objective is to develop a package that meets standard mechanical and thermal requirements using fused silica and to be compatible with semiconductor devices operating up to at least 44 GHz. The second step is to modify the package design and add multilayer and multicavity capacity to allow for application specific integrated circuits (ASIC's) to control multiple phase shifters. The final step is to adapt the package design to a phased array module with integral radiating elements. The first task was a continuation of the SBIR Phase 1 work. Phase 1 identified fused silica as a viable substrate material by demonstrating various plating, machining, and adhesion properties. In Phase 2 Task 1, a package was designed and fabricated to validate these findings. Task 2 was to take the next step in packaging and fabricate a multilayer, multichip module (MCM). This package is the predecessor to the phased array module and demonstrates the ability to via fill, circuit print, laminate, and to form vertical interconnects. The final task was to build a phased array module. The radiating elements were to be incorporated into the package instead of connecting to it with wire or ribbon bonds.

Three-Dimensional, Inkjet-Printed Organic Transistors and Integrated Circuits with 100% Yield, High Uniformity, and Long-Term Stability.

PubMed

Kwon, Jimin; Takeda, Yasunori; Fukuda, Kenjiro; Cho, Kilwon; Tokito, Shizuo; Jung, Sungjune

2016-11-22

In this paper, we demonstrate three-dimensional (3D) integrated circuits (ICs) based on a 3D complementary organic field-effect transistor (3D-COFET). The transistor-on-transistor structure was achieved by vertically stacking a p-type OFET over an n-type OFET with a shared gate joining the two transistors, effectively halving the footprint of printed transistors. All the functional layers including organic semiconductors, source/drain/gate electrodes, and interconnection paths were fully inkjet-printed except a parylene dielectric which was deposited by chemical vapor deposition. An array of printed 3D-COFETs and their inverter logic gates comprising over 100 transistors showed 100% yield, and the uniformity and long-term stability of the device were also investigated. A full-adder circuit, the most basic computing unit, has been successfully demonstrated using nine NAND gates based on the 3D structure. The present study fulfills the essential requirements for the fabrication of organic printed complex ICs (increased transistor density, 100% yield, high uniformity, and long-term stability), and the findings can be applied to realize more complex digital/analogue ICs and intelligent devices.

Ion chromatography in the manufacture of multilayer circuit boards

NASA Astrophysics Data System (ADS)

Smith, R. E.

1987-10-01

Ion chromatography (IC) has proven useful in analyzing chemical solutions used in the manufacture of multilayer circuit boards. IC provides results on ions not expected in the production solutions. Thus, solution contamination and breakdown products can be monitored in every phase of the circuit board manufacturing. During the first phase, epoxy laminates experience an etchback, first in chromic acid, which can be analyzed for trace chloride and sulfate, then in ammonium bifluoride/HCl, which can be analyzed for fluoride and chloride. Following a wet blasting to roughen up the surface, 20 mu in. of copper are deposited using an electroless bath. Again, IC is applicable for monitoring formate, tartarate, and sulfate levels. Next, an acid copper bath is used to electroplate the through holes with 0.001 in. of ductile copper. This bath is analyzed for trace chloride. Photoimaging is then performed, and the organic solvents used can be assayed for trace ionic chloride. Finally, a fluoroboric acid-based tin-lead bath is used to deposit a solderable alloy. This bath is analyzed for total fluoroborate, tin, and lead. In addition, mobile phase ion chromatography (MPIC) is used to monitor the nonionic organic brighteners in the baths.

Ion chromatography in the manufacture of multilayer circuit boards

NASA Astrophysics Data System (ADS)

Smith, Robert E.

1990-01-01

Ion chromatography (IC) has proven useful in analyzing chemical solutions used in the manufacture of multilayer circuit boards. Unlike other chemical quantification techniques, IC provides results on ions not expected in the production solutions. Thus, solution contamination and break-down products can be monitored in every phase of the circuit board manufacturing. During the first phase, epoxy laminates experience an etchback, first in chromic acid, which can be analyzed for trace chloride and sulfate, then in ammonium bifluoride/HCl, which can be analyzed for fluoride and chloride. Following a wet-blasting to roughen up the surface, 20 microinches of copper are deposited using an electroless bath. Again, IC is applicable for monitoring formate, tartarate, and sulfate levels. Next, an acid copper bath is used to electroplate the through holes with 0.001 inches of ductile copper. This bath is analyzed for trace chloride. Photoimaging is then performed, and the organic solvents used can be assayed for trace ionic chloride. Finally, a fluoroboric acid-based tin-lead bath is used to deposit a solderable alloy. This bath is analyzed for fluoroborate, tin, and lead. In addition, mobile phase ion chromatography (MPIC) is used to monitor the nonionic organic brighteners in the baths.

Correlation of the ionisation response at selected points of IC sensitive regions with SEE sensitivity parameters under pulsed laser irradiation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gordienko, A V; Mavritskii, O B; Egorov, A N

2014-12-31

The statistics of the ionisation response amplitude measured at selected points and their surroundings within sensitive regions of integrated circuits (ICs) under focused femtosecond laser irradiation is obtained for samples chosen from large batches of two types of ICs. A correlation between these data and the results of full-chip scanning is found for each type. The criteria for express validation of IC single-event effect (SEE) hardness based on ionisation response measurements at selected points are discussed. (laser applications and other topics in quantum electronics)

Integrated circuit layer image segmentation

NASA Astrophysics Data System (ADS)

Masalskis, Giedrius; Petrauskas, Romas

2010-09-01

In this paper we present IC layer image segmentation techniques which are specifically created for precise metal layer feature extraction. During our research we used many samples of real-life de-processed IC metal layer images which were obtained using optical light microscope. We have created sequence of various image processing filters which provides segmentation results of good enough precision for our application. Filter sequences were fine tuned to provide best possible results depending on properties of IC manufacturing process and imaging technology. Proposed IC image segmentation filter sequences were experimentally tested and compared with conventional direct segmentation algorithms.

Effect of Joule heating and current crowding on electromigration in mobile technology

NASA Astrophysics Data System (ADS)

Tu, K. N.; Liu, Yingxia; Li, Menglu

2017-03-01

In the present era of big data and internet of things, the use of microelectronic products in all aspects of our life is manifested by the ubiquitous presence of mobile devices as i-phones and wearable i-products. These devices are facing the need for higher power and greater functionality applications such as in i-health, yet they are limited by physical size. At the moment, software (Apps) is much ahead of hardware in mobile technology. To advance hardware, the end of Moore's law in two-dimensional integrated circuits can be extended by three-dimensional integrated circuits (3D ICs). The concept of 3D ICs has been with us for more than ten years. The challenge in 3D IC technology is dense packing by using both vertical and horizontal interconnections. Mass production of 3D IC devices is behind schedule due to cost because of low yield and uncertain reliability. Joule heating is serious in a dense structure because of heat generation and dissipation. A change of reliability paradigm has advanced from failure at a specific circuit component to failure at a system level weak-link. Currently, the electronic industry is introducing 3D IC devices in mainframe computers, where cost is not an issue, for the purpose of collecting field data of failure, especially the effect of Joule heating and current crowding on electromigration. This review will concentrate on the positive feedback between Joule heating and electromigration, resulting in an accelerated system level weak-link failure. A new driving force of electromigration, the electric potential gradient force due to current crowding, will be reviewed critically. The induced failure tends to occur in the low current density region.

Low-dielectric constant insulators for future integrated circuits and packages.

PubMed

Kohl, Paul A

2011-01-01

Future integrated circuits and packages will require extraordinary dielectric materials for interconnects to allow transistor advances to be translated into system-level advances. Exceedingly low-permittivity and low-loss materials are required at every level of the electronic system, from chip-level insulators to packages and printed wiring boards. In this review, the requirements and goals for future insulators are discussed followed by a summary of current state-of-the-art materials and technical approaches. Much work needs to be done for insulating materials and structures to meet future needs.

Temperature-Adaptive Circuits on Reconfigurable Analog Arrays

NASA Technical Reports Server (NTRS)

Stoica, Adrian; Zebulum, Ricardo S.; Keymeulen, Didier; Ramesham, Rajeshuni; Neff, Joseph; Katkoori, Srinivas

2006-01-01

Demonstration of a self-reconfigurable Integrated Circuit (IC) that would operate under extreme temperature (-180 C and 120 C) and radiation (300krad), without the protection of thermal controls and radiation shields. Self-Reconfigurable Electronics platform: a) Evolutionary Processor (EP) to run reconfiguration mechanism; b) Reconfigurable chip (FPGA, FPAA, etc).

An Integrated Circuit for Simultaneous Extracellular Electrophysiology Recording and Optogenetic Neural Manipulation.

PubMed

Chen, Chang Hao; McCullagh, Elizabeth A; Pun, Sio Hang; Mak, Peng Un; Vai, Mang I; Mak, Pui In; Klug, Achim; Lei, Tim C

2017-03-01

The ability to record and to control action potential firing in neuronal circuits is critical to understand how the brain functions. The objective of this study is to develop a monolithic integrated circuit (IC) to record action potentials and simultaneously control action potential firing using optogenetics. A low-noise and high input impedance (or low input capacitance) neural recording amplifier is combined with a high current laser/light-emitting diode (LED) driver in a single IC. The low input capacitance of the amplifier (9.7 pF) was achieved by adding a dedicated unity gain stage optimized for high impedance metal electrodes. The input referred noise of the amplifier is [Formula: see text], which is lower than the estimated thermal noise of the metal electrode. Thus, the action potentials originating from a single neuron can be recorded with a signal-to-noise ratio of at least 6.6. The LED/laser current driver delivers a maximum current of 330 mA, which is adequate for optogenetic control. The functionality of the IC was tested with an anesthetized Mongolian gerbil and auditory stimulated action potentials were recorded from the inferior colliculus. Spontaneous firings of fifth (trigeminal) nerve fibers were also inhibited using the optogenetic protein Halorhodopsin. Moreover, a noise model of the system was derived to guide the design. A single IC to measure and control action potentials using optogenetic proteins is realized so that more complicated behavioral neuroscience research and the translational neural disorder treatments become possible in the future.

Fabrication process of superconducting integrated circuits with submicron Nb/AlOx/Nb junctions using electron-beam direct writing technique

NASA Astrophysics Data System (ADS)

Aoyagi, Masahiro; Nakagawa, Hiroshi

1997-07-01

For enhancing operating speed of a superconducting integrated circuit (IC), the device size must be reduced into the submicron level. For this purpose, we have introduced electron beam (EB) direct writing technique into the fabrication process of a Nb/AlOx/Nb Josephson IC. A two-layer (PMMA/(alpha) M-CMS) resist method called the portable conformable mask (PCM) method was utilized for having a high aspect ratio. The electron cyclotron resonance (ECR) plasma etching technique was utilized. We have fabricated micron or submicron-size Nb/AlOx/Nb Josephson junctions, where the size of the junction was varied from 2 micrometer to 0.5 micrometer at 0.1 micrometer intervals. These junctions were designed for evaluating the spread of the junction critical current. We achieved minimum-to-maximum Ic spread of plus or minus 13% for 0.81-micrometer-square (plus or minus 16% for 0.67-micrometer-square) 100 junctions spreading in 130- micrometer-square area. The size deviation of 0.05 micrometer was estimated from the spread values. We have successfully demonstrated a small-scale logic IC with 0.9-micrometer-square junctions having a 50 4JL OR-gate chain, where 4JL means four junctions logic family. The circuit was designed for measuring the gate delay. We obtained a preliminary result of the OR- gate logic delay, where the minimum delay was 8.6 ps/gate.

Image Noise, CNR, and Detectability of Low-Contrast, Low-Attenuation Liver Lesions in a Phantom: Effects of Radiation Exposure, Phantom Size, Integrated Circuit Detector, and Iterative Reconstruction.

PubMed

Goenka, Ajit H; Herts, Brian R; Dong, Frank; Obuchowski, Nancy A; Primak, Andrew N; Karim, Wadih; Baker, Mark E

2016-08-01

Purpose To assess image noise, contrast-to-noise ratio (CNR) and detectability of low-contrast, low-attenuation liver lesions in a semianthropomorphic phantom by using either a discrete circuit (DC) detector and filtered back projection (FBP) or an integrated circuit (IC) detector and iterative reconstruction (IR) with changes in radiation exposure and phantom size. Materials and Methods An anthropomorphic phantom without or with a 5-cm-thick fat-mimicking ring (widths, 30 and 40 cm) containing liver inserts with four spherical lesions was scanned with five exposure settings on each of two computed tomography scanners, one equipped with a DC detector and the other with an IC detector. Images from the DC and IC detector scanners were reconstructed with FBP and IR, respectively. Image noise and lesion CNR were measured. Four radiologists evaluated lesion presence on a five-point diagnostic confidence scale. Data analyses included receiver operating characteristic (ROC) curve analysis and noninferiority analysis. Results The combination of IC and IR significantly reduced image noise (P < .001) (with the greatest reduction in the 40-cm phantom and at lower exposures) and improved lesion CNR (P < .001). There was no significant difference in area under the ROC curve between detector-reconstruction combinations at fixed exposure for either phantom. Reader accuracy with IC-IR was noninferior at 50% (100 mAs [effective]) and 25% (300 mAs [effective]) exposure reduction for the 30- and 40-cm phantoms, respectively (adjusted P < .001 and .04 respectively). IC-IR improved readers' confidence in the presence of a lesion (P = .029) independent of phantom size or exposure level. Conclusion IC-IR improved objective image quality and lesion detection confidence but did not result in superior diagnostic accuracy when compared with DC-FBP. Moderate exposure reductions maintained comparable diagnostic accuracy for both detector-reconstruction combinations. Lesion detection in the 40-cm phantom was inferior at smaller exposure reduction than in the 30-cm phantom. (©) RSNA, 2016 Online supplemental material is available for this article.

Area efficient layout design of CMOS circuit for high-density ICs

NASA Astrophysics Data System (ADS)

Mishra, Vimal Kumar; Chauhan, R. K.

2018-01-01

Efficient layouts have been an active area of research to accommodate the greater number of devices fabricated on a given chip area. In this work a new layout of CMOS circuit is proposed, with an aim to improve its electrical performance and reduce the chip area consumed. The study shows that the design of CMOS circuit and SRAM cells comprising tapered body reduced source fully depleted silicon on insulator (TBRS FD-SOI)-based n- and p-type MOS devices. The proposed TBRS FD-SOI n- and p-MOSFET exhibits lower sub-threshold slope and higher Ion to Ioff ratio when compared with FD-SOI MOSFET and FinFET technology. Other parameters like power dissipation, delay time and signal-to-noise margin of CMOS inverter circuits show improvement when compared with available inverter designs. The above device design is used in 6-T SRAM cell so as to see the effect of proposed layout on high density integrated circuits (ICs). The SNM obtained from the proposed SRAM cell is 565 mV which is much better than any other SRAM cell designed at 50 nm gate length MOS device. The Sentaurus TCAD device simulator is used to design the proposed MOS structure.

I/O impedance controller

DOEpatents

Ruesch, Rodney; Jenkins, Philip N.; Ma, Nan

2004-03-09

There is disclosed apparatus and apparatus for impedance control to provide for controlling the impedance of a communication circuit using an all-digital impedance control circuit wherein one or more control bits are used to tune the output impedance. In one example embodiment, the impedance control circuit is fabricated using circuit components found in a standard macro library of a computer aided design system. According to another example embodiment, there is provided a control for an output driver on an integrated circuit ("IC") device to provide for forming a resistor divider network with the output driver and a resistor off the IC device so that the divider network produces an output voltage, comparing the output voltage of the divider network with a reference voltage, and adjusting the output impedance of the output driver to attempt to match the output voltage of the divider network and the reference voltage. Also disclosed is over-sampling the divider network voltage, storing the results of the over sampling, repeating the over-sampling and storing, averaging the results of multiple over sampling operations, controlling the impedance with a plurality of bits forming a word, and updating the value of the word by only one least significant bit at a time.

60 V tolerance full symmetrical switch for battery monitor IC

NASA Astrophysics Data System (ADS)

Zhang, Qidong; Yang, Yintang; Chai, Changchun

2017-06-01

For stacked battery monitoring IC high speed and high precision voltage acquisition requirements, this paper introduces a kind of symmetrical type high voltage switch circuit. This kind of switch circuit uses the voltage following structure, which eliminates the leakage path of input signals. At the same time, this circuit adopts a high speed charge pump structure, in any case the input signal voltage is higher than the supply voltage, it can fast and accurately turn on high voltage MOS devices, and convert the battery voltage to an analog to digital converter. The proposed high voltage full symmetry switch has been implemented in a 0.18 μm BCD process; simulated and measured results show that the proposed switch can always work properly regardless of the polarity of the voltage difference between the input signal ports and an input signal higher than the power supply. Project supported by the National Natural Science Foundation of China (No. 61334003).

High-performance packaging for monolithic microwave and millimeter-wave integrated circuits

NASA Technical Reports Server (NTRS)

Shalkhauser, K. A.; Li, K.; Shih, Y. C.

1992-01-01

Packaging schemes were developed that provide low-loss, hermetic enclosure for advanced monolithic microwave and millimeter-wave integrated circuits (MMICs). The package designs are based on a fused quartz substrate material that offers improved radio frequency (RF) performance through 44 gigahertz (GHz). The small size and weight of the packages make them appropriate for a variety of applications, including phased array antenna systems. Packages were designed in two forms; one for housing a single MMIC chip, the second in the form of a multi-chip phased array module. The single chip array module was developed in three separate sizes, for chips of different geometry and frequency requirements. The phased array module was developed to address packaging directly for antenna applications, and includes transmission line and interconnect structures to support multi-element operation. All packages are fabricated using fused quartz substrate materials. As part of the packaging effort, a test fixture was developed to interface the single chip packages to conventional laboratory instrumentation for characterization of the packaged devices. The package and test fixture designs were both developed in a generic sense, optimizing performance for a wide range of possible applications and devices.

Design and fabrication of a foldable 3D silicon based package for solid state lighting applications

NASA Astrophysics Data System (ADS)

Sokolovskij, R.; Liu, P.; van Zeijl, H. W.; Mimoun, B.; Zhang, G. Q.

2015-05-01

Miniaturization of solid state lighting (SSL) luminaires as well as reduction of packaging and assembly costs are of prime interest for the SSL lighting industry. A novel silicon based LED package for lighting applications is presented in this paper. The proposed design consists of 5 rigid Si tiles connected by flexible polyimide hinges with embedded interconnects (ICs). Electrical, optical and thermal characteristics were taken into consideration during design. The fabrication process involved polyimide (PI) application and patterning, aluminium interconnect integration in the flexible hinge, LED reflector cavity formation and metalization followed by through wafer DRIE etching for chip formation and release. A method to connect chip front to backside without TSVs was also integrated into the process. Post-fabrication wafer level assembly included LED mounting and wirebond, phosphor-based colour conversion and silicone encapsulation. The package formation was finalized by vacuum assisted wrapping around an assembly structure to form a 3D geometry, which is beneficial for omnidirectional lighting. Bending tests were performed on the flexible ICs and optical performance at different temperatures was evaluated. It is suggested that 3D packages can be expanded to platforms for miniaturized luminaire applications by combining monolithic silicon integration and system-in-package (SiP) technologies.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Deng, Junjing; Hong, Young Pyo; Chen, Si

Modern integrated circuits (ICs) employ a myriad of materials organized at nanoscale dimensions, and certain critical tolerances must be met for them to function. To understand departures from intended functionality, it is essential to examine ICs as manufactured so as to adjust design rules ideally in a nondestructive way so that imaged structures can be correlated with electrical performance. Electron microscopes can do this on thin regions or on exposed surfaces, but the required processing alters or even destroys functionality. Microscopy with multi-keV x-rays provides an alternative approach with greater penetration, but the spatial resolution of x-ray imaging lenses hasmore » not allowed one to see the required detail in the latest generation of ICs. X-ray ptychography provides a way to obtain images of ICs without lens-imposed resolution limits with past work delivering 20–40-nm resolution on thinned ICs. We describe a simple model for estimating the required exposure and use it to estimate the future potential for this technique. Here we show that this approach can be used to image circuit detail through an unprocessed 300-μm-thick silicon wafer with sub-20-nm detail clearly resolved after mechanical polishing to 240-μm thickness was used to eliminate image contrast caused by Si wafer surface scratches. Here, by using continuous x-ray scanning, massively parallel computation, and a new generation of synchrotron light sources, this should enable entire nonetched ICs to be imaged to 10-nm resolution or better while maintaining their ability to function in electrical tests.« less

The Design and Assessment of a Hypermedia Course on Semiconductor Manufacturing.

ERIC Educational Resources Information Center

Schank, Patrick K.; Rowe, Lawrence A.

1993-01-01

Describes the design and evaluation of a multimedia course on integrated circuit manufacturing that was developed at the University of California at Berkeley using IC-HIP (Integrated Circuit-Hypermedia in PICASSO), a hypermedia-based instructional system. Learning effects based on prior knowledge, methods of navigation, and other factors are…

Two-Wire to Four-Wire Audio Converter

NASA Technical Reports Server (NTRS)

Talley, G. L., Jr; Seale, B. L.

1983-01-01

Simple circuit provides interface between normally incompatible voicecommunication lines. Circuit maintains 40 dB of isolation between input and output halves of four-wire line permitting two-wire line to be connected. Balancing potentiometer, Rg, adjusts gain of IC2 to null feed through from input to output. Adjustment is done on workbench just after assembly.

Scanning capacitance microscope as a tool for the characterization of integrated circuits

NASA Astrophysics Data System (ADS)

Born, A.; Wiesendanger, R.

With the decreasing size of integrated circuits (ICs), there is an increasing demand for the measurement of doping profiles with high spatial resolution. The scanning capacitance microscope (SCM) offers the possibility of measuring 2D dopant profiles with spatial resolution of less than 20 nm. A great problem of the SCM technique is the influence of previous measurements on subsequent ones. We have observed hysteresis in the SCM images and measured low-frequency C-V curves with high-frequency equipment. A theoretical model was developed to understand this phenomenon. We are now undertaking the first steps using the SCM as a standard device for the characterization of ICs.

Integrated Electrode Arrays for Neuro-Prosthetic Implants

NASA Technical Reports Server (NTRS)

Brandon, Erik; Mojarradi, Mohammede

2003-01-01

Arrays of electrodes integrated with chip-scale packages and silicon-based integrated circuits have been proposed for use as medical electronic implants, including neuro-prosthetic devices that might be implanted in brains of patients who suffer from strokes, spinal-cord injuries, or amyotrophic lateral sclerosis. The electrodes of such a device would pick up signals from neurons in the cerebral cortex, and the integrated circuit would perform acquisition and preprocessing of signal data. The output of the integrated circuit could be used to generate, for example, commands for a robotic arm. Electrode arrays capable of acquiring electrical signals from neurons already exist, but heretofore, there has been no convenient means to integrate these arrays with integrated-circuit chips. Such integration is needed in order to eliminate the need for the extensive cabling now used to pass neural signals to data-acquisition and -processing equipment outside the body. The proposed integration would enable progress toward neuro-prostheses that would be less restrictive of patients mobility. An array of electrodes would comprise a set of thin wires of suitable length and composition protruding from and supported by a fine-pitch micro-ball grid array or chip-scale package (see figure). The associated integrated circuit would be mounted on the package face opposite the probe face, using the solder bumps (the balls of the ball grid array) to make the electrical connections between the probes and the input terminals of the integrated circuit. The key innovation is the insertion of probe wires of the appropriate length and material into the solder bumps through a reflow process, thereby fixing the probes in place and electrically connecting them with the integrated circuit. The probes could be tailored to any distribution of lengths and made of any suitable metal that could be drawn into fine wires. Furthermore, the wires could be coated with an insulating layer using anodization or other processes, to achieve the correct electrical impedance. The probe wires and the packaging materials must be biocompatible using such materials as lead-free solders. For protection, the chip and package can be coated with parylene.

Digital model of a vacuum circuit breaker for the analysis of switching waveforms in electrical circuits

NASA Astrophysics Data System (ADS)

Budzisz, Joanna; Wróblewski, Zbigniew

2016-03-01

The article presents a method of modelling a vaccum circuit breaker in the ATP/EMTP package, the results of the verification of the correctness of the developed digital circuit breaker model operation and its practical usefulness for analysis of overvoltages and overcurrents occurring in commutated capacitive electrical circuits and also examples of digital simulations of overvoltages and overcurrents in selected electrical circuits.

Conformal Thin Film Packaging for SiC Sensor Circuits in Harsh Environments

NASA Technical Reports Server (NTRS)

Scardelletti, Maximilian C.; Karnick, David A.; Ponchak, George E.; Zorman, Christian A.

2011-01-01

In this investigation sputtered silicon carbide annealed at 300 C for one hour is used as a conformal thin film package. A RF magnetron sputterer was used to deposit 500 nm silicon carbide films on gold metal structures on alumina wafers. To determine the reliability and resistance to immersion in harsh environments, samples were submerged in gold etchant for 24 hours, in BOE for 24 hours, and in an O2 plasma etch for one hour. The adhesion strength of the thin film was measured by a pull test before and after the chemical immersion, which indicated that the film has an adhesion strength better than 10(exp 8) N/m2; this is similar to the adhesion of the gold layer to the alumina wafer. MIM capacitors are used to determine the dielectric constant, which is dependent on the SiC anneal temperature. Finally, to demonstrate that the SiC, conformal, thin film may be used to package RF circuits and sensors, an LC resonator circuit was fabricated and tested with and without the conformal SiC thin film packaging. The results indicate that the SiC coating adds no appreciable degradation to the circuits RF performance. Index Terms Sputter, silicon carbide, MIM capacitors, LC resonators, gold etchants, BOE, O2 plasma

Description of the three axis low-g accelerometer package

NASA Technical Reports Server (NTRS)

Amalavage, A. J.; Fikes, E. H.; Berry, E. H.

1978-01-01

The three axis low-g accelerometer package designed for use on the Space Processing Application Rocket (SPAR) Program is described. The package consists of the following major sections: (1) three Kearfott model 2412 accelerometers mounted in an orthogonal triad configuration on a temperature controlled, thermally isolated cube, (2) the accelerometer servoelectronics (printed circuit cards PC-6 through PC-12), and (3) the signal conditioner (printed circuit cards PC-15 and PC-16). The measurement range is 0 + or - 0.031 g with a quantization of 1.1 x 10 to the 7th power g. The package was flown successfully on six SPAR launches with the Black Brant booster. These flights provide approximately 300 s of free fall or zero-g environment.

[An integral chip for the multiphase pulse-duration modulation used for voltage changer in biomedical microprocessor systems].

PubMed

Balashov, A M; Selishchev, S V

2004-01-01

An integral chip (IC) was designed for controlling the step-down pulse voltage converter, which is based on the multiphase pulse-duration modulation, for use in biomedical microprocessor systems. The CMOS technology was an optimal basis for the IC designing. An additional feedback circuit diminishes the output voltage dispersion at dynamically changing loads.

Qualification and Reliability for MEMS and IC Packages

NASA Technical Reports Server (NTRS)

Ghaffarian, Reza

2004-01-01

Advanced IC electronic packages are moving toward miniaturization from two key different approaches, front and back-end processes, each with their own challenges. Successful use of more of the back-end process front-end, e.g. microelectromechanical systems (MEMS) Wafer Level Package (WLP), enable reducing size and cost. Use of direct flip chip die is the most efficient approach if and when the issues of know good die and board/assembly are resolved. Wafer level package solve the issue of known good die by enabling package test, but it has its own limitation, e.g., the I/O limitation, additional cost, and reliability. From the back-end approach, system-in-a-package (SIAP/SIP) development is a response to an increasing demand for package and die integration of different functions into one unit to reduce size and cost and improve functionality. MEMS add another challenging dimension to electronic packaging since they include moving mechanical elements. Conventional qualification and reliability need to be modified and expanded in most cases in order to detect new unknown failures. This paper will review four standards that already released or being developed that specifically address the issues on qualification and reliability of assembled packages. Exposures to thermal cycles, monotonic bend test, mechanical shock and drop are covered in these specifications. Finally, mechanical and thermal cycle qualification data generated for MEMS accelerometer will be presented. The MEMS was an element of an inertial measurement unit (IMU) qualified for NASA Mars Exploration Rovers (MERs), Spirit and Opportunity that successfully is currently roaring the Martian surface

Variational data assimilation system "INM RAS - Black Sea"

NASA Astrophysics Data System (ADS)

Parmuzin, Eugene; Agoshkov, Valery; Assovskiy, Maksim; Giniatulin, Sergey; Zakharova, Natalia; Kuimov, Grigory; Fomin, Vladimir

2013-04-01

Development of Informational-Computational Systems (ICS) for Data Assimilation Procedures is one of multidisciplinary problems. To study and solve these problems one needs to apply modern results from different disciplines and recent developments in: mathematical modeling; theory of adjoint equations and optimal control; inverse problems; numerical methods theory; numerical algebra and scientific computing. The problems discussed above are studied in the Institute of Numerical Mathematics of the Russian Academy of Science (INM RAS) in ICS for Personal Computers (PC). Special problems and questions arise while effective ICS versions for PC are being developed. These problems and questions can be solved with applying modern methods of numerical mathematics and by solving "parallelism problem" using OpenMP technology and special linear algebra packages. In this work the results on the ICS development for PC-ICS "INM RAS - Black Sea" are presented. In the work the following problems and questions are discussed: practical problems that can be studied by ICS; parallelism problems and their solutions with applying of OpenMP technology and the linear algebra packages used in ICS "INM - Black Sea"; Interface of ICS. The results of ICS "INM RAS - Black Sea" testing are presented. Efficiency of technologies and methods applied are discussed. The work was supported by RFBR, grants No. 13-01-00753, 13-05-00715 and by The Ministry of education and science of Russian Federation, project 8291, project 11.519.11.1005 References: [1] V.I. Agoshkov, M.V. Assovskii, S.A. Lebedev, Numerical simulation of Black Sea hydrothermodynamics taking into account tide-forming forces. Russ. J. Numer. Anal. Math. Modelling (2012) 27, No.1, 5-31 [2] E.I. Parmuzin, V.I. Agoshkov, Numerical solution of the variational assimilation problem for sea surface temperature in the model of the Black Sea dynamics. Russ. J. Numer. Anal. Math. Modelling (2012) 27, No.1, 69-94 [3] V.B. Zalesny, N.A. Diansky, V.V. Fomin, S.N. Moshonkin, S.G. Demyshev, Numerical model of the circulation of Black Sea and Sea of Azov. Russ. J. Numer. Anal. Math. Modelling (2012) 27, No.1, 95-111 [4] V.I. Agoshkov, S.V. Giniatulin, G.V. Kuimov. OpenMP technology and linear algebra packages in the variation data assimilation systems. - Abstracts of the 1-st China-Russia Conference on Numerical Algebra with Applications in Radiactive Hydrodynamics, Beijing, China, October 16-18, 2012. [5] Zakharova N.B., Agoshkov V.I., Parmuzin E.I., The new method of ARGO buoys system observation data interpolation. Russian Journal of Numerical Analysis and Mathematical Modelling. Vol. 28, Issue 1, 2013.

VCSEL-based optical transceiver module operating at 25 Gb/s and using a single CMOS IC

NASA Astrophysics Data System (ADS)

Afriat, Gil; Horwitz, Lior; Lazar, Dror; Issachar, Assaf; Pogrebinsky, Alexander; Ran, Adee; Shoor, Ehud; Bar, Roi; Saba, Rushdy

2012-01-01

We present here a low cost, small form factor, optical transceiver module composed of a CMOS IC transceiver, 850 nm emission wavelength VCSEL modulated at 25 Gb/s, and an InGaAs/InP PIN Photo Diode (PD). The transceiver IC is fabricated in a standard 28 nm CMOS process and integrates the analog circuits interfacing the VCSEL and PD, namely the VCSEL driver and Transimpedance Amplifier (TIA), as well as all other required transmitter and receiver circuits like Phase Locked Loop (PLL), Post Amplifier and Clock & Data Recovery (CDR). The transceiver module couples into a 62.5/125 um multi-mode (OM1) TX/RX fiber pair via a low cost plastic cover realizing the transmitter and receiver lens systems and demonstrates BER < 10-12 at the 25 Gb/s data rate over a distance of 3 meters. Using a 50/125 um laser optimized multi-mode fiber (OM3), the same performance was achieved over a distance of 30 meters.

Auditory cortex controls sound-driven innate defense behaviour through corticofugal projections to inferior colliculus

PubMed Central

Xiong, Xiaorui R.; Liang, Feixue; Zingg, Brian; Ji, Xu-ying; Ibrahim, Leena A.; Tao, Huizhong W.; Zhang, Li I.

2015-01-01

Defense against environmental threats is essential for animal survival. However, the neural circuits responsible for transforming unconditioned sensory stimuli and generating defensive behaviours remain largely unclear. Here, we show that corticofugal neurons in the auditory cortex (ACx) targeting the inferior colliculus (IC) mediate an innate, sound-induced flight behaviour. Optogenetic activation of these neurons, or their projection terminals in the IC, is sufficient for initiating flight responses, while the inhibition of these projections reduces sound-induced flight responses. Corticocollicular axons monosynaptically innervate neurons in the cortex of the IC (ICx), and optogenetic activation of the projections from the ICx to the dorsal periaqueductal gray is sufficient for provoking flight behaviours. Our results suggest that ACx can both amplify innate acoustic-motor responses and directly drive flight behaviours in the absence of sound input through corticocollicular projections to ICx. Such corticofugal control may be a general feature of innate defense circuits across sensory modalities. PMID:26068082

Drive and protection circuit for converter module of cascaded H-bridge STATCOM

NASA Astrophysics Data System (ADS)

Wang, Xuan; Yuan, Hongliang; Wang, Xiaoxing; Wang, Shuai; Fu, Yongsheng

2018-04-01

Drive and protection circuit is an important part of power electronics, which is related to safe and stable operation issues in the power electronics. The drive and protection circuit is designed for the cascaded H-bridge STATCOM. This circuit can realize flexible dead-time setting, operation status self-detection, fault priority protection and detailed fault status uploading. It can help to improve the reliability of STATCOM's operation. Finally, the proposed circuit is tested and analyzed by power electronic simulation software PSPICE (Simulation Program with IC Emphasis) and a series of experiments. Further studies showed that the proposed circuit can realize drive and control of H-bridge circuit, meanwhile it also can realize fast processing faults and have advantage of high reliability.

Attachment method for stacked integrated circuit (IC) chips

DOEpatents

Bernhardt, Anthony F.; Malba, Vincent

1999-01-01

An attachment method for stacked integrated circuit (IC) chips. The method involves connecting stacked chips, such as DRAM memory chips, to each other and/or to a circuit board. Pads on the individual chips are rerouted to form pads on the side of the chip, after which the chips are stacked on top of each other whereby desired interconnections to other chips or a circuit board can be accomplished via the side-located pads. The pads on the side of a chip are connected to metal lines on a flexible plastic tape (flex) by anisotropically conductive adhesive (ACA). Metal lines on the flex are likewise connected to other pads on chips and/or to pads on a circuit board. In the case of a stack of DRAM chips, pads to corresponding address lines on the various chips may be connected to the same metal line on the flex to form an address bus. This method has the advantage of reducing the number of connections required to be made to the circuit board due to bussing; the flex can accommodate dimensional variation in the alignment of chips in the stack; bonding of the ACA is accomplished at low temperature and is otherwise simpler and less expensive than solder bonding; chips can be bonded to the ACA all at once if the sides of the chips are substantially coplanar, as in the case for stacks of identical chips, such as DRAM.

A bipolar analog front-end integrated circuit for the SDC silicon tracker

NASA Astrophysics Data System (ADS)

Kipnis, I.; Spieler, H.; Collins, T.

1993-11-01

A low noise, low power, high bandwidth, radiation hard, silicon bipolar transistor full-custom integrated circuit (IC) containing 64 channels of analog signal processing has been developed for the SDC silicon tracker. The IC was designed and tested at LBL and was fabricated using CBIC-U2, 4 GHz f(sub T) complementary bipolar technology. Each channel contains the following functions: low noise preamplification, pulse shaping, and threshold discrimination. This is the first iteration of the production analog IC for the SDC silicon tracker. The IC is laid out to directly match the 50 micron pitch double-sided silicon strip detector. The chip measures 6.8 mm by 3.1 mm and contains 3,600 transistors. Three stages of amplification provide 180 mV/fC of gain with a 35 nsec peaking time at the comparator input. For a 14 pF detector capacitance, the equivalent noise charge is 1300 el. rms at a power consumption of 1 mW/channel from a single 3.5 V supply. With the discriminator threshold set to four times the noise level, a 16 nsec time-walk for 1.25 to 10 fC signals is achieved using a time-walk compensation network. Irradiation tests at TRIUMF to a Phi = 10(exp 14) protons/sq cm have been performed on the IC, demonstrating the radiation hardness of the complementary bipolar process.

Switched-capacitor realization of presynaptic short-term-plasticity and stop-learning synapses in 28 nm CMOS.

PubMed

Noack, Marko; Partzsch, Johannes; Mayr, Christian G; Hänzsche, Stefan; Scholze, Stefan; Höppner, Sebastian; Ellguth, Georg; Schüffny, Rene

2015-01-01

Synaptic dynamics, such as long- and short-term plasticity, play an important role in the complexity and biological realism achievable when running neural networks on a neuromorphic IC. For example, they endow the IC with an ability to adapt and learn from its environment. In order to achieve the millisecond to second time constants required for these synaptic dynamics, analog subthreshold circuits are usually employed. However, due to process variation and leakage problems, it is almost impossible to port these types of circuits to modern sub-100nm technologies. In contrast, we present a neuromorphic system in a 28 nm CMOS process that employs switched capacitor (SC) circuits to implement 128 short term plasticity presynapses as well as 8192 stop-learning synapses. The neuromorphic system consumes an area of 0.36 mm(2) and runs at a power consumption of 1.9 mW. The circuit makes use of a technique for minimizing leakage effects allowing for real-time operation with time constants up to several seconds. Since we rely on SC techniques for all calculations, the system is composed of only generic mixed-signal building blocks. These generic building blocks make the system easy to port between technologies and the large digital circuit part inherent in an SC system benefits fully from technology scaling.

A neural circuit transforming temporal periodicity information into a rate-based representation in the mammalian auditory system.

PubMed

Dicke, Ulrike; Ewert, Stephan D; Dau, Torsten; Kollmeier, Birger

2007-01-01

Periodic amplitude modulations (AMs) of an acoustic stimulus are presumed to be encoded in temporal activity patterns of neurons in the cochlear nucleus. Physiological recordings indicate that this temporal AM code is transformed into a rate-based periodicity code along the ascending auditory pathway. The present study suggests a neural circuit for the transformation from the temporal to the rate-based code. Due to the neural connectivity of the circuit, bandpass shaped rate modulation transfer functions are obtained that correspond to recorded functions of inferior colliculus (IC) neurons. In contrast to previous modeling studies, the present circuit does not employ a continuously changing temporal parameter to obtain different best modulation frequencies (BMFs) of the IC bandpass units. Instead, different BMFs are yielded from varying the number of input units projecting onto different bandpass units. In order to investigate the compatibility of the neural circuit with a linear modulation filterbank analysis as proposed in psychophysical studies, complex stimuli such as tones modulated by the sum of two sinusoids, narrowband noise, and iterated rippled noise were processed by the model. The model accounts for the encoding of AM depth over a large dynamic range and for modulation frequency selective processing of complex sounds.

Half-dose non-contrast CT in the investigation of urolithiasis: image quality improvement with third-generation integrated circuit CT detectors.

PubMed

Wang, Jun; Kang, Tony; Arepalli, Chesnal; Barrett, Sarah; O'Connell, Tim; Louis, Luck; Nicolaou, Savvakis; McLaughlin, Patrick

2015-06-01

The objective of this study is to establish the effect of third-generation integrated circuit (IC) CT detector on objective image quality in full- and half-dose non-contrast CT of the urinary tract. 51 consecutive patients with acute renal colic underwent non-contrast CT of the urinary tract using a 128-slice dual-source CT before (n = 24) and after (n = 27) the installation of third-generation IC detectors. Half-dose images were generated using projections from detector A using the dual-source RAW data. Objective image noise in the liver, spleen, right renal cortex, and right psoas muscle was compared between DC and IC cohorts for full-dose and half-dose images reconstructed with FBP and IR algorithms using 1 cm(2) regions of interest. Presence and size of obstructing ureteric calculi were also compared for full-dose and half-dose reconstructions using DC and IC detectors. No statistical difference in age and lateral body size was found between patients in the IC and DC cohorts. Radiation dose, as measured by size-specific dose estimates, did not differ significantly either between the two cohorts (10.02 ± 4.54 mGy IC vs. 12.28 ± 7.03 mGy DC). At full dose, objective image noise was not significantly lower in the IC cohort as compared to the DC cohort for the liver, spleen, and right psoas muscle. At half dose, objective image noise was lower in the IC cohort as compared to DC cohort at the liver (21.32 IC vs. 24.99 DC, 14.7% decrease, p < 0.001), spleen (19.33 IC vs. 20.83 DC, 7.20% decrease, p = 0.02), and right renal cortex (20.28 IC vs. 22.98 DC, 11.7% decrease, p = 0.005). Mean obstructing ureteric calculi size was not significantly different when comparison was made between full-dose and half-dose images, regardless of detector type (p > 0.05 for all comparisons). Third-generation IC detectors result in lower objective image noise at full- and half-radiation dose levels as compared with traditional DC detectors. The magnitude of noise reduction was greater at half-radiation dose indicating that the benefits of using novel IC detectors are greater in low and ultra-low-dose CT imaging.

Integrated three-dimensional module heat exchanger for power electronics cooling

DOEpatents

Bennion, Kevin; Lustbader, Jason

2013-09-24

Embodiments discussed herein are directed to a power semiconductor packaging that removes heat from a semiconductor package through one or more cooling zones that are located in a laterally oriented position with respect to the semiconductor package. Additional embodiments are directed to circuit elements that are constructed from one or more modular power semiconductor packages.

Integrated readout electronics for Belle II pixel detector

NASA Astrophysics Data System (ADS)

Blanco, R.; Leys, R.; Perić, I.

2018-03-01

This paper describes the readout components for Belle II that have been designed as integrated circuits. The ICs are connected to DEPFET sensor by bump bonding. Three types of ICs have been developed: SWITCHER for pixel matrix control, DCD for readout and digitizing of sensor signals and DHP for digital data processing. The ICs are radiation tolerant and use several novel features, such as the multiple-input differential amplifiers and the fast and radiation hard high-voltage drivers. SWITCHER and DCD have been developed at University of Heidelberg, Karlsruhe Institute of Technology (KIT) and DHP at Bonn University. The IC-development started in 2009 and was accomplished in 2016 with the submissions of final designs. The final ICs for Belle II pixel detector and the related measurement results will be presented in this contribution.

Modelling of optoelectronic circuits based on resonant tunneling diodes

NASA Astrophysics Data System (ADS)

Rei, João. F. M.; Foot, James A.; Rodrigues, Gil C.; Figueiredo, José M. L.

2017-08-01

Resonant tunneling diodes (RTDs) are the fastest pure electronic semiconductor devices at room temperature. When integrated with optoelectronic devices they can give rise to new devices with novel functionalities due to their highly nonlinear properties and electrical gain, with potential applications in future ultra-wide-band communication systems (see e.g. EU H2020 iBROW Project). The recent coverage on these devices led to the need to have appropriated simulation tools. In this work, we present RTD based optoelectronic circuits simulation packages to provide circuit signal level analysis such as transient and frequency responses. We will present and discuss the models, and evaluate the simulation packages.

Innovative Magnetic-Field Array Probe for TRUST Integrated Circuits

DTIC Science & Technology

2017-03-01

real-time an IC device. This non-invasive solution is cost effective, with a small form factor. Keywords: Electromagnetic radiation; Near-Field...solicitation was to design, develop and fabricate a low cost electromagnetic probe array for ICs counterfeit. The probe array should operate in the near...Our overall effort was focus on modeling, designing, fabricating, and utilizing novel electromagnetic probes for the analysis, characterization

Night-day-night sleep-wakefulness monitoring by ambulatory integrated circuit memories.

PubMed

Yamamoto, M; Nakao, M; Katayama, N; Waku, M; Suzuki, K; Irokawa, K; Abe, M; Ueno, T

1999-04-01

A medium-sized portable digital recorder with fully integrated circuit (IC) memories for sleep monitoring has been developed. It has five amplifiers for EEG, EMG, EOG, ECG, and a signal of body acceleration or respiration sound, four event markers, an 8 ch A/D converter, a digital signal processor (DSP), 192 Mbytes IC flash memories, and batteries. The whole system weighs 1200 g including batteries and is put into a small bag worn on the subject's waist or carried in their hand. The sampling rate for each input channel is programmable through the DSP. This apparatus is valuable for continuously monitoring the states of sleep-wakefulness over 24 h, making a night-day-night recording possible in a hospital, home, or car.

Prototyping and implementing flight qualifiable semicustom CMOS P-well bulk integrated circuits in the JPL environment

NASA Technical Reports Server (NTRS)

Olson, E. M.

1986-01-01

Presently, there are many difficulties associated with implementing application specific custom or semi-custom (standard cell based) integrated circuits (ICs) into JPL flight projects. One of the primary difficulties is developing prototype semi-custom integrated circuits for use and evaluation in engineering prototype flight hardware. The prototype semi-custom ICs must be extremely cost-effective and yet still representative of flight qualifiable versions of the design. A second difficulty is encountered in the transport of the design from engineering prototype quality to flight quality. Normally, flight quality integrated circuits have stringent quality standards, must be radiation resistant and should consume minimal power. It is often not necessary or cost effective, however, to impose such stringent quality standards on engineering models developed for systems analysis in controlled lab environments. This article presents work originally initiated for ground based applications that also addresses these two problems. Furthermore, this article suggests a method that has been shown successful in prototyping flight quality semi-custom ICs through the Metal Oxide Semiconductor Implementation Service (MOSIS) program run by the University of Southern California's Information Sciences Institute. The method has been used successfully to design and fabricate through the MOSIS three different semi-custom prototype CMOS p-well chips. The three designs make use of the work presented and were designed consistent with design techniques and structures that are flight qualifiable, allowing one hour transfer of the design from engineering model status to flight qualifiable foundry-ready status through methods outlined in this article.

Analysis of a Statistical Relationship Between Dose and Error Tallies in Semiconductor Digital Integrated Circuits for Application to Radiation Monitoring Over a Wireless Sensor Network

NASA Astrophysics Data System (ADS)

Colins, Karen; Li, Liqian; Liu, Yu

2017-05-01

Mass production of widely used semiconductor digital integrated circuits (ICs) has lowered unit costs to the level of ordinary daily consumables of a few dollars. It is therefore reasonable to contemplate the idea of an engineered system that consumes unshielded low-cost ICs for the purpose of measuring gamma radiation dose. Underlying the idea is the premise of a measurable correlation between an observable property of ICs and radiation dose. Accumulation of radiation-damage-induced state changes or error events is such a property. If correct, the premise could make possible low-cost wide-area radiation dose measurement systems, instantiated as wireless sensor networks (WSNs) with unshielded consumable ICs as nodes, communicating error events to a remote base station. The premise has been investigated quantitatively for the first time in laboratory experiments and related analyses performed at the Canadian Nuclear Laboratories. State changes or error events were recorded in real time during irradiation of samples of ICs of different types in a 60Co gamma cell. From the error-event sequences, empirical distribution functions of dose were generated. The distribution functions were inverted and probabilities scaled by total error events, to yield plots of the relationship between dose and error tallies. Positive correlation was observed, and discrete functional dependence of dose quantiles on error tallies was measured, demonstrating the correctness of the premise. The idea of an engineered system that consumes unshielded low-cost ICs in a WSN, for the purpose of measuring gamma radiation dose over wide areas, is therefore tenable.

Four-Channel PC/104 MIL-STD-1553 Circuit Board

NASA Technical Reports Server (NTRS)

Cox, Gary L.

2004-01-01

The mini bus interface card (miniBIC) is the first four-channel electronic circuit board that conforms to MIL-STD-1553 and to the electrical-footprint portion of PC/104. [MIL-STD-1553 is a military standard that encompasses a method of communication and electrical- interface requirements for digital electronic subsystems connected to a data bus. PC/104 is an industry standard for compact, stackable modules that are fully compatible (in architecture, hardware, and software) with personal-computer data- and power-bus circuitry.] Prior to the development of the miniBIC, only one- and two-channel PC/104 MIL-STD-1553 boards were available. To obtain four channels, it was necessary to include at least two boards in a PC/104 stack. In comparison with such a two-board stack, the miniBIC takes up less space, consumes less power, and is more reliable. In addition, the miniBIC includes 32 digital input/output channels. The miniBIC (see figure) contains four MIL-STD-1553B hybrid integrated circuits (ICs), four transformers, a field-programmable gate array (FPGA), and an Industry Standard Architecture (ISA) interface. Each hybrid IC includes a MILSTD-1553 dual transceiver, memory-management circuitry, processor interface logic circuitry, and 64Kx16 bits of shared static random access memory. The memory is used to configure message and data blocks. In addition, 23 16-bit registers are available for (1) configuring the hybrid IC for, and starting it in, various modes of operation; (2) reading the status of the functionality of the hybrid IC; and (3) resetting the hybrid IC to a known state. The miniBIC can operate as a remote terminal, bus controller, or bus monitor. The FPGA provides the chip-select and data-strobe signals needed for operation of the hybrid ICs. The FPGA also receives interruption signals and forwards them to the ISA bus. The ISA interface connects the address, data, and control interfaces of the hybrid ICs to the ISA backplane. Each channel is, in effect, a MIL-STD-1553 interface that can operate either independently of the others or else as a redundant version of one of the others. The transformer in each channel provides electrical isolation between the rest of the miniBIC circuitry and the bus to which that channel is connected.

High Temperature Pt/Alumina Co-Fired System for 500 C Electronic Packaging Applications

NASA Technical Reports Server (NTRS)

Chen, Liang-Yu; Neudeck, Philip G.; Spry, David J.; Beheim, Glenn M.; Hunter, Gary W.

2015-01-01

Gold thick-film metallization and 96 alumina substrate based prototype packaging system developed for 500C SiC electronics and sensors is briefly reviewed, the needs of improvement are discussed. A high temperature co-fired alumina material system based packaging system composed of 32-pin chip-level package and printed circuit board is discussed for packaging 500C SiC electronics and sensors.

SPICE Modeling of Body Bias Effect in 4H-SiC Integrated Circuit Resistors

NASA Technical Reports Server (NTRS)

Neudeck, Philip G.

2017-01-01

The DC electrical behavior of n-type 4H-SiC resistors used for realizing 500C durable integrated circuits (ICs) is studied as a function of substrate bias and temperature. Improved fidelity electrical simulation is described using SPICE NMOS model to simulate resistor substrate body bias effect that is absent from the SPICE semiconductor resistor model.

Ambient temperature cadmium zinc telluride radiation detector and amplifier circuit

DOEpatents

McQuaid, James H.; Lavietes, Anthony D.

1998-05-29

A low noise, low power consumption, compact, ambient temperature signal amplifier for a Cadmium Zinc Telluride (CZT) radiation detector. The amplifier can be used within a larger system (e.g., including a multi-channel analyzer) to allow isotopic analysis of radionuclides in the field. In one embodiment, the circuit stages of the low power, low noise amplifier are constructed using integrated circuit (IC) amplifiers , rather than discrete components, and include a very low noise, high gain, high bandwidth dual part preamplification stage, an amplification stage, and an filter stage. The low noise, low power consumption, compact, ambient temperature amplifier enables the CZT detector to achieve both the efficiency required to determine the presence of radio nuclides and the resolution necessary to perform isotopic analysis to perform nuclear material identification. The present low noise, low power, compact, ambient temperature amplifier enables a CZT detector to achieve resolution of less than 3% full width at half maximum at 122 keV for a Cobalt-57 isotope source. By using IC circuits and using only a single 12 volt supply and ground, the novel amplifier provides significant power savings and is well suited for prolonged portable in-field use and does not require heavy, bulky power supply components.

NASA Tech Briefs, July 1999. Volume 23, No. 7

NASA Technical Reports Server (NTRS)

1999-01-01

Topics: Test and Measurement; Electronic Components and Circuits; Electronic Systems; Physical Sciences; Materials; Computer Software; Mechanics; Machinery/Automation; Bio-Medical; Books and Reports; Semiconductors/ICs.

Modular chassis simplifies packaging and interconnecting of circuit boards

NASA Technical Reports Server (NTRS)

Arens, W. E.; Boline, K. G.

1964-01-01

A system of modular chassis structures has simplified the design for mounting a number of printed circuit boards. This design is structurally adaptable to computer and industrial control system applications.

Design and performance of clock-recovery GaAs ICs for high-speed optical communication systems

NASA Astrophysics Data System (ADS)

Imai, Yuhki; Sano, Eiichi; Nakamura, Makoto; Ishihara, Noboru; Kikuchi, Hiroyuki; Ono, Takashi

1993-05-01

Design and performance of clock-recovery GaAs ICs are presented. Four kinds of ICs were developed: a limiting amplifier, a tuning amplifier, a rectifier, and a differentiator. The cascaded limiting amplifier together with a tuning amplifier achieved a 58-dB gain and a 10-degree phase deviation with 20-dB input dynamic range at 10 GHz. A clock-recovery circuit successfully extracts a low-jitter 10-GHz clock signal of 1-dBm constant power from 10-Gb/s NRZ pseudorandom bit streams using a pulse pattern generator.

Experimentally Observed Electrical Durability of 4H-SiC JFET ICs Operating from 500 C to 700 C

NASA Technical Reports Server (NTRS)

Neudeck, Philip G.; Spry, David J.; Chen, Liangyu; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.

2016-01-01

Prolonged 500 degrees Celsius to 700 degrees Celsius electrical testing data from 4H-SiC junction field effect transistor (JFET) integrated circuits (ICs) are combined with post-testing microscopic studies in order to gain more comprehensive understanding of the durability limits of the present version of NASA Glenn's extreme temperature microelectronics technology. The results of this study support the hypothesis that T = 500 degrees Celsius durability-limiting IC failure initiates with thermal-stress-related crack formation where dielectric passivation layers overcoat micron-scale vertical features including patterned metal traces.

Electrical Characterization of 4H-SiC JFET Wafer: DC Parameter Variations for Extreme Temperature IC Design

NASA Technical Reports Server (NTRS)

Neudeck, Philip G.; Chen, Liangyu; Spry, David J.; Beheim, Glenn M.; Chang, Carl W.

2014-01-01

This work reports DC electrical characterization of a 76 mm diameter 4H-SiC JFET test wafer fabricated as part of NASA's on-going efforts to realize medium-scale ICs with prolonged and stable circuit operation at temperatures as high as 500 degC. In particular, these measurements provide quantitative parameter ranges for use in JFET IC design and simulation. Larger than expected parameter variations were observed both as a function of position across the wafer as well as a function of ambient testing temperature from 23 degC to 500 degC.

Development of high-performance printed organic field-effect transistors and integrated circuits.

PubMed

Xu, Yong; Liu, Chuan; Khim, Dongyoon; Noh, Yong-Young

2015-10-28

Organic electronics is regarded as an important branch of future microelectronics especially suited for large-area, flexible, transparent, and green devices, with their low cost being a key benefit. Organic field-effect transistors (OFETs), the primary building blocks of numerous expected applications, have been intensively studied, and considerable progress has recently been made. However, there are still a number of challenges to the realization of high-performance OFETs and integrated circuits (ICs) using printing technologies. Therefore, in this perspective article, we investigate the main issues concerning developing high-performance printed OFETs and ICs and seek strategies for further improvement. Unlike many other studies in the literature that deal with organic semiconductors (OSCs), printing technology, and device physics, our study commences with a detailed examination of OFET performance parameters (e.g., carrier mobility, threshold voltage, and contact resistance) by which the related challenges and potential solutions to performance development are inspected. While keeping this complete understanding of device performance in mind, we check the printed OFETs' components one by one and explore the possibility of performance improvement regarding device physics, material engineering, processing procedure, and printing technology. Finally, we analyze the performance of various organic ICs and discuss ways to optimize OFET characteristics and thus develop high-performance printed ICs for broad practical applications.

Low-power analog integrated circuits for wireless ECG acquisition systems.

PubMed

Tsai, Tsung-Heng; Hong, Jia-Hua; Wang, Liang-Hung; Lee, Shuenn-Yuh

2012-09-01

This paper presents low-power analog ICs for wireless ECG acquisition systems. Considering the power-efficient communication in the body sensor network, the required low-power analog ICs are developed for a healthcare system through miniaturization and system integration. To acquire the ECG signal, a low-power analog front-end system, including an ECG signal acquisition board, an on-chip low-pass filter, and an on-chip successive-approximation analog-to-digital converter for portable ECG detection devices is presented. A quadrature CMOS voltage-controlled oscillator and a 2.4 GHz direct-conversion transmitter with a power amplifier and upconversion mixer are also developed to transmit the ECG signal through wireless communication. In the receiver, a 2.4 GHz fully integrated CMOS RF front end with a low-noise amplifier, differential power splitter, and quadrature mixer based on current-reused folded architecture is proposed. The circuits have been implemented to meet the specifications of the IEEE 802.15.4 2.4 GHz standard. The low-power ICs of the wireless ECG acquisition systems have been fabricated using a 0.18 μm Taiwan Semiconductor Manufacturing Company (TSMC) CMOS standard process. The measured results on the human body reveal that ECG signals can be acquired effectively by the proposed low-power analog front-end ICs.

Attachment method for stacked integrated circuit (IC) chips

DOEpatents

Bernhardt, A.F.; Malba, V.

1999-08-03

An attachment method for stacked integrated circuit (IC) chips is disclosed. The method involves connecting stacked chips, such as DRAM memory chips, to each other and/or to a circuit board. Pads on the individual chips are rerouted to form pads on the side of the chip, after which the chips are stacked on top of each other whereby desired interconnections to other chips or a circuit board can be accomplished via the side-located pads. The pads on the side of a chip are connected to metal lines on a flexible plastic tape (flex) by anisotropically conductive adhesive (ACA). Metal lines on the flex are likewise connected to other pads on chips and/or to pads on a circuit board. In the case of a stack of DRAM chips, pads to corresponding address lines on the various chips may be connected to the same metal line on the flex to form an address bus. This method has the advantage of reducing the number of connections required to be made to the circuit board due to bussing; the flex can accommodate dimensional variation in the alignment of chips in the stack; bonding of the ACA is accomplished at low temperature and is otherwise simpler and less expensive than solder bonding; chips can be bonded to the ACA all at once if the sides of the chips are substantially coplanar, as in the case for stacks of identical chips, such as DRAM. 12 figs.

The Insula and Taste Learning

PubMed Central

Yiannakas, Adonis; Rosenblum, Kobi

2017-01-01

The sense of taste is a key component of the sensory machinery, enabling the evaluation of both the safety as well as forming associations regarding the nutritional value of ingestible substances. Indicative of the salience of the modality, taste conditioning can be achieved in rodents upon a single pairing of a tastant with a chemical stimulus inducing malaise. This robust associative learning paradigm has been heavily linked with activity within the insular cortex (IC), among other regions, such as the amygdala and medial prefrontal cortex. A number of studies have demonstrated taste memory formation to be dependent on protein synthesis at the IC and to correlate with the induction of signaling cascades involved in synaptic plasticity. Taste learning has been shown to require the differential involvement of dopaminergic GABAergic, glutamatergic, muscarinic neurotransmission across an extended taste learning circuit. The subsequent activation of downstream protein kinases (ERK, CaMKII), transcription factors (CREB, Elk-1) and immediate early genes (c-fos, Arc), has been implicated in the regulation of the different phases of taste learning. This review discusses the relevant neurotransmission, molecular signaling pathways and genetic markers involved in novel and aversive taste learning, with a particular focus on the IC. Imaging and other studies in humans have implicated the IC in the pathophysiology of a number of cognitive disorders. We conclude that the IC participates in circuit-wide computations that modulate the interception and encoding of sensory information, as well as the formation of subjective internal representations that control the expression of motivated behaviors. PMID:29163022

An analog front-end bipolar-transistor integrated circuit for the SDC silicon tracker

NASA Astrophysics Data System (ADS)

Kipnis, I.; Spieler, H.; Collins, T.

1994-08-01

A low-noise, low-power, high-bandwidth, radiation hard, silicon bipolar-transistor full-custom integrated circuit (IC) containing 64 channels of analog signal processing has been developed for the SDC silicon tracker The IC was designed and tested at LBL and was fabricated using AT&T's CBIC-U2, 4 GHz f/sub /spl tau// complementary bipolar technology. Each channel contains the following functions: low-noise preamplification, pulse shaping and threshold discrimination. This is the first iteration of the production analog IC for the SDC silicon tracker. The IC is laid out to directly match the 50 /spl mu/m pitch double-sided silicon strip detector. The chip measures 6.8 mm/spl times/3.1 mm and contains 3,600 transistors. Three stages of amplification provide 180 mV/fC of gain with a 35 nsec peaking time at the comparator input. For a 14 pF detector capacitance, the equivalent noise charge is 1300 el. RMS at a power consumption of 1 mW/channel from a single 3.5 V supply. With the discriminator threshold set to 4 times the noise level, a 16 nsec time-walk for 1.25 to 10 fC signals is achieved using a time-walk compensation network. Irradiation tests at TRIUMF to a /spl Phi/=10/sup 14/ protons/cm/sup 2/ have been performed on the IC, demonstrating the radiation hardness of the complementary bipolar process.

Developing terahertz imaging equation and enhancement of the resolution of terahertz images using deconvolution

NASA Astrophysics Data System (ADS)

Ahi, Kiarash; Anwar, Mehdi

2016-04-01

This paper introduces a novel reconstruction approach for enhancing the resolution of the terahertz (THz) images. For this purpose the THz imaging equation is derived. According to our best knowledge we are reporting the first THz imaging equation by this paper. This imaging equation is universal for THz far-field imaging systems and can be used for analyzing, describing and modeling of these systems. The geometry and behavior of Gaussian beams in far-field region imply that the FWHM of the THz beams diverge as the frequencies of the beams decrease. Thus, the resolution of the measurement decreases in lower frequencies. On the other hand, the depth of penetration of THz beams decreases as frequency increases. Roughly speaking beams in sub 1.5 THz, are transmitted into integrated circuit (IC) packages and the similar packaged objects. Thus, it is not possible to use the THz pulse with higher frequencies in order to achieve higher resolution inspection of packaged items. In this paper, after developing the 3-D THz point spread function (PSF) of the scanning THz beam and then the THz imaging equation, THz images are enhanced through deconvolution of the THz PSF and THz images. As a result, the resolution has been improved several times beyond the physical limitations of the THz measurement setup in the far-field region and sub-Nyquist images have been achieved. Particularly, MSE and SSIḾ have been increased by 27% and 50% respectively. Details as small as 0.2 mm were made visible in the THz images which originally reveals no details smaller than 2.2 mm. In other words the resolution of the images has been increased by 10 times. The accuracy of the reconstructed images was proved by high resolution X-ray images.

NASA Tech Briefs, September 2000. Volume 24, No. 9

NASA Technical Reports Server (NTRS)

2000-01-01

Topics include: Sensors; Test and Measurement; Electronic Components and Circuits; Electronic Systems; Physical Sciences; Materials; Computer Programs; Mechanics; Machinery/Automation; Bio-Medical; semiconductors/ICs; Books and Reports.

Intermetallic compounds in 3D integrated circuits technology: a brief review

NASA Astrophysics Data System (ADS)

Annuar, Syahira; Mahmoodian, Reza; Hamdi, Mohd; Tu, King-Ning

2017-12-01

The high performance and downsizing technology of three-dimensional integrated circuits (3D-ICs) for mobile consumer electronic products have gained much attention in the microelectronics industry. This has been driven by the utilization of chip stacking by through-Si-via and solder microbumps. Pb-free solder microbumps are intended to replace conventional Pb-containing solder joints due to the rising awareness of environmental preservation. The use of low-volume solder microbumps has led to crucial constraints that cause several reliability issues, including excessive intermetallic compounds (IMCs) formation and solder microbump embrittlement due to IMCs growth. This article reviews technologies related to 3D-ICs, IMCs formation mechanisms and reliability issues concerning IMCs with Pb-free solder microbumps. Finally, future outlook on the potential growth of research in this area is discussed.

Intermetallic compounds in 3D integrated circuits technology: a brief review.

PubMed

Annuar, Syahira; Mahmoodian, Reza; Hamdi, Mohd; Tu, King-Ning

2017-01-01

The high performance and downsizing technology of three-dimensional integrated circuits (3D-ICs) for mobile consumer electronic products have gained much attention in the microelectronics industry. This has been driven by the utilization of chip stacking by through-Si-via and solder microbumps. Pb-free solder microbumps are intended to replace conventional Pb-containing solder joints due to the rising awareness of environmental preservation. The use of low-volume solder microbumps has led to crucial constraints that cause several reliability issues, including excessive intermetallic compounds (IMCs) formation and solder microbump embrittlement due to IMCs growth. This article reviews technologies related to 3D-ICs, IMCs formation mechanisms and reliability issues concerning IMCs with Pb-free solder microbumps. Finally, future outlook on the potential growth of research in this area is discussed.

Device-level and module-level three-dimensional integrated circuits created using oblique processing

NASA Astrophysics Data System (ADS)

Burckel, D. Bruce

2016-07-01

This paper demonstrates that another class of three-dimensional integrated circuits (3-D-ICs) exists, distinct from through-silicon-via-centric and monolithic 3-D-ICs. Furthermore, it is possible to create devices that are 3-D "at the device level" (i.e., with active channels oriented in each of the three coordinate axes), by performing standard CMOS fabrication operations at an angle with respect to the wafer surface into high aspect ratio silicon substrates using membrane projection lithography (MPL). MPL requires only minimal fixturing changes to standard CMOS equipment, and no change to current state-of-the-art lithography. Eliminating the constraint of two-dimensional planar device architecture enables a wide range of interconnect topologies which could help reduce interconnect resistance/capacitance, and potentially improve performance.

Non-invasive current and voltage imaging techniques for integrated circuits using scanning probe microscopy. Final report, LDRD Project FY93 and FY94

DOE Office of Scientific and Technical Information (OSTI.GOV)

Campbell, A.N.; Cole, E.I. Jr.; Tangyunyong, Paiboon

This report describes the first practical, non-invasive technique for detecting and imaging currents internal to operating integrated circuits (ICs). This technique is based on magnetic force microscopy and was developed under Sandia National Laboratories` LDRD (Laboratory Directed Research and Development) program during FY 93 and FY 94. LDRD funds were also used to explore a related technique, charge force microscopy, for voltage probing of ICs. This report describes the technical work performed under this LDRD as well as the outcomes of the project in terms of publications and awards, intellectual property and licensing, synergistic work, potential future work, hiring ofmore » additional permanent staff, and benefits to DOE`s defense programs (DP).« less

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tanaka, T.J.; Nowlen, S.P.; Anderson, D.J.

Smoke can adversely affect digital electronics; in the short term, it can lead to circuit bridging and in the long term to corrosion of metal parts. This report is a summary of the work to date and component-level tests by Sandia National Laboratories for the Nuclear Regulatory Commission to determine the impact of smoke on digital instrumentation and control equipment. The component tests focused on short-term effects such as circuit bridging in typical components and the factors that can influence how much the smoke will affect them. These factors include the component technology and packaging, physical board protection, and environmentalmore » conditions such as the amount of smoke, temperature of burn, and humidity level. The likelihood of circuit bridging was tested by measuring leakage currents and converting those currents to resistance in ohms. Hermetically sealed ceramic packages were more resistant to smoke than plastic packages. Coating the boards with an acrylic spray provided some protection against circuit bridging. The smoke generation factors that affect the resistance the most are humidity, fuel level, and burn temperature. The use of CO{sub 2} as a fire suppressant, the presence of galvanic metal, and the presence of PVC did not significantly affect the outcome of these results.« less

Small, Optically-Driven Power Source

NASA Technical Reports Server (NTRS)

Cockrum, Richard H.; Wang, Ke-Li J.

1988-01-01

Power transmitted along fiber-optic cables. Transmitted as infrared light along fiber-optic cable, converted to electricity to supply small electronic circuit. Power source and circuit remains electrically isolated from each other for safety or reduces electromagnetic interference. Array of diodes made by standard integrated-circuit techniques and packaged for mounting at end of fiber-optic cable.

Switched-capacitor realization of presynaptic short-term-plasticity and stop-learning synapses in 28 nm CMOS

PubMed Central

Noack, Marko; Partzsch, Johannes; Mayr, Christian G.; Hänzsche, Stefan; Scholze, Stefan; Höppner, Sebastian; Ellguth, Georg; Schüffny, Rene

2015-01-01

Synaptic dynamics, such as long- and short-term plasticity, play an important role in the complexity and biological realism achievable when running neural networks on a neuromorphic IC. For example, they endow the IC with an ability to adapt and learn from its environment. In order to achieve the millisecond to second time constants required for these synaptic dynamics, analog subthreshold circuits are usually employed. However, due to process variation and leakage problems, it is almost impossible to port these types of circuits to modern sub-100nm technologies. In contrast, we present a neuromorphic system in a 28 nm CMOS process that employs switched capacitor (SC) circuits to implement 128 short term plasticity presynapses as well as 8192 stop-learning synapses. The neuromorphic system consumes an area of 0.36 mm2 and runs at a power consumption of 1.9 mW. The circuit makes use of a technique for minimizing leakage effects allowing for real-time operation with time constants up to several seconds. Since we rely on SC techniques for all calculations, the system is composed of only generic mixed-signal building blocks. These generic building blocks make the system easy to port between technologies and the large digital circuit part inherent in an SC system benefits fully from technology scaling. PMID:25698914

Massively Parallel, Molecular Analysis Platform Developed Using a CMOS Integrated Circuit With Biological Nanopores

PubMed Central

Roever, Stefan

2012-01-01

A massively parallel, low cost molecular analysis platform will dramatically change the nature of protein, molecular and genomics research, DNA sequencing, and ultimately, molecular diagnostics. An integrated circuit (IC) with 264 sensors was fabricated using standard CMOS semiconductor processing technology. Each of these sensors is individually controlled with precision analog circuitry and is capable of single molecule measurements. Under electronic and software control, the IC was used to demonstrate the feasibility of creating and detecting lipid bilayers and biological nanopores using wild type α-hemolysin. The ability to dynamically create bilayers over each of the sensors will greatly accelerate pore development and pore mutation analysis. In addition, the noise performance of the IC was measured to be 30fA(rms). With this noise performance, single base detection of DNA was demonstrated using α-hemolysin. The data shows that a single molecule, electrical detection platform using biological nanopores can be operationalized and can ultimately scale to millions of sensors. Such a massively parallel platform will revolutionize molecular analysis and will completely change the field of molecular diagnostics in the future.

SiC Integrated Circuits for Power Device Drivers Able to Operate in Harsh Environments

NASA Astrophysics Data System (ADS)

Godignon, P.; Alexandru, M.; Banu, V.; Montserrat, J.; Jorda, X.; Vellvehi, M.; Schmidt, B.; Michel, P.; Millan, J.

2014-08-01

The currently developed SiC electronic devices are more robust to high temperature operation and radiation exposure damage than correspondingly rated Si ones. In order to integrate the existent SiC high power and high temperature electronics into more complex systems, a SiC integrated circuit (IC) technology capable of operation at temperatures substantially above the conventional ones is required. Therefore, this paper is a step towards the development of ICs-control electronics that have to attend the harsh environment power applications. Concretely, we present the development of SiC MESFET-based digital circuitry, able to integrate gate driver for SiC power devices. Furthermore, a planar lateral power MESFET is developed with the aim of its co-integration on the same chip with the previously mentioned SiC digital ICs technology. And finally, experimental results on SiC Schottky-gated devices irradiated with protons and electrons are presented. This development is based on the Tungsten-Schottky interface technology used for the fabrication of stable SiC Schottky diodes for the European Space Agency Mission BepiColombo.

Inclusion of Body Bias Effect in SPICE Modeling of 4H-SiC Integrated Circuit Resistors

NASA Technical Reports Server (NTRS)

Neudeck, Philip G.

2017-01-01

The DC electrical behavior of n-type 4H-SiC resistors used for realizing 500 degrees Celsius durable integrated circuits (ICs) is studied as a function of substrate bias and temperature. Improved fidelity electrical simulation is described using SPICE NMOS model to simulate resistor substrate body bias effect that is absent from the SPICE semiconductor resistor model.

Inclusion of Body-Bias Effect in SPICE Modeling of 4H-SiC Integrated Circuit Resistors

NASA Technical Reports Server (NTRS)

Neudeck, Philip G.

2017-01-01

The DC electrical behavior of n-type 4H-SiC resistors used for realizing 500 C durable integrated circuits (ICs) is studied as a function of substrate bias and temperature. Improved fidelity electrical simulation is described using SPICE NMOS model to simulate resistor substrate body bias effect that is absent from the SPICE semiconductor resistor model.

Single Circuit Board Implementation of a Digitally Compensated SAW Oscillator (DCSO).

DTIC Science & Technology

1983-12-01

Through this project a design for a Digitally Compensated SAW Oscillator (DCSO) was developed and implemented on a single circuit board. The AFIT IC, which...is the heart of the design , did not function properly. Therefore, my work was halted after testing several of the subcircuits and assembling the...o.... -7 Standards ........ o..o....... -8 Approach-9 Sequence of Presentation .................. -10 II, Design

JPRS Report: Science & Technology - Europe.

DTIC Science & Technology

1992-12-21

in the aero- nautical industry—through the use of hybrids, ASICs [application-specific integrated circuits ], etc. "The system will also have an... Module ], the cylinder-shaped pressurized cabin that can be firmly attached to the international space station), which is to be launched in 1999...34] [Excerpt] Two hundred scientists and $1 billion to design the chip of the future, an integrated circuit (IC) giving microcomputers power

Fault-tolerant, high-level quantum circuits: form, compilation and description

NASA Astrophysics Data System (ADS)

Paler, Alexandru; Polian, Ilia; Nemoto, Kae; Devitt, Simon J.

2017-06-01

Fault-tolerant quantum error correction is a necessity for any quantum architecture destined to tackle interesting, large-scale problems. Its theoretical formalism has been well founded for nearly two decades. However, we still do not have an appropriate compiler to produce a fault-tolerant, error-corrected description from a higher-level quantum circuit for state-of the-art hardware models. There are many technical hurdles, including dynamic circuit constructions that occur when constructing fault-tolerant circuits with commonly used error correcting codes. We introduce a package that converts high-level quantum circuits consisting of commonly used gates into a form employing all decompositions and ancillary protocols needed for fault-tolerant error correction. We call this form the (I)initialisation, (C)NOT, (M)measurement form (ICM) and consists of an initialisation layer of qubits into one of four distinct states, a massive, deterministic array of CNOT operations and a series of time-ordered X- or Z-basis measurements. The form allows a more flexible approach towards circuit optimisation. At the same time, the package outputs a standard circuit or a canonical geometric description which is a necessity for operating current state-of-the-art hardware architectures using topological quantum codes.

Packaged Capacitive Pressure Sensor System for Aircraft Engine Health Monitoring

NASA Technical Reports Server (NTRS)

Scardelletti, Maximilian C.; Zorman, Christian A.

2016-01-01

This paper describes the development of a packaged silicon carbide (SiC) based MEMS pressure sensor system designed specifically for a conventional turbofan engine. The electronic circuit is based on a Clapp-type oscillator that incorporates a 6H-SiC MESFET, a SiCN MEMS capacitive pressure sensor, titanate MIM capacitors, wirewound inductors, and thick film resistors. The pressure sensor serves as the capacitor in the LC tank circuit, thereby linking pressure to the resonant frequency of the oscillator. The oscillator and DC bias circuitry were fabricated on an alumina substrate and secured inside a metal housing. The packaged sensing system reliably operates at 0 to 350 psi and 25 to 540C. The system has a pressure sensitivity of 6.8 x 10E-2 MHzpsi. The packaged system shows negligible difference in frequency response between 25 and 400C. The fully packaged sensor passed standard benchtop acceptance tests and was evaluated on a flight-worthy engine.

Functional Laser Trimming Of Thin Film Resistors On Silicon ICs

NASA Astrophysics Data System (ADS)

Mueller, Michael J.; Mickanin, Wes

1986-07-01

Modern Laser Wafer Trimming (LWT) technology achieves exceptional analog circuit performance and precision while maintain-ing the advantages of high production throughput and yield. Microprocessor-driven instrumentation has both emphasized the role of data conversion circuits and demanded sophisticated signal conditioning functions. Advanced analog semiconductor circuits with bandwidths over 1 GHz, and high precision, trimmable, thin-film resistors meet many of todays emerging circuit requirements. Critical to meeting these requirements are optimum choices of laser characteristics, proper materials, trimming process control, accurate modeling of trimmed resistor performance, and appropriate circuit design. Once limited exclusively to hand-crafted, custom integrated circuits, designs are now available in semi-custom circuit configurations. These are similar to those provided for digital designs and supported by computer-aided design (CAD) tools. Integrated with fully automated measurement and trimming systems, these quality circuits can now be produced in quantity to meet the requirements of communications, instrumentation, and signal processing markets.

General technique for the integration of MIC/MMIC'S with waveguides

NASA Technical Reports Server (NTRS)

Geller, Bernard D. (Inventor); Zaghloul, Amir I. (Inventor)

1987-01-01

A technique for packaging and integrating of a microwave integrated circuit (MIC) or monolithic microwave integrated circuit (MMIC) with a waveguide uses a printed conductive circuit pattern on a dielectric substrate to transform impedance and mode of propagation between the MIC/MMIC and the waveguide. The virtually coplanar circuit pattern lies on an equipotential surface within the waveguide and therefore makes possible single or dual polarized mode structures.

Physically separating printed circuit boards with a resilient, conductive contact

NASA Technical Reports Server (NTRS)

Baker, John D. (Inventor); Montalvo, Alberto (Inventor)

1999-01-01

A multi-board module provides high density electronic packaging in which multiple printed circuit boards are stacked. Electrical power, or signals, are conducted between the boards through a resilient contact. One end of the contact is located at a via in the lower circuit board and soldered to a pad near the via. The top surface of the contact rests against a via of the facing printed circuit board.

21 CFR 814.39 - PMA supplements.

Code of Federal Regulations, 2014 CFR

2014-04-01

... sterilization procedures. (5) Changes in packaging. (6) Changes in the performance or design specifications, circuits, components, ingredients, principle of operation, or physical layout of the device. (7) Extension... the performance or design specifications, circuits, components, ingredients, principles of operation...

Self-Adaptive System based on Field Programmable Gate Array for Extreme Temperature Electronics

NASA Technical Reports Server (NTRS)

Keymeulen, Didier; Zebulum, Ricardo; Rajeshuni, Ramesham; Stoica, Adrian; Katkoori, Srinivas; Graves, Sharon; Novak, Frank; Antill, Charles

2006-01-01

In this work, we report the implementation of a self-adaptive system using a field programmable gate array (FPGA) and data converters. The self-adaptive system can autonomously recover the lost functionality of a reconfigurable analog array (RAA) integrated circuit (IC) [3]. Both the RAA IC and the self-adaptive system are operating in extreme temperatures (from 120 C down to -180 C). The RAA IC consists of reconfigurable analog blocks interconnected by several switches and programmable by bias voltages. It implements filters/amplifiers with bandwidth up to 20 MHz. The self-adaptive system controls the RAA IC and is realized on Commercial-Off-The-Shelf (COTS) parts. It implements a basic compensation algorithm that corrects a RAA IC in less than a few milliseconds. Experimental results for the cold temperature environment (down to -180 C) demonstrate the feasibility of this approach.

Low power, compact charge coupled device signal processing system

NASA Technical Reports Server (NTRS)

Bosshart, P. W.; Buss, D. D.; Eversole, W. L.; Hewes, C. R.; Mayer, D. J.

1980-01-01

A variety of charged coupled devices (CCDs) for performing programmable correlation for preprocessing environmental sensor data preparatory to its transmission to the ground were developed. A total of two separate ICs were developed and a third was evaluated. The first IC was a CCD chirp z transform IC capable of performing a 32 point DFT at frequencies to 1 MHz. All on chip circuitry operated as designed with the exception of the limited dynamic range caused by a fixed pattern noise due to interactions between the digital and analog circuits. The second IC developed was a 64 stage CCD analog/analog correlator for performing time domain correlation. Multiplier errors were found to be less than 1 percent at designed signal levels and less than 0.3 percent at the measured smaller levels. A prototype IC for performing time domain correlation was also evaluated.

QDENSITY—A Mathematica quantum computer simulation

NASA Astrophysics Data System (ADS)

Juliá-Díaz, Bruno; Burdis, Joseph M.; Tabakin, Frank

2009-03-01

This Mathematica 6.0 package is a simulation of a Quantum Computer. The program provides a modular, instructive approach for generating the basic elements that make up a quantum circuit. The main emphasis is on using the density matrix, although an approach using state vectors is also implemented in the package. The package commands are defined in Qdensity.m which contains the tools needed in quantum circuits, e.g., multiqubit kets, projectors, gates, etc. New version program summaryProgram title: QDENSITY 2.0 Catalogue identifier: ADXH_v2_0 Program summary URL:http://cpc.cs.qub.ac.uk/summaries/ADXH_v2_0.html Program obtainable from: CPC Program Library, Queen's University, Belfast, N. Ireland Licensing provisions: Standard CPC licence, http://cpc.cs.qub.ac.uk/licence/licence.html No. of lines in distributed program, including test data, etc.: 26 055 No. of bytes in distributed program, including test data, etc.: 227 540 Distribution format: tar.gz Programming language: Mathematica 6.0 Operating system: Any which supports Mathematica; tested under Microsoft Windows XP, Macintosh OS X, and Linux FC4 Catalogue identifier of previous version: ADXH_v1_0 Journal reference of previous version: Comput. Phys. Comm. 174 (2006) 914 Classification: 4.15 Does the new version supersede the previous version?: Offers an alternative, more up to date, implementation Nature of problem: Analysis and design of quantum circuits, quantum algorithms and quantum clusters. Solution method: A Mathematica package is provided which contains commands to create and analyze quantum circuits. Several Mathematica notebooks containing relevant examples: Teleportation, Shor's Algorithm and Grover's search are explained in detail. A tutorial, Tutorial.nb is also enclosed. Reasons for new version: The package has been updated to make it fully compatible with Mathematica 6.0 Summary of revisions: The package has been updated to make it fully compatible with Mathematica 6.0 Running time: Most examples included in the package, e.g., the tutorial, Shor's examples, Teleportation examples and Grover's search, run in less than a minute on a Pentium 4 processor (2.6 GHz). The running time for a quantum computation depends crucially on the number of qubits employed.

Integrated microsystems packaging approach with LCP

NASA Astrophysics Data System (ADS)

Jaynes, Paul; Shacklette, Lawrence W.

2006-05-01

Within the government communication market there is an increasing push to further miniaturize systems with the use of chip-scale packages, flip-chip bonding, and other advances over traditional packaging techniques. Harris' approach to miniaturization includes these traditional packaging advances, but goes beyond this level of miniaturization by combining the functional and structural elements of a system, thus creating a Multi-Functional Structural Circuit (MFSC). An emerging high-frequency, near hermetic, thermoplastic electronic substrate material, Liquid Crystal Polymer (LCP), is the material that will enable the combination of the electronic circuit and the physical structure of the system. The first embodiment of this vision for Harris is the development of a battlefield acoustic sensor module. This paper will introduce LCP and its advantages for MFSC, present an example of the work that Harris has performed, and speak to LCP MFSCs' potential benefits to miniature communications modules and sensor platforms.

Elements configuration of the open lead test circuit

DOE Office of Scientific and Technical Information (OSTI.GOV)

Fukuzaki, Yumi, E-mail: 14514@sr.kagawa-nct.ac.jp; Ono, Akira

In the field of electronics, small electronic devices are widely utilized because they are easy to carry. The devices have various functions by user’s request. Therefore, the lead’s pitch or the ball’s pitch have been narrowed and high-density printed circuit board has been used in the devices. Use of the ICs which have narrow lead pitch makes normal connection difficult. When logic circuits in the devices are fabricated with the state-of-the-art technology, some faults have occurred more frequently. It can be divided into types of open faults and short faults. We have proposed a new test method using a testmore » circuit in the past. This paper propose elements configuration of the test circuit.« less

Computer-Aided Design Package for Designers of Digital Optical Computers

DTIC Science & Technology

1991-02-01

circuit depth and in circuit breadth. It appears, from initial studies by PhD students Gupta and Majidi using the newly modified tools, that a few irregular...Gupta, which is based on an earlier tool developed by Majidi . The tool allows logic gates to have fan-ins and fan-outs that vary, and allows circuits

Microstructure Evolution and Protrusion of Electroplated Cu-Filled Through-Silicon Vias Subjected to Thermal Cyclic Loading

NASA Astrophysics Data System (ADS)

Chen, Si; An, Tong; Qin, Fei; Chen, Pei

2017-10-01

Through-silicon vias (TSVs) have become an important technology for three-dimensional integrated circuit (3D IC) packaging. Protrusion of electroplated Cu-filled vias is a critical reliability issue for TSV technology. In this work, thermal cycling tests were carried out to identify how the microstructure affects protrusion during thermal cycling. Cu protrusion occurs when the loading temperature is higher than 149°C. During the first five thermal cycles, the grain size of Cu plays a dominant role in the protrusion behavior. Larger Cu grain size before thermal cycling results in greater Cu protrusion. With increasing thermal cycle number, the effect of the Cu grain size reduces and the microstrain begins to dominate the Cu protrusion behavior. Higher magnitude of microstrain within Cu results in greater protrusion increment during subsequent thermal cycles. When the thermal cycle number reaches 25, the protrusion rate of Cu slows down due to strain hardening. After 30 thermal cycles, the Cu protrusion stabilizes within the range of 1.92 μm to 2.09 μm.

An application specific integrated circuit based multi-anode microchannel array readout system

NASA Technical Reports Server (NTRS)

Smeins, Larry G.; Stechman, John M.; Cole, Edward H.

1991-01-01

Size reduction of two new multi-anode microchannel array (MAMA) readout systems is described. The systems are based on two analog and one digital application specific integrated circuits (ASICs). The new readout systems reduce volume over previous discrete designs by 80 percent while improving electrical performance on virtually every significant parameter. Emphasis is made on the packaging used to achieve the volume reduction. Surface mount technology (SMT) is combined with modular construction for the analog portion of the readout. SMT reliability concerns and the board area impact of MIL SPEC SMT components is addressed. Package selection for the analog ASIC is discussed. Future sytems will require even denser packaging and the volume reduction progression is shown.

Simulation of materials processing: Fantasy or reality?

NASA Technical Reports Server (NTRS)

Jenkins, Thomas J.; Bright, Victor M.

1994-01-01

This experiment introduces students to the application of computer-aided design (CAD) and analysis of materials processing in the context of integrated circuit (IC) fabrication. The fabrication of modern IC's is a complex process which consists of several sequential steps. These steps involve the precise control of processing variables such as temperature, humidity, and ambient gas composition. In essence, the particular process employed during the fabrication becomes a 'recipe'. Due to economic and other considerations, CAD is becoming an indispensable part of the development of new recipes for IC fabrication. In particular, this experiment permits the students to explore the CAD of the thermal oxidation of silicon.

Packaging Technologies for 500 C SiC Electronics and Sensors: Challenges in Material Science and Technology

NASA Technical Reports Server (NTRS)

Chen, Liang-Yu; Neudeck, Philip G.; Behelm, Glenn M.; Spry, David J.; Meredith, Roger D.; Hunter, Gary W.

2015-01-01

This paper presents ceramic substrates and thick-film metallization based packaging technologies in development for 500C silicon carbide (SiC) electronics and sensors. Prototype high temperature ceramic chip-level packages and printed circuit boards (PCBs) based on ceramic substrates of aluminum oxide (Al2O3) and aluminum nitride (AlN) have been designed and fabricated. These ceramic substrate-based chip-level packages with gold (Au) thick-film metallization have been electrically characterized at temperatures up to 550C. The 96 alumina packaging system composed of chip-level packages and PCBs has been successfully tested with high temperature SiC discrete transistor devices at 500C for over 10,000 hours. In addition to tests in a laboratory environment, a SiC junction field-effect-transistor (JFET) with a packaging system composed of a 96 alumina chip-level package and an alumina printed circuit board was tested on low earth orbit for eighteen months via a NASA International Space Station experiment. In addition to packaging systems for electronics, a spark-plug type sensor package based on this high temperature interconnection system for high temperature SiC capacitive pressure sensors was also developed and tested. In order to further significantly improve the performance of packaging system for higher packaging density, higher operation frequency, power rating, and even higher temperatures, some fundamental material challenges must be addressed. This presentation will discuss previous development and some of the challenges in material science (technology) to improve high temperature dielectrics for packaging applications.

Hearing-aid tester

NASA Technical Reports Server (NTRS)

Kessinger, R.; Polhemus, J. T.; Waring, J. G.

1977-01-01

Hearing aids are automatically checked by circuit that applies half-second test signal every thirty minutes. If hearing-aid output is distorted, too small, or if battery is too low, a warning lamp is activated. Test circuit is incorporated directly into hearing-aid package.

Ambient temperature cadmium zinc telluride radiation detector and amplifier circuit

DOEpatents

McQuaid, J.H.; Lavietes, A.D.

1998-05-26

A low noise, low power consumption, compact, ambient temperature signal amplifier for a Cadmium Zinc Telluride (CZT) radiation detector is disclosed. The amplifier can be used within a larger system (e.g., including a multi-channel analyzer) to allow isotopic analysis of radionuclides in the field. In one embodiment, the circuit stages of the low power, low noise amplifier are constructed using integrated circuit (IC) amplifiers , rather than discrete components, and include a very low noise, high gain, high bandwidth dual part preamplification stage, an amplification stage, and an filter stage. The low noise, low power consumption, compact, ambient temperature amplifier enables the CZT detector to achieve both the efficiency required to determine the presence of radionuclides and the resolution necessary to perform isotopic analysis to perform nuclear material identification. The present low noise, low power, compact, ambient temperature amplifier enables a CZT detector to achieve resolution of less than 3% full width at half maximum at 122 keV for a Cobalt-57 isotope source. By using IC circuits and using only a single 12 volt supply and ground, the novel amplifier provides significant power savings and is well suited for prolonged portable in-field use and does not require heavy, bulky power supply components. 9 figs.

Proceedings of the International Electronic Circuit Packaging Symposium (3rd) on Advances in Electronic Circuit Packaging Held at Boulder, Colorado on 15-17 August 1962. Volume 3,

DTIC Science & Technology

1963-01-01

the connector pin, which was then sol - dered at various levels of wire build up. It is proposed, with a slight modification of the connector terminal...sacrificial anode for galvanic protection of other metals. Aluminum Aluminum and its alloys show promise for applications in long-life oceano - graphic...section of a dumet weld lead. Calculations and actual heat measurements on the effects of welding and sol - dering within 0.060 in. of the component

Advanced Packaging for VLSI/VHSIC (Very Large Scale Integrated Circuits/Very High Speed Integrated Circuits) Applications: Electrical, Thermal, and Mechanical Considerations - An IR&D Report.

DTIC Science & Technology

1987-11-01

developed that can be used by circuit engineers to extract the maximum performance from the devices on various board technologies including multilayer ceramic...Design guidelines have been developed that can be used by circuit engineers to extract the maxi- mum performance from the devices on various board...25 Attenuation and Dispersion Effects ......................................... 27 Skin Effect

Silicon photonics integrated circuits: a manufacturing platform for high density, low power optical I/O's.

PubMed

Absil, Philippe P; Verheyen, Peter; De Heyn, Peter; Pantouvaki, Marianna; Lepage, Guy; De Coster, Jeroen; Van Campenhout, Joris

2015-04-06

Silicon photonics integrated circuits are considered to enable future computing systems with optical input-outputs co-packaged with CMOS chips to circumvent the limitations of electrical interfaces. In this paper we present the recent progress made to enable dense multiplexing by exploiting the integration advantage of silicon photonics integrated circuits. We also discuss the manufacturability of such circuits, a key factor for a wide adoption of this technology.

Substrate noise coupling: a pain for mixed-signal systems (Keynote Address)

NASA Astrophysics Data System (ADS)

Wambacq, Piet; Van der Plas, Geert; Donnay, Stephane; Badaroglu, Mustafa; Soens, Charlotte

2005-06-01

Crosstalk from digital to analog in mixed-signal ICs is recognized as one of the major roadblocks for systems-on-chip (SoC) in future CMOS technologies. This crosstalk mainly happens via the semiconducting silicon substrate, which is usually treated as a ground node by analog and RF designers. The substrate noise coupling problem leads more and more to malfunctioning or extra design iterations. One of the reasons is that the phenomenon of substrate noise coupling is difficult to model and hence difficult to understand. It can be caused by the switching of thousands or millions of gates and depends on layout details. From the generation side (the digital domain), coping with the large amount of noise generators can be solved by macromodeling. On the other hand, the impact of substrate noise on the analog circuits requires careful modeling at the level of transistors and parasitics of layout, power supply, package, PCB, Comparison to measurements of macromodeling at the digital side and careful modeling at the analog side, shows that both the generation and the impact of substrate noise can be predicted with an accuracy of a few dB. In addition, this combination of macromodeling at the digital side and careful modeling at the analog side leads to an understanding of the problem, which can be used for digital low-noise design techniques to minimize the generation of noise, and substrate noise immune design of analog/RF circuits.

Technology CAD for integrated circuit fabrication technology development and technology transfer

NASA Astrophysics Data System (ADS)

Saha, Samar

2003-07-01

In this paper systematic simulation-based methodologies for integrated circuit (IC) manufacturing technology development and technology transfer are presented. In technology development, technology computer-aided design (TCAD) tools are used to optimize the device and process parameters to develop a new generation of IC manufacturing technology by reverse engineering from the target product specifications. While in technology transfer to manufacturing co-location, TCAD is used for process centering with respect to high-volume manufacturing equipment of the target manufacturing equipment of the target manufacturing facility. A quantitative model is developed to demonstrate the potential benefits of the simulation-based methodology in reducing the cycle time and cost of typical technology development and technology transfer projects over the traditional practices. The strategy for predictive simulation to improve the effectiveness of a TCAD-based project, is also discussed.

Continuous adjustment of threshold voltage in carbon nanotube field-effect transistors through gate engineering

NASA Astrophysics Data System (ADS)

Zhong, Donglai; Zhao, Chenyi; Liu, Lijun; Zhang, Zhiyong; Peng, Lian-Mao

2018-04-01

In this letter, we report a gate engineering method to adjust threshold voltage of carbon nanotube (CNT) based field-effect transistors (FETs) continuously in a wide range, which makes the application of CNT FETs especially in digital integrated circuits (ICs) easier. Top-gated FETs are fabricated using solution-processed CNT network films with stacking Pd and Sc films as gate electrodes. By decreasing the thickness of the lower layer metal (Pd) from 20 nm to zero, the effective work function of the gate decreases, thus tuning the threshold voltage (Vt) of CNT FETs from -1.0 V to 0.2 V. The continuous adjustment of threshold voltage through gate engineering lays a solid foundation for multi-threshold technology in CNT based ICs, which then can simultaneously provide high performance and low power circuit modules on one chip.

Intermetallic compounds in 3D integrated circuits technology: a brief review

PubMed Central

Annuar, Syahira; Mahmoodian, Reza; Hamdi, Mohd; Tu, King-Ning

2017-01-01

Abstract The high performance and downsizing technology of three-dimensional integrated circuits (3D-ICs) for mobile consumer electronic products have gained much attention in the microelectronics industry. This has been driven by the utilization of chip stacking by through-Si-via and solder microbumps. Pb-free solder microbumps are intended to replace conventional Pb-containing solder joints due to the rising awareness of environmental preservation. The use of low-volume solder microbumps has led to crucial constraints that cause several reliability issues, including excessive intermetallic compounds (IMCs) formation and solder microbump embrittlement due to IMCs growth. This article reviews technologies related to 3D-ICs, IMCs formation mechanisms and reliability issues concerning IMCs with Pb-free solder microbumps. Finally, future outlook on the potential growth of research in this area is discussed. PMID:29057024

3D Printing of Ball Grid Arrays

NASA Astrophysics Data System (ADS)

Sinha, Shayandev; Hines, Daniel; Dasgupta, Abhijit; Das, Siddhartha

Ball grid arrays (BGA) are interconnects between an integrated circuit (IC) and a printed circuit board (PCB), that are used for surface mounting electronic components. Typically, lead free alloys are used to make solder balls which, after a reflow process, establish a mechanical and electrical connection between the IC and the PCB. High temperature processing is required for most of these alloys leading to thermal shock causing damage to ICs. For producing flexible circuits on a polymer substrate, there is a requirement for low temperature processing capabilities (around 150 C) and for reducing strain from mechanical stresses. Additive manufacturing techniques can provide an alternative methodology for fabricating BGAs as a direct replacement for standard solder bumped BGAs. We have developed aerosol jet (AJ) printing methods to fabricate a polymer bumped BGA. As a demonstration of the process developed, a daisy chain test chip was polymer bumped using an AJ printed ultra violet (UV) curable polymer ink that was then coated with an AJ printed silver nanoparticle laden ink as a conducting layer printed over the polymer bump. The structure for the balls were achieved by printing the polymer ink using a specific toolpath coupled with in-situ UV curing of the polymer which provided good control over the shape, resulting in well-formed spherical bumps on the order of 200 um wide by 200 um tall for this initial demonstration. A detailed discussion of the AJ printing method and results from accelerated life-time testing will be presented

Good Trellises for IC Implementation of Viterbi Decoders for Linear Block Codes

NASA Technical Reports Server (NTRS)

Moorthy, Hari T.; Lin, Shu; Uehara, Gregory T.

1997-01-01

This paper investigates trellis structures of linear block codes for the integrated circuit (IC) implementation of Viterbi decoders capable of achieving high decoding speed while satisfying a constraint on the structural complexity of the trellis in terms of the maximum number of states at any particular depth. Only uniform sectionalizations of the code trellis diagram are considered. An upper-bound on the number of parallel and structurally identical (or isomorphic) subtrellises in a proper trellis for a code without exceeding the maximum state complexity of the minimal trellis of the code is first derived. Parallel structures of trellises with various section lengths for binary BCH and Reed-Muller (RM) codes of lengths 32 and 64 are analyzed. Next, the complexity of IC implementation of a Viterbi decoder based on an L-section trellis diagram for a code is investigated. A structural property of a Viterbi decoder called add-compare-select (ACS)-connectivity which is related to state connectivity is introduced. This parameter affects the complexity of wire-routing (interconnections within the IC). The effect of five parameters namely: (1) effective computational complexity; (2) complexity of the ACS-circuit; (3) traceback complexity; (4) ACS-connectivity; and (5) branch complexity of a trellis diagram on the very large scale integration (VISI) complexity of a Viterbi decoder is investigated. It is shown that an IC implementation of a Viterbi decoder based on a nonminimal trellis requires less area and is capable of operation at higher speed than one based on the minimal trellis when the commonly used ACS-array architecture is considered.

Good trellises for IC implementation of viterbi decoders for linear block codes

NASA Technical Reports Server (NTRS)

Lin, Shu; Moorthy, Hari T.; Uehara, Gregory T.

1996-01-01

This paper investigates trellis structures of linear block codes for the IC (integrated circuit) implementation of Viterbi decoders capable of achieving high decoding speed while satisfying a constraint on the structural complexity of the trellis in terms of the maximum number of states at any particular depth. Only uniform sectionalizations of the code trellis diagram are considered. An upper bound on the number of parallel and structurally identical (or isomorphic) subtrellises in a proper trellis for a code without exceeding the maximum state complexity of the minimal trellis of the code is first derived. Parallel structures of trellises with various section lengths for binary BCH and Reed-Muller (RM) codes of lengths 32 and 64 are analyzed. Next, the complexity of IC implementation of a Viterbi decoder based on an L-section trellis diagram for a code is investigated. A structural property of a Viterbi decoder called ACS-connectivity which is related to state connectivity is introduced. This parameter affects the complexity of wire-routing (interconnections within the IC). The effect of five parameters namely: (1) effective computational complexity; (2) complexity of the ACS-circuit; (3) traceback complexity; (4) ACS-connectivity; and (5) branch complexity of a trellis diagram on the VLSI complexity of a Viterbi decoder is investigated. It is shown that an IC implementation of a Viterbi decoder based on a non-minimal trellis requires less area and is capable of operation at higher speed than one based on the minimal trellis when the commonly used ACS-array architecture is considered.

Programmable logic devices

NASA Astrophysics Data System (ADS)

Jacobs, J. L.

1993-04-01

Erasable programmable logic devices (EPLD's) were investigated to determine their advantages and/or disadvantages in Test Equipment Engineering applications. It was found that EPLD's performed as well as or better than identical circuits using standard transistor transistor logic (TTL). The chip count in these circuits was reduced, saving printed circuit board space and shortening fabrication and prove-in time. Troubleshooting circuits of EPLD's was also easier with 10 to 100 times fewer wires needed. The reduced number of integrated circuits (IC's) contributed to faster system speeds and an overall lower power consumption. In some cases changes to the circuit became software changes using EPLD's instead of hardware changes for standard logic. Using EPLD's was fairly easy; however, as with any new technology, a learning curve must be overcome before EPLD's can be used efficiently. The many benefits of EPLD's outweighed this initial inconvenience.

Novel Low Loss Wide-Band Multi-Port Integrated Circuit Technology for RF/Microwave Applications

NASA Technical Reports Server (NTRS)

Simons, Rainee N.; Goverdhanam, Kavita; Katehi, Linda P. B.; Burke, Thomas P. (Technical Monitor)

2001-01-01

In this paper, novel low loss, wide-band coplanar stripline technology for radio frequency (RF)/microwave integrated circuits is demonstrated on high resistivity silicon wafer. In particular, the fabrication process for the deposition of spin-on-glass (SOG) as a dielectric layer, the etching of microvias for the vertical interconnects, the design methodology for the multiport circuits and their measured/simulated characteristics are graphically illustrated. The study shows that circuits with very low loss, large bandwidth, and compact size are feasible using this technology. This multilayer planar technology has potential to significantly enhance RF/microwave IC performance when combined with semi-conductor devices and microelectromechanical systems (MEMS).

Radiation-Hardened Electronics for Advanced Communications Systems

NASA Technical Reports Server (NTRS)

Whitaker, Sterling

2015-01-01

Novel approach enables high-speed special-purpose processors Advanced reconfigurable and reprogrammable communication systems will require sub-130-nanometer electronics. Legacy single event upset (SEU) radiation-tolerant circuits are ineffective at speeds greater than 125 megahertz. In Phase I of this project, ICs, LLC, demonstrated new base-level logic circuits that provide SEU immunity for sub-130-nanometer high-speed circuits. In Phase II, the company developed an innovative self-restoring logic (SRL) circuit and a system approach that provides high-speed, SEU-tolerant solutions that are effective for sub-130-nanometer electronics scalable to at least 22-nanometer processes. The SRL system can be used in the design of NASA's next-generation special-purpose processors, especially reconfigurable communication processors.

Hybrid measurement chains for the SAS-C spacecraft. [advantages over analog signal processing circuits

NASA Technical Reports Server (NTRS)

Goeke, R. F.

1975-01-01

Spacecraft electronic systems usually demand tight packaging. It was this consideration which initially forced us to consider hybrid circuits for the analog signal processing circuits in the Small Astronomy Satellite-C (SAS-C) scientific payload. We gradually discovered that increased reliability, low power consumption, and reduced program costs all followed. This paper will attempt to share our laboratory's first experience with hybrid circuits and indicate those areas which we found to be important.

Computer aided design of monolithic microwave and millimeter wave integrated circuits and subsystems

NASA Astrophysics Data System (ADS)

Ku, Walter H.

1989-05-01

The objectives of this research are to develop analytical and computer aided design techniques for monolithic microwave and millimeter wave integrated circuits (MMIC and MIMIC) and subsystems and to design and fabricate those ICs. Emphasis was placed on heterojunction-based devices, especially the High Electron Mobility Transition (HEMT), for both low noise and medium power microwave and millimeter wave applications. Circuits to be considered include monolithic low noise amplifiers, power amplifiers, and distributed and feedback amplifiers. Interactive computer aided design programs were developed, which include large signal models of InP MISFETs and InGaAs HEMTs. Further, a new unconstrained optimization algorithm POSM was developed and implemented in the general Analysis and Design program for Integrated Circuit (ADIC) for assistance in the design of largesignal nonlinear circuits.

GaAs digital dynamic IC's for applications up to 10 GHz

NASA Astrophysics Data System (ADS)

Rocchi, M.; Gabillard, B.

1983-06-01

To evaluate the potentiality of GaAs MESFET's as transmitting gates, dynamic TT-bar flip-flops have been fabricated using a self-aligned planar process. The maximum operating frequency is 10.2 GHz, which is the best speed performance ever reported for a digital circuit. The performance of the transmitting gates within the circuits are discussed in detail. Speed improvement and topological simplification of fully static LSI subsystems are investigated.

Defense Industrial Base Assessment: U.S. Integrated Circuit Design and Fabrication Capability

DTIC Science & Technology

2009-05-01

in the U.S for the period 2003-2006, with projections to 2011.6 The resulting draft OTE survey was field tested for accuracy and usability with a...custom application specific integrated circuits (ASICs) to field programmable gate arrays (FPGAs). Companies of all sizes can manufacture these IC...able to design one-time Electronically Programmable Gate Arrays (EPGAs) while nine are able to design Field Programmable Gate Arrays (FPGAs). Eight

Intelligent structures technology

NASA Astrophysics Data System (ADS)

Crawley, Edward F.

1991-07-01

Viewgraphs on intelligent structures technology are presented. Topics covered include: embedding electronics; electrical and mechanical compatibility; integrated circuit chip packaged for embedding; embedding devices within composite structures; test of embedded circuit in G/E coupon; temperature/humidity/bias test; single-chip microcomputer control experiment; and structural shape determination.

Intelligent structures technology

NASA Technical Reports Server (NTRS)

Crawley, Edward F.

1991-01-01

Viewgraphs on intelligent structures technology are presented. Topics covered include: embedding electronics; electrical and mechanical compatibility; integrated circuit chip packaged for embedding; embedding devices within composite structures; test of embedded circuit in G/E coupon; temperature/humidity/bias test; single-chip microcomputer control experiment; and structural shape determination.

Cooling system for electronic components

DOEpatents

Anderl, William James; Colgan, Evan George; Gerken, James Dorance; Marroquin, Christopher Michael; Tian, Shurong

2015-12-15

Embodiments of the present invention provide for non interruptive fluid cooling of an electronic enclosure. One or more electronic component packages may be removable from a circuit card having a fluid flow system. When installed, the electronic component packages are coincident to and in a thermal relationship with the fluid flow system. If a particular electronic component package becomes non-functional, it may be removed from the electronic enclosure without affecting either the fluid flow system or other neighboring electronic component packages.

Cooling system for electronic components

DOEpatents

Anderl, William James; Colgan, Evan George; Gerken, James Dorance; Marroquin, Christopher Michael; Tian, Shurong

2016-05-17

Embodiments of the present invention provide for non interruptive fluid cooling of an electronic enclosure. One or more electronic component packages may be removable from a circuit card having a fluid flow system. When installed, the electronic component packages are coincident to and in a thermal relationship with the fluid flow system. If a particular electronic component package becomes non-functional, it may be removed from the electronic enclosure without affecting either the fluid flow system or other neighboring electronic component packages.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Britton, C.L.; Jagadish, U.; Bryan, W.L.

An Integrated Circuit (IC) readout chip with four channels arranged so as to receive input charge from the corners of the chip was designed for use with 5- to 7-mm pixel detectors. This Application Specific IC (ASIC) can be used for cold neutron imaging, for study of structural order in materials using cold neutron scattering or for particle physics experiments. The ASIC is fabricated in a 0.5-{micro}m n-well AMI process. The design of the ASIC and the test measurements made is reported. Noise measurements are also reported.

Broadband millimeter-wave GaAs transmitters and receivers using planar bow-tie antennas

NASA Technical Reports Server (NTRS)

Konishi, Y.; Kamegawa, M.; Case, M.; Yu, R.; Rodwell, M. J. W.; York, R. A.; Rutledge, D. B.

1992-01-01

We report broadband monolithic transmitters and receivers IC's for mm-wave electromagnetic measurements. The IC's use nonlinear transmission lines (NLTL) and sampling circuits as picosecond pulse generators and detectors. The pulses are radiated and received by planar monolithic bow-tie antennas, collimated with silicon substrate lenses and off-axis parabolic reflectors. Through Fourier transformation of the received pulse, 30-250 GHz free space gain-frequency measurements are demonstrated with an accuracy approximately = 0.17 dB, RMS.

Novel Manufacturing Technologies for GHZ/THz Integrated Circuits on Synthetic Diamond Substrates

DTIC Science & Technology

2010-11-15

silicon form palladium silicide Pd2Si at a temperature of 400 ºС, thus ensuring high reliability of the contacts. All the above metallization layers were...indicate possibility of realization of ICs on diamond substrates. In the course of our studies it was found that the Ti-Pd-Au metallization system...thickness of 2-3 um) can be applied when forming the topology of IC elements on synthetic diamond layers, while the Cr–Cu–Ni–Au metallization system with

Silicon photonic IC embedded optical-PCB for high-speed interconnect application

NASA Astrophysics Data System (ADS)

Kallega, Rakshitha; Nambiar, Siddharth; Kumar, Abhai; Ranganath, Praveen; Selvaraja, Shankar Kumar

2018-02-01

Optical-Printed Circuit Board (PCB) is an emerging optical interconnect technology to bridge the gap between the board edge and the processing module. The technology so far has been used as a broadband transmitter using polymer waveguides in the PCB. In this paper, we report a Silicon Nitride based photonic IC embedded in the PCB along with the polymers as waveguides in the PCB. The motivation for such integration is to bring routing capability and to reduce the power loss due to broadcasting mode.

The Impact of 3D Stacking and Technology Scaling on the Power and Area of Stereo Matching Processors.

PubMed

Ok, Seung-Ho; Lee, Yong-Hwan; Shim, Jae Hoon; Lim, Sung Kyu; Moon, Byungin

2017-02-22

Recently, stereo matching processors have been adopted in real-time embedded systems such as intelligent robots and autonomous vehicles, which require minimal hardware resources and low power consumption. Meanwhile, thanks to the through-silicon via (TSV), three-dimensional (3D) stacking technology has emerged as a practical solution to achieving the desired requirements of a high-performance circuit. In this paper, we present the benefits of 3D stacking and process technology scaling on stereo matching processors. We implemented 2-tier 3D-stacked stereo matching processors with GlobalFoundries 130-nm and Nangate 45-nm process design kits and compare them with their two-dimensional (2D) counterparts to identify comprehensive design benefits. In addition, we examine the findings from various analyses to identify the power benefits of 3D-stacked integrated circuit (IC) and device technology advancements. From experiments, we observe that the proposed 3D-stacked ICs, compared to their 2D IC counterparts, obtain 43% area, 13% power, and 14% wire length reductions. In addition, we present a logic partitioning method suitable for a pipeline-based hardware architecture that minimizes the use of TSVs.

The Impact of 3D Stacking and Technology Scaling on the Power and Area of Stereo Matching Processors

PubMed Central

Ok, Seung-Ho; Lee, Yong-Hwan; Shim, Jae Hoon; Lim, Sung Kyu; Moon, Byungin

2017-01-01

Recently, stereo matching processors have been adopted in real-time embedded systems such as intelligent robots and autonomous vehicles, which require minimal hardware resources and low power consumption. Meanwhile, thanks to the through-silicon via (TSV), three-dimensional (3D) stacking technology has emerged as a practical solution to achieving the desired requirements of a high-performance circuit. In this paper, we present the benefits of 3D stacking and process technology scaling on stereo matching processors. We implemented 2-tier 3D-stacked stereo matching processors with GlobalFoundries 130-nm and Nangate 45-nm process design kits and compare them with their two-dimensional (2D) counterparts to identify comprehensive design benefits. In addition, we examine the findings from various analyses to identify the power benefits of 3D-stacked integrated circuit (IC) and device technology advancements. From experiments, we observe that the proposed 3D-stacked ICs, compared to their 2D IC counterparts, obtain 43% area, 13% power, and 14% wire length reductions. In addition, we present a logic partitioning method suitable for a pipeline-based hardware architecture that minimizes the use of TSVs. PMID:28241437

GaAs integrated circuits and heterojunction devices

NASA Astrophysics Data System (ADS)

Fowlis, Colin

1986-06-01

The state of the art of GaAs technology in the U.S. as it applies to digital and analog integrated circuits is examined. In a market projection, it is noted that whereas analog ICs now largely dominate the market, in 1994 they will amount to only 39 percent vs. 57 percent for digital ICs. The military segment of the market will remain the largest (42 percent in 1994 vs. 70 percent today). ICs using depletion-mode-only FETs can be constructed in various forms, the closest to production being BFL or buffered FET logic. Schottky diode FET logic - a lower power approach - can reach higher complexities and strong efforts are being made in this direction. Enhancement type devices appear essential to reach LSI and VLSI complexity, but process control is still very difficult; strong efforts are under way, both in the U.S. and in Japan. Heterojunction devices appear very promising, although structures are fairly complex, and special fabrication techniques, such as molecular beam epitaxy and MOCVD, are necessary. High-electron-mobility-transistor (HEMT) devices show significant performance advantages over MESFETs at low temperatures. Initial results of heterojunction bipolar transistor devices show promise for high speed A/D converter applications.

Visible light laser voltage probing on thinned substrates

DOEpatents

Beutler, Joshua; Clement, John Joseph; Miller, Mary A.; Stevens, Jeffrey; Cole, Jr., Edward I.

2017-03-21

The various technologies presented herein relate to utilizing visible light in conjunction with a thinned structure to enable characterization of operation of one or more features included in an integrated circuit (IC). Short wavelength illumination (e.g., visible light) is applied to thinned samples (e.g., ultra-thinned samples) to achieve a spatial resolution for laser voltage probing (LVP) analysis to be performed on smaller technology node silicon-on-insulator (SOI) and bulk devices. Thinning of a semiconductor material included in the IC (e.g., backside material) can be controlled such that the thinned semiconductor material has sufficient thickness to enable operation of one or more features comprising the IC during LVP investigation.

Interface design for CMOS-integrated Electrochemical Impedance Spectroscopy (EIS) biosensors.

PubMed

Manickam, Arun; Johnson, Christopher Andrew; Kavusi, Sam; Hassibi, Arjang

2012-10-29

Electrochemical Impedance Spectroscopy (EIS) is a powerful electrochemical technique to detect biomolecules. EIS has the potential of carrying out label-free and real-time detection, and in addition, can be easily implemented using electronic integrated circuits (ICs) that are built through standard semiconductor fabrication processes. This paper focuses on the various design and optimization aspects of EIS ICs, particularly the bio-to-semiconductor interface design. We discuss, in detail, considerations such as the choice of the electrode surface in view of IC manufacturing, surface linkers, and development of optimal bio-molecular detection protocols. We also report experimental results, using both macro- and micro-electrodes to demonstrate the design trade-offs and ultimately validate our optimization procedures.

Comparing the Robustness of High-Frequency Traveling-Wave Tube Slow-Wave Circuits

NASA Technical Reports Server (NTRS)

Chevalier, Christine T.; Wilson, Jeffrey D.; Kory, Carol L.

2007-01-01

A three-dimensional electromagnetic field simulation software package was used to compute the cold-test parameters, phase velocity, on-axis interaction impedance, and attenuation, for several high-frequency traveling-wave tube slow-wave circuit geometries. This research effort determined the effects of variations in circuit dimensions on cold-test performance. The parameter variations were based on the tolerances of conventional micromachining techniques.

High-Tc superconductor coplanar waveguide filter

NASA Technical Reports Server (NTRS)

Chew, Wilbert; Bajuk, Louis J.; Cooley, Thomas W.; Foote, Marc C.; Hunt, Brian D.; Rascoe, Daniel L.; Riley, A. L.

1991-01-01

Coplanar waveguide (CPW) low-pass filters made of YBa2Cu3O(7-delta) (YBCO) on LaAlO3 substrates, with dimensions suited for integrated circuits, were fabricated and packaged. A complete filter gives a true idea of the advantages and difficulties in replacing thin-film metal with a high-temperature superconductor in a practical circuit. Measured insertion losses in liquid nitrogen were superior to the loss of a similar thin-film copper filter throughout the 0- to 9.5-GHz passband. These results demonstrate the performance of fully patterned YBCO in a practical CPW structure after sealing in a hermetic package.

PCSIM: A Parallel Simulation Environment for Neural Circuits Fully Integrated with Python

PubMed Central

Pecevski, Dejan; Natschläger, Thomas; Schuch, Klaus

2008-01-01

The Parallel Circuit SIMulator (PCSIM) is a software package for simulation of neural circuits. It is primarily designed for distributed simulation of large scale networks of spiking point neurons. Although its computational core is written in C++, PCSIM's primary interface is implemented in the Python programming language, which is a powerful programming environment and allows the user to easily integrate the neural circuit simulator with data analysis and visualization tools to manage the full neural modeling life cycle. The main focus of this paper is to describe PCSIM's full integration into Python and the benefits thereof. In particular we will investigate how the automatically generated bidirectional interface and PCSIM's object-oriented modular framework enable the user to adopt a hybrid modeling approach: using and extending PCSIM's functionality either employing pure Python or C++ and thus combining the advantages of both worlds. Furthermore, we describe several supplementary PCSIM packages written in pure Python and tailored towards setting up and analyzing neural simulations. PMID:19543450

Thick photosensitive polyimide film side wall angle variability and scum improvement for IC packaging stress control

NASA Astrophysics Data System (ADS)

Mehta, Sohan Singh; Yeung, Marco; Mirza, Fahad; Raman, Thiagarajan; Longenbach, Travis; Morgan, Justin; Duggan, Mark; Soedibyo, Rio A.; Reidy, Sean; Rabie, Mohamed; Cho, Jae Kyu; Premachandran, C. S.; Faruqui, Danish

2018-03-01

In this paper, we demonstrate photosensitive polyimide (PSPI) profile optimization to effectively reduce stress concentrations and enable PSPI as protection package-induced stress. Through detailed package simulation, we demonstrate 45% reduction in stress as the sidewall angle (SWA) of PSPI is increased from 45 to 80 degrees in Cu pillar package types. Through modulation of coating and develop multi-step baking temperature and time, as well as dose energy and post litho surface treatments, we demonstrate a method for reliably obtaining PSPI sidewall angle >75 degree. Additionally, we experimentally validate the simulation findings that PSPI sidewall angle impacts chip package interaction (CPI). Finally, we conclude this paper with PSPI material and tool qualification requirements for future technology node based on current challenges.

Push plate, mounting assembly, circuit board, and method of assembling thereof for ball grid array packages

DOE Office of Scientific and Technical Information (OSTI.GOV)

Vaughn, Mark R.; Montague, Stephen

A push plate that includes springs in the form of cantilever flexures and an inspection window is disclosed. The push plate provides a known, uniform, down force and minimal torque to a package to be tested. The cantilevers have a known, calculable down force producing stiffness. The window provides for viewing of the package during testing.

IEEE WMED 2016 Homepage

Science.gov Websites

characterization, design, and new device technologies. This workshop will consist of invited talks, contributed and Reliability Semiconductor package reliability, Design for Manufacturability, Stacked die packaging and Novel assembly processes Microelectronic Circuit Design New product design, high-speed and/or low

Molecular Isotopic Distribution Analysis (MIDAs) with Adjustable Mass Accuracy

NASA Astrophysics Data System (ADS)

Alves, Gelio; Ogurtsov, Aleksey Y.; Yu, Yi-Kuo

2014-01-01

In this paper, we present Molecular Isotopic Distribution Analysis (MIDAs), a new software tool designed to compute molecular isotopic distributions with adjustable accuracies. MIDAs offers two algorithms, one polynomial-based and one Fourier-transform-based, both of which compute molecular isotopic distributions accurately and efficiently. The polynomial-based algorithm contains few novel aspects, whereas the Fourier-transform-based algorithm consists mainly of improvements to other existing Fourier-transform-based algorithms. We have benchmarked the performance of the two algorithms implemented in MIDAs with that of eight software packages (BRAIN, Emass, Mercury, Mercury5, NeutronCluster, Qmass, JFC, IC) using a consensus set of benchmark molecules. Under the proposed evaluation criteria, MIDAs's algorithms, JFC, and Emass compute with comparable accuracy the coarse-grained (low-resolution) isotopic distributions and are more accurate than the other software packages. For fine-grained isotopic distributions, we compared IC, MIDAs's polynomial algorithm, and MIDAs's Fourier transform algorithm. Among the three, IC and MIDAs's polynomial algorithm compute isotopic distributions that better resemble their corresponding exact fine-grained (high-resolution) isotopic distributions. MIDAs can be accessed freely through a user-friendly web-interface at http://www.ncbi.nlm.nih.gov/CBBresearch/Yu/midas/index.html.

Molecular Isotopic Distribution Analysis (MIDAs) with adjustable mass accuracy.

PubMed

Alves, Gelio; Ogurtsov, Aleksey Y; Yu, Yi-Kuo

2014-01-01

In this paper, we present Molecular Isotopic Distribution Analysis (MIDAs), a new software tool designed to compute molecular isotopic distributions with adjustable accuracies. MIDAs offers two algorithms, one polynomial-based and one Fourier-transform-based, both of which compute molecular isotopic distributions accurately and efficiently. The polynomial-based algorithm contains few novel aspects, whereas the Fourier-transform-based algorithm consists mainly of improvements to other existing Fourier-transform-based algorithms. We have benchmarked the performance of the two algorithms implemented in MIDAs with that of eight software packages (BRAIN, Emass, Mercury, Mercury5, NeutronCluster, Qmass, JFC, IC) using a consensus set of benchmark molecules. Under the proposed evaluation criteria, MIDAs's algorithms, JFC, and Emass compute with comparable accuracy the coarse-grained (low-resolution) isotopic distributions and are more accurate than the other software packages. For fine-grained isotopic distributions, we compared IC, MIDAs's polynomial algorithm, and MIDAs's Fourier transform algorithm. Among the three, IC and MIDAs's polynomial algorithm compute isotopic distributions that better resemble their corresponding exact fine-grained (high-resolution) isotopic distributions. MIDAs can be accessed freely through a user-friendly web-interface at http://www.ncbi.nlm.nih.gov/CBBresearch/Yu/midas/index.html.

A Integrated Circuit for a Biomedical Capacitive Pressure Transducer

NASA Astrophysics Data System (ADS)

Smith, Michael John Sebastian

Medical research has an urgent need for a small, accurate, stable, low-power, biocompatible and inexpensive pressure sensor with a zero to full-scale range of 0-300 mmHg. An integrated circuit (IC) for use with a capacitive pressure transducer was designed, built and tested. The random pressure measurement error due to resolution and non-linearity is (+OR-)0.4 mmHg (at mid-range with a full -scale of 300 mmHg). The long-term systematic error due to falling battery voltage is (+OR-)0.6 mmHg. These figures were calculated from measurements of temperature, supply dependence and non-linearity on completed integrated circuits. The sensor IC allows measurement of temperature to (+OR-)0.1(DEGREES)C to allow for temperature compensation of the transducer. Novel micropower circuit design of the system components enabled these levels of accuracy to be reached. Capacitance is measured by a new ratiometric scheme employing an on -chip reference capacitor. This method greatly reduces the effects of voltage supply, temperature and manufacturing variations on the sensor circuit performance. The limits on performance of the bandgap reference circuit fabricated with a standard bipolar process using ion-implanted resistors were determined. Measurements confirm the limits of temperature stability as approximately (+OR-)300 ppm/(DEGREES)C. An exact analytical expression for the period of the Schmitt trigger oscillator, accounting for non-constant capacitor charging current, was formulated. Experiments to test agreement with theory showed that prediction of the oscillator period was very accurate. The interaction of fundamental and practical limits on the scaling of the transducer size was investigated including a correction to previous theoretical analysis of jitter in an RC oscillator. An areal reduction of 4 times should be achievable.

Novel AlInN/GaN integrated circuits operating up to 500 °C

NASA Astrophysics Data System (ADS)

Gaska, R.; Gaevski, M.; Jain, R.; Deng, J.; Islam, M.; Simin, G.; Shur, M.

2015-11-01

High electron concentration in 2DEG channel of AlInN/GaN devices is remarkably stable over a broad temperature range, enabling device operation above 500 °C. The developed IC technology is based on three key elements: (1) exceptional quality AlInN/GaN heterostructure with very high carrier concentration and mobility enables IC fast operation in a broad temperature range; (2) heterostructure field effect transistor approach t provides fully planar IC structure which is easy to scale and to combine with the other high temperature electronic components; (3) fabrication advancements including novel metallization scheme and high-K passivation/gate dielectrics enable high temperature operation. The feasibility of the developed technology was confirmed by fabrication and testing of the high temperature inverter and differential amplifier ICs using AlInN/GaN heterostructures. The developed ICs showed stable performance with unit-gain bandwidth above 1 MHz and internal response time 45 ns at temperatures as high as 500 °C.

High operating temperature interband cascade focal plane arrays

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tian, Z.-B.; Godoy, S. E.; Kim, H. S.

2014-08-04

In this paper, we report the initial demonstration of mid-infrared interband cascade (IC) photodetector focal plane arrays with multiple-stage/junction design. The merits of IC photodetectors include low noise and efficient photocarrier extraction, even for zero-bias operation. By adopting enhanced electron barrier design and a total absorber thickness of 0.7 μm, the 5-stage IC detectors show very low dark current (1.10 × 10{sup −7} A/cm{sup 2} at −5 mV and 150 K). Even with un-optimized fabrication and standard commercial (mis-matched) read-out circuit technology, infrared images are obtained by the 320 × 256 IC focal plane array up to 180 K with f/2.3 optics. The minimum noise equivalent temperature differencemore » of 28 mK is obtained at 120 K. These initial results indicate great potential of IC photodetectors, particularly for high operating temperature applications.« less

How thin barrier metal can be used to prevent Co diffusion in the modern integrated circuits?

NASA Astrophysics Data System (ADS)

Dixit, Hemant; Konar, Aniruddha; Pandey, Rajan; Ethirajan, Tamilmani

2017-11-01

In modern integrated circuits (ICs), billions of transistors are connected to each other via thin metal layers (e.g. copper, cobalt, etc) known as interconnects. At elevated process temperatures, inter-diffusion of atomic species can occur among these metal layers, causing sub-optimal performance of interconnects, which may lead to the failure of an IC. Thus, typically a thin barrier metal layer is used to prevent the inter-diffusion of atomic species within interconnects. For ICs with sub-10 nm transistors (10 nm technology node), the design rule (thickness scaling) demands the thinnest possible barrier layer. Therefore, here we investigate the critical thickness of a titanium-nitride (TiN) barrier that can prevent the cobalt diffusion using multi-scale modeling and simulations. First, we compute the Co diffusion barrier in crystalline and amorphous TiN with the nudged elastic band method within first-principles density functional theory simulations. Later, using the calculated activation energy barriers, we quantify the Co diffusion length in the TiN metal layer with the help of kinetic Monte Carlo simulations. Such a multi-scale modelling approach yields an exact critical thickness of the metal layer sufficient to prevent the Co diffusion in IC interconnects. We obtain a diffusion length of a maximum of 2 nm for a typical process of thermal annealing at 400 °C for 30 min. Our study thus provides useful physical insights for the Co diffusion in the TiN layer and further quantifies the critical thickness (~2 nm) to which the metal barrier layer can be thinned down for sub-10 nm ICs.

Imbalanced spontaneous brain activity in orbitofrontal-insular circuits in individuals with cognitive vulnerability to depression.

PubMed

Zhang, Xiaocui; Di, Xin; Lei, Hui; Yang, Juan; Xiao, Jing; Wang, Xiang; Yao, Shuqiao; Rao, Hengyi

2016-07-01

The hopelessness theory of depression posits that individuals with negative cognitive styles are at risk of developing depression following negative life events. The purpose of this work was to examine whether individuals with cognitive vulnerability to depression (CVD) exhibit similar spontaneous brain activity patterns as compared to patients with major depressive disorder (MDD). Subjects with CVD (N=32), drug-naïve first-episode patients with major depressive disorder (N=32), and sex-, age- and education-matched healthy controls (HCs; N=35) were subjected to resting state functional magnetic resonance imaging (RS-fMRI) and amplitudes of low-frequency fluctuation (ALFF) was compared between the groups. Pearson correlation analysis was performed between regional ALFFs and psychometric scores, namely the Cognitive Style Questionnaire (CSQ) and the Center for Epidemiologic Studies Depression (CES-D) scale scores. Significant group differences in ALFF values were observed bilaterally in the orbitofrontal cortex (OFC) and insular cortex (IC), and in the left fusiform gyrus (FFG). Compared to HCs, CVD subjects had reduced ALFFs in the bilateral OFC and increased ALFF in the bilateral IC and the left FFG, which were similar to the differences observed between the HCs and MDD patients. Compared to MDD patients, CVD subjects showed significant reduced ALFF values in right IC. Additionally, CSQ scores for the CVD group correlated with ALFF values in the left IC. We did not conduct a longitudinal study. Our findings were limited in cross-sectional analysis. A hypoactive OFC and hyperactive IC in a resting-state may underlie an imbalance in the spontaneous brain activity in orbitofrontal-insular circuits, and these differences may represent a trait-related marker of vulnerability to depression. Copyright © 2016 Elsevier B.V. All rights reserved.

Postinhibitory rebound neurons and networks are disrupted in retrovirus-induced spongiform neurodegeneration

PubMed Central

Li, Ying; Davey, Robert A.; Lynch, William P.

2014-01-01

Certain retroviruses induce progressive spongiform motor neuron disease with features resembling prion diseases and amyotrophic lateral sclerosis. With the neurovirulent murine leukemia virus (MLV) FrCasE, Env protein expression within glia leads to postsynaptic vacuolation, cellular effacement, and neuronal loss in the absence of neuroinflammation. To understand the physiological changes associated with MLV-induced spongiosis, and its neuronal specificity, we employed patch-clamp recordings and voltage-sensitive dye imaging in brain slices of the mouse inferior colliculus (IC), a midbrain nucleus that undergoes extensive spongiosis. IC neurons characterized by postinhibitory rebound firing (PIR) were selectively affected in FrCasE-infected mice. Coincident with Env expression in microglia and in glia characterized by NG2 proteoglycan expression (NG2 cells), rebound neurons (RNs) lost PIR, became hyperexcitable, and were reduced in number. PIR loss and hyperexcitability were reversed by raising internal calcium buffer concentrations in RNs. PIR-initiated rhythmic circuits were disrupted, and spontaneous synchronized bursting and prolonged depolarizations were widespread. Other IC neuron cell types and circuits within the same degenerative environment were unaffected. Antagonists of NMDA and/or AMPA receptors reduced burst firing in the IC but did not affect prolonged depolarizations. Antagonists of L-type calcium channels abolished both bursts and slow depolarizations. IC infection by the nonneurovirulent isogenic virus Friend 57E (Fr57E), whose Env protein is structurally similar to FrCasE, showed no RN hyperactivity or cell loss; however, PIR latency increased. These findings suggest that spongiform neurodegeneration arises from the unique excitability of RNs, their local regulation by glia, and the disruption of this relationship by glial expression of abnormal protein. PMID:25252336

Out Flying the Eagle: China’s Drive for Domestic Economic Innovation and Its Impact on U.S.-China Relations

DTIC Science & Technology

2014-03-01

wind turbines from General Electric. China recognizes the issues with IPR but it is something that will take time to fix. It will be a significant...Large aircraft  Large-scale oil and gas exploration  Manned space, including lunar exploration  Next-generation broadband wireless ...circuits, and building an innovation system for China’s integrated circuit (IC) manufacturing industry. 3. New generation broadband wireless mobile

Non-Contact Circuit for Real-Time Electric and Magnetic Field Measurements

DTIC Science & Technology

2015-10-01

addresses these needs, and additionally has “smart” features that adjust integrated circuits ( ICs ) on the sensor during start-up based upon the...Hall effect sensors, the datasheet information on the MLX91205 gives a dynamic range of 66 to 96 dB for frequencies of 10 Hz and 10 kHz, respectively...Electric Field Sensors. 18 August 2009. 4. Melexis. IMC-Hall Current Sensor, MLX91205 Datasheet . June. 2012 5. Vinci SJ, Hull DM. Electrostatic

Silicon ball grid array chip carrier

DOEpatents

Palmer, David W.; Gassman, Richard A.; Chu, Dahwey

2000-01-01

A ball-grid-array integrated circuit (IC) chip carrier formed from a silicon substrate is disclosed. The silicon ball-grid-array chip carrier is of particular use with ICs having peripheral bond pads which can be reconfigured to a ball-grid-array. The use of a semiconductor substrate such as silicon for forming the ball-grid-array chip carrier allows the chip carrier to be fabricated on an IC process line with, at least in part, standard IC processes. Additionally, the silicon chip carrier can include components such as transistors, resistors, capacitors, inductors and sensors to form a "smart" chip carrier which can provide added functionality and testability to one or more ICs mounted on the chip carrier. Types of functionality that can be provided on the "smart" chip carrier include boundary-scan cells, built-in test structures, signal conditioning circuitry, power conditioning circuitry, and a reconfiguration capability. The "smart" chip carrier can also be used to form specialized or application-specific ICs (ASICs) from conventional ICs. Types of sensors that can be included on the silicon ball-grid-array chip carrier include temperature sensors, pressure sensors, stress sensors, inertia or acceleration sensors, and/or chemical sensors. These sensors can be fabricated by IC processes and can include microelectromechanical (MEM) devices.

A Subthreshold Digital Library Using a Dynamic-Threshold Metal-Oxide Semiconductor (DTMOS) and Transmission Gate Logic

DTIC Science & Technology

2014-09-01

electrocardiography (ECG), electromyography (EMG), and electroencephalography (EEG) applications that operate using thermoelectrically generated energy...semiconductor ECG electrocardiography EEG electroencephalography EMG electromyography FY15 fiscal year 2015 IC integrated circuit MOSFETs

Multilead, Vaporization-Cooled Soldering Heat Sink

NASA Technical Reports Server (NTRS)

Rice, John

1995-01-01

Vaporization-cooled heat sink proposed for use during soldering of multiple electrical leads of packaged electronic devices to circuit boards. Heat sink includes compliant wicks held in grooves on edges of metal fixture. Wicks saturated with water. Prevents excessive increases in temperature at entrances of leads into package.

Reduced-order modeling of piezoelectric energy harvesters with nonlinear circuits under complex conditions

NASA Astrophysics Data System (ADS)

Xiang, Hong-Jun; Zhang, Zhi-Wei; Shi, Zhi-Fei; Li, Hong

2018-04-01

A fully coupled modeling approach is developed for piezoelectric energy harvesters in this work based on the use of available robust finite element packages and efficient reducing order modeling techniques. At first, the harvester is modeled using finite element packages. The dynamic equilibrium equations of harvesters are rebuilt by extracting system matrices from the finite element model using built-in commands without any additional tools. A Krylov subspace-based scheme is then applied to obtain a reduced-order model for improving simulation efficiency but preserving the key features of harvesters. Co-simulation of the reduced-order model with nonlinear energy harvesting circuits is achieved in a system level. Several examples in both cases of harmonic response and transient response analysis are conducted to validate the present approach. The proposed approach allows to improve the simulation efficiency by several orders of magnitude. Moreover, the parameters used in the equivalent circuit model can be conveniently obtained by the proposed eigenvector-based model order reduction technique. More importantly, this work establishes a methodology for modeling of piezoelectric energy harvesters with any complicated mechanical geometries and nonlinear circuits. The input load may be more complex also. The method can be employed by harvester designers to optimal mechanical structures or by circuit designers to develop novel energy harvesting circuits.

Stoves or Sugar? Willingness to Adopt Improved Cookstoves in Malawi

PubMed Central

Jagger, Pamela; Jumbe, Charles

2016-01-01

Malawi has set a target of adoption of two million improved cookstoves (ICS) by 2020. Meeting this objective requires knowledge about determinants of adoption, particularly in rural areas where the cost of traditional cooking technologies and fuels are non-monetary, and where people have limited capacity to purchase an ICS. We conducted a discrete choice experiment with 383 households in rural Malawi asking them if they would chose a locally made ICS or a package of sugar and salt of roughly equal value. Six months later, we assessed adoption and stove use patterns. Sixty-six percent of households chose the ICS. We find that having a larger share of crop residues in household fuel supply, awareness of the environmental impacts of woodfuel reliance, time the primary cook devotes to collecting fuelwood, and peer effects at the village-level increase the odds of choosing the ICS. Having a large labor supply for fuelwood collection and experience with a non-traditional cooking technology decreased the odds of choosing the ICS. In a rapid assessment six months after stoves were distributed, we found 80% of households were still using the ICS, but not exclusively. Our findings suggest considerable potential for wide-scale adoption of ICS in Malawi. PMID:27346912

Novel Vertical Interconnects With 180 Degree Phase Shift for Amplifiers, Filters, and Integrated Antennas

NASA Technical Reports Server (NTRS)

Goverdhanam, Kavita; Simons, Rainee N.; Katehi, Linda P. B.; Burke, Thomas P. (Technical Monitor)

2001-01-01

In this paper, novel low loss, wide-band coplanar stripline technology for RF/microwave integrated circuits is demonstrated on high resistivity silicon wafer. In particular, the fabrication process for the deposition of spin-on-glass (SOG) as a dielectric layer, the etching of microvias for the vertical interconnects, the design methodology for the multiport circuits and their measured/simulated characteristics are graphically illustrated. The study shows that circuits with very low loss, large bandwidth and compact size are feasible using this technology. This multilayer planar technology has potential to significantly enhance RF/microwave IC performance when combined with semiconductor devices and microelectromechanical systems (MEMS).

Milliwatt dc/dc Inverter

NASA Technical Reports Server (NTRS)

Mclyman, C. W.

1983-01-01

Compact dc/dc inverter uses single integrated-circuit package containing six inverter gates that generate and amplify 100-kHz square-wave switching signal. Square-wave switching inverts 10-volt local power to isolated voltage at another desired level. Relatively high operating frequency reduces size of filter capacitors required, resulting in small package unit.

An RFID-based on-lens sensor system for long-term IOP monitoring.

PubMed

Hsu, Shun-Hsi; Chiou, Jin-Chern; Liao, Yu-Te; Yang, Tzu-Sen; Kuei, Cheng-Kai; Wu, Tsung-Wei; Huang, Yu-Chieh

2015-01-01

In this paper, an RFID-based on-lens sensor system is proposed for noninvasive long-term intraocular pressure monitoring. The proposed sensor IC, fabricated in a 0.18um CMOS process, consists of capacitive sensor readout circuitry, RFID communication circuits, and digital processing units. The sensor IC is integrated with electroplating capacitive sensors and a receiving antenna on the contact lens. The sensor IC can be wirelessly powered, communicate with RFID compatible equipment, and perform IOP measurement using on-lens capacitive sensor continuously from a 2cm distance while the incident power from an RFID reader is 20 dBm. The proposed system is compatible to Gen2 RFID protocol, extending the flexibility and reducing the self-developed firmware efforts.

3D-ICs created using oblique processing

NASA Astrophysics Data System (ADS)

Burckel, D. Bruce

2016-03-01

This paper demonstrates that another class of three-dimensional integrated circuits (3D-ICs) exists, distinct from through silicon via centric and monolithic 3D-ICs. Furthermore, it is possible to create devices that are 3D at the device level (i.e. with active channels oriented in each of the three coordinate axes), by performing standard CMOS fabrication operations at an angle with respect to the wafer surface into high aspect ratio silicon substrates using membrane projection lithography (MPL). MPL requires only minimal fixturing changes to standard CMOS equipment, and no change to current state-of-the-art lithography. Eliminating the constraint of 2D planar device architecture enables a wide range of new interconnect topologies which could help reduce interconnect resistance/capacitance, and potentially improve performance.

Counterfeit Electronics Detection Using Image Processing and Machine Learning

NASA Astrophysics Data System (ADS)

Asadizanjani, Navid; Tehranipoor, Mark; Forte, Domenic

2017-01-01

Counterfeiting is an increasing concern for businesses and governments as greater numbers of counterfeit integrated circuits (IC) infiltrate the global market. There is an ongoing effort in experimental and national labs inside the United States to detect and prevent such counterfeits in the most efficient time period. However, there is still a missing piece to automatically detect and properly keep record of detected counterfeit ICs. Here, we introduce a web application database that allows users to share previous examples of counterfeits through an online database and to obtain statistics regarding the prevalence of known defects. We also investigate automated techniques based on image processing and machine learning to detect different physical defects and to determine whether or not an IC is counterfeit.

Towards co-packaging of photonics and microelectronics in existing manufacturing facilities

NASA Astrophysics Data System (ADS)

Janta-Polczynski, Alexander; Cyr, Elaine; Bougie, Jerome; Drouin, Alain; Langlois, Richard; Childers, Darrell; Takenobu, Shotaro; Taira, Yoichi; Lichoulas, Ted W.; Kamlapurkar, Swetha; Engelmann, Sebastian; Fortier, Paul; Boyer, Nicolas; Barwicz, Tymon

2018-02-01

The impact of integrated photonics on optical interconnects is currently muted by challenges in photonic packaging and in the dense integration of photonic modules with microelectronic components on printed circuit boards. Single mode optics requires tight alignment tolerance for optical coupling and maintaining this alignment in a cost-efficient package can be challenging during thermal excursions arising from downstream microelectronic assembly processes. In addition, the form factor of typical fiber connectors is incompatible with the dense module integration expected on printed circuit boards. We have implemented novel approaches to interfacing photonic chips to standard optical fibers. These leverage standard high throughput microelectronic assembly tooling and self-alignment techniques resulting in photonic packaging that is scalable in manufacturing volume and in the number of optical IOs per chip. In addition, using dense optical fiber connectors with space-efficient latching of fiber patch cables results in compact module size and efficient board integration, bringing the optics closer to the logic chip to alleviate bandwidth bottlenecks. This packaging direction is also well suited for embedding optics in multi-chip modules, including both photonic and microelectronic chips. We discuss the challenges and rewards in this type of configuration such as thermal management and signal integrity.

Optomechanical Design and Characterization of a Printed-Circuit-Board-Based Free-Space Optical Interconnect Package

NASA Astrophysics Data System (ADS)

Zheng, Xuezhe; Marchand, Philippe J.; Huang, Dawei; Kibar, Osman; Ozkan, Nur S. E.; Esener, Sadik C.

1999-09-01

We present a proof of concept and a feasibility demonstration of a practical packaging approach in which free-space optical interconnects (FSOI s) can be integrated simply on electronic multichip modules (MCM s) for intra-MCM board interconnects. Our system-level packaging architecture is based on a modified folded 4 f imaging system that has been implemented with only off-the-shelf optics, conventional electronic packaging, and passive-assembly techniques to yield a potentially low-cost and manufacturable packaging solution. The prototypical system as built supports 48 independent FSOI channels with 8 separate laser and detector chips, for which each chip consists of a one-dimensional array of 12 devices. All the chips are assembled on a single substrate that consists of a printed circuit board or a ceramic MCM. Optical link channel efficiencies of greater than 90% and interchannel cross talk of less than 20 dB at low frequency have been measured. The system is compact at only 10 in. 3 (25.4 cm 3 ) and is scalable, as it can easily accommodate additional chips as well as two-dimensional optoelectronic device arrays for increased interconnection density.

Packaging of microwave integrated circuits operating beyond 100 GHz

NASA Technical Reports Server (NTRS)

Samoska, L.; Daniel, E.; Sokolov, V.; Sommerfeldt, S.; Bublitz, J.; Olson, K.; Gilbert, B.; Chow, D.

2002-01-01

Several methods of packaging high speed (75-330 GHz) InP HEMT MMIC devices are discussed. Coplanar wirebonding is presented with measured insertion loss of less than 0.5dB and return loss better than -17 dB from DC to 110 GHz. A motherboard/daughterboard packaging scheme is presented which supports minimum loss chains of MMICs using this coplanar wirebonding method. Split waveguide block packaging approaches are presented in G-band (140-220 GHz) with two types of MMIC-waveguide transitions: E-plane probe andantipodal finline.

[Not Available].

PubMed

Pecevski, Dejan; Natschläger, Thomas; Schuch, Klaus

2009-01-01

The Parallel Circuit SIMulator (PCSIM) is a software package for simulation of neural circuits. It is primarily designed for distributed simulation of large scale networks of spiking point neurons. Although its computational core is written in C++, PCSIM's primary interface is implemented in the Python programming language, which is a powerful programming environment and allows the user to easily integrate the neural circuit simulator with data analysis and visualization tools to manage the full neural modeling life cycle. The main focus of this paper is to describe PCSIM's full integration into Python and the benefits thereof. In particular we will investigate how the automatically generated bidirectional interface and PCSIM's object-oriented modular framework enable the user to adopt a hybrid modeling approach: using and extending PCSIM's functionality either employing pure Python or C++ and thus combining the advantages of both worlds. Furthermore, we describe several supplementary PCSIM packages written in pure Python and tailored towards setting up and analyzing neural simulations.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Li, Menglu; Tu, K. N., E-mail: kntu@ucla.edu; Kim, Dong Wook

Thermal-crosstalk induced thermomigration failure in un-powered microbumps has been found in 2.5D integrated circuit (IC) circuit. In 2.5D IC, a Si interposer was used between a polymer substrate and a device chip which has transistors. The interposer has no transistors. If transistors are added to the interposer chip, it becomes 3D IC. In our test structure, there are two Si chips placed horizontally on a Si interposer. The vertical connections between the interposer and the Si chips are through microbumps. We powered one daisy chain of the microbumps under one Si chip; however, the un-powered microbumps in the neighboring chipmore » are failed with big holes in the solder layer. We find that Joule heating from the powered microbumps is transferred horizontally to the bottom of the neighboring un-powered microbumps, and creates a large temperature gradient, in the order of 1000 °C/cm, through the un-powered microbumps in the neighboring chip, so the latter failed by thermomigration. In addition, we used synchrotron radiation tomography to compare three sets of microbumps in the test structure: microbumps under electromigration, microbumps under thermomigration, and microbumps under a constant temperature thermal annealing. The results show that the microbumps under thermomigration have the largest damage. Furthermore, simulation of temperature distribution in the test structure supports the finding of thermomigration.« less

System-on-chip-centric unattended embedded sensors in homeland security and defense applications

NASA Astrophysics Data System (ADS)

Jannson, Tomasz; Forrester, Thomas; Degrood, Kevin; Shih, Min-Yi; Walter, Kevin; Lee, Kang; Gans, Eric; Esterkin, Vladimir

2009-05-01

System-on-chip (SoC) single-die electronic integrated circuit (IC) integration has recently been attracting a great deal of attention, due to its high modularity, universality, and relatively low fabrication cost. The SoC also has low power consumption and it is naturally suited to being a base for integration of embedded sensors. Such sensors can run unattended, and can be either commercial off-the-shelf (COTS) electronic, COTS microelectromechanical systems (MEMS), or optical-COTS or produced in house (i.e., at Physical Optics Corporation, POC). In the version with the simplest electronic packaging, they can be integrated with low-power wireless RF that can communicate with a central processing unit (CPU) integrated in-house and installed on the specific platform of interest. Such a platform can be a human body (for e-clothing), unmanned aerial vehicle (UAV), unmanned ground vehicle (UGV), or many others. In this paper we discuss SoC-centric embedded unattended sensors in Homeland Security and military applications, including specific application scenarios (or CONOPS). In one specific example, we analyze an embedded polarization optical sensor produced in house, including generalized Lambertian light-emitting diode (LED) sources and secondary nonimaging optics (NIO).

Thick resist for MEMS processing

NASA Astrophysics Data System (ADS)

Brown, Joe; Hamel, Clifford

2001-11-01

The need for technical innovation is always present in today's economy. Microfabrication methods have evolved in support of the demand for smaller and faster integrated circuits with price performance improvements always in the scope of the manufacturing design engineer. The dispersion of processing technology spans well beyond IC fabrication today with batch fabrication and wafer scale processing lending advantages to MEMES applications from biotechnology to consumer electronics from oil exploration to aerospace. Today the demand for innovative processing techniques that enable technology is apparent where only a few years ago appeared too costly or not reliable. In high volume applications where yield and cost improvements are measured in fractions of a percent it is imperative to have process technologies that produce consistent results. Only a few years ago thick resist coatings were limited to thickness less than 20 microns. Factors such as uniformity, edge bead and multiple coatings made high volume production impossible. New developments in photoresist formulation combined with advanced coating equipment techniques that closely controls process parameters have enable thick photoresist coatings of 70 microns with acceptable uniformity and edge bead in one pass. Packaging of microelectronic and micromechanical devices is often a significant cost factor and a reliability issue for high volume low cost production. Technologies such as flip- chip assembly provide a solution for cost and reliability improvements over wire bond techniques. The processing for such technology demands dimensional control and presents a significant cost savings if it were compatible with mainstream technologies. Thick photoresist layers, with good sidewall control would allow wafer-bumping technologies to penetrate the barriers to yield and production where costs for technology are the overriding issue. Single pass processing is paramount to the manufacturability of packaging technology. Uniformity and edge bead control defined the success of process implementation. Today advanced packaging solutions are created with thick photoresist coatings. The techniques and results will be presented.

AIN-Coated Al(2)O(3) Substrates For Electronic Circuits

NASA Technical Reports Server (NTRS)

Kolawa, Elzbieta; Lowry, Lynn; Herman, Martin; Lee, Karen

1996-01-01

Type of improved ceramic substrate for high-frequency, high-power electronic circuits combines relatively high thermal conductivity of aluminum nitride with surface smoothness of alumina. Consists of 15-micrometer layer of AIN deposited on highly polished alumina. Used for packaging millimeter-wave gallium arsenide transmitter chips, power silicon chips, and like.

Thin-film decoupling capacitors for multi-chip modules

NASA Astrophysics Data System (ADS)

Dimos, D.; Lockwood, S. J.; Schwartz, R. W.; Rogers, M. S.

Thin-film decoupling capacitors based on ferroelectric lead lanthanum zirconate titanate (PLZT) films are being developed for use in advanced packages, such as multi-chip modules. These thin-film decoupling capacitors are intended to replace multi-layer ceramic capacitors for certain applications, since they can be more fully integrated into the packaging architecture. The increased integration that can be achieved should lead to decreased package volume and improved high-speed performance, due to a decrease in interconnect inductance. PLZT films are fabricated by spin coating using metal carboxylate/alkoxide solutions. These films exhibit very high dielectric constants ((var epsilon) greater than or equal to 900), low dielectric losses (tan(delta) = 0.01), excellent insulation resistances (rho greater than 10(exp 13) (Omega)-cm at 125 C), and good breakdown field strengths (E(sub B) = 900 kV/cm). For integrated circuit applications, the PLZT dielectric is less than 1 micron thick, which results in a large capacitance/area (8-9 nF/sq mm). The thin-film geometry and processing conditions also make these capacitors suitable for direct incorporation onto integrated circuits and for packages that require embedded components.

Design of a Low-Power, Small-Area AEC-Q100-Compliant SENT Transmitter in Signal Conditioning IC for Automotive Pressure and Temperature Complex Sensors in 180 Nm CMOS Technology.

PubMed

Ali, Imran; Rikhan, Behnam Samadpoor; Kim, Dong-Gyu; Lee, Dong-Soo; Rehman, Muhammad Riaz Ur; Abbasizadeh, Hamed; Asif, Muhammad; Lee, Minjae; Hwang, Keum Cheol; Yang, Youngoo; Lee, Kang-Yoon

2018-05-14

In this paper, a low-power and small-area Single Edge Nibble Transmission (SENT) transmitter design is proposed for automotive pressure and temperature complex sensor applications. To reduce the cost and size of the hardware, the pressure and temperature information is processed with a single integrated circuit (IC) and transmitted at the same time to the electronic control unit (ECU) through SENT. Due to its digital nature, it is immune to noise, has reduced sensitivity to electromagnetic interference (EMI), and generates low EMI. It requires only one PAD for its connectivity with ECU, and thus reduces the pin requirements, simplifies the connectivity, and minimizes the printed circuit board (PCB) complexity. The design is fully synthesizable, and independent of technology. The finite state machine-based approach is employed for area efficient implementation, and to translate the proposed architecture into hardware. The IC is fabricated in 1P6M 180 nm CMOS process with an area of (116 μm × 116 μm) and 4.314 K gates. The current consumption is 50 μA from a 1.8 V supply with a total 90 μW power. For compliance with AEC-Q100 for automotive reliability, a reverse and over voltage protection circuit is also implemented with human body model (HBM) electro-static discharge (ESD) of +6 kV, reverse voltage of -16 V to 0 V, over voltage of 8.2 V to 16 V, and fabricated area of 330 μm × 680 μm. The extensive testing, measurement, and simulation results prove that the design is fully compliant with SAE J2716 standard.

Design of a Low-Power, Small-Area AEC-Q100-Compliant SENT Transmitter in Signal Conditioning IC for Automotive Pressure and Temperature Complex Sensors in 180 Nm CMOS Technology

PubMed Central

Rikhan, Behnam Samadpoor; Kim, Dong-Gyu; Lee, Dong-Soo; Rehman, Muhammad Riaz Ur; Abbasizadeh, Hamed; Asif, Muhammad; Lee, Minjae; Yang, Youngoo; Lee, Kang-Yoon

2018-01-01

In this paper, a low-power and small-area Single Edge Nibble Transmission (SENT) transmitter design is proposed for automotive pressure and temperature complex sensor applications. To reduce the cost and size of the hardware, the pressure and temperature information is processed with a single integrated circuit (IC) and transmitted at the same time to the electronic control unit (ECU) through SENT. Due to its digital nature, it is immune to noise, has reduced sensitivity to electromagnetic interference (EMI), and generates low EMI. It requires only one PAD for its connectivity with ECU, and thus reduces the pin requirements, simplifies the connectivity, and minimizes the printed circuit board (PCB) complexity. The design is fully synthesizable, and independent of technology. The finite state machine-based approach is employed for area efficient implementation, and to translate the proposed architecture into hardware. The IC is fabricated in 1P6M 180 nm CMOS process with an area of (116 μm × 116 μm) and 4.314 K gates. The current consumption is 50 μA from a 1.8 V supply with a total 90 μW power. For compliance with AEC-Q100 for automotive reliability, a reverse and over voltage protection circuit is also implemented with human body model (HBM) electro-static discharge (ESD) of +6 kV, reverse voltage of −16 V to 0 V, over voltage of 8.2 V to 16 V, and fabricated area of 330 μm × 680 μm. The extensive testing, measurement, and simulation results prove that the design is fully compliant with SAE J2716 standard. PMID:29757996

Compact Receiver Front Ends for Submillimeter-Wave Applications

NASA Technical Reports Server (NTRS)

Mehdi, Imran; Chattopadhyay, Goutam; Schlecht, Erich T.; Lin, Robert H.; Sin, Seth; Peralta, Alejandro; Lee, Choonsup; Gill, John J.; Gulkis, Samuel; Thomas, Bertrand C.

2012-01-01

The current generation of submillimeter-wave instruments is relatively mass and power-hungry. The receiver front ends (RFEs) of a submillimeter instrument form the heart of the instrument, and any mass reduction achieved in this subsystem is propagated through the instrument. In the current implementation, the RFE consists of different blocks for the mixer and LO circuits. The motivation for this work is to reduce the mass of the RFE by integrating the mixer and LO circuits in one waveguide block. The mixer and its associated LO chips will all be packaged in a single waveguide package. This will reduce the mass of the RFE and also provide a number of other advantages. By bringing the mixer and LO circuits close together, losses in the waveguide will be reduced. Moreover, the compact nature of the block will allow for better thermal control of the block, which is important in order to reduce gain fluctuations. A single waveguide block with a 600- GHz RFE functionality (based on a subharmonically pumped Schottky diode pair) has been demonstrated. The block is about 3x3x3 cubic centimeters. The block combines the mixer and multiplier chip in a single package. 3D electromagnetic simulations were carried out to design the waveguide circuit around the mixer and multiplier chip. The circuit is optimized to provide maximum output power and maximum bandwidth. An integrated submillimeter front end featuring a 520-600-GHz sub-harmonic mixer and a 260-300-GHz frequency tripler in a single cavity was tested. Both devices used GaAs MMIC membrane planar Schottky diode technology. The sub-harmonic mixer/tripler circuit has been tested using conventional metal-machined blocks. Measurement results on the metal block give best DSB (double sideband) mixer noise temperature of 2,360 K and conversion losses of 7.7 dB at 520 GHz. The LO input power required to pump the integrated tripler/sub-harmonic mixer is between 30 and 50 mW.

The design of radiation-hardened ICs for space - A compendium of approaches

NASA Technical Reports Server (NTRS)

Kerns, Sherra E.; Shafer, B. D; Rockett, L. R., Jr.; Pridmore, J. S.; Berndt, D. F.

1988-01-01

Several technologies, including bulk and epi CMOS, CMOS/SOI-SOS (silicon-on-insulator-silicon-on-sapphire), CML (current-mode logic), ECL (emitter-coupled logic), analog bipolar (JI, single-poly DI, and SOI) and GaAs E/D (enhancement/depletion) heterojunction MESFET, are discussed. The discussion includes the direct effects of space radiation on microelectronic materials and devices, how these effects are evidenced in circuit and device design parameter variations, the particular effects of most significance to each functional class of circuit, specific techniques for hardening high-speed circuits, design examples for integrated systems, including operational amplifiers and A/D (analog/digital) converters, and the computer simulation of radiation effects on microelectronic ISs.

QDENSITY—A Mathematica Quantum Computer simulation

NASA Astrophysics Data System (ADS)

Juliá-Díaz, Bruno; Burdis, Joseph M.; Tabakin, Frank

2006-06-01

This Mathematica 5.2 package is a simulation of a Quantum Computer. The program provides a modular, instructive approach for generating the basic elements that make up a quantum circuit. The main emphasis is on using the density matrix, although an approach using state vectors is also implemented in the package. The package commands are defined in Qdensity.m which contains the tools needed in quantum circuits, e.g., multiqubit kets, projectors, gates, etc. Selected examples of the basic commands are presented here and a tutorial notebook, Tutorial.nb is provided with the package (available on our website) that serves as a full guide to the package. Finally, application is made to a variety of relevant cases, including Teleportation, Quantum Fourier transform, Grover's search and Shor's algorithm, in separate notebooks: QFT.nb, Teleportation.nb, Grover.nb and Shor.nb where each algorithm is explained in detail. Finally, two examples of the construction and manipulation of cluster states, which are part of "one way computing" ideas, are included as an additional tool in the notebook Cluster.nb. A Mathematica palette containing most commands in QDENSITY is also included: QDENSpalette.nb. Program summaryTitle of program: QDENSITY Catalogue identifier: ADXH_v1_0 Program summary URL:http://cpc.cs.qub.ac.uk/summaries/ADXH_v1_0 Program available from: CPC Program Library, Queen's University of Belfast, N. Ireland Operating systems: Any which supports Mathematica; tested under Microsoft Windows XP, Macintosh OS X, and Linux FC4 Programming language used: Mathematica 5.2 No. of bytes in distributed program, including test data, etc.: 180 581 No. of lines in distributed program, including test data, etc.: 19 382 Distribution format: tar.gz Method of solution: A Mathematica package is provided which contains commands to create and analyze quantum circuits. Several Mathematica notebooks containing relevant examples: Teleportation, Shor's Algorithm and Grover's search are explained in detail. A tutorial, Tutorial.nb is also enclosed. QDENSITY is available at http://www.pitt.edu/~tabakin/QDENSITY.

A high-speed trapezoid image sensor design for continuous traffic monitoring at signalized intersection approaches.

DOT National Transportation Integrated Search

2014-10-01

The goal of this project is to monitor traffic flow continuously with an innovative camera system composed of a custom : designed image sensor integrated circuit (IC) containing trapezoid pixel array and camera system that is capable of : intelligent...

Field Programmable Gate Array Failure Rate Estimation Guidelines for Launch Vehicle Fault Tree Models

NASA Technical Reports Server (NTRS)

Al Hassan, Mohammad; Britton, Paul; Hatfield, Glen Spencer; Novack, Steven D.

2017-01-01

Today's launch vehicles complex electronic and avionics systems heavily utilize Field Programmable Gate Array (FPGA) integrated circuits (IC) for their superb speed and reconfiguration capabilities. Consequently, FPGAs are prevalent ICs in communication protocols such as MILSTD- 1553B and in control signal commands such as in solenoid valve actuations. This paper will identify reliability concerns and high level guidelines to estimate FPGA total failure rates in a launch vehicle application. The paper will discuss hardware, hardware description language, and radiation induced failures. The hardware contribution of the approach accounts for physical failures of the IC. The hardware description language portion will discuss the high level FPGA programming languages and software/code reliability growth. The radiation portion will discuss FPGA susceptibility to space environment radiation.

On the use of new generation mobile phone (smart phone) for retrospective accident dosimetry

NASA Astrophysics Data System (ADS)

Lee, J. I.; Chang, I.; Pradhan, A. S.; Kim, J. L.; Kim, B. H.; Chung, K. S.

2015-11-01

Optically stimulated luminescence (OSL) characteristics of resistors, inductors and integrated-circuit (IC) chips, extracted from new generation smart phones, were investigated for the purpose of retrospective accident dosimetry. Inductor samples were found to exhibit OSL sensitivity about 5 times and 40 times higher than that of the resistors and the IC chips, respectively. On post-irradiation storage, the resistors exhibited a much higher OSL fading (about 80 % in 36 h as compared to the value 3 min after irradiation) than IC chips (about 20 % after 36 h) and inductors (about 50 % in 36 h). Higher OSL sensitivity, linear dose response (from 8.7 mGy up to 8.9 Gy) and acceptable fading make inductors more attractive for accident dosimetry than widely studied resistors.

Nonlinear relaxation algorithms for circuit simulation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Saleh, R.A.

Circuit simulation is an important Computer-Aided Design (CAD) tool in the design of Integrated Circuits (IC). However, the standard techniques used in programs such as SPICE result in very long computer-run times when applied to large problems. In order to reduce the overall run time, a number of new approaches to circuit simulation were developed and are described. These methods are based on nonlinear relaxation techniques and exploit the relative inactivity of large circuits. Simple waveform-processing techniques are described to determine the maximum possible speed improvement that can be obtained by exploiting this property of large circuits. Three simulation algorithmsmore » are described, two of which are based on the Iterated Timing Analysis (ITA) method and a third based on the Waveform-Relaxation Newton (WRN) method. New programs that incorporate these techniques were developed and used to simulate a variety of industrial circuits. The results from these simulations are provided. The techniques are shown to be much faster than the standard approach. In addition, a number of parallel aspects of these algorithms are described, and a general space-time model of parallel-task scheduling is developed.« less

FAST: a framework for simulation and analysis of large-scale protein-silicon biosensor circuits.

PubMed

Gu, Ming; Chakrabartty, Shantanu

2013-08-01

This paper presents a computer aided design (CAD) framework for verification and reliability analysis of protein-silicon hybrid circuits used in biosensors. It is envisioned that similar to integrated circuit (IC) CAD design tools, the proposed framework will be useful for system level optimization of biosensors and for discovery of new sensing modalities without resorting to laborious fabrication and experimental procedures. The framework referred to as FAST analyzes protein-based circuits by solving inverse problems involving stochastic functional elements that admit non-linear relationships between different circuit variables. In this regard, FAST uses a factor-graph netlist as a user interface and solving the inverse problem entails passing messages/signals between the internal nodes of the netlist. Stochastic analysis techniques like density evolution are used to understand the dynamics of the circuit and estimate the reliability of the solution. As an example, we present a complete design flow using FAST for synthesis, analysis and verification of our previously reported conductometric immunoassay that uses antibody-based circuits to implement forward error-correction (FEC).

Sensing circuits for multiwire proportional chambers

NASA Technical Reports Server (NTRS)

Peterson, H. T.; Worley, E. R.

1977-01-01

Integrated sensing circuits were designed, fabricated, and packaged for use in determining the direction and fluence of ionizing radiation passing through a multiwire proportional chamber. CMOS on sapphire was selected because of its high speed and low power capabilities. The design of the proposed circuits is described and the results of computer simulations are presented. The fabrication processes for the CMOS on sapphire sensing circuits and hybrid substrates are outlined. Several design options are described and the cost implications of each discussed. To be most effective, each chip should handle not more than 32 inputs, and should be mounted on its own hybrid substrate.

Compact fluid cooled power converter supporting multiple circuit boards

DOEpatents

Radosevich, Lawrence D.; Meyer, Andreas A.; Beihoff, Bruce C.; Kannenberg, Daniel G.

2005-03-08

A support may receive one or more power electronic circuits. The support may aid in removing heat from the circuits through fluid circulating through the support. The support, in conjunction with other packaging features may form a shield from both external EMI/RFI and from interference generated by operation of the power electronic circuits. Features may be provided to permit and enhance connection of the circuitry to external circuitry, such as improved terminal configurations. Modular units may be assembled that may be coupled to electronic circuitry via plug-in arrangements or through interface with a backplane or similar mounting and interconnecting structures.

MEMS Applications in Aerodynamic Measurement Technology

NASA Technical Reports Server (NTRS)

Reshotko, E.; Mehregany, M.; Bang, C.

1998-01-01

Microelectromechanical systems (MEMS) embodies the integration of sensors, actuators, and electronics on a single substrate using integrated circuit fabrication techniques and compatible bulk and surface micromachining processes. Silicon and its derivatives form the material base for the MEMS technology. MEMS devices, including microsensors and microactuators, are attractive because they can be made small (characteristic dimension about 100 microns), be produced in large numbers with uniform performance, include electronics for high performance and sophisticated functionality, and be inexpensive. For aerodynamic measurements, it is preferred that sensors be small so as to approximate measurement at a point, and in fact, MEMS pressure sensors, wall shear-stress sensors, heat flux sensors and micromachined hot wires are nearing application. For the envisioned application to wind tunnel models, MEMS sensors can be placed on the surface or in very shallow grooves. MEMS devices have often been fabricated on stiff, flat silicon substrates, about 0.5 mm thick, and therefore were not easily mounted on curved surfaces. However, flexible substrates are now available and heat-flux sensor arrays have been wrapped around a curved turbine blade. Electrical leads can also be built into the flexible substrate. Thus MEMS instrumented wind tunnel models do not require deep spanwise grooves for tubes and leads that compromise the strength of conventionally instrumented models. With MEMS, even the electrical leads can potentially be eliminated if telemetry of the signals to an appropriate receiver can be implemented. While semiconductor silicon is well known for its electronic properties, it is also an excellent mechanical material for MEMS applications. However, silicon electronics are limited to operations below about 200 C, and silicon's mechanical properties start to diminish above 400 C. In recent years, silicon carbide (SiC) has emerged as the leading material candidate for applications in high temperature environments and can be used for high-temperature MEMS applications. With SiC, diodes and more complex electronics have been shown to operate to about 600 C, while the mechanical properties of SiC are maintained to much higher temperatures. Even when MEMS devices show benefits in the laboratory, there are many packaging challenges for any aeronautics application. Incorporating MEMS into these applications requires new approaches to packaging that goes beyond traditional integrated circuit (IC) packaging technologies. MEMS must interact mechanically, as well as electrically with their environment, making most traditional chip packaging and mounting techniques inadequate. Wind tunnels operate over wide temperature ranges in an environment that is far from being a 'clean-room.' In flight, aircraft are exposed to natural elements (e.g. rain, sun, ice, insects and dirt) and operational interferences(e.g. cleaning and deicing fluids, and maintenance crews). In propulsion systems applications, MEMS devices will have to operate in environments containing gases with very high temperatures, abrasive particles and combustion products. Hence deployment and packaging that maintains the integrity of the MEMS system is crucial. This paper presents an overview of MEMS fabrication and materials, descriptions of available sensors with more details on those being developed in our laboratories, and a discussion of sensor deployment options for wind tunnel and flight applications.

Thermal Conductivity of Carbon Nanotube Composite Films

NASA Technical Reports Server (NTRS)

Ngo, Quoc; Cruden, Brett A.; Cassell, Alan M.; Walker, Megan D.; Koehne, Jessica E.; Meyyappan, M.; Li, Jun; Yang, Cary Y.

2004-01-01

State-of-the-art ICs for microprocessors routinely dissipate power densities on the order of 50 W/sq cm. This large power is due to the localized heating of ICs operating at high frequencies, and must be managed for future high-frequency microelectronic applications. Our approach involves finding new and efficient thermally conductive materials. Exploiting carbon nanotube (CNT) films and composites for their superior axial thermal conductance properties has the potential for such an application requiring efficient heat transfer. In this work, we present thermal contact resistance measurement results for CNT and CNT-Cu composite films. It is shown that Cu-filled CNT arrays enhance thermal conductance when compared to as-grown CNT arrays. Furthermore, the CNT-Cu composite material provides a mechanically robust alternative to current IC packaging technology.

Recent advances in photonics packaging materials

NASA Astrophysics Data System (ADS)

Zweben, Carl

2006-02-01

There are now over a dozen low-CTE materials with thermal conductivities between that of copper (400 w/m-K) and over 4X copper (1700 W/m-K). Most have low densities. For comparison, traditional low-CTE packaging materials like copper/tungsten have thermal conductivities that are little or no better than that of aluminum (200 W/m-K) and high densities. There are also low-density thermal insulators with low CTEs. Some advanced materials are low cost. Most do not outgas. They have a wide range of electrical properties that can be used to minimize electromagnetic emissions or provide EMI shielding. Several are now in commercial and aerospace applications, including laser diode packages; light-emitting diode (LED) packages; thermoelectric cooler bases, plasma displays; power modules; servers; laptops; heat sinks; thermally conductive, low-CTE printed circuit boards; and printed circuit board cold plates. Advanced material payoffs include: improved thermal performance, reliability, alignment and manufacturing yield; reduced thermal stresses and heating power requirements; simplified thermal design; enablement of hard solder direct attach; weight savings up to 85%; size reductions up to 65%; and lower cost. This paper discusses the large and increasing number of advanced packaging materials, including properties, development status, applications, increasing manufacturing yield, cost, lessons learned and future directions, including nanocomposites.

Recent progress in low-temperature-process monolithic three dimension technology

NASA Astrophysics Data System (ADS)

Yang, Chih-Chao; Hsieh, Tung-Ying; Huang, Wen-Hsien; Shen, Chang-Hong; Shieh, Jia-Min; Yeh, Wen-Kuan; Wu, Meng-Chyi

2018-04-01

Monolithic three-dimension (3D) integration is an ultimate alternative method of fabricating high density, high performance, and multi-functional integrated circuits. It offers the promise of being a new approach to increase system performance. How to manage the thermal impact of multi-tiered processes, such as dopant activation, source/drain silicidation, and channel formation, and to prevent the degradation of pre-existing devices/circuits become key challenges. In this paper, we provide updates on several important monolithic 3D works, particularly in sequentially stackable channels, and our recent achievements in monolithic 3D integrated circuit (3D-IC). These results indicate that the advanced 3D architecture with novel design tools enables ultrahigh-density stackable circuits to have superior performance and low power consumption for future artificial intelligence (AI) and internet of things (IoTs) application.

CAFE: an R package for the detection of gross chromosomal abnormalities from gene expression microarray data.

PubMed

Bollen, Sander; Leddin, Mathias; Andrade-Navarro, Miguel A; Mah, Nancy

2014-05-15

The current methods available to detect chromosomal abnormalities from DNA microarray expression data are cumbersome and inflexible. CAFE has been developed to alleviate these issues. It is implemented as an R package that analyzes Affymetrix *.CEL files and comes with flexible plotting functions, easing visualization of chromosomal abnormalities. CAFE is available from https://bitbucket.org/cob87icW6z/cafe/ as both source and compiled packages for Linux and Windows. It is released under the GPL version 3 license. CAFE will also be freely available from Bioconductor. sander.h.bollen@gmail.com or nancy.mah@mdc-berlin.de Supplementary data are available at Bioinformatics online.

Bi-level microelectronic device package with an integral window

DOEpatents

Peterson, Kenneth A.; Watson, Robert D.

2004-01-06

A package with an integral window for housing a microelectronic device. The integral window is bonded directly to the package without having a separate layer of adhesive material disposed in-between the window and the package. The device can be a semiconductor chip, CCD chip, CMOS chip, VCSEL chip, laser diode, MEMS device, or IMEMS device. The multilayered package can be formed of a LTCC or HTCC cofired ceramic material, with the integral window being simultaneously joined to the package during LTCC or HTCC processing. The microelectronic device can be flip-chip bonded so that the light-sensitive side is optically accessible through the window. The package has at least two levels of circuits for making electrical interconnections to a pair of microelectronic devices. The result is a compact, low-profile package having an integral window that is hermetically sealed to the package prior to mounting and interconnecting the microelectronic device(s).

Preparation of calibrated test packages for particle impact noise detection

NASA Technical Reports Server (NTRS)

1977-01-01

A standard calibration method for any particle impact noise detection (PIND) test system used to detect loose particles responsible for failures in hybrid circuits was developed along with a procedure for preparing PIND standard test devices. Hybrid packages were seeded with a single gold ball, hermetically sealed, leak tested, and PIND tested. Conclusions are presented.

A flexible CPW package for a 30 GHz MMIC amplifier. [coplanar waveguide

NASA Technical Reports Server (NTRS)

Simons, Rainee N.; Taub, Susan R.

1992-01-01

A novel package, which consists of a carrier housing, has been developed for monolithic-millimeter wave Integrated Circuit amplifiers which operate at 30 giga-Hz. The carrier has coplanar waveguide (CPW) interconnects and provides heat-sinking, tuning, and cascading capabilities. The housing provides electrical isolation, mechanical protection and a feed-thru for biasing.

Packaging Technology for SiC High Temperature Electronics

NASA Technical Reports Server (NTRS)

Chen, Liang-Yu; Neudeck, Philip G.; Spry, David J.; Meredith, Roger D.; Nakley, Leah M.; Beheim, Glenn M.; Hunter, Gary W.

2017-01-01

High-temperature environment operable sensors and electronics are required for long-term exploration of Venus and distributed control of next generation aeronautical engines. Various silicon carbide (SiC) high temperature sensors, actuators, and electronics have been demonstrated at and above 500 C. A compatible packaging system is essential for long-term testing and application of high temperature electronics and sensors in relevant environments. This talk will discuss a ceramic packaging system developed for high temperature electronics, and related testing results of SiC integrated circuits at 500 C facilitated by this high temperature packaging system, including the most recent progress.

A Basic Research for the Development and Evaluation of Novel MEMS Digital Accelerometers

DTIC Science & Technology

2013-02-01

that timing differences as measured by the circuit are linearly dependent on the measured capacitance changes. As such, the circuit’s readout is...error in the electronic measurement to refine the technique. An additional capability of the circuit is the ability to observe the impact of cold...low resistivity on (ɘ.01 Ω-cm) silicon on insulator wafers (SOI). The beams are fabricated in a 0.3 cm by 0.3 cm die which is then packaged and wire

Changes in electrical and thermal parameters of led packages under different current and heating stresses

NASA Astrophysics Data System (ADS)

Jayawardena, Adikaramge Asiri

The goal of this dissertation is to identify electrical and thermal parameters of an LED package that can be used to predict catastrophic failure real-time in an application. Through an experimental study the series electrical resistance and thermal resistance were identified as good indicators of contact failure of LED packages. This study investigated the long-term changes in series electrical resistance and thermal resistance of LED packages at three different current and junction temperature stress conditions. Experiment results showed that the series electrical resistance went through four phases of change; including periods of latency, rapid increase, saturation, and finally a sharp decline just before failure. Formation of voids in the contact metallization was identified as the underlying mechanism for series resistance increase. The rate of series resistance change was linked to void growth using the theory of electromigration. The rate of increase of series resistance is dependent on temperature and current density. The results indicate that void growth occurred in the cap (Au) layer, was constrained by the contact metal (Ni) layer, preventing open circuit failure of contact metal layer. Short circuit failure occurred due to electromigration induced metal diffusion along dislocations in GaN. The increase in ideality factor, and reverse leakage current with time provided further evidence to presence of metal in the semiconductor. An empirical model was derived for estimation of LED package failure time due to metal diffusion. The model is based on the experimental results and theories of electromigration and diffusion. Furthermore, the experimental results showed that the thermal resistance of LED packages increased with aging time. A relationship between thermal resistance change rate, with case temperature and temperature gradient within the LED package was developed. The results showed that dislocation creep is responsible for creep induced plastic deformation in the die-attach solder. The temperatures inside the LED package reached the melting point of die-attach solder due to delamination just before catastrophic open circuit failure. A combined model that could estimate life of LED packages based on catastrophic failure of thermal and electrical contacts is presented for the first time. This model can be used to make a-priori or real-time estimation of LED package life based on catastrophic failure. Finally, to illustrate the usefulness of the findings from this thesis, two different implementations of real-time life prediction using prognostics and health monitoring techniques are discussed.

CMOS compatible fabrication process of MEMS resonator for timing reference and sensing application

NASA Astrophysics Data System (ADS)

Huynh, Duc H.; Nguyen, Phuong D.; Nguyen, Thanh C.; Skafidas, Stan; Evans, Robin

2015-12-01

Frequency reference and timing control devices are ubiquitous in electronic applications. There is at least one resonator required for each of this device. Currently electromechanical resonators such as crystal resonator, ceramic resonator are the ultimate choices. This tendency will probably keep going for many more years. However, current market demands for small size, low power consumption, cheap and reliable products, has divulged many limitations of this type of resonators. They cannot be integrated into standard CMOS (Complement metaloxide- semiconductor) IC (Integrated Circuit) due to material and fabrication process incompatibility. Currently, these devices are off-chip and they require external circuitries to interface with the ICs. This configuration significantly increases the overall size and cost of the entire electronic system. In addition, extra external connection, especially at high frequency, will potentially create negative impacts on the performance of the entire system due to signal degradation and parasitic effects. Furthermore, due to off-chip packaging nature, these devices are quite expensive, particularly for high frequency and high quality factor devices. To address these issues, researchers have been intensively studying on an alternative for type of resonator by utilizing the new emerging MEMS (Micro-electro-mechanical systems) technology. Recent progress in this field has demonstrated a MEMS resonator with resonant frequency of 2.97 GHz and quality factor (measured in vacuum) of 42900. Despite this great achievement, this prototype is still far from being fully integrated into CMOS system due to incompatibility in fabrication process and its high series motional impedance. On the other hand, fully integrated MEMS resonator had been demonstrated but at lower frequency and quality factor. We propose a design and fabrication process for a low cost, high frequency and a high quality MEMS resonator, which can be integrated into a standard CMOS IC. This device is expected to operate in hundreds of Mhz frequency range; quality factor surpasses 10000 and series motional impedance low enough that could be matching into conventional system without enormous effort. This MEMS resonator can be used in the design of many blocks in wireless and RF (Radio Frequency) systems such as low phase noise oscillator, band pass filter, power amplifier and in many sensing application.

Study of IEMP Effects on IC Operational Amplifier Circuits

DTIC Science & Technology

1975-12-10

plasma focus to study their IEMP responses with and without superposition of TREE responses. The 30-kJ plasma focus device produced photons primarily in the 8- to 100-keV range with pulse widths typically in the range of 10 to 15 nsec. Pulses of electrons were also deposited on the external leads of the operational amplifiers to determine the characteristic responses. These units were operated in circuits with closed-loop gains ranging from 5 to 100. During direct irradiation of the operational amplifiers, it was found that the IEMP responses (caused

Tailoring femtosecond 1.5-μm Bessel beams for manufacturing high-aspect-ratio through-silicon vias

NASA Astrophysics Data System (ADS)

He, Fei; Yu, Junjie; Tan, Yuanxin; Chu, Wei; Zhou, Changhe; Cheng, Ya; Sugioka, Koji

2017-01-01

Three-dimensional integrated circuits (3D ICs) are an attractive replacement for conventional 2D ICs as high-performance, low-power-consumption, and small-footprint microelectronic devices. However, one of the major remaining challenges is the manufacture of high-aspect-ratio through-silicon vias (TSVs), which is a crucial technology for the assembly of 3D Si ICs. Here, we present the fabrication of high-quality TSVs using a femtosecond (fs) 1.5-μm Bessel beam. To eliminate the severe ablation caused by the sidelobes of a conventional Bessel beam, a fs Bessel beam is tailored using a specially designed binary phase plate. We demonstrate that the tailored fs Bessel beam can be used to fabricate a 2D array of approximately ∅10-μm TSVs on a 100-μm-thick Si substrate without any sidelobe damage, suggesting potential application in the 3D assembly of 3D Si ICs.

Tailoring femtosecond 1.5-μm Bessel beams for manufacturing high-aspect-ratio through-silicon vias.

PubMed

He, Fei; Yu, Junjie; Tan, Yuanxin; Chu, Wei; Zhou, Changhe; Cheng, Ya; Sugioka, Koji

2017-01-18

Three-dimensional integrated circuits (3D ICs) are an attractive replacement for conventional 2D ICs as high-performance, low-power-consumption, and small-footprint microelectronic devices. However, one of the major remaining challenges is the manufacture of high-aspect-ratio through-silicon vias (TSVs), which is a crucial technology for the assembly of 3D Si ICs. Here, we present the fabrication of high-quality TSVs using a femtosecond (fs) 1.5-μm Bessel beam. To eliminate the severe ablation caused by the sidelobes of a conventional Bessel beam, a fs Bessel beam is tailored using a specially designed binary phase plate. We demonstrate that the tailored fs Bessel beam can be used to fabricate a 2D array of approximately ∅10-μm TSVs on a 100-μm-thick Si substrate without any sidelobe damage, suggesting potential application in the 3D assembly of 3D Si ICs.

Fibre Optic Connections And Method For Using Same

DOEpatents

Chan, Benson; Cohen, Mitchell S.; Fortier, Paul F.; Freitag, Ladd W.; Hall, Richard R.; Johnson, Glen W.; Lin, How Tzu; Sherman, John H.

2004-03-30

A package is described that couples a twelve channel wide fiber optic cable to a twelve channel Vertical Cavity Surface Emitting Laser (VCSEL) transmitter and a multiple channel Perpendicularly Aligned Integrated Die (PAID) receiver. The package allows for reduction in the height of the assembly package by vertically orienting certain dies parallel to the fiber optic cable and horizontally orienting certain other dies. The assembly allows the vertically oriented optoelectronic dies to be perpendicularly attached to the horizontally oriented laminate via a flexible circuit.

Make Your Own Digital Thermometer!

ERIC Educational Resources Information Center

Sorey, Timothy; Willard, Teri; Kim, Bom

2010-01-01

In the hands-on, guided-inquiry lesson presented in this article, high school students create, calibrate, and apply an affordable scientific-grade instrument (Lapp and Cyrus 2000). In just four class periods, they build a homemade integrated circuit (IC) digital thermometer, apply a math model to calibrate their instrument, and ask a researchable…

Printed stretchable circuit on soft elastic substrate for wearable application

NASA Astrophysics Data System (ADS)

Yuan, Wei; Wu, Xinzhou; Gu, Weibing; Lin, Jian; Cui, Zheng

2018-01-01

In this paper, a flexible and stretchable circuit has been fabricated by the printing method based on Ag NWs/PDMS composite. The randomly oriented Ag NWs were buried in PDMS to form a conductive and stretchable electrode. Stable conductivity was achieved with a large range of tensile strain (0-50%) after the initial stretching/releasing cycle. The stable electrical response is due to the buckling of the Ag NWs/PDMS composite layer. Furthermore, printed stretchable circuits integrated with commercial ICs have been demonstrated for wearable applications. Project supported by the National Program on Key Basic Research Project (No. 2015CB351901), the Strategic Priority Research Program of the Chinese Academy of Sciences (No. XDA09020201), and the National Science Foundation of China (Nos. 51603227, 51603228).

Charge Yield at Low Electric Fields: Considerations for Bipolar Integrated Circuits

NASA Technical Reports Server (NTRS)

Johnston, A. H.; Swimm, R. T.; Thorbourn, D. O.

2013-01-01

A significant reduction in total dose damage is observed when bipolar integrated circuits are irradiated at low temperature. This can be partially explained by the Onsager theory of recombination, which predicts a strong temperature dependence for charge yield under low-field conditions. Reduced damage occurs for biased as well as unbiased devices because the weak fringing field in thick bipolar oxides only affects charge yield near the Si/SiO2 interface, a relatively small fraction of the total oxide thickness. Lowering the temperature of bipolar ICs - either continuously, or for time periods when they are exposed to high radiation levels - provides an additional degree of freedom to improve total dose performance of bipolar circuits, particularly in space applications.

Field Programmable Gate Array Reliability Analysis Guidelines for Launch Vehicle Reliability Block Diagrams

NASA Technical Reports Server (NTRS)

Al Hassan, Mohammad; Britton, Paul; Hatfield, Glen Spencer; Novack, Steven D.

2017-01-01

Field Programmable Gate Arrays (FPGAs) integrated circuits (IC) are one of the key electronic components in today's sophisticated launch and space vehicle complex avionic systems, largely due to their superb reprogrammable and reconfigurable capabilities combined with relatively low non-recurring engineering costs (NRE) and short design cycle. Consequently, FPGAs are prevalent ICs in communication protocols and control signal commands. This paper will identify reliability concerns and high level guidelines to estimate FPGA total failure rates in a launch vehicle application. The paper will discuss hardware, hardware description language, and radiation induced failures. The hardware contribution of the approach accounts for physical failures of the IC. The hardware description language portion will discuss the high level FPGA programming languages and software/code reliability growth. The radiation portion will discuss FPGA susceptibility to space environment radiation.

Field Programmable Gate Array Failure Rate Estimation Guidelines for Launch Vehicle Fault Tree Models

NASA Technical Reports Server (NTRS)

Al Hassan, Mohammad; Novack, Steven D.; Hatfield, Glen S.; Britton, Paul

2017-01-01

Today's launch vehicles complex electronic and avionic systems heavily utilize the Field Programmable Gate Array (FPGA) integrated circuit (IC). FPGAs are prevalent ICs in communication protocols such as MIL-STD-1553B, and in control signal commands such as in solenoid/servo valves actuations. This paper will demonstrate guidelines to estimate FPGA failure rates for a launch vehicle, the guidelines will account for hardware, firmware, and radiation induced failures. The hardware contribution of the approach accounts for physical failures of the IC, FPGA memory and clock. The firmware portion will provide guidelines on the high level FPGA programming language and ways to account for software/code reliability growth. The radiation portion will provide guidelines on environment susceptibility as well as guidelines on tailoring other launch vehicle programs historical data to a specific launch vehicle.

Space station power semiconductor package

NASA Technical Reports Server (NTRS)

Balodis, Vilnis; Berman, Albert; Devance, Darrell; Ludlow, Gerry; Wagner, Lee

1987-01-01

A package of high-power switching semiconductors for the space station have been designed and fabricated. The package includes a high-voltage (600 volts) high current (50 amps) NPN Fast Switching Power Transistor and a high-voltage (1200 volts), high-current (50 amps) Fast Recovery Diode. The package features an isolated collector for the transistors and an isolated anode for the diode. Beryllia is used as the isolation material resulting in a thermal resistance for both devices of .2 degrees per watt. Additional features include a hermetical seal for long life -- greater than 10 years in a space environment. Also, the package design resulted in a low electrical energy loss with the reduction of eddy currents, stray inductances, circuit inductance, and capacitance. The required package design and device parameters have been achieved. Test results for the transistor and diode utilizing the space station package is given.

Toward printed integrated circuits based on unipolar or ambipolar polymer semiconductors.

PubMed

Baeg, Kang-Jun; Caironi, Mario; Noh, Yong-Young

2013-08-21

For at least the past ten years printed electronics has promised to revolutionize our daily life by making cost-effective electronic circuits and sensors available through mass production techniques, for their ubiquitous applications in wearable components, rollable and conformable devices, and point-of-care applications. While passive components, such as conductors, resistors and capacitors, had already been fabricated by printing techniques at industrial scale, printing processes have been struggling to meet the requirements for mass-produced electronics and optoelectronics applications despite their great potential. In the case of logic integrated circuits (ICs), which constitute the focus of this Progress Report, the main limitations have been represented by the need of suitable functional inks, mainly high-mobility printable semiconductors and low sintering temperature conducting inks, and evoluted printing tools capable of higher resolution, registration and uniformity than needed in the conventional graphic arts printing sector. Solution-processable polymeric semiconductors are the best candidates to fulfill the requirements for printed logic ICs on flexible substrates, due to their superior processability, ease of tuning of their rheology parameters, and mechanical properties. One of the strongest limitations has been mainly represented by the low charge carrier mobility (μ) achievable with polymeric, organic field-effect transistors (OFETs). However, recently unprecedented values of μ ∼ 10 cm(2) /Vs have been achieved with solution-processed polymer based OFETs, a value competing with mobilities reported in organic single-crystals and exceeding the performances enabled by amorphous silicon (a-Si). Interestingly these values were achieved thanks to the design and synthesis of donor-acceptor copolymers, showing limited degree of order when processed in thin films and therefore fostering further studies on the reason leading to such improved charge transport properties. Among this class of materials, various polymers can show well balanced electrons and holes mobility, therefore being indicated as ambipolar semiconductors, good environmental stability, and a small band-gap, which simplifies the tuning of charge injection. This opened up the possibility of taking advantage of the superior performances offered by complementary "CMOS-like" logic for the design of digital ICs, easing the scaling down of critical geometrical features, and achieving higher complexity from robust single gates (e.g., inverters) and test circuits (e.g., ring oscillators) to more complete circuits. Here, we review the recent progress in the development of printed ICs based on polymeric semiconductors suitable for large-volume micro- and nano-electronics applications. Particular attention is paid to the strategies proposed in the literature to design and synthesize high mobility polymers and to develop suitable printing tools and techniques to allow for improved patterning capability required for the down-scaling of devices in order to achieve the operation frequencies needed for applications, such as flexible radio-frequency identification (RFID) tags, near-field communication (NFC) devices, ambient electronics, and portable flexible displays. Copyright © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Truck circuits diagnosis for railway lines equipped with an automatic block signalling system

NASA Astrophysics Data System (ADS)

Spunei, E.; Piroi, I.; Muscai, C.; Răduca, E.; Piroi, F.

2018-01-01

This work presents a diagnosis method for detecting track circuits failures on a railway traffic line equipped with an Automatic Block Signalling installation. The diagnosis method uses the installation’s electrical schemas, based on which a series of diagnosis charts have been created. Further, the diagnosis charts were used to develop a software package, CDCBla, which substantially contributes to reducing the diagnosis time and human error during failure remedies. The proposed method can also be used as a training package for the maintenance staff. Since the diagnosis method here does not need signal or measurement inputs, using it does not necessitate additional IT knowledge and can be deployed on a mobile computing device (tablet, smart phone).

Packaging Technologies for 500C SiC Electronics and Sensors

NASA Technical Reports Server (NTRS)

Chen, Liang-Yu

2013-01-01

Various SiC electronics and sensors are currently under development for applications in 500C high temperature environments such as hot sections of aerospace engines and the surface of Venus. In order to conduct long-term test and eventually commercialize these SiC devices, compatible packaging technologies for the SiC electronics and sensors are required. This presentation reviews packaging technologies developed for 500C SiC electronics and sensors to address both component and subsystem level packaging needs for high temperature environments. The packaging system for high temperature SiC electronics includes ceramic chip-level packages, ceramic printed circuit boards (PCBs), and edge-connectors. High temperature durable die-attach and precious metal wire-bonding are used in the chip-level packaging process. A high temperature sensor package is specifically designed to address high temperature micro-fabricated capacitive pressure sensors for high differential pressure environments. This presentation describes development of these electronics and sensor packaging technologies, including some testing results of SiC electronics and capacitive pressure sensors using these packaging technologies.

HEMT Amplifiers and Equipment for their On-Wafer Testing

NASA Technical Reports Server (NTRS)

Fung, King man; Gaier, Todd; Samoska, Lorene; Deal, William; Radisic, Vesna; Mei, Xiaobing; Lai, Richard

2008-01-01

Power amplifiers comprising InP-based high-electron-mobility transistors (HEMTs) in coplanar-waveguide (CPW) circuits designed for operation at frequencies of hundreds of gigahertz, and a test set for onwafer measurement of their power levels have been developed. These amplifiers utilize an advanced 35-nm HEMT monolithic microwave integrated-circuit (MMIC) technology and have potential utility as local-oscillator drivers and power sources in future submillimeter-wavelength heterodyne receivers and imaging systems. The test set can reduce development time by enabling rapid output power characterization, not only of these and similar amplifiers, but also of other coplanar-waveguide power circuits, without the necessity of packaging the circuits.

The instrument control software package for the Habitable-Zone Planet Finder spectrometer

NASA Astrophysics Data System (ADS)

Bender, Chad F.; Robertson, Paul; Stefansson, Gudmundur Kari; Monson, Andrew; Anderson, Tyler; Halverson, Samuel; Hearty, Frederick; Levi, Eric; Mahadevan, Suvrath; Nelson, Matthew; Ramsey, Larry; Roy, Arpita; Schwab, Christian; Shetrone, Matthew; Terrien, Ryan

2016-08-01

We describe the Instrument Control Software (ICS) package that we have built for The Habitable-Zone Planet Finder (HPF) spectrometer. The ICS controls and monitors instrument subsystems, facilitates communication with the Hobby-Eberly Telescope facility, and provides user interfaces for observers and telescope operators. The backend is built around the asynchronous network software stack provided by the Python Twisted engine, and is linked to a suite of custom hardware communication protocols. This backend is accessed through Python-based command-line and PyQt graphical frontends. In this paper we describe several of the customized subsystem communication protocols that provide access to and help maintain the hardware systems that comprise HPF, and show how asynchronous communication benefits the numerous hardware components. We also discuss our Detector Control Subsystem, built as a set of custom Python wrappers around a C-library that provides native Linux access to the SIDECAR ASIC and Hawaii-2RG detector system used by HPF. HPF will be one of the first astronomical instruments on sky to utilize this native Linux capability through the SIDECAR Acquisition Module (SAM) electronics. The ICS we have created is very flexible, and we are adapting it for NEID, NASA's Extreme Precision Doppler Spectrometer for the WIYN telescope; we will describe this adaptation, and describe the potential for use in other astronomical instruments.

A novel multi-actuation CMOS RF MEMS switch

NASA Astrophysics Data System (ADS)

Lee, Chiung-I.; Ko, Chih-Hsiang; Huang, Tsun-Che

2008-12-01

This paper demonstrates a capacitive shunt type RF MEMS switch, which is actuated by electro-thermal actuator and electrostatic actuator at the same time, and than latching the switching status by electrostatic force only. Since thermal actuators need relative low voltage compare to electrostatic actuators, and electrostatic force needs almost no power to maintain the switching status, the benefits of the mechanism are very low actuation voltage and low power consumption. Moreover, the RF MEMS switch has considered issues for integrated circuit compatible in design phase. So the switch is fabricated by a standard 0.35um 2P4M CMOS process and uses wet etching and dry etching technologies for postprocess. This compatible ability is important because the RF characteristics are not only related to the device itself. If a packaged RF switch and a packaged IC wired together, the parasitic capacitance will cause the problem for optimization. The structure of the switch consists of a set of CPW transmission lines and a suspended membrane. The CPW lines and the membrane are in metal layers of CMOS process. Besides, the electro-thermal actuators are designed by polysilicon layer of the CMOS process. So the RF switch is only CMOS process layers needed for both electro-thermal and electrostatic actuations in switch. The thermal actuator is composed of a three-dimensional membrane and two heaters. The membrane is a stacked step structure including two metal layers in CMOS process, and heat is generated by poly silicon resistors near the anchors of membrane. Measured results show that the actuation voltage of the switch is under 7V for electro-thermal added electrostatic actuation.

Effectiveness of X-ray grating interferometry for non-destructive inspection of packaged devices

NASA Astrophysics Data System (ADS)

Uehara, Masato; Yashiro, Wataru; Momose, Atsushi

2013-10-01

It is difficult to inspect packaged devices such as IC packages and power modules because the devices contain various components, such as semiconductors, metals, ceramics, and resin. In this paper, we demonstrated the effectiveness of X-ray grating interferometry (XGI) using a laboratory X-ray tube for the industrial inspection of packaged devices. The obtained conventional absorption image showed heavy-elemental components such as metal wires and electrodes, but the image did not reveal the defects in the light-elemental components. On the other hand, the differential phase-contrast image obtained by XGI revealed microvoids and scars in the encapsulant of the samples. The visibility contrast image also obtained by XGI showed some cracks in the ceramic insulator of power module sample. In addition, the image showed the silicon plate surrounded by the encapsulant having the same X-ray absorption coefficient. While these defects and components are invisible in the conventional industrial X-ray imaging, XGI thus has an attractive potential for the industrial inspection of the packaged devices.

Integrated circuit-based instrumentation for microchip capillary electrophoresis.

PubMed

Behnam, M; Kaigala, G V; Khorasani, M; Martel, S; Elliott, D G; Backhouse, C J

2010-09-01

Although electrophoresis with laser-induced fluorescence (LIF) detection has tremendous potential in lab on chip-based point-of-care disease diagnostics, the wider use of microchip electrophoresis has been limited by the size and cost of the instrumentation. To address this challenge, the authors designed an integrated circuit (IC, i.e. a microelectronic chip, with total silicon area of <0.25 cm2, less than 5 mmx5 mm, and power consumption of 28 mW), which, with a minimal additional infrastructure, can perform microchip electrophoresis with LIF detection. The present work enables extremely compact and inexpensive portable systems consisting of one or more complementary metal-oxide-semiconductor (CMOS) chips and several other low-cost components. There are, to the authors' knowledge, no other reports of a CMOS-based LIF capillary electrophoresis instrument (i.e. high voltage generation, switching, control and interface circuit combined with LIF detection). This instrument is powered and controlled using a universal serial bus (USB) interface to a laptop computer. The authors demonstrate this IC in various configurations and can readily analyse the DNA produced by a standard medical diagnostic protocol (end-labelled polymerase chain reaction (PCR) product) with a limit of detection of approximately 1 ng/microl (approximately 1 ng of total DNA). The authors believe that this approach may ultimately enable lab-on-a-chip-based electrophoretic instruments that cost on the order of several dollars.

Low-Power Analog Processing for Sensing Applications: Low-Frequency Harmonic Signal Classification

PubMed Central

White, Daniel J.; William, Peter E.; Hoffman, Michael W.; Balkir, Sina

2013-01-01

A low-power analog sensor front-end is described that reduces the energy required to extract environmental sensing spectral features without using Fast Fouriér Transform (FFT) or wavelet transforms. An Analog Harmonic Transform (AHT) allows selection of only the features needed by the back-end, in contrast to the FFT, where all coefficients must be calculated simultaneously. We also show that the FFT coefficients can be easily calculated from the AHT results by a simple back-substitution. The scheme is tailored for low-power, parallel analog implementation in an integrated circuit (IC). Two different applications are tested with an ideal front-end model and compared to existing studies with the same data sets. Results from the military vehicle classification and identification of machine-bearing fault applications shows that the front-end suits a wide range of harmonic signal sources. Analog-related errors are modeled to evaluate the feasibility of and to set design parameters for an IC implementation to maintain good system-level performance. Design of a preliminary transistor-level integrator circuit in a 0.13 μm complementary metal-oxide-silicon (CMOS) integrated circuit process showed the ability to use online self-calibration to reduce fabrication errors to a sufficiently low level. Estimated power dissipation is about three orders of magnitude less than similar vehicle classification systems that use commercially available FFT spectral extraction. PMID:23892765

Improved Signal Chains for Readout of CMOS Imagers

NASA Technical Reports Server (NTRS)

Pain, Bedabrata; Hancock, Bruce; Cunningham, Thomas

2009-01-01

An improved generic design has been devised for implementing signal chains involved in readout from complementary metal oxide/semiconductor (CMOS) image sensors and for other readout integrated circuits (ICs) that perform equivalent functions. The design applies to any such IC in which output signal charges from the pixels in a given row are transferred simultaneously into sampling capacitors at the bottoms of the columns, then voltages representing individual pixel charges are read out in sequence by sequentially turning on column-selecting field-effect transistors (FETs) in synchronism with source-follower- or operational-amplifier-based amplifier circuits. The improved design affords the best features of prior source-follower-and operational- amplifier-based designs while overcoming the major limitations of those designs. The limitations can be summarized as follows: a) For a source-follower-based signal chain, the ohmic voltage drop associated with DC bias current flowing through the column-selection FET causes unacceptable voltage offset, nonlinearity, and reduced small-signal gain. b) For an operational-amplifier-based signal chain, the required bias current and the output noise increase superlinearly with size of the pixel array because of a corresponding increase in the effective capacitance of the row bus used to couple the sampled column charges to the operational amplifier. The effect of the bus capacitance is to simultaneously slow down the readout circuit and increase noise through the Miller effect.

Experimental Verification of the Use of Metal Filled Via Hole Fences for Crosstalk Control of Microstrip Lines in LTCC Packages

NASA Technical Reports Server (NTRS)

Ponchak, George E.; Chun, Donghoon; Katehi, Linda P. B.; Yook, Jong-Gwan

1999-01-01

Coupling between microstrip lines in dense RF packages is a common problem that degrades circuit performance. Prior 3D-FEM electromagnetic simulations have shown that metal filled via hole fences between two adjacent microstrip lines actually increases coupling between the lines; however, if the top of the via posts are connected by a metal Strip, coupling is reduced. In this paper, experimental verification of the 3D-FEM simulations Is demonstrated for commercially fabricated LTCC packages.

Oxygen ion-beam microlithography

DOEpatents

Tsuo, Y.S.

1991-08-20

A method of providing and developing a resist on a substrate for constructing integrated circuit (IC) chips includes the following steps: of depositing a thin film of amorphous silicon or hydrogenated amorphous silicon on the substrate and exposing portions of the amorphous silicon to low-energy oxygen ion beams to oxidize the amorphous silicon at those selected portions. The nonoxidized portions are then removed by etching with RF-excited hydrogen plasma. Components of the IC chip can then be constructed through the removed portions of the resist. The entire process can be performed in an in-line vacuum production system having several vacuum chambers. Nitrogen or carbon ion beams can also be used. 5 figures.

Solar cell and I.C. aspects of ingot-to-slice mechanical processing

NASA Astrophysics Data System (ADS)

Dyer, L. D.

1985-08-01

Intensive efforts have been put into the growth of silicon crystals to suit today's solar cell and integrated circuit requirements. Each step of processing the crystal must also receive concentrated attention to preserve the grown-in perfection and to provide a suitable device-ready wafer at reasonable cost. A comparison is made between solar cell and I.C. requirements on the mechanical processing of silicon from ingot to wafer. Specific defects are described that can ruin the slice or can possibly lead to device degradation. These include grinding cracks, saw exit chips, crow's-foot fractures, edge cracks, and handling scratches.

Solar cell and I.C. aspects of ingot-to-slice mechanical processing

NASA Technical Reports Server (NTRS)

Dyer, L. D.

1985-01-01

Intensive efforts have been put into the growth of silicon crystals to suit today's solar cell and integrated circuit requirements. Each step of processing the crystal must also receive concentrated attention to preserve the grown-in perfection and to provide a suitable device-ready wafer at reasonable cost. A comparison is made between solar cell and I.C. requirements on the mechanical processing of silicon from ingot to wafer. Specific defects are described that can ruin the slice or can possibly lead to device degradation. These include grinding cracks, saw exit chips, crow's-foot fractures, edge cracks, and handling scratches.

Oxygen ion-beam microlithography

DOEpatents

Tsuo, Y. Simon

1991-01-01

A method of providing and developing a resist on a substrate for constructing integrated circuit (IC) chips includes the following steps: of depositing a thin film of amorphous silicon or hydrogenated amorphous silicon on the substrate and exposing portions of the amorphous silicon to low-energy oxygen ion beams to oxidize the amorphous silicon at those selected portions. The nonoxidized portions are then removed by etching with RF-excited hydrogen plasma. Components of the IC chip can then be constructed through the removed portions of the resist. The entire process can be performed in an in-line vacuum production system having several vacuum chambers. Nitrogen or carbon ion beams can also be used.

Military Curricula for Vocational & Technical Education. Basic Electricity and Electronics. CANTRAC A-100-0010. Module 34: Linear Integrated Circuits. Study Booklet.

ERIC Educational Resources Information Center

Chief of Naval Education and Training Support, Pensacola, FL.

This individualized learning module on linear integrated circuits is one in a series of modules for a course in basic electricity and electronics. The course is one of a number of military-developed curriculum packages selected for adaptation to vocational instructional and curriculum development in a civilian setting. Two lessons are included in…

Using the Arduino with MakerPlot software for the display of resonance curves characterisic of a series LCR circuit

NASA Astrophysics Data System (ADS)

Atkin, Keith

2016-11-01

This paper shows how very simple circuitry attached to an Arduino microcontroller can be used for the measurement of both frequency and amplitude of a sinusoidal signal. It is also shown how the addition of a readily available software package, MakerPlot, can facilitate the display and investigation of resonance curves for a series LCR circuit.

The use of hybrid integrated circuit techniques in biotelemetry applications

NASA Technical Reports Server (NTRS)

Fryer, T. B.

1977-01-01

A review is presented of some features of hybrid integrated circuits that make their use advantageous in miniature biotelemetry applications. The various techniques for fabricating resistors, capacitors and interconnections by both thin film and thick film technology are discussed. The use of chip capacitors, resistors, and especially standard IC chips on substrates with fired-on interconnection patterns is emphasized. The review is designed primarily to acquaint biotelemetry users and designers with an overview of this fabrication technique so that they can better communicate their needs with an understanding of its limitations and advantages to facilities specializing in hybrid construction.

Dielectric Spectroscopic Detection of Early Failures in 3-D Integrated Circuits.

PubMed

Obeng, Yaw; Okoro, C A; Ahn, Jung-Joon; You, Lin; Kopanski, Joseph J

The commercial introduction of three dimensional integrated circuits (3D-ICs) has been hindered by reliability challenges, such as stress related failures, resistivity changes, and unexplained early failures. In this paper, we discuss a new RF-based metrology, based on dielectric spectroscopy, for detecting and characterizing electrically active defects in fully integrated 3D devices. These defects are traceable to the chemistry of the insolation dielectrics used in the through silicon via (TSV) construction. We show that these defects may be responsible for some of the unexplained early reliability failures observed in TSV enabled 3D devices.

Christmas Light Display

NASA Astrophysics Data System (ADS)

Ross, Arthur; Renfro, Timothy

2012-03-01

The Digital Electronics class at McMurry University created a Christmas light display that toggles the power of different strands of lights, according to what frequencies are played in a song, as an example of an analog to digital circuit. This was accomplished using a BA3830S IC six-band audio filter and six solid-state relays.

An Electrifying Quiz! Constructing a Printed-Circuit Board Quiz Game

ERIC Educational Resources Information Center

Calhoun, Michael J.

2005-01-01

Laptop computers, cell phones and the Apple iPod all contain transistors, IC chips, capacitors, and other electronic components. To the general public--and especially students in upper elementary and middle school grades--these components are most often very mysterious items. Yet, it is at elementary and middle school levels that scientists and…

Microwave evaluation of electromigration susceptibility in advanced interconnects

NASA Astrophysics Data System (ADS)

Sunday, Christopher E.; Veksler, Dmitry; Cheung, Kin C.; Obeng, Yaw S.

2017-11-01

Traditional metrology has been unable to adequately address the needs of the emerging integrated circuits (ICs) at the nano scale; thus, new metrology and techniques are needed. For example, the reliability challenges in fabrication need to be well understood and controlled to facilitate mass production of through-substrate-via (TSV) enabled three-dimensional integrated circuits (3D-ICs). This requires new approaches to the metrology. In this paper, we use the microwave propagation characteristics to study the reliability issues that precede the physical damage caused by electromigration in the Cu-filled TSVs. The pre-failure microwave insertion losses and group delay are dependent on both the device temperature and the amount of current forced through the devices-under-test. The microwave insertion losses increase with the increase in the test temperature, while the group delay increases with the increase in the forced direct current magnitude. The microwave insertion losses are attributed to the defect mobility at the Cu-TiN interface, and the group delay changes are due to resistive heating in the interconnects, which perturbs the dielectric properties of the cladding dielectrics of the copper fill in the TSVs.

Active C4 Electrodes for Local Field Potential Recording Applications

PubMed Central

Wang, Lu; Freedman, David; Sahin, Mesut; Ünlü, M. Selim; Knepper, Ronald

2016-01-01

Extracellular neural recording, with multi-electrode arrays (MEAs), is a powerful method used to study neural function at the network level. However, in a high density array, it can be costly and time consuming to integrate the active circuit with the expensive electrodes. In this paper, we present a 4 mm × 4 mm neural recording integrated circuit (IC) chip, utilizing IBM C4 bumps as recording electrodes, which enable a seamless active chip and electrode integration. The IC chip was designed and fabricated in a 0.13 μm BiCMOS process for both in vitro and in vivo applications. It has an input-referred noise of 4.6 μVrms for the bandwidth of 10 Hz to 10 kHz and a power dissipation of 11.25 mW at 2.5 V, or 43.9 μW per input channel. This prototype is scalable for implementing larger number and higher density electrode arrays. To validate the functionality of the chip, electrical testing results and acute in vivo recordings from a rat barrel cortex are presented. PMID:26861324

Package architecture and component design for an implanted neural stimulator with closed loop control.

PubMed

Bjune, Caroline K; Marinis, Thomas F; Brady, Jeanne M; Moran, James; Wheeler, Jesse; Sriram, Tirunelveli S; Parks, Philip D; Widge, Alik S; Dougherty, Darin D; Eskandar, Emad N

2015-08-01

An implanted neural stimulator with closed loop control requires electrodes for stimulation pulses and recording neuron activity. Our system features arrays of 64 electrodes. Each electrode can be addressed through a cross bar switch, to enable it to be used for stimulation or recording. This electrode switch, a bank of low noise amplifiers with an integrated analog to digital converter, power conditioning electronics, and a communications and control gate array are co-located with the electrode array in a 14 millimeter diameter satellite package that is designed to be flush mounted in a skull burr hole. Our system features five satellite packages connected to a central hub processor-controller via ten conductor cables that terminate in a custom designed, miniaturized connector. The connector incorporates features of high reliability, military grade devices and utilizes three distinct seals to isolate the contacts from fluid permeation. The hub system is comprised of a connector header, hermetic electronics package, and rechargeable battery pack, which are mounted on and electrically interconnected by a flexible circuit board. The assembly is over molded with a compliant silicone rubber. The electronics package contains two antennas, a large coil, used for recharging the battery and a high bandwidth antenna that is used to download data and update software. The package is assembled from two machined alumina pieces, a flat base with brazed in, electrical feed through pins and a rectangular cover with rounded corners. Titanium seal rings are brazed onto these two pieces so that they can be sealed by laser welding. A third system antenna is incorporated in the flexible circuit board. It is used to communicate with an externally worn control package, which monitors the health of the system and allows both the user and clinician to control or modify various system function parameters.

A Suprachoroidal Electrical Retinal Stimulator Design for Long-Term Animal Experiments and In Vivo Assessment of Its Feasibility and Biocompatibility in Rabbits

PubMed Central

Zhou, J. A.; Woo, S. J.; Park, S. I.; Kim, E. T.; Seo, J. M.; Chung, H.; Kim, S. J.

2008-01-01

This article reports on a retinal stimulation system for long-term use in animal electrical stimulation experiments. The presented system consisted of an implantable stimulator which provided continuous electrical stimulation, and an external component which provided preset stimulation patterns and power to the implanted stimulator via a paired radio frequency (RF) coil. A rechargeable internal battery and a parameter memory component were introduced to the implanted retinal stimulator. As a result, the external component was not necessary during the stimulation mode. The inductive coil pair was used to pass the parameter data and to recharge the battery. A switch circuit was used to separate the stimulation mode from the battery recharging mode. The implantable stimulator was implemented with IC chips and the electronics, except for the stimulation electrodes, were hermetically packaged in a biocompatible metal case. A polyimide-based gold electrode array was used. Surgical implantation into rabbits was performed to verify the functionality and safety of this newly designed system. The electrodes were implanted in the suprachoroidal space. Evoked cortical potentials were recorded during electrical stimulation of the retina. Long-term follow-up using OCT showed no chorioretinal abnormality after implantation of the electrodes. PMID:18317521

A low-power RFID integrated circuits for intelligent healthcare systems.

PubMed

Lee, Shuenn-Yuh; Wang, Liang-Hung; Fang, Qiang

2010-11-01

This paper presents low-power radio-frequency identification (RFID) technology for intelligent healthcare systems. With attention to power-efficient communication in the body sensor network, RF power transfer was estimated and the required low-power ICs, which are important in the development of a healthcare system with miniaturization and system integration, are discussed based on the RFID platform. To analyze the power transformation, this paper adopts a 915-MHz industrial, scientific, and medical RF with a radiation power of 70 mW to estimate the power loss under the 1-m communication distance between an RFID reader (bioinformation node) and a transponder (biosignal acquisition nodes). The low-power ICs of the transponder will be implemented in the TSMC 0.18-μm CMOS process. The simulation result reveals that the transponder's IC can fit in with the link budget of the UHF RFID system.

Realization of MEMS-IC Vertical Integration Utilizing Smart Bumpless Bonding

NASA Astrophysics Data System (ADS)

Shiozaki, Masayoshi; Moriguchi, Makoto; Sasaki, Sho; Oba, Masatoshi

This paper reports fundamental technologies, properties, and new experimental results of SBB (Smart Bumpless Bonding) to realize MEMS-IC vertical integration. Although conventional bonding technologies have had difficulties integrating MEMS and its processing circuit because of their rough bonding surfaces, fragile structures, and thermal restriction, SBB technology realized the vertical integration without thermal treatment, any adhesive materials including bumps, and chemical mechanical polishing. The SBB technology bonds sealing parts for vacuum sealing and electrodes for electrical connection simultaneously as published in previous experimental study. The plasma CVD SiO2 is utilized to realize vacuum sealing as sealing material. And Au projection studs are formed on each electrode and connected electrically between two wafers by compressive plastic deformation and surface activation. In this paper, new experimental results including vacuum sealing properties, electrical improvement, IC bonding results on the described fundamental concept and properties are reported.

All optical programmable logic array (PLA)

NASA Astrophysics Data System (ADS)

Hiluf, Dawit

2018-03-01

A programmable logic array (PLA) is an integrated circuit (IC) logic device that can be reconfigured to implement various kinds of combinational logic circuits. The device has a number of AND and OR gates which are linked together to give output or further combined with more gates or logic circuits. This work presents the realization of PLAs via the physics of a three level system interacting with light. A programmable logic array is designed such that a number of different logical functions can be combined as a sum-of-product or product-of-sum form. We present an all optical PLAs with the aid of laser light and observables of quantum systems, where encoded information can be considered as memory chip. The dynamics of the physical system is investigated using Lie algebra approach.

Porous Diblock Copolymer Thin Films in High-Performance Semiconductor Microelectronics

DOE Office of Scientific and Technical Information (OSTI.GOV)

Black, C.T.

2011-02-01

The engine fueling more than 40 years of performance improvements in semiconductor integrated circuits (ICs) has been industry's ability to pattern circuit elements at ever-higher resolution and with ever-greater precision. Steady advances in photolithography - the process wherein ultraviolet light chemically changes a photosensitive polymer resist material in order to create a latent image - have resulted in scaling of minimum printed feature sizes from tens of microns during the 1980s to sub-50 nanometer transistor gate lengths in today's state-of-the-art ICs. The history of semiconductor technology scaling as well as future technology requirements is documented in the International Technology Roadmapmore » for Semiconductors (ITRS). The progression of the semiconductor industry to the realm of nanometer-scale sizes has brought enormous challenges to device and circuit fabrication, rendering performance improvements by conventional scaling alone increasingly difficult. Most often this discussion is couched in terms of field effect transistor (FET) feature sizes such as the gate length or gate oxide thickness, however these challenges extend to many other aspects of the IC, including interconnect dimensions and pitch, device packing density, power consumption, and heat dissipation. The ITRS Technology Roadmap forecasts a difficult set of scientific and engineering challenges with no presently-known solutions. The primary focus of this chapter is the research performed at IBM on diblock copolymer films composed of polystyrene (PS) and poly(methyl-methacrylate) (PMMA) (PS-b-PMMA) with total molecular weights M{sub n} in the range of {approx}60K (g/mol) and polydispersities (PD) of {approx}1.1. These materials self assemble to form patterns having feature sizes in the range of 15-20nm. PS-b-PMMA was selected as a self-assembling patterning material due to its compatibility with the semiconductor microelectronics manufacturing infrastructure, as well as the significant body of existing research on understanding its material properties.« less

An NFC-Enabled CMOS IC for a Wireless Fully Implantable Glucose Sensor.

PubMed

DeHennis, Andrew; Getzlaff, Stefan; Grice, David; Mailand, Marko

2016-01-01

This paper presents an integrated circuit (IC) that merges integrated optical and temperature transducers, optical interface circuitry, and a near-field communication (NFC)-enabled digital, wireless readout for a fully passive implantable sensor platform to measure glucose in people with diabetes. A flip-chip mounted LED and monolithically integrated photodiodes serve as the transduction front-end to enable fluorescence readout. A wide-range programmable transimpedance amplifier adapts the sensor signals to the input of an 11-bit analog-to-digital converter digitizing the measurements. Measurement readout is enabled by means of wireless backscatter modulation to a remote NFC reader. The system is able to resolve current levels of less than 10 pA with a single fluorescent measurement energy consumption of less than 1 μJ. The wireless IC is fabricated in a 0.6-μm-CMOS process and utilizes a 13.56-MHz-based ISO15693 for passive wireless readout through a NFC interface. The IC is utilized as the core interface to a fluorescent, glucose transducer to enable a fully implantable sensor-based continuous glucose monitoring system.

Robust, High-Speed Network Design for Large-Scale Multiprocessing

DTIC Science & Technology

1993-09-01

3.17 Left: Non-expansive Wiring of Processors to First Stage Routing Elements . ... 38 3.18 Right: Expansive Wiring of Processors to First Stage...162 8.2 RNI Micro -architecture ........ .............................. 163 8.3 Packaged RN I IC...169 11.1 MLUNK Message Formats ........ .............................. 173 12.1 Routing Board Arrangement for 64- processor Machine

Automotive Stirling engine development program

NASA Technical Reports Server (NTRS)

Ernst, W.; Richey, A.; Farrell, R.; Riecke, G.; Smith, G.; Howarth, R.; Cronin, M.; Simetkosky, M.; Meacher, J.

1986-01-01

The major accomplishments were the completion of the Basic Stirling Engine (BSE) and the Stirling Engine System (SES) designs on schedule, the approval and acceptance of those designs by NASA, and the initiation of manufacture of BSE components. The performance predictions indicate the Mod II engine design will meet or exceed the original program goals of 30% improvement in fuel economy over a conventional Internal Combustion (IC) powered vehicle, while providing acceptable emissions. This was accomplished while simultaneously reducing Mod II engine weight to a level comparable with IC engine power density, and packaging the Mod II in a 1985 Celebrity with no external sheet metal changes. The projected mileage of the Mod II Celebrity for the combined urban and highway CVS cycle is 40.9 mpg which is a 32% improvement over the IC Celebrity. If additional potential improvements are verified and incorporated in the Mod II, the mileage could increase to 42.7 mpg.

Military Curricula for Vocational & Technical Education. Basic Electricity and Electronics Individualized Learning System. CANTRAC A-100-0010. Module Six: Parallel Circuits. Study Booklet.

ERIC Educational Resources Information Center

Chief of Naval Education and Training Support, Pensacola, FL.

This individualized learning module on parallel circuits is one in a series of modules for a course in basic electricity and electronics. The course is one of a number of military-developed curriculum packages selected for adaptation to vocational instructional and curriculum development in a civilian setting. Four lessons are included in the…

Vision Technology for Automated Inspection of Hybrid Microelectronics Assemblies

DTIC Science & Technology

1988-06-01

circuits are a very efficient packaging technique, with the primary advantages of size, better resistance to environ - 0 ments, and the flexibility to...produced for the military are much more complex and have more stringent performance requirements, particularly in their resistance to environments and...boards, particularly because of the need to protect circuits from a hostile environment such as salt, heat, and moisture. Included among the major U.S

Modular power converter having fluid cooled support

DOEpatents

Beihoff, Bruce C.; Radosevich, Lawrence D.; Meyer, Andreas A.; Gollhardt, Neil; Kannenberg, Daniel G.

2005-09-06

A support may receive one or more power electronic circuits. The support may aid in removing heat from the circuits through fluid circulating through the support. The support, in conjunction with other packaging features may form a shield from both external EMI/RFI and from interference generated by operation of the power electronic circuits. Features may be provided to permit and enhance connection of the circuitry to external circuitry, such as improved terminal configurations. Modular units may be assembled that may be coupled to electronic circuitry via plug-in arrangements or through interface with a backplane or similar mounting and interconnecting structures.

Modular power converter having fluid cooled support

DOEpatents

Beihoff, Bruce C.; Radosevich, Lawrence D.; Meyer, Andreas A.; Gollhardt, Neil; Kannenberg, Daniel G.

2005-12-06

A support may receive one or more power electronic circuits. The support may aid in removing heat from the circuits through fluid circulating through the support. The support, in conjunction with other packaging features may form a shield from both external EMI/RFI and from interference generated by operation of the power electronic circuits. Features may be provided to permit and enhance connection of the circuitry to external circuitry, such as improved terminal configurations. Modular units may be assembled that may be coupled to electronic circuitry via plug-in arrangements or through interface with a backplane or similar mounting and interconnecting structures.

Integrated Circuit Wear out Prediction and Recycling Detection using Radio Frequency Distinct Native Attribute Features

DTIC Science & Technology

2016-12-22

105 A.1 Main Loop ... loop monitoring for preventative maintenance rather than early replacement based on statistical projections or replacement-after- failure schemes. IC...estimates, RF-DNA may provide a means to track an IC’s physical degradation during actual use. Monitoring an IC’s degradation in a closed loop fashion

Deterioration of ZnO/SiO2 diode packages in high humidity

NASA Technical Reports Server (NTRS)

Evans, John; Wagner, Scott

1987-01-01

A case study is reported in which the ZnO/SiO2 glass used to package a power rectifier combined with the design to produce a catastropic corrosion failure of the system. Metallic Zn inclusions, present in the glass, played a critical role in creating a conductive path for corrosion currents. Actual equipment failure was the result of an open circuit trace created by corrosion. It is concluded that the presence of Zn inclusions in the glass of this type of package may result in long-term reliability problems for equipment used in high humidity environments.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pease, R.L.; Shaneyfelt, M.; Winokur, P.

The ionizing radiation response of several semiconductor process technologies has been shown to be enhanced by plastic packaging and/or pre-conditioning (burn-in). Potential mechanisms for this effect are discussed and data on bipolar linear circuits are presented.

Single-Event Transient Testing of Low Dropout PNP Series Linear Voltage Regulators

NASA Technical Reports Server (NTRS)

Adell, Philippe; Allen, Gregory

2013-01-01

As demand for high-speed, on-board, digital-processing integrated circuits on spacecraft increases (field-programmable gate arrays and digital signal processors in particular), the need for the next generation point-of-load (POL) regulator becomes a prominent design issue. Shrinking process nodes have resulted in core rails dropping to values close to 1.0 V, drastically reducing margin to standard switching converters or regulators that power digital ICs. The goal of this task is to perform SET characterization of several commercial POL converters, and provide a discussion of the impact of these results to state-of-the-art digital processing IC through laser and heavy ion testing

RF to millimeter wave integration and module technologies

NASA Astrophysics Data System (ADS)

Vähä-Heikkilä, T.

2015-04-01

Radio Frequency (RF) consumer applications have boosted silicon integrated circuits (IC) and corresponding technologies. More and more functions are integrated to ICs and their performance is also increasing. However, RF front-end modules with filters and switches as well as antennas still need other way of integration. This paper focuses to RF front-end module and antenna developments as well as to the integration of millimeter wave radios. VTT Technical Research Centre of Finland has developed both Low Temperature Co-fired Ceramics (LTCC) and Integrated Passive Devices (IPD) integration platforms for RF and millimeter wave integrated modules. In addition to in-house technologies, VTT is using module and component technologies from other commercial sources.

Off-line, built-in test techniques for VLSI circuits

NASA Technical Reports Server (NTRS)

Buehler, M. G.; Sievers, M. W.

1982-01-01

It is shown that the use of redundant on-chip circuitry improves the testability of an entire VLSI circuit. In the study described here, five techniques applied to a two-bit ripple carry adder are compared. The techniques considered are self-oscillation, self-comparison, partition, scan path, and built-in logic block observer. It is noted that both classical stuck-at faults and nonclassical faults, such as bridging faults (shorts), stuck-on x faults where x may be 0, 1, or vary between the two, and parasitic flip-flop faults occur in IC structures. To simplify the analysis of the testing techniques, however, a stuck-at fault model is assumed.

An adiabatic quantum flux parametron as an ultra-low-power logic device

NASA Astrophysics Data System (ADS)

Takeuchi, Naoki; Ozawa, Dan; Yamanashi, Yuki; Yoshikawa, Nobuyuki

2013-03-01

Ultra-low-power adiabatic quantum flux parametron (QFP) logic is investigated since it has the potential to reduce the bit energy per operation to the order of the thermal energy. In this approach, nonhysteretic QFPs are operated slowly to prevent nonadiabatic energy dissipation occurring during switching events. The designed adiabatic QFP gate is estimated to have a dynamic energy dissipation of 12% of IcΦ0 for a rise/fall time of 1000 ps. It can be further reduced by reducing circuit inductances. Three stages of adiabatic QFP NOT gates were fabricated using a Nb Josephson integrated circuit process and their correct operation was confirmed.

Faraday Cup Array Integrated with a Readout IC and Method for Manufacture Thereof

NASA Technical Reports Server (NTRS)

Temple, Dorota (Inventor); Bower, Christopher A. (Inventor); Hedgepath Gilchrist, Kristin (Inventor); Stoner, Brian R. (Inventor)

2014-01-01

A detector array and method for making the detector array. The array includes a substrate including a plurality of trenches formed therein, and includes a plurality of collectors electrically isolated from each other, formed on the walls of the trenches, and configured to collect charge particles incident on respective ones of the collectors and to output from said collectors signals indicative of charged particle collection. The array includes a plurality of readout circuits disposed on a side of the substrate opposite openings to the collectors. The readout circuits are configured to read charge collection signals from respective ones of the plurality of collectors.

The MSFC complementary metal oxide semiconductor (including multilevel interconnect metallization) process handbook

NASA Technical Reports Server (NTRS)

Bouldin, D. L.; Eastes, R. W.; Feltner, W. R.; Hollis, B. R.; Routh, D. E.

1979-01-01

The fabrication techniques for creation of complementary metal oxide semiconductor integrated circuits at George C. Marshall Space Flight Center are described. Examples of C-MOS integrated circuits manufactured at MSFC are presented with functional descriptions of each. Typical electrical characteristics of both p-channel metal oxide semiconductor and n-channel metal oxide semiconductor discrete devices under given conditions are provided. Procedures design, mask making, packaging, and testing are included.

Designing an Electronics Data Package for Printed Circuit Boards (PCBs)

DTIC Science & Technology

2013-08-01

finished PCB flatness deviation should be less than 0.010 inches per inch. 4  The minimum copper wall thickness of plated-thru holes should be...Memory Card International Association)  IPC-6015 MCM-L (Multi-Chip Module – Laminated )  IPC-6016 HDI (High Density Interconnect)  IPC-6018...Interconnect ICT In Circuit Tester IPC Association Connecting Electronics Industries MCM-L Multi-Chip Module – Laminated MIL Military NEMA National

The NATO III 5 MHz Distribution System

NASA Technical Reports Server (NTRS)

Vulcan, A.; Bloch, M.

1981-01-01

A high performance 5 MHz distribution system is described which has extremely low phase noise and jitter characteristics and provides multiple buffered outputs. The system is completely redundant with automatic switchover and is self-testing. Since the 5 MHz reference signals distributed by the NATO III distribution system are used for up-conversion and multiplicative functions, a high degree of phase stability and isolation between outputs is necessary. Unique circuit design and packaging concepts insure that the isolation between outputs is sufficient to quarantee a phase perturbation of less than 0.0016 deg when other outputs are open circuited, short circuited or terminated in 50 ohms. Circuit design techniques include high isolation cascode amplifiers. Negative feedback stabilizes system gain and minimizes circuit phase noise contributions. Balanced lines, in lieu of single ended coaxial transmission media, minimize pickup.

Incentive memory: evidence the basolateral amygdala encodes and the insular cortex retrieves outcome values to guide choice between goal-directed actions.

PubMed

Parkes, Shauna L; Balleine, Bernard W

2013-05-15

Choice between goal-directed actions is determined by the relative value of their consequences. Such values are encoded during incentive learning and later retrieved to guide performance. Although the basolateral amygdala (BLA) and the gustatory region of insular cortex (IC) have been implicated in these processes, their relative contribution is still a matter of debate. Here we assessed whether these structures interact during incentive learning and retrieval to guide choice. In these experiments, rats were trained on two actions for distinct outcomes after which one of the two outcomes was devalued by specific satiety immediately before a choice extinction test. We first confirmed that, relative to appropriate controls, outcome devaluation recruited both the BLA and IC based on activation of the immediate early gene Arc; however, we found that infusion of the NMDAr antagonist ifenprodil into the BLA only abolished outcome devaluation when given before devaluation. In contrast, ifenprodil infusion into the IC was effective whether made before devaluation or test. We hypothesized that the BLA encodes and the IC retrieves incentive value for choice and, to test this, developed a novel sequential disconnection procedure. Blocking NMDAr activation unilaterally in the BLA before devaluation and then contralaterally in the IC before test abolished selective devaluation. In contrast, reversing the order of these infusions left devaluation intact. These results confirm that the BLA and IC form a circuit mediating the encoding and retrieval of outcome values, with the BLA encoding and the IC retrieving such values to guide choice.

Cochlear Implants (For Parents)

MedlinePlus

... nerve, and send it to the brain. The cochlear implant package is made up of: a receiver-stimulator that contains all of the electronic circuits that control the flow of electrical pulses into the ear an antenna ...

Designing skin response meter for psycho galvanic reflex

NASA Astrophysics Data System (ADS)

Dhokalia, Dhruv M.; Atreya, Parul; Kumar, Arun

2011-12-01

Human skin offers some resistance to current and voltage. This resistance changes with the emotional state of the body. The circuit proposed here measures changes in our skin resistance following changes in our mental state. In the relaxed state, the resistance offered by the skin is as high as 2 mega-ohms or more, which reduces to 500 kilo-ohms or less when the emotional stress is too high. The reduction in skin resistance is related to increased blood flow and permeability followed by the physiological changes during high stress. This increases the electrical conductivity of the skin. This circuit is useful to monitor the skin's response to relaxation techniques. It is very sensitive and shows response during a sudden moment of stress. Even a deep sigh will give response in the circuit. The circuit uses a sensitive amplifier to sense variations in the skin resistance. IC CA3140 is designed as a resistance- to-voltage converter that outputs varying voltage based on the skin's conductivity.

Characterization of 6H-SiC JFET Integrated Circuits Over A Broad Temperature Range from -150 C to +500 C

NASA Technical Reports Server (NTRS)

Neudeck, Philip G.; Krasowski, Michael J.; Chen, Liang-Yu; Prokop, Norman F.

2009-01-01

The NASA Glenn Research Center has previously reported prolonged stable operation of simple prototype 6H-SiC JFET integrated circuits (logic gates and amplifier stages) for thousands of hours at +500 C. This paper experimentally investigates the ability of these 6H-SiC JFET devices and integrated circuits to also function at cold temperatures expected to arise in some envisioned applications. Prototype logic gate ICs experimentally demonstrated good functionality down to -125 C without changing circuit input voltages. Cascaded operation of gates at cold temperatures was verified by externally wiring gates together to form a 3-stage ring oscillator. While logic gate output voltages exhibited little change across the broad temperature range from -125 C to +500 C, the change in operating frequency and power consumption of these non-optimized logic gates as a function of temperature was much larger and tracked JFET channel conduction properties.

An assessment of the impact of the Department of Defense very high speed integrated circuit program

NASA Astrophysics Data System (ADS)

1982-01-01

The technical and economic effects of the Department of Defense's (DoD) development program for very-high-speed integrated circuits (VHSIC) are examined. The probable effects of this program on the domestic aspects and international position of the integrated-circuit (IC) industry as they relate to the interests of the general public and the DoD are considered. The report presents a review of the unique DoD needs that motivate VHSIC research and development; an estimate of the degree of which these needs are likely to be met by the VHSIC program; a discussion of the effects of the program's demands for manpower, materials, and design and processing technologies; the problems connected with the program's technology export controls; and an assessment of the impact of the program on the structure of the U.S. integrated-circuit industry, its continued development and production of civilian consumer products, and its international competitive position.

High-frequency output characteristics of AlGaAs/GaAs heterojunction bipolar transistors for large-signal applications

NASA Astrophysics Data System (ADS)

Chen, J.; Gao, G. B.; Ünlü, M. S.; Morkoç, H.

1991-11-01

High-frequency ic- vce output characteristics of bipolar transistors, derived from calculated device cutoff frequencies, are reported. The generation of high-frequency output characteristics from device design specifications represents a novel bridge between microwave circuit design and device design: the microwave performance of simulated device structures can be analyzed, or tailored transistor device structures can be designed to fit specific circuit applications. The details of our compact transistor model are presented, highlighting the high-current base-widening (Kirk) effect. The derivation of the output characteristics from the modeled cutoff frequencies are then presented, and the computed characteristics of an AlGaAs/GaAs heterojunction bipolar transistor operating at 10 GHz are analyzed. Applying the derived output characteristics to microwave circuit design, we examine large-signal class A and class B amplification.

Pulse transducer with artifact signal attenuator. [heart rate sensors

NASA Technical Reports Server (NTRS)

Cash, W. H., Jr.; Polhemus, J. T. (Inventor)

1980-01-01

An artifact signal attenuator for a pulse rate sensor is described. The circuit for attenuating background noise signals is connected with a pulse rate transducer which has a light source and a detector for light reflected from blood vessels of a living body. The heart signal provided consists of a modulated dc signal voltage indicative of pulse rate. The artifact signal resulting from light reflected from the skin of the body comprises both a constant dc signal voltage and a modulated dc signal voltage. The amplitude of the artifact signal is greater and the frequency less than that of the heart signal. The signal attenuator circuit includes an operational amplifier for canceling the artifact signal from the output signal of the transducer and has the capability of meeting packaging requirements for wrist-watch-size packages.

Development Unit Configuration and Current Status of the MIP/MTERC Experiment

NASA Technical Reports Server (NTRS)

Juanero, K. J.; Johnson, K. R.

1999-01-01

The Mars In-Situ Propellant Production (ISPP) Precursor (MIP) experiment package is planned for inclusion on the Mars 2001 Lander. This experiment package consists of five experiments whose purpose is to demonstrate the performance of various ISPP processes in-situ on Mars. The demonstrated ability to produce propellant for Mars Return Vehicles (MRV) is considered to be a necessary precursor to any future manned mission to Mars. The Mars Thermal Environment/Radiator Characterization (MTERC) experiment is part of the MIP package and is intended to determine the Mars night sky temperature as well as to characterize the performance degradation of radiators caused by environmental exposure on Mars over time. Radiators are needed as part of the ISPP process to remove heat from the Mars Atmosphere Acquisition and Compression (MAAC) C02 sorption compressor. MTERC will provide the data needed to optimize the design of radiators for ISPP and other processes. A MTERC Development Unit (DU) has been fabricated and tested at JPL. The MTERC DU consists of: (1) a radiator subassembly, (2) a motor/cover subassembly, (3) a differential temperature control circuit and motor control electronics circuit board, and (4) a command and data handling electronics circuit board. This paper will describe the operational theory and the configuration of the MTERC DU and will discuss the current status of the MTERC experiment development including some selected results of performance testing that has been completed prior to the ISRU III meeting.

Development Unit Configuration and Current Status of the MIP/MTERC Experiment

NASA Technical Reports Server (NTRS)

Juanero, K. J.; Johnson, K. R.

1999-01-01

The Mars In-Situ Propellant Production (ISPP) Precursor (MIP) experiment package is planned for inclusion on the Mars 2001 Lander. This experiment package consists of five experiments whose purpose is to demonstrate the performance of various ISPP processes in-situ on Mars. The demonstrated ability to produce propellant for Mars Return Vehicles (MRV) is considered to be a necessary precursor to any future manned mission to Mars. The Mars Thermal Environment/Radiator Characterization (MTERC) experiment is part of the MIP package and is intended to determine the Mars night sky temperature as well as to characterize the performance degradation of radiators caused by environmental exposure on Mars over time. Radiators are needed as part of the ISPP process to remove heat from the Mars Atmosphere Acquisition and Compression (MAAC) CO2 sorption compressor. MTERC will provide the data needed to optimize the design of radiators for ISPP and other processes. A MTERC Development Unit (DU) has been fabricated and tested at JPL. The MTERC DU consists of 1) a radiator subassembly, 2) a motor/cover subassembly, 3) a differential temperature control circuit and motor control electronics circuit board, and 4) a command and data handling electronics circuit board. This paper will describe the operational theory and the configuration of the MTERC DU and will discuss the current status of the MTERC experiment development including some selected results of performance testing that has been completed prior to the ISRU III meeting.

Compact high voltage solid state switch

DOEpatents

Glidden, Steven C.

2003-09-23

A compact, solid state, high voltage switch capable of high conduction current with a high rate of current risetime (high di/dt) that can be used to replace thyratrons in existing and new applications. The switch has multiple thyristors packaged in a single enclosure. Each thyristor has its own gate drive circuit that circuit obtains its energy from the energy that is being switched in the main circuit. The gate drives are triggered with a low voltage, low current pulse isolated by a small inexpensive transformer. The gate circuits can also be triggered with an optical signal, eliminating the trigger transformer altogether. This approach makes it easier to connect many thyristors in series to obtain the hold off voltages of greater than 80 kV.

Free-world microelectronic manufacturing equipment

NASA Astrophysics Data System (ADS)

Kilby, J. S.; Arnold, W. H.; Booth, W. T.; Cunningham, J. A.; Hutcheson, J. D.; Owen, R. W.; Runyan, W. R.; McKenney, Barbara L.; McGrain, Moira; Taub, Renee G.

1988-12-01

Equipment is examined and evaluated for the manufacture of microelectronic integrated circuit devices and sources for that equipment within the Free World. Equipment suitable for the following are examined: single-crystal silicon slice manufacturing and processing; required lithographic processes; wafer processing; device packaging; and test of digital integrated circuits. Availability of the equipment is also discussed, now and in the near future. Very adequate equipment for most stages of the integrated circuit manufacturing process is available from several sources, in different countries, although the best and most widely used versions of most manufacturing equipment are made in the United States or Japan. There is also an active market in used equipment, suitable for manufacture of capable integrated circuits with performance somewhat short of the present state of the art.

CMOS Imaging of Pin-Printed Xerogel-Based Luminescent Sensor Microarrays.

PubMed

Yao, Lei; Yung, Ka Yi; Khan, Rifat; Chodavarapu, Vamsy P; Bright, Frank V

2010-12-01

We present the design and implementation of a luminescence-based miniaturized multisensor system using pin-printed xerogel materials which act as host media for chemical recognition elements. We developed a CMOS imager integrated circuit (IC) to image the luminescence response of the xerogel-based sensor array. The imager IC uses a 26 × 20 (520 elements) array of active pixel sensors and each active pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. The imager includes a correlated double sampling circuit and pixel address/digital control circuit; the image data is read-out as coded serial signal. The sensor system uses a light-emitting diode (LED) to excite the target analyte responsive luminophores doped within discrete xerogel-based sensor elements. As a prototype, we developed a 4 × 4 (16 elements) array of oxygen (O 2 ) sensors. Each group of 4 sensor elements in the array (arranged in a row) is designed to provide a different and specific sensitivity to the target gaseous O 2 concentration. This property of multiple sensitivities is achieved by using a strategic mix of two oxygen sensitive luminophores ([Ru(dpp) 3 ] 2+ and ([Ru(bpy) 3 ] 2+ ) in each pin-printed xerogel sensor element. The CMOS imager consumes an average power of 8 mW operating at 1 kHz sampling frequency driven at 5 V. The developed prototype system demonstrates a low cost and miniaturized luminescence multisensor system.

An Integrated Circuit for Simultaneous Extracellular Electrophysiology Recording and Optogenetic Neural Manipulation

PubMed Central

Chen, Chang Hao; McCullagh, Elizabeth A.; Pun, Sio Hang; Mak, Peng Un; Vai, Mang I; Mak, Pui In; Klug, Achim; Lei, Tim C.

2017-01-01

The ability to record and to control action potential firing in neuronal circuits of the brain is critical to understand how the brain functions on the cellular and network levels. Recent development of optogenetic proteins allows direct stimulation or inhibition of action potential firing of neurons upon optical illumination. In this paper, we combined a low-noise and high input impedance (or low input capacitance) neural recording amplifier, and a high current laser/LED driver in a monolithic integrated circuit (IC) for simultaneous neural recording and optogenetic neural control. The low input capacitance of the amplifier (9.7 pF) was achieved through adding a dedicated unity gain input stage optimized for high impedance metal electrodes. The input referred noise of the amplifier was measured to be 4.57 µVrms, which is lower than the estimated thermal noise of the metal electrode. Thus, action potentials originating from a single neuron can be recorded with a signal-to-noise ratio of ~6.6. The LED/laser current driver delivers a maximum current of 330 mA to generate adequate light for optogenetic control. We experimentally tested the functionality of the IC with an anesthetized Mongolian gerbil and recorded auditory stimulated action potentials from the inferior colliculus. Furthermore, we showed that spontaneous firing of 5th (trigeminal) nerve fibers was inhibited using the optogenetic protein Halorhodopsin. A noise model was also derived including the equivalent electronic components of the metal electrode and the high current driver to guide the design. PMID:28221990

Minimally-Invasive Neural Interface for Distributed Wireless Electrocorticogram Recording Systems

PubMed Central

Chang, Sun-Il

2018-01-01

This paper presents a minimally-invasive neural interface for distributed wireless electrocorticogram (ECoG) recording systems. The proposed interface equips all necessary components for ECoG recording, such as the high performance front-end integrated circuits, a fabricated flexible microelectrode array, and wireless communication inside a miniaturized custom-made platform. The multiple units of the interface systems can be deployed to cover a broad range of the target brain region and transmit signals via a built-in intra-skin communication (ISCOM) module. The core integrated circuit (IC) consists of 16-channel, low-power push-pull double-gated preamplifiers, in-channel successive approximation register analog-to-digital converters (SAR ADC) with a single-clocked bootstrapping switch and a time-delayed control unit, an ISCOM module for wireless data transfer through the skin instead of a power-hungry RF wireless transmitter, and a monolithic voltage/current reference generator to support the aforementioned analog and mixed-signal circuit blocks. The IC was fabricated using 250 nm CMOS processes in an area of 3.2 × 0.9 mm2 and achieved the low-power operation of 2.5 µW per channel. Input-referred noise was measured as 5.62 µVrms for 10 Hz to 10 kHz and ENOB of 7.21 at 31.25 kS/s. The implemented system successfully recorded multi-channel neural activities in vivo from a primate and demonstrated modular expandability using the ISCOM with power consumption of 160 µW. PMID:29342103

Minimally-Invasive Neural Interface for Distributed Wireless Electrocorticogram Recording Systems.

PubMed

Chang, Sun-Il; Park, Sung-Yun; Yoon, Euisik

2018-01-17

This paper presents a minimally-invasive neural interface for distributed wireless electrocorticogram (ECoG) recording systems. The proposed interface equips all necessary components for ECoG recording, such as the high performance front-end integrated circuits, a fabricated flexible microelectrode array, and wireless communication inside a miniaturized custom-made platform. The multiple units of the interface systems can be deployed to cover a broad range of the target brain region and transmit signals via a built-in intra-skin communication (ISCOM) module. The core integrated circuit (IC) consists of 16-channel, low-power push-pull double-gated preamplifiers, in-channel successive approximation register analog-to-digital converters (SAR ADC) with a single-clocked bootstrapping switch and a time-delayed control unit, an ISCOM module for wireless data transfer through the skin instead of a power-hungry RF wireless transmitter, and a monolithic voltage/current reference generator to support the aforementioned analog and mixed-signal circuit blocks. The IC was fabricated using 250 nm CMOS processes in an area of 3.2 × 0.9 mm² and achieved the low-power operation of 2.5 µW per channel. Input-referred noise was measured as 5.62 µV rms for 10 Hz to 10 kHz and ENOB of 7.21 at 31.25 kS/s. The implemented system successfully recorded multi-channel neural activities in vivo from a primate and demonstrated modular expandability using the ISCOM with power consumption of 160 µW.

Parallel interconnect for a novel system approach to short distance high information transfer data links

NASA Astrophysics Data System (ADS)

Raskin, Glenn; Lebby, Michael S.; Carney, F.; Kazakia, M.; Schwartz, Daniel B.; Gaw, Craig A.

1997-04-01

The OPTOBUSTM family of products provides for high performance parallel interconnection utilizing optical links in a 10-bit wide bi-directional configuration. The link is architected to be 'transparent' in that it is totally asynchronous and dc coupled so that it can be treated as a perfect cable with extremely low skew and no losses. An optical link consists of two identical transceiver modules and a pair of connectorized 62.5 micrometer multi mode fiber ribbon cables. The OPTOBUSTM I link provides bi- directional functionality at 4 Gbps (400 Mbps per channel), while the OPTOBUSTM II link will offer the same capability at 8 Gbps (800 Mbps per channel). The transparent structure of the OPTOBUSTM links allow for an arbitrary data stream regardless of its structure. Both the OPTOBUSTM I and OPTOBUSTM II transceiver modules are packaged as partially populated 14 by 14 pin grid arrays (PGA) with optical receptacles on one side of the module. The modules themselves are composed of several elements; including passives, integrated circuits optoelectronic devices and optical interface units (OIUs) (which consist of polymer waveguides and a specially designed lead frame). The initial offering of the modules electrical interface utilizes differential CML. The CML line driver sinks 5 mA of current into one of two pins. When terminated with 50 ohm pull-up resistors tied to a voltage between VCC and VCC-2, the result is a differential swing of plus or minus 250 mV, capable of driving standard PECL I/Os. Future offerings of the OPTOBUSTM links will incorporate LVDS and PECL interfaces as well as CML. The integrated circuits are silicon based. For OPTOBUSTM I links, a 1.5 micrometer drawn emitter NPN bipolar process is used for the receiver and an enhanced 0.8 micrometer CMOS process for the laser driver. For OPTOBUSTM II links, a 0.8 micrometer drawn emitter NPN bipolar process is used for the receiver and the driver IC utilizes 0.8 micrometer BiCMOS technology. The OPTOBUSTM architecture uses AlGaAs vertical cavity surface emitting lasers (VCSELs) at 850 nm in conjunction with unique opto-electronic packaging concepts. Most laser based transmitter subsystems are incapable of carrying an arbitrary NRZ data stream at high data rates. The receiver subsystem utilizes a conventional GaAs PIN photo-detector. In parallel interconnect systems. The design must take into account the simultaneous switching noise from the neighboring systems. If not well controlled, the high density of the multiple interconnects can limit the sensitivity and therefore the performance of the system. The packaging approach of the VCSEL and PIN arrays allow for high bandwidths and provide the coupling mechanisms necessary to interface to the 62.5 micrometer multi mode fiber. To allow for extremely high electrical signals the OPTOBUSTM package utilizes a multilayer tape automated bonded (TAB) lead frame. The lead frame contains separate signal and ground layers. The ground layer successfully provides for a pseudo-coaxial environment (low inductance and effective signal coupling to the ground plane).

Iterative categorization (IC): a systematic technique for analysing qualitative data

PubMed Central

2016-01-01

Abstract The processes of analysing qualitative data, particularly the stage between coding and publication, are often vague and/or poorly explained within addiction science and research more broadly. A simple but rigorous and transparent technique for analysing qualitative textual data, developed within the field of addiction, is described. The technique, iterative categorization (IC), is suitable for use with inductive and deductive codes and can support a range of common analytical approaches, e.g. thematic analysis, Framework, constant comparison, analytical induction, content analysis, conversational analysis, discourse analysis, interpretative phenomenological analysis and narrative analysis. Once the data have been coded, the only software required is a standard word processing package. Worked examples are provided. PMID:26806155

Packaging of MEMS/MOEMS and nanodevices: reliability, testing, and characterization aspects

NASA Astrophysics Data System (ADS)

Tekin, Tolga; Ngo, Ha-Duong; Wittler, Olaf; Bouhlal, Bouchaib; Lang, Klaus-Dieter

2011-02-01

The last decade witnessed an explosive growth in research and development efforts devoted to MEMS devices and packaging. The successfully developed MEMS devices are, for example inkjet, pressure sensors, silicon microphones, accelerometers, gyroscopes, MOEMS, micro fuel cells and emerging MEMS. For the next decade, MEMS/MOEMS and nanodevice based products will penetrate into IT, telecommunications, automotive, defense, life sciences, medical and implantable applications. Forecasts say the MEMS market to be $14 billion by 2012. The packaging cost of MEMS/MOEMS products in general is about 70 percent. Unlike today's electronics IC packaging, their packaging are custom-built and difficult due to the moving structural elements. In order for the moving elements of a MEMS device to move effectively in a well-controlled atmosphere, hermetic sealing of the MEMS device in a cap is necessary. For some MEMS devices, such as resonators and gyroscopes, vacuum packaging is required. Usually, the cap is processed at the wafer level, and thus MEMS packaging is truly a wafer level packaging. In terms of MEMS/MOEMS and nanodevice packaging, there are still many critical issues need to be addressed due to the increasing integration density supported by 3D heterogeneous integration of multi-physic components/layers consisting of photonics, electronics, rf, plasmonics, and wireless. The infrastructure of MEMS/MOEMS and nanodevices and their packaging is not well established yet. Generic packaging platform technologies are not available. Some of critical issues have been studied intensively in the last years. In this paper we will discuss about processes, reliability, testing and characterization of MEMS/MOEMS and nanodevice packaging.

Critical role of domain crystallinity, domain purity and domain interface sharpness for reduced bimolecular recombination in polymer solar cells

DOE PAGES

Venkatesan, Swaminathan; Chen, Jihua; Ngo, Evan C.; ...

2014-12-31

In this study, inverted bulk heterojunction solar cells were fabricated using poly(3-hexylthiophene) (P3HT) blended with two different fullerene derivatives namely phenyl-C61-butyric acid methyl ester (PC 60BM) and indene-C 60 bis-adduct (IC 60BA). The effects of annealing temperatures on the morphology, optical and structural properties were studied and correlated to differences in photovoltaic device performance. It was observed that annealing temperature significantly improved the performance of P3HT:IC 60BA solar cells while P3HT:PC 60BM cells showed relatively less improvement. The performance improvement is attributed to the extent of fullerene mixing with polymer domains. Energy filtered transmission electron microscopy (EFTEM) and x-ray diffractionmore » (XRD) results showed that ICBA mixes with disordered P3HT much more readily than PC 60BM which leads to lower short circuit current density and fill factor for P3HT:IC 60BA cells annealed below 120°C. Annealing above 120°C improves the crystallinity of P3HT in case of P3HT:IC 60BA whereas in P3HT:PC 60BM films, annealing above 80°C leads to negligible change in crystallinity. Crystallization of P3HT also leads to higher domain purity as seen EFTEM. Further it is seen that cells processed with additive nitrobenzene (NB) showed enhanced short circuit current density and power conversion efficiency regardless of the fullerene derivative used. Addition of NB led to nanoscale phase separation between purer polymer and fullerene domains. Kelvin probe force microscopy (KPFM) images showed that enhanced domain purity in additive casted films led to a sharper interface between polymer and fullerene. Lastly, enhanced domain purity and interfacial sharpness led to lower bimolecular recombination and higher mobility and charge carrier lifetime in NB modified devices.« less

A Physics-Based Approach for Power Integrity in Multi-Layered PCBs

NASA Astrophysics Data System (ADS)

Zhao, Biyao

Developing a power distribution network (PDN) for ASICs and ICs to achieve the low-voltage ripple specifications for current digital designs is challenging with the high-speed and low-voltage ICs. Present methods are typically guided by best engineering practices for low impedance looking into the PDN from the IC. A pre-layout design methodology for power integrity in multi-layered PCB PDN geometry is proposed in the thesis. The PCB PDN geometry is segmented into four parts and every part is modelled using different methods based on the geometry details of the part. Physics-based circuit models are built for every part and the four parts are re-assembled into one model. The influence of geometry details is clearly revealed in this methodology. Based on the physics-based circuit mode, the procedures of using the pre-layout design methodology as a guideline during the PDN design is illustrated. Some common used geometries are used to build design space, and the design curves with the geometry details are provided to be a look up library for engineering use. The pre-layout methodology is based on the resonant cavity model of parallel planes for the cavity structures, and parallel-plane PEEC (PPP) for the irregular shaped plane inductance, and PEEC for the decoupling capacitor connection above the top most or bottom most power-return planes. PCB PDN is analyzed based on the input impedance looking into the PCB from the IC. The pre-layout design methodology can be used to obtain the best possible PCB PDN design. With the switching current profile, the target impedance can be selected to evaluate the PDN performance, and the frequency domain PDN input impedance can be used to obtain the voltage ripple in the time domain to give intuitive insight of the geometry impact on the voltage ripple.

High Voltage Dielectrophoretic and Magnetophoretic Hybrid Integrated Circuit / Microfluidic Chip

PubMed Central

Issadore, David; Franke, Thomas; Brown, Keith A.; Hunt, Thomas P.; Westervelt, Robert M.

2010-01-01

A hybrid integrated circuit (IC) / microfluidic chip is presented that independently and simultaneously traps and moves microscopic objects suspended in fluid using both electric and magnetic fields. This hybrid chip controls the location of dielectric objects, such as living cells and drops of fluid, on a 60 × 61 array of pixels that are 30 × 38 μm2 in size, each of which can be individually addressed with a 50 V peak-to-peak, DC to 10 MHz radio frequency voltage. These high voltage pixels produce electric fields above the chip’s surface with a magnitude , resulting in strong dielectrophoresis (DEP) forces . Underneath the array of DEP pixels there is a magnetic matrix that consists of two perpendicular sets of 60 metal wires running across the chip. Each wire can be sourced with 120 mA to trap and move magnetically susceptible objects using magnetophoresis (MP). The DEP pixel array and magnetic matrix can be used simultaneously to apply forces to microscopic objects, such as living cells or lipid vesicles, that are tagged with magnetic nanoparticles. The capabilities of the hybrid IC / microfluidic chip demonstrated in this paper provide important building blocks for a platform for biological and chemical applications. PMID:20625468

High Voltage Dielectrophoretic and Magnetophoretic Hybrid Integrated Circuit / Microfluidic Chip.

PubMed

Issadore, David; Franke, Thomas; Brown, Keith A; Hunt, Thomas P; Westervelt, Robert M

2009-12-01

A hybrid integrated circuit (IC) / microfluidic chip is presented that independently and simultaneously traps and moves microscopic objects suspended in fluid using both electric and magnetic fields. This hybrid chip controls the location of dielectric objects, such as living cells and drops of fluid, on a 60 × 61 array of pixels that are 30 × 38 μm(2) in size, each of which can be individually addressed with a 50 V peak-to-peak, DC to 10 MHz radio frequency voltage. These high voltage pixels produce electric fields above the chip's surface with a magnitude , resulting in strong dielectrophoresis (DEP) forces . Underneath the array of DEP pixels there is a magnetic matrix that consists of two perpendicular sets of 60 metal wires running across the chip. Each wire can be sourced with 120 mA to trap and move magnetically susceptible objects using magnetophoresis (MP). The DEP pixel array and magnetic matrix can be used simultaneously to apply forces to microscopic objects, such as living cells or lipid vesicles, that are tagged with magnetic nanoparticles. The capabilities of the hybrid IC / microfluidic chip demonstrated in this paper provide important building blocks for a platform for biological and chemical applications.

Microwave evaluation of electromigration susceptibility in advanced interconnects.

PubMed

Sunday, Christopher E; Veksler, Dmitry; Cheung, Kin C; Obeng, Yaw S

2017-11-07

Traditional metrology has been unable to adequately address the needs of the emerging integrated circuits (ICs) at the nano scale; thus, new metrology and techniques are needed. For example, the reliability challenges in fabrication need to be well understood and controlled to facilitate mass production of through-substrate-via (TSV) enabled three-dimensional integrated circuits (3D-ICs). This requires new approaches to the metrology. In this paper, we use the microwave propagation characteristics to study the reliability issues that precede the physical damage caused by electromigration in the Cu-filled TSVs. The pre-failure microwave insertion losses and group delay are dependent on both the device temperature and the amount of current forced through the devices-under-test. The microwave insertion losses increase with the increase in the test temperature, while the group delay increases with the increase in the forced direct current magnitude. The microwave insertion losses are attributed to the defect mobility at the Cu-TiN interface, and the group delay changes are due to resistive heating in the interconnects, which perturbs the dielectric properties of the cladding dielectrics of the copper fill in the TSVs. https://doi.org/10.1063/1.4992135.

Molding compound trends in a denser packaging world: Qualification tests and reliability concerns

NASA Astrophysics Data System (ADS)

Nguyen, L. T.; Lo, R. H. Y.; Chen, A. S.; Belani, J. G.

1993-12-01

Molding compound development has traditionally been driven by the memory market, then subsequent applications filter down to other IC technologies such as logic, analog, and ASIC. However, this strategy has changed lately with the introduction of thin packages such as PQFP & TSOP. Rather than targeting a compound for a family of IC such as DRAM or SRAM, compound development efforts are now focused at specific classes of packages. The configurations of these thin packages impose new functional requirements that need to be revisited to provide the optimized combination of properties. The evolution of qualification tests mirrors the advances in epoxy and compounding technologies. From the first standard novolac-based epoxies of the 1970s to the latest 3(sup rd)-generation ultra-low stress materials, longer test times at increasingly harsher environments were achieved. This paper benchmarks the current reliability tests used by the electronic industry, examines those tests that affect and are affected by the molding compounds, discusses the relevance of accelerated testing, and addresses the major reliability issues facing current molding compound development efforts. Six compound-related reliability concerns were selected: moldability, package stresses, package cracking, halogen-induced intermetallic growth at bond pads, moisture-induced corrosion, and interfacial delamination. Causes of each failure type are surveyed and remedies are recommended. Accelerated tests are designed to apply to a limited quantity of devices, bias, or environmental conditions larger than usual ratings, to intensify failure mechanisms that would occur under normal operating conditions. The observed behavior is then extrapolated from the lot to the entire population. Emphasis is on compressing the time necessary to obtain reliability data. This approach has two main drawbacks. With increasingly complex devices, even accelerated tests are expensive. And with new technologies, it becomes difficult to ascertain that the applied stress 1) induces the failure phenomenon linked with usual field conditions, and 2) does not create any new ones. Technology evolution and reliability testing are interdependent. Devices get larger with increasingly smaller features and more complex geometries. Molding compounds have evolved considerably over the past decade to provide ultra-low stress levels and moldability for thin packages.

Basic Mechanisms of Radiation Effects on Electronic Materials, Devices, and Integrated Circuits

DTIC Science & Technology

1982-08-01

recovery time versus reciprocal tempera- ture derived from data of the type shown in Figure 18. . . .31 20 Several ways to alter the charje state of...and long-term recovery processes that occUr in neutron-irradiated silicon ........ 40 29 Annealing factor versus time for 11 ohm-cm p-type bulk silicon...radioactive ele- ments (such as uranium and thorium) which, when incorporated in packaged integrated circuits, can cause occasional transient upsets

Electrical power converter method and system employing multiple output converters

DOEpatents

Beihoff, Bruce C [Wauwatosa, WI; Radosevich, Lawrence D [Muskego, WI; Meyer, Andreas A [Richmond Heights, OH; Gollhardt, Neil [Fox Point, WI; Kannenberg, Daniel G [Waukesha, WI

2007-05-01

A support may receive one or more power electronic circuits. The support may aid in removing heat from the circuits through fluid circulating through the support. The support, in conjunction with other packaging features may form a shield from both external EMI/RFI and from interference generated by operation of the power electronic circuits. Features may be provided to permit and enhance connection of the circuitry to external circuitry, such as improved terminal configurations. Modular units may be assembled that may be coupled to electronic circuitry via plug-in arrangements or through interface with a backplane or similar mounting and interconnecting structures.

Fluid cooled vehicle drive module

DOEpatents

Beihoff, Bruce C.; Radosevich, Lawrence D.; Meyer, Andreas A.; Gollhardt, Neil; Kannenberg, Daniel G.

2005-11-15

An electric vehicle drive includes a support may receive one or more power electronic circuits. The support may aid in removing heat from the circuits through fluid circulating through the support. The support, in conjunction with other packaging features may form a shield from both external EM/RFI and from interference generated by operation of the power electronic circuits. Features may be provided to permit and enhance connection of the circuitry to external circuitry, such as improved terminal configurations. Modular units may be assembled that may be coupled to electronic circuitry via plug-in arrangements or through interface with a backplane or similar mounting and interconnecting structures.

Electrical power converter method and system employing multiple-output converters

DOEpatents

Beihoff, Bruce C.; Radosevich, Lawrence D.; Meyer, Andreas A.; Gollhardt, Neil; Kannenberg, Daniel G.

2006-03-21

A support may receive one or more power electronic circuits. The support may aid in removing heat from the circuits through fluid circulating through the support. The support, in conjunction with other packaging features may form a shield from both external EMI/RFI and from interference generated by operation of the power electronic circuits. Features may be provided to permit and enhance connection of the circuitry to external circuitry, such as improved terminal configurations. Modular units may be assembled that may be coupled to electronic circuitry via plug-in arrangements or through interface with a backplane or similar mounting and interconnecting structures.

Radio controlled release apparatus for animal data acquisition devices

DOEpatents

Stamps, James Frederick

2000-01-01

A novel apparatus for reliably and selectively releasing a data acquisition package from an animal for recovery. The data package comprises two parts: 1) an animal data acquisition device and 2) a co-located release apparatus. One embodiment, which is useful for land animals, the release apparatus includes two major components: 1) an electronics package, comprising a receiver; a decoder comparator, having at plurality of individually selectable codes; and an actuator circuit and 2) a release device, which can be a mechanical device, which acts to release the data package from the animal. To release a data package from a particular animal, a radio transmitter sends a coded signal which is decoded to determine if the code is valid for that animal data package. Having received a valid code, the release device is activated to release the data package from the animal for subsequent recovery. A second embodiment includes floatation means and is useful for releasing animal data acquisition devices attached to sea animals. This embodiment further provides for releasing a data package underwater by employing an acoustic signal.

Integrated circuits for volumetric ultrasound imaging with 2-D CMUT arrays.

PubMed

Bhuyan, Anshuman; Choe, Jung Woo; Lee, Byung Chul; Wygant, Ira O; Nikoozadeh, Amin; Oralkan, Ömer; Khuri-Yakub, Butrus T

2013-12-01

Real-time volumetric ultrasound imaging systems require transmit and receive circuitry to generate ultrasound beams and process received echo signals. The complexity of building such a system is high due to requirement of the front-end electronics needing to be very close to the transducer. A large number of elements also need to be interfaced to the back-end system and image processing of a large dataset could affect the imaging volume rate. In this work, we present a 3-D imaging system using capacitive micromachined ultrasonic transducer (CMUT) technology that addresses many of the challenges in building such a system. We demonstrate two approaches in integrating the transducer and the front-end electronics. The transducer is a 5-MHz CMUT array with an 8 mm × 8 mm aperture size. The aperture consists of 1024 elements (32 × 32) with an element pitch of 250 μm. An integrated circuit (IC) consists of a transmit beamformer and receive circuitry to improve the noise performance of the overall system. The assembly was interfaced with an FPGA and a back-end system (comprising of a data acquisition system and PC). The FPGA provided the digital I/O signals for the IC and the back-end system was used to process the received RF echo data (from the IC) and reconstruct the volume image using a phased array imaging approach. Imaging experiments were performed using wire and spring targets, a ventricle model and a human prostrate. Real-time volumetric images were captured at 5 volumes per second and are presented in this paper.

A hybrid approach to nanoelectronics

NASA Astrophysics Data System (ADS)

Cerofolini, G. F.; Arena, G.; Camalleri, C. M.; Galati, C.; Reina, S.; Renna, L.; Mascolo, D.

2005-08-01

The definition of features on the nanometre length scale (NLS) is impossible via conventional lithography, but can be done using extreme ultraviolet, synchrotron-radiation, or electron beam lithography. However, since these techniques are very expensive and still in their infancy, their exploitation in integrated circuit (IC) processing is still highly putative. Geometries on the NLS can however be produced with relative ease using the spacer patterning technique, i.e. transforming vertical features (like film thickness) in the vicinity of a step of a sacrificial layer into horizontal features. The ultimate length that can be produced in this way is controlled by the steepness of the step defining the sacrificial layer, the uniformity of the deposited or grown films, and the anisotropy of its etching. While useful for the preparation of a few devices with special needs, the above trick does not allow by itself the development of a nanotechnology where each layer useful for defining the circuit should be on the NLS and aligned on the underlying geometries with tolerances on the NLS. Setting up such a nanotechnology is a major problem which will involve the IC industry in the post-Roadmap era. Irrespective of the detailed structure of the basic constituents (molecules, supramolecular structures, clusters, etc), ICs with nanoscopic active elements can hardly be prepared without the ability to produce arrays of conductive strips with pitch on the NLS. This work is devoted to describing a scheme (essentially based on the existing microelectronic technology) for their production without the use of advanced lithography and how it can be arranged to host molecular devices.

Sex Differences in Gamma Band Functional Connectivity Between the Frontal Lobe and Cortical Areas During an Auditory Oddball Task, as Revealed by Imaginary Coherence Assessment.

PubMed

Fujimoto, Toshiro; Okumura, Eiichi; Kodabashi, Atsushi; Takeuchi, Kouzou; Otsubo, Toshiaki; Nakamura, Katsumi; Yatsushiro, Kazutaka; Sekine, Masaki; Kamiya, Shinichiro; Shimooki, Susumu; Tamura, Toshiyo

2016-01-01

We studied sex-related differences in gamma oscillation during an auditory oddball task, using magnetoencephalography and electroencephalography assessment of imaginary coherence (IC). We obtained a statistical source map of event-related desynchronization (ERD) / event-related synchronization (ERS), and compared females and males regarding ERD / ERS. Based on the results, we chose respectively seed regions for IC determinations in low (30-50 Hz), mid (50-100 Hz) and high gamma (100-150 Hz) bands. In males, ERD was increased in the left posterior cingulate cortex (CGp) at 500 ms in the low gamma band, and in the right caudal anterior cingulate cortex (cACC) at 125 ms in the mid-gamma band. ERS was increased in the left rostral anterior cingulate cortex (rACC) at 375 ms in the high gamma band. We chose the CGp, cACC and rACC as seeds, and examined IC between the seed and certain target regions using the IC map. IC changes depended on the height of the gamma frequency and the time window in the gamma band. Although IC in the mid and high gamma bands did not show sex-specific differences, IC at 30-50 Hz in males was increased between the left rACC and the frontal, orbitofrontal, inferior temporal and fusiform target regions. Increased IC in males suggested that males may acomplish the task constructively, analysingly, emotionally, and by perfoming analysis, and that information processing was more complicated in the cortico-cortical circuit. On the other hand, females showed few differences in IC. Females planned the task with general attention and economical well-balanced processing, which was explained by the higher overall functional cortical connectivity. CGp, cACC and rACC were involved in sex differences in information processing and were likely related to differences in neuroanatomy, hormones and neurotransmitter systems.

A novel readout integrated circuit for ferroelectric FPA detector

NASA Astrophysics Data System (ADS)

Bai, Piji; Li, Lihua; Ji, Yulong; Zhang, Jia; Li, Min; Liang, Yan; Hu, Yanbo; Li, Songying

2017-11-01

Uncooled infrared detectors haves some advantages such as low cost light weight low power consumption, and superior reliability, compared with cryogenically cooled ones Ferroelectric uncooled focal plane array(FPA) are being developed for its AC response and its high reliability As a key part of the ferroelectric assembly the ROIC determines the performance of the assembly. A top-down design model for uncooled ferroelectric readout integrated circuit(ROIC) has been developed. Based on the optical thermal and electrical properties of the ferroelectric detector the RTIA readout integrated circuit is designed. The noise bandwidth of RTIA readout circuit has been developed and analyzed. A novel high gain amplifier, a high pass filter and a low pass filter circuits are designed on the ROIC. In order to improve the ferroelectric FPA package performance and decrease of package cost a temperature sensor is designed on the ROIC chip At last the novel RTIA ROIC is implemented on 0.6μm 2P3M CMOS silicon techniques. According to the experimental chip test results the temporal root mean square(RMS)noise voltage is about 1.4mV the sensitivity of the on chip temperature sensor is 0.6 mV/K from -40°C to 60°C the linearity performance of the ROIC chip is better than 99% Based on the 320×240 RTIA ROIC, a 320×240 infrared ferroelectric FPA is fabricated and tested. Test results shows that the 320×240 RTIA ROIC meets the demand of infrared ferroelectric FPA.

Thermal Testing and Quality Assurance of BGA LCC & QFN Electronic Packages

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kuper, Cameron Mathias

The purpose of this project is to experimentally validate the thermal fatigue life of solder interconnects for a variety of surface mount electronic packages. Over the years, there has been a significant amount of research and analysis in the fracture of solder joints on printed circuit boards. Solder is important in the mechanical and electronic functionality of the component. It is important throughout the life of the product that the solder remains crack and fracture free. The specific type of solder used in this experiment is a 63Sn37Pb eutectic alloy. Each package was surrounded conformal coating or underfill material.

FInal Technical Repot of the Project: Design and Implementation of Low-Power 10Gb/s/channel Laser/Silicon Photonics Modulator Drivers with SEU Tolerance for HL-LHC

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gui, Ping

During the funding period of this award from May 1, 2014 through March 30, 2016, we have accomplished the design, implementation and measurement results of two laser driver chips: LpGBLD10+ which is a low-power single-channel 10Gb/s laser driver IC, and LDQ10P, which is a 4x10Gb/s driver array chip for High Energy Physics (HEP) applications. With new circuit techniques, the driver consumes a record-low power consumption, 31 mW @10Gb/s/channel and occupies a small area of 400 µm × 1750 µm for the single-channel driver IC and 1900umx1700um for the LDQ10P chip. These characteristics allow for both the LpGBLD10+ ICs and LDQ10P suitable candidatemore » for the Versatile Link PLUS (VL+) project, offering flexibility in configuring multiple Transmitters and receivers.« less

INTELSAT V-E(F-5)

NASA Technical Reports Server (NTRS)

1982-01-01

Prelaunch mission plans for the INTELSAT V-5 (F-5) commercial communications satellites are summarized. Voice circuits, television channels, and a Maritime Communications Services package for the Maritime Satellite Organization (INMARSAT) to provide ship/shore/ship communications are described.

Packaging strategy for maximizing the performance of a screen printed piezoelectric energy harvester

NASA Astrophysics Data System (ADS)

Zhang, Z.; Zhu, D.; Tudor, M. J.; Beeby, S. P.

2013-12-01

This paper reports the extended design and simulation of a screen printed piezoelectric energy harvester. The proposed design was based on a previous credit card sized smart tag sensor node, and packages the power conditioning circuit in the free space above the tungsten proof mass layer. This approach enables electronic components to be mounted onto the cantilever beam, which provides additional weight at the tip of the cantilever structure. The design structure contains a T-shape cantilever beam with size of 47 mm × 30 mm × 0.85 mm which is fabricated using screen printing. ANSYS simulation results predict the revised architecture can generate 421.9 μW approximately twice of the RMS power produced by the original design along with a higher open-circuit RMS Voltage of 8.0 V while the resonant frequency is dropped to 53.4 Hz.

Fully Solution-Processable Fabrication of Multi-Layered Circuits on a Flexible Substrate Using Laser Processing

PubMed Central

Ji, Seok Young; Choi, Wonsuk; Jeon, Jin-Woo; Chang, Won Seok

2018-01-01

The development of printing technologies has enabled the realization of electric circuit fabrication on a flexible substrate. However, the current technique remains restricted to single-layer patterning. In this paper, we demonstrate a fully solution-processable patterning approach for multi-layer circuits using a combined method of laser sintering and ablation. Selective laser sintering of silver (Ag) nanoparticle-based ink is applied to make conductive patterns on a heat-sensitive substrate and insulating layer. The laser beam path and irradiation fluence are controlled to create circuit patterns for flexible electronics. Microvia drilling using femtosecond laser through the polyvinylphenol-film insulating layer by laser ablation, as well as sequential coating of Ag ink and laser sintering, achieves an interlayer interconnection between multi-layer circuits. The dimension of microvia is determined by a sophisticated adjustment of the laser focal position and intensity. Based on these methods, a flexible electronic circuit with chip-size-package light-emitting diodes was successfully fabricated and demonstrated to have functional operations. PMID:29425144

Contributions of the German Research Center for Geosciences (GFZ) to the EPOS (European Plate Observing System) Implementation Phase 2015-18

NASA Astrophysics Data System (ADS)

Hoffmann, T. L.; Lauterjung, J.

2017-12-01

The European Plate Observing System project is currently approaching the end of year two of its four-year Implementation Phase 2015-18 (EPOS-IP). Under the Horizon 2020 Programme INFRADEV-3, the EPOS cyberinfrastructure is being established as an ERIC (European Research Infrastructure Consortium) and encompasses the implementation of both the EPOS Integrated Core Services (ICS) for solid Earth Science and a multitude of EPOS Thematic Core Services (TCS). During year two, a basic set of ICS and TCS services was developed and implemented, so that in October 2017 the validation phase (year 3) of EPOS is ready to be launched. Up to now, various TCS-Elements have integrated different Service Providers (SD) that are delivering Data, Data Products, Services and Software (DDSS) to their specific scientific community. As one of the 29 awardees of the EC grant, the German Research Center for Geosciences (GFZ) plays an important role in the implementation of EPOS and its Thematic and Integrated Core Services. The presented poster will give an overview of GFZ's participation in the work of nine technical EPOS Work Packages (WP7 ICS Development, WP8 Seismology, WP11 Volcano Observations, WP12 Satellite Data, WP13 Geomagnetic Observations, WP14 Anthropogenic Hazards, WP15 Geological Information and Modelling, WP16 Multi-Scale Laboratories and WP17 Geo Energy Test Beds) as well as in four administrative EPOS Work Packages (WP2 Communication, WP3 Harmonization, WP4 Legal & Governance, and WP5 Financial).