Agile high resolution arbitrary waveform generator with jitterless frequency stepping

DOEpatents

Reilly, Peter T. A.; Koizumi, Hideya

2010-05-11

Jitterless transition of the programmable clock waveform is generated employing a set of two coupled direct digital synthesis (DDS) circuits. The first phase accumulator in the first DDS circuit runs at least one cycle of a common reference clock for the DDS circuits ahead of the second phase accumulator in the second DDS circuit. As a phase transition through the beginning of a phase cycle is detected from the first phase accumulator, a first phase offset word and a second phase offset word for the first and second phase accumulators are calculated and loaded into the first and second DDS circuits. The programmable clock waveform is employed as a clock input for the RAM address controller. A well defined jitterless transition in frequency of the arbitrary waveform is provided which coincides with the beginning of the phase cycle of the DDS output signal from the second DDS circuit.

Printed wiring board system programmer's manual

NASA Technical Reports Server (NTRS)

Brinkerhoff, C. D.

1973-01-01

The printed wiring board system provides automated techniques for the design of printed circuit boards and hybrid circuit boards. The system consists of four programs: (1) the preprocessor program combines user supplied data and pre-defined library data to produce the detailed circuit description data; (2) the placement program assigns circuit components to specific areas of the board in a manner that optimizes the total interconnection length of the circuit; (3) the organizer program assigns pin interconnections to specific board levels and determines the optimal order in which the router program should attempt to layout the paths connecting the pins; and (4) the router program determines the wire paths which are to be used to connect each input pin pair on the circuit board. This document is intended to serve as a programmer's reference manual for the printed wiring board system. A detailed description of the internal logic and flow of the printed wiring board programs is included.

Engineering Synthetic Gene Circuits in Living Cells with CRISPR Technology.

PubMed

Jusiak, Barbara; Cleto, Sara; Perez-Piñera, Pablo; Lu, Timothy K

2016-07-01

One of the goals of synthetic biology is to build regulatory circuits that control cell behavior, for both basic research purposes and biomedical applications. The ability to build transcriptional regulatory devices depends on the availability of programmable, sequence-specific, and effective synthetic transcription factors (TFs). The prokaryotic clustered regularly interspaced short palindromic repeat (CRISPR) system, recently harnessed for transcriptional regulation in various heterologous host cells, offers unprecedented ease in designing synthetic TFs. We review how CRISPR can be used to build synthetic gene circuits and discuss recent advances in CRISPR-mediated gene regulation that offer the potential to build increasingly complex, programmable, and efficient gene circuits in the future. Copyright © 2016. Published by Elsevier Ltd.

All optical programmable logic array (PLA)

NASA Astrophysics Data System (ADS)

Hiluf, Dawit

2018-03-01

A programmable logic array (PLA) is an integrated circuit (IC) logic device that can be reconfigured to implement various kinds of combinational logic circuits. The device has a number of AND and OR gates which are linked together to give output or further combined with more gates or logic circuits. This work presents the realization of PLAs via the physics of a three level system interacting with light. A programmable logic array is designed such that a number of different logical functions can be combined as a sum-of-product or product-of-sum form. We present an all optical PLAs with the aid of laser light and observables of quantum systems, where encoded information can be considered as memory chip. The dynamics of the physical system is investigated using Lie algebra approach.

Programmable nanowire circuits for nanoprocessors.

PubMed

Yan, Hao; Choe, Hwan Sung; Nam, SungWoo; Hu, Yongjie; Das, Shamik; Klemic, James F; Ellenbogen, James C; Lieber, Charles M

2011-02-10

A nanoprocessor constructed from intrinsically nanometre-scale building blocks is an essential component for controlling memory, nanosensors and other functions proposed for nanosystems assembled from the bottom up. Important steps towards this goal over the past fifteen years include the realization of simple logic gates with individually assembled semiconductor nanowires and carbon nanotubes, but with only 16 devices or fewer and a single function for each circuit. Recently, logic circuits also have been demonstrated that use two or three elements of a one-dimensional memristor array, although such passive devices without gain are difficult to cascade. These circuits fall short of the requirements for a scalable, multifunctional nanoprocessor owing to challenges in materials, assembly and architecture on the nanoscale. Here we describe the design, fabrication and use of programmable and scalable logic tiles for nanoprocessors that surmount these hurdles. The tiles were built from programmable, non-volatile nanowire transistor arrays. Ge/Si core/shell nanowires coupled to designed dielectric shells yielded single-nanowire, non-volatile field-effect transistors (FETs) with uniform, programmable threshold voltages and the capability to drive cascaded elements. We developed an architecture to integrate the programmable nanowire FETs and define a logic tile consisting of two interconnected arrays with 496 functional configurable FET nodes in an area of ∼960 μm(2). The logic tile was programmed and operated first as a full adder with a maximal voltage gain of ten and input-output voltage matching. Then we showed that the same logic tile can be reprogrammed and used to demonstrate full-subtractor, multiplexer, demultiplexer and clocked D-latch functions. These results represent a significant advance in the complexity and functionality of nanoelectronic circuits built from the bottom up with a tiled architecture that could be cascaded to realize fully integrated nanoprocessors with computing, memory and addressing capabilities.

Optical programmable Boolean logic unit.

PubMed

Chattopadhyay, Tanay

2011-11-10

Logic units are the building blocks of many important computational operations likes arithmetic, multiplexer-demultiplexer, radix conversion, parity checker cum generator, etc. Multifunctional logic operation is very much essential in this respect. Here a programmable Boolean logic unit is proposed that can perform 16 Boolean logical operations from a single optical input according to the programming input without changing the circuit design. This circuit has two outputs. One output is complementary to the other. Hence no loss of data can occur. The circuit is basically designed by a 2×2 polarization independent optical cross bar switch. Performance of the proposed circuit has been achieved by doing numerical simulations. The binary logical states (0,1) are represented by the absence of light (null) and presence of light, respectively.

Rapid evolution of analog circuits configured on a field programmable transistor array

NASA Technical Reports Server (NTRS)

Stoica, A.; Ferguson, M. I.; Zebulum, R. S.; Keymeulen, D.; Duong, V.; Daud, T.

2002-01-01

The purpose of this paper is to illustrate evolution of analog circuits on a stand-alone board-level evolvable system (SABLES). SABLES is part of an effort to achieve integrated evolvable systems. SABLES provides autonomous, fast (tens to hundreds of seconds), on-chip circuit evolution involving about 100,000 circuit evaluations. Its main components are a JPL Field Programmable Transistor Array (FPTA) chip used as transistor-level reconfigurable hardware, and a TI DSP that implements the evolutionary algorithm controlling the FPTA reconfiguration. The paper details an example of evolution on SABLES and points out to certain transient and memory effects that affect the stability of solutions obtained reusing the same piece of hardware for rapid testing of individuals during evolution.

Toward Evolvable Hardware Chips: Experiments with a Programmable Transistor Array

NASA Technical Reports Server (NTRS)

Stoica, Adrian

1998-01-01

Evolvable Hardware is reconfigurable hardware that self-configures under the control of an evolutionary algorithm. We search for a hardware configuration can be performed using software models or, faster and more accurate, directly in reconfigurable hardware. Several experiments have demonstrated the possibility to automatically synthesize both digital and analog circuits. The paper introduces an approach to automated synthesis of CMOS circuits, based on evolution on a Programmable Transistor Array (PTA). The approach is illustrated with a software experiment showing evolutionary synthesis of a circuit with a desired DC characteristic. A hardware implementation of a test PTA chip is then described, and the same evolutionary experiment is performed on the chip demonstrating circuit synthesis/self-configuration directly in hardware.

Programmable resistive-switch nanowire transistor logic circuits.

PubMed

Shim, Wooyoung; Yao, Jun; Lieber, Charles M

2014-09-10

Programmable logic arrays (PLA) constitute a promising architecture for developing increasingly complex and functional circuits through nanocomputers from nanoscale building blocks. Here we report a novel one-dimensional PLA element that incorporates resistive switch gate structures on a semiconductor nanowire and show that multiple elements can be integrated to realize functional PLAs. In our PLA element, the gate coupling to the nanowire transistor can be modulated by the memory state of the resistive switch to yield programmable active (transistor) or inactive (resistor) states within a well-defined logic window. Multiple PLA nanowire elements were integrated and programmed to yield a working 2-to-4 demultiplexer with long-term retention. The well-defined, controllable logic window and long-term retention of our new one-dimensional PLA element provide a promising route for building increasingly complex circuits with nanoscale building blocks.

Programmable Pulser

NASA Technical Reports Server (NTRS)

Baumann, Eric; Merolla, Anthony

1988-01-01

User controls number of clock pulses to prevent burnout. New digital programmable pulser circuit in three formats; freely running, counted, and single pulse. Operates at frequencies up to 5 MHz, with no special consideration given to layout of components or to terminations. Pulser based on sequential circuit with four states and binary counter with appropriate decoding logic. Number of programmable pulses increased beyond 127 by addition of another counter and decoding logic. For very large pulse counts and/or very high frequencies, use synchronous counters to avoid errors caused by propagation delays. Invaluable tool for initial verification or diagnosis of digital or digitally controlled circuity.

A Digitally Programmable Cytomorphic Chip for Simulation of Arbitrary Biochemical Reaction Networks.

PubMed

Woo, Sung Sik; Kim, Jaewook; Sarpeshkar, Rahul

2018-04-01

Prior work has shown that compact analog circuits can faithfully represent and model fundamental biomolecular circuits via efficient log-domain cytomorphic transistor equivalents. Such circuits have emphasized basis functions that are dominant in genetic transcription and translation networks and deoxyribonucleic acid (DNA)-protein binding. Here, we report a system featuring digitally programmable 0.35 μm BiCMOS analog cytomorphic chips that enable arbitrary biochemical reaction networks to be exactly represented thus enabling compact and easy composition of protein networks as well. Since all biomolecular networks can be represented as chemical reaction networks, our protein networks also include the former genetic network circuits as a special case. The cytomorphic analog protein circuits use one fundamental association-dissociation-degradation building-block circuit that can be configured digitally to exactly represent any zeroth-, first-, and second-order reaction including loading, dynamics, nonlinearity, and interactions with other building-block circuits. To address a divergence issue caused by random variations in chip fabrication processes, we propose a unique way of performing computation based on total variables and conservation laws, which we instantiate at both the circuit and network levels. Thus, scalable systems that operate with finite error over infinite time can be built. We show how the building-block circuits can be composed to form various network topologies, such as cascade, fan-out, fan-in, loop, dimerization, or arbitrary networks using total variables. We demonstrate results from a system that combines interacting cytomorphic chips to simulate a cancer pathway and a glycolysis pathway. Both simulations are consistent with conventional software simulations. Our highly parallel digitally programmable analog cytomorphic systems can lead to a useful design, analysis, and simulation tool for studying arbitrary large-scale biological networks in systems and synthetic biology.

Programmable electronic synthesized capacitance

NASA Technical Reports Server (NTRS)

Kleinberg, Leonard L. (Inventor)

1987-01-01

A predetermined and variable synthesized capacitance which may be incorporated into the resonant portion of an electronic oscillator for the purpose of tuning the oscillator comprises a programmable operational amplifier circuit. The operational amplifier circuit has its output connected to its inverting input, in a follower configuration, by a network which is low impedance at the operational frequency of the circuit. The output of the operational amplifier is also connected to the noninverting input by a capacitor. The noninverting input appears as a synthesized capacitance which may be varied with a variation in gain-bandwidth product of the operational amplifier circuit. The gain-bandwidth product may, in turn, be varied with a variation in input set current with a digital to analog converter whose output is varied with a command word. The output impedance of the circuit may also be varied by the output set current. This circuit may provide very small ranges in oscillator frequency with relatively large control voltages unaffected by noise.

Radiation Hardened 10BASE-T Ethernet Physical Layer (PHY)

NASA Technical Reports Server (NTRS)

Lin, Michael R. (Inventor); Petrick, David J. (Inventor); Ballou, Kevin M. (Inventor); Espinosa, Daniel C. (Inventor); James, Edward F. (Inventor); Kliesner, Matthew A. (Inventor)

2017-01-01

Embodiments may provide a radiation hardened 10BASE-T Ethernet interface circuit suitable for space flight and in compliance with the IEEE 802.3 standard for Ethernet. The various embodiments may provide a 10BASE-T Ethernet interface circuit, comprising a field programmable gate array (FPGA), a transmitter circuit connected to the FPGA, a receiver circuit connected to the FPGA, and a transformer connected to the transmitter circuit and the receiver circuit. In the various embodiments, the FPGA, transmitter circuit, receiver circuit, and transformer may be radiation hardened.

A Low-Cost CMOS Programmable Temperature Switch

PubMed Central

Li, Yunlong; Wu, Nanjian

2008-01-01

A novel uncalibrated CMOS programmable temperature switch with high temperature accuracy is presented. Its threshold temperature Tth can be programmed by adjusting the ratios of width and length of the transistors. The operating principles of the temperature switch circuit is theoretically explained. A floating gate neural MOS circuit is designed to compensate automatically the threshold temperature Tth variation that results form the process tolerance. The switch circuit is implemented in a standard 0.35 μm CMOS process. The temperature switch can be programmed to perform the switch operation at 16 different threshold temperature Tths from 45—120°C with a 5°C increment. The measurement shows a good consistency in the threshold temperatures. The chip core area is 0.04 mm2 and power consumption is 3.1 μA at 3.3V power supply. The advantages of the temperature switch are low power consumption, the programmable threshold temperature and the controllable hysteresis. PMID:27879871

A programmable heater control circuit for spacecraft

NASA Technical Reports Server (NTRS)

Nguyen, D. D.; Owen, J. W.; Smith, D. A.; Lewter, W. J.

1994-01-01

Spacecraft thermal control is accomplished for many components through use of multilayer insulation systems, electrical heaters, and radiator systems. The heaters are commanded to maintain component temperatures within design specifications. The programmable heater control circuit (PHCC) was designed to obtain an effective and efficient means of spacecraft thermal control. The hybrid circuit provides use of control instrumentation as temperature data, available to the spacecraft central data system, reprogramming capability of the local microprocessor during the spacecraft's mission, and the elimination of significant spacecraft wiring. The hybrid integrated circuit has a temperature sensing and conditioning circuit, a microprocessor, and a heater power and control circuit. The device is miniature and housed in a volume which allows physical integration with the component to be controlled. Applications might include alternate battery-powered logic-circuit configurations. A prototype unit with appropriate physical and functional interfaces was procured for testing. The physical functionality and the feasibility of fabrication of the hybrid integrated circuit were successfully verified. The remaining work to develop a flight-qualified device includes fabrication and testing of a Mil-certified part. An option for completing the PHCC flight qualification testing is to enter into a joint venture with industry.

Postirradiation Effects In Integrated Circuits

NASA Technical Reports Server (NTRS)

Shaw, David C.; Barnes, Charles E.

1993-01-01

Two reports discuss postirradiation effects in integrated circuits. Presents examples of postirradiation measurements of performances of integrated circuits of five different types: dual complementary metal oxide/semiconductor (CMOS) flip-flop; CMOS analog multiplier; two CMOS multiplying digital-to-analog converters; electrically erasable programmable read-only memory; and semiconductor/oxide/semiconductor octal buffer driver.

Flexible programmable logic module

DOEpatents

Robertson, Perry J.; Hutchinson, Robert L.; Pierson, Lyndon G.

2001-01-01

The circuit module of this invention is a VME board containing a plurality of programmable logic devices (PLDs), a controlled impedance clock tree, and interconnecting buses. The PLDs are arranged to permit systolic processing of a problem by offering wide data buses and a plurality of processing nodes. The board contains a clock reference and clock distribution tree that can drive each of the PLDs with two critically timed clock references. External clock references can be used to drive additional circuit modules all operating from the same synchronous clock reference.

A programmable CCD driver circuit for multiphase CCD operation

NASA Technical Reports Server (NTRS)

Ewin, Audrey J.; Reed, Kenneth V.

1989-01-01

A programmable CCD (charge-coupled device) driver circuit was designed to drive CCDs in multiphased modes. The purpose of the drive electronics is to operate developmental CCD imaging arrays for NASA's tiltable moderate resolution imaging spectrometer (MODIS-T). Five objectives for the driver were considered during its design: (1) the circuit drives CCD electrode voltages between 0 V and +30 V to produce reasonable potential wells, (2) the driving sequence is started with one input signal, (3) the driving sequence is started with one input signal, (4) the circuit allows programming of frame sequences required by arrays of any size, (5) it produces interfacing signals for the CCD and the DTF (detector test facility). Simulation of the driver verified its function with the master clock running up to 10 MHz. This suggests a maximum rate of 400,000 pixels/s. Timing and packaging parameters were verified. The design uses 54 TTL (transistor-transistor logic) chips. Two versions of hardware were fabricated: wirewrap and printed circuit board. Both were verified functionally with a logic analyzer.

A Uniform Approach to Type Theory

DTIC Science & Technology

1989-01-01

logical and statistical techniques. There is no comprehensive survey on implementation issues. Some partial aspects are described in...U. de Paris (1930). In: Ecrits logiques de Jacques Herbrand, PUF Paris (1968). [71] C. M. Hoffmann, M. J. O’Donnell. "Programming with Equations

SENARIET, A Programme To Solve Transient Flows Of Liquids In Complex Circuits

NASA Astrophysics Data System (ADS)

Vargas-Munoz, M.; Rodriguez-Fernandez, M.; Perena-Tapiador, A.

2011-05-01

SENARIET is a programme to study fluid transients in pipeline systems in order to obtain pressure and velocity distributions along a circuit. When a transient process occurs in periods of the same order of the pressure waves’ travelling time along a circuit (the order of the circuit length divided by the effective propagation speed), the compressibility effects in liquids have to be considered. Taking this effect into account, the appropriate equations of continuity and momentum are solved by the method of characteristics, to obtain pressure and velocity along pipes as a function of time. The simulated results have been compared to theoretical and experimental ones to validate and evaluate the precision of the software. The results help to perform efficient and accurate predictions in order to define the propulsion sub-system. This type of analysis is very important in order to evaluate the water hammer effects in propulsion systems used on spacecrafts and launchers.

Experiences in Digital Circuit Design Courses: A Self-Study Platform for Learning Support

ERIC Educational Resources Information Center

Bañeres, David; Clarisó, Robert; Jorba, Josep; Serra, Montse

2014-01-01

The synthesis of digital circuits is a basic skill in all the bachelor programmes around the ICT area of knowledge, such as Computer Science, Telecommunication Engineering or Electrical Engineering. An important hindrance in the learning process of this skill is that the existing educational tools for the design of circuits do not allow the…

The Pragmatics of Critiquing

DTIC Science & Technology

2006-02-01

philosophie (logique et argumentation), de la linguistique, de la psychologie et de la sociologie , ce document propose une étude de la critique...linguistique, de la psychologie et de la sociologie . Elle présente une revue exhaustive de l’analyse de l’argument et de l’argumentation qui nous

Analog hardware for delta-backpropagation neural networks

NASA Technical Reports Server (NTRS)

Eberhardt, Silvio P. (Inventor)

1992-01-01

This is a fully parallel analog backpropagation learning processor which comprises a plurality of programmable resistive memory elements serving as synapse connections whose values can be weighted during learning with buffer amplifiers, summing circuits, and sample-and-hold circuits arranged in a plurality of neuron layers in accordance with delta-backpropagation algorithms modified so as to control weight changes due to circuit drift.

On Polymorphic Circuits and Their Design Using Evolutionary Algorithms

NASA Technical Reports Server (NTRS)

Stoica, Adrian; Zebulum, Ricardo; Keymeulen, Didier; Lohn, Jason; Clancy, Daniel (Technical Monitor)

2002-01-01

This paper introduces the concept of polymorphic electronics (polytronics) - referring to electronics with superimposed built-in functionality. A function change does not require switches/reconfiguration as in traditional approaches. Instead the change comes from modifications in the characteristics of devices involved in the circuit, in response to controls such as temperature, power supply voltage (VDD), control signals, light, etc. The paper illustrates polytronic circuits in which the control is done by temperature, morphing signals, and VDD respectively. Polytronic circuits are obtained by evolutionary design/evolvable hardware techniques. These techniques are ideal for the polytronics design, a new area that lacks design guidelines, know-how,- yet the requirements/objectives are easy to specify and test. The circuits are evolved/synthesized in two different modes. The first mode explores an unstructured space, in which transistors can be interconnected freely in any arrangement (in simulations only). The second mode uses a Field Programmable Transistor Array (FPTA) model, and the circuit topology is sought as a mapping onto a programmable architecture (these experiments are performed both in simulations and on FPTA chips). The experiments demonstrated the synthesis. of polytronic circuits by evolution. The capacity of storing/hiding "extra" functions provides for watermark/invisible functionality, thus polytronics may find uses in intelligence/security applications.

EHWPACK: An evolvable hardware environment using the SPICE simulator and the Field Programmable Transistor Array

NASA Technical Reports Server (NTRS)

Keymeulen, D.; Klimeck, G.; Zebulum, R.; Stoica, A.; Jin, Y.; Lazaro, C.

2000-01-01

This paper describes the EHW development system, a tool that performs the evolutionary synthesis of electronic circuits, using the SPICE simulator and the Field Programmable Transistor Array hardware (FPTA) developed at JPL.

The Feasibility and Acceptability to Service Users of CIRCuiTS, a Computerized Cognitive Remediation Therapy Programme for Schizophrenia.

PubMed

Reeder, Clare; Pile, Victoria; Crawford, Polly; Cella, Matteo; Rose, Diana; Wykes, Til; Watson, Andrew; Huddy, Vyv; Callard, Felicity

2016-05-01

Cognitive remediation (CR) is a psychological therapy, effective in improving cognitive performance and functioning in people with schizophrenia. As the therapy becomes more widely implemented within mental health services its longevity and uptake is likely to depend on its feasibility and acceptability to service users and clinicians. To assess the feasibility and acceptability of a new strategy-based computerized CR programme (CIRCuiTS) for people with psychosis. Four studies were conducted using mixed methods. Perceptions of attractiveness, comprehensibility, acceptability and usability were assessed using self-report questionnaires in 34 non-clinical participants (study 1), and five people with a schizophrenia diagnosis and three experienced CR therapists (studies 2 and 3). The ease with which pre-specified therapy programmes could be assembled was also assessed by three therapists (Study 2). Finally, the satisfaction of 20 service users with a diagnosis of schizophrenia regarding their experience of using CIRCuiTS in the context of a course of the CR therapy was assessed in a qualitative interview study (study 4). Ratings of perceived attractiveness, comprehensibility, acceptability and usability consistently exceeded pre-set high targets by non-clinical, clinical and therapist participants. Qualitative analysis of satisfaction with CIRCuiTS showed that receiving the therapy was generally seen to be a positive experience, leading to perceptions that cognitive functioning had improved and attempts to incorporate new strategy use into daily activities. CIRCuiTS demonstrates high acceptability and ease of use for both service users with a schizophrenia diagnosis and clinicians.

Logique des langues europeennes VII: Le Neerlandais et le polder (Logic of European Languages VII: Dutch and the Polder).

ERIC Educational Resources Information Center

Van Lier, Henri

1990-01-01

Views the Dutch language as analogous to the polder typical of the Netherlands, an area of low-lying land reclaimed from a body of water and protected by dikes. Phonological, morphological, syntactic, semantic, and stylistic analyses are presented. (MSE)

A Hearing Aid Primer 1

ERIC Educational Resources Information Center

Yetter, Carol J.

2009-01-01

This hearing aid primer is designed to define the differences among the three levels of hearing instrument technology: conventional analog circuit technology (most basic), digitally programmable/analog circuit technology (moderately advanced), and fully digital technology (most advanced). Both moderate and advanced technologies mean that hearing…

High speed, long distance, data transmission multiplexing circuit

DOEpatents

Mariotti, Razvan

1991-01-01

A high speed serial data transmission multiplexing circuit, which is operable to accurately transmit data over long distances (up to 3 Km), and to multiplex, select and continuously display real time analog signals in a bandwidth from DC to 100 Khz. The circuit is made fault tolerant by use of a programmable flywheel algorithm, which enables the circuit to tolerate one transmission error before losing synchronization of the transmitted frames of data. A method of encoding and framing captured and transmitted data is used which has a low overhead and prevents some particular transmitted data patterns from locking an included detector/decoder circuit.

The evolvability of programmable hardware.

PubMed

Raman, Karthik; Wagner, Andreas

2011-02-06

In biological systems, individual phenotypes are typically adopted by multiple genotypes. Examples include protein structure phenotypes, where each structure can be adopted by a myriad individual amino acid sequence genotypes. These genotypes form vast connected 'neutral networks' in genotype space. The size of such neutral networks endows biological systems not only with robustness to genetic change, but also with the ability to evolve a vast number of novel phenotypes that occur near any one neutral network. Whether technological systems can be designed to have similar properties is poorly understood. Here we ask this question for a class of programmable electronic circuits that compute digital logic functions. The functional flexibility of such circuits is important in many applications, including applications of evolutionary principles to circuit design. The functions they compute are at the heart of all digital computation. We explore a vast space of 10(45) logic circuits ('genotypes') and 10(19) logic functions ('phenotypes'). We demonstrate that circuits that compute the same logic function are connected in large neutral networks that span circuit space. Their robustness or fault-tolerance varies very widely. The vicinity of each neutral network contains circuits with a broad range of novel functions. Two circuits computing different functions can usually be converted into one another via few changes in their architecture. These observations show that properties important for the evolvability of biological systems exist in a commercially important class of electronic circuitry. They also point to generic ways to generate fault-tolerant, adaptable and evolvable electronic circuitry.

The evolvability of programmable hardware

PubMed Central

Raman, Karthik; Wagner, Andreas

2011-01-01

In biological systems, individual phenotypes are typically adopted by multiple genotypes. Examples include protein structure phenotypes, where each structure can be adopted by a myriad individual amino acid sequence genotypes. These genotypes form vast connected ‘neutral networks’ in genotype space. The size of such neutral networks endows biological systems not only with robustness to genetic change, but also with the ability to evolve a vast number of novel phenotypes that occur near any one neutral network. Whether technological systems can be designed to have similar properties is poorly understood. Here we ask this question for a class of programmable electronic circuits that compute digital logic functions. The functional flexibility of such circuits is important in many applications, including applications of evolutionary principles to circuit design. The functions they compute are at the heart of all digital computation. We explore a vast space of 1045 logic circuits (‘genotypes’) and 1019 logic functions (‘phenotypes’). We demonstrate that circuits that compute the same logic function are connected in large neutral networks that span circuit space. Their robustness or fault-tolerance varies very widely. The vicinity of each neutral network contains circuits with a broad range of novel functions. Two circuits computing different functions can usually be converted into one another via few changes in their architecture. These observations show that properties important for the evolvability of biological systems exist in a commercially important class of electronic circuitry. They also point to generic ways to generate fault-tolerant, adaptable and evolvable electronic circuitry. PMID:20534598

A novel FPGA-programmable switch matrix interconnection element in quantum-dot cellular automata

NASA Astrophysics Data System (ADS)

Hashemi, Sara; Rahimi Azghadi, Mostafa; Zakerolhosseini, Ali; Navi, Keivan

2015-04-01

The Quantum-dot cellular automata (QCA) is a novel nanotechnology, promising extra low-power, extremely dense and very high-speed structure for the construction of logical circuits at a nanoscale. In this paper, initially previous works on QCA-based FPGA's routing elements are investigated, and then an efficient, symmetric and reliable QCA programmable switch matrix (PSM) interconnection element is introduced. This element has a simple structure and offers a complete routing capability. It is implemented using a bottom-up design approach that starts from a dense and high-speed 2:1 multiplexer and utilise it to build the target PSM interconnection element. In this study, simulations of the proposed circuits are carried out using QCAdesigner, a layout and simulation tool for QCA circuits. The results demonstrate high efficiency of the proposed designs in QCA-based FPGA routing.

Silicon photonic integrated circuits with electrically programmable non-volatile memory functions.

PubMed

Song, J-F; Lim, A E-J; Luo, X-S; Fang, Q; Li, C; Jia, L X; Tu, X-G; Huang, Y; Zhou, H-F; Liow, T-Y; Lo, G-Q

2016-09-19

Conventional silicon photonic integrated circuits do not normally possess memory functions, which require on-chip power in order to maintain circuit states in tuned or field-configured switching routes. In this context, we present an electrically programmable add/drop microring resonator with a wavelength shift of 426 pm between the ON/OFF states. Electrical pulses are used to control the choice of the state. Our experimental results show a wavelength shift of 2.8 pm/ms and a light intensity variation of ~0.12 dB/ms for a fixed wavelength in the OFF state. Theoretically, our device can accommodate up to 65 states of multi-level memory functions. Such memory functions can be integrated into wavelength division mutiplexing (WDM) filters and applied to optical routers and computing architectures fulfilling large data downloading demands.

Efficient Multiplexer FPGA Block Structures Based on G4FETs

NASA Technical Reports Server (NTRS)

Vatan, Farrokh; Fijany, Amir

2009-01-01

Generic structures have been conceived for multiplexer blocks to be implemented in field-programmable gate arrays (FPGAs) based on four-gate field-effect transistors (G(sup 4)FETs). This concept is a contribution to the continuing development of digital logic circuits based on G4FETs and serves as a further demonstration that logic circuits based on G(sup 4)FETs could be more efficient (in the sense that they could contain fewer transistors), relative to functionally equivalent logic circuits based on conventional transistors. Results in this line of development at earlier stages were summarized in two previous NASA Tech Briefs articles: "G(sup 4)FETs as Universal and Programmable Logic Gates" (NPO-41698), Vol. 31, No. 7 (July 2007), page 44, and "Efficient G4FET-Based Logic Circuits" (NPO-44407), Vol. 32, No. 1 ( January 2008), page 38 . As described in the first-mentioned previous article, a G4FET can be made to function as a three-input NOT-majority gate, which has been shown to be a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer components than are required for conventional transistor-based circuits performing the same logic functions. The second-mentioned previous article reported results of a comparative study of NOT-majority-gate (G(sup 4)FET)-based logic-circuit designs and equivalent NOR- and NAND-gate-based designs utilizing conventional transistors. [NOT gates (inverters) were also included, as needed, in both the G(sup 4)FET- and the NOR- and NAND-based designs.] In most of the cases studied, fewer logic gates (and, hence, fewer transistors), were required in the G(sup 4)FET-based designs. There are two popular categories of FPGA block structures or architectures: one based on multiplexers, the other based on lookup tables. In standard multiplexer- based architectures, the basic building block is a tree-like configuration of multiplexers, with possibly a few additional logic gates such as ANDs or ORs. Interconnections are realized by means of programmable switches that may connect the input terminals of a block to output terminals of other blocks, may bridge together some of the inputs, or may connect some of the input terminals to signal sources representing constant logical levels 0 or 1. The left part of the figure depicts a four-to-one G(sup 4)FET-based multiplexer tree; the right part of the figure depicts a functionally equivalent four-to-one multiplexer based on conventional transistors. The G(sup 4)FET version would contains 54 transistors; the conventional version contains 70 transistors.

The Value of the "Blueprint" Festival

ERIC Educational Resources Information Center

Cawley-Gelling, India; Hyland, Steven; McCarron-Roberts, Connah; Noor, Sufea Mohamad; Morrissey, Ruth

2015-01-01

"Blueprint" was a three-day festival which took place at Tate Liverpool in July 2014 and was organised and produced by Tate Collective Liverpool, as part of "Circuit", a four-year national programme connecting 15-25 year olds to the arts. "Circuit" aims to be open, reflective and critical and bring about…

Programmable dispersion on a photonic integrated circuit for classical and quantum applications.

PubMed

Notaros, Jelena; Mower, Jacob; Heuck, Mikkel; Lupo, Cosmo; Harris, Nicholas C; Steinbrecher, Gregory R; Bunandar, Darius; Baehr-Jones, Tom; Hochberg, Michael; Lloyd, Seth; Englund, Dirk

2017-09-04

We demonstrate a large-scale tunable-coupling ring resonator array, suitable for high-dimensional classical and quantum transforms, in a CMOS-compatible silicon photonics platform. The device consists of a waveguide coupled to 15 ring-based dispersive elements with programmable linewidths and resonance frequencies. The ability to control both quality factor and frequency of each ring provides an unprecedented 30 degrees of freedom in dispersion control on a single spatial channel. This programmable dispersion control system has a range of applications, including mode-locked lasers, quantum key distribution, and photon-pair generation. We also propose a novel application enabled by this circuit - high-speed quantum communications using temporal-mode-based quantum data locking - and discuss the utility of the system for performing the high-dimensional unitary optical transformations necessary for a quantum data locking demonstration.

Digital MOS integrated circuits

NASA Astrophysics Data System (ADS)

Elmasry, M. I.

MOS in digital circuit design is considered along with aspects of digital VLSI, taking into account a comparison of MOSFET logic circuits, 1-micrometer MOSFET VLSI technology, a generalized guide for MOSFET miniaturization, processing technologies, novel circuit structures for VLSI, and questions of circuit and system design for VLSI. MOS memory cells and circuits are discussed, giving attention to a survey of high-density dynamic RAM cell concepts, one-device cells for dynamic random-access memories, variable resistance polysilicon for high density CMOS Ram, high performance MOS EPROMs using a stacked-gate cell, and the optimization of the latching pulse for dynamic flip-flop sensors. Programmable logic arrays are considered along with digital signal processors, microprocessors, static RAMs, and dynamic RAMs.

Analog Delta-Back-Propagation Neural-Network Circuitry

NASA Technical Reports Server (NTRS)

Eberhart, Silvio

1990-01-01

Changes in synapse weights due to circuit drifts suppressed. Proposed fully parallel analog version of electronic neural-network processor based on delta-back-propagation algorithm. Processor able to "learn" when provided with suitable combinations of inputs and enforced outputs. Includes programmable resistive memory elements (corresponding to synapses), conductances (synapse weights) adjusted during learning. Buffer amplifiers, summing circuits, and sample-and-hold circuits arranged in layers of electronic neurons in accordance with delta-back-propagation algorithm.

Evolutionary Multiobjective Design Targeting a Field Programmable Transistor Array

NASA Technical Reports Server (NTRS)

Aguirre, Arturo Hernandez; Zebulum, Ricardo S.; Coello, Carlos Coello

2004-01-01

This paper introduces the ISPAES algorithm for circuit design targeting a Field Programmable Transistor Array (FPTA). The use of evolutionary algorithms is common in circuit design problems, where a single fitness function drives the evolution process. Frequently, the design problem is subject to several goals or operating constraints, thus, designing a suitable fitness function catching all requirements becomes an issue. Such a problem is amenable for multi-objective optimization, however, evolutionary algorithms lack an inherent mechanism for constraint handling. This paper introduces ISPAES, an evolutionary optimization algorithm enhanced with a constraint handling technique. Several design problems targeting a FPTA show the potential of our approach.

Synthetic biology in mammalian cells: Next generation research tools and therapeutics

PubMed Central

Lienert, Florian; Lohmueller, Jason J; Garg, Abhishek; Silver, Pamela A

2014-01-01

Recent progress in DNA manipulation and gene circuit engineering has greatly improved our ability to programme and probe mammalian cell behaviour. These advances have led to a new generation of synthetic biology research tools and potential therapeutic applications. Programmable DNA-binding domains and RNA regulators are leading to unprecedented control of gene expression and elucidation of gene function. Rebuilding complex biological circuits such as T cell receptor signalling in isolation from their natural context has deepened our understanding of network motifs and signalling pathways. Synthetic biology is also leading to innovative therapeutic interventions based on cell-based therapies, protein drugs, vaccines and gene therapies. PMID:24434884

Tumor Immunotherapy by Gene-circuit Recruited Immunomodulatory Systems (TIGRIS) for Prostate Cancer

DTIC Science & Technology

2017-09-01

Fu, X., Huang, W., and Cai, Z. (2014). Syn- thesizing AND gate genetic circuits based on CRISPR -Cas9 for identification of bladder cancer cells. Nat...and Lu, T.K. (2014). Multi- plexed and programmable regulation of gene networks with an integrated RNA and CRISPR /Cas toolkit in human cells. Mol

Modeling and simulation of floating gate nanocrystal FET devices and circuits

NASA Astrophysics Data System (ADS)

Hasaneen, El-Sayed A. M.

The nonvolatile memory market has been growing very fast during the last decade, especially for mobile communication systems. The Semiconductor Industry Association International Technology Roadmap for Semiconductors states that the difficult challenge for nonvolatile semiconductor memories is to achieve reliable, low power, low voltage performance and high-speed write/erase. This can be achieved by aggressive scaling of the nonvolatile memory cells. Unfortunately, scaling down of conventional nonvolatile memory will further degrade the retention time due to the charge loss between the floating gate and drain/source contacts and substrate which makes conventional nonvolatile memory unattractive. Using nanocrystals as charge storage sites reduces dramatically the charge leakage through oxide defects and drain/source contacts. Floating gate nanocrystal nonvolatile memory, FG-NCNVM, is a candidate for future memory because it is advantageous in terms of high-speed write/erase, small size, good scalability, low-voltage, low-power applications, and the capability to store multiple bits per cell. Many studies regarding FG-NCNVMs have been published. Most of them have dealt with fabrication improvements of the devices and device characterizations. Due to the promising FG-NCNVM applications in integrated circuits, there is a need for circuit a simulation model to simulate the electrical characteristics of the floating gate devices. In this thesis, a FG-NCNVM circuit simulation model has been proposed. It is based on the SPICE BSIM simulation model. This model simulates the cell behavior during normal operation. Model validation results have been presented. The SPICE model shows good agreement with experimental results. Current-voltage characteristics, transconductance and unity gain frequency (fT) have been studied showing the effect of the threshold voltage shift (DeltaVth) due to nanocrystal charge on the device characteristics. The threshold voltage shift due to nanocrystal charge has a strong effect on the memory characteristics. Also, the programming operation of the memory cell has been investigated. The tunneling rate from quantum well channel to quantum dot (nanocrystal) gate is calculated. The calculations include various memory parameters, wavefunctions, and energies of quantum well channel and quantum dot gate. The use of floating gate nanocrystal memory as a transistor with a programmable threshold voltage has been demonstrated. The incorporation of FG-NCFETs to design programmable integrated circuit building blocks has been discussed. This includes the design of programmable current and voltage reference circuits. Finally, we demonstrated the design of tunable gain op-amp incorporating FG-NCFETs. Programmable integrated circuit building blocks can be used in intelligent analog and digital systems.

Sign-And-Magnitude Up/Down Counter

NASA Technical Reports Server (NTRS)

Cole, Steven W.

1991-01-01

Magnitude-and-sign counter includes conventional up/down counter for magnitude part and special additional circuitry for sign part. Negative numbers indicated more directly. Counter implemented by programming erasable programmable logic device (EPLD) or programmable logic array (PLA). Used in place of conventional up/down counter to provide sign and magnitude values directly to other circuits.

Chaos in a neural network circuit

NASA Astrophysics Data System (ADS)

Kepler, Thomas B.; Datt, Sumeet; Meyer, Robert B.; Abott, L. F.

1990-12-01

We have constructed a neural network circuit of four clipped, high-grain, integrating operational amplifiers coupled to each other through an array of digitally programmable resistor ladders (MDACs). In addition to fixed-point and cyclic behavior, the circuit exhibits chaotic behavior with complex strange attractors which are approached through period doubling, intermittent attractor expansion and/or quasiperiodic pathways. Couplings between the nonlinear circuit elements are controlled by a computer which can automatically search through the space of couplings for interesting phenomena. We report some initial statistical results relating the behavior of the network to properties of its coupling matrix. Through these results and further research the circuit should help resolve fundamental issues concerning chaos in neural networks.

A new 4D chaotic system with hidden attractor and its engineering applications: Analog circuit design and field programmable gate array implementation

NASA Astrophysics Data System (ADS)

Abdolmohammadi, Hamid Reza; Khalaf, Abdul Jalil M.; Panahi, Shirin; Rajagopal, Karthikeyan; Pham, Viet-Thanh; Jafari, Sajad

2018-06-01

Nowadays, designing chaotic systems with hidden attractor is one of the most interesting topics in nonlinear dynamics and chaos. In this paper, a new 4D chaotic system is proposed. This new chaotic system has no equilibria, and so it belongs to the category of systems with hidden attractors. Dynamical features of this system are investigated with the help of its state-space portraits, bifurcation diagram, Lyapunov exponents diagram, and basin of attraction. Also a hardware realisation of this system is proposed by using field programmable gate arrays (FPGA). In addition, an electronic circuit design for the chaotic system is introduced.

Programmable Pulse-Position-Modulation Encoder

NASA Technical Reports Server (NTRS)

Zhu, David; Farr, William

2006-01-01

A programmable pulse-position-modulation (PPM) encoder has been designed for use in testing an optical communication link. The encoder includes a programmable state machine and an electronic code book that can be updated to accommodate different PPM coding schemes. The encoder includes a field-programmable gate array (FPGA) that is programmed to step through the stored state machine and code book and that drives a custom high-speed serializer circuit board that is capable of generating subnanosecond pulses. The stored state machine and code book can be updated by means of a simple text interface through the serial port of a personal computer.

Error-rate prediction for programmable circuits: methodology, tools and studied cases

NASA Astrophysics Data System (ADS)

Velazco, Raoul

2013-05-01

This work presents an approach to predict the error rates due to Single Event Upsets (SEU) occurring in programmable circuits as a consequence of the impact or energetic particles present in the environment the circuits operate. For a chosen application, the error-rate is predicted by combining the results obtained from radiation ground testing and the results of fault injection campaigns performed off-beam during which huge numbers of SEUs are injected during the execution of the studied application. The goal of this strategy is to obtain accurate results about different applications' error rates, without using particle accelerator facilities, thus significantly reducing the cost of the sensitivity evaluation. As a case study, this methodology was applied a complex processor, the Power PC 7448 executing a program issued from a real space application and a crypto-processor application implemented in an SRAM-based FPGA and accepted to be embedded in the payload of a scientific satellite of NASA. The accuracy of predicted error rates was confirmed by comparing, for the same circuit and application, predictions with measures issued from radiation ground testing performed at the cyclotron Cyclone cyclotron of HIF (Heavy Ion Facility) of Louvain-la-Neuve (Belgium).

Multipurpose silicon photonics signal processor core.

PubMed

Pérez, Daniel; Gasulla, Ivana; Crudgington, Lee; Thomson, David J; Khokhar, Ali Z; Li, Ke; Cao, Wei; Mashanovich, Goran Z; Capmany, José

2017-09-21

Integrated photonics changes the scaling laws of information and communication systems offering architectural choices that combine photonics with electronics to optimize performance, power, footprint, and cost. Application-specific photonic integrated circuits, where particular circuits/chips are designed to optimally perform particular functionalities, require a considerable number of design and fabrication iterations leading to long development times. A different approach inspired by electronic Field Programmable Gate Arrays is the programmable photonic processor, where a common hardware implemented by a two-dimensional photonic waveguide mesh realizes different functionalities through programming. Here, we report the demonstration of such reconfigurable waveguide mesh in silicon. We demonstrate over 20 different functionalities with a simple seven hexagonal cell structure, which can be applied to different fields including communications, chemical and biomedical sensing, signal processing, multiprocessor networks, and quantum information systems. Our work is an important step toward this paradigm.Integrated optical circuits today are typically designed for a few special functionalities and require complex design and development procedures. Here, the authors demonstrate a reconfigurable but simple silicon waveguide mesh with different functionalities.

Solid state control system for oil well bailer pump

DOE Office of Scientific and Technical Information (OSTI.GOV)

Senghaas, K. A.; Senghaas, P.

1985-05-14

A solid state switching controller for use with various types of oil well bailer pumps. Individually programmable steps with lockouts provide multiple mutual exclusivity between various circuit operations. A trickle charge battery system powers the control circuits. A tank overflow float protects against oil spillage. An automatic production rate adjustment circuit is provided which increases cycle time in proportion to the rate of production. The circuit includes a low power voltage detector for disabling the control circuits until the line voltage is acceptable. A three-phase power and control system with an isolation transformer for the controls avoids unreliable ground connections.more » The timers include a dividing circuit with an RC circuit. All power actuated apparatus are actuated by triac switches which are controlled by an opto driver. The bailer brake is pulse actuated for allowing the bailer to sink into crude oil without excess cable looseness.« less

Integrating DNA strand-displacement circuitry with DNA tile self-assembly

PubMed Central

Zhang, David Yu; Hariadi, Rizal F.; Choi, Harry M.T.; Winfree, Erik

2013-01-01

DNA nanotechnology has emerged as a reliable and programmable way of controlling matter at the nanoscale through the specificity of Watson–Crick base pairing, allowing both complex self-assembled structures with nanometer precision and complex reaction networks implementing digital and analog behaviors. Here we show how two well-developed frameworks, DNA tile self-assembly and DNA strand-displacement circuits, can be systematically integrated to provide programmable kinetic control of self-assembly. We demonstrate the triggered and catalytic isothermal self-assembly of DNA nanotubes over 10 μm long from precursor DNA double-crossover tiles activated by an upstream DNA catalyst network. Integrating more sophisticated control circuits and tile systems could enable precise spatial and temporal organization of dynamic molecular structures. PMID:23756381

Designed cell consortia as fragrance-programmable analog-to-digital converters.

PubMed

Müller, Marius; Ausländer, Simon; Spinnler, Andrea; Ausländer, David; Sikorski, Julian; Folcher, Marc; Fussenegger, Martin

2017-03-01

Synthetic biology advances the rational engineering of mammalian cells to achieve cell-based therapy goals. Synthetic gene networks have nearly reached the complexity of digital electronic circuits and enable single cells to perform programmable arithmetic calculations or to provide dynamic remote control of transgenes through electromagnetic waves. We designed a synthetic multilayered gaseous-fragrance-programmable analog-to-digital converter (ADC) allowing for remote control of digital gene expression with 2-bit AND-, OR- and NOR-gate logic in synchronized cell consortia. The ADC consists of multiple sampling-and-quantization modules sensing analog gaseous fragrance inputs; a gas-to-liquid transducer converting fragrance intensity into diffusible cell-to-cell signaling compounds; a digitization unit with a genetic amplifier circuit to improve the signal-to-noise ratio; and recombinase-based digital expression switches enabling 2-bit processing of logic gates. Synthetic ADCs that can remotely control cellular activities with digital precision may enable the development of novel biosensors and may provide bioelectronic interfaces synchronizing analog metabolic pathways with digital electronics.

Improved Remapping Processor For Digital Imagery

NASA Technical Reports Server (NTRS)

Fisher, Timothy E.

1991-01-01

Proposed digital image processor improved version of Programmable Remapper, which performs geometric and radiometric transformations on digital images. Features include overlapping and variably sized preimages. Overcomes some of limitations of image-warping circuit boards implementing only those geometric tranformations expressible in terms of polynomials of limited order. Also overcomes limitations of existing Programmable Remapper and made to perform transformations at video rate.

The Implementation and Evaluation of a Project-Oriented Problem-Based Learning Module in a First Year Engineering Programme

ERIC Educational Resources Information Center

McLoone, Seamus C.; Lawlor, Bob J.; Meehan, Andrew R.

2016-01-01

This paper describes how a circuits-based project-oriented problem-based learning educational model was integrated into the first year of a Bachelor of Engineering in Electronic Engineering programme at Maynooth University, Ireland. While many variations of problem based learning exist, the presented model is closely aligned with the model used in…

Effectiveness of Resistance Circuit-Based Training for Maximum Oxygen Uptake and Upper-Body One-Repetition Maximum Improvements: A Systematic Review and Meta-Analysis.

PubMed

Muñoz-Martínez, Francisco Antonio; Rubio-Arias, Jacobo Á; Ramos-Campo, Domingo Jesús; Alcaraz, Pedro E

2017-12-01

It is well known that concurrent increases in both maximal strength and aerobic capacity are associated with improvements in sports performance as well as overall health. One of the most popular training methods used for achieving these objectives is resistance circuit-based training. The objective of the present systematic review with a meta-analysis was to evaluate published studies that have investigated the effects of resistance circuit-based training on maximum oxygen uptake and one-repetition maximum of the upper-body strength (bench press exercise) in healthy adults. The following electronic databases were searched from January to June 2016: PubMed, Web of Science and Cochrane. Studies were included if they met the following criteria: (1) examined healthy adults aged between 18 and 65 years; (2) met the characteristics of resistance circuit-based training; and (3) analysed the outcome variables of maximum oxygen uptake using a gas analyser and/or one-repetition maximum bench press. Of the 100 articles found from the database search and after all duplicates were removed, eight articles were analysed for maximum oxygen uptake. Of 118 healthy adults who performed resistance circuit-based training, maximum oxygen uptake was evaluated before and after the training programme. Additionally, from the 308 articles found for one-repetition maximum, eight articles were analysed. The bench press one-repetition maximum load, of 237 healthy adults who performed resistance circuit-based training, was evaluated before and after the training programme. Significant increases in maximum oxygen uptake and one-repetition maximum bench press were observed following resistance circuit-based training. Additionally, significant differences in maximum oxygen uptake and one-repetition maximum bench press were found between the resistance circuit-based training and control groups. The meta-analysis showed that resistance circuit-based training, independent of the protocol used in the studies, is effective in increasing maximum oxygen uptake and one-repetition maximum bench press in healthy adults. However, its effect appears to be larger depending on the population and training characteristics. For large effects in maximum oxygen uptake, the programme should include ~14-30 sessions for ~6-12 weeks, with each session lasting at least ~20-30 min, at intensities between ~60 and 90% one-repetition maximum. For large effects in one-repetition maximum bench press, the data indicate that intensity should be ~30-60% one-repetition maximum, with sessions lasting at least ~22.5-60 min. However, the lower participant's baseline fitness level may explain the lighter optimal loads used in the circuit training studies where greater strength gains were reported.

Capability approval programme for Microwave Hybrid Integrated Circuits (MHICS)

NASA Astrophysics Data System (ADS)

1990-11-01

The general requirements for capability approval of a manufacturing line for Microwave Hybrid Integrated Circuits (MHICs) are defined. ESA approval mandate will be exercized upon conclusion of the evaluation phase and at the end of the program. Before the evaluation phase can commence, the manufacturer must define the capability approval domain by specifying the processes, materials and technology for which approval is sought.

G(sup 4)FET Implementations of Some Logic Circuits

NASA Technical Reports Server (NTRS)

Mojarradi, Mohammad; Akarvardar, Kerem; Cristoleveanu, Sorin; Gentil, Paul; Blalock, Benjamin; Chen, Suhan

2009-01-01

Some logic circuits have been built and demonstrated to work substantially as intended, all as part of a continuing effort to exploit the high degrees of design flexibility and functionality of the electronic devices known as G(sup 4)FETs and described below. These logic circuits are intended to serve as prototypes of more complex advanced programmable-logicdevice-type integrated circuits, including field-programmable gate arrays (FPGAs). In comparison with prior FPGAs, these advanced FPGAs could be much more efficient because the functionality of G(sup 4)FETs is such that fewer discrete components are needed to perform a given logic function in G(sup 4)FET circuitry than are needed perform the same logic function in conventional transistor-based circuitry. The underlying concept of using G(sup 4)FETs as building blocks of programmable logic circuitry was also described, from a different perspective, in G(sup 4)FETs as Universal and Programmable Logic Gates (NPO-41698), NASA Tech Briefs, Vol. 31, No. 7 (July 2007), page 44. A G(sup 4)FET can be characterized as an accumulation-mode silicon-on-insulator (SOI) metal oxide/semiconductor field-effect transistor (MOSFET) featuring two junction field-effect transistor (JFET) gates. The structure of a G(sup 4)FET (see Figure 1) is the same as that of a p-channel inversion-mode SOI MOSFET with two body contacts on each side of the channel. The top gate (G1), the substrate emulating a back gate (G2), and the junction gates (JG1 and JG2) can be biased independently of each other and, hence, each can be used to independently control some aspects of the conduction characteristics of the transistor. The independence of the actions of the four gates is what affords the enhanced functionality and design flexibility of G(sup 4)FETs. The present G(sup 4)FET logic circuits include an adjustable-threshold inverter, a real-time-reconfigurable logic gate, and a dynamic random-access memory (DRAM) cell (see Figure 2). The configuration of the adjustable-threshold inverter is similar to that of an ordinary complementary metal oxide semiconductor (CMOS) inverter except that an NMOSFET (a MOSFET having an n-doped channel and a p-doped Si substrate) is replaced by an n-channel G(sup 4)FET

STICAP: A linear circuit analysis program with stiff systems capability. Volume 1: Theory manual. [network analysis

NASA Technical Reports Server (NTRS)

Cooke, C. H.

1975-01-01

STICAP (Stiff Circuit Analysis Program) is a FORTRAN 4 computer program written for the CDC-6400-6600 computer series and SCOPE 3.0 operating system. It provides the circuit analyst a tool for automatically computing the transient responses and frequency responses of large linear time invariant networks, both stiff and nonstiff (algorithms and numerical integration techniques are described). The circuit description and user's program input language is engineer-oriented, making simple the task of using the program. Engineering theories underlying STICAP are examined. A user's manual is included which explains user interaction with the program and gives results of typical circuit design applications. Also, the program structure from a systems programmer's viewpoint is depicted and flow charts and other software documentation are given.

Current Radiation Issues for Programmable Elements and Devices

NASA Technical Reports Server (NTRS)

Katz, R.; Wang, J. J.; Koga, R.; LaBel, A.; McCollum, J.; Brown, R.; Reed, R. A.; Cronquist, B.; Crain, S.; Scott, T.;

An IO block array in a radiation-hardened SOI SRAM-based FPGA

NASA Astrophysics Data System (ADS)

Yan, Zhao; Lihua, Wu; Xiaowei, Han; Yan, Li; Qianli, Zhang; Liang, Chen; Guoquan, Zhang; Jianzhong, Li; Bo, Yang; Jiantou, Gao; Jian, Wang; Ming, Li; Guizhai, Liu; Feng, Zhang; Xufeng, Guo; Kai, Zhao; Chen, Stanley L.; Fang, Yu; Zhongli, Liu

2012-01-01

We present an input/output block (IOB) array used in the radiation-hardened SRAM-based field-programmable gate array (FPGA) VS1000, which is designed and fabricated with a 0.5 μm partially depleted silicon-on-insulator (SOI) logic process at the CETC 58th Institute. Corresponding with the characteristics of the FPGA, each IOB includes a local routing pool and two IO cells composed of a signal path circuit, configurable input/output buffers and an ESD protection network. A boundary-scan path circuit can be used between the programmable buffers and the input/output circuit or as a transparent circuit when the IOB is applied in different modes. Programmable IO buffers can be used at TTL/CMOS standard levels. The local routing pool enhances the flexibility and routability of the connection between the IOB array and the core logic. Radiation-hardened designs, including A-type and H-type body-tied transistors and special D-type registers, improve the anti-radiation performance. The ESD protection network, which provides a high-impulse discharge path on a pad, prevents the breakdown of the core logic caused by the immense current. These design strategies facilitate the design of FPGAs with different capacities or architectures to form a series of FPGAs. The functionality and performance of the IOB array is proved after a functional test. The radiation test indicates that the proposed VS1000 chip with an IOB array has a total dose tolerance of 100 krad(Si), a dose survivability rate of 1.5 × 1011 rad(Si)/s, and a neutron fluence immunity of 1 × 1014 n/cm2.

A versatile pulse programmer for pulsed nuclear magnetic resonance spectroscopy.

NASA Technical Reports Server (NTRS)

Tarr, C. E.; Nickerson, M. A.

1972-01-01

A digital pulse programmer producing the standard pulse sequences required for pulsed nuclear magnetic resonance spectroscopy is described. In addition, a 'saturation burst' sequence, useful in the measurement of long relaxation times in solids, is provided. Both positive and negative 4 V trigger pulses are produced that are fully synchronous with a crystal-controlled time base, and the pulse programmer may be phase-locked with a maximum pulse jitter of 3 ns to the oscillator of a coherent pulse spectrometer. Medium speed TTL integrated circuits are used throughout.

Feedforward, high density, programmable read only neural network based memory system

NASA Technical Reports Server (NTRS)

Daud, Taher; Moopenn, Alex; Lamb, James; Thakoor, Anil; Khanna, Satish

1988-01-01

Neural network-inspired, nonvolatile, programmable associative memory using thin-film technology is demonstrated. The details of the architecture, which uses programmable resistive connection matrices in synaptic arrays and current summing and thresholding amplifiers as neurons, are described. Several synapse configurations for a high-density array of a binary connection matrix are also described. Test circuits are evaluated for operational feasibility and to demonstrate the speed of the read operation. The results are discussed to highlight the potential for a read data rate exceeding 10 megabits/sec.

Hierarchical MFMO Circuit Modules for an Energy-Efficient SDR DBF

NASA Astrophysics Data System (ADS)

Mar, Jeich; Kuo, Chi-Cheng; Wu, Shin-Ru; Lin, You-Rong

The hierarchical multi-function matrix operation (MFMO) circuit modules are designed using coordinate rotations digital computer (CORDIC) algorithm for realizing the intensive computation of matrix operations. The paper emphasizes that the designed hierarchical MFMO circuit modules can be used to develop a power-efficient software-defined radio (SDR) digital beamformer (DBF). The formulas of the processing time for the scalable MFMO circuit modules implemented in field programmable gate array (FPGA) are derived to allocate the proper logic resources for the hardware reconfiguration. The hierarchical MFMO circuit modules are scalable to the changing number of array branches employed for the SDR DBF to achieve the purpose of power saving. The efficient reuse of the common MFMO circuit modules in the SDR DBF can also lead to energy reduction. Finally, the power dissipation and reconfiguration function in the different modes of the SDR DBF are observed from the experiment results.

Programmable genetic circuits for pathway engineering.

PubMed

Hoynes-O'Connor, Allison; Moon, Tae Seok

2015-12-01

Synthetic biology has the potential to provide decisive advances in genetic control of metabolic pathways. However, there are several challenges that synthetic biologists must overcome before this vision becomes a reality. First, a library of diverse and well-characterized sensors, such as metabolite-sensing or condition-sensing promoters, must be constructed. Second, robust programmable circuits that link input conditions with a specific gene regulation response must be developed. Finally, multi-gene targeting strategies must be integrated with metabolically relevant sensors and complex, robust logic. Achievements in each of these areas, which employ the CRISPR/Cas system, in silico modeling, and dynamic sensor-regulators, among other tools, provide a strong basis for future research. Overall, the future for synthetic biology approaches in metabolic engineering holds immense promise. Copyright © 2015 Elsevier Ltd. All rights reserved.

Pulse transmission transmitter including a higher order time derivate filter

DOEpatents

Dress, Jr., William B.; Smith, Stephen F.

2003-09-23

Systems and methods for pulse-transmission low-power communication modes are disclosed. A pulse transmission transmitter includes: a clock; a pseudorandom polynomial generator coupled to the clock, the pseudorandom polynomial generator having a polynomial load input; an exclusive-OR gate coupled to the pseudorandom polynomial generator, the exclusive-OR gate having a serial data input; a programmable delay circuit coupled to both the clock and the exclusive-OR gate; a pulse generator coupled to the programmable delay circuit; and a higher order time derivative filter coupled to the pulse generator. The systems and methods significantly reduce lower-frequency emissions from pulse transmission spread-spectrum communication modes, which reduces potentially harmful interference to existing radio frequency services and users and also simultaneously permit transmission of multiple data bits by utilizing specific pulse shapes.

Evolutionary Based Techniques for Fault Tolerant Field Programmable Gate Arrays

NASA Technical Reports Server (NTRS)

Larchev, Gregory V.; Lohn, Jason D.

2006-01-01

The use of SRAM-based Field Programmable Gate Arrays (FPGAs) is becoming more and more prevalent in space applications. Commercial-grade FPGAs are potentially susceptible to permanently debilitating Single-Event Latchups (SELs). Repair methods based on Evolutionary Algorithms may be applied to FPGA circuits to enable successful fault recovery. This paper presents the experimental results of applying such methods to repair four commonly used circuits (quadrature decoder, 3-by-3-bit multiplier, 3-by-3-bit adder, 440-7 decoder) into which a number of simulated faults have been introduced. The results suggest that evolutionary repair techniques can improve the process of fault recovery when used instead of or as a supplement to Triple Modular Redundancy (TMR), which is currently the predominant method for mitigating FPGA faults.

FPGA Implementation of Generalized Hebbian Algorithm for Texture Classification

PubMed Central

Lin, Shiow-Jyu; Hwang, Wen-Jyi; Lee, Wei-Hao

2012-01-01

This paper presents a novel hardware architecture for principal component analysis. The architecture is based on the Generalized Hebbian Algorithm (GHA) because of its simplicity and effectiveness. The architecture is separated into three portions: the weight vector updating unit, the principal computation unit and the memory unit. In the weight vector updating unit, the computation of different synaptic weight vectors shares the same circuit for reducing the area costs. To show the effectiveness of the circuit, a texture classification system based on the proposed architecture is physically implemented by Field Programmable Gate Array (FPGA). It is embedded in a System-On-Programmable-Chip (SOPC) platform for performance measurement. Experimental results show that the proposed architecture is an efficient design for attaining both high speed performance and low area costs. PMID:22778640

Integrated Circuit For Simulation Of Neural Network

NASA Technical Reports Server (NTRS)

Thakoor, Anilkumar P.; Moopenn, Alexander W.; Khanna, Satish K.

1988-01-01

Ballast resistors deposited on top of circuit structure. Cascadable, programmable binary connection matrix fabricated in VLSI form as basic building block for assembly of like units into content-addressable electronic memory matrices operating somewhat like networks of neurons. Connections formed during storage of data, and data recalled from memory by prompting matrix with approximate or partly erroneous signals. Redundancy in pattern of connections causes matrix to respond with correct stored data.

RAD hard PROM design study

NASA Technical Reports Server (NTRS)

1981-01-01

The results of a preliminary study on the design of a radiation hardened fusible link programmable read-only memory (PROM) are presented. Various fuse technologies and the effects of radiation on MOS integrated circuits are surveyed. A set of design rules allowing the fabrication of a radiation hardened PROM using a Si-gate CMOS process is defined. A preliminary cell layout was completed and the programming concept defined. A block diagram is used to describe the circuit components required for a 4 K design. A design goal data sheet giving target values for the AC, DC, and radiation parameters of the circuit is presented.

Programmable Hydrogel Ionic Circuits for Biologically Matched Electronic Interfaces.

PubMed

Zhao, Siwei; Tseng, Peter; Grasman, Jonathan; Wang, Yu; Li, Wenyi; Napier, Bradley; Yavuz, Burcin; Chen, Ying; Howell, Laurel; Rincon, Javier; Omenetto, Fiorenzo G; Kaplan, David L

2018-06-01

The increased need for wearable and implantable medical devices has driven the demand for electronics that interface with living systems. Current bioelectronic systems have not fully resolved mismatches between engineered circuits and biological systems, including the resulting pain and damage to biological tissues. Here, salt/poly(ethylene glycol) (PEG) aqueous two-phase systems are utilized to generate programmable hydrogel ionic circuits. High-conductivity salt-solution patterns are stably encapsulated within PEG hydrogel matrices using salt/PEG phase separation, which route ionic current with high resolution and enable localized delivery of electrical stimulation. This strategy allows designer electronics that match biological systems, including transparency, stretchability, complete aqueous-based connective interface, distribution of ionic electrical signals between engineered and biological systems, and avoidance of tissue damage from electrical stimulation. The potential of such systems is demonstrated by generating light-emitting diode (LED)-based displays, skin-mounted electronics, and stimulators that deliver localized current to in vitro neuron cultures and muscles in vivo with reduced adverse effects. Such electronic platforms may form the basis of future biointegrated electronic systems. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Compiling probabilistic, bio-inspired circuits on a field programmable analog array

PubMed Central

Marr, Bo; Hasler, Jennifer

2014-01-01

A field programmable analog array (FPAA) is presented as an energy and computational efficiency engine: a mixed mode processor for which functions can be compiled at significantly less energy costs using probabilistic computing circuits. More specifically, it will be shown that the core computation of any dynamical system can be computed on the FPAA at significantly less energy per operation than a digital implementation. A stochastic system that is dynamically controllable via voltage controlled amplifier and comparator thresholds is implemented, which computes Bernoulli random variables. From Bernoulli variables it is shown exponentially distributed random variables, and random variables of an arbitrary distribution can be computed. The Gillespie algorithm is simulated to show the utility of this system by calculating the trajectory of a biological system computed stochastically with this probabilistic hardware where over a 127X performance improvement over current software approaches is shown. The relevance of this approach is extended to any dynamical system. The initial circuits and ideas for this work were generated at the 2008 Telluride Neuromorphic Workshop. PMID:24847199

Compact sub-nanosecond pulse seed source with diode laser driven by a high-speed circuit

NASA Astrophysics Data System (ADS)

Wang, Xiaoqian; Wang, Bo; Wang, Junhua; Cheng, Wenyong

2018-06-01

A compact sub-nanosecond pulse seed source with 1550 nm diode laser (DL) was obtained by employing a high-speed circuit. The circuit mainly consisted of a short pulse generator and a short pulse driver. The short pulse generator, making up of a complex programmable logic device (CPLD), a level translator, two programmable delay chips and an AND gate chip, output a triggering signal to control metal-oxide-semiconductor field-effect transistor (MOSFET) switch of the short pulse driver. The MOSFET switch with fast rising time and falling time both shorter than 1 ns drove the DL to emit short optical pulses. Performances of the pulse seed source were tested. The results showed that continuously adjustable repetition frequency ranging from 500 kHz to 100 MHz and pulse duration in the range of 538 ps to 10 ns were obtained, respectively. 537 μW output was obtained at the highest repetition frequency of 100 MHz with the shortest pulse duration of 538 ps. These seed pulses were injected into an fiber amplifier, and no optical pulse distortions were found.

Means and method of sampling flow related variables from a waterway in an accurate manner using a programmable calculator

Treesearch

Rand E. Eads; Mark R. Boolootian; Steven C. [Inventors] Hankin

1987-01-01

Abstract - A programmable calculator is connected to a pumping sampler by an interface circuit board. The calculator has a sediment sampling program stored therein and includes a timer to periodically wake up the calculator. Sediment collection is controlled by a Selection At List Time (SALT) scheme in which the probability of taking a sample is proportional to its...

A Survey of Memristive Threshold Logic Circuits.

PubMed

Maan, Akshay Kumar; Jayadevi, Deepthi Anirudhan; James, Alex Pappachen

2017-08-01

In this paper, we review different memristive threshold logic (MTL) circuits that are inspired from the synaptic action of the flow of neurotransmitters in the biological brain. The brainlike generalization ability and the area minimization of these threshold logic circuits aim toward crossing Moore's law boundaries at device, circuits, and systems levels. Fast switching memory, signal processing, control systems, programmable logic, image processing, reconfigurable computing, and pattern recognition are identified as some of the potential applications of MTL systems. The physical realization of nanoscale devices with memristive behavior from materials, such as TiO 2 , ferroelectrics, silicon, and polymers, has accelerated research effort in these application areas, inspiring the scientific community to pursue the design of high-speed, low-cost, low-power, and high-density neuromorphic architectures.

Programmable data communications controller requirements

NASA Technical Reports Server (NTRS)

1977-01-01

The design requirements for a Programmable Data Communications Controller (PDCC) that reduces the difficulties in attaching data terminal equipment to a computer are presented. The PDCC is an interface between the computer I/O channel and the bit serial communication lines. Each communication line is supported by a communication port that handles all line control functions and performs most terminal control functions. The port is fabricated on a printed circuit board that plugs into a card chassis, mating with a connector that is joined to all other card stations by a data bus. Ports are individually programmable; each includes a microprocessor, a programmable read-only memory for instruction storage, and a random access memory for data storage.

Behavioral Variability, Learning Processes, and Creativity

DTIC Science & Technology

1992-03-01

socio- logiques, 6conomiques ou iddologiques auxquels n𔄀chappent pas les entreprises dducatives. Nous retrouvons IA trois themes de d~bat assez courants...pour ne pas dire traditionnels, dans les milieux pidagogiques, trois arguments que I’on pourrait reforinuler de la maniere suivante: 1 . Les...vain de concevoir I’enseignement comme un domaine d’ap- plication de la psychologie de I’apprentissage. Sans doute aucune de ces trois propositions ne

A Simple Model of Circuit Design.

DTIC Science & Technology

1980-05-01

mathematicians who discover mathematical ideas (i.cnat>, programmers who write code <Manna> <Barstow>, physicists who solve mechanics problems <de Kiecr-l...rules and shows how - they result in the design of circuits. ’l’he design rules must not only capture the purely mathematical constralints given by VICs...K VI.. *? and KCI, but also how those constraints can implement mechanism. Mathematical constraints tell us an amplifier’s input and output voltages

Evolution of Analog Circuits on Field Programmable Transistor Arrays

NASA Technical Reports Server (NTRS)

Stoica, A.; Keymeulen, D.; Zebulum, R.; Thakoor, A.; Daud, T.; Klimeck, G.; Jin, Y.; Tawel, R.; Duong, V.

2000-01-01

Evolvable Hardware (EHW) refers to HW design and self-reconfiguration using evolutionary/genetic mechanisms. The paper presents an overview of some key concepts of EHW, describing also a set of selected applications.

Dynamically reconfigurable photovoltaic system

DOEpatents

Okandan, Murat; Nielson, Gregory N.

2016-05-31

A PV system composed of sub-arrays, each having a group of PV cells that are electrically connected to each other. A power management circuit for each sub-array has a communications interface and serves to connect or disconnect the sub-array to a programmable power grid. The power grid has bus rows and bus columns. A bus management circuit is positioned at a respective junction of a bus column and a bus row and is programmable through its communication interface to connect or disconnect a power path in the grid. As a result, selected sub-arrays are connected by selected power paths to be in parallel so as to produce a low system voltage, and, alternately in series so as to produce a high system voltage that is greater than the low voltage by at least a factor of ten.

Programmable Differential Delay Circuit With Fine Delay Adjustment

DOEpatents

DeRyckere, John F.; Jenkins, Philip Nord; Cornett, Frank Nolan

2002-07-09

Circuitry that provides additional delay to early arriving signals such that all data signals arrive at a receiving latch with same path delay. The delay of a forwarded clock reference is also controlled such that the capturing clock edge will be optimally positioned near quadrature (depending on latch setup/hold requirements). The circuitry continuously adapts to data and clock path delay changes and digital filtering of phase measurements reduce errors brought on by jittering data edges. The circuitry utilizes only the minimum amount of delay necessary to achieve objective thereby limiting any unintended jitter. Particularly, this programmable differential delay circuit with fine delay adjustment is designed to allow the skew between ASICS to be minimized. This includes skew between data bits, between data bits and clocks as well as minimizing the overall skew in a channel between ASICS.

Dynamically reconfigurable photovoltaic system

DOEpatents

Okandan, Murat; Nielson, Gregory N.

2016-12-27

A PV system composed of sub-arrays, each having a group of PV cells that are electrically connected to each other. A power management circuit for each sub-array has a communications interface and serves to connect or disconnect the sub-array to a programmable power grid. The power grid has bus rows and bus columns. A bus management circuit is positioned at a respective junction of a bus column and a bus row and is programmable through its communication interface to connect or disconnect a power path in the grid. As a result, selected sub-arrays are connected by selected power paths to be in parallel so as to produce a low system voltage, and, alternately in series so as to produce a high system voltage that is greater than the low voltage by at least a factor of ten.

A High-Voltage Integrated Circuit Engine for a Dielectrophoresis-based Programmable Micro-Fluidic Processor

PubMed Central

Current, K. Wayne; Yuk, Kelvin; McConaghy, Charles; Gascoyne, Peter R. C.; Schwartz, Jon A.; Vykoukal, Jody V.; Andrews, Craig

2010-01-01

A high-voltage (HV) integrated circuit has been demonstrated to transport droplets on programmable paths across its coated surface. This chip is the engine for a dielectrophoresis (DEP)-based micro-fluidic lab-on-a-chip system. This chip creates DEP forces that move and help inject droplets. Electrode excitation voltage and frequency are variable. With the electrodes driven with a 100V peak-to-peak periodic waveform, the maximum high-voltage electrode waveform frequency is about 200Hz. Data communication rate is variable up to 250kHz. This demonstration chip has a 32×32 array of nominally 100V electrode drivers. It is fabricated in a 130V SOI CMOS fabrication technology, dissipates a maximum of 1.87W, and is about 10.4 mm × 8.2 mm. PMID:23989241

Programmable high-output-impedance, large-voltage compliance, microstimulator for low-voltage biomedical applications.

PubMed

Farahmand, Sina; Maghami, Mohammad Hossein; Sodagar, Amir M

2012-01-01

This paper reports on the design of a programmable, high output impedance, large voltage compliance microstimulator for low-voltage biomedical applications. A 6-bit binary-weighted digital to analog converter (DAC) is used to generate biphasic stimulus current pulses. A compact current mirror with large output voltage compliance and high output resistance conveys the current pulses to the target tissue. Designed and simulated in a standard 0.18µm CMOS process, the microstimulator circuit is capable of delivering a maximum stimulation current of 160µA to a 10-kΩ resistive load. Operated at a 1.8-V supply voltage, the output stage exhibits a voltage compliance of 1.69V and output resistance of 160MΩ at full scale stimulus current. Layout of the core microelectrode circuit measures 25.5µm×31.5µm.

Nanowire nanocomputer as a finite-state machine.

PubMed

Yao, Jun; Yan, Hao; Das, Shamik; Klemic, James F; Ellenbogen, James C; Lieber, Charles M

2014-02-18

Implementation of complex computer circuits assembled from the bottom up and integrated on the nanometer scale has long been a goal of electronics research. It requires a design and fabrication strategy that can address individual nanometer-scale electronic devices, while enabling large-scale assembly of those devices into highly organized, integrated computational circuits. We describe how such a strategy has led to the design, construction, and demonstration of a nanoelectronic finite-state machine. The system was fabricated using a design-oriented approach enabled by a deterministic, bottom-up assembly process that does not require individual nanowire registration. This methodology allowed construction of the nanoelectronic finite-state machine through modular design using a multitile architecture. Each tile/module consists of two interconnected crossbar nanowire arrays, with each cross-point consisting of a programmable nanowire transistor node. The nanoelectronic finite-state machine integrates 180 programmable nanowire transistor nodes in three tiles or six total crossbar arrays, and incorporates both sequential and arithmetic logic, with extensive intertile and intratile communication that exhibits rigorous input/output matching. Our system realizes the complete 2-bit logic flow and clocked control over state registration that are required for a finite-state machine or computer. The programmable multitile circuit was also reprogrammed to a functionally distinct 2-bit full adder with 32-set matched and complete logic output. These steps forward and the ability of our unique design-oriented deterministic methodology to yield more extensive multitile systems suggest that proposed general-purpose nanocomputers can be realized in the near future.

Nanowire nanocomputer as a finite-state machine

PubMed Central

Yao, Jun; Yan, Hao; Das, Shamik; Klemic, James F.; Ellenbogen, James C.; Lieber, Charles M.

2014-01-01

Implementation of complex computer circuits assembled from the bottom up and integrated on the nanometer scale has long been a goal of electronics research. It requires a design and fabrication strategy that can address individual nanometer-scale electronic devices, while enabling large-scale assembly of those devices into highly organized, integrated computational circuits. We describe how such a strategy has led to the design, construction, and demonstration of a nanoelectronic finite-state machine. The system was fabricated using a design-oriented approach enabled by a deterministic, bottom–up assembly process that does not require individual nanowire registration. This methodology allowed construction of the nanoelectronic finite-state machine through modular design using a multitile architecture. Each tile/module consists of two interconnected crossbar nanowire arrays, with each cross-point consisting of a programmable nanowire transistor node. The nanoelectronic finite-state machine integrates 180 programmable nanowire transistor nodes in three tiles or six total crossbar arrays, and incorporates both sequential and arithmetic logic, with extensive intertile and intratile communication that exhibits rigorous input/output matching. Our system realizes the complete 2-bit logic flow and clocked control over state registration that are required for a finite-state machine or computer. The programmable multitile circuit was also reprogrammed to a functionally distinct 2-bit full adder with 32-set matched and complete logic output. These steps forward and the ability of our unique design-oriented deterministic methodology to yield more extensive multitile systems suggest that proposed general-purpose nanocomputers can be realized in the near future. PMID:24469812

Programmable Analog Memory Resistors For Electronic Neural Networks

NASA Technical Reports Server (NTRS)

Ramesham, Rajeshuni; Thakoor, Sarita; Daud, Taher; Thakoor, Anilkumar P.

1990-01-01

Electrical resistance of new solid-state device altered repeatedly by suitable control signals, yet remains at steady value when control signal removed. Resistance set at low value ("on" state), high value ("off" state), or at any convenient intermediate value and left there until new value desired. Circuits of this type particularly useful in nonvolatile, associative electronic memories based on models of neural networks. Such programmable analog memory resistors ideally suited as synaptic interconnects in "self-learning" neural nets. Operation of device depends on electrochromic property of WO3, which when pure is insulator. Potential uses include nonvolatile, erasable, electronically programmable read-only memories.

Programmable Direct-Memory-Access Controller

NASA Technical Reports Server (NTRS)

Hendry, David F.

1990-01-01

Proposed programmable direct-memory-access controller (DMAC) operates with computer systems of 32000 series, which have 32-bit data buses and use addresses of 24 (or potentially 32) bits. Controller functions with or without help of central processing unit (CPU) and starts itself. Includes such advanced features as ability to compare two blocks of memory for equality and to search block of memory for specific value. Made as single very-large-scale integrated-circuit chip.

Testability Design Rating System: Testability Handbook. Volume 1

DTIC Science & Technology

1992-02-01

4-10 4.7.5 Summary of False BIT Alarms (FBA) ............................. 4-10 4.7.6 Smart BIT Technique...Circuit Board PGA Pin Grid Array PLA Programmable Logic Array PLD Programmable Logic Device PN Pseudo-Random Number PREDICT Probabilistic Estimation of...11 4.7.6 Smart BIT ( reference: RADC-TR-85-198). " Smart " BIT is a term given to BIT circuitry in a system LRU which includes dedicated processor/memory

NASA Communications Division (NASCOM) Tracking and Data Relay Satellite System (TDRSS) shuttle multiplexer-demultiplexer data system (MDM) and supporting items

NASA Technical Reports Server (NTRS)

New, S. R.

1981-01-01

The multiplexer-demultiplexer (MDM) project included the design, documentation, manufacture, and testing of three MDM Data Systems. The equipment is contained in 59 racks, and includes more than 3,000 circuit boards and 600 microprocessors. Spares, circuit card testers, a master set of programmable integrated circuits, and a program development system were included as deliverables. All three MDM's were installed, and were operationally tested. The systems performed well with no major problems. The progress and problems analysis, addresses schedule conformance, new technology, items awaiting government approval, and project conclusions are summarized. All contract modifications are described.

NASA Communications Division (NASCOM) Tracking and Data Relay Satellite System (TDRSS) shuttle multiplexer-demultiplexer data system (MDM) and supporting items

NASA Astrophysics Data System (ADS)

New, S. R.

1981-06-01

The multiplexer-demultiplexer (MDM) project included the design, documentation, manufacture, and testing of three MDM Data Systems. The equipment is contained in 59 racks, and includes more than 3,000 circuit boards and 600 microprocessors. Spares, circuit card testers, a master set of programmable integrated circuits, and a program development system were included as deliverables. All three MDM's were installed, and were operationally tested. The systems performed well with no major problems. The progress and problems analysis, addresses schedule conformance, new technology, items awaiting government approval, and project conclusions are summarized. All contract modifications are described.

Secure TRNG with random phase stimulation

NASA Astrophysics Data System (ADS)

Wieczorek, Piotr Z.

2017-08-01

In this paper a novel TRNG concept is proposed which is a vital part of cryptographic systems. The proposed TRNG involves phase variability of a pair of ring oscillators (ROs) to force the multiple metastable events in a flip-flop (FF). In the solution, the ROs are periodically activated to ensure the violation of the FF timing and resultant state randomness, while the TRNG circuit adapts the structure of ROs to obtain the maximum entropy and circuit security. The TRNG can be implemented in inexpensive re-programmable devices (CPLDs or FPGAs) without the use of Digital Clock Managers (DCMs). Preliminary test results proved the circuit's immunity to the intentional frequency injection attacks.

Peptide Logic Circuits Based on Chemoenzymatic Ligation for Programmable Cell Apoptosis.

PubMed

Li, Yong; Sun, Sujuan; Fan, Lin; Hu, Shanfang; Huang, Yan; Zhang, Ke; Nie, Zhou; Yao, Shouzhou

2017-11-20

A novel and versatile peptide-based bio-logic system capable of regulating cell function is developed using sortase A (SrtA), a peptide ligation enzyme, as a generic processor. By modular peptide design, we demonstrate that mammalian cells apoptosis can be programmed by peptide-based logic operations, including binary and combination gates (AND, INHIBIT, OR, and AND-INHIBIT), and a complex sequential logic circuit (multi-input keypad lock). Moreover, a proof-of-concept peptide regulatory circuit was developed to analyze the expression profile of cell-secreted protein biomarkers and trigger cancer-cell-specific apoptosis. © 2017 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim.

Compiler-aided systematic construction of large-scale DNA strand displacement circuits using unpurified components

NASA Astrophysics Data System (ADS)

Thubagere, Anupama J.; Thachuk, Chris; Berleant, Joseph; Johnson, Robert F.; Ardelean, Diana A.; Cherry, Kevin M.; Qian, Lulu

2017-02-01

Biochemical circuits made of rationally designed DNA molecules are proofs of concept for embedding control within complex molecular environments. They hold promise for transforming the current technologies in chemistry, biology, medicine and material science by introducing programmable and responsive behaviour to diverse molecular systems. As the transformative power of a technology depends on its accessibility, two main challenges are an automated design process and simple experimental procedures. Here we demonstrate the use of circuit design software, combined with the use of unpurified strands and simplified experimental procedures, for creating a complex DNA strand displacement circuit that consists of 78 distinct species. We develop a systematic procedure for overcoming the challenges involved in using unpurified DNA strands. We also develop a model that takes synthesis errors into consideration and semi-quantitatively reproduces the experimental data. Our methods now enable even novice researchers to successfully design and construct complex DNA strand displacement circuits.

Analog Computation by DNA Strand Displacement Circuits.

PubMed

Song, Tianqi; Garg, Sudhanshu; Mokhtar, Reem; Bui, Hieu; Reif, John

2016-08-19

DNA circuits have been widely used to develop biological computing devices because of their high programmability and versatility. Here, we propose an architecture for the systematic construction of DNA circuits for analog computation based on DNA strand displacement. The elementary gates in our architecture include addition, subtraction, and multiplication gates. The input and output of these gates are analog, which means that they are directly represented by the concentrations of the input and output DNA strands, respectively, without requiring a threshold for converting to Boolean signals. We provide detailed domain designs and kinetic simulations of the gates to demonstrate their expected performance. On the basis of these gates, we describe how DNA circuits to compute polynomial functions of inputs can be built. Using Taylor Series and Newton Iteration methods, functions beyond the scope of polynomials can also be computed by DNA circuits built upon our architecture.

Magnetomicrofluidics Circuits for Organizing Bioparticle Arrays

NASA Astrophysics Data System (ADS)

Abedini-Nassab, Roozbeh

Single-cell analysis (SCA) tools have important applications in the analysis of phenotypic heterogeneity, which is difficult or impossible to analyze in bulk cell culture or patient samples. SCA tools thus have a myriad of applications ranging from better credentialing of drug therapies to the analysis of rare latent cells harboring HIV infection or in Cancer. However, existing SCA systems usually lack the required combination of programmability, flexibility, and scalability necessary to enable the study of cell behaviors and cell-cell interactions at the scales sufficient to analyze extremely rare events. To advance the field, I have developed a novel, programmable, and massively-parallel SCA tool which is based on the principles of computer circuits. By integrating these magnetic circuits with microfluidics channels, I developed a platform that can organize a large number of single particles into an array in a controlled manner. My magnetophoretic circuits use passive elements constructed in patterned magnetic thin films to move cells along programmed tracks with an external rotating magnetic field. Cell motion along these tracks is analogous to the motion of charges in an electrical conductor, following a rule similar to Ohm's law. I have also developed asymmetric conductors, similar to electrical diodes, and storage sites for cells that behave similarly to electrical capacitors. I have also developed magnetophoretic circuits which use an overlaid pattern of microwires to switch single cells between different tracks. This switching mechanism, analogous to the operation of electronic transistors, is achieved by establishing a semiconducting gap in the magnetic pattern which can be changed from an insulating state to a conducting state by application of electrical current to an overlaid electrode. I performed an extensive study on the operation of transistors to optimize their geometry and minimize the required gate currents. By combining these elements into integrated circuits, I have built devices which are capable of organizing a precise number of cells into individually addressable array sites, similar to how a random access memory (RAM) stores electronic data. My programmable magnetic circuits allow for the organization of both cells and single-cell pairs into large arrays. Single cells can also potentially be retrieved for downstream high-throughput genomic analysis. In order to enhance the efficiency of the tool and to increase the delivery speed of the particles, I have also developed microfluidics systems that are combined with the magnetophoretic circuits. This hybrid system, called magnetomicrofluidics, is capable of rapidly organizing an array of particles and cells with the high precision and control. I have also shown that cells can be grown inside these chips for multiple days, enabling the long-term phenotypic analysis of rare cellular events. These types of studies can reveal important insights about the intercellular signaling networks and answer crucial questions in biology and immunology.

Automated ILA design for synchronous sequential circuits

NASA Technical Reports Server (NTRS)

Liu, M. N.; Liu, K. Z.; Maki, G. K.; Whitaker, S. R.

1991-01-01

An iterative logic array (ILA) architecture for synchronous sequential circuits is presented. This technique utilizes linear algebra to produce the design equations. The ILA realization of synchronous sequential logic can be fully automated with a computer program. A programmable design procedure is proposed to fullfill the design task and layout generation. A software algorithm in the C language has been developed and tested to generate 1 micron CMOS layouts using the Hewlett-Packard FUNGEN module generator shell.

A programmable microsystem using system-on-chip for real-time biotelemetry.

PubMed

Wang, Lei; Johannessen, Erik A; Hammond, Paul A; Cui, Li; Reid, Stuart W J; Cooper, Jonathan M; Cumming, David R S

2005-07-01

A telemetry microsystem, including multiple sensors, integrated instrumentation and a wireless interface has been implemented. We have employed a methodology akin to that for System-on-Chip microelectronics to design an integrated circuit instrument containing several "intellectual property" blocks that will enable convenient reuse of modules in future projects. The present system was optimized for low-power and included mixed-signal sensor circuits, a programmable digital system, a feedback clock control loop and RF circuits integrated on a 5 mm x 5 mm silicon chip using a 0.6 microm, 3.3 V CMOS process. Undesirable signal coupling between circuit components has been investigated and current injection into sensitive instrumentation nodes was minimized by careful floor-planning. The chip, the sensors, a magnetic induction-based transmitter and two silver oxide cells were packaged into a 36 mm x 12 mm capsule format. A base station was built in order to retrieve the data from the microsystem in real-time. The base station was designed to be adaptive and timing tolerant since the microsystem design was simplified to reduce power consumption and size. The telemetry system was found to have a packet error rate of 10(-3) using an asynchronous simplex link. Trials in animal carcasses were carried out to show that the transmitter was as effective as a conventional RF device whilst consuming less power.

Synthesis of energy-efficient FSMs implemented in PLD circuits

NASA Astrophysics Data System (ADS)

Nawrot, Radosław; Kulisz, Józef; Kania, Dariusz

2017-11-01

The paper presents an outline of a simple synthesis method of energy-efficient FSMs. The idea consists in using local clock gating to selectively block the clock signal, if no transition of a state of a memory element is required. The research was dedicated to logic circuits using Programmable Logic Devices as the implementation platform, but the conclusions can be applied to any synchronous circuit. The experimental section reports a comparison of three methods of implementing sequential circuits in PLDs with respect to clock distribution: the classical fully synchronous structure, the structure exploiting the Enable Clock inputs of memory elements, and the structure using clock gating. The results show that the approach based on clock gating is the most efficient one, and it leads to significant reduction of dynamic power consumed by the FSM.

Genetically Encoded Catalytic Hairpin Assembly for Sensitive RNA Imaging in Live Cells.

PubMed

Mudiyanselage, Aruni P K K Karunanayake; Yu, Qikun; Leon-Duque, Mark A; Zhao, Bin; Wu, Rigumula; You, Mingxu

2018-06-26

DNA and RNA nanotechnology has been used for the development of dynamic molecular devices. In particular, programmable enzyme-free nucleic acid circuits, such as catalytic hairpin assembly, have been demonstrated as useful tools for bioanalysis and to scale up system complexity to an extent beyond current cellular genetic circuits. However, the intracellular functions of most synthetic nucleic acid circuits have been hindered by challenges in the biological delivery and degradation. On the other hand, genetically encoded and transcribed RNA circuits emerge as alternative powerful tools for long-term embedded cellular analysis and regulation. Herein, we reported a genetically encoded RNA-based catalytic hairpin assembly circuit for sensitive RNA imaging inside living cells. The split version of Broccoli, a fluorogenic RNA aptamer, was used as the reporter. One target RNA can catalytically trigger the fluorescence from tens-to-hundreds of Broccoli. As a result, target RNAs can be sensitively detected. We have further engineered our circuit to allow easy programming to image various target RNA sequences. This design principle opens the arena for developing a large variety of genetically encoded RNA circuits for cellular applications.

Engineering a robust DNA split proximity circuit with minimized circuit leakage

PubMed Central

Ang, Yan Shan; Tong, Rachel; Yung, Lin-Yue Lanry

2016-01-01

DNA circuit is a versatile and highly-programmable toolbox which can potentially be used for the autonomous sensing of dynamic events, such as biomolecular interactions. However, the experimental implementation of in silico circuit designs has been hindered by the problem of circuit leakage. Here, we systematically analyzed the sources and characteristics of various types of leakage in a split proximity circuit which was engineered to spatially probe for target sites held within close proximity. Direct evidence that 3′-truncated oligonucleotides were the major impurity contributing to circuit leakage was presented. More importantly, a unique strategy of translocating a single nucleotide between domains, termed ‘inter-domain bridging’, was introduced to eliminate toehold-independent leakages while enhancing the strand displacement kinetics across a three-way junction. We also analyzed the dynamics of intermediate complexes involved in the circuit computation in order to define the working range of domain lengths for the reporter toehold and association region respectively. The final circuit design was successfully implemented on a model streptavidin-biotin system and demonstrated to be robust against both circuit leakage and biological interferences. We anticipate that this simple signal transduction strategy can be used to probe for diverse biomolecular interactions when used in conjunction with specific target recognition moieties. PMID:27207880

Design and implementation of a low-cost multiple-range digital phase detector

NASA Astrophysics Data System (ADS)

Omran, Hesham; Albasha, Lutfi; Al-Ali, A. R.

2012-06-01

This article describes the design, simulation, implementation and testing of a novel low-cost multiple-range programmable digital phase detector. The detector receives two periodic signals and calculates the ratio of the time difference to the time period to measure and display the phase difference. The resulting output values are in integer form ranging from -180° to 180°. Users can select the detector pre-set operation frequency ranges using a three-bit pre-scalar. This enables to use the detector for various applications. The proposed detector can be programmed over a frequency range of 10 Hz to 25 kHz by configuring its clock divider circuit. Detector simulations were conducted and verified using ModelSim and the design was implemented and tested using an Altera Cyclone II field-programmable gate array board. Both the simulation and actual circuit testing results showed that the phase detector has a magnitude of error of only 1°. The detector is ideal for applications such as power factor measurement and correction, self-tuning resonant circuits and in metal detection systems. Unlike other stand-alone phase detection systems, the reported system has the ability to be programmed to several frequency ranges, hence expanding its bandwidth.

A wide-range programmable frequency synthesizer based on a finite state machine filter

NASA Astrophysics Data System (ADS)

Alser, Mohammed H.; Assaad, Maher M.; Hussin, Fawnizu A.

2013-11-01

In this article, an FPGA-based design and implementation of a fully digital wide-range programmable frequency synthesizer based on a finite state machine filter is presented. The advantages of the proposed architecture are that, it simultaneously generates a high frequency signal from a low frequency reference signal (i.e. synthesising), and synchronising the two signals (signals have the same phase, or a constant difference) without jitter accumulation issue. The architecture is portable and can be easily implemented for various platforms, such as FPGAs and integrated circuits. The frequency synthesizer circuit can be used as a part of SERDES devices in intra/inter chip communication in system-on-chip (SoC). The proposed circuit is designed using Verilog language and synthesized for the Altera DE2-70 development board, with the Cyclone II (EP2C35F672C6) device on board. Simulation and experimental results are included; they prove the synthesizing and tracking features of the proposed architecture. The generated clock signal frequency of a range from 19.8 MHz to 440 MHz is synchronized to the input reference clock with a frequency step of 0.12 MHz.

Characterization and recovery of Deep Sub Micron (DSM) technologies behavior under radiation

NASA Technical Reports Server (NTRS)

Stoica, Adrian; Wang, Xiao

2005-01-01

This paper serves a twofold purpose: characterize the behavior of a reconfigurable chip exposed to radiation; and demonstrate a method for functionality recovery due to Total Ionizing Dose (TID) effects. The experiments are performed using a PL developed reconfigurable device, a Field Programmable Transistor Array (FPTA). The paper initially describes experiments on the characterization of the NMOS transistor behavior for TID values up to 300krad. The behavior of analog and digital circuits downloaded onto the FPTA chip is also assessed for TID effects. This paper also presents a novel approach for circuit functionality recovery due to radiation effects based on Evolvable Hardware. The key idea is to reconfigure a programmable device, in-situ, to compensate, or bypass its degraded or damaged components. Experiments with total radiation dose up to 300kRad show that while the functionality of a variety of circuits, including digital gates, a rectifier and a Digital to Analog Converter implemented on a FPTA-2 chip is degraded/lost at levels before 200kRad, the correct functionality can be recovered through the proposed evolutionary approach and the chips are able to survive higher radiation, for several functions in excess of total radiation dose of 250kRad.

Programmable autonomous synthesis of single-stranded DNA

NASA Astrophysics Data System (ADS)

Kishi, Jocelyn Y.; Schaus, Thomas E.; Gopalkrishnan, Nikhil; Xuan, Feng; Yin, Peng

2018-02-01

DNA performs diverse functional roles in biology, nanotechnology and biotechnology, but current methods for autonomously synthesizing arbitrary single-stranded DNA are limited. Here, we introduce the concept of primer exchange reaction (PER) cascades, which grow nascent single-stranded DNA with user-specified sequences following prescribed reaction pathways. PER synthesis happens in a programmable, autonomous, in situ and environmentally responsive fashion, providing a platform for engineering molecular circuits and devices with a wide range of sensing, monitoring, recording, signal-processing and actuation capabilities. We experimentally demonstrate a nanodevice that transduces the detection of a trigger RNA into the production of a DNAzyme that degrades an independent RNA substrate, a signal amplifier that conditionally synthesizes long fluorescent strands only in the presence of a particular RNA signal, molecular computing circuits that evaluate logic (AND, OR, NOT) combinations of RNA inputs, and a temporal molecular event recorder that records in the PER transcript the order in which distinct RNA inputs are sequentially detected.

A digital optical phase-locked loop for diode lasers based on field programmable gate array.

PubMed

Xu, Zhouxiang; Zhang, Xian; Huang, Kaikai; Lu, Xuanhui

2012-09-01

We have designed and implemented a highly digital optical phase-locked loop (OPLL) for diode lasers in atom interferometry. The three parts of controlling circuit in this OPLL, including phase and frequency detector (PFD), loop filter and proportional integral derivative (PID) controller, are implemented in a single field programmable gate array chip. A structure type compatible with the model MAX9382∕MCH12140 is chosen for PFD and pipeline and parallelism technology have been adapted in PID controller. Especially, high speed clock and twisted ring counter have been integrated in the most crucial part, the loop filter. This OPLL has the narrow beat note line width below 1 Hz, residual mean-square phase error of 0.14 rad(2) and transition time of 100 μs under 10 MHz frequency step. A main innovation of this design is the completely digitalization of the whole controlling circuit in OPLL for diode lasers.

A digital optical phase-locked loop for diode lasers based on field programmable gate array

NASA Astrophysics Data System (ADS)

Xu, Zhouxiang; Zhang, Xian; Huang, Kaikai; Lu, Xuanhui

2012-09-01

We have designed and implemented a highly digital optical phase-locked loop (OPLL) for diode lasers in atom interferometry. The three parts of controlling circuit in this OPLL, including phase and frequency detector (PFD), loop filter and proportional integral derivative (PID) controller, are implemented in a single field programmable gate array chip. A structure type compatible with the model MAX9382/MCH12140 is chosen for PFD and pipeline and parallelism technology have been adapted in PID controller. Especially, high speed clock and twisted ring counter have been integrated in the most crucial part, the loop filter. This OPLL has the narrow beat note line width below 1 Hz, residual mean-square phase error of 0.14 rad2 and transition time of 100 μs under 10 MHz frequency step. A main innovation of this design is the completely digitalization of the whole controlling circuit in OPLL for diode lasers.

Programmable autonomous synthesis of single-stranded DNA.

PubMed

Kishi, Jocelyn Y; Schaus, Thomas E; Gopalkrishnan, Nikhil; Xuan, Feng; Yin, Peng

2018-02-01

DNA performs diverse functional roles in biology, nanotechnology and biotechnology, but current methods for autonomously synthesizing arbitrary single-stranded DNA are limited. Here, we introduce the concept of primer exchange reaction (PER) cascades, which grow nascent single-stranded DNA with user-specified sequences following prescribed reaction pathways. PER synthesis happens in a programmable, autonomous, in situ and environmentally responsive fashion, providing a platform for engineering molecular circuits and devices with a wide range of sensing, monitoring, recording, signal-processing and actuation capabilities. We experimentally demonstrate a nanodevice that transduces the detection of a trigger RNA into the production of a DNAzyme that degrades an independent RNA substrate, a signal amplifier that conditionally synthesizes long fluorescent strands only in the presence of a particular RNA signal, molecular computing circuits that evaluate logic (AND, OR, NOT) combinations of RNA inputs, and a temporal molecular event recorder that records in the PER transcript the order in which distinct RNA inputs are sequentially detected.

Deep learning with coherent nanophotonic circuits

NASA Astrophysics Data System (ADS)

Shen, Yichen; Harris, Nicholas C.; Skirlo, Scott; Prabhu, Mihika; Baehr-Jones, Tom; Hochberg, Michael; Sun, Xin; Zhao, Shijie; Larochelle, Hugo; Englund, Dirk; Soljačić, Marin

2017-07-01

Artificial neural networks are computational network models inspired by signal processing in the brain. These models have dramatically improved performance for many machine-learning tasks, including speech and image recognition. However, today's computing hardware is inefficient at implementing neural networks, in large part because much of it was designed for von Neumann computing schemes. Significant effort has been made towards developing electronic architectures tuned to implement artificial neural networks that exhibit improved computational speed and accuracy. Here, we propose a new architecture for a fully optical neural network that, in principle, could offer an enhancement in computational speed and power efficiency over state-of-the-art electronics for conventional inference tasks. We experimentally demonstrate the essential part of the concept using a programmable nanophotonic processor featuring a cascaded array of 56 programmable Mach-Zehnder interferometers in a silicon photonic integrated circuit and show its utility for vowel recognition.

Predicting the behavior of microfluidic circuits made from discrete elements

PubMed Central

Bhargava, Krisna C.; Thompson, Bryant; Iqbal, Danish; Malmstadt, Noah

2015-01-01

Microfluidic devices can be used to execute a variety of continuous flow analytical and synthetic chemistry protocols with a great degree of precision. The growing availability of additive manufacturing has enabled the design of microfluidic devices with new functionality and complexity. However, these devices are prone to larger manufacturing variation than is typical of those made with micromachining or soft lithography. In this report, we demonstrate a design-for-manufacturing workflow that addresses performance variation at the microfluidic element and circuit level, in context of mass-manufacturing and additive manufacturing. Our approach relies on discrete microfluidic elements that are characterized by their terminal hydraulic resistance and associated tolerance. Network analysis is employed to construct simple analytical design rules for model microfluidic circuits. Monte Carlo analysis is employed at both the individual element and circuit level to establish expected performance metrics for several specific circuit configurations. A protocol based on osmometry is used to experimentally probe mixing behavior in circuits in order to validate these approaches. The overall workflow is applied to two application circuits with immediate use at on the bench-top: series and parallel mixing circuits that are modularly programmable, virtually predictable, highly precise, and operable by hand. PMID:26516059

Master/Programmable-Slave Computer

NASA Technical Reports Server (NTRS)

Smaistrla, David; Hall, William A.

1990-01-01

Unique modular computer features compactness, low power, mass storage of data, multiprocessing, and choice of various input/output modes. Master processor communicates with user via usual keyboard and video display terminal. Coordinates operations of as many as 24 slave processors, each dedicated to different experiment. Each slave circuit card includes slave microprocessor and assortment of input/output circuits for communication with external equipment, with master processor, and with other slave processors. Adaptable to industrial process control with selectable degrees of automatic control, automatic and/or manual monitoring, and manual intervention.

Harnessing vision for computation.

PubMed

Changizi, Mark

2008-01-01

Might it be possible to harness the visual system to carry out artificial computations, somewhat akin to how DNA has been harnessed to carry out computation? I provide the beginnings of a research programme attempting to do this. In particular, new techniques are described for building 'visual circuits' (or 'visual software') using wire, NOT, OR, and AND gates in a visual 6modality such that our visual system acts as 'visual hardware' computing the circuit, and generating a resultant perception which is the output.

High performance digital read out integrated circuit (DROIC) for infrared imaging

NASA Astrophysics Data System (ADS)

Mizuno, Genki; Olah, Robert; Oduor, Patrick; Dutta, Achyut K.; Dhar, Nibir K.

2016-05-01

Banpil Photonics has developed a high-performance Digital Read-Out Integrated Circuit (DROIC) for image sensors and camera systems targeting various military, industrial and commercial Infrared (IR) imaging applications. The on-chip digitization of the pixel output eliminates the necessity for an external analog-to-digital converter (ADC), which not only cuts costs, but also enables miniaturization of packaging to achieve SWaP-C camera systems. In addition, the DROIC offers new opportunities for greater on-chip processing intelligence that are not possible in conventional analog ROICs prevalent today. Conventional ROICs, which typically can enhance only one high performance attribute such as frame rate, power consumption or noise level, fail when simultaneously targeting the most aggressive performance requirements demanded in imaging applications today. Additionally, scaling analog readout circuits to meet such requirements leads to expensive, high-power consumption with large and complex systems that are untenable in the trend towards SWaP-C. We present the implementation of a VGA format (640x512 pixels 15μm pitch) capacitivetransimpedance amplifier (CTIA) DROIC architecture that incorporates a 12-bit ADC at the pixel level. The CTIA pixel input circuitry has two gain modes with programmable full-well capacity values of 100K e- and 500K e-. The DROIC has been developed with a system-on-chip architecture in mind, where all the timing and biasing are generated internally without requiring any critical external inputs. The chip is configurable with many parameters programmable through a serial programmable interface (SPI). It features a global shutter, low power, and high frame rates programmable from 30 up 500 frames per second in full VGA format supported through 24 LVDS outputs. This DROIC, suitable for hybridization with focal plane arrays (FPA) is ideal for high-performance uncooled camera applications ranging from near IR (NIR) and shortwave IR (SWIR) to mid-wave IR (MWIR) and long-wave IR (LWIR) spectral bands.

Design on the x-ray oral digital image display card

NASA Astrophysics Data System (ADS)

Wang, Liping; Gu, Guohua; Chen, Qian

2009-10-01

According to the main characteristics of X-ray imaging, the X-ray display card is successfully designed and debugged using the basic principle of correlated double sampling (CDS) and combined with embedded computer technology. CCD sensor drive circuit and the corresponding procedures have been designed. Filtering and sampling hold circuit have been designed. The data exchange with PC104 bus has been implemented. Using complex programmable logic device as a device to provide gating and timing logic, the functions which counting, reading CPU control instructions, corresponding exposure and controlling sample-and-hold have been completed. According to the image effect and noise analysis, the circuit components have been adjusted. And high-quality images have been obtained.

Catalytic nucleic acids (DNAzymes) as functional units for logic gates and computing circuits: from basic principles to practical applications.

PubMed

Orbach, Ron; Willner, Bilha; Willner, Itamar

2015-03-11

This feature article addresses the implementation of catalytic nucleic acids as functional units for the construction of logic gates and computing circuits, and discusses the future applications of these systems. The assembly of computational modules composed of DNAzymes has led to the operation of a universal set of logic gates, to field programmable logic gates and computing circuits, to the development of multiplexers/demultiplexers, and to full-adder systems. Also, DNAzyme cascades operating as logic gates and computing circuits were demonstrated. DNAzyme logic systems find important practical applications. These include the use of DNAzyme-based systems for sensing and multiplexed analyses, for the development of controlled release and drug delivery systems, for regulating intracellular biosynthetic pathways, and for the programmed synthesis and operation of cascades.

Implementing neural nets with programmable logic

NASA Technical Reports Server (NTRS)

Vidal, Jacques J.

1988-01-01

Networks of Boolean programmable logic modules are presented as one purely digital class of artificial neural nets. The approach contrasts with the continuous analog framework usually suggested. Programmable logic networks are capable of handling many neural-net applications. They avoid some of the limitations of threshold logic networks and present distinct opportunities. The network nodes are called dynamically programmable logic modules. They can be implemented with digitally controlled demultiplexers. Each node performs a Boolean function of its inputs which can be dynamically assigned. The overall network is therefore a combinational circuit and its outputs are Boolean global functions of the network's input variables. The approach offers definite advantages for VLSI implementation, namely, a regular architecture with limited connectivity, simplicity of the control machinery, natural modularity, and the support of a mature technology.

Universal programmable logic gate and routing method

NASA Technical Reports Server (NTRS)

Vatan, Farrokh (Inventor); Akarvardar, Kerem (Inventor); Mojarradi, Mohammad M. (Inventor); Fijany, Amir (Inventor); Cristoloveanu, Sorin (Inventor); Kolawa, Elzbieta (Inventor); Blalock, Benjamin (Inventor); Chen, Suheng (Inventor); Toomarian, Nikzad (Inventor)

2009-01-01

An universal and programmable logic gate based on G.sup.4-FET technology is disclosed, leading to the design of more efficient logic circuits. A new full adder design based on the G.sup.4-FET is also presented. The G.sup.4-FET can also function as a unique router device offering coplanar crossing of signal paths that are isolated and perpendicular to one another. This has the potential of overcoming major limitations in VLSI design where complex interconnection schemes have become increasingly problematic.

A 16-Channel CMOS Chopper-Stabilized Analog Front-End ECoG Acquisition Circuit for a Closed-Loop Epileptic Seizure Control System.

PubMed

Wu, Chung-Yu; Cheng, Cheng-Hsiang; Chen, Zhi-Xin

2018-06-01

In this paper, a 16-channel analog front-end (AFE) electrocorticography signal acquisition circuit for a closed-loop seizure control system is presented. It is composed of 16 input protection circuits, 16 auto-reset chopper-stabilized capacitive-coupled instrumentation amplifiers (AR-CSCCIA) with bandpass filters, 16 programmable transconductance gain amplifiers, a multiplexer, a transimpedance amplifier, and a 128-kS/s 10-bit delta-modulated successive-approximation-register analog-to-digital converter (SAR ADC). In closed-loop seizure control system applications, the stimulator shares the same electrode with the AFE amplifier for effective suppression of epileptic seizures. To prevent from overstress in MOS devices caused by high stimulation voltage, an input protection circuit with a high-voltage-tolerant switch is proposed for the AFE amplifier. Moreover, low input-referred noise is achieved by using the chopper modulation technique in the AR-CSCCIA. To reduce the undesired effects of chopper modulation, an improved offset reduction loop is proposed to reduce the output offset generated by input chopper mismatches. The digital ripple reduction loop is also used to reduce the chopper ripple. The fabricated AFE amplifier has 49.1-/59.4-/67.9-dB programmable gain and 2.02-μVrms input referred noise in a bandwidth of 0.59-117 Hz. The measured power consumption of the AFE amplifier is 3.26 μW per channel, and the noise efficiency factor is 3.36. The in vivo animal test has been successfully performed to verify the functions. It is shown that the proposed AFE acquisition circuit is suitable for implantable closed-loop seizure control systems.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nishimura, Takahiro, E-mail: t-nishimura@ist.osaka-u.ac.jp; Fujii, Ryo; Ogura, Yusuke

Molecular logic circuits represent a promising technology for observation and manipulation of biological systems at the molecular level. However, the implementation of molecular logic circuits for temporal and programmable operation remains challenging. In this paper, we demonstrate an optically controllable logic circuit that uses fluorescence resonance energy transfer (FRET) for signaling. The FRET-based signaling process is modulated by both molecular and optical inputs. Based on the distance dependence of FRET, the FRET pathways required to execute molecular logic operations are formed on a DNA nanostructure as a circuit based on its molecular inputs. In addition, the FRET pathways on themore » DNA nanostructure are controlled optically, using photoswitching fluorescent molecules to instruct the execution of the desired operation and the related timings. The behavior of the circuit can thus be controlled using external optical signals. As an example, a molecular logic circuit capable of executing two different logic operations was studied. The circuit contains functional DNAs and a DNA scaffold to construct two FRET routes for executing Input 1 AND Input 2 and Input 1 AND NOT Input 3 operations on molecular inputs. The circuit produced the correct outputs with all possible combinations of the inputs by following the light signals. Moreover, the operation execution timings were controlled based on light irradiation and the circuit responded to time-dependent inputs. The experimental results demonstrate that the circuit changes the output for the required operations following the input of temporal light signals.« less

Optical reversible programmable Boolean logic unit.

PubMed

Chattopadhyay, Tanay

2012-07-20

Computing with reversibility is the only way to avoid dissipation of energy associated with bit erase. So, a reversible microprocessor is required for future computing. In this paper, a design of a simple all-optical reversible programmable processor is proposed using a polarizing beam splitter, liquid crystal-phase spatial light modulators, a half-wave plate, and plane mirrors. This circuit can perform 16 logical operations according to three programming inputs. Also, inputs can be easily recovered from the outputs. It is named the "reversible programmable Boolean logic unit (RPBLU)." The logic unit is the basic building block of many complex computational operations. Hence the design is important in sense. Two orthogonally polarized lights are defined here as two logical states, respectively.

Design and implementation of a programming circuit in radiation-hardened FPGA

NASA Astrophysics Data System (ADS)

Lihua, Wu; Xiaowei, Han; Yan, Zhao; Zhongli, Liu; Fang, Yu; Chen, Stanley L.

2011-08-01

We present a novel programming circuit used in our radiation-hardened field programmable gate array (FPGA) chip. This circuit provides the ability to write user-defined configuration data into an FPGA and then read it back. The proposed circuit adopts the direct-access programming point scheme instead of the typical long token shift register chain. It not only saves area but also provides more flexible configuration operations. By configuring the proposed partial configuration control register, our smallest configuration section can be conveniently configured as a single data and a flexible partial configuration can be easily implemented. The hierarchical simulation scheme, optimization of the critical path and the elaborate layout plan make this circuit work well. Also, the radiation hardened by design programming point is introduced. This circuit has been implemented in a static random access memory (SRAM)-based FPGA fabricated by a 0.5 μm partial-depletion silicon-on-insulator CMOS process. The function test results of the fabricated chip indicate that this programming circuit successfully realizes the desired functions in the configuration and read-back. Moreover, the radiation test results indicate that the programming circuit has total dose tolerance of 1 × 105 rad(Si), dose rate survivability of 1.5 × 1011 rad(Si)/s and neutron fluence immunity of 1 × 1014 n/cm2.

Real-time monitoring of enzyme-free strand displacement cascades by colorimetric assays

NASA Astrophysics Data System (ADS)

Duan, Ruixue; Wang, Boya; Hong, Fan; Zhang, Tianchi; Jia, Yongmei; Huang, Jiayu; Hakeem, Abdul; Liu, Nannan; Lou, Xiaoding; Xia, Fan

2015-03-01

The enzyme-free toehold-mediated strand displacement reaction has shown potential for building programmable DNA circuits, biosensors, molecular machines and chemical reaction networks. Here we report a simple colorimetric method using gold nanoparticles as signal generators for the real-time detection of the product of the strand displacement cascade. During the process the assembled gold nanoparticles can be separated, resulting in a color change of the solution. This assay can also be applied in complex mixtures, fetal bovine serum, and to detect single-base mismatches. These results suggest that this method could be of general utility to monitor more complex enzyme-free strand displacement reaction-based programmable systems or for further low-cost diagnostic applications.The enzyme-free toehold-mediated strand displacement reaction has shown potential for building programmable DNA circuits, biosensors, molecular machines and chemical reaction networks. Here we report a simple colorimetric method using gold nanoparticles as signal generators for the real-time detection of the product of the strand displacement cascade. During the process the assembled gold nanoparticles can be separated, resulting in a color change of the solution. This assay can also be applied in complex mixtures, fetal bovine serum, and to detect single-base mismatches. These results suggest that this method could be of general utility to monitor more complex enzyme-free strand displacement reaction-based programmable systems or for further low-cost diagnostic applications. Electronic supplementary information (ESI) available: Experimental procedures and analytical data are provided. See DOI: 10.1039/c5nr00697j

Research on laser detonation pulse circuit with low-power based on super capacitor

NASA Astrophysics Data System (ADS)

Wang, Hao-yu; Hong, Jin; He, Aifeng; Jing, Bo; Cao, Chun-qiang; Ma, Yue; Chu, En-yi; Hu, Ya-dong

2018-03-01

According to the demand of laser initiating device miniaturization and low power consumption of weapon system, research on the low power pulse laser detonation circuit with super capacitor. Established a dynamic model of laser output based on super capacitance storage capacity, discharge voltage and programmable output pulse width. The output performance of the super capacitor under different energy storage capacity and discharge voltage is obtained by simulation. The experimental test system was set up, and the laser diode of low power pulsed laser detonation circuit was tested and the laser output waveform of laser diode in different energy storage capacity and discharge voltage was collected. Experiments show that low power pulse laser detonation based on super capacitor energy storage circuit discharge with high efficiency, good transient performance, for a low power consumption requirement, for laser detonation system and low power consumption and provide reference light miniaturization of engineering practice.

Heavy-Ion Microbeam Fault Injection into SRAM-Based FPGA Implementations of Cryptographic Circuits

NASA Astrophysics Data System (ADS)

Li, Huiyun; Du, Guanghua; Shao, Cuiping; Dai, Liang; Xu, Guoqing; Guo, Jinlong

2015-06-01

Transistors hit by heavy ions may conduct transiently, thereby introducing transient logic errors. Attackers can exploit these abnormal behaviors and extract sensitive information from the electronic devices. This paper demonstrates an ion irradiation fault injection attack experiment into a cryptographic field-programmable gate-array (FPGA) circuit. The experiment proved that the commercial FPGA chip is vulnerable to low-linear energy transfer carbon irradiation, and the attack can cause the leakage of secret key bits. A statistical model is established to estimate the possibility of an effective fault injection attack on cryptographic integrated circuits. The model incorporates the effects from temporal, spatial, and logical probability of an effective attack on the cryptographic circuits. The rate of successful attack calculated from the model conforms well to the experimental results. This quantitative success rate model can help evaluate security risk for designers as well as for the third-party assessment organizations.

VIRTEX-5 Fpga Implementation of Advanced Encryption Standard Algorithm

NASA Astrophysics Data System (ADS)

Rais, Muhammad H.; Qasim, Syed M.

2010-06-01

In this paper, we present an implementation of Advanced Encryption Standard (AES) cryptographic algorithm using state-of-the-art Virtex-5 Field Programmable Gate Array (FPGA). The design is coded in Very High Speed Integrated Circuit Hardware Description Language (VHDL). Timing simulation is performed to verify the functionality of the designed circuit. Performance evaluation is also done in terms of throughput and area. The design implemented on Virtex-5 (XC5VLX50FFG676-3) FPGA achieves a maximum throughput of 4.34 Gbps utilizing a total of 399 slices.

CMOS-micromachined, two-dimenisional transistor arrays for neural recording and stimulation.

PubMed

Lin, J S; Chang, S R; Chang, C H; Lu, S C; Chen, H

2007-01-01

In-plane microelectrode arrays have proven to be useful tools for studying the connectivities and the functions of neural tissues. However, seldom microelectrode arrays are monolithically-integrated with signal-processing circuits, without which the maximum number of electrodes is limited by the compromise with routing complexity and interferences. This paper proposes a CMOS-compatible, two-dimensional array of oxide-semiconductor field-effect transistors(OSFETs), capable of both recording and stimulating neuronal activities. The fabrication of the OSFETs not only requires simply die-level, post-CMOS micromachining process, but also retains metal layers for monolithic integration with signal-processing circuits. A CMOS microsystem containing the OSFET arrays and gain-programmable recording circuits has been fabricated and tested. The preliminary testing results are presented and discussed.

A feasibility study of a new computerised cognitive remediation for young adults with schizophrenia

PubMed Central

Cellard, Caroline; Reeder, Clare; Paradis-Giroux, Andrée-Anne; Roy, Marc-André; Gilbert, Elsa; Ivers, Hans; Bouchard, Roch-Hugo; Maziade, Michel; Wykes, Til

2016-01-01

Cognitive remediation therapy is effective for improving cognition, symptoms and social functioning in individuals with schizophrenia; however, the impact on visual episodic memory remains unclear. The objectives of this feasibility study were: (1) to explore whether or not CIRCuiTS—a new computerised cognitive remediation therapy programme developed in England—improves visual episodic memory and other cognitive domains in young adults with early course schizophrenia; and (2) to evaluate acceptability of the CIRCuiTS programme in French-Canadians. Three participants with visual episodic memory impairments at baseline were recruited from clinical settings in Canada, and consented to participate. Neuropsychological, clinical and social functioning was evaluated at baseline and post-treatment. Intervention involved 40 sessions of cognitive remediation. First, the reliable change index (RCI) revealed that each participant demonstrated significant post-therapy change in episodic memory and in other cognitive domains. The response profile was characterised by the use of organisational strategies. Second, the treatment was considered acceptable to participants in terms of session frequency (number of sessions per week), intensity (hours per week; total hours), and number of missed sessions and total completed sessions. This preliminary study yielded encouraging data demonstrating the feasibility of the CIRCuiTS programme in French-Canadian young adults with schizophrenia. PMID:25753694

Field-programmable lab-on-a-chip based on microelectrode dot array architecture.

PubMed

Wang, Gary; Teng, Daniel; Lai, Yi-Tse; Lu, Yi-Wen; Ho, Yingchieh; Lee, Chen-Yi

2014-09-01

The fundamentals of electrowetting-on-dielectric (EWOD) digital microfluidics are very strong: advantageous capability in the manipulation of fluids, small test volumes, precise dynamic control and detection, and microscale systems. These advantages are very important for future biochip developments, but the development of EWOD microfluidics has been hindered by the absence of: integrated detector technology, standard commercial components, on-chip sample preparation, standard manufacturing technology and end-to-end system integration. A field-programmable lab-on-a-chip (FPLOC) system based on microelectrode dot array (MEDA) architecture is presented in this research. The MEDA architecture proposes a standard EWOD microfluidic component called 'microelectrode cell', which can be dynamically configured into microfluidic components to perform microfluidic operations of the biochip. A proof-of-concept prototype FPLOC, containing a 30 × 30 MEDA, was developed by using generic integrated circuits computer aided design tools, and it was manufactured with standard low-voltage complementary metal-oxide-semiconductor technology, which allows smooth on-chip integration of microfluidics and microelectronics. By integrating 900 droplet detection circuits into microelectrode cells, the FPLOC has achieved large-scale integration of microfluidics and microelectronics. Compared to the full-custom and bottom-up design methods, the FPLOC provides hierarchical top-down design approach, field-programmability and dynamic manipulations of droplets for advanced microfluidic operations.

A digital optical phase-locked loop for diode lasers based on field programmable gate array

DOE Office of Scientific and Technical Information (OSTI.GOV)

Xu Zhouxiang; Zhang Xian; Huang Kaikai

2012-09-15

We have designed and implemented a highly digital optical phase-locked loop (OPLL) for diode lasers in atom interferometry. The three parts of controlling circuit in this OPLL, including phase and frequency detector (PFD), loop filter and proportional integral derivative (PID) controller, are implemented in a single field programmable gate array chip. A structure type compatible with the model MAX9382/MCH12140 is chosen for PFD and pipeline and parallelism technology have been adapted in PID controller. Especially, high speed clock and twisted ring counter have been integrated in the most crucial part, the loop filter. This OPLL has the narrow beat notemore » line width below 1 Hz, residual mean-square phase error of 0.14 rad{sup 2} and transition time of 100 {mu}s under 10 MHz frequency step. A main innovation of this design is the completely digitalization of the whole controlling circuit in OPLL for diode lasers.« less

Design of an FPGA-based electronic flow regulator (EFR) for spacecraft propulsion system

NASA Astrophysics Data System (ADS)

Manikandan, J.; Jayaraman, M.; Jayachandran, M.

2011-02-01

This paper describes a scheme for electronically regulating the flow of propellant to the thruster from a high-pressure storage tank used in spacecraft application. Precise flow delivery of propellant to thrusters ensures propulsion system operation at best efficiency by maximizing the propellant and power utilization for the mission. The proposed field programmable gate array (FPGA) based electronic flow regulator (EFR) is used to ensure precise flow of propellant to the thrusters from a high-pressure storage tank used in spacecraft application. This paper presents hardware and software design of electronic flow regulator and implementation of the regulation logic onto an FPGA.Motivation for proposed FPGA-based electronic flow regulation is on the disadvantages of conventional approach of using analog circuits. Digital flow regulation overcomes the analog equivalent as digital circuits are highly flexible, are not much affected due to noise, accurate performance is repeatable, interface is easier to computers, storing facilities are possible and finally failure rate of digital circuits is less. FPGA has certain advantages over ASIC and microprocessor/micro-controller that motivated us to opt for FPGA-based electronic flow regulator. Also the control algorithm being software, it is well modifiable without changing the hardware. This scheme is simple enough to adopt for a wide range of applications, where the flow is to be regulated for efficient operation.The proposed scheme is based on a space-qualified re-configurable field programmable gate arrays (FPGA) and hybrid micro circuit (HMC). A graphical user interface (GUI) based application software is also developed for debugging, monitoring and controlling the electronic flow regulator from PC COM port.

Precursors to Gender Attitudes in the Air Cadet Gliding Population

DTIC Science & Technology

2011-04-01

Hendriks (2008) révélait également une différence de traitement entre les hommes et les femmes dans le contexte de la formation de pilotage de ...Toutefois, les recherches indiquent aussi qu’en comparaison des hommes , les élèves pilotes de sexe féminin peuvent saisir plus rapidement les...menace du stéréotype et qui mesure le rendement des hommes et des femmes pilotes est la prochaine étape logique pour étudier l’écart entre les hommes

Advances in Techniques and Technologies for Air Vehicle Navigation and Guidance

DTIC Science & Technology

1989-12-01

sur l’automatisation nous amene a poser le probleme de linterface homme /machine non pas comme un sous-prob leme A trai ter en corol lai reA a automat i...conditions de la recherche (couverture nuageuse, temps de recalage allou6,... Zon. do ,rech.h (16ftIU) A~e (32-32) fig. 3 Fo’- L Illustration do Ia...itendue h une logique A valeurs continues sur [- l ,+Il. Ces valeurs de decision sont ensuite pondiries par 1’efficacild relative des critIres pour

Method and infrastructure for cycle-reproducible simulation on large scale digital circuits on a coordinated set of field-programmable gate arrays (FPGAs)

DOEpatents

Asaad, Sameh W; Bellofatto, Ralph E; Brezzo, Bernard; Haymes, Charles L; Kapur, Mohit; Parker, Benjamin D; Roewer, Thomas; Tierno, Jose A

2014-01-28

A plurality of target field programmable gate arrays are interconnected in accordance with a connection topology and map portions of a target system. A control module is coupled to the plurality of target field programmable gate arrays. A balanced clock distribution network is configured to distribute a reference clock signal, and a balanced reset distribution network is coupled to the control module and configured to distribute a reset signal to the plurality of target field programmable gate arrays. The control module and the balanced reset distribution network are cooperatively configured to initiate and control a simulation of the target system with the plurality of target field programmable gate arrays. A plurality of local clock control state machines reside in the target field programmable gate arrays. The local clock state machines are configured to generate a set of synchronized free-running and stoppable clocks to maintain cycle-accurate and cycle-reproducible execution of the simulation of the target system. A method is also provided.

A Memory-Based Programmable Logic Device Using Look-Up Table Cascade with Synchronous Static Random Access Memories

NASA Astrophysics Data System (ADS)

Nakamura, Kazuyuki; Sasao, Tsutomu; Matsuura, Munehiro; Tanaka, Katsumasa; Yoshizumi, Kenichi; Nakahara, Hiroki; Iguchi, Yukihiro

2006-04-01

A large-scale memory-technology-based programmable logic device (PLD) using a look-up table (LUT) cascade is developed in the 0.35-μm standard complementary metal oxide semiconductor (CMOS) logic process. Eight 64 K-bit synchronous SRAMs are connected to form an LUT cascade with a few additional circuits. The features of the LUT cascade include: 1) a flexible cascade connection structure, 2) multi phase pseudo asynchronous operations with synchronous static random access memory (SRAM) cores, and 3) LUT-bypass redundancy. This chip operates at 33 MHz in 8-LUT cascades at 122 mW. Benchmark results show that it achieves a comparable performance to field programmable gate array (FPGAs).

Notes on Experiments.

ERIC Educational Resources Information Center

Physics Education, 1984

1984-01-01

Describes (1) use of VELA (a stand-alone programmable instrument); (2) forced harmonic motion of galvanometers; (3) holographic interferometry and measurement of small angular displacement; and (4) an analogy useful on teaching capacitors at A-level. Also describes a comparison of fuses and circuit breakers using a microcomputer as a storage…

Liquid on Paper: Rapid Prototyping of Soft Functional Components for Paper Electronics.

PubMed

Han, Yu Long; Liu, Hao; Ouyang, Cheng; Lu, Tian Jian; Xu, Feng

2015-07-01

This paper describes a novel approach to fabricate paper-based electric circuits consisting of a paper matrix embedded with three-dimensional (3D) microchannels and liquid metal. Leveraging the high electric conductivity and good flowability of liquid metal, and metallophobic property of paper, it is possible to keep electric and mechanical functionality of the electric circuit even after a thousand cycles of deformation. Embedding liquid metal into paper matrix is a promising method to rapidly fabricate low-cost, disposable, and soft electric circuits for electronics. As a demonstration, we designed a programmable displacement transducer and applied it as variable resistors and pressure sensors. The unique metallophobic property, combined with softness, low cost and light weight, makes paper an attractive alternative to other materials in which liquid metal are currently embedded.

Radiation Effects on Current Field Programmable Technologies

NASA Technical Reports Server (NTRS)

Katz, R.; LaBel, K.; Wang, J. J.; Cronquist, B.; Koga, R.; Penzin, S.; Swift, G.

1997-01-01

Manufacturers of field programmable gate arrays (FPGAS) take different technological and architectural approaches that directly affect radiation performance. Similar y technological and architectural features are used in related technologies such as programmable substrates and quick-turn application specific integrated circuits (ASICs). After analyzing current technologies and architectures and their radiation-effects implications, this paper includes extensive test data quantifying various devices total dose and single event susceptibilities, including performance degradation effects and temporary or permanent re-configuration faults. Test results will concentrate on recent technologies being used in space flight electronic systems and those being developed for use in the near term. This paper will provide the first extensive study of various configuration memories used in programmable devices. Radiation performance limits and their impacts will be discussed for each design. In addition, the interplay between device scaling, process, bias voltage, design, and architecture will be explored. Lastly, areas of ongoing research will be discussed.

Wire like link for cycle reproducible and cycle accurate hardware accelerator

DOEpatents

Asaad, Sameh; Kapur, Mohit; Parker, Benjamin D

2015-04-07

First and second field programmable gate arrays are provided which implement first and second blocks of a circuit design to be simulated. The field programmable gate arrays are operated at a first clock frequency and a wire like link is provided to send a plurality of signals between them. The wire like link includes a serializer, on the first field programmable gate array, to serialize the plurality of signals; a deserializer on the second field programmable gate array, to deserialize the plurality of signals; and a connection between the serializer and the deserializer. The serializer and the deserializer are operated at a second clock frequency, greater than the first clock frequency, and the second clock frequency is selected such that latency of transmission and reception of the plurality of signals is less than the period corresponding to the first clock frequency.

A Test Methodology for Determining Space-Readiness of Xilinx SRAM-Based FPGA Designs

DOE Office of Scientific and Technical Information (OSTI.GOV)

Quinn, Heather M; Graham, Paul S; Morgan, Keith S

2008-01-01

Using reconfigurable, static random-access memory (SRAM) based field-programmable gate arrays (FPGAs) for space-based computation has been an exciting area of research for the past decade. Since both the circuit and the circuit's state is stored in radiation-tolerant memory, both could be alterd by the harsh space radiation environment. Both the circuit and the circuit's state can be prote cted by triple-moduler redundancy (TMR), but applying TMR to FPGA user designs is often an error-prone process. Faulty application of TMR could cause the FPGA user circuit to output incorrect data. This paper will describe a three-tiered methodology for testing FPGA usermore » designs for space-readiness. We will describe the standard approach to testing FPGA user designs using a particle accelerator, as well as two methods using fault injection and a modeling tool. While accelerator testing is the current 'gold standard' for pre-launch testing, we believe the use of fault injection and modeling tools allows for easy, cheap and uniform access for discovering errors early in the design process.« less

Quantum optics of lossy asymmetric beam splitters.

PubMed

Uppu, Ravitej; Wolterink, Tom A W; Tentrup, Tristan B H; Pinkse, Pepijn W H

2016-07-25

We theoretically investigate quantum interference of two single photons at a lossy asymmetric beam splitter, the most general passive 2×2 optical circuit. The losses in the circuit result in a non-unitary scattering matrix with a non-trivial set of constraints on the elements of the scattering matrix. Our analysis using the noise operator formalism shows that the loss allows tunability of quantum interference to an extent not possible with a lossless beam splitter. Our theoretical studies support the experimental demonstrations of programmable quantum interference in highly multimodal systems such as opaque scattering media and multimode fibers.

Variable-Resistivity Material For Memory Circuits

NASA Technical Reports Server (NTRS)

Nagasubramanian, Ganesan; Distefano, Salvador; Moacanin, Jovan

1989-01-01

Nonvolatile memory elements packed densely. Electrically-erasable, programmable, read-only memory matrices made with newly-synthesized organic material of variable electrical resistivity. Material, polypyrrole doped with tetracyanoquinhydrone (TCNQ), changes reversibly between insulating or higher-resistivity state and conducting or low-resistivity state. Thin film of conductive polymer separates layer of row conductors from layer of column conductors. Resistivity of film at each intersection and, therefore, resistance of memory element defined by row and column, increased or decreased by application of suitable switching voltage. Matrix circuits made with this material useful for experiments in associative electronic memories based on models of neural networks.

Electrically reconfigurable logic array

NASA Technical Reports Server (NTRS)

Agarwal, R. K.

1982-01-01

To compose the complicated systems using algorithmically specialized logic circuits or processors, one solution is to perform relational computations such as union, division and intersection directly on hardware. These relations can be pipelined efficiently on a network of processors having an array configuration. These processors can be designed and implemented with a few simple cells. In order to determine the state-of-the-art in Electrically Reconfigurable Logic Array (ERLA), a survey of the available programmable logic array (PLA) and the logic circuit elements used in such arrays was conducted. Based on this survey some recommendations are made for ERLA devices.

The Art of Electronics

NASA Astrophysics Data System (ADS)

Horowitz, Paul; Hill, Winfield

2015-04-01

1. Foundations; 2. Bipolar transistors; 3. Field effect transistors; 4. Operational amplifiers; 5. Precision circuits; 6. Filters; 7. Oscillators and timers; 8. Low noise techniques and transimpedance; 9. Power regulation; 10. Digital electronics; 11. Programmable logic devices; 12. Logical interfacing; 13. Digital meets analog; 14. Computers, controllers, and data links; 15. Microcontrollers.

Programmable chemical reaction networks: emulating regulatory functions in living cells using a bottom-up approach.

PubMed

van Roekel, Hendrik W H; Rosier, Bas J H M; Meijer, Lenny H H; Hilbers, Peter A J; Markvoort, Albert J; Huck, Wilhelm T S; de Greef, Tom F A

2015-11-07

Living cells are able to produce a wide variety of biological responses when subjected to biochemical stimuli. It has become apparent that these biological responses are regulated by complex chemical reaction networks (CRNs). Unravelling the function of these circuits is a key topic of both systems biology and synthetic biology. Recent progress at the interface of chemistry and biology together with the realisation that current experimental tools are insufficient to quantitatively understand the molecular logic of pathways inside living cells has triggered renewed interest in the bottom-up development of CRNs. This builds upon earlier work of physical chemists who extensively studied inorganic CRNs and showed how a system of chemical reactions can give rise to complex spatiotemporal responses such as oscillations and pattern formation. Using purified biochemical components, in vitro synthetic biologists have started to engineer simplified model systems with the goal of mimicking biological responses of intracellular circuits. Emulation and reconstruction of system-level properties of intracellular networks using simplified circuits are able to reveal key design principles and molecular programs that underlie the biological function of interest. In this Tutorial Review, we present an accessible overview of this emerging field starting with key studies on inorganic CRNs followed by a discussion of recent work involving purified biochemical components. Finally, we review recent work showing the versatility of programmable biochemical reaction networks (BRNs) in analytical and diagnostic applications.

Effects of supplemental training on fitness and aesthetic competence parameters in contemporary dance: a randomised controlled trial.

PubMed

Angioi, Manuela; Metsios, George; Twitchett, Emily A; Koutedakis, Yiannis; Wyon, Matthew

2012-03-01

Within aesthetic sports such as figure skating and rhythmic gymnastics, physical fitness has been shown to have positive benefits on performance outcomes. Presently the link between physical fitness and aesthetic contemporary dance performance has not been demonstrated within an intervention study. In this study, 24 females engaged in contemporary dance (age 27 ± 5.9 yrs; height 165.3 ± 4.8 cm; weight 59.2 ± 7.6 kg) were recruited and randomly assigned to either an exercise (n = 12) or a control group (n = 12). Three dancers withdrew during the study. The intervention group completed a 6-week conditioning programme comprising two 1-hr sessions of circuit and vibration training per week. The circuit training focused on local muscular endurance and aerobic conditioning and vibration training protocol concentrated on power. Repeated measures ANOVA revealed significant increases for the conditioning group in lower body muscular power (11%), upper body muscular endurance (22%), aerobic fitness (11%), and aesthetic competence (12%) (p < 0.05). The control group reported decreases in all the fitness parameters with the exception of aerobic fitness as well as a decrease in aesthetic competence (7%). A 6-week circuit and vibration training programme, which supplemented normal dance commitments, revealed significant increases in selected fitness components and a concomitant increase in aesthetic competence in contemporary professional and student dancers.

Wide tracking range, auto ranging, low jitter phase lock loop for swept and fixed frequency systems

DOEpatents

Kerner, Thomas M.

2001-01-01

The present invention provides a wide tracking range phase locked loop (PLL) circuit that achieves minimal jitter in a recovered clock signal, regardless of the source of the jitter (i.e. whether it is in the source or the transmission media). The present invention PLL has automatic harmonic lockout detection circuitry via a novel lock and seek control logic in electrical communication with a programmable frequency discriminator and a code balance detector. (The frequency discriminator enables preset of a frequency window of upper and lower frequency limits to derive a programmable range within which signal acquisition is effected. The discriminator works in combination with the code balance detector circuit to minimize the sensitivity of the PLL circuit to random data in the data stream). In addition, the combination of a differential loop integrator with the lock and seek control logic obviates a code preamble and guarantees signal acquisition without harmonic lockup. An adaptive cable equalizer is desirably used in combination with the present invention PLL to recover encoded transmissions containing a clock and/or data. The equalizer automatically adapts to equalize short haul cable lengths of coaxial and twisted pair cables or wires and provides superior jitter performance itself. The combination of the equalizer with the present invention PLL is desirable in that such combination permits the use of short haul wires without significant jitter.

Electro pneumatic trainer embedded with programmable integrated circuit (PIC) microcontroller and graphical user interface platform for aviation industries training purposes

NASA Astrophysics Data System (ADS)

Burhan, I.; Azman, A. A.; Othman, R.

2016-10-01

An electro pneumatic trainer embedded with programmable integrated circuit (PIC) microcontroller and Visual Basic (VB) platform is fabricated as a supporting tool to existing teaching and learning process, and to achieve the objectives and learning outcomes towards enhancing the student's knowledge and hands-on skill, especially in electro pneumatic devices. The existing learning process for electro pneumatic courses conducted in the classroom does not emphasize on simulation and complex practical aspects. VB is used as the platform for graphical user interface (GUI) while PIC as the interface circuit between the GUI and hardware of electro pneumatic apparatus. Fabrication of electro pneumatic trainer interfacing between PIC and VB has been designed and improved by involving multiple types of electro pneumatic apparatus such as linear drive, air motor, semi rotary motor, double acting cylinder and single acting cylinder. Newly fabricated electro pneumatic trainer microcontroller interface can be programmed and re-programmed for numerous combination of tasks. Based on the survey to 175 student participants, 97% of the respondents agreed that the newly fabricated trainer is user friendly, safe and attractive, and 96.8% of the respondents strongly agreed that there is improvement in knowledge development and also hands-on skill in their learning process. Furthermore, the Lab Practical Evaluation record has indicated that the respondents have improved their academic performance (hands-on skills) by an average of 23.5%.

Interlocked DNA nanostructures controlled by a reversible logic circuit.

PubMed

Li, Tao; Lohmann, Finn; Famulok, Michael

2014-09-17

DNA nanostructures constitute attractive devices for logic computing and nanomechanics. An emerging interest is to integrate these two fields and devise intelligent DNA nanorobots. Here we report a reversible logic circuit built on the programmable assembly of a double-stranded (ds) DNA [3]pseudocatenane that serves as a rigid scaffold to position two separate branched-out head-motifs, a bimolecular i-motif and a G-quadruplex. The G-quadruplex only forms when preceded by the assembly of the i-motif. The formation of the latter, in turn, requires acidic pH and unhindered mobility of the head-motif containing dsDNA nanorings with respect to the central ring to which they are interlocked, triggered by release oligodeoxynucleotides. We employ these features to convert the structural changes into Boolean operations with fluorescence labelling. The nanostructure behaves as a reversible logic circuit consisting of tandem YES and AND gates. Such reversible logic circuits integrated into functional nanodevices may guide future intelligent DNA nanorobots to manipulate cascade reactions in biological systems.

Interlocked DNA nanostructures controlled by a reversible logic circuit

PubMed Central

Li, Tao; Lohmann, Finn; Famulok, Michael

2014-01-01

DNA nanostructures constitute attractive devices for logic computing and nanomechanics. An emerging interest is to integrate these two fields and devise intelligent DNA nanorobots. Here we report a reversible logic circuit built on the programmable assembly of a double-stranded (ds) DNA [3]pseudocatenane that serves as a rigid scaffold to position two separate branched-out head-motifs, a bimolecular i-motif and a G-quadruplex. The G-quadruplex only forms when preceded by the assembly of the i-motif. The formation of the latter, in turn, requires acidic pH and unhindered mobility of the head-motif containing dsDNA nanorings with respect to the central ring to which they are interlocked, triggered by release oligodeoxynucleotides. We employ these features to convert the structural changes into Boolean operations with fluorescence labelling. The nanostructure behaves as a reversible logic circuit consisting of tandem YES and AND gates. Such reversible logic circuits integrated into functional nanodevices may guide future intelligent DNA nanorobots to manipulate cascade reactions in biological systems. PMID:25229207

Engineering genetic circuit interactions within and between synthetic minimal cells

NASA Astrophysics Data System (ADS)

Adamala, Katarzyna P.; Martin-Alarcon, Daniel A.; Guthrie-Honea, Katriona R.; Boyden, Edward S.

2017-05-01

Genetic circuits and reaction cascades are of great importance for synthetic biology, biochemistry and bioengineering. An open question is how to maximize the modularity of their design to enable the integration of different reaction networks and to optimize their scalability and flexibility. One option is encapsulation within liposomes, which enables chemical reactions to proceed in well-isolated environments. Here we adapt liposome encapsulation to enable the modular, controlled compartmentalization of genetic circuits and cascades. We demonstrate that it is possible to engineer genetic circuit-containing synthetic minimal cells (synells) to contain multiple-part genetic cascades, and that these cascades can be controlled by external signals as well as inter-liposomal communication without crosstalk. We also show that liposomes that contain different cascades can be fused in a controlled way so that the products of incompatible reactions can be brought together. Synells thus enable a more modular creation of synthetic biology cascades, an essential step towards their ultimate programmability.

An integrated multichannel neural recording analog front-end ASIC with area-efficient driven right leg circuit.

PubMed

Tao Tang; Wang Ling Goh; Lei Yao; Jia Hao Cheong; Yuan Gao

2017-07-01

This paper describes an integrated multichannel neural recording analog front end (AFE) with a novel area-efficient driven right leg (DRL) circuit to improve the system common mode rejection ratio (CMRR). The proposed AFE consists of an AC-coupled low-noise programmable-gain amplifier, an area-efficient DRL block and a 10-bit SAR ADC. Compared to conventional DRL circuit, the proposed capacitor-less DRL design achieves 90% chip area reduction with enhanced CMRR performance, making it ideal for multichannel biomedical recording applications. The AFE circuit has been designed in a standard 0.18-μm CMOS process. Post-layout simulation results show that the AFE provides two gain settings of 54dB/60dB while consuming 1 μA per channel under a supply voltage of 1 V. The input-referred noise of the AFE integrated from 1 Hz to 10k Hz is only 4 μVrms and the CMRR is 110 dB.

Bidirectional automatic release of reserve for low voltage network made with low capacity PLCs

NASA Astrophysics Data System (ADS)

Popa, I.; Popa, G. N.; Diniş, C. M.; Deaconu, S. I.

2018-01-01

The article presents the design of a bidirectional automatic release of reserve made on two types low capacity programmable logic controllers: PS-3 from Klöckner-Moeller and Zelio from Schneider. It analyses the electronic timing circuits that can be used for making the bidirectional automatic release of reserve: time-on delay circuit and time-off delay circuit (two types). In the paper are present the sequences code for timing performed on the PS-3 PLC, the logical functions for the bidirectional automatic release of reserve, the classical control electrical diagram (with contacts, relays, and time relays), the electronic control diagram (with logical gates and timing circuits), the code (in IL language) made for the PS-3 PLC, and the code (in FBD language) made for Zelio PLC. A comparative analysis will be carried out on the use of the two types of PLC and will be present the advantages of using PLCs.

Banning PRF programmer's manual. [considering MOS integrated circuits

NASA Technical Reports Server (NTRS)

Kuelthau, R. L.

1970-01-01

This manual describes a modification of the Banning placement routing folding program. The modifications to this program have been made to implement it on a Sigma 5 computer. Flow charts of various levels, beginning with high level functional diagrams and working down to the level of detail deemed necessary to understand the operations of the various sections of the program are included. Along with the flow charts of each subroutine is a narrative description of its functional operation and definitions of its arrays and key variables, and a section to assist the programmer in dimensioning the program's arrays.

A control system based on field programmable gate array for papermaking sewage treatment

NASA Astrophysics Data System (ADS)

Zhang, Zi Sheng; Xie, Chang; Qing Xiong, Yan; Liu, Zhi Qiang; Li, Qing

2013-03-01

A sewage treatment control system is designed to improve the efficiency of papermaking wastewater treatment system. The automation control system is based on Field Programmable Gate Array (FPGA), coded with Very-High-Speed Integrate Circuit Hardware Description Language (VHDL), compiled and simulated with Quartus. In order to ensure the stability of the data used in FPGA, the data is collected through temperature sensors, water level sensor and online PH measurement system. The automatic control system is more sensitive, and both the treatment efficiency and processing power are increased. This work provides a new method for sewage treatment control.

High throughput reconfigurable data analysis system

NASA Technical Reports Server (NTRS)

Bearman, Greg (Inventor); Pelletier, Michael J. (Inventor); Seshadri, Suresh (Inventor); Pain, Bedabrata (Inventor)

2008-01-01

The present invention relates to a system and method for performing rapid and programmable analysis of data. The present invention relates to a reconfigurable detector comprising at least one array of a plurality of pixels, where each of the plurality of pixels can be selected to receive and read-out an input. The pixel array is divided into at least one pixel group for conducting a common predefined analysis. Each of the pixels has a programmable circuitry programmed with a dynamically configurable user-defined function to modify the input. The present detector also comprises a summing circuit designed to sum the modified input.

A novel productivity-driven logic element for field-programmable devices

NASA Astrophysics Data System (ADS)

Marconi, Thomas; Bertels, Koen; Gaydadjiev, Georgi

2014-06-01

Although various techniques have been proposed for power reduction in field-programmable devices (FPDs), they are still all based on conventional logic elements (LEs). In the conventional LE, the output of the combinational logic (e.g. the look-up table (LUT) in many field-programmable gate arrays (FPGAs)) is connected to the input of the storage element; while the D flip-flop (DFF) is always clocked even when not necessary. Such unnecessary transitions waste power. To address this problem, we propose a novel productivity-driven LE with reduced number of transitions. The differences between our LE and the conventional LE are in the FFs-type used and the internal LE organisation. In our LEs, DFFs have been replaced by T flip-flops with the T input permanently connected to logic value 1. Instead of connecting the output of the combinational logic to the FF input, we use it as the FF clock. The proposed LE has been validated via Simulation Program with Integrated Circuit Emphasis (SPICE) simulations for a 45-nm Complementary Metal-Oxide-Semiconductor (CMOS) technology as well as via a real Computer-Aided Design (CAD) tools on a real FPGA using the standard Microelectronic Center of North Carolina (MCNC) benchmark circuits. The experimental results show that FPDs using our proposal not only have 48% lower total power but also run 17% faster than conventional FPDs on average.

Versatile Stimulation Back-End With Programmable Exponential Current Pulse Shapes for a Retinal Visual Prosthesis.

PubMed

Maghami, Mohammad Hossein; Sodagar, Amir M; Sawan, Mohamad

2016-11-01

This paper reports on the design, implementation, and test of a stimulation back-end, for an implantable retinal prosthesis. In addition to traditional rectangular pulse shapes, the circuit features biphasic stimulation pulses with both rising and falling exponential shapes, whose time constants are digitally programmable. A class-B second generation current conveyor is used as a wide-swing, high-output-resistance stimulation current driver, delivering stimulation current pulses of up to ±96 μA to the target tissue. Duration of the generated current pulses is programmable within the range of 100 μs to 3 ms. Current-mode digital-to-analog converters (DACs) are used to program the amplitudes of the stimulation pulses. Fabricated using the IBM 130 nm process, the circuit consumes 1.5×1.5 mm 2 of silicon area. According to the measurements, the DACs exhibit DNL and INL of 0.23 LSB and 0.364 LSB, respectively. Experimental results indicate that the stimuli generator meets expected requirements when connected to electrode-tissue impedance of as high as 25 k Ω. Maximum power consumption of the proposed design is 3.4 mW when delivering biphasic rectangular pulses to the target load. A charge pump block is in charge of the upconversion of the standard 1.2-V supply voltage to ±3.3V.

Programmable nanometer-scale electrolytic metal deposition and depletion

DOEpatents

Lee, James Weifu [Oak Ridge, TN; Greenbaum, Elias [Oak Ridge, TN

2002-09-10

A method of nanometer-scale deposition of a metal onto a nanostructure includes the steps of: providing a substrate having thereon at least two electrically conductive nanostructures spaced no more than about 50 .mu.m apart; and depositing metal on at least one of the nanostructures by electric field-directed, programmable, pulsed electrolytic metal deposition. Moreover, a method of nanometer-scale depletion of a metal from a nanostructure includes the steps of providing a substrate having thereon at least two electrically conductive nanostructures spaced no more than about 50 .mu.m apart, at least one of the nanostructures having a metal disposed thereon; and depleting at least a portion of the metal from the nanostructure by electric field-directed, programmable, pulsed electrolytic metal depletion. A bypass circuit enables ultra-finely controlled deposition.

Nanoeletromechanical switch and logic circuits formed therefrom

DOEpatents

Nordquist, Christopher D [Albuquerque, NM; Czaplewski, David A [Albuquerque, NM

2010-05-18

A nanoelectromechanical (NEM) switch is formed on a substrate with a source electrode containing a suspended electrically-conductive beam which is anchored to the substrate at each end. This beam, which can be formed of ruthenium, bows laterally in response to a voltage applied between a pair of gate electrodes and the source electrode to form an electrical connection between the source electrode and a drain electrode located near a midpoint of the beam. Another pair of gate electrodes and another drain electrode can be located on an opposite side of the beam to allow for switching in an opposite direction. The NEM switch can be used to form digital logic circuits including NAND gates, NOR gates, programmable logic gates, and SRAM and DRAM memory cells which can be used in place of conventional CMOS circuits, or in combination therewith.

Liquid on Paper: Rapid Prototyping of Soft Functional Components for Paper Electronics

PubMed Central

Long Han, Yu; Liu, Hao; Ouyang, Cheng; Jian Lu, Tian; Xu, Feng

2015-01-01

This paper describes a novel approach to fabricate paper-based electric circuits consisting of a paper matrix embedded with three-dimensional (3D) microchannels and liquid metal. Leveraging the high electric conductivity and good flowability of liquid metal, and metallophobic property of paper, it is possible to keep electric and mechanical functionality of the electric circuit even after a thousand cycles of deformation. Embedding liquid metal into paper matrix is a promising method to rapidly fabricate low-cost, disposable, and soft electric circuits for electronics. As a demonstration, we designed a programmable displacement transducer and applied it as variable resistors and pressure sensors. The unique metallophobic property, combined with softness, low cost and light weight, makes paper an attractive alternative to other materials in which liquid metal are currently embedded. PMID:26129723

A shared synapse architecture for efficient FPGA implementation of autoencoders.

PubMed

Suzuki, Akihiro; Morie, Takashi; Tamukoh, Hakaru

2018-01-01

This paper proposes a shared synapse architecture for autoencoders (AEs), and implements an AE with the proposed architecture as a digital circuit on a field-programmable gate array (FPGA). In the proposed architecture, the values of the synapse weights are shared between the synapses of an input and a hidden layer, and between the synapses of a hidden and an output layer. This architecture utilizes less of the limited resources of an FPGA than an architecture which does not share the synapse weights, and reduces the amount of synapse modules used by half. For the proposed circuit to be implemented into various types of AEs, it utilizes three kinds of parameters; one to change the number of layers' units, one to change the bit width of an internal value, and a learning rate. By altering a network configuration using these parameters, the proposed architecture can be used to construct a stacked AE. The proposed circuits are logically synthesized, and the number of their resources is determined. Our experimental results show that single and stacked AE circuits utilizing the proposed shared synapse architecture operate as regular AEs and as regular stacked AEs. The scalability of the proposed circuit and the relationship between the bit widths and the learning results are also determined. The clock cycles of the proposed circuits are formulated, and this formula is used to estimate the theoretical performance of the circuit when the circuit is used to construct arbitrary networks.

A shared synapse architecture for efficient FPGA implementation of autoencoders

PubMed Central

Morie, Takashi; Tamukoh, Hakaru

2018-01-01

This paper proposes a shared synapse architecture for autoencoders (AEs), and implements an AE with the proposed architecture as a digital circuit on a field-programmable gate array (FPGA). In the proposed architecture, the values of the synapse weights are shared between the synapses of an input and a hidden layer, and between the synapses of a hidden and an output layer. This architecture utilizes less of the limited resources of an FPGA than an architecture which does not share the synapse weights, and reduces the amount of synapse modules used by half. For the proposed circuit to be implemented into various types of AEs, it utilizes three kinds of parameters; one to change the number of layers’ units, one to change the bit width of an internal value, and a learning rate. By altering a network configuration using these parameters, the proposed architecture can be used to construct a stacked AE. The proposed circuits are logically synthesized, and the number of their resources is determined. Our experimental results show that single and stacked AE circuits utilizing the proposed shared synapse architecture operate as regular AEs and as regular stacked AEs. The scalability of the proposed circuit and the relationship between the bit widths and the learning results are also determined. The clock cycles of the proposed circuits are formulated, and this formula is used to estimate the theoretical performance of the circuit when the circuit is used to construct arbitrary networks. PMID:29543909

An Undergraduate Survey Course on Asynchronous Sequential Logic, Ladder Logic, and Fuzzy Logic

ERIC Educational Resources Information Center

Foster, D. L.

2012-01-01

For a basic foundation in computer engineering, universities traditionally teach synchronous sequential circuit design, using discrete gates or field programmable gate arrays, and a microcomputers course that includes basic I/O processing. These courses, though critical, expose students to only a small subset of tools. At co-op schools like…

An Analysis of Heavy-Ion Single Event Effects for a Variety of Finite State-Machine Mitigation Strategies

NASA Technical Reports Server (NTRS)

Berg, Melanie D.; Label, Kenneth A.; Kim, Hak; Phan, Anthony; Seidleck, Christina

2014-01-01

Finite state-machines (FSMs) are used to control operational flow in application specific integrated circuits (ASICs) and field programmable gate array (FPGA) devices. Because of their ease of interpretation, FSMs simplify the design and verification process and consequently are significant components in a synchronous design.

Design of resolution/power controllable Asynchronous Sigma-Delta Modulator

NASA Astrophysics Data System (ADS)

Deshmukh, Anita Arvind; Deshmukh, Raghvendra B.

2016-12-01

This paper presents the design of a Programmable Asynchronous Modulator (PAM) with field control of resolution and power. A novel variable hysteresis Schmitt Trigger (ST) is used for external programmability. Asynchronous Sigma-Delta Modulator (ASDM) implementation with external control voltages is proposed to supervise the resolution and power. This architecture with reduced circuit complexity considerably improves the earlier realizations by eliminating multiple current sources as well switched capacitor circuits and results in power saving up to 87 %. Proposed PAM design demonstrates an improved SNDR of 115 dB, DR of 96 dB, and power consumption below 280 μW. It illustrates Effective Number of Bits (ENOB) to 18.81 and Figure of Merit (FoM) to 0.15 fJ/conversion step. Modulator is implemented in Cadence UMC Hspice 0.18 μm CMOS analog technology. Off-chip PAM control for resolution/power performance has potential applications in battery operated ultra low power applications like IoT; where ADC is one of the major power consuming components. It offers the promise for an efficient performance with power saving.

A SPAD-based 3D imager with in-pixel TDC for 145ps-accuracy ToF measurement

NASA Astrophysics Data System (ADS)

Vornicu, I.; Carmona-Galán, R.; Rodríguez-Vázquez, Á.

2015-03-01

The design and measurements of a CMOS 64 × 64 Single-Photon Avalanche-Diode (SPAD) array with in-pixel Time-to-Digital Converter (TDC) are presented. This paper thoroughly describes the imager at architectural and circuit level with particular emphasis on the characterization of the SPAD-detector ensemble. It is aimed to 2D imaging and 3D image reconstruction in low light environments. It has been fabricated in a standard 0.18μm CMOS process, i. e. without high voltage or low noise features. In these circumstances, we are facing a high number of dark counts and low photon detection efficiency. Several techniques have been applied to ensure proper functionality, namely: i) time-gated SPAD front-end with fast active-quenching/recharge circuit featuring tunable dead-time, ii) reverse start-stop scheme, iii) programmable time resolution of the TDC based on a novel pseudo-differential voltage controlled ring oscillator with fast start-up, iv) a global calibration scheme against temperature and process variation. Measurements results of individual SPAD-TDC ensemble jitter, array uniformity and time resolution programmability are also provided.

An integrated interface for peripheral neural system recording and stimulation: system design, electrical tests and in-vivo results.

PubMed

Carboni, Caterina; Bisoni, Lorenzo; Carta, Nicola; Puddu, Roberto; Raspopovic, Stanisa; Navarro, Xavier; Raffo, Luigi; Barbaro, Massimo

2016-04-01

The prototype of an electronic bi-directional interface between the Peripheral Nervous System (PNS) and a neuro-controlled hand prosthesis is presented. The system is composed of 2 integrated circuits: a standard CMOS device for neural recording and a HVCMOS device for neural stimulation. The integrated circuits have been realized in 2 different 0.35μ m CMOS processes available from ams. The complete system incorporates 8 channels each including the analog front-end, the A/D conversion, based on a sigma delta architecture and a programmable stimulation module implemented as a 5-bit current DAC; two voltage boosters supply the output stimulation stage with a programmable voltage scalable up to 17V. Successful in-vivo experiments with rats having a TIME electrode implanted in the sciatic nerve were carried out, showing the capability of recording neural signals in the tens of microvolts, with a global noise of 7μ V r m s , and to selectively elicit the tibial and plantar muscles using different active sites of the electrode.

Design of a Programmable Gain, Temperature Compensated Current-Input Current-Output CMOS Logarithmic Amplifier.

PubMed

Ming Gu; Chakrabartty, Shantanu

2014-06-01

This paper presents the design of a programmable gain, temperature compensated, current-mode CMOS logarithmic amplifier that can be used for biomedical signal processing. Unlike conventional logarithmic amplifiers that use a transimpedance technique to generate a voltage signal as a logarithmic function of the input current, the proposed approach directly produces a current output as a logarithmic function of the input current. Also, unlike a conventional transimpedance amplifier the gain of the proposed logarithmic amplifier can be programmed using floating-gate trimming circuits. The synthesis of the proposed circuit is based on the Hart's extended translinear principle which involves embedding a floating-voltage source and a linear resistive element within a translinear loop. Temperature compensation is then achieved using a translinear-based resistive cancelation technique. Measured results from prototypes fabricated in a 0.5 μm CMOS process show that the amplifier has an input dynamic range of 120 dB and a temperature sensitivity of 230 ppm/°C (27 °C- 57°C), while consuming less than 100 nW of power.

Programmable Thermostats for MPLM Shell Heater Control ULF1. 1; Thermal Performances

NASA Technical Reports Server (NTRS)

Glasgow, Shaun; Clark, Dallas; Trichilo, Michele; Trichilo, Michele

2007-01-01

The Multi-Purpose Logistics Module (MPLM) is the primary carrier for "pressurized" logistics to and from the International Space Station (ISS). The MPLM is transported in the payload bay of the Space Shuttle and is docked to the ISS for unloading, and reloading, of contents within the ISS shirt sleeve environment. Foil heaters, controlled originally with bi-metallic thermostats, are distributed across the outside of the MPLM structure and are utilized to provide energy to the structure to avoid exposure to cold temperatures and prevent condensation. The existing bi-metallic, fixed temperature set point thermostats have been replaced with Programmable Thermostats Modules (PTMs) in the Passive Thermal Control Subsystem (PTCS) 28Vdc shell heater circuits. The goal of using the PTM thermostat is to improve operational efficiency of the MPLM on-orbit shell heaters by providing better shell temperature control via feedback control capability. Each heater circuit contains a programmable thermostat connected to an external temperature sensor, a Resistive Temperature Device (RTD), which is used to provide continuous temperature monitoring capability. Each thermostat has programmable temperature set points and control spans. The data acquisition system uses a standard RS-485 serial interface communications cable to provide digital control capability. The PTM system was designed by MSFC, relying upon ALTEC support for their integration within the MPLM system design, while KSC performed the installation and ground checkout testing of the thermostat and RS-485 communication cable on the MPLM FM1 flight module. The PTMs were used for the first time during the STS-121/ULF1.1 mission. This paper will describe the design, development and verification of the PTM system, as well as the PTM flight performance and comparisons with SINDA thermal model predictions.

Miniature Intelligent Sensor Module

NASA Technical Reports Server (NTRS)

Beech, Russell S.

2007-01-01

An electronic unit denoted the Miniature Intelligent Sensor Module performs sensor-signal-conditioning functions and local processing of sensor data. The unit includes four channels of analog input/output circuitry, a processor, volatile and nonvolatile memory, and two Ethernet communication ports, all housed in a weathertight enclosure. The unit accepts AC or DC power. The analog inputs provide programmable gain, offset, and filtering as well as shunt calibration and auto-zeroing. Analog outputs include sine, square, and triangular waves having programmable frequencies and amplitudes, as well as programmable amplitude DC. One innovative aspect of the design of this unit is the integration of a relatively powerful processor and large amount of memory along with the sensor-signalconditioning circuitry so that sophisticated computer programs can be used to acquire and analyze sensor data and estimate and track the health of the overall sensor-data-acquisition system of which the unit is a part. The unit includes calibration, zeroing, and signalfeedback circuitry to facilitate health monitoring. The processor is also integrated with programmable logic circuitry in such a manner as to simplify and enhance acquisition of data and generation of analog outputs. A notable unique feature of the unit is a cold-junction compensation circuit in the back shell of a sensor connector. This circuit makes it possible to use Ktype thermocouples without compromising a housing seal. Replicas of this unit may prove useful in industrial and manufacturing settings - especially in such large outdoor facilities as refineries. Two features can be expected to simplify installation: the weathertight housings should make it possible to mount the units near sensors, and the Ethernet communication capability of the units should facilitate establishment of communication connections for the units.

Memristor-CMOS hybrid integrated circuits for reconfigurable logic.

PubMed

Xia, Qiangfei; Robinett, Warren; Cumbie, Michael W; Banerjee, Neel; Cardinali, Thomas J; Yang, J Joshua; Wu, Wei; Li, Xuema; Tong, William M; Strukov, Dmitri B; Snider, Gregory S; Medeiros-Ribeiro, Gilberto; Williams, R Stanley

2009-10-01

Hybrid reconfigurable logic circuits were fabricated by integrating memristor-based crossbars onto a foundry-built CMOS (complementary metal-oxide-semiconductor) platform using nanoimprint lithography, as well as materials and processes that were compatible with the CMOS. Titanium dioxide thin-film memristors served as the configuration bits and switches in a data routing network and were connected to gate-level CMOS components that acted as logic elements, in a manner similar to a field programmable gate array. We analyzed the chips using a purpose-built testing system, and demonstrated the ability to configure individual devices, use them to wire up various logic gates and a flip-flop, and then reconfigure devices.

Nonlinear dynamics based digital logic and circuits.

PubMed

Kia, Behnam; Lindner, John F; Ditto, William L

2015-01-01

We discuss the role and importance of dynamics in the brain and biological neural networks and argue that dynamics is one of the main missing elements in conventional Boolean logic and circuits. We summarize a simple dynamics based computing method, and categorize different techniques that we have introduced to realize logic, functionality, and programmability. We discuss the role and importance of coupled dynamics in networks of biological excitable cells, and then review our simple coupled dynamics based method for computing. In this paper, for the first time, we show how dynamics can be used and programmed to implement computation in any given base, including but not limited to base two.

Sequence invariant state machines

NASA Technical Reports Server (NTRS)

Whitaker, S.; Manjunath, S.

1990-01-01

A synthesis method and new VLSI architecture are introduced to realize sequential circuits that have the ability to implement any state machine having N states and m inputs, regardless of the actual sequence specified in the flow table. A design method is proposed that utilizes BTS logic to implement regular and dense circuits. A given state sequence can be programmed with power supply connections or dynamically reallocated if stored in a register. Arbitrary flow table sequences can be modified or programmed to dynamically alter the function of the machine. This allows VLSI controllers to be designed with the programmability of a general purpose processor but with the compact size and performance of dedicated logic.

Sequence-invariant state machines

NASA Technical Reports Server (NTRS)

Whitaker, Sterling R.; Manjunath, Shamanna K.; Maki, Gary K.

1991-01-01

A synthesis method and an MOS VLSI architecture are presented to realize sequential circuits that have the ability to implement any state machine having N states and m inputs, regardless of the actual sequence specified in the flow table. The design method utilizes binary tree structured (BTS) logic to implement regular and dense circuits. The desired state sequence can be hardwired with power supply connections or can be dynamically reallocated if stored in a register. This allows programmable VLSI controllers to be designed with a compact size and performance approaching that of dedicated logic. Results of ICV implementations are reported and an example sequence-invariant state machine is contrasted with implementations based on traditional methods.

Radiation-Tolerant Intelligent Memory Stack - RTIMS

NASA Technical Reports Server (NTRS)

Ng, Tak-kwong; Herath, Jeffrey A.

2011-01-01

This innovation provides reconfigurable circuitry and 2-Gb of error-corrected or 1-Gb of triple-redundant digital memory in a small package. RTIMS uses circuit stacking of heterogeneous components and radiation shielding technologies. A reprogrammable field-programmable gate array (FPGA), six synchronous dynamic random access memories, linear regulator, and the radiation mitigation circuits are stacked into a module of 42.7 42.7 13 mm. Triple module redundancy, current limiting, configuration scrubbing, and single- event function interrupt detection are employed to mitigate radiation effects. The novel self-scrubbing and single event functional interrupt (SEFI) detection allows a relatively soft FPGA to become radiation tolerant without external scrubbing and monitoring hardware

Demonstration of nonreciprocity in a microwave cavity optomechanical circuit

NASA Astrophysics Data System (ADS)

Peterson, Gabriel; Lecocq, Florent; Kotler, Shlomi; Cicak, Katarina; Simmonds, Raymond; Aumentado, Jose; Teufel, John

The ability to engineer nonreciprocal interactions is essential for many applications including quantum signal processing and quantum transduction. While attributes such as high efficiency and low added noise are always beneficial, for quantum applications these metrics are crucial. Here we present recent experimental results on a parametric, nonreciprocal microwave circuit based on the optomechanical interaction between a superconducting microwave resonator and a mechanically compliant vacuum gap capacitor. Unlike standard Faraday-based circulators, this parametric interaction does not require magnetic fields, and the direction of circulation can be controlled dynamically in situ. Looking forward, such devices could enable programmable, high-efficiency connections between disparate nodes of a quantum network.

Design of Timer Circuit for Dynamic Data System

NASA Technical Reports Server (NTRS)

Young, Nathaniel, III

2004-01-01

The Branch That I work in is in the Aero Electronic Test Branch, which is part of the Research and Testing Division. The Aero Electronic Test Branch deals with electronic control and instrumentation systems. This branch supports the research and test study of wind tunnels such as the l0x10,9x15, and 8x6. Wind tunnels are used in research to test certain parts of a jet, plane, shuttle or any other flying object in certain test conditions. My assignment is to design a programmable trigger circuit on a 19 standard rack mount that will allow the circuit to latch and hold for a predefined amount of time entered by the user when receiving a signal. It should then re-arm itself within 0.25 seconds after the time is finished. The time should be able to be seen on a display showing the time entered. The time range has to be from 0-600 seconds in 0.01 second increments (600.00). From the information given, counters will be needed to design and build this circuit. A counter, in it s simplest form, is a group of flip flops that can temporarily store bits of information put into the circuit. They can be constructed in many different ways, such as in 4 flip flops (4-bit counter) or 8 flip flops and even higher. Counters are usually cascaded with other counters to reach higher bits, such as 16 or 24 bit counters. The application in which I will use the counters will be to count down from any programmable number that I input either by a keyboard or a thumbwheel. Also, I will use counters that will be used specifically as a frequency divider to divide the pulses that enter the circuit through an input signal from a crystal clock. The pulses will need to be divided so that it will function as a 100Hz clock putting out 100 pulses per second. A switch will be used to load my inputs in and more than likely a button also so that I can stop and hold the count at any point of time. I will use 5 BCD up/down programmable counters, and a certain amount (depending on what kind of "divide by N" counter I use) of frequency dividing counters for the assignment. After the design is carefully made, a task order will be written and then given to the manufacturer to create a rack mount circuit board that will match my specifications given. The applications in which this design will be used for is in the use of the six-component balance signal conditioner for measurement and electronic system control. It can be used as a timer system for the balance signal conditioner in which it does numerous tests for the Wind tunnel research, in which a preset time can be set for how long it performs its tests. Specifically, my design should be applied to the balance signal conditioner used for the 8x6 wind tunnel research. Hopefully this design should aid in more efficient research for the 8x6 wind tunnel.

Programmable logic construction kits for hyper-real-time neuronal modeling.

PubMed

Guerrero-Rivera, Ruben; Morrison, Abigail; Diesmann, Markus; Pearce, Tim C

2006-11-01

Programmable logic designs are presented that achieve exact integration of leaky integrate-and-fire soma and dynamical synapse neuronal models and incorporate spike-time dependent plasticity and axonal delays. Highly accurate numerical performance has been achieved by modifying simpler forward-Euler-based circuitry requiring minimal circuit allocation, which, as we show, behaves equivalently to exact integration. These designs have been implemented and simulated at the behavioral and physical device levels, demonstrating close agreement with both numerical and analytical results. By exploiting finely grained parallelism and single clock cycle numerical iteration, these designs achieve simulation speeds at least five orders of magnitude faster than the nervous system, termed here hyper-real-time operation, when deployed on commercially available field-programmable gate array (FPGA) devices. Taken together, our designs form a programmable logic construction kit of commonly used neuronal model elements that supports the building of large and complex architectures of spiking neuron networks for real-time neuromorphic implementation, neurophysiological interfacing, or efficient parameter space investigations.

Programmable neural processing on a smartdust for brain-computer interfaces.

PubMed

Yuwen Sun; Shimeng Huang; Oresko, Joseph J; Cheng, Allen C

2010-10-01

Brain-computer interfaces (BCIs) offer tremendous promise for improving the quality of life for disabled individuals. BCIs use spike sorting to identify the source of each neural firing. To date, spike sorting has been performed by either using off-chip analysis, which requires a wired connection penetrating the skull to a bulky external power/processing unit, or via custom application-specific integrated circuits that lack the programmability to perform different algorithms and upgrades. In this research, we propose and test the feasibility of performing on-chip, real-time spike sorting on a programmable smartdust, including feature extraction, classification, compression, and wireless transmission. A detailed power/performance tradeoff analysis using DVFS is presented. Our experimental results show that the execution time and power density meet the requirements to perform real-time spike sorting and wireless transmission on a single neural channel.

Paper-based Synthetic Gene Networks

PubMed Central

Pardee, Keith; Green, Alexander A.; Ferrante, Tom; Cameron, D. Ewen; DaleyKeyser, Ajay; Yin, Peng; Collins, James J.

2014-01-01

Synthetic gene networks have wide-ranging uses in reprogramming and rewiring organisms. To date, there has not been a way to harness the vast potential of these networks beyond the constraints of a laboratory or in vivo environment. Here, we present an in vitro paper-based platform that provides a new venue for synthetic biologists to operate, and a much-needed medium for the safe deployment of engineered gene circuits beyond the lab. Commercially available cell-free systems are freeze-dried onto paper, enabling the inexpensive, sterile and abiotic distribution of synthetic biology-based technologies for the clinic, global health, industry, research and education. For field use, we create circuits with colorimetric outputs for detection by eye, and fabricate a low-cost, electronic optical interface. We demonstrate this technology with small molecule and RNA actuation of genetic switches, rapid prototyping of complex gene circuits, and programmable in vitro diagnostics, including glucose sensors and strain-specific Ebola virus sensors. PMID:25417167

Paper-based synthetic gene networks.

PubMed

Pardee, Keith; Green, Alexander A; Ferrante, Tom; Cameron, D Ewen; DaleyKeyser, Ajay; Yin, Peng; Collins, James J

2014-11-06

Synthetic gene networks have wide-ranging uses in reprogramming and rewiring organisms. To date, there has not been a way to harness the vast potential of these networks beyond the constraints of a laboratory or in vivo environment. Here, we present an in vitro paper-based platform that provides an alternate, versatile venue for synthetic biologists to operate and a much-needed medium for the safe deployment of engineered gene circuits beyond the lab. Commercially available cell-free systems are freeze dried onto paper, enabling the inexpensive, sterile, and abiotic distribution of synthetic-biology-based technologies for the clinic, global health, industry, research, and education. For field use, we create circuits with colorimetric outputs for detection by eye and fabricate a low-cost, electronic optical interface. We demonstrate this technology with small-molecule and RNA actuation of genetic switches, rapid prototyping of complex gene circuits, and programmable in vitro diagnostics, including glucose sensors and strain-specific Ebola virus sensors.

A visually guided collision warning system with a neuromorphic architecture.

PubMed

Okuno, Hirotsugu; Yagi, Tetsuya

2008-12-01

We have designed a visually guided collision warning system with a neuromorphic architecture, employing an algorithm inspired by the visual nervous system of locusts. The system was implemented with mixed analog-digital integrated circuits consisting of an analog resistive network and field-programmable gate array (FPGA) circuits. The resistive network processes the interaction between the laterally spreading excitatory and inhibitory signals instantaneously, which is essential for real-time computation of collision avoidance with a low power consumption and a compact hardware. The system responded selectively to approaching objects of simulated movie images at close range. The system was, however, confronted with serious noise problems due to the vibratory ego-motion, when it was installed in a mobile miniature car. To overcome this problem, we developed the algorithm, which is also installable in FPGA circuits, in order for the system to respond robustly during the ego-motion.

Integrated Circuits/Segregated Labor: Women in Three Computer-Related Occupations. Project Report No. 84-A27.

ERIC Educational Resources Information Center

Strober, Myra H.; Arnold, Carolyn L.

This discussion of the impact of new computer occupations on women's employment patterns is divided into four major sections. The first section describes the six computer-related occupations to be analyzed: (1) engineers; (2) computer scientists and systems analysts; (3) programmers; (4) electronic technicians; (5) computer operators; and (6) data…

Bus-Programmable Slave Card

NASA Technical Reports Server (NTRS)

Hall, William A.

1990-01-01

Slave microprocessors in multimicroprocessor computing system contains modified circuit cards programmed via bus connecting master processor with slave microprocessors. Enables interactive, microprocessor-based, single-loop control. Confers ability to load and run program from master/slave bus, without need for microprocessor development station. Tristate buffers latch all data and information on status. Slave central processing unit never connected directly to bus.

The Department of Defense Very High Speed Integrated Circuit (VHSIC) Technology Availability Program Plan for the Committees on Armed Services United States Congress.

DTIC Science & Technology

1986-06-30

features of computer aided design systems and statistical quality control procedures that are generic to chip sets and processes. RADIATION HARDNESS -The...System PSP Programmable Signal Processor SSI Small Scale Integration ." TOW Tube Launched, Optically Tracked, Wire Guided TTL Transistor Transitor Logic

Hardware Design and Implementation of a Wavelet De-Noising Procedure for Medical Signal Preprocessing

PubMed Central

Chen, Szi-Wen; Chen, Yuan-Ho

2015-01-01

In this paper, a discrete wavelet transform (DWT) based de-noising with its applications into the noise reduction for medical signal preprocessing is introduced. This work focuses on the hardware realization of a real-time wavelet de-noising procedure. The proposed de-noising circuit mainly consists of three modules: a DWT, a thresholding, and an inverse DWT (IDWT) modular circuits. We also proposed a novel adaptive thresholding scheme and incorporated it into our wavelet de-noising procedure. Performance was then evaluated on both the architectural designs of the software and. In addition, the de-noising circuit was also implemented by downloading the Verilog codes to a field programmable gate array (FPGA) based platform so that its ability in noise reduction may be further validated in actual practice. Simulation experiment results produced by applying a set of simulated noise-contaminated electrocardiogram (ECG) signals into the de-noising circuit showed that the circuit could not only desirably meet the requirement of real-time processing, but also achieve satisfactory performance for noise reduction, while the sharp features of the ECG signals can be well preserved. The proposed de-noising circuit was further synthesized using the Synopsys Design Compiler with an Artisan Taiwan Semiconductor Manufacturing Company (TSMC, Hsinchu, Taiwan) 40 nm standard cell library. The integrated circuit (IC) synthesis simulation results showed that the proposed design can achieve a clock frequency of 200 MHz and the power consumption was only 17.4 mW, when operated at 200 MHz. PMID:26501290

Hardware design and implementation of a wavelet de-noising procedure for medical signal preprocessing.

PubMed

Chen, Szi-Wen; Chen, Yuan-Ho

2015-10-16

In this paper, a discrete wavelet transform (DWT) based de-noising with its applications into the noise reduction for medical signal preprocessing is introduced. This work focuses on the hardware realization of a real-time wavelet de-noising procedure. The proposed de-noising circuit mainly consists of three modules: a DWT, a thresholding, and an inverse DWT (IDWT) modular circuits. We also proposed a novel adaptive thresholding scheme and incorporated it into our wavelet de-noising procedure. Performance was then evaluated on both the architectural designs of the software and. In addition, the de-noising circuit was also implemented by downloading the Verilog codes to a field programmable gate array (FPGA) based platform so that its ability in noise reduction may be further validated in actual practice. Simulation experiment results produced by applying a set of simulated noise-contaminated electrocardiogram (ECG) signals into the de-noising circuit showed that the circuit could not only desirably meet the requirement of real-time processing, but also achieve satisfactory performance for noise reduction, while the sharp features of the ECG signals can be well preserved. The proposed de-noising circuit was further synthesized using the Synopsys Design Compiler with an Artisan Taiwan Semiconductor Manufacturing Company (TSMC, Hsinchu, Taiwan) 40 nm standard cell library. The integrated circuit (IC) synthesis simulation results showed that the proposed design can achieve a clock frequency of 200 MHz and the power consumption was only 17.4 mW, when operated at 200 MHz.

Multilevel Resistance Programming in Conductive Bridge Resistive Memory

NASA Astrophysics Data System (ADS)

Mahalanabis, Debayan

This work focuses on the existence of multiple resistance states in a type of emerging non-volatile resistive memory device known commonly as Programmable Metallization Cell (PMC) or Conductive Bridge Random Access Memory (CBRAM), which can be important for applications such as multi-bit memory as well as non-volatile logic and neuromorphic computing. First, experimental data from small signal, quasi-static and pulsed mode electrical characterization of such devices are presented which clearly demonstrate the inherent multi-level resistance programmability property in CBRAM devices. A physics based analytical CBRAM compact model is then presented which simulates the ion-transport dynamics and filamentary growth mechanism that causes resistance change in such devices. Simulation results from the model are fitted to experimental dynamic resistance switching characteristics. The model designed using Verilog-a language is computation-efficient and can be integrated with industry standard circuit simulation tools for design and analysis of hybrid circuits involving both CMOS and CBRAM devices. Three main circuit applications for CBRAM devices are explored in this work. Firstly, the susceptibility of CBRAM memory arrays to single event induced upsets is analyzed via compact model simulation and experimental heavy ion testing data that show possibility of both high resistance to low resistance and low resistance to high resistance transitions due to ion strikes. Next, a non-volatile sense amplifier based flip-flop architecture is proposed which can help make leakage power consumption negligible by allowing complete shutdown of power supply while retaining its output data in CBRAM devices. Reliability and energy consumption of the flip-flop circuit for different CBRAM low resistance levels and supply voltage values are analyzed and compared to CMOS designs. Possible extension of this architecture for threshold logic function computation using the CBRAM devices as re-configurable resistive weights is also discussed. Lastly, Spike timing dependent plasticity (STDP) based gradual resistance change behavior in CBRAM device fabricated in back-end-of-line on a CMOS die containing integrate and fire CMOS neuron circuits is demonstrated for the first time which indicates the feasibility of using CBRAM devices as electronic synapses in spiking neural network hardware implementations for non-Boolean neuromorphic computing.

Prototype Focal-Plane-Array Optoelectronic Image Processor

NASA Technical Reports Server (NTRS)

Fang, Wai-Chi; Shaw, Timothy; Yu, Jeffrey

1995-01-01

Prototype very-large-scale integrated (VLSI) planar array of optoelectronic processing elements combines speed of optical input and output with flexibility of reconfiguration (programmability) of electronic processing medium. Basic concept of processor described in "Optical-Input, Optical-Output Morphological Processor" (NPO-18174). Performs binary operations on binary (black and white) images. Each processing element corresponds to one picture element of image and located at that picture element. Includes input-plane photodetector in form of parasitic phototransistor part of processing circuit. Output of each processing circuit used to modulate one picture element in output-plane liquid-crystal display device. Intended to implement morphological processing algorithms that transform image into set of features suitable for high-level processing; e.g., recognition.

Flexible implementation of front-end bioelectric signal amplifier using FPAA for telemedicine system.

PubMed

Chan, U Fai; Chan, Wai Wong; Pun, Sio Hang; Vai, Mang I; Mak, Peng Un

2007-01-01

Traditional/Current electronic circuits for Telemedicine have significant performance on certain bioelectric signal detection. However, it is rarely seen that can handle multiple signals without changing of hardware. This paper introduces a general front-end amplifier for various bioelectric signals based on Field Programmable Analogy Array (FPAA) Technology. Employing FPAA technology, the implemented amplifier can be adapted for various bioelectric signals without alternating the circuitry while its compact size (core parts < 2 cm2) provides an alternative solution for miniaturized Telemedicine system and Wearable Devices. The proposed design implementation has demonstrated, through successfully ECG and EMG signal extractions, a quick way to miniaturize analog biomedical circuit in a convenient and cost effective way.

Hybrid CMOS/Molecular Integrated Circuits

NASA Astrophysics Data System (ADS)

Stan, M. R.; Rose, G. S.; Ziegler, M. M.

CMOS silicon technologies are likely to run out of steam in the next 10-15 years despite revolutionary advances in the past few decades. Molecular and other nanoscale technologies show significant promise but it is unlikely that they will completely replace CMOS, at least in the near term. This chapter explores opportunities for using CMOS and nanotechnology to enhance and complement each other in hybrid circuits. As an example of such a hybrid CMOS/nano system, a nanoscale programmable logic array (PLA) based on majority logic is described along with its supplemental CMOS circuitry. It is believed that such systems will be able to sustain the historical advances in the semiconductor industry while addressing manufacturability, yield, power, cost, and performance challenges.

Radiation induced failures of complementary metal oxide semiconductor containing pacemakers: a potentially lethal complication

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lewin, A.A.; Serago, C.F.; Schwade, J.G.

1984-10-01

New multi-programmable pacemakers frequently employ complementary metal oxide semiconductors (CMOS). This circuitry appears more sensitive to the effects of ionizing radiation when compared to the semiconductor circuits used in older pacemakers. A case of radiation induced runaway pacemaker in a CMOS device is described. Because of this and other recent reports of radiation therapy-induced CMOS type pacemaker failure, these pacemakers should not be irradiated. If necessary, the pacemaker can be shielded or moved to a site which can be shielded before institution of radiation therapy. This is done to prevent damage to the CMOS circuit and the life threatening arrythmiasmore » which may result from such damage.« less

Operating manual: Fast response solar array simulator

NASA Technical Reports Server (NTRS)

Vonhatten, R.; Weimer, A.; Zerbel, D. W.

1971-01-01

The fast response solar array simulator (FRSAS) is a universal solar array simulator which features an AC response identical to that of a real array over a large range of DC operating points. In addition, short circuit current (I sub sc) and open circuit voltage (V sub oc) are digitally programmable over a wide range for use not only in simulating a wide range of array sizes, but also to simulate (I sub sc) and (V sub oc) variations with illumination and temperature. A means for simulation of current variations due to spinning is available. Provisions for remote control and monitoring, automatic failure sensing and warning, and a load simulator are also included.

EHW Approach to Temperature Compensation of Electronics

NASA Technical Reports Server (NTRS)

Stoica, Adrian

2004-01-01

Efforts are under way to apply the concept of evolvable hardware (EHW) to compensate for variations, with temperature, in the operational characteristics of electronic circuits. To maintain the required functionality of a given circuit at a temperature above or below the nominal operating temperature for which the circuit was originally designed, a new circuit would be evolved; moreover, to obtain the required functionality over a very wide temperature range, there would be evolved a number of circuits, each of which would satisfy the performance requirements over a small part of the total temperature range. The basic concepts and some specific implementations of EHW were described in a number of previous NASA Tech Briefs articles, namely, "Reconfigurable Arrays of Transistors for Evolvable Hardware" (NPO-20078), Vol. 25, No. 2 (February 2001), page 36; Evolutionary Automated Synthesis of Electronic Circuits (NPO- 20535), Vol. 26, No. 7 (July 2002), page 37; "Designing Reconfigurable Antennas Through Hardware Evolution" (NPO-20666), Vol. 26, No. 7 (July 2002), page 38; "Morphing in Evolutionary Synthesis of Electronic Circuits" (NPO-20837), Vol. 26, No. 8 (August 2002), page 31; "Mixtrinsic Evolutionary Synthesis of Electronic Circuits" (NPO-20773) Vol. 26, No. 8 (August 2002), page 32; and "Synthesis of Fuzzy-Logic Circuits in Evolvable Hardware" (NPO-21095) Vol. 26, No. 11 (November 2002), page 38. To recapitulate from the cited prior articles: EHW is characterized as evolutionary in a quasi-genetic sense. The essence of EHW is to construct and test a sequence of populations of circuits that function as incrementally better solutions of a given design problem through the selective, repetitive connection and/or disconnection of capacitors, transistors, amplifiers, inverters, and/or other circuit building blocks. The connection and disconnection can be effected by use of field-programmable transistor arrays (FPTAs). The evolution is guided by a search-andoptimization algorithm (in particular, a genetic algorithm) that operates in the space of possible circuits to find a circuit that exhibits an acceptably close approximation of the desired functionality. The evolved circuits can be tested by mathematical modeling (that is, computational simulation) only, tested in real hardware, or tested in combinations of computational simulation and real hardware.

Programmable Oscillator

NASA Technical Reports Server (NTRS)

Quirk, Kevin J.; Patawaran, Ferze D.; Nguyen, Danh H.; Lee, Clement G.; Nguyen, Huy

2011-01-01

A programmable oscillator is a frequency synthesizer with an output phase that tracks an arbitrary function. An offset, phase-locked loop circuit is used in combination with an error control feedback loop to precisely control the output phase of the oscillator. To down-convert the received signal, several stages of mixing may be employed with the compensation for the time-base distortion of the carrier occurring at any one of those stages. In the Goldstone Solar System Radar (GSSR), the compensation occurs in the mixing from an intermediate frequency (IF), whose value is dependent on the station and band, to a common IF used in the final stage of down-conversion to baseband. The programmable oscillator (PO) is used in the final stage of down-conversion to generate the IF, along with a time-varying phase component that matches the time-base distortion of the carrier, thus removing it from the final down-converted signal.

Self-Adaptive System based on Field Programmable Gate Array for Extreme Temperature Electronics

NASA Technical Reports Server (NTRS)

Keymeulen, Didier; Zebulum, Ricardo; Rajeshuni, Ramesham; Stoica, Adrian; Katkoori, Srinivas; Graves, Sharon; Novak, Frank; Antill, Charles

2006-01-01

In this work, we report the implementation of a self-adaptive system using a field programmable gate array (FPGA) and data converters. The self-adaptive system can autonomously recover the lost functionality of a reconfigurable analog array (RAA) integrated circuit (IC) [3]. Both the RAA IC and the self-adaptive system are operating in extreme temperatures (from 120 C down to -180 C). The RAA IC consists of reconfigurable analog blocks interconnected by several switches and programmable by bias voltages. It implements filters/amplifiers with bandwidth up to 20 MHz. The self-adaptive system controls the RAA IC and is realized on Commercial-Off-The-Shelf (COTS) parts. It implements a basic compensation algorithm that corrects a RAA IC in less than a few milliseconds. Experimental results for the cold temperature environment (down to -180 C) demonstrate the feasibility of this approach.

Design of a wideband CMOS impedance spectroscopy ASIC analog front-end for multichannel biosensor interfaces.

PubMed

Valente, Virgilio; Dai Jiang; Demosthenous, Andreas

2015-08-01

This paper presents the preliminary design and simulation of a flexible and programmable analog front-end (AFE) circuit with current and voltage readout capabilities for electric impedance spectroscopy (EIS). The AFE is part of a fully integrated multifrequency EIS platform. The current readout comprises of a transimpedance stage and an automatic gain control (AGC) unit designed to accommodate impedance changes larger than 3 order of magnitude. The AGC is based on a dynamic peak detector that tracks changes in the input current over time and regulates the gain of a programmable gain amplifier in order to optimise the signal-to-noise ratio. The system works up to 1 MHz. The voltage readout consists of a 2 stages of fully differential current-feedback instrumentation amplifier which provide 100 dB of CMRR and a programmable gain up to 20 V/V per stage with a bandwidth in excess of 10MHz.

Rad-Hard Structured ASIC Body of Knowledge

NASA Technical Reports Server (NTRS)

Heidecker, Jason

2013-01-01

Structured Application-Specific Integrated Circuit (ASIC) technology is a platform between traditional ASICs and Field-Programmable Gate Arrays (FPGA). The motivation behind structured ASICs is to combine the low nonrecurring engineering costs (NRE) costs of FPGAs with the high performance of ASICs. This report provides an overview of the structured ASIC platforms that are radiation-hardened and intended for space application

Field Programmable Gate Aray (FPGA) Radiation Data: All Data is Not Equal

NASA Technical Reports Server (NTRS)

Label, Kenneth A.; Berg, Melanie D.

2016-01-01

Electronic parts (integrated circuits) have grown in complexity such that determining all failure modes and risks based on single particle event radiation testing is impossible. In this presentation, the authors will present why this is so and provide some realism on what this means to FPGAs. Its all about understanding actual risks and not making assumptions.

Controllable 0–π Josephson junctions containing a ferromagnetic spin valve

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gingrich, E. C.; Niedzielski, Bethany M.; Glick, Joseph A.

Superconductivity and ferromagnetism are antagonistic forms of order, and rarely coexist. Many interesting new phenomena occur, however, in hybrid superconducting/ferromagnetic systems. For example, a Josephson junction containing a ferromagnetic material can exhibit an intrinsic phase shift of π in its ground state for certain thicknesses of the material. Such ‘π-junctions’ were first realized experimentally in 2001, and have been proposed as circuit elements for both high-speed classical superconducting computing and for quantum computing. Here we demonstrate experimentally that the phase state of a Josephson junction containing two ferromagnetic layers can be toggled between 0 and pi by changing the relativemore » orientation of the two magnetizations. These controllable 0–π junctions have immediate applications in cryogenic memory, where they serve as a necessary component to an ultralow power superconducting computer. Such a fully superconducting computer is estimated to be orders of magnitude more energy-efficient than current semiconductor-based supercomputers. Here, phase-controllable junctions also open up new possibilities for superconducting circuit elements such as superconducting ‘programmable logic’, where they could function in superconducting analogues to field-programmable gate arrays.« less

Theory and implementation of a very high throughput true random number generator in field programmable gate array

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Yonggang, E-mail: wangyg@ustc.edu.cn; Hui, Cong; Liu, Chong

The contribution of this paper is proposing a new entropy extraction mechanism based on sampling phase jitter in ring oscillators to make a high throughput true random number generator in a field programmable gate array (FPGA) practical. Starting from experimental observation and analysis of the entropy source in FPGA, a multi-phase sampling method is exploited to harvest the clock jitter with a maximum entropy and fast sampling speed. This parametrized design is implemented in a Xilinx Artix-7 FPGA, where the carry chains in the FPGA are explored to realize the precise phase shifting. The generator circuit is simple and resource-saving,more » so that multiple generation channels can run in parallel to scale the output throughput for specific applications. The prototype integrates 64 circuit units in the FPGA to provide a total output throughput of 7.68 Gbps, which meets the requirement of current high-speed quantum key distribution systems. The randomness evaluation, as well as its robustness to ambient temperature, confirms that the new method in a purely digital fashion can provide high-speed high-quality random bit sequences for a variety of embedded applications.« less

Theory and implementation of a very high throughput true random number generator in field programmable gate array.

PubMed

Wang, Yonggang; Hui, Cong; Liu, Chong; Xu, Chao

2016-04-01

The contribution of this paper is proposing a new entropy extraction mechanism based on sampling phase jitter in ring oscillators to make a high throughput true random number generator in a field programmable gate array (FPGA) practical. Starting from experimental observation and analysis of the entropy source in FPGA, a multi-phase sampling method is exploited to harvest the clock jitter with a maximum entropy and fast sampling speed. This parametrized design is implemented in a Xilinx Artix-7 FPGA, where the carry chains in the FPGA are explored to realize the precise phase shifting. The generator circuit is simple and resource-saving, so that multiple generation channels can run in parallel to scale the output throughput for specific applications. The prototype integrates 64 circuit units in the FPGA to provide a total output throughput of 7.68 Gbps, which meets the requirement of current high-speed quantum key distribution systems. The randomness evaluation, as well as its robustness to ambient temperature, confirms that the new method in a purely digital fashion can provide high-speed high-quality random bit sequences for a variety of embedded applications.

Programmable single-cell mammalian biocomputers.

PubMed

Ausländer, Simon; Ausländer, David; Müller, Marius; Wieland, Markus; Fussenegger, Martin

2012-07-05

Synthetic biology has advanced the design of standardized control devices that program cellular functions and metabolic activities in living organisms. Rational interconnection of these synthetic switches resulted in increasingly complex designer networks that execute input-triggered genetic instructions with precision, robustness and computational logic reminiscent of electronic circuits. Using trigger-controlled transcription factors, which independently control gene expression, and RNA-binding proteins that inhibit the translation of transcripts harbouring specific RNA target motifs, we have designed a set of synthetic transcription–translation control devices that could be rewired in a plug-and-play manner. Here we show that these combinatorial circuits integrated a two-molecule input and performed digital computations with NOT, AND, NAND and N-IMPLY expression logic in single mammalian cells. Functional interconnection of two N-IMPLY variants resulted in bitwise intracellular XOR operations, and a combinatorial arrangement of three logic gates enabled independent cells to perform programmable half-subtractor and half-adder calculations. Individual mammalian cells capable of executing basic molecular arithmetic functions isolated or coordinated to metabolic activities in a predictable, precise and robust manner may provide new treatment strategies and bio-electronic interfaces in future gene-based and cell-based therapies.

Controllable 0–π Josephson junctions containing a ferromagnetic spin valve

DOE PAGES

Gingrich, E. C.; Niedzielski, Bethany M.; Glick, Joseph A.; ...

2016-03-14

Superconductivity and ferromagnetism are antagonistic forms of order, and rarely coexist. Many interesting new phenomena occur, however, in hybrid superconducting/ferromagnetic systems. For example, a Josephson junction containing a ferromagnetic material can exhibit an intrinsic phase shift of π in its ground state for certain thicknesses of the material. Such ‘π-junctions’ were first realized experimentally in 2001, and have been proposed as circuit elements for both high-speed classical superconducting computing and for quantum computing. Here we demonstrate experimentally that the phase state of a Josephson junction containing two ferromagnetic layers can be toggled between 0 and pi by changing the relativemore » orientation of the two magnetizations. These controllable 0–π junctions have immediate applications in cryogenic memory, where they serve as a necessary component to an ultralow power superconducting computer. Such a fully superconducting computer is estimated to be orders of magnitude more energy-efficient than current semiconductor-based supercomputers. Here, phase-controllable junctions also open up new possibilities for superconducting circuit elements such as superconducting ‘programmable logic’, where they could function in superconducting analogues to field-programmable gate arrays.« less

Nonreciprocal Microwave Signal Processing with a Field-Programmable Josephson Amplifier

NASA Astrophysics Data System (ADS)

Lecocq, F.; Ranzani, L.; Peterson, G. A.; Cicak, K.; Simmonds, R. W.; Teufel, J. D.; Aumentado, J.

2017-02-01

We report on the design and implementation of a field-programmable Josephson amplifier (FPJA)—a compact and lossless superconducting circuit that can be programmed in situ by a set of microwave drives to perform reciprocal and nonreciprocal frequency conversion and amplification. In this work, we demonstrate four modes of operation: frequency conversion (transmission of -0.5 dB, reflection of -30 dB), circulation (transmission of -0.5 dB, reflection of -30 dB, isolation of 30 dB), phase-preserving amplification (gain >20 dB , one photon of added noise) and directional phase-preserving amplification (reflection of -10 dB, forward gain of 18 dB, reverse isolation of 8 dB, one photon of added noise). The system exhibits quantitative agreement with the theoretical prediction. Based on a gradiometric superconducting quantum-interference device with Nb /Al -Al Ox/Nb Josephson junctions, the FPJA is first-order insensitive to flux noise and can be operated without magnetic shielding at low temperature. Owing to its flexible design and compatibility with existing superconducting fabrication techniques, the FPJA offers a straightforward route toward on-chip integration with superconducting quantum circuits such as qubits and microwave optomechanical systems.

Design Methodology of an Equalizer for Unipolar Non Return to Zero Binary Signals in the Presence of Additive White Gaussian Noise Using a Time Delay Neural Network on a Field Programmable Gate Array

PubMed Central

Pérez Suárez, Santiago T.; Travieso González, Carlos M.; Alonso Hernández, Jesús B.

2013-01-01

This article presents a design methodology for designing an artificial neural network as an equalizer for a binary signal. Firstly, the system is modelled in floating point format using Matlab. Afterward, the design is described for a Field Programmable Gate Array (FPGA) using fixed point format. The FPGA design is based on the System Generator from Xilinx, which is a design tool over Simulink of Matlab. System Generator allows one to design in a fast and flexible way. It uses low level details of the circuits and the functionality of the system can be fully tested. System Generator can be used to check the architecture and to analyse the effect of the number of bits on the system performance. Finally the System Generator design is compiled for the Xilinx Integrated System Environment (ISE) and the system is described using a hardware description language. In ISE the circuits are managed with high level details and physical performances are obtained. In the Conclusions section, some modifications are proposed to improve the methodology and to ensure portability across FPGA manufacturers.

Real-time monitoring of enzyme-free strand displacement cascades by colorimetric assays.

PubMed

Duan, Ruixue; Wang, Boya; Hong, Fan; Zhang, Tianchi; Jia, Yongmei; Huang, Jiayu; Hakeem, Abdul; Liu, Nannan; Lou, Xiaoding; Xia, Fan

2015-03-19

The enzyme-free toehold-mediated strand displacement reaction has shown potential for building programmable DNA circuits, biosensors, molecular machines and chemical reaction networks. Here we report a simple colorimetric method using gold nanoparticles as signal generators for the real-time detection of the product of the strand displacement cascade. During the process the assembled gold nanoparticles can be separated, resulting in a color change of the solution. This assay can also be applied in complex mixtures, fetal bovine serum, and to detect single-base mismatches. These results suggest that this method could be of general utility to monitor more complex enzyme-free strand displacement reaction-based programmable systems or for further low-cost diagnostic applications.

Self-Recovery Experiments in Extreme Environments Using a Field Programmable Transistor Array

NASA Technical Reports Server (NTRS)

Stoica, Adrian; Keymeulen, Didier; Arslan, Tughrul; Duong, Vu; Zebulum, Ricardo; Ferguson, Ian; Guo, Xin

2004-01-01

Temperature and radiation tolerant electronics, as well as long life survivability are key capabilities required for future NASA missions. Current approaches to electronics for extreme environments focus on component level robustness and hardening. However, current technology can only ensure very limited lifetime in extreme environments. This paper describes novel experiments that allow adaptive in-situ circuit redesign/reconfiguration during operation in extreme temperature and radiation environments. This technology would complement material/device advancements and increase the mission capability to survive harsh environments. The approach is demonstrated on a mixed-signal programmable chip (FPTA-2), which recovers functionality for temperatures until 28 C and with total radiation dose up to 250kRad.

Circuit design for the retina-like image sensor based on space-variant lens array

NASA Astrophysics Data System (ADS)

Gao, Hongxun; Hao, Qun; Jin, Xuefeng; Cao, Jie; Liu, Yue; Song, Yong; Fan, Fan

2013-12-01

Retina-like image sensor is based on the non-uniformity of the human eyes and the log-polar coordinate theory. It has advantages of high-quality data compression and redundant information elimination. However, retina-like image sensors based on the CMOS craft have drawbacks such as high cost, low sensitivity and signal outputting efficiency and updating inconvenience. Therefore, this paper proposes a retina-like image sensor based on space-variant lens array, focusing on the circuit design to provide circuit support to the whole system. The circuit includes the following parts: (1) A photo-detector array with a lens array to convert optical signals to electrical signals; (2) a strobe circuit for time-gating of the pixels and parallel paths for high-speed transmission of the data; (3) a high-precision digital potentiometer for the I-V conversion, ratio normalization and sensitivity adjustment, a programmable gain amplifier for automatic generation control(AGC), and a A/D converter for the A/D conversion in every path; (4) the digital data is displayed on LCD and stored temporarily in DDR2 SDRAM; (5) a USB port to transfer the data to PC; (6) the whole system is controlled by FPGA. This circuit has advantages as lower cost, larger pixels, updating convenience and higher signal outputting efficiency. Experiments have proved that the grayscale output of every pixel basically matches the target and a non-uniform image of the target is ideally achieved in real time. The circuit can provide adequate technical support to retina-like image sensors based on space-variant lens array.

Plastic-Based Structurally Programmable Microfluidic Biochips for Clinical Diagnostics

DTIC Science & Technology

2005-05-01

BIOCOMPATIBILITY CRITERIA OF SELECTED UV ADHESIVE LOCTITE 3211™......... 63 1 I. Executive Summary The objective of this project is to develop a smart...added into biochip design for improving the biocompatibility of entire biochip. Detailed problems include: • Design and development of structure... biocompatible biosensor array. 6 • Design and development of the sensor-to-circuit interface. Electronic Control System and Analyzer Design of the

Performance evaluation of coherent Ising machines against classical neural networks

NASA Astrophysics Data System (ADS)

Haribara, Yoshitaka; Ishikawa, Hitoshi; Utsunomiya, Shoko; Aihara, Kazuyuki; Yamamoto, Yoshihisa

2017-12-01

The coherent Ising machine is expected to find a near-optimal solution in various combinatorial optimization problems, which has been experimentally confirmed with optical parametric oscillators and a field programmable gate array circuit. The similar mathematical models were proposed three decades ago by Hopfield et al in the context of classical neural networks. In this article, we compare the computational performance of both models.

FPGA Boot Loader and Scrubber

NASA Technical Reports Server (NTRS)

Wade, Randall S.; Jones, Bailey

2009-01-01

A computer program loads configuration code into a Xilinx field-programmable gate array (FPGA), reads back and verifies that code, reloads the code if an error is detected, and monitors the performance of the FPGA for errors in the presence of radiation. The program consists mainly of a set of VHDL files (wherein "VHDL" signifies "VHSIC Hardware Description Language" and "VHSIC" signifies "very-high-speed integrated circuit").

CCD Analog Programmable Microprocessor (APUP) Study

DTIC Science & Technology

1980-08-01

so important to electronic warfare support measures applicatLons. A comprehensive imager develop- ment program is currently being formulated to... comprehensive treatment of this subject could easily fill a book as it has at least twice in the past (1,2) These textbooks F’ (3)are periodically updated... comprehensive treatment of circuit modeling, the resultant noise predictions are included here as expected values in further describing critical

Multi-GHz Synchronous Waveform Acquisition With Real-Time Pattern-Matching Trigger Generation

NASA Astrophysics Data System (ADS)

Kleinfelder, Stuart A.; Chiang, Shiuh-hua Wood; Huang, Wei

2013-10-01

A transient waveform capture and digitization circuit with continuous synchronous 2-GHz sampling capability and real-time programmable windowed trigger generation has been fabricated and tested. Designed in 0.25 μm CMOS, the digitizer contains a circular array of 128 sample and hold circuits for continuous sample acquisition, and attains 2-GHz sample speeds with over 800-MHz analog bandwidth. Sample clock generation is synchronous, combining a phase-locked loop for high-speed clock generation and a high-speed fully-differential shift register for distributing clocks to all 128 sample circuits. Using two comparators per sample, the sampled voltage levels are compared against two reference levels, a high threshold and a low threshold, that are set via per-comparator digital to analog converters (DACs). The 256 per-comparator 5-bit DACs compensate for comparator offsets and allow for fine reference level adjustment. The comparator results are matched in 8-sample-wide windows against up to 72 programmable patterns in real time using an on-chip programmable logic array. Each 8-sample trigger window is equivalent to 4 ns of acquisition, overlapped sample by sample in a circular fashion through the entire 128-sample array. The 72 pattern-matching trigger criteria can be programmed to be any combination of High-above the high threshold, Low-below the low threshold, Middle-between the two thresholds, or “Don't Care”-any state is accepted. A trigger pattern of “HLHLHLHL,” for example, watches for a waveform that is oscillating at about 1 GHz given the 2-GHz sample rate. A trigger is flagged in under 20 ns if there is a match, after which sampling is stopped, and on-chip digitization can proceed via 128 parallel 10-bit converters, or off-chip conversion can proceed via an analog readout. The chip exceeds 11 bits of dynamic range, nets over 800-MHz -3-dB bandwidth in a realistic system, and jitter in the PLL-based sampling clock has been measured to be about 1 part per million, RMS.

Night-day-night sleep-wakefulness monitoring by ambulatory integrated circuit memories.

PubMed

Yamamoto, M; Nakao, M; Katayama, N; Waku, M; Suzuki, K; Irokawa, K; Abe, M; Ueno, T

1999-04-01

A medium-sized portable digital recorder with fully integrated circuit (IC) memories for sleep monitoring has been developed. It has five amplifiers for EEG, EMG, EOG, ECG, and a signal of body acceleration or respiration sound, four event markers, an 8 ch A/D converter, a digital signal processor (DSP), 192 Mbytes IC flash memories, and batteries. The whole system weighs 1200 g including batteries and is put into a small bag worn on the subject's waist or carried in their hand. The sampling rate for each input channel is programmable through the DSP. This apparatus is valuable for continuously monitoring the states of sleep-wakefulness over 24 h, making a night-day-night recording possible in a hospital, home, or car.

Towards programmable plant genetic circuits.

PubMed

Medford, June I; Prasad, Ashok

2016-07-01

Synthetic biology enables the construction of genetic circuits with predictable gene functions in plants. Detailed quantitative descriptions of the transfer function or input-output function for genetic parts (promoters, 5' and 3' untranslated regions, etc.) are collected. These data are then used in computational simulations to determine their robustness and desired properties, thereby enabling the best components to be selected for experimental testing in plants. In addition, the process forms an iterative workflow which allows vast improvement to validated elements with sub-optimal function. These processes enable computational functions such as digital logic in living plants and follow the pathway of technological advances which took us from vacuum tubes to cell phones. © 2016 The Authors The Plant Journal © 2016 John Wiley & Sons Ltd.

Performance of an optical encoder based on a nondiffractive beam implemented with a specific photodetection integrated circuit and a diffractive optical element.

PubMed

Quintián, Fernando Perez; Calarco, Nicolás; Lutenberg, Ariel; Lipovetzky, José

2015-09-01

In this paper, we study the incremental signal produced by an optical encoder based on a nondiffractive beam (NDB). The NDB is generated by means of a diffractive optical element (DOE). The detection system is composed by an application specific integrated circuit (ASIC) sensor. The sensor consists of an array of eight concentric annular photodiodes, each one provided with a programmable gain amplifier. In this way, the system is able to synthesize a nonuniform detectivity. The contrast, amplitude, and harmonic content of the sinusoidal output signal are analyzed. The influence of the cross talk among the annular photodiodes is placed in evidence through the dependence of the signal contrast on the wavelength.

Advanced digital SAR processing study

NASA Technical Reports Server (NTRS)

Martinson, L. W.; Gaffney, B. P.; Liu, B.; Perry, R. P.; Ruvin, A.

1982-01-01

A highly programmable, land based, real time synthetic aperture radar (SAR) processor requiring a processed pixel rate of 2.75 MHz or more in a four look system was designed. Variations in range and azimuth compression, number of looks, range swath, range migration and SR mode were specified. Alternative range and azimuth processing algorithms were examined in conjunction with projected integrated circuit, digital architecture, and software technologies. The advaced digital SAR processor (ADSP) employs an FFT convolver algorithm for both range and azimuth processing in a parallel architecture configuration. Algorithm performace comparisons, design system design, implementation tradeoffs and the results of a supporting survey of integrated circuit and digital architecture technologies are reported. Cost tradeoffs and projections with alternate implementation plans are presented.

Study of feasibility of solid-state electric switch gear for aircraft and spacecraft

NASA Technical Reports Server (NTRS)

Buchanan, E.; Waddington, D.

1973-01-01

The design of a solid-state circuit breaker that can be interconnected to a second breaker to form a transfer switch is presented. The breaker operates on a nominal 270-V dc circuit and controls power to loads of up to 15 A. Automatic overload trip is provided as a function of excess energy measured through the breaker and/or excess current through the breaker. After an overload trip, up to nine preprogrammable attempts to reclose may be tried with programmable delays between each attempt. The breaker or switch is remotely controllable. Test data on performance in the laboratory over temperatures from -45 to 100 C are provided. The feasibility of solid-state switch gear has been established.

Efficient Digital Implementation of The Sigmoidal Function For Artificial Neural Network

NASA Astrophysics Data System (ADS)

Pratap, Rana; Subadra, M.

2011-10-01

An efficient piecewise linear approximation of a nonlinear function (PLAN) is proposed. This uses simulink environment design to perform a direct transformation from X to Y, where X is the input and Y is the approximated sigmoidal output. This PLAN is then used within the outputs of an artificial neural network to perform the nonlinear approximation. In This paper, is proposed a method to implement in FPGA (Field Programmable Gate Array) circuits different approximation of the sigmoid function.. The major benefit of the proposed method resides in the possibility to design neural networks by means of predefined block systems created in System Generator environment and the possibility to create a higher level design tools used to implement neural networks in logical circuits.

Synthetic biology devices and circuits for RNA-based 'smart vaccines': a propositional review.

PubMed

Andries, Oliwia; Kitada, Tasuku; Bodner, Katie; Sanders, Niek N; Weiss, Ron

2015-02-01

Nucleic acid vaccines have been gaining attention as an alternative to the standard attenuated pathogen or protein based vaccine. However, an unrealized advantage of using such DNA or RNA based vaccination modalities is the ability to program within these nucleic acids regulatory devices that would provide an immunologist with the power to control the production of antigens and adjuvants in a desirable manner by administering small molecule drugs as chemical triggers. Advances in synthetic biology have resulted in the creation of highly predictable and modular genetic parts and devices that can be composed into synthetic gene circuits with complex behaviors. With the recent advent of modified RNA gene delivery methods and developments in the RNA replicon platform, we foresee a future in which mammalian synthetic biologists will create genetic circuits encoded exclusively on RNA. Here, we review the current repertoire of devices used in RNA synthetic biology and propose how programmable 'smart vaccines' will revolutionize the field of RNA vaccination.

Software defined network architecture based research on load balancing strategy

NASA Astrophysics Data System (ADS)

You, Xiaoqian; Wu, Yang

2018-05-01

As a new type network architecture, software defined network has the key idea of separating the control place of the network from the transmission plane, to manage and control the network in a concentrated way; in addition, the network interface is opened on the control layer and the data layer, so as to achieve programmable control of the network. Considering that only the single shortest route is taken into the calculation of traditional network data flow transmission, and congestion and resource consumption caused by excessive load of link circuits are ignored, a link circuit load based flow media business QoS gurantee system is proposed in this article to divide the flow in the network into ordinary data flow and QoS flow. In this way, it supervises the link circuit load with the controller so as to calculate reasonable route rapidly and issue the flow table to the exchanger, to finish rapid data transmission. In addition, it establishes a simulation platform to acquire optimized result through simulation experiment.

The Development of a Portable Hard Disk Encryption/Decryption System with a MEMS Coded Lock.

PubMed

Zhang, Weiping; Chen, Wenyuan; Tang, Jian; Xu, Peng; Li, Yibin; Li, Shengyong

2009-01-01

In this paper, a novel portable hard-disk encryption/decryption system with a MEMS coded lock is presented, which can authenticate the user and provide the key for the AES encryption/decryption module. The portable hard-disk encryption/decryption system is composed of the authentication module, the USB portable hard-disk interface card, the ATA protocol command decoder module, the data encryption/decryption module, the cipher key management module, the MEMS coded lock controlling circuit module, the MEMS coded lock and the hard disk. The ATA protocol circuit, the MEMS control circuit and AES encryption/decryption circuit are designed and realized by FPGA(Field Programmable Gate Array). The MEMS coded lock with two couplers and two groups of counter-meshing-gears (CMGs) are fabricated by a LIGA-like process and precision engineering method. The whole prototype was fabricated and tested. The test results show that the user's password could be correctly discriminated by the MEMS coded lock, and the AES encryption module could get the key from the MEMS coded lock. Moreover, the data in the hard-disk could be encrypted or decrypted, and the read-write speed of the dataflow could reach 17 MB/s in Ultra DMA mode.

Three-Function Logic Gate Controlled by Analog Voltage

NASA Technical Reports Server (NTRS)

Zebulum, Ricardo; Stoica, Adrian

2006-01-01

The figure is a schematic diagram of a complementary metal oxide/semiconductor (CMOS) electronic circuit that performs one of three different logic functions, depending on the level of an externally applied control voltage, V(sub sel). Specifically, the circuit acts as A NAND gate at V(sub sel) = 0.0 V, A wire (the output equals one of the inputs) at V(sub sel) = 1.0 V, or An AND gate at V(sub sel) = -1.8 V. [The nominal power-supply potential (VDD) and logic "1" potential of this circuit is 1.8 V.] Like other multifunctional circuits described in several prior NASA Tech Briefs articles, this circuit was synthesized following an automated evolutionary approach that is so named because it is modeled partly after the repetitive trial-and-error process of biological evolution. An evolved circuit can be tested by computational simulation and/or tested in real hardware, and the results of the test can provide guidance for refining the design through further iteration. The evolutionary synthesis of electronic circuits can now be implemented by means of a software package Genetic Algorithms for Circuit Synthesis (GACS) that was developed specifically for this purpose. GACS was used to synthesize the present trifunctional circuit. As in the cases of other multifunctional circuits described in several prior NASA Tech Briefs articles, the multiple functionality of this circuit, the use of a single control voltage to select the function, and the automated evolutionary approach to synthesis all contribute synergistically to a combination of features that are potentially advantageous for the further development of robust, multiple-function logic circuits, including, especially, field-programmable gate arrays (FPGAs). These advantages include the following: This circuit contains only 9 transistors about half the number of transistors that would be needed to obtain equivalent NAND/wire/AND functionality by use of components from a standard digital design library. If multifunctional gates like this circuit were used in the place of the configurable logic blocks of present commercial FPGAs, it would be possible to change the functions of the resulting digital systems within shorter times. For example, by changing a single control voltage, one could change the function of thousands of FPGA cells within nanoseconds. In contrast, typically, the reconfiguration in a conventional FPGA by use of bits downloaded from look-up tables via a digital bus takes microseconds.

A low power, low noise Programmable Analog Front End (PAFE) for biopotential measurements.

PubMed

Adimulam, Mahesh Kumar; Divya, A; Tejaswi, K; Srinivas, M B

2017-07-01

A low power Programmable Analog Front End (PAFE) for biopotential measurements is presented in this paper. The PAFE circuit processes electrocardiogram (ECG), electromyography (EMG) and electroencephalogram (EEG) signals with higher accuracy. It consists mainly of improved transconductance programmable gain instrumentational amplifier (PGIA), programmable high pass filter (PHPF), and second order low pass filter (SLPF). A 15-bit programmable 5-stage successive approximation analog-to-digital converter (SAR-ADC) is implemented for improving the performance, whose power consumption is reduced due to multiple stages and by OTA/Comparator sharing technique between the stages. The power consumption is further reduced by operating the analog portion of PAFE on 0.5V supply voltage and digital portion on 0.3V supply voltage generated internally through a voltage regulator. The proposed low power PAFE has been fabricated in 180nm standard CMOS process. The performance parameters of PAFE in 15-bit mode are found to be, gain of 31-70 dB, input referred noise of 1.15 μVrms, CMRR of 110 dB, PSRR of 104 dB, and signal-to-noise distortion ratio (SNDR) of 83.5dB. The power consumption of the design is 1.1 μW @ 0.5 V supply voltage and it occupies a core silicon area of 1.2 mm 2 .

Flexible CMOS low-noise amplifiers for beyond-3G wireless hand-held devices

NASA Astrophysics Data System (ADS)

Becerra-Alvarez, Edwin C.; Sandoval-Ibarra, Federico; de la Rosa, José M.

2009-05-01

This paper explores the use of reconfigurable Low-Noise Amplifiers (LNAs) for the implementation of CMOS Radio Frequency (RF) front-ends in the next generation of multi-standard wireless transceivers. Main circuit strategies reported so far for multi-standard LNAs are reviewed and a novel flexible LNA intended for Beyond-3G RF hand-held terminals is presented. The proposed LNA circuit consists of a two-stage topology that combines inductive-source degeneration with PMOS-varactor based tuning network and a programmable load to adapt its performance to different standard specifications without penalizing the circuit noise and with a reduced number of inductors as compared to previous reported reconfigurable LNAs. The circuit has been designed in a 90-nm CMOS technology to cope with the requirements of the GSM, WCDMA, Bluetooth and WLAN (IEEE 802.11b-g) standards. Simulation results, including technology and packaging parasitics, demonstrate correct operation of the circuit for all the standards under study, featuring NF<2.8dB, S21>13.3dB and IIP3>10.9dBm, over a 1.85GHz-2.4GHz band, with an adaptive power consumption between 17mW and 22mW from a 1-V supply voltage. Preliminary experimental measurements are included, showing a correct reconfiguration operation within the operation band.

High-performance reconfigurable coincidence counting unit based on a field programmable gate array.

PubMed

Park, Byung Kwon; Kim, Yong-Su; Kwon, Osung; Han, Sang-Wook; Moon, Sung

2015-05-20

We present a high-performance reconfigurable coincidence counting unit (CCU) using a low-end field programmable gate array (FPGA) and peripheral circuits. Because of the flexibility guaranteed by the FPGA program, we can easily change system parameters, such as internal input delays, coincidence configurations, and the coincidence time window. In spite of a low-cost implementation, the proposed CCU architecture outperforms previous ones in many aspects: it has 8 logic inputs and 4 coincidence outputs that can measure up to eight-fold coincidences. The minimum coincidence time window and the maximum input frequency are 0.47 ns and 163 MHz, respectively. The CCU will be useful in various experimental research areas, including the field of quantum optics and quantum information.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Citterio, M.; Camplani, A.; Cannon, M.

SRAM based Field Programmable Gate Arrays (FPGAs) have been rarely used in High Energy Physics (HEP) due to their sensitivity to radiation. The last generation of commercial FPGAs based on 28 nm feature size and on Silicon On Insulator (SOI) technologies are more tolerant to radiation to the level that their use in front-end electronics is now feasible. FPGAs provide re-programmability, high-speed computation and fast data transmission through the embedded serial transceivers. They could replace custom application specific integrated circuits in front end electronics in locations with moderate radiation field. Finally, the use of a FPGA in HEP experiments ismore » only limited by our ability to mitigate single event effects induced by the high energy hadrons present in the radiation field.« less

Monitoring Digital Closed-Loop Feedback Systems

NASA Technical Reports Server (NTRS)

Katz, Richard; Kleyner, Igor

2011-01-01

A technique of monitoring digital closed-loop feedback systems has been conceived. The basic idea is to obtain information on the performances of closed-loop feedback circuits in such systems to aid in the determination of the functionality and integrity of the circuits and of performance margins. The need for this technique arises as follows: Some modern digital systems include feedback circuits that enable other circuits to perform with precision and are tolerant of changes in environment and the device s parameters. For example, in a precision timing circuit, it is desirable to make the circuit insensitive to variability as a result of the manufacture of circuit components and to the effects of temperature, voltage, radiation, and aging. However, such a design can also result in masking the indications of damaged and/or deteriorating components. The present technique incorporates test circuitry and associated engineering-telemetry circuitry into an embedded system to monitor the closed-loop feedback circuits, using spare gates that are often available in field programmable gate arrays (FPGAs). This technique enables a test engineer to determine the amount of performance margin in the system, detect out of family circuit performance, and determine one or more trend(s) in the performance of the system. In one system to which the technique has been applied, an ultra-stable oscillator is used as a reference for internal adjustment of 12 time-to-digital converters (TDCs). The feedback circuit produces a pulse-width-modulated signal that is fed as a control input into an amplifier, which controls the circuit s operating voltage. If the circuit s gates are determined to be operating too slowly or rapidly when their timing is compared with that of the reference signal, then the pulse width increases or decreases, respectively, thereby commanding the amplifier to increase or reduce, respectively, its output level, and "adjust" the speed of the circuits. The nominal frequency of the TDC s pulse width modulated outputs is approximately 40 kHz. In this system, the technique is implemented by means of a monitoring circuit that includes a 20-MHz sampling circuit and a 24-bit accumulator with a gate time of 10 ms. The monitoring circuit measures the duty cycle of each of the 12 TDCs at a repetition rate of 28 Hz. The accumulator content is reset to all zeroes at the beginning of each measurement period and is then incremented or decremented based of the value of the state of the pulse width modulated signal. Positive or negative values in the accumulator correspond to duty cycles greater or less, respectively, than 50 percent.

Evolvable Hardware for Space Applications

NASA Technical Reports Server (NTRS)

Lohn, Jason; Globus, Al; Hornby, Gregory; Larchev, Gregory; Kraus, William

2004-01-01

This article surveys the research of the Evolvable Systems Group at NASA Ames Research Center. Over the past few years, our group has developed the ability to use evolutionary algorithms in a variety of NASA applications ranging from spacecraft antenna design, fault tolerance for programmable logic chips, atomic force field parameter fitting, analog circuit design, and earth observing satellite scheduling. In some of these applications, evolutionary algorithms match or improve on human performance.

Pneumatically Modulated Liquid Delivery System for Nebulizers

DTIC Science & Technology

2011-12-02

VII. Acknowledgements 18 APPENDIX A: Complete Parts List 19 APPENDIX B: Source code for the Arduino Uno microcontroller (CD) 23 1 I...implemented. The Arduino Uno is a well-established hobbyist microcontroller, focused on ease-of-use and teaching non-computer programmers about embedded...circuits. The Arduino Uno uses an Atmega328 microcontroller with thirteen digital TTL control lines, six 10-bit resolution 0-5 V analog inputs, TTL

Hardware Evolution of Analog Speed Controllers for a DC Motor

NASA Technical Reports Server (NTRS)

Gwaltney, David A.; Ferguson, Michael I.

2003-01-01

Evolvable hardware provides the capability to evolve analog circuits to produce amplifier and filter functions. Conventional analog controller designs employ these same functions. Analog controllers for the control of the shaft speed of a DC motor are evolved on an evolvable hardware platform utilizing a Field Programmable Transistor Array (FPTA). The performance of these evolved controllers is compared to that of a conventional proportional-integral (PI) controller.

Configurable hardware integrate and fire neurons for sparse approximation.

PubMed

Shapero, Samuel; Rozell, Christopher; Hasler, Paul

2013-09-01

Sparse approximation is an important optimization problem in signal and image processing applications. A Hopfield-Network-like system of integrate and fire (IF) neurons is proposed as a solution, using the Locally Competitive Algorithm (LCA) to solve an overcomplete L1 sparse approximation problem. A scalable system architecture is described, including IF neurons with a nonlinear firing function, and current-based synapses to provide linear computation. A network of 18 neurons with 12 inputs is implemented on the RASP 2.9v chip, a Field Programmable Analog Array (FPAA) with directly programmable floating gate elements. Said system uses over 1400 floating gates, the largest system programmed on a FPAA to date. The circuit successfully reproduced the outputs of a digital optimization program, converging to within 4.8% RMS, and an objective cost only 1.7% higher on average. The active circuit consumed 559 μA of current at 2.4 V and converges on solutions in 25 μs, with measurement of the converged spike rate taking an additional 1 ms. Extrapolating the scaling trends to a N=1000 node system, the spiking LCA compares favorably with state-of-the-art digital solutions, and analog solutions using a non-spiking approach. Copyright © 2013 Elsevier Ltd. All rights reserved.

Albion: the UK 3rd generation high-performance thermal imaging programme

NASA Astrophysics Data System (ADS)

McEwen, R. K.; Lupton, M.; Lawrence, M.; Knowles, P.; Wilson, M.; Dennis, P. N. J.; Gordon, N. T.; Lees, D. J.; Parsons, J. F.

2007-04-01

The first generation of high performance thermal imaging sensors in the UK was based on two axis opto-mechanical scanning systems and small (4-16 element) arrays of the SPRITE detector, developed during the 1970s. Almost two decades later, a 2nd Generation system, STAIRS C was introduced, based on single axis scanning and a long linear array of approximately 3000 elements. The UK has now begun the industrialisation of 3 rd Generation High Performance Thermal Imaging under a programme known as "Albion". Three new high performance cadmium mercury telluride arrays are being manufactured. The CMT material is grown by MOVPE on low cost substrates and bump bonded to the silicon read out circuit (ROIC). To maintain low production costs, all three detectors are designed to fit with existing standard Integrated Detector Cooling Assemblies (IDCAs). The two largest focal planes are conventional devices operating in the MWIR and LWIR spectral bands. A smaller format LWIR device is also described which has a smart ROIC, enabling much longer stare times than are feasible with conventional pixel circuits, thus achieving very high sensitivity. A new reference surface technology for thermal imaging sensors is described, based on Negative Luminescence (NL), which offers several advantages over conventional peltier references, improving the quality of the Non-Uniformity Correction (NUC) algorithms.

Digital-Analog Hybrid Scheme and Its Application to Chaotic Random Number Generators

NASA Astrophysics Data System (ADS)

Yuan, Zeshi; Li, Hongtao; Miao, Yunchi; Hu, Wen; Zhu, Xiaohua

2017-12-01

Practical random number generation (RNG) circuits are typically achieved with analog devices or digital approaches. Digital-based techniques, which use field programmable gate array (FPGA) and graphics processing units (GPU) etc. usually have better performances than analog methods as they are programmable, efficient and robust. However, digital realizations suffer from the effect of finite precision. Accordingly, the generated random numbers (RNs) are actually periodic instead of being real random. To tackle this limitation, in this paper we propose a novel digital-analog hybrid scheme that employs the digital unit as the main body, and minimum analog devices to generate physical RNs. Moreover, the possibility of realizing the proposed scheme with only one memory element is discussed. Without loss of generality, we use the capacitor and the memristor along with FPGA to construct the proposed hybrid system, and a chaotic true random number generator (TRNG) circuit is realized, producing physical RNs at a throughput of Gbit/s scale. These RNs successfully pass all the tests in the NIST SP800-22 package, confirming the significance of the scheme in practical applications. In addition, the use of this new scheme is not restricted to RNGs, and it also provides a strategy to solve the effect of finite precision in other digital systems.

A Spaceborne Synthetic Aperture Radar Partial Fixed-Point Imaging System Using a Field- Programmable Gate Array—Application-Specific Integrated Circuit Hybrid Heterogeneous Parallel Acceleration Technique

PubMed Central

Li, Bingyi; Chen, Liang; Wei, Chunpeng; Xie, Yizhuang; Chen, He; Yu, Wenyue

2017-01-01

With the development of satellite load technology and very large scale integrated (VLSI) circuit technology, onboard real-time synthetic aperture radar (SAR) imaging systems have become a solution for allowing rapid response to disasters. A key goal of the onboard SAR imaging system design is to achieve high real-time processing performance with severe size, weight, and power consumption constraints. In this paper, we analyse the computational burden of the commonly used chirp scaling (CS) SAR imaging algorithm. To reduce the system hardware cost, we propose a partial fixed-point processing scheme. The fast Fourier transform (FFT), which is the most computation-sensitive operation in the CS algorithm, is processed with fixed-point, while other operations are processed with single precision floating-point. With the proposed fixed-point processing error propagation model, the fixed-point processing word length is determined. The fidelity and accuracy relative to conventional ground-based software processors is verified by evaluating both the point target imaging quality and the actual scene imaging quality. As a proof of concept, a field- programmable gate array—application-specific integrated circuit (FPGA-ASIC) hybrid heterogeneous parallel accelerating architecture is designed and realized. The customized fixed-point FFT is implemented using the 130 nm complementary metal oxide semiconductor (CMOS) technology as a co-processor of the Xilinx xc6vlx760t FPGA. A single processing board requires 12 s and consumes 21 W to focus a 50-km swath width, 5-m resolution stripmap SAR raw data with a granularity of 16,384 × 16,384. PMID:28672813

A SHORT-TERM CIRCUIT RESISTANCE PROGRAMME REDUCED EPICARDIAL FAT IN OBESE AGED WOMEN.

PubMed

Rosety, Miguel Angel; Pery, Maria Teresa; Rodriguez-Pareja, Maria Antonia; Diaz, Antonio; Rosety, Jesus; Garcia, Natalia; Brenes-Martin, Francisco; Rosety-Rodríguez, Manuel; Toro, Rocío; Ordoñez, Francisco Javier; Rosety, Ignacio

2015-11-01

this study was conducted to ascertain the effects of resistance circuit training on epicardial adipose tissue (EAT) in obese aged women. A secondary objective was to assess muscle damage induced by supervised resistance training to confirm the intervention program was effective and safe. in the present interventional study, a total of 48 obese aged women were recruited from the community. Twenty-four of them were randomly assigned to perform a 12-week resistance circuit training programme, 3-days per week. This training was circularly performed in 6 stations: arm curl, leg extension, seated row, leg curl, triceps extension and leg press. The Jamar handgrip electronic dynamometer was used to assess maximal handgrip strength of the dominant hand. Two experienced observers assessed EAT by transthoracic two-dimensional echocardiography. Lastly, serum samples were analysed using one-step sandwich assays for creatine kinase activity (CK) and myoglobin (MB) concentration. as was hypothesized, resistance training significantly reduced EAT thickness (8.4 ± 1.0 vs. 7.3 ± 1.3 mm; p = 0.014; d = 0.76) in the experimental group. Resistance training induced no significant changes in markers of muscle damage such as CK (181.6 ± 36.9 vs. 194.2 ± 37.8 U/l; p = 0.31) and MB (62.4 ± 7.1 vs. 67.3 ± 7.7 ng/ml; p = 0.26). No significant changes in any of the tested outcomes were found in the control group. resistance training reduced EAT in aged obese women. A secondary finding was that the training program was effective and safe. While current results are promising, future studies are still required to consolidate this approach in clinical application. Copyright AULA MEDICA EDICIONES 2014. Published by AULA MEDICA. All rights reserved.

A Spaceborne Synthetic Aperture Radar Partial Fixed-Point Imaging System Using a Field- Programmable Gate Array-Application-Specific Integrated Circuit Hybrid Heterogeneous Parallel Acceleration Technique.

PubMed

Yang, Chen; Li, Bingyi; Chen, Liang; Wei, Chunpeng; Xie, Yizhuang; Chen, He; Yu, Wenyue

2017-06-24

With the development of satellite load technology and very large scale integrated (VLSI) circuit technology, onboard real-time synthetic aperture radar (SAR) imaging systems have become a solution for allowing rapid response to disasters. A key goal of the onboard SAR imaging system design is to achieve high real-time processing performance with severe size, weight, and power consumption constraints. In this paper, we analyse the computational burden of the commonly used chirp scaling (CS) SAR imaging algorithm. To reduce the system hardware cost, we propose a partial fixed-point processing scheme. The fast Fourier transform (FFT), which is the most computation-sensitive operation in the CS algorithm, is processed with fixed-point, while other operations are processed with single precision floating-point. With the proposed fixed-point processing error propagation model, the fixed-point processing word length is determined. The fidelity and accuracy relative to conventional ground-based software processors is verified by evaluating both the point target imaging quality and the actual scene imaging quality. As a proof of concept, a field- programmable gate array-application-specific integrated circuit (FPGA-ASIC) hybrid heterogeneous parallel accelerating architecture is designed and realized. The customized fixed-point FFT is implemented using the 130 nm complementary metal oxide semiconductor (CMOS) technology as a co-processor of the Xilinx xc6vlx760t FPGA. A single processing board requires 12 s and consumes 21 W to focus a 50-km swath width, 5-m resolution stripmap SAR raw data with a granularity of 16,384 × 16,384.

Two-dimensional non-volatile programmable p-n junctions

NASA Astrophysics Data System (ADS)

Li, Dong; Chen, Mingyuan; Sun, Zhengzong; Yu, Peng; Liu, Zheng; Ajayan, Pulickel M.; Zhang, Zengxing

2017-09-01

Semiconductor p-n junctions are the elementary building blocks of most electronic and optoelectronic devices. The need for their miniaturization has fuelled the rapid growth of interest in two-dimensional (2D) materials. However, the performance of a p-n junction considerably degrades as its thickness approaches a few nanometres and traditional technologies, such as doping and implantation, become invalid at the nanoscale. Here we report stable non-volatile programmable p-n junctions fabricated from the vertically stacked all-2D semiconductor/insulator/metal layers (WSe2/hexagonal boron nitride/graphene) in a semifloating gate field-effect transistor configuration. The junction exhibits a good rectifying behaviour with a rectification ratio of 104 and photovoltaic properties with a power conversion efficiency up to 4.1% under a 6.8 nW light. Based on the non-volatile programmable properties controlled by gate voltages, the 2D p-n junctions have been exploited for various electronic and optoelectronic applications, such as memories, photovoltaics, logic rectifiers and logic optoelectronic circuits.

Two-dimensional non-volatile programmable p-n junctions.

PubMed

Li, Dong; Chen, Mingyuan; Sun, Zhengzong; Yu, Peng; Liu, Zheng; Ajayan, Pulickel M; Zhang, Zengxing

2017-09-01

Semiconductor p-n junctions are the elementary building blocks of most electronic and optoelectronic devices. The need for their miniaturization has fuelled the rapid growth of interest in two-dimensional (2D) materials. However, the performance of a p-n junction considerably degrades as its thickness approaches a few nanometres and traditional technologies, such as doping and implantation, become invalid at the nanoscale. Here we report stable non-volatile programmable p-n junctions fabricated from the vertically stacked all-2D semiconductor/insulator/metal layers (WSe 2 /hexagonal boron nitride/graphene) in a semifloating gate field-effect transistor configuration. The junction exhibits a good rectifying behaviour with a rectification ratio of 10 4 and photovoltaic properties with a power conversion efficiency up to 4.1% under a 6.8 nW light. Based on the non-volatile programmable properties controlled by gate voltages, the 2D p-n junctions have been exploited for various electronic and optoelectronic applications, such as memories, photovoltaics, logic rectifiers and logic optoelectronic circuits.

A programmable positioning stepper-motor controller with a multibus/IEEE 796 compatible interface.

PubMed

Papoff, P; Ricci, D

1984-02-01

A programmable positioning stepper-motor controller, based on the Multibus/IEEE 796 standard interface, has been assembled by use of some intelligent and programmable integrated circuits. This controller, organized as a bus-slave unit, has been planned for local management of up to four stepper motors working simultaneously. The number of steps, the direction of rotation and the step-rate for the positioning of each motor are issued by the bus master microcomputer to the controller which handles all the required operations. Once each positioning has been performed, the controller informs the master by generating a proper bus-vectored interrupt. Displacements in up to 64,000 steps may be programmed with step-rates ranging from 0.1 to 6550 steps/sec. This device, for which only low-cost, high-performance components are required, can be successfully used in a wide range of applications and can be easily extended to control more than four stepper motors.

Digital-only PLL with adaptive search step

NASA Astrophysics Data System (ADS)

Lin, Ming-Lang; Huang, Shu-Chuan; Liu, Jie-Cherng

2014-06-01

In this paper, an all-digital phase-locked loop (PLL) with adaptively controlled up/down counter serves as the loop filter is presented, and it is implemented on a field-programmable gate array. The detailed circuit of the adaptive up/down counter implementing the adaptive search algorithm is also given, in which the search step for frequency acquisition is adaptively scaled down in half until it is reduced to zero. The phase jitter of the proposed PLL can be lowered, yet keeping with fast lock-in time. Thus, the dilemma between the low phase jitter and fast lock-in time of the traditional PLL can be resolved. Simulation results and circuit implementation show that the locked count, phase jitter and lock-in time of the proposed PLL are consistent with the theoretical predictions.

Sequential power-up circuit

DOEpatents

Kronberg, James W.

1992-01-01

A sequential power-up circuit for starting several electrical load elements in series to avoid excessive current surge, comprising a voltage ramp generator and a set of voltage comparators, each comparator having a different reference voltage and interfacing with a switch that is capable of turning on one of the load elements. As the voltage rises, it passes the reference voltages one at a time and causes the switch corresponding to that voltage to turn on its load element. The ramp is turned on and off by a single switch or by a logic-level electrical signal. The ramp rate for turning on the load element is relatively slow and the rate for turning the elements off is relatively fast. Optionally, the duration of each interval of time between the turning on of the load elements is programmable.

Design of a Closed-Loop, Bidirectional Brain Machine Interface System With Energy Efficient Neural Feature Extraction and PID Control.

PubMed

Liu, Xilin; Zhang, Milin; Richardson, Andrew G; Lucas, Timothy H; Van der Spiegel, Jan

2017-08-01

This paper presents a bidirectional brain machine interface (BMI) microsystem designed for closed-loop neuroscience research, especially experiments in freely behaving animals. The system-on-chip (SoC) consists of 16-channel neural recording front-ends, neural feature extraction units, 16-channel programmable neural stimulator back-ends, in-channel programmable closed-loop controllers, global analog-digital converters (ADC), and peripheral circuits. The proposed neural feature extraction units includes 1) an ultra low-power neural energy extraction unit enabling a 64-step natural logarithmic domain frequency tuning, and 2) a current-mode action potential (AP) detection unit with time-amplitude window discriminator. A programmable proportional-integral-derivative (PID) controller has been integrated in each channel enabling a various of closed-loop operations. The implemented ADCs include a 10-bit voltage-mode successive approximation register (SAR) ADC for the digitization of the neural feature outputs and/or local field potential (LFP) outputs, and an 8-bit current-mode SAR ADC for the digitization of the action potential outputs. The multi-mode stimulator can be programmed to perform monopolar or bipolar, symmetrical or asymmetrical charge balanced stimulation with a maximum current of 4 mA in an arbitrary channel configuration. The chip has been fabricated in 0.18 μ m CMOS technology, occupying a silicon area of 3.7 mm 2 . The chip dissipates 56 μW/ch on average. General purpose low-power microcontroller with Bluetooth module are integrated in the system to provide wireless link and SoC configuration. Methods, circuit techniques and system topology proposed in this work can be used in a wide range of relevant neurophysiology research, especially closed-loop BMI experiments.

G4-FETs as Universal and Programmable Logic Gates

NASA Technical Reports Server (NTRS)

Johnson, Travis; Fijany, Amir; Mojarradi, Mohammad; Vatan, Farrokh; Toomarian, Nikzad; Kolawa, Elizabeth; Cristoloveanu, Sorin; Blalock, Benjamin

2007-01-01

An analysis of a patented generic silicon- on-insulator (SOI) electronic device called a G4-FET has revealed that the device could be designed to function as a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer discrete components than are required for conventional transistor-based circuits performing the same logic functions. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G4-FET can also be regarded as a single transistor having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of the SOI substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. With proper choice of the specific dimensions for the gates, channels, and ancillary features of the generic G4-FET, the device could be made to function as a three-input, one-output logic gate. As illustrated by the truth table in the top part of the figure, the behavior of this logic gate would be the inverse (the NOT) of that of a majority gate. In other words, the device would function as a NOT-majority gate. By simply adding an inverter, one could obtain a majority gate. In contrast, to construct a majority gate in conventional complementary metal oxide/semiconductor (CMOS) circuitry, one would need four three-input AND gates and a four-input OR gate, altogether containing 32 transistors.

Advanced Data Acquisition Systems

NASA Technical Reports Server (NTRS)

Perotti, J.

2003-01-01

Current and future requirements of the aerospace sensors and transducers field make it necessary for the design and development of new data acquisition devices and instrumentation systems. New designs are sought to incorporate self-health, self-calibrating, self-repair capabilities, allowing greater measurement reliability and extended calibration cycles. With the addition of power management schemes, state-of-the-art data acquisition systems allow data to be processed and presented to the users with increased efficiency and accuracy. The design architecture presented in this paper displays an innovative approach to data acquisition systems. The design incorporates: electronic health self-check, device/system self-calibration, electronics and function self-repair, failure detection and prediction, and power management (reduced power consumption). These requirements are driven by the aerospace industry need to reduce operations and maintenance costs, to accelerate processing time and to provide reliable hardware with minimum costs. The project's design architecture incorporates some commercially available components identified during the market research investigation like: Field Programmable Gate Arrays (FPGA) Programmable Analog Integrated Circuits (PAC IC) and Field Programmable Analog Arrays (FPAA); Digital Signal Processing (DSP) electronic/system control and investigation of specific characteristics found in technologies like: Electronic Component Mean Time Between Failure (MTBF); and Radiation Hardened Component Availability. There are three main sections discussed in the design architecture presented in this document. They are the following: (a) Analog Signal Module Section, (b) Digital Signal/Control Module Section and (c) Power Management Module Section. These sections are discussed in detail in the following pages. This approach to data acquisition systems has resulted in the assignment of patent rights to Kennedy Space Center under U.S. patent # 6,462,684. Furthermore, NASA KSC commercialization office has issued licensing rights to Circuit Avenue Netrepreneurs, LLC , a minority-owned business founded in 1999 located in Camden, NJ.

Implementing a Cancer Fast-track Programme between primary and specialised care in Catalonia (Spain): a mixed methods study

PubMed Central

Prades, J; Espinàs, J A; Font, R; Argimon, J M; Borràs, J M

2011-01-01

Background: The Cancer Fast-track Programme's aim was to reduce the time that elapsed between well-founded suspicion of breast, colorectal and lung cancer and the start of initial treatment in Catalonia (Spain). We sought to analyse its implementation and overall effectiveness. Methods: A quantitative analysis of the programme was performed using data generated by the hospitals on the basis of seven fast-track monitoring indicators for the period 2006–2009. In addition, we conducted a qualitative study, based on 83 semistructured interviews with primary and specialised health professionals and health administrators, to obtain their perception of the programme's implementation. Results: About half of all new patients with breast, lung or colorectal cancer were diagnosed via the fast track, though the cancer detection rate declined across the period. Mean time from detection of suspected cancer in primary care to start of initial treatment was 32 days for breast, 30 for colorectal and 37 for lung cancer (2009). Professionals associated with the implementation of the programme showed that general practitioners faced with suspicion of cancer had changed their conduct with the aim of preventing lags. Furthermore, hospitals were found to have pursued three specific implementation strategies (top-down, consensus-based and participatory), which made for the cohesion and sustainability of the circuits. Conclusion: The programme has contributed to speeding up diagnostic assessment and treatment of patients with suspicion of cancer, and to clarifying the patient pathway between primary and specialised care. PMID:21829194

Physical employment standard for Canadian wildland firefighters: examining test-retest reliability and the impact of familiarisation and physical fitness training.

PubMed

Gumieniak, Robert J; Gledhill, Norman; Jamnik, Veronica K

2018-05-04

To assess the impact of repeat performances (familiarisation) plus exercise training on completion time for the Ontario Wildland Firefighter (WFF) Fitness Test circuit (WFX-FIT), normally active general population participants (n = 145) were familiarised to the protocol then randomised into (i) exercise training, (ii) circuit only weekly performances or (iii) controls. At Baseline, the WFX-FIT pass rate for all groups combined was 11% for females and 73% for males, indicating that the Ontario WFX-FIT standard had a possible adverse impact on females. Following test familiarisation, mean circuit completion times improved by 11.9% and 10.2% for females and males, respectively. There were significant improvements in completion time for females (19.8%) and males (16.9%) who trained, plus females (12.2%) and males (9.8%) who performed the circuit only, while control participants were unchanged. Post training, the pass rate of the training group was 80% for females and 100% for males. Practitioner Summary: This paper details the impact of familiarisation plus exercise training as accommodation to mitigate potential adverse impact on initial attack wildland firefighter test performance. The results underscore the importance of test familiarisation opportunities and physical fitness training programmes that are specific to the demands of the job.

Integrated biocircuits: engineering functional multicellular circuits and devices.

PubMed

Prox, Jordan; Smith, Tory; Holl, Chad; Chehade, Nick; Guo, Liang

2018-04-01

Implantable neurotechnologies have revolutionized neuromodulatory medicine for treating the dysfunction of diseased neural circuitry. However, challenges with biocompatibility and lack of full control over neural network communication and function limits the potential to create more stable and robust neuromodulation devices. Thus, we propose a platform technology of implantable and programmable cellular systems, namely Integrated Biocircuits, which use only cells as the functional components of the device. We envision the foundational principles for this concept begins with novel in vitro platforms used for the study and reconstruction of cellular circuitry. Additionally, recent advancements in organoid and 3D culture systems account for microenvironment factors of cytoarchitecture to construct multicellular circuits as they are normally formed in the brain. We explore the current state of the art of these platforms to provide knowledge of their advancements in circuit fabrication and identify the current biological principles that could be applied in designing integrated biocircuit devices. We have highlighted the exemplary methodologies and techniques of in vitro circuit fabrication and propose the integration of selected controllable parameters, which would be required in creating suitable biodevices. We provide our perspective and propose new insights into the future of neuromodulaion devices within the scope of living cellular systems that can be applied in designing more reliable and biocompatible stimulation-based neuroprosthetics.

Integrated biocircuits: engineering functional multicellular circuits and devices

NASA Astrophysics Data System (ADS)

Prox, Jordan; Smith, Tory; Holl, Chad; Chehade, Nick; Guo, Liang

2018-04-01

Objective. Implantable neurotechnologies have revolutionized neuromodulatory medicine for treating the dysfunction of diseased neural circuitry. However, challenges with biocompatibility and lack of full control over neural network communication and function limits the potential to create more stable and robust neuromodulation devices. Thus, we propose a platform technology of implantable and programmable cellular systems, namely Integrated Biocircuits, which use only cells as the functional components of the device. Approach. We envision the foundational principles for this concept begins with novel in vitro platforms used for the study and reconstruction of cellular circuitry. Additionally, recent advancements in organoid and 3D culture systems account for microenvironment factors of cytoarchitecture to construct multicellular circuits as they are normally formed in the brain. We explore the current state of the art of these platforms to provide knowledge of their advancements in circuit fabrication and identify the current biological principles that could be applied in designing integrated biocircuit devices. Main results. We have highlighted the exemplary methodologies and techniques of in vitro circuit fabrication and propose the integration of selected controllable parameters, which would be required in creating suitable biodevices. Significance. We provide our perspective and propose new insights into the future of neuromodulaion devices within the scope of living cellular systems that can be applied in designing more reliable and biocompatible stimulation-based neuroprosthetics.

The Development of a Portable Hard Disk Encryption/Decryption System with a MEMS Coded Lock

PubMed Central

Zhang, Weiping; Chen, Wenyuan; Tang, Jian; Xu, Peng; Li, Yibin; Li, Shengyong

2009-01-01

In this paper, a novel portable hard-disk encryption/decryption system with a MEMS coded lock is presented, which can authenticate the user and provide the key for the AES encryption/decryption module. The portable hard-disk encryption/decryption system is composed of the authentication module, the USB portable hard-disk interface card, the ATA protocol command decoder module, the data encryption/decryption module, the cipher key management module, the MEMS coded lock controlling circuit module, the MEMS coded lock and the hard disk. The ATA protocol circuit, the MEMS control circuit and AES encryption/decryption circuit are designed and realized by FPGA(Field Programmable Gate Array). The MEMS coded lock with two couplers and two groups of counter-meshing-gears (CMGs) are fabricated by a LIGA-like process and precision engineering method. The whole prototype was fabricated and tested. The test results show that the user's password could be correctly discriminated by the MEMS coded lock, and the AES encryption module could get the key from the MEMS coded lock. Moreover, the data in the hard-disk could be encrypted or decrypted, and the read-write speed of the dataflow could reach 17 MB/s in Ultra DMA mode. PMID:22291566

Synthetic dual-input mammalian genetic circuits enable tunable and stringent transcription control by chemical and light.

PubMed

Chen, Xianjun; Li, Ting; Wang, Xue; Du, Zengmin; Liu, Renmei; Yang, Yi

2016-04-07

Programmable transcription factors can enable precise control of gene expression triggered by a chemical inducer or light. To obtain versatile transgene system with combined benefits of a chemical inducer and light inducer, we created various chimeric promoters through the assembly of different copies of the tet operator and Gal4 operator module, which simultaneously responded to a tetracycline-responsive transcription factor and a light-switchable transactivator. The activities of these chimeric promoters can be regulated by tetracycline and blue light synergistically or antagonistically. Further studies of the antagonistic genetic circuit exhibited high spatiotemporal resolution and extremely low leaky expression, which therefore could be used to spatially and stringently control the expression of highly toxic protein Diphtheria toxin A for light regulated gene therapy. When transferring plasmids engineered for the gene switch-driven expression of a firefly luciferase (Fluc) into mice, the Fluc expression levels of the treated animals directly correlated with the tetracycline and light input program. We suggest that dual-input genetic circuits using TET and light that serve as triggers to achieve expression profiles may enable the design of robust therapeutic gene circuits for gene- and cell-based therapies. © The Author(s) 2015. Published by Oxford University Press on behalf of Nucleic Acids Research.

Generalized reconfigurable memristive dynamical system (MDS) for neuromorphic applications

PubMed Central

Bavandpour, Mohammad; Soleimani, Hamid; Linares-Barranco, Bernabé; Abbott, Derek; Chua, Leon O.

2015-01-01

This study firstly presents (i) a novel general cellular mapping scheme for two dimensional neuromorphic dynamical systems such as bio-inspired neuron models, and (ii) an efficient mixed analog-digital circuit, which can be conveniently implemented on a hybrid memristor-crossbar/CMOS platform, for hardware implementation of the scheme. This approach employs 4n memristors and no switch for implementing an n-cell system in comparison with 2n2 memristors and 2n switches of a Cellular Memristive Dynamical System (CMDS). Moreover, this approach allows for dynamical variables with both analog and one-hot digital values opening a wide range of choices for interconnections and networking schemes. Dynamical response analyses show that this circuit exhibits various responses based on the underlying bifurcation scenarios which determine the main characteristics of the neuromorphic dynamical systems. Due to high programmability of the circuit, it can be applied to a variety of learning systems, real-time applications, and analytically indescribable dynamical systems. We simulate the FitzHugh-Nagumo (FHN), Adaptive Exponential (AdEx) integrate and fire, and Izhikevich neuron models on our platform, and investigate the dynamical behaviors of these circuits as case studies. Moreover, error analysis shows that our approach is suitably accurate. We also develop a simple hardware prototype for experimental demonstration of our approach. PMID:26578867

Laser patterning of highly conductive flexible circuits

NASA Astrophysics Data System (ADS)

Ji, Seok Young; Muhammed Ajmal, C.; Kim, Taehun; Chang, Won Seok; Baik, Seunghyun

2017-04-01

There has been considerable attention paid to highly conductive flexible adhesive (CFA) materials as electrodes and interconnectors for future flexible electronic devices. However, the patterning technology still needs to be developed to construct micro-scale electrodes and circuits. Here we developed the selective laser sintering technology where the pattering and curing were accomplished simultaneously without making additional masks. The CFA was composed of micro-scale Ag flakes, multiwalled carbon nanotubes decorated with Ag nanoparticles, and a nitrile-butadiene-rubber matrix. The Teflon-coated polyethylene terephthalate film was used as a flexible substrate. The width of lines (50-500 μm) and circuit patterns were controlled by the programmable scanning of a focused laser beam (power = 50 mW, scanning speed = 1 mm s-1). The laser irradiation removed solvent and induced effective coalescence among fillers providing a conductivity as high as 25 012 S cm-1. The conductivity stability was excellent under the ambient air and humid environments. The normalized resistance change of the pattern was smaller than 1.2 at the bending radius of 5 mm. The cyclability and adhesion of the laser-sintered line pattern on the substrate was excellent. A flexible circuit was fabricated sequentially for operating light emitting diodes during the bending motion, demonstrating excellent feasibility for practical applications in flexible electronics.

Generalized reconfigurable memristive dynamical system (MDS) for neuromorphic applications.

PubMed

Bavandpour, Mohammad; Soleimani, Hamid; Linares-Barranco, Bernabé; Abbott, Derek; Chua, Leon O

2015-01-01

This study firstly presents (i) a novel general cellular mapping scheme for two dimensional neuromorphic dynamical systems such as bio-inspired neuron models, and (ii) an efficient mixed analog-digital circuit, which can be conveniently implemented on a hybrid memristor-crossbar/CMOS platform, for hardware implementation of the scheme. This approach employs 4n memristors and no switch for implementing an n-cell system in comparison with 2n (2) memristors and 2n switches of a Cellular Memristive Dynamical System (CMDS). Moreover, this approach allows for dynamical variables with both analog and one-hot digital values opening a wide range of choices for interconnections and networking schemes. Dynamical response analyses show that this circuit exhibits various responses based on the underlying bifurcation scenarios which determine the main characteristics of the neuromorphic dynamical systems. Due to high programmability of the circuit, it can be applied to a variety of learning systems, real-time applications, and analytically indescribable dynamical systems. We simulate the FitzHugh-Nagumo (FHN), Adaptive Exponential (AdEx) integrate and fire, and Izhikevich neuron models on our platform, and investigate the dynamical behaviors of these circuits as case studies. Moreover, error analysis shows that our approach is suitably accurate. We also develop a simple hardware prototype for experimental demonstration of our approach.

Laser patterning of highly conductive flexible circuits.

PubMed

Ji, Seok Young; Ajmal, C Muhammed; Kim, Taehun; Chang, Won Seok; Baik, Seunghyun

2017-04-21

There has been considerable attention paid to highly conductive flexible adhesive (CFA) materials as electrodes and interconnectors for future flexible electronic devices. However, the patterning technology still needs to be developed to construct micro-scale electrodes and circuits. Here we developed the selective laser sintering technology where the pattering and curing were accomplished simultaneously without making additional masks. The CFA was composed of micro-scale Ag flakes, multiwalled carbon nanotubes decorated with Ag nanoparticles, and a nitrile-butadiene-rubber matrix. The Teflon-coated polyethylene terephthalate film was used as a flexible substrate. The width of lines (50-500 μm) and circuit patterns were controlled by the programmable scanning of a focused laser beam (power = 50 mW, scanning speed = 1 mm s -1 ). The laser irradiation removed solvent and induced effective coalescence among fillers providing a conductivity as high as 25 012 S cm -1 . The conductivity stability was excellent under the ambient air and humid environments. The normalized resistance change of the pattern was smaller than 1.2 at the bending radius of 5 mm. The cyclability and adhesion of the laser-sintered line pattern on the substrate was excellent. A flexible circuit was fabricated sequentially for operating light emitting diodes during the bending motion, demonstrating excellent feasibility for practical applications in flexible electronics.

Non-destructive evaluation of composite materials using ultrasound

NASA Technical Reports Server (NTRS)

Miller, J. G.

1984-01-01

Investigation of the nondestructive evaluation of advanced composite-laminates is summarized. Indices derived from the measurement of fundamental acoustic parameters are used in order to quantitatively estimate the local material properties of the laminate. The following sections describe ongoing studies of phase insensitive attenuation measurements, and discuss several phenomena which influences the previously reported technique of polar backscatter. A simple and effective programmable gate circuit designed for use in estimating attenuation from backscatter is described.

European Conference on Advanced Materials and Processes Held in Aachen, Federal Republic of Germany on November 22-24 1989. Abstracts

DTIC Science & Technology

1989-11-24

However, the combination of increasing circuit complexity, customization, size, speed and heat flux is leading to a crisis in packaging technology(1...material properties and tooling restrictions, * production by an economic single-step sintering technique with subsequent heat treatment, * achievement of...programme, page 16. Numerical Mlodelling of Heat Transfer at Interfaces: Finite Element Approaches, Testing and Examples I W. Schafer, MAGM

Spacecube V2.0 Micro Single Board Computer

NASA Technical Reports Server (NTRS)

Petrick, David J. (Inventor); Geist, Alessandro (Inventor); Lin, Michael R. (Inventor); Crum, Gary R. (Inventor)

2017-01-01

A single board computer system radiation hardened for space flight includes a printed circuit board having a top side and bottom side; a reconfigurable field programmable gate array (FPGA) processor device disposed on the top side; a connector disposed on the top side; a plurality of peripheral components mounted on the bottom side; and wherein a size of the single board computer system is not greater than approximately 7 cm.times.7 cm.

Programmable logic controller performance enhancement by field programmable gate array based design.

PubMed

Patel, Dhruv; Bhatt, Jignesh; Trivedi, Sanjay

2015-01-01

PLC, the core element of modern automation systems, due to serial execution, exhibits limitations like slow speed and poor scan time. Improved PLC design using FPGA has been proposed based on parallel execution mechanism for enhancement of performance and flexibility. Modelsim as simulation platform and VHDL used to translate, integrate and implement the logic circuit in FPGA. Xilinx's Spartan kit for implementation-testing and VB has been used for GUI development. Salient merits of the design include cost-effectiveness, miniaturization, user-friendliness, simplicity, along with lower power consumption, smaller scan time and higher speed. Various functionalities and applications like typical PLC and industrial alarm annunciator have been developed and successfully tested. Results of simulation, design and implementation have been reported. Copyright © 2014 ISA. Published by Elsevier Ltd. All rights reserved.

Digital high speed programmable convolver

NASA Astrophysics Data System (ADS)

Rearick, T. C.

1984-12-01

A circuit module for rapidly calculating a discrete numerical convolution is described. A convolution such as finding the sum of the products of a 16 bit constant and a 16 bit variable is performed by a module which is programmable so that the constant may be changed for a new problem. In addition, the module may be programmed to find the sum of the products of 4 and 8 bit constants and variables. RAM (Random Access Memories) are loaded with partial products of the selected constant and all possible variables. Then, when the actual variable is loaded, it acts as an address to find the correct partial product in the particular RAM. The partial products from all of the RAMs are shifted to the appropriate numerical power position (if necessary) and then added in adder elements.

Field-Programmable Gate Array-based fluxgate magnetometer with digital integration

NASA Astrophysics Data System (ADS)

Butta, Mattia; Janosek, Michal; Ripka, Pavel

2010-05-01

In this paper, a digital magnetometer based on printed circuit board fluxgate is presented. The fluxgate is pulse excited and the signal is extracted by gate integration. We investigate the possibility to perform integration on very narrow gates (typically 500 ns) by using digital techniques. The magnetometer is based on field-programmable gate array (FPGA) card: we will show all the advantages and disadvantages, given by digitalization of fluxgate output voltage by means of analog-to-digital converter on FPGA card, as well as digitalization performed by external digitizer. Due to very narrow gate, it is shown that a magnetometer entirely based on a FPGA card is preferable, because it avoids noise due to trigger instability. Both open loop and feedback operative mode are described and achieved results are presented.

A low power flash-FPGA based brain implant micro-system of PID control.

PubMed

Lijuan Xia; Fattah, Nabeel; Soltan, Ahmed; Jackson, Andrew; Chester, Graeme; Degenaar, Patrick

2017-07-01

In this paper, we demonstrate that a low power flash FPGA based micro-system can provide a low power programmable interface for closed-loop brain implant inter- faces. The proposed micro-system receives recording local field potential (LFP) signals from an implanted probe, performs closed-loop control using a first order control system, then converts the signal into an optogenetic control stimulus pattern. Stimulus can be implemented through optoelectronic probes. The long term target is for both fundamental neuroscience applications and for clinical use in treating epilepsy. Utilizing our device, closed-loop processing consumes only 14nJ of power per PID cycle compared to 1.52μJ per cycle for a micro-controller implementation. Compared to an application specific digital integrated circuit, flash FPGA's are inherently programmable.

Field Programmable Gate Array Failure Rate Estimation Guidelines for Launch Vehicle Fault Tree Models

NASA Technical Reports Server (NTRS)

Al Hassan, Mohammad; Britton, Paul; Hatfield, Glen Spencer; Novack, Steven D.

2017-01-01

Today's launch vehicles complex electronic and avionics systems heavily utilize Field Programmable Gate Array (FPGA) integrated circuits (IC) for their superb speed and reconfiguration capabilities. Consequently, FPGAs are prevalent ICs in communication protocols such as MILSTD- 1553B and in control signal commands such as in solenoid valve actuations. This paper will identify reliability concerns and high level guidelines to estimate FPGA total failure rates in a launch vehicle application. The paper will discuss hardware, hardware description language, and radiation induced failures. The hardware contribution of the approach accounts for physical failures of the IC. The hardware description language portion will discuss the high level FPGA programming languages and software/code reliability growth. The radiation portion will discuss FPGA susceptibility to space environment radiation.

Radiation testing campaign results for understanding the suitability of FPGAs in detector electronics

DOE PAGES

Citterio, M.; Camplani, A.; Cannon, M.; ...

2015-11-19

SRAM based Field Programmable Gate Arrays (FPGAs) have been rarely used in High Energy Physics (HEP) due to their sensitivity to radiation. The last generation of commercial FPGAs based on 28 nm feature size and on Silicon On Insulator (SOI) technologies are more tolerant to radiation to the level that their use in front-end electronics is now feasible. FPGAs provide re-programmability, high-speed computation and fast data transmission through the embedded serial transceivers. They could replace custom application specific integrated circuits in front end electronics in locations with moderate radiation field. Finally, the use of a FPGA in HEP experiments ismore » only limited by our ability to mitigate single event effects induced by the high energy hadrons present in the radiation field.« less

JavaGenes: Evolving Graphs with Crossover

NASA Technical Reports Server (NTRS)

Globus, Al; Atsatt, Sean; Lawton, John; Wipke, Todd

2000-01-01

Genetic algorithms usually use string or tree representations. We have developed a novel crossover operator for a directed and undirected graph representation, and used this operator to evolve molecules and circuits. Unlike strings or trees, a single point in the representation cannot divide every possible graph into two parts, because graphs may contain cycles. Thus, the crossover operator is non-trivial. A steady-state, tournament selection genetic algorithm code (JavaGenes) was written to implement and test the graph crossover operator. All runs were executed by cycle-scavagging on networked workstations using the Condor batch processing system. The JavaGenes code has evolved pharmaceutical drug molecules and simple digital circuits. Results to date suggest that JavaGenes can evolve moderate sized drug molecules and very small circuits in reasonable time. The algorithm has greater difficulty with somewhat larger circuits, suggesting that directed graphs (circuits) are more difficult to evolve than undirected graphs (molecules), although necessary differences in the crossover operator may also explain the results. In principle, JavaGenes should be able to evolve other graph-representable systems, such as transportation networks, metabolic pathways, and computer networks. However, large graphs evolve significantly slower than smaller graphs, presumably because the space-of-all-graphs explodes combinatorially with graph size. Since the representation strongly affects genetic algorithm performance, adding graphs to the evolutionary programmer's bag-of-tricks should be beneficial. Also, since graph evolution operates directly on the phenotype, the genotype-phenotype translation step, common in genetic algorithm work, is eliminated.

Floating-Gate Manipulated Graphene-Black Phosphorus Heterojunction for Nonvolatile Ambipolar Schottky Junction Memories, Memory Inverter Circuits, and Logic Rectifiers.

PubMed

Li, Dong; Chen, Mingyuan; Zong, Qijun; Zhang, Zengxing

2017-10-11

The Schottky junction is an important unit in electronics and optoelectronics. However, its properties greatly degrade with device miniaturization. The fast development of circuits has fueled a rapid growth in the study of two-dimensional (2D) crystals, which may lead to breakthroughs in the semiconductor industry. Here we report a floating-gate manipulated nonvolatile ambipolar Schottky junction memory from stacked all-2D layers of graphene-BP/h-BN/graphene (BP, black phosphorus; h-BN, hexagonal boron nitride) in a designed floating-gate field-effect Schottky barrier transistor configuration. By manipulating the voltage pulse applied to the control gate, the device exhibits ambipolar characteristics and can be tuned to act as graphene-p-BP or graphene-n-BP junctions with reverse rectification behavior. Moreover, the junction exhibits good storability properties of more than 10 years and is also programmable. On the basis of these characteristics, we further demonstrate the application of the device to dual-mode nonvolatile Schottky junction memories, memory inverter circuits, and logic rectifiers.

Pax narcotica

PubMed Central

Bourgois, Philippe; Hart, Laurie Kain

2016-01-01

RÉSUMÉ/ABSTRACT Fondé sur un travail de terrain mené pendant cinq ans dans le ghetto portoricain de Philadelphie, cet article explore les logiques de violence et de paix à l’œuvre dans ce secteur situé en fin de circuit de l’industrie globale du narcotrafic. Tout en recourant à la violence armée pour éliminer leurs rivaux et défendre leur territoire, les patrons locaux de la drogue doivent simultanément renvoyer l’image de figures généreuses pour éviter que les habitants ne les dénoncent à la police, en se montrant responsables, prêts à redistribuer les ressources, à offrir des emplois bien rémunérés, à discipliner leurs employés et à contenir les excès de violence. Les chefs de la drogue sont donc contraints de transformer leur force brute en un pouvoir vertueux pour prospérer. Ils participent ainsi, avec voisins et employés, à une économie morale de relations patrimoniales et clientélistes au sein de laquelle ils s’imposent comme des leaders charismatiques. À partir d’une relecture du concept d’ « accumulation primitive », cet article revient à la fois : 1) sur la relation coloniale qui pousse la diaspora portoricaine ghettoïsée dans la niche économique que représente la revente de drogue au détail; 2) sur la violence symbolique à l’œuvre à tous les échelons de ce trafic; 3) sur les profits artificiellement élevés générés par cette industrie criminalisée par l’État; 4) et sur la prolifération opportuniste de secteurs spécialisés de l’économie légale et de la bureaucratie publique chargés de gérer les effets collatéraux de la coercition et des violences d’État. PMID:28090135

Intelligent layered nanoflare: ``lab-on-a-nanoparticle'' for multiple DNA logic gate operations and efficient intracellular delivery

NASA Astrophysics Data System (ADS)

Yang, Bin; Zhang, Xiao-Bing; Kang, Li-Ping; Huang, Zhi-Mei; Shen, Guo-Li; Yu, Ru-Qin; Tan, Weihong

2014-07-01

DNA strand displacement cascades have been engineered to construct various fascinating DNA circuits. However, biological applications are limited by the insufficient cellular internalization of naked DNA structures, as well as the separated multicomponent feature. In this work, these problems are addressed by the development of a novel DNA nanodevice, termed intelligent layered nanoflare, which integrates DNA computing at the nanoscale, via the self-assembly of DNA flares on a single gold nanoparticle. As a ``lab-on-a-nanoparticle'', the intelligent layered nanoflare could be engineered to perform a variety of Boolean logic gate operations, including three basic logic gates, one three-input AND gate, and two complex logic operations, in a digital non-leaky way. In addition, the layered nanoflare can serve as a programmable strategy to sequentially tune the size of nanoparticles, as well as a new fingerprint spectrum technique for intelligent multiplex biosensing. More importantly, the nanoflare developed here can also act as a single entity for intracellular DNA logic gate delivery, without the need of commercial transfection agents or other auxiliary carriers. By incorporating DNA circuits on nanoparticles, the presented layered nanoflare will broaden the applications of DNA circuits in biological systems, and facilitate the development of DNA nanotechnology.DNA strand displacement cascades have been engineered to construct various fascinating DNA circuits. However, biological applications are limited by the insufficient cellular internalization of naked DNA structures, as well as the separated multicomponent feature. In this work, these problems are addressed by the development of a novel DNA nanodevice, termed intelligent layered nanoflare, which integrates DNA computing at the nanoscale, via the self-assembly of DNA flares on a single gold nanoparticle. As a ``lab-on-a-nanoparticle'', the intelligent layered nanoflare could be engineered to perform a variety of Boolean logic gate operations, including three basic logic gates, one three-input AND gate, and two complex logic operations, in a digital non-leaky way. In addition, the layered nanoflare can serve as a programmable strategy to sequentially tune the size of nanoparticles, as well as a new fingerprint spectrum technique for intelligent multiplex biosensing. More importantly, the nanoflare developed here can also act as a single entity for intracellular DNA logic gate delivery, without the need of commercial transfection agents or other auxiliary carriers. By incorporating DNA circuits on nanoparticles, the presented layered nanoflare will broaden the applications of DNA circuits in biological systems, and facilitate the development of DNA nanotechnology. Electronic supplementary information (ESI) available: Additional figures (Table S1, Fig. S1-S5). See DOI: 10.1039/c4nr01676a

Operating scheme for the light-emitting diode array of a volumetric display that exhibits multiple full-color dynamic images

NASA Astrophysics Data System (ADS)

Hirayama, Ryuji; Shiraki, Atsushi; Nakayama, Hirotaka; Kakue, Takashi; Shimobaba, Tomoyoshi; Ito, Tomoyoshi

2017-07-01

We designed and developed a control circuit for a three-dimensional (3-D) light-emitting diode (LED) array to be used in volumetric displays exhibiting full-color dynamic 3-D images. The circuit was implemented on a field-programmable gate array; therefore, pulse-width modulation, which requires high-speed processing, could be operated in real time. We experimentally evaluated the developed system by measuring the luminance of an LED with varying input and confirmed that the system works appropriately. In addition, we demonstrated that the volumetric display exhibits different full-color dynamic two-dimensional images in two orthogonal directions. Each of the exhibited images could be obtained only from the prescribed viewpoint. Such directional characteristics of the system are beneficial for applications, including digital signage, security systems, art, and amusement.

Sequential power-up circuit

DOEpatents

Kronberg, J.W.

1992-06-02

A sequential power-up circuit for starting several electrical load elements in series to avoid excessive current surge, comprising a voltage ramp generator and a set of voltage comparators, each comparator having a different reference voltage and interfacing with a switch that is capable of turning on one of the load elements. As the voltage rises, it passes the reference voltages one at a time and causes the switch corresponding to that voltage to turn on its load element. The ramp is turned on and off by a single switch or by a logic-level electrical signal. The ramp rate for turning on the load element is relatively slow and the rate for turning the elements off is relatively fast. Optionally, the duration of each interval of time between the turning on of the load elements is programmable. 2 figs.

Comparison between two photovoltaic module models based on transistors

NASA Astrophysics Data System (ADS)

Saint-Eve, Frédéric; Sawicki, Jean-Paul; Petit, Pierre; Maufay, Fabrice; Aillerie, Michel

2018-05-01

The main objective of this paper is to verify the possibility to reduce to a simple electronic circuit with very few components the behavior simulation of an un-shaded photovoltaic (PV) module. Particularly, two models based on well-tried elementary structures, i.e., the Darlington structure in first model and the voltage regulation with programmable Zener diode in the second are analyzed. Specifications extracted from the behavior of a real I-V characteristic of a panel are considered and the principal electrical variables are deduced. The two models are expected to match with open circuit voltage, maximum power point (MPP) and short circuit current, without forgetting realistic current slopes on the both sides of MPP. The robustness is mentioned when irradiance varies and is considered as an additional fundamental property. For both models, two simulations are done to identify influence of some parameters. In the first model, a parameter allowing to adjust current slope on left side of MPP proves to be also important for the calculation of open circuit voltage. Besides this model does not authorize an entirely adjustment of I-V characteristic and MPP moves significantly away from real value when irradiance increases. On the contrary, the second model seems to have only qualities: open circuit voltage is easy to calculate, current slopes are realistic and there is perhaps a good robustness when irradiance variations are simulated by adjusting short circuit current of PV module. We have shown that these two simplified models are expected to make reliable and easier simulations of complex PV architecture integrating many different devices like PV modules or other renewable energy sources and storage capacities coupled in parallel association.

Design of a signal conditioner for the Fermilab Magnet Test Facility

DOE Office of Scientific and Technical Information (OSTI.GOV)

Giannelli, Pietro

2012-01-01

This thesis describes the design of a remotely-programmable signal conditioner for the harmonic measurement of accelerator magnets. A 10-channel signal conditioning circuit featuring bucking capabilities was designed from scratch and implemented to the level of the printed circuit board layout. Other system components were chosen from those available on the market. Software design was started with the definition of routine procedures. This thesis is part of an upgrade project for replacing obsolescent automated test equipment belonging to the Fermilab Magnet Test Facility. The design started with a given set of requirements. Using a top-down approach, all the circuits were designedmore » and their expected performances were theoretically predicted and simulated. A limited prototyping phase followed. The printed circuit boards were laid out and routed using a CAD software and focusing the design on maximum electromagnetic interference immunity. An embedded board was selected for controlling and interfacing the signal conditioning circuitry with the instrumentation network. Basic low level routines for hardware access were defined. This work covered the entire design process of the signal conditioner, resulting in a project ready for manufacturing. The expected performances are in line with the requirements and, in the cases where this was not possible, approval of trade-offs was sought and received from the end users. Part I deals with the global structure of the signal conditioner and the subdivision in functional macro-blocks. Part II treats the hardware design phase in detail, covering the analog and digital circuits, the printed circuit layouts, the embedded controller and the power supply selection. Part III deals with the basic hardware-related routines to be implemented in the final software.« less

Electrically Erasable Programmable Integrated Circuits for Replacement of Obsolete TTL Logic

DTIC Science & Technology

1991-12-01

different discrete devices" [7]. Fowler-Nordheim Tunneling Simplified Theory. Electrons in polysilicon are usually prevented from entering SiO 2 by an...overcomes the energy barrier, the tunneling electrons will not return to the polysilicon but will be carried by the electric field, causing a current to flow...Floating Gate Transistors A floating gate transistor is an insulated-gate field effect transistor (FET) that has a gate, usually made of polysilicon , which

Programmable cells: Interfacing natural and engineered gene networks

NASA Astrophysics Data System (ADS)

Kobayashi, Hideki; Kærn, Mads; Araki, Michihiro; Chung, Kristy; Gardner, Timothy S.; Cantor, Charles R.; Collins, James J.

2004-06-01

Novel cellular behaviors and characteristics can be obtained by coupling engineered gene networks to the cell's natural regulatory circuitry through appropriately designed input and output interfaces. Here, we demonstrate how an engineered genetic circuit can be used to construct cells that respond to biological signals in a predetermined and programmable fashion. We employ a modular design strategy to create Escherichia coli strains where a genetic toggle switch is interfaced with: (i) the SOS signaling pathway responding to DNA damage, and (ii) a transgenic quorum sensing signaling pathway from Vibrio fischeri. The genetic toggle switch endows these strains with binary response dynamics and an epigenetic inheritance that supports a persistent phenotypic alteration in response to transient signals. These features are exploited to engineer cells that form biofilms in response to DNA-damaging agents and cells that activate protein synthesis when the cell population reaches a critical density. Our work represents a step toward the development of "plug-and-play" genetic circuitry that can be used to create cells with programmable behaviors. heterologous gene expression | synthetic biology | Escherichia coli

Clock jitter generator with picoseconds resolution

NASA Astrophysics Data System (ADS)

Jovanović, Goran; Stojčev, Mile; Nikolić, Tatjana

2013-06-01

The clock is one of the most critical signals in any synchronous system. As CMOS technology has scaled, supply voltages have dropped chip power consumption has increased and the effects of jitter due to clock frequency increase have become critical and jitter budget has become tighter. This article describes design and development of low-cost mixed-signal programmable jitter generator with high resolution. The digital technique is used for coarse-grain and an analogue technique for fine-grain clock phase shifting. Its structure allows injection of various random and deterministic jitter components in a controllable and programmable fashion. Each jitter component can be switched on or off. The jitter generator can be used in jitter tolerance test and jitter transfer function measurement of high-speed synchronous digital circuits. At operating system clock frequency of 220 MHz, a jitter with 4 ps resolution can be injected.

A reconfigurable medically cohesive biomedical front-end with ΣΔ ADC in 0.18µm CMOS.

PubMed

Jha, Pankaj; Patra, Pravanjan; Naik, Jairaj; Acharya, Amit; Rajalakshmi, P; Singh, Shiv Govind; Dutta, Ashudeb

2015-08-01

This paper presents a generic programmable analog front-end (AFE) for acquisition and digitization of various biopotential signals. This includes a lead-off detection circuit, an ultra-low current capacitively coupled signal conditioning stage with programmable gain and bandwidth, a new mixed signal automatic gain control (AGC) mechanism and a medically cohesive reconfigurable ΣΔ ADC. The full system is designed in UMC 0.18μm CMOS. The AFE achieves an overall linearity of more 10 bits with 0.47μW power consumption. The ADC provides 2(nd) order noise-shaping while using single integrator and an ENOB of ~11 bits with 5μW power consumption. The system was successfully verified for various ECG signals from PTB database. This system is intended for portable batteryless u-Healthcare devices.

Field Programmable Gate Array Reliability Analysis Guidelines for Launch Vehicle Reliability Block Diagrams

NASA Technical Reports Server (NTRS)

Al Hassan, Mohammad; Britton, Paul; Hatfield, Glen Spencer; Novack, Steven D.

2017-01-01

Field Programmable Gate Arrays (FPGAs) integrated circuits (IC) are one of the key electronic components in today's sophisticated launch and space vehicle complex avionic systems, largely due to their superb reprogrammable and reconfigurable capabilities combined with relatively low non-recurring engineering costs (NRE) and short design cycle. Consequently, FPGAs are prevalent ICs in communication protocols and control signal commands. This paper will identify reliability concerns and high level guidelines to estimate FPGA total failure rates in a launch vehicle application. The paper will discuss hardware, hardware description language, and radiation induced failures. The hardware contribution of the approach accounts for physical failures of the IC. The hardware description language portion will discuss the high level FPGA programming languages and software/code reliability growth. The radiation portion will discuss FPGA susceptibility to space environment radiation.

Field Programmable Gate Array Failure Rate Estimation Guidelines for Launch Vehicle Fault Tree Models

NASA Technical Reports Server (NTRS)

Al Hassan, Mohammad; Novack, Steven D.; Hatfield, Glen S.; Britton, Paul

2017-01-01

Today's launch vehicles complex electronic and avionic systems heavily utilize the Field Programmable Gate Array (FPGA) integrated circuit (IC). FPGAs are prevalent ICs in communication protocols such as MIL-STD-1553B, and in control signal commands such as in solenoid/servo valves actuations. This paper will demonstrate guidelines to estimate FPGA failure rates for a launch vehicle, the guidelines will account for hardware, firmware, and radiation induced failures. The hardware contribution of the approach accounts for physical failures of the IC, FPGA memory and clock. The firmware portion will provide guidelines on the high level FPGA programming language and ways to account for software/code reliability growth. The radiation portion will provide guidelines on environment susceptibility as well as guidelines on tailoring other launch vehicle programs historical data to a specific launch vehicle.

[Circuit resistance training improved endothelial dysfunction in obese aged women].

PubMed

Rosety, Ignacio; Pery, María Teresa; Rosety, Jesús; García, Natalia; Rodríguez-Pareja, María Antonia; Brenes-Martín, Francisco; Díaz, Antonio; Rosety-Rodríguez, Manuel; Ordoñez, Francisco Javier; Rosety, Miguel Ángel

2016-02-16

It is widely accepted that obesity is associated with endothelial dysfunction. In a recent paper, we have also found circuit resistance training may reduce visceral fat in obese aged women. Accordingly, the current study was conducted to ascertain the effects of circuit resistance training on markers of endothelial dysfunction in this population group. In the present interventional study, a total of 48 obese aged women were recruited from the community. Twenty-four of them were randomly assigned to perform a 12-week resistance circuit training programme, 3-days per week. This training was circularly performed in 6 stations: arm curl, leg extension, seated row, leg curl, triceps extension and leg press. The Jamar handgrip electronic dynamometer was used to assess maximal handgrip strength of the dominant hand. Lastly, serum samples were analysed using an immunoassay (ELISA) for endothelin-1, intercellular adhesion molecule-1 (ICAM-1) and vascular cell adhesion molecule-1 (VCAM-1). When compared to baseline, resistance training significantly reduced serum levels of endothelin-1 (2.28 ± 0.7 vs. 1.98 ± 1.1 pg/ml; p = 0.019; d = 0.67) and ICAM-1 (290 ± 69 vs. 255 ± 76 ng/ml; p = 0.004; d = 0.92) in the experimental group. No significant changes in any of the tested outcomes were found in the control group. A short-term circuit resistance program improved endothelial dysfunction in aged obese women. Further studies on this topic are still required to consolidate this approach in clinical application.

[Influence of a programme of therapeutic exercise on different clinical indicators related to dyslipidaemia in adult subjects aged between 26 to 73 years with a cardiovascular risk factor].

PubMed

Meseguer Zafra, M; Rosa Guillamón, A; García-Cantó, E; Rodríguez García, P L; Pérez-Soto, J J; Tárraga López, P J; Del Moral García, J E; Tárraga Marcos, M L

2018-04-07

A sedentary lifestyle is indicated in the international literature as one of the main causes for the onset of some cardiovascular risk factors. To assess the effect of a therapeutic physical exercise programme on different clinical indicators related to dyslipidaemia (total cholesterol, HDL and LDL) in sedentary subjects with a cardiovascular risk factor. Intervention study with before-and-after evaluation of a sample of 340 patients (132 males and 208 females) referred from the 2 primary care centres of the municipality of Molina de Segura (Murcia), and who participated in a 30-week programme of physical exercise combining muscle-conditioning work circuits with other cardio-respiratory resistance workouts. Regarding the clinical indicators, the health professionals collected in the medical history the health indicators corresponding to the biological evolution of the process for which the subjects studied had started the physical exercise programme. The statistical analyses showed a significant improvement (p<.005) in the LDL indicator and a non-significant improvement in total and HDL cholesterol indicators after a 3-month exercise programme of 3 weekly sessions. The prescription of physical exercise in dyslipidaemic subjects from primary care centre should be evaluated as a resource for improving the clinical indicators specific to their pathology. Copyright © 2018 SEH-LELHA. Publicado por Elsevier España, S.L.U. All rights reserved.

A Secure and Reliable High-Performance Field Programmable Gate Array for Information Processing

DTIC Science & Technology

2012-03-01

receives a data token from its control input (shown as a horizontal arrow above). The value of this data token is used to select an input port. The input...dual of a merge. It receives a data token from its control input (shown as a horizontal arrow above). The value of this data token is used to select...Transactions on Computer-Aided Design of Intergrated Circuits and Systems, Vol. 26, No. 2, February 2007. [12] Cadence Design Systems, “Clock Domain

CMOS array design automation techniques

NASA Technical Reports Server (NTRS)

Lombardi, T.; Feller, A.

1976-01-01

The design considerations and the circuit development for a 4096-bit CMOS SOS ROM chip, the ATL078 are described. Organization of the ATL078 is 512 words by 8 bits. The ROM was designed to be programmable either at the metal mask level or by a directed laser beam after processing. The development of a 4K CMOS SOS ROM fills a void left by available ROM chip types, and makes the design of a totally major high speed system more realizable.

Fly-By-Light/Power-By-Wire Fault-Tolerant Fiber-Optic Backplane

NASA Technical Reports Server (NTRS)

Malekpour, Mahyar R.

2002-01-01

The design and development of a fault-tolerant fiber-optic backplane to demonstrate feasibility of such architecture is presented. The simulation results of test cases on the backplane in the advent of induced faults are presented, and the fault recovery capability of the architecture is demonstrated. The architecture was designed, developed, and implemented using the Very High Speed Integrated Circuits (VHSIC) Hardware Description Language (VHDL). The architecture was synthesized and implemented in hardware using Field Programmable Gate Arrays (FPGA) on multiple prototype boards.

Laser programmable integrated circuit for forming synapses in neural networks

DOEpatents

Fu, C.Y.

1997-02-11

Customizable neural network in which one or more resistors form each synapse is disclosed. All the resistors in the synaptic array are identical, thus simplifying the processing issues. Highly doped, amorphous silicon is used as the resistor material, to create extremely high resistances occupying very small spaces. Connected in series with each resistor in the array is at least one severable conductor whose uppermost layer has a lower reflectivity of laser energy than typical metal conductors at a desired laser wavelength. 5 figs.

Performance characteristics of a nanoscale double-gate reconfigurable array

NASA Astrophysics Data System (ADS)

Beckett, Paul

2008-12-01

The double gate transistor is a promising device applicable to deep sub-micron design due to its inherent resistance to short-channel effects and superior subthreshold performance. Using both TCAD and SPICE circuit simulation, it is shown that the characteristics of fully depleted dual-gate thin-body Schottky barrier silicon transistors will not only uncouple the conflicting requirements of high performance and low standby power in digital logic, but will also allow the development of a locally-connected reconfigurable computing mesh. The magnitude of the threshold shift effect will scale with device dimensions and will remain compatible with oxide reliability constraints. A field-programmable architecture based on the double gate transistor is described in which the operating point of the circuit is biased via one gate while the other gate is used to form the logic array, such that complex heterogeneous computing functions may be developed from this homogeneous, mesh-connected organization.

A Pipelined Non-Deterministic Finite Automaton-Based String Matching Scheme Using Merged State Transitions in an FPGA

PubMed Central

Choi, Kang-Il

2016-01-01

This paper proposes a pipelined non-deterministic finite automaton (NFA)-based string matching scheme using field programmable gate array (FPGA) implementation. The characteristics of the NFA such as shared common prefixes and no failure transitions are considered in the proposed scheme. In the implementation of the automaton-based string matching using an FPGA, each state transition is implemented with a look-up table (LUT) for the combinational logic circuit between registers. In addition, multiple state transitions between stages can be performed in a pipelined fashion. In this paper, it is proposed that multiple one-to-one state transitions, called merged state transitions, can be performed with an LUT. By cutting down the number of used LUTs for implementing state transitions, the hardware overhead of combinational logic circuits is greatly reduced in the proposed pipelined NFA-based string matching scheme. PMID:27695114

A Pipelined Non-Deterministic Finite Automaton-Based String Matching Scheme Using Merged State Transitions in an FPGA.

PubMed

Kim, HyunJin; Choi, Kang-Il

2016-01-01

This paper proposes a pipelined non-deterministic finite automaton (NFA)-based string matching scheme using field programmable gate array (FPGA) implementation. The characteristics of the NFA such as shared common prefixes and no failure transitions are considered in the proposed scheme. In the implementation of the automaton-based string matching using an FPGA, each state transition is implemented with a look-up table (LUT) for the combinational logic circuit between registers. In addition, multiple state transitions between stages can be performed in a pipelined fashion. In this paper, it is proposed that multiple one-to-one state transitions, called merged state transitions, can be performed with an LUT. By cutting down the number of used LUTs for implementing state transitions, the hardware overhead of combinational logic circuits is greatly reduced in the proposed pipelined NFA-based string matching scheme.

Hyperbranched Hybridization Chain Reaction for Triggered Signal Amplification and Concatenated Logic Circuits.

PubMed

Bi, Sai; Chen, Min; Jia, Xiaoqiang; Dong, Ying; Wang, Zonghua

2015-07-06

A hyper-branched hybridization chain reaction (HB-HCR) is presented herein, which consists of only six species that can metastably coexist until the introduction of an initiator DNA to trigger a cascade of hybridization events, leading to the self-sustained assembly of hyper-branched and nicked double-stranded DNA structures. The system can readily achieve ultrasensitive detection of target DNA. Moreover, the HB-HCR principle is successfully applied to construct three-input concatenated logic circuits with excellent specificity and extended to design a security-mimicking keypad lock system. Significantly, the HB-HCR-based keypad lock can alarm immediately if the "password" is incorrect. Overall, the proposed HB-HCR with high amplification efficiency is simple, homogeneous, fast, robust, and low-cost, and holds great promise in the development of biosensing, in the programmable assembly of DNA architectures, and in molecular logic operations. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

FPGA implementation of self organizing map with digital phase locked loops.

PubMed

Hikawa, Hiroomi

2005-01-01

The self-organizing map (SOM) has found applicability in a wide range of application areas. Recently new SOM hardware with phase modulated pulse signal and digital phase-locked loops (DPLLs) has been proposed (Hikawa, 2005). The system uses the DPLL as a computing element since the operation of the DPLL is very similar to that of SOM's computation. The system also uses square waveform phase to hold the value of the each input vector element. This paper discuss the hardware implementation of the DPLL SOM architecture. For effective hardware implementation, some components are redesigned to reduce the circuit size. The proposed SOM architecture is described in VHDL and implemented on field programmable gate array (FPGA). Its feasibility is verified by experiments. Results show that the proposed SOM implemented on the FPGA has a good quantization capability, and its circuit size very small.

Real-time fast physical random number generator with a photonic integrated circuit.

PubMed

Ugajin, Kazusa; Terashima, Yuta; Iwakawa, Kento; Uchida, Atsushi; Harayama, Takahisa; Yoshimura, Kazuyuki; Inubushi, Masanobu

2017-03-20

Random number generators are essential for applications in information security and numerical simulations. Most optical-chaos-based random number generators produce random bit sequences by offline post-processing with large optical components. We demonstrate a real-time hardware implementation of a fast physical random number generator with a photonic integrated circuit and a field programmable gate array (FPGA) electronic board. We generate 1-Tbit random bit sequences and evaluate their statistical randomness using NIST Special Publication 800-22 and TestU01. All of the BigCrush tests in TestU01 are passed using 410-Gbit random bit sequences. A maximum real-time generation rate of 21.1 Gb/s is achieved for random bit sequences in binary format stored in a computer, which can be directly used for applications involving secret keys in cryptography and random seeds in large-scale numerical simulations.

Medical telesensors

NASA Astrophysics Data System (ADS)

Ferrell, Trinidad L.; Crilly, P. B.; Smith, S. F.; Wintenberg, Alan L.; Britton, Charles L., Jr.; Morrison, Gilbert W.; Ericson, M. N.; Hedden, D.; Bouldin, Donald W.; Passian, A.; Downey, Todd R.; Wig, A. G.; Meriaudeau, Fabrice

1998-05-01

Medical telesensors are self-contained integrated circuits for measuring and transmitting vital signs over a distance of approximately 1-2 meters. The circuits are unhoused and contain a sensor, signal processing and modulation electronics, a spread-spectrum transmitter, an antenna and a thin-film battery. We report on a body-temperature telesensor, which is sufficiently small to be placed on a tympanic membrane in a child's ear. We also report on a pulse-oximeter telesensor and a micropack receiver/long- range transmitter unit, which receives form a telesensor array and analyzes and re-transmits the vital signs over a longer range. Signal analytics are presented for the pulse oximeter, which is currently in the form of a finger ring. A multichip module is presented as the basic signal-analysis component. The module contains a microprocessor, a field=programmable gate array, memory elements and other components necessary for determining trauma and reporting signals.

FPGA-based gating and logic for multichannel single photon counting

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pooser, Raphael C; Earl, Dennis Duncan; Evans, Philip G

2012-01-01

We present results characterizing multichannel InGaAs single photon detectors utilizing gated passive quenching circuits (GPQC), self-differencing techniques, and field programmable gate array (FPGA)-based logic for both diode gating and coincidence counting. Utilizing FPGAs for the diode gating frontend and the logic counting backend has the advantage of low cost compared to custom built logic circuits and current off-the-shelf detector technology. Further, FPGA logic counters have been shown to work well in quantum key distribution (QKD) test beds. Our setup combines multiple independent detector channels in a reconfigurable manner via an FPGA backend and post processing in order to perform coincidencemore » measurements between any two or more detector channels simultaneously. Using this method, states from a multi-photon polarization entangled source are detected and characterized via coincidence counting on the FPGA. Photons detection events are also processed by the quantum information toolkit for application testing (QITKAT)« less

An embedded measurement system for the electrical characterization of EGFET as a pH sensor

NASA Astrophysics Data System (ADS)

Diniz Batista, Pablo

2014-02-01

This work presents the development of an electronic system for the electrical characterization of pH sensors based on the extended gate field effect transistor (EGFET). We designed an electronic circuit with a microcontroller (PIC15F14K50) as the main component in order to provide two programmable output voltages as well as circuits to measure electric current and voltages. The instrument performance analysis was carried out using a glass electrode as a sensitive membrane for investigating the EGFET operation as a pH sensor. The results show that the system is an alternative to the commercial equipment for the electrical characterization of sensors based on field effect devices. In addition, some of the key features expected of this electronic module are: low cost, flexibility, portability and communication with a personal computer using a USB port.

A digital receiver module with direct data acquisition for magnetic resonance imaging systems.

PubMed

Tang, Weinan; Sun, Hongyu; Wang, Weimin

2012-10-01

A digital receiver module for magnetic resonance imaging (MRI) with detailed hardware implementations is presented. The module is based on a direct sampling scheme using the latest mixed-signal circuit design techniques. A single field-programmable gate array chip is employed to perform software-based digital down conversion for radio frequency signals. The modular architecture of the receiver allows multiple acquisition channels to be implemented on a highly integrated printed circuit board. To maintain the phase coherence of the receiver and the exciter in the context of direct sampling, an effective phase synchronization method was proposed to achieve a phase deviation as small as 0.09°. The performance of the described receiver module was verified in the experiments for both low- and high-field (0.5 T and 1.5 T) MRI scanners and was compared to a modern commercial MRI receiver system.

High-voltage, high-power, solid-state remote power controllers for aerospace applications

NASA Technical Reports Server (NTRS)

Sturman, J. C.

1985-01-01

Two general types of remote power controller (RPC) that combine the functions of a circuit breaker and a switch were developed for use in direct-current (dc) aerospace systems. Power-switching devices used in these designs are the relatively new gate-turnoff thyristor (GTO) and poweer metal-oxide-semiconductor field-effect transistors (MOSFET). The various RPC's can switch dc voltages to 1200 V and currents to 100 A. Seven different units were constructed and subjected to comprehensive laboratory and thermal vacuum testing. Two of these were dual units that switch both positive and negative voltages simultaneously. The RPC's using MOSFET's have slow turnon and turnoff times to limit voltage spiking from high di/dt. The GTO's have much faster transition times. All RPC's have programmable overload tripout and microsecond tripout for large overloads. The basic circuits developed can be used to build switchgear limited only by the ratings of the switching device used.

Synthetic Biology Platform for Sensing and Integrating Endogenous Transcriptional Inputs in Mammalian Cells.

PubMed

Angelici, Bartolomeo; Mailand, Erik; Haefliger, Benjamin; Benenson, Yaakov

2016-08-30

One of the goals of synthetic biology is to develop programmable artificial gene networks that can transduce multiple endogenous molecular cues to precisely control cell behavior. Realizing this vision requires interfacing natural molecular inputs with synthetic components that generate functional molecular outputs. Interfacing synthetic circuits with endogenous mammalian transcription factors has been particularly difficult. Here, we describe a systematic approach that enables integration and transduction of multiple mammalian transcription factor inputs by a synthetic network. The approach is facilitated by a proportional amplifier sensor based on synergistic positive autoregulation. The circuits efficiently transduce endogenous transcription factor levels into RNAi, transcriptional transactivation, and site-specific recombination. They also enable AND logic between pairs of arbitrary transcription factors. The results establish a framework for developing synthetic gene networks that interface with cellular processes through transcriptional regulators. Copyright © 2016 The Author(s). Published by Elsevier Inc. All rights reserved.

Circuit design and simulation of a transmit beamforming ASIC for high-frequency ultrasonic imaging systems.

PubMed

Athanasopoulos, Georgios I; Carey, Stephen J; Hatfield, John V

2011-07-01

This paper describes the design of a programmable transmit beamformer application-specific integrated circuit (ASIC) with 8 channels for ultrasound imaging systems. The system uses a 20-MHz reference clock. A digital delay-locked loop (DLL) was designed with 50 variable delay elements, each of which provides a clock with different phase from a single reference. Two phase detectors compare the phase difference of the reference clock with the feedback clock, adjusting the delay of the delay elements to bring the feedback clock signal in phase with the reference clock signal. Two independent control voltages for the delay elements ensure that the mark space ratio of the pulses remain at 50%. By combining a 10- bit asynchronous counter with the delays from the DLL, each channel can be programmed to give a maximum time delay of 51 μs with 1 ns resolution. It can also give bursts of up to 64 pulses. Finally, for a single pulse, it can adjust the pulse width between 9 ns and 100 ns by controlling the current flowing through a capacitor in a one-shot circuit, for use with 40-MHz and 5-MHz transducers, respectively.

Communications technology

NASA Astrophysics Data System (ADS)

Sokoloski, Martin M.

1988-09-01

The objective of the Communications Technology Program is to enable data transmission to and from low Earth orbit, geostationary orbit, and solar and deep space missions. This can be achieved by maintaining an effective, balances effort in basic, applied, and demonstration prototype communications technology through work in theory, experimentation, and components. The program consists of three major research and development discipline areas which are: microwave and millimeter wave tube components; solid state monolithic integrated circuit; and free space laser communications components and devices. The research ranges from basic research in surface physics (to study the mechanisms of surface degradation from under high temperature and voltage operating conditions which impacts cathode tube reliability and lifetime) to generic research on the dynamics of electron beams and circuits (for exploitation in various micro- and millimeter wave tube devices). Work is also performed on advanced III-V semiconductor materials and devices for use in monolithic integrated analog circuits (used in adaptive, programmable phased arrays for microwave antenna feeds and receivers) - on the use of electromagnetic theory in antennas and on technology necessary for eventual employment of lasers for free space communications for future low earth, geostationary, and deep space missions requiring high data rates with corresponding directivity and reliability.

A sigma factor toolbox for orthogonal gene expression in Escherichia coli

PubMed Central

Van Brempt, Maarten; Van Nerom, Katleen; Van Hove, Bob; Maertens, Jo; De Mey, Marjan; Charlier, Daniel

2018-01-01

Abstract Synthetic genetic sensors and circuits enable programmable control over timing and conditions of gene expression and, as a result, are increasingly incorporated into the control of complex and multi-gene pathways. Size and complexity of genetic circuits are growing, but stay limited by a shortage of regulatory parts that can be used without interference. Therefore, orthogonal expression and regulation systems are needed to minimize undesired crosstalk and allow for dynamic control of separate modules. This work presents a set of orthogonal expression systems for use in Escherichia coli based on heterologous sigma factors from Bacillus subtilis that recognize specific promoter sequences. Up to four of the analyzed sigma factors can be combined to function orthogonally between each other and toward the host. Additionally, the toolbox is expanded by creating promoter libraries for three sigma factors without loss of their orthogonal nature. As this set covers a wide range of transcription initiation frequencies, it enables tuning of multiple outputs of the circuit in response to different sensory signals in an orthogonal manner. This sigma factor toolbox constitutes an interesting expansion of the synthetic biology toolbox and may contribute to the assembly of more complex synthetic genetic systems in the future. PMID:29361130

Communications technology

NASA Technical Reports Server (NTRS)

Sokoloski, Martin M.

1988-01-01

The objective of the Communications Technology Program is to enable data transmission to and from low Earth orbit, geostationary orbit, and solar and deep space missions. This can be achieved by maintaining an effective, balances effort in basic, applied, and demonstration prototype communications technology through work in theory, experimentation, and components. The program consists of three major research and development discipline areas which are: microwave and millimeter wave tube components; solid state monolithic integrated circuit; and free space laser communications components and devices. The research ranges from basic research in surface physics (to study the mechanisms of surface degradation from under high temperature and voltage operating conditions which impacts cathode tube reliability and lifetime) to generic research on the dynamics of electron beams and circuits (for exploitation in various micro- and millimeter wave tube devices). Work is also performed on advanced III-V semiconductor materials and devices for use in monolithic integrated analog circuits (used in adaptive, programmable phased arrays for microwave antenna feeds and receivers) - on the use of electromagnetic theory in antennas and on technology necessary for eventual employment of lasers for free space communications for future low earth, geostationary, and deep space missions requiring high data rates with corresponding directivity and reliability.

Le changement comme tradition dans la recherche et la formation a la recherche en biotechnologie et en peripherie Etude de cas en sciences de la sante, sciences naturelles et genie

NASA Astrophysics Data System (ADS)

Bourque, Claude Julie

Le champ de la recherche scientifique et de la formation a la recherche est traverse depuis quelques dizaines d'annees par plusieurs courants et discours associes au changement, mais peu de travaux empiriques permettent de comprendre ce qui change concretement. C'est la contribution originale de cette these au champ de l'education, plus specifiquement a l'etude sociologique de l'enseignement superieur ou sont concentrees les activites liees a la triade thematique du programme doctoral dans lequel elle a ete produite : recherche, formation et pratique. L'enquete-terrain a ete realisee en 2009 et 2010 aupres de 808 repondants affilies a 60 etablissements au Quebec et a produit un vaste materiau de nature mixte (donnees quantitatives et qualitatives). Un portrait de la nebuleuse biotechnologique qui touche les secteurs des sciences de la sante, des sciences naturelles et du genie a ete realise. Ce domaine concerne des dizaines de disciplines et se revele de nature transdisciplinaire, mais les pratiques n'y sont pas davantage marquees par le changement que celles d'autres domaines connexes. Les dynamiques sociales ont fait l'objet d'analyses comparatives dans quatre contextes: le choix des programmes, des objets et des methodes, le financement, la diffusion et la planification de la carriere. Les resultats indiquent que les echanges entre les agents traditionnellement situes au coeur des activites de recherche dominent ces dynamiques dans tous les contextes etudies. L'etude des representations au fondement des pratiques a revele l'existence de trois ecoles de pensee qui coexistent dans le champ scientifique: academique, pragmatique et economiste. Ces ecoles permettent de categoriser les agents en fonction des zones de fractures qui marquent leurs oppositions tout en identifiant ce qu'ils ont en commun. Les representations et les pratiques liees a la formation temoignent d'un habitus plutot homogene, alors que les contradictions semblent plus souvent ancrees dans des luttes universitaires que scientifiques, concentrees sur la negociation du capital scientifique, symbolique et economique en jeu dans la formation doctorale, dans les carrieres auxquelles elle mene, et dans les qualites du titre de Ph.D. Au final, la confusion entre des logiques opposees peut etre reduite en reinterpretant le changement comme tradition du champ scientifique. Mots-cles Sociologie, education, enseignement superieur, science et technologie, biotechnologie, formation doctorale, champ scientifique, reseaux sociaux

DNA nanotechnology from the test tube to the cell.

PubMed

Chen, Yuan-Jyue; Groves, Benjamin; Muscat, Richard A; Seelig, Georg

2015-09-01

The programmability of Watson-Crick base pairing, combined with a decrease in the cost of synthesis, has made DNA a widely used material for the assembly of molecular structures and dynamic molecular devices. Working in cell-free settings, researchers in DNA nanotechnology have been able to scale up system complexity and quantitatively characterize reaction mechanisms to an extent that is infeasible for engineered gene circuits or other cell-based technologies. However, the most intriguing applications of DNA nanotechnology - applications that best take advantage of the small size, biocompatibility and programmability of DNA-based systems - lie at the interface with biology. Here, we review recent progress in the transition of DNA nanotechnology from the test tube to the cell. We highlight key successes in the development of DNA-based imaging probes, prototypes of smart therapeutics and drug delivery systems, and explore the future challenges and opportunities for cellular DNA nanotechnology.

Three Realizations and Comparison of Hardware for Piezoresistive Tactile Sensors

PubMed Central

Vidal-Verdú, Fernando; Oballe-Peinado, Óscar; Sánchez-Durán, José A.; Castellanos-Ramos, Julián; Navas-González, Rafael

2011-01-01

Tactile sensors are basically arrays of force sensors that are intended to emulate the skin in applications such as assistive robotics. Local electronics are usually implemented to reduce errors and interference caused by long wires. Realizations based on standard microcontrollers, Programmable Systems on Chip (PSoCs) and Field Programmable Gate Arrays (FPGAs) have been proposed by the authors for the case of piezoresistive tactile sensors. The solution employing FPGAs is especially relevant since their performance is closer to that of Application Specific Integrated Circuits (ASICs) than that of the other devices. This paper presents an implementation of such an idea for a specific sensor. For the purpose of comparison, the circuitry based on the other devices is also made for the same sensor. This paper discusses the implementation issues, provides details regarding the design of the hardware based on the three devices and compares them. PMID:22163797

Gas Sensors Characterization and Multilayer Perceptron (MLP) Hardware Implementation for Gas Identification Using a Field Programmable Gate Array (FPGA)

PubMed Central

Benrekia, Fayçal; Attari, Mokhtar; Bouhedda, Mounir

2013-01-01

This paper develops a primitive gas recognition system for discriminating between industrial gas species. The system under investigation consists of an array of eight micro-hotplate-based SnO2 thin film gas sensors with different selectivity patterns. The output signals are processed through a signal conditioning and analyzing system. These signals feed a decision-making classifier, which is obtained via a Field Programmable Gate Array (FPGA) with Very High-Speed Integrated Circuit Hardware Description Language. The classifier relies on a multilayer neural network based on a back propagation algorithm with one hidden layer of four neurons and eight neurons at the input and five neurons at the output. The neural network designed after implementation consists of twenty thousand gates. The achieved experimental results seem to show the effectiveness of the proposed classifier, which can discriminate between five industrial gases. PMID:23529119

Hierarchical Address Event Routing for Reconfigurable Large-Scale Neuromorphic Systems.

PubMed

Park, Jongkil; Yu, Theodore; Joshi, Siddharth; Maier, Christoph; Cauwenberghs, Gert

2017-10-01

We present a hierarchical address-event routing (HiAER) architecture for scalable communication of neural and synaptic spike events between neuromorphic processors, implemented with five Xilinx Spartan-6 field-programmable gate arrays and four custom analog neuromophic integrated circuits serving 262k neurons and 262M synapses. The architecture extends the single-bus address-event representation protocol to a hierarchy of multiple nested buses, routing events across increasing scales of spatial distance. The HiAER protocol provides individually programmable axonal delay in addition to strength for each synapse, lending itself toward biologically plausible neural network architectures, and scales across a range of hierarchies suitable for multichip and multiboard systems in reconfigurable large-scale neuromorphic systems. We show approximately linear scaling of net global synaptic event throughput with number of routing nodes in the network, at 3.6×10 7 synaptic events per second per 16k-neuron node in the hierarchy.

Field-Controlled Electrical Switch with Liquid Metal.

PubMed

Wissman, James; Dickey, Michael D; Majidi, Carmel

2017-12-01

When immersed in an electrolyte, droplets of Ga-based liquid metal (LM) alloy can be manipulated in ways not possible with conventional electrocapillarity or electrowetting. This study demonstrates how LM electrochemistry can be exploited to coalesce and separate droplets under moderate voltages of ~1-10 V. This novel approach to droplet interaction can be explained with a theory that accounts for oxidation and reduction as well as fluidic instabilities. Based on simulations and experimental analysis, this study finds that droplet separation is governed by a unique limit-point instability that arises from gradients in bipolar electrochemical reactions that lead to gradients in interfacial tension. The LM coalescence and separation are used to create a field-programmable electrical switch. As with conventional relays or flip-flop latch circuits, the system can transition between bistable (separated or coalesced) states, making it useful for memory storage, logic, and shape-programmable circuitry using entirely liquids instead of solid-state materials.

Field Programmable Gate Array for Implementation of Redundant Advanced Digital Feedback Control

NASA Technical Reports Server (NTRS)

King, K. D.

2003-01-01

The goal of this effort was to develop a digital motor controller using field programmable gate arrays (FPGAs). This is a more rugged approach than a conventional microprocessor digital controller. FPGAs typically have higher radiation (rad) tolerance than both the microprocessor and memory required for a conventional digital controller. Furthermore, FPGAs can typically operate at higher speeds. (While speed is usually not an issue for motor controllers, it can be for other system controllers.) Other than motor power, only a 3.3-V digital power supply was used in the controller; no analog bias supplies were used. Since most of the circuit was implemented in the FPGA, no additional parts were needed other than the power transistors to drive the motor. The benefits that FPGAs provide over conventional designs-lower power and fewer parts-allow for smaller packaging and reduced weight and cost.

Maximizing MST's inductive capability with a Bp programmable power supply

NASA Astrophysics Data System (ADS)

Chapman, B. E.; Holly, D. J.; Jacobson, C. M.; McCollam, K. J.; Morin, J. C.; Sarff, J. S.; Squitieri, A.

2016-10-01

A major goal of the MST program is the advancement of inductive control for the development of both the RFP's fusion potential and, synergistically, the predictive capability of fusion science. This entails programmable power supplies (PPS's) for the Bt and Bp circuits. A Bt PPS is already in place, allowing advanced RFP operation and the production of tokamak plasmas, and a Bp PPS prototype is under construction. To explore some of the new capabilities to be provided by the Bp PPS, the existing Bt PPS has been temporarily connected to the Bp circuit. One key result is new-found access to very low Ip (20 kA) and very low Lundquist number, S (104). At this low S, simulation of RFP plasmas with the MHD code NIMROD is readily achievable, and work toward validation of extended MHD models using NIMROD is underway with direct comparisons to these MST plasmas. The full Bp PPS will also provide higher Ip and S than presently possible, allowing MST to produce plasmas with S spanning as much as five orders of magnitude, a dramatic extension of MST's capability. In these initial tests, the PPS has also increased five-fold MST's Ip flattop duration, to about 100 ms. This, coupled with the recently demonstrated PPS ability to drive large-amplitude sinusoidal oscillations in Ip, will allow tests of extended-duration oscillating field current drive, the goal of which is ac sustainment of a quasi-dc plasma current. Work supported by US DOE.

Circuit weight training and cardiac morphology: a trial with magnetic resonance imaging.

PubMed

Camargo, M D; Stein, R; Ribeiro, J P; Schvartzman, P R; Rizzatti, M O; Schaan, B D

2008-02-01

Aerobic training (AT) and circuit weight training (CWT) improve peak oxygen uptake (VO(2)peak). During CWT the circulatory system is exposed to higher pressure, which could induce left ventricle morphological adaptations, possibly distinct from those derived from aerobic training. To compare the effects of aerobic training and CWT upon morphological and functional cardiac adaptations detected by magnetic resonance imaging. Twenty healthy sedentary individuals were randomly assigned to participate in a 12-week programme of aerobic training (n = 6), CWR (n = 7) or no intervention (n = 7, controls). Training programmes consisted of 36 sessions, 35 min each, 3 times per week, at 70% of maximal heart rate, and CWT included series of resistance exercises performed at 60% of 1 maximal repetition. Cardiopulmonary exercise testing and cardiac magnetic resonance imaging were performed before and after the intervention. There was a similar improvement in VO(2)peak following aerobic training (mean (SD) increment: 12 (4)%) and CWT (12 (4)%), while there was no change in the control group. Aerobic training (12 (6)%) and CWT (16 (5)%) improved strength in the lower limbs, and only CWT resulted in improvement of 13 (4)% in the strength of the upper limbs. However, there were no detectable changes in left ventricular mass, end-diastolic volume, stroke volume or ejection fraction. In previously sedentary individuals, short-term CWT and aerobic training induce similar improvement in functional capacity without any adaptation in cardiac morphology detectable by cardiac magnetic resonance imaging.

An embedded face-classification system for infrared images on an FPGA

NASA Astrophysics Data System (ADS)

Soto, Javier E.; Figueroa, Miguel

2014-10-01

We present a face-classification architecture for long-wave infrared (IR) images implemented on a Field Programmable Gate Array (FPGA). The circuit is fast, compact and low power, can recognize faces in real time and be embedded in a larger image-processing and computer vision system operating locally on an IR camera. The algorithm uses Local Binary Patterns (LBP) to perform feature extraction on each IR image. First, each pixel in the image is represented as an LBP pattern that encodes the similarity between the pixel and its neighbors. Uniform LBP codes are then used to reduce the number of patterns to 59 while preserving more than 90% of the information contained in the original LBP representation. Then, the image is divided into 64 non-overlapping regions, and each region is represented as a 59-bin histogram of patterns. Finally, the algorithm concatenates all 64 regions to create a 3,776-bin spatially enhanced histogram. We reduce the dimensionality of this histogram using Linear Discriminant Analysis (LDA), which improves clustering and enables us to store an entire database of 53 subjects on-chip. During classification, the circuit applies LBP and LDA to each incoming IR image in real time, and compares the resulting feature vector to each pattern stored in the local database using the Manhattan distance. We implemented the circuit on a Xilinx Artix-7 XC7A100T FPGA and tested it with the UCHThermalFace database, which consists of 28 81 x 150-pixel images of 53 subjects in indoor and outdoor conditions. The circuit achieves a 98.6% hit ratio, trained with 16 images and tested with 12 images of each subject in the database. Using a 100 MHz clock, the circuit classifies 8,230 images per second, and consumes only 309mW.

Estimating the circuit delay of FPGA with a transfer learning method

NASA Astrophysics Data System (ADS)

Cui, Xiuhai; Liu, Datong; Peng, Yu; Peng, Xiyuan

2017-10-01

With the increase of FPGA (Field Programmable Gate Array, FPGA) functionality, FPGA has become an on-chip system platform. Due to increase the complexity of FPGA, estimating the delay of FPGA is a very challenge work. To solve the problems, we propose a transfer learning estimation delay (TLED) method to simplify the delay estimation of different speed grade FPGA. In fact, the same style different speed grade FPGA comes from the same process and layout. The delay has some correlation among different speed grade FPGA. Therefore, one kind of speed grade FPGA is chosen as a basic training sample in this paper. Other training samples of different speed grade can get from the basic training samples through of transfer learning. At the same time, we also select a few target FPGA samples as training samples. A general predictive model is trained by these samples. Thus one kind of estimation model is used to estimate different speed grade FPGA circuit delay. The framework of TRED includes three phases: 1) Building a basic circuit delay library which includes multipliers, adders, shifters, and so on. These circuits are used to train and build the predictive model. 2) By contrasting experiments among different algorithms, the forest random algorithm is selected to train predictive model. 3) The target circuit delay is predicted by the predictive model. The Artix-7, Kintex-7, and Virtex-7 are selected to do experiments. Each of them includes -1, -2, -2l, and -3 different speed grade. The experiments show the delay estimation accuracy score is more than 92% with the TLED method. This result shows that the TLED method is a feasible delay assessment method, especially in the high-level synthesis stage of FPGA tool, which is an efficient and effective delay assessment method.

Controlled initialization of superconducting π-phaseshifters and possible applications

NASA Astrophysics Data System (ADS)

Mielke, Olaf; Ortlepp, Thomas; Kunert, Juergen; Meyer, Hans-Georg; Toepfer, Hannes

2010-05-01

The rapid single-flux quantum electronics (RSFQ) is a superconducting, naturally digital circuit family which is currently close to being commercially applied. RSFQ is outstanding because of its very low switching energy resulting in very low power consumption. This advantage causes, however, a significant influence of thermal noise. For industrial applications, a certain noise immunity is required which is still a challenge, especially for circuits of higher complexity. Integrating phase-shifting elements is a new concept for further improvements concerning stability against the influence of thermal noise. We have already shown that the implementation of phase-shifting elements significantly reduces the influence of thermal noise on circuit behavior by experimentally analyzing the bit-error rate (Mielke et al 2009 IEEE Trans. Appl. Supercond. 19 621-5). Concepts which are easily implementable in standard niobium technology are especially promising. The π-phaseshifter consists of a superconducting loop which is able to store a single flux quantum. The loop current related to the stored flux creates a well-defined phase shift. To achieve the correct functionality of complex circuits it is essential to store exactly one flux quantum in each π-phaseshifter during the cooling down of the chip. Thus, for studying the feasibility of this new approach, the initialization reliability of the π-phaseshifter needs to be verified. We present an experimental investigation of this reliability to obtain a general assessment for the application of the π-phaseshifter in niobium technology. Furthermore, we compare the configuration shielded by a solid ground plane with a configuration with a ground-plane hole below the π-phaseshifter. Justified by the experimental results we suggest programmable RSFQ circuits based on π-phaseshifters. The characteristics of these devices can be influenced by a controlled initialization of the π-phaseshifter. The fabrication was performed by FLUXONICS Foundry.

Delay grid multiplexing: simple time-based multiplexing and readout method for silicon photomultipliers

NASA Astrophysics Data System (ADS)

Won, Jun Yeon; Ko, Guen Bae; Lee, Jae Sung

2016-10-01

In this paper, we propose a fully time-based multiplexing and readout method that uses the principle of the global positioning system. Time-based multiplexing allows simplifying the multiplexing circuits where the only innate traces that connect the signal pins of the silicon photomultiplier (SiPM) channels to the readout channels are used as the multiplexing circuit. Every SiPM channel is connected to the delay grid that consists of the traces on a printed circuit board, and the inherent transit times from each SiPM channel to the readout channels encode the position information uniquely. Thus, the position of each SiPM can be identified using the time difference of arrival (TDOA) measurements. The proposed multiplexing can also allow simplification of the readout circuit using the time-to-digital converter (TDC) implemented in a field-programmable gate array (FPGA), where the time-over-threshold (ToT) is used to extract the energy information after multiplexing. In order to verify the proposed multiplexing method, we built a positron emission tomography (PET) detector that consisted of an array of 4  ×  4 LGSO crystals, each with a dimension of 3  ×  3  ×  20 mm3, and one- to-one coupled SiPM channels. We first employed the waveform sampler as an initial study, and then replaced the waveform sampler with an FPGA-TDC to further simplify the readout circuits. The 16 crystals were clearly resolved using only the time information obtained from the four readout channels. The coincidence resolving times (CRTs) were 382 and 406 ps FWHM when using the waveform sampler and the FPGA-TDC, respectively. The proposed simple multiplexing and readout methods can be useful for time-of-flight (TOF) PET scanners.

The research of PSD location method in micro laser welding fields

NASA Astrophysics Data System (ADS)

Zhang, Qiue; Zhang, Rong; Dong, Hua

2010-11-01

In the field of micro laser welding, besides the special requirement in the parameter of lasers, the locating in welding points accurately is very important. The article adopt position sensitive detector (PSD) as hard core, combine optic system, electric circuits and PC and software processing, confirm the location of welding points. The signal detection circuits adopt the special integrate circuit H-2476 to process weak signal. It is an integrated circuit for high-speed, high-sensitivity optical range finding, which has stronger noiseproof feature, combine digital filter arithmetic, carry out repair the any non-ideal factors, increasing the measure precision. The amplifier adopt programmable amplifier LTC6915. The system adapt two dimension stepping motor drive the workbench, computer and corresponding software processing, make sure the location of spot weld. According to different workpieces to design the clamps. The system on-line detect PSD 's output signal in the moving processing. At the workbench moves in the X direction, the filaments offset is detected dynamic. Analyze the X axes moving sampling signal direction could be estimate the Y axes moving direction, and regulate the Y axes moving values. The workbench driver adopt A3979, it is a stepping motor driver with insert transducer and operate easily. It adapts the requirement of location in micro laser welding fields, real-time control to adjust by computer. It can be content up 20 μm's laser micro welding requirement on the whole. Using laser powder cladding technology achieve inter-penetration welding of high quality and reliability.

Efficient G(sup 4)FET-Based Logic Circuits

NASA Technical Reports Server (NTRS)

Vatan, Farrokh

2008-01-01

A total of 81 optimal logic circuits based on four-gate field-effect transistors (G(sup 4)4FETs) have been designed to implement all Boolean functions of up to three variables. The purpose of this development was to lend credence to the expectation that logic circuits based on G(sup 4)FETs could be more efficient (in the sense that they could contain fewer transistors), relative to functionally equivalent logic circuits based on conventional transistors. A G(sup 4)FET a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G(sup 4)FET can also be regarded as a single device having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of a silicon-on-insulator substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. One such option is to design a G(sup 4)FET to function as a three-input NOT-majority gate, which has been shown to be a universal and programmable logic gate. Optimal NOT-majority-gate, G(sup 4)FET-based logic-circuit designs were obtained in a comparative study that also included formulation of functionally equivalent logic circuits based on NOR and NAND gates implemented by use of conventional transistors. In the study, the problem of finding the optimal design for each logic function and each transistor type was solved as an integer-programming optimization problem. Considering all 81 non-equivalent Boolean functions included in the study, it was found that in 63% of the cases, fewer logic gates (and, hence, fewer transistors) would be needed in the G(sup 4)FET-based implementations.

A High-Voltage SOI CMOS Exciter Chip for a Programmable Fluidic Processor System.

PubMed

Current, K W; Yuk, K; McConaghy, C; Gascoyne, P R C; Schwartz, J A; Vykoukal, J V; Andrews, C

2007-06-01

A high-voltage (HV) integrated circuit has been demonstrated to transport fluidic droplet samples on programmable paths across the array of driving electrodes on its hydrophobically coated surface. This exciter chip is the engine for dielectrophoresis (DEP)-based micro-fluidic lab-on-a-chip systems, creating field excitations that inject and move fluidic droplets onto and about the manipulation surface. The architecture of this chip is expandable to arrays of N X N identical HV electrode driver circuits and electrodes. The exciter chip is programmable in several senses. The routes of multiple droplets may be set arbitrarily within the bounds of the electrode array. The electrode excitation waveform voltage amplitude, phase, and frequency may be adjusted based on the system configuration and the signal required to manipulate a particular fluid droplet composition. The voltage amplitude of the electrode excitation waveform can be set from the minimum logic level up to the maximum limit of the breakdown voltage of the fabrication technology. The frequency of the electrode excitation waveform can also be set independently of its voltage, up to a maximum depending upon the type of droplets that must be driven. The exciter chip can be coated and its oxide surface used as the droplet manipulation surface or it can be used with a top-mounted, enclosed fluidic chamber consisting of a variety of materials. The HV capability of the exciter chip allows the generated DEP forces to penetrate into the enclosed chamber region and an adjustable voltage amplitude can accommodate a variety of chamber floor thicknesses. This demonstration exciter chip has a 32 x 32 array of nominally 100 V electrode drivers that are individually programmable at each time point in the procedure to either of two phases: 0deg and 180deg with respect to the reference clock. For this demonstration chip, while operating the electrodes with a 100-V peak-to-peak periodic waveform, the maximum HV electrode waveform frequency is about 200 Hz; and standard 5-V CMOS logic data communication rate is variable up to 250 kHz. This HV demonstration chip is fabricated in a 130-V 1.0-mum SOI CMOS fabrication technology, dissipates a maximum of 1.87 W, and is about 10.4 mm x 8.2 mm.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pierson, L.G.; Witzke, E.L.

This effort studied the integration of innovative methods of key management crypto synchronization, and key agility while scaling encryption speed. Viability of these methods for encryption of ATM cell payloads at the SONET OC- 192 data rate (10 Gb/s), and for operation at OC-48 rates (2.5 Gb/s) was shown. An SNL-Developed pipelined DES design was adapted for the encryption of ATM cells. A proof-of-principle prototype circuit board containing 11 Electronically Programmable Logic Devices (each holding the equivalent of 100,000 gates) was designed, built, and used to prototype a high speed encryptor.

Research of vibration controlling based on programmable logic controller for electrostatic precipitator

NASA Astrophysics Data System (ADS)

Zhang, Zisheng; Li, Yanhu; Li, Jiaojiao; Liu, Zhiqiang; Li, Qing

2013-03-01

In order to improve the reliability, stability and automation of electrostatic precipitator, circuits of vibration motor for ESP and vibration control ladder diagram program are investigated using Schneider PLC with high performance and programming software of Twidosoft. Operational results show that after adopting PLC, vibration motor can run automatically; compared with traditional control system of vibration based on single-chip microcomputer, it has higher reliability, better stability and higher dust removal rate, when dust emission concentrations <= 50 mg m-3, providing a new method for vibration controlling of ESP.

Improved On-Chip Measurement of Delay in an FPGA or ASIC

NASA Technical Reports Server (NTRS)

Chen, Yuan; Burke, Gary; Sheldon, Douglas

2007-01-01

An improved design has been devised for on-chip-circuitry for measuring the delay through a chain of combinational logic elements in a field-programmable gate array (FPGA) or application-specific integrated circuit (ASIC). In the improved design, the delay chain does not include input and output buffers and is not configured as an oscillator. Instead, the delay chain is made part of the signal chain of an on-chip pulse generator. The duration of the pulse is measured on-chip and taken to equal the delay.

A microprogrammable radar controller

NASA Technical Reports Server (NTRS)

Law, D. C.

1986-01-01

The Wave Propagation Lab. has completed the design and construction of a microprogrammable radar controller for atmospheric wind profiling. Unlike some radar controllers using state machines or hardwired logic for radar timing, this design is a high speed programmable sequencer with signal processing resources. A block diagram of the device is shown. The device is a single 8 1/2 inch by 10 1/2 inch printed circuit board and consists of three main subsections: (1) the host computer interface; (2) the microprogram sequencer; and (3) the signal processing circuitry. Each of these subsections are described in detail.

Development of a space-systems network testbed

NASA Technical Reports Server (NTRS)

Lala, Jaynarayan; Alger, Linda; Adams, Stuart; Burkhardt, Laura; Nagle, Gail; Murray, Nicholas

1988-01-01

This paper describes a communications network testbed which has been designed to allow the development of architectures and algorithms that meet the functional requirements of future NASA communication systems. The central hardware components of the Network Testbed are programmable circuit switching communication nodes which can be adapted by software or firmware changes to customize the testbed to particular architectures and algorithms. Fault detection, isolation, and reconfiguration has been implemented in the Network with a hybrid approach which utilizes features of both centralized and distributed techniques to provide efficient handling of faults within the Network.

Electronically controllable spoof localized surface plasmons

NASA Astrophysics Data System (ADS)

Zhou, Yong Jin; Zhang, Chao; Yang, Liu; Xun Xiao, Qian

2017-10-01

Electronically controllable multipolar spoof localized surface plasmons (LSPs) are experimentally demonstrated in the microwave frequencies. It has been shown that half integer order LSPs modes exist on the corrugated ring loaded with a slit, which actually arise from the Fabry-Perot-like resonances. By mounting active components across the slit in the corrugated rings, electronic switchability and tunability of spoof LSPs modes have been accomplished. Both simulated and measured results demonstrate efficient dynamic control of the spoof LSPs. These elements may form the basis of highly integrated programmable plasmonic circuits in microwave and terahertz regimes.

Challenges Regarding IP Core Functional Reliability

NASA Technical Reports Server (NTRS)

Berg, Melanie D.; LaBel, Kenneth A.

2017-01-01

For many years, intellectual property (IP) cores have been incorporated into field programmable gate array (FPGA) and application specific integrated circuit (ASIC) design flows. However, the usage of large complex IP cores were limited within products that required a high level of reliability. This is no longer the case. IP core insertion has become mainstream including their use in highly reliable products. Due to limited visibility and control, challenges exist when using IP cores and subsequently compromise product reliability. We discuss challenges and suggest potential solutions to critical application IP insertion.

Strategies facilitant les tests en pre-certification pour la robustesse a l'egard des radiations =

NASA Astrophysics Data System (ADS)

Souari, Anis

Les effets des radiations cosmiques sur l'electronique embarquee preoccupent depuis. quelques decennies les chercheurs interesses par la robustesse des circuits integres. Plusieurs. recherches ont ete menees dans cette direction, principalement pour les applications spatiales. ou l’environnement de leur deploiement est hostile. En effet, ces environnements sont denses. en termes de particules qui, lorsqu’elles interagissent avec les circuits integres, peuvent. mener a leur dysfonctionnement, voir meme a leur destruction. De plus, les effets des. radiations s’accentuent pour les nouvelles generations des circuits integres ou la diminution. de la taille des transistors et l’augmentation de la complexite de ces circuits augmentent la. probabilite d’apparition des anomalies et par consequence la croissance des besoins de test. L’expansion de l’electronique grand public (commercial off-the-shelf, COTS) et l’adoption. de ces composants pour des applications critiques comme les applications avioniques et. spatiales incitent egalement les chercheurs a doubler les efforts de verification de la fiabilite. de ces circuits. Les COTS, malgre leurs meilleures caracteristiques en comparaison avec les. circuits durcis tolerants aux radiations qui sont couteux et en retard en termes de technologie. utilisee, sont vulnerables aux radiations. Afin d’ameliorer la fiabilite de ces circuits, une evaluation de leur vulnerabilite dans les. differents niveaux d’abstraction du flot de conception est recommandee. Ceci aide les. concepteurs a prendre les mesures de mitigation necessaires sur le design au niveau. d’abstraction en question. Enfin, afin de satisfaire les exigences de tolerance aux pannes, des. tests tres couteux de certification, obtenus a l’aide de bombardement de particules (protons, neutrons, etc.), sont necessaires. Dans cette these, nous nous interessons principalement a definir une strategie de precertification. permettant d’evaluer d’une facon realiste la sensibilite des circuits integres face. aux effets des radiations afin d’eviter d’envoyer des circuits non robustes a la phase tres. couteuse de la certification. Les circuits cibles par nos travaux sont les circuits integres. programmables par l’usager (FPGA) a base de memoire SRAM et le type de pannes ciblees, causees par les radiations, est les SEU (single event upset) consistant a un basculement de. l’etat logique d’un element de memoire a son complementaire. En effet, les FPGA a base de. memoire SRAM sont de plus en plus demandes par la communaute de l’aerospatial grace a. leurs caracteristiques de prototypage rapide et de reconfiguration sur site mais ils sont. vulnerables face aux radiations ou les SEU sont les pannes les plus frequentes dans les. elements de memoire de type SRAM. Nous proposons une nouvelle approche d’injection de. pannes par emulation permettant de mimer les effets des radiations sur la memoire de. configuration des FPGA et de generer des resultats les plus fideles possibles des resultats des. tests de certification. Cette approche est basee sur la consideration de la difference de. sensibilite des elements de memoire de configuration lorsqu’ils sont a l’etat '1' et a l’etat '0', observee sous des tests acceleres sous faisceaux de protons au renomme laboratoire. TRIUMF, dans la procedure de generation des sequences de test dans le but de mimer la. distribution des pannes dans la memoire de configuration. Les resultats des experimentations. de validation montrent que la strategie proposee est efficace et genere des resultats realistes. Ces resultats revelent que ne pas considerer la difference de sensibilite peut mener a une. sous-estimation de la sensibilite des circuits face aux radiations. Dans la meme optique d’optimisation de la procedure d’injection des pannes par emulation, a. savoir le test de pre-certification, nous proposons une methodologie permettant de maximiser. la detection des bits critiques (bits provoquant une defaillance fonctionnelle s’ils changent. d’etat) pour un nombre bien determine de SEU (qui est le modele de pannes adopte) ou de. maximiser la precision de l’estimation de nombre des bits critiques. Pour ce faire, une. classification des bits de configuration en differents ensembles est tout d’abord mise en. oeuvre, selon leur contenu, les ressources qu’ils configurent et leur criticite. Ensuite, une. evaluation de la sensibilite de chaque ensemble est accomplie. Enfin, la priorisation. d’injection des pannes dans les ensembles les plus sensibles est recommandee. Plusieurs. scenarios d’optimisation d’injection des pannes sont proposes et les resultats sont compares. avec ceux donnes par la methode conventionnelle d’injection aleatoire des pannes. La. methodologie d’optimisation proposee assure une amelioration de plus de deux ordres de. grandeur. Une derniere approche facilitant l’evaluation de la sensibilite des bits configurant les LUT. (look up table) de FPGA, les plus petites entites configurables du FPGA permettant. d’implementer des fonctions combinatoires, utilises par un design est presentee. Elle permet. l’identification facile et sans cout en termes d’utilisation du materiel ou d’outils externes des. bits des LUT. L’approche proposee est simple et efficace, offrant une couverture de pannes. de 100 % et applicable aux nouvelles generations des FPGA de Xilinx. Les approches proposees contribuent a repondre aux exigences du cahier des charges de cette. these et a achever les objectifs definis. Le realisme et la maximisation de l’estimation de la. vulnerabilite des circuits sous test offerts par les nouvelles approches assurent le. developpement d’une strategie de test en pre-certification efficace. En effet, la premiere. approche d’injection de pannes considerant la difference de sensibilite relative des elements. de memoire selon leur contenu genere des resultats donnant une erreur relative atteignant. 3.1 % quand compares aux resultats obtenus a TRIUMF alors que l’erreur relative donnee. par la comparaison des resultats d’une injection conventionnelle aleatoire de pannes avec. ceux de TRIUMF peut atteindre la valeur de 75 %. De plus, l’application de cette approche a. des circuits plus conventionnels montre que 2.3 fois plus d’erreurs sont detectees en. comparaison avec l’injection aleatoire des pannes. Ceci suggere que ne pas considerer la. difference de sensibilite relative dans la procedure d’emulation peut mener a une sousestimation. de la sensibilite du design face aux radiations. Les resultats de la deuxieme. approche proposee ont ete aussi compares aux resultats d’une injection aleatoire de pannes. L’approche proposee, maximisant le nombre des bits critiques inverses, permet d’atteindre. un facteur d’acceleration de 108 de la procedure d’injection des pannes en comparaison a. l’approche aleatoire. Elle permet aussi de minimiser l’erreur d’estimation du nombre des bits. critiques pour atteindre une valeur de ±1.1 % calculee pour un intervalle de confiance de. 95 % tandis que la valeur d’erreur d’estimation des bits critiques generee par l’approche. aleatoire d’injection des pannes pour le meme intervalle de confiance peut atteindre ±8.6 %. Enfin, la derniere approche proposee d’injection de pannes dans les LUT se distingue des. autres approches disponibles dans la litterature par sa simplicite tout en assurant une. couverture maximale de pannes de 100 %. En effet, l’approche proposee est independante. des outils externes permettant d’identifier les bits configurant les LUT qui sont obsoletes ou. ne supportent pas les nouvelles generations des FPGA. Elle agit directement sur les fichiers. generes par l’outil de synthese adopte.

Board Saver for Use with Developmental FPGAs

NASA Technical Reports Server (NTRS)

Berkun, Andrew

2009-01-01

A device denoted a board saver has been developed as a means of reducing wear and tear of a printed-circuit board onto which an antifuse field programmable gate array (FPGA) is to be eventually soldered permanently after a number of design iterations. The need for the board saver or a similar device arises because (1) antifuse-FPGA design iterations are common and (2) repeated soldering and unsoldering of FPGAs on the printed-circuit board to accommodate design iterations can wear out the printed-circuit board. The board saver is basically a solderable/unsolderable FPGA receptacle that is installed temporarily on the printed-circuit board. The board saver is, more specifically, a smaller, square-ring-shaped, printed-circuit board (see figure) that contains half via holes one for each contact pad along its periphery. As initially fabricated, the board saver is a wider ring containing full via holes, but then it is milled along its outer edges, cutting the via holes in half and laterally exposing their interiors. The board saver is positioned in registration with the designated FPGA footprint and each via hole is soldered to the outer portion of the corresponding FPGA contact pad on the first-mentioned printed-circuit board. The via-hole/contact joints can be inspected visually and can be easily unsoldered later. The square hole in the middle of the board saver is sized to accommodate the FPGA, and the thickness of the board saver is the same as that of the FPGA. Hence, when a non-final FPGA is placed in the square hole, the combination of the non-final FPGA and the board saver occupy no more area and thickness than would a final FPGA soldered directly into its designated position on the first-mentioned circuit board. The contact leads of a non-final FPGA are not bent and are soldered, at the top of the board saver, to the corresponding via holes. A non-final FPGA can readily be unsoldered from the board saver and replaced by another one. Once the final FPGA design has been determined, the board saver can be unsoldered from the contact pads on the first-mentioned printed-circuit board and replaced by the final FPGA.

Intelligent layered nanoflare: "lab-on-a-nanoparticle" for multiple DNA logic gate operations and efficient intracellular delivery.

PubMed

Yang, Bin; Zhang, Xiao-Bing; Kang, Li-Ping; Huang, Zhi-Mei; Shen, Guo-Li; Yu, Ru-Qin; Tan, Weihong

2014-08-07

DNA strand displacement cascades have been engineered to construct various fascinating DNA circuits. However, biological applications are limited by the insufficient cellular internalization of naked DNA structures, as well as the separated multicomponent feature. In this work, these problems are addressed by the development of a novel DNA nanodevice, termed intelligent layered nanoflare, which integrates DNA computing at the nanoscale, via the self-assembly of DNA flares on a single gold nanoparticle. As a "lab-on-a-nanoparticle", the intelligent layered nanoflare could be engineered to perform a variety of Boolean logic gate operations, including three basic logic gates, one three-input AND gate, and two complex logic operations, in a digital non-leaky way. In addition, the layered nanoflare can serve as a programmable strategy to sequentially tune the size of nanoparticles, as well as a new fingerprint spectrum technique for intelligent multiplex biosensing. More importantly, the nanoflare developed here can also act as a single entity for intracellular DNA logic gate delivery, without the need of commercial transfection agents or other auxiliary carriers. By incorporating DNA circuits on nanoparticles, the presented layered nanoflare will broaden the applications of DNA circuits in biological systems, and facilitate the development of DNA nanotechnology.

A real-time spectrum acquisition system design based on quantum dots-quantum well detector

NASA Astrophysics Data System (ADS)

Zhang, S. H.; Guo, F. M.

2016-01-01

In this paper, we studied the structure characteristics of quantum dots-quantum well photodetector with response wavelength range from 400 nm to 1000 nm. It has the characteristics of high sensitivity, low dark current and the high conductance gain. According to the properties of the quantum dots-quantum well photodetectors, we designed a new type of capacitive transimpedence amplifier (CTIA) readout circuit structure with the advantages of adjustable gain, wide bandwidth and high driving ability. We have implemented the chip packaging between CTIA-CDS structure readout circuit and quantum dots detector and tested the readout response characteristics. According to the timing signals requirements of our readout circuit, we designed a real-time spectral data acquisition system based on FPGA and ARM. Parallel processing mode of programmable devices makes the system has high sensitivity and high transmission rate. In addition, we realized blind pixel compensation and smoothing filter algorithm processing to the real time spectrum data by using C++. Through the fluorescence spectrum measurement of carbon quantum dots and the signal acquisition system and computer software system to realize the collection of the spectrum signal processing and analysis, we verified the excellent characteristics of detector. It meets the design requirements of quantum dot spectrum acquisition system with the characteristics of short integration time, real-time and portability.

Memristor-based cellular nonlinear/neural network: design, analysis, and applications.

PubMed

Duan, Shukai; Hu, Xiaofang; Dong, Zhekang; Wang, Lidan; Mazumder, Pinaki

2015-06-01

Cellular nonlinear/neural network (CNN) has been recognized as a powerful massively parallel architecture capable of solving complex engineering problems by performing trillions of analog operations per second. The memristor was theoretically predicted in the late seventies, but it garnered nascent research interest due to the recent much-acclaimed discovery of nanocrossbar memories by engineers at the Hewlett-Packard Laboratory. The memristor is expected to be co-integrated with nanoscale CMOS technology to revolutionize conventional von Neumann as well as neuromorphic computing. In this paper, a compact CNN model based on memristors is presented along with its performance analysis and applications. In the new CNN design, the memristor bridge circuit acts as the synaptic circuit element and substitutes the complex multiplication circuit used in traditional CNN architectures. In addition, the negative differential resistance and nonlinear current-voltage characteristics of the memristor have been leveraged to replace the linear resistor in conventional CNNs. The proposed CNN design has several merits, for example, high density, nonvolatility, and programmability of synaptic weights. The proposed memristor-based CNN design operations for implementing several image processing functions are illustrated through simulation and contrasted with conventional CNNs. Monte-Carlo simulation has been used to demonstrate the behavior of the proposed CNN due to the variations in memristor synaptic weights.

Majority logic gate for 3D magnetic computing.

PubMed

Eichwald, Irina; Breitkreutz, Stephan; Ziemys, Grazvydas; Csaba, György; Porod, Wolfgang; Becherer, Markus

2014-08-22

For decades now, microelectronic circuits have been exclusively built from transistors. An alternative way is to use nano-scaled magnets for the realization of digital circuits. This technology, known as nanomagnetic logic (NML), may offer significant improvements in terms of power consumption and integration densities. Further advantages of NML are: non-volatility, radiation hardness, and operation at room temperature. Recent research focuses on the three-dimensional (3D) integration of nanomagnets. Here we show, for the first time, a 3D programmable magnetic logic gate. Its computing operation is based on physically field-interacting nanometer-scaled magnets arranged in a 3D manner. The magnets possess a bistable magnetization state representing the Boolean logic states '0' and '1.' Magneto-optical and magnetic force microscopy measurements prove the correct operation of the gate over many computing cycles. Furthermore, micromagnetic simulations confirm the correct functionality of the gate even for a size in the nanometer-domain. The presented device demonstrates the potential of NML for three-dimensional digital computing, enabling the highest integration densities.

Programmable chemical controllers made from DNA.

PubMed

Chen, Yuan-Jyue; Dalchau, Neil; Srinivas, Niranjan; Phillips, Andrew; Cardelli, Luca; Soloveichik, David; Seelig, Georg

2013-10-01

Biological organisms use complex molecular networks to navigate their environment and regulate their internal state. The development of synthetic systems with similar capabilities could lead to applications such as smart therapeutics or fabrication methods based on self-organization. To achieve this, molecular control circuits need to be engineered to perform integrated sensing, computation and actuation. Here we report a DNA-based technology for implementing the computational core of such controllers. We use the formalism of chemical reaction networks as a 'programming language' and our DNA architecture can, in principle, implement any behaviour that can be mathematically expressed as such. Unlike logic circuits, our formulation naturally allows complex signal processing of intrinsically analogue biological and chemical inputs. Controller components can be derived from biologically synthesized (plasmid) DNA, which reduces errors associated with chemically synthesized DNA. We implement several building-block reaction types and then combine them into a network that realizes, at the molecular level, an algorithm used in distributed control systems for achieving consensus between multiple agents.

Self-adjusting threshold mechanism for pixel detectors

NASA Astrophysics Data System (ADS)

Heim, Timon; Garcia-Sciveres, Maurice

2017-09-01

Readout chips of hybrid pixel detectors use a low power amplifier and threshold discrimination to process charge deposited in semiconductor sensors. Due to transistor mismatch each pixel circuit needs to be calibrated individually to achieve response uniformity. Traditionally this is addressed by programmable threshold trimming in each pixel, but requires robustness against radiation effects, temperature, and time. In this paper a self-adjusting threshold mechanism is presented, which corrects the threshold for both spatial inequality and time variation and maintains a constant response. It exploits the electrical noise as relative measure for the threshold and automatically adjust the threshold of each pixel to always achieve a uniform frequency of noise hits. A digital implementation of the method in the form of an up/down counter and combinatorial logic filter is presented. The behavior of this circuit has been simulated to evaluate its performance and compare it to traditional calibration results. The simulation results show that this mechanism can perform equally well, but eliminates instability over time and is immune to single event upsets.

Programmable chemical controllers made from DNA

NASA Astrophysics Data System (ADS)

Chen, Yuan-Jyue; Dalchau, Neil; Srinivas, Niranjan; Phillips, Andrew; Cardelli, Luca; Soloveichik, David; Seelig, Georg

2013-10-01

Biological organisms use complex molecular networks to navigate their environment and regulate their internal state. The development of synthetic systems with similar capabilities could lead to applications such as smart therapeutics or fabrication methods based on self-organization. To achieve this, molecular control circuits need to be engineered to perform integrated sensing, computation and actuation. Here we report a DNA-based technology for implementing the computational core of such controllers. We use the formalism of chemical reaction networks as a 'programming language' and our DNA architecture can, in principle, implement any behaviour that can be mathematically expressed as such. Unlike logic circuits, our formulation naturally allows complex signal processing of intrinsically analogue biological and chemical inputs. Controller components can be derived from biologically synthesized (plasmid) DNA, which reduces errors associated with chemically synthesized DNA. We implement several building-block reaction types and then combine them into a network that realizes, at the molecular level, an algorithm used in distributed control systems for achieving consensus between multiple agents.

Design and Fabrication of Automatic Glass Cutting Machine

NASA Astrophysics Data System (ADS)

Veena, T. R.; Kadadevaramath, R. S.; Nagaraj, P. M.; Madhusudhan, S. V.

2016-09-01

This paper deals with the design and fabrication of the automatic glass or mirror cutting machine. In order to increase the accuracy of cut and production rate; and decrease the production time and accidents caused due to manual cutting of mirror or glass, this project aims at development of an automatic machine which uses a programmable logic controller (PLC) for controlling the movement of the conveyer and also to control the pneumatic circuit. In this machine, the work of the operator is to load and unload the mirror. The cutter used in this machine is carbide wheel with its cutting edge ground to a V-shaped profile. The PLC controls the pneumatic cylinder and intern actuates the cutter along the glass, a fracture layer is formed causing a mark to be formed below the fracture layer and a crack to be formed below the rib mark. The machine elements are designed using CATIA V5R20 and pneumatic circuit are designed using FESTO FLUID SIM software.

Programmable chemical controllers made from DNA

PubMed Central

Chen, Yuan-Jyue; Dalchau, Neil; Srinivas, Niranjan; Phillips, Andrew; Cardelli, Luca; Soloveichik, David; Seelig, Georg

2014-01-01

Biological organisms use complex molecular networks to navigate their environment and regulate their internal state. The development of synthetic systems with similar capabilities could lead to applications such as smart therapeutics or fabrication methods based on self-organization. To achieve this, molecular control circuits need to be engineered to perform integrated sensing, computation and actuation. Here we report a DNA-based technology for implementing the computational core of such controllers. We use the formalism of chemical reaction networks as a 'programming language', and our DNA architecture can, in principle, implement any behaviour that can be mathematically expressed as such. Unlike logic circuits, our formulation naturally allows complex signal processing of intrinsically analogue biological and chemical inputs. Controller components can be derived from biologically synthesized (plasmid) DNA, which reduces errors associated with chemically synthesized DNA. We implement several building-block reaction types and then combine them into a network that realizes, at the molecular level, an algorithm used in distributed control systems for achieving consensus between multiple agents. PMID:24077029

Memory switches based on metal oxide thin films

NASA Technical Reports Server (NTRS)

Ramesham, Rajeshuni (Inventor); Thakoor, Anilkumar P. (Inventor); Lambe, John J. (Inventor)

1990-01-01

MnO.sub.2-x thin films (12) exhibit irreversible memory switching (28) with an OFF/ON resistance ratio of at least about 10.sup.3 and the tailorability of ON state (20) resistance. Such films are potentially extremely useful as a connection element in a variety of microelectronic circuits and arrays (24). Such films provide a pre-tailored, finite, non-volatile resistive element at a desired place in an electric circuit, which can be electrically turned OFF (22) or disconnected as desired, by application of an electrical pulse. Microswitch structures (10) constitute the thin film element, contacted by a pair of separate electrodes (16a, 16b) and have a finite, pre-selected ON resistance which is ideally suited, for example, as a programmable binary synaptic connection for electronic implementation of neural network architectures. The MnO.sub.2-x microswitch is non-volatile, patternable, insensitive to ultraviolet light, and adherent to a variety of insulating substrates (14), such as glass and silicon dioxide-coated silicon substrates.

Software-Reconfigurable Processors for Spacecraft

NASA Technical Reports Server (NTRS)

Farrington, Allen; Gray, Andrew; Bell, Bryan; Stanton, Valerie; Chong, Yong; Peters, Kenneth; Lee, Clement; Srinivasan, Jeffrey

2005-01-01

A report presents an overview of an architecture for a software-reconfigurable network data processor for a spacecraft engaged in scientific exploration. When executed on suitable electronic hardware, the software performs the functions of a physical layer (in effect, acts as a software radio in that it performs modulation, demodulation, pulse-shaping, error correction, coding, and decoding), a data-link layer, a network layer, a transport layer, and application-layer processing of scientific data. The software-reconfigurable network processor is undergoing development to enable rapid prototyping and rapid implementation of communication, navigation, and scientific signal-processing functions; to provide a long-lived communication infrastructure; and to provide greatly improved scientific-instrumentation and scientific-data-processing functions by enabling science-driven in-flight reconfiguration of computing resources devoted to these functions. This development is an extension of terrestrial radio and network developments (e.g., in the cellular-telephone industry) implemented in software running on such hardware as field-programmable gate arrays, digital signal processors, traditional digital circuits, and mixed-signal application-specific integrated circuits (ASICs).

A pipelined architecture for real time correction of non-uniformity in infrared focal plane arrays imaging system using multiprocessors

NASA Astrophysics Data System (ADS)

Zou, Liang; Fu, Zhuang; Zhao, YanZheng; Yang, JunYan

2010-07-01

This paper proposes a kind of pipelined electric circuit architecture implemented in FPGA, a very large scale integrated circuit (VLSI), which efficiently deals with the real time non-uniformity correction (NUC) algorithm for infrared focal plane arrays (IRFPA). Dual Nios II soft-core processors and a DSP with a 64+ core together constitute this image system. Each processor undertakes own systematic task, coordinating its work with each other's. The system on programmable chip (SOPC) in FPGA works steadily under the global clock frequency of 96Mhz. Adequate time allowance makes FPGA perform NUC image pre-processing algorithm with ease, which has offered favorable guarantee for the work of post image processing in DSP. And at the meantime, this paper presents a hardware (HW) and software (SW) co-design in FPGA. Thus, this systematic architecture yields an image processing system with multiprocessor, and a smart solution to the satisfaction with the performance of the system.

Readout electronics for LGAD sensors

NASA Astrophysics Data System (ADS)

Alonso, O.; Franch, N.; Canals, J.; Palacio, F.; López, M.; Vilà, A.; Diéguez, A.; Carulla, M.; Flores, D.; Hidalgo, S.; Merlos, A.; Pellegrini, G.; Quirion, D.

2017-02-01

In this paper, an ASIC fabricated in 180 nm CMOS technology from AMS with the very front-end electronics used to readout LGAD sensors is presented as well as its experimental results. The front-end has the typical architecture for Si-strip readout, i.e., preamplification stage with a Charge Sensitive Amplifier (CSA) followed by a CR-RC shaper. Both amplifiers are based on a folded cascode structure with a PMOS input transistor and the shaper only uses passive elements for the feedback stage. The CSA has programmable gain and a configurable input stage in order to adapt to the different input capacitance of the LGAD sensors (pixelated, short and long strips) and to the different input signal (depending on the gain of the LGAD). The fabricated prototype has an area of 0.865 mm × 0.965 mm and includes the biasing circuit for the CSA and the shaper, 4 analog channels (CSA+shaper) and programmable charge injection circuits included for testing purposes. Noise and power analysis performed during simulation fixed the size of the input transistor to W/L = 860 μm/0.2 μm. The shaping time is fixed by design at 1 us and, in this ASIC version, the feedback elements of the shaper are passive, which means that the area of the shaper can be reduced using active elements in future versions. Finally, the different gains of the CSA have been selected to maintain an ENC below 400 electrons for a detector capacitor of 20 pF, with a power consumption of 150 μ W per channel.

An integrated circuit with transmit beamforming flip-chip bonded to a 2-D CMUT array for 3-D ultrasound imaging.

PubMed

Wygant, Ira O; Jamal, Nafis S; Lee, Hyunjoo J; Nikoozadeh, Amin; Oralkan, Omer; Karaman, Mustafa; Khuri-Yakub, Butrus T

2009-10-01

State-of-the-art 3-D medical ultrasound imaging requires transmitting and receiving ultrasound using a 2-D array of ultrasound transducers with hundreds or thousands of elements. A tight combination of the transducer array with integrated circuitry eliminates bulky cables connecting the elements of the transducer array to a separate system of electronics. Furthermore, preamplifiers located close to the array can lead to improved receive sensitivity. A combined IC and transducer array can lead to a portable, high-performance, and inexpensive 3-D ultrasound imaging system. This paper presents an IC flip-chip bonded to a 16 x 16-element capacitive micromachined ultrasonic transducer (CMUT) array for 3-D ultrasound imaging. The IC includes a transmit beamformer that generates 25-V unipolar pulses with programmable focusing delays to 224 of the 256 transducer elements. One-shot circuits allow adjustment of the pulse widths for different ultrasound transducer center frequencies. For receiving reflected ultrasound signals, the IC uses the 32-elements along the array diagonals. The IC provides each receiving element with a low-noise 25-MHz-bandwidth transimpedance amplifier. Using a field-programmable gate array (FPGA) clocked at 100 MHz to operate the IC, the IC generated properly timed transmit pulses with 5-ns accuracy. With the IC flip-chip bonded to a CMUT array, we show that the IC can produce steered and focused ultrasound beams. We present 2-D and 3-D images of a wire phantom and 2-D orthogonal cross-sectional images (Bscans) of a latex heart phantom.

Design of a Ferroelectric Programmable Logic Gate Array

NASA Technical Reports Server (NTRS)

MacLeod, Todd C.; Ho, Fat Duen

2003-01-01

A programmable logic gate array has been designed utilizing ferroelectric field effect transistors. The design has only a small number of gates, but this could be scaled up to a more useful size. Using FFET's in a logic array gives several advantages. First, it allows real-time programmability to the array to give high speed reconfiguration. It also allows the array to be configured nearly an unlimited number of times, unlike a FLASH FPGA. Finally, the Ferroelectric Programmable Logic Gate Array (FPLGA) can be implemented using a smaller number of transistors because of the inherent logic characteristics of an FFET. The device was only designed and modeled using Spice models of the circuit, including the FFET. The actual device was not produced. The design consists of a small array of NAND and NOR logic gates. Other gates could easily be produced. They are linked by FFET's that control the logic flow. Timing and logic tables have been produced showing the array can produce a variety of logic combinations at a real time usable speed. This device could be a prototype for a device that could be put into imbedded systems that need the high speed of hardware implementation of logic and the complexity to need to change the logic algorithm. Because of the non-volatile nature of the FFET, it would also be useful in situations that needed to program a logic array once and use it repeatedly after the power has been shut off.

A Low Power Linear Phase Programmable Long Delay Circuit.

PubMed

Rodriguez-Villegas, Esther; Logesparan, Lojini; Casson, Alexander J

2014-06-01

A novel linear phase programmable delay is being proposed and implemented in a 0.35 μm CMOS process. The delay line consists of N cascaded cells, each of which delays the input signal by Td/N, where Td is the total line delay. The delay generated by each cell is programmable by changing a clock frequency and is also fully independent of the frequency of the input signal. The total delay hence depends only on the chosen clock frequency and the total number of cascaded cells. The minimum clock frequency is limited by the maximum time a voltage signal can effectively be held by an individual cell. The maximum number of cascaded cells will be limited by the effects of accumulated offset due to transistor mismatch, which eventually will affect the operating mode of the individual transistors in a cell. This latter limitation has however been dealt with in the topology by having an offset compensation mechanism that makes possible having a large number of cascaded cells and hence a long resulting delay. The delay line has been designed for scalp-based neural activity analysis that is predominantly in the sub-100 Hz frequency range. For these signals, the delay generated by a 31-cell cascade has been demonstrated to be programmable from 30 ms to 3 s. Measurement results demonstrate a 31 stage, 50 Hz bandwidth, 0.3 s delay that operates from a 1.1 V supply with power consumption of 270 nW.

Results from the UK 3rd generation programme: Albion

NASA Astrophysics Data System (ADS)

McEwen, R. K.; Axcell, C.; Knowles, P.; Hoade, K. P.; Wilson, M.; Dennis, P. N. J.; Backhouse, P.; Gordon, N. T.

2008-10-01

Following the development of 1st Generation systems in the 1970s, thermal imaging has been in service with the UK armed forces for over 25 years and has proven itself to be a battle winning technology. More recently the wider accessibility to similar technologies within opposing forces has reduced the military advantage provided by these 1st Generation systems and a clear requirement has been identified by the UK MOD for thermal imaging sensors providing increased detection, recognition and identification (DRI) ranges together with a simplified logistical deployment burden and reduced through-life costs. In late 2005, the UK MOD initiated a programme known as "Albion" to develop high performance 3rd Generation single waveband infrared detectors to meet this requirement. At the same time, under a separate programme supporting higher risk technology, a dual waveband infrared detector was also developed. The development phase of the Albion programme has now been completed and prototype detectors are now available and have been integrated into demonstration thermal imaging cameras. The Albion programme has now progressed into the second phase, incorporating both single and dual waveband devices, focussing on low rate initial production (LRIP) and qualification of the devices for military applications. All of the detectors have been fabricated using cadmium mercury telluride material (CMT), grown by metal organic vapour phase epitaxy (MOVPE) on low cost, gallium arsenide (GaAs) substrates and bump bonded to the silicon read out circuit (ROIC). This paper discusses the design features of the 3rd Generation detectors developed in the UK together with the results obtained from the prototype devices both in the laboratory and when integrated into field deployable thermal imaging cameras.

Circuit board routing attachment for Fermilab Gerber plotter

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lindenmeyer, C.

1984-05-10

A new and potentially important method of producing large circuit boards has been developed at Fermilab. A Gerber Flat Bed Plotter with an active area of 5' x 16' has been fitted with a machining head to produce a circuit board without the use of photography or chemicals. The modifications of the Gerber Plotter do not impair its use as a photoplotter or pen plotter, the machining head is merely exchanged with the standard attachments. The modifications to the program are minimal; this will be described in another report. The machining head is fitted with an air bearing motorized spindlemore » driven at a speed of 40,000 rpm to 90,000 rpm. The spindle also is provided with air bearings on its outside diameter, offering frictionless vertical travel guidance. Vertical travel of the spindle is driven by a spring return single acting air cylinder. An adjustable hydraulic damper slows the spindle travel near the end of its downward stroke. Two programmable stops control spindle down stroke position, and limit switches are provided for position feedback to the control system. A vacuum system collects chips at the cutter head. No lubrication or regular maintenance is required. The circuit board to be fabricated is supported on a porous plastic mat which allows table vacuum to hold the board in place while allowing the cutters or drills to cut through the board without damaging the rubber platen of the plotter. The perimeter of the board must be covered to the limits of the table vacuum area used to prevent excessive leakage.« less

Compact universal logic gates realized using quantization of current in nanodevices.

PubMed

Zhang, Wancheng; Wu, Nan-Jian; Yang, Fuhua

2007-12-12

This paper proposes novel universal logic gates using the current quantization characteristics of nanodevices. In nanodevices like the electron waveguide (EW) and single-electron (SE) turnstile, the channel current is a staircase quantized function of its control voltage. We use this unique characteristic to compactly realize Boolean functions. First we present the concept of the periodic-threshold threshold logic gate (PTTG), and we build a compact PTTG using EW and SE turnstiles. We show that an arbitrary three-input Boolean function can be realized with a single PTTG, and an arbitrary four-input Boolean function can be realized by using two PTTGs. We then use one PTTG to build a universal programmable two-input logic gate which can be used to realize all two-input Boolean functions. We also build a programmable three-input logic gate by using one PTTG. Compared with linear threshold logic gates, with the PTTG one can build digital circuits more compactly. The proposed PTTGs are promising for future smart nanoscale digital system use.

Programmable rate modem utilizing digital signal processing techniques

NASA Technical Reports Server (NTRS)

Bunya, George K.; Wallace, Robert L.

1989-01-01

The engineering development study to follow was written to address the need for a Programmable Rate Digital Satellite Modem capable of supporting both burst and continuous transmission modes with either binary phase shift keying (BPSK) or quadrature phase shift keying (QPSK) modulation. The preferred implementation technique is an all digital one which utilizes as much digital signal processing (DSP) as possible. Here design tradeoffs in each portion of the modulator and demodulator subsystem are outlined, and viable circuit approaches which are easily repeatable, have low implementation losses and have low production costs are identified. The research involved for this study was divided into nine technical papers, each addressing a significant region of concern in a variable rate modem design. Trivial portions and basic support logic designs surrounding the nine major modem blocks were omitted. In brief, the nine topic areas were: (1) Transmit Data Filtering; (2) Transmit Clock Generation; (3) Carrier Synthesizer; (4) Receive AGC; (5) Receive Data Filtering; (6) RF Oscillator Phase Noise; (7) Receive Carrier Selectivity; (8) Carrier Recovery; and (9) Timing Recovery.

Some reactions to a dry-land training programme for dinghy sailors.

PubMed Central

Wright, G.; Clarke, J.; Niinimaa, V.; Shephard, R. J.

1976-01-01

A dry-land winter training programme for dinghy-sailors is described. Individual elements include circuit training, specific exercises for muscle strength and endurance, and distance running. Ten international-class sailors followed a progressive regimen of this type for 14 weeks after completion of the 1973 season. Excess weight and skinfold thicknesses were reduced, while muscle strength, endurance and anaerobic capacity increased. Aerobic power remained substantially unchanged, although a smaller oxygen debt was incurred in reaching maximum effort. Team members were enthusiastic about the benefits gained from the training, commenting on their greater tolerance of the hiking position and all proposed to continue or to increase their efforts during subsequent winters. Racing results during 1974 were also an improvement on the 1973 record. However, it was difficult to link physiological gains to improvements in the relative rankings of individual competitors under either light or high wind conditions; the main factor changing relative standings seems to have been the additional year of competitive experiences in younger team members. PMID:963372

Some reactions to a dry-land training programme for dinghy sailors.

PubMed

Wright, G; Clarke, J; Niinimaa, V; Shephard, R J

1976-03-01

A dry-land winter training programme for dinghy-sailors is described. Individual elements include circuit training, specific exercises for muscle strength and endurance, and distance running. Ten international-class sailors followed a progressive regimen of this type for 14 weeks after completion of the 1973 season. Excess weight and skinfold thicknesses were reduced, while muscle strength, endurance and anaerobic capacity increased. Aerobic power remained substantially unchanged, although a smaller oxygen debt was incurred in reaching maximum effort. Team members were enthusiastic about the benefits gained from the training, commenting on their greater tolerance of the hiking position and all proposed to continue or to increase their efforts during subsequent winters. Racing results during 1974 were also an improvement on the 1973 record. However, it was difficult to link physiological gains to improvements in the relative rankings of individual competitors under either light or high wind conditions; the main factor changing relative standings seems to have been the additional year of competitive experiences in younger team members.

A Versatile Planetary Radio Science Microreceiver

NASA Technical Reports Server (NTRS)

Fry, Craig D.; Rosenberg, T. J.

1999-01-01

We have developed a low-power. programmable radio "microreceiver" that combines the functionality of two science instruments: a Relative Ionospheric Opacity Meter (riometer) and a swept-frequency, VTF/HF radio spectrometer. The radio receiver, calibration noise source, data acquisition and processing, and command and control functions are all contained on a single circuit board. This design is suitable for miniaturizing as a complete flight instrument. Several of the subsystems were implemented in a field-programmable gate array (FPGA), including the receiver detector, the control logic, and the data acquisition and processing blocks. Considerable efforts were made to reduce the power consumption of the instrument, and eliminate or minimize RF noise and spurious emissions generated by the receiver's digital circuitry. A prototype instrument was deployed at McMurdo Station, Antarctica, and operated in parallel with a traditional riometer instrument for approximately three weeks. The attached paper (accepted for publication by Radio Science) describes in detail the microreceiver theory of operation, performance specifications and test results.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dondero, Rachel Elizabeth

The increased use of Field Programmable Gate Arrays (FPGAs) in critical systems brings new challenges in securing the diversely programmable fabric from cyber-attacks. FPGAs are an inexpensive, efficient, and flexible alternative to Application Specific Integrated Circuits (ASICs), which are becoming increasingly expensive and impractical for low volume manufacturing as technology nodes continue to shrink. Unfortunately, FPGAs are not designed for high security applications, and their high-flexibility lends itself to low security and vulnerability to malicious attacks. Similar to securing an ASIC’s functionality, FPGA programmers can exploit the inherent randomness introduced into hardware structures during fabrication for security applications. Physically Unclonablemore » Functions (PUFs) are one such solution that uses the die specific variability in hardware fabrication for both secret key generation and verification. PUFs strive to be random, unique, and reliable. Throughout recent years many PUF structures have been presented to try and maximize these three design constraints, reliability being the most difficult of the three to achieve. This thesis presents a new PUF structure that combines two elementary PUF concepts (a bi-stable SRAM PUF and a delay-based arbiter PUF) to create a PUF with increased reliability, while maintaining both random and unique qualities. Properties of the new PUF will be discussed as well as the various design modifications that can be made to tweak the desired performance and overhead.« less

Strength and endurance training of an individual with left upper and lower limb amputations.

PubMed

Donachy, J E; Brannon, K D; Hughes, L S; Seahorn, J; Crutcher, T T; Christian, E L

2004-04-22

The purpose of this article is to describe the development of a strength and endurance training programme designed to prepare an individual with a left glenohumeral disarticulation and transtibial amputation for a bike trip across the USA. The subject was scheduled for training three times per week over a two-month period followed by two times per week for an additional two months. Training consisted of a resistance training circuit using variable resistance machines, cycling using a recumbent stationary bike, and core stability training using stability ball exercises. Changes in strength were assessed using 10 RM tests on the resistance machines and changes in peak VO(2) were monitored utilizing the Cosmed K4b pulmonary function tester. The subject demonstrated a 30.3% gain in peak VO(2). The subject's 10 RM for left single limb leg press increased 36.8% and gains of at least 7.7% were seen for all other muscle groups tested. The strength and endurance training programme adapted to compensate for this subject's limb losses was effective in increasing both strength and peak VO(2). Adapting exercise programmes to compensate for limb loss may allow individuals with amputations to participate in physically challenging activities that otherwise may not be available to them.

Low-voltage-operated organic one-time programmable memory using printed organic thin-film transistors and antifuse capacitors.

PubMed

Jung, Soon-Won; Na, Bock Soon; Park, Chan Woo; Koo, Jae Bon

2014-11-01

We demonstrate an organic one-time programmable memory cell formed entirely at plastic-compatible temperatures. All the processes are performed at below 130 degrees C. Our memory cell consists of a printed organic transistor and an organic capacitor. Inkjet-printed organic transistors are fabricated by using high-k polymer dielectric blends comprising poly(vinylidenefluoride-trifluoroethylene) [P(VDF-TrFE)] and poly(methyl methacrylate) (PMMA) for low-voltage operation. P(NDI2OD-T2) transistors have a high field-effect mobility of 0.2 cm2/Vs and a low operation gate voltage of less than 10 V. The operation voltage effectively decreases owing to the high permittivity of the P(VDF-TrFE):PMMA blended film. The data in the memory cell are programmed by electrically breaking the organic capacitor. The organic capacitor acts like an antifuse capacitor, because it is initially open, and it becomes permanently short-circuited by applying a high voltage. The organic memory cells are programmed with 4 V, and they are read out with 2 V. The memory data are read out by sensing the current in the memory cell. The printed organic one-time programmable memory is suitable for applications storing small amount of data, such as low-cost radio-frequency identification (RFID) tag.

High-Precision Pulse Generator

NASA Technical Reports Server (NTRS)

Katz, Richard; Kleyner, Igor

2011-01-01

A document discusses a pulse generator with subnanosecond resolution implemented with a low-cost field-programmable gate array (FPGA) at low power levels. The method used exploits the fast carry chains of certain FPGAs. Prototypes have been built and tested in both Actel AX and Xilinx Virtex 4 technologies. In-flight calibration or control can be performed by using a similar and related technique as a time interval measurement circuit by measuring a period of the stable oscillator, as the delays through the fast carry chains will vary as a result of manufacturing variances as well as the result of environmental conditions (voltage, aging, temperature, and radiation).

Inappropriate implantable cardioverter defibrillator shocks in fractured Sprint Fidelis leads associated with 'appropriate' interrogation.

PubMed

Farwell, David; Redpath, Calum; Birnie, David; Gollob, Michael; Lemery, Robert; Posan, Emoke; Green, Martin

2008-06-01

We present two patients with fractures within the pace-sense circuit of their Medtronic Sprint Fidelis leads who received inappropriate shocks from their Medtronic defibrillators during device interrogation. This was not simply a coincidence, but due to electromagnetic interference induced within the Sprint Fidelis lead by the device programmer during two-way communication with the defibrillator. Our subsequent investigations have uncovered at least two other similar incidents in Canada. We have also discovered that the Medtronic 'Auto-resume' feature may leave future patients uniquely vulnerable to such inappropriate shocks in the future.

System for fuel rod removal from a reactor module

DOEpatents

Matchett, R.L.; Fodor, G.; Kikta, T.J.; Bacvinsicas, W.S.; Roof, D.R.; Nilsen, R.J.; Wilczynski, R.

1988-07-28

A robotic system for remote underwater withdrawal of the fuel rods from fuel modules of a light water breeder reactor includes a collet/grapple assembly for gripping and removing fuel rods in each module, which is positioned by use of a winch and a radial support means attached to a vertical support tube which is mounted over the fuel module. A programmable logic controller in conjunction with a microcomputer, provides control for the accurate positioning and pulling force of the rod grapple assembly. Closed circuit television cameras are provided which aid in operator interface with the robotic system. 7 figs.

System for fuel rod removal from a reactor module

DOEpatents

Matchett, Richard L.; Roof, David R.; Kikta, Thomas J.; Wilczynski, Rosemarie; Nilsen, Roy J.; Bacvinskas, William S.; Fodor, George

1990-01-01

A robotic system for remote underwater withdrawal of the fuel rods from fuel modules of a light water breeder reactor includes a collet/grapple assembly for gripping and removing fuel rods in each module, which is positioned by use of a winch and a radial support means attached to a vertical support tube which is mounted over the fuel module. A programmable logic controller in conjunction with a microcomputer, provides control for the accurate positioning and pulling force of the rod grapple assembly. Closed circuit television cameras are provided which aid in operator interface with the robotic system.

CCD correlation techniques

NASA Technical Reports Server (NTRS)

Hewes, C. R.; Bosshart, P. W.; Eversole, W. L.; Dewit, M.; Buss, D. D.

1976-01-01

Two CCD techniques were discussed for performing an N-point sampled data correlation between an input signal and an electronically programmable reference function. The design and experimental performance of an implementation of the direct time correlator utilizing two analog CCDs and MOS multipliers on a single IC were evaluated. The performance of a CCD implementation of the chirp z transform was described, and the design of a new CCD integrated circuit for performing correlation by multiplication in the frequency domain was presented. This chip provides a discrete Fourier transform (DFT) or inverse DFT, multipliers, and complete support circuitry for the CCD CZT. The two correlation techniques are compared.

Introduction to focus issue: quantitative approaches to genetic networks.

PubMed

Albert, Réka; Collins, James J; Glass, Leon

2013-06-01

All cells of living organisms contain similar genetic instructions encoded in the organism's DNA. In any particular cell, the control of the expression of each different gene is regulated, in part, by binding of molecular complexes to specific regions of the DNA. The molecular complexes are composed of protein molecules, called transcription factors, combined with various other molecules such as hormones and drugs. Since transcription factors are coded by genes, cellular function is partially determined by genetic networks. Recent research is making large strides to understand both the structure and the function of these networks. Further, the emerging discipline of synthetic biology is engineering novel gene circuits with specific dynamic properties to advance both basic science and potential practical applications. Although there is not yet a universally accepted mathematical framework for studying the properties of genetic networks, the strong analogies between the activation and inhibition of gene expression and electric circuits suggest frameworks based on logical switching circuits. This focus issue provides a selection of papers reflecting current research directions in the quantitative analysis of genetic networks. The work extends from molecular models for the binding of proteins, to realistic detailed models of cellular metabolism. Between these extremes are simplified models in which genetic dynamics are modeled using classical methods of systems engineering, Boolean switching networks, differential equations that are continuous analogues of Boolean switching networks, and differential equations in which control is based on power law functions. The mathematical techniques are applied to study: (i) naturally occurring gene networks in living organisms including: cyanobacteria, Mycoplasma genitalium, fruit flies, immune cells in mammals; (ii) synthetic gene circuits in Escherichia coli and yeast; and (iii) electronic circuits modeling genetic networks using field-programmable gate arrays. Mathematical analyses will be essential for understanding naturally occurring genetic networks in diverse organisms and for providing a foundation for the improved development of synthetic genetic networks.

Introduction to Focus Issue: Quantitative Approaches to Genetic Networks

NASA Astrophysics Data System (ADS)

Albert, Réka; Collins, James J.; Glass, Leon

2013-06-01

All cells of living organisms contain similar genetic instructions encoded in the organism's DNA. In any particular cell, the control of the expression of each different gene is regulated, in part, by binding of molecular complexes to specific regions of the DNA. The molecular complexes are composed of protein molecules, called transcription factors, combined with various other molecules such as hormones and drugs. Since transcription factors are coded by genes, cellular function is partially determined by genetic networks. Recent research is making large strides to understand both the structure and the function of these networks. Further, the emerging discipline of synthetic biology is engineering novel gene circuits with specific dynamic properties to advance both basic science and potential practical applications. Although there is not yet a universally accepted mathematical framework for studying the properties of genetic networks, the strong analogies between the activation and inhibition of gene expression and electric circuits suggest frameworks based on logical switching circuits. This focus issue provides a selection of papers reflecting current research directions in the quantitative analysis of genetic networks. The work extends from molecular models for the binding of proteins, to realistic detailed models of cellular metabolism. Between these extremes are simplified models in which genetic dynamics are modeled using classical methods of systems engineering, Boolean switching networks, differential equations that are continuous analogues of Boolean switching networks, and differential equations in which control is based on power law functions. The mathematical techniques are applied to study: (i) naturally occurring gene networks in living organisms including: cyanobacteria, Mycoplasma genitalium, fruit flies, immune cells in mammals; (ii) synthetic gene circuits in Escherichia coli and yeast; and (iii) electronic circuits modeling genetic networks using field-programmable gate arrays. Mathematical analyses will be essential for understanding naturally occurring genetic networks in diverse organisms and for providing a foundation for the improved development of synthetic genetic networks.

Σ-Δ modulator for a programmable gain, low-power, high-linearity automotive sensor interface

NASA Astrophysics Data System (ADS)

de la Rosa, Jose M.; Medeiro, Fernando; Perez-Verdu, Belen; del Rio, Rocio; Rodriguez-Vazquez, Angel

2003-04-01

Smart sensors play a critical role in modern automotive electronic systems, covering a wide range of data capturing functions and operating under adverse environmental conditions - temperature range of [-40¦C,175¦C]. In such sensors, the signal provided by transducers is composed of an offset voltage, which depends on the manufacturing process, and a low-frequency signal carrying the information. In practice, the offset voltage is subject to temperature variations, thus causing a shifting of the signal range to be measured. Therefore, the measuring circuit driving the sensor, normally formed by a low-noise preamplifier and an Analog-to-Digital Converter (ADC), must accommodate the complete range of possible offsets and real signals. In this scenario, the use of ADCs based on Sigma-Delta Modulators (SDMs) is convenient for several reasons. On the one hand, the noise-shaping performed by SDMs allows to achieve high resolution (16-17bits), in the band of interest (10-20kHz), with less power consumption than full Nyquist ADCs. On the other hand, the action of feedback renders SDMs very linear, and high-linearity is a must for automotive applications. Last but not least, the robustness of SDMs with respect to circuit imperfections make them suitable to include programmable gain without significant performance degradation. This feature allows to accommodate the complete range of possible offsets and information signals in a sensor interface with relaxed specifications for the preamplifier circuitry. This paper describes the design and implementation of a third-order cascade (2-1) SDM with programmable gain in a 0.35mm CMOS technology - the type of technology commonly employed for automotive applications (deep submicron is mostly employed for telecom). It is capable of handling signals up to 20-kHz bandwidth with 17-bit resolution. The programmable gain is implemented by a capacitor array whose unitary capacitors are connected or disconnected depending on the value of the selected gain. In order to relax the amplifier dynamics requirements as the modulator gain varies, switchable capacitor arrays have been used for all the capacitors in the first integrator. The design of the modulator building blocks is based upon a top-down CAD methodology which combines simulation and statistical optimization at different levels of the modulator hierarchy. As a result, a dynamic range equal to 105 dB is obtained for all cases of the modulator gain, which corresponds to 17 bit resolution.

A design method for high performance seismic data acquisition based on oversampling delta-sigma modulation

NASA Astrophysics Data System (ADS)

Gao, Shanghua; Xue, Bing

2017-04-01

The dynamic range of the currently most widely used 24-bit seismic data acquisition devices is 10-20 dB lower than that of broadband seismometers, and this can affect the completeness of seismic waveform recordings under certain conditions. However, this problem is not easy to solve because of the lack of analog to digital converter (ADC) chips with more than 24 bits in the market. So the key difficulties for higher-resolution data acquisition devices lie in achieving more than 24-bit ADC circuit. In the paper, we propose a method in which an adder, an integrator, a digital to analog converter chip, a field-programmable gate array, and an existing low-resolution ADC chip are used to build a third-order 16-bit oversampling delta-sigma modulator. This modulator is equipped with a digital decimation filter, thus forming a complete analog to digital converting circuit. Experimental results show that, within the 0.1-40 Hz frequency range, the circuit board's dynamic range reaches 158.2 dB, its resolution reaches 25.99 dB, and its linearity error is below 2.5 ppm, which is better than what is achieved by the commercial 24-bit ADC chips ADS1281 and CS5371. This demonstrates that the proposed method may alleviate or even solve the amplitude-limitation problem that broadband observation systems so commonly have to face during strong earthquakes.

Coherent quantum dynamics launched by incoherent relaxation in a quantum circuit simulator of a light-harvesting complex

NASA Astrophysics Data System (ADS)

Chin, A. W.; Mangaud, E.; Atabek, O.; Desouter-Lecomte, M.

2018-06-01

Engineering and harnessing coherent excitonic transport in organic nanostructures has recently been suggested as a promising way towards improving manmade light-harvesting materials. However, realizing and testing the dissipative system-environment models underlying these proposals is presently very challenging in supramolecular materials. A promising alternative is to use simpler and highly tunable "quantum simulators" built from programmable qubits, as recently achieved in a superconducting circuit by Potočnik et al. [A. Potočnik et al., Nat. Commun. 9, 904 (2018), 10.1038/s41467-018-03312-x]. We simulate the real-time dynamics of an exciton coupled to a quantum bath as it moves through a network based on the quantum circuit of Potočnik et al. Using the numerically exact hierarchical equations of motion to capture the open quantum system dynamics, we find that an ultrafast but completely incoherent relaxation from a high-lying "bright" exciton into a doublet of closely spaced "dark" excitons can spontaneously generate electronic coherences and oscillatory real-space motion across the network (quantum beats). Importantly, we show that this behavior also survives when the environmental noise is classically stochastic (effectively high temperature), as in present experiments. These predictions highlight the possibilities of designing matched electronic and spectral noise structures for robust coherence generation that do not require coherent excitation or cold environments.

A digital pixel cell for address event representation image convolution processing

NASA Astrophysics Data System (ADS)

Camunas-Mesa, Luis; Acosta-Jimenez, Antonio; Serrano-Gotarredona, Teresa; Linares-Barranco, Bernabe

2005-06-01

Address Event Representation (AER) is an emergent neuromorphic interchip communication protocol that allows for real-time virtual massive connectivity between huge number of neurons located on different chips. By exploiting high speed digital communication circuits (with nano-seconds timings), synaptic neural connections can be time multiplexed, while neural activity signals (with mili-seconds timings) are sampled at low frequencies. Also, neurons generate events according to their information levels. Neurons with more information (activity, derivative of activities, contrast, motion, edges,...) generate more events per unit time, and access the interchip communication channel more frequently, while neurons with low activity consume less communication bandwidth. AER technology has been used and reported for the implementation of various type of image sensors or retinae: luminance with local agc, contrast retinae, motion retinae,... Also, there has been a proposal for realizing programmable kernel image convolution chips. Such convolution chips would contain an array of pixels that perform weighted addition of events. Once a pixel has added sufficient event contributions to reach a fixed threshold, the pixel fires an event, which is then routed out of the chip for further processing. Such convolution chips have been proposed to be implemented using pulsed current mode mixed analog and digital circuit techniques. In this paper we present a fully digital pixel implementation to perform the weighted additions and fire the events. This way, for a given technology, there is a fully digital implementation reference against which compare the mixed signal implementations. We have designed, implemented and tested a fully digital AER convolution pixel. This pixel will be used to implement a full AER convolution chip for programmable kernel image convolution processing.

Report of the Odyssey FPGA Independent Assessment Team

NASA Technical Reports Server (NTRS)

Mayer, Donald C.; Katz, Richard B.; Osborn, Jon V.; Soden, Jerry M.; Barto, R.; Day, John H. (Technical Monitor)

2001-01-01

An independent assessment team (IAT) was formed and met on April 2, 2001, at Lockheed Martin in Denver, Colorado, to aid in understanding a technical issue for the Mars Odyssey spacecraft scheduled for launch on April 7, 2001. An RP1280A field-programmable gate array (FPGA) from a lot of parts common to the SIRTF, Odyssey, and Genesis missions had failed on a SIRTF printed circuit board. A second FPGA from an earlier Odyssey circuit board was also known to have failed and was also included in the analysis by the IAT. Observations indicated an abnormally high failure rate for flight RP1280A devices (the first flight lot produced using this flow) at Lockheed Martin and the causes of these failures were not determined. Standard failure analysis techniques were applied to these parts, however, additional diagnostic techniques unique for devices of this class were not used, and the parts were prematurely submitted to a destructive physical analysis, making a determination of the root cause of failure difficult. Any of several potential failure scenarios may have caused these failures, including electrostatic discharge, electrical overstress, manufacturing defects, board design errors, board manufacturing errors, FPGA design errors, or programmer errors. Several of these mechanisms would have relatively benign consequences for disposition of the parts currently installed on boards in the Odyssey spacecraft if established as the root cause of failure. However, other potential failure mechanisms could have more dire consequences. As there is no simple way to determine the likely failure mechanisms with reasonable confidence before Odyssey launch, it is not possible for the IAT to recommend a disposition for the other parts on boards in the Odyssey spacecraft based on sound engineering principles.

A Gain-Programmable Transit-Time-Stable and Temperature-Stable PMT Voltage Divider

NASA Astrophysics Data System (ADS)

Liu, Yaqiang; Li, Hongdi; Wang, Yu; Xing, Tao; Xie, Shuping; Uribe, J.; Baghaei, H.; Ramirez, R.; Kim, Soonseok; Wong, Wai-Hoi

2004-10-01

A gain-programmable, transit-time-stable, temperature-stable photomultiplier (PMT) voltage divider design is described in this paper. The signal-to-noise ratio can be increased by changing a PMT gain directly instead of adjusting the gain of the preamplifier. PMT gain can be changed only by adjusting the voltages for the dynodes instead of changing the total high voltage between the anode and the photocathode, which can cause a significant signal transit-time variation that cannot be accepted by an application with a critical timing requirement, such as positron emission tomography (PET) or time-of-flight (TOF) detection/PET. The dynode voltage can be controlled by a digital analog converter isolated with a linear optocoupler. The optocoupler consists of an infrared light emission diode (LED) optically coupled with two phototransistors, and one is used in a servo feedback circuit to control the LED drive current for compensating temperature characteristics. The results showed that a six times gain range could be achieved; the gain drift was <0.5% over a 20/spl deg/C temperature range; 250 ps transit-time variation was measured over the entire gain range. A compact print circuit board (PCB) for the voltage divider integrated with a fixed-gain preamplifier has been designed and constructed. It can save about $30 per PMT channel compared with a commercial PMT voltage divider along with a variable gain amplifier. The preamplifier can be totally disabled, therefore in a system with a large amount of PMTs, only one channel can be enabled for calibrating the PMT gain. This new PMT voltage divider design is being applied to our animal PET camera and TOF/PET research.

Complex cellular logic computation using ribocomputing devices.

PubMed

Green, Alexander A; Kim, Jongmin; Ma, Duo; Silver, Pamela A; Collins, James J; Yin, Peng

2017-08-03

Synthetic biology aims to develop engineering-driven approaches to the programming of cellular functions that could yield transformative technologies. Synthetic gene circuits that combine DNA, protein, and RNA components have demonstrated a range of functions such as bistability, oscillation, feedback, and logic capabilities. However, it remains challenging to scale up these circuits owing to the limited number of designable, orthogonal, high-performance parts, the empirical and often tedious composition rules, and the requirements for substantial resources for encoding and operation. Here, we report a strategy for constructing RNA-only nanodevices to evaluate complex logic in living cells. Our 'ribocomputing' systems are composed of de-novo-designed parts and operate through predictable and designable base-pairing rules, allowing the effective in silico design of computing devices with prescribed configurations and functions in complex cellular environments. These devices operate at the post-transcriptional level and use an extended RNA transcript to co-localize all circuit sensing, computation, signal transduction, and output elements in the same self-assembled molecular complex, which reduces diffusion-mediated signal losses, lowers metabolic cost, and improves circuit reliability. We demonstrate that ribocomputing devices in Escherichia coli can evaluate two-input logic with a dynamic range up to 900-fold and scale them to four-input AND, six-input OR, and a complex 12-input expression (A1 AND A2 AND NOT A1*) OR (B1 AND B2 AND NOT B2*) OR (C1 AND C2) OR (D1 AND D2) OR (E1 AND E2). Successful operation of ribocomputing devices based on programmable RNA interactions suggests that systems employing the same design principles could be implemented in other host organisms or in extracellular settings.

Comparative study of diastolic filling under varying left ventricular wall stiffness

NASA Astrophysics Data System (ADS)

Mekala, Pritam; Santhanakrishnan, Arvind

2014-11-01

Pathological remodeling of the human cardiac left ventricle (LV) is observed in hypertensive heart failure as a result of pressure overload. Myocardial stiffening occurs in these patients prior to chronic maladaptive changes, resulting in increased LV wall stiffness. The goal of this study was to investigate the change in intraventricular filling fluid dynamics inside a physical model of the LV as a function of wall stiffness. Three LV models of varying wall stiffness were incorporated into an in vitro flow circuit driven by a programmable piston pump. Windkessel elements were used to tune the inflow and systemic pressure in the model with least stiffness to match healthy conditions. Models with stiffer walls were comparatively tested maintaining circuit compliance, resistance and pump amplitude constant. 2D phase-locked PIV measurements along the central plane showed that with increase in wall stiffness, the peak velocity and cardiac output inside the LV decreased. Further, inflow vortex ring propagation toward the LV apex was reduced with increasing stiffness. The above findings indicate the importance of considering LV wall relaxation characteristics in pathological studies of filling fluid dynamics.

A hybrid analog-digital phase-locked loop for frequency mode non-contact scanning probe microscopy.

PubMed

Mehta, M M; Chandrasekhar, V

2014-01-01

Non-contact scanning probe microscopy (SPM) has developed into a powerful technique to image many different properties of samples. The conventional method involves monitoring the amplitude, phase, or frequency of a cantilever oscillating at or near its resonant frequency as it is scanned across the surface of a sample. For high Q factor cantilevers, monitoring the resonant frequency is the preferred method in order to obtain reasonable scan times. This can be done by using a phase-locked-loop (PLL). PLLs can be obtained as commercial integrated circuits, but these do not have the frequency resolution required for SPM. To increase the resolution, all-digital PLLs requiring sophisticated digital signal processors or field programmable gate arrays have also been implemented. We describe here a hybrid analog/digital PLL where most of the components are implemented using discrete analog integrated circuits, but the frequency resolution is provided by a direct digital synthesis chip controlled by a simple peripheral interface controller (PIC) microcontroller. The PLL has excellent frequency resolution and noise, and can be controlled and read by a computer via a universal serial bus connection.

A hybrid analog-digital phase-locked loop for frequency mode non-contact scanning probe microscopy

NASA Astrophysics Data System (ADS)

Mehta, M. M.; Chandrasekhar, V.

2014-01-01

Non-contact scanning probe microscopy (SPM) has developed into a powerful technique to image many different properties of samples. The conventional method involves monitoring the amplitude, phase, or frequency of a cantilever oscillating at or near its resonant frequency as it is scanned across the surface of a sample. For high Q factor cantilevers, monitoring the resonant frequency is the preferred method in order to obtain reasonable scan times. This can be done by using a phase-locked-loop (PLL). PLLs can be obtained as commercial integrated circuits, but these do not have the frequency resolution required for SPM. To increase the resolution, all-digital PLLs requiring sophisticated digital signal processors or field programmable gate arrays have also been implemented. We describe here a hybrid analog/digital PLL where most of the components are implemented using discrete analog integrated circuits, but the frequency resolution is provided by a direct digital synthesis chip controlled by a simple peripheral interface controller (PIC) microcontroller. The PLL has excellent frequency resolution and noise, and can be controlled and read by a computer via a universal serial bus connection.

Path programmable logic: A structured design method for digital and/or mixed analog integrated circuits

NASA Technical Reports Server (NTRS)

Taylor, B.

1990-01-01

The design of Integrated Circuits has evolved past the black art practiced by a few semiconductor companies to a world wide community of users. This was basically accomplished by the development of computer aided design tools which were made available to this community. As the tools matured into different components of the design task they were accepted into the community at large. However, the next step in this evolution is being ignored by the large tool vendors hindering the continuation of this process. With system level definition and simulation through the logic specification well understood, why is the physical generation so blatantly ignored. This portion of the development is still treated as an isolated task with information being passed from the designer to the layout function. Some form of result given back but it severely lacks full definition of what has transpired. The level of integration in I.C.'s for tomorrow, whether through new processes or applications will require higher speeds, increased transistor density, and non-digital performance which can only be achieved through attention to the physical implementation.

VHDL Descriptions for the FPGA Implementation of PWL-Function-Based Multi-Scroll Chaotic Oscillators

PubMed Central

2016-01-01

Nowadays, chaos generators are an attractive field for research and the challenge is their realization for the development of engineering applications. From more than three decades ago, chaotic oscillators have been designed using discrete electronic devices, very few with integrated circuit technology, and in this work we propose the use of field-programmable gate arrays (FPGAs) for fast prototyping. FPGA-based applications require that one be expert on programming with very-high-speed integrated circuits hardware description language (VHDL). In this manner, we detail the VHDL descriptions of chaos generators for fast prototyping from high-level programming using Python. The cases of study are three kinds of chaos generators based on piecewise-linear (PWL) functions that can be systematically augmented to generate even and odd number of scrolls. We introduce new algorithms for the VHDL description of PWL functions like saturated functions series, negative slopes and sawtooth. The generated VHDL-code is portable, reusable and open source to be synthesized in an FPGA. Finally, we show experimental results for observing 2, 10 and 30-scroll attractors. PMID:27997930

VHDL Descriptions for the FPGA Implementation of PWL-Function-Based Multi-Scroll Chaotic Oscillators.

PubMed

Tlelo-Cuautle, Esteban; Quintas-Valles, Antonio de Jesus; de la Fraga, Luis Gerardo; Rangel-Magdaleno, Jose de Jesus

2016-01-01

Nowadays, chaos generators are an attractive field for research and the challenge is their realization for the development of engineering applications. From more than three decades ago, chaotic oscillators have been designed using discrete electronic devices, very few with integrated circuit technology, and in this work we propose the use of field-programmable gate arrays (FPGAs) for fast prototyping. FPGA-based applications require that one be expert on programming with very-high-speed integrated circuits hardware description language (VHDL). In this manner, we detail the VHDL descriptions of chaos generators for fast prototyping from high-level programming using Python. The cases of study are three kinds of chaos generators based on piecewise-linear (PWL) functions that can be systematically augmented to generate even and odd number of scrolls. We introduce new algorithms for the VHDL description of PWL functions like saturated functions series, negative slopes and sawtooth. The generated VHDL-code is portable, reusable and open source to be synthesized in an FPGA. Finally, we show experimental results for observing 2, 10 and 30-scroll attractors.

Design of microcontroller based system for automation of streak camera.

PubMed

Joshi, M J; Upadhyay, J; Deshpande, P P; Sharma, M L; Navathe, C P

2010-08-01

A microcontroller based system has been developed for automation of the S-20 optical streak camera, which is used as a diagnostic tool to measure ultrafast light phenomenon. An 8 bit MCS family microcontroller is employed to generate all control signals for the streak camera. All biasing voltages required for various electrodes of the tubes are generated using dc-to-dc converters. A high voltage ramp signal is generated through a step generator unit followed by an integrator circuit and is applied to the camera's deflecting plates. The slope of the ramp can be changed by varying values of the capacitor and inductor. A programmable digital delay generator has been developed for synchronization of ramp signal with the optical signal. An independent hardwired interlock circuit has been developed for machine safety. A LABVIEW based graphical user interface has been developed which enables the user to program the settings of the camera and capture the image. The image is displayed with intensity profiles along horizontal and vertical axes. The streak camera was calibrated using nanosecond and femtosecond lasers.

Digital optical processing of optical communications: towards an Optical Turing Machine

NASA Astrophysics Data System (ADS)

Touch, Joe; Cao, Yinwen; Ziyadi, Morteza; Almaiman, Ahmed; Mohajerin-Ariaei, Amirhossein; Willner, Alan E.

2017-01-01

Optical computing is needed to support Tb/s in-network processing in a way that unifies communication and computation using a single data representation that supports in-transit network packet processing, security, and big data filtering. Support for optical computation of this sort requires leveraging the native properties of optical wave mixing to enable computation and switching for programmability. As a consequence, data must be encoded digitally as phase (M-PSK), semantics-preserving regeneration is the key to high-order computation, and data processing at Tb/s rates requires mixing. Experiments have demonstrated viable approaches to phase squeezing and power restoration. This work led our team to develop the first serial, optical Internet hop-count decrement, and to design and simulate optical circuits for calculating the Internet checksum and multiplexing Internet packets. The current exploration focuses on limited-lookback computational models to reduce the need for permanent storage and hybrid nanophotonic circuits that combine phase-aligned comb sources, non-linear mixing, and switching on the same substrate to avoid the macroscopic effects that hamper benchtop prototypes.

Design of microcontroller based system for automation of streak camera

DOE Office of Scientific and Technical Information (OSTI.GOV)

Joshi, M. J.; Upadhyay, J.; Deshpande, P. P.

2010-08-15

A microcontroller based system has been developed for automation of the S-20 optical streak camera, which is used as a diagnostic tool to measure ultrafast light phenomenon. An 8 bit MCS family microcontroller is employed to generate all control signals for the streak camera. All biasing voltages required for various electrodes of the tubes are generated using dc-to-dc converters. A high voltage ramp signal is generated through a step generator unit followed by an integrator circuit and is applied to the camera's deflecting plates. The slope of the ramp can be changed by varying values of the capacitor and inductor.more » A programmable digital delay generator has been developed for synchronization of ramp signal with the optical signal. An independent hardwired interlock circuit has been developed for machine safety. A LABVIEW based graphical user interface has been developed which enables the user to program the settings of the camera and capture the image. The image is displayed with intensity profiles along horizontal and vertical axes. The streak camera was calibrated using nanosecond and femtosecond lasers.« less

Image processing using Gallium Arsenide (GaAs) technology

NASA Technical Reports Server (NTRS)

Miller, Warner H.

1989-01-01

The need to increase the information return from space-borne imaging systems has increased in the past decade. The use of multi-spectral data has resulted in the need for finer spatial resolution and greater spectral coverage. Onboard signal processing will be necessary in order to utilize the available Tracking and Data Relay Satellite System (TDRSS) communication channel at high efficiency. A generally recognized approach to the increased efficiency of channel usage is through data compression techniques. The compression technique implemented is a differential pulse code modulation (DPCM) scheme with a non-uniform quantizer. The need to advance the state-of-the-art of onboard processing was recognized and a GaAs integrated circuit technology was chosen. An Adaptive Programmable Processor (APP) chip set was developed which is based on an 8-bit slice general processor. The reason for choosing the compression technique for the Multi-spectral Linear Array (MLA) instrument is described. Also a description is given of the GaAs integrated circuit chip set which will demonstrate that data compression can be performed onboard in real time at data rate in the order of 500 Mb/s.

Scalability, Timing, and System Design Issues for Intrinsic Evolvable Hardware

NASA Technical Reports Server (NTRS)

Hereford, James; Gwaltney, David

2004-01-01

In this paper we address several issues pertinent to intrinsic evolvable hardware (EHW). The first issue is scalability; namely, how the design space scales as the programming string for the programmable device gets longer. We develop a model for population size and the number of generations as a function of the programming string length, L, and show that the number of circuit evaluations is an O(L2) process. We compare our model to several successful intrinsic EHW experiments and discuss the many implications of our model. The second issue that we address is the timing of intrinsic EHW experiments. We show that the processing time is a small part of the overall time to derive or evolve a circuit and that major improvements in processor speed alone will have only a minimal impact on improving the scalability of intrinsic EHW. The third issue we consider is the system-level design of intrinsic EHW experiments. We review what other researchers have done to break the scalability barrier and contend that the type of reconfigurable platform and the evolutionary algorithm are tied together and impose limits on each other.

The design of CMOS general-purpose analog front-end circuit with tunable gain and bandwidth for biopotential signal recording systems.

PubMed

Chen, Wei-Ming; Yang, Wen-Chia; Tsai, Tzung-Yun; Chiueh, Herming; Wu, Chung-Yu

2011-01-01

In this paper an 8-channel CMOS general-purpose analog front-end (AFE) circuit with tunable gain and bandwidth for biopotential signal recording systems is presented. The proposed AFE consists of eight chopper stabilized pre-amplifiers, an 8-to-1 analog multiplexer, and a programmable gain amplifier. It can be used to sense and amplify different kinds of biopotential signals, such as electrocorticogram (ECoG), electrocardiogram (ECG) and electromyogram (EMG). The AFE chip is designed and fabricated in 0.18-μm CMOS technology. The measured maximum gain of AFE is 60.8 dB. The low cutoff frequency can achieve as low as 0.8 Hz and high cutoff frequency can be adjusted from 200 Hz to 10 kHz to suit for different kinds of biopotential signals. The measured input-referred noise is 0.9 μV(rms), with the power consumption of 18μW per channel at 1.8-V power supply. And the noise efficiency factor (NEF) is only 1.3 for pre-amplifier.

Biomechanical cell regulatory networks as complex adaptive systems in relation to cancer.

PubMed

Feller, Liviu; Khammissa, Razia Abdool Gafaar; Lemmer, Johan

2017-01-01

Physiological structure and function of cells are maintained by ongoing complex dynamic adaptive processes in the intracellular molecular pathways controlling the overall profile of gene expression, and by genes in cellular gene regulatory circuits. Cytogenetic mutations and non-genetic factors such as chronic inflammation or repetitive trauma, intrinsic mechanical stresses within extracellular matrix may induce redirection of gene regulatory circuits with abnormal reactivation of embryonic developmental programmes which can now drive cell transformation and cancer initiation, and later cancer progression and metastasis. Some of the non-genetic factors that may also favour cancerization are dysregulation in epithelial-mesenchymal interactions, in cell-to-cell communication, in extracellular matrix turnover, in extracellular matrix-to-cell interactions and in mechanotransduction pathways. Persistent increase in extracellular matrix stiffness, for whatever reason, has been shown to play an important role in cell transformation, and later in cancer cell invasion. In this article we review certain cell regulatory networks driving carcinogenesis, focussing on the role of mechanical stresses modulating structure and function of cells and their extracellular matrices.

An Asynchronous Recurrent Network of Cellular Automaton-Based Neurons and Its Reproduction of Spiking Neural Network Activities.

PubMed

Matsubara, Takashi; Torikai, Hiroyuki

2016-04-01

Modeling and implementation approaches for the reproduction of input-output relationships in biological nervous tissues contribute to the development of engineering and clinical applications. However, because of high nonlinearity, the traditional modeling and implementation approaches encounter difficulties in terms of generalization ability (i.e., performance when reproducing an unknown data set) and computational resources (i.e., computation time and circuit elements). To overcome these difficulties, asynchronous cellular automaton-based neuron (ACAN) models, which are described as special kinds of cellular automata that can be implemented as small asynchronous sequential logic circuits have been proposed. This paper presents a novel type of such ACAN and a theoretical analysis of its excitability. This paper also presents a novel network of such neurons, which can mimic input-output relationships of biological and nonlinear ordinary differential equation model neural networks. Numerical analyses confirm that the presented network has a higher generalization ability than other major modeling and implementation approaches. In addition, Field-Programmable Gate Array-implementations confirm that the presented network requires lower computational resources.

A Low-cost 4 Bit, 10 Giga-samples-per-second Analog-to-digital Converter Printed Circuit Board Assembly for FPGA-based Backends

NASA Astrophysics Data System (ADS)

Jiang, Homin; Yu, Chen-Yu; Kubo, Derek; Chen, Ming-Tang; Guzzino, Kim

2016-11-01

In this study, a 4 bit, 10 giga-samples-per-second analog-to-digital converter (ADC) printed circuit board assembly (PCBA) was designed, manufactured, and characterized for digitizing radio telescopes. For this purpose, an Adsantec ANST7120A-KMA flash ADC chip was used. Together with the field-programmable gate array platform, developed by the Collaboration for Astronomy Signal Processing and Electronics Research community, the PCBA enables data acquisition with a wide bandwidth and simplifies the intermediate frequency section. In the current version, the PCBA and the chip exhibit an analog bandwidth of 10 GHz (3 dB loss) and 20 GHz, respectively, which facilitates second, third, and even fourth Nyquist sampling. The following average performance parameters were obtained from the first and second Nyquist zones of the three boards: a spurious-free dynamic range of 31.35/30.45 dB, a signal-to-noise and distortion ratio of 22.95/21.83 dB, and an effective number of bits of 3.65/3.43, respectively.

Hardware Prototyping of Neural Network based Fetal Electrocardiogram Extraction

NASA Astrophysics Data System (ADS)

Hasan, M. A.; Reaz, M. B. I.

2012-01-01

The aim of this paper is to model the algorithm for Fetal ECG (FECG) extraction from composite abdominal ECG (AECG) using VHDL (Very High Speed Integrated Circuit Hardware Description Language) for FPGA (Field Programmable Gate Array) implementation. Artificial Neural Network that provides efficient and effective ways of separating FECG signal from composite AECG signal has been designed. The proposed method gives an accuracy of 93.7% for R-peak detection in FHR monitoring. The designed VHDL model is synthesized and fitted into Altera's Stratix II EP2S15F484C3 using the Quartus II version 8.0 Web Edition for FPGA implementation.

Quorum-Sensing Signal-Response Systems in Gram-Negative Bacteria

PubMed Central

Papenfort, Kai; Bassler, Bonnie

2016-01-01

Abstract / Preface Bacteria use quorum sensing to orchestrate gene expression programmes that underlie collective behaviours. Quorum sensing relies on the production, release, detection and group-level response to extracellular signalling molecules, which are called autoinducers. Recent work has discovered new autoinducers in Gram-negative bacteria, shown how these molecules are recognized by cognate receptors, revealed new regulatory components that are embedded in canonical signalling circuits and identified novel regulatory network designs. In this Review we examine how, together, these features of quorum sensing signal–response systems combine to control collective behaviours in Gram-negative bacteria and we discuss the implications for host–microbial associations and antibacterial therapy. PMID:27510864

Dynamic analyses, FPGA implementation and engineering applications of multi-butterfly chaotic attractors generated from generalised Sprott C system

NASA Astrophysics Data System (ADS)

Lai, Qiang; Zhao, Xiao-Wen; Rajagopal, Karthikeyan; Xu, Guanghui; Akgul, Akif; Guleryuz, Emre

2018-01-01

This paper considers the generation of multi-butterfly chaotic attractors from a generalised Sprott C system with multiple non-hyperbolic equilibria. The system is constructed by introducing an additional variable whose derivative has a switching function to the Sprott C system. It is numerically found that the system creates two-, three-, four-, five-butterfly attractors and any other multi-butterfly attractors. First, the dynamic analyses of multi-butterfly chaotic attractors are presented. Secondly, the field programmable gate array implementation, electronic circuit realisation and random number generator are done with the multi-butterfly chaotic attractors.

General-Purpose Serial Interface For Remote Control

NASA Technical Reports Server (NTRS)

Busquets, Anthony M.; Gupton, Lawrence E.

1990-01-01

Computer controls remote television camera. General-purpose controller developed to serve as interface between host computer and pan/tilt/zoom/focus functions on series of automated video cameras. Interface port based on 8251 programmable communications-interface circuit configured for tristated outputs, and connects controller system to any host computer with RS-232 input/output (I/O) port. Accepts byte-coded data from host, compares them with prestored codes in read-only memory (ROM), and closes or opens appropriate switches. Six output ports control opening and closing of as many as 48 switches. Operator controls remote television camera by speaking commands, in system including general-purpose controller.

Processing circuitry for single channel radiation detector

NASA Technical Reports Server (NTRS)

Holland, Samuel D. (Inventor); Delaune, Paul B. (Inventor); Turner, Kathryn M. (Inventor)

2009-01-01

Processing circuitry is provided for a high voltage operated radiation detector. An event detector utilizes a comparator configured to produce an event signal based on a leading edge threshold value. A preferred event detector does not produce another event signal until a trailing edge threshold value is satisfied. The event signal can be utilized for counting the number of particle hits and also for controlling data collection operation for a peak detect circuit and timer. The leading edge threshold value is programmable such that it can be reprogrammed by a remote computer. A digital high voltage control is preferably operable to monitor and adjust high voltage for the detector.

Theoretical lower bounds for parallel pipelined shift-and-add constant multiplications with n-input arithmetic operators

NASA Astrophysics Data System (ADS)

Cruz Jiménez, Miriam Guadalupe; Meyer Baese, Uwe; Jovanovic Dolecek, Gordana

2017-12-01

New theoretical lower bounds for the number of operators needed in fixed-point constant multiplication blocks are presented. The multipliers are constructed with the shift-and-add approach, where every arithmetic operation is pipelined, and with the generalization that n-input pipelined additions/subtractions are allowed, along with pure pipelining registers. These lower bounds, tighter than the state-of-the-art theoretical limits, are particularly useful in early design stages for a quick assessment in the hardware utilization of low-cost constant multiplication blocks implemented in the newest families of field programmable gate array (FPGA) integrated circuits.

The latency validation of the optical link for the ATLAS Liquid Argon Calorimeter Phase-I trigger upgrade

NASA Astrophysics Data System (ADS)

Deng, B.; Xiao, L.; Zhao, X.; Baker, E.; Gong, D.; Guo, D.; He, H.; Hou, S.; Liu, C.; Liu, T.; Sun, Q.; Thomas, J.; Wang, J.; Xiang, A. C.; Yang, D.; Ye, J.; Zhou, W.

2018-05-01

Two optical data link data transmission Application Specific Integrated Circuits (ASICs), the baseline and its backup, have been designed for the ATLAS Liquid Argon (LAr) Calorimeter Phase-I trigger upgrade. The latency of each ASIC and that of its corresponding receiver implemented in a back-end Field-Programmable Gate Array (FPGA) are critical specifications. In this paper, we present the latency measurements and simulation of two ASICs. The measurement results indicate that both ASICs achieve their design goals and meet the latency specifications. The consistency between the simulation and measurements validates the ASIC latency characterization.

Single Event Effects Test Results for Advanced Field Programmable Gate Arrays

NASA Technical Reports Server (NTRS)

Allen, Gregory R.; Swift, Gary M.

2006-01-01

Reconfigurable Field Programmable Gate Arrays (FPGAs) from Altera and Actel and an FPGA-based quick-turnApplication Specific Integrated Circuit (ASIC) from Altera were subjected to single-event testing using heavy ions. Both Altera devices (Stratix II and HardCopy II) exhibited a low latchup threshold (below an LET of 3 MeV-cm2/mg) and thus are not recommended for applications in the space radiation environment. The flash-based Actel ProASIC Plus device did not exhibit latchup to an effective LET of 75 MeV-cm2/mg at room temperature. In addition, these tests did not show flash cell charge loss (upset) or retention damage. Upset characterization of the design-level flip-flops yielded an LET threshold below 10 MeV-cm2/mg and a high LET cross section of about lxlO-6 cm2/bit for storing ones and about lxl0-7 cm2/bit for storing zeros . Thus, the ProASIC device may be suitable for critical flight applications with appropriate triple modular redundancy mitigation techniques.

A 4 μW/Ch analog front-end module with moderate inversion and power-scalable sampling operation for 3-D neural microsystems.

PubMed

Al-Ashmouny, Khaled M; Chang, Sun-Il; Yoon, Euisik

2012-10-01

We report an analog front-end prototype designed in 0.25 μm CMOS process for hybrid integration into 3-D neural recording microsystems. For scaling towards massive parallel neural recording, the prototype has investigated some critical circuit challenges in power, area, interface, and modularity. We achieved extremely low power consumption of 4 μW/channel, optimized energy efficiency using moderate inversion in low-noise amplifiers (K of 5.98 × 10⁸ or NEF of 2.9), and minimized asynchronous interface (only 2 per 16 channels) for command and data capturing. We also implemented adaptable operations including programmable-gain amplification, power-scalable sampling (up to 50 kS/s/channel), wide configuration range (9-bit) for programmable gain and bandwidth, and 5-bit site selection capability (selecting 16 out of 128 sites). The implemented front-end module has achieved a reduction in noise-energy-area product by a factor of 5-25 times as compared to the state-of-the-art analog front-end approaches reported to date.

Programmable computing with a single magnetoresistive element

NASA Astrophysics Data System (ADS)

Ney, A.; Pampuch, C.; Koch, R.; Ploog, K. H.

2003-10-01

The development of transistor-based integrated circuits for modern computing is a story of great success. However, the proved concept for enhancing computational power by continuous miniaturization is approaching its fundamental limits. Alternative approaches consider logic elements that are reconfigurable at run-time to overcome the rigid architecture of the present hardware systems. Implementation of parallel algorithms on such `chameleon' processors has the potential to yield a dramatic increase of computational speed, competitive with that of supercomputers. Owing to their functional flexibility, `chameleon' processors can be readily optimized with respect to any computer application. In conventional microprocessors, information must be transferred to a memory to prevent it from getting lost, because electrically processed information is volatile. Therefore the computational performance can be improved if the logic gate is additionally capable of storing the output. Here we describe a simple hardware concept for a programmable logic element that is based on a single magnetic random access memory (MRAM) cell. It combines the inherent advantage of a non-volatile output with flexible functionality which can be selected at run-time to operate as an AND, OR, NAND or NOR gate.

Design and implementation of a reconfigurable mixed-signal SoC based on field programmable analog arrays

NASA Astrophysics Data System (ADS)

Liu, Lintao; Gao, Yuhan; Deng, Jun

2017-11-01

This work presents a reconfigurable mixed-signal system-on-chip (SoC), which integrates switched-capacitor-based field programmable analog arrays (FPAA), analog-to-digital converter (ADC), digital-to-analog converter, digital down converter , digital up converter, 32-bit reduced instruction-set computer central processing unit (CPU) and other digital IPs on a single chip with 0.18 μm CMOS technology. The FPAA intellectual property could be reconfigured as different function circuits, such as gain amplifier, divider, sine generator, and so on. This single-chip integrated mixed-signal system is a complete modern signal processing system, occupying a die area of 7 × 8 mm 2 and consuming 719 mW with a clock frequency of 150 MHz for CPU and 200 MHz for ADC/DAC. This SoC chip can help customers to shorten design cycles, save board area, reduce the system power consumption and depress the system integration risk, which would afford a big prospect of application for wireless communication. Project supported by the National High Technology and Development Program of China (No. 2012AA012303).

Microwave metamaterials—from passive to digital and programmable controls of electromagnetic waves

NASA Astrophysics Data System (ADS)

Cui, Tie Jun

2017-08-01

Since 2004, my group at Southeast University has been carrying out research into microwave metamaterials, which are classified into three catagories: metamaterials based on the effective medium model, plasmonic metamaterials for spoof surface plasmon polaritons (SPPs), and coding and programmable metamaterials. For effective-medium metamaterials, we have developed a general theory to accurately describe effective permittivity and permeability in semi-analytical forms, from which we have designed and realized a three dimensional (3D) wideband ground-plane invisibility cloak, a free-space electrostatic invisibility cloak, an electromagnetic black hole, optical/radar illusions, and radially anisotropic zero-index metamaterial for omni-directional radiation and a nearly perfect power combination of source array, etc. We have also considered the engineering applications of microwave metamaterials, such as a broadband and low-loss 3D transformation-optics lens for wide-angle scanning, a 3D planar gradient-index lens for high-gain radiations, and a random metasurface for reducing radar cross sections. In the area of plasmonic metamaterials, we proposed an ultrathin, narrow, and flexible corrugated metallic strip to guide SPPs with a small bending loss and radiation loss, from which we designed and realized a series of SPP passive devices (e.g. power divider, coupler, filter, and resonator) and active devices (e.g. amplifier and duplexer). We also showed a significant feature of the ultrathin SPP waveguide in overcoming the challenge of signal integrity in traditional integrated circuits, which will help build a high-performance SPP wireless communication system. In the area of coding and programmable metamaterials, we proposed a new measure to describe a metamaterial from the viewpoint of information theory. We have illustrated theoretically and experimentally that coding metamaterials composed of digital units can be controlled by coding sequences, leading to different functions. We realised that when the digital state of a coding unit is controlled by a field programmable gate array, the programmable metamaterial, which is capable of manipulating electromagnetic waves in real time, can generate many different functions.

Integration and manufacture of multifunctional planar lightwave circuits

NASA Astrophysics Data System (ADS)

Lipscomb, George F.; Ticknor, Anthony J.; Stiller, Marc A.; Chen, Wenjie; Schroeter, Paul

2001-11-01

The demands of exponentially growing Internet traffic, coupled with the advent of Dense Wavelength Division Multiplexing (DWDM) fiber optic systems to meet those demands, have triggered a revolution in the telecommunications industry. This dramatic change has been built upon, and has driven, improvements in fiber optic component technology. The next generation of systems for the all optical network will require higher performance components coupled with dramatically lower costs. One approach to achieve significantly lower costs per function is to employ Planar Lightwave Circuits (PLC) to integrate multiple optical functions in a single package. PLCs are optical circuits laid out on a silicon wafer, and are made using tools and techniques developed to extremely high levels by the semi-conductor industry. In this way multiple components can be fabricated and interconnected at once, significantly reducing both the manufacturing and the packaging/assembly costs. Currently, the predominant commercial application of PLC technology is arrayed-waveguide gratings (AWG's) for multiplexing and demultiplexing multiple wavelength channels in a DWDM system. Although this is generally perceived as a single-function device, it can be performing the function of more than 100 discrete fiber-optic components and already represents a considerable degree of integration. Furthermore, programmable functions such as variable-optical attenuators (VOAs) and switches made with compatible PLC technology are now moving into commercial production. In this paper, we present results on the integration of active and passive functions together using PLC technology, e.g. a 40 channel AWG multiplexer with 40 individually controllable VOAs.

A Bidirectional Neural Interface IC with Chopper Stabilized BioADC Array and Charge Balanced Stimulator

PubMed Central

Greenwald, Elliot; So, Ernest; Wang, Qihong; Mollazadeh, Mohsen; Maier, Christoph; Etienne-Cummings, Ralph; Cauwenberghs, Gert; Thakor, Nitish

2016-01-01

We present a bidirectional neural interface with a 4-channel biopotential analog-to-digital converter (bioADC) and a 4-channel current-mode stimulator in 180nm CMOS. The bioADC directly transduces microvolt biopotentials into a digital representation without a voltage-amplification stage. Each bioADC channel comprises a continuous-time first-order ΔΣ modulator with a chopper-stabilized OTA input and current feedback, followed by a second-order comb-filter decimator with programmable oversampling ratio. Each stimulator channel contains two independent digital-to-analog converters for anodic and cathodic current generation. A shared calibration circuit matches the amplitude of the anodic and cathodic currents for charge balancing. Powered from a 1.5V supply, the analog and digital circuits in each recording channel draw on average 1.54 μA and 2.13 μA of supply current, respectively. The bioADCs achieve an SNR of 58 dB and a SFDR of >70 dB, for better than 9-b ENOB. Intracranial EEG recordings from an anesthetized rat are shown and compared to simultaneous recordings from a commercial reference system to validate performance in-vivo. Additionally, we demonstrate bidirectional operation by recording cardiac modulation induced through vagus nerve stimulation, and closed-loop control of cardiac rhythm. The micropower operation, direct digital readout, and integration of electrical stimulation circuits make this interface ideally suited for closed-loop neuromodulation applications. PMID:27845676

All-Digital Time-Domain CMOS Smart Temperature Sensor with On-Chip Linearity Enhancement.

PubMed

Chen, Chun-Chi; Chen, Chao-Lieh; Lin, Yi

2016-01-30

This paper proposes the first all-digital on-chip linearity enhancement technique for improving the accuracy of the time-domain complementary metal-oxide semiconductor (CMOS) smart temperature sensor. To facilitate on-chip application and intellectual property reuse, an all-digital time-domain smart temperature sensor was implemented using 90 nm Field Programmable Gate Arrays (FPGAs). Although the inverter-based temperature sensor has a smaller circuit area and lower complexity, two-point calibration must be used to achieve an acceptable inaccuracy. With the help of a calibration circuit, the influence of process variations was reduced greatly for one-point calibration support, reducing the test costs and time. However, the sensor response still exhibited a large curvature, which substantially affected the accuracy of the sensor. Thus, an on-chip linearity-enhanced circuit is proposed to linearize the curve and achieve a new linearity-enhanced output. The sensor was implemented on eight different Xilinx FPGA using 118 slices per sensor in each FPGA to demonstrate the benefits of the linearization. Compared with the unlinearized version, the maximal inaccuracy of the linearized version decreased from 5 °C to 2.5 °C after one-point calibration in a range of -20 °C to 100 °C. The sensor consumed 95 μW using 1 kSa/s. The proposed linearity enhancement technique significantly improves temperature sensing accuracy, avoiding costly curvature compensation while it is fully synthesizable for future Very Large Scale Integration (VLSI) system.

All-Digital Time-Domain CMOS Smart Temperature Sensor with On-Chip Linearity Enhancement

PubMed Central

Chen, Chun-Chi; Chen, Chao-Lieh; Lin, Yi

2016-01-01

This paper proposes the first all-digital on-chip linearity enhancement technique for improving the accuracy of the time-domain complementary metal-oxide semiconductor (CMOS) smart temperature sensor. To facilitate on-chip application and intellectual property reuse, an all-digital time-domain smart temperature sensor was implemented using 90 nm Field Programmable Gate Arrays (FPGAs). Although the inverter-based temperature sensor has a smaller circuit area and lower complexity, two-point calibration must be used to achieve an acceptable inaccuracy. With the help of a calibration circuit, the influence of process variations was reduced greatly for one-point calibration support, reducing the test costs and time. However, the sensor response still exhibited a large curvature, which substantially affected the accuracy of the sensor. Thus, an on-chip linearity-enhanced circuit is proposed to linearize the curve and achieve a new linearity-enhanced output. The sensor was implemented on eight different Xilinx FPGA using 118 slices per sensor in each FPGA to demonstrate the benefits of the linearization. Compared with the unlinearized version, the maximal inaccuracy of the linearized version decreased from 5 °C to 2.5 °C after one-point calibration in a range of −20 °C to 100 °C. The sensor consumed 95 μW using 1 kSa/s. The proposed linearity enhancement technique significantly improves temperature sensing accuracy, avoiding costly curvature compensation while it is fully synthesizable for future Very Large Scale Integration (VLSI) system. PMID:26840316

Optical Characterization of Tissue Phantoms Using a Silicon Integrated fdNIRS System on Chip.

PubMed

Sthalekar, Chirag C; Miao, Yun; Koomson, Valencia Joyner

2017-04-01

An interface circuit with signal processing and digitizing circuits for a high frequency, large area avalanche photodiode (APD) has been integrated in a 130 nm BiCMOS chip. The system enables the absolute oximetry of tissue using frequency domain Near Infrared Spectroscopy (fdNIRS). The system measures the light absorbed and scattered by the tissue by measuring the reduction in the amplitude of signal and phase shift introduced between the light source and detector which are placed a finite distance away from each other. The received 80 MHz RF signal is downconverted to a low frequency and amplified using a heterodyning scheme. The front-end transimpedance amplifier has a 3-level programmable gain that increases the dynamic range to 60 dB. The phase difference between an identical reference channel and the optical channel is measured with a 0.5° accuracy. The detectable current range is [Formula: see text] and with a 40 A/W reponsivity using the APD, power levels as low as 500 pW can be detected. Measurements of the absorption and reduced scattering coefficients of solid tissue phantoms using this system are compared with those using a commercial instrument with differences within 30%. Measurement of a milk based liquid tissue phantom show an increase in absorption coefficient with addition of black ink. The miniaturized circuit serves as an efficiently scalable system for multi-site detection for applications in neonatal cerebral oximetry and optical mammography.

Multilevel Regulation of Bacterial Gene Expression with the Combined STAR and Antisense RNA System.

PubMed

Lee, Young Je; Kim, Soo-Jung; Moon, Tae Seok

2018-03-16

Synthetic small RNA regulators have emerged as a versatile tool to predictably control bacterial gene expression. Owing to their simple design principles, small size, and highly orthogonal behavior, these engineered genetic parts have been incorporated into genetic circuits. However, efforts to achieve more sophisticated cellular functions using RNA regulators have been hindered by our limited ability to integrate different RNA regulators into complex circuits. Here, we present a combined RNA regulatory system in Escherichia coli that uses small transcription activating RNA (STAR) and antisense RNA (asRNA) to activate or deactivate target gene expression in a programmable manner. Specifically, we demonstrated that the activated target output by the STAR system can be deactivated by expressing two different types of asRNAs: one binds to and sequesters the STAR regulator, affecting the transcription process, while the other binds to the target mRNA, affecting the translation process. We improved deactivation efficiencies (up to 96%) by optimizing each type of asRNA and then integrating the two optimized asRNAs into a single circuit. Furthermore, we demonstrated that the combined STAR and asRNA system can control gene expression in a reversible way and can regulate expression of a gene in the genome. Lastly, we constructed and simultaneously tested two A AND NOT B logic gates in the same cell to show sophisticated multigene regulation by the combined system. Our approach establishes a methodology for integrating multiple RNA regulators to rationally control multiple genes.

One-Step Laser Patterned Highly Uniform Reduced Graphene Oxide Thin Films for Circuit-Enabled Tattoo and Flexible Humidity Sensor Application.

PubMed

Park, Rowoon; Kim, Hyesu; Lone, Saifullah; Jeon, Sangheon; Kwon, Young Woo; Shin, Bosung; Hong, Suck Won

2018-06-06

The conversion of graphene oxide (GO) into reduced graphene oxide (rGO) is imperative for the electronic device applications of graphene-based materials. Efficient and cost-effective fabrication of highly uniform GO films and the successive reduction into rGO on a large area is still a cumbersome task through conventional protocols. Improved film casting of GO sheets on a polymeric substrate with quick and green reduction processes has a potential that may establish a path to the practical flexible electronics. Herein, we report a facile deposition process of GO on flexible polymer substrates to create highly uniform thin films over a large area by a flow-enabled self-assembly approach. The self-assembly of GO sheets was successfully performed by dragging the trapped solution of GO in confined geometry, which consisted of an upper stationary blade and a lower moving substrate on a motorized translational stage. The prepared GO thin films could be selectively reduced and facilitated from the simple laser direct writing process for programmable circuit printing with the desired configuration and less sample damage due to the non-contact mode operation without the use of photolithography, toxic chemistry, or high-temperature reduction methods. Furthermore, two different modes of the laser operating system for the reduction of GO films turned out to be valuable for the construction of novel graphene-based high-throughput electrical circuit boards compatible with integrating electronic module chips and flexible humidity sensors.

A 1024×768-12μm Digital ROIC for uncooled microbolometer FPAs

NASA Astrophysics Data System (ADS)

Eminoglu, Selim

2017-02-01

This paper reports the development of a new digital microbolometer Readout Integrated Circuit (D-ROIC), called MT10212BD. It has a format of 1024 × 768 (XGA) and a pixel pitch of 12μm. MT10212BD is Mikro Tasarim's second 12μm pitch microbolometer ROIC, which is developed specifically for surface micro machined microbolometer detector arrays with small pixel pitch using high-TCR pixel materials, such as VOx and a Si. MT10212BD has an alldigital system on-chip architecture, which generates programmable timing and biasing, and performs 14-bit analog to digital conversion (ADC). The signal processing chain in the ROIC is composed of pixel bias circuitry, integrator based programmable gain amplifier followed by column parallel ADC circuitry. MT10212BD has a serial programming interface that can be used to configure the programmable ROIC features and to load the Non-Uniformity-Correction (NUC) date to the ROIC. MT10212BD has a total of 8 high-speed serial digital video outputs, which can be programmed to operate in the 2, 4, and 8-output modes and can support frames rates above 60 fps. The high-speed serial digital outputs supports data rates as high as 400 Mega-bits/s, when operated at 50 MHz system clock frequency. There is an on-chip phase-locked-loop (PLL) based timing circuitry to generate the high speed clocks used in the ROIC. The ROIC is designed to support pixel resistance values ranging from 30KΩ to 90kΩ, with a nominal value of 60KΩ. The ROIC has a globally programmable gain in the column readout, which can be adjusted based on the detector resistance value.

Eight-Channel Continuous Timer

NASA Technical Reports Server (NTRS)

Cole, Steven

2004-01-01

A custom laboratory electronic timer circuit measures the durations of successive cycles of nominally highly stable input clock signals in as many as eight channels, for the purpose of statistically quantifying the small instabilities of these signals. The measurement data generated by this timer are sent to a personal computer running software that integrates the measurements to form a phase residual for each channel and uses the phase residuals to compute Allan variances for each channel. (The Allan variance is a standard statistical measure of instability of a clock signal.) Like other laboratory clock-cycle-measuring circuits, this timer utilizes an externally generated reference clock signal having a known frequency (100 MHz) much higher than the frequencies of the input clock signals (between 100 and 120 Hz). It counts the number of reference-clock cycles that occur between successive rising edges of each input clock signal of interest, thereby affording a measurement of the input clock-signal period to within the duration (10 ns) of one reference clock cycle. Unlike typical prior laboratory clock-cycle-measuring circuits, this timer does not skip some cycles of the input clock signals. The non-cycle-skipping feature is an important advantage because in applications that involve integration of measurements over long times for characterizing nominally highly stable clock signals, skipping cycles can degrade accuracy. The timer includes a field-programmable gate array that functions as a 20-bit counter running at the reference clock rate of 100 MHz. The timer also includes eight 20-bit latching circuits - one for each channel - at the output terminals of the counter. Each transition of an input signal from low to high causes the corresponding latching circuit to latch the count at that instant. Each such transition also sets a status flip-flop circuit to indicate the presence of the latched count. A microcontroller reads the values of all eight status flipflops and then reads the latched count for each channel for which the flip-flop indicates the presence of a count. Reading the count for each channel automatically causes the flipflop of that channel to be reset. The microcontroller places the counts in time order, identifies the channel number for each count, and transmits these data to the personal computer.

Compliant heterogeneous assemblies of micro-VCSELs as a new materials platform for integrated optoelectronics

NASA Astrophysics Data System (ADS)

Kang, Dongseok; Lee, Sung-Min; Kwong, Anthony; Yoon, Jongseung

2015-03-01

Despite many unique advantages, vertical cavity surface emitting lasers (VCSELs) have been available mostly on rigid, planar wafers over restricted areas, thereby limiting their usage for applications that can benefit from large-scale, programmable assemblies, hybrid integration with dissimilar materials and devices, or mechanically flexible constructions. Here, materials design and fabrication strategies that address these limitations of conventional VCSELs are presented. Specialized design of epitaxial materials and etching processes, together with printing-based deterministic assemblies and substrate thermal engineering, enabled defect-free release of microscale VCSELs and their device- and circuit-level implementation on non-native, flexible substrates with performance comparable to devices on the growth substrate.

A Synthetic Circuit for Mercury Bioremediation Using Self-Assembling Functional Amyloids.

PubMed

Tay, Pei Kun R; Nguyen, Peter Q; Joshi, Neel S

2017-10-20

Synthetic biology approaches to bioremediation are a key sustainable strategy to leverage the self-replicating and programmable aspects of biology for environmental stewardship. The increasing spread of anthropogenic mercury pollution into our habitats and food chains is a pressing concern. Here, we explore the use of programmed bacterial biofilms to aid in the sequestration of mercury. We demonstrate that by integrating a mercury-responsive promoter and an operon encoding a mercury-absorbing self-assembling extracellular protein nanofiber, we can engineer bacteria that can detect and sequester toxic Hg 2+ ions from the environment. This work paves the way for the development of on-demand biofilm living materials that can operate autonomously as heavy-metal absorbents.

Logic Design Pathology and Space Flight Electronics

NASA Technical Reports Server (NTRS)

Katz, Richard; Barto, Rod L.; Erickson, K.

1997-01-01

Logic design errors have been observed in space flight missions and the final stages of ground test. The technologies used by designers and their design/analysis methodologies will be analyzed. This will give insight to the root causes of the failures. These technologies include discrete integrated circuit based systems, systems based on field and mask programmable logic, and the use computer aided engineering (CAE) systems. State-of-the-art (SOTA) design tools and methodologies will be analyzed with respect to high-reliability spacecraft design and potential pitfalls are discussed. Case studies of faults from large expensive programs to "smaller, faster, cheaper" missions will be used to explore the fundamental reasons for logic design problems.

Wide-Range Filter-Based Sinusoidal Wave Synthesizer for Electrochemical Impedance Spectroscopy Measurements.

PubMed

Chia-Ling Wei; Yi-Wen Wang; Bin-Da Liu

2014-06-01

A filter-based wide-range programmable sinusoidal wave synthesizer for electrochemical impedance spectroscopy measurement is proposed. The adopted filter is implemented with switched-capacitor circuits, so its corner frequency is accurate and adjustable by changing its switching frequency. The proposed sine wave synthesizer is implemented by using a 0.35 μm 2P4M 3.3 V mixed-signal polycide process. According to the measured results, the output frequency of the proposed synthesizer is 40 mHz-40 kHz . The measured total harmonic distortion is 0.073% at 10 Hz and 0.075% at 10 kHz, both of which are better than that of a typical function generator.

FPGA implementation of current-sharing strategy for parallel-connected SEPICs

NASA Astrophysics Data System (ADS)

Ezhilarasi, A.; Ramaswamy, M.

2016-01-01

The attempt echoes to evolve an equal current-sharing algorithm over a number of single-ended primary inductance converters connected in parallel. The methodology involves the development of state-space model to predict the condition for the existence of a stable equilibrium portrait. It acquires the role of a variable structure controller to guide the trajectory, with a view to circumvent the circuit non-linearities and arrive at a stable performance through a preferred operating range. The design elicits an acceptable servo and regulatory characteristics, the desired time response and ensures regulation of the load voltage. The simulation results validated through a field programmable gate array-based prototype serves to illustrate its suitability for present-day applications.

System for energy harvesting and/or generation, storage, and delivery

NASA Technical Reports Server (NTRS)

DeGreeff, Jenniffer Leigh (Inventor); Trainor, John T. (Inventor); Fleig, Patrick Franz (Inventor); Lakeman, Charles D. E. (Inventor)

2011-01-01

A device and method for harvesting, generating, storing, and delivering energy to a load, particularly for remote or inaccessible applications. The device preferably comprises one or more energy sources, at least one supercapacitor, at least one rechargeable battery, and a controller. The charging of the energy storage devices and the delivery of power to the load is preferably dynamically varied to maximize efficiency. A low power consumption charge pump circuit is preferably employed to collect power from low power energy sources while also enabling the delivery of higher voltage power to the load. The charging voltage is preferably programmable, enabling one device to be used for a wide range of specific applications.

System for energy harvesting and/or generation, storage, and delivery

NASA Technical Reports Server (NTRS)

DeGreeff, Jenniffer Leigh (Inventor); Trainor, John T. (Inventor); Fleig, Patrick Franz (Inventor); Lakeman, Charles D. E. (Inventor)

2010-01-01

A device and method for harvesting, generating, storing, and delivering energy to a load, particularly for remote or inaccessible applications. The device preferably comprises one or more energy sources, at least one supercapacitor, at least one rechargeable battery, and a controller. The charging of the energy storage devices and the delivery of power to the load is preferably dynamically varied to maximize efficiency. A low power consumption charge pump circuit is preferably employed to collect power from low power energy sources while also enabling the delivery of higher voltage power to the load. The charging voltage is preferably programmable, enabling one device to be used for a wide range of specific applications.

Design of an Oximeter Based on LED-LED Configuration and FPGA Technology

PubMed Central

Stojanovic, Radovan; Karadaglic, Dejan

2013-01-01

A fully digital photoplethysmographic (PPG) sensor and actuator has been developed. The sensing circuit uses one Light Emitting Diode (LED) for emitting light into human tissue and one LED for detecting the reflectance light from human tissue. A Field Programmable Gate Array (FPGA) is used to control the LEDs and determine the PPG and Blood Oxygen Saturation (SpO2). The configurations with two LEDs and four LEDs are developed for measuring PPG signal and Blood Oxygen Saturation (SpO2). N-LEDs configuration is proposed for multichannel SpO2 measurements. The approach resulted in better spectral sensitivity, increased and adjustable resolution, reduced noise, small size, low cost and low power consumption. PMID:23291575

Single-Event Transient Testing of Low Dropout PNP Series Linear Voltage Regulators

NASA Technical Reports Server (NTRS)

Adell, Philippe; Allen, Gregory

2013-01-01

As demand for high-speed, on-board, digital-processing integrated circuits on spacecraft increases (field-programmable gate arrays and digital signal processors in particular), the need for the next generation point-of-load (POL) regulator becomes a prominent design issue. Shrinking process nodes have resulted in core rails dropping to values close to 1.0 V, drastically reducing margin to standard switching converters or regulators that power digital ICs. The goal of this task is to perform SET characterization of several commercial POL converters, and provide a discussion of the impact of these results to state-of-the-art digital processing IC through laser and heavy ion testing

Fully digital routing logic for single-photon avalanche diode arrays in highly efficient time-resolved imaging

NASA Astrophysics Data System (ADS)

Cominelli, Alessandro; Acconcia, Giulia; Ghioni, Massimo; Rech, Ivan

2018-03-01

Time-correlated single-photon counting (TCSPC) is a powerful optical technique, which permits recording fast luminous signals with picosecond precision. Unfortunately, given its repetitive nature, TCSPC is recognized as a relatively slow technique, especially when a large time-resolved image has to be recorded. In recent years, there has been a fast trend toward the development of TCPSC imagers. Unfortunately, present systems still suffer from a trade-off between number of channels and performance. Even worse, the overall measurement speed is still limited well below the saturation of the transfer bandwidth toward the external processor. We present a routing algorithm that enables a smart connection between a 32×32 detector array and five shared high-performance converters able to provide an overall conversion rate up to 10 Gbit/s. The proposed solution exploits a fully digital logic circuit distributed in a tree structure to limit the number and length of interconnections, which is a major issue in densely integrated circuits. The behavior of the logic has been validated by means of a field-programmable gate array, while a fully integrated prototype has been designed in 180-nm technology and analyzed by means of postlayout simulations.

Design and construction of a high frame rate imaging system

NASA Astrophysics Data System (ADS)

Wang, Jing; Waugaman, John L.; Liu, Anjun; Lu, Jian-Yu

2002-05-01

A new high frame rate imaging method has been developed recently [Jian-yu Lu, ``2D and 3D high frame rate imaging with limited diffraction beams,'' IEEE Trans. Ultrason. Ferroelectr. Freq. Control 44, 839-856 (1997)]. This method may have a clinical application for imaging of fast moving objects such as human hearts, velocity vector imaging, and low-speckle imaging. To implement the method, an imaging system has been designed. The system consists of one main printed circuit board (PCB) and 16 channel boards (each channel board contains 8 channels), in addition to a set-top box for connections to a personal computer (PC), a front panel board for user control and message display, and a power control and distribution board. The main board contains a field programmable gate array (FPGA) and controls all channels (each channel has also an FPGA). We will report the analog and digital circuit design and simulations, multiplayer PCB designs with commercial software (Protel 99), PCB signal integrity testing and system RFI/EMI shielding, and the assembly and construction of the entire system. [Work supported in part by Grant 5RO1 HL60301 from NIH.

Efficient architecture for spike sorting in reconfigurable hardware.

PubMed

Hwang, Wen-Jyi; Lee, Wei-Hao; Lin, Shiow-Jyu; Lai, Sheng-Ying

2013-11-01

This paper presents a novel hardware architecture for fast spike sorting. The architecture is able to perform both the feature extraction and clustering in hardware. The generalized Hebbian algorithm (GHA) and fuzzy C-means (FCM) algorithm are used for feature extraction and clustering, respectively. The employment of GHA allows efficient computation of principal components for subsequent clustering operations. The FCM is able to achieve near optimal clustering for spike sorting. Its performance is insensitive to the selection of initial cluster centers. The hardware implementations of GHA and FCM feature low area costs and high throughput. In the GHA architecture, the computation of different weight vectors share the same circuit for lowering the area costs. Moreover, in the FCM hardware implementation, the usual iterative operations for updating the membership matrix and cluster centroid are merged into one single updating process to evade the large storage requirement. To show the effectiveness of the circuit, the proposed architecture is physically implemented by field programmable gate array (FPGA). It is embedded in a System-on-Chip (SOC) platform for performance measurement. Experimental results show that the proposed architecture is an efficient spike sorting design for attaining high classification correct rate and high speed computation.

High speed imager test station

DOEpatents

Yates, George J.; Albright, Kevin L.; Turko, Bojan T.

1995-01-01

A test station enables the performance of a solid state imager (herein called a focal plane array or FPA) to be determined at high image frame rates. A programmable waveform generator is adapted to generate clock pulses at determinable rates for clock light-induced charges from a FPA. The FPA is mounted on an imager header board for placing the imager in operable proximity to level shifters for receiving the clock pulses and outputting pulses effective to clock charge from the pixels forming the FPA. Each of the clock level shifters is driven by leading and trailing edge portions of the clock pulses to reduce power dissipation in the FPA. Analog circuits receive output charge pulses clocked from the FPA pixels. The analog circuits condition the charge pulses to cancel noise in the pulses and to determine and hold a peak value of the charge for digitizing. A high speed digitizer receives the peak signal value and outputs a digital representation of each one of the charge pulses. A video system then displays an image associated with the digital representation of the output charge pulses clocked from the FPA. In one embodiment, the FPA image is formatted to a standard video format for display on conventional video equipment.

High speed imager test station

DOEpatents

Yates, G.J.; Albright, K.L.; Turko, B.T.

1995-11-14

A test station enables the performance of a solid state imager (herein called a focal plane array or FPA) to be determined at high image frame rates. A programmable waveform generator is adapted to generate clock pulses at determinable rates for clock light-induced charges from a FPA. The FPA is mounted on an imager header board for placing the imager in operable proximity to level shifters for receiving the clock pulses and outputting pulses effective to clock charge from the pixels forming the FPA. Each of the clock level shifters is driven by leading and trailing edge portions of the clock pulses to reduce power dissipation in the FPA. Analog circuits receive output charge pulses clocked from the FPA pixels. The analog circuits condition the charge pulses to cancel noise in the pulses and to determine and hold a peak value of the charge for digitizing. A high speed digitizer receives the peak signal value and outputs a digital representation of each one of the charge pulses. A video system then displays an image associated with the digital representation of the output charge pulses clocked from the FPA. In one embodiment, the FPA image is formatted to a standard video format for display on conventional video equipment. 12 figs.

A CMOS application-specified-integrated-circuit for 40 GHz high-electron-mobility-transistors automatic biasing

NASA Astrophysics Data System (ADS)

De Matteis, M.; De Blasi, M.; Vallicelli, E. A.; Zannoni, M.; Gervasi, M.; Bau, A.; Passerini, A.; Baschirotto, A.

2017-02-01

This paper presents the design and the experimental results of a CMOS Automatic Control System (ACS) for the biasing of High-Electron-Mobility-Transistors (HEMT). The ACS is the first low-power mixed-signal Application-Specified-Integrated-Circuit (ASIC) able to automatically set and regulate the operating point of an off-chip 6 HEMT Low-Noise-Amplifiers (LNAs), hence it composes a two-chip system (the ACS+LNAs) to be used in the Large Scale Polarization Explorer (LSPE) stratospheric balloon for Cosmic Microwave Background (CMB) signal observation. The hereby presented ACS ASIC provides a reliable instrumentation for gradual and very stable LNAs characterization, switching-on, and operating point (<4 mV accuracy). Moreover, it simplifies the electronic instrumentation needed for biasing the LNAs, since it replaces several off-the-shelf and digital programmable device components. The ASIC prototype has been implemented in a CMOS 0.35 μ m technology (12 mm2 area occupancy). It operates at 4 kHz clock frequency. The power consumption of one-channel ASIC (biasing one LNA) is 3.6 mW, whereas 30 mW are consumed by a single LNA device.

A CMOS application-specified-integrated-circuit for 40 GHz high-electron-mobility-transistors automatic biasing.

PubMed

De Matteis, M; De Blasi, M; Vallicelli, E A; Zannoni, M; Gervasi, M; Bau, A; Passerini, A; Baschirotto, A

2017-02-01

This paper presents the design and the experimental results of a CMOS Automatic Control System (ACS) for the biasing of High-Electron-Mobility-Transistors (HEMT). The ACS is the first low-power mixed-signal Application-Specified-Integrated-Circuit (ASIC) able to automatically set and regulate the operating point of an off-chip 6 HEMT Low-Noise-Amplifiers (LNAs), hence it composes a two-chip system (the ACS+LNAs) to be used in the Large Scale Polarization Explorer (LSPE) stratospheric balloon for Cosmic Microwave Background (CMB) signal observation. The hereby presented ACS ASIC provides a reliable instrumentation for gradual and very stable LNAs characterization, switching-on, and operating point (<4 mV accuracy). Moreover, it simplifies the electronic instrumentation needed for biasing the LNAs, since it replaces several off-the-shelf and digital programmable device components. The ASIC prototype has been implemented in a CMOS 0.35 μm technology (12 mm 2 area occupancy). It operates at 4 kHz clock frequency. The power consumption of one-channel ASIC (biasing one LNA) is 3.6 mW, whereas 30 mW are consumed by a single LNA device.

A digitally controlled AGC loop circuitry for GNSS receiver chip with a binary weighted accurate dB-linear PGA

NASA Astrophysics Data System (ADS)

Gang, Jin; Yiqi, Zhuang; Yue, Yin; Miao, Cui

2015-03-01

A novel digitally controlled automatic gain control (AGC) loop circuitry for the global navigation satellite system (GNSS) receiver chip is presented. The entire AGC loop contains a programmable gain amplifier (PGA), an AGC circuit and an analog-to-digital converter (ADC), which is implemented in a 0.18 μm complementary metal-oxide-semiconductor (CMOS) process and measured. A binary-weighted approach is proposed in the PGA to achieve wide dB-linear gain control with small gain error. With binary-weighted cascaded amplifiers for coarse gain control, and parallel binary-weighted trans-conductance amplifier array for fine gain control, the PGA can provide a 64 dB dynamic range from -4 to 60 dB in 1.14 dB gain steps with a less than 0.15 dB gain error. Based on the Gaussian noise statistic characteristic of the GNSS signal, a digital AGC circuit is also proposed with low area and fast settling. The feed-backward AGC loop occupies an area of 0.27 mm2 and settles within less than 165 μs while consuming an average current of 1.92 mA at 1.8 V.

In vivo voltammetry: from wire to wireless measurements.

PubMed

Crespi, Francesco; Dalessandro, Davide; Annovazzi-Lodi, Valerio; Heidbreder, Christian; Norgia, Michele

2004-12-30

A novel telemetric system based on either differential pulse voltammetry (DPV) or direct current amperometry (DCA) by using a diffused infrared transmission channel is presented. Unlike similar pre-existing instruments based on infrared transmission, the present system works on a single-way communication, thus avoiding problems related to cross-talking between two-way channels. The infrared channel is also immune from electromagnetic interferences from the surrounding environment. Further advancement is the development of an original miniaturised system (dimension 1cm x 1.2 cm x 0.5 cm) with reduced weight (5-6 g), suitable for affixing to the rat head and allowing real time telemetric monitoring using DCA sampling of neurotransmitters such as dopamine or serotonin every 100 ms. The set-up is based on a transmitter (TX) circuit mounted on the animal's head and connected to the electrodes inserted into its brain. The TX circuit generates the proper electrical signals for DPV or DCA, collects the electrical response of the brain and transmits it, via an infrared channel, to a receiving station (RX) interfaced with a personal computer. The PC performs the sampling and elaboration of polarographic traces in a flexible and programmable way.

Ultrasonic resonant piezoelectric actuator with intrinsic torque measurement.

PubMed

Pott, Peter P; Matich, Sebastian; Schlaak, Helmut F

2012-11-01

Piezoelectric ultrasonic actuators are widely used in small-scale actuation systems, in which a closed-loop position control is usually utilized. To save an additional torque sensor, the intrinsic measurement capabilities of the piezoelectric material can be employed. To prove feasibility, a motor setup with clearly separated actuation for the friction and driving forces is chosen. The motor concept is based on resonant ultrasonic vibrations. To assess the effects of the direct piezoelectric effect, a capacitance bridge-type circuit has been selected. Signal processing is done by a measurement card with an integrated field-programmable gate array. The motor is used to drive a winch, and different torques are applied by means of weights to be lifted. Assessing the bridge voltage, a good proportionality to the applied torque of 1.47 mV/mN·m is shown. A hysteresis of 1% has been determined. The chosen motor concept is useful for intrinsic torque measurement. However, it provides drawbacks in terms of limited mechanical performance, wear, and thermal losses because of the soft piezoelectric material. Future work will comprise the application of the method to commercially available piezoelectric actuators as well as the implementation of the measurement circuit in an embedded system.

Effects of Krankcycle Training on Performance and Body Composition in Wheelchair Users.

PubMed

Čichoň, Rostislav; Maszczyk, Adam; Stastny, Petr; Uhlíř, Petr; Petr, Miroslav; Doubrava, Ondřej; Mostowik, Aleksandra; Gołaś, Artur; Cieszczyk, Paweł; Żmijewski, Piotr

2015-11-22

Innovation in training equipment is important for increasing training effectiveness, performance and changes in body composition, especially in wheelchair users with paraplegia. The main objective of a workout session is to induce an adaptation stimulus, which requires overload of involved muscles by voluntary effort, yet this overload may be highly influenced by the size of the spinal cord lesion. Krancykl construction is designed to allow exercise on any wheelchair and with adjustable height or width of crank handles, where even the grip handle may be altered. The aim of this study was to determine the differences in body composition, performance and the rate of perceived exertion (RPE) in paraplegics with a different level of paralyses after a 12 week training programme of a unilateral regime on Krankcycle equipment (a crank machine). The study sample included four men and one women at a different spine lesion level. The 12 weeks programme was successfully completed by four participants, while one subject got injured during the intervention process. Three participants were paraplegics and one was quadriplegic with innervation of the biceps humeri, triceps humeri and deltoideus. The Krankcycle 30 min programme was followed by four other exercises, which were performed after themselves rather than in a circuit training manner as the latter would result in much longer rest periods between exercises, because paraplegics have to be fixed by straps during exercise on hydraulic machines. The RPE after the workout decreased following the twelve week adaptation period.

Effects of Krankcycle Training on Performance and Body Composition in Wheelchair Users

PubMed Central

Čichoň, Rostislav; Maszczyk, Adam; Stastny, Petr; Uhlíř, Petr; Petr, Miroslav; Doubrava, Ondřej; Mostowik, Aleksandra; Gołaś, Artur; Cieszczyk, Paweł; Żmijewski, Piotr

2015-01-01

Innovation in training equipment is important for increasing training effectiveness, performance and changes in body composition, especially in wheelchair users with paraplegia. The main objective of a workout session is to induce an adaptation stimulus, which requires overload of involved muscles by voluntary effort, yet this overload may be highly influenced by the size of the spinal cord lesion. Krancykl construction is designed to allow exercise on any wheelchair and with adjustable height or width of crank handles, where even the grip handle may be altered. The aim of this study was to determine the differences in body composition, performance and the rate of perceived exertion (RPE) in paraplegics with a different level of paralyses after a 12 week training programme of a unilateral regime on Krankcycle equipment (a crank machine). The study sample included four men and one women at a different spine lesion level. The 12 weeks programme was successfully completed by four participants, while one subject got injured during the intervention process. Three participants were paraplegics and one was quadriplegic with innervation of the biceps humeri, triceps humeri and deltoideus. The Krankcycle 30 min programme was followed by four other exercises, which were performed after themselves rather than in a circuit training manner as the latter would result in much longer rest periods between exercises, because paraplegics have to be fixed by straps during exercise on hydraulic machines. The RPE after the workout decreased following the twelve week adaptation period. PMID:26834875

Do previous sports experiences influence the effect of an enrichment programme in basketball skills?

PubMed

Santos, Sara; Mateus, Nuno; Sampaio, Jaime; Leite, Nuno

2017-09-01

The aim of this study was to examine the effect of an enrichment programme in motor, technical and tactical basketball skills, when accounting for the age of youth sport specialisation. Seventy-six college students (age: M = 20.4, SD = 1.9) were allocated according to three different paths: (i) non-structured (n = 14), (ii) early specialisation (n = 34), and (iii) late specialisation (n = 28), according to information previously provided by the participants about the quantity and type of sporting activities performed throughout their sporting careers. Then, the participants of each path were randomly distributed across control and experimental groups. Variables under study included agility, technical skills circuit, as well as tactical actions performed in a 4-on-4 full-court basketball game. The results indicated improvements in the early and late specialisation paths namely in the experimental training groups. However, the late specialisation path revealed larger benefits, in contrast with the non-structured path, which showed less sensitivity to the enrichment programme, mostly sustained in physical literacy and differential learning. Higher improvements were observed in agility, and also in reducing the number of unsuccessful actions performed during the game. Overall, this study provided evidence of how early sports experiences affect basketball skill acquisition and contribute to adapt to new contexts with motor and technical-tactical challenges. In addition, a path supported by late specialisation might present several advantages in sport performance achievement.

A Re-programmable Platform for Dynamic Burn-in Test of Xilinx Virtexll 3000 FPGA for Military and Aerospace Applications

NASA Technical Reports Server (NTRS)

Roosta, Ramin; Wang, Xinchen; Sadigursky, Michael; Tracton, Phil

2004-01-01

Field Programmable Gate Arrays (FPGA) have played increasingly important roles in military and aerospace applications. Xilinx SRAM-based FPGAs have been extensively used in commercial applications. They have been used less frequently in space flight applications due to their susceptibility to single-event upsets. Reliability of these devices in space applications is a concern that has not been addressed. The objective of this project is to design a fully programmable hardware/software platform that allows (but is not limited to) comprehensive static/dynamic burn-in test of Virtex-II 3000 FPGAs, at speed test and SEU test. Conventional methods test very few discrete AC parameters (primarily switching) of a given integrated circuit. This approach will test any possible configuration of the FPGA and any associated performance parameters. It allows complete or partial re-programming of the FPGA and verification of the program by using read back followed by dynamic test. Designers have full control over which functional elements of the FPGA to stress. They can completely simulate all possible types of configurations/functions. Another benefit of this platform is that it allows collecting information on elevation of the junction temperature as a function of gate utilization, operating frequency and functionality. A software tool has been implemented to demonstrate the various features of the system. The software consists of three major parts: the parallel interface driver, main system procedure and a graphical user interface (GUI).

High-Precision Hysteresis Sensing of the Quartz Crystal Inductance-to-Frequency Converter

PubMed Central

Matko, Vojko; Milanović, Miro

2016-01-01

A new method for the automated measurement of the hysteresis of the temperature-compensated inductance-to-frequency converter with a single quartz crystal is proposed. The new idea behind this method is a converter with two programmable analog switches enabling the automated measurement of the converter hysteresis, as well as the temperature compensation of the quartz crystal and any other circuit element. Also used is the programmable timing control device that allows the selection of different oscillating frequencies. In the proposed programmable method two different inductances connected in series to the quartz crystal are switched in a short time sequence, compensating the crystal’s natural temperature characteristics (in the temperature range between 0 and 50 °C). The procedure allows for the measurement of the converter hysteresis at various values of capacitance connected in parallel with the quartz crystal for the converter sensitivity setting at selected inductance. It, furthermore, enables the measurement of hysteresis at various values of inductance at selected parallel capacitance (sensitivity) connected to the quartz crystal. The article shows that the proposed hysteresis measurement of the converter, which converts the inductance in the range between 95 and 100 μH to a frequency in the range between 1 and 200 kHz, has only 7 × 10−13 frequency instability (during the temperature change between 0 and 50 °C) with a maximum 1 × 10−11 hysteresis frequency difference. PMID:27367688

Large-scale quantum photonic circuits in silicon

NASA Astrophysics Data System (ADS)

Harris, Nicholas C.; Bunandar, Darius; Pant, Mihir; Steinbrecher, Greg R.; Mower, Jacob; Prabhu, Mihika; Baehr-Jones, Tom; Hochberg, Michael; Englund, Dirk

2016-08-01

Quantum information science offers inherently more powerful methods for communication, computation, and precision measurement that take advantage of quantum superposition and entanglement. In recent years, theoretical and experimental advances in quantum computing and simulation with photons have spurred great interest in developing large photonic entangled states that challenge today's classical computers. As experiments have increased in complexity, there has been an increasing need to transition bulk optics experiments to integrated photonics platforms to control more spatial modes with higher fidelity and phase stability. The silicon-on-insulator (SOI) nanophotonics platform offers new possibilities for quantum optics, including the integration of bright, nonclassical light sources, based on the large third-order nonlinearity (χ(3)) of silicon, alongside quantum state manipulation circuits with thousands of optical elements, all on a single phase-stable chip. How large do these photonic systems need to be? Recent theoretical work on Boson Sampling suggests that even the problem of sampling from e30 identical photons, having passed through an interferometer of hundreds of modes, becomes challenging for classical computers. While experiments of this size are still challenging, the SOI platform has the required component density to enable low-loss and programmable interferometers for manipulating hundreds of spatial modes. Here, we discuss the SOI nanophotonics platform for quantum photonic circuits with hundreds-to-thousands of optical elements and the associated challenges. We compare SOI to competing technologies in terms of requirements for quantum optical systems. We review recent results on large-scale quantum state evolution circuits and strategies for realizing high-fidelity heralded gates with imperfect, practical systems. Next, we review recent results on silicon photonics-based photon-pair sources and device architectures, and we discuss a path towards large-scale source integration. Finally, we review monolithic integration strategies for single-photon detectors and their essential role in on-chip feed forward operations.

Effect of startup circuit exercise on derivatives reactive oxygen metabolites, biological antioxidant potential levels and physical fitness of adolescents boys with intellectual disabilities.

PubMed

Kim, Chang-Gyun; Lee, Jin-Seok

2016-10-01

The purpose of this study was to examine the effect of starup circuit exercise program on derivatives reactive oxygen metabolite (d-ROM) and biological antioxidant potential (BAP) levels and physical fitness of adolescents with intellectual disabilities, and to sugesst exercise programs to promote the health and physical development of such adolescents. Twelve students with intellectual disabilities were divided into two groups; circuit exercise group (CE group: n=6; age, 14.83±0.98 years; height, 163.83±5.78 cm; body mass, 67.08±3.32 kg; %Fat, 25.68±2.42), control group (CON group: n=6; age: 15.00±0.63 years; height, 162.33±4.41 cm; body mass, 67.50±3.62 kg; %Fat, 26.96±2.06). The CE group performed the CE program 4 times a week over a 12-week period. The CON group maintained their activities of daily living. The following were measured before and after intervention: physical fitness by before and after the completion of the training programm, and were measured and blood samples were assessed. The results of the study indicate that the 12-week CE program increased significantly physical fitness ( P <0.05). Furthermore, This study proved that the CE program improved physical fitness, and reduced the d-ROM levels, and increased the BAP levels of the adolescents with intellectual disabilities. Therefore, it may enhance the health and physical development of adolescents boys with intellectual disabilities.

Real-time cerebellar neuroprosthetic system based on a spiking neural network model of motor learning.

PubMed

Xu, Tao; Xiao, Na; Zhai, Xiaolong; Kwan Chan, Pak; Tin, Chung

2018-02-01

Damage to the brain, as a result of various medical conditions, impacts the everyday life of patients and there is still no complete cure to neurological disorders. Neuroprostheses that can functionally replace the damaged neural circuit have recently emerged as a possible solution to these problems. Here we describe the development of a real-time cerebellar neuroprosthetic system to substitute neural function in cerebellar circuitry for learning delay eyeblink conditioning (DEC). The system was empowered by a biologically realistic spiking neural network (SNN) model of the cerebellar neural circuit, which considers the neuronal population and anatomical connectivity of the network. The model simulated synaptic plasticity critical for learning DEC. This SNN model was carefully implemented on a field programmable gate array (FPGA) platform for real-time simulation. This hardware system was interfaced in in vivo experiments with anesthetized rats and it used neural spikes recorded online from the animal to learn and trigger conditioned eyeblink in the animal during training. This rat-FPGA hybrid system was able to process neuronal spikes in real-time with an embedded cerebellum model of ~10 000 neurons and reproduce learning of DEC with different inter-stimulus intervals. Our results validated that the system performance is physiologically relevant at both the neural (firing pattern) and behavioral (eyeblink pattern) levels. This integrated system provides the sufficient computation power for mimicking the cerebellar circuit in real-time. The system interacts with the biological system naturally at the spike level and can be generalized for including other neural components (neuron types and plasticity) and neural functions for potential neuroprosthetic applications.

Memristor-based programmable logic array (PLA) and analysis as Memristive networks.

PubMed

Lee, Kwan-Hee; Lee, Sang-Jin; Kim, Seok-Man; Cho, Kyoungrok

2013-05-01

A Memristor theorized by Chua in 1971 has the potential to dramatically influence the way electronic circuits are designed. It is a two terminal device whose resistance state is based on the history of charge flow brought about as the result of the voltage being applied across its terminals and hence can be thought of as a special case of a reconfigurable resistor. Nanoscale devices using dense and regular fabrics such as Memristor cross-bar is promising new architecture for System-on-Chip (SoC) implementations in terms of not only the integration density that the technology can offer but also both improved performance and reduced power dissipation. Memristor has the capacity to switch between high and low resistance states in a cross-bar circuit configuration. The cross-bars are formed from an array of vertical conductive nano-wires cross a second array of horizontal conductive wires. Memristors are realized at the intersection of the two wires in the array through appropriate processing technology such that any particular wire in the vertical array can be connected to a wire in the horizontal array by switching the resistance of a particular intersection to a low state while other cross-points remain in a high resistance state. However the approach introduces a number of challenges. The lack of voltage gain prevents logic being cascaded and voltage level degradation affects robustness of the operation. Moreover the cross-bars introduce sneak current paths when two or more cross points are connected through the switched Memristor. In this paper, we propose Memristor-based programmable logic array (PLA) architecture and develop an analytical model to analyze the logic level on the memristive networks. The proposed PLA architecture has 12 inputs maximum and can be cascaded for more input variables with R(off)/R(on) ratio in the range from 55 to 160 of Memristors.

Field-programmable analogue arrays for the sensorless control of DC motors

NASA Astrophysics Data System (ADS)

Rivera, J.; Dueñas, I.; Ortega, S.; Del Valle, J. L.

2018-02-01

This work presents the analogue implementation of a sensorless controller for direct current motors based on the super-twisting (ST) sliding mode technique, by means of field programmable analogue arrays (FPAA). The novelty of this work is twofold, first is the use of the ST algorithm in a sensorless scheme for DC motors, and the implementation method of this type of sliding mode controllers in FPAAs. The ST algorithm reduces the chattering problem produced with the deliberate use of the sign function in classical sliding mode approaches. On the other hand, the advantages of the implementation method over a digital one are that the controller is not digitally approximated, the controller gains are not fine tuned and the implementation does not require the use of analogue-to-digital and digital-to-analogue converter circuits. In addition to this, the FPAA is a reconfigurable, lower cost and power consumption technology. Simulation and experimentation results were registered, where a more accurate transient response and lower power consumption were obtained by the proposed implementation method when compared to a digital implementation. Also, a more accurate performance by the DC motor is obtained with proposed sensorless ST technique when compared with a classical sliding mode approach.

SAD-Based Stereo Vision Machine on a System-on-Programmable-Chip (SoPC)

PubMed Central

Zhang, Xiang; Chen, Zhangwei

2013-01-01

This paper, proposes a novel solution for a stereo vision machine based on the System-on-Programmable-Chip (SoPC) architecture. The SOPC technology provides great convenience for accessing many hardware devices such as DDRII, SSRAM, Flash, etc., by IP reuse. The system hardware is implemented in a single FPGA chip involving a 32-bit Nios II microprocessor, which is a configurable soft IP core in charge of managing the image buffer and users' configuration data. The Sum of Absolute Differences (SAD) algorithm is used for dense disparity map computation. The circuits of the algorithmic module are modeled by the Matlab-based DSP Builder. With a set of configuration interfaces, the machine can process many different sizes of stereo pair images. The maximum image size is up to 512 K pixels. This machine is designed to focus on real time stereo vision applications. The stereo vision machine offers good performance and high efficiency in real time. Considering a hardware FPGA clock of 90 MHz, 23 frames of 640 × 480 disparity maps can be obtained in one second with 5 × 5 matching window and maximum 64 disparity pixels. PMID:23459385

20-GFLOPS QR processor on a Xilinx Virtex-E FPGA

NASA Astrophysics Data System (ADS)

Walke, Richard L.; Smith, Robert W. M.; Lightbody, Gaye

2000-11-01

Adaptive beamforming can play an important role in sensor array systems in countering directional interference. In high-sample rate systems, such as radar and comms, the calculation of adaptive weights is a very computational task that requires highly parallel solutions. For systems where low power consumption and volume are important the only viable implementation is as an Application Specific Integrated Circuit (ASIC). However, the rapid advancement of Field Programmable Gate Array (FPGA) technology is enabling highly credible re-programmable solutions. In this paper we present the implementation of a scalable linear array processor for weight calculation using QR decomposition. We employ floating-point arithmetic with mantissa size optimized to the target application to minimize component size, and implement them as relationally placed macros (RPMs) on Xilinx Virtex FPGAs to achieve predictable dense layout and high-speed operation. We present results that show that 20GFLOPS of sustained computation on a single XCV3200E-8 Virtex-E FPGA is possible. We also describe the parameterized implementation of the floating-point operators and QR-processor, and the design methodology that enables us to rapidly generate complex FPGA implementations using the industry standard hardware description language VHDL.

Design and FPGA implementation for MAC layer of Ethernet PON

NASA Astrophysics Data System (ADS)

Zhu, Zengxi; Lin, Rujian; Chen, Jian; Ye, Jiajun; Chen, Xinqiao

2004-04-01

Ethernet passive optical network (EPON), which represents the convergence of low-cost, high-bandwidth and supporting multiple services, appears to be one of the best candidates for the next-generation access network. The work of standardizing EPON as a solution for access network is still underway in the IEEE802.3ah Ethernet in the first mile (EFM) task force. The final release is expected in 2004. Up to now, there has been no standard application specific integrated circuit (ASIC) chip available which fulfills the functions of media access control (MAC) layer of EPON. The MAC layer in EPON system has many functions, such as point-to-point emulation (P2PE), Ethernet MAC functionality, multi-point control protocol (MPCP), network operation, administration and maintenance (OAM) and link security. To implement those functions mentioned above, an embedded real-time operating system (RTOS) and a flexible programmable logic device (PLD) with an embedded processor are used. The software and hardware functions in MAC layer are realized through programming embedded microprocessor and field programmable gate array(FPGA). Finally, some experimental results are given in this paper. The method stated here can provide a valuable reference for developing EPON MAC layer ASIC.

Effects of two physical education programmes on health- and skill-related physical fitness of Albanian children.

PubMed

Jarani, J; Grøntved, A; Muca, F; Spahi, A; Qefalia, D; Ushtelenca, K; Kasa, A; Caporossi, D; Gallotta, M C

2016-01-01

This study aims to evaluate the effectiveness of two school-based physical education (PE) programmes (exercise-based and games-based) compared with traditional PE, on health- and skill-related physical fitness components in children in Tirana, Albania. Participants were 378 first-grade (6.8 years) and 389 fourth-grade (9.8 years) children attending four randomly selected schools in Tirana. Twenty-four school classes within these schools were randomly selected (stratified by school and school grade) to participate as exercise group (EG), games group (GG) and control group (CG). Both EG and GG intervention programmes were taught by professional PE teachers using station/circuit teaching framework while CG referred to traditional PE school lessons by a general teacher. All programmes ran in parallel and lasted 5 months, having the same frequency (twice weekly) and duration (45 min). Heart rate (HR) monitoring showed that intensity during PE lessons was significantly higher in the intervention groups compared with control (P < 0.001). Both PE exercise- and games programmes significantly improved several health- and skill-related fitness indicators compared with traditional PE lessons (e.g. gross motor skill summary score: 9.4 (95% CI 7.9; 10.9) for exercise vs. control and 6.5 (95% CI 5.1; 8.1) for games vs. control, cardiorespiratory fitness: 2.0 ml O2 · min(-1) · kg(-1) (95% CI 1.5; 2.4) for exercise vs. control and 1.4 ml O2 · min(-1) · kg(-1) (95% CI 1.0; 1.8) for games vs. control). Furthermore, compared to games-based PE, exercise-based PE showed more positive changes in some gross motor coordination skills outcomes, coordination skills outcomes and cardiorespiratory fitness. The results from this study show that exercise- and games-based PE represents a useful strategy for improving health- and skill-related physical fitness in Albanian elementary school children. In addition, the study shows that exercise-based PE was more effective than games-based PE in improving gross motor function and cardiorespiratory fitness.

DNA-Based Dynamic Reaction Networks.

PubMed

Fu, Ting; Lyu, Yifan; Liu, Hui; Peng, Ruizi; Zhang, Xiaobing; Ye, Mao; Tan, Weihong

2018-05-21

Deriving from logical and mechanical interactions between DNA strands and complexes, DNA-based artificial reaction networks (RNs) are attractive for their high programmability, as well as cascading and fan-out ability, which are similar to the basic principles of electronic logic gates. Arising from the dream of creating novel computing mechanisms, researchers have placed high hopes on the development of DNA-based dynamic RNs and have strived to establish the basic theories and operative strategies of these networks. This review starts by looking back on the evolution of DNA dynamic RNs; in particular' the most significant applications in biochemistry occurring in recent years. Finally, we discuss the perspectives of DNA dynamic RNs and give a possible direction for the development of DNA circuits. Copyright © 2018. Published by Elsevier Ltd.

A wideband analog correlator system for AMiBA

NASA Astrophysics Data System (ADS)

Li, Chao-Te; Kubo, Derek; Han, Chih-Chiang; Chen, Chung-Cheng; Chen, Ming-Tang; Lien, Chun-Hsien; Wang, Huei; Wei, Ray-Ming; Yang, Chia-Hsiang; Chiueh, Tzi-Dar; Peterson, Jeffrey; Kesteven, Michael; Wilson, Warwick

2004-10-01

A wideband correlator system with a bandwidth of 16 GHz or more is required for Array for Microwave Background Anisotropy (AMiBA) to achieve the sensitivity of 10μK in one hour of observation. Double-balanced diode mixers were used as multipliers in 4-lag correlator modules. Several wideband modules were developed for IF signal distribution between receivers and correlators. Correlator outputs were amplified, and digitized by voltage-to-frequency converters. Data acquisition circuits were designed using field programmable gate arrays (FPGA). Subsequent data transfer and control software were based on the configuration for Australia Telescope Compact Array. Transform matrix method will be adopted during calibration to take into account the phase and amplitude variations of analog devices across the passband.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Li, Na; Wu, Yu-Ping; Min, Hao

A radio-frequency (RF) source designed for cold atom experiments is presented. The source uses AD9858, a direct digital synthesizer, to generate the sine wave directly, up to 400 MHz, with sub-Hz resolution. An amplitude control circuit consisting of wideband variable gain amplifier and high speed digital to analog converter is integrated into the source, capable of 70 dB off isolation and 4 ns on-off keying. A field programmable gate array is used to implement a versatile frequency and amplitude co-sweep logic. Owing to modular design, the RF sources have been used on many cold atom experiments to generate various complicatedmore » RF sequences, enriching the operation schemes of cold atoms, which cannot be done by standard RF source instruments.« less

An Active Damping at Blade Resonances Using Piezoelectric Transducers

NASA Technical Reports Server (NTRS)

Choi, Benjamin; Morrison, Carlos; Duffy, Kirsten

2008-01-01

The NASA Glenn Research Center (GRC) is developing an active damping at blade resonances using piezoelectric structure to reduce excessive vibratory stresses that lead to high cycle fatigue (HCF) failures in aircraft engine turbomachinery. Conventional passive damping work was shown first on a nonrotating beam made by Ti-6A1-4V with a pair of identical piezoelectric patches, and then active feedback control law was derived in terms of inductor, resister, and capacitor to control resonant frequency only. Passive electronic circuit components and adaptive feature could be easily programmable into control algorithm. Experimental active damping was demonstrated on two test specimens achieving significant damping on tip displacement and patch location. Also a multimode control technique was shown to control several modes.

Design of a 0.13-μm CMOS cascade expandable ΣΔ modulator for multi-standard RF telecom systems

NASA Astrophysics Data System (ADS)

Morgado, Alonso; del Río, Rocío; de la Rosa, José M.

2007-05-01

This paper reports a 130-nm CMOS programmable cascade ΣΔ modulator for multi-standard wireless terminals, capable of operating on three standards: GSM, Bluetooth and UMTS. The modulator is reconfigured at both architecture- and circuit- level in order to adapt its performance to the different standards specifications with optimized power consumption. The design of the building blocks is based upon a top-down CAD methodology that combines simulation and statistical optimization at different levels of the system hierarchy. Transistor-level simulations show correct operation for all standards, featuring 13-bit, 11.3-bit and 9-bit effective resolution within 200-kHz, 1-MHz and 4-MHz bandwidth, respectively.

All-spin logic operations: Memory device and reconfigurable computing

NASA Astrophysics Data System (ADS)

Patra, Moumita; Maiti, Santanu K.

2018-02-01

Exploiting spin degree of freedom of electron a new proposal is given to characterize spin-based logical operations using a quantum interferometer that can be utilized as a programmable spin logic device (PSLD). The ON and OFF states of both inputs and outputs are described by spin state only, circumventing spin-to-charge conversion at every stage as often used in conventional devices with the inclusion of extra hardware that can eventually diminish the efficiency. All possible logic functions can be engineered from a single device without redesigning the circuit which certainly offers the opportunities of designing new generation spintronic devices. Moreover, we also discuss the utilization of the present model as a memory device and suitable computing operations with proposed experimental setups.

A physically transient form of silicon electronics.

PubMed

Hwang, Suk-Won; Tao, Hu; Kim, Dae-Hyeong; Cheng, Huanyu; Song, Jun-Kyul; Rill, Elliott; Brenckle, Mark A; Panilaitis, Bruce; Won, Sang Min; Kim, Yun-Soung; Song, Young Min; Yu, Ki Jun; Ameen, Abid; Li, Rui; Su, Yewang; Yang, Miaomiao; Kaplan, David L; Zakin, Mitchell R; Slepian, Marvin J; Huang, Yonggang; Omenetto, Fiorenzo G; Rogers, John A

2012-09-28

A remarkable feature of modern silicon electronics is its ability to remain physically invariant, almost indefinitely for practical purposes. Although this characteristic is a hallmark of applications of integrated circuits that exist today, there might be opportunities for systems that offer the opposite behavior, such as implantable devices that function for medically useful time frames but then completely disappear via resorption by the body. We report a set of materials, manufacturing schemes, device components, and theoretical design tools for a silicon-based complementary metal oxide semiconductor (CMOS) technology that has this type of transient behavior, together with integrated sensors, actuators, power supply systems, and wireless control strategies. An implantable transient device that acts as a programmable nonantibiotic bacteriocide provides a system-level example.

The design and development of low- and high-voltage ASICs for space-borne CCD cameras

NASA Astrophysics Data System (ADS)

Waltham, N.; Morrissey, Q.; Clapp, M.; Bell, S.; Jones, L.; Torbet, M.

2017-12-01

The CCD remains the pre-eminent visible and UV wavelength image sensor in space science, Earth and planetary remote sensing. However, the design of space-qualified CCD readout electronics is a significant challenge with requirements for low-volume, low-mass, low-power, high-reliability and tolerance to space radiation. Space-qualified components are frequently unavailable and up-screened commercial components seldom meet project or international space agency requirements. In this paper, we describe an alternative approach of designing and space-qualifying a series of low- and high-voltage mixed-signal application-specific integrated circuits (ASICs), the ongoing development of two low-voltage ASICs with successful flight heritage, and two new high-voltage designs. A challenging sub-system of any CCD camera is the video processing and digitisation electronics. We describe recent developments to improve performance and tolerance to radiation-induced single event latchup of a CCD video processing ASIC originally developed for NASA's Solar Terrestrial Relations Observatory and Solar Dynamics Observatory. We also describe a programme to develop two high-voltage ASICs to address the challenges presented with generating a CCD's bias voltages and drive clocks. A 0.35 μm, 50 V tolerant, CMOS process has been used to combine standard low-voltage 3.3 V transistors with high-voltage 50 V diffused MOSFET transistors that enable output buffers to drive CCD bias drains, gates and clock electrodes directly. We describe a CCD bias voltage generator ASIC that provides 24 independent and programmable 0-32 V outputs. Each channel incorporates a 10-bit digital-to-analogue converter, provides current drive of up to 20 mA into loads of 10 μF, and includes current-limiting and short-circuit protection. An on-chip telemetry system with a 12-bit analogue-to-digital converter enables the outputs and multiple off-chip camera voltages to be monitored. The ASIC can drive one or more CCDs and replaces the many discrete components required in current cameras. We also describe a CCD clock driver ASIC that provides six independent and programmable drivers with high-current capacity. The device enables various CCD clock parameters to be programmed independently, for example the clock-low and clock-high voltage levels, and the clock-rise and clock-fall times, allowing configuration for serial clock frequencies in the range 0.1-2 MHz and image clock frequencies in the range 10-100 kHz. Finally, we demonstrate the impact and importance of this technology for the development of compact, high-performance and low-power integrated focal plane electronics.

Real-time cerebellar neuroprosthetic system based on a spiking neural network model of motor learning

NASA Astrophysics Data System (ADS)

Xu, Tao; Xiao, Na; Zhai, Xiaolong; Chan, Pak Kwan; Tin, Chung

2018-02-01

Objective. Damage to the brain, as a result of various medical conditions, impacts the everyday life of patients and there is still no complete cure to neurological disorders. Neuroprostheses that can functionally replace the damaged neural circuit have recently emerged as a possible solution to these problems. Here we describe the development of a real-time cerebellar neuroprosthetic system to substitute neural function in cerebellar circuitry for learning delay eyeblink conditioning (DEC). Approach. The system was empowered by a biologically realistic spiking neural network (SNN) model of the cerebellar neural circuit, which considers the neuronal population and anatomical connectivity of the network. The model simulated synaptic plasticity critical for learning DEC. This SNN model was carefully implemented on a field programmable gate array (FPGA) platform for real-time simulation. This hardware system was interfaced in in vivo experiments with anesthetized rats and it used neural spikes recorded online from the animal to learn and trigger conditioned eyeblink in the animal during training. Main results. This rat-FPGA hybrid system was able to process neuronal spikes in real-time with an embedded cerebellum model of ~10 000 neurons and reproduce learning of DEC with different inter-stimulus intervals. Our results validated that the system performance is physiologically relevant at both the neural (firing pattern) and behavioral (eyeblink pattern) levels. Significance. This integrated system provides the sufficient computation power for mimicking the cerebellar circuit in real-time. The system interacts with the biological system naturally at the spike level and can be generalized for including other neural components (neuron types and plasticity) and neural functions for potential neuroprosthetic applications.

A multi-scale PDMS fabrication strategy to bridge the size mismatch between integrated circuits and microfluidics†

PubMed Central

Muluneh, Melaku

2015-01-01

In recent years there has been great progress harnessing the small-feature size and programmability of integrated circuits (ICs) for biological applications, by building microfluidics directly on top of ICs. However, a major hurdle to the further development of this technology is the inherent size-mismatch between ICs (~mm) and microfluidic chips (~cm). Increasing the area of the ICs to match the size of the microfluidic chip, as has often been done in previous studies, leads to a waste of valuable space on the IC and an increase in fabrication cost (>100×). To address this challenge, we have developed a three dimensional PDMS chip that can straddle multiple length scales of hybrid IC/microfluidic chips. This approach allows millimeter-scale ICs, with no post-processing, to be integrated into a centimeter-sized PDMS chip. To fabricate this PDMS chip we use a combination of soft-lithography and laser micromachining. Soft lithography was used to define micrometer-scale fluid channels directly on the surface of the IC, allowing fluid to be controlled with high accuracy and brought into close proximity to sensors for highly sensitive measurements. Laser micromachining was used to create ~50 μm vias to connect these molded PDMS channels to a larger PDMS chip, which can connect multiple ICs and house fluid connections to the outside world. To demonstrate the utility of this approach, we built and demonstrated an in-flow magnetic cytometer that consisted of a 5 × 5 cm2 microfluidic chip that incorporated a commercial 565 × 1145 μm2 IC with a GMR sensing circuit. We additionally demonstrated the modularity of this approach by building a chip that incorporated two of these GMR chips connected in series. PMID:25284502

Neuromorphic VLSI vision system for real-time texture segregation.

PubMed

Shimonomura, Kazuhiro; Yagi, Tetsuya

2008-10-01

The visual system of the brain can perceive an external scene in real-time with extremely low power dissipation, although the response speed of an individual neuron is considerably lower than that of semiconductor devices. The neurons in the visual pathway generate their receptive fields using a parallel and hierarchical architecture. This architecture of the visual cortex is interesting and important for designing a novel perception system from an engineering perspective. The aim of this study is to develop a vision system hardware, which is designed inspired by a hierarchical visual processing in V1, for real time texture segregation. The system consists of a silicon retina, orientation chip, and field programmable gate array (FPGA) circuit. The silicon retina emulates the neural circuits of the vertebrate retina and exhibits a Laplacian-Gaussian-like receptive field. The orientation chip selectively aggregates multiple pixels of the silicon retina in order to produce Gabor-like receptive fields that are tuned to various orientations by mimicking the feed-forward model proposed by Hubel and Wiesel. The FPGA circuit receives the output of the orientation chip and computes the responses of the complex cells. Using this system, the neural images of simple cells were computed in real-time for various orientations and spatial frequencies. Using the orientation-selective outputs obtained from the multi-chip system, a real-time texture segregation was conducted based on a computational model inspired by psychophysics and neurophysiology. The texture image was filtered by the two orthogonally oriented receptive fields of the multi-chip system and the filtered images were combined to segregate the area of different texture orientation with the aid of FPGA. The present system is also useful for the investigation of the functions of the higher-order cells that can be obtained by combining the simple and complex cells.

A multi-scale PDMS fabrication strategy to bridge the size mismatch between integrated circuits and microfluidics.

PubMed

Muluneh, Melaku; Issadore, David

2014-12-07

In recent years there has been great progress harnessing the small-feature size and programmability of integrated circuits (ICs) for biological applications, by building microfluidics directly on top of ICs. However, a major hurdle to the further development of this technology is the inherent size-mismatch between ICs (~mm) and microfluidic chips (~cm). Increasing the area of the ICs to match the size of the microfluidic chip, as has often been done in previous studies, leads to a waste of valuable space on the IC and an increase in fabrication cost (>100×). To address this challenge, we have developed a three dimensional PDMS chip that can straddle multiple length scales of hybrid IC/microfluidic chips. This approach allows millimeter-scale ICs, with no post-processing, to be integrated into a centimeter-sized PDMS chip. To fabricate this PDMS chip we use a combination of soft-lithography and laser micromachining. Soft lithography was used to define micrometer-scale fluid channels directly on the surface of the IC, allowing fluid to be controlled with high accuracy and brought into close proximity to sensors for highly sensitive measurements. Laser micromachining was used to create ~50 μm vias to connect these molded PDMS channels to a larger PDMS chip, which can connect multiple ICs and house fluid connections to the outside world. To demonstrate the utility of this approach, we built and demonstrated an in-flow magnetic cytometer that consisted of a 5 × 5 cm(2) microfluidic chip that incorporated a commercial 565 × 1145 μm(2) IC with a GMR sensing circuit. We additionally demonstrated the modularity of this approach by building a chip that incorporated two of these GMR chips connected in series.

Advanced High-Definition Video Cameras

NASA Technical Reports Server (NTRS)

Glenn, William

2007-01-01

A product line of high-definition color video cameras, now under development, offers a superior combination of desirable characteristics, including high frame rates, high resolutions, low power consumption, and compactness. Several of the cameras feature a 3,840 2,160-pixel format with progressive scanning at 30 frames per second. The power consumption of one of these cameras is about 25 W. The size of the camera, excluding the lens assembly, is 2 by 5 by 7 in. (about 5.1 by 12.7 by 17.8 cm). The aforementioned desirable characteristics are attained at relatively low cost, largely by utilizing digital processing in advanced field-programmable gate arrays (FPGAs) to perform all of the many functions (for example, color balance and contrast adjustments) of a professional color video camera. The processing is programmed in VHDL so that application-specific integrated circuits (ASICs) can be fabricated directly from the program. ["VHDL" signifies VHSIC Hardware Description Language C, a computing language used by the United States Department of Defense for describing, designing, and simulating very-high-speed integrated circuits (VHSICs).] The image-sensor and FPGA clock frequencies in these cameras have generally been much higher than those used in video cameras designed and manufactured elsewhere. Frequently, the outputs of these cameras are converted to other video-camera formats by use of pre- and post-filters.

Demonstration of two-qubit algorithms with a superconducting quantum processor.

PubMed

DiCarlo, L; Chow, J M; Gambetta, J M; Bishop, Lev S; Johnson, B R; Schuster, D I; Majer, J; Blais, A; Frunzio, L; Girvin, S M; Schoelkopf, R J

2009-07-09

Quantum computers, which harness the superposition and entanglement of physical states, could outperform their classical counterparts in solving problems with technological impact-such as factoring large numbers and searching databases. A quantum processor executes algorithms by applying a programmable sequence of gates to an initialized register of qubits, which coherently evolves into a final state containing the result of the computation. Building a quantum processor is challenging because of the need to meet simultaneously requirements that are in conflict: state preparation, long coherence times, universal gate operations and qubit readout. Processors based on a few qubits have been demonstrated using nuclear magnetic resonance, cold ion trap and optical systems, but a solid-state realization has remained an outstanding challenge. Here we demonstrate a two-qubit superconducting processor and the implementation of the Grover search and Deutsch-Jozsa quantum algorithms. We use a two-qubit interaction, tunable in strength by two orders of magnitude on nanosecond timescales, which is mediated by a cavity bus in a circuit quantum electrodynamics architecture. This interaction allows the generation of highly entangled states with concurrence up to 94 per cent. Although this processor constitutes an important step in quantum computing with integrated circuits, continuing efforts to increase qubit coherence times, gate performance and register size will be required to fulfil the promise of a scalable technology.

Real-time emulation of neural images in the outer retinal circuit.

PubMed

Hasegawa, Jun; Yagi, Tetsuya

2008-12-01

We describe a novel real-time system that emulates the architecture and functionality of the vertebrate retina. This system reconstructs the neural images formed by the retinal neurons in real time by using a combination of analog and digital systems consisting of a neuromorphic silicon retina chip, a field-programmable gate array, and a digital computer. While the silicon retina carries out the spatial filtering of input images instantaneously, using the embedded resistive networks that emulate the receptive field structure of the outer retinal neurons, the digital computer carries out the temporal filtering of the spatially filtered images to emulate the dynamical properties of the outer retinal circuits. The emulations of the neural image, including 128 x 128 bipolar cells, are carried out at a frame rate of 62.5 Hz. The emulation of the response to the Hermann grid and a spot of light and an annulus of lights has demonstrated that the system responds as expected by previous physiological and psychophysical observations. Furthermore, the emulated dynamics of neural images in response to natural scenes revealed the complex nature of retinal neuron activity. We have concluded that the system reflects the spatiotemporal responses of bipolar cells in the vertebrate retina. The proposed emulation system is expected to aid in understanding the visual computation in the retina and the brain.

Training Deep Convolutional Neural Networks with Resistive Cross-Point Devices

PubMed Central

Gokmen, Tayfun; Onen, Murat; Haensch, Wilfried

2017-01-01

In a previous work we have detailed the requirements for obtaining maximal deep learning performance benefit by implementing fully connected deep neural networks (DNN) in the form of arrays of resistive devices. Here we extend the concept of Resistive Processing Unit (RPU) devices to convolutional neural networks (CNNs). We show how to map the convolutional layers to fully connected RPU arrays such that the parallelism of the hardware can be fully utilized in all three cycles of the backpropagation algorithm. We find that the noise and bound limitations imposed by the analog nature of the computations performed on the arrays significantly affect the training accuracy of the CNNs. Noise and bound management techniques are presented that mitigate these problems without introducing any additional complexity in the analog circuits and that can be addressed by the digital circuits. In addition, we discuss digitally programmable update management and device variability reduction techniques that can be used selectively for some of the layers in a CNN. We show that a combination of all those techniques enables a successful application of the RPU concept for training CNNs. The techniques discussed here are more general and can be applied beyond CNN architectures and therefore enables applicability of the RPU approach to a large class of neural network architectures. PMID:29066942

Optimizations of a Hardware Decoder for Deep-Space Optical Communications

NASA Technical Reports Server (NTRS)

Cheng, Michael K.; Nakashima, Michael A.; Moision, Bruce E.; Hamkins, Jon

2007-01-01

The National Aeronautics and Space Administration has developed a capacity approaching modulation and coding scheme that comprises a serial concatenation of an inner accumulate pulse-position modulation (PPM) and an outer convolutional code [or serially concatenated PPM (SCPPM)] for deep-space optical communications. Decoding of this code uses the turbo principle. However, due to the nonbinary property of SCPPM, a straightforward application of classical turbo decoding is very inefficient. Here, we present various optimizations applicable in hardware implementation of the SCPPM decoder. More specifically, we feature a Super Gamma computation to efficiently handle parallel trellis edges, a pipeline-friendly 'maxstar top-2' circuit that reduces the max-only approximation penalty, a low-latency cyclic redundancy check circuit for window-based decoders, and a high-speed algorithmic polynomial interleaver that leads to memory savings. Using the featured optimizations, we implement a 6.72 megabits-per-second (Mbps) SCPPM decoder on a single field-programmable gate array (FPGA). Compared to the current data rate of 256 kilobits per second from Mars, the SCPPM coded scheme represents a throughput increase of more than twenty-six fold. Extension to a 50-Mbps decoder on a board with multiple FPGAs follows naturally. We show through hardware simulations that the SCPPM coded system can operate within 1 dB of the Shannon capacity at nominal operating conditions.

D0 Superconducting Solenoid Quench Data and Slow Dump Data Acquisition

DOE Office of Scientific and Technical Information (OSTI.GOV)

Markley, D.; /Fermilab

1998-06-09

This Dzero Engineering note describes the method for which the 2 Tesla Superconducting Solenoid Fast Dump and Slow Dump data are accumulated, tracked and stored. The 2 Tesla Solenoid has eleven data points that need to be tracked and then stored when a fast dump or a slow dump occur. The TI555(Texas Instruments) PLC(Programmable Logic Controller) which controls the DC power circuit that powers the Solenoid, also has access to all the voltage taps and other equipment in the circuit. The TI555 constantly logs these eleven points in a rotating memory buffer. When either a fast dump(dump switch opens) ormore » a slow dump (power supply turns off) occurs, the TI555 organizes the respective data and will down load the data to a file on DO-CCRS2. This data in this file is moved over ethernet and is stored in a CSV (comma separated format) file which can easily be examined by Microsoft Excel or any other spreadsheet. The 2 Tesla solenoid control system also locks in first fault information. The TI555 decodes the first fault and passes it along to the program collecting the data and storing it on DO-CCRS2. This first fault information is then part of the file.« less

Training Deep Convolutional Neural Networks with Resistive Cross-Point Devices.

PubMed

Gokmen, Tayfun; Onen, Murat; Haensch, Wilfried

2017-01-01

In a previous work we have detailed the requirements for obtaining maximal deep learning performance benefit by implementing fully connected deep neural networks (DNN) in the form of arrays of resistive devices. Here we extend the concept of Resistive Processing Unit (RPU) devices to convolutional neural networks (CNNs). We show how to map the convolutional layers to fully connected RPU arrays such that the parallelism of the hardware can be fully utilized in all three cycles of the backpropagation algorithm. We find that the noise and bound limitations imposed by the analog nature of the computations performed on the arrays significantly affect the training accuracy of the CNNs. Noise and bound management techniques are presented that mitigate these problems without introducing any additional complexity in the analog circuits and that can be addressed by the digital circuits. In addition, we discuss digitally programmable update management and device variability reduction techniques that can be used selectively for some of the layers in a CNN. We show that a combination of all those techniques enables a successful application of the RPU concept for training CNNs. The techniques discussed here are more general and can be applied beyond CNN architectures and therefore enables applicability of the RPU approach to a large class of neural network architectures.

Possible central nervous system oxygen toxicity seizures among US recreational air or enriched air nitrox open circuit diving fatalities 2004-2013.

PubMed

Buzzacott, P; Denoble, P J

2017-01-01

The first diver certification programme for recreational 'enriched air nitrox' (EAN) diving was released in 1985. Concerns were expressed that many EAN divers might suffer central nervous system (CNS) oxygen toxicity seizures and drown. US fatalities on open-circuit scuba occurring between 2004-2013, where the breathing gas was either air or EAN, were identified. Causes of death and preceding circumstances were examined by a medical examiner experienced in diving autopsies. Case notes were searched for witnessed seizures at elevated partial pressures of oxygen. The dataset comprised 344 air divers (86%) and 55 divers breathing EAN (14%). EAN divers' fatal dives were deeper than air divers' (28 msw vs 18 msw, p < 0.0001). Despite this, of the 249 cases where a cause of death was established, only three EAN divers were considered to have possibly died following CNS oxygen toxicity seizures at depth (ppO2 132, 142 and 193 kPa). The analysis of recreational diving fatalities in the US over 10 years found just one death likely from CNS oxygen toxicity among EAN divers. A further two possible, although unlikely, cases were also found. Fears of commonplace CNS oxygen toxicity seizures while EAN diving have not apparently been realized.

Summary of Proton Test on the Quick Logic QL3025 at Indiana University

NASA Technical Reports Server (NTRS)

Katz, Richard

1998-01-01

This issue of the Programmable Logic Application Notes is a compilation of topics: (1) Proton irradiation tests were performed on the Quick Logic QL3025 at the Indian University Cyclotron facility. The devices, tests, and results are discussed; (2) The functional failure of EEPROM's in heavy ion environment is presented; (3) the Act 1 architecture is summarized; (4) Antifuse hardness and hardness testing is updated; the single even upset (SEU) response of hardwired flip-flops is also presented; (4) Total dose results of the ACT 2 and ACT 3 circuits is presented in a chart; (5) Recent sub-micron devices testing of total dose is presented in a chart along with brief discussion; and (6) a reference to the WWW site for more articles of interest.

Hardware Design and Implementation of Fixed-Width Standard and Truncated 4×4, 6×6, 8×8 and 12×12-BIT Multipliers Using Fpga

NASA Astrophysics Data System (ADS)

Rais, Muhammad H.

2010-06-01

This paper presents Field Programmable Gate Array (FPGA) implementation of standard and truncated multipliers using Very High Speed Integrated Circuit Hardware Description Language (VHDL). Truncated multiplier is a good candidate for digital signal processing (DSP) applications such as finite impulse response (FIR) and discrete cosine transform (DCT). Remarkable reduction in FPGA resources, delay, and power can be achieved using truncated multipliers instead of standard parallel multipliers when the full precision of the standard multiplier is not required. The truncated multipliers show significant improvement as compared to standard multipliers. Results show that the anomaly in Spartan-3 AN average connection and maximum pin delay have been efficiently reduced in Virtex-4 device.

Bistable metamaterial for switching and cascading elastic vibrations

PubMed Central

Foehr, André; Daraio, Chiara

2017-01-01

The realization of acoustic devices analogous to electronic systems, like diodes, transistors, and logic elements, suggests the potential use of elastic vibrations (i.e., phonons) in information processing, for example, in advanced computational systems, smart actuators, and programmable materials. Previous experimental realizations of acoustic diodes and mechanical switches have used nonlinearities to break transmission symmetry. However, existing solutions require operation at different frequencies or involve signal conversion in the electronic or optical domains. Here, we show an experimental realization of a phononic transistor-like device using geometric nonlinearities to switch and amplify elastic vibrations, via magnetic coupling, operating at a single frequency. By cascading this device in a tunable mechanical circuit board, we realize the complete set of mechanical logic elements and interconnect selected ones to execute simple calculations. PMID:28416663

Artificial brains. A million spiking-neuron integrated circuit with a scalable communication network and interface.

PubMed

Merolla, Paul A; Arthur, John V; Alvarez-Icaza, Rodrigo; Cassidy, Andrew S; Sawada, Jun; Akopyan, Filipp; Jackson, Bryan L; Imam, Nabil; Guo, Chen; Nakamura, Yutaka; Brezzo, Bernard; Vo, Ivan; Esser, Steven K; Appuswamy, Rathinakumar; Taba, Brian; Amir, Arnon; Flickner, Myron D; Risk, William P; Manohar, Rajit; Modha, Dharmendra S

2014-08-08

Inspired by the brain's structure, we have developed an efficient, scalable, and flexible non-von Neumann architecture that leverages contemporary silicon technology. To demonstrate, we built a 5.4-billion-transistor chip with 4096 neurosynaptic cores interconnected via an intrachip network that integrates 1 million programmable spiking neurons and 256 million configurable synapses. Chips can be tiled in two dimensions via an interchip communication interface, seamlessly scaling the architecture to a cortexlike sheet of arbitrary size. The architecture is well suited to many applications that use complex neural networks in real time, for example, multiobject detection and classification. With 400-pixel-by-240-pixel video input at 30 frames per second, the chip consumes 63 milliwatts. Copyright © 2014, American Association for the Advancement of Science.

A Star Image Extractor for Small Satellites

NASA Astrophysics Data System (ADS)

Yamada, Yoshiyuki; Yamauchi, Masahiro; Gouda, Naoteru; Kobayashi, Yukiyasu; Tsujimoto, Takuji; Yano, Taihei; Suganuma, Masahiro; Nakasuka, Shinichi; Sako, Nobutada; Inamori, Takaya

We have developed a Star Image Extractor (SIE) which works as an on-board real-time image processor. It is a logic circuit written on an FPGA(Field Programmable Gate Array) device. It detects and extracts only an object data from raw image data. SIE will be required with the Nano-JASMINE 1) satellite. Nano-JASMINE is the small astrometry satellite that observes objects in our galaxy. It will be launched in 2010 and needs two years mission period. Nano-JASMINE observes an object with the TDI (Time Delayed Integration) observation mode. TDI is one of operation modes of CCD detector. Data is obtained, by rotating the imaging system including CCD at a rated synchronized with a vertical charge transfer of CCD. Obtained image data is sent through SIE to the Mission-controller.

Portable multiplicity counter

DOEpatents

Newell, Matthew R [Los Alamos, NM; Jones, David Carl [Los Alamos, NM

2009-09-01

A portable multiplicity counter has signal input circuitry, processing circuitry and a user/computer interface disposed in a housing. The processing circuitry, which can comprise a microcontroller integrated circuit operably coupled to shift register circuitry implemented in a field programmable gate array, is configured to be operable via the user/computer interface to count input signal pluses receivable at said signal input circuitry and record time correlations thereof in a total counting mode, coincidence counting mode and/or a multiplicity counting mode. The user/computer interface can be for example an LCD display/keypad and/or a USB interface. The counter can include a battery pack for powering the counter and low/high voltage power supplies for biasing external detectors so that the counter can be configured as a hand-held device for counting neutron events.

Development of Automated Monitoring and Management System of Municipal Solid Waste Landfill Based on the Industrial OMRON Controller

NASA Astrophysics Data System (ADS)

Kostarev, S. N.; Sereda, T. G.

2018-01-01

The application of the programmable logic integrated circuits (PLC) for creating the software and hardware complexes of the medium complexity is an economically sound solution. The application of the OMRON controller to solve the monitoring and management tasks of safety of the municipal solid waste (MSW) landfill with the use of technology of the filtrate recirculation and the landfill maps irrigation is shown in the article. The article contains the technical solution connected with the implementation of the 2162059RU invention patent for the municipal solid waste landfill management in the Kurgan region of Russia. The calculation of maps and ponds was made with consideration of the limited sanitary and protection zone. The GRUNDFOS dosing and reactor equipment was proposed to use in the project.

Design of high-voltage, high-power, solid state remote power controllers for aerospace applications

NASA Technical Reports Server (NTRS)

Sturman, J. C.

1985-01-01

Two general types of remote power controllers (RPC's), which combine the functions of a circuit breaker and a switch, were developed for use in dc aerospace systems. Power-switching devices used in the designs are the gate-turnoff thyristor (GTO) and MOSFET. The RPC's can switch dc voltages to 1200 V and currents to 1000 A. Seven different units were constructed and subjected to laboratory and thermal vacuum testing. Two of these were dual units that switch both positive and negative voltages simultaneously. The RPC's using MOSFET's have slow turnon and turnoff times which limit surge currents and voltage spiking from high di/dt. The GTO's have much faster transition times. All RPC's have programmable overload tripout proportional to I sq T and microsecond tripout for large overloads.

Design of high-voltage, high-power, solid state remote power controllers for aerospace applications

NASA Astrophysics Data System (ADS)

Sturman, J. C.

1985-05-01

Two general types of remote power controllers (RPC's), which combine the functions of a circuit breaker and a switch, were developed for use in dc aerospace systems. Power-switching devices used in the designs are the gate-turnoff thyristor (GTO) and MOSFET. The RPC's can switch dc voltages to 1200 V and currents to 1000 A. Seven different units were constructed and subjected to laboratory and thermal vacuum testing. Two of these were dual units that switch both positive and negative voltages simultaneously. The RPC's using MOSFET's have slow turnon and turnoff times which limit surge currents and voltage spiking from high di/dt. The GTO's have much faster transition times. All RPC's have programmable overload tripout proportional to I sq T and microsecond tripout for large overloads.

DNA sequence-directed shape change of photopatterned hydrogels via high-degree swelling

NASA Astrophysics Data System (ADS)

Cangialosi, Angelo; Yoon, ChangKyu; Liu, Jiayu; Huang, Qi; Guo, Jingkai; Nguyen, Thao D.; Gracias, David H.; Schulman, Rebecca

2017-09-01

Shape-changing hydrogels that can bend, twist, or actuate in response to external stimuli are critical to soft robots, programmable matter, and smart medicine. Shape change in hydrogels has been induced by global cues, including temperature, light, or pH. Here we demonstrate that specific DNA molecules can induce 100-fold volumetric hydrogel expansion by successive extension of cross-links. We photopattern up to centimeter-sized gels containing multiple domains that undergo different shape changes in response to different DNA sequences. Experiments and simulations suggest a simple design rule for controlled shape change. Because DNA molecules can be coupled to molecular sensors, amplifiers, and logic circuits, this strategy introduces the possibility of building soft devices that respond to diverse biochemical inputs and autonomously implement chemical control programs.

A single-board NMR spectrometer based on a software defined radio architecture

NASA Astrophysics Data System (ADS)

Tang, Weinan; Wang, Weimin

2011-01-01

A single-board software defined radio (SDR) spectrometer for nuclear magnetic resonance (NMR) is presented. The SDR-based architecture, realized by combining a single field programmable gate array (FPGA) and a digital signal processor (DSP) with peripheral radio frequency (RF) front-end circuits, makes the spectrometer compact and reconfigurable. The DSP, working as a pulse programmer, communicates with a personal computer via a USB interface and controls the FPGA through a parallel port. The FPGA accomplishes digital processing tasks such as a numerically controlled oscillator (NCO), digital down converter (DDC) and gradient waveform generator. The NCO, with agile control of phase, frequency and amplitude, is part of a direct digital synthesizer that is used to generate an RF pulse. The DDC performs quadrature demodulation, multistage low-pass filtering and gain adjustment to produce a bandpass signal (receiver bandwidth from 3.9 kHz to 10 MHz). The gradient waveform generator is capable of outputting shaped gradient pulse waveforms and supports eddy-current compensation. The spectrometer directly acquires an NMR signal up to 30 MHz in the case of baseband sampling and is suitable for low-field (<0.7 T) application. Due to the featured SDR architecture, this prototype has flexible add-on ability and is expected to be suitable for portable NMR systems.

Talent identification and deliberate programming in skeleton: ice novice to Winter Olympian in 14 months.

PubMed

Bullock, Nicola; Gulbin, Jason P; Martin, David T; Ross, Angus; Holland, Terry; Marino, Frank

2009-02-15

The aims of this study were to talent transfer, rapidly develop, and qualify an Australian female athlete in the skeleton event at the 2006 Torino Winter Olympic Games and quantify the volume of skeleton-specific training and competition that would enable this to be achieved. Initially, 26 athletes were recruited through a talent identification programme based on their 30-m sprint time. After attending a selection camp, 10 athletes were invited to undertake an intensified skeleton training programme. Four of these athletes were then selected to compete for Australia on the World Cup circuit. All completed runs and simulated push starts were documented over a 14-month period. The athlete who eventually represented Australia at the Torino Winter Olympic Games did so following approximately 300 start simulations and about 220 training/competition runs over a period of 14 months. Using a deliberate programming model, these findings provide a guide to the minimum exposure required for a novice skeleton athlete to reach Olympic representative standard following intensified sport-specific training. The findings of this study are discussed in the context of the deliberate practice theory and offer the term "deliberate programming" as an alternative way of incorporating all aspects of expert development.

Circadian pacemaking in cells and circuits of the suprachiasmatic nucleus.

PubMed

Hastings, M H; Brancaccio, M; Maywood, E S

2014-01-01

The suprachiasmatic nucleus (SCN) of the hypothalamus is the principal circadian pacemaker of the brain. It co-ordinates the daily rhythms of sleep and wakefulness, as well as physiology and behaviour, that set the tempo to our lives. Disturbance of this daily pattern, most acutely with jet-lag but more insidiously with rotational shift-work, can have severely deleterious effects for mental function and long-term health. The present review considers recent developments in our understanding of the properties of the SCN that make it a robust circadian time-keeper. It first focuses on the intracellular transcriptional/ translational feedback loops (TTFL) that constitute the cellular clockwork of the SCN neurone. Daily timing by these loops pivots around the negative regulation of the Period (Per) and Cryptochrome (Cry) genes by their protein products. The period of the circadian cycle is set by the relative stability of Per and Cry proteins, and this can be controlled by both genetic and pharmacological interventions. It then considers the function of these feedback loops in the context of cytosolic signalling by cAMP and intracellular calcium ([Ca(2+) ]i ), which are both outputs from, and inputs to, the TTFL, as well as the critical role of vasoactive intestinal peptide (VIP) signalling in synchronising cellular clocks across the SCN. Synchronisation by VIP in the SCN is paracrine, operating over an unconventionally long time frame (i.e. 24 h) and wide spatial domain, mediated via the cytosolic pathways upstream of the TTFL. Finally, we show how intersectional pharmacogenetics can be used to control G-protein-coupled signalling in individual SCN neurones, and how manipulation of Gq/[Ca(2+) ]i -signalling in VIP neurones can re-programme the circuit-level encoding of circadian time. Circadian pacemaking in the SCN therefore provides an unrivalled context in which to understand how a complex, adaptive behaviour can be organised by the dynamic activity of a relatively few gene products, operating in a clearly defined neuronal circuit, with both cell-autonomous and emergent, circuit-level properties. © 2014 The Authors. Journal of Neuroendocrinology published by John Wiley & Sons Ltd on behalf of The British Society for Neuroendocrinology.

Efficient audio signal processing for embedded systems

NASA Astrophysics Data System (ADS)

Chiu, Leung Kin

As mobile platforms continue to pack on more computational power, electronics manufacturers start to differentiate their products by enhancing the audio features. However, consumers also demand smaller devices that could operate for longer time, hence imposing design constraints. In this research, we investigate two design strategies that would allow us to efficiently process audio signals on embedded systems such as mobile phones and portable electronics. In the first strategy, we exploit properties of the human auditory system to process audio signals. We designed a sound enhancement algorithm to make piezoelectric loudspeakers sound ”richer" and "fuller." Piezoelectric speakers have a small form factor but exhibit poor response in the low-frequency region. In the algorithm, we combine psychoacoustic bass extension and dynamic range compression to improve the perceived bass coming out from the tiny speakers. We also developed an audio energy reduction algorithm for loudspeaker power management. The perceptually transparent algorithm extends the battery life of mobile devices and prevents thermal damage in speakers. This method is similar to audio compression algorithms, which encode audio signals in such a ways that the compression artifacts are not easily perceivable. Instead of reducing the storage space, however, we suppress the audio contents that are below the hearing threshold, therefore reducing the signal energy. In the second strategy, we use low-power analog circuits to process the signal before digitizing it. We designed an analog front-end for sound detection and implemented it on a field programmable analog array (FPAA). The system is an example of an analog-to-information converter. The sound classifier front-end can be used in a wide range of applications because programmable floating-gate transistors are employed to store classifier weights. Moreover, we incorporated a feature selection algorithm to simplify the analog front-end. A machine learning algorithm AdaBoost is used to select the most relevant features for a particular sound detection application. In this classifier architecture, we combine simple "base" analog classifiers to form a strong one. We also designed the circuits to implement the AdaBoost-based analog classifier.

Millimeter-wave silicon-based ultra-wideband automotive radar transceivers

NASA Astrophysics Data System (ADS)

Jain, Vipul

Since the invention of the integrated circuit, the semiconductor industry has revolutionized the world in ways no one had ever anticipated. With the advent of silicon technologies, consumer electronics became light-weight and affordable and paved the way for an Information-Communication-Entertainment age. While silicon almost completely replaced compound semiconductors from these markets, it has been unable to compete in areas with more stringent requirements due to technology limitations. One of these areas is automotive radar sensors, which will enable next-generation collision-warning systems in automobiles. A low-cost implementation is absolutely essential for widespread use of these systems, which leads us to the subject of this dissertation---silicon-based solutions for automotive radars. This dissertation presents architectures and design techniques for mm-wave automotive radar transceivers. Several fully-integrated transceivers and receivers operating at 22-29 GHz and 77-81 GHz are demonstrated in both CMOS and SiGe BiCMOS technologies. Excellent performance is achieved indicating the suitability of silicon technologies for automotive radar sensors. The first CMOS 22-29-GHz pulse-radar receiver front-end for ultra-wideband radars is presented. The chip includes a low noise amplifier, I/Q mixers, quadrature voltage-controlled oscillators, pulse formers and variable-gain amplifiers. Fabricated in 0.18-mum CMOS, the receiver achieves a conversion gain of 35-38.1 dB and a noise figure of 5.5-7.4 dB. Integration of multi-mode multi-band transceivers on a single chip will enable next-generation low-cost automotive radar sensors. Two highly-integrated silicon ICs are designed in a 0.18-mum BiCMOS technology. These designs are also the first reported demonstrations of mm-wave circuits with high-speed digital circuits on the same chip. The first mm-wave dual-band frequency synthesizer and transceiver, operating in the 24-GHz and 77-GHz bands, are demonstrated. All circuits except the oscillators are shared between the two bands. A multi-functional injection-locked circuit is used after the oscillators to reconfigure the division ratio inside the phase-locked loop. The synthesizer is suitable for integration in automotive radar transceivers and heterodyne receivers for 94-GHz imaging applications. The transceiver chip includes a dual-band low noise amplifier, a shared downconversion chain, dual-band pulse formers, power amplifiers, a dual-band frequency synthesizer and a high-speed programmable baseband pulse generator. Radar functionality is demonstrated using loopback measurements.

Video rate morphological processor based on a redundant number representation

NASA Astrophysics Data System (ADS)

Kuczborski, Wojciech; Attikiouzel, Yianni; Crebbin, Gregory A.

1992-03-01

This paper presents a video rate morphological processor for automated visual inspection of printed circuit boards, integrated circuit masks, and other complex objects. Inspection algorithms are based on gray-scale mathematical morphology. Hardware complexity of the known methods of real-time implementation of gray-scale morphology--the umbra transform and the threshold decomposition--has prompted us to propose a novel technique which applied an arithmetic system without carrying propagation. After considering several arithmetic systems, a redundant number representation has been selected for implementation. Two options are analyzed here. The first is a pure signed digit number representation (SDNR) with the base of 4. The second option is a combination of the base-2 SDNR (to represent gray levels of images) and the conventional twos complement code (to represent gray levels of structuring elements). Operation principle of the morphological processor is based on the concept of the digit level systolic array. Individual processing units and small memory elements create a pipeline. The memory elements store current image windows (kernels). All operation primitives of processing units apply a unified direction of digit processing: most significant digit first (MSDF). The implementation technology is based on the field programmable gate arrays by Xilinx. This paper justified the rationality of a new approach to logic design, which is the decomposition of Boolean functions instead of Boolean minimization.

Assimilation of Biophysical Neuronal Dynamics in Neuromorphic VLSI.

PubMed

Wang, Jun; Breen, Daniel; Akinin, Abraham; Broccard, Frederic; Abarbanel, Henry D I; Cauwenberghs, Gert

2017-12-01

Representing the biophysics of neuronal dynamics and behavior offers a principled analysis-by-synthesis approach toward understanding mechanisms of nervous system functions. We report on a set of procedures assimilating and emulating neurobiological data on a neuromorphic very large scale integrated (VLSI) circuit. The analog VLSI chip, NeuroDyn, features 384 digitally programmable parameters specifying for 4 generalized Hodgkin-Huxley neurons coupled through 12 conductance-based chemical synapses. The parameters also describe reversal potentials, maximal conductances, and spline regressed kinetic functions for ion channel gating variables. In one set of experiments, we assimilated membrane potential recorded from one of the neurons on the chip to the model structure upon which NeuroDyn was designed using the known current input sequence. We arrived at the programmed parameters except for model errors due to analog imperfections in the chip fabrication. In a related set of experiments, we replicated songbird individual neuron dynamics on NeuroDyn by estimating and configuring parameters extracted using data assimilation from intracellular neural recordings. Faithful emulation of detailed biophysical neural dynamics will enable the use of NeuroDyn as a tool to probe electrical and molecular properties of functional neural circuits. Neuroscience applications include studying the relationship between molecular properties of neurons and the emergence of different spike patterns or different brain behaviors. Clinical applications include studying and predicting effects of neuromodulators or neurodegenerative diseases on ion channel kinetics.

Novel microwave photonic fractional Hilbert transformer using a ring resonator-based optical all-pass filter.

PubMed

Zhuang, Leimeng; Khan, Muhammad Rezaul; Beeker, Willem; Leinse, Arne; Heideman, René; Roeloffzen, Chris

2012-11-19

We propose and demonstrate a novel wideband microwave photonic fractional Hilbert transformer implemented using a ring resonator-based optical all-pass filter. The full programmability of the ring resonator allows variable and arbitrary fractional order of the Hilbert transformer. The performance analysis in both frequency and time domain validates that the proposed implementation provides a good approximation to an ideal fractional Hilbert transformer. This is also experimentally verified by an electrical S₂₁ response characterization performed on a waveguide realization of a ring resonator. The waveguide-based structure allows the proposed Hilbert transformer to be integrated together with other building blocks on a photonic integrated circuit to create various system-level functionalities for on-chip microwave photonic signal processors. As an example, a circuit consisting of a splitter and a ring resonator has been realized which can perform on-chip phase control of microwave signals generated by means of optical heterodyning, and simultaneous generation of in-phase and quadrature microwave signals for a wide frequency range. For these functionalities, this simple and on-chip solution is considered to be practical, particularly when operating together with a dual-frequency laser. To our best knowledge, this is the first-time on-chip demonstration where ring resonators are employed to perform phase control functionalities for optical generation of microwave signals by means of optical heterodyning.

Word-Synchronous Optical Sampling of Periodically Repeated OTDM Data Words for True Waveform Visualization

NASA Astrophysics Data System (ADS)

Benkler, Erik; Telle, Harald R.

2007-06-01

An improved phase-locked loop (PLL) for versatile synchronization of a sampling pulse train to an optical data stream is presented. It enables optical sampling of the true waveform of repetitive high bit-rate optical time division multiplexed (OTDM) data words such as pseudorandom bit sequences. Visualization of the true waveform can reveal details, which cause systematic bit errors. Such errors cannot be inferred from eye diagrams and require word-synchronous sampling. The programmable direct-digital-synthesis circuit used in our novel PLL approach allows flexible adaption of virtually any problem-specific synchronization scenario, including those required for waveform sampling, for jitter measurements by slope detection, and for classical eye-diagrams. Phase comparison of the PLL is performed at 10-GHz OTDM base clock rate, leading to a residual synchronization jitter of less than 70 fs.

Flexible Ionic-Electronic Hybrid Oxide Synaptic TFTs with Programmable Dynamic Plasticity for Brain-Inspired Neuromorphic Computing.

PubMed

John, Rohit Abraham; Ko, Jieun; Kulkarni, Mohit R; Tiwari, Naveen; Chien, Nguyen Anh; Ing, Ng Geok; Leong, Wei Lin; Mathews, Nripan

2017-08-01

Emulation of biological synapses is necessary for future brain-inspired neuromorphic computational systems that could look beyond the standard von Neuman architecture. Here, artificial synapses based on ionic-electronic hybrid oxide-based transistors on rigid and flexible substrates are demonstrated. The flexible transistors reported here depict a high field-effect mobility of ≈9 cm 2 V -1 s -1 with good mechanical performance. Comprehensive learning abilities/synaptic rules like paired-pulse facilitation, excitatory and inhibitory postsynaptic currents, spike-time-dependent plasticity, consolidation, superlinear amplification, and dynamic logic are successfully established depicting concurrent processing and memory functionalities with spatiotemporal correlation. The results present a fully solution processable approach to fabricate artificial synapses for next-generation transparent neural circuits. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Recognizing and engineering digital-like logic gates and switches in gene regulatory networks.

PubMed

Bradley, Robert W; Buck, Martin; Wang, Baojun

2016-10-01

A central aim of synthetic biology is to build organisms that can perform useful activities in response to specified conditions. The digital computing paradigm which has proved so successful in electrical engineering is being mapped to synthetic biological systems to allow them to make such decisions. However, stochastic molecular processes have graded input-output functions, thus, bioengineers must select those with desirable characteristics and refine their transfer functions to build logic gates with digital-like switching behaviour. Recent efforts in genome mining and the development of programmable RNA-based switches, especially CRISPRi, have greatly increased the number of parts available to synthetic biologists. Improvements to the digital characteristics of these parts are required to enable robust predictable design of deeply layered logic circuits. Copyright © 2016 The Author(s). Published by Elsevier Ltd.. All rights reserved.

On-chip wavelength multiplexed detection of cancer DNA biomarkers in blood

PubMed Central

Cai, H.; Stott, M. A.; Ozcelik, D.; Parks, J. W.; Hawkins, A. R.; Schmidt, H.

2016-01-01

We have developed an optofluidic analysis system that processes biomolecular samples starting from whole blood and then analyzes and identifies multiple targets on a silicon-based molecular detection platform. We demonstrate blood filtration, sample extraction, target enrichment, and fluorescent labeling using programmable microfluidic circuits. We detect and identify multiple targets using a spectral multiplexing technique based on wavelength-dependent multi-spot excitation on an antiresonant reflecting optical waveguide chip. Specifically, we extract two types of melanoma biomarkers, mutated cell-free nucleic acids —BRAFV600E and NRAS, from whole blood. We detect and identify these two targets simultaneously using the spectral multiplexing approach with up to a 96% success rate. These results point the way toward a full front-to-back chip-based optofluidic compact system for high-performance analysis of complex biological samples. PMID:28058082

Genetic Parallel Programming: design and implementation.

PubMed

Cheang, Sin Man; Leung, Kwong Sak; Lee, Kin Hong

2006-01-01

This paper presents a novel Genetic Parallel Programming (GPP) paradigm for evolving parallel programs running on a Multi-Arithmetic-Logic-Unit (Multi-ALU) Processor (MAP). The MAP is a Multiple Instruction-streams, Multiple Data-streams (MIMD), general-purpose register machine that can be implemented on modern Very Large-Scale Integrated Circuits (VLSIs) in order to evaluate genetic programs at high speed. For human programmers, writing parallel programs is more difficult than writing sequential programs. However, experimental results show that GPP evolves parallel programs with less computational effort than that of their sequential counterparts. It creates a new approach to evolving a feasible problem solution in parallel program form and then serializes it into a sequential program if required. The effectiveness and efficiency of GPP are investigated using a suite of 14 well-studied benchmark problems. Experimental results show that GPP speeds up evolution substantially.

Radiation Mitigation and Power Optimization Design Tools for Reconfigurable Hardware in Orbit

NASA Technical Reports Server (NTRS)

French, Matthew; Graham, Paul; Wirthlin, Michael; Wang, Li; Larchev, Gregory

2005-01-01

The Reconfigurable Hardware in Orbit (RHinO)project is focused on creating a set of design tools that facilitate and automate design techniques for reconfigurable computing in space, using SRAM-based field-programmable-gate-array (FPGA) technology. In the second year of the project, design tools that leverage an established FPGA design environment have been created to visualize and analyze an FPGA circuit for radiation weaknesses and power inefficiencies. For radiation, a single event Upset (SEU) emulator, persistence analysis tool, and a half-latch removal tool for Xilinx/Virtex-II devices have been created. Research is underway on a persistence mitigation tool and multiple bit upsets (MBU) studies. For power, synthesis level dynamic power visualization and analysis tools have been completed. Power optimization tools are under development and preliminary test results are positive.

Compact quantum random number generator based on superluminescent light-emitting diodes

NASA Astrophysics Data System (ADS)

Wei, Shihai; Yang, Jie; Fan, Fan; Huang, Wei; Li, Dashuang; Xu, Bingjie

2017-12-01

By measuring the amplified spontaneous emission (ASE) noise of the superluminescent light emitting diodes, we propose and realize a quantum random number generator (QRNG) featured with practicability. In the QRNG, after the detection and amplification of the ASE noise, the data acquisition and randomness extraction which is integrated in a field programmable gate array (FPGA) are both implemented in real-time, and the final random bit sequences are delivered to a host computer with a real-time generation rate of 1.2 Gbps. Further, to achieve compactness, all the components of the QRNG are integrated on three independent printed circuit boards with a compact design, and the QRNG is packed in a small enclosure sized 140 mm × 120 mm × 25 mm. The final random bit sequences can pass all the NIST-STS and DIEHARD tests.

Optimized 4-bit Quantum Reversible Arithmetic Logic Unit

NASA Astrophysics Data System (ADS)

Ayyoub, Slimani; Achour, Benslama

2017-08-01

Reversible logic has received a great attention in the recent years due to its ability to reduce the power dissipation. The main purposes of designing reversible logic are to decrease quantum cost, depth of the circuits and the number of garbage outputs. The arithmetic logic unit (ALU) is an important part of central processing unit (CPU) as the execution unit. This paper presents a complete design of a new reversible arithmetic logic unit (ALU) that can be part of a programmable reversible computing device such as a quantum computer. The proposed ALU based on a reversible low power control unit and small performance parameters full adder named double Peres gates. The presented ALU can produce the largest number (28) of arithmetic and logic functions and have the smallest number of quantum cost and delay compared with existing designs.

Intrinsic Hardware Evolution for the Design and Reconfiguration of Analog Speed Controllers for a DC Motor

NASA Technical Reports Server (NTRS)

Gwaltney, David A.; Ferguson, Michael I.

2003-01-01

Evolvable hardware provides the capability to evolve analog circuits to produce amplifier and filter functions. Conventional analog controller designs employ these same functions. Analog controllers for the control of the shaft speed of a DC motor are evolved on an evolvable hardware platform utilizing a second generation Field Programmable Transistor Array (FPTA2). The performance of an evolved controller is compared to that of a conventional proportional-integral (PI) controller. It is shown that hardware evolution is able to create a compact design that provides good performance, while using considerably less functional electronic components than the conventional design. Additionally, the use of hardware evolution to provide fault tolerance by reconfiguring the design is explored. Experimental results are presented showing that significant recovery of capability can be made in the face of damaging induced faults.