A CMOS In-Pixel CTIA High Sensitivity Fluorescence Imager.

PubMed

Murari, Kartikeya; Etienne-Cummings, Ralph; Thakor, Nitish; Cauwenberghs, Gert

2011-10-01

Traditionally, charge coupled device (CCD) based image sensors have held sway over the field of biomedical imaging. Complementary metal oxide semiconductor (CMOS) based imagers so far lack sensitivity leading to poor low-light imaging. Certain applications including our work on animal-mountable systems for imaging in awake and unrestrained rodents require the high sensitivity and image quality of CCDs and the low power consumption, flexibility and compactness of CMOS imagers. We present a 132×124 high sensitivity imager array with a 20.1 μm pixel pitch fabricated in a standard 0.5 μ CMOS process. The chip incorporates n-well/p-sub photodiodes, capacitive transimpedance amplifier (CTIA) based in-pixel amplification, pixel scanners and delta differencing circuits. The 5-transistor all-nMOS pixel interfaces with peripheral pMOS transistors for column-parallel CTIA. At 70 fps, the array has a minimum detectable signal of 4 nW/cm(2) at a wavelength of 450 nm while consuming 718 μA from a 3.3 V supply. Peak signal to noise ratio (SNR) was 44 dB at an incident intensity of 1 μW/cm(2). Implementing 4×4 binning allowed the frame rate to be increased to 675 fps. Alternately, sensitivity could be increased to detect about 0.8 nW/cm(2) while maintaining 70 fps. The chip was used to image single cell fluorescence at 28 fps with an average SNR of 32 dB. For comparison, a cooled CCD camera imaged the same cell at 20 fps with an average SNR of 33.2 dB under the same illumination while consuming over a watt.

A CMOS In-Pixel CTIA High Sensitivity Fluorescence Imager

PubMed Central

Murari, Kartikeya; Etienne-Cummings, Ralph; Thakor, Nitish; Cauwenberghs, Gert

2012-01-01

Traditionally, charge coupled device (CCD) based image sensors have held sway over the field of biomedical imaging. Complementary metal oxide semiconductor (CMOS) based imagers so far lack sensitivity leading to poor low-light imaging. Certain applications including our work on animal-mountable systems for imaging in awake and unrestrained rodents require the high sensitivity and image quality of CCDs and the low power consumption, flexibility and compactness of CMOS imagers. We present a 132×124 high sensitivity imager array with a 20.1 μm pixel pitch fabricated in a standard 0.5 μ CMOS process. The chip incorporates n-well/p-sub photodiodes, capacitive transimpedance amplifier (CTIA) based in-pixel amplification, pixel scanners and delta differencing circuits. The 5-transistor all-nMOS pixel interfaces with peripheral pMOS transistors for column-parallel CTIA. At 70 fps, the array has a minimum detectable signal of 4 nW/cm2 at a wavelength of 450 nm while consuming 718 μA from a 3.3 V supply. Peak signal to noise ratio (SNR) was 44 dB at an incident intensity of 1 μW/cm2. Implementing 4×4 binning allowed the frame rate to be increased to 675 fps. Alternately, sensitivity could be increased to detect about 0.8 nW/cm2 while maintaining 70 fps. The chip was used to image single cell fluorescence at 28 fps with an average SNR of 32 dB. For comparison, a cooled CCD camera imaged the same cell at 20 fps with an average SNR of 33.2 dB under the same illumination while consuming over a watt. PMID:23136624

Design and Test of a 65nm CMOS Front-End with Zero Dead Time for Next Generation Pixel Detectors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gaioni, L.; Braga, D.; Christian, D.

This work is concerned with the experimental characterization of a synchronous analog processor with zero dead time developed in a 65 nm CMOS technology, conceived for pixel detectors at the HL-LHC experiment upgrades. It includes a low noise, fast charge sensitive amplifier with detector leakage compensation circuit, and a compact, single ended comparator able to correctly process hits belonging to two consecutive bunch crossing periods. A 2-bit Flash ADC is exploited for digital conversion immediately after the preamplifier. A description of the circuits integrated in the front-end processor and the initial characterization results are provided

CMOS sensor as charged particles and ionizing radiation detector

NASA Astrophysics Data System (ADS)

Cruz-Zaragoza, E.; Piña López, I.

2015-01-01

This paper reports results of CMOS sensor suitable for use as charged particles and ionizing radiation detector. The CMOS sensor with 640 × 480 pixels area has been integrated into an electronic circuit for detection of ionizing radiation and it was exposed to alpha particle (Am-241, Unat), beta (Sr-90), and gamma photons (Cs-137). Results show after long period of time (168 h) irradiation the sensor had not loss of functionality and also the energy of the charge particles and photons were very well obtained.

Development of cryogenic CMOS Readout ASICs for the Point-Contact HPGe Detectors for Dark Matter Search and Neutrino Experiments

NASA Astrophysics Data System (ADS)

Deng, Zhi; He, Li; Liu, Feng; Liu, Yinong; Xue, Tao; Li, Yulan; Yue, Qian

2017-05-01

The paper presents the developments of two cryogenic readout ASICs for the point-contact HPGe detectors for dark matter search and neutrino experiments. Extremely low noise readout electronics were demanded and the capability of working at cryogenic temperatures may bring great advantages. The first ASIC was a monolithic CMOS charge sensitive preamplifier with its noise optimized for ∼1 pF input capacitance. The second ASIC was a waveform recorder based on switched capacitor array. These two ASICs were fabricated in CMOS 350 nm and 180 nm processes respectively. The prototype chips were tested and showed promising results. Both ASICs worked well at low temperature. The preamplifier had achieved ENC of 10.3 electrons with 0.7 pF input capacitance and the SCA chip could run at 9 bit effective resolution and 25 MSPS sampling rate.

Method for characterizing the upset response of CMOS circuits using alpha-particle sensitive test circuits

NASA Technical Reports Server (NTRS)

Buehler, Martin G. (Inventor); Nixon, Robert H. (Inventor); Soli, George A. (Inventor); Blaes, Brent R. (Inventor)

1995-01-01

A method for predicting the SEU susceptibility of a standard-cell D-latch using an alpha-particle sensitive SRAM, SPICE critical charge simulation results, and alpha-particle interaction physics. A technique utilizing test structures to quickly and inexpensively characterize the SEU sensitivity of standard cell latches intended for use in a space environment. This bench-level approach utilizes alpha particles to induce upsets in a low LET sensitive 4-k bit test SRAM. This SRAM consists of cells that employ an offset voltage to adjust their upset sensitivity and an enlarged sensitive drain junction to enhance the cell's upset rate.

Delta-Doped Back-Illuminated CMOS Imaging Arrays: Progress and Prospects

NASA Technical Reports Server (NTRS)

Hoenk, Michael E.; Jones, Todd J.; Dickie, Matthew R.; Greer, Frank; Cunningham, Thomas J.; Blazejewski, Edward; Nikzad, Shouleh

2009-01-01

In this paper, we report the latest results on our development of delta-doped, thinned, back-illuminated CMOS imaging arrays. As with charge-coupled devices, thinning and back-illumination are essential to the development of high performance CMOS imaging arrays. Problems with back surface passivation have emerged as critical to the prospects for incorporating CMOS imaging arrays into high performance scientific instruments, just as they did for CCDs over twenty years ago. In the early 1990's, JPL developed delta-doped CCDs, in which low temperature molecular beam epitaxy was used to form an ideal passivation layer on the silicon back surface. Comprising only a few nanometers of highly-doped epitaxial silicon, delta-doping achieves the stability and uniformity that are essential for high performance imaging and spectroscopy. Delta-doped CCDs were shown to have high, stable, and uniform quantum efficiency across the entire spectral range from the extreme ultraviolet through the near infrared. JPL has recently bump-bonded thinned, delta-doped CMOS imaging arrays to a CMOS readout, and demonstrated imaging. Delta-doped CMOS devices exhibit the high quantum efficiency that has become the standard for scientific-grade CCDs. Together with new circuit designs for low-noise readout currently under development, delta-doping expands the potential scientific applications of CMOS imaging arrays, and brings within reach important new capabilities, such as fast, high-sensitivity imaging with parallel readout and real-time signal processing. It remains to demonstrate manufacturability of delta-doped CMOS imaging arrays. To that end, JPL has acquired a new silicon MBE and ancillary equipment for delta-doping wafers up to 200mm in diameter, and is now developing processes for high-throughput, high yield delta-doping of fully-processed wafers with CCD and CMOS imaging devices.

Design and Fabrication of High-Efficiency CMOS/CCD Imagers

NASA Technical Reports Server (NTRS)

Pain, Bedabrata

2007-01-01

An architecture for back-illuminated complementary metal oxide/semiconductor (CMOS) and charge-coupled-device (CCD) ultraviolet/visible/near infrared- light image sensors, and a method of fabrication to implement the architecture, are undergoing development. The architecture and method are expected to enable realization of the full potential of back-illuminated CMOS/CCD imagers to perform with high efficiency, high sensitivity, excellent angular response, and in-pixel signal processing. The architecture and method are compatible with next-generation CMOS dielectric-forming and metallization techniques, and the process flow of the method is compatible with process flows typical of the manufacture of very-large-scale integrated (VLSI) circuits. The architecture and method overcome all obstacles that have hitherto prevented high-yield, low-cost fabrication of back-illuminated CMOS/CCD imagers by use of standard VLSI fabrication tools and techniques. It is not possible to discuss the obstacles in detail within the space available for this article. Briefly, the obstacles are posed by the problems of generating light-absorbing layers having desired uniform and accurate thicknesses, passivation of surfaces, forming structures for efficient collection of charge carriers, and wafer-scale thinning (in contradistinction to diescale thinning). A basic element of the present architecture and method - the element that, more than any other, makes it possible to overcome the obstacles - is the use of an alternative starting material: Instead of starting with a conventional bulk-CMOS wafer that consists of a p-doped epitaxial silicon layer grown on a heavily-p-doped silicon substrate, one starts with a special silicon-on-insulator (SOI) wafer that consists of a thermal oxide buried between a lightly p- or n-doped, thick silicon layer and a device silicon layer of appropriate thickness and doping. The thick silicon layer is used as a handle: that is, as a mechanical support for the device silicon layer during micro-fabrication.

Monolithic pixel development in TowerJazz 180 nm CMOS for the outer pixel layers in the ATLAS experiment

NASA Astrophysics Data System (ADS)

Berdalovic, I.; Bates, R.; Buttar, C.; Cardella, R.; Egidos Plaja, N.; Hemperek, T.; Hiti, B.; van Hoorne, J. W.; Kugathasan, T.; Mandic, I.; Maneuski, D.; Marin Tobon, C. A.; Moustakas, K.; Musa, L.; Pernegger, H.; Riedler, P.; Riegel, C.; Schaefer, D.; Schioppa, E. J.; Sharma, A.; Snoeys, W.; Solans Sanchez, C.; Wang, T.; Wermes, N.

2018-01-01

The upgrade of the ATLAS tracking detector (ITk) for the High-Luminosity Large Hadron Collider at CERN requires the development of novel radiation hard silicon sensor technologies. Latest developments in CMOS sensor processing offer the possibility of combining high-resistivity substrates with on-chip high-voltage biasing to achieve a large depleted active sensor volume. We have characterised depleted monolithic active pixel sensors (DMAPS), which were produced in a novel modified imaging process implemented in the TowerJazz 180 nm CMOS process in the framework of the monolithic sensor development for the ALICE experiment. Sensors fabricated in this modified process feature full depletion of the sensitive layer, a sensor capacitance of only a few fF and radiation tolerance up to 1015 neq/cm2. This paper summarises the measurements of charge collection properties in beam tests and in the laboratory using radioactive sources and edge TCT. The results of these measurements show significantly improved radiation hardness obtained for sensors manufactured using the modified process. This has opened the way to the design of two large scale demonstrators for the ATLAS ITk. To achieve a design compatible with the requirements of the outer pixel layers of the tracker, a charge sensitive front-end taking 500 nA from a 1.8 V supply is combined with a fast digital readout architecture. The low-power front-end with a 25 ns time resolution exploits the low sensor capacitance to reduce noise and analogue power, while the implemented readout architectures minimise power by reducing the digital activity.

A 7 ke-SD-FWC 1.2 e-RMS Temporal Random Noise 128×256 Time-Resolved CMOS Image Sensor With Two In-Pixel SDs for Biomedical Applications.

PubMed

Seo, Min-Woong; Kawahito, Shoji

2017-12-01

A large full well capacity (FWC) for wide signal detection range and low temporal random noise for high sensitivity lock-in pixel CMOS image sensor (CIS) embedded with two in-pixel storage diodes (SDs) has been developed and presented in this paper. For fast charge transfer from photodiode to SDs, a lateral electric field charge modulator (LEFM) is used for the developed lock-in pixel. As a result, the time-resolved CIS achieves a very large SD-FWC of approximately 7ke-, low temporal random noise of 1.2e-rms at 20 fps with true correlated double sampling operation and fast intrinsic response less than 500 ps at 635 nm. The proposed imager has an effective pixel array of and a pixel size of . The sensor chip is fabricated by Dongbu HiTek 1P4M 0.11 CIS process.

High-voltage pixel sensors for ATLAS upgrade

NASA Astrophysics Data System (ADS)

Perić, I.; Kreidl, C.; Fischer, P.; Bompard, F.; Breugnon, P.; Clemens, J.-C.; Fougeron, D.; Liu, J.; Pangaud, P.; Rozanov, A.; Barbero, M.; Feigl, S.; Capeans, M.; Ferrere, D.; Pernegger, H.; Ristic, B.; Muenstermann, D.; Gonzalez Sevilla, S.; La Rosa, A.; Miucci, A.; Nessi, M.; Iacobucci, G.; Backhaus, M.; Hügging, Fabian; Krüger, H.; Hemperek, T.; Obermann, T.; Wermes, N.; Garcia-Sciveres, M.; Quadt, A.; Weingarten, J.; George, M.; Grosse-Knetter, J.; Rieger, J.; Bates, R.; Blue, A.; Buttar, C.; Hynds, D.

2014-11-01

The high-voltage (HV-) CMOS pixel sensors offer several good properties: a fast charge collection by drift, the possibility to implement relatively complex CMOS in-pixel electronics and the compatibility with commercial processes. The sensor element is a deep n-well diode in a p-type substrate. The n-well contains CMOS pixel electronics. The main charge collection mechanism is drift in a shallow, high field region, which leads to a fast charge collection and a high radiation tolerance. We are currently evaluating the use of the high-voltage detectors implemented in 180 nm HV-CMOS technology for the high-luminosity ATLAS upgrade. Our approach is replacing the existing pixel and strip sensors with the CMOS sensors while keeping the presently used readout ASICs. By intelligence we mean the ability of the sensor to recognize a particle hit and generate the address information. In this way we could benefit from the advantages of the HV sensor technology such as lower cost, lower mass, lower operating voltage, smaller pitch, smaller clusters at high incidence angles. Additionally we expect to achieve a radiation hardness necessary for ATLAS upgrade. In order to test the concept, we have designed two HV-CMOS prototypes that can be readout in two ways: using pixel and strip readout chips. In the case of the pixel readout, the connection between HV-CMOS sensor and the readout ASIC can be established capacitively.

Design of fast signal processing readout front-end electronics implemented in CMOS 40 nm technology

NASA Astrophysics Data System (ADS)

Kleczek, Rafal

2016-12-01

The author presents considerations on the design of fast readout front-end electronics implemented in a CMOS 40 nm technology with an emphasis on the system dead time, noise performance and power dissipation. The designed processing channel consists of a charge sensitive amplifier with different feedback types (Krummenacher, resistive and constant current blocks), a threshold setting block, a discriminator and a counter with logic circuitry. The results of schematic and post-layout simulations with randomly generated input pulses in a time domain according to the Poisson distribution are presented and analyzed. Dead time below 20 ns is possible while keeping noise ENC ≈ 90 e- for a detector capacitance CDET = 160 fF.

CMOS minimal array

NASA Astrophysics Data System (ADS)

Janesick, James; Cheng, John; Bishop, Jeanne; Andrews, James T.; Tower, John; Walker, Jeff; Grygon, Mark; Elliot, Tom

2006-08-01

A high performance prototype CMOS imager is introduced. Test data is reviewed for different array formats that utilize 3T photo diode, 5T pinned photo diode and 6T photo gate CMOS pixel architectures. The imager allows several readout modes including progressive scan, snap and windowed operation. The new imager is built on different silicon substrates including very high resistivity epitaxial wafers for deep depletion operation. Data products contained in this paper focus on sensor's read noise, charge capacity, charge transfer efficiency, thermal dark current, RTS dark spikes, QE, pixel cross- talk and on-chip analog circuitry performance.

CMOS serial link for fully duplexed data communication

NASA Astrophysics Data System (ADS)

Lee, Kyeongho; Kim, Sungjoon; Ahn, Gijung; Jeong, Deog-Kyoon

1995-04-01

This paper describes a CMOS serial link allowing fully duplexed 500 Mbaud serial data communication. The CMOS serial link is a robust and low-cost solution to high data rate requirements. A central charge pump PLL for generating multiphase clocks for oversampling is shared by several serial link channels. Fully duplexed serial data communication is realized in the bidirectional bridge by separating incoming data from the mixed signal on the cable end. The digital PLL accomplishes process-independent data recovery by using a low-ratio oversampling, a majority voting, and a parallel data recovery scheme. Mostly, digital approach could extend its bandwidth further with scaled CMOS technology. A single channel serial link and a charge pump PLL are integrated in a test chip using 1.2 micron CMOS process technology. The test chip confirms upto 500 Mbaud unidirectional mode operation and 320 Mbaud fully duplexed mode operation with pseudo random data patterns.

Vision Sensors and Cameras

NASA Astrophysics Data System (ADS)

Hoefflinger, Bernd

Silicon charge-coupled-device (CCD) imagers have been and are a specialty market ruled by a few companies for decades. Based on CMOS technologies, active-pixel sensors (APS) began to appear in 1990 at the 1 μm technology node. These pixels allow random access, global shutters, and they are compatible with focal-plane imaging systems combining sensing and first-level image processing. The progress towards smaller features and towards ultra-low leakage currents has provided reduced dark currents and μm-size pixels. All chips offer Mega-pixel resolution, and many have very high sensitivities equivalent to ASA 12.800. As a result, HDTV video cameras will become a commodity. Because charge-integration sensors suffer from a limited dynamic range, significant processing effort is spent on multiple exposure and piece-wise analog-digital conversion to reach ranges >10,000:1. The fundamental alternative is log-converting pixels with an eye-like response. This offers a range of almost a million to 1, constant contrast sensitivity and constant colors, important features in professional, technical and medical applications. 3D retino-morphic stacking of sensing and processing on top of each other is being revisited with sub-100 nm CMOS circuits and with TSV technology. With sensor outputs directly on top of neurons, neural focal-plane processing will regain momentum, and new levels of intelligent vision will be achieved. The industry push towards thinned wafers and TSV enables backside-illuminated and other pixels with a 100% fill-factor. 3D vision, which relies on stereo or on time-of-flight, high-speed circuitry, will also benefit from scaled-down CMOS technologies both because of their size as well as their higher speed.

JPL CMOS Active Pixel Sensor Technology

NASA Technical Reports Server (NTRS)

Fossum, E. R.

1995-01-01

This paper will present the JPL-developed complementary metal- oxide-semiconductor (CMOS) active pixel sensor (APS) technology. The CMOS APS has achieved performance comparable to charge coupled devices, yet features ultra low power operation, random access readout, on-chip timing and control, and on-chip analog to digital conversion. Previously published open literature will be reviewed.

Assessment of a Low-Power 65 nm CMOS Technology for Analog Front-End Design

NASA Astrophysics Data System (ADS)

Manghisoni, Massimo; Gaioni, Luigi; Ratti, Lodovico; Re, Valerio; Traversi, Gianluca

2014-02-01

This work is concerned with the study of the analog properties of MOSFET devices belonging to a 65 nm CMOS technology with emphasis on intrinsic voltage gain and noise performance. This node appears to be a robust and promising solution to cope with the unprecedented requirements set by silicon vertex trackers in experiments upgrades and future colliders as well as by imaging detectors at light sources and free electron lasers. In this scaled-down technology, the impact of new dielectric materials and processing techniques on the analog behavior of MOSFETs has to be carefully evaluated. An inversion level design methodology has been adopted to analyze data obtained from device measurements and provide a powerful tool to establish design criteria for detector front-ends in this nanoscale CMOS process. A comparison with data coming from less scaled technologies, such as 90 nm and 130 nm nodes, is also provided and can be used to evaluate the resolution limits achievable for low-noise charge sensitive amplifiers in the 100 nm minimum feature size range.

A low-cost CMOS-MEMS piezoresistive accelerometer with large proof mass.

PubMed

Khir, Mohd Haris Md; Qu, Peng; Qu, Hongwei

2011-01-01

This paper reports a low-cost, high-sensitivity CMOS-MEMS piezoresistive accelerometer with large proof mass. In the device fabricated using ON Semiconductor 0.5 μm CMOS technology, an inherent CMOS polysilicon thin film is utilized as the piezoresistive sensing material. A full Wheatstone bridge was constructed through easy wiring allowed by the three metal layers in the 0.5 μm CMOS technology. The device fabrication process consisted of a standard CMOS process for sensor configuration, and a deep reactive ion etching (DRIE) based post-CMOS microfabrication for MEMS structure release. A bulk single-crystal silicon (SCS) substrate is included in the proof mass to increase sensor sensitivity. In device design and analysis, the self heating of the polysilicon piezoresistors and its effect to the sensor performance is also discussed. With a low operating power of 1.5 mW, the accelerometer demonstrates a sensitivity of 0.077 mV/g prior to any amplification. Dynamic tests have been conducted with a high-end commercial calibrating accelerometer as reference.

CMOS Image Sensors: Electronic Camera On A Chip

NASA Technical Reports Server (NTRS)

Fossum, E. R.

1995-01-01

Recent advancements in CMOS image sensor technology are reviewed, including both passive pixel sensors and active pixel sensors. On- chip analog to digital converters and on-chip timing and control circuits permit realization of an electronic camera-on-a-chip. Highly miniaturized imaging systems based on CMOS image sensor technology are emerging as a competitor to charge-coupled devices for low cost uses.

A Low-Cost CMOS-MEMS Piezoresistive Accelerometer with Large Proof Mass

PubMed Central

Khir, Mohd Haris Md; Qu, Peng; Qu, Hongwei

2011-01-01

This paper reports a low-cost, high-sensitivity CMOS-MEMS piezoresistive accelerometer with large proof mass. In the device fabricated using ON Semiconductor 0.5 μm CMOS technology, an inherent CMOS polysilicon thin film is utilized as the piezoresistive sensing material. A full Wheatstone bridge was constructed through easy wiring allowed by the three metal layers in the 0.5 μm CMOS technology. The device fabrication process consisted of a standard CMOS process for sensor configuration, and a deep reactive ion etching (DRIE) based post-CMOS microfabrication for MEMS structure release. A bulk single-crystal silicon (SCS) substrate is included in the proof mass to increase sensor sensitivity. In device design and analysis, the self heating of the polysilicon piezoresistors and its effect to the sensor performance is also discussed. With a low operating power of 1.5 mW, the accelerometer demonstrates a sensitivity of 0.077 mV/g prior to any amplification. Dynamic tests have been conducted with a high-end commercial calibrating accelerometer as reference. PMID:22164052

Large Format CMOS-based Detectors for Diffraction Studies

NASA Astrophysics Data System (ADS)

Thompson, A. C.; Nix, J. C.; Achterkirchen, T. G.; Westbrook, E. M.

2013-03-01

Complementary Metal Oxide Semiconductor (CMOS) devices are rapidly replacing CCD devices in many commercial and medical applications. Recent developments in CMOS fabrication have improved their radiation hardness, device linearity, readout noise and thermal noise, making them suitable for x-ray crystallography detectors. Large-format (e.g. 10 cm × 15 cm) CMOS devices with a pixel size of 100 μm × 100 μm are now becoming available that can be butted together on three sides so that very large area detector can be made with no dead regions. Like CCD systems our CMOS systems use a GdOS:Tb scintillator plate to convert stopping x-rays into visible light which is then transferred with a fiber-optic plate to the sensitive surface of the CMOS sensor. The amount of light per x-ray on the sensor is much higher in the CMOS system than a CCD system because the fiber optic plate is only 3 mm thick while on a CCD system it is highly tapered and much longer. A CMOS sensor is an active pixel matrix such that every pixel is controlled and readout independently of all other pixels. This allows these devices to be readout while the sensor is collecting charge in all the other pixels. For x-ray diffraction detectors this is a major advantage since image frames can be collected continuously at up 20 Hz while the crystal is rotated. A complete diffraction dataset can be collected over five times faster than with CCD systems with lower radiation exposure to the crystal. In addition, since the data is taken fine-phi slice mode the 3D angular position of diffraction peaks is improved. We have developed a cooled 6 sensor CMOS detector with an active area of 28.2 × 29.5 cm with 100 μm × 100 μm pixels and a readout rate of 20 Hz. The detective quantum efficiency exceeds 60% over the range 8-12 keV. One, two and twelve sensor systems are also being developed for a variety of scientific applications. Since the sensors are butt able on three sides, even larger systems could be built at reasonable cost.

Single event upset vulnerability of selected 4K and 16K CMOS static RAM's

NASA Technical Reports Server (NTRS)

Kolasinski, W. A.; Koga, R.; Blake, J. B.; Brucker, G.; Pandya, P.; Petersen, E.; Price, W.

1982-01-01

Upset thresholds for bulk CMOS and CMOS/SOS RAMS were deduced after bombardment of the devices with 140 MeV Kr, 160 MeV Ar, and 33 MeV O beams in a cyclotron. The trials were performed to test prototype devices intended for space applications, to relate feature size to the critical upset charge, and to check the validity of computer simulation models. The tests were run on 4 and 1 K memory cells with 6 transistors, in either hardened or unhardened configurations. The upset cross sections were calculated to determine the critical charge for upset from the soft errors observed in the irradiated cells. Computer simulations of the critical charge were found to deviate from the experimentally observed variation of the critical charge as the square of the feature size. Modeled values of series resistors decoupling the inverter pairs of memory cells showed that above some minimum resistance value a small increase in resistance produces a large increase in the critical charge, which the experimental data showed to be of questionable validity unless the value is made dependent on the maximum allowed read-write time.

Charge Transfer Inefficiency in Pinned Photodiode CMOS image sensors: Simple Montecarlo modeling and experimental measurement based on a pulsed storage-gate method

NASA Astrophysics Data System (ADS)

Pelamatti, Alice; Goiffon, Vincent; Chabane, Aziouz; Magnan, Pierre; Virmontois, Cédric; Saint-Pé, Olivier; de Boisanger, Michel Breart

2016-11-01

The charge transfer time represents the bottleneck in terms of temporal resolution in Pinned Photodiode (PPD) CMOS image sensors. This work focuses on the modeling and estimation of this key parameter. A simple numerical model of charge transfer in PPDs is presented. The model is based on a Montecarlo simulation and takes into account both charge diffusion in the PPD and the effect of potential obstacles along the charge transfer path. This work also presents a new experimental approach for the estimation of the charge transfer time, called pulsed Storage Gate (SG) method. This method, which allows reproduction of a ;worst-case; transfer condition, is based on dedicated SG pixel structures and is particularly suitable to compare transfer efficiency performances for different pixel geometries.

Fundamental performance differences between CMOS and CCD imagers: Part II

NASA Astrophysics Data System (ADS)

Janesick, James; Andrews, James; Tower, John; Grygon, Mark; Elliott, Tom; Cheng, John; Lesser, Michael; Pinter, Jeff

2007-09-01

A new class of CMOS imagers that compete with scientific CCDs is presented. The sensors are based on deep depletion backside illuminated technology to achieve high near infrared quantum efficiency and low pixel cross-talk. The imagers deliver very low read noise suitable for single photon counting - Fano-noise limited soft x-ray applications. Digital correlated double sampling signal processing necessary to achieve low read noise performance is analyzed and demonstrated for CMOS use. Detailed experimental data products generated by different pixel architectures (notably 3TPPD, 5TPPD and 6TPG designs) are presented including read noise, charge capacity, dynamic range, quantum efficiency, charge collection and transfer efficiency and dark current generation. Radiation damage data taken for the imagers is also reported.

Quantitative evaluation of the accuracy and variance of individual pixels in a scientific CMOS (sCMOS) camera for computational imaging

NASA Astrophysics Data System (ADS)

Watanabe, Shigeo; Takahashi, Teruo; Bennett, Keith

2017-02-01

The"scientific" CMOS (sCMOS) camera architecture fundamentally differs from CCD and EMCCD cameras. In digital CCD and EMCCD cameras, conversion from charge to the digital output is generally through a single electronic chain, and the read noise and the conversion factor from photoelectrons to digital outputs are highly uniform for all pixels, although quantum efficiency may spatially vary. In CMOS cameras, the charge to voltage conversion is separate for each pixel and each column has independent amplifiers and analog-to-digital converters, in addition to possible pixel-to-pixel variation in quantum efficiency. The "raw" output from the CMOS image sensor includes pixel-to-pixel variability in the read noise, electronic gain, offset and dark current. Scientific camera manufacturers digitally compensate the raw signal from the CMOS image sensors to provide usable images. Statistical noise in images, unless properly modeled, can introduce errors in methods such as fluctuation correlation spectroscopy or computational imaging, for example, localization microscopy using maximum likelihood estimation. We measured the distributions and spatial maps of individual pixel offset, dark current, read noise, linearity, photoresponse non-uniformity and variance distributions of individual pixels for standard, off-the-shelf Hamamatsu ORCA-Flash4.0 V3 sCMOS cameras using highly uniform and controlled illumination conditions, from dark conditions to multiple low light levels between 20 to 1,000 photons / pixel per frame to higher light conditions. We further show that using pixel variance for flat field correction leads to errors in cameras with good factory calibration.

DNA decorated carbon nanotube sensors on CMOS circuitry for environmental monitoring

NASA Astrophysics Data System (ADS)

Liu, Yu; Chen, Chia-Ling; Agarwal, V.; Li, Xinghui; Sonkusale, S.; Dokmeci, Mehmet R.; Wang, Ming L.

2010-04-01

Single-walled carbon nanotubes (SWNTs) with their large surface area, high aspect ratio are one of the novel materials which have numerous attractive features amenable for high sensitivity sensors. Several nanotube based sensors including, gas, chemical and biosensors have been demonstrated. Moreover, most of these sensors require off chip components to detect the variations in the signals making them complicated and hard to commercialize. Here we present a novel complementary metal oxide semiconductor (CMOS) integrated carbon nanotube sensors for portable high sensitivity chemical sensing applications. Multiple zincation steps have been developed to ascertain proper electrical connectivity between the carbon nanotubes and the foundry made CMOS circuitry. The SWNTs have been integrated onto (CMOS) circuitry as the feedback resistor of a Miller compensated operational amplifier utilizing low temperature Dielectrophoretic (DEP) assembly process which has been tailored to be compatible with the post-CMOS integration at the die level. Building nanotube sensors directly on commercial CMOS circuitry allows single chip solutions eliminating the need for long parasitic lines and numerous wire bonds. The carbon nanotube sensors realized on CMOS circuitry show strong response to various vapors including Dimethyl methylphosphonate and Dinitrotoluene. The remarkable set of attributes of the SWNTs realized on CMOS electronic chips provides an attractive platform for high sensitivity portable nanotube based bio and chemical sensors.

Local sensor based on nanowire field effect transistor from inhomogeneously doped silicon on insulator

NASA Astrophysics Data System (ADS)

Presnov, Denis E.; Bozhev, Ivan V.; Miakonkikh, Andrew V.; Simakin, Sergey G.; Trifonov, Artem S.; Krupenin, Vladimir A.

2018-02-01

We present the original method for fabricating a sensitive field/charge sensor based on field effect transistor (FET) with a nanowire channel that uses CMOS-compatible processes only. A FET with a kink-like silicon nanowire channel was fabricated from the inhomogeneously doped silicon on insulator wafer very close (˜100 nm) to the extremely sharp corner of a silicon chip forming local probe. The single e-beam lithographic process with a shadow deposition technique, followed by separate two reactive ion etching processes, was used to define the narrow semiconductor nanowire channel. The sensors charge sensitivity was evaluated to be in the range of 0.1-0.2 e /√{Hz } from the analysis of their transport and noise characteristics. The proposed method provides a good opportunity for the relatively simple manufacture of a local field sensor for measuring the electrical field distribution, potential profiles, and charge dynamics for a wide range of mesoscopic objects. Diagnostic systems and devices based on such sensors can be used in various fields of physics, chemistry, material science, biology, electronics, medicine, etc.

A 190 mV start-up and 59.2% efficiency CMOS gate boosting voltage doubler charge pump in 0.18 µm standard CMOS process for energy harvesting

NASA Astrophysics Data System (ADS)

Yoshida, Minori; Miyaji, Kousuke

2018-04-01

A start-up charge pump circuit for an extremely low input voltage (V IN) is proposed and demonstrated. The proposed circuit uses an inverter level shifter to generate a 2V IN voltage swing to the gate of both main NMOS and PMOS power transistors in a charge pump to reduce the channel resistance. The proposed circuit is fully implemented in a standard 0.18 µm CMOS process, and the measurement result shows that a minimum input voltage of 190 mV is achieved and output power increases by 181% compared with the conventional forward-body-bias scheme at a 300 mV input voltage. The proposed scheme achieves a maximum efficiency of 59.2% when the input voltage is 390 mV and the output current is 320 nA. The proposed circuit is suitable as a start-up circuit in ultralow power energy harvesting power management applications to boost-up from below threshold voltage.

Charge transfer efficiency improvement of 4T pixel for high speed CMOS image sensor

NASA Astrophysics Data System (ADS)

Jin, Xiangliang; Liu, Weihui; Yang, Hongjiao; Tang, Lizhen; Yang, Jia

2015-03-01

The charge transfer efficiency improvement method is proposed by optimizing the electrical potential distribution along the transfer path from the PPD to the FD. In this work, we present a non-uniform doped transfer transistor channel, with the adjustments to the overlap length between the CPIA layer and the transfer gate, and the overlap length between the SEN layer and transfer gate. Theory analysis and TCAD simulation results show that the density of the residual charge reduces from 1e11 /cm3 to 1e9 /cm3, and the transfer time reduces from 500 ns to 143 ns, and the charge transfer efficiency is about 77 e-/ns. This optimizing design effectively improves the charge transfer efficiency of 4T pixel and the performance of 4T high speed CMOS image sensor.

A study of charged particles/radiation damage to VLSI device materials

NASA Technical Reports Server (NTRS)

Okyere, John G.

1987-01-01

Future spacecraft systems such as the manned space station will be subjected to low-dose long term radiation particles. Most electronic systems are affected by such particles. There is therefore a great need to understand device physics and failure mechanisms affected by radiation and to design circuits that would be less susceptible to radiation. Using 2 MeV electron radiation and bias temperature aging, it was found that MOS capacitors that were prepositively biased have lower flatband voltage shift and lesser increase in density of surface state charge than those that were not prepositively biased. In addition, it was shown that there is continued recovery of flatband voltage and density of state charge in irradiated capacitors during both room temperature anneal and 137 degree anneal. When nMOS transistors were subjected to 1 MeV proton radiation, charge pumping and current versus voltage measurements indicated that transconductance degradation, threshold voltage shifts and changes in interface states density may be the primary cause of nMOS transistor failure after radiation. Simulation studies using SPICE were performed on CMOS SRAM cells of various transistor sizes. It is shown that transistor sizing affects the noise margins of CMOS SRAM cells, and that as the beta ratio of the transistors of the CMOS SRAM cell decreases, the effective noise margin of the SRAM cell increases. Some suggestions were made in connection with the design of CMOS SRAMS that are hardened against single event upsets.

Charge pump-based MOSFET-only 1.5-bit pipelined ADC stage in digital CMOS technology

NASA Astrophysics Data System (ADS)

Singh, Anil; Agarwal, Alpana

2016-10-01

A simple low-power and low-area metal-oxide-semiconductor field-effect transistor-only fully differential 1.5-bit pipelined analog-to-digital converter stage is proposed and designed in Taiwan Semiconductor Manufacturing Company 0.18 μm-technology using BSIM3v3 parameters with supply voltage of 1.8 V in inexpensive digital complementary metal-oxide semiconductor (CMOS) technology. It is based on charge pump technique to achieve the desired voltage gain of 2, independent of capacitor mismatch and avoiding the need of power hungry operational amplifier-based architecture to reduce the power, Si area and cost. Various capacitances are implemented by metal-oxide semiconductor capacitors, offering compatibility with cheaper digital CMOS process in order to reduce the much required manufacturing cost.

CMOS-Compatible Room-Temperature Rectifier Toward Terahertz Radiation Detection

NASA Astrophysics Data System (ADS)

Varlamava, Volha; De Amicis, Giovanni; Del Monte, Andrea; Perticaroli, Stefano; Rao, Rosario; Palma, Fabrizio

2016-08-01

In this paper, we present a new rectifying device, compatible with the technology of CMOS image sensors, suitable for implementing a direct-conversion detector operating at room temperature for operation at up to terahertz frequencies. The rectifying device can be obtained by introducing some simple modifications of the charge-storage well in conventional CMOS integrated circuits, making the proposed solution easy to integrate with the existing imaging systems. The rectifying device is combined with the different elements of the detector, composed of a 3D high-performance antenna and a charge-storage well. In particular, its position just below the edge of the 3D antenna takes maximum advantage of the high electric field concentrated by the antenna itself. In addition, the proposed structure ensures the integrity of the charge-storage well of the detector. In the structure, it is not necessary to use very scaled and costly technological nodes, since the CMOS transistor only provides the necessary integrated readout electronics. On-wafer measurements of RF characteristics of the designed junction are reported and discussed. The overall performances of the entire detector in terms of noise equivalent power (NEP) are evaluated by combining low-frequency measurements of the rectifier with numerical simulations of the 3D antenna and the semiconductor structure at 1 THz, allowing prediction of the achievable NEP.

Fundamental performance differences between CMOS and CCD imagers: part III

NASA Astrophysics Data System (ADS)

Janesick, James; Pinter, Jeff; Potter, Robert; Elliott, Tom; Andrews, James; Tower, John; Cheng, John; Bishop, Jeanne

2009-08-01

This paper is a status report on recent scientific CMOS imager developments since when previous publications were written. Focus today is being given on CMOS design and process optimization because fundamental problems affecting performance are now reasonably well understood. Topics found in this paper include discussions on a low cost custom scientific CMOS fabrication approach, substrate bias for deep depletion imagers, near IR and x-ray point-spread performance, custom fabricated high resisitivity epitaxial and SOI silicon wafers for backside illuminated imagers, buried channel MOSFETs for ultra low noise performance, 1 e- charge transfer imagers, high speed transfer pixels, RTS/ flicker noise versus MOSFET geometry, pixel offset and gain non uniformity measurements, high S/N dCDS/aCDS signal processors, pixel thermal dark current sources, radiation damage topics, CCDs fabricated in CMOS and future large CMOS imagers planned at Sarnoff.

CMOS Image Sensors for High Speed Applications.

PubMed

El-Desouki, Munir; Deen, M Jamal; Fang, Qiyin; Liu, Louis; Tse, Frances; Armstrong, David

2009-01-01

Recent advances in deep submicron CMOS technologies and improved pixel designs have enabled CMOS-based imagers to surpass charge-coupled devices (CCD) imaging technology for mainstream applications. The parallel outputs that CMOS imagers can offer, in addition to complete camera-on-a-chip solutions due to being fabricated in standard CMOS technologies, result in compelling advantages in speed and system throughput. Since there is a practical limit on the minimum pixel size (4∼5 μm) due to limitations in the optics, CMOS technology scaling can allow for an increased number of transistors to be integrated into the pixel to improve both detection and signal processing. Such smart pixels truly show the potential of CMOS technology for imaging applications allowing CMOS imagers to achieve the image quality and global shuttering performance necessary to meet the demands of ultrahigh-speed applications. In this paper, a review of CMOS-based high-speed imager design is presented and the various implementations that target ultrahigh-speed imaging are described. This work also discusses the design, layout and simulation results of an ultrahigh acquisition rate CMOS active-pixel sensor imager that can take 8 frames at a rate of more than a billion frames per second (fps).

Fault handling schemes in electronic systems with specific application to radiation tolerance and VLSI design

NASA Technical Reports Server (NTRS)

Attia, John Okyere

1993-01-01

Naturally occurring space radiation particles can produce transient and permanent changes in the electrical properties of electronic devices and systems. In this work, the transient radiation effects on DRAM and CMOS SRAM were considered. In addition, the effect of total ionizing dose radiation of the switching times of CMOS logic gates were investigated. Effects of transient radiation on the column and cell of MOS dynamic memory cell was simulated using SPICE. It was found that the critical charge of the bitline was higher than that of the cell. In addition, the critical charge of the combined cell-bitline was found to be dependent on the gate voltage of the access transistor. In addition, the effect of total ionizing dose radiation on the switching times of CMOS logic gate was obtained. The results of this work indicate that, the rise time of CMOS logic gates increases, while the fall time decreases with an increase in total ionizing dose radiation. Also, by increasing the size of the P-channel transistor with respect to that of the N-channel transistor, the propagation delay of CMOS logic gate can be made to decrease with, or be independent of an increase in total ionizing dose radiation. Furthermore, a method was developed for replacing polysilicon feedback resistance of SRAMs with a switched capacitor network. A switched capacitor SRAM was implemented using MOS Technology. The critical change of the switched capacitor SRAM has a very large critical charge. The results of this work indicate that switched capacitor SRAM is a viable alternative to SRAM with polysilicon feedback resistance.

Ageing and proton irradiation damage of a low voltage EMCCD in a CMOS process

NASA Astrophysics Data System (ADS)

Dunford, A.; Stefanov, K.; Holland, A.

2018-02-01

Electron Multiplying Charge Coupled Devices (EMCCDs) have revolutionised low light level imaging, providing highly sensitive detection capabilities. Implementing Electron Multiplication (EM) in Charge Coupled Devices (CCDs) can increase the Signal to Noise Ratio (SNR) and lead to further developments in low light level applications such as improvements in image contrast and single photon imaging. Demand has grown for EMCCD devices with properties traditionally restricted to Complementary Metal-Oxide-Semiconductor (CMOS) image sensors, such as lower power consumption and higher radiation tolerance. However, EMCCDs are known to experience an ageing effect, such that the gain gradually decreases with time. This paper presents results detailing EM ageing in an Electron Multiplying Complementary Metal-Oxide-Semiconductor (EMCMOS) device and its effect on several device characteristics such as Charge Transfer Inefficiency (CTI) and thermal dark signal. When operated at room temperature an average decrease in gain of over 20% after an operational period of 175 hours was detected. With many image sensors deployed in harsh radiation environments, the radiation hardness of the device following proton irradiation was also tested. This paper presents the results of a proton irradiation completed at the Paul Scherrer Institut (PSI) at a 10 MeV equivalent fluence of 4.15× 1010 protons/cm2. The pre-irradiation characterisation, irradiation methodology and post-irradiation results are detailed, demonstrating an increase in dark current and a decrease in its activation energy. Finally, this paper presents a comparison of the damage caused by EM gain ageing and proton irradiation.

Development of a 750x750 pixels CMOS imager sensor for tracking applications

NASA Astrophysics Data System (ADS)

Larnaudie, Franck; Guardiola, Nicolas; Saint-Pé, Olivier; Vignon, Bruno; Tulet, Michel; Davancens, Robert; Magnan, Pierre; Corbière, Franck; Martin-Gonthier, Philippe; Estribeau, Magali

2017-11-01

Solid-state optical sensors are now commonly used in space applications (navigation cameras, astronomy imagers, tracking sensors...). Although the charge-coupled devices are still widely used, the CMOS image sensor (CIS), which performances are continuously improving, is a strong challenger for Guidance, Navigation and Control (GNC) systems. This paper describes a 750x750 pixels CMOS image sensor that has been specially designed and developed for star tracker and tracking sensor applications. Such detector, that is featuring smart architecture enabling very simple and powerful operations, is built using the AMIS 0.5μm CMOS technology. It contains 750x750 rectangular pixels with 20μm pitch. The geometry of the pixel sensitive zone is optimized for applications based on centroiding measurements. The main feature of this device is the on-chip control and timing function that makes the device operation easier by drastically reducing the number of clocks to be applied. This powerful function allows the user to operate the sensor with high flexibility: measurement of dark level from masked lines, direct access to the windows of interest… A temperature probe is also integrated within the CMOS chip allowing a very precise measurement through the video stream. A complete electro-optical characterization of the sensor has been performed. The major parameters have been evaluated: dark current and its uniformity, read-out noise, conversion gain, Fixed Pattern Noise, Photo Response Non Uniformity, quantum efficiency, Modulation Transfer Function, intra-pixel scanning. The characterization tests are detailed in the paper. Co60 and protons irradiation tests have been also carried out on the image sensor and the results are presented. The specific features of the 750x750 image sensor such as low power CMOS design (3.3V, power consumption<100mW), natural windowing (that allows efficient and robust tracking algorithms), simple proximity electronics (because of the on-chip control and timing function) enabling a high flexibility architecture, make this imager a good candidate for high performance tracking applications.

Investigation of CMOS pixel sensor with 0.18 μm CMOS technology for high-precision tracking detector

NASA Astrophysics Data System (ADS)

Zhang, L.; Fu, M.; Zhang, Y.; Yan, W.; Wang, M.

2017-01-01

The Circular Electron Positron Collider (CEPC) proposed by the Chinese high energy physics community is aiming to measure Higgs particles and their interactions precisely. The tracking detector including Silicon Inner Tracker (SIT) and Forward Tracking Disks (FTD) has driven stringent requirements on sensor technologies in term of spatial resolution, power consumption and readout speed. CMOS Pixel Sensor (CPS) is a promising candidate to approach these requirements. This paper presents the preliminary studies on the sensor optimization for tracking detector to achieve high collection efficiency while keeping necessary spatial resolution. Detailed studies have been performed on the charge collection using a 0.18 μm CMOS image sensor process. This process allows high resistivity epitaxial layer, leading to a significant improvement on the charge collection and therefore improving the radiation tolerance. Together with the simulation results, the first exploratory prototype has bee designed and fabricated. The prototype includes 9 different pixel arrays, which vary in terms of pixel pitch, diode size and geometry. The total area of the prototype amounts to 2 × 7.88 mm2.

A Pixel Readout Chip in 40 nm CMOS Process for High Count Rate Imaging Systems with Minimization of Charge Sharing Effects

DOE Office of Scientific and Technical Information (OSTI.GOV)

Maj, Piotr; Grybos, P.; Szczgiel, R.

2013-11-07

We present a prototype chip in 40 nm CMOS technology for readout of hybrid pixel detector. The prototype chip has a matrix of 18x24 pixels with a pixel pitch of 100 μm. It can operate both in single photon counting (SPC) mode and in C8P1 mode. In SPC the measured ENC is 84 e ₋rms (for the peaking time of 48 ns), while the effective offset spread is below 2 mV rms. In the C8P1 mode the chip reconstructs full charge deposited in the detector, even in the case of charge sharing, and it identifies a pixel with the largestmore » charge deposition. The chip architecture and preliminary measurements are reported.« less

The effects of the geosynchronous energetic particle radiation environment on spacecraft charging phenomena

NASA Technical Reports Server (NTRS)

Reagan, J. B.; Imhof, W. L.; Gaines, E. E.

1977-01-01

The energetic electron environment at the geosynchronous orbit is responsible for a variety of adverse charging effects on spacecraft components. The most serious of these is the degradation and failure of a complementary-metal-oxide-semiconductor (CMOS) electronic components as a result of internal charge-buildup induced by the energetic electrons. Efforts to accurately determine the expected lifetime of these components in this orbit are hampered by the lack of detailed knowledge of the electron spectrum and intensity, particularly of the more penetrating energies greater than 1.5 MeV. This problem is illustrated through the calculation of the dose received by a CMOS device from the energetic electrons and associated bremsstrahlung as a function of aluminum shielding thickness using the NASA AE-6 and the Aerospace measured electron environments. Two computational codes which were found to be in good agreement were used to perform the calculations. For a given shielding thickness the dose received with the two radiation environments differ by as much as a factor of seven with a corresponding variation in lifetime of the CMOS.

Design and Characterization of a Built-In CMOS TID Smart Sensor

NASA Astrophysics Data System (ADS)

Agustin, Javier; Gil, Carlos; Lopez-Vallejo, Marisa; Ituero, Pablo

2015-04-01

This paper describes a total ionization dose (TID) sensor that presents the following advantages: it is a digital sensor able to be integrated in CMOS circuits; it has a configurable sensitivity that allows radiation doses ranging from very low to high levels; its interface helps to integrate this design in a multidisciplinary sensor network; and it is self-timed, hence it does not need a clock signal. We designed, implemented and manufactured the sensor in a 0.35 μm CMOS commercial technology. It was irradiated with a 60Co source. This test was used to characterize the sensor in terms of the radiation response up to 575 krad. After irradiation, we monitored the sensor to control charge redistribution and annealing effects for 80 hours. We also exposed our design to meticulous temperature analysis from 0 to 50°C and we studied the acceleration on the annealing phenomena due to high temperatures. Sensor calibration takes into account the results of all tests. Finally we propose to use this sensor in a self-recovery system. The sensor manufactured in this work has an area of 0.047 mm 2, of which 22% is dedicated to measuring radiation. Its energy per conversion is 463 pJ.

Improved sensitivity to fluorescence for cancer detection in wide-field image-guided neurosurgery

PubMed Central

Jermyn, Michael; Gosselin, Yoann; Valdes, Pablo A.; Sibai, Mira; Kolste, Kolbein; Mercier, Jeanne; Angulo, Leticia; Roberts, David W.; Paulsen, Keith D.; Petrecca, Kevin; Daigle, Olivier; Wilson, Brian C.; Leblond, Frederic

2015-01-01

In glioma surgery, Protoporphyrin IX (PpIX) fluorescence may identify residual tumor that could be resected while minimizing damage to normal brain. We demonstrate that improved sensitivity for wide-field spectroscopic fluorescence imaging is achieved with minimal disruption to the neurosurgical workflow using an electron-multiplying charge-coupled device (EMCCD) relative to a state-of-the-art CMOS system. In phantom experiments the EMCCD system can detect at least two orders-of-magnitude lower PpIX. Ex vivo tissue imaging on a rat glioma model demonstrates improved fluorescence contrast compared with neurosurgical fluorescence microscope technology, and the fluorescence detection is confirmed with measurements from a clinically-validated spectroscopic probe. Greater PpIX sensitivity in wide-field fluorescence imaging may improve the residual tumor detection during surgery with consequent impact on survival. PMID:26713218

Monolithic integration of a plasmonic sensor with CMOS technology

NASA Astrophysics Data System (ADS)

Shakoor, Abdul; Cheah, Boon C.; Hao, Danni; Al-Rawhani, Mohammed; Nagy, Bence; Grant, James; Dale, Carl; Keegan, Neil; McNeil, Calum; Cumming, David R. S.

2017-02-01

Monolithic integration of nanophotonic sensors with CMOS detectors can transform the laboratory based nanophotonic sensors into practical devices with a range of applications in everyday life. In this work, by monolithically integrating an array of gold nanodiscs with the CMOS photodiode we have developed a compact and miniaturized nanophotonic sensor system having direct electrical read out. Doing so eliminates the need of expensive and bulky laboratory based optical spectrum analyzers used currently for measurements of nanophotonic sensor chips. The experimental optical sensitivity of the gold nanodiscs is measured to be 275 nm/RIU which translates to an electrical sensitivity of 5.4 V/RIU. This integration of nanophotonic sensors with the CMOS electronics has the potential to revolutionize personalized medical diagnostics similar to the way in which the CMOS technology has revolutionized the electronics industry.

Possible layout solutions for the improvement of the dark rate of geiger mode avalanche structures in the GLOBALFOUNDRIES BCDLITE 0.18 μm CMOS technology

NASA Astrophysics Data System (ADS)

D'Ascenzo, N.; Xie, Q.

2018-04-01

Modern concepts of single photon or charged particle detection systems are based on geiger mode avalanche devices developed in CMOS technology. The key-problem encountered in the fabrication of these devices in CMOS is the dark rate level. The dark rate and single photon signal are not distinguishable. This sets also the limits of the application of geiger mode avalanche devices to single photon or charged particle detection systems. We report the design and fabrication of four possible layouts of these devices using the 0.18 μm BCDLite GLOBALFOUNDRIES process. The devices have an area of 50×50 μm2. They are characterized by a fast response time and an approximately 60 ns recovery time. The best topology exhibits an average dark rate as low as 3×103 kHz/mm2.

An RF Energy Harvester System Using UHF Micropower CMOS Rectifier Based on a Diode Connected CMOS Transistor

PubMed Central

Shokrani, Mohammad Reza; Hamidon, Mohd Nizar B.; Rokhani, Fakhrul Zaman; Shafie, Suhaidi Bin

2014-01-01

This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18 μm TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier's output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18 μm TSMC CMOS technology. PMID:24782680

An RF energy harvester system using UHF micropower CMOS rectifier based on a diode connected CMOS transistor.

PubMed

Shokrani, Mohammad Reza; Khoddam, Mojtaba; Hamidon, Mohd Nizar B; Kamsani, Noor Ain; Rokhani, Fakhrul Zaman; Shafie, Suhaidi Bin

2014-01-01

This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18  μm TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier's output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18 μm TSMC CMOS technology.

Self-calibrated humidity sensor in CMOS without post-processing.

PubMed

Nizhnik, Oleg; Higuchi, Kohei; Maenaka, Kazusuke

2012-01-01

A 1.1 μW power dissipation, voltage-output humidity sensor with 10% relative humidity accuracy was developed in the LFoundry 0.15 μm CMOS technology without post-processing. The sensor consists of a woven lateral array of electrodes implemented in CMOS top metal, a humidity-sensitive layer of Intervia Photodielectric 8023D-10, a CMOS capacitance to voltage converter, and the self-calibration circuitry.

A webcam in Bayer-mode as a light beam profiler for the near infra-red

PubMed Central

Langer, Gregor; Hochreiner, Armin; Burgholzer, Peter; Berer, Thomas

2013-01-01

Beam profiles are commonly measured with complementary metal oxide semiconductors (CMOS) or charge coupled devices (CCD). The devices are fast and reliable but expensive. By making use of the fact that the Bayer-filter in commercial webcams is transparent in the near infra-red (>800 nm) and their CCD chips are sensitive up to about 1100 nm, we demonstrate a cheap and simple way to measure laser beam profiles with a resolution down to around ±1 μm, which is close to the resolution of the knife-edge technique. PMID:23645943

Design of analog pixels front-end active feedback

NASA Astrophysics Data System (ADS)

Kmon, P.; Kadlubowski, L. A.; Kaczmarczyk, P.

2018-01-01

The paper presents the design of the active feedback used in a charge-sensitive amplifier. The predominant advantages of the presented circuit are its ability for setting wide range of pulse-time widths, small silicon area occupation and low power consumption. The feedback also allows sensor leakage current compensation and, thanks to an additional DC amplifier, it minimizes the output DC voltage variations, which is especially important in the DC coupled recording chain and for processes with limited supply voltage. The paper provides feedback description and its operation principle. The proposed circuit was designed in the CMOS 130nm technology.

Development of CMOS Active Pixel Image Sensors for Low Cost Commercial Applications

NASA Technical Reports Server (NTRS)

Gee, R.; Kemeny, S.; Kim, Q.; Mendis, S.; Nakamura, J.; Nixon, R.; Ortiz, M.; Pain, B.; Staller, C.; Zhou, Z;

A webcam in Bayer-mode as a light beam profiler for the near infra-red.

PubMed

Langer, Gregor; Hochreiner, Armin; Burgholzer, Peter; Berer, Thomas

2013-05-01

Beam profiles are commonly measured with complementary metal oxide semiconductors (CMOS) or charge coupled devices (CCD). The devices are fast and reliable but expensive. By making use of the fact that the Bayer-filter in commercial webcams is transparent in the near infra-red (>800 nm) and their CCD chips are sensitive up to about 1100 nm, we demonstrate a cheap and simple way to measure laser beam profiles with a resolution down to around ±1 μm, which is close to the resolution of the knife-edge technique.

A Charge Sensitive Pre-Amplifier for Smart Point-of-Care Devices Employing Polymer Based Lab-on-a-Chip

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Hanfeng; Britton, Charles; Quaiyum, Farhan

With increasing emphasis on implantable and portable medical devices, low-power, small-chip-area sensor readout system realized in lab-on-a-chip (LOC) platform is gaining more and more importance these days. The main building blocks of the LOC system include a front-end transducer that generates an electrical signal in response to the presence of an analyte of interest, signal processing electronics to process the signal to comply with a specific transmission protocol and a low-power transmitter, all realized in a single integrated circuit platform. Low power consumption and compactness of the components are essential requirements of the LOC system. This paper presents a novelmore » charge sensitive pre-amplifier developed in a standard 180-nm CMOS process suitable for implementing in an LOC platform. The pre-amplifier converts the charge generated by a pyroelectric transducer into a voltage signal, which provides a measurement of the temperature variation in biological fluids. The proposed design is capable of providing 0.8-mV/pC gain while consuming only 2.1 μW of power. Finally, the pre-amplifier composed of integrated components occupies an area of 0.038 mm 2.« less

A Charge Sensitive Pre-Amplifier for Smart Point-of-Care Devices Employing Polymer Based Lab-on-a-Chip

DOE PAGES

Wang, Hanfeng; Britton, Charles; Quaiyum, Farhan; ...

2018-01-01

With increasing emphasis on implantable and portable medical devices, low-power, small-chip-area sensor readout system realized in lab-on-a-chip (LOC) platform is gaining more and more importance these days. The main building blocks of the LOC system include a front-end transducer that generates an electrical signal in response to the presence of an analyte of interest, signal processing electronics to process the signal to comply with a specific transmission protocol and a low-power transmitter, all realized in a single integrated circuit platform. Low power consumption and compactness of the components are essential requirements of the LOC system. This paper presents a novelmore » charge sensitive pre-amplifier developed in a standard 180-nm CMOS process suitable for implementing in an LOC platform. The pre-amplifier converts the charge generated by a pyroelectric transducer into a voltage signal, which provides a measurement of the temperature variation in biological fluids. The proposed design is capable of providing 0.8-mV/pC gain while consuming only 2.1 μW of power. Finally, the pre-amplifier composed of integrated components occupies an area of 0.038 mm 2.« less

A 128 x 128 CMOS Active Pixel Image Sensor for Highly Integrated Imaging Systems

NASA Technical Reports Server (NTRS)

Mendis, Sunetra K.; Kemeny, Sabrina E.; Fossum, Eric R.

1993-01-01

A new CMOS-based image sensor that is intrinsically compatible with on-chip CMOS circuitry is reported. The new CMOS active pixel image sensor achieves low noise, high sensitivity, X-Y addressability, and has simple timing requirements. The image sensor was fabricated using a 2 micrometer p-well CMOS process, and consists of a 128 x 128 array of 40 micrometer x 40 micrometer pixels. The CMOS image sensor technology enables highly integrated smart image sensors, and makes the design, incorporation and fabrication of such sensors widely accessible to the integrated circuit community.

Ultrahigh sensitivity endoscopic camera using a new CMOS image sensor: providing with clear images under low illumination in addition to fluorescent images.

PubMed

Aoki, Hisae; Yamashita, Hiromasa; Mori, Toshiyuki; Fukuyo, Tsuneo; Chiba, Toshio

2014-11-01

We developed a new ultrahigh-sensitive CMOS camera using a specific sensor that has a wide range of spectral sensitivity characteristics. The objective of this study is to present our updated endoscopic technology that has successfully integrated two innovative functions; ultrasensitive imaging as well as advanced fluorescent viewing. Two different experiments were conducted. One was carried out to evaluate the function of the ultrahigh-sensitive camera. The other was to test the availability of the newly developed sensor and its performance as a fluorescence endoscope. In both studies, the distance from the endoscopic tip to the target was varied and those endoscopic images in each setting were taken for further comparison. In the first experiment, the 3-CCD camera failed to display the clear images under low illumination, and the target was hardly seen. In contrast, the CMOS camera was able to display the targets regardless of the camera-target distance under low illumination. Under high illumination, imaging quality given by both cameras was quite alike. In the second experiment as a fluorescence endoscope, the CMOS camera was capable of clearly showing the fluorescent-activated organs. The ultrahigh sensitivity CMOS HD endoscopic camera is expected to provide us with clear images under low illumination in addition to the fluorescent images under high illumination in the field of laparoscopic surgery.

Organic-on-silicon complementary metal-oxide-semiconductor colour image sensors.

PubMed

Lim, Seon-Jeong; Leem, Dong-Seok; Park, Kyung-Bae; Kim, Kyu-Sik; Sul, Sangchul; Na, Kyoungwon; Lee, Gae Hwang; Heo, Chul-Joon; Lee, Kwang-Hee; Bulliard, Xavier; Satoh, Ryu-Ichi; Yagi, Tadao; Ro, Takkyun; Im, Dongmo; Jung, Jungkyu; Lee, Myungwon; Lee, Tae-Yon; Han, Moon Gyu; Jin, Yong Wan; Lee, Sangyoon

2015-01-12

Complementary metal-oxide-semiconductor (CMOS) colour image sensors are representative examples of light-detection devices. To achieve extremely high resolutions, the pixel sizes of the CMOS image sensors must be reduced to less than a micron, which in turn significantly limits the number of photons that can be captured by each pixel using silicon (Si)-based technology (i.e., this reduction in pixel size results in a loss of sensitivity). Here, we demonstrate a novel and efficient method of increasing the sensitivity and resolution of the CMOS image sensors by superposing an organic photodiode (OPD) onto a CMOS circuit with Si photodiodes, which consequently doubles the light-input surface area of each pixel. To realise this concept, we developed organic semiconductor materials with absorption properties selective to green light and successfully fabricated highly efficient green-light-sensitive OPDs without colour filters. We found that such a top light-receiving OPD, which is selective to specific green wavelengths, demonstrates great potential when combined with a newly designed Si-based CMOS circuit containing only blue and red colour filters. To demonstrate the effectiveness of this state-of-the-art hybrid colour image sensor, we acquired a real full-colour image using a camera that contained the organic-on-Si hybrid CMOS colour image sensor.

Organic-on-silicon complementary metal–oxide–semiconductor colour image sensors

PubMed Central

Lim, Seon-Jeong; Leem, Dong-Seok; Park, Kyung-Bae; Kim, Kyu-Sik; Sul, Sangchul; Na, Kyoungwon; Lee, Gae Hwang; Heo, Chul-Joon; Lee, Kwang-Hee; Bulliard, Xavier; Satoh, Ryu-Ichi; Yagi, Tadao; Ro, Takkyun; Im, Dongmo; Jung, Jungkyu; Lee, Myungwon; Lee, Tae-Yon; Han, Moon Gyu; Jin, Yong Wan; Lee, Sangyoon

2015-01-01

Complementary metal–oxide–semiconductor (CMOS) colour image sensors are representative examples of light-detection devices. To achieve extremely high resolutions, the pixel sizes of the CMOS image sensors must be reduced to less than a micron, which in turn significantly limits the number of photons that can be captured by each pixel using silicon (Si)-based technology (i.e., this reduction in pixel size results in a loss of sensitivity). Here, we demonstrate a novel and efficient method of increasing the sensitivity and resolution of the CMOS image sensors by superposing an organic photodiode (OPD) onto a CMOS circuit with Si photodiodes, which consequently doubles the light-input surface area of each pixel. To realise this concept, we developed organic semiconductor materials with absorption properties selective to green light and successfully fabricated highly efficient green-light-sensitive OPDs without colour filters. We found that such a top light-receiving OPD, which is selective to specific green wavelengths, demonstrates great potential when combined with a newly designed Si-based CMOS circuit containing only blue and red colour filters. To demonstrate the effectiveness of this state-of-the-art hybrid colour image sensor, we acquired a real full-colour image using a camera that contained the organic-on-Si hybrid CMOS colour image sensor. PMID:25578322

Design and characterization of high precision in-pixel discriminators for rolling shutter CMOS pixel sensors with full CMOS capability

NASA Astrophysics Data System (ADS)

Fu, Y.; Hu-Guo, C.; Dorokhov, A.; Pham, H.; Hu, Y.

2013-07-01

In order to exploit the ability to integrate a charge collecting electrode with analog and digital processing circuitry down to the pixel level, a new type of CMOS pixel sensors with full CMOS capability is presented in this paper. The pixel array is read out based on a column-parallel read-out architecture, where each pixel incorporates a diode, a preamplifier with a double sampling circuitry and a discriminator to completely eliminate analog read-out bottlenecks. The sensor featuring a pixel array of 8 rows and 32 columns with a pixel pitch of 80 μm×16 μm was fabricated in a 0.18 μm CMOS process. The behavior of each pixel-level discriminator isolated from the diode and the preamplifier was studied. The experimental results indicate that all in-pixel discriminators which are fully operational can provide significant improvements in the read-out speed and the power consumption of CMOS pixel sensors.

Pick-and-place process for sensitivity improvement of the capacitive type CMOS MEMS 2-axis tilt sensor

NASA Astrophysics Data System (ADS)

Chang, Chun-I.; Tsai, Ming-Han; Liu, Yu-Chia; Sun, Chih-Ming; Fang, Weileun

2013-09-01

This study exploits the foundry available complimentary metal-oxide-semiconductor (CMOS) process and the packaging house available pick-and-place technology to implement a capacitive type micromachined 2-axis tilt sensor. The suspended micro mechanical structures such as the spring, stage and sensing electrodes are fabricated using the CMOS microelectromechanical systems (MEMS) processes. A bulk block is assembled onto the suspended stage by pick-and-place technology to increase the proof-mass of the tilt sensor. The low temperature UV-glue dispensing and curing processes are employed to bond the block onto the stage. Thus, the sensitivity of the CMOS MEMS capacitive type 2-axis tilt sensor is significantly improved. In application, this study successfully demonstrates the bonding of a bulk solder ball of 100 µm in diameter with a 2-axis tilt sensor fabricated using the standard TSMC 0.35 µm 2P4M CMOS process. Measurements show the sensitivities of the 2-axis tilt sensor are increased for 2.06-fold (x-axis) and 1.78-fold (y-axis) after adding the solder ball. Note that the sensitivity can be further improved by reducing the parasitic capacitance and the mismatch of sensing electrodes caused by the solder ball.

Micro-scale characterization of a CMOS-based neutron detector for in-phantom measurements in radiation therapy

NASA Astrophysics Data System (ADS)

Arbor, Nicolas; Higueret, Stephane; Husson, Daniel

2018-04-01

The CMOS sensor AlphaRad has been designed at the IPHC Strasbourg for real-time monitoring of fast and thermal neutrons over a full energy spectrum. Completely integrated, highly transparent to photons and optimized for low power consumption, this sensor offers very interesting characteristics for the study of internal neutrons in radiation therapy with anthropomorphic phantoms. However, specific effects related to the CMOS metal substructure and to the charge collection process of low energy particles must be carefully estimated before being used for medical applications. We present a detailed characterization of the AlphaRad chip in the MeV energy range using proton and alpha micro-beam experiments performed at the AIFIRA facility (CENBG, Bordeaux). Two-dimensional maps of the charge collection were carried out on a micro-metric scale to be integrated into a Geant4 Monte Carlo simulation of the system. The gamma rejection, as well as the fast and thermal neutrons separation, were studied using both simulation and experimental data. The results highlight the potential of a future system based on CMOS sensor for in-phantom neutron detection in radiation therapies.

Charge collection and non-ionizing radiation tolerance of CMOS pixel sensors using a 0.18 μm CMOS process

NASA Astrophysics Data System (ADS)

Zhang, Ying; Zhu, Hongbo; Zhang, Liang; Fu, Min

2016-09-01

The proposed Circular Electron Positron Collider (CEPC) will be primarily aimed for precision measurements of the discovered Higgs boson. Its innermost vertex detector, which will play a critical role in heavy-flavor tagging, must be constructed with fine-pitched silicon pixel sensors with low power consumption and fast readout. CMOS pixel sensor (CPS), as one of the most promising candidate technologies, has already demonstrated its excellent performance in several high energy physics experiments. Therefore it has been considered for R&D for the CEPC vertex detector. In this paper, we present the preliminary studies to improve the collected signal charge over the equivalent input capacitance ratio (Q / C), which will be crucial to reduce the analog power consumption. We have performed detailed 3D device simulation and evaluated potential impacts from diode geometry, epitaxial layer properties and non-ionizing radiation damage. We have proposed a new approach to improve the treatment of the boundary conditions in simulation. Along with the TCAD simulation, we have designed the exploratory prototype utilizing the TowerJazz 0.18 μm CMOS imaging sensor process and we will verify the simulation results with future measurements.

Camera-on-a-Chip

NASA Technical Reports Server (NTRS)

1999-01-01

Jet Propulsion Laboratory's research on a second generation, solid-state image sensor technology has resulted in the Complementary Metal- Oxide Semiconductor Active Pixel Sensor (CMOS), establishing an alternative to the Charged Coupled Device (CCD). Photobit Corporation, the leading supplier of CMOS image sensors, has commercialized two products of their own based on this technology: the PB-100 and PB-300. These devices are cameras on a chip, combining all camera functions. CMOS "active-pixel" digital image sensors offer several advantages over CCDs, a technology used in video and still-camera applications for 30 years. The CMOS sensors draw less energy, they use the same manufacturing platform as most microprocessors and memory chips, and they allow on-chip programming of frame size, exposure, and other parameters.

Single phase dynamic CMOS PLA using charge sharing technique

NASA Technical Reports Server (NTRS)

Dhong, Y. B.; Tsang, C. P.

1991-01-01

A single phase dynamic CMOS NOR-NOR programmable logic array (PLA) using triggered decoders and charge sharing techniques for high speed and low power is presented. By using the triggered decoder technique, the ground switches are eliminated, thereby, making this new design much faster and lower power dissipation than conventional PLA's. By using the charge-sharing technique in a dynamic CMOS NOR structure, a cascading AND gate can be implemented. The proposed PLA's are presented with a delay-time of 15.95 and 18.05 nsec, respectively, which compare with a conventional single phase PLA with 35.5 nsec delay-time. For a typical example of PLA like the Signetics 82S100 with 16 inputs, 48 input minterms (m) and 8 output minterms (n), the 2-SOP PLA using the triggered 2-bit decoder is 2.23 times faster and has 2.1 times less power dissipation than the conventional PLA. These results are simulated using maximum drain current of 600 micro-A, gate length of 2.0 micron, V sub DD of 5 V, the capacitance of an input miniterm of 1600 fF, and the capacitance of an output minterm of 1500 fF.

Pitch dependence of the tolerance of CMOS monolithic active pixel sensors to non-ionizing radiation

NASA Astrophysics Data System (ADS)

Doering, D.; Deveaux, M.; Domachowski, M.; Fröhlich, I.; Koziel, M.; Müntz, C.; Scharrer, P.; Stroth, J.

2013-12-01

CMOS monolithic active pixel sensors (MAPS) have demonstrated excellent performance as tracking detectors for charged particles. They provide an outstanding spatial resolution (a few μm), a detection efficiency of ≳ 99.9 %, very low material budget (0.05 %X0) and good radiation tolerance (≳ 1 Mrad, ≳1013neq /cm2) (Deveaux et al. [1]). This makes them an interesting technology for various applications in heavy ion and particle physics. Their tolerance to bulk damage was recently improved by using high-resistivity (∼ 1 kΩ cm) epitaxial layers as sensitive volume (Deveaux et al. [1], Dorokhov et al. [2]). The radiation tolerance of conventional MAPS is known to depend on the pixel pitch. This is as a higher pitch extends the distance, which signal electrons have to travel by thermal diffusion before being collected. Increased diffusion paths turn into a higher probability of loosing signal charge due to recombination. Provided that a similar effect exists in MAPS with high-resistivity epitaxial layer, it could be used to extend their radiation tolerance further. We addressed this question with MIMOSA-18AHR prototypes, which were provided by the IPHC Strasbourg and irradiated with reactor neutrons. We report about the results of this study and provide evidences that MAPS with 10 μm pixel pitch tolerate doses of ≳ 3 ×1014neq /cm2.

UHF front-end feeding RFID-based body sensor networks by exploiting the reader signal

NASA Astrophysics Data System (ADS)

Pasca, M.; Colella, R.; Catarinucci, L.; Tarricone, L.; D'Amico, S.; Baschirotto, A.

2016-05-01

This paper presents an integrated, high-sensitivity UHF radio frequency identification (RFID) power management circuit for body sensor network applications. The circuit consists of a two-stage RF-DC Dickson's rectifier followed by an integrated five-stage DC-DC Pelliconi's charge pump driven by an ultralow start-up voltage LC oscillator. The DC-DC charge pump interposed between the RF-DC rectifier and the output load provides the RF to load isolation avoiding losses due to the diodes reverse saturation current. The RF-DC rectifier has been realized on FR4 substrate, while the charge pump and the oscillator have been realized in 180 nm complementary metal oxide semiconductor (CMOS) technology. Outdoor measurements demonstrate the ability of the power management circuit to provide 400 mV output voltage at 14 m distance from the UHF reader, in correspondence of -25 dBm input signal power. As demonstrated in the literature, such output voltage level is suitable to supply body sensor network nodes.

Geiger-Mode Avalanche Photodiode Arrays Integrated to All-Digital CMOS Circuits.

PubMed

Aull, Brian

2016-04-08

This article reviews MIT Lincoln Laboratory's work over the past 20 years to develop photon-sensitive image sensors based on arrays of silicon Geiger-mode avalanche photodiodes. Integration of these detectors to all-digital CMOS readout circuits enable exquisitely sensitive solid-state imagers for lidar, wavefront sensing, and passive imaging.

A MEMS Interface IC With Low-Power and Wide-Range Frequency-to-Voltage Converter for Biomedical Applications.

PubMed

Arefin, Md Shamsul; Redouté, Jean-Michel; Yuce, Mehmet Rasit

2016-04-01

This paper presents an interface circuit for capacitive and inductive MEMS biosensors using an oscillator and a charge pump based frequency-to-voltage converter. Frequency modulation using a differential crossed coupled oscillator is adopted to sense capacitive and inductive changes. The frequency-to-voltage converter is designed with a negative feedback system and external controlling parameters to adjust the sensitivity, dynamic range, and nominal point for the measurement. The sensitivity of the frequency-to-voltage converter is from 13.28 to 35.96 mV/MHz depending on external voltage and charging current. The sensitivity ranges of the capacitive and inductive interface circuit are 17.08 to 54.4 mV/pF and 32.11 to 82.88 mV/mH, respectively. A capacitive MEMS based pH sensor is also connected with the interface circuit to measure the high acidic gastric acid throughout the digestive tract. The sensitivity for pH from 1 to 3 is 191.4 mV/pH with 550 μV(pp) noise. The readout circuit is designed and fabricated using the UMC 0.18 μm CMOS technology. It occupies an area of 0.18 mm (2) and consumes 11.8 mW.

Fabrication and Characterization of a Micro Methanol Sensor Using the CMOS-MEMS Technique.

PubMed

Fong, Chien-Fu; Dai, Ching-Liang; Wu, Chyan-Chyi

2015-10-23

A methanol microsensor integrated with a micro heater manufactured using the complementary metal oxide semiconductor (CMOS)-microelectromechanical system (MEMS) technique was presented. The sensor has a capability of detecting low concentration methanol gas. Structure of the sensor is composed of interdigitated electrodes, a sensitive film and a heater. The heater located under the interdigitated electrodes is utilized to provide a working temperature to the sensitive film. The sensitive film prepared by the sol-gel method is tin dioxide doped cadmium sulfide, which is deposited on the interdigitated electrodes. To obtain the suspended structure and deposit the sensitive film, the sensor needs a post-CMOS process to etch the sacrificial silicon dioxide layer and silicon substrate. The methanol senor is a resistive type. A readout circuit converts the resistance variation of the sensor into the output voltage. The experimental results show that the methanol sensor has a sensitivity of 0.18 V/ppm.

Fabrication and Characterization of a Micro Methanol Sensor Using the CMOS-MEMS Technique

PubMed Central

Fong, Chien-Fu; Dai, Ching-Liang; Wu, Chyan-Chyi

2015-01-01

A methanol microsensor integrated with a micro heater manufactured using the complementary metal oxide semiconductor (CMOS)-microelectromechanical system (MEMS) technique was presented. The sensor has a capability of detecting low concentration methanol gas. Structure of the sensor is composed of interdigitated electrodes, a sensitive film and a heater. The heater located under the interdigitated electrodes is utilized to provide a working temperature to the sensitive film. The sensitive film prepared by the sol-gel method is tin dioxide doped cadmium sulfide, which is deposited on the interdigitated electrodes. To obtain the suspended structure and deposit the sensitive film, the sensor needs a post-CMOS process to etch the sacrificial silicon dioxide layer and silicon substrate. The methanol senor is a resistive type. A readout circuit converts the resistance variation of the sensor into the output voltage. The experimental results show that the methanol sensor has a sensitivity of 0.18 V/ppm. PMID:26512671

A Multidisciplinary Approach to High Throughput Nuclear Magnetic Resonance Spectroscopy

PubMed Central

Pourmodheji, Hossein; Ghafar-Zadeh, Ebrahim; Magierowski, Sebastian

2016-01-01

Nuclear Magnetic Resonance (NMR) is a non-contact, powerful structure-elucidation technique for biochemical analysis. NMR spectroscopy is used extensively in a variety of life science applications including drug discovery. However, existing NMR technology is limited in that it cannot run a large number of experiments simultaneously in one unit. Recent advances in micro-fabrication technologies have attracted the attention of researchers to overcome these limitations and significantly accelerate the drug discovery process by developing the next generation of high-throughput NMR spectrometers using Complementary Metal Oxide Semiconductor (CMOS). In this paper, we examine this paradigm shift and explore new design strategies for the development of the next generation of high-throughput NMR spectrometers using CMOS technology. A CMOS NMR system consists of an array of high sensitivity micro-coils integrated with interfacing radio-frequency circuits on the same chip. Herein, we first discuss the key challenges and recent advances in the field of CMOS NMR technology, and then a new design strategy is put forward for the design and implementation of highly sensitive and high-throughput CMOS NMR spectrometers. We thereafter discuss the functionality and applicability of the proposed techniques by demonstrating the results. For microelectronic researchers starting to work in the field of CMOS NMR technology, this paper serves as a tutorial with comprehensive review of state-of-the-art technologies and their performance levels. Based on these levels, the CMOS NMR approach offers unique advantages for high resolution, time-sensitive and high-throughput bimolecular analysis required in a variety of life science applications including drug discovery. PMID:27294925

CMOS image sensor for detection of interferon gamma protein interaction as a point-of-care approach.

PubMed

Marimuthu, Mohana; Kandasamy, Karthikeyan; Ahn, Chang Geun; Sung, Gun Yong; Kim, Min-Gon; Kim, Sanghyo

2011-09-01

Complementary metal oxide semiconductor (CMOS)-based image sensors have received increased attention owing to the possibility of incorporating them into portable diagnostic devices. The present research examined the efficiency and sensitivity of a CMOS image sensor for the detection of antigen-antibody interactions involving interferon gamma protein without the aid of expensive instruments. The highest detection sensitivity of about 1 fg/ml primary antibody was achieved simply by a transmission mechanism. When photons are prevented from hitting the sensor surface, a reduction in digital output occurs in which the number of photons hitting the sensor surface is approximately proportional to the digital number. Nanoscale variation in substrate thickness after protein binding can be detected with high sensitivity by the CMOS image sensor. Therefore, this technique can be easily applied to smartphones or any clinical diagnostic devices for the detection of several biological entities, with high impact on the development of point-of-care applications.

CMOS image sensor with lateral electric field modulation pixels for fluorescence lifetime imaging with sub-nanosecond time response

NASA Astrophysics Data System (ADS)

Li, Zhuo; Seo, Min-Woong; Kagawa, Keiichiro; Yasutomi, Keita; Kawahito, Shoji

2016-04-01

This paper presents the design and implementation of a time-resolved CMOS image sensor with a high-speed lateral electric field modulation (LEFM) gating structure for time domain fluorescence lifetime measurement. Time-windowed signal charge can be transferred from a pinned photodiode (PPD) to a pinned storage diode (PSD) by turning on a pair of transfer gates, which are situated beside the channel. Unwanted signal charge can be drained from the PPD to the drain by turning on another pair of gates. The pixel array contains 512 (V) × 310 (H) pixels with 5.6 × 5.6 µm2 pixel size. The imager chip was fabricated using 0.11 µm CMOS image sensor process technology. The prototype sensor has a time response of 150 ps at 374 nm. The fill factor of the pixels is 5.6%. The usefulness of the prototype sensor is demonstrated for fluorescence lifetime imaging through simulation and measurement results.

Experiments with synchronized sCMOS cameras

NASA Astrophysics Data System (ADS)

Steele, Iain A.; Jermak, Helen; Copperwheat, Chris M.; Smith, Robert J.; Poshyachinda, Saran; Soonthorntham, Boonrucksar

2016-07-01

Scientific-CMOS (sCMOS) cameras can combine low noise with high readout speeds and do not suffer the charge multiplication noise that effectively reduces the quantum efficiency of electron multiplying CCDs by a factor 2. As such they have strong potential in fast photometry and polarimetry instrumentation. In this paper we describe the results of laboratory experiments using a pair of commercial off the shelf sCMOS cameras based around a 4 transistor per pixel architecture. In particular using a both stable and a pulsed light sources we evaluate the timing precision that may be obtained when the cameras readouts are synchronized either in software or electronically. We find that software synchronization can introduce an error of 200-msec. With electronic synchronization any error is below the limit ( 50-msec) of our simple measurement technique.

Graphene/Si CMOS Hybrid Hall Integrated Circuits

PubMed Central

Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

2014-01-01

Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18 um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process. PMID:24998222

Graphene/Si CMOS hybrid hall integrated circuits.

PubMed

Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

2014-07-07

Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18 um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process.

Highly sensitive and area-efficient CMOS image sensor using a PMOSFET-type photodetector with a built-in transfer gate

NASA Astrophysics Data System (ADS)

Seo, Sang-Ho; Kim, Kyoung-Do; Kong, Jae-Sung; Shin, Jang-Kyoo; Choi, Pyung

2007-02-01

In this paper, a new CMOS image sensor is presented, which uses a PMOSFET-type photodetector with a transfer gate that has a high and variable sensitivity. The proposed CMOS image sensor has been fabricated using a 0.35 μm 2-poly 4- metal standard CMOS technology and is composed of a 256 × 256 array of 7.05 × 7.10 μm pixels. The unit pixel has a configuration of a pseudo 3-transistor active pixel sensor (APS) with the PMOSFET-type photodetector with a transfer gate, which has a function of conventional 4-transistor APS. The generated photocurrent is controlled by the transfer gate of the PMOSFET-type photodetector. The maximum responsivity of the photodetector is larger than 1.0 × 10 3 A/W without any optical lens. Fabricated 256 × 256 CMOS image sensor exhibits a good response to low-level illumination as low as 5 lux.

Advancing the Technology of Monolithic CMOS detectors for their use as X-ray Imaging Spectrometers

NASA Astrophysics Data System (ADS)

Kenter, Almus

The Smithsonian Astrophysical Observatory (SAO) proposes a two year program to further advance the scientific capabilities of monolithic CMOS detectors for use as x-ray imaging spectrometers. This proposal will build upon the progress achieved with funding from a previous APRA proposal that ended in 2013. As part of that previous proposal, x- ray optimized, highly versatile, monolithic CMOS imaging detectors and technology were developed and tested. The performance and capabilities of these devices were then demonstrated, with an emphasis on the performance advantages these devices have over CCDs and other technologies. The developed SAO/SRI-Sarnoff CMOS devices incorporate: Low noise, high sensitivity ("gain") pixels; Highly parallel on-chip signal chains; Standard and very high resistivity (30,000Ohm-cm) Si; Back-Side thinning and passivation. SAO demonstrated the performance benefits of each of these features in these devices. This new proposal high-lights the performance of this previous generation of devices, and segues into new technology and capability. The high sensitivity ( 135uV/e) 6 Transistor (6T) Pinned Photo Diode (PPD) pixels provided a large charge to voltage conversion gain to the detect and resolve even small numbers of photo electrons produced by x-rays. The on-chip, parallel signal chain processed an entire row of pixels in the same time that a CCD requires to processes a single pixel. The resulting high speed operation ( 1000 times faster than CCD) provide temporal resolution while mitigating dark current and allowed room temperature operation. The high resistivity Si provided full (over) depletion for thicker devices which increased QE for higher energy x-rays. In this proposal, SAO will investigate existing NMOS and existing PMOS devices as xray imaging spectrometers. Conventional CMOS imagers are NMOS. NMOS devices collect and measure photo-electrons. In contrast, PMOS devices collect and measure photo-holes. PMOS devices have various attributes that would make them superior for use in X-ray astronomy. In particular, PMOS has: "no" photo-charge recombination; "no" Random Telegraph Signal noise (RTS); and lower read noise. The existing SRI/Sarnoff PMOS devices are small and have been developed for non-intensified night vision applications, however, no x-ray evaluation of a monolithic PMOS device has ever been made. In addition to these PMOS devices, SAO will also evaluate existing NMOS scale-able format devices that can be fabricated in any rectangular size/shape using stitchable reticles. These "Mk by Nk" devices would be ideal for large X-ray focal planes or long grating readouts. The Sarnoff/SRI Mk by Nk format devices have been designed, with foresight, so that they can be fabricated in either PMOS or NMOS by changing a single fabrication reticle and by changing the type of Si substrate. If X-ray performance results are expected, this proposal will lead the way to future fabrication of Mk by Nk PMOS devices that would be ideal for X-ray astronomy missions such as "X-ray Surveyor". SAO will also investigate the interaction of directly deposited Optical Blocking Filters (OBFs) on various back side passivated devices, and their resultant effects on very "soft" x-ray response. The latest CMOS processes and very fast on-chip, and off-chip digital readout signal chains and camera systems will be demonstrated.

Read disturb errors in a CMOS static RAM chip. [radiation hardened for spacedraft

NASA Technical Reports Server (NTRS)

Wood, Steven H.; Marr, James C., IV; Nguyen, Tien T.; Padgett, Dwayne J.; Tran, Joe C.; Griswold, Thomas W.; Lebowitz, Daniel C.

1989-01-01

Results are reported from an extensive investigation into pattern-sensitive soft errors (read disturb errors) in the TCC244 CMOS static RAM chip. The TCC244, also known as the SA2838, is a radiation-hard single-event-upset-resistant 4 x 256 memory chip. This device is being used by the Jet Propulsion Laboratory in the Galileo and Magellan spacecraft, which will have encounters with Jupiter and Venus, respectively. Two aspects of the part's design are shown to result in the occurrence of read disturb errors: the transparence of the signal path from the address pins to the array of cells, and the large resistance in the Vdd and Vss lines of the cells in the center of the array. Probe measurements taken during a read disturb failure illustrate how address skews and the data pattern in the chip combine to produce a bit flip. A capacitive charge pump formed by the individual cell capacitances and the resistance in the supply lines pumps down both the internal cell voltage and the local supply voltage until a bit flip occurs.

P-channel differential multiple-time programmable memory cells by laterally coupled floating metal gate fin field-effect transistors

NASA Astrophysics Data System (ADS)

Wang, Tai-Min; Chien, Wei-Yu; Hsu, Chia-Ling; Lin, Chrong Jung; King, Ya-Chin

2018-04-01

In this paper, we present a new differential p-channel multiple-time programmable (MTP) memory cell that is fully compatible with advanced 16 nm CMOS fin field-effect transistors (FinFET) logic processes. This differential MTP cell stores complementary data in floating gates coupled by a slot contact structure, which make different read currents possible on a single cell. In nanoscale CMOS FinFET logic processes, the gate dielectric layer becomes too thin to retain charges inside floating gates for nonvolatile data storage. By using a differential architecture, the sensing window of the cell can be extended and maintained by an advanced blanket boost scheme. The charge retention problem in floating gate cells can be improved by periodic restoring lost charges when significant read window narrowing occurs. In addition to high programming efficiency, this p-channel MTP cells also exhibit good cycling endurance as well as disturbance immunity. The blanket boost scheme can remedy the charge loss problem under thin gate dielectrics.

Modeling methodology for a CMOS-MEMS electrostatic comb

NASA Astrophysics Data System (ADS)

Iyer, Sitaraman V.; Lakdawala, Hasnain; Mukherjee, Tamal; Fedder, Gary K.

2002-04-01

A methodology for combined modeling of capacitance and force 9in a multi-layer electrostatic comb is demonstrated in this paper. Conformal mapping-based analytical methods are limited to 2D symmetric cross-sections and cannot account for charge concentration effects at corners. Vertex capacitance can be more than 30% of the total capacitance in a single-layer 2 micrometers thick comb with 10 micrometers overlap. Furthermore, analytical equations are strictly valid only for perfectly symmetrical finger positions. Fringing and corner effects are likely to be more significant in a multi- layered CMOS-MEMS comb because of the presence of more edges and vertices. Vertical curling of CMOS-MEMS comb fingers may also lead to reduced capacitance and vertical forces. Gyroscopes are particularly sensitive to such undesirable forces, which therefore, need to be well-quantified. In order to address the above issues, a hybrid approach of superposing linear regression models over a set of core analytical models is implemented. Design of experiments is used to obtain data for capacitance and force using a commercial 3D boundary-element solver. Since accurate force values require significantly higher mesh refinement than accurate capacitance, we use numerical derivatives of capacitance values to compute the forces. The model is formulated such that the capacitance and force models use the same regression coefficients. The comb model thus obtained, fits the numerical capacitance data to within +/- 3% and force to within +/- 10%. The model is experimentally verified by measuring capacitance change in a specially designed test structure. The capacitance model matches measurements to within 10%. The comb model is implemented in an Analog Hardware Description Language (ADHL) for use in behavioral simulation of manufacturing variations in a CMOS-MEMS gyroscope.

A highly sensitive CMOS digital Hall sensor for low magnetic field applications.

PubMed

Xu, Yue; Pan, Hong-Bin; He, Shu-Zhuan; Li, Li

2012-01-01

Integrated CMOS Hall sensors have been widely used to measure magnetic fields. However, they are difficult to work with in a low magnetic field environment due to their low sensitivity and large offset. This paper describes a highly sensitive digital Hall sensor fabricated in 0.18 μm high voltage CMOS technology for low field applications. The sensor consists of a switched cross-shaped Hall plate and a novel signal conditioner. It effectively eliminates offset and low frequency 1/f noise by applying a dynamic quadrature offset cancellation technique. The measured results show the optimal Hall plate achieves a high current related sensitivity of about 310 V/AT. The whole sensor has a remarkable ability to measure a minimum ± 2 mT magnetic field and output a digital Hall signal in a wide temperature range from -40 °C to 120 °C.

Microprocessor control of photovoltaic systems

NASA Technical Reports Server (NTRS)

Millner, A. R.; Kaufman, D. L.

1984-01-01

The present low power CMOS microprocessor controller for photovoltaic power systems possesses three programs, which are respectively intended for (1) conventional battery-charging systems with state-of-charge estimation and sequential shedding of subarrays and loads, (2) maximum power-controlled battery-charging systems, and (3) variable speed dc motor drives. Attention is presently given to the development of this terrestrial equipment for spacecraft use.

Temporal Noise Analysis of Charge-Domain Sampling Readout Circuits for CMOS Image Sensors.

PubMed

Ge, Xiaoliang; Theuwissen, Albert J P

2018-02-27

This paper presents a temporal noise analysis of charge-domain sampling readout circuits for Complementary Metal-Oxide Semiconductor (CMOS) image sensors. In order to address the trade-off between the low input-referred noise and high dynamic range, a Gm-cell-based pixel together with a charge-domain correlated-double sampling (CDS) technique has been proposed to provide a way to efficiently embed a tunable conversion gain along the read-out path. Such readout topology, however, operates in a non-stationery large-signal behavior, and the statistical properties of its temporal noise are a function of time. Conventional noise analysis methods for CMOS image sensors are based on steady-state signal models, and therefore cannot be readily applied for Gm-cell-based pixels. In this paper, we develop analysis models for both thermal noise and flicker noise in Gm-cell-based pixels by employing the time-domain linear analysis approach and the non-stationary noise analysis theory, which help to quantitatively evaluate the temporal noise characteristic of Gm-cell-based pixels. Both models were numerically computed in MATLAB using design parameters of a prototype chip, and compared with both simulation and experimental results. The good agreement between the theoretical and measurement results verifies the effectiveness of the proposed noise analysis models.

Temporal Noise Analysis of Charge-Domain Sampling Readout Circuits for CMOS Image Sensors †

PubMed Central

Theuwissen, Albert J. P.

2018-01-01

This paper presents a temporal noise analysis of charge-domain sampling readout circuits for Complementary Metal-Oxide Semiconductor (CMOS) image sensors. In order to address the trade-off between the low input-referred noise and high dynamic range, a Gm-cell-based pixel together with a charge-domain correlated-double sampling (CDS) technique has been proposed to provide a way to efficiently embed a tunable conversion gain along the read-out path. Such readout topology, however, operates in a non-stationery large-signal behavior, and the statistical properties of its temporal noise are a function of time. Conventional noise analysis methods for CMOS image sensors are based on steady-state signal models, and therefore cannot be readily applied for Gm-cell-based pixels. In this paper, we develop analysis models for both thermal noise and flicker noise in Gm-cell-based pixels by employing the time-domain linear analysis approach and the non-stationary noise analysis theory, which help to quantitatively evaluate the temporal noise characteristic of Gm-cell-based pixels. Both models were numerically computed in MATLAB using design parameters of a prototype chip, and compared with both simulation and experimental results. The good agreement between the theoretical and measurement results verifies the effectiveness of the proposed noise analysis models. PMID:29495496

Process techniques of charge transfer time reduction for high speed CMOS image sensors

NASA Astrophysics Data System (ADS)

Zhongxiang, Cao; Quanliang, Li; Ye, Han; Qi, Qin; Peng, Feng; Liyuan, Liu; Nanjian, Wu

2014-11-01

This paper proposes pixel process techniques to reduce the charge transfer time in high speed CMOS image sensors. These techniques increase the lateral conductivity of the photo-generated carriers in a pinned photodiode (PPD) and the voltage difference between the PPD and the floating diffusion (FD) node by controlling and optimizing the N doping concentration in the PPD and the threshold voltage of the reset transistor, respectively. The techniques shorten the charge transfer time from the PPD diode to the FD node effectively. The proposed process techniques do not need extra masks and do not cause harm to the fill factor. A sub array of 32 × 64 pixels was designed and implemented in the 0.18 μm CIS process with five implantation conditions splitting the N region in the PPD. The simulation and measured results demonstrate that the charge transfer time can be decreased by using the proposed techniques. Comparing the charge transfer time of the pixel with the different implantation conditions of the N region, the charge transfer time of 0.32 μs is achieved and 31% of image lag was reduced by using the proposed process techniques.

A novel high-speed CMOS circuit based on a gang of capacitors

NASA Astrophysics Data System (ADS)

Sharroush, Sherif M.

2017-08-01

There is no doubt that complementary metal-oxide semiconductor (CMOS) circuits with wide fan-in suffers from the relatively sluggish operation. In this paper, a circuit that contains a gang of capacitors sharing their charge with each other is proposed as an alternative to long N-channel MOS and P-channel MOS stacks. The proposed scheme is investigated quantitatively and verified by simulation using the 45-nm CMOS technology with VDD = 1 V. The time delay, area and power consumption of the proposed scheme are investigated and compared with the conventional static CMOS logic circuit. It is verified that the proposed scheme achieves 52% saving in the average propagation delay for eight inputs and that it has a smaller area compared to the conventional CMOS logic when the number of inputs exceeds three and a smaller power consumption for a number of inputs exceeding two. The impacts of process variations, component mismatches and technology scaling on the proposed scheme are also investigated.

A power management system for energy harvesting and wireless sensor networks application based on a novel charge pump circuit

NASA Astrophysics Data System (ADS)

Aloulou, R.; De Peslouan, P.-O. Lucas; Mnif, H.; Alicalapa, F.; Luk, J. D. Lan Sun; Loulou, M.

2016-05-01

Energy Harvesting circuits are developed as an alternative solution to supply energy to autonomous sensor nodes in Wireless Sensor Networks. In this context, this paper presents a micro-power management system for multi energy sources based on a novel design of charge pump circuit to allow the total autonomy of self-powered sensors. This work proposes a low-voltage and high performance charge pump (CP) suitable for implementation in standard complementary metal oxide semiconductor (CMOS) technologies. The CP design was implemented using Cadence Virtuoso with AMS 0.35μm CMOS technology parameters. Its active area is 0.112 mm2. Consistent results were obtained between the measured findings of the chip testing and the simulation results. The circuit can operate with an 800 mV supply and generate a boosted output voltage of 2.835 V with 1 MHz as frequency.

SAMPA Chip: the New 32 Channels ASIC for the ALICE TPC and MCH Upgrades

NASA Astrophysics Data System (ADS)

Adolfsson, J.; Ayala Pabon, A.; Bregant, M.; Britton, C.; Brulin, G.; Carvalho, D.; Chambert, V.; Chinellato, D.; Espagnon, B.; Hernandez Herrera, H. D.; Ljubicic, T.; Mahmood, S. M.; Mjörnmark, U.; Moraes, D.; Munhoz, M. G.; Noël, G.; Oskarsson, A.; Osterman, L.; Pilyar, A.; Read, K.; Ruette, A.; Russo, P.; Sanches, B. C. S.; Severo, L.; Silvermyr, D.; Suire, C.; Tambave, G. J.; Tun-Lanoë, K. M. M.; van Noije, W.; Velure, A.; Vereschagin, S.; Wanlin, E.; Weber, T. O.; Zaporozhets, S.

2017-04-01

This paper presents the test results of the second prototype of SAMPA, the ASIC designed for the upgrade of read-out front end electronics of the ALICE Time Projection Chamber (TPC) and Muon Chamber (MCH). SAMPA is made in a 130 nm CMOS technology with 1.25 V nominal voltage supply and provides 32 channels, with selectable input polarity, and three possible combinations of shaping time and sensitivity. Each channel consists of a Charge Sensitive Amplifier, a semi-Gaussian shaper and a 10-bit ADC; a Digital Signal Processor provides digital filtering and compression capability. In the second prototype run both full chip and single test blocks were fabricated, allowing block characterization and full system behaviour studies. Experimental results are here presented showing agreement with requirements for both the blocks and the full chip.

Investigation of HV/HR-CMOS technology for the ATLAS Phase-II Strip Tracker Upgrade

NASA Astrophysics Data System (ADS)

Fadeyev, V.; Galloway, Z.; Grabas, H.; Grillo, A. A.; Liang, Z.; Martinez-Mckinney, F.; Seiden, A.; Volk, J.; Affolder, A.; Buckland, M.; Meng, L.; Arndt, K.; Bortoletto, D.; Huffman, T.; John, J.; McMahon, S.; Nickerson, R.; Phillips, P.; Plackett, R.; Shipsey, I.; Vigani, L.; Bates, R.; Blue, A.; Buttar, C.; Kanisauskas, K.; Maneuski, D.; Benoit, M.; Di Bello, F.; Caragiulo, P.; Dragone, A.; Grenier, P.; Kenney, C.; Rubbo, F.; Segal, J.; Su, D.; Tamma, C.; Das, D.; Dopke, J.; Turchetta, R.; Wilson, F.; Worm, S.; Ehrler, F.; Peric, I.; Gregor, I. M.; Stanitzki, M.; Hoeferkamp, M.; Seidel, S.; Hommels, L. B. A.; Kramberger, G.; Mandić, I.; Mikuž, M.; Muenstermann, D.; Wang, R.; Zhang, J.; Warren, M.; Song, W.; Xiu, Q.; Zhu, H.

2016-09-01

ATLAS has formed strip CMOS project to study the use of CMOS MAPS devices as silicon strip sensors for the Phase-II Strip Tracker Upgrade. This choice of sensors promises several advantages over the conventional baseline design, such as better resolution, less material in the tracking volume, and faster construction speed. At the same time, many design features of the sensors are driven by the requirement of minimizing the impact on the rest of the detector. Hence the target devices feature long pixels which are grouped to form a virtual strip with binary-encoded z position. The key performance aspects are radiation hardness compatibility with HL-LHC environment, as well as extraction of the full hit position with full-reticle readout architecture. To date, several test chips have been submitted using two different CMOS technologies. The AMS 350 nm is a high voltage CMOS process (HV-CMOS), that features the sensor bias of up to 120 V. The TowerJazz 180 nm high resistivity CMOS process (HR-CMOS) uses a high resistivity epitaxial layer to provide the depletion region on top of the substrate. We have evaluated passive pixel performance, and charge collection projections. The results strongly support the radiation tolerance of these devices to radiation dose of the HL-LHC in the strip tracker region. We also describe design features for the next chip submission that are motivated by our technology evaluation.

Quantitative optical metrology with CMOS cameras

NASA Astrophysics Data System (ADS)

Furlong, Cosme; Kolenovic, Ervin; Ferguson, Curtis F.

2004-08-01

Recent advances in laser technology, optical sensing, and computer processing of data, have lead to the development of advanced quantitative optical metrology techniques for high accuracy measurements of absolute shapes and deformations of objects. These techniques provide noninvasive, remote, and full field of view information about the objects of interest. The information obtained relates to changes in shape and/or size of the objects, characterizes anomalies, and provides tools to enhance fabrication processes. Factors that influence selection and applicability of an optical technique include the required sensitivity, accuracy, and precision that are necessary for a particular application. In this paper, sensitivity, accuracy, and precision characteristics in quantitative optical metrology techniques, and specifically in optoelectronic holography (OEH) based on CMOS cameras, are discussed. Sensitivity, accuracy, and precision are investigated with the aid of National Institute of Standards and Technology (NIST) traceable gauges, demonstrating the applicability of CMOS cameras in quantitative optical metrology techniques. It is shown that the advanced nature of CMOS technology can be applied to challenging engineering applications, including the study of rapidly evolving phenomena occurring in MEMS and micromechatronics.

Characterization of the Photon Counting CHASE Jr., Chip Built in a 40-nm CMOS Process With a Charge Sharing Correction Algorithm Using a Collimated X-Ray Beam

DOE Office of Scientific and Technical Information (OSTI.GOV)

Krzyżanowska, A.; Deptuch, G. W.; Maj, P.

This paper presents the detailed characterization of a single photon counting chip, named CHASE Jr., built in a CMOS 40-nm process, operating with synchrotron radiation. The chip utilizes an on-chip implementation of the C8P1 algorithm. The algorithm eliminates the charge sharing related uncertainties, namely, the dependence of the number of registered photons on the discriminator’s threshold, set for monochromatic irradiation, and errors in the assignment of an event to a certain pixel. The article presents a short description of the algorithm as well as the architecture of the CHASE Jr., chip. The analog and digital functionalities, allowing for proper operationmore » of the C8P1 algorithm are described, namely, an offset correction for two discriminators independently, two-stage gain correction, and different operation modes of the digital blocks. The results of tests of the C8P1 operation are presented for the chip bump bonded to a silicon sensor and exposed to the 3.5- μm -wide pencil beam of 8-keV photons of synchrotron radiation. It was studied how sensitive the algorithm performance is to the chip settings, as well as the uniformity of parameters of the analog front-end blocks. Presented results prove that the C8P1 algorithm enables counting all photons hitting the detector in between readout channels and retrieving the actual photon energy.« less

CMOS-MEMS Chemiresistive and Chemicapacitive Chemical Sensor System

NASA Astrophysics Data System (ADS)

Lazarus, Nathan S.

Integrating chemical sensors with testing electronics is a powerful technique with the potential to lower power and cost and allow for lower system limits of detection. This thesis explores the possibility of creating an integrated sensor system intended to be embedded within respirator cartridges to notify the user that hazardous chemicals will soon leak into the face mask. For a chemical sensor designer, this application is particularly challenging due to the need for a very sensitive and cheap sensor that will be exposed to widely varying environmental conditions during use. An octanethiol-coated gold nanoparticle chemiresistor to detect industrial solvents is developed, focusing on characterizing the environmental stability and limits of detection of the sensor. Since the chemiresistor was found to be highly sensitive to water vapor, a series of highly sensitive humidity sensor topologies were developed, with sensitivities several times previous integrated capacitive humidity sensors achieved. Circuit techniques were then explored to reduce the humidity sensor limits of detection, including the analysis of noise, charge injection, jitter and clock feedthrough in a charge-based capacitance measurement (CBCM) circuit and the design of a low noise Colpitts LC oscillator. The characterization of high resistance gold nanoclusters for capacitive chemical sensing was also performed. In the final section, a preconcentrator, a heater element intended to release a brief concentrated pulse of analate, was developed and tested for the purposes of lowering the system limit of detection.

Optimization of CMOS image sensor utilizing variable temporal multisampling partial transfer technique to achieve full-frame high dynamic range with superior low light and stop motion capability

NASA Astrophysics Data System (ADS)

Kabir, Salman; Smith, Craig; Armstrong, Frank; Barnard, Gerrit; Schneider, Alex; Guidash, Michael; Vogelsang, Thomas; Endsley, Jay

2018-03-01

Differential binary pixel technology is a threshold-based timing, readout, and image reconstruction method that utilizes the subframe partial charge transfer technique in a standard four-transistor (4T) pixel CMOS image sensor to achieve a high dynamic range video with stop motion. This technology improves low light signal-to-noise ratio (SNR) by up to 21 dB. The method is verified in silicon using a Taiwan Semiconductor Manufacturing Company's 65 nm 1.1 μm pixel technology 1 megapixel test chip array and is compared with a traditional 4 × oversampling technique using full charge transfer to show low light SNR superiority of the presented technology.

Single-photon sensitive fast ebCMOS camera system for multiple-target tracking of single fluorophores: application to nano-biophotonics

NASA Astrophysics Data System (ADS)

Cajgfinger, Thomas; Chabanat, Eric; Dominjon, Agnes; Doan, Quang T.; Guerin, Cyrille; Houles, Julien; Barbier, Remi

2011-03-01

Nano-biophotonics applications will benefit from new fluorescent microscopy methods based essentially on super-resolution techniques (beyond the diffraction limit) on large biological structures (membranes) with fast frame rate (1000 Hz). This trend tends to push the photon detectors to the single-photon counting regime and the camera acquisition system to real time dynamic multiple-target tracing. The LUSIPHER prototype presented in this paper aims to give a different approach than those of Electron Multiplied CCD (EMCCD) technology and try to answer to the stringent demands of the new nano-biophotonics imaging techniques. The electron bombarded CMOS (ebCMOS) device has the potential to respond to this challenge, thanks to the linear gain of the accelerating high voltage of the photo-cathode, to the possible ultra fast frame rate of CMOS sensors and to the single-photon sensitivity. We produced a camera system based on a 640 kPixels ebCMOS with its acquisition system. The proof of concept for single-photon based tracking for multiple single-emitters is the main result of this paper.

Beyond detection: nuclear physics with a webcam in an educational setting

NASA Astrophysics Data System (ADS)

Pallone, Arthur

2015-03-01

Nuclear physics affects our daily lives in such diverse fields from medicine to art. I believe three obstacles - limited time, lack of subject familiarity and thus comfort on the part of educators, and equipment expense - must be overcome to produce a nuclear-educated populace. Educators regularly use webcams to actively engage students in scientific discovery as evidenced by a literature search for the term webcam paired with topics such as astronomy, biology, and physics. Inspired by YouTube videos that demonstrate alpha particle detection by modified webcams, I searched for examples that go beyond simple detection with only one education-oriented result - the determination of the in-air range of alphas using a modified CCD camera. Custom-built, radiation-hardened CMOS detectors exist in high energy physics and for soft x-ray detection. Commercial CMOS cameras are used for direct imaging in electron microscopy. I demonstrate charged-particle spectrometry with a slightly modified CMOS-based webcam. When used with inexpensive sources of radiation and free software, the webcam charged-particle spectrometer presents educators with a simple, low-cost technique to include nuclear physics in science education.

Resistive switching phenomena of tungsten nitride thin films with excellent CMOS compatibility

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hong, Seok Man; Kim, Hee-Dong; An, Ho-Myoung

2013-12-15

Graphical abstract: - Highlights: • The resistive switching characteristics of WN{sub x} thin films. • Excellent CMOS compatibility WN{sub x} films as a resistive switching material. • Resistive switching mechanism revealed trap-controlled space charge limited conduction. • Good endurance and retention properties over 10{sup 5} cycles, and 10{sup 5} s, respectively - Abstract: We report the resistive switching (RS) characteristics of tungsten nitride (WN{sub x}) thin films with excellent complementary metal-oxide-semiconductor (CMOS) compatibility. A Ti/WN{sub x}/Pt memory cell clearly shows bipolar RS behaviors at a low voltage of approximately ±2.2 V. The dominant conduction mechanisms at low and high resistancemore » states were verified by Ohmic behavior and trap-controlled space-charge-limited conduction, respectively. A conducting filament model by a redox reaction explains the RS behavior in WN{sub x} films. We also demonstrate the memory characteristics during pulse operation, including a high endurance over >10{sup 5} cycles and a long retention time of >10{sup 5} s.« less

Respiration detection chip with integrated temperature-insensitive MEMS sensors and CMOS signal processing circuits.

PubMed

Wei, Chia-Ling; Lin, Yu-Chen; Chen, Tse-An; Lin, Ren-Yi; Liu, Tin-Hao

2015-02-01

An airflow sensing chip, which integrates MEMS sensors with their CMOS signal processing circuits into a single chip, is proposed for respiration detection. Three micro-cantilever-based airflow sensors were designed and fabricated using a 0.35 μm CMOS/MEMS 2P4M mixed-signal polycide process. Two main differences were present among these three designs: they were either metal-covered or metal-free structures, and had either bridge-type or fixed-type reference resistors. The performances of these sensors were measured and compared, including temperature sensitivity and airflow sensitivity. Based on the measured results, the metal-free structure with fixed-type reference resistors is recommended for use, because it has the highest airflow sensitivity and also can effectively reduce the output voltage drift caused by temperature change.

A 0.13µm CMOS Bluetooth EDR Transceiver with High Sensitivity over Wide Temperature Range and Immunity to Process Variation

NASA Astrophysics Data System (ADS)

Agawa, Kenichi; Ishizuka, Shinichiro; Majima, Hideaki; Kobayashi, Hiroyuki; Koizumi, Masayuki; Nagano, Takeshi; Arai, Makoto; Shimizu, Yutaka; Maki, Asuka; Urakawa, Go; Terada, Tadashi; Itoh, Nobuyuki; Hamada, Mototsugu; Fujii, Fumie; Kato, Tadamasa; Yoshitomi, Sadayuki; Otsuka, Nobuaki

A 2.4GHz 0.13µm CMOS transceiver LSI, supporting Bluetooth V2.1 + enhanced data rate (EDR) standard, has achieved a high reception sensitivity and high-quality transmission signals between -40°C and +90°C. A low-IF receiver and direct-conversion transmitter architecture are employed. A temperature compensated receiver chain including a low-noise amplifier accomplishes a sensitivity of -90dBm at frequency shift keying modulation even in the worst environmental condition. Design optimization of phase noise in a local oscillator and linearity of a power amplifier improves transmission signals and enables them to meet Bluetooth radio specifications. Fabrication in scaled 0.13µm CMOS and operation at a low supply voltage of 1.5V result in small area and low power consumption.

Characteristics of Various Photodiode Structures in CMOS Technology with Monolithic Signal Processing Electronics

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mukhopadhyay, Sourav; Chandratre, V. B.; Sukhwani, Menka

2011-10-20

Monolithic optical sensor with readout electronics are needed in optical communication, medical imaging and scintillator based gamma spectroscopy system. This paper presents the design of three different CMOS photodiode test structures and two readout channels in a commercial CMOS technology catering to the need of nuclear instrumentation. The three photodiode structures each of 1 mm{sup 2} with readout electronics are fabricated in 0.35 um, 4 metal, double poly, N-well CMOS process. These photodiode structures are based on available P-N junction of standard CMOS process i.e. N-well/P-substrate, P+/N-well/P-substrate and inter-digitized P+/N-well/P-substrate. The comparisons of typical characteristics among three fabricated photo sensorsmore » are reported in terms of spectral sensitivity, dark current and junction capacitance. Among the three photodiode structures N-well/P-substrate photodiode shows higher spectral sensitivity compared to the other two photodiode structures. The inter-digitized P+/N-well/P-substrate structure has enhanced blue response compared to N-well/P-substrate and P+/N-well/P-substrate photodiode. Design and test results of monolithic readout electronics, for three different CMOS photodiode structures for application related to nuclear instrumentation, are also reported.« less

Label-free CMOS bio sensor with on-chip noise reduction scheme for real-time quantitative monitoring of biomolecules.

PubMed

Seong-Jin Kim; Euisik Yoon

2012-06-01

We present a label-free CMOS field-effect transistor sensing array to detect the surface potential change affected by the negative charge in DNA molecules for real-time monitoring and quantification. The proposed CMOS bio sensor includes a new sensing pixel architecture implemented with correlated double sampling for reducing offset fixed pattern noise and 1/f noise of the sensing devices. We incorporated non-surface binding detection which allows real-time continuous monitoring of DNA concentrations without immobilizing them on the sensing surface. Various concentrations of 19-bp oligonucleotides solution can be discriminated using the prototype device fabricated in 1- μm double-poly double-metal standard CMOS process. The detection limit was measured as 1.1 ng/μl with a dynamic range of 40 dB and the transient response time was measured less than 20 seconds.

A fast, low power and low noise charge sensitive amplifier ASIC for a UV imaging single photon detector

NASA Astrophysics Data System (ADS)

Seljak, A.; Cumming, H. S.; Varner, G.; Vallerga, J.; Raffanti, R.; Virta, V.

2017-04-01

NASA has funded, through their Strategic Astrophysics Technology (SAT) program, the development of a cross strip (XS) microchannel plate (MCP) detector with the intention to increase its technology readiness level (TRL), enabling prototyping for future NASA missions. One aspect of the development is to convert the large and high powered laboratory Parallel Cross Strip (PXS) readout electronics into application specific integrated circuits (ASICs) to decrease their mass, volume, and power consumption (all limited resources in space) and to make them more robust to the environments of rocket launch and space. The redesign also foresees to increase the overall readout event rate, and decrease the noise contribution of the readout system. This work presents the design and verification of the first stage for the new readout system, the 16 channel charge sensitive amplifier ASIC, called the CSAv3. The single channel amplifier is composed of a charge sensitive amplifier (pre-amplifier), a pole zero cancellation circuit and a shaping amplifier. An additional output stage buffer allows polarity selection of the output analog signal. The operation of the amplifier is programmable via serial bus. It provides an equivalent noise charge (ENC) of around 600 e^- and a baseline gain of 10 mV/fC. The full scale pulse shaped output signal is confined within 100 ns, without long recovery tails, enabling up to 10 MHz periodic event rates without signal pile up. This ASIC was designed and fabricated in 130 nm, TSMC CMOS 1.2 V technology. In addition, we briefly discuss the construction of the readout system and plans for the future work.

Broadband image sensor array based on graphene-CMOS integration

NASA Astrophysics Data System (ADS)

Goossens, Stijn; Navickaite, Gabriele; Monasterio, Carles; Gupta, Shuchi; Piqueras, Juan José; Pérez, Raúl; Burwell, Gregory; Nikitskiy, Ivan; Lasanta, Tania; Galán, Teresa; Puma, Eric; Centeno, Alba; Pesquera, Amaia; Zurutuza, Amaia; Konstantatos, Gerasimos; Koppens, Frank

2017-06-01

Integrated circuits based on complementary metal-oxide-semiconductors (CMOS) are at the heart of the technological revolution of the past 40 years, enabling compact and low-cost microelectronic circuits and imaging systems. However, the diversification of this platform into applications other than microcircuits and visible-light cameras has been impeded by the difficulty to combine semiconductors other than silicon with CMOS. Here, we report the monolithic integration of a CMOS integrated circuit with graphene, operating as a high-mobility phototransistor. We demonstrate a high-resolution, broadband image sensor and operate it as a digital camera that is sensitive to ultraviolet, visible and infrared light (300-2,000 nm). The demonstrated graphene-CMOS integration is pivotal for incorporating 2D materials into the next-generation microelectronics, sensor arrays, low-power integrated photonics and CMOS imaging systems covering visible, infrared and terahertz frequencies.

CMOS Imager Has Better Cross-Talk and Full-Well Performance

NASA Technical Reports Server (NTRS)

Pain, Bedabrata; Cunningham, Thomas J.

2011-01-01

A complementary metal oxide/semiconductor (CMOS) image detector now undergoing development is designed to exhibit less cross-talk and greater full-well capacity than do prior CMOS image detectors of the same type. Imagers of the type in question are designed to operate from low-voltage power supplies and are fabricated by processes that yield device features having dimensions in the deep submicron range. Because of the use of low supply potentials, maximum internal electric fields and depletion widths are correspondingly limited. In turn, these limitations are responsible for increases in cross-talk and decreases in charge-handling capacities. Moreover, for small pixels, lateral depletion cannot be extended. These adverse effects are even more accentuated in a back-illuminated CMOS imager, in which photogenerated charge carriers must travel across the entire thickness of the device. The figure shows a partial cross section of the structure in the device layer of the present developmental CMOS imager. (In a practical imager, the device layer would sit atop either a heavily doped silicon substrate or a thin silicon oxide layer on a silicon substrate, not shown here.) The imager chip is divided into two areas: area C, which contains readout circuits and other electronic circuits; and area I, which contains the imaging (photodetector and photogenerated-charge-collecting) pixel structures. Areas C and I are electrically isolated from each other by means of a trench filled with silicon oxide. The electrical isolation between areas C and I makes it possible to apply different supply potentials to these areas, thereby enabling optimization of the supply potential and associated design features for each area. More specifically, metal oxide semiconductor field-effect transistors (MOSFETs) that are typically included in CMOS imagers now reside in area C and can remain unchanged from established designs and operated at supply potentials prescribed for those designs, while the dopings and the lower supply potentials in area I can be tailored to optimize imager performance. In area I, the device layer includes an n+ -doped silicon layer on which is grown an n-doped silicon layer. A p-doped silicon layer is grown on top of the n -doped layer. The total imaging device thickness is the sum of the thickness of the n+, n, and p layers. A pixel photodiode is formed between a surface n+ implant, a p implant underneath it, the aforementioned p layer, and the n and n+ layers. Adjacent to the diode is a gate for transferring photogenerated charges out of the photodiode and into a floating diffusion formed by an implanted p+ layer on an implanted n-doped region. Metal contact pads are added to the back-side for providing back-side bias.

Image sensor pixel with on-chip high extinction ratio polarizer based on 65-nm standard CMOS technology.

PubMed

Sasagawa, Kiyotaka; Shishido, Sanshiro; Ando, Keisuke; Matsuoka, Hitoshi; Noda, Toshihiko; Tokuda, Takashi; Kakiuchi, Kiyomi; Ohta, Jun

2013-05-06

In this study, we demonstrate a polarization sensitive pixel for a complementary metal-oxide-semiconductor (CMOS) image sensor based on 65-nm standard CMOS technology. Using such a deep-submicron CMOS technology, it is possible to design fine metal patterns smaller than the wavelengths of visible light by using a metal wire layer. We designed and fabricated a metal wire grid polarizer on a 20 × 20 μm(2) pixel for image sensor. An extinction ratio of 19.7 dB was observed at a wavelength 750 nm.

CMOS Time-Resolved, Contact, and Multispectral Fluorescence Imaging for DNA Molecular Diagnostics

PubMed Central

Guo, Nan; Cheung, Ka Wai; Wong, Hiu Tung; Ho, Derek

2014-01-01

Instrumental limitations such as bulkiness and high cost prevent the fluorescence technique from becoming ubiquitous for point-of-care deoxyribonucleic acid (DNA) detection and other in-field molecular diagnostics applications. The complimentary metal-oxide-semiconductor (CMOS) technology, as benefited from process scaling, provides several advanced capabilities such as high integration density, high-resolution signal processing, and low power consumption, enabling sensitive, integrated, and low-cost fluorescence analytical platforms. In this paper, CMOS time-resolved, contact, and multispectral imaging are reviewed. Recently reported CMOS fluorescence analysis microsystem prototypes are surveyed to highlight the present state of the art. PMID:25365460

Charged particle detection performances of CMOS pixel sensors produced in a 0.18 μm process with a high resistivity epitaxial layer

NASA Astrophysics Data System (ADS)

Senyukov, S.; Baudot, J.; Besson, A.; Claus, G.; Cousin, L.; Dorokhov, A.; Dulinski, W.; Goffe, M.; Hu-Guo, C.; Winter, M.

2013-12-01

The apparatus of the ALICE experiment at CERN will be upgraded in 2017/18 during the second long shutdown of the LHC (LS2). A major motivation for this upgrade is to extend the physics reach for charmed and beauty particles down to low transverse momenta. This requires a substantial improvement of the spatial resolution and the data rate capability of the ALICE Inner Tracking System (ITS). To achieve this goal, the new ITS will be equipped with 50 μm thin CMOS Pixel Sensors (CPS) covering either the three innermost layers or all the 7 layers of the detector. The CPS being developed for the ITS upgrade at IPHC (Strasbourg) is derived from the MIMOSA 28 sensor realised for the STAR-PXL at RHIC in a 0.35 μm CMOS process. In order to satisfy the ITS upgrade requirements in terms of readout speed and radiation tolerance, a CMOS process with a reduced feature size and a high resistivity epitaxial layer should be exploited. In this respect, the charged particle detection performance and radiation hardness of the TowerJazz 0.18 μm CMOS process were studied with the help of the first prototype chip MIMOSA 32. The beam tests performed with negative pions of 120 GeV/c at the CERN-SPS allowed to measure a signal-to-noise ratio (SNR) for the non-irradiated chip in the range between 22 and 32 depending on the pixel design. The chip irradiated with the combined dose of 1 MRad and 1013neq /cm2 was observed to yield an SNR ranging between 11 and 23 for coolant temperatures varying from 15 °C to 30 °C. These SNR values were measured to result in particle detection efficiencies above 99.5% and 98% before and after irradiation, respectively. These satisfactory results allow to validate the TowerJazz 0.18 μm CMOS process for the ALICE ITS upgrade.

CMOS Amperometric ADC With High Sensitivity, Dynamic Range and Power Efficiency for Air Quality Monitoring.

PubMed

Li, Haitao; Boling, C Sam; Mason, Andrew J

2016-08-01

Airborne pollutants are a leading cause of illness and mortality globally. Electrochemical gas sensors show great promise for personal air quality monitoring to address this worldwide health crisis. However, implementing miniaturized arrays of such sensors demands high performance instrumentation circuits that simultaneously meet challenging power, area, sensitivity, noise and dynamic range goals. This paper presents a new multi-channel CMOS amperometric ADC featuring pixel-level architecture for gas sensor arrays. The circuit combines digital modulation of input currents and an incremental Σ∆ ADC to achieve wide dynamic range and high sensitivity with very high power efficiency and compact size. Fabricated in 0.5 [Formula: see text] CMOS, the circuit was measured to have 164 dB cross-scale dynamic range, 100 fA sensitivity while consuming only 241 [Formula: see text] and 0.157 [Formula: see text] active area per channel. Electrochemical experiments with liquid and gas targets demonstrate the circuit's real-time response to a wide range of analyte concentrations.

Switching Oxide Traps

NASA Technical Reports Server (NTRS)

Oldham, Timothy R.

2003-01-01

We consider radiation-induced charge trapping in SiO2 dielectric layers, primarily from the point of view of CMOS devices. However, SiO2 insulators are used in many other ways, and the same defects occur in other contexts. The key studies, which determined the nature of the oxide charge traps, were done primarily on gate oxides in CMOS devices, because that was the main radiation problem in CMOS at one time. There are two major reviews of radiation-induced oxide charge trapping already in the literature, which discuss the subject in far greater detail than is possible here. The first of these was by McLean et al. in 1989, and the second, ten years later, was intended as an update, because of additional, new work that had been reported. Basically, the picture that has emerged is that ionizing radiation creates electron-hole pairs in the oxide, and the electrons have much higher mobility than the holes. Therefore, the electrons are swept out of the oxide very rapidly by any field that is present, leaving behind any holes that escape the initial recombination process. These holes then undergo a polaron hopping transport toward the Si/SiO2 interface (under positive bias). Near the interface, some fraction of them fall into deep, relatively stable, long-lived hole traps. The nature and annealing behavior of these hole traps is the main focus of this paper.

A Real-Time Ultraviolet Radiation Imaging System Using an Organic Photoconductive Image Sensor†

PubMed Central

Okino, Toru; Yamahira, Seiji; Yamada, Shota; Hirose, Yutaka; Odagawa, Akihiro; Kato, Yoshihisa; Tanaka, Tsuyoshi

2018-01-01

We have developed a real time ultraviolet (UV) imaging system that can visualize both invisible UV light and a visible (VIS) background scene in an outdoor environment. As a UV/VIS image sensor, an organic photoconductive film (OPF) imager is employed. The OPF has an intrinsically higher sensitivity in the UV wavelength region than those of conventional consumer Complementary Metal Oxide Semiconductor (CMOS) image sensors (CIS) or Charge Coupled Devices (CCD). As particular examples, imaging of hydrogen flame and of corona discharge is demonstrated. UV images overlapped on background scenes are simply made by on-board background subtraction. The system is capable of imaging weaker UV signals by four orders of magnitude than that of VIS background. It is applicable not only to future hydrogen supply stations but also to other UV/VIS monitor systems requiring UV sensitivity under strong visible radiation environment such as power supply substations. PMID:29361742

Ultrananocrystalline diamond films with optimized dielectric properties for advanced RF MEMS capacitive switches

DOEpatents

Sumant, Anirudha V.; Auciello, Orlando H.; Mancini, Derrick C.

2013-01-15

An efficient deposition process is provided for fabricating reliable RF MEMS capacitive switches with multilayer ultrananocrystalline (UNCD) films for more rapid recovery, charging and discharging that is effective for more than a billion cycles of operation. Significantly, the deposition process is compatible for integration with CMOS electronics and thereby can provide monolithically integrated RF MEMS capacitive switches for use with CMOS electronic devices, such as for insertion into phase array antennas for radars and other RF communication systems.

Optical design of microlens array for CMOS image sensors

NASA Astrophysics Data System (ADS)

Zhang, Rongzhu; Lai, Liping

2016-10-01

The optical crosstalk between the pixel units can influence the image quality of CMOS image sensor. In the meantime, the duty ratio of CMOS is low because of its pixel structure. These two factors cause the low detection sensitivity of CMOS. In order to reduce the optical crosstalk and improve the fill factor of CMOS image sensor, a microlens array has been designed and integrated with CMOS. The initial parameters of the microlens array have been calculated according to the structure of a CMOS. Then the parameters have been optimized by using ZEMAX and the microlens arrays with different substrate thicknesses have been compared. The results show that in order to obtain the best imaging quality, when the effect of optical crosstalk for CMOS is the minimum, the best distance between microlens array and CMOS is about 19.3 μm. When incident light successively passes through microlens array and the distance, obtaining the minimum facula is around 0.347 um in the active area. In addition, when the incident angle of the light is 0o 22o, the microlens array has obvious inhibitory effect on the optical crosstalk. And the anti-crosstalk distance between microlens array and CMOS is 0 μm 162 μm.

Non-Linearity in Wide Dynamic Range CMOS Image Sensors Utilizing a Partial Charge Transfer Technique.

PubMed

Shafie, Suhaidi; Kawahito, Shoji; Halin, Izhal Abdul; Hasan, Wan Zuha Wan

2009-01-01

The partial charge transfer technique can expand the dynamic range of a CMOS image sensor by synthesizing two types of signal, namely the long and short accumulation time signals. However the short accumulation time signal obtained from partial transfer operation suffers of non-linearity with respect to the incident light. In this paper, an analysis of the non-linearity in partial charge transfer technique has been carried, and the relationship between dynamic range and the non-linearity is studied. The results show that the non-linearity is caused by two factors, namely the current diffusion, which has an exponential relation with the potential barrier, and the initial condition of photodiodes in which it shows that the error in the high illumination region increases as the ratio of the long to the short accumulation time raises. Moreover, the increment of the saturation level of photodiodes also increases the error in the high illumination region.

Monolithic integration of GMR sensors for standard CMOS-IC current sensing

NASA Astrophysics Data System (ADS)

De Marcellis, A.; Reig, C.; Cubells-Beltrán, M.-D.; Madrenas, J.; Santos, J. D.; Cardoso, S.; Freitas, P. P.

2017-09-01

In this work we report on the development of Giant Magnetoresistive (GMR) sensors for off-line current measurements in standard integrated circuits. An ASIC has been specifically designed and fabricated in the well-known AMS-0.35 μm CMOS technology, including the electronic circuitry for sensor interfacing. It implements an oscillating circuit performing a voltage-to-frequency conversion. Subsequently, a fully CMOS-compatible low temperature post-process has been applied for depositing the GMR sensing devices in a full-bridge configuration onto the buried current straps. Sensitivity and resolution of these sensors have been investigated achieving experimental results that show a detection sensitivity of about 100 Hz/mA, with a resolution of about 5 μA.

Full-wafer fabrication by nanostencil lithography of micro/nanomechanical mass sensors monolithically integrated with CMOS.

PubMed

Arcamone, J; van den Boogaart, M A F; Serra-Graells, F; Fraxedas, J; Brugger, J; Pérez-Murano, F

2008-07-30

Wafer-scale nanostencil lithography (nSL) is used to define several types of silicon mechanical resonators, whose dimensions range from 20 µm down to 200 nm, monolithically integrated with CMOS circuits. We demonstrate the simultaneous patterning by nSL of ∼2000 nanodevices per wafer by post-processing standard CMOS substrates using one single metal evaporation, pattern transfer to silicon and subsequent etch of the sacrificial layer. Resonance frequencies in the MHz range were measured in air and vacuum. As proof-of-concept towards an application as high performance sensors, CMOS integrated nano/micromechanical resonators are successfully implemented as ultra-sensitive areal mass sensors. These devices demonstrate the ability to monitor the deposition of gold layers whose average thickness is smaller than a monolayer. Their areal mass sensitivity is in the range of 10(-11) g cm(-2) Hz(-1), and their thickness resolution corresponds to approximately a thousandth of a monolayer.

CMOS direct time interval measurement of long-lived luminescence lifetimes.

PubMed

Yao, Lei; Yung, Ka Yi; Cheung, Maurice C; Chodavarapu, Vamsy P; Bright, Frank V

2011-01-01

We describe a Complementary Metal-Oxide Semiconductor (CMOS) Direct Time Interval Measurement (DTIM) Integrated Circuit (IC) to detect the decay (fall) time of the luminescence emission when analyte-sensitive luminophores are excited with an optical pulse. The CMOS DTIM IC includes 14 × 14 phototransistor array, transimpedance amplifier, regulated gain amplifier, fall time detector, and time-to-digital convertor. We examined the DTIM system to measure the emission lifetime of oxygen-sensitive luminophores tris(4,7-diphenyl-1, 10-phenanthroline) ruthenium(II) ([Ru(dpp)(3)](2+)) encapsulated in sol-gel derived xerogel thin-films. The DTIM system fabricated using TSMC 0.35 μm process functions to detect lifetimes from 4 μs to 14.4 μs but can be tuned to detect longer lifetimes. The system provides 8-bit digital output proportional to lifetimes and consumes 4.5 mW of power with 3.3 V DC supply. The CMOS system provides a useful platform for the development of reliable, robust, and miniaturized optical chemical sensors.

CMOS Imaging of Temperature Effects on Pin-Printed Xerogel Sensor Microarrays.

PubMed

Lei Yao; Ka Yi Yung; Chodavarapu, Vamsy P; Bright, Frank V

2011-04-01

In this paper, we study the effect of temperature on the operation and performance of a xerogel-based sensor microarrays coupled to a complementary metal-oxide semiconductor (CMOS) imager integrated circuit (IC) that images the photoluminescence response from the sensor microarray. The CMOS imager uses a 32 × 32 (1024 elements) array of active pixel sensors and each pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. A correlated double sampling circuit and pixel address/digital control/signal integration circuit are also implemented on-chip. The CMOS imager data are read out as a serial coded signal. The sensor system uses a light-emitting diode to excite target analyte responsive organometallic luminophores doped within discrete xerogel-based sensor elements. As a proto type, we developed a 3 × 3 (9 elements) array of oxygen (O2) sensors. Each group of three sensor elements in the array (arranged in a column) is designed to provide a different and specific sensitivity to the target gaseous O2 concentration. This property of multiple sensitivities is achieved by using a mix of two O2 sensitive luminophores in each pin-printed xerogel sensor element. The CMOS imager is designed to be low noise and consumes a static power of 320.4 μW and an average dynamic power of 624.6 μW when operating at 100-Hz sampling frequency and 1.8-V dc power supply.

A Wireless Fiber Photometry System Based on a High-Precision CMOS Biosensor With Embedded Continuous-Time Modulation.

PubMed

Khiarak, Mehdi Noormohammadi; Martianova, Ekaterina; Bories, Cyril; Martel, Sylvain; Proulx, Christophe D; De Koninck, Yves; Gosselin, Benoit

2018-06-01

Fluorescence biophotometry measurements require wide dynamic range (DR) and high-sensitivity laboratory apparatus. Indeed, it is often very challenging to accurately resolve the small fluorescence variations in presence of noise and high-background tissue autofluorescence. There is a great need for smaller detectors combining high linearity, high sensitivity, and high-energy efficiency. This paper presents a new biophotometry sensor merging two individual building blocks, namely a low-noise sensing front-end and a order continuous-time modulator (CTSDM), into a single module for enabling high-sensitivity and high energy-efficiency photo-sensing. In particular, a differential CMOS photodetector associated with a differential capacitive transimpedance amplifier-based sensing front-end is merged with an incremental order 1-bit CTSDM to achieve a large DR, low hardware complexity, and high-energy efficiency. The sensor leverages a hardware sharing strategy to simplify the implementation and reduce power consumption. The proposed CMOS biosensor is integrated within a miniature wireless head mountable prototype for enabling biophotometry with a single implantable fiber in the brain of live mice. The proposed biophotometry sensor is implemented in a 0.18- CMOS technology, consuming from a 1.8- supply voltage, while achieving a peak dynamic range of over a 50- input bandwidth, a sensitivity of 24 mV/nW, and a minimum detectable current of 2.46- at a 20- sampling rate.

Label free sensing of creatinine using a 6 GHz CMOS near-field dielectric immunosensor.

PubMed

Guha, S; Warsinke, A; Tientcheu, Ch M; Schmalz, K; Meliani, C; Wenger, Ch

2015-05-07

In this work we present a CMOS high frequency direct immunosensor operating at 6 GHz (C-band) for label free determination of creatinine. The sensor is fabricated in standard 0.13 μm SiGe:C BiCMOS process. The report also demonstrates the ability to immobilize creatinine molecules on a Si3N4 passivation layer of the standard BiCMOS/CMOS process, therefore, evading any further need of cumbersome post processing of the fabricated sensor chip. The sensor is based on capacitive detection of the amount of non-creatinine bound antibodies binding to an immobilized creatinine layer on the passivated sensor. The chip bound antibody amount in turn corresponds indirectly to the creatinine concentration used in the incubation phase. The determination of creatinine in the concentration range of 0.88-880 μM is successfully demonstrated in this work. A sensitivity of 35 MHz/10 fold increase in creatinine concentration (during incubation) at the centre frequency of 6 GHz is gained by the immunosensor. The results are compared with a standard optical measurement technique and the dynamic range and sensitivity is of the order of the established optical indication technique. The C-band immunosensor chip comprising an area of 0.3 mm(2) reduces the sensing area considerably, therefore, requiring a sample volume as low as 2 μl. The small analyte sample volume and label free approach also reduce the experimental costs in addition to the low fabrication costs offered by the batch fabrication technique of CMOS/BiCMOS process.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Trippe, J. M.; Reed, R. A.; Austin, R. A.

In this study, we present experimental evidence of single electron-induced upsets in commercial 28 nm and 45 nm CMOS SRAMs from a monoenergetic electron beam. Upsets were observed in both technology nodes when the SRAM was operated in a low power state. The experimental cross section depends strongly on both bias and technology node feature size, consistent with previous work in which SRAMs were irradiated with low energy muons and protons. Accompanying simulations demonstrate that δ-rays produced by the primary electrons are responsible for the observed upsets. Additional simulations predict the on-orbit event rates for various Earth and Jovian environmentsmore » for a set of sensitive volumes representative of current technology nodes. The electron contribution to the total upset rate for Earth environments is significant for critical charges as high as 0.2 fC. This value is comparable to that of sub-22 nm bulk SRAMs. Similarly, for the Jovian environment, the electron-induced upset rate is larger than the proton-induced upset rate for critical charges as high as 0.3 fC.« less

Simulating the bio nanoelectronic interface

NASA Astrophysics Data System (ADS)

Millar, Campbell; Roy, Scott; Brown, Andrew R.; Asenov, Asen

2007-05-01

As the size of conventional nano-CMOS devices continues to shrink, they are beginning to approach the size of biologically relevant macromolecules such as ion channels. This, in concert with the increasing understanding of the behaviour of proteins in vivo, creates the potential for a revolution in the sensing, measurement and interaction with biological systems. In this paper we will demonstrate the theoretical possibility of directly coupling a nanoscale MOSFET with a model ion channel protein. This will potentially allow a much better understanding of the behaviour of biologically relevant molecules, since the measurement of the motion of charged particles can reveal a substantial amount of information about protein structure-function relationships. We can use the MOSFET's innate sensitivity to stray charge to detect the positions of single ions and, thus, better explore the dynamics of ion conduction in channel proteins. In addition, we also demonstrate that the MOSFET can be 'tuned' to sense current flow through channel proteins, thus providing, for the first time, a direct solid state/biological interface at the atomic level.

Towards High Throughput Cell Growth Screening: A New CMOS 8 × 8 Biosensor Array for Life Science Applications.

PubMed

Nabovati, Ghazal; Ghafar-Zadeh, Ebrahim; Letourneau, Antoine; Sawan, Mohamad

2017-04-01

In this paper we present a CMOS capacitive sensor array as a compact and low-cost platform for high-throughput cell growth monitoring. The proposed biosensor, consists of an array of 8 × 8 CMOS fully differential charge-based capacitive measurement sensors. A DC-input Σ∆ modulator is used to convert the sensors' signals to digital values for reading out the biological/chemical data and further signal processing. To compensate the mismatch variations between the current mirror transistors, a calibration circuitry is proposed which removes the output voltage offset with less than 8.2% error. We validate the chip functionality using various organic solvents with different dielectric constants. Moreover, we show the response of the chip to different concentrations of Polystyrene beads that have the same electrical properties as the living cells. The experimental results show that the chip allows the detection of a wide range of Polystyrene beads concentrations from as low as 10 beads/ml to 100 k beads/ml. In addition, we present the experimental results from H1299 (human lung carcinoma) cell line where we show that the chip successfully allows the detection of cell attachment and growth over capacitive electrodes in a 30 h measurement time and the results are in consistency with the standard cell-based assays. The capability of proposed device for label-free and real-time detection of cell growth with very high sensitivity opens up the important opportunity for utilizing the device in rapid screening of living cells.

High speed CMOS acquisition system based on FPGA embedded image processing for electro-optical measurements

NASA Astrophysics Data System (ADS)

Rosu-Hamzescu, Mihnea; Polonschii, Cristina; Oprea, Sergiu; Popescu, Dragos; David, Sorin; Bratu, Dumitru; Gheorghiu, Eugen

2018-06-01

Electro-optical measurements, i.e., optical waveguides and plasmonic based electrochemical impedance spectroscopy (P-EIS), are based on the sensitive dependence of refractive index of electro-optical sensors on surface charge density, modulated by an AC electrical field applied to the sensor surface. Recently, P-EIS has emerged as a new analytical tool that can resolve local impedance with high, optical spatial resolution, without using microelectrodes. This study describes a high speed image acquisition and processing system for electro-optical measurements, based on a high speed complementary metal-oxide semiconductor (CMOS) sensor and a field-programmable gate array (FPGA) board. The FPGA is used to configure CMOS parameters, as well as to receive and locally process the acquired images by performing Fourier analysis for each pixel, deriving the real and imaginary parts of the Fourier coefficients for the AC field frequencies. An AC field generator, for single or multi-sine signals, is synchronized with the high speed acquisition system for phase measurements. The system was successfully used for real-time angle-resolved electro-plasmonic measurements from 30 Hz up to 10 kHz, providing results consistent to ones obtained by a conventional electrical impedance approach. The system was able to detect amplitude variations with a relative variation of ±1%, even for rather low sampling rates per period (i.e., 8 samples per period). The PC (personal computer) acquisition and control software allows synchronized acquisition for multiple FPGA boards, making it also suitable for simultaneous angle-resolved P-EIS imaging.

Design of a Sub-Picosecond Jitter with Adjustable-Range CMOS Delay-Locked Loop for High-Speed and Low-Power Applications

PubMed Central

Abdulrazzaq, Bilal I.; Ibrahim, Omar J.; Kawahito, Shoji; Sidek, Roslina M.; Shafie, Suhaidi; Yunus, Nurul Amziah Md.; Lee, Lini; Halin, Izhal Abdul

2016-01-01

A Delay-Locked Loop (DLL) with a modified charge pump circuit is proposed for generating high-resolution linear delay steps with sub-picosecond jitter performance and adjustable delay range. The small-signal model of the modified charge pump circuit is analyzed to bring forth the relationship between the DLL’s internal control voltage and output time delay. Circuit post-layout simulation shows that a 0.97 ps delay step within a 69 ps delay range with 0.26 ps Root-Mean Square (RMS) jitter performance is achievable using a standard 0.13 µm Complementary Metal-Oxide Semiconductor (CMOS) process. The post-layout simulation results show that the power consumption of the proposed DLL architecture’s circuit is 0.1 mW when the DLL is operated at 2 GHz. PMID:27690040

Monolithic Active Pixel Sensors (MAPS) in a Quadruple Well Technology for Nearly 100% Fill Factor and Full CMOS Pixels.

PubMed

Ballin, Jamie Alexander; Crooks, Jamie Phillip; Dauncey, Paul Dominic; Magnan, Anne-Marie; Mikami, Yoshiari; Miller, Owen Daniel; Noy, Matthew; Rajovic, Vladimir; Stanitzki, Marcel; Stefanov, Konstantin; Turchetta, Renato; Tyndel, Mike; Villani, Enrico Giulio; Watson, Nigel Keith; Wilson, John Allan

2008-09-02

In this paper we present a novel, quadruple well process developed in a modern 0.18 mm CMOS technology called INMAPS. On top of the standard process, we have added a deep P implant that can be used to form a deep P-well and provide screening of N-wells from the P-doped epitaxial layer. This prevents the collection of radiation-induced charge by unrelated N-wells, typically ones where PMOS transistors are integrated. The design of a sensor specifically tailored to a particle physics experiment is presented, where each 50 mm pixel has over 150 PMOS and NMOS transistors. The sensor has been fabricated in the INMAPS process and first experimental evidence of the effectiveness of this process on charge collection is presented, showing a significant improvement in efficiency.

Characterizing Subpixel Spatial Resolution of a Hybrid CMOS Detector

NASA Astrophysics Data System (ADS)

Bray, Evan; Burrows, Dave; Chattopadhyay, Tanmoy; Falcone, Abraham; Hull, Samuel; Kern, Matthew; McQuaide, Maria; Wages, Mitchell

2018-01-01

The detection of X-rays is a unique process relative to other wavelengths, and allows for some novel features that increase the scientific yield of a single observation. Unlike lower photon energies, X-rays liberate a large number of electrons from the silicon absorber array of the detector. This number is usually on the order of several hundred to a thousand for moderate-energy X-rays. These electrons tend to diffuse outward into what is referred to as the charge cloud. This cloud can then be picked up by several pixels, forming a specific pattern based on the exact incident location. By conducting the first ever “mesh experiment" on a hybrid CMOS detector (HCD), we have experimentally determined the charge cloud shape and used it to characterize responsivity of the detector with subpixel spatial resolution.

Giant Gating Tunability of Optical Refractive Index in Transition Metal Dichalcogenide Monolayers.

PubMed

Yu, Yiling; Yu, Yifei; Huang, Lujun; Peng, Haowei; Xiong, Liwei; Cao, Linyou

2017-06-14

We report that the refractive index of transition metal dichacolgenide (TMDC) monolayers, such as MoS 2 , WS 2 , and WSe 2 , can be substantially tuned by >60% in the imaginary part and >20% in the real part around exciton resonances using complementary metal-oxide-semiconductor (CMOS) compatible electrical gating. This giant tunablility is rooted in the dominance of excitonic effects in the refractive index of the monolayers and the strong susceptibility of the excitons to the influence of injected charge carriers. The tunability mainly results from the effects of injected charge carriers to broaden the spectral width of excitonic interband transitions and to facilitate the interconversion of neutral and charged excitons. The other effects of the injected charge carriers, such as renormalizing bandgap and changing exciton binding energy, only play negligible roles. We also demonstrate that the atomically thin monolayers, when combined with photonic structures, can enable the efficiencies of optical absorption (reflection) tuned from 40% (60%) to 80% (20%) due to the giant tunability of the refractive index. This work may pave the way toward the development of field-effect photonics in which the optical functionality can be controlled with CMOS circuits.

A low jitter PLL clock used for phase change memory

NASA Astrophysics Data System (ADS)

Xiao, Hong; Houpeng, Chen; Zhitang, Song; Daolin, Cai; Xi, Li

2013-02-01

A fully integrated low-jitter, precise frequency CMOS phase-locked loop (PLL) clock for the phase change memory (PCM) drive circuit is presented. The design consists of a dynamic dual-reset phase frequency detector (PFD) with high frequency acquisition, a novel low jitter charge pump, a CMOS ring oscillator based voltage-controlled oscillator (VCO), a 2nd order passive loop filter, and a digital frequency divider. The design is fabricated in 0.35 μm CMOS technology and consumes 20 mW from a supply voltage of 5 V. In terms of the PCM's program operation requirement, the output frequency range is from 1 to 140 MHz. For the 140 MHz output frequency, the circuit features a cycle-to-cycle jitter of 28 ps RMS and 250 ps peak-to-peak.

Mk x Nk gated CMOS imager

NASA Astrophysics Data System (ADS)

Janesick, James; Elliott, Tom; Andrews, James; Tower, John; Bell, Perry; Teruya, Alan; Kimbrough, Joe; Bishop, Jeanne

2014-09-01

Our paper will describe a recently designed Mk x Nk x 10 um pixel CMOS gated imager intended to be first employed at the LLNL National Ignition Facility (NIF). Fabrication involves stitching MxN 1024x1024x10 um pixel blocks together into a monolithic imager (where M = 1, 2, . .10 and N = 1, 2, . . 10). The imager has been designed for either NMOS or PMOS pixel fabrication using a base 0.18 um/3.3V CMOS process. Details behind the design are discussed with emphasis on a custom global reset feature which erases the imager of unwanted charge in ~1 us during the fusion ignition process followed by an exposure to obtain useful data. Performance data generated by prototype imagers designed similar to the Mk x Nk sensor is presented.

Critical issues for the application of integrated MEMS/CMOS technologies to inertial measurement units

DOE Office of Scientific and Technical Information (OSTI.GOV)

Smith, J.H.; Ellis, J.R.; Montague, S.

1997-03-01

One of the principal applications of monolithically integrated micromechanical/microelectronic systems has been accelerometers for automotive applications. As integrated MEMS/CMOS technologies such as those developed by U.C. Berkeley, Analog Devices, and Sandia National Laboratories mature, additional systems for more sensitive inertial measurements will enter the commercial marketplace. In this paper, the authors will examine key technology design rules which impact the performance and cost of inertial measurement devices manufactured in integrated MEMS/CMOS technologies. These design parameters include: (1) minimum MEMS feature size, (2) minimum CMOS feature size, (3) maximum MEMS linear dimension, (4) number of mechanical MEMS layers, (5) MEMS/CMOS spacing.more » In particular, the embedded approach to integration developed at Sandia will be examined in the context of these technology features. Presently, this technology offers MEMS feature sizes as small as 1 {micro}m, CMOS critical dimensions of 1.25 {micro}m, MEMS linear dimensions of 1,000 {micro}m, a single mechanical level of polysilicon, and a 100 {micro}m space between MEMS and CMOS. This is applicable to modern precision guided munitions.« less

High-speed imaging using CMOS image sensor with quasi pixel-wise exposure

NASA Astrophysics Data System (ADS)

Sonoda, T.; Nagahara, H.; Endo, K.; Sugiyama, Y.; Taniguchi, R.

2017-02-01

Several recent studies in compressive video sensing have realized scene capture beyond the fundamental trade-off limit between spatial resolution and temporal resolution using random space-time sampling. However, most of these studies showed results for higher frame rate video that were produced by simulation experiments or using an optically simulated random sampling camera, because there are currently no commercially available image sensors with random exposure or sampling capabilities. We fabricated a prototype complementary metal oxide semiconductor (CMOS) image sensor with quasi pixel-wise exposure timing that can realize nonuniform space-time sampling. The prototype sensor can reset exposures independently by columns and fix these amount of exposure by rows for each 8x8 pixel block. This CMOS sensor is not fully controllable via the pixels, and has line-dependent controls, but it offers flexibility when compared with regular CMOS or charge-coupled device sensors with global or rolling shutters. We propose a method to realize pseudo-random sampling for high-speed video acquisition that uses the flexibility of the CMOS sensor. We reconstruct the high-speed video sequence from the images produced by pseudo-random sampling using an over-complete dictionary.

3-D readout-electronics packaging for high-bandwidth massively paralleled imager

DOEpatents

Kwiatkowski, Kris; Lyke, James

2007-12-18

Dense, massively parallel signal processing electronics are co-packaged behind associated sensor pixels. Microchips containing a linear or bilinear arrangement of photo-sensors, together with associated complex electronics, are integrated into a simple 3-D structure (a "mirror cube"). An array of photo-sensitive cells are disposed on a stacked CMOS chip's surface at a 45.degree. angle from light reflecting mirror surfaces formed on a neighboring CMOS chip surface. Image processing electronics are held within the stacked CMOS chip layers. Electrical connections couple each of said stacked CMOS chip layers and a distribution grid, the connections for distributing power and signals to components associated with each stacked CSMO chip layer.

Radiation induced failures of complementary metal oxide semiconductor containing pacemakers: a potentially lethal complication

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lewin, A.A.; Serago, C.F.; Schwade, J.G.

1984-10-01

New multi-programmable pacemakers frequently employ complementary metal oxide semiconductors (CMOS). This circuitry appears more sensitive to the effects of ionizing radiation when compared to the semiconductor circuits used in older pacemakers. A case of radiation induced runaway pacemaker in a CMOS device is described. Because of this and other recent reports of radiation therapy-induced CMOS type pacemaker failure, these pacemakers should not be irradiated. If necessary, the pacemaker can be shielded or moved to a site which can be shielded before institution of radiation therapy. This is done to prevent damage to the CMOS circuit and the life threatening arrythmiasmore » which may result from such damage.« less

A process modification for CMOS monolithic active pixel sensors for enhanced depletion, timing performance and radiation tolerance

NASA Astrophysics Data System (ADS)

Snoeys, W.; Aglieri Rinella, G.; Hillemanns, H.; Kugathasan, T.; Mager, M.; Musa, L.; Riedler, P.; Reidt, F.; Van Hoorne, J.; Fenigstein, A.; Leitner, T.

2017-11-01

For the upgrade of its Inner Tracking System, the ALICE experiment plans to install a new tracker fully constructed with monolithic active pixel sensors implemented in a standard 180 nm CMOS imaging sensor process, with a deep pwell allowing full CMOS within the pixel. Reverse substrate bias increases the tolerance to non-ionizing energy loss (NIEL) well beyond 1013 1 MeVneq /cm2, but does not allow full depletion of the sensitive layer and hence full charge collection by drift, mandatory for more extreme radiation tolerance. This paper describes a process modification to fully deplete the epitaxial layer even with a small charge collection electrode. It uses a low dose blanket deep high energy n-type implant in the pixel array and does not require significant circuit or layout changes so that the same design can be fabricated both in the standard and modified process. When exposed to a 55 Fe source at a reverse substrate bias of -6 V, pixels implemented in the standard and the modified process in a low and high dose variant for the deep n-type implant respectively yield a signal of about 115 mV, 110 mV and 90 mV at the output of a follower circuit. Signal rise times heavily affected by the speed of this circuit are 27 . 8 + / - 5 ns, 23 . 2 + / - 4 . 2 ns, and 22 . 2 + / - 3 . 7 ns rms, respectively. In a different setup, the single pixel signal from a 90 Sr source only degrades by less than 20% for the modified process after a 1015 1 MeVneq /cm2 irradiation, while the signal rise time only degrades by about 16 + / - 2 ns to 19 + / - 2 . 8 ns rms. From sensors implemented in the standard process no useful signal could be extracted after the same exposure. These first results indicate the process modification maintains low sensor capacitance, improves timing performance and increases NIEL tolerance by at least an order of magnitude.

Application specific serial arithmetic arrays

NASA Technical Reports Server (NTRS)

Winters, K.; Mathews, D.; Thompson, T.

1990-01-01

High performance systolic arrays of serial-parallel multiplier elements may be rapidly constructed for specific applications by applying hardware description language techniques to a library of full-custom CMOS building blocks. Single clock pre-charged circuits have been implemented for these arrays at clock rates in excess of 100 Mhz using economical 2-micron (minimum feature size) CMOS processes, which may be quickly configured for a variety of applications. A number of application-specific arrays are presented, including a 2-D convolver for image processing, an integer polynomial solver, and a finite-field polynomial solver.

CMOS Cell Sensors for Point-of-Care Diagnostics

PubMed Central

Adiguzel, Yekbun; Kulah, Haluk

2012-01-01

The burden of health-care related services in a global era with continuously increasing population and inefficient dissipation of the resources requires effective solutions. From this perspective, point-of-care diagnostics is a demanded field in clinics. It is also necessary both for prompt diagnosis and for providing health services evenly throughout the population, including the rural districts. The requirements can only be fulfilled by technologies whose productivity has already been proven, such as complementary metal-oxide-semiconductors (CMOS). CMOS-based products can enable clinical tests in a fast, simple, safe, and reliable manner, with improved sensitivities. Portability due to diminished sensor dimensions and compactness of the test set-ups, along with low sample and power consumption, is another vital feature. CMOS-based sensors for cell studies have the potential to become essential counterparts of point-of-care diagnostics technologies. Hence, this review attempts to inform on the sensors fabricated with CMOS technology for point-of-care diagnostic studies, with a focus on CMOS image sensors and capacitance sensors for cell studies. PMID:23112587

CMOS cell sensors for point-of-care diagnostics.

PubMed

Adiguzel, Yekbun; Kulah, Haluk

2012-01-01

The burden of health-care related services in a global era with continuously increasing population and inefficient dissipation of the resources requires effective solutions. From this perspective, point-of-care diagnostics is a demanded field in clinics. It is also necessary both for prompt diagnosis and for providing health services evenly throughout the population, including the rural districts. The requirements can only be fulfilled by technologies whose productivity has already been proven, such as complementary metal-oxide-semiconductors (CMOS). CMOS-based products can enable clinical tests in a fast, simple, safe, and reliable manner, with improved sensitivities. Portability due to diminished sensor dimensions and compactness of the test set-ups, along with low sample and power consumption, is another vital feature. CMOS-based sensors for cell studies have the potential to become essential counterparts of point-of-care diagnostics technologies. Hence, this review attempts to inform on the sensors fabricated with CMOS technology for point-of-care diagnostic studies, with a focus on CMOS image sensors and capacitance sensors for cell studies.

An electrostatic CMOS/BiCMOS Lithium ion vibration-based harvester-charger IC

NASA Astrophysics Data System (ADS)

Torres, Erick Omar

Self-powered microsystems, such as wireless transceiver microsensors, appeal to an expanding application space in monitoring, control, and diagnosis for commercial, industrial, military, space, and biomedical products. As these devices continue to shrink, their microscale dimensions allow them to be unobtrusive and economical, with the potential to operate from typically unreachable environments and, in wireless network applications, deploy numerous distributed sensing nodes simultaneously. Extended operational life, however, is difficult to achieve since their limited volume space constrains the stored energy available, even with state-of-the-art technologies, such as thin-film lithium-ion batteries (Li Ion) and micro-fuel cells. Harvesting ambient energy overcomes this deficit by continually replenishing the energy reservoir and, as a result, indefinitely extending system lifetime. In this work, an electrostatic harvester that harnesses ambient kinetic energy from vibrations to charge an energy-storage device (e.g., a battery) is investigated, developed, and evaluated. The proposed harvester charges and holds the voltage across a vibration-sensitive variable capacitor so that vibrations can induce it to generate current into the battery when capacitance decreases (as its plates separate). The challenge is that energy is harnessed at relatively slow rates, producing low output power, and the electronics required to transfer it to charge a battery can easily demand more than the power produced. To this end, the system reduces losses by time-managing and biasing its circuits to operate only when needed and with just enough energy while charging the capacitor through an efficient quasi-lossless inductor-based precharger. As result, the proposed energy harvester stores a net energy gain in the battery during every vibration cycle. Two energy-harvesting integrated circuits (IC) were analyzed, designed, developed, and validated using a 0.7-im BiCMOS process and a 30-Hz mechanical variable capacitor. The precharger, harvester, monitoring, and control microelectronics of the first prototype draw sufficient power to operate and at the same time produce experimentally 1.27, 2.14, and 2.87 nJ per vibration cycle for battery voltages at 2.7, 3.5, and 4.2 V, which with 30-Hz vibrations produce 38.1, 64.2, and 86.1 nW. By incorporating into the system a self-tuning loop that adapts optimally the inductor-based precharger to varying battery voltages, the second prototype harnessed and gained 1.93, 2.43, and 3.89 nJ per vibration cycle at battery voltages 2.7, 3.5, and 4.2 V, generating 57.89, 73.02, and 116.55 nW at 30 Hz. The harvester ultimately charges from 2.7 to 4.2 V a 1-muF capacitor (which emulates a small thin-film Li Ion) in approximately 69 s, harnessing in the same length of time 47.9% more energy than with a non-adapting harvester.

A 75-ps Gated CMOS Image Sensor with Low Parasitic Light Sensitivity

PubMed Central

Zhang, Fan; Niu, Hanben

2016-01-01

In this study, a 40 × 48 pixel global shutter complementary metal-oxide-semiconductor (CMOS) image sensor with an adjustable shutter time as low as 75 ps was implemented using a 0.5-μm mixed-signal CMOS process. The implementation consisted of a continuous contact ring around each p+/n-well photodiode in the pixel array in order to apply sufficient light shielding. The parasitic light sensitivity of the in-pixel storage node was measured to be 1/8.5 × 107 when illuminated by a 405-nm diode laser and 1/1.4 × 104 when illuminated by a 650-nm diode laser. The pixel pitch was 24 μm, the size of the square p+/n-well photodiode in each pixel was 7 μm per side, the measured random readout noise was 217 e− rms, and the measured dynamic range of the pixel of the designed chip was 5500:1. The type of gated CMOS image sensor (CIS) that is proposed here can be used in ultra-fast framing cameras to observe non-repeatable fast-evolving phenomena. PMID:27367699

A 75-ps Gated CMOS Image Sensor with Low Parasitic Light Sensitivity.

PubMed

Zhang, Fan; Niu, Hanben

2016-06-29

In this study, a 40 × 48 pixel global shutter complementary metal-oxide-semiconductor (CMOS) image sensor with an adjustable shutter time as low as 75 ps was implemented using a 0.5-μm mixed-signal CMOS process. The implementation consisted of a continuous contact ring around each p+/n-well photodiode in the pixel array in order to apply sufficient light shielding. The parasitic light sensitivity of the in-pixel storage node was measured to be 1/8.5 × 10⁷ when illuminated by a 405-nm diode laser and 1/1.4 × 10⁴ when illuminated by a 650-nm diode laser. The pixel pitch was 24 μm, the size of the square p+/n-well photodiode in each pixel was 7 μm per side, the measured random readout noise was 217 e(-) rms, and the measured dynamic range of the pixel of the designed chip was 5500:1. The type of gated CMOS image sensor (CIS) that is proposed here can be used in ultra-fast framing cameras to observe non-repeatable fast-evolving phenomena.

A 0.18 μm CMOS fluorescent detector system for bio-sensing application

NASA Astrophysics Data System (ADS)

Nan, Liu; Guoping, Chen; Zhiliang, Hong

2009-01-01

A CMOS fluorescent detector system for biological experiment is presented. This system integrates a CMOS compatible photodiode, a capacitive trans-impedance amplifier (CTIA), and a 12 bit pipelined analog-to-digital converter (ADC), and is implemented in a 0.18 μm standard CMOS process. Some special techniques, such as a 'contact imaging' detecting method, pseudo-differential architecture, dummy photodiodes, and a T-type reset switch, are adopted to achieve low-level sensing application. Experiment results show that the Nwell/Psub photodiode with CTIA pixel achieves a sensitivity of 0.1 A/W at 515 nm and a dark current of 300 fA with 300 mV reverse biased voltage. The maximum differential and integral nonlinearity of the designed ADC are 0.8 LSB and 3 LSB, respectively. With an integrating time of 50 ms, this system is sensitive to the fluorescence emitted by the fluorescein solution with concentration as low as 20 ng/mL and can generate 7 fA photocurrent. This chip occupies 3 mm2 and consumes 37 mW.

Novel CMOS photosensor with a gate-body tied NMOSFET structure

NASA Astrophysics Data System (ADS)

Kook, Youn-Jae; Jeong, Jae-Hun; Park, Young-June; Min, Hong-Shick

2000-07-01

A novel CMOS photosensor with a gate-body tied NMOSFET structure realized in the triple is well presented. The photocurrent is amplified by the lateral and vertical BJT action, which results in two different output photocurrents, which can be used for different applications within a pixel. The lateral action results in the drain current with a higher sensitivity at low light intensity. And the vertical action results in the collector current with uniform responsivity over wider range of the light intensity. The proposed photosensor in compatible with CMOS circuits.

Fabricating a hybrid imaging device

NASA Technical Reports Server (NTRS)

Wadsworth, Mark (Inventor); Atlas, Gene (Inventor)

2003-01-01

A hybrid detector or imager includes two substrates fabricated under incompatible processes. An array of detectors, such as charged-coupled devices, are formed on the first substrate using a CCD fabrication process, such as a buried channel or peristaltic process. One or more charge-converting amplifiers are formed on a second substrate using a CMOS fabrication process. The two substrates are then bonded together to form a hybrid detector.

MEMS capacitive pressure sensor monolithically integrated with CMOS readout circuit by using post CMOS processes

NASA Astrophysics Data System (ADS)

Jang, Munseon; Yun, Kwang-Seok

2017-12-01

In this paper, we presents a MEMS pressure sensor integrated with a readout circuit on a chip for an on-chip signal processing. The capacitive pressure sensor is formed on a CMOS chip by using a post-CMOS MEMS processes. The proposed device consists of a sensing capacitor that is square in shape, a reference capacitor and a readout circuitry based on a switched-capacitor scheme to detect capacitance change at various environmental pressures. The readout circuit was implemented by using a commercial 0.35 μm CMOS process with 2 polysilicon and 4 metal layers. Then, the pressure sensor was formed by wet etching of metal 2 layer through via hole structures. Experimental results show that the MEMS pressure sensor has a sensitivity of 11 mV/100 kPa at the pressure range of 100-400 kPa.

Growth of carbon nanotubes on fully processed silicon-on-insulator CMOS substrates.

PubMed

Haque, M Samiul; Ali, S Zeeshan; Guha, P K; Oei, S P; Park, J; Maeng, S; Teo, K B K; Udrea, F; Milne, W I

2008-11-01

This paper describes the growth of Carbon Nanotubes (CNTs) both aligned and non-aligned on fully processed CMOS substrates containing high temperature tungsten metallization. While the growth method has been demonstrated in fabricating CNT gas sensitive layers for high temperatures SOI CMOS sensors, it can be employed in a variety of applications which require the use of CNTs or other nanomaterials with CMOS electronics. In our experiments we have grown CNTs both on SOI CMOS substrates and SOI CMOS microhotplates (suspended on membranes formed by post-CMOS deep RIE etching). The fully processed SOI substrates contain CMOS devices and circuits and additionally, some wafers contained high current LDMOSFETs and bipolar structures such as Lateral Insulated Gate Bipolar Transistors. All these devices were used as test structures to investigate the effect of additional post-CMOS processing such as CNT growth, membrane formation, high temperature annealing, etc. Electrical characterisation of the devices with CNTs were performed along with SEM and Raman spectroscopy. The CNTs were grown both at low and high temperatures, the former being compatible with Aluminium metallization while the latter being possible through the use of the high temperature CMOS metallization (Tungsten). In both cases we have found that there is no change in the electrical behaviour of the CMOS devices, circuits or the high current devices. A slight degradation of the thermal performance of the CMOS microhotplates was observed due to the extra heat dissipation path created by the CNT layers, but this is expected as CNTs exhibit a high thermal conductance. In addition we also observed that in the case of high temperature CNT growth a slight degradation in the manufacturing yield was observed. This is especially the case where large area membranes with a diameter in excess of 500 microns are used.

Ethanol Microsensors with a Readout Circuit Manufactured Using the CMOS-MEMS Technique

PubMed Central

Yang, Ming-Zhi; Dai, Ching-Liang

2015-01-01

The design and fabrication of an ethanol microsensor integrated with a readout circuit on-a-chip using the complementary metal oxide semiconductor (CMOS)-microelectro-mechanical system (MEMS) technique are investigated. The ethanol sensor is made up of a heater, a sensitive film and interdigitated electrodes. The sensitive film is tin dioxide that is prepared by the sol-gel method. The heater is located under the interdigitated electrodes, and the sensitive film is coated on the interdigitated electrodes. The sensitive film needs a working temperature of 220 °C. The heater is employed to provide the working temperature of sensitive film. The sensor generates a change in capacitance when the sensitive film senses ethanol gas. A readout circuit is used to convert the capacitance variation of the sensor into the output frequency. Experiments show that the sensitivity of the ethanol sensor is 0.9 MHz/ppm. PMID:25594598

Ethanol microsensors with a readout circuit manufactured using the CMOS-MEMS technique.

PubMed

Yang, Ming-Zhi; Dai, Ching-Liang

2015-01-14

The design and fabrication of an ethanol microsensor integrated with a readout circuit on-a-chip using the complementary metal oxide semiconductor (CMOS)-microelectro -mechanical system (MEMS) technique are investigated. The ethanol sensor is made up of a heater, a sensitive film and interdigitated electrodes. The sensitive film is tin dioxide that is prepared by the sol-gel method. The heater is located under the interdigitated electrodes, and the sensitive film is coated on the interdigitated electrodes. The sensitive film needs a working temperature of 220 °C. The heater is employed to provide the working temperature of sensitive film. The sensor generates a change in capacitance when the sensitive film senses ethanol gas. A readout circuit is used to convert the capacitance variation of the sensor into the output frequency. Experiments show that the sensitivity of the ethanol sensor is 0.9 MHz/ppm.

Monolithic Active Pixel Sensors (MAPS) in a Quadruple Well Technology for Nearly 100% Fill Factor and Full CMOS Pixels

PubMed Central

Ballin, Jamie Alexander; Crooks, Jamie Phillip; Dauncey, Paul Dominic; Magnan, Anne-Marie; Mikami, Yoshinari; Miller, Owen Daniel; Noy, Matthew; Rajovic, Vladimir; Stanitzki, Marcel; Stefanov, Konstantin; Turchetta, Renato; Tyndel, Mike; Villani, Enrico Giulio; Watson, Nigel Keith; Wilson, John Allan

2008-01-01

In this paper we present a novel, quadruple well process developed in a modern 0.18 μm CMOS technology called INMAPS. On top of the standard process, we have added a deep P implant that can be used to form a deep P-well and provide screening of N-wells from the P-doped epitaxial layer. This prevents the collection of radiation-induced charge by unrelated N-wells, typically ones where PMOS transistors are integrated. The design of a sensor specifically tailored to a particle physics experiment is presented, where each 50 μm pixel has over 150 PMOS and NMOS transistors. The sensor has been fabricated in the INMAPS process and first experimental evidence of the effectiveness of this process on charge collection is presented, showing a significant improvement in efficiency. PMID:27873817

Measurement of charge transfer potential barrier in pinned photodiode CMOS image sensors

NASA Astrophysics Data System (ADS)

Chen, Cao; Bing, Zhang; Junfeng, Wang; Longsheng, Wu

2016-05-01

The charge transfer potential barrier (CTPB) formed beneath the transfer gate causes a noticeable image lag issue in pinned photodiode (PPD) CMOS image sensors (CIS), and is difficult to measure straightforwardly since it is embedded inside the device. From an understanding of the CTPB formation mechanism, we report on an alternative method to feasibly measure the CTPB height by performing a linear extrapolation coupled with a horizontal left-shift on the sensor photoresponse curve under the steady-state illumination. The theoretical study was performed in detail on the principle of the proposed method. Application of the measurements on a prototype PPD-CIS chip with an array of 160 × 160 pixels is demonstrated. Such a method intends to shine new light on the guidance for the lag-free and high-speed sensors optimization based on PPD devices. Project supported by the National Defense Pre-Research Foundation of China (No. 51311050301095).

A Demonstration of TIA Using FD-SOI CMOS OPAMP for Far-Infrared Astronomy

NASA Astrophysics Data System (ADS)

Nagase, Koichi; Wada, Takehiko; Ikeda, Hirokazu; Arai, Yasuo; Ohno, Morifumi; Hanaoka, Misaki; Kanada, Hidehiro; Oyabu, Shinki; Hattori, Yasuki; Ukai, Sota; Suzuki, Toyoaki; Watanabe, Kentaroh; Baba, Shunsuke; Kochi, Chihiro; Yamamoto, Keita

2016-07-01

We are developing a fully depleted silicon-on-insulator (FD-SOI) CMOS readout integrated circuit (ROIC) operated at temperatures below ˜ 4 K. Its application is planned for the readout circuit of high-impedance far-infrared detectors for astronomical observations. We designed a trans-impedance amplifier (TIA) using a CMOS operational amplifier (OPAMP) with FD-SOI technique. The TIA is optimized to readout signals from a germanium blocked impurity band (Ge BIB) detector which is highly sensitive to wavelengths of up to ˜ 200 \\upmu m. For the first time, we demonstrated the FD-SOI CMOS OPAMP combined with the Ge BIB detector at 4.5 K. The result promises to solve issues faced by conventional cryogenic ROICs.

Monolithic circuits for barium fluoride detectors used in nuclear physics experiments. CRADA final report

DOE Office of Scientific and Technical Information (OSTI.GOV)

Varner, R.L.; Blankenship, J.L.; Beene, J.R.

1998-02-01

Custom monolithic electronic circuits have been developed recently for large detector applications in high energy physics where subsystems require tens of thousands of channels of signal processing and data acquisition. In the design and construction of these enormous detectors, it has been found that monolithic circuits offer significant advantages over discrete implementations through increased performance, flexible packaging, lower power and reduced cost per channel. Much of the integrated circuit design for the high energy physics community is directly applicable to intermediate energy heavy-ion and electron physics. This STTR project conducted in collaboration with researchers at the Holifield Radioactive Ion Beammore » Facility (HRIBF) at Oak Ridge National Laboratory, sought to develop a new integrated circuit chip set for barium fluoride (BaF{sub 2}) detector arrays based upon existing CMOS monolithic circuit designs created for the high energy physics experiments. The work under the STTR Phase 1 demonstrated through the design, simulation, and testing of several prototype chips the feasibility of using custom CMOS integrated circuits for processing signals from BaF{sub 2} detectors. Function blocks including charge-sensitive amplifiers, comparators, one shots, time-to-amplitude converters, analog memory circuits and buffer amplifiers were implemented during Phase 1 effort. Experimental results from bench testing and laboratory testing with sources were documented.« less

Use and imaging performance of CMOS flat panel imager with LiF/ZnS(Ag) and Gadox scintillation screens for neutron radiography

NASA Astrophysics Data System (ADS)

Cha, B. K.; kim, J. Y.; Kim, T. J.; Sim, C.; Cho, G.; Lee, D. H.; Seo, C.-W.; Jeon, S.; Huh, Y.

2011-01-01

In digital neutron radiography system, a thermal neutron imaging detector based on neutron-sensitive scintillating screens with CMOS(complementary metal oxide semiconductor) flat panel imager is introduced for non-destructive testing (NDT) application. Recently, large area CMOS APS (active-pixel sensor) in conjunction with scintillation films has been widely used in many digital X-ray imaging applications. Instead of typical imaging detectors such as image plates, cooled-CCD cameras and amorphous silicon flat panel detectors in combination with scintillation screens, we tried to apply a scintillator-based CMOS APS to neutron imaging detection systems for high resolution neutron radiography. In this work, two major Gd2O2S:Tb and 6LiF/ZnS:Ag scintillation screens with various thickness were fabricated by a screen printing method. These neutron converter screens consist of a dispersion of Gd2O2S:Tb and 6LiF/ZnS:Ag scintillating particles in acrylic binder. These scintillating screens coupled-CMOS flat panel imager with 25x50mm2 active area and 48μm pixel pitch was used for neutron radiography. Thermal neutron flux with 6x106n/cm2/s was utilized at the NRF facility of HANARO in KAERI. The neutron imaging characterization of the used detector was investigated in terms of relative light output, linearity and spatial resolution in detail. The experimental results of scintillating screen-based CMOS flat panel detectors demonstrate possibility of high sensitive and high spatial resolution imaging in neutron radiography system.

Precise Side-Chain Engineering of Thienylenevinylene-Benzotriazole-Based Conjugated Polymers with Coplanar Backbone for Organic Field Effect Transistors and CMOS-like Inverters.

PubMed

Lee, Min-Hye; Kim, Juhwan; Kang, Minji; Kim, Jihong; Kang, Boseok; Hwang, Hansu; Cho, Kilwon; Kim, Dong-Yu

2017-01-25

Two donor-acceptor (D-A) alternating conjugated polymers based on thienylenevinylene-benzotriazole (TV-BTz), PTV6B with a linear side chain and PTVEhB with a branched side chain, were synthesized and characterized for organic field effect transistors (OFETs) and complementary metal-oxide-semiconductor (CMOS)-like inverters. According to density functional theory (DFT), polymers based on TV-BTz exhibit a coplanar and rigid structure with no significant twists, which could cause to an increase in charge-carrier mobility in OFETs. Alternating alkyl side chains of the polymers impacted neither the band gap nor the energy level. However, it significantly affected the morphology and crystallinity when the polymer films were thermally annealed. To investigate the effect of thermal annealing on the morphology and crystallinity, we characterized the polymer films using atomic force microscopy (AFM) and 2D-grazing incidence X-ray diffraction (2D-GIWAXD). Fibrillary morphologies with larger domains and increased crystallinity were observed in the polymer films after thermal annealing. These polymers exhibited improved charge-carrier mobilities in annealed films at 200 °C and demonstrated optimal OFET device performance with p-type transport characteristics with charge-carrier mobilities of 1.51 cm 2 /(V s) (PTV6B) and 2.58 cm 2 /(V s) (PTVEhB). Furthermore, CMOS-like inorganic (ZnO)-organic (PTVEhB) hybrid bilayer inverter showed that the inverting voltage (V inv ) was positioned near the ideal switching point at half (1/2) of supplied voltage (V DD ) due to fairly balanced p- and n-channels.

Defect-sensitivity analysis of an SEU immune CMOS logic family

NASA Technical Reports Server (NTRS)

Ingermann, Erik H.; Frenzel, James F.

1992-01-01

Fault testing of resistive manufacturing defects is done on a recently developed single event upset immune logic family. Resistive ranges and delay times are compared with those of traditional CMOS logic. Reaction of the logic to these defects is observed for a NOR gate, and an evaluation of its ability to cope with them is determined.

X-ray performance of 0.18 µm CMOS APS test arrays for solar observation

NASA Astrophysics Data System (ADS)

Dryer, B. J.; Holland, A. D.; Jerram, P.; Sakao, Taro

2012-07-01

Solar-C is the third generation solar observatory led by JAXA. The accepted ‘Plan-B’ payload calls for a radiation-hard solar-staring photon-counting x-ray spectrometer. CMOS APS technology offers advantages over CCDs for such an application such as increased radiation hardness and high frame rate (instrument target of 1000 fps). Looking towards the solution of a bespoke CMOS APS, this paper reports the x-ray spectroscopy performance, concentrating on charge collection efficiency and split event analysis, of two baseline e2v CMOS APSs not designed for x-ray performance, the EV76C454 and the Ocean Colour Imager (OCI) test array. The EV76C454 is an industrial 5T APS designed for machine vision, available back and front illuminated. The OCI test arrays have varying pixel design across the chips, but are 4T, back illuminated and have thin low-resistivity and thick high-resistivity variants. The OCI test arrays’ pixel variants allow understanding of how pixel design can affect x-ray performance.

Co-integrating plasmonics with Si3N4 photonics towards a generic CMOS compatible PIC platform for high-sensitivity multi-channel biosensors: the H2020 PlasmoFab approach (Conference Presentation)

NASA Astrophysics Data System (ADS)

Tsiokos, Dimitris M.; Dabos, George; Ketzaki, Dimitra; Weeber, Jean-Claude; Markey, Laurent; Dereux, Alain; Giesecke, Anna Lena; Porschatis, Caroline; Chmielak, Bartos; Wahlbrink, Thorsten; Rochracher, Karl; Pleros, Nikos

2017-05-01

Silicon photonics meet most fabrication requirements of standard CMOS process lines encompassing the photonics-electronics consolidation vision. Despite this remarkable progress, further miniaturization of PICs for common integration with electronics and for increasing PIC functional density is bounded by the inherent diffraction limit of light imposed by optical waveguides. Instead, Surface Plasmon Polariton (SPP) waveguides can guide light at sub-wavelength scales at the metal surface providing unique light-matter interaction properties, exploiting at the same time their metallic nature to naturally integrate with electronics in high-performance ASPICs. In this article, we demonstrate the main goals of the recently introduced H2020 project PlasmoFab towards addressing the ever increasing needs for low energy, small size and high performance mass manufactured PICs by developing a revolutionary yet CMOS-compatible fabrication platform for seamless co-integration of plasmonics with photonic and supporting electronic. We demonstrate recent advances on the hosting SiN photonic hosting platform reporting on low-loss passive SiN waveguide and Grating Coupler circuits for both the TM and TE polarization states. We also present experimental results of plasmonic gold thin-film and hybrid slot waveguide configurations that can allow for high-sensitivity sensing, providing also the ongoing activities towards replacing gold with Cu, Al or TiN metal in order to yield the same functionality over a CMOS metallic structure. Finally, the first experimental results on the co-integrated SiN+plasmonic platform are demonstrated, concluding to an initial theoretical performance analysis of the CMOS plasmo-photonic biosensor that has the potential to allow for sensitivities beyond 150000nm/RIU.

Resolution Properties of a Calcium Tungstate (CaWO4) Screen Coupled to a CMOS Imaging Detector

NASA Astrophysics Data System (ADS)

Koukou, Vaia; Martini, Niki; Valais, Ioannis; Bakas, Athanasios; Kalyvas, Nektarios; Lavdas, Eleftherios; Fountos, George; Kandarakis, Ioannis; Michail, Christos

2017-11-01

The aim of the current work was to assess the resolution properties of a calcium tungstate (CaWO4) screen (screen coating thickness: 50.09 mg/cm2, actual thickness: 167.2 μm) coupled to a high resolution complementary metal oxide semiconductor (CMOS) digital imaging sensor. A 2.7x3.6 cm2 CaWO4 sample was extracted from an Agfa Curix universal screen and was coupled directly with the active area of the active pixel sensor (APS) CMOS sensor. Experiments were performed following the new IEC 62220-1-1:2015 International Standard, using an RQA-5 beam quality. Resolution was assessed in terms of the Modulation Transfer Function (MTF), using the slanted-edge method. The CaWO4/CMOS detector configuration was found with linear response, in the exposure range under investigation. The final MTF was obtained through averaging the oversampled edge spread function (ESF), using a custom-made software developed by our team, according to the IEC 62220-1-1:2015. Considering the renewed interest in calcium tungstate for various applications, along with the resolution results of this work, CaWO4 could be also considered for use in X-ray imaging devices such as charged-coupled devices (CCD) and CMOS.

Design and image-quality performance of high resolution CMOS-based X-ray imaging detectors for digital mammography

NASA Astrophysics Data System (ADS)

Cha, B. K.; Kim, J. Y.; Kim, Y. J.; Yun, S.; Cho, G.; Kim, H. K.; Seo, C.-W.; Jeon, S.; Huh, Y.

2012-04-01

In digital X-ray imaging systems, X-ray imaging detectors based on scintillating screens with electronic devices such as charge-coupled devices (CCDs), thin-film transistors (TFT), complementary metal oxide semiconductor (CMOS) flat panel imagers have been introduced for general radiography, dental, mammography and non-destructive testing (NDT) applications. Recently, a large-area CMOS active-pixel sensor (APS) in combination with scintillation films has been widely used in a variety of digital X-ray imaging applications. We employed a scintillator-based CMOS APS image sensor for high-resolution mammography. In this work, both powder-type Gd2O2S:Tb and a columnar structured CsI:Tl scintillation screens with various thicknesses were fabricated and used as materials to convert X-ray into visible light. These scintillating screens were directly coupled to a CMOS flat panel imager with a 25 × 50 mm2 active area and a 48 μm pixel pitch for high spatial resolution acquisition. We used a W/Al mammographic X-ray source with a 30 kVp energy condition. The imaging characterization of the X-ray detector was measured and analyzed in terms of linearity in incident X-ray dose, modulation transfer function (MTF), noise-power spectrum (NPS) and detective quantum efficiency (DQE).

A High Sensitivity Bio Photosensor for Detecting a Luciferase Bioluminescence

NASA Astrophysics Data System (ADS)

Kameda, Seiji; Moriyama, Yusuke; Noda, Kenichi; Iwata, Atsushi

A high sensitivity CMOS bio photosensor applicable to a bioluminescent assay was developed with a 0.18µm CMOS image sensor (CIS) process. The bio photosensor consisting of a photosensor and a PWM 20bit A/D converter achieved high sensitivity for detecting a extremely low bioluminescence due to a large photodiode area, a long exposure time and the other noise reduction techniques. The bio photosensor chip has a 2×4 sensor array on a 2.45×2.45mm2 die. Experimental results with the bioluminescence showed the chip can detect below 10-5lux luminescence at room temperature and the power consumption is 32µW.

Fabricating a hybrid imaging device having non-destructive sense nodes

NASA Technical Reports Server (NTRS)

Wadsworth, Mark (Inventor); Atlas, Gene (Inventor)

2001-01-01

A hybrid detector or imager includes two substrates fabricated under incompatible processes. An array of detectors, such as charged-coupled devices, are formed on the first substrate using a CCD fabrication process, such as a buried channel or peristaltic process. One or more charge-converting amplifiers are formed on a second substrate using a CMOS fabrication process. The two substrates are then bonded together to form a hybrid detector.

Innovative monolithic detector for tri-spectral (THz, IR, Vis) imaging

NASA Astrophysics Data System (ADS)

Pocas, S.; Perenzoni, M.; Massari, N.; Simoens, F.; Meilhan, J.; Rabaud, W.; Martin, S.; Delplanque, B.; Imperinetti, P.; Goudon, V.; Vialle, C.; Arnaud, A.

2012-10-01

Fusion of multispectral images has been explored for many years for security and used in a number of commercial products. CEA-Leti and FBK have developed an innovative sensor technology that gathers monolithically on a unique focal plane arrays, pixels sensitive to radiation in three spectral ranges that are terahertz (THz), infrared (IR) and visible. This technology benefits of many assets for volume market: compactness, full CMOS compatibility on 200mm wafers, advanced functions of the CMOS read-out integrated circuit (ROIC), and operation at room temperature. The ROIC houses visible APS diodes while IR and THz detections are carried out by microbolometers collectively processed above the CMOS substrate. Standard IR bolometric microbridges (160x160 pixels) are surrounding antenna-coupled bolometers (32X32 pixels) built on a resonant cavity customized to THz sensing. This paper presents the different technological challenges achieved in this development and first electrical and sensitivity experimental tests.

Charge Splitting In Situ Recorder (CSIR) for Real-Time Examination of Plasma Charging Effect in FinFET BEOL Processes

NASA Astrophysics Data System (ADS)

Tsai, Yi-Pei; Hsieh, Ting-Huan; Lin, Chrong Jung; King, Ya-Chin

2017-09-01

A novel device for monitoring plasma-induced damage in the back-end-of-line (BEOL) process with charge splitting capability is first-time proposed and demonstrated. This novel charge splitting in situ recorder (CSIR) can independently trace the amount and polarity of plasma charging effects during the manufacturing process of advanced fin field-effect transistor (FinFET) circuits. Not only does it reveal the real-time and in situ plasma charging levels on the antennas, but it also separates positive and negative charging effect and provides two independent readings. As CMOS technologies push for finer metal lines in the future, the new charge separation scheme provides a powerful tool for BEOL process optimization and further device reliability improvements.

Charge integration successive approximation analog-to-digital converter for focal plane applications using a single amplifier

NASA Technical Reports Server (NTRS)

Zhou, Zhimin (Inventor); Pain, Bedabrata (Inventor)

1999-01-01

An analog-to-digital converter for on-chip focal-plane image sensor applications. The analog-to-digital converter utilizes a single charge integrating amplifier in a charge balancing architecture to implement successive approximation analog-to-digital conversion. This design requires minimal chip area and has high speed and low power dissipation for operation in the 2-10 bit range. The invention is particularly well suited to CMOS on-chip applications requiring many analog-to-digital converters, such as column-parallel focal-plane architectures.

3-Axis Fully-Integrated Capacitive Tactile Sensor with Flip-Bonded CMOS on LTCC Interposer.

PubMed

Asano, Sho; Muroyama, Masanori; Nakayama, Takahiro; Hata, Yoshiyuki; Nonomura, Yutaka; Tanaka, Shuji

2017-10-25

This paper reports a 3-axis fully integrated differential capacitive tactile sensor surface-mountable on a bus line. The sensor integrates a flip-bonded complementary metal-oxide semiconductor (CMOS) with capacitive sensing circuits on a low temperature cofired ceramic (LTCC) interposer with Au through vias by Au-Au thermo-compression bonding. The CMOS circuit and bonding pads on the sensor backside were electrically connected through Au bumps and the LTCC interposer, and the differential capacitive gap was formed by an Au sealing frame. A diaphragm for sensing 3-axis force was formed in the CMOS substrate. The dimensions of the completed sensor are 2.5 mm in width, 2.5 mm in length, and 0.66 mm in thickness. The fabricated sensor output coded 3-axis capacitive sensing data according to applied 3-axis force by three-dimensional (3D)-printed pins. The measured sensitivity was as high as over 34 Count/mN for normal force and 14 to 15 Count/mN for shear force with small noise, which corresponds to less than 1 mN. The hysteresis and the average cross-sensitivity were also found to be less than 2% full scale and 11%, respectively.

Nanometric Integrated Temperature and Thermal Sensors in CMOS-SOI Technology.

PubMed

Malits, Maria; Nemirovsky, Yael

2017-07-29

This paper reviews and compares the thermal and noise characterization of CMOS (complementary metal-oxide-semiconductor) SOI (Silicon on insulator) transistors and lateral diodes used as temperature and thermal sensors. DC analysis of the measured sensors and the experimental results in a broad (300 K up to 550 K) temperature range are presented. It is shown that both sensors require small chip area, have low power consumption, and exhibit linearity and high sensitivity over the entire temperature range. However, the diode's sensitivity to temperature variations in CMOS-SOI technology is highly dependent on the diode's perimeter; hence, a careful calibration for each fabrication process is needed. In contrast, the short thermal time constant of the electrons in the transistor's channel enables measuring the instantaneous heating of the channel and to determine the local true temperature of the transistor. This allows accurate "on-line" temperature sensing while no additional calibration is needed. In addition, the noise measurements indicate that the diode's small area and perimeter causes a high 1/ f noise in all measured bias currents. This is a severe drawback for the sensor accuracy when using the sensor as a thermal sensor; hence, CMOS-SOI transistors are a better choice for temperature sensing.

3-Axis Fully-Integrated Capacitive Tactile Sensor with Flip-Bonded CMOS on LTCC Interposer †

PubMed Central

Asano, Sho; Nakayama, Takahiro; Hata, Yoshiyuki; Tanaka, Shuji

2017-01-01

This paper reports a 3-axis fully integrated differential capacitive tactile sensor surface-mountable on a bus line. The sensor integrates a flip-bonded complementary metal-oxide semiconductor (CMOS) with capacitive sensing circuits on a low temperature cofired ceramic (LTCC) interposer with Au through vias by Au-Au thermo-compression bonding. The CMOS circuit and bonding pads on the sensor backside were electrically connected through Au bumps and the LTCC interposer, and the differential capacitive gap was formed by an Au sealing frame. A diaphragm for sensing 3-axis force was formed in the CMOS substrate. The dimensions of the completed sensor are 2.5 mm in width, 2.5 mm in length, and 0.66 mm in thickness. The fabricated sensor output coded 3-axis capacitive sensing data according to applied 3-axis force by three-dimensional (3D)-printed pins. The measured sensitivity was as high as over 34 Count/mN for normal force and 14 to 15 Count/mN for shear force with small noise, which corresponds to less than 1 mN. The hysteresis and the average cross-sensitivity were also found to be less than 2% full scale and 11%, respectively. PMID:29068429

Fully-Coupled Thermo-Electrical Modeling and Simulation of Transition Metal Oxide Memristors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mamaluy, Denis; Gao, Xujiao; Tierney, Brian David

2016-11-01

Transition metal oxide (TMO) memristors have recently attracted special attention from the semiconductor industry and academia. Memristors are one of the strongest candidates to replace flash memory, and possibly DRAM and SRAM in the near future. Moreover, memristors have a high potential to enable beyond-CMOS technology advances in novel architectures for high performance computing (HPC). The utility of memristors has been demonstrated in reprogrammable logic (cross-bar switches), brain-inspired computing and in non-CMOS complementary logic. Indeed, the potential use of memristors as logic devices is especially important considering the inevitable end of CMOS technology scaling that is anticipated by 2025. Inmore » order to aid the on-going Sandia memristor fabrication effort with a memristor design tool and establish a clear physical picture of resistance switching in TMO memristors, we have created and validated with experimental data a simulation tool we name the Memristor Charge Transport (MCT) Simulator.« less

TID Simulation of Advanced CMOS Devices for Space Applications

NASA Astrophysics Data System (ADS)

Sajid, Muhammad

2016-07-01

This paper focuses on Total Ionizing Dose (TID) effects caused by accumulation of charges at silicon dioxide, substrate/silicon dioxide interface, Shallow Trench Isolation (STI) for scaled CMOS bulk devices as well as at Buried Oxide (BOX) layer in devices based on Silicon-On-Insulator (SOI) technology to be operated in space radiation environment. The radiation induced leakage current and corresponding density/concentration electrons in leakage current path was presented/depicted for 180nm, 130nm and 65nm NMOS, PMOS transistors based on CMOS bulk as well as SOI process technologies on-board LEO and GEO satellites. On the basis of simulation results, the TID robustness analysis for advanced deep sub-micron technologies was accomplished up to 500 Krad. The correlation between the impact of technology scaling and magnitude of leakage current with corresponding total dose was established utilizing Visual TCAD Genius program.

Design and standalone characterisation of a capacitively coupled HV-CMOS sensor chip for the CLIC vertex detector

NASA Astrophysics Data System (ADS)

Kremastiotis, I.; Ballabriga, R.; Campbell, M.; Dannheim, D.; Fiergolski, A.; Hynds, D.; Kulis, S.; Peric, I.

2017-09-01

The concept of capacitive coupling between sensors and readout chips is under study for the vertex detector at the proposed high-energy CLIC electron positron collider. The CLICpix Capacitively Coupled Pixel Detector (C3PD) is an active High-Voltage CMOS sensor, designed to be capacitively coupled to the CLICpix2 readout chip. The chip is implemented in a commercial 180 nm HV-CMOS process and contains a matrix of 128×128 square pixels with 25μm pitch. First prototypes have been produced with a standard resistivity of ~20 Ωcm for the substrate and tested in standalone mode. The results show a rise time of ~20 ns, charge gain of 190 mV/ke- and ~40 e- RMS noise for a power consumption of 4.8μW/pixel. The main design aspects, as well as standalone measurement results, are presented.

Break-before-make CMOS inverter for power-efficient delay implementation.

PubMed

Puhan, Janez; Raič, Dušan; Tuma, Tadej; Bűrmen, Árpád

2014-01-01

A modified static CMOS inverter with two inputs and two outputs is proposed to reduce short-circuit current in order to increment delay and reduce power overhead where slow operation is required. The circuit is based on bidirectional delay element connected in series with the PMOS and NMOS switching transistors. It provides differences in the dynamic response so that the direct-path current in the next stage is reduced. The switching transistors are never ON at the same time. Characteristics of various delay element implementations are presented and verified by circuit simulations. Global optimization procedure is used to obtain the most power-efficient transistor sizing. The performance of the modified CMOS inverter chain is compared to standard implementation for various delays. The energy (charge) per delay is reduced up to 40%. The use of the proposed delay element is demonstrated by implementing a low-power delay line and a leading-edge detector cell.

Break-before-Make CMOS Inverter for Power-Efficient Delay Implementation

PubMed Central

Raič, Dušan

2014-01-01

A modified static CMOS inverter with two inputs and two outputs is proposed to reduce short-circuit current in order to increment delay and reduce power overhead where slow operation is required. The circuit is based on bidirectional delay element connected in series with the PMOS and NMOS switching transistors. It provides differences in the dynamic response so that the direct-path current in the next stage is reduced. The switching transistors are never ON at the same time. Characteristics of various delay element implementations are presented and verified by circuit simulations. Global optimization procedure is used to obtain the most power-efficient transistor sizing. The performance of the modified CMOS inverter chain is compared to standard implementation for various delays. The energy (charge) per delay is reduced up to 40%. The use of the proposed delay element is demonstrated by implementing a low-power delay line and a leading-edge detector cell. PMID:25538951

Electron-induced single event upsets in 28 nm and 45 nm bulk SRAMs

DOE PAGES

Trippe, J. M.; Reed, R. A.; Austin, R. A.; ...

2015-12-01

In this study, we present experimental evidence of single electron-induced upsets in commercial 28 nm and 45 nm CMOS SRAMs from a monoenergetic electron beam. Upsets were observed in both technology nodes when the SRAM was operated in a low power state. The experimental cross section depends strongly on both bias and technology node feature size, consistent with previous work in which SRAMs were irradiated with low energy muons and protons. Accompanying simulations demonstrate that δ-rays produced by the primary electrons are responsible for the observed upsets. Additional simulations predict the on-orbit event rates for various Earth and Jovian environmentsmore » for a set of sensitive volumes representative of current technology nodes. The electron contribution to the total upset rate for Earth environments is significant for critical charges as high as 0.2 fC. This value is comparable to that of sub-22 nm bulk SRAMs. Similarly, for the Jovian environment, the electron-induced upset rate is larger than the proton-induced upset rate for critical charges as high as 0.3 fC.« less

A zirconium dioxide ammonia microsensor integrated with a readout circuit manufactured using the 0.18 μm CMOS process.

PubMed

Lin, Guan-Ming; Dai, Ching-Liang; Yang, Ming-Zhi

2013-03-15

The study presents an ammonia microsensor integrated with a readout circuit on-a-chip fabricated using the commercial 0.18 μm complementary metal oxide semiconductor (CMOS) process. The integrated sensor chip consists of a heater, an ammonia sensor and a readout circuit. The ammonia sensor is constructed by a sensitive film and the interdigitated electrodes. The sensitive film is zirconium dioxide that is coated on the interdigitated electrodes. The heater is used to provide a working temperature to the sensitive film. A post-process is employed to remove the sacrificial layer and to coat zirconium dioxide on the sensor. When the sensitive film adsorbs or desorbs ammonia gas, the sensor produces a change in resistance. The readout circuit converts the resistance variation of the sensor into the output voltage. The experiments show that the integrated ammonia sensor has a sensitivity of 4.1 mV/ppm.

Characterization of various Si-photodiode junction combinations and layout specialities in 0.18µm CMOS and HV-CMOS technologies

NASA Astrophysics Data System (ADS)

Jonak-Auer, I.; Synooka, O.; Kraxner, A.; Roger, F.

2017-12-01

With the ongoing miniaturization of CMOS technologies the need for integrated optical sensors on smaller scale CMOS nodes arises. In this paper we report on the development and implementation of different optical sensor concepts in high performance 0.18µm CMOS and high voltage (HV) CMOS technologies on three different substrate materials. The integration process is such that complete modularity of the CMOS processes remains untouched and no additional masks or ion implantation steps are necessary for the sensor integration. The investigated processes support 1.8V and 3V standard CMOS functionality as well as HV transistors capable of operating voltages of 20V and 50V. These processes intrinsically offer a wide variety of junction combinations, which can be exploited for optical sensing purposes. The availability of junction depths from submicron to several microns enables the selection of spectral range from blue to infrared wavelengths. By appropriate layout the contributions of photo-generated carriers outside the target spectral range can be kept to a minimum. Furthermore by making use of other features intrinsically available in 0.18µm CMOS and HV-CMOS processes dark current rates of optoelectronic devices can be minimized. We present TCAD simulations as well as spectral responsivity, dark current and capacitance data measured for various photodiode layouts and the influence of different EPI and Bulk substrate materials thereon. We show examples of spectral responsivity of junction combinations optimized for peak sensitivity in the ranges of 400-500nm, 550-650nm and 700-900nm. Appropriate junction combination enables good spectral resolution for colour sensing applications even without any additional filter implementation. We also show that by appropriate use of shallow trenches dark current values of photodiodes can further be reduced.

The Speedster-EXD- A New Event-Driven Hybrid CMOS X-ray Detector

NASA Astrophysics Data System (ADS)

Griffith, Christopher V.; Falcone, Abraham D.; Prieskorn, Zachary R.; Burrows, David N.

2016-01-01

The Speedster-EXD is a new 64×64 pixel, 40-μm pixel pitch, 100-μm depletion depth hybrid CMOS x-ray detector with the capability of reading out only those pixels containing event charge, thus enabling fast effective frame rates. A global charge threshold can be specified, and pixels containing charge above this threshold are flagged and read out. The Speedster detector has also been designed with other advanced in-pixel features to improve performance, including a low-noise, high-gain capacitive transimpedance amplifier that eliminates interpixel capacitance crosstalk (IPC), and in-pixel correlated double sampling subtraction to reduce reset noise. We measure the best energy resolution on the Speedster-EXD detector to be 206 eV (3.5%) at 5.89 keV and 172 eV (10.0%) at 1.49 keV. The average IPC to the four adjacent pixels is measured to be 0.25%±0.2% (i.e., consistent with zero). The pixel-to-pixel gain variation is measured to be 0.80%±0.03%, and a Monte Carlo simulation is applied to better characterize the contributions to the energy resolution.

Design of a Multi-Channel Front-End Readout ASIC With Low Noise and Large Dynamic Input Range for APD-Based PET Imaging

NASA Astrophysics Data System (ADS)

Fang, X. C.; Hu-Guo, Ch.; Ollivier-Henry, N.; Brasse, D.; Hu, Y.

2010-06-01

This paper represents the design of a low-noise, wide band multi-channel readout integrated circuit (IC) used as front end readout electronics of avalanche photo diodes (APD) dedicated to a small animal positron emission tomography (PET) system. The first ten-channel prototype chip (APD-Chip) of the analog parts has been designed and fabricated in a 0.35 μm CMOS process. Every channel of the APD_Chip includes a charge-sensitive preamplifier (CSA), a CR-(RC)2 shaper, and an analog buffer. In a channel, the CSA reads charge signals (10 bits dynamic range) from an APD array having 10 pF of capacitance per pixel. A linearized degenerated differential pair which ensures high linearity in all dynamical range is used as the high feedback resistor for preventing pile up of signals. The designed CSA has the capability of compensating automatically up to 200 nA leakage current from the detector. The CR-(RC)2 shaper filters and shapes the output signal of the CSA. An equivalent input noise charge obtained from test is 275 e -+ 10 e-/pF. In this paper the prototype is presented for both its theoretical analysis and its test results.

A Comparative Study of Heavy Ion and Proton Induced Bit Error Sensitivity and Complex Burst Error Modes in Commercially Available High Speed SiGe BiCMOS

NASA Technical Reports Server (NTRS)

Marshall, Paul; Carts, Marty; Campbell, Art; Reed, Robert; Ladbury, Ray; Seidleck, Christina; Currie, Steve; Riggs, Pam; Fritz, Karl; Randall, Barb

2004-01-01

A viewgraph presentation that reviews recent SiGe bit error test data for different commercially available high speed SiGe BiCMOS chips that were subjected to various levels of heavy ion and proton radiation. Results for the tested chips at different operating speeds are displayed in line graphs.

Intraoperative colon mucosal oxygen saturation during aortic surgery.

PubMed

Lee, Eugene S; Bass, Arie; Arko, Frank R; Heikkinen, Maarit; Harris, E John; Zarins, Christopher K; van der Starre, Pieter; Olcott, Cornelius

2006-11-01

Colonic ischemia after aortic reconstruction is a devastating complication with high mortality rates. This study evaluates whether Colon Mucosal Oxygen Saturation (CMOS) correlates with colon ischemia during aortic surgery. Aortic reconstruction was performed in 25 patients, using a spectrophotometer probe that was inserted in each patient's rectum before the surgical procedure. Continuous CMOS, buccal mucosal oxygen saturation, systemic mean arterial pressure, heart rate, pulse oximetry, and pivotal intra-operative events were collected. Endovascular aneurysm repair (EVAR) was performed in 20 and open repair in 5 patients with a mean age of 75 +/- 10 (+/-SE) years. CMOS reliably decreased in EVAR from a baseline of 56% +/- 8% to 26 +/- 17% (P < 0.0001) during infrarenal aortic balloon occlusion and femoral arterial sheath placement. CMOS similarly decreased during open repair from 56% +/- 9% to 15 +/- 19% (P < 0.0001) when the infrarenal aorta and iliac arteries were clamped. When aortic circulation was restored in both EVAR and open surgery, CMOS returned to baseline values 56.5 +/- 10% (P = 0.81). Mean recovery time in CMOS after an aortic intervention was 6.4 +/- 3.3 min. Simultaneous buccal mucosal oxygen saturation was stable (82% +/- 6%) during aortic manipulation but would fall significantly during active bleeding. There were no device related CMOS measurement complications. Intra-operative CMOS is a sensitive measure of colon ischemia where intraoperative events correlated well with changes in mucosal oxygen saturation. Transient changes demonstrate no problem. However, persistently low CMOS suggests colon ischemia, thus providing an opportunity to revascularize the inferior mesenteric artery or hypogastric arteries to prevent colon infarction.

Fabrication and characterization of polyaniline/PVA humidity microsensors.

PubMed

Yang, Ming-Zhi; Dai, Ching-Liang; Lin, Wei-Yi

2011-01-01

This study presents the fabrication and characterization of a humidity microsensor that consists of interdigitated electrodes and a sensitive film. The area of the humidity microsensor is about 2 mm(2). The sensitive film is polyaniline doping polyvinyl alcohol (PVA) that is prepared by the sol-gel method, and the film has nanofiber and porous structures that help increase the sensing reaction. The commercial 0.35 μm Complimentary Metal Oxide Semiconductor (CMOS) process is used to fabricate the humidity microsensor. The sensor needs a post-CMOS process to etch the sacrificial layer and to coat the sensitive film on the interdigitated electrodes. The sensor produces a change in resistance as the polyaniline/PVA film absorbs or desorbs vapor. Experimental results show that the sensitivity of the humidity sensor is about 12.6 kΩ/%RH at 25 °C.

Analysis of multiple cell upset sensitivity in bulk CMOS SRAM after neutron irradiation

NASA Astrophysics Data System (ADS)

Pan, Xiaoyu; Guo, Hongxia; Luo, Yinhong; Zhang, Fengqi; Ding, Lili

2018-03-01

In our previous studies, we have proved that neutron irradiation can decrease the single event latch-up (SEL) sensitivity of CMOS SRAM. And one of the key contributions to the multiple cell upset (MCU) is the parasitic bipolar amplification, it bring us to study the impact of neutron irradiation on the SRAM’s MCU sensitivity. After the neutron experiment, we test the devices’ function and electrical parameters. Then, we use the heavy ion fluence to examine the changes on the devices’ MCU sensitivity pre- and post-neutron-irradiation. Unfortunately, neutron irradiation makes the MCU phenomenon worse. Finally, we use the electric static discharge (ESD) testing technology to deduce the experimental results and find that the changes on the WPM region take the lead rather than the changes on the parasitic bipolar amplification for the 90 nm process.

1T Pixel Using Floating-Body MOSFET for CMOS Image Sensors.

PubMed

Lu, Guo-Neng; Tournier, Arnaud; Roy, François; Deschamps, Benoît

2009-01-01

We present a single-transistor pixel for CMOS image sensors (CIS). It is a floating-body MOSFET structure, which is used as photo-sensing device and source-follower transistor, and can be controlled to store and evacuate charges. Our investigation into this 1T pixel structure includes modeling to obtain analytical description of conversion gain. Model validation has been done by comparing theoretical predictions and experimental results. On the other hand, the 1T pixel structure has been implemented in different configurations, including rectangular-gate and ring-gate designs, and variations of oxidation parameters for the fabrication process. The pixel characteristics are presented and discussed.

Test beam measurement of the first prototype of the fast silicon pixel monolithic detector for the TT-PET project

NASA Astrophysics Data System (ADS)

Paolozzi, L.; Bandi, Y.; Benoit, M.; Cardarelli, R.; Débieux, S.; Forshaw, D.; Hayakawa, D.; Iacobucci, G.; Kaynak, M.; Miucci, A.; Nessi, M.; Ratib, O.; Ripiccini, E.; Rücker, H.; Valerio, P.; Weber, M.

2018-04-01

The TT-PET collaboration is developing a PET scanner for small animals with 30 ps time-of-flight resolution and sub-millimetre 3D detection granularity. The sensitive element of the scanner is a monolithic silicon pixel detector based on state-of-the-art SiGe BiCMOS technology. The first ASIC prototype for the TT-PET was produced and tested in the laboratory and with minimum ionizing particles. The electronics exhibit an equivalent noise charge below 600 e‑ RMS and a pulse rise time of less than 2 ns , in accordance with the simulations. The pixels with a capacitance of 0.8 pF were measured to have a detection efficiency greater than 99% and, although in the absence of the post-processing, a time resolution of approximately 200 ps .

CMOS active pixel sensors response to low energy light ions

NASA Astrophysics Data System (ADS)

Spiriti, E.; Finck, Ch.; Baudot, J.; Divay, C.; Juliani, D.; Labalme, M.; Rousseau, M.; Salvador, S.; Vanstalle, M.; Agodi, C.; Cuttone, G.; De Napoli, M.; Romano, F.

2017-12-01

Recently CMOS active pixel sensors have been used in Hadrontherapy ions fragmentation cross section measurements. Their main goal is to reconstruct tracks generated by the non interacting primary ions or by the produced fragments. In this framework the sensors, unexpectedly, demonstrated the possibility to obtain also some informations that could contribute to the ion type identification. The present analysis shows a clear dependency in charge and number of pixels per cluster (pixels with a collected amount of charge above a given threshold) with both fragment atomic number Z and energy loss in the sensor. This information, in the FIRST (F ragmentation of I ons R elevant for S pace and T herapy) experiment, has been used in the overall particle identification analysis algorithm. The aim of this paper is to present the data analysis and the obtained results. An empirical model was developed, in this paper, that reproduce the cluster size as function of the deposited energy in the sensor.

Analysis of Preoperative Airway Examination with the CMOS Video Rhino-laryngoscope.

PubMed

Tsukamoto, Masanori; Hitosugi, Takashi; Yokoyama, Takeshi

2017-05-01

Endoscopy is one of the most useful clinical techniques in difficult airway management Comparing with the fibroptic endoscope, this compact device is easy to operate and can provide the clear image. In this study, we investigated its usefulness in the preoperative examination of endoscopy. Patients undergoing oral maxillofacial surgery were enrolled in this study. We performed preoperative airway examination by electronic endoscope (The CMOS video rhino-laryngoscope, KARL STORZ Endoscopy Japan, Tokyo). The system is composed of a videoendoscope, a compact video processor and a video recorder. In addition, the endoscope has a small color charge coupled device (CMOS) chip built into the tip of the endoscope. The outer diameter of the tip of this scope is 3.7 mm. In this study, electronic endoscope was used for preoperative airway examination in 7 patients. The preoperative airway examination with electronic endoscope was performed successfully in all the patients except one patient The patient had the symptoms such as nausea and vomiting at the examination. We could perform preoperative airway examination with excellent visualization and convenient recording of video sequence images with the CMOS video rhino-laryngoscope. It might be a especially useful device for the patients of difficult airways.

A Novel Offset Cancellation Based on Parasitic-Insensitive Switched-Capacitor Sensing Circuit for the Out-of-Plane Single-Gimbaled Decoupled CMOS-MEMS Gyroscope

PubMed Central

Chang, Ming-Hui; Huang, Han-Pang

2013-01-01

This paper presents a novel parasitic-insensitive switched-capacitor (PISC) sensing circuit design in order to obtain high sensitivity and ultra linearity and reduce the parasitic effect for the out-of-plane single-gimbaled decoupled CMOS-MEMS gyroscope (SGDG). According to the simulation results, the proposed PISC circuit has better sensitivity and high linearity in a wide dynamic range. Experimental results also show a better performance. In addition, the PISC circuit can use signal processing to cancel the offset and noise. Thus, this circuit is very suitable for gyroscope measurement. PMID:23493122

Error analysis and prevention of cosmic ion-induced soft errors in static CMOS RAMs

NASA Astrophysics Data System (ADS)

Diehl, S. E.; Ochoa, A., Jr.; Dressendorfer, P. V.; Koga, P.; Kolasinski, W. A.

1982-12-01

Cosmic ray interactions with memory cells are known to cause temporary, random, bit errors in some designs. The sensitivity of polysilicon gate CMOS static RAM designs to logic upset by impinging ions has been studied using computer simulations and experimental heavy ion bombardment. Results of the simulations are confirmed by experimental upset cross-section data. Analytical models have been extended to determine and evaluate design modifications which reduce memory cell sensitivity to cosmic ions. A simple design modification, the addition of decoupling resistance in the feedback path, is shown to produce static RAMs immune to cosmic ray-induced bit errors.

A robust color signal processing with wide dynamic range WRGB CMOS image sensor

NASA Astrophysics Data System (ADS)

Kawada, Shun; Kuroda, Rihito; Sugawa, Shigetoshi

2011-01-01

We have developed a robust color reproduction methodology by a simple calculation with a new color matrix using the formerly developed wide dynamic range WRGB lateral overflow integration capacitor (LOFIC) CMOS image sensor. The image sensor was fabricated through a 0.18 μm CMOS technology and has a 45 degrees oblique pixel array, the 4.2 μm effective pixel pitch and the W pixels. A W pixel was formed by replacing one of the two G pixels in the Bayer RGB color filter. The W pixel has a high sensitivity through the visible light waveband. An emerald green and yellow (EGY) signal is generated from the difference between the W signal and the sum of RGB signals. This EGY signal mainly includes emerald green and yellow lights. These colors are difficult to be reproduced accurately by the conventional simple linear matrix because their wave lengths are in the valleys of the spectral sensitivity characteristics of the RGB pixels. A new linear matrix based on the EGY-RGB signal was developed. Using this simple matrix, a highly accurate color processing with a large margin to the sensitivity fluctuation and noise has been achieved.

Large CMOS imager using hadamard transform based multiplexing

NASA Technical Reports Server (NTRS)

Karasik, Boris S.; Wadsworth, Mark V.

2005-01-01

We have developed a concept design for a large (10k x 10k) CMOS imaging array whose elements are grouped in small subarrays with N pixels in each. The subarrays are code-division multiplexed using the Hadamard Transform (HT) based encoding. The Hadamard code improves the signal-to-noise (SNR) ratio to the reference of the read-out amplifier by a factor of N^1/2. This way of grouping pixels reduces the number of hybridization bumps by N. A single chip layout has been designed and the architecture of the imager has been developed to accommodate the HT base multiplexing into the existing CMOS technology. The imager architecture allows for a trade-off between the speed and the sensitivity. The envisioned imager would operate at a speed >100 fps with the pixel noise < 20 e-. The power dissipation would be 100 pW/pixe1. The combination of the large format, high speed, high sensitivity and low power dissipation can be very attractive for space reconnaissance applications.

Miniature atomic scalar magnetometer for space based on the rubidium isotope 87Rb.

PubMed

Korth, Haje; Strohbehn, Kim; Tejada, Francisco; Andreou, Andreas G; Kitching, John; Knappe, Svenja; Lehtonen, S John; London, Shaughn M; Kafel, Matiwos

2016-08-01

A miniature atomic scalar magnetometer based on the rubidium isotope 87 Rb was developed for operation in space. The instrument design implements both M x and M z mode operation and leverages a novel microelectromechanical system (MEMS) fabricated vapor cell and a custom silicon-on-sapphire (SOS) complementary metal-oxide-semiconductor (CMOS) integrated circuit. The vapor cell has a volume of only 1 mm 3 so that it can be efficiently heated to its operating temperature by a specially designed, low-magnetic-field-generating resistive heater implemented in multiple metal layers of the transparent sapphire substrate of the SOS-CMOS chips. The SOS-CMOS chip also hosts the Helmholtz coil and associated circuitry to stimulate the magnetically sensitive atomic resonance and temperature sensors. The prototype instrument has a total mass of fewer than 500 g and uses less than 1 W of power, while maintaining a sensitivity of 15 pT/√Hz at 1 Hz, comparable to present state-of-the-art absolute magnetometers.

A CMOS-Compatible Poly-Si Nanowire Device with Hybrid Sensor/Memory Characteristics for System-on-Chip Applications

PubMed Central

Chen, Min-Cheng; Chen, Hao-Yu; Lin, Chia-Yi; Chien, Chao-Hsin; Hsieh, Tsung-Fan; Horng, Jim-Tong; Qiu, Jian-Tai; Huang, Chien-Chao; Ho, Chia-Hua; Yang, Fu-Liang

2012-01-01

This paper reports a versatile nano-sensor technology using “top-down” poly-silicon nanowire field-effect transistors (FETs) in the conventional Complementary Metal-Oxide Semiconductor (CMOS)-compatible semiconductor process. The nanowire manufacturing technique reduced nanowire width scaling to 50 nm without use of extra lithography equipment, and exhibited superior device uniformity. These n type polysilicon nanowire FETs have positive pH sensitivity (100 mV/pH) and sensitive deoxyribonucleic acid (DNA) detection ability (100 pM) at normal system operation voltages. Specially designed oxide-nitride-oxide buried oxide nanowire realizes an electrically Vth-adjustable sensor to compensate device variation. These nanowire FETs also enable non-volatile memory application for a large and steady Vth adjustment window (>2 V Programming/Erasing window). The CMOS-compatible manufacturing technique of polysilicon nanowire FETs offers a possible solution for commercial System-on-Chip biosensor application, which enables portable physiology monitoring and in situ recording. PMID:22666012

A CMOS micromachined capacitive tactile sensor with integrated readout circuits and compensation of process variations.

PubMed

Tsai, Tsung-Heng; Tsai, Hao-Cheng; Wu, Tien-Keng

2014-10-01

This paper presents a capacitive tactile sensor fabricated in a standard CMOS process. Both of the sensor and readout circuits are integrated on a single chip by a TSMC 0.35 μm CMOS MEMS technology. In order to improve the sensitivity, a T-shaped protrusion is proposed and implemented. This sensor comprises the metal layer and the dielectric layer without extra thin film deposition, and can be completed with few post-processing steps. By a nano-indenter, the measured spring constant of the T-shaped structure is 2.19 kNewton/m. Fully differential correlated double sampling capacitor-to-voltage converter (CDS-CVC) and reference capacitor correction are utilized to compensate process variations and improve the accuracy of the readout circuits. The measured displacement-to-voltage transductance is 7.15 mV/nm, and the sensitivity is 3.26 mV/μNewton. The overall power dissipation is 132.8 μW.

Nanometric Integrated Temperature and Thermal Sensors in CMOS-SOI Technology

PubMed Central

Malits, Maria; Nemirovsky, Yael

2017-01-01

This paper reviews and compares the thermal and noise characterization of CMOS (complementary metal-oxide-semiconductor) SOI (Silicon on insulator) transistors and lateral diodes used as temperature and thermal sensors. DC analysis of the measured sensors and the experimental results in a broad (300 K up to 550 K) temperature range are presented. It is shown that both sensors require small chip area, have low power consumption, and exhibit linearity and high sensitivity over the entire temperature range. However, the diode’s sensitivity to temperature variations in CMOS-SOI technology is highly dependent on the diode’s perimeter; hence, a careful calibration for each fabrication process is needed. In contrast, the short thermal time constant of the electrons in the transistor’s channel enables measuring the instantaneous heating of the channel and to determine the local true temperature of the transistor. This allows accurate “on-line” temperature sensing while no additional calibration is needed. In addition, the noise measurements indicate that the diode’s small area and perimeter causes a high 1/f noise in all measured bias currents. This is a severe drawback for the sensor accuracy when using the sensor as a thermal sensor; hence, CMOS-SOI transistors are a better choice for temperature sensing. PMID:28758932

Image stacking approach to increase sensitivity of fluorescence detection using a low cost complementary metal-oxide-semiconductor (CMOS) webcam.

PubMed

Balsam, Joshua; Bruck, Hugh Alan; Kostov, Yordan; Rasooly, Avraham

2012-01-01

Optical technologies are important for biological analysis. Current biomedical optical analyses rely on high-cost, high-sensitivity optical detectors such as photomultipliers, avalanched photodiodes or cooled CCD cameras. In contrast, Webcams, mobile phones and other popular consumer electronics use lower-sensitivity, lower-cost optical components such as photodiodes or CMOS sensors. In order for consumer electronics devices, such as webcams, to be useful for biomedical analysis, they must have increased sensitivity. We combined two strategies to increase the sensitivity of CMOS-based fluorescence detector. We captured hundreds of low sensitivity images using a Webcam in video mode, instead of a single image typically used in cooled CCD devices.We then used a computational approach consisting of an image stacking algorithm to remove the noise by combining all of the images into a single image. While video mode is widely used for dynamic scene imaging (e.g. movies or time-lapse photography), it is not used to capture a single static image, which removes noise and increases sensitivity by more than thirty fold. The portable, battery-operated Webcam-based fluorometer system developed here consists of five modules: (1) a low cost CMOS Webcam to monitor light emission, (2) a plate to perform assays, (3) filters and multi-wavelength LED illuminator for fluorophore excitation, (4) a portable computer to acquire and analyze images, and (5) image stacking software for image enhancement. The samples consisted of various concentrations of fluorescein, ranging from 30 μM to 1000 μM, in a 36-well miniature plate. In the single frame mode, the fluorometer's limit-of-detection (LOD) for fluorescein is ∼1000 μM, which is relatively insensitive. However, when used in video mode combined with image stacking enhancement, the LOD is dramatically reduced to 30 μM, sensitivity which is similar to that of state-of-the-art ELISA plate photomultiplier-based readers. Numerous medical diagnostics assays rely on optical and fluorescence readers. Our novel combination of detection technologies, which is new to biodetection may enable the development of new low cost optical detectors based on an inexpensive Webcam (<$10). It has the potential to form the basis for high sensitivity, low cost medical diagnostics in resource-poor settings.

Image stacking approach to increase sensitivity of fluorescence detection using a low cost complementary metal-oxide-semiconductor (CMOS) webcam

PubMed Central

Balsam, Joshua; Bruck, Hugh Alan; Kostov, Yordan; Rasooly, Avraham

2013-01-01

Optical technologies are important for biological analysis. Current biomedical optical analyses rely on high-cost, high-sensitivity optical detectors such as photomultipliers, avalanched photodiodes or cooled CCD cameras. In contrast, Webcams, mobile phones and other popular consumer electronics use lower-sensitivity, lower-cost optical components such as photodiodes or CMOS sensors. In order for consumer electronics devices, such as webcams, to be useful for biomedical analysis, they must have increased sensitivity. We combined two strategies to increase the sensitivity of CMOS-based fluorescence detector. We captured hundreds of low sensitivity images using a Webcam in video mode, instead of a single image typically used in cooled CCD devices.We then used a computational approach consisting of an image stacking algorithm to remove the noise by combining all of the images into a single image. While video mode is widely used for dynamic scene imaging (e.g. movies or time-lapse photography), it is not used to capture a single static image, which removes noise and increases sensitivity by more than thirty fold. The portable, battery-operated Webcam-based fluorometer system developed here consists of five modules: (1) a low cost CMOS Webcam to monitor light emission, (2) a plate to perform assays, (3) filters and multi-wavelength LED illuminator for fluorophore excitation, (4) a portable computer to acquire and analyze images, and (5) image stacking software for image enhancement. The samples consisted of various concentrations of fluorescein, ranging from 30 μM to 1000 μM, in a 36-well miniature plate. In the single frame mode, the fluorometer's limit-of-detection (LOD) for fluorescein is ∼1000 μM, which is relatively insensitive. However, when used in video mode combined with image stacking enhancement, the LOD is dramatically reduced to 30 μM, sensitivity which is similar to that of state-of-the-art ELISA plate photomultiplier-based readers. Numerous medical diagnostics assays rely on optical and fluorescence readers. Our novel combination of detection technologies, which is new to biodetection may enable the development of new low cost optical detectors based on an inexpensive Webcam (<$10). It has the potential to form the basis for high sensitivity, low cost medical diagnostics in resource-poor settings. PMID:23990697

Implementation of the CMOS MEMS Condenser Microphone with Corrugated Metal Diaphragm and Silicon Back-Plate

PubMed Central

Huang, Chien-Hsin; Lee, Chien-Hsing; Hsieh, Tsung-Min; Tsao, Li-Chi; Wu, Shaoyi; Liou, Jhyy-Cheng; Wang, Ming-Yi; Chen, Li-Che; Yip, Ming-Chuen; Fang, Weileun

2011-01-01

This study reports a CMOS-MEMS condenser microphone implemented using the standard thin film stacking of 0.35 μm UMC CMOS 3.3/5.0 V logic process, and followed by post-CMOS micromachining steps without introducing any special materials. The corrugated diaphragm for the microphone is designed and implemented using the metal layer to reduce the influence of thin film residual stresses. Moreover, a silicon substrate is employed to increase the stiffness of the back-plate. Measurements show the sensitivity of microphone is −42 ± 3 dBV/Pa at 1 kHz (the reference sound-level is 94 dB) under 6 V pumping voltage, the frequency response is 100 Hz–10 kHz, and the S/N ratio >55 dB. It also has low power consumption of less than 200 μA, and low distortion of less than 1% (referred to 100 dB). PMID:22163953

Toward CMOS image sensor based glucose monitoring.

PubMed

Devadhasan, Jasmine Pramila; Kim, Sanghyo

2012-09-07

Complementary metal oxide semiconductor (CMOS) image sensor is a powerful tool for biosensing applications. In this present study, CMOS image sensor has been exploited for detecting glucose levels by simple photon count variation with high sensitivity. Various concentrations of glucose (100 mg dL(-1) to 1000 mg dL(-1)) were added onto a simple poly-dimethylsiloxane (PDMS) chip and the oxidation of glucose was catalyzed with the aid of an enzymatic reaction. Oxidized glucose produces a brown color with the help of chromogen during enzymatic reaction and the color density varies with the glucose concentration. Photons pass through the PDMS chip with varying color density and hit the sensor surface. Photon count was recognized by CMOS image sensor depending on the color density with respect to the glucose concentration and it was converted into digital form. By correlating the obtained digital results with glucose concentration it is possible to measure a wide range of blood glucose levels with great linearity based on CMOS image sensor and therefore this technique will promote a convenient point-of-care diagnosis.

A monolithic 640 × 512 CMOS imager with high-NIR sensitivity

NASA Astrophysics Data System (ADS)

Lauxtermann, Stefan; Fisher, John; McDougal, Michael

2014-06-01

In this paper we present first results from a backside illuminated CMOS image sensor that we fabricated on high resistivity silicon. Compared to conventional CMOS imagers, a thicker photosensitive membrane can be depleted when using silicon with low background doping concentration while maintaining low dark current and good MTF performance. The benefits of such a fully depleted silicon sensor are high quantum efficiency over a wide spectral range and a fast photo detector response. Combining these characteristics with the circuit complexity and manufacturing maturity available from a modern, mixed signal CMOS technology leads to a new type of sensor, with an unprecedented performance spectrum in a monolithic device. Our fully depleted, backside illuminated CMOS sensor was designed to operate at integration times down to 100nsec and frame rates up to 1000Hz. Noise in Integrate While Read (IWR) snapshot shutter operation for these conditions was simulated to be below 10e- at room temperature. 2×2 binning with a 4× increase in sensitivity and a maximum frame rate of 4000 Hz is supported. For application in hyperspectral imaging systems the full well capacity in each row can individually be programmed between 10ke-, 60ke- and 500ke-. On test structures we measured a room temperature dark current of 360pA/cm2 at a reverse bias of 3.3V. A peak quantum efficiency of 80% was measured with a single layer AR coating on the backside. Test images captured with the 50μm thick VGA imager between 30Hz and 90Hz frame rate show a strong response at NIR wavelengths.

An SOI CMOS-Based Multi-Sensor MEMS Chip for Fluidic Applications.

PubMed

Mansoor, Mohtashim; Haneef, Ibraheem; Akhtar, Suhail; Rafiq, Muhammad Aftab; De Luca, Andrea; Ali, Syed Zeeshan; Udrea, Florin

2016-11-04

An SOI CMOS multi-sensor MEMS chip, which can simultaneously measure temperature, pressure and flow rate, has been reported. The multi-sensor chip has been designed keeping in view the requirements of researchers interested in experimental fluid dynamics. The chip contains ten thermodiodes (temperature sensors), a piezoresistive-type pressure sensor and nine hot film-based flow rate sensors fabricated within the oxide layer of the SOI wafers. The silicon dioxide layers with embedded sensors are relieved from the substrate as membranes with the help of a single DRIE step after chip fabrication from a commercial CMOS foundry. Very dense sensor packing per unit area of the chip has been enabled by using technologies/processes like SOI, CMOS and DRIE. Independent apparatuses were used for the characterization of each sensor. With a drive current of 10 µA-0.1 µA, the thermodiodes exhibited sensitivities of 1.41 mV/°C-1.79 mV/°C in the range 20-300 °C. The sensitivity of the pressure sensor was 0.0686 mV/(V excit kPa) with a non-linearity of 0.25% between 0 and 69 kPa above ambient pressure. Packaged in a micro-channel, the flow rate sensor has a linearized sensitivity of 17.3 mV/(L/min) -0.1 in the tested range of 0-4.7 L/min. The multi-sensor chip can be used for simultaneous measurement of fluid pressure, temperature and flow rate in fluidic experiments and aerospace/automotive/biomedical/process industries.

An SOI CMOS-Based Multi-Sensor MEMS Chip for Fluidic Applications †

PubMed Central

Mansoor, Mohtashim; Haneef, Ibraheem; Akhtar, Suhail; Rafiq, Muhammad Aftab; De Luca, Andrea; Ali, Syed Zeeshan; Udrea, Florin

2016-01-01

An SOI CMOS multi-sensor MEMS chip, which can simultaneously measure temperature, pressure and flow rate, has been reported. The multi-sensor chip has been designed keeping in view the requirements of researchers interested in experimental fluid dynamics. The chip contains ten thermodiodes (temperature sensors), a piezoresistive-type pressure sensor and nine hot film-based flow rate sensors fabricated within the oxide layer of the SOI wafers. The silicon dioxide layers with embedded sensors are relieved from the substrate as membranes with the help of a single DRIE step after chip fabrication from a commercial CMOS foundry. Very dense sensor packing per unit area of the chip has been enabled by using technologies/processes like SOI, CMOS and DRIE. Independent apparatuses were used for the characterization of each sensor. With a drive current of 10 µA–0.1 µA, the thermodiodes exhibited sensitivities of 1.41 mV/°C–1.79 mV/°C in the range 20–300 °C. The sensitivity of the pressure sensor was 0.0686 mV/(Vexcit kPa) with a non-linearity of 0.25% between 0 and 69 kPa above ambient pressure. Packaged in a micro-channel, the flow rate sensor has a linearized sensitivity of 17.3 mV/(L/min)−0.1 in the tested range of 0–4.7 L/min. The multi-sensor chip can be used for simultaneous measurement of fluid pressure, temperature and flow rate in fluidic experiments and aerospace/automotive/biomedical/process industries. PMID:27827904

Low-noise low-jitter 32-pixels CMOS single-photon avalanche diodes array for single-photon counting from 300 nm to 900 nm

DOE Office of Scientific and Technical Information (OSTI.GOV)

Scarcella, Carmelo; Tosi, Alberto, E-mail: alberto.tosi@polimi.it; Villa, Federica

2013-12-15

We developed a single-photon counting multichannel detection system, based on a monolithic linear array of 32 CMOS SPADs (Complementary Metal-Oxide-Semiconductor Single-Photon Avalanche Diodes). All channels achieve a timing resolution of 100 ps (full-width at half maximum) and a photon detection efficiency of 50% at 400 nm. Dark count rate is very low even at room temperature, being about 125 counts/s for 50 μm active area diameter SPADs. Detection performance and microelectronic compactness of this CMOS SPAD array make it the best candidate for ultra-compact time-resolved spectrometers with single-photon sensitivity from 300 nm to 900 nm.

A Power-Efficient Wireless Capacitor Charging System Through an Inductive Link

PubMed Central

Lee, Hyung-Min; Ghovanloo, Maysam

2014-01-01

A power-efficient wireless capacitor charging system for inductively powered applications has been presented. A bank of capacitors can be directly charged from an ac source by generating a current through a series charge injection capacitor and a capacitor charger circuit. The fixed charging current reduces energy loss in switches, while maximizing the charging efficiency. An adaptive capacitor tuner compensates for the resonant capacitance variations during charging to keep the amplitude of the ac input voltage at its peak. We have fabricated the capacitor charging system prototype in a 0.35-μm 4-metal 2-poly standard CMOS process in 2.1 mm2 of chip area. It can charge four pairs of capacitors sequentially. While receiving 2.7-V peak ac input through a 2-MHz inductive link, the capacitor charging system can charge each pair of 1 μF capacitors up to ±2 V in 420 μs, achieving a high measured charging efficiency of 82%. PMID:24678284

A Power-Efficient Wireless Capacitor Charging System Through an Inductive Link.

PubMed

Lee, Hyung-Min; Ghovanloo, Maysam

2013-10-01

A power-efficient wireless capacitor charging system for inductively powered applications has been presented. A bank of capacitors can be directly charged from an ac source by generating a current through a series charge injection capacitor and a capacitor charger circuit. The fixed charging current reduces energy loss in switches, while maximizing the charging efficiency. An adaptive capacitor tuner compensates for the resonant capacitance variations during charging to keep the amplitude of the ac input voltage at its peak. We have fabricated the capacitor charging system prototype in a 0.35- μ m 4-metal 2-poly standard CMOS process in 2.1 mm 2 of chip area. It can charge four pairs of capacitors sequentially. While receiving 2.7-V peak ac input through a 2-MHz inductive link, the capacitor charging system can charge each pair of 1 μ F capacitors up to ±2 V in 420 μ s, achieving a high measured charging efficiency of 82%.

Recent progress and development of a speedster-EXD: a new event-triggered hybrid CMOS x-ray detector

NASA Astrophysics Data System (ADS)

Griffith, Christopher V.; Falcone, Abraham D.; Prieskorn, Zachary R.; Burrows, David N.

2015-08-01

We present the characterization of a new event-driven X-ray hybrid CMOS detector developed by Penn State University in collaboration with Teledyne Imaging Sensors. Along with its low susceptibility to radiation damage, low power consumption, and fast readout time to avoid pile-up, the Speedster-EXD has been designed with the capability to limit its readout to only those pixels containing charge, thus enabling even faster effective frame rates. The threshold for the comparator in each pixel can be set by the user so that only pixels with signal above the set threshold are read out. The Speedster-EXD hybrid CMOS detector also has two new in-pixel features that reduce noise from known noise sources: (1) a low-noise, high-gain CTIA amplifier to eliminate crosstalk from interpixel capacitance (IPC) and (2) in-pixel CDS subtraction to reduce kTC noise. We present the read noise, dark current, IPC, energy resolution, and gain variation measurements of one Speedster-EXD detector.

Investigating Degradation Mechanisms in 130 nm and 90 nm Commercial CMOS Technologies Under Extreme Radiation Conditions

NASA Astrophysics Data System (ADS)

Ratti, Lodovico; Gaioni, Luigi; Manghisoni, Massimo; Traversi, Gianluca; Pantano, Devis

2008-08-01

The purpose of this paper is to study the mechanisms underlying performance degradation in 130 nm and 90 nm commercial CMOS technologies exposed to high doses of ionizing radiation. The investigation has been mainly focused on their noise properties in view of applications to the design of low-noise, low-power analog circuits to be operated in harsh environment. Experimental data support the hypothesis that charge trapping in shallow trench isolation (STI), besides degrading the static characteristics of interdigitated NMOS transistors, also affects their noise performances in a substantial fashion. The model discussed in this paper, presented in a previous work focused on CMOS devices irradiated with a 10 Mrad(SiO2) gamma -ray dose, has been applied here also to transistors exposed to much higher (up to 100 Mrad(SiO2 )) doses of X-rays. Such a model is able to account for the extent of the observed noise degradation as a function of the device polarity, dimensions and operating point.

Micro Ethanol Sensors with a Heater Fabricated Using the Commercial 0.18 μm CMOS Process

PubMed Central

Liao, Wei-Zhen; Dai, Ching-Liang; Yang, Ming-Zhi

2013-01-01

The study investigates the fabrication and characterization of an ethanol microsensor equipped with a heater. The ethanol sensor is manufactured using the commercial 0.18 μm complementary metal oxide semiconductor (CMOS) process. The sensor consists of a sensitive film, a heater and interdigitated electrodes. The sensitive film is zinc oxide prepared by the sol-gel method, and it is coated on the interdigitated electrodes. The heater is located under the interdigitated electrodes, and it is used to supply a working temperature to the sensitive film. The sensor needs a post-processing step to remove the sacrificial oxide layer, and to coat zinc oxide on the interdigitated electrodes. When the sensitive film senses ethanol gas, the resistance of the sensor generates a change. An inverting amplifier circuit is utilized to convert the resistance variation of the sensor into the output voltage. Experiments show that the sensitivity of the ethanol sensor is 0.35 mV/ppm. PMID:24072022

Micro ethanol sensors with a heater fabricated using the commercial 0.18 μm CMOS process.

PubMed

Liao, Wei-Zhen; Dai, Ching-Liang; Yang, Ming-Zhi

2013-09-25

The study investigates the fabrication and characterization of an ethanol microsensor equipped with a heater. The ethanol sensor is manufactured using the commercial 0.18 µm complementary metal oxide semiconductor (CMOS) process. The sensor consists of a sensitive film, a heater and interdigitated electrodes. The sensitive film is zinc oxide prepared by the sol-gel method, and it is coated on the interdigitated electrodes. The heater is located under the interdigitated electrodes, and it is used to supply a working temperature to the sensitive film. The sensor needs a post-processing step to remove the sacrificial oxide layer, and to coat zinc oxide on the interdigitated electrodes. When the sensitive film senses ethanol gas, the resistance of the sensor generates a change. An inverting amplifier circuit is utilized to convert the resistance variation of the sensor into the output voltage. Experiments show that the sensitivity of the ethanol sensor is 0.35 mV/ppm.

5A Zirconium Dioxide Ammonia Microsensor Integrated with a Readout Circuit Manufactured Using the 0.18 μm CMOS Process

PubMed Central

Lin, Guan-Ming; Dai, Ching-Liang; Yang, Ming-Zhi

2013-01-01

The study presents an ammonia microsensor integrated with a readout circuit on-a-chip fabricated using the commercial 0.18 μm complementary metal oxide semiconductor (CMOS) process. The integrated sensor chip consists of a heater, an ammonia sensor and a readout circuit. The ammonia sensor is constructed by a sensitive film and the interdigitated electrodes. The sensitive film is zirconium dioxide that is coated on the interdigitated electrodes. The heater is used to provide a working temperature to the sensitive film. A post-process is employed to remove the sacrificial layer and to coat zirconium dioxide on the sensor. When the sensitive film adsorbs or desorbs ammonia gas, the sensor produces a change in resistance. The readout circuit converts the resistance variation of the sensor into the output voltage. The experiments show that the integrated ammonia sensor has a sensitivity of 4.1 mV/ppm. PMID:23503294

Radiation-hardened-by-design clocking circuits in 0.13-μm CMOS technology

NASA Astrophysics Data System (ADS)

You, Y.; Huang, D.; Chen, J.; Gong, D.; Liu, T.; Ye, J.

2014-01-01

We present a single-event-hardened phase-locked loop for frequency generation applications and a digital delay-locked loop for DDR2 memory interface applications. The PLL covers a 12.5 MHz to 500 MHz frequency range with an RMS Jitter (RJ) of 4.70-pS. The DLL operates at 267 MHz and has a phase resolution of 60-pS. Designed in 0.13-μm CMOS technology, the PLL and the DLL are hardened against SEE for charge injection of 250 fC. The PLL and the DLL consume 17 mW and 22 mW of power under a 1.5 V power supply, respectively.

Solar XUV Imaging and Non-dispersive Spectroscopy for Solar-C Enabled by Scientific CMOS APS Arrays

NASA Astrophysics Data System (ADS)

Stern, Robert A.; Lemen, J. R.; Shing, L.; Janesick, J.; Tower, J.

2009-05-01

Monolithic CMOS Advanced Pixel Sensor (APS) arrays are showing great promise as eventual replacements for the current workhorse of solar physics focal planes, the scientific CCD. CMOS APS devices have individually addressable pixels, increased radiation tolerance compared to CCDs, and require lower clock voltages, and thus lower power. However, commercially available CMOS chips, while suitable for use with intensifiers or fluorescent coatings, are generally not optimized for direct detection of EUV and X-ray photons. A high performance scientific CMOS array designed for these wavelengths will have significant new capabilities compared to CCDs, including the ability to read out small regions of the solar disk at high (sub sec) cadence, count single X-ray photons with Fano-limited energy resolution, and even operate at room temperature with good noise performance. Such capabilities will be crucial for future solar X-ray and EUV missions such as Solar-C. Sarnoff Corporation has developed scientific grade, monolithic CMOS arrays for X-ray imaging and photon counting. One prototype device, the "minimal" array, has 8 um pixels, is 15 to 25 um thick, is fabricated on high-resistivity ( 10 to 20 kohm-cm) Si wafers, and can be back-illuminated. These characteristics yield high quantum efficiency and high spatial resolution with minimal charge sharing among pixels, making it ideal for the detection of keV X-rays. When used with digital correlated double sampling, the array has demonstrated noise performance as low as 2 e, allowing single photon counting of X-rays over a range of temperatures. We report test results for this device in X-rays, and discuss the implications for future solar space missions.

CMOS-compatible spintronic devices: a review

NASA Astrophysics Data System (ADS)

Makarov, Alexander; Windbacher, Thomas; Sverdlov, Viktor; Selberherr, Siegfried

2016-11-01

For many decades CMOS devices have been successfully scaled down to achieve higher speed and increased performance of integrated circuits at lower cost. Today’s charge-based CMOS electronics encounters two major challenges: power dissipation and variability. Spintronics is a rapidly evolving research and development field, which offers a potential solution to these issues by introducing novel ‘more than Moore’ devices. Spin-based magnetoresistive random-access memory (MRAM) is already recognized as one of the most promising candidates for future universal memory. Magnetic tunnel junctions, the main elements of MRAM cells, can also be used to build logic-in-memory circuits with non-volatile storage elements on top of CMOS logic circuits, as well as versatile compact on-chip oscillators with low power consumption. We give an overview of CMOS-compatible spintronics applications. First, we present a brief introduction to the physical background considering such effects as magnetoresistance, spin-transfer torque (STT), spin Hall effect, and magnetoelectric effects. We continue with a comprehensive review of the state-of-the-art spintronic devices for memory applications (STT-MRAM, domain wall-motion MRAM, and spin-orbit torque MRAM), oscillators (spin torque oscillators and spin Hall nano-oscillators), logic (logic-in-memory, all-spin logic, and buffered magnetic logic gate grid), sensors, and random number generators. Devices with different types of resistivity switching are analyzed and compared, with their advantages highlighted and challenges revealed. CMOS-compatible spintronic devices are demonstrated beginning with predictive simulations, proceeding to their experimental confirmation and realization, and finalized by the current status of application in modern integrated systems and circuits. We conclude the review with an outlook, where we share our vision on the future applications of the prospective devices in the area.

AC signal characterization for optimization of a CMOS single-electron pump

NASA Astrophysics Data System (ADS)

Murray, Roy; Perron, Justin K.; Stewart, M. D., Jr.; Zimmerman, Neil M.

2018-02-01

Pumping single electrons at a set rate is being widely pursued as an electrical current standard. Semiconductor charge pumps have been pursued in a variety of modes, including single gate ratchet, a variety of 2-gate ratchet pumps, and 2-gate turnstiles. Whether pumping with one or two AC signals, lower error rates can result from better knowledge of the properties of the AC signal at the device. In this work, we operated a CMOS single-electron pump with a 2-gate ratchet style measurement and used the results to characterize and optimize our two AC signals. Fitting this data at various frequencies revealed both a difference in signal path length and attenuation between our two AC lines. Using this data, we corrected for the difference in signal path length and attenuation by applying an offset in both the phase and the amplitude at the signal generator. Operating the device as a turnstile while using the optimized parameters determined from the 2-gate ratchet measurement led to much flatter, more robust charge pumping plateaus. This method was useful in tuning our device up for optimal charge pumping, and may prove useful to the semiconductor quantum dot community to determine signal attenuation and path differences at the device.

Improvements of low-detection-limit filter-free fluorescence sensor developed by charge accumulation operation

NASA Astrophysics Data System (ADS)

Tanaka, Kiyotsugu; Choi, Yong Joon; Moriwaki, Yu; Hizawa, Takeshi; Iwata, Tatsuya; Dasai, Fumihiro; Kimura, Yasuyuki; Takahashi, Kazuhiro; Sawada, Kazuaki

2017-04-01

We developed a low-detection-limit filter-free fluorescence sensor by a charge accumulation technique. For charge accumulation, a floating diffusion amplifier (FDA), which included a floating diffusion capacitor, a transfer gate, and a source follower circuit, was used. To integrate CMOS circuits with the filter-free fluorescence sensor, we adopted a triple-well process to isolate transistors from the sensor on a single chip. We detected 0.1 nW fluorescence under the illumination of excitation light by 1.5 ms accumulation, which was one order of magnitude greater than that of a previous current detection sensor.

Using a Floating-Gate MOS Transistor as a Transducer in a MEMS Gas Sensing System

PubMed Central

Barranca, Mario Alfredo Reyes; Mendoza-Acevedo, Salvador; Flores-Nava, Luis M.; Avila-García, Alejandro; Vazquez-Acosta, E. N.; Moreno-Cadenas, José Antonio; Casados-Cruz, Gaspar

2010-01-01

Floating-gate MOS transistors have been widely used in diverse analog and digital applications. One of these is as a charge sensitive device in sensors for pH measurement in solutions or using gates with metals like Pd or Pt for hydrogen sensing. Efforts are being made to monolithically integrate sensors together with controlling and signal processing electronics using standard technologies. This can be achieved with the demonstrated compatibility between available CMOS technology and MEMS technology. In this paper an in-depth analysis is done regarding the reliability of floating-gate MOS transistors when charge produced by a chemical reaction between metallic oxide thin films with either reducing or oxidizing gases is present. These chemical reactions need temperatures around 200 °C or higher to take place, so thermal insulation of the sensing area must be assured for appropriate operation of the electronics at room temperature. The operation principle of the proposal here presented is confirmed by connecting the gate of a conventional MOS transistor in series with a Fe2O3 layer. It is shown that an electrochemical potential is present on the ferrite layer when reacting with propane. PMID:22163478

A low jitter all - digital phase - locked loop in 180 nm CMOS technology

NASA Astrophysics Data System (ADS)

Shumkin, O. V.; Butuzov, V. A.; Normanov, D. D.; Ivanov, P. Yu

2016-02-01

An all-digital phase locked loop (ADPLL) was implemented in 180 nm CMOS technology. The proposed ADPLL uses a digitally controlled oscillator to achieve 3 ps resolution. The pure digital phase locked loop is attractive because it is less sensitive to noise and operating conditions than its analog counterpart. The proposed ADPLL can be easily applied to different process as a soft IP block, making it very suitable for system-on-chip applications.

Binary CMOS image sensor with a gate/body-tied MOSFET-type photodetector for high-speed operation

NASA Astrophysics Data System (ADS)

Choi, Byoung-Soo; Jo, Sung-Hyun; Bae, Myunghan; Kim, Sang-Hwan; Shin, Jang-Kyoo

2016-05-01

In this paper, a binary complementary metal oxide semiconductor (CMOS) image sensor with a gate/body-tied (GBT) metal oxide semiconductor field effect transistor (MOSFET)-type photodetector is presented. The sensitivity of the GBT MOSFET-type photodetector, which was fabricated using the standard CMOS 0.35-μm process, is higher than the sensitivity of the p-n junction photodiode, because the output signal of the photodetector is amplified by the MOSFET. A binary image sensor becomes more efficient when using this photodetector. Lower power consumptions and higher speeds of operation are possible, compared to the conventional image sensors using multi-bit analog to digital converters (ADCs). The frame rate of the proposed image sensor is over 2000 frames per second, which is higher than those of the conventional CMOS image sensors. The output signal of an active pixel sensor is applied to a comparator and compared with a reference level. The 1-bit output data of the binary process is determined by this level. To obtain a video signal, the 1-bit output data is stored in the memory and is read out by horizontal scanning. The proposed chip is composed of a GBT pixel array (144 × 100), binary-process circuit, vertical scanner, horizontal scanner, and readout circuit. The operation mode can be selected from between binary mode and multi-bit mode.

Direct reading of charge multipliers with a self-triggering CMOS analog chip with 105 k pixels at 50 μm pitch

NASA Astrophysics Data System (ADS)

Bellazzini, R.; Spandre, G.; Minuti, M.; Baldini, L.; Brez, A.; Cavalca, F.; Latronico, L.; Omodei, N.; Massai, M. M.; Sgro', C.; Costa, E.; Soffitta, P.; Krummenacher, F.; de Oliveira, R.

2006-10-01

We report on a large area (15×15 mm2), high channel density (470 pixel/mm2), self-triggering CMOS analog chip that we have developed as a pixelized charge collecting electrode of a Micropattern Gas Detector. This device represents a big step forward both in terms of size and performance, and is in fact the last version of three generations of custom ASICs of increasing complexity. The top metal layer of the CMOS pixel array is patterned in a matrix of 105,600 hexagonal pixels with a 50 μm pitch. Each pixel is directly connected to the underlying full electronics chain which has been realized in the remaining five metal and single poly-silicon layers of a 0.18 μm VLSI technology. The chip, which has customizable self-triggering capabilities, also includes a signal pre-processing function for the automatic localization of the event coordinates. Thanks to these advances it is possible to significantly reduce the read-out time and the data volume by limiting the signal output only to those pixels belonging to the region of interest. In addition to the reduced read-out time and data volume, the very small pixel area and the use of a deep sub-micron CMOS technology has allowed bringing the noise down to 50 electrons ENC. Results from in depth tests of this device when coupled to a fine pitch (50 μm on a triangular pattern) Gas Electron Multiplier are presented. It was found that matching the read-out and gas amplification pitch allows getting optimal results. The experimental detector response to polarized and unpolarized X-ray radiation when working with two gas mixtures and two different photon energies is shown and the application of this detector for Astronomical X-ray Polarimetry is discussed. Results from a full Monte-Carlo simulation for several galactic and extragalactic astronomical sources are also reported.

A Review of the CMOS Buried Double Junction (BDJ) Photodetector and its Applications

PubMed Central

Feruglio, Sylvain; Lu, Guo-Neng; Garda, Patrick; Vasilescu, Gabriel

2008-01-01

A CMOS Buried Double Junction PN (BDJ) photodetector consists of two vertically-stacked photodiodes. It can be operated as a photodiode with improved performance and wavelength-sensitive response. This paper presents a review of this device and its applications. The CMOS implementation and operating principle are firstly described. This includes the description of several key aspects directly related to the device performances, such as surface reflection, photon absorption and electron-hole pair generation, photocurrent and dark current generation, etc. SPICE modelling of the detector is then presented. Next, design and process considerations are proposed in order to improve the BDJ performance. Finally, several BDJ-detector-based image sensors provide a survey of their applications. PMID:27873887

SFERA: An Integrated Circuit for the Readout of X and gamma -Ray Detectors

NASA Astrophysics Data System (ADS)

Schembari, Filippo; Quaglia, Riccardo; Bellotti, Giovanni; Fiorini, Carlo

2016-06-01

In this work we present SFERA, a low-noise fully-programmable 16 channel readout ASIC designed for both Xand y-ray spectroscopy and imaging applications. The chip is designed to process signals coming from solid-state detectors and CMOS preamplifiers. The design has been guided by the use of Silicon Drift Detectors (SDDs) and CUBE charge sensitive amplifiers (CSAs), although we consider the ASIC sufficiently versatile to be used with other types of detectors. Five different gains are implemented, namely 2800 e-, 4400 e-, 10000 e-, 14000 e- and 20000 e-, considering the input connected to a 25 fF feedback capacitance CMOS preamplifier. Filter peaking times (tP) are also programmable among 0.5, 1, 2, 3, 4 and 6 μs. Each readout channel is the cascade of a 9th order semi-Gaussian shaping-amplifier (SA) and a peak detector (PKS), followed by a dedicated pile-up rejection (PUR) digital logic. Three data multiplexing strategies are implemented: the so-called polling X, intended for high-rate X-ray applications, the polling y, for scintillation light detection and the sparse, for signals derandomization. The spectroscopic characterization has shown an energy resolution of 122.1 eV FWHM on the Mn-Ku line of an 55Fe X-ray source using a 10 mm2 SDD cooled at -35 °C at 4 μs filter peaking time. The measured resolution is 130 eV at the peaking time of 500 ns. At 1 Mcps input count rate and 500 ns peaking time, we have measured 42% of processed events at the output of the ASIC after the PUR selection. Output data can be digitized on-chip by means of an embedded 12-bit successive-approximation ADC. The effective resolution of the data converter is 10.75-bit when operated at 4.5 MS/s. The chosen technology is the AMS 0.35 μm CMOS and the chip area occupancy is 5 × 5 mm2.

Polypyrrole Porous Micro Humidity Sensor Integrated with a Ring Oscillator Circuit on Chip

PubMed Central

Yang, Ming-Zhi; Dai, Ching-Liang; Lu, De-Hao

2010-01-01

This study presents the design and fabrication of a capacitive micro humidity sensor integrated with a five-stage ring oscillator circuit on chip using the complimentary metal oxide semiconductor (CMOS) process. The area of the humidity sensor chip is about 1 mm2. The humidity sensor consists of a sensing capacitor and a sensing film. The sensing capacitor is constructed from spiral interdigital electrodes that can enhance the sensitivity of the sensor. The sensing film of the sensor is polypyrrole, which is prepared by the chemical polymerization method, and the film has a porous structure. The sensor needs a post-CMOS process to coat the sensing film. The post-CMOS process uses a wet etching to etch the sacrificial layers, and then the polypyrrole is coated on the sensing capacitor. The sensor generates a change in capacitance when the sensing film absorbs or desorbs vapor. The ring oscillator circuit converts the capacitance variation of the sensor into the oscillation frequency output. Experimental results show that the sensitivity of the humidity sensor is about 99 kHz/%RH at 25 °C. PMID:22163459

Polypyrrole porous micro humidity sensor integrated with a ring oscillator circuit on chip.

PubMed

Yang, Ming-Zhi; Dai, Ching-Liang; Lu, De-Hao

2010-01-01

This study presents the design and fabrication of a capacitive micro humidity sensor integrated with a five-stage ring oscillator circuit on chip using the complimentary metal oxide semiconductor (CMOS) process. The area of the humidity sensor chip is about 1 mm(2). The humidity sensor consists of a sensing capacitor and a sensing film. The sensing capacitor is constructed from spiral interdigital electrodes that can enhance the sensitivity of the sensor. The sensing film of the sensor is polypyrrole, which is prepared by the chemical polymerization method, and the film has a porous structure. The sensor needs a post-CMOS process to coat the sensing film. The post-CMOS process uses a wet etching to etch the sacrificial layers, and then the polypyrrole is coated on the sensing capacitor. The sensor generates a change in capacitance when the sensing film absorbs or desorbs vapor. The ring oscillator circuit converts the capacitance variation of the sensor into the oscillation frequency output. Experimental results show that the sensitivity of the humidity sensor is about 99 kHz/%RH at 25 °C.

Fabrication and Characterization of a CMOS-MEMS Humidity Sensor.

PubMed

Dennis, John-Ojur; Ahmed, Abdelaziz-Yousif; Khir, Mohd-Haris

2015-07-10

This paper reports on the fabrication and characterization of a Complementary Metal Oxide Semiconductor-Microelectromechanical System (CMOS-MEMS) device with embedded microheater operated at relatively elevated temperatures (40 °C to 80 °C) for the purpose of relative humidity measurement. The sensing principle is based on the change in amplitude of the device due to adsorption or desorption of humidity on the active material layer of titanium dioxide (TiO2) nanoparticles deposited on the moving plate, which results in changes in the mass of the device. The sensor has been designed and fabricated through a standard 0.35 µm CMOS process technology and post-CMOS micromachining technique has been successfully implemented to release the MEMS structures. The sensor is operated in the dynamic mode using electrothermal actuation and the output signal measured using a piezoresistive (PZR) sensor connected in a Wheatstone bridge circuit. The output voltage of the humidity sensor increases from 0.585 mV to 30.580 mV as the humidity increases from 35% RH to 95% RH. The output voltage is found to be linear from 0.585 mV to 3.250 mV as the humidity increased from 35% RH to 60% RH, with sensitivity of 0.107 mV/% RH; and again linear from 3.250 mV to 30.580 mV as the humidity level increases from 60% RH to 95% RH, with higher sensitivity of 0.781 mV/% RH. On the other hand, the sensitivity of the humidity sensor increases linearly from 0.102 mV/% RH to 0.501 mV/% RH with increase in the temperature from 40 °C to 80 °C and a maximum hysteresis of 0.87% RH is found at a relative humidity of 80%. The sensitivity is also frequency dependent, increasing from 0.500 mV/% RH at 2 Hz to reach a maximum value of 1.634 mV/% RH at a frequency of 12 Hz, then decreasing to 1.110 mV/% RH at a frequency of 20 Hz. Finally, the CMOS-MEMS humidity sensor showed comparable response, recovery, and repeatability of measurements in three cycles as compared to a standard sensor that directly measures humidity in % RH.

Fabrication and Characterization of a CMOS-MEMS Humidity Sensor

PubMed Central

Dennis, John-Ojur; Ahmed, Abdelaziz-Yousif; Khir, Mohd-Haris

2015-01-01

This paper reports on the fabrication and characterization of a Complementary Metal Oxide Semiconductor-Microelectromechanical System (CMOS-MEMS) device with embedded microheater operated at relatively elevated temperatures (40 °C to 80 °C) for the purpose of relative humidity measurement. The sensing principle is based on the change in amplitude of the device due to adsorption or desorption of humidity on the active material layer of titanium dioxide (TiO2) nanoparticles deposited on the moving plate, which results in changes in the mass of the device. The sensor has been designed and fabricated through a standard 0.35 µm CMOS process technology and post-CMOS micromachining technique has been successfully implemented to release the MEMS structures. The sensor is operated in the dynamic mode using electrothermal actuation and the output signal measured using a piezoresistive (PZR) sensor connected in a Wheatstone bridge circuit. The output voltage of the humidity sensor increases from 0.585 mV to 30.580 mV as the humidity increases from 35% RH to 95% RH. The output voltage is found to be linear from 0.585 mV to 3.250 mV as the humidity increased from 35% RH to 60% RH, with sensitivity of 0.107 mV/% RH; and again linear from 3.250 mV to 30.580 mV as the humidity level increases from 60% RH to 95% RH, with higher sensitivity of 0.781 mV/% RH. On the other hand, the sensitivity of the humidity sensor increases linearly from 0.102 mV/% RH to 0.501 mV/% RH with increase in the temperature from 40 °C to 80 °C and a maximum hysteresis of 0.87% RH is found at a relative humidity of 80%. The sensitivity is also frequency dependent, increasing from 0.500 mV/% RH at 2 Hz to reach a maximum value of 1.634 mV/% RH at a frequency of 12 Hz, then decreasing to 1.110 mV/% RH at a frequency of 20 Hz. Finally, the CMOS-MEMS humidity sensor showed comparable response, recovery, and repeatability of measurements in three cycles as compared to a standard sensor that directly measures humidity in % RH. PMID:26184204

Determining the Performance of Fluorescence Molecular Imaging Devices using Traceable Working Standards with SI Units of Radiance

PubMed Central

Zhu, Banghe; Rasmussen, John C.; Litorja, Maritoni

2017-01-01

To date, no emerging preclinical or clinical near-infrared fluorescence (NIRF) imaging devices for non-invasive and/or surgical guidance have their performances validated on working standards with SI units of radiance that enable comparison or quantitative quality assurance. In this work, we developed and deployed a methodology to calibrate a stable, solid phantom for emission radiance with units of mW · sr−1 · cm−2 for use in characterizing the measurement sensitivity of ICCD and IsCMOS detection, signal-to-noise ratio, and contrast. In addition, at calibrated radiances, we assess transverse and lateral resolution of ICCD and IsCMOS camera systems. The methodology allowed determination of superior SNR of the ICCD over the IsCMOS camera system and superior resolution of the IsCMOS over the ICCD camera system. Contrast depended upon the camera settings (binning and integration time) and gain of intensifier. Finally, because of architecture of CMOS and CCD camera systems resulting in vastly different performance, we comment on the utility of these systems for small animal imaging as well as clinical applications for non-invasive and surgical guidance. PMID:26552078

FDSOI 28nm performances study for RF energy scavenging

NASA Astrophysics Data System (ADS)

Rochefeuille, E.; Alicalapa, F.; Douyère, A.; Vuong, T. P.

2018-03-01

This paper presents a study on an integrated technology: Fully-Depleted-Silicon-On-Insulator (FDSOI) at a 28nm node. FDSOI results are compared to another technology: Complementary-Metal-Oxide-Semiconductor (CMOS) 350nm. The aim of this work was to demonstrate the advantages of using FDSOI technology in RF energy scavenging applications. Characteristics of transistors are pointed out and results showed an improved 22%-output voltage gain for a series rectifier and a 13%-output voltage gain for a Dickson charge pump in FDSOI technology compared to CMOS, for an input voltage and power of 0.5 V and 0 dBm respectively. Those results allowed to prove that FDSOI 28nm is a better technology choice for energy scavenging and low-power applications.

Read-noise characterization of focal plane array detectors via mean-variance analysis.

PubMed

Sperline, R P; Knight, A K; Gresham, C A; Koppenaal, D W; Hieftje, G M; Denton, M B

2005-11-01

Mean-variance analysis is described as a method for characterization of the read-noise and gain of focal plane array (FPA) detectors, including charge-coupled devices (CCDs), charge-injection devices (CIDs), and complementary metal-oxide-semiconductor (CMOS) multiplexers (infrared arrays). Practical FPA detector characterization is outlined. The nondestructive readout capability available in some CIDs and FPA devices is discussed as a means for signal-to-noise ratio improvement. Derivations of the equations are fully presented to unify understanding of this method by the spectroscopic community.

SEE Sensitivity Analysis of 180 nm NAND CMOS Logic Cell for Space Applications

NASA Astrophysics Data System (ADS)

Sajid, Muhammad

2016-07-01

This paper focus on Single Event Effects caused by energetic particle strike on sensitive locations in CMOS NAND logic cell designed in 180nm technology node to be operated in space radiation environment. The generation of SE transients as well as upsets as function of LET of incident particle has been determined for logic devices onboard LEO and GEO satellites. The minimum magnitude pulse and pulse-width for threshold LET was determined to estimate the vulnerability /susceptibility of device for heavy ion strike. The impact of temperature, strike location and logic state of NAND circuit on total SEU/SET rate was estimated with physical mechanism simulations using Visual TCAD, Genius, runSEU program and Crad computer codes.

A Monolithic CMOS Magnetic Hall Sensor with High Sensitivity and Linearity Characteristics

PubMed Central

Huang, Haiyun; Wang, Dejun; Xu, Yue

2015-01-01

This paper presents a fully integrated linear Hall sensor by means of 0.8 μm high voltage complementary metal-oxide semiconductor (CMOS) technology. This monolithic Hall sensor chip features a highly sensitive horizontal switched Hall plate and an efficient signal conditioner using dynamic offset cancellation technique. An improved cross-like Hall plate achieves high magnetic sensitivity and low offset. A new spinning current modulator stabilizes the quiescent output voltage and improves the reliability of the signal conditioner. The tested results show that at the 5 V supply voltage, the maximum Hall output voltage of the monolithic Hall sensor microsystem, is up to ±2.1 V and the linearity of Hall output voltage is higher than 99% in the magnetic flux density range from ±5 mT to ±175 mT. The output equivalent residual offset is 0.48 mT and the static power consumption is 20 mW. PMID:26516864

A Monolithic CMOS Magnetic Hall Sensor with High Sensitivity and Linearity Characteristics.

PubMed

Huang, Haiyun; Wang, Dejun; Xu, Yue

2015-10-27

This paper presents a fully integrated linear Hall sensor by means of 0.8 μm high voltage complementary metal-oxide semiconductor (CMOS) technology. This monolithic Hall sensor chip features a highly sensitive horizontal switched Hall plate and an efficient signal conditioner using dynamic offset cancellation technique. An improved cross-like Hall plate achieves high magnetic sensitivity and low offset. A new spinning current modulator stabilizes the quiescent output voltage and improves the reliability of the signal conditioner. The tested results show that at the 5 V supply voltage, the maximum Hall output voltage of the monolithic Hall sensor microsystem, is up to ±2.1 V and the linearity of Hall output voltage is higher than 99% in the magnetic flux density range from ±5 mT to ±175 mT. The output equivalent residual offset is 0.48 mT and the static power consumption is 20 mW.

Sol-gel zinc oxide humidity sensors integrated with a ring oscillator circuit on-a-chip.

PubMed

Yang, Ming-Zhi; Dai, Ching-Liang; Wu, Chyan-Chyi

2014-10-28

The study develops an integrated humidity microsensor fabricated using the commercial 0.18 μm complementary metal oxide semiconductor (CMOS) process. The integrated humidity sensor consists of a humidity sensor and a ring oscillator circuit on-a-chip. The humidity sensor is composed of a sensitive film and branch interdigitated electrodes. The sensitive film is zinc oxide prepared by sol-gel method. After completion of the CMOS process, the sensor requires a post-process to remove the sacrificial oxide layer and to coat the zinc oxide film on the interdigitated electrodes. The capacitance of the sensor changes when the sensitive film adsorbs water vapor. The circuit is used to convert the capacitance of the humidity sensor into the oscillation frequency output. Experimental results show that the output frequency of the sensor changes from 84.3 to 73.4 MHz at 30 °C as the humidity increases 40 to 90%RH.

An acetone microsensor with a ring oscillator circuit fabricated using the commercial 0.18 μm CMOS process.

PubMed

Yang, Ming-Zhi; Dai, Ching-Liang; Shih, Po-Jen

2014-07-17

This study investigates the fabrication and characterization of an acetone microsensor with a ring oscillator circuit using the commercial 0.18 μm complementary metal oxide semiconductor (CMOS) process. The acetone microsensor contains a sensitive material, interdigitated electrodes and a polysilicon heater. The sensitive material is α-Fe2O3 synthesized by the hydrothermal method. The sensor requires a post-process to remove the sacrificial oxide layer between the interdigitated electrodes and to coat the α-Fe2O3 on the electrodes. When the sensitive material adsorbs acetone vapor, the sensor produces a change in capacitance. The ring oscillator circuit converts the capacitance of the sensor into the oscillation frequency output. The experimental results show that the output frequency of the acetone sensor changes from 128 to 100 MHz as the acetone concentration increases 1 to 70 ppm.

An Acetone Microsensor with a Ring Oscillator Circuit Fabricated Using the Commercial 0.18 μm CMOS Process

PubMed Central

Yang, Ming-Zhi; Dai, Ching-Liang; Shih, Po-Jen

2014-01-01

This study investigates the fabrication and characterization of an acetone microsensor with a ring oscillator circuit using the commercial 0.18 μm complementary metal oxide semiconductor (CMOS) process. The acetone microsensor contains a sensitive material, interdigitated electrodes and a polysilicon heater. The sensitive material is α-Fe2O3 synthesized by the hydrothermal method. The sensor requires a post-process to remove the sacrificial oxide layer between the interdigitated electrodes and to coat the α-Fe2O3 on the electrodes. When the sensitive material adsorbs acetone vapor, the sensor produces a change in capacitance. The ring oscillator circuit converts the capacitance of the sensor into the oscillation frequency output. The experimental results show that the output frequency of the acetone sensor changes from 128 to 100 MHz as the acetone concentration increases 1 to 70 ppm. PMID:25036331

Effects of Shuttle bay environment on UV sensitive photographic film - Instrumentation for Get-Away-Special

NASA Technical Reports Server (NTRS)

Kreplin, R. W.; Dohne, B.; Feldman, U.; Neupert, W. M.

1984-01-01

An account is given of a Get-Away-Special experiment flown on Space Shuttles 7 and 8 investigating the effect of the space environment on Shumann emulsions. Shumann emulsions, having low gelatin content and no protective gelatin overcoating, are useful detectors of ultraviolet radiation shorter than 2200 angstroms but are extremely sensitive to environmental conditions and handling. The instrument required no interface with the Shuttle. It was turned on by an aneroid switch at an altitude of 50,000 feet. After that, its operation was controlled completely by a CMOS digital controller. Each hour, two temperatures and one voltage were read and stored in a CMOS programmable read only memory. At intervals, valves were opened and closed to expose SO 652 film strips of three sensitivities to the cargo bay environment for various time periods. The design and operation of the instrument package is described.

Radiation dependence of inverter propagation delay from timing sampler measurements

NASA Technical Reports Server (NTRS)

Buehler, M. G.; Blaes, B. R.; Lin, Y.-S.

1989-01-01

A timing sampler consisting of 14 four-stage inverter-pair chains with different load capacitances was fabricated in 1.6-micron n-well CMOS and irradiated with cobalt-60 at 10 rad(Si)/s. For this CMOS process the measured results indicate that the rising delay increases by about 2.2 ns/Mrad(Si) and the falling delay increase is very small, i.e., less than 300 ps/Mrad(Si). The amount of radiation-induced delay depends on the size of the load capacitance. The maximum value observed for this effect was 5.65 ns/pF-Mrad(Si). Using a sensitivity analysis, the sensitivity of the rising delay to radiation can be explained by a simple timing model and the radiation sensitivity of dc MOSFET parameters. This same approach could not explain the insensitivity of the falling delay to radiation. This may be due to a failure of the timing model and/or trapping effects.

Design considerations for a new, high resolution Micro-Angiographic Fluoroscope based on a CMOS sensor (MAF-CMOS).

PubMed

Loughran, Brendan; Swetadri Vasan, S N; Singh, Vivek; Ionita, Ciprian N; Jain, Amit; Bednarek, Daniel R; Titus, Albert; Rudin, Stephen

2013-03-06

The detectors that are used for endovascular image-guided interventions (EIGI), particularly for neurovascular interventions, do not provide clinicians with adequate visualization to ensure the best possible treatment outcomes. Developing an improved x-ray imaging detector requires the determination of estimated clinical x-ray entrance exposures to the detector. The range of exposures to the detector in clinical studies was found for the three modes of operation: fluoroscopic mode, high frame-rate digital angiographic mode (HD fluoroscopic mode), and DSA mode. Using these estimated detector exposure ranges and available CMOS detector technical specifications, design requirements were developed to pursue a quantum limited, high resolution, dynamic x-ray detector based on a CMOS sensor with 50 μm pixel size. For the proposed MAF-CMOS, the estimated charge collected within the full exposure range was found to be within the estimated full well capacity of the pixels. Expected instrumentation noise for the proposed detector was estimated to be 50-1,300 electrons. Adding a gain stage such as a light image intensifier would minimize the effect of the estimated instrumentation noise on total image noise but may not be necessary to ensure quantum limited detector operation at low exposure levels. A recursive temporal filter may decrease the effective total noise by 2 to 3 times, allowing for the improved signal to noise ratios at the lowest estimated exposures despite consequent loss in temporal resolution. This work can serve as a guide for further development of dynamic x-ray imaging prototypes or improvements for existing dynamic x-ray imaging systems.

Real-time optically sectioned wide-field microscopy employing structured light illumination and a CMOS detector

NASA Astrophysics Data System (ADS)

Mitic, Jelena; Anhut, Tiemo; Serov, Alexandre; Lasser, Theo; Bourquin, Stephane

2003-07-01

Real-time optically sectioned microscopy is demonstrated using an AC-sensitive detection concept realized with smart CMOS image sensor and structured light illumination by a continuously moving periodic pattern. We describe two different detection systems based on CMOS image sensors for the detection and on-chip processing of the sectioned images in real time. A region-of-interest is sampled at high frame rate. The demodulated signal delivered by the detector corresponds to the depth discriminated image of the sample. The measured FWHM of the axial response depends on the spatial frequency of the projected grid illumination and is in the μm-range. The effect of using broadband incoherent illumination is discussed. The performance of these systems is demonstrated by imaging technical as well as biological samples.

Analog CMOS design for optical coherence tomography signal detection and processing.

PubMed

Xu, Wei; Mathine, David L; Barton, Jennifer K

2008-02-01

A CMOS circuit was designed and fabricated for optical coherence tomography (OCT) signal detection and processing. The circuit includes a photoreceiver, differential gain stage and lock-in amplifier based demodulator. The photoreceiver consists of a CMOS photodetector and low noise differential transimpedance amplifier which converts the optical interference signal into a voltage. The differential gain stage further amplifies the signal. The in-phase and quadrature channels of the lock-in amplifier each include an analog mixer and switched-capacitor low-pass filter with an external mixer reference signal. The interferogram envelope and phase can be extracted with this configuration, enabling Doppler OCT measurements. A sensitivity of -80 dB is achieved with faithful reproduction of the interferometric signal envelope. A sample image of finger tip is presented.

1024-Pixel CMOS Multimodality Joint Cellular Sensor/Stimulator Array for Real-Time Holistic Cellular Characterization and Cell-Based Drug Screening.

PubMed

Park, Jong Seok; Aziz, Moez Karim; Li, Sensen; Chi, Taiyun; Grijalva, Sandra Ivonne; Sung, Jung Hoon; Cho, Hee Cheol; Wang, Hua

2018-02-01

This paper presents a fully integrated CMOS multimodality joint sensor/stimulator array with 1024 pixels for real-time holistic cellular characterization and drug screening. The proposed system consists of four pixel groups and four parallel signal-conditioning blocks. Every pixel group contains 16 × 16 pixels, and each pixel includes one gold-plated electrode, four photodiodes, and in-pixel circuits, within a pixel footprint. Each pixel supports real-time extracellular potential recording, optical detection, charge-balanced biphasic current stimulation, and cellular impedance measurement for the same cellular sample. The proposed system is fabricated in a standard 130-nm CMOS process. Rat cardiomyocytes are successfully cultured on-chip. Measured high-resolution optical opacity images, extracellular potential recordings, biphasic current stimulations, and cellular impedance images demonstrate the unique advantages of the system for holistic cell characterization and drug screening. Furthermore, this paper demonstrates the use of optical detection on the on-chip cultured cardiomyocytes to real-time track their cyclic beating pattern and beating rate.

MoS2/Ni3S4 composite nanosheets on interconnected carbon shells as an excellent supercapacitor electrode architecture for long term cycling at high current densities

NASA Astrophysics Data System (ADS)

Qin, Shengchun; Yao, Tinghui; Guo, Xin; Chen, Qiang; Liu, Dequan; Liu, Qiming; Li, Yali; Li, Junshuai; He, Deyan

2018-05-01

In this paper, we report an electrode architecture of molybdenum disulfide (MoS2)/nickel sulfide (Ni3S4) composite nanosheets anchored on interconnected carbon (C) shells (C@MoS2/Ni3S4). Electrochemical measurements indicate that the C@MoS2/Ni3S4 structure possesses excellent supercapacitive properties especially for long term cycling at high current densities. A specific capacitance as high as ∼640.7 F g-1 can still be delivered even after 10,000 cycles at a high current density of 20 A g-1. From comparison of microstructures and electrochemical properties of the related materials/structures, the improved performance of C@MoS2/Ni3S4 can be attributed to the relatively dispersedly distributed nanosheet-shaped MoS2/Ni3S4 that provides efficient contact with electrolyte and effectively buffers the volume change during charge/discharge processes, enhanced cycling stability by MoS2, and reduced equivalent series resistance by the interconnected C shells.

Hyperspectral Image-Based Night-Time Vehicle Light Detection Using Spectral Normalization and Distance Mapper for Intelligent Headlight Control.

PubMed

Kim, Heekang; Kwon, Soon; Kim, Sungho

2016-07-08

This paper proposes a vehicle light detection method using a hyperspectral camera instead of a Charge-Coupled Device (CCD) or Complementary metal-Oxide-Semiconductor (CMOS) camera for adaptive car headlamp control. To apply Intelligent Headlight Control (IHC), the vehicle headlights need to be detected. Headlights are comprised from a variety of lighting sources, such as Light Emitting Diodes (LEDs), High-intensity discharge (HID), and halogen lamps. In addition, rear lamps are made of LED and halogen lamp. This paper refers to the recent research in IHC. Some problems exist in the detection of headlights, such as erroneous detection of street lights or sign lights and the reflection plate of ego-car from CCD or CMOS images. To solve these problems, this study uses hyperspectral images because they have hundreds of bands and provide more information than a CCD or CMOS camera. Recent methods to detect headlights used the Spectral Angle Mapper (SAM), Spectral Correlation Mapper (SCM), and Euclidean Distance Mapper (EDM). The experimental results highlight the feasibility of the proposed method in three types of lights (LED, HID, and halogen).

Improved Signal Chains for Readout of CMOS Imagers

NASA Technical Reports Server (NTRS)

Pain, Bedabrata; Hancock, Bruce; Cunningham, Thomas

2009-01-01

An improved generic design has been devised for implementing signal chains involved in readout from complementary metal oxide/semiconductor (CMOS) image sensors and for other readout integrated circuits (ICs) that perform equivalent functions. The design applies to any such IC in which output signal charges from the pixels in a given row are transferred simultaneously into sampling capacitors at the bottoms of the columns, then voltages representing individual pixel charges are read out in sequence by sequentially turning on column-selecting field-effect transistors (FETs) in synchronism with source-follower- or operational-amplifier-based amplifier circuits. The improved design affords the best features of prior source-follower-and operational- amplifier-based designs while overcoming the major limitations of those designs. The limitations can be summarized as follows: a) For a source-follower-based signal chain, the ohmic voltage drop associated with DC bias current flowing through the column-selection FET causes unacceptable voltage offset, nonlinearity, and reduced small-signal gain. b) For an operational-amplifier-based signal chain, the required bias current and the output noise increase superlinearly with size of the pixel array because of a corresponding increase in the effective capacitance of the row bus used to couple the sampled column charges to the operational amplifier. The effect of the bus capacitance is to simultaneously slow down the readout circuit and increase noise through the Miller effect.

How small can MOSFETs get?

NASA Astrophysics Data System (ADS)

Risch, Lothar

2001-10-01

Scaling of CMOS technology made possible the key appliances of our information technology society, like the PC, mobile communication, and the internet. Reduction of feature sizes for semiconductor devices continued according to Moore's law for the last 25 years in order to achieve higher integration densities, higher speed, lower power consumption, and lower costs. But now, as we approach the sub 100 nm regime, several roadblocks have been predicted for the next generations down to 35 nm. The latest ITRS roadmap 99 describes in detail the challenges which have to be addressed for the future CMOS technology nodes, regarding lithography, metallization, power dissipation, and circuit design. Also for the MOSFET, performance degradation is a big issue. Because this is not a limitation from basic physical laws, novel architectures for MOSFETs will be needed to improve again the electrical characteristics and thus pave the way to much smaller transistors than expected in the past. 25 nm CMOS seems to be feasible using very thin silicon substrates on insulator. Further improvements down to 10 nm are very likely with two gates for the control of the charge carriers. So, it is very likely that CMOS will not end with today's roadmap at 35 nm or even before, but may continue with non bulk devices and fully depleted channels. Finally, tunnelling from source to drain will set an end to the reduction of channel length, which is estimated to be below 5 nm.

Frontend Receiver Electronics for High Frequency Monolithic CMUT-on-CMOS Imaging Arrays

PubMed Central

Gurun, Gokce; Hasler, Paul; Degertekin, F. Levent

2012-01-01

This paper describes the design of CMOS receiver electronics for monolithic integration with capacitive micromachined ultrasonic transducer (CMUT) arrays for high-frequency intravascular ultrasound imaging. A custom 8-inch wafer is fabricated in a 0.35 μm two-poly, four-metal CMOS process and then CMUT arrays are built on top of the application specific integrated circuits (ASICs) on the wafer. We discuss advantages of the single-chip CMUT-on-CMOS approach in terms of receive sensitivity and SNR. Low-noise and high-gain design of a transimpedance amplifier (TIA) optimized for a forward-looking volumetric-imaging CMUT array element is discussed as a challenging design example. Amplifier gain, bandwidth, dynamic range and power consumption trade-offs are discussed in detail. With minimized parasitics provided by the CMUT-on-CMOS approach, the optimized TIA design achieves a 90 fA/√Hz input referred current noise, which is less than the thermal-mechanical noise of the CMUT element. We show successful system operation with a pulse-echo measurement. Transducer noise-dominated detection in immersion is also demonstrated through output noise spectrum measurement of the integrated system at different CMUT bias voltages. A noise figure of 1.8 dB is obtained in the designed CMUT bandwidth of 10 MHz to 20 MHz. PMID:21859585

Front-end receiver electronics for high-frequency monolithic CMUT-on-CMOS imaging arrays.

PubMed

Gurun, Gokce; Hasler, Paul; Degertekin, F

2011-08-01

This paper describes the design of CMOS receiver electronics for monolithic integration with capacitive micromachined ultrasonic transducer (CMUT) arrays for highfrequency intravascular ultrasound imaging. A custom 8-inch (20-cm) wafer is fabricated in a 0.35-μm two-poly, four-metal CMOS process and then CMUT arrays are built on top of the application specific integrated circuits (ASICs) on the wafer. We discuss advantages of the single-chip CMUT-on-CMOS approach in terms of receive sensitivity and SNR. Low-noise and high-gain design of a transimpedance amplifier (TIA) optimized for a forward-looking volumetric-imaging CMUT array element is discussed as a challenging design example. Amplifier gain, bandwidth, dynamic range, and power consumption trade-offs are discussed in detail. With minimized parasitics provided by the CMUT-on-CMOS approach, the optimized TIA design achieves a 90 fA/√Hz input-referred current noise, which is less than the thermal-mechanical noise of the CMUT element. We show successful system operation with a pulseecho measurement. Transducer-noise-dominated detection in immersion is also demonstrated through output noise spectrum measurement of the integrated system at different CMUT bias voltages. A noise figure of 1.8 dB is obtained in the designed CMUT bandwidth of 10 to 20 MHz.

Realize multiple hermetic chamber pressures for system-on-chip process by using the capping wafer with diverse cavity depths

NASA Astrophysics Data System (ADS)

Cheng, Shyh-Wei; Weng, Jui-Chun; Liang, Kai-Chih; Sun, Yi-Chiang; Fang, Weileun

2018-04-01

Many mechanical and thermal characteristics, for example the air damping, of suspended micromachined structures are sensitive to the ambient pressure. Thus, micromachined devices such as the gyroscope and accelerometer have different ambient pressure requirements. Commercially available process platforms could be used to fabricate and integrate devices of various functions to reduce the chip size. However, it remains a challenge to offer different ambient pressures for micromachined devices after sealing them by wafer level capping (WLC). This study exploits the outgassing characteristics of the CMOS chip to fabricate chambers of various pressures after the WLC of the Si-above-CMOS (TSMC 0.18 µm 1P5M CMOS process) MEMS process platform. The pressure of the sealed chamber can be modulated by the chamber volume after the outgassing. In other words, the pressure of hermetic sealed chambers can be easily and properly defined by the etching depth of the cavity on an Si capping wafer. In applications, devices sealed with different cavity depths are implemented using the Si-above-CMOS (TSMC 0.18 µm 1P5M CMOS process) MEMS process platform to demonstrate the present approach. Measurements show the feasibility of this simple chamber pressure modulation approach on eight-inch wafers.

A 32 x 32 capacitive micromachined ultrasonic transducer array manufactured in standard CMOS.

PubMed

Lemmerhirt, David F; Cheng, Xiaoyang; White, Robert; Rich, Collin A; Zhang, Man; Fowlkes, J Brian; Kripfgans, Oliver D

2012-07-01

As ultrasound imagers become increasingly portable and lower cost, breakthroughs in transducer technology will be needed to provide high-resolution, real-time 3-D imaging while maintaining the affordability needed for portable systems. This paper presents a 32 x 32 ultrasound array prototype, manufactured using a CMUT-in-CMOS approach whereby ultrasonic transducer elements and readout circuits are integrated on a single chip using a standard integrated circuit manufacturing process in a commercial CMOS foundry. Only blanket wet-etch and sealing steps are added to complete the MEMS devices after the CMOS process. This process typically yields better than 99% working elements per array, with less than ±1.5 dB variation in receive sensitivity among the 1024 individually addressable elements. The CMUT pulseecho frequency response is typically centered at 2.1 MHz with a -6 dB fractional bandwidth of 60%, and elements are arranged on a 250 μm hexagonal grid (less than half-wavelength pitch). Multiplexers and CMOS buffers within the array are used to make on-chip routing manageable, reduce the number of physical output leads, and drive the transducer cable. The array has been interfaced to a commercial imager as well as a set of custom transmit and receive electronics, and volumetric images of nylon fishing line targets have been produced.

Development of Integrated Preamplifier for High-Frequency Ultrasonic Transducers and Low-Power Handheld Receiver

PubMed Central

Choi, Hojong; Li, Xiang; Lau, Sien-Ting; Hu, ChangHong; Zhou, Qifa; Shung, K. Kirk

2012-01-01

This paper describes the design of a front-end circuit consisting of an integrated preamplifier with a Sallen-Key Butterworth filter for very-high-frequency ultrasonic transducers and a low-power handheld receiver. This preamplifier was fabricated using a 0.18-μm 7WL SiGe bi-polar complementary metal oxide semiconductor (BiCMOS) process. The Sallen-Key filter is used to increase the voltage gain of the front-end circuit for high-frequency transducers which are generally low in sensitivity. The measured peak voltage gain of the frontend circuits for the BiCMOS preamplifier with the Sallen-Key filter was 41.28 dB at 100 MHz with a −6-dB bandwidth of 91%, and the dc power consumption of the BiCMOS preamplifier was 49.53 mW. The peak voltage gain of the front-end circuits for the CMOS preamplifier with the Sallen-Key filter was 39.52 dB at 100 MHz with a −6-dB bandwidth of 108%, and the dc power consumption of the CMOS preamplifier was 43.57 mW. Pulse-echo responses and wire phantom images with a single-element ultrasonic transducer have been acquired to demonstrate the performance of the front-end circuit. PMID:23443700

Latchup in CMOS devices from heavy ions

NASA Technical Reports Server (NTRS)

Soliman, K.; Nichols, D. K.

1983-01-01

It is noted that complementary metal oxide semiconductor (CMOS) microcircuits are inherently latchup prone. The four-layer n-p-n-p structures formed from the parasitic pnp and npn transistors make up a silicon controlled rectifier. If properly biased, this rectifier may be triggered 'ON' by electrical transients, ionizing radiation, or a single heavy ion. This latchup phenomenon might lead to a loss of functionality or device burnout. Results are presented from tests on 19 different device types from six manufacturers which investigate their latchup sensitivity with argon and krypton beams. The parasitic npnp paths are identified in general, and a qualitative rationale is given for latchup susceptibility, along with a latchup cross section for each type of device. Also presented is the correlation between bit-flip sensitivity and latchup susceptibility.

A FPGA-based Cluster Finder for CMOS Monolithic Active Pixel Sensors of the MIMOSA-26 Family

NASA Astrophysics Data System (ADS)

Li, Qiyan; Amar-Youcef, S.; Doering, D.; Deveaux, M.; Fröhlich, I.; Koziel, M.; Krebs, E.; Linnik, B.; Michel, J.; Milanovic, B.; Müntz, C.; Stroth, J.; Tischler, T.

2014-06-01

CMOS Monolithic Active Pixel Sensors (MAPS) demonstrated excellent performances in the field of charged particle tracking. Among their strong points are an single point resolution few μm, a light material budget of 0.05% X0 in combination with a good radiation tolerance and high rate capability. Those features make the sensors a valuable technology for vertex detectors of various experiments in heavy ion and particle physics. To reduce the load on the event builders and future mass storage systems, we have developed algorithms suited for preprocessing and reducing the data streams generated by the MAPS. This real-time processing employs remaining free resources of the FPGAs of the readout controllers of the detector and complements the on-chip data reduction circuits of the MAPS.

Sensitivity-Enhanced CMOS Phase Luminometry System Using Xerogel-Based Sensors.

PubMed

Lei Yao; Khan, R; Chodavarapu, V P; Tripathi, V S; Bright, F V

2009-10-01

We present the design and implementation of a phase luminometry sensor system with improved and tunable detection sensitivity achieved using a complementary metal-oxide semiconductor (CMOS) integrated circuit. We use sol-gel derived xerogel thin films as an immobilization media to house oxygen (O2) responsive luminescent molecules. The sensor operates on the principal of phase luminometry wherein a sinusoidal modulation signal is used to excite the luminophores encapsulated in the porous xerogel films and the corresponding phase shift of the emission signals is monitored. The phase shift is directly related to excited state lifetimes of the luminophores which in turn are related to the concentration of the target analyte species present in the vicinity of the luminophores. The CMOS IC, which consists of a 16 times 16 high-gain phototransistor array, current-to-voltage converter, amplifier and tunable phase shift detector, consumes an average power of 14 mW with 5-V power supply operating at a 38-kHz modulation frequency. The output of the IC is a dc voltage that corresponds to the detected luminescence phase shift with respect to the excitation signal. As a prototype, we demonstrate an oxygen sensor system by encapsulating the luminophore tris(4,7-diphenyl-1,10-phenanthroline)ruthenium(II) within the xerogel matrices. The sensor system showed a fast response on the order of few seconds and we obtained a detection sensitivity of 118 mV per 1% change in O2 concentration. The system demonstrates a novel concept to tune and improve the detection sensitivity for specific concentrations of the target analyte in many biomedical monitoring applications.

CMOS image sensor with organic photoconductive layer having narrow absorption band and proposal of stack type solid-state image sensors

NASA Astrophysics Data System (ADS)

Takada, Shunji; Ihama, Mikio; Inuiya, Masafumi

2006-02-01

Digital still cameras overtook film cameras in Japanese market in 2000 in terms of sales volume owing to their versatile functions. However, the image-capturing capabilities such as sensitivity and latitude of color films are still superior to those of digital image sensors. In this paper, we attribute the cause for the high performance of color films to their multi-layered structure, and propose the solid-state image sensors with stacked organic photoconductive layers having narrow absorption bands on CMOS read-out circuits.

Single photon detection using Geiger mode CMOS avalanche photodiodes

NASA Astrophysics Data System (ADS)

Lawrence, William G.; Stapels, Christopher; Augustine, Frank L.; Christian, James F.

2005-10-01

Geiger mode Avalanche Photodiodes fabricated using complementary metal-oxide-semiconductor (CMOS) fabrication technology combine high sensitivity detectors with pixel-level auxiliary circuitry. Radiation Monitoring Devices has successfully implemented CMOS manufacturing techniques to develop prototype detectors with active diameters ranging from 5 to 60 microns and measured detection efficiencies of up to 60%. CMOS active quenching circuits are included in the pixel layout. The actively quenched pixels have a quenching time less than 30 ns and a maximum count rate greater than 10 MHz. The actively quenched Geiger mode avalanche photodiode (GPD) has linear response at room temperature over six orders of magnitude. When operating in Geiger mode, these GPDs act as single photon-counting detectors that produce a digital output pulse for each photon with no associated read noise. Thermoelectrically cooled detectors have less than 1 Hz dark counts. The detection efficiency, dark count rate, and after-pulsing of two different pixel designs are measured and demonstrate the differences in the device operation. Additional applications for these devices include nuclear imaging and replacement of photomultiplier tubes in dosimeters.

CMOS integration of inkjet-printed graphene for humidity sensing.

PubMed

Santra, S; Hu, G; Howe, R C T; De Luca, A; Ali, S Z; Udrea, F; Gardner, J W; Ray, S K; Guha, P K; Hasan, T

2015-11-30

We report on the integration of inkjet-printed graphene with a CMOS micro-electro-mechanical-system (MEMS) microhotplate for humidity sensing. The graphene ink is produced via ultrasonic assisted liquid phase exfoliation in isopropyl alcohol (IPA) using polyvinyl pyrrolidone (PVP) polymer as the stabilizer. We formulate inks with different graphene concentrations, which are then deposited through inkjet printing over predefined interdigitated gold electrodes on a CMOS microhotplate. The graphene flakes form a percolating network to render the resultant graphene-PVP thin film conductive, which varies in presence of humidity due to swelling of the hygroscopic PVP host. When the sensors are exposed to relative humidity ranging from 10-80%, we observe significant changes in resistance with increasing sensitivity from the amount of graphene in the inks. Our sensors show excellent repeatability and stability, over a period of several weeks. The location specific deposition of functional graphene ink onto a low cost CMOS platform has the potential for high volume, economic manufacturing and application as a new generation of miniature, low power humidity sensors for the internet of things.

CMOS integration of inkjet-printed graphene for humidity sensing

PubMed Central

Santra, S.; Hu, G.; Howe, R. C. T.; De Luca, A.; Ali, S. Z.; Udrea, F.; Gardner, J. W.; Ray, S. K.; Guha, P. K.; Hasan, T.

2015-01-01

We report on the integration of inkjet-printed graphene with a CMOS micro-electro-mechanical-system (MEMS) microhotplate for humidity sensing. The graphene ink is produced via ultrasonic assisted liquid phase exfoliation in isopropyl alcohol (IPA) using polyvinyl pyrrolidone (PVP) polymer as the stabilizer. We formulate inks with different graphene concentrations, which are then deposited through inkjet printing over predefined interdigitated gold electrodes on a CMOS microhotplate. The graphene flakes form a percolating network to render the resultant graphene-PVP thin film conductive, which varies in presence of humidity due to swelling of the hygroscopic PVP host. When the sensors are exposed to relative humidity ranging from 10–80%, we observe significant changes in resistance with increasing sensitivity from the amount of graphene in the inks. Our sensors show excellent repeatability and stability, over a period of several weeks. The location specific deposition of functional graphene ink onto a low cost CMOS platform has the potential for high volume, economic manufacturing and application as a new generation of miniature, low power humidity sensors for the internet of things. PMID:26616216

CMOS integration of inkjet-printed graphene for humidity sensing

NASA Astrophysics Data System (ADS)

Santra, S.; Hu, G.; Howe, R. C. T.; de Luca, A.; Ali, S. Z.; Udrea, F.; Gardner, J. W.; Ray, S. K.; Guha, P. K.; Hasan, T.

2015-11-01

We report on the integration of inkjet-printed graphene with a CMOS micro-electro-mechanical-system (MEMS) microhotplate for humidity sensing. The graphene ink is produced via ultrasonic assisted liquid phase exfoliation in isopropyl alcohol (IPA) using polyvinyl pyrrolidone (PVP) polymer as the stabilizer. We formulate inks with different graphene concentrations, which are then deposited through inkjet printing over predefined interdigitated gold electrodes on a CMOS microhotplate. The graphene flakes form a percolating network to render the resultant graphene-PVP thin film conductive, which varies in presence of humidity due to swelling of the hygroscopic PVP host. When the sensors are exposed to relative humidity ranging from 10-80%, we observe significant changes in resistance with increasing sensitivity from the amount of graphene in the inks. Our sensors show excellent repeatability and stability, over a period of several weeks. The location specific deposition of functional graphene ink onto a low cost CMOS platform has the potential for high volume, economic manufacturing and application as a new generation of miniature, low power humidity sensors for the internet of things.

Radiation-Hard Complementary Integrated Circuits Based on Semiconducting Single-Walled Carbon Nanotubes.

PubMed

McMorrow, Julian J; Cress, Cory D; Gaviria Rojas, William A; Geier, Michael L; Marks, Tobin J; Hersam, Mark C

2017-03-28

Increasingly complex demonstrations of integrated circuit elements based on semiconducting single-walled carbon nanotubes (SWCNTs) mark the maturation of this technology for use in next-generation electronics. In particular, organic materials have recently been leveraged as dopant and encapsulation layers to enable stable SWCNT-based rail-to-rail, low-power complementary metal-oxide-semiconductor (CMOS) logic circuits. To explore the limits of this technology in extreme environments, here we study total ionizing dose (TID) effects in enhancement-mode SWCNT-CMOS inverters that employ organic doping and encapsulation layers. Details of the evolution of the device transport properties are revealed by in situ and in operando measurements, identifying n-type transistors as the more TID-sensitive component of the CMOS system with over an order of magnitude larger degradation of the static power dissipation. To further improve device stability, radiation-hardening approaches are explored, resulting in the observation that SWNCT-CMOS circuits are TID-hard under dynamic bias operation. Overall, this work reveals conditions under which SWCNTs can be employed for radiation-hard integrated circuits, thus presenting significant potential for next-generation satellite and space applications.

Integration of Si-CMOS embedded photo detector array and mixed signal processing system with embedded optical waveguide input

NASA Astrophysics Data System (ADS)

Kim, Daeik D.; Thomas, Mikkel A.; Brooke, Martin A.; Jokerst, Nan M.

2004-06-01

Arrays of embedded bipolar junction transistor (BJT) photo detectors (PD) and a parallel mixed-signal processing system were fabricated as a silicon complementary metal oxide semiconductor (Si-CMOS) circuit for the integration optical sensors on the surface of the chip. The circuit was fabricated with AMI 1.5um n-well CMOS process and the embedded PNP BJT PD has a pixel size of 8um by 8um. BJT PD was chosen to take advantage of its higher gain amplification of photo current than that of PiN type detectors since the target application is a low-speed and high-sensitivity sensor. The photo current generated by BJT PD is manipulated by mixed-signal processing system, which consists of parallel first order low-pass delta-sigma oversampling analog-to-digital converters (ADC). There are 8 parallel ADCs on the chip and a group of 8 BJT PDs are selected with CMOS switches. An array of PD is composed of three or six groups of PDs depending on the number of rows.

PNP PIN bipolar phototransistors for high-speed applications built in a 180 nm CMOS process.

PubMed

Kostov, P; Gaberl, W; Hofbauer, M; Zimmermann, H

2012-08-01

This work reports on three speed optimized pnp bipolar phototransistors build in a standard 180 nm CMOS process using a special starting wafer. The starting wafer consists of a low doped p epitaxial layer on top of the p substrate. This low doped p epitaxial layer leads to a thick space-charge region between base and collector and thus to a high -3 dB bandwidth at low collector-emitter voltages. For a further increase of the bandwidth the presented phototransistors were designed with small emitter areas resulting in a small base-emitter capacitance. The three presented phototransistors were implemented in sizes of 40 × 40 μm 2 and 100 × 100 μm 2 . Optical DC and AC measurements at 410 nm, 675 nm and 850 nm were done for phototransistor characterization. Due to the speed optimized design and the layer structure of the phototransistors, bandwidths up to 76.9 MHz and dynamic responsivities up to 2.89 A/W were achieved. Furthermore simulations of the electric field strength and space-charge regions were done.

The effect of the bottom electrode on ferroelectric tunnel junctions based on CMOS-compatible HfO2.

PubMed

Goh, Youngin; Jeon, Sanghun

2018-08-17

Ferroelectric tunnel junctions (FTJs) have attracted research interest as promising candidates for non-destructive readout non-volatile memories. Unlike conventional perovskite FTJs, hafnia FTJs offer many advantages in terms of scalability and CMOS compatibility. However, so far, hafnia FTJs have shown poor endurance and relatively low resistance ratios and these have remained issues for real device applications. In our study, we fabricated HfZrO(HZO)-based FTJs with various electrodes (TiN, Si, SiGe, Ge) and improved the memory performance of HZO-based FTJs by using the asymmetry of the charge screening lengths of the electrodes. For the HZO-based FTJ with a Ge substrate, the effective barrier afforded by this FTJ can be electrically modulated because of the space charge-limited region formed at the ferroelectric/semiconductor interface. The optimized HZO-based FTJ with a Ge bottom electrode presents excellent ferroelectricity with a high remnant polarization of 18 μC cm -2 , high tunneling electroresistance value of 30, good retention at 85 °C and high endurance of 10 7 . The results demonstrate the great potential of HfO 2 -based FTJs in non-destructive readout non-volatile memories.

Microbeam mapping of single event latchups and single event upsets in CMOS SRAMs

DOE Office of Scientific and Technical Information (OSTI.GOV)

Barak, J.; Adler, E.; Fischer, B.E.

1998-06-01

The first simultaneous microbeam mapping of single event upset (SEU) and latchup (SEL) in the CMOS RAM HM65162 is presented. The authors found that the shapes of the sensitive areas depend on V{sub DD}, on the ions being used and on the site on the chip being hit by the ion. In particular, they found SEL sensitive sites close to the main power supply lines between the memory-bit-arrays by detecting the accompanying current surge. All these SELs were also accompanied by bit-flips elsewhere in the memory (which they call indirect SEUs in contrast to the well known SEUs induced inmore » the hit memory cell only). When identical SEL sensitive sites were hit farther away from the supply lines only indirect SEL sensitive sites could be detected. They interpret these events as latent latchups in contrast to the classical ones detected by their induced current surge. These latent SELs were probably decoupled from the main supply lines by the high resistivity of the local supply lines.« less

Development of a compact radiation-hardened low-noise front-end readout ASIC for CZT-based hard X-ray imager

NASA Astrophysics Data System (ADS)

Gao, W.; Gan, B.; Li, X.; Wei, T.; Gao, D.; Hu, Y.

2015-04-01

In this paper, we present the development and performances of a radiation-hardened front-end readout application-specific integrated circuit (ASIC) dedicated to CZT detectors for a hard X-ray imager in space applications. The readout channel consists of a charge sensitive amplifier (CSA), a CR-RC shaper, a fast shaper, a discriminator and a driving buffer. With the additional digital filtering, the readout channel can achieve very low noise performances and low power dissipation. An eight-channel prototype ASIC is designed and fabricated in 0.35 μm CMOS process. The energy range of the detected X-rays is evaluated as 1.45 keV to 281 keV. The gain is larger than 100 mV/fC. The equivalent noise charge (ENC) of the ASIC is 53 e- at zero farad plus 10 e- per picofarad. The power dissipation is less than 4.4 mW/channel. Through the measurement with a CZT detector, the energy resolution is less than 3.45 keV (FWHM) under the irradiation of the radioactive source 241Am. The radiation effect experiments indicate that the proposed ASIC can resist the total ionization dose (TID) irradiation of higher than 200 krad (Si).

Development of monolithic pixel detector with SOI technology for the ILC vertex detector

NASA Astrophysics Data System (ADS)

Yamada, M.; Ono, S.; Tsuboyama, T.; Arai, Y.; Haba, J.; Ikegami, Y.; Kurachi, I.; Togawa, M.; Mori, T.; Aoyagi, W.; Endo, S.; Hara, K.; Honda, S.; Sekigawa, D.

2018-01-01

We have been developing a monolithic pixel sensor for the International Linear Collider (ILC) vertex detector with the 0.2 μm FD-SOI CMOS process by LAPIS Semiconductor Co., Ltd. We aim to achieve a 3 μm single-point resolution required for the ILC with a 20×20 μm2 pixel. Beam bunch crossing at the ILC occurs every 554 ns in 1-msec-long bunch trains with an interval of 200 ms. Each pixel must record the charge and time stamp of a hit to identify a collision bunch for event reconstruction. Necessary functions include the amplifier, comparator, shift register, analog memory and time stamp implementation in each pixel, and column ADC and Zero-suppression logic on the chip. We tested the first prototype sensor, SOFIST ver.1, with a 120 GeV proton beam at the Fermilab Test Beam Facility in January 2017. SOFIST ver.1 has a charge sensitive amplifier and two analog memories in each pixel, and an 8-bit Wilkinson-type ADC is implemented for each column on the chip. We measured the residual of the hit position to the reconstructed track. The standard deviation of the residual distribution fitted by a Gaussian is better than 3 μm.

An analog neural hardware implementation using charge-injection multipliers and neutron-specific gain control.

PubMed

Massengill, L W; Mundie, D B

1992-01-01

A neural network IC based on a dynamic charge injection is described. The hardware design is space and power efficient, and achieves massive parallelism of analog inner products via charge-based multipliers and spatially distributed summing buses. Basic synaptic cells are constructed of exponential pulse-decay modulation (EPDM) dynamic injection multipliers operating sequentially on propagating signal vectors and locally stored analog weights. Individually adjustable gain controls on each neutron reduce the effects of limited weight dynamic range. A hardware simulator/trainer has been developed which incorporates the physical (nonideal) characteristics of actual circuit components into the training process, thus absorbing nonlinearities and parametric deviations into the macroscopic performance of the network. Results show that charge-based techniques may achieve a high degree of neural density and throughput using standard CMOS processes.

Development of a dedicated readout ASIC for TPC based X-ray polarimeter

NASA Astrophysics Data System (ADS)

Zhang, Hongyan; Deng, Zhi; Li, Hong; Liu, Yinong; Feng, Hua

2016-07-01

X-ray polarimetry with time projection chambers was firstly proposed by JK Black in 2007 and has been greatly developed since then. It measured two dimensional photoelectron tracks with one dimensional strip and the other dimension was estimated by the drift time from the signal waveforms. A readout ASIC, APV25, originally developed for CMS silicon trackers was used and has shown some limitations such as waveform sampling depth. A dedicated ASIC was developed for TPC based X-ray polarimeters in this paper. It integrated 32 channel circuits and each channel consisted of an analog front-end and a waveform sampler based on switched capacitor array. The analog front-end has a charge sensitive preamplifier with a gain of 25 mV/fC, a CR-RC shaper with a peaking time of 25 ns, a baseline holder and a discriminator for self-triggering. The SCA has a buffer latency of 3.2 μs with 64 cells operating at 20 MSPS. The ASIC was fabricated in a 0.18 μm CMOS process. The equivalent noise charge (ENC) of the analog front-end was measured to be 274.8 e+34.6 e/pF. The effective resolution of the SCA was 8.8 bits at sampling rate up to 50 MSPS. The total power consumption was 2.8 mW per channel. The ASIC was also tested with real TPC detectors and two dimensional photoelectron tracks have been successfully acquired. More tests and analysis on the sensitivity to the polarimetry are undergoing and will be presented in this paper.

A Stimulated Raman Scattering CMOS Pixel Using a High-Speed Charge Modulator and Lock-in Amplifier.

PubMed

Lioe, De Xing; Mars, Kamel; Kawahito, Shoji; Yasutomi, Keita; Kagawa, Keiichiro; Yamada, Takahiro; Hashimoto, Mamoru

2016-04-13

A complementary metal-oxide semiconductor (CMOS) lock-in pixel to observe stimulated Raman scattering (SRS) using a high speed lateral electric field modulator (LEFM) for photo-generated charges and in-pixel readout circuits is presented. An effective SRS signal generated after the SRS process is very small and needs to be extracted from an extremely large offset due to a probing laser signal. In order to suppress the offset components while amplifying high-frequency modulated small SRS signal components, the lock-in pixel uses a high-speed LEFM for demodulating the SRS signal, resistor-capacitor low-pass filter (RC-LPF) and switched-capacitor (SC) integrator with a fully CMOS differential amplifier. AC (modulated) components remained in the RC-LPF outputs are eliminated by the phase-adjusted sampling with the SC integrator and the demodulated DC (unmodulated) components due to the SRS signal are integrated over many samples in the SC integrator. In order to suppress further the residual offset and the low frequency noise (1/f noise) components, a double modulation technique is introduced in the SRS signal measurements, where the phase of high-frequency modulated laser beam before irradiation of a specimen is modulated at an intermediate frequency and the demodulation is done at the lock-in pixel output. A prototype chip for characterizing the SRS lock-in pixel is implemented and a successful operation is demonstrated. The reduction effects of residual offset and 1/f noise components are confirmed by the measurements. A ratio of the detected small SRS to offset a signal of less than 10(-)⁵ is experimentally demonstrated, and the SRS spectrum of a Benzonitrile sample is successfully observed.

Sol-Gel Zinc Oxide Humidity Sensors Integrated with a Ring Oscillator Circuit On-a-Chip

PubMed Central

Yang, Ming-Zhi; Dai, Ching-Liang; Wu, Chyan-Chyi

2014-01-01

The study develops an integrated humidity microsensor fabricated using the commercial 0.18 μm complementary metal oxide semiconductor (CMOS) process. The integrated humidity sensor consists of a humidity sensor and a ring oscillator circuit on-a-chip. The humidity sensor is composed of a sensitive film and branch interdigitated electrodes. The sensitive film is zinc oxide prepared by sol-gel method. After completion of the CMOS process, the sensor requires a post-process to remove the sacrificial oxide layer and to coat the zinc oxide film on the interdigitated electrodes. The capacitance of the sensor changes when the sensitive film adsorbs water vapor. The circuit is used to convert the capacitance of the humidity sensor into the oscillation frequency output. Experimental results show that the output frequency of the sensor changes from 84.3 to 73.4 MHz at 30 °C as the humidity increases 40 to 90 %RH. PMID:25353984

NV-CMOS HD camera for day/night imaging

NASA Astrophysics Data System (ADS)

Vogelsong, T.; Tower, J.; Sudol, Thomas; Senko, T.; Chodelka, D.

2014-06-01

SRI International (SRI) has developed a new multi-purpose day/night video camera with low-light imaging performance comparable to an image intensifier, while offering the size, weight, ruggedness, and cost advantages enabled by the use of SRI's NV-CMOS HD digital image sensor chip. The digital video output is ideal for image enhancement, sharing with others through networking, video capture for data analysis, or fusion with thermal cameras. The camera provides Camera Link output with HD/WUXGA resolution of 1920 x 1200 pixels operating at 60 Hz. Windowing to smaller sizes enables operation at higher frame rates. High sensitivity is achieved through use of backside illumination, providing high Quantum Efficiency (QE) across the visible and near infrared (NIR) bands (peak QE <90%), as well as projected low noise (<2h+) readout. Power consumption is minimized in the camera, which operates from a single 5V supply. The NVCMOS HD camera provides a substantial reduction in size, weight, and power (SWaP) , ideal for SWaP-constrained day/night imaging platforms such as UAVs, ground vehicles, fixed mount surveillance, and may be reconfigured for mobile soldier operations such as night vision goggles and weapon sights. In addition the camera with the NV-CMOS HD imager is suitable for high performance digital cinematography/broadcast systems, biofluorescence/microscopy imaging, day/night security and surveillance, and other high-end applications which require HD video imaging with high sensitivity and wide dynamic range. The camera comes with an array of lens mounts including C-mount and F-mount. The latest test data from the NV-CMOS HD camera will be presented.

A Biosensor-CMOS Platform and Integrated Readout Circuit in 0.18-μm CMOS Technology for Cancer Biomarker Detection.

PubMed

Alhoshany, Abdulaziz; Sivashankar, Shilpa; Mashraei, Yousof; Omran, Hesham; Salama, Khaled N

2017-08-23

This paper presents a biosensor-CMOS platform for measuring the capacitive coupling of biorecognition elements. The biosensor is designed, fabricated, and tested for the detection and quantification of a protein that reveals the presence of early-stage cancer. For the first time, the spermidine/spermine N1 acetyltransferase (SSAT) enzyme has been screened and quantified on the surface of a capacitive sensor. The sensor surface is treated to immobilize antibodies, and the baseline capacitance of the biosensor is reduced by connecting an array of capacitors in series for fixed exposure area to the analyte. A large sensing area with small baseline capacitance is implemented to achieve a high sensitivity to SSAT enzyme concentrations. The sensed capacitance value is digitized by using a 12-bit highly digital successive-approximation capacitance-to-digital converter that is implemented in a 0.18 μm CMOS technology. The readout circuit operates in the near-subthreshold regime and provides power and area efficient operation. The capacitance range is 16.137 pF with a 4.5 fF absolute resolution, which adequately covers the concentrations of 10 mg/L, 5 mg/L, 2.5 mg/L, and 1.25 mg/L of the SSAT enzyme. The concentrations were selected as a pilot study, and the platform was shown to demonstrate high sensitivity for SSAT enzymes on the surface of the capacitive sensor. The tested prototype demonstrated 42.5 μS of measurement time and a total power consumption of 2.1 μW.

CMOS Image Sensor and System for Imaging Hemodynamic Changes in Response to Deep Brain Stimulation.

PubMed

Zhang, Xiao; Noor, Muhammad S; McCracken, Clinton B; Kiss, Zelma H T; Yadid-Pecht, Orly; Murari, Kartikeya

2016-06-01

Deep brain stimulation (DBS) is a therapeutic intervention used for a variety of neurological and psychiatric disorders, but its mechanism of action is not well understood. It is known that DBS modulates neural activity which changes metabolic demands and thus the cerebral circulation state. However, it is unclear whether there are correlations between electrophysiological, hemodynamic and behavioral changes and whether they have any implications for clinical benefits. In order to investigate these questions, we present a miniaturized system for spectroscopic imaging of brain hemodynamics. The system consists of a 144 ×144, [Formula: see text] pixel pitch, high-sensitivity, analog-output CMOS imager fabricated in a standard 0.35 μm CMOS process, along with a miniaturized imaging system comprising illumination, focusing, analog-to-digital conversion and μSD card based data storage. This enables stand alone operation without a computer, nor electrical or fiberoptic tethers. To achieve high sensitivity, the pixel uses a capacitive transimpedance amplifier (CTIA). The nMOS transistors are in the pixel while pMOS transistors are column-parallel, resulting in a fill factor (FF) of 26%. Running at 60 fps and exposed to 470 nm light, the CMOS imager has a minimum detectable intensity of 2.3 nW/cm(2) , a maximum signal-to-noise ratio (SNR) of 49 dB at 2.45 μW/cm(2) leading to a dynamic range (DR) of 61 dB while consuming 167 μA from a 3.3 V supply. In anesthetized rats, the system was able to detect temporal, spatial and spectral hemodynamic changes in response to DBS.

A Biosensor-CMOS Platform and Integrated Readout Circuit in 0.18-μm CMOS Technology for Cancer Biomarker Detection

PubMed Central

Alhoshany, Abdulaziz; Sivashankar, Shilpa; Mashraei, Yousof; Omran, Hesham; Salama, Khaled N.

2017-01-01

This paper presents a biosensor-CMOS platform for measuring the capacitive coupling of biorecognition elements. The biosensor is designed, fabricated, and tested for the detection and quantification of a protein that reveals the presence of early-stage cancer. For the first time, the spermidine/spermine N1 acetyltransferase (SSAT) enzyme has been screened and quantified on the surface of a capacitive sensor. The sensor surface is treated to immobilize antibodies, and the baseline capacitance of the biosensor is reduced by connecting an array of capacitors in series for fixed exposure area to the analyte. A large sensing area with small baseline capacitance is implemented to achieve a high sensitivity to SSAT enzyme concentrations. The sensed capacitance value is digitized by using a 12-bit highly digital successive-approximation capacitance-to-digital converter that is implemented in a 0.18 μm CMOS technology. The readout circuit operates in the near-subthreshold regime and provides power and area efficient operation. The capacitance range is 16.137 pF with a 4.5 fF absolute resolution, which adequately covers the concentrations of 10 mg/L, 5 mg/L, 2.5 mg/L, and 1.25 mg/L of the SSAT enzyme. The concentrations were selected as a pilot study, and the platform was shown to demonstrate high sensitivity for SSAT enzymes on the surface of the capacitive sensor. The tested prototype demonstrated 42.5 μS of measurement time and a total power consumption of 2.1 μW. PMID:28832523

Charge shielding in the In-situ Storage Image Sensor for a vertex detector at the ILC

NASA Astrophysics Data System (ADS)

Zhang, Z.; Stefanov, K. D.; Bailey, D.; Banda, Y.; Buttar, C.; Cheplakov, A.; Cussans, D.; Damerell, C.; Devetak, E.; Fopma, J.; Foster, B.; Gao, R.; Gillman, A.; Goldstein, J.; Greenshaw, T.; Grimes, M.; Halsall, R.; Harder, K.; Hawes, B.; Hayrapetyan, K.; Heath, H.; Hillert, S.; Jackson, D.; Pinto Jayawardena, T.; Jeffery, B.; John, J.; Johnson, E.; Kundu, N.; Laing, A.; Lastovicka, T.; Lau, W.; Li, Y.; Lintern, A.; Lynch, C.; Mandry, S.; Martin, V.; Murray, P.; Nichols, A.; Nomerotski, A.; Page, R.; Parkes, C.; Perry, C.; O'Shea, V.; Sopczak, A.; Tabassam, H.; Thomas, S.; Tikkanen, T.; Velthuis, J.; Walsh, R.; Woolliscroft, T.; Worm, S.

2009-08-01

The Linear Collider Flavour Identification (LCFI) collaboration has successfully developed the first prototype of a novel particle detector, the In-situ Storage Image Sensor (ISIS). This device ideally suits the challenging requirements for the vertex detector at the future International Linear Collider (ILC), combining the charge storing capabilities of the Charge-Coupled Devices (CCD) with readout commonly used in CMOS imagers. The ISIS avoids the need for high-speed readout and offers low power operation combined with low noise, high immunity to electromagnetic interference and increased radiation hardness compared to typical CCDs. The ISIS is one of the most promising detector technologies for vertexing at the ILC. In this paper we describe the measurements on the charge-shielding properties of the p-well, which is used to protect the storage register from parasitic charge collection and is at the core of device's operation. We show that the p-well can suppress the parasitic charge collection by almost two orders of magnitude, satisfying the requirements for the application.

Contact CMOS imaging of gaseous oxygen sensor array

PubMed Central

Daivasagaya, Daisy S.; Yao, Lei; Yi Yung, Ka; Hajj-Hassan, Mohamad; Cheung, Maurice C.; Chodavarapu, Vamsy P.; Bright, Frank V.

2014-01-01

We describe a compact luminescent gaseous oxygen (O2) sensor microsystem based on the direct integration of sensor elements with a polymeric optical filter and placed on a low power complementary metal-oxide semiconductor (CMOS) imager integrated circuit (IC). The sensor operates on the measurement of excited-state emission intensity of O2-sensitive luminophore molecules tris(4,7-diphenyl-1,10-phenanthroline) ruthenium(II) ([Ru(dpp)3]2+) encapsulated within sol–gel derived xerogel thin films. The polymeric optical filter is made with polydimethylsiloxane (PDMS) that is mixed with a dye (Sudan-II). The PDMS membrane surface is molded to incorporate arrays of trapezoidal microstructures that serve to focus the optical sensor signals on to the imager pixels. The molded PDMS membrane is then attached with the PDMS color filter. The xerogel sensor arrays are contact printed on top of the PDMS trapezoidal lens-like microstructures. The CMOS imager uses a 32 × 32 (1024 elements) array of active pixel sensors and each pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. Correlated double sampling circuit, pixel address, digital control and signal integration circuits are also implemented on-chip. The CMOS imager data is read out as a serial coded signal. The CMOS imager consumes a static power of 320 µW and an average dynamic power of 625 µW when operating at 100 Hz sampling frequency and 1.8 V DC. This CMOS sensor system provides a useful platform for the development of miniaturized optical chemical gas sensors. PMID:24493909

Contact CMOS imaging of gaseous oxygen sensor array.

PubMed

Daivasagaya, Daisy S; Yao, Lei; Yi Yung, Ka; Hajj-Hassan, Mohamad; Cheung, Maurice C; Chodavarapu, Vamsy P; Bright, Frank V

2011-10-01

We describe a compact luminescent gaseous oxygen (O 2 ) sensor microsystem based on the direct integration of sensor elements with a polymeric optical filter and placed on a low power complementary metal-oxide semiconductor (CMOS) imager integrated circuit (IC). The sensor operates on the measurement of excited-state emission intensity of O 2 -sensitive luminophore molecules tris(4,7-diphenyl-1,10-phenanthroline) ruthenium(II) ([Ru(dpp) 3 ] 2+ ) encapsulated within sol-gel derived xerogel thin films. The polymeric optical filter is made with polydimethylsiloxane (PDMS) that is mixed with a dye (Sudan-II). The PDMS membrane surface is molded to incorporate arrays of trapezoidal microstructures that serve to focus the optical sensor signals on to the imager pixels. The molded PDMS membrane is then attached with the PDMS color filter. The xerogel sensor arrays are contact printed on top of the PDMS trapezoidal lens-like microstructures. The CMOS imager uses a 32 × 32 (1024 elements) array of active pixel sensors and each pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. Correlated double sampling circuit, pixel address, digital control and signal integration circuits are also implemented on-chip. The CMOS imager data is read out as a serial coded signal. The CMOS imager consumes a static power of 320 µW and an average dynamic power of 625 µW when operating at 100 Hz sampling frequency and 1.8 V DC. This CMOS sensor system provides a useful platform for the development of miniaturized optical chemical gas sensors.

Capacitively coupled hybrid pixel assemblies for the CLIC vertex detector

NASA Astrophysics Data System (ADS)

Tehrani, N. Alipour; Arfaoui, S.; Benoit, M.; Dannheim, D.; Dette, K.; Hynds, D.; Kulis, S.; Perić, I.; Petrič, M.; Redford, S.; Sicking, E.; Valerio, P.

2016-07-01

The vertex detector at the proposed CLIC multi-TeV linear e+e- collider must have minimal material content and high spatial resolution, combined with accurate time-stamping to cope with the expected high rate of beam-induced backgrounds. One of the options being considered is the use of active sensors implemented in a commercial high-voltage CMOS process, capacitively coupled to hybrid pixel ASICs. A prototype of such an assembly, using two custom designed chips (CCPDv3 as active sensor glued to a CLICpix readout chip), has been characterised both in the lab and in beam tests at the CERN SPS using 120 GeV/c positively charged hadrons. Results of these characterisation studies are presented both for single and dual amplification stages in the active sensor, where efficiencies of greater than 99% have been achieved at -60 V substrate bias, with a single hit resolution of 6.1 μm . Pixel cross-coupling results are also presented, showing the sensitivity to placement precision and planarity of the glue layer.

Novel active signal compression in low-noise analog readout at future X-ray FEL facilities

NASA Astrophysics Data System (ADS)

Manghisoni, M.; Comotti, D.; Gaioni, L.; Lodola, L.; Ratti, L.; Re, V.; Traversi, G.; Vacchi, C.

2015-04-01

This work presents the design of a low-noise front-end implementing a novel active signal compression technique. This feature can be exploited in the design of analog readout channels for application to the next generation free electron laser (FEL) experiments. The readout architecture includes the low-noise charge sensitive amplifier (CSA) with dynamic signal compression, a time variant shaper used to process the signal at the preamplifier output and a 10-bit successive approximation register (SAR) analog-to-digital converter (ADC). The channel will be operated in such a way to cope with the high frame rate (exceeding 1 MHz) foreseen for future XFEL machines. The choice of a 65 nm CMOS technology has been made in order to include all the building blocks in the target pixel pitch of 100 μm. This work has been carried out in the frame of the PixFEL Project funded by the Istituto Nazionale di Fisica Nucleare (INFN), Italy.

CMOS Imaging of Pin-Printed Xerogel-Based Luminescent Sensor Microarrays.

PubMed

Yao, Lei; Yung, Ka Yi; Khan, Rifat; Chodavarapu, Vamsy P; Bright, Frank V

2010-12-01

We present the design and implementation of a luminescence-based miniaturized multisensor system using pin-printed xerogel materials which act as host media for chemical recognition elements. We developed a CMOS imager integrated circuit (IC) to image the luminescence response of the xerogel-based sensor array. The imager IC uses a 26 × 20 (520 elements) array of active pixel sensors and each active pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. The imager includes a correlated double sampling circuit and pixel address/digital control circuit; the image data is read-out as coded serial signal. The sensor system uses a light-emitting diode (LED) to excite the target analyte responsive luminophores doped within discrete xerogel-based sensor elements. As a prototype, we developed a 4 × 4 (16 elements) array of oxygen (O 2 ) sensors. Each group of 4 sensor elements in the array (arranged in a row) is designed to provide a different and specific sensitivity to the target gaseous O 2 concentration. This property of multiple sensitivities is achieved by using a strategic mix of two oxygen sensitive luminophores ([Ru(dpp) 3 ] 2+ and ([Ru(bpy) 3 ] 2+ ) in each pin-printed xerogel sensor element. The CMOS imager consumes an average power of 8 mW operating at 1 kHz sampling frequency driven at 5 V. The developed prototype system demonstrates a low cost and miniaturized luminescence multisensor system.

Meteor Film Recording with Digital Film Cameras with large CMOS Sensors

NASA Astrophysics Data System (ADS)

Slansky, P. C.

2016-12-01

In this article the author combines his professional know-how about cameras for film and television production with his amateur astronomy activities. Professional digital film cameras with high sensitivity are still quite rare in astronomy. One reason for this may be their costs of up to 20 000 and more (camera body only). In the interim, however,consumer photo cameras with film mode and very high sensitivity have come to the market for about 2 000 EUR. In addition, ultra-high sensitive professional film cameras, that are very interesting for meteor observation, have been introduced to the market. The particular benefits of digital film cameras with large CMOS sensors, including photo cameras with film recording function, for meteor recording are presented by three examples: a 2014 Camelopardalid, shot with a Canon EOS C 300, an exploding 2014 Aurigid, shot with a Sony alpha7S, and the 2016 Perseids, shot with a Canon ME20F-SH. All three cameras use large CMOS sensors; "large" meaning Super-35 mm, the classic 35 mm film format (24x13.5 mm, similar to APS-C size), or full format (36x24 mm), the classic 135 photo camera format. Comparisons are made to the widely used cameras with small CCD sensors, such as Mintron or Watec; "small" meaning 12" (6.4x4.8 mm) or less. Additionally, special photographic image processing of meteor film recordings is discussed.

Design of the low area monotonic trim DAC in 40 nm CMOS technology for pixel readout chips

NASA Astrophysics Data System (ADS)

Drozd, A.; Szczygiel, R.; Maj, P.; Satlawa, T.; Grybos, P.

2014-12-01

The recent research in hybrid pixel detectors working in single photon counting mode focuses on nanometer or 3D technologies which allow making pixels smaller and implementing more complex solutions in each of the pixels. Usually single pixel in readout electronics for X-ray detection comprises of charge amplifier, shaper and discriminator that allow classification of events occurring at the detector as true or false hits by comparing amplitude of the signal obtained with threshold voltage, which minimizes the influence of noise effects. However, making the pixel size smaller often causes problems with pixel to pixel uniformity and additional effects like charge sharing become more visible. To improve channel-to-channel uniformity or implement an algorithm for charge sharing effect minimization, small area trimming DACs working in each pixel independently are necessary. However, meeting the requirement of small area often results in poor linearity and even non-monotonicity. In this paper we present a novel low-area thermometer coded 6-bit DAC implemented in 40 nm CMOS technology. Monte Carlo simulations were performed on the described design proving that under all conditions designed DAC is inherently monotonic. Presented DAC was implemented in the prototype readout chip with 432 pixels working in single photon counting mode, with two trimming DACs in each pixel. Each DAC occupies the area of 8 μm × 18.5 μm. Measurements and chips' tests were performed to obtain reliable statistical results.

Homogeneous 2D MoTe2 p-n Junctions and CMOS Inverters formed by Atomic-Layer-Deposition-Induced Doping.

PubMed

Lim, June Yeong; Pezeshki, Atiye; Oh, Sehoon; Kim, Jin Sung; Lee, Young Tack; Yu, Sanghyuck; Hwang, Do Kyung; Lee, Gwan-Hyoung; Choi, Hyoung Joon; Im, Seongil

2017-08-01

Recently, α-MoTe 2 , a 2D transition-metal dichalcogenide (TMD), has shown outstanding properties, aiming at future electronic devices. Such TMD structures without surface dangling bonds make the 2D α-MoTe 2 a more favorable candidate than conventional 3D Si on the scale of a few nanometers. The bandgap of thin α-MoTe 2 appears close to that of Si and is quite smaller than those of other typical TMD semiconductors. Even though there have been a few attempts to control the charge-carrier polarity of MoTe 2 , functional devices such as p-n junction or complementary metal-oxide-semiconductor (CMOS) inverters have not been reported. Here, we demonstrate a 2D CMOS inverter and p-n junction diode in a single α-MoTe 2 nanosheet by a straightforward selective doping technique. In a single α-MoTe 2 flake, an initially p-doped channel is selectively converted to an n-doped region with high electron mobility of 18 cm 2 V -1 s -1 by atomic-layer-deposition-induced H-doping. The ultrathin CMOS inverter exhibits a high DC voltage gain of 29, an AC gain of 18 at 1 kHz, and a low static power consumption of a few nanowatts. The results show a great potential of α-MoTe 2 for future electronic devices based on 2D semiconducting materials. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Radiation damage caused by cold neutrons in boron doped CMOS active pixel sensors

NASA Astrophysics Data System (ADS)

Linnik, B.; Bus, T.; Deveaux, M.; Doering, D.; Kudejova, P.; Wagner, F. M.; Yazgili, A.; Stroth, J.

2017-05-01

CMOS Monolithic Active Pixel Sensors (MAPS) are considered as an emerging technology in the field of charged particle tracking. They will be used in the vertex detectors of experiments like STAR, CBM and ALICE and are considered for the ILC and the tracker of ATLAS. In those applications, the sensors are exposed to sizeable radiation doses. While the tolerance of MAPS to ionizing radiation and fast hadrons is well known, the damage caused by low energy neutrons was not studied so far. Those slow neutrons may initiate nuclear fission of 10B dopants found in the B-doped silicon active medium of MAPS. This effect was expected to create an unknown amount of radiation damage beyond the predictions of the NIEL (Non Ionizing Energy Loss) model for pure silicon. We estimate the impact of this effect by calculating the additional NIEL created by this fission. Moreover, we show first measured data for CMOS sensors which were irradiated with cold neutrons. The empirical results contradict the prediction of the updated NIEL model both, qualitatively and quantitatively: the sensors irradiated with slow neutrons show an unexpected and strong acceptor removal, which is not observed in sensors irradiated with MeV neutrons.

Hyperspectral Image-Based Night-Time Vehicle Light Detection Using Spectral Normalization and Distance Mapper for Intelligent Headlight Control

PubMed Central

Kim, Heekang; Kwon, Soon; Kim, Sungho

2016-01-01

This paper proposes a vehicle light detection method using a hyperspectral camera instead of a Charge-Coupled Device (CCD) or Complementary metal-Oxide-Semiconductor (CMOS) camera for adaptive car headlamp control. To apply Intelligent Headlight Control (IHC), the vehicle headlights need to be detected. Headlights are comprised from a variety of lighting sources, such as Light Emitting Diodes (LEDs), High-intensity discharge (HID), and halogen lamps. In addition, rear lamps are made of LED and halogen lamp. This paper refers to the recent research in IHC. Some problems exist in the detection of headlights, such as erroneous detection of street lights or sign lights and the reflection plate of ego-car from CCD or CMOS images. To solve these problems, this study uses hyperspectral images because they have hundreds of bands and provide more information than a CCD or CMOS camera. Recent methods to detect headlights used the Spectral Angle Mapper (SAM), Spectral Correlation Mapper (SCM), and Euclidean Distance Mapper (EDM). The experimental results highlight the feasibility of the proposed method in three types of lights (LED, HID, and halogen). PMID:27399720

Implementation of material decomposition using an EMCCD and CMOS-based micro-CT system.

PubMed

Podgorsak, Alexander R; Nagesh, Sv Setlur; Bednarek, Daniel R; Rudin, Stephen; Ionita, Ciprian N

2017-02-11

This project assessed the effectiveness of using two different detectors to obtain dual-energy (DE) micro-CT data for the carrying out of material decomposition. A micro-CT coupled to either a complementary metal-oxide semiconductor (CMOS) or an electron multiplying CCD (EMCCD) detector was used to acquire image data of a 3D-printed phantom with channels filled with different materials. At any instance, materials such as iohexol contrast agent, water, and platinum were selected to make up the scanned object. DE micro-CT data was acquired, and slices of the scanned object were differentiated by material makeup. The success of the decomposition was assessed quantitatively through the computation of percentage normalized root-mean-square error (%NRMSE). Our results indicate a successful decomposition of iohexol for both detectors (%NRMSE values of 1.8 for EMCCD, 2.4 for CMOS), as well as platinum (%NRMSE value of 4.7). The CMOS detector performed material decomposition on air and water on average with 7 times more %NRMSE, possibly due to the decreased sensitivity of the CMOS system. Material decomposition showed the potential to differentiate between materials such as the iohexol and platinum, perhaps opening the door for its use in the neurovascular anatomical region. Work supported by Toshiba America Medical Systems, and partially supported by NIH grant 2R01EB002873.

Implementation of material decomposition using an EMCCD and CMOS-based micro-CT system

NASA Astrophysics Data System (ADS)

Podgorsak, Alexander R.; Nagesh, S. V. Setlur; Bednarek, Daniel R.; Rudin, Stephen; Ionita, Ciprian N.

2017-03-01

This project assessed the effectiveness of using two different detectors to obtain dual-energy (DE) micro-CT data for the carrying out of material decomposition. A micro-CT coupled to either a complementary metal-oxide semiconductor (CMOS) or an electron multiplying CCD (EMCCD) detector was used to acquire image data of a 3D-printed phantom with channels filled with different materials. At any instance, materials such as iohexol contrast agent, water, and platinum were selected to make up the scanned object. DE micro-CT data was acquired, and slices of the scanned object were differentiated by material makeup. The success of the decomposition was assessed quantitatively through the computation of percentage normalized root-mean-square error (%NRMSE). Our results indicate a successful decomposition of iohexol for both detectors (%NRMSE values of 1.8 for EMCCD, 2.4 for CMOS), as well as platinum (%NRMSE value of 4.7). The CMOS detector performed material decomposition on air and water on average with 7 times more %NRMSE, possibly due to the decreased sensitivity of the CMOS system. Material decomposition showed the potential to differentiate between materials such as the iohexol and platinum, perhaps opening the door for its use in the neurovascular anatomical region. Work supported by Toshiba America Medical Systems, and partially supported by NIH grant 2R01EB002873.

Capacitive Micro Pressure Sensor Integrated with a Ring Oscillator Circuit on Chip

PubMed Central

Dai, Ching-Liang; Lu, Po-Wei; Chang, Chienliu; Liu, Cheng-Yang

2009-01-01

The study investigates a capacitive micro pressure sensor integrated with a ring oscillator circuit on a chip. The integrated capacitive pressure sensor is fabricated using the commercial CMOS (complementary metal oxide semiconductor) process and a post-process. The ring oscillator is employed to convert the capacitance of the pressure sensor into the frequency output. The pressure sensor consists of 16 sensing cells in parallel. Each sensing cell contains a top electrode and a lower electrode, and the top electrode is a sandwich membrane. The pressure sensor needs a post-CMOS process to release the membranes after completion of the CMOS process. The post-process uses etchants to etch the sacrificial layers, and to release the membranes. The advantages of the post-process include easy execution and low cost. Experimental results reveal that the pressure sensor has a high sensitivity of 7 Hz/Pa in the pressure range of 0–300 kPa. PMID:22303167

Capacitive micro pressure sensor integrated with a ring oscillator circuit on chip.

PubMed

Dai, Ching-Liang; Lu, Po-Wei; Chang, Chienliu; Liu, Cheng-Yang

2009-01-01

The study investigates a capacitive micro pressure sensor integrated with a ring oscillator circuit on a chip. The integrated capacitive pressure sensor is fabricated using the commercial CMOS (complementary metal oxide semiconductor) process and a post-process. The ring oscillator is employed to convert the capacitance of the pressure sensor into the frequency output. The pressure sensor consists of 16 sensing cells in parallel. Each sensing cell contains a top electrode and a lower electrode, and the top electrode is a sandwich membrane. The pressure sensor needs a post-CMOS process to release the membranes after completion of the CMOS process. The post-process uses etchants to etch the sacrificial layers, and to release the membranes. The advantages of the post-process include easy execution and low cost. Experimental results reveal that the pressure sensor has a high sensitivity of 7 Hz/Pa in the pressure range of 0-300 kPa.

Si light-emitting device in integrated photonic CMOS ICs

NASA Astrophysics Data System (ADS)

Xu, Kaikai; Snyman, Lukas W.; Aharoni, Herzl

2017-07-01

The motivation for integrated Si optoelectronics is the creation of low-cost photonics for mass-market applications. Especially, the growing demand for sensitive biochemical sensors in the environmental control or medicine leads to the development of integrated high resolution sensors. Here CMOS-compatible Si light-emitting device structures are presented for investigating the effect of various depletion layer profiles and defect engineering on the photonic transition in the 1.4-2.8 eV. A novel Si device is proposed to realize both a two-terminal Si-diode light-emitting device and a three-terminal Si gate-controlled diode light-emitting device in the same device structure. In addition to the spectral analysis, differences between two-terminal and three-terminal devices are discussed, showing the light emission efficiency change. The proposed Si optical source may find potential applications in micro-photonic systems and micro-optoelectro-mechanical systems (MOEMS) in CMOS integrated circuitry.

Real-time detection of fast and thermal neutrons in radiotherapy with CMOS sensors.

PubMed

Arbor, Nicolas; Higueret, Stephane; Elazhar, Halima; Combe, Rodolphe; Meyer, Philippe; Dehaynin, Nicolas; Taupin, Florence; Husson, Daniel

2017-03-07

The peripheral dose distribution is a growing concern for the improvement of new external radiation modalities. Secondary particles, especially photo-neutrons produced by the accelerator, irradiate the patient more than tens of centimeters away from the tumor volume. However the out-of-field dose is still not estimated accurately by the treatment planning softwares. This study demonstrates the possibility of using a specially designed CMOS sensor for fast and thermal neutron monitoring in radiotherapy. The 14 microns-thick sensitive layer and the integrated electronic chain of the CMOS are particularly suitable for real-time measurements in γ/n mixed fields. An experimental field size dependency of the fast neutron production rate, supported by Monte Carlo simulations and CR-39 data, has been observed. This dependency points out the potential benefits of a real-time monitoring of fast and thermal neutron during beam intensity modulated radiation therapies.

Nano-Multiplication-Region Avalanche Photodiodes and Arrays

NASA Technical Reports Server (NTRS)

Zheng, Xinyu; Pain, Bedabrata; Cunningham, Thomas

2008-01-01

Nano-multiplication-region avalanche photodiodes (NAPDs), and imaging arrays of NAPDs integrated with complementary metal oxide/semiconductor (CMOS) active-pixel-sensor integrated circuitry, are being developed for applications in which there are requirements for high-sensitivity (including photoncounting) detection and imaging at wavelengths from about 250 to 950 nm. With respect to sensitivity and to such other characteristics as speed, geometric array format, radiation hardness, power demand of associated circuitry, size, weight, and robustness, NAPDs and arrays thereof are expected to be superior to prior photodetectors and arrays including CMOS active-pixel sensors (APSs), charge-coupled devices (CCDs), traditional APDs, and microchannelplate/ CCD combinations. Figure 1 depicts a conceptual NAPD array, integrated with APS circuitry, fabricated on a thick silicon-on-insulator wafer (SOI). Figure 2 presents selected aspects of the structure of a typical single pixel, which would include a metal oxide/semiconductor field-effect transistor (MOSFET) integrated with the NAPD. The NAPDs would reside in silicon islands formed on the buried oxide (BOX) layer of the SOI wafer. The silicon islands would be surrounded by oxide-filled insulation trenches, which, together with the BOX layer, would constitute an oxide embedding structure. There would be two kinds of silicon islands: NAPD islands for the NAPDs and MOSFET islands for in-pixel and global CMOS circuits. Typically, the silicon islands would be made between 5 and 10 m thick, but, if necessary, the thickness could be chosen outside this range. The side walls of the silicon islands would be heavily doped with electron-acceptor impurities (p+-doped) to form anodes for the photodiodes and guard layers for the MOSFETs. A nanoscale reach-through structure at the front (top in the figures) central position of each NAPD island would contain the APD multiplication region. Typically, the reach-through structure would be about 0.1 microns in diameter and between 0.3 and 0.4 nm high. The top layer in the reach-through structure would be heavily doped with electron-donor impurities (n+-doped) to make it act as a cathode. A layer beneath the cathode, between 0.1 and 0.2 nm thick, would be p-doped to a concentration .10(exp 17)cu cm. A thin n+-doped polysilicon pad would be formed on the top of the cathode to protect the cathode against erosion during a metal-silicon alloying step that would be part of the process of fabricating the array.

CMOS Active Pixel Sensor Star Tracker with Regional Electronic Shutter

NASA Technical Reports Server (NTRS)

Yadid-Pecht, Orly; Pain, Bedabrata; Staller, Craig; Clark, Christopher; Fossum, Eric

1996-01-01

The guidance system in a spacecraft determines spacecraft attitude by matching an observed star field to a star catalog....An APS(active pixel sensor)-based system can reduce mass and power consumption and radiation effects compared to a CCD(charge-coupled device)-based system...This paper reports an APS (active pixel sensor) with locally variable times, achieved through individual pixel reset (IPR).

Vertical Isolation for Photodiodes in CMOS Imagers

NASA Technical Reports Server (NTRS)

Pain, Bedabrata

2008-01-01

In a proposed improvement in complementary metal oxide/semi conduct - or (CMOS) image detectors, two additional implants in each pixel would effect vertical isolation between the metal oxide/semiconductor field-effect transistors (MOSFETs) and the photodiode of the pixel. This improvement is expected to enable separate optimization of the designs of the photodiode and the MOSFETs so as to optimize their performances independently of each other. The purpose to be served by enabling this separate optimization is to eliminate or vastly reduce diffusion cross-talk, thereby increasing sensitivity, effective spatial resolution, and color fidelity while reducing noise.

A CMOS smart temperature and humidity sensor with combined readout.

PubMed

Eder, Clemens; Valente, Virgilio; Donaldson, Nick; Demosthenous, Andreas

2014-09-16

A fully-integrated complementary metal-oxide semiconductor (CMOS) sensor for combined temperature and humidity measurements is presented. The main purpose of the device is to monitor the hermeticity of micro-packages for implanted integrated circuits and to ensure their safe operation by monitoring the operating temperature and humidity on-chip. The smart sensor has two modes of operation, in which either the temperature or humidity is converted into a digital code representing a frequency ratio between two oscillators. This ratio is determined by the ratios of the timing capacitances and bias currents in both oscillators. The reference oscillator is biased by a current whose temperature dependency is complementary to the proportional to absolute temperature (PTAT) current. For the temperature measurement, this results in an exceptional normalized sensitivity of about 0.77%/°C at the accepted expense of reduced linearity. The humidity sensor is a capacitor, whose value varies linearly with relative humidity (RH) with a normalized sensitivity of 0.055%/% RH. For comparison, two versions of the humidity sensor with an area of either 0.2 mm2 or 1.2 mm2 were fabricated in a commercial 0.18 μm CMOS process. The on-chip readout electronics operate from a 5 V power supply and consume a current of approximately 85 µA.

Enhancing the far-UV sensitivity of silicon CMOS imaging arrays

NASA Astrophysics Data System (ADS)

Retherford, K. D.; Bai, Yibin; Ryu, Kevin K.; Gregory, J. A.; Welander, Paul B.; Davis, Michael W.; Greathouse, Thomas K.; Winter, Gregory S.; Suntharalingam, Vyshnavi; Beletic, James W.

2014-07-01

We report our progress toward optimizing backside-illuminated silicon PIN CMOS devices developed by Teledyne Imaging Sensors (TIS) for far-UV planetary science applications. This project was motivated by initial measurements at Southwest Research Institute (SwRI) of the far-UV responsivity of backside-illuminated silicon PIN photodiode test structures described in Bai et al., SPIE, 2008, which revealed a promising QE in the 100-200 nm range as reported in Davis et al., SPIE, 2012. Our effort to advance the capabilities of thinned silicon wafers capitalizes on recent innovations in molecular beam epitaxy (MBE) doping processes. Key achievements to date include: 1) Representative silicon test wafers were fabricated by TIS, and set up for MBE processing at MIT Lincoln Laboratory (LL); 2) Preliminary far-UV detector QE simulation runs were completed to aid MBE layer design; 3) Detector fabrication was completed through the pre-MBE step; and 4) Initial testing of the MBE doping process was performed on monitoring wafers, with detailed quality assessments. Early results suggest that potential challenges in optimizing the UV-sensitivity of silicon PIN type CMOS devices, compared with similar UV enhancement methods established for CCDs, have been mitigated through our newly developed methods. We will discuss the potential advantages of our approach and briefly describe future development steps.

Charge collection properties in an irradiated pixel sensor built in a thick-film HV-SOI process

NASA Astrophysics Data System (ADS)

Hiti, B.; Cindro, V.; Gorišek, A.; Hemperek, T.; Kishishita, T.; Kramberger, G.; Krüger, H.; Mandić, I.; Mikuž, M.; Wermes, N.; Zavrtanik, M.

2017-10-01

Investigation of HV-CMOS sensors for use as a tracking detector in the ATLAS experiment at the upgraded LHC (HL-LHC) has recently been an active field of research. A potential candidate for a pixel detector built in Silicon-On-Insulator (SOI) technology has already been characterized in terms of radiation hardness to TID (Total Ionizing Dose) and charge collection after a moderate neutron irradiation. In this article we present results of an extensive irradiation hardness study with neutrons up to a fluence of 1× 1016 neq/cm2. Charge collection in a passive pixelated structure was measured by Edge Transient Current Technique (E-TCT). The evolution of the effective space charge concentration was found to be compliant with the acceptor removal model, with the minimum of the space charge concentration being reached after 5× 1014 neq/cm2. An investigation of the in-pixel uniformity of the detector response revealed parasitic charge collection by the epitaxial silicon layer characteristic for the SOI design. The results were backed by a numerical simulation of charge collection in an equivalent detector layout.

Conduction band offset at GeO{sub 2}/Ge interface determined by internal photoemission and charge-corrected x-ray photoelectron spectroscopies

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zhang, W. F.; Nishimula, T.; Nagashio, K.

2013-03-11

We report a consistent conduction band offset (CBO) at a GeO{sub 2}/Ge interface determined by internal photoemission spectroscopy (IPE) and charge-corrected X-ray photoelectron spectroscopy (XPS). IPE results showed that the CBO value was larger than 1.5 eV irrespective of metal electrode and substrate type variance, while an accurate determination of valence band offset (VBO) by XPS requires a careful correction of differential charging phenomena. The VBO value was determined to be 3.60 {+-} 0.2 eV by XPS after charge correction, thus yielding a CBO (1.60 {+-} 0.2 eV) in excellent agreement with the IPE results. Such a large CBO (>1.5more » eV) confirmed here is promising in terms of using GeO{sub 2} as a potential passivation layer for future Ge-based scaled CMOS devices.« less

A Hybrid Readout Solution for GaN-Based Detectors Using CMOS Technology.

PubMed

Padmanabhan, Preethi; Hancock, Bruce; Nikzad, Shouleh; Bell, L Douglas; Kroep, Kees; Charbon, Edoardo

2018-02-03

Gallium nitride (GaN) and its alloys are becoming preferred materials for ultraviolet (UV) detectors due to their wide bandgap and tailorable out-of-band cutoff from 3.4 eV to 6.2 eV. GaN based avalanche photodiodes (APDs) are particularly suitable for their high photon sensitivity and quantum efficiency in the UV region and for their inherent insensitivity to visible wavelengths. Challenges exist however for practical utilization. With growing interests in such photodetectors, hybrid readout solutions are becoming prevalent with CMOS technology being adopted for its maturity, scalability, and reliability. In this paper, we describe our approach to combine GaN APDs with a CMOS readout circuit, comprising of a linear array of 1 × 8 capacitive transimpedance amplifiers (CTIAs), implemented in a 0.35 µm high voltage CMOS technology. Further, we present a simple, yet sustainable circuit technique to allow operation of APDs under high reverse biases, up to ≈80 V with verified measurement results. The readout offers a conversion gain of 0.43 µV/e - , obtaining avalanche gains up to 10³. Several parameters of the CTIA are discussed followed by a perspective on possible hybridization, exploiting the advantages of a 3D-stacked technology.

Evaluation of Magnetoresistive RAM for Space Applications

NASA Technical Reports Server (NTRS)

Heidecker, Jason

2014-01-01

Magnetoresistive random-access memory (MRAM) is a non-volatile memory that exploits electronic spin, rather than charge, to store data. Instead of moving charge on and off a floating gate to alter the threshold voltage of a CMOS transistor (creating different bit states), MRAM uses magnetic fields to flip the polarization of a ferromagnetic material thus switching its resistance and bit state. These polarized states are immune to radiation-induced upset, thus making MRAM very attractive for space application. These magnetic memory elements also have infinite data retention and erase/program endurance. Presented here are results of reliability testing of two space-qualified MRAM products from Aeroflex and Honeywell.

Laser as a Tool to Study Radiation Effects in CMOS

NASA Astrophysics Data System (ADS)

Ajdari, Bahar

Energetic particles from cosmic ray or terrestrial sources can strike sensitive areas of CMOS devices and cause soft errors. Understanding the effects of such interactions is crucial as the device technology advances, and chip reliability has become more important than ever. Particle accelerator testing has been the standard method to characterize the sensitivity of chips to single event upsets (SEUs). However, because of their costs and availability limitations, other techniques have been explored. Pulsed laser has been a successful tool for characterization of SEU behavior, but to this day, laser has not been recognized as a comparable method to beam testing. In this thesis, I propose a methodology of correlating laser soft error rate (SER) to particle beam gathered data. Additionally, results are presented showing a temperature dependence of SER and the "neighbor effect" phenomenon where due to the close proximity of devices a "weakening effect" in the ON state can be observed.

A Dual-Mode Large-Arrayed CMOS ISFET Sensor for Accurate and High-Throughput pH Sensing in Biomedical Diagnosis.

PubMed

Huang, Xiwei; Yu, Hao; Liu, Xu; Jiang, Yu; Yan, Mei; Wu, Dongping

2015-09-01

The existing ISFET-based DNA sequencing detects hydrogen ions released during the polymerization of DNA strands on microbeads, which are scattered into microwell array above the ISFET sensor with unknown distribution. However, false pH detection happens at empty microwells due to crosstalk from neighboring microbeads. In this paper, a dual-mode CMOS ISFET sensor is proposed to have accurate pH detection toward DNA sequencing. Dual-mode sensing, optical and chemical modes, is realized by integrating a CMOS image sensor (CIS) with ISFET pH sensor, and is fabricated in a standard 0.18-μm CIS process. With accurate determination of microbead physical locations with CIS pixel by contact imaging, the dual-mode sensor can correlate local pH for one DNA slice at one location-determined microbead, which can result in improved pH detection accuracy. Moreover, toward a high-throughput DNA sequencing, a correlated-double-sampling readout that supports large array for both modes is deployed to reduce pixel-to-pixel nonuniformity such as threshold voltage mismatch. The proposed CMOS dual-mode sensor is experimentally examined to show a well correlated pH map and optical image for microbeads with a pH sensitivity of 26.2 mV/pH, a fixed pattern noise (FPN) reduction from 4% to 0.3%, and a readout speed of 1200 frames/s. A dual-mode CMOS ISFET sensor with suppressed FPN for accurate large-arrayed pH sensing is proposed and demonstrated with state-of-the-art measured results toward accurate and high-throughput DNA sequencing. The developed dual-mode CMOS ISFET sensor has great potential for future personal genome diagnostics with high accuracy and low cost.

A CMOS-based high-resolution fluoroscope (HRF) detector prototype with 49.5μm pixels for use in endovascular image guided interventions (EIGI)

NASA Astrophysics Data System (ADS)

Russ, M.; Shankar, A.; Setlur Nagesh, S. V.; Ionita, C. N.; Bednarek, D. R.; Rudin, S.

2017-03-01

X-ray detectors to meet the high-resolution requirements for endovascular image-guided interventions (EIGIs) are being developed and evaluated. A new 49.5-micron pixel prototype detector is being investigated and compared to the current suite of high-resolution fluoroscopic (HRF) detectors. This detector featuring a 300-micron thick CsI(Tl) scintillator, and low electronic noise CMOS readout is designated the HRF- CMOS50. To compare the abilities of this detector with other existing high resolution detectors, a standard performance metric analysis was applied, including the determination of the modulation transfer function (MTF), noise power spectra (NPS), noise equivalent quanta (NEQ), and detective quantum efficiency (DQE) for a range of energies and exposure levels. The advantage of the smaller pixel size and reduced blurring due to the thin phosphor was exemplified when the MTF of the HRF-CMOS50 was compared to the other high resolution detectors, which utilize larger pixels, other optical designs or thicker scintillators. However, the thinner scintillator has the disadvantage of a lower quantum detective efficiency (QDE) for higher diagnostic x-ray energies. The performance of the detector as part of an imaging chain was examined by employing the generalized metrics GMTF, GNEQ, and GDQE, taking standard focal spot size and clinical imaging parameters into consideration. As expected, the disparaging effects of focal spot unsharpness, exacerbated by increasing magnification, degraded the higher-frequency performance of the HRF-CMOS50, while increasing scatter fraction diminished low-frequency performance. Nevertheless, the HRF-CMOS50 brings improved resolution capabilities for EIGIs, but would require increased sensitivity and dynamic range for future clinical application.

High-speed line-scan camera with digital time delay integration

NASA Astrophysics Data System (ADS)

Bodenstorfer, Ernst; Fürtler, Johannes; Brodersen, Jörg; Mayer, Konrad J.; Eckel, Christian; Gravogl, Klaus; Nachtnebel, Herbert

2007-02-01

Dealing with high-speed image acquisition and processing systems, the speed of operation is often limited by the amount of available light, due to short exposure times. Therefore, high-speed applications often use line-scan cameras, based on charge-coupled device (CCD) sensors with time delayed integration (TDI). Synchronous shift and accumulation of photoelectric charges on the CCD chip - according to the objects' movement - result in a longer effective exposure time without introducing additional motion blur. This paper presents a high-speed color line-scan camera based on a commercial complementary metal oxide semiconductor (CMOS) area image sensor with a Bayer filter matrix and a field programmable gate array (FPGA). The camera implements a digital equivalent to the TDI effect exploited with CCD cameras. The proposed design benefits from the high frame rates of CMOS sensors and from the possibility of arbitrarily addressing the rows of the sensor's pixel array. For the digital TDI just a small number of rows are read out from the area sensor which are then shifted and accumulated according to the movement of the inspected objects. This paper gives a detailed description of the digital TDI algorithm implemented on the FPGA. Relevant aspects for the practical application are discussed and key features of the camera are listed.

IR sensitivity enhancement of CMOS Image Sensor with diffractive light trapping pixels.

PubMed

Yokogawa, Sozo; Oshiyama, Itaru; Ikeda, Harumi; Ebiko, Yoshiki; Hirano, Tomoyuki; Saito, Suguru; Oinoue, Takashi; Hagimoto, Yoshiya; Iwamoto, Hayato

2017-06-19

We report on the IR sensitivity enhancement of back-illuminated CMOS Image Sensor (BI-CIS) with 2-dimensional diffractive inverted pyramid array structure (IPA) on crystalline silicon (c-Si) and deep trench isolation (DTI). FDTD simulations of semi-infinite thick c-Si having 2D IPAs on its surface whose pitches over 400 nm shows more than 30% improvement of light absorption at λ = 850 nm and the maximum enhancement of 43% with the 540 nm pitch at the wavelength is confirmed. A prototype BI-CIS sample with pixel size of 1.2 μm square containing 400 nm pitch IPAs shows 80% sensitivity enhancement at λ = 850 nm compared to the reference sample with flat surface. This is due to diffraction with the IPA and total reflection at the pixel boundary. The NIR images taken by the demo camera equip with a C-mount lens show 75% sensitivity enhancement in the λ = 700-1200 nm wavelength range with negligible spatial resolution degradation. Light trapping CIS pixel technology promises to improve NIR sensitivity and appears to be applicable to many different image sensor applications including security camera, personal authentication, and range finding Time-of-Flight camera with IR illuminations.

A portable electronic system for radiation dosimetry using electrets

NASA Astrophysics Data System (ADS)

Cruvinel, P. E.; Mascarenhas, S.; Cameron, J.

1990-02-01

An electret dosimeter with a cylindrical active volume has been introduced by Mascarenhas and collaborators [Proc. 10th Anniversary Conf. 1969-1979, Associacâo Brasileira de Fisicos em Medicina, p. 488; Topics Appl. Phys. 33 (1987) 321] for possible use in personnel and area monitoring. The full energy response curve as well as the degree of reproducibility and accuracy of the dosimeter are reported in a previous report [O. Guerrini, Master Science Thesis, São Carlos, USP-IFQSC (1982)]. For dimensions similar to those of the common pen dosimeter, the electret has a total surface charge of the order of 10 -9 C and it has a readout sensitivity of the order of 10 -5 Gy with a useful range of 5 × 10 -2 Gy. In this paper we describe a portable electronic system to measure X and γ-rays using a cylindrical electret ionization chamber. It uses commercially available operational amplifiers, and charge measurements can also be made by connecting a suitable capacitor in the feedback loop. With this system it is possible to measure equivalent surface charges up to (19.99±0.01) on the dosimeter. The readout doses are shown on a 3 {1}/{2} digit liquid crystal display (LCD). We have used complementary metal oxide semiconductor (CMOS) and bipolar metal oxide semiconductor (BiMOS) operatonal amplifier devices in the system's design. This choice provides small power consumption and is ideal for battery powered instruments. Furthermore the instrument is ideally suited for in situ measurements of X and γ radiation using a cylindrical electret ionization chamber.

Affordable Wide-field Optical Space Surveillance using sCMOS and GPUs

NASA Astrophysics Data System (ADS)

Zimmer, P.; McGraw, J.; Ackermann, M.

2016-09-01

Recent improvements in sCMOS technology allow for affordable, wide-field, and rapid cadence surveillance from LEO to out past GEO using largely off-the-shelf hardware. sCMOS sensors, until very recently, suffered from several shortcomings when compared to CCD sensors - lower sensitivity, smaller physical size and less predictable noise characteristics. Sensors that overcome the first two of these are now available commercially and the principals at J.T. McGraw and Associates (JTMA) have developed observing strategies that minimize the impact of the third, while leveraging the key features of sCMOS, fast readout and low average readout noise. JTMA has integrated a new generation sCMOS sensor into an existing COTS telescope system in order to develop and test new detection techniques designed for uncued optical surveillance across a wide range of apparent object angular rates - from degree per second scale of LEO objects to a few arcseconds per second for objects out past GEO. One further complication arises from this: increased useful frame rate means increased data volume. Fortunately, GPU technology continues to advance at a breakneck pace and we report on the results and performance of our new detection techniques implemented on new generation GPUs. Early results show significance within 20% of the expected theoretical limiting signal-to-noise using commodity GPUs in near real time across a wide range of object parameters, closing the gap in detectivity between moving objects and tracked objects.

Low temperature processed complementary metal oxide semiconductor (CMOS) device by oxidation effect from capping layer.

PubMed

Wang, Zhenwei; Al-Jawhari, Hala A; Nayak, Pradipta K; Caraveo-Frescas, J A; Wei, Nini; Hedhili, M N; Alshareef, H N

2015-04-20

In this report, both p- and n-type tin oxide thin-film transistors (TFTs) were simultaneously achieved using single-step deposition of the tin oxide channel layer. The tuning of charge carrier polarity in the tin oxide channel is achieved by selectively depositing a copper oxide capping layer on top of tin oxide, which serves as an oxygen source, providing additional oxygen to form an n-type tin dioxide phase. The oxidation process can be realized by annealing at temperature as low as 190 °C in air, which is significantly lower than the temperature generally required to form tin dioxide. Based on this approach, CMOS inverters based entirely on tin oxide TFTs were fabricated. Our method provides a solution to lower the process temperature for tin dioxide phase, which facilitates the application of this transparent oxide semiconductor in emerging electronic devices field.

Low Temperature Processed Complementary Metal Oxide Semiconductor (CMOS) Device by Oxidation Effect from Capping Layer

PubMed Central

Wang, Zhenwei; Al-Jawhari, Hala A.; Nayak, Pradipta K.; Caraveo-Frescas, J. A.; Wei, Nini; Hedhili, M. N.; Alshareef, H. N.

2015-01-01

In this report, both p- and n-type tin oxide thin-film transistors (TFTs) were simultaneously achieved using single-step deposition of the tin oxide channel layer. The tuning of charge carrier polarity in the tin oxide channel is achieved by selectively depositing a copper oxide capping layer on top of tin oxide, which serves as an oxygen source, providing additional oxygen to form an n-type tin dioxide phase. The oxidation process can be realized by annealing at temperature as low as 190°C in air, which is significantly lower than the temperature generally required to form tin dioxide. Based on this approach, CMOS inverters based entirely on tin oxide TFTs were fabricated. Our method provides a solution to lower the process temperature for tin dioxide phase, which facilitates the application of this transparent oxide semiconductor in emerging electronic devices field. PMID:25892711

Detection systems for mass spectrometry imaging: a perspective on novel developments with a focus on active pixel detectors.

PubMed

Jungmann, Julia H; Heeren, Ron M A

2013-01-15

Instrumental developments for imaging and individual particle detection for biomolecular mass spectrometry (imaging) and fundamental atomic and molecular physics studies are reviewed. Ion-counting detectors, array detection systems and high mass detectors for mass spectrometry (imaging) are treated. State-of-the-art detection systems for multi-dimensional ion, electron and photon detection are highlighted. Their application and performance in three different imaging modes--integrated, selected and spectral image detection--are described. Electro-optical and microchannel-plate-based systems are contrasted. The analytical capabilities of solid-state pixel detectors--both charge coupled device (CCD) and complementary metal oxide semiconductor (CMOS) chips--are introduced. The Medipix/Timepix detector family is described as an example of a CMOS hybrid active pixel sensor. Alternative imaging methods for particle detection and their potential for future applications are investigated. Copyright © 2012 John Wiley & Sons, Ltd.

PAM-4 Signaling over VCSELs with 0.13µm CMOS Chip Technology

NASA Astrophysics Data System (ADS)

Cunningham, J. E.; Beckman, D.; Zheng, Xuezhe; Huang, Dawei; Sze, T.; Krishnamoorthy, A. V.

2006-12-01

We present results for VCSEL based links operating PAM-4 signaling using a commercial 0.13µm CMOS technology. We perform a complete link analysis of the Bit Error Rate, Q factor, random and deterministic jitter by measuring waterfall curves versus margins in time and amplitude. We demonstrate that VCSEL based PAM 4 can match or even improve performance over binary signaling under conditions of a bandwidth limited, 100meter multi-mode optical link at 5Gbps. We present the first sensitivity measurements for optical PAM-4 and compare it with binary signaling. Measured benefits are reconciled with information theory predictions.

PAM-4 Signaling over VCSELs with 0.13microm CMOS Chip Technology.

PubMed

Cunningham, J E; Beckman, D; Zheng, Xuezhe; Huang, Dawei; Sze, T; Krishnamoorthy, A V

2006-12-11

We present results for VCSEL based links operating PAM-4 signaling using a commercial 0.13microm CMOS technology. We perform a complete link analysis of the Bit Error Rate, Q factor, random and deterministic jitter by measuring waterfall curves versus margins in time and amplitude. We demonstrate that VCSEL based PAM-4 can match or even improve performance over binary signaling under conditions of a bandwidth limited, 100meter multi-mode optical link at 5Gbps. We present the first sensitivity measurements for optical PAM-4 and compare it with binary signaling. Measured benefits are reconciled with information theory predictions.

Optimum Design Rules for CMOS Hall Sensors

PubMed Central

Crescentini, Marco; Biondi, Michele; Romani, Aldo; Tartagni, Marco; Sangiorgi, Enrico

2017-01-01

This manuscript analyzes the effects of design parameters, such as aspect ratio, doping concentration and bias, on the performance of a general CMOS Hall sensor, with insight on current-related sensitivity, power consumption, and bandwidth. The article focuses on rectangular-shaped Hall probes since this is the most general geometry leading to shape-independent results. The devices are analyzed by means of 3D-TCAD simulations embedding galvanomagnetic transport model, which takes into account the Lorentz force acting on carriers due to a magnetic field. Simulation results define a set of trade-offs and design rules that can be used by electronic designers to conceive their own Hall probes. PMID:28375191

Optimum Design Rules for CMOS Hall Sensors.

PubMed

Crescentini, Marco; Biondi, Michele; Romani, Aldo; Tartagni, Marco; Sangiorgi, Enrico

2017-04-04

This manuscript analyzes the effects of design parameters, such as aspect ratio, doping concentration and bias, on the performance of a general CMOS Hall sensor, with insight on current-related sensitivity, power consumption, and bandwidth. The article focuses on rectangular-shaped Hall probes since this is the most general geometry leading to shape-independent results. The devices are analyzed by means of 3D-TCAD simulations embedding galvanomagnetic transport model, which takes into account the Lorentz force acting on carriers due to a magnetic field. Simulation results define a set of trade-offs and design rules that can be used by electronic designers to conceive their own Hall probes.

Space-charge Effect on Electroresistance in Metal-Ferroelectric-Metal capacitors

PubMed Central

Tian, Bo Bo; Liu, Yang; Chen, Liu Fang; Wang, Jian Lu; Sun, Shuo; Shen, Hong; Sun, Jing Lan; Yuan, Guo Liang; Fusil, Stéphane; Garcia, Vincent; Dkhil, Brahim; Meng, Xiang Jian; Chu, Jun Hao

2015-01-01

Resistive switching through electroresistance (ER) effect in metal-ferroelectric-metal (MFM) capacitors has attracted increasing interest due to its potential applications as memories and logic devices. However, the detailed electronic mechanisms resulting in large ER when polarisation switching occurs in the ferroelectric barrier are still not well understood. Here, ER effect up to 1000% at room temperature is demonstrated in C-MOS compatible MFM nanocapacitors with a 8.8 nm-thick poly(vinylidene fluoride) (PVDF) homopolymer ferroelectric, which is very promising for silicon industry integration. Most remarkably, using theory developed for metal-semiconductor rectifying contacts, we derive an analytical expression for the variation of interfacial barrier heights due to space-charge effect that can interpret the observed ER response. We extend this space-charge model, related to the release of trapped charges by defects, to MFM structures made of ferroelectric oxides. This space-charge model provides a simple and straightforward tool to understand recent unusual reports. Finally, this work suggests that defect-engineering could be an original and efficient route for tuning the space-charge effect and thus the ER performances in future electronic devices. PMID:26670138

Space-charge Effect on Electroresistance in Metal-Ferroelectric-Metal capacitors

NASA Astrophysics Data System (ADS)

Tian, Bo Bo; Liu, Yang; Chen, Liu Fang; Wang, Jian Lu; Sun, Shuo; Shen, Hong; Sun, Jing Lan; Yuan, Guo Liang; Fusil, Stéphane; Garcia, Vincent; Dkhil, Brahim; Meng, Xiang Jian; Chu, Jun Hao

2015-12-01

Resistive switching through electroresistance (ER) effect in metal-ferroelectric-metal (MFM) capacitors has attracted increasing interest due to its potential applications as memories and logic devices. However, the detailed electronic mechanisms resulting in large ER when polarisation switching occurs in the ferroelectric barrier are still not well understood. Here, ER effect up to 1000% at room temperature is demonstrated in C-MOS compatible MFM nanocapacitors with a 8.8 nm-thick poly(vinylidene fluoride) (PVDF) homopolymer ferroelectric, which is very promising for silicon industry integration. Most remarkably, using theory developed for metal-semiconductor rectifying contacts, we derive an analytical expression for the variation of interfacial barrier heights due to space-charge effect that can interpret the observed ER response. We extend this space-charge model, related to the release of trapped charges by defects, to MFM structures made of ferroelectric oxides. This space-charge model provides a simple and straightforward tool to understand recent unusual reports. Finally, this work suggests that defect-engineering could be an original and efficient route for tuning the space-charge effect and thus the ER performances in future electronic devices.

Integration of an optical CMOS sensor with a microfluidic channel allows a sensitive readout for biological assays in point-of-care tests.

PubMed

Van Dorst, Bieke; Brivio, Monica; Van Der Sar, Elfried; Blom, Marko; Reuvekamp, Simon; Tanzi, Simone; Groenhuis, Roelf; Adojutelegan, Adewole; Lous, Erik-Jan; Frederix, Filip; Stuyver, Lieven J

2016-04-15

In this manuscript, a microfluidic detection module, which allows a sensitive readout of biological assays in point-of-care (POC) tests, is presented. The proposed detection module consists of a microfluidic flow cell with an integrated Complementary Metal-Oxide-Semiconductor (CMOS)-based single photon counting optical sensor. Due to the integrated sensor-based readout, the detection module could be implemented as the core technology in stand-alone POC tests, for use in mobile or rural settings. The performance of the detection module was demonstrated in three assays: a peptide, a protein and an antibody detection assay. The antibody detection assay with readout in the detection module proved to be 7-fold more sensitive that the traditional colorimetric plate-based ELISA. The protein and peptide assay showed a lower limit of detection (LLOD) of 200 fM and 460 fM respectively. Results demonstrate that the sensitivity of the immunoassays is comparable with lab-based immunoassays and at least equal or better than current mainstream POC devices. This sensitive readout holds the potential to develop POC tests, which are able to detect low concentrations of biomarkers. This will broaden the diagnostic capabilities at the clinician's office and at patient's home, where currently only the less sensitive lateral flow and dipstick POC tests are implemented. Copyright © 2015 Elsevier B.V. All rights reserved.

MEDUSA-32: A low noise, low power silicon strip detector front-end electronics, for space applications

NASA Astrophysics Data System (ADS)

Cicuttin, Andres; Colavita, Alberto; Cerdeira, Alberto; Fratnik, Fabio; Vacchi, Andrea

1997-02-01

In this report we describe a mixed analog-digital integrated circuit (IC) designed as the front-end electronics for silicon strip-detectors for space applications. In space power consumption, compactness and robustness become critical constraints for a pre-amplifier design. The IC is a prototype with 32 complete channels, and it is intended for a large area particle tracker of a new generation of gamma ray telescopes. Each channel contains a charge sensitive amplifier, a pulse shaper, a discriminator and two digital buffers. The reference trip point of the discriminator is adjustable. This chip also has a custom PMOSFET transistor per channel, included in order to provide the high dynamic resistance needed to reverse-bias the strip diode. The digital part of the chip is used to store and serially shift out the state of the channels. There is also a storage buffer that allows the disabling of non-functioning channels if it is required by the data acquisition system. An input capacitance of 30 pF introduced at the input of the front-end produces less than 1000 electrons of RMS equivalent noise charge (ENC), for a total power dissipation of only 60 μW per channel. The chip was made using Orbit's 1.2 μm double poly, double metal n-well low noise CMOS process. The dimensions of the IC are 2400 μm × 8840 μm.

A 25μm pitch LWIR focal plane array with pixel-level 15-bit ADC providing high well capacity and targeting 2mK NETD

NASA Astrophysics Data System (ADS)

Guellec, Fabrice; Peizerat, Arnaud; Tchagaspanian, Michael; de Borniol, Eric; Bisotto, Sylvette; Mollard, Laurent; Castelein, Pierre; Zanatta, Jean-Paul; Maillart, Patrick; Zecri, Michel; Peyrard, Jean-Christophe

2010-04-01

CEA Leti has recently developed a new readout IC (ROIC) with pixel-level ADC for cooled infrared focal plane arrays (FPAs). It operates at 50Hz frame rate in a snapshot Integrate-While-Read (IWR) mode. It targets applications that provide a large amount of integrated charge thanks to a long integration time. The pixel-level analog-to-digital conversion is based on charge packets counting. This technique offers a large well capacity that paves the way for a breakthrough in NETD performances. The 15 bits ADC resolution preserves the excellent detector SNR at full well (3Ge-). These characteristics are essential for LWIR FPAs as broad intra-scene dynamic range imaging requires high sensitivity. The ROIC, featuring a 320x256 array with 25μm pixel pitch, has been designed in a standard 0.18μm CMOS technology. The main design challenges for this digital pixel array (SNR, power consumption and layout density) are discussed. The IC has been hybridized to a LWIR detector fabricated using our in-house HgCdTe process. The first electro-optical test results of the detector dewar assembly are presented. They validate both the pixel-level ADC concept and its circuit implementation. Finally, the benefit of this LWIR FPA in terms of NETD performance is demonstrated.

Room Temperature Silicene Field-Effect Transistors

NASA Astrophysics Data System (ADS)

Akinwande, Deji

Silicene, a buckled Si analogue of graphene, holds significant promise for future electronics beyond traditional CMOS. In our predefined experiments via encapsulated delamination with native electrodes approach, silicene devices exhibit an ambipolar charge transport behavior, corroborating theories on Dirac band in Ag-free silicene. Monolayer silicene device has extracted field-effect mobility within the theoretical expectation and ON/OFF ratio greater than monolayer graphene, while multilayer silicene devices show decreased mobility and gate modulation. Air-stability of silicene devices depends on the number of layers of silicene and intrinsic material structure determined by growth temperature. Few or multi-layer silicene devices maintain their ambipolar behavior for days in contrast to minutes time scale for monolayer counterparts under similar conditions. Multilayer silicene grown at different temperatures below 300oC possess different intrinsic structures and yield different electrical property and air-stability. This work suggests a practical prospect to enable more air-stable silicene devices with layer and growth condition control, which can be leveraged for other air-sensitive 2D materials. In addition, we describe quantum and classical transistor device concepts based on silicene and related buckled materials that exploit the 2D topological insulating phenomenon. The transistor device physics offer the potential for ballistic transport that is robust against scattering and can be employed for both charge and spin transport. This work was supported by the ARO.

IDeF-X ECLAIRs: A CMOS ASIC for the Readout of CdTe and CdZnTe Detectors for High Resolution Spectroscopy

NASA Astrophysics Data System (ADS)

Gevin, Olivier; Baron, Pascal; Coppolani, Xavier; Daly, FranÇois; Delagnes, Eric; Limousin, Olivier; Lugiez, Francis; Meuris, Aline; Pinsard, FrÉdÉric; Renaud, Diana

2009-08-01

The very last member of the IDeF-X ASIC family is presented: IDeF-X ECLAIRs is a 32-channel front end ASIC designed for the readout of Cadmium Telluride (CdTe) and Cadmium Zinc Telluride (CdZnTe) Detectors. Thanks to its noise performance (Equivalent Noise Charge floor of 33 e- rms) and to its radiation hardened design (Single Event Latchup Linear Energy Transfer threshold of 56 MeV.cm2.mg-1), the chip is well suited for soft X-rays energy discrimination and high energy resolution, ldquospace proof,rdquo hard X-ray spectroscopy. We measured an energy low threshold of less than 4 keV with a 10 pF input capacitor and a minimal reachable sensitivity of the Equivalent Noise Charge (ENC) to input capacitance of less than 7 e-/pF obtained with a 6 mus peak time. IDeF-X ECLAIRs will be used for the readout of 6400 CdTe Schottky monopixel detectors of the 2D coded mask imaging telescope ECLAIRs aboard the SVOM satellite. IDeF-X ECLAIRs (or IDeF-X V2) has also been designed for the readout of a pixelated CdTe detector in the miniature spectro-imager prototype Caliste 256 that is currently foreseen for the high energy detector module of the Simbol-X mission.

A High Frequency Active Voltage Doubler in Standard CMOS Using Offset-Controlled Comparators for Inductive Power Transmission

PubMed Central

Lee, Hyung-Min; Ghovanloo, Maysam

2014-01-01

In this paper, we present a fully integrated active voltage doubler in CMOS technology using offset-controlled high speed comparators for extending the range of inductive power transmission to implantable microelectronic devices (IMD) and radio-frequency identification (RFID) tags. This active voltage doubler provides considerably higher power conversion efficiency (PCE) and lower dropout voltage compared to its passive counterpart and requires lower input voltage than active rectifiers, leading to reliable and efficient operation with weakly coupled inductive links. The offset-controlled functions in the comparators compensate for turn-on and turn-off delays to not only maximize the forward charging current to the load but also minimize the back current, optimizing PCE in the high frequency (HF) band. We fabricated the active voltage doubler in a 0.5-μm 3M2P std. CMOS process, occupying 0.144 mm2 of chip area. With 1.46 V peak AC input at 13.56 MHz, the active voltage doubler provides 2.4 V DC output across a 1 kΩ load, achieving the highest PCE = 79% ever reported at this frequency. In addition, the built-in start-up circuit ensures a reliable operation at lower voltages. PMID:23853321

A reliable ground bounce noise reduction technique for nanoscale CMOS circuits

NASA Astrophysics Data System (ADS)

Sharma, Vijay Kumar; Pattanaik, Manisha

2015-11-01

Power gating is the most effective method to reduce the standby leakage power by adding header/footer high-VTH sleep transistors between actual and virtual power/ground rails. When a power gating circuit transitions from sleep mode to active mode, a large instantaneous charge current flows through the sleep transistors. Ground bounce noise (GBN) is the high voltage fluctuation on real ground rail during sleep mode to active mode transitions of power gating circuits. GBN disturbs the logic states of internal nodes of circuits. A novel and reliable power gating structure is proposed in this article to reduce the problem of GBN. The proposed structure contains low-VTH transistors in place of high-VTH footer. The proposed power gating structure not only reduces the GBN but also improves other performance metrics. A large mitigation of leakage power in both modes eliminates the need of high-VTH transistors. A comprehensive and comparative evaluation of proposed technique is presented in this article for a chain of 5-CMOS inverters. The simulation results are compared to other well-known GBN reduction circuit techniques at 22 nm predictive technology model (PTM) bulk CMOS model using HSPICE tool. Robustness against process, voltage and temperature (PVT) variations is estimated through Monte-Carlo simulations.

Study of CMOS-SOI Integrated Temperature Sensing Circuits for On-Chip Temperature Monitoring.

PubMed

Malits, Maria; Brouk, Igor; Nemirovsky, Yael

2018-05-19

This paper investigates the concepts, performance and limitations of temperature sensing circuits realized in complementary metal-oxide-semiconductor (CMOS) silicon on insulator (SOI) technology. It is shown that the MOSFET threshold voltage ( V t ) can be used to accurately measure the chip local temperature by using a V t extractor circuit. Furthermore, the circuit's performance is compared to standard circuits used to generate an accurate output current or voltage proportional to the absolute temperature, i.e., proportional-to-absolute temperature (PTAT), in terms of linearity, sensitivity, power consumption, speed, accuracy and calibration needs. It is shown that the V t extractor circuit is a better solution to determine the temperature of low power, analog and mixed-signal designs due to its accuracy, low power consumption and no need for calibration. The circuit has been designed using 1 µm partially depleted (PD) CMOS-SOI technology, and demonstrates a measurement inaccuracy of ±1.5 K across 300 K⁻500 K temperature range while consuming only 30 µW during operation.

High-speed receiver based on waveguide germanium photodetector wire-bonded to 90nm SOI CMOS amplifier.

PubMed

Pan, Huapu; Assefa, Solomon; Green, William M J; Kuchta, Daniel M; Schow, Clint L; Rylyakov, Alexander V; Lee, Benjamin G; Baks, Christian W; Shank, Steven M; Vlasov, Yurii A

2012-07-30

The performance of a receiver based on a CMOS amplifier circuit designed with 90nm ground rules wire-bonded to a waveguide germanium photodetector is characterized at data rates up to 40Gbps. Both chips were fabricated through the IBM Silicon CMOS Integrated Nanophotonics process on specialty photonics-enabled SOI wafers. At the data rate of 28Gbps which is relevant to the new generation of optical interconnects, a sensitivity of -7.3dBm average optical power is demonstrated with 3.4pJ/bit power-efficiency and 0.6UI horizontal eye opening at a bit-error-rate of 10(-12). The receiver operates error-free (bit-error-rate < 10(-12)) up to 40Gbps with optimized power supply settings demonstrating an energy efficiency of 1.4pJ/bit and 4pJ/bit at data rates of 32Gbps and 40Gbps, respectively, with an average optical power of -0.8dBm.

Degradation of CMOS image sensors in deep-submicron technology due to γ-irradiation

NASA Astrophysics Data System (ADS)

Rao, Padmakumar R.; Wang, Xinyang; Theuwissen, Albert J. P.

2008-09-01

In this work, radiation induced damage mechanisms in deep submicron technology is resolved using finger gated-diodes (FGDs) as a radiation sensitive tool. It is found that these structures are simple yet efficient structures to resolve radiation induced damage in advanced CMOS processes. The degradation of the CMOS image sensors in deep-submicron technology due to γ-ray irradiation is studied by developing a model for the spectral response of the sensor and also by the dark-signal degradation as a function of STI (shallow-trench isolation) parameters. It is found that threshold shifts in the gate-oxide/silicon interface as well as minority carrier life-time variations in the silicon bulk are minimal. The top-layer material properties and the photodiode Si-SiO2 interface quality are degraded due to γ-ray irradiation. Results further suggest that p-well passivated structures are inevitable for radiation-hard designs. It was found that high electrical fields in submicron technologies pose a threat to high quality imaging in harsh environments.

A CMOS-Compatible, Low-Noise ISFET Based on High Efficiency Ion-Modulated Lateral-Bipolar Conduction

PubMed Central

Chang, Sheng-Ren; Chen, Hsin

2009-01-01

Ion-sensitive, field-effect transistors (ISFET) have been useful biosensors in many applications. However, the signal-to-noise ratio of the ISFET is limited by its intrinsic, low-frequency noise. This paper presents an ISFET capable of utilizing lateral-bipolar conduction to reduce low-frequency noise. With a particular layout design, the conduction efficiency is further enhanced. Moreover, the ISFET is compatible with the standard CMOS technology. All materials above the gate-oxide are removed by simple, die-level post-CMOS process, allowing ions to modulate the lateral-bipolar current directly. By varying the gate-to-bulk voltage, the operation mode of the ISFET is controlled effectively, so is the noise performance measured and compared. Finally, the biasing conditions preferable for different low-noise applications are identified. Under the identified biasing condition, the signal-to-noise ratio of the ISFET as a pH sensor is proved to be improved by more than five times. PMID:22408508

Fabrication and characterization of high-K dielectric integrated silicon nanowire sensor for DNA sensing application (Conference Presentation)

NASA Astrophysics Data System (ADS)

Jayakumar, Ganesh; Legallais, Maxime; Hellström, Per-Erik; Mouis, Mireille; Stambouli, Valérie; Ternon, Céline; Östling, Mikael

2016-09-01

1D silicon nanowires (SiNW) are attractive for charge based DNA sensing applications due to their small size and large surface to volume ratio. An ideal portable biosensor is expected to have repeatable and reliable sensitivity, selectivity, low production cost and small feature size. Instead of using tools such as e-beam that are capital and time intensive, we propose a low cost CMOS self-aligned-double-patterning I-line lithography process to fabricate 60 nm wide SiNW. DNA probes are grafted on a thin dielectric layer that is deposited on top of the SiNW surface. Here we used HfO2 instead of the usual SiO2. Indeed, compared to SiO2, HfO2 has been reported to have higher amount of OH groups on its surface leading to enhanced signal quality. We also report preliminary biosensor characterizations. After HfO2 functionalization and single-stranded DNA probe grafting onto the SiNWs, the sensors were first put in contact with fluorophore labelled complementary DNA targets in order to test the efficiency of DNA hybridization optically. Then, a sequence of hybridization, de-hybridization and re-hybridization steps was followed by Id-Vg measurements in order to measure the electrical response of the sensors to target DNA as well as recycling capability. After each step, SiNW devices exhibited a threshold voltage shift larger than device-to-device dispersion, showing that both complementary DNA hybridization and de-hybridization can be electrically detected. These results are very encouraging as they open new frontiers for heterogeneous integration of liquid interacting array of nano sensors with CMOS circuits to fabricate a complete lab on chip.

IR CMOS: near infrared enhanced digital imaging (Presentation Recording)

NASA Astrophysics Data System (ADS)

Pralle, Martin U.; Carey, James E.; Joy, Thomas; Vineis, Chris J.; Palsule, Chintamani

2015-08-01

SiOnyx has demonstrated imaging at light levels below 1 mLux (moonless starlight) at video frame rates with a 720P CMOS image sensor in a compact, low latency camera. Low light imaging is enabled by the combination of enhanced quantum efficiency in the near infrared together with state of the art low noise image sensor design. The quantum efficiency enhancements are achieved by applying Black Silicon, SiOnyx's proprietary ultrafast laser semiconductor processing technology. In the near infrared, silicon's native indirect bandgap results in low absorption coefficients and long absorption lengths. The Black Silicon nanostructured layer fundamentally disrupts this paradigm by enhancing the absorption of light within a thin pixel layer making 5 microns of silicon equivalent to over 300 microns of standard silicon. This results in a demonstrate 10 fold improvements in near infrared sensitivity over incumbent imaging technology while maintaining complete compatibility with standard CMOS image sensor process flows. Applications include surveillance, nightvision, and 1064nm laser see spot. Imaging performance metrics will be discussed. Demonstrated performance characteristics: Pixel size : 5.6 and 10 um Array size: 720P/1.3Mpix Frame rate: 60 Hz Read noise: 2 ele/pixel Spectral sensitivity: 400 to 1200 nm (with 10x QE at 1064nm) Daytime imaging: color (Bayer pattern) Nighttime imaging: moonless starlight conditions 1064nm laser imaging: daytime imaging out to 2Km

Energy efficient circuit design using nanoelectromechanical relays

NASA Astrophysics Data System (ADS)

Venkatasubramanian, Ramakrishnan

Nano-electromechanical (NEM) relays are a promising class of emerging devices that offer zero off-state leakage and behave like an ideal switch. Recent advances in planar fabrication technology have demonstrated that microelectromechanical (MEMS) scale miniature relays could be manufactured reliably and could be used to build fully functional, complex integrated circuits. The zero leakage operation of relays has renewed the interest in relay based low power logic design. This dissertation explores circuit architectures using NEM relays and NEMS-CMOS heterogeneous integration. Novel circuit topologies for sequential logic, memory, and power management circuits have been proposed taking into consideration the NEM relay device properties and optimizing for energy efficiency and area. In nanoscale electromechanical devices, dispersion forces like Van der Waals' force (vdW) affect the pull-in stability of the relay devices significantly. Verilog-A electromechanical model of the suspended gate relay operating at 1V with a nominal air gap of 5 - 10nm has been developed taking into account all the electrical, mechanical and dispersion effects. This dissertation explores different relay based latch and flip-flop topologies. It has been shown that as few as 4 relay cells could be used to build flip-flops. An integrated voltage doubler based flip flop that improves the performance by 2X by overdriving Vgb has been proposed. Three NEM relay based parallel readout memory bitcell architectures have been proposed that have faster access time, and remove the reliability issues associated with previously reported serial readout architectures. A paradigm shift in design of power switches using NEM relays is proposed. An interesting property of the relay device is that the ON state resistance (Ron) of the NEM relay switch is constant and is insensitive to the gate slew rate. This coupled with infinite OFF state resistance (Roff ) offers significant area and power advantages over CMOS. This dissertation demonstrates NEM relay based charge pump and NEM-CMOS heterogeneous discontinuous conduction mode (DCM) buck regulator and the results are compared against a standard commercial 0.35μm CMOS implementation. It is shown that NEM-CMOS heterogeneous DC-DC converter has an area savings of 60% over CMOS and achieves an overall higher efficiency over CMOS, with a peak efficiency of 94.3% at 100mA. NEM relays offers unprecedented 10X-30X energy efficiency improvement in logic design for low frequency operation and has the potential to break the CMOS efficiency barrier in power electronic circuits as well. The practical aspects of NEM Relay integration are evaluated and algorithms for synthesis and development of large NEM relay based logic circuits are explored.

A Hybrid Readout Solution for GaN-Based Detectors Using CMOS Technology †

PubMed Central

Hancock, Bruce; Nikzad, Shouleh; Bell, L. Douglas; Kroep, Kees; Charbon, Edoardo

2018-01-01

Gallium nitride (GaN) and its alloys are becoming preferred materials for ultraviolet (UV) detectors due to their wide bandgap and tailorable out-of-band cutoff from 3.4 eV to 6.2 eV. GaN based avalanche photodiodes (APDs) are particularly suitable for their high photon sensitivity and quantum efficiency in the UV region and for their inherent insensitivity to visible wavelengths. Challenges exist however for practical utilization. With growing interests in such photodetectors, hybrid readout solutions are becoming prevalent with CMOS technology being adopted for its maturity, scalability, and reliability. In this paper, we describe our approach to combine GaN APDs with a CMOS readout circuit, comprising of a linear array of 1 × 8 capacitive transimpedance amplifiers (CTIAs), implemented in a 0.35 µm high voltage CMOS technology. Further, we present a simple, yet sustainable circuit technique to allow operation of APDs under high reverse biases, up to ≈80 V with verified measurement results. The readout offers a conversion gain of 0.43 µV/e−, obtaining avalanche gains up to 103. Several parameters of the CTIA are discussed followed by a perspective on possible hybridization, exploiting the advantages of a 3D-stacked technology. PMID:29401655

Arrays of suspended silicon nanowires defined by ion beam implantation: mechanical coupling and combination with CMOS technology.

PubMed

Llobet, J; Rius, G; Chuquitarqui, A; Borrisé, X; Koops, R; van Veghel, M; Perez-Murano, F

2018-04-02

We present the fabrication, operation, and CMOS integration of arrays of suspended silicon nanowires (SiNWs). The functional structures are obtained by a top-down fabrication approach consisting in a resistless process based on focused ion beam irradiation, causing local gallium implantation and silicon amorphization, plus selective silicon etching by tetramethylammonium hydroxide, and a thermal annealing process in a boron rich atmosphere. The last step enables the electrical functionality of the irradiated material. Doubly clamped silicon beams are fabricated by this method. The electrical readout of their mechanical response can be addressed by a frequency down-mixing detection technique thanks to an enhanced piezoresistive transduction mechanism. Three specific aspects are discussed: (i) the engineering of mechanically coupled SiNWs, by making use of the nanometer scale overhang that it is inherently-generated with this fabrication process, (ii) the statistical distribution of patterned lateral dimensions when fabricating large arrays of identical devices, and (iii) the compatibility of the patterning methodology with CMOS circuits. Our results suggest that the application of this method to the integration of large arrays of suspended SiNWs with CMOS circuitry is interesting in view of applications such as advanced radio frequency band pass filters and ultra-high-sensitivity mass sensors.

Arrays of suspended silicon nanowires defined by ion beam implantation: mechanical coupling and combination with CMOS technology

NASA Astrophysics Data System (ADS)

Llobet, J.; Rius, G.; Chuquitarqui, A.; Borrisé, X.; Koops, R.; van Veghel, M.; Perez-Murano, F.

2018-04-01

We present the fabrication, operation, and CMOS integration of arrays of suspended silicon nanowires (SiNWs). The functional structures are obtained by a top-down fabrication approach consisting in a resistless process based on focused ion beam irradiation, causing local gallium implantation and silicon amorphization, plus selective silicon etching by tetramethylammonium hydroxide, and a thermal annealing process in a boron rich atmosphere. The last step enables the electrical functionality of the irradiated material. Doubly clamped silicon beams are fabricated by this method. The electrical readout of their mechanical response can be addressed by a frequency down-mixing detection technique thanks to an enhanced piezoresistive transduction mechanism. Three specific aspects are discussed: (i) the engineering of mechanically coupled SiNWs, by making use of the nanometer scale overhang that it is inherently-generated with this fabrication process, (ii) the statistical distribution of patterned lateral dimensions when fabricating large arrays of identical devices, and (iii) the compatibility of the patterning methodology with CMOS circuits. Our results suggest that the application of this method to the integration of large arrays of suspended SiNWs with CMOS circuitry is interesting in view of applications such as advanced radio frequency band pass filters and ultra-high-sensitivity mass sensors.

Particle and Photon Detection: Counting and Energy Measurement

PubMed Central

Janesick, James; Tower, John

2016-01-01

Fundamental limits for photon counting and photon energy measurement are reviewed for CCD and CMOS imagers. The challenges to extend photon counting into the visible/nIR wavelengths and achieve energy measurement in the UV with specific read noise requirements are discussed. Pixel flicker and random telegraph noise sources are highlighted along with various methods used in reducing their contribution on the sensor’s read noise floor. Practical requirements for quantum efficiency, charge collection efficiency, and charge transfer efficiency that interfere with photon counting performance are discussed. Lastly we will review current efforts in reducing flicker noise head-on, in hopes to drive read noise substantially below 1 carrier rms. PMID:27187398

QLog Solar-Cell Mode Photodiode Logarithmic CMOS Pixel Using Charge Compression and Readout †

PubMed Central

Ni, Yang

2018-01-01

In this paper, we present a new logarithmic pixel design currently under development at New Imaging Technologies SA (NIT). This new logarithmic pixel design uses charge domain logarithmic signal compression and charge-transfer-based signal readout. This structure gives a linear response in low light conditions and logarithmic response in high light conditions. The charge transfer readout efficiently suppresses the reset (KTC) noise by using true correlated double sampling (CDS) in low light conditions. In high light conditions, thanks to charge domain logarithmic compression, it has been demonstrated that 3000 electrons should be enough to cover a 120 dB dynamic range with a mobile phone camera-like signal-to-noise ratio (SNR) over the whole dynamic range. This low electron count permits the use of ultra-small floating diffusion capacitance (sub-fF) without charge overflow. The resulting large conversion gain permits a single photon detection capability with a wide dynamic range without a complex sensor/system design. A first prototype sensor with 320 × 240 pixels has been implemented to validate this charge domain logarithmic pixel concept and modeling. The first experimental results validate the logarithmic charge compression theory and the low readout noise due to the charge-transfer-based readout. PMID:29443903

QLog Solar-Cell Mode Photodiode Logarithmic CMOS Pixel Using Charge Compression and Readout.

PubMed

Ni, Yang

2018-02-14

In this paper, we present a new logarithmic pixel design currently under development at New Imaging Technologies SA (NIT). This new logarithmic pixel design uses charge domain logarithmic signal compression and charge-transfer-based signal readout. This structure gives a linear response in low light conditions and logarithmic response in high light conditions. The charge transfer readout efficiently suppresses the reset (KTC) noise by using true correlated double sampling (CDS) in low light conditions. In high light conditions, thanks to charge domain logarithmic compression, it has been demonstrated that 3000 electrons should be enough to cover a 120 dB dynamic range with a mobile phone camera-like signal-to-noise ratio (SNR) over the whole dynamic range. This low electron count permits the use of ultra-small floating diffusion capacitance (sub-fF) without charge overflow. The resulting large conversion gain permits a single photon detection capability with a wide dynamic range without a complex sensor/system design. A first prototype sensor with 320 × 240 pixels has been implemented to validate this charge domain logarithmic pixel concept and modeling. The first experimental results validate the logarithmic charge compression theory and the low readout noise due to the charge-transfer-based readout.

Floating Gate CMOS Dosimeter With Frequency Output

NASA Astrophysics Data System (ADS)

Garcia-Moreno, E.; Isern, E.; Roca, M.; Picos, R.; Font, J.; Cesari, J.; Pineda, A.

2012-04-01

This paper presents a gamma radiation dosimeter based on a floating gate sensor. The sensor is coupled with a signal processing circuitry, which furnishes a square wave output signal, the frequency of which depends on the total dose. Like any other floating gate dosimeter, it exhibits zero bias operation and reprogramming capabilities. The dosimeter has been designed in a standard 0.6 m CMOS technology. The whole dosimeter occupies a silicon area of 450 m250 m. The initial sensitivity to a radiation dose is Hz/rad, and to temperature and supply voltage is kHz/°C and 0.067 kHz/mV, respectively. The lowest detectable dose is less than 1 rad.

Performance and Transient Behavior of Vertically Integrated Thin-film Silicon Sensors

PubMed Central

Wyrsch, Nicolas; Choong, Gregory; Miazza, Clément; Ballif, Christophe

2008-01-01

Vertical integration of amorphous hydrogenated silicon diodes on CMOS readout chips offers several advantages compared to standard CMOS imagers in terms of sensitivity, dynamic range and dark current while at the same time introducing some undesired transient effects leading to image lag. Performance of such sensors is here reported and their transient behaviour is analysed and compared to the one of corresponding amorphous silicon test diodes deposited on glass. The measurements are further compared to simulations for a deeper investigation. The long time constant observed in dark or photocurrent decay is found to be rather independent of the density of defects present in the intrinsic layer of the amorphous silicon diode. PMID:27873778

Radiation tolerant 1 micron CMOS technology

NASA Astrophysics Data System (ADS)

Crevel, P.; Rodde, K.

1991-03-01

Starting from a standard one micron Complementary Metal Oxide Semiconductor (CMOS) for high density, low power memory applications, the degree of radiation tolerance of the baseline process is evaluated. Implemented process modifications to improve latchup sensitivity under heavy ion irradiation as well as total dose effects without changing layout rules are described. By changing doping profiles in Metal Nitride Oxide Semiconductors (MNOS) and P-channel MOS (PMOS) device regions, it is possible to guarantee data sheet specification of a 64 K low power static RAM for total gamma dose up to 35 krad (Si) (and even higher values for the gate array family) without latch up for Linear Energy Transfer LET up to 115 MeV/(mg/cm squared).

Measurement of Bacterial Bioluminescence Intensity and Spectrum: Current Physical Techniques and Principles.

PubMed

Jia, Kun; Ionescu, Rodica Elena

2016-01-01

: Bioluminescence is light production by living organisms, which can be observed in numerous marine creatures and some terrestrial invertebrates. More specifically, bacterial bioluminescence is the "cold light" produced and emitted by bacterial cells, including both wild-type luminescent and genetically engineered bacteria. Because of the lively interplay of synthetic biology, microbiology, toxicology, and biophysics, different configurations of whole-cell biosensors based on bacterial bioluminescence have been designed and are widely used in different fields, such as ecotoxicology, food toxicity, and environmental pollution. This chapter first discusses the background of the bioluminescence phenomenon in terms of optical spectrum. Platforms for bacterial bioluminescence detection using various techniques are then introduced, such as a photomultiplier tube, charge-coupled device (CCD) camera, micro-electro-mechanical systems (MEMS), and complementary metal-oxide-semiconductor (CMOS) based integrated circuit. Furthermore, some typical biochemical methods to optimize the analytical performances of bacterial bioluminescent biosensors/assays are reviewed, followed by a presentation of author's recent work concerning the improved sensitivity of a bioluminescent assay for pesticides. Finally, bacterial bioluminescence as implemented in eukaryotic cells, bioluminescent imaging, and cancer cell therapies is discussed.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chumacero, E. Miguel; De Celis Alonso, B.; Martínez Hernández, M. I.

The development in semiconductor CMOS technology has enabled the creation of sensitive detectors for a wide range of ionizing radiation. These devices are suitable for photon counting and can be used in imaging and tomography X-ray diagnostics. The Medipix[1] radiation detection system is a hybrid silicon pixel chip developed for particle tracking applications in High Energy Physics. Its exceptional features (high spatial and energy resolution, embedded ultra fast readout, different operation modes, etc.) make the Medipix an attractive device for applications in medical imaging. In this work the energy characterization of a third-generation Medipix chip (Medipix3) coupled to a siliconmore » sensor is presented. We used different radiation sources (strontium 90, iron 55 and americium 241) to obtain the response curve of the hybrid detector as a function of energy. We also studied the contrast of the Medipix as a measure of pixel noise. Finally we studied the response to fluorescence X rays from different target materials (In, Pd and Cd) for the two data acquisition modes of the chip; single pixel mode and charge summing mode.« less

Highly Enhanced Raman Scattering on Carbonized Polymer Films.

PubMed

Yoon, Jong-Chul; Hwang, Jongha; Thiyagarajan, Pradheep; Ruoff, Rodney S; Jang, Ji-Hyun

2017-06-28

We have discovered a carbonized polymer film to be a reliable and durable carbon-based substrate for carbon enhanced Raman scattering (CERS). Commercially available SU8 was spin coated and carbonized (c-SU8) to yield a film optimized to have a favorable Fermi level position for efficient charge transfer, which results in a significant Raman scattering enhancement under mild measurement conditions. A highly sensitive CERS (detection limit of 10 -8 M) that was uniform over a large area was achieved on a patterned c-SU8 film and the Raman signal intensity has remained constant for 2 years. This approach works not only for the CMOS-compatible c-SU8 film but for any carbonized film with the correct composition and Fermi level, as demonstrated with carbonized-PVA (poly(vinyl alcohol)) and carbonized-PVP (polyvinylpyrollidone) films. Our study certainly expands the rather narrow range of Raman-active material platforms to include robust carbon-based films readily obtained from polymer precursors. As it uses broadly applicable and cheap polymers, it could offer great advantages in the development of practical devices for chemical/bio analysis and sensors.

Benchtop and Animal Validation of a Projective Imaging System for Potential Use in Intraoperative Surgical Guidance

PubMed Central

Gan, Qi; Wang, Dong; Ye, Jian; Zhang, Zeshu; Wang, Xinrui; Hu, Chuanzhen; Shao, Pengfei; Xu, Ronald X.

2016-01-01

We propose a projective navigation system for fluorescence imaging and image display in a natural mode of visual perception. The system consists of an excitation light source, a monochromatic charge coupled device (CCD) camera, a host computer, a projector, a proximity sensor and a Complementary metal–oxide–semiconductor (CMOS) camera. With perspective transformation and calibration, our surgical navigation system is able to achieve an overall imaging speed higher than 60 frames per second, with a latency of 330 ms, a spatial sensitivity better than 0.5 mm in both vertical and horizontal directions, and a projection bias less than 1 mm. The technical feasibility of image-guided surgery is demonstrated in both agar-agar gel phantoms and an ex vivo chicken breast model embedding Indocyanine Green (ICG). The biological utility of the system is demonstrated in vivo in a classic model of ICG hepatic metabolism. Our benchtop, ex vivo and in vivo experiments demonstrate the clinical potential for intraoperative delineation of disease margin and image-guided resection surgery. PMID:27391764

First light from a very large area pixel array for high-throughput x-ray polarimetry

NASA Astrophysics Data System (ADS)

Bellazzini, R.; Spandre, G.; Minuti, M.; Baldini, L.; Brez, A.; Cavalca, F.; Latronico, L.; Omodei, N.; Massai, M. M.; Sgrò, C.; Costa, E.; Soffitta, P.; Krummenacher, F.; de Oliveira, R.

2006-06-01

We report on a large active area (15x15mm2), high channel density (470 pixels/mm2), self-triggering CMOS analog chip that we have developed as pixelized charge collecting electrode of a Micropattern Gas Detector. This device, which represents a big step forward both in terms of size and performance, is the last version of three generations of custom ASICs of increasing complexity. The CMOS pixel array has the top metal layer patterned in a matrix of 105600 hexagonal pixels at 50μm pitch. Each pixel is directly connected to the underneath full electronics chain which has been realized in the remaining five metal and single poly-silicon layers of a standard 0.18μm CMOS VLSI technology. The chip has customizable self-triggering capability and includes a signal pre-processing function for the automatic localization of the event coordinates. In this way it is possible to reduce significantly the readout time and the data volume by limiting the signal output only to those pixels belonging to the region of interest. The very small pixel area and the use of a deep sub-micron CMOS technology has brought the noise down to 50 electrons ENC. Results from in depth tests of this device when coupled to a fine pitch (50μm on a triangular pattern) Gas Electron Multiplier are presented. The matching of readout and gas amplification pitch allows getting optimal results. The application of this detector for Astronomical X-Ray Polarimetry is discussed. The experimental detector response to polarized and unpolarized X-ray radiation when working with two gas mixtures and two different photon energies is shown. Results from a full MonteCarlo simulation for several galactic and extragalactic astronomical sources are also reported.

An RF energy harvesting power management circuit for appropriate duty-cycled operation

NASA Astrophysics Data System (ADS)

Shirane, Atsushi; Ito, Hiroyuki; Ishihara, Noboru; Masu, Kazuya

2015-04-01

In this study, we present an RF energy harvesting power management unit (PMU) for battery-less wireless sensor devices (WSDs). The proposed PMU realizes a duty-cycled operation that is divided into the energy charging time and discharging time. The proposed PMU detects two types of timing, thus, the appropriate timing for the activation can be recognized. The activation of WSDs at the proper timing leads to energy efficient operation and stable wireless communication. The proposed PMU includes a hysteresis comparator (H-CMP) and an RF signal detector (RF-SD) to detect the timings. The proposed RF-SD can operate without the degradation of charge efficiency by reusing the RF energy harvester (RF-EH) and H-CMP. The PMU fabricated in a 180 nm Si CMOS demonstrated the charge operation using the RF signal at 915 MHz and the two types of timing detection with less than 124 nW in the charge phase. Furthermore, in the active phase, the PMU generates a 0.5 V regulated power supply from the charged energy.

Emergency positioning system accuracy with infrared LEDs in high-security facilities

NASA Astrophysics Data System (ADS)

Knoch, Sierra N.; Nelson, Charles; Walker, Owens

2017-05-01

Instantaneous personnel location presents a challenge in Department of Defense applications where high levels of security restrict real-time tracking of crew members. During emergency situations, command and control requires immediate accountability of all personnel. Current radio frequency (RF) based indoor positioning systems can be unsuitable due to RF leakage and electromagnetic interference with sensitively calibrated machinery on variable platforms like ships, submarines and high-security facilities. Infrared light provide a possible solution to this problem. This paper proposes and evaluates an indoor line-of-sight positioning system that is comprised of IR and high-sensitivity CMOS camera receivers. In this system the movement of the LEDs is captured by the camera, uploaded and analyzed; the highest point of power is located and plotted to create a blueprint of crewmember location. Results provided evaluate accuracy as a function of both wavelength and environmental conditions. Research will further evaluate the accuracy of the LED transmitter and CMOS camera receiver system. Transmissions in both the 780 and 850nm IR are analyzed.

A dual-mode secure UHF RFID tag with a crypto engine in 0.13-μm CMOS

NASA Astrophysics Data System (ADS)

Tao, Yang; Linghao, Zhu; Xi, Tan; Junyu, Wang; Lirong, Zheng; Hao, Min

2016-07-01

An ultra-high-frequency (UHF) radio frequency identification (RFID) secure tag chip with a non-crypto mode and a crypto mode is presented. During the supply chain management, the tag works in the non-crypto mode in which the on-chip crypto engine is not enabled and the tag chip has a sensitivity of -12.8 dBm for long range communication. At the point of sales (POS), the tag will be switched to the crypto mode in order to protect the privacy of customers. In the crypto mode, an advanced encryption standard (AES) crypto engine is enabled and the sensitivity of the tag chip is switched to +2 dBm for short range communication, which is a method of physical protection. The tag chip is implemented and verified in a standard 0.13-μm CMOS process. Project supported by the National Science & Technology Pillar Program of China (No. 2015BAK36B01).

A comparison of imaging methods for use in an array biosensor

NASA Technical Reports Server (NTRS)

Golden, Joel P.; Ligler, Frances S.

2002-01-01

An array biosensor has been developed which uses an actively-cooled, charge-coupled device (CCD) imager. In an effort to save money and space, a complementary metal-oxide semiconductor (CMOS) camera and photodiode were tested as replacements for the cooled CCD imager. Different concentrations of CY5 fluorescent dye in glycerol were imaged using the three different detection systems with the same imaging optics. Signal discrimination above noise was compared for each of the three systems.

A reliable and controllable graphene doping method compatible with current CMOS technology and the demonstration of its device applications

NASA Astrophysics Data System (ADS)

Kim, Seonyeong; Shin, Somyeong; Kim, Taekwang; Du, Hyewon; Song, Minho; Kim, Ki Soo; Cho, Seungmin; Lee, Sang Wook; Seo, Sunae

2017-04-01

The modulation of charge carrier concentration allows us to tune the Fermi level (E F) of graphene thanks to the low electronic density of states near the E F. The introduced metal oxide thin films as well as the modified transfer process can elaborately maneuver the amounts of charge carrier concentration in graphene. The self-encapsulation provides a solution to overcome the stability issues of metal oxide hole dopants. We have manipulated systematic graphene p-n junction structures for electronic or photonic application-compatible doping methods with current semiconducting process technology. We have demonstrated the anticipated transport properties on the designed heterojunction devices with non-destructive doping methods. This mitigates the device architecture limitation imposed in previously known doping methods. Furthermore, we employed E F-modulated graphene source/drain (S/D) electrodes in a low dimensional transition metal dichalcogenide field effect transistor (TMDFET). We have succeeded in fulfilling n-type, ambipolar, or p-type field effect transistors (FETs) by moving around only the graphene work function. Besides, the graphene/transition metal dichalcogenide (TMD) junction in either both p- and n-type transistor reveals linear voltage dependence with the enhanced contact resistance. We accomplished the complete conversion of p-/n-channel transistors with S/D tunable electrodes. The E F modulation using metal oxide facilitates graphene to access state-of-the-art complimentary-metal-oxide-semiconductor (CMOS) technology.

A 4 GHz phase locked loop design in 65 nm CMOS for the Jiangmen Underground Neutrino Observatory detector

NASA Astrophysics Data System (ADS)

Parkalian, N.; Robens, M.; Grewing, C.; Christ, V.; Kruth, A.; Liebau, D.; Muralidharan, P.; Nielinger, D.; Roth, C.; Yegin, U.; Zambanini, A.; van Waasen, S.

2018-02-01

This paper presents a 4 GHz phase locked loop (PLL), which is implemented in a 65 nm standard CMOS process to provide low noise and high frequency sampling clocks for readout electronics to be used in the Jiangmen Underground Neutrino Observatory (JUNO) experiment. Based on the application requirements the target of the design is to find the best compromise between power consumption, area and phase noise for a highly reliable topology. The design implements a novel method for the charge pump that suppresses current mismatch when the PLL is locked. This reduces static phase offset at the inputs of the phase-frequency detector (PFD) that otherwise would introduce spurs at the PLL output. In addition, a technique of amplitude regulation for the voltage controlled oscillator (VCO) is presented to provide low noise and reliable operation. The combination of thin and thick oxide varactor transistors ensures optimum tuning range and linearity over process as well as temperature changes for the VCO without additional calibration steps. The current mismatch at the output of the charge pump for the control voltage at about half the 1 V supply voltage is below 0.3% and static phase offset down to 0.25% is reached. The total PLL consumes 18.5 mW power at 1.8 V supply for the VCO and 1 V supply for the other parts.

Maximization of DRAM yield by control of surface charge and particle addition during high dose implantation

NASA Astrophysics Data System (ADS)

Horvath, J.; Moffatt, S.

1991-04-01

Ion implantation processing exposes semiconductor devices to an energetic ion beam in order to deposit dopant ions in shallow layers. In addition to this primary process, foreign materials are deposited as particles and surface films. The deposition of particles is a major cause of IC yield loss and becomes even more significant as device dimensions are decreased. Control of particle addition in a high-volume production environment requires procedures to limit beamline and endstation sources, control of particle transport, cleaning procedures and a well grounded preventative maintenance philosophy. Control of surface charge by optimization of the ion beam and electron shower conditions and measurement with a real-time charge sensor has been effective in improving the yield of NMOS and CMOS DRAMs. Control of surface voltages to a range between 0 and -20 V was correlated with good implant yield with PI9200 implanters for p + and n + source-drain implants.

Single Event Upset in Static Random Access Memories in Atmospheric Neutron Environments

NASA Astrophysics Data System (ADS)

Arita, Yutaka; Takai, Mikio; Ogawa, Izumi; Kishimoto, Tadafumi

2003-07-01

Single-event upsets (SEUs) in a 0.4 μm 4 Mbit complementary metal oxide semiconductor (CMOS) static random access memory (SRAM) were investigated in various atmospheric neutron environments at sea level, at an altitude of 2612 m mountain, at an altitude of commercial airplane, and at an underground depth of 476 m. Neutron-induced SEUs increase with the increase in altitude. For a device with a borophosphosilicate glass (BPSG) film, SEU rates induced by thermal neutrons increase with the decrease in the cell charge of a memory cell. A thermal neutron-induced SEU is significant in SRAMs with a small cell charge. With the conditions of small cell charge, thermal neutron-induced SEUs account for 60% or more of the total neutron-induced SEUs. The SEU rate induced by atmospheric thermal neutrons can be estimated by an acceleration test using 252Cf.

FEM Analysis of Sezawa Mode SAW Sensor for VOC Based on CMOS Compatible AlN/SiO₂/Si Multilayer Structure.

PubMed

Aslam, Muhammad Zubair; Jeoti, Varun; Karuppanan, Saravanan; Malik, Aamir Farooq; Iqbal, Asif

2018-05-24

A Finite Element Method (FEM) simulation study is conducted, aiming to scrutinize the sensitivity of Sezawa wave mode in a multilayer AlN/SiO₂/Si Surface Acoustic Wave (SAW) sensor to low concentrations of Volatile Organic Compounds (VOCs), that is, trichloromethane, trichloroethylene, carbon tetrachloride and tetrachloroethene. A Complimentary Metal-Oxide Semiconductor (CMOS) compatible AlN/SiO₂/Si based multilayer SAW resonator structure is taken into account for this purpose. In this study, first, the influence of AlN and SiO₂ layers’ thicknesses over phase velocities and electromechanical coupling coefficients ( k ²) of two SAW modes (i.e., Rayleigh and Sezawa) is analyzed and the optimal thicknesses of AlN and SiO₂ layers are opted for best propagation characteristics. Next, the study is further extended to analyze the mass loading effect on resonance frequencies of SAW modes by coating a thin Polyisobutylene (PIB) polymer film over the AlN surface. Finally, the sensitivity of the two SAW modes is examined for VOCs. This study concluded that the sensitivity of Sezawa wave mode for 1 ppm of selected volatile organic gases is twice that of the Rayleigh wave mode.

Novel pH sensing semiconductor for point-of-care detection of HIV-1 viremia

PubMed Central

Gurrala, R.; Lang, Z.; Shepherd, L.; Davidson, D.; Harrison, E.; McClure, M.; Kaye, S.; Toumazou, C.; Cooke, G. S.

2016-01-01

The timely detection of viremia in HIV-infected patients receiving antiviral treatment is key to ensuring effective therapy and preventing the emergence of drug resistance. In high HIV burden settings, the cost and complexity of diagnostics limit their availability. We have developed a novel complementary metal-oxide semiconductor (CMOS) chip based, pH-mediated, point-of-care HIV-1 viral load monitoring assay that simultaneously amplifies and detects HIV-1 RNA. A novel low-buffer HIV-1 pH-LAMP (loop-mediated isothermal amplification) assay was optimised and incorporated into a pH sensitive CMOS chip. Screening of 991 clinical samples (164 on the chip) yielded a sensitivity of 95% (in vitro) and 88.8% (on-chip) at >1000 RNA copies/reaction across a broad spectrum of HIV-1 viral clades. Median time to detection was 20.8 minutes in samples with >1000 copies RNA. The sensitivity, specificity and reproducibility are close to that required to produce a point-of-care device which would be of benefit in resource poor regions, and could be performed on an USB stick or similar low power device. PMID:27829667

3D Silicon Coincidence Avalanche Detector (3D-SiCAD) for charged particle detection

NASA Astrophysics Data System (ADS)

Vignetti, M. M.; Calmon, F.; Pittet, P.; Pares, G.; Cellier, R.; Quiquerez, L.; Chaves de Albuquerque, T.; Bechetoille, E.; Testa, E.; Lopez, J.-P.; Dauvergne, D.; Savoy-Navarro, A.

2018-02-01

Single-Photon Avalanche Diodes (SPADs) are p-n junctions operated in Geiger Mode by applying a reverse bias above the breakdown voltage. SPADs have the advantage of featuring single photon sensitivity with timing resolution in the picoseconds range. Nevertheless, their relatively high Dark Count Rate (DCR) is a major issue for charged particle detection, especially when it is much higher than the incoming particle rate. To tackle this issue, we have developed a 3D Silicon Coincidence Avalanche Detector (3D-SiCAD). This novel device implements two vertically aligned SPADs featuring on-chip electronics for the detection of coincident avalanche events occurring on both SPADs. Such a coincidence detection mode allows an efficient discrimination of events related to an incoming charged particle (producing a quasi-simultaneous activation of both SPADs) from dark counts occurring independently on each SPAD. A 3D-SiCAD detector prototype has been fabricated in CMOS technology adopting a 3D flip-chip integration technique, and the main results of its characterization are reported in this work. The particle detection efficiency and noise rejection capability for this novel device have been evaluated by means of a β- strontium-90 radioactive source. Moreover the impact of the main operating parameters (i.e. the hold-off time, the coincidence window duration, the SPAD excess bias voltage) over the particle detection efficiency has been studied. Measurements have been performed with different β- particles rates and show that a 3D-SiCAD device outperforms single SPAD detectors: the former is indeed capable to detect particle rates much lower than the individual DCR observed in a single SPAD-based detectors (i.e. 2 to 3 orders of magnitudes lower).

A novel optical detector concept for dedicated and multi-modality in vivo small animal imaging

NASA Astrophysics Data System (ADS)

Peter, Jörg; Schulz, Ralf B.; Unholtz, Daniel; Semmler, Wolfhard

2007-07-01

An optical detector suitable for inclusion in tomographic arrangements for non-contact in vivo bioluminescence and fluorescence imaging applications is proposed. It consists of a microlens array (MLA) intended for field-of-view definition, a large-field complementary metal-oxide-semiconductor (CMOS) chip for light detection, a septum mask for cross-talk suppression, and an exchangeable filter to block excitation light. Prototype detector units with sensitive areas of 2.5 cm x 5 cm each were assembled. The CMOS sensor constitutes a 512 x 1024 photodiode matrix at 48 μm pixel pitch. Refractive MLAs with plano-convex lenses of 480 μm in diameter and pitch were selected resulting in a 55 x 105 lens matrix. The CMOS sensor is aligned on the focal plane of the MLA at 2.15mm distance. To separate individual microlens images an opaque multi-bore septum mask of 2.1mm in thickness and bore diameters of 400 μm at 480 μm pitch, aligned with the lens pattern, is placed between MLA and CMOS. Intrinsic spatial detector resolution and sensitivity was evaluated experimentally as a function of detector-object distance. Due to its small overall dimensions such detectors can be favorably packed for tomographic imaging (optical diffusion tomography, ODT) yielding complete 2 π field-of-view coverage. We also present a design study of a device intended to simultaneously image positron labeled substrates (positron emission tomography, PET) and optical molecular probes in small animals such as mice and rats. It consists of a cylindrical allocation of optical detector units which form an inner detector ring while PET detector blocks are mounted in radial extension, those gaining complementary information in a single, intrinsically coregistered experimental data acquisition study. Finally, in a second design study we propose a method for integrated optical and magnetic resonance imaging (MRI) which yields in vivo functional/molecular information that is intrinsically registered with the anatomy of the image object.

Low power, highly linear output buffer. [for infrared focal plane arrays

NASA Technical Reports Server (NTRS)

Foley, D.; Butler, N.; Stobie, J.

1992-01-01

A class AB CMOS output buffer has been designed for use on an IR focal plane array. Given the requirements for power dissipation and load capacitance a class A output, such as a source follower, would be unsuitable. The approach taken uses a class AB amplifier configured as a charge integrator. Thus it converts a charge packet in the focal plane multiplexer to a voltage which is then the output of the focal plane. With a quiescent current of 18 micro-a and a load capacitance of 100 pf, the amplifier has an open loop unity gain bandwidth of 900 khz. Integral nonlinearity is better than .03 percent over 5.5 volts when run with VDD-VSS = 6v.

Extreme Carrier Depletion and Superlinear Photoconductivity in Ultrathin Parallel-Aligned ZnO Nanowire Array Photodetectors Fabricated by Infiltration Synthesis

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nam, Chang-Yong; Stein, Aaron

Ultrathin semiconductor nanowires enable high-performance chemical sensors and photodetectors, but their synthesis and device integration by standard complementary metal-oxide-semiconductor (CMOS)-compatible processes remain persistent challenges. This work demonstrates fully CMOS-compatible synthesis and integration of parallel-aligned polycrystalline ZnO nanowire arrays into ultraviolet photodetectors via infiltration synthesis, material hybridization technique derived from atomic layer deposition. The nanowire photodetector features unique, high device performances originating from extreme charge carrier depletion, achieving photoconductive on–off ratios of >6 decades, blindness to visible light, and ultralow dark currents as low as 1 fA, the lowest reported for nanostructure-based photoconductive photodetectors. Surprisingly, the low dark current is invariantmore » with increasing number of nanowires and the photodetector shows unusual superlinear photoconductivity, observed for the first time in nanowires, leading to increasing detector responsivity and other parameters for higher incident light powers. Temperature-dependent carrier concentration and mobility reveal the photoelectrochemical-thermionic emission process at grain boundaries, responsible for the observed unique photodetector performances and superlinear photoconductivity. Here, the results elucidate fundamental processes responsible for photogain in polycrystalline nanostructures, providing useful guidelines for developing nanostructure-based detectors and sensors. Lastly, the developed fully CMOS-compatible nanowire synthesis and device fabrication methods also have potentials for scalable integration of nanowire sensor devices and circuitries.« less

Extreme Carrier Depletion and Superlinear Photoconductivity in Ultrathin Parallel-Aligned ZnO Nanowire Array Photodetectors Fabricated by Infiltration Synthesis

DOE PAGES

Nam, Chang-Yong; Stein, Aaron

2017-11-15

Ultrathin semiconductor nanowires enable high-performance chemical sensors and photodetectors, but their synthesis and device integration by standard complementary metal-oxide-semiconductor (CMOS)-compatible processes remain persistent challenges. This work demonstrates fully CMOS-compatible synthesis and integration of parallel-aligned polycrystalline ZnO nanowire arrays into ultraviolet photodetectors via infiltration synthesis, material hybridization technique derived from atomic layer deposition. The nanowire photodetector features unique, high device performances originating from extreme charge carrier depletion, achieving photoconductive on–off ratios of >6 decades, blindness to visible light, and ultralow dark currents as low as 1 fA, the lowest reported for nanostructure-based photoconductive photodetectors. Surprisingly, the low dark current is invariantmore » with increasing number of nanowires and the photodetector shows unusual superlinear photoconductivity, observed for the first time in nanowires, leading to increasing detector responsivity and other parameters for higher incident light powers. Temperature-dependent carrier concentration and mobility reveal the photoelectrochemical-thermionic emission process at grain boundaries, responsible for the observed unique photodetector performances and superlinear photoconductivity. Here, the results elucidate fundamental processes responsible for photogain in polycrystalline nanostructures, providing useful guidelines for developing nanostructure-based detectors and sensors. Lastly, the developed fully CMOS-compatible nanowire synthesis and device fabrication methods also have potentials for scalable integration of nanowire sensor devices and circuitries.« less

A hybrid magnetic/complementary metal oxide semiconductor three-context memory bit cell for non-volatile circuit design

NASA Astrophysics Data System (ADS)

Jovanović, B.; Brum, R. M.; Torres, L.

2014-04-01

After decades of continued scaling to the beat of Moore's law, it now appears that conventional silicon based devices are approaching their physical limits. In today's deep-submicron nodes, a number of short-channel and quantum effects are emerging that affect the manufacturing process, as well as, the functionality of the microelectronic systems-on-chip. Spintronics devices that exploit both the intrinsic spin of the electron and its associated magnetic moment, in addition to its fundamental electronic charge, are promising solutions to circumvent these scaling threats. Being compatible with the CMOS technology, such devices offer a promising synergy of radiation immunity, infinite endurance, non-volatility, increased density, etc. In this paper, we present a hybrid (magnetic/CMOS) cell that is able to store and process data both electrically and magnetically. The cell is based on perpendicular spin-transfer torque magnetic tunnel junctions (STT-MTJs) and is suitable for use in magnetic random access memories and reprogrammable computing (non-volatile registers, processor cache memories, magnetic field-programmable gate arrays, etc). To demonstrate the potential our hybrid cell, we physically implemented a small hybrid memory block using 45 nm × 45 nm round MTJs for the magnetic part and 28 nm fully depleted silicon on insulator (FD-SOI) technology for the CMOS part. We also report the cells measured performances in terms of area, robustness, read/write speed and energy consumption.

MONDO: A tracker for the characterization of secondary fast and ultrafast neutrons emitted in particle therapy

NASA Astrophysics Data System (ADS)

Mirabelli, R.; Battistoni, G.; Giacometti, V.; Patera, V.; Pinci, D.; Sarti, A.; Sciubba, A.; Traini, G.; Marafini, M.

2018-01-01

In Particle Therapy (PT) accelerated charged particles and light ions are used for treating tumors. One of the main limitation to the precision of PT is the emission of secondary particles due to the beam interaction with the patient: secondary emitted neutrons can release a significant dose far from the tumor. Therefore, a precise characterization of their flux, production energy and angle distribution is eagerly needed in order to improve the Treatment Planning Systems (TPS) codes. The principal aim of the MONDO (MOnitor for Neutron Dose in hadrOntherapy) project is the development of a tracking device optimized for the detection of fast and ultra-fast secondary neutrons emitted in PT. The detector consists of a matrix of scintillating square fibres coupled with a CMOS-based readout. Here, we present the characterization of the detector tracker prototype and CMOS-based digital SPAD (Single Photon Avalanche Diode) array sensor tested with protons at the Beam Test Facility (Frascati, Italy) and at the Proton Therapy Centre (Trento, Italy), respectively.

Multiplexed Oversampling Digitizer in 65 nm CMOS for Column-Parallel CCD Readout

DOE Office of Scientific and Technical Information (OSTI.GOV)

Grace, Carl; Walder, Jean-Pierre; von der Lippe, Henrik

2012-04-10

A digitizer designed to read out column-parallel charge-coupled devices (CCDs) used for high-speed X-ray imaging is presented. The digitizer is included as part of the High-Speed Image Preprocessor with Oversampling (HIPPO) integrated circuit. The digitizer module comprises a multiplexed, oversampling, 12-bit, 80 MS/s pipelined Analog-to-Digital Converter (ADC) and a bank of four fast-settling sample-and-hold amplifiers to instrument four analog channels. The ADC multiplexes and oversamples to reduce its area to allow integration that is pitch-matched to the columns of the CCD. Novel design techniques are used to enable oversampling and multiplexing with a reduced power penalty. The ADC exhibits 188more » ?V-rms noise which is less than 1 LSB at a 12-bit level. The prototype is implemented in a commercially available 65 nm CMOS process. The digitizer will lead to a proof-of-principle 2D 10 Gigapixel/s X-ray detector.« less

Silicon CMOS architecture for a spin-based quantum computer.

PubMed

Veldhorst, M; Eenink, H G J; Yang, C H; Dzurak, A S

2017-12-15

Recent advances in quantum error correction codes for fault-tolerant quantum computing and physical realizations of high-fidelity qubits in multiple platforms give promise for the construction of a quantum computer based on millions of interacting qubits. However, the classical-quantum interface remains a nascent field of exploration. Here, we propose an architecture for a silicon-based quantum computer processor based on complementary metal-oxide-semiconductor (CMOS) technology. We show how a transistor-based control circuit together with charge-storage electrodes can be used to operate a dense and scalable two-dimensional qubit system. The qubits are defined by the spin state of a single electron confined in quantum dots, coupled via exchange interactions, controlled using a microwave cavity, and measured via gate-based dispersive readout. We implement a spin qubit surface code, showing the prospects for universal quantum computation. We discuss the challenges and focus areas that need to be addressed, providing a path for large-scale quantum computing.

MAPS development for the ALICE ITS upgrade

NASA Astrophysics Data System (ADS)

Yang, P.; Aglieri, G.; Cavicchioli, C.; Chalmet, P. L.; Chanlek, N.; Collu, A.; Gao, C.; Hillemanns, H.; Junique, A.; Kofarago, M.; Keil, M.; Kugathasan, T.; Kim, D.; Kim, J.; Lattuca, A.; Marin Tobon, C. A.; Marras, D.; Mager, M.; Martinengo, P.; Mazza, G.; Mugnier, H.; Musa, L.; Puggioni, C.; Rousset, J.; Reidt, F.; Riedler, P.; Snoeys, W.; Siddhanta, S.; Usai, G.; van Hoorne, J. W.; Yi, J.

2015-03-01

Monolithic Active Pixel Sensors (MAPS) offer the possibility to build pixel detectors and tracking layers with high spatial resolution and low material budget in commercial CMOS processes. Significant progress has been made in the field of MAPS in recent years, and they are now considered for the upgrades of the LHC experiments. This contribution will focus on MAPS detectors developed for the ALICE Inner Tracking System (ITS) upgrade and manufactured in the TowerJazz 180 nm CMOS imaging sensor process on wafers with a high resistivity epitaxial layer. Several sensor chip prototypes have been developed and produced to optimise both charge collection and readout circuitry. The chips have been characterised using electrical measurements, radioactive sources and particle beams. The tests indicate that the sensors satisfy the ALICE requirements and first prototypes with the final size of 1.5 × 3 cm2 have been produced in the first half of 2014. This contribution summarises the characterisation measurements and presents first results from the full-scale chips.

Monolithic CMOS imaging x-ray spectrometers

NASA Astrophysics Data System (ADS)

Kenter, Almus; Kraft, Ralph; Gauron, Thomas; Murray, Stephen S.

2014-07-01

The Smithsonian Astrophysical Observatory (SAO) in collaboration with SRI/Sarnoff is developing monolithic CMOS detectors optimized for x-ray astronomy. The goal of this multi-year program is to produce CMOS x-ray imaging spectrometers that are Fano noise limited over the 0.1-10keV energy band while incorporating the many benefits of CMOS technology. These benefits include: low power consumption, radiation "hardness", high levels of integration, and very high read rates. Small format test devices from a previous wafer fabrication run (2011-2012) have recently been back-thinned and tested for response below 1keV. These devices perform as expected in regards to dark current, read noise, spectral response and Quantum Efficiency (QE). We demonstrate that running these devices at rates ~> 1Mpix/second eliminates the need for cooling as shot noise from any dark current is greatly mitigated. The test devices were fabricated on 15μm, high resistivity custom (~30kΩ-cm) epitaxial silicon and have a 16 by 192 pixel format. They incorporate 16μm pitch, 6 Transistor Pinned Photo Diode (6TPPD) pixels which have ~40μV/electron sensitivity and a highly parallel analog CDS signal chain. Newer, improved, lower noise detectors have just been fabricated (October 2013). These new detectors are fabricated on 9μm epitaxial silicon and have a 1k by 1k format. They incorporate similar 16μm pitch, 6TPPD pixels but have ~ 50% higher sensitivity and much (3×) lower read noise. These new detectors have undergone preliminary testing for functionality in Front Illuminated (FI) form and are presently being prepared for back thinning and packaging. Monolithic CMOS devices such as these, would be ideal candidate detectors for the focal planes of Solar, planetary and other space-borne x-ray astronomy missions. The high through-put, low noise and excellent low energy response, provide high dynamic range and good time resolution; bright, time varying x-ray features could be temporally and spectrally resolved without saturation. We present details of our camera design and device performance with particular emphasis on those aspects of interest to single photon counting x-ray astronomy. These features include read noise, x-ray spectral response and quantum efficiency. Funding for this work has been provided in large part by NASA Grant NNX09AE86G and a grant from the Betty and Gordon Moore Foundation.

A 40 GHz fully integrated circuit with a vector network analyzer and a coplanar-line-based detection area for circulating tumor cell analysis using 65 nm CMOS technology

NASA Astrophysics Data System (ADS)

Nakanishi, Taiki; Matsunaga, Maya; Kobayashi, Atsuki; Nakazato, Kazuo; Niitsu, Kiichi

2018-03-01

A 40-GHz fully integrated CMOS-based circuit for circulating tumor cells (CTC) analysis, consisting of an on-chip vector network analyzer (VNA) and a highly sensitive coplanar-line-based detection area is presented in this paper. In this work, we introduce a fully integrated architecture that eliminates unwanted parasitic effects. The proposed analyzer was designed using 65 nm CMOS technology, and SPICE and MWS simulations were used to validate its operation. The simulation confirmed that the proposed circuit can measure S-parameter shifts resulting from the addition of various types of tumor cells to the detection area, the data of which are provided in a previous study: the |S 21| values for HepG2, A549, and HEC-1-A cells are -0.683, -0.580, and -0.623 dB, respectively. Additionally, the measurement demonstrated an S-parameters reduction of -25.7% when a silicone resin was put on the circuit. Hence, the proposed system is expected to contribute to cancer diagnosis.

Development of CMOS MEMS inductive type tactile sensor with the integration of chrome steel ball force interface

NASA Astrophysics Data System (ADS)

Yeh, Sheng-Kai; Chang, Heng-Chung; Fang, Weileun

2018-04-01

This study presents an inductive tactile sensor with a chrome steel ball sensing interface based on the commercially available standard complementary metal-oxide-semiconductor (CMOS) process (the TSMC 0.18 µm 1P6M CMOS process). The tactile senor has a deformable polymer layer as the spring of the device and no fragile suspended thin film structures are required. As a tactile force is applied on the chrome steel ball, the polymer would deform. The distance between the chrome steel ball and the sensing coil would changed. Thus, the tactile force can be detected by the inductance change of the sensing coil. In short, the chrome steel ball acts as a tactile bump as well as the sensing interface. Experimental results show that the proposed inductive tactile sensor has a sensing range of 0-1.4 N with a sensitivity of 9.22(%/N) and nonlinearity of 2%. Preliminary wireless sensing test is also demonstrated. Moreover, the influence of the process and material issues on the sensor performances have also been investigated.

Design of a Programmable Gain, Temperature Compensated Current-Input Current-Output CMOS Logarithmic Amplifier.

PubMed

Ming Gu; Chakrabartty, Shantanu

2014-06-01

This paper presents the design of a programmable gain, temperature compensated, current-mode CMOS logarithmic amplifier that can be used for biomedical signal processing. Unlike conventional logarithmic amplifiers that use a transimpedance technique to generate a voltage signal as a logarithmic function of the input current, the proposed approach directly produces a current output as a logarithmic function of the input current. Also, unlike a conventional transimpedance amplifier the gain of the proposed logarithmic amplifier can be programmed using floating-gate trimming circuits. The synthesis of the proposed circuit is based on the Hart's extended translinear principle which involves embedding a floating-voltage source and a linear resistive element within a translinear loop. Temperature compensation is then achieved using a translinear-based resistive cancelation technique. Measured results from prototypes fabricated in a 0.5 μm CMOS process show that the amplifier has an input dynamic range of 120 dB and a temperature sensitivity of 230 ppm/°C (27 °C- 57°C), while consuming less than 100 nW of power.

A high sensitivity 20Mfps CMOS image sensor with readout speed of 1Tpixel/sec for visualization of ultra-high speed phenomena

NASA Astrophysics Data System (ADS)

Kuroda, R.; Sugawa, S.

2017-02-01

Ultra-high speed (UHS) CMOS image sensors with on-chop analog memories placed on the periphery of pixel array for the visualization of UHS phenomena are overviewed in this paper. The developed UHS CMOS image sensors consist of 400H×256V pixels and 128 memories/pixel, and the readout speed of 1Tpixel/sec is obtained, leading to 10 Mfps full resolution video capturing with consecutive 128 frames, and 20 Mfps half resolution video capturing with consecutive 256 frames. The first development model has been employed in the high speed video camera and put in practical use in 2012. By the development of dedicated process technologies, photosensitivity improvement and power consumption reduction were simultaneously achieved, and the performance improved version has been utilized in the commercialized high-speed video camera since 2015 that offers 10 Mfps with ISO16,000 photosensitivity. Due to the improved photosensitivity, clear images can be captured and analyzed even under low light condition, such as under a microscope as well as capturing of UHS light emission phenomena.

Direct ultrasensitive electrical detection of prostate cancer biomarkers with CMOS-compatible n- and p-type silicon nanowire sensor arrays.

PubMed

Gao, Anran; Lu, Na; Dai, Pengfei; Fan, Chunhai; Wang, Yuelin; Li, Tie

2014-11-07

Sensitive and quantitative analysis of proteins is central to disease diagnosis, drug screening, and proteomic studies. Here, a label-free, real-time, simultaneous and ultrasensitive prostate-specific antigen (PSA) sensor was developed using CMOS-compatible silicon nanowire field effect transistors (SiNW FET). Highly responsive n- and p-type SiNW arrays were fabricated and integrated on a single chip with a complementary metal oxide semiconductor (CMOS) compatible anisotropic self-stop etching technique which eliminated the need for a hybrid method. The incorporated n- and p-type nanowires revealed complementary electrical response upon PSA binding, providing a unique means of internal control for sensing signal verification. The highly selective, simultaneous and multiplexed detection of PSA marker at attomolar concentrations, a level useful for clinical diagnosis of prostate cancer, was demonstrated. The detection ability was corroborated to be effective by comparing the detection results at different pH values. Furthermore, the real-time measurement was also carried out in a clinically relevant sample of blood serum, indicating the practicable development of rapid, robust, high-performance, and low-cost diagnostic systems.

Dual light field and polarization imaging using CMOS diffractive image sensors.

PubMed

Jayasuriya, Suren; Sivaramakrishnan, Sriram; Chuang, Ellen; Guruaribam, Debashree; Wang, Albert; Molnar, Alyosha

2015-05-15

In this Letter we present, to the best of our knowledge, the first integrated CMOS image sensor that can simultaneously perform light field and polarization imaging without the use of external filters or additional optical elements. Previous work has shown how photodetectors with two stacks of integrated metal gratings above them (called angle sensitive pixels) diffract light in a Talbot pattern to capture four-dimensional light fields. We show, in addition to diffractive imaging, that these gratings polarize incoming light and characterize the response of these sensors to polarization and incidence angle. Finally, we show two applications of polarization imaging: imaging stress-induced birefringence and identifying specular reflections in scenes to improve light field algorithms for these scenes.

Radiation Tolerant, Low Noise Phase Locked Loops in 65 nm CMOS Technology

NASA Astrophysics Data System (ADS)

Prinzie, Jeffrey; Christiansen, Jorgen; Moreira, Paulo; Steyaert, Michiel; Leroux, Paul

2018-04-01

This work presents an introduction to radiation hardened Phase Locked Loops (PLLs) for nuclear and high-energy physics application. An experimental circuit has been fabricated and irradiated with Xrays up to 600 Mrad. Heavy ions with an LET between 3.2 and 69.2 MeV.cm2/mg were used to verify the SEU cross section of the devices. A Two-photon Absorption (TPA) laser facility has been used to provide detailed results on the SEU sensitivity. The presented circuit employs TMR in the digital logic and an asynchronous phase-frequency detector (PFD) is presented. The PLL has a ringand LC-oscillator to be compared experimentally. The circuit has been fabricated in a 65 nm CMOS technology.

Principle of the electrically induced Transient Current Technique

NASA Astrophysics Data System (ADS)

Bronuzzi, J.; Moll, M.; Bouvet, D.; Mapelli, A.; Sallese, J. M.

2018-05-01

In the field of detector development for High Energy Physics, the so-called Transient Current Technique (TCT) is used to characterize the electric field profile and the charge trapping inside silicon radiation detectors where particles or photons create electron-hole pairs in the bulk of a semiconductor device, as PiN diodes. In the standard approach, the TCT signal originates from the free carriers generated close to the surface of a silicon detector, by short pulses of light or by alpha particles. This work proposes a new principle of charge injection by means of lateral PN junctions implemented in one of the detector electrodes, called the electrical TCT (el-TCT). This technique is fully compatible with CMOS technology and therefore opens new perspectives for assessment of radiation detectors performances.

Preamplifiers for non-contact capacitive biopotential measurements.

PubMed

Peng, GuoChen; Ignjatovic, Zeljko; Bocko, Mark F

2013-01-01

Non-contact biopotential sensing is an attractive measurement strategy for a number of health monitoring applications, primarily the ECG and the EEG. In all such applications a key technical challenge is the design of a low-noise trans-impedance preamplifier for the typically low-capacitance, high source impedance sensing electrodes. In this paper, we compare voltage and charge amplifier designs in terms of their common mode rejection ratio, noise performance, and frequency response. Both amplifier types employ the same operational-transconductance amplifier (OTA), which was fabricated in a 0.35 um CMOS process. The results show that a charge amplifier configuration has advantages for small electrode-to-subject coupling capacitance values (less than 10 pF--typical of noncontact electrodes) and that the voltage amplifier configuration has advantages for electrode capacitances above 10 pF.

A 66pW Discontinuous Switch-Capacitor Energy Harvester for Self-Sustaining Sensor Applications

PubMed Central

Wu, Xiao; Shi, Yao; Jeloka, Supreet; Yang, Kaiyuan; Lee, Inhee; Sylvester, Dennis; Blaauw, David

2016-01-01

We present a discontinuous harvesting approach for switch capacitor DC-DC converters that enables ultra-low power energy harvesting. By slowly accumulating charge on an input capacitor and then transferring it to a battery in burst-mode, switching and leakage losses in the DC-DC converter can be optimally traded-off with the loss due to non-ideal MPPT operation. The harvester uses a 15pW mode controller, an automatic conversion ratio modulator, and a moving sum charge pump for low startup energy upon a mode switch. In 180nm CMOS, the harvester achieves >40% end-to-end efficiency from 113pW to 1.5μW with 66pW minimum input power, marking a >10× improvement over prior ultra-low power harvesters. PMID:28392977

A 66pW Discontinuous Switch-Capacitor Energy Harvester for Self-Sustaining Sensor Applications.

PubMed

Wu, Xiao; Shi, Yao; Jeloka, Supreet; Yang, Kaiyuan; Lee, Inhee; Sylvester, Dennis; Blaauw, David

2016-06-01

We present a discontinuous harvesting approach for switch capacitor DC-DC converters that enables ultra-low power energy harvesting. By slowly accumulating charge on an input capacitor and then transferring it to a battery in burst-mode, switching and leakage losses in the DC-DC converter can be optimally traded-off with the loss due to non-ideal MPPT operation. The harvester uses a 15pW mode controller, an automatic conversion ratio modulator, and a moving sum charge pump for low startup energy upon a mode switch. In 180nm CMOS, the harvester achieves >40% end-to-end efficiency from 113pW to 1.5μW with 66pW minimum input power, marking a >10× improvement over prior ultra-low power harvesters.

Annual Conference on Nuclear and Space Radiation Effects, Gatlinburg, TN, July 18-21, 1983, Proceedings

NASA Technical Reports Server (NTRS)

1983-01-01

Topics discussed include radiation effects in devices; the basic mechanisms of radiation effects in structures and materials; radiation effects in integrated circuits; spacecraft charging and space radiation effects; hardness assurance for devices and systems; and radiation transport, energy deposition and charge collection. Papers are presented on the mechanisms of small instabilities in irradiated MOS transistors, on the radiation effects on oxynitride gate dielectrics, on the discharge characteristics of a simulated solar cell array, and on latchup in CMOS devices from heavy ions. Attention is also given to proton upsets in orbit, to the modeling of single-event upset in bipolar integrated circuits, to high-resolution studies of the electrical breakdown of soil, and to a finite-difference solution of Maxwell's equations in generalized nonorthogonal coordinates.

Making A D-Latch Sensitive To Alpha Particles

NASA Technical Reports Server (NTRS)

Buehler, Martin G.; Blaes, Brent R.; Nixon, Robert H.

1994-01-01

Standard complementary metal oxide/semiconductor (CMOS) D-latch integrated circuit modified to increase susceptibility to single-event upsets (SEU's) (changes in logic state) caused by impacts of energetic alpha particles. Suitable for use in relatively inexpensive bench-scale SEU tests of itself and of related integrated circuits like static random-access memories.

Integrated fiber optical receiver reducing the gap to the quantum limit.

PubMed

Zimmermann, Horst; Steindl, Bernhard; Hofbauer, Michael; Enne, Reinhard

2017-06-01

Experimental results of a single-photon avalanche diode (SPAD) based optical fiber receiver integrated in 0.35 µm PIN-photodiode CMOS technology are presented. To cope with the parasitic effects of SPADs an array of four receivers is implemented. The SPADs consist of a multiplication zone and a separate thick absorption zone to achieve a high photon detection probability (PDP). In addition cascoded quenchers allow to use a quenching voltage of twice the usual supply voltage, i.e. 6.6 V instead of 3.3 V, in order to increase the PDP further. Measurements result in sensitivities of -55.7 dBm at a data rate of 50 Mbit/s and -51.6 dBm at 100 Mbit/s for a wavelength of 635 nm and a bit-error ratio of 2 × 10 -3 , which is sufficient to perform error correction. These sensitivities are better than those of linear-mode APD receivers integrated in the same CMOS technology. These results are a major advance towards direct detection optical receivers working close to the quantum limit.

A Low-Noise CMOS THz Imager Based on Source Modulation and an In-Pixel High-Q Passive Switched-Capacitor N-Path Filter.

PubMed

Boukhayma, Assim; Dupret, Antoine; Rostaing, Jean-Pierre; Enz, Christian

2016-03-03

This paper presents the first low noise complementary metal oxide semiconductor (CMOS) deletedCMOS terahertz (THz) imager based on source modulation and in-pixel high-Q filtering. The 31 × 31 focal plane array has been fully integrated in a 0 . 13 μ m standard CMOS process. The sensitivity has been improved significantly by modulating the active THz source that lights the scene and performing on-chip high-Q filtering. Each pixel encompass a broadband bow tie antenna coupled to an N-type metal-oxide-semiconductor (NMOS) detector that shifts the THz radiation, a low noise adjustable gain amplifier and a high-Q filter centered at the modulation frequency. The filter is based on a passive switched-capacitor (SC) N-path filter combined with a continuous-time broad-band Gm-C filter. A simplified analysis that helps in designing and tuning the passive SC N-path filter is provided. The characterization of the readout chain shows that a Q factor of 100 has been achieved for the filter with a good matching between the analytical calculation and the measurement results. An input-referred noise of 0 . 2 μ V RMS has been measured. Characterization of the chip with different THz wavelengths confirms the broadband feature of the antenna and shows that this THz imager reaches a total noise equivalent power of 0 . 6 nW at 270 GHz and 0 . 8 nW at 600 GHz.

A novel CMOS image sensor system for quantitative loop-mediated isothermal amplification assays to detect food-borne pathogens.

PubMed

Wang, Tiantian; Kim, Sanghyo; An, Jeong Ho

2017-02-01

Loop-mediated isothermal amplification (LAMP) is considered as one of the alternatives to the conventional PCR and it is an inexpensive portable diagnostic system with minimal power consumption. The present work describes the application of LAMP in real-time photon detection and quantitative analysis of nucleic acids integrated with a disposable complementary-metal-oxide semiconductor (CMOS) image sensor. This novel system works as an amplification-coupled detection platform, relying on a CMOS image sensor, with the aid of a computerized circuitry controller for the temperature and light sources. The CMOS image sensor captures the light which is passing through the sensor surface and converts into digital units using an analog-to-digital converter (ADC). This new system monitors the real-time photon variation, caused by the color changes during amplification. Escherichia coli O157 was used as a proof-of-concept target for quantitative analysis, and compared with the results for Staphylococcus aureus and Salmonella enterica to confirm the efficiency of the system. The system detected various DNA concentrations of E. coli O157 in a short time (45min), with a detection limit of 10fg/μL. The low-cost, simple, and compact design, with low power consumption, represents a significant advance in the development of a portable, sensitive, user-friendly, real-time, and quantitative analytic tools for point-of-care diagnosis. Copyright © 2016 Elsevier B.V. All rights reserved.

A CMOS-based large-area high-resolution imaging system for high-energy x-ray applications

NASA Astrophysics Data System (ADS)

Rodricks, Brian; Fowler, Boyd; Liu, Chiao; Lowes, John; Haeffner, Dean; Lienert, Ulrich; Almer, John

2008-08-01

CCDs have been the primary sensor in imaging systems for x-ray diffraction and imaging applications in recent years. CCDs have met the fundamental requirements of low noise, high-sensitivity, high dynamic range and spatial resolution necessary for these scientific applications. State-of-the-art CMOS image sensor (CIS) technology has experienced dramatic improvements recently and their performance is rivaling or surpassing that of most CCDs. The advancement of CIS technology is at an ever-accelerating pace and is driven by the multi-billion dollar consumer market. There are several advantages of CIS over traditional CCDs and other solid-state imaging devices; they include low power, high-speed operation, system-on-chip integration and lower manufacturing costs. The combination of superior imaging performance and system advantages makes CIS a good candidate for high-sensitivity imaging system development. This paper will describe a 1344 x 1212 CIS imaging system with a 19.5μm pitch optimized for x-ray scattering studies at high-energies. Fundamental metrics of linearity, dynamic range, spatial resolution, conversion gain, sensitivity are estimated. The Detective Quantum Efficiency (DQE) is also estimated. Representative x-ray diffraction images are presented. Diffraction images are compared against a CCD-based imaging system.

Optical Characterization of Lorentz Force Based CMOS-MEMS Magnetic Field Sensor

PubMed Central

Dennis, John Ojur; Ahmad, Farooq; Khir, M. Haris Bin Md; Hamid, Nor Hisham Bin

2015-01-01

Magnetic field sensors are becoming an essential part of everyday life due to the improvements in their sensitivities and resolutions, while at the same time they have become compact, smaller in size and economical. In the work presented herein a Lorentz force based CMOS-MEMS magnetic field sensor is designed, fabricated and optically characterized. The sensor is fabricated by using CMOS thin layers and dry post micromachining is used to release the device structure and finally the sensor chip is packaged in DIP. The sensor consists of a shuttle which is designed to resonate in the lateral direction (first mode of resonance). In the presence of an external magnetic field, the Lorentz force actuates the shuttle in the lateral direction and the amplitude of resonance is measured using an optical method. The differential change in the amplitude of the resonating shuttle shows the strength of the external magnetic field. The resonance frequency of the shuttle is determined to be 8164 Hz experimentally and from the resonance curve, the quality factor and damping ratio are obtained. In an open environment, the quality factor and damping ratio are found to be 51.34 and 0.00973 respectively. The sensitivity of the sensor is determined in static mode to be 0.034 µm/mT when a current of 10 mA passes through the shuttle, while it is found to be higher at resonance with a value of 1.35 µm/mT at 8 mA current. Finally, the resolution of the sensor is found to be 370.37 µT. PMID:26225972

Optical Characterization of Lorentz Force Based CMOS-MEMS Magnetic Field Sensor.

PubMed

Dennis, John Ojur; Ahmad, Farooq; Khir, M Haris Bin Md; Bin Hamid, Nor Hisham

2015-07-27

Magnetic field sensors are becoming an essential part of everyday life due to the improvements in their sensitivities and resolutions, while at the same time they have become compact, smaller in size and economical. In the work presented herein a Lorentz force based CMOS-MEMS magnetic field sensor is designed, fabricated and optically characterized. The sensor is fabricated by using CMOS thin layers and dry post micromachining is used to release the device structure and finally the sensor chip is packaged in DIP. The sensor consists of a shuttle which is designed to resonate in the lateral direction (first mode of resonance). In the presence of an external magnetic field, the Lorentz force actuates the shuttle in the lateral direction and the amplitude of resonance is measured using an optical method. The differential change in the amplitude of the resonating shuttle shows the strength of the external magnetic field. The resonance frequency of the shuttle is determined to be 8164 Hz experimentally and from the resonance curve, the quality factor and damping ratio are obtained. In an open environment, the quality factor and damping ratio are found to be 51.34 and 0.00973 respectively. The sensitivity of the sensor is determined in static mode to be 0.034 µm/mT when a current of 10 mA passes through the shuttle, while it is found to be higher at resonance with a value of 1.35 µm/mT at 8 mA current. Finally, the resolution of the sensor is found to be 370.37 µT.

SU-E-I-25: Performance Evaluation of a Proposed CMOS-Based X-Ray Detector Using Linear Cascade Model Analysis.

PubMed

Jain, A; Bednarek, D; Rudin, S

2012-06-01

The need for high-resolution, dynamic x-ray imaging capability for neurovascular applications has put an ever increasing demand on x-ray detector technology. Present state-of-the-art detectors such as flat panels have limited resolution and noise performance. A linear cascade model analysis was used to estimate the theoretical performance for a proposed CMOS-based detector. The proposed CMOS-based detector was assumed to have a 300-micron thick HL type CsI phosphor, 35-micron pixels, a variable gain light image intensifier (LU), and 400 electron readout noise. The proposed detector has a CMOS sensor coupled to an LII which views the output of the CsI phosphor. For the analysis the whole imaging chain was divided into individual stages characterized by one of the basic processes (stochastic/deterministic blurring, binomial selection, quantum gain, additive noise). Standard linear cascade modeling was used for the propagation of signal and noise through the stages and an RQA5 spectrum was assumed. The gain, blurring or transmission of different stages was either measured or taken from manufacturer's specifications. The theoretically calculated MTF and DQE for the proposed detector were compared with a high-resolution, high-sensitive Micro-Angio Fluoroscope (MAF), predecessor of the proposed detector. Signal and noise for each of the 19 stages in the complete imaging chain were calculated and showed improved performance. For example, at 5 cycles/mm the MTF and DQE were 0.08 and 0.28, respectively, for the CMOS detector compared to 0.05 and 0.07 for the MAF detector. The proposed detector will have improved MTF and DQE and slimmer physical dimension due to the elimination of the large fiber-optic taper used in the MAF. Once operational, the proposed CMOS detector will serve as a further improvement over standard flat panel detectors compared to the MAF which is already receiving a very positive reception by neuro-vascular interventionalists. (Support:NIH-Grant R01EB002873) NIH Grants R01- EB008425, R01-EB002873 and an equipment grant from Toshiba Medical Systems Corp. © 2012 American Association of Physicists in Medicine.

Measuring momentum for charged particle tomography

DOEpatents

Morris, Christopher; Fraser, Andrew Mcleod; Schultz, Larry Joe; Borozdin, Konstantin N.; Klimenko, Alexei Vasilievich; Sossong, Michael James; Blanpied, Gary

2010-11-23

Methods, apparatus and systems for detecting charged particles and obtaining tomography of a volume by measuring charged particles including measuring the momentum of a charged particle passing through a charged particle detector. Sets of position sensitive detectors measure scattering of the charged particle. The position sensitive detectors having sufficient mass to cause the charged particle passing through the position sensitive detectors to scatter in the position sensitive detectors. A controller can be adapted and arranged to receive scattering measurements of the charged particle from the charged particle detector, determine at least one trajectory of the charged particle from the measured scattering; and determine at least one momentum measurement of the charged particle from the at least one trajectory. The charged particle can be a cosmic ray-produced charged particle, such as a cosmic ray-produced muon. The position sensitive detectors can be drift cells, such as gas-filled drift tubes.

Recent advances in Optical Computed Tomography (OCT) imaging system for three dimensional (3D) radiotherapy dosimetry

NASA Astrophysics Data System (ADS)

Rahman, Ahmad Taufek Abdul; Farah Rosli, Nurul; Zain, Shafirah Mohd; Zin, Hafiz M.

2018-01-01

Radiotherapy delivery techniques for cancer treatment are becoming more complex and highly focused, to enable accurate radiation dose delivery to the cancerous tissue and minimum dose to the healthy tissue adjacent to tumour. Instrument to verify the complex dose delivery in radiotherapy such as optical computed tomography (OCT) measures the dose from a three-dimensional (3D) radiochromic dosimeter to ensure the accuracy of the radiotherapy beam delivery to the patient. OCT measures the optical density in radiochromic material that changes predictably upon exposure to radiotherapy beams. OCT systems have been developed using a photodiode and charged coupled device (CCD) as the detector. The existing OCT imaging systems have limitation in terms of the accuracy and the speed of the measurement. Advances in on-pixel intelligence CMOS image sensor (CIS) will be exploited in this work to replace current detector in OCT imaging systems. CIS is capable of on-pixel signal processing at a very fast imaging speed (over several hundred images per second) that will allow improvement in the 3D measurement of the optical density. The paper will review 3D radiochromic dosimeters and OCT systems developed and discuss how CMOS based OCT imaging will provide accurate and fast optical density measurements in 3D. The paper will also discuss the configuration of the CMOS based OCT developed in this work and how it may improve the existing OCT system.

Investigation of multilayer WS2 flakes as charge trapping stack layers in non-volatile memories

NASA Astrophysics Data System (ADS)

Wang, Hong; Ren, Deliang; Lu, Chao; Yan, Xiaobing

2018-06-01

In this study, the non-volatile flash memory devices utilize tungsten sulfide flakes as the charge trapping stack layers were fabricated. The sandwiched structure of Pd/ZHO/WS2/ZHO/WS2/SiO2/Si manifests a memory window of 2.26 V and a high density of trapped charges 4.88 × 1012/cm2 under a ±5 V gate sweeping voltage. Moreover, the data retention results of as-fabricated non-volatile memories demonstrate that the high and low capacitance states are enhanced by 3.81% and 3.11%, respectively, after a measurement duration of 1.20 × 104 s. These remarkable achievements are probably attributed to the defects and band gap of WS2 flakes. Besides, the proposed memory fabrication is not only compatible with CMOS manufacturing processes but also gets rid of the high-temperature annealing process. Overall, this proposed non-volatile memory is highly attractive for low voltage, long data retention applications.

A 256×256 low-light-level CMOS imaging sensor with digital CDS

NASA Astrophysics Data System (ADS)

Zou, Mei; Chen, Nan; Zhong, Shengyou; Li, Zhengfen; Zhang, Jicun; Yao, Li-bin

2016-10-01

In order to achieve high sensitivity for low-light-level CMOS image sensors (CIS), a capacitive transimpedance amplifier (CTIA) pixel circuit with a small integration capacitor is used. As the pixel and the column area are highly constrained, it is difficult to achieve analog correlated double sampling (CDS) to remove the noise for low-light-level CIS. So a digital CDS is adopted, which realizes the subtraction algorithm between the reset signal and pixel signal off-chip. The pixel reset noise and part of the column fixed-pattern noise (FPN) can be greatly reduced. A 256×256 CIS with CTIA array and digital CDS is implemented in the 0.35μm CMOS technology. The chip size is 7.7mm×6.75mm, and the pixel size is 15μm×15μm with a fill factor of 20.6%. The measured pixel noise is 24LSB with digital CDS in RMS value at dark condition, which shows 7.8× reduction compared to the image sensor without digital CDS. Running at 7fps, this low-light-level CIS can capture recognizable images with the illumination down to 0.1lux.

Design of a Multi-Channel Low-Noise Readout ASIC for CdZnTe-Based X-Ray and γ-Ray Spectrum Analyzer

NASA Astrophysics Data System (ADS)

Gan, B.; Wei, T.; Gao, W.; Zheng, R.; Hu, Y.

2015-10-01

In this paper, we report on the recent development of a 32-channel low-noise front-end readout ASIC for cadmium zinc telluride (CdZnTe) X-ray and γ-ray detectors. Each readout channel includes a charge sensitive amplifier, a CR-RC shaping amplifier and an analog output buffer. The readout ASIC is implemented using TSMC 0.35 - μm mixed-signal CMOS technology, the die size of the prototype chip is 2.2 mm ×4.8 mm. At room temperature, the equivalent noise level of a typical channel reaches 133 e- (rms) with the input parasitic capacitance of 0 pF for the average power consumption of 2.8 mW per channel. The linearity error is less than ±2% and the input energy dynamic range of the readout ASIC is from 10 keV to 1 MeV. The crosstalk between the channels is less than 0.4%. By connecting the readout ASIC to a CdZnTe detector, we obtained a γ-ray spectrum, the energy resolution is 1.8% at the 662-keV line of 137Cs source.

Design of a 2.4-GHz CMOS monolithic fractional-N frequency synthesizer

NASA Astrophysics Data System (ADS)

Shu, Keliu

The wireless communication technology and market have been growing rapidly since a decade ago. The high demand market is a driving need for higher integration in the wireless transceivers. The trend is to achieve low-cost, small form factor and low power consumption. With the ever-reducing feature size, it is becoming feasible to integrate the RF front-end together with the baseband in the low-cost CMOS technology. The frequency synthesizer is a key building block in the RF front-end of the transceivers. It is used as a local oscillator for frequency translation and channel selection. The design of a 2.4-GHz low-power frequency synthesizer in 0.35mum CMOS is a challenging task mainly due to the high-speed prescaler. In this dissertation, a brief review of conventional PLL and frequency synthesizers is provided. Design techniques of a 2.4-GHz monolithic SigmaDelta fractional-N frequency synthesizer are investigated. Novel techniques are proposed to tackle the speed and integration bottlenecks of high-frequency PLL. A low-power and inherently glitch-free phase-switching prescaler and an on-chip loop filter with capacitance multiplier are developed. Compared with the existing and popular dual-path topology, the proposed loop filter reduces circuit complexity and its power consumption and noise are negligible. Furthermore, a third-order three-level digital SigmaDelta modulator topology is employed to reduce the phase noise generated by the modulator. Suitable PFD and charge-pump designs are employed to reduce their nonlinearity effects and thus minimize the folding of the SigmaDelta modulator-shaped phase noise. A prototype of the fractional-N synthesizer together with some standalone building blocks is designed and fabricated in TSMC 0.35mum CMOS through MOSIS. The prototype frequency synthesizer and standalone prescaler and loop filter are characterized. The feasibility and practicality of the proposed prescaler and loop filter are experimentally verified.

A Fully Implantable, NFC Enabled, Continuous Interstitial Glucose Monitor

PubMed Central

Anabtawi, Nijad; Freeman, Sabrina; Ferzli, Rony

2017-01-01

This work presents an integrated system-on-chip (SoC) that forms the core of a long-term, fully implantable, battery assisted, passive continuous glucose monitor. It integrates an amperometric glucose sensor interface, a near field communication (NFC) wireless front-end and a fully digital switched mode power management unit for supply regulation and on board battery charging. It uses 13.56 MHz (ISM) band to harvest energy and backscatter data to an NFC reader. System was implemented in 14nm CMOS technology and validated with post layout simulations. PMID:28702512

A Fully Implantable, NFC Enabled, Continuous Interstitial Glucose Monitor.

PubMed

Anabtawi, Nijad; Freeman, Sabrina; Ferzli, Rony

2016-02-01

This work presents an integrated system-on-chip (SoC) that forms the core of a long-term, fully implantable, battery assisted, passive continuous glucose monitor. It integrates an amperometric glucose sensor interface, a near field communication (NFC) wireless front-end and a fully digital switched mode power management unit for supply regulation and on board battery charging. It uses 13.56 MHz (ISM) band to harvest energy and backscatter data to an NFC reader. System was implemented in 14nm CMOS technology and validated with post layout simulations.

Floating Gate sensor for in-vivo dosimetry in radiation therapies. Design and first characterization.

NASA Astrophysics Data System (ADS)

Faigon, A.; Martinez Vazquez, I.; Carbonetto, S.; García Inza, M.; G

2017-01-01

A floating gate dosimeter was designed and fabricated in a standard CMOS technology. The design guides and characterization are presented. The characterization included the controlled charging by tunneling of the floating gate, and its discharging under irradiation while measuring the transistor drain current whose change is the measure of the absorbed dose. The resolution of the obtained device is close to 1 cGy satisfying the requirements for most radiation therapies dosimetry. Pending statistical proofs, the dosimeter is a potential candidate for wide in-vivo control of radiotherapy treatments.

Direct ultrasensitive electrical detection of prostate cancer biomarkers with CMOS-compatible n- and p-type silicon nanowire sensor arrays

NASA Astrophysics Data System (ADS)

Gao, Anran; Lu, Na; Dai, Pengfei; Fan, Chunhai; Wang, Yuelin; Li, Tie

2014-10-01

Sensitive and quantitative analysis of proteins is central to disease diagnosis, drug screening, and proteomic studies. Here, a label-free, real-time, simultaneous and ultrasensitive prostate-specific antigen (PSA) sensor was developed using CMOS-compatible silicon nanowire field effect transistors (SiNW FET). Highly responsive n- and p-type SiNW arrays were fabricated and integrated on a single chip with a complementary metal oxide semiconductor (CMOS) compatible anisotropic self-stop etching technique which eliminated the need for a hybrid method. The incorporated n- and p-type nanowires revealed complementary electrical response upon PSA binding, providing a unique means of internal control for sensing signal verification. The highly selective, simultaneous and multiplexed detection of PSA marker at attomolar concentrations, a level useful for clinical diagnosis of prostate cancer, was demonstrated. The detection ability was corroborated to be effective by comparing the detection results at different pH values. Furthermore, the real-time measurement was also carried out in a clinically relevant sample of blood serum, indicating the practicable development of rapid, robust, high-performance, and low-cost diagnostic systems.Sensitive and quantitative analysis of proteins is central to disease diagnosis, drug screening, and proteomic studies. Here, a label-free, real-time, simultaneous and ultrasensitive prostate-specific antigen (PSA) sensor was developed using CMOS-compatible silicon nanowire field effect transistors (SiNW FET). Highly responsive n- and p-type SiNW arrays were fabricated and integrated on a single chip with a complementary metal oxide semiconductor (CMOS) compatible anisotropic self-stop etching technique which eliminated the need for a hybrid method. The incorporated n- and p-type nanowires revealed complementary electrical response upon PSA binding, providing a unique means of internal control for sensing signal verification. The highly selective, simultaneous and multiplexed detection of PSA marker at attomolar concentrations, a level useful for clinical diagnosis of prostate cancer, was demonstrated. The detection ability was corroborated to be effective by comparing the detection results at different pH values. Furthermore, the real-time measurement was also carried out in a clinically relevant sample of blood serum, indicating the practicable development of rapid, robust, high-performance, and low-cost diagnostic systems. Electronic supplementary information (ESI) available: Electrical characterization of fabricated n- and p-type nanowires, and influence of Debye screening on PSA sensing. See DOI: 10.1039/c4nr03210a

A capacitive CMOS-MEMS sensor designed by multi-physics simulation for integrated CMOS-MEMS technology

NASA Astrophysics Data System (ADS)

Konishi, Toshifumi; Yamane, Daisuke; Matsushima, Takaaki; Masu, Kazuya; Machida, Katsuyuki; Toshiyoshi, Hiroshi

2014-01-01

This paper reports the design and evaluation results of a capacitive CMOS-MEMS sensor that consists of the proposed sensor circuit and a capacitive MEMS device implemented on the circuit. To design a capacitive CMOS-MEMS sensor, a multi-physics simulation of the electromechanical behavior of both the MEMS structure and the sensing LSI was carried out simultaneously. In order to verify the validity of the design, we applied the capacitive CMOS-MEMS sensor to a MEMS accelerometer implemented by the post-CMOS process onto a 0.35-µm CMOS circuit. The experimental results of the CMOS-MEMS accelerometer exhibited good agreement with the simulation results within the input acceleration range between 0.5 and 6 G (1 G = 9.8 m/s2), corresponding to the output voltages between 908.6 and 915.4 mV, respectively. Therefore, we have confirmed that our capacitive CMOS-MEMS sensor and the multi-physics simulation will be beneficial method to realize integrated CMOS-MEMS technology.

Fundamental performance differences of CMOS and CCD imagers: part V

NASA Astrophysics Data System (ADS)

Janesick, James R.; Elliott, Tom; Andrews, James; Tower, John; Pinter, Jeff

2013-02-01

Previous papers delivered over the last decade have documented developmental progress made on large pixel scientific CMOS imagers that match or surpass CCD performance. New data and discussions presented in this paper include: 1) a new buried channel CCD fabricated on a CMOS process line, 2) new data products generated by high performance custom scientific CMOS 4T/5T/6T PPD pixel imagers, 3) ultimate CTE and speed limits for large pixel CMOS imagers, 4) fabrication and test results of a flight 4k x 4k CMOS imager for NRL's SoloHi Solar Orbiter Mission, 5) a progress report on ultra large stitched Mk x Nk CMOS imager, 6) data generated by on-chip sub-electron CDS signal chain circuitry used in our imagers, 7) CMOS and CMOSCCD proton and electron radiation damage data for dose levels up to 10 Mrd, 8) discussions and data for a new class of PMOS pixel CMOS imagers and 9) future CMOS development work planned.

Technical Note: Asteroid Detection Demonstration from SkySat-3 - B612 Data Using Synthetic Tracking

NASA Technical Reports Server (NTRS)

Zhai, C.; Shao, M.; Lai, S.; Boerner, P.; Dyer, J.; Lu, E.; Reitsema, H.; Buie, M.

2018-01-01

We report results from analyzing the data taken by the sCMOS cameras on board of SkySat3 using the synthetic tracking technique. The analysis demonstrates the expected sensitivity improvement in the signal-to-noise ratio of the faint asteroids from properly stacking up the short exposure images in post-processing.

Pixel pitch and particle energy influence on the dark current distribution of neutron irradiated CMOS image sensors.

PubMed

Belloir, Jean-Marc; Goiffon, Vincent; Virmontois, Cédric; Raine, Mélanie; Paillet, Philippe; Duhamel, Olivier; Gaillardin, Marc; Molina, Romain; Magnan, Pierre; Gilard, Olivier

2016-02-22

The dark current produced by neutron irradiation in CMOS Image Sensors (CIS) is investigated. Several CIS with different photodiode types and pixel pitches are irradiated with various neutron energies and fluences to study the influence of each of these optical detector and irradiation parameters on the dark current distribution. An empirical model is tested on the experimental data and validated on all the irradiated optical imagers. This model is able to describe all the presented dark current distributions with no parameter variation for neutron energies of 14 MeV or higher, regardless of the optical detector and irradiation characteristics. For energies below 1 MeV, it is shown that a single parameter has to be adjusted because of the lower mean damage energy per nuclear interaction. This model and these conclusions can be transposed to any silicon based solid-state optical imagers such as CIS or Charged Coupled Devices (CCD). This work can also be used when designing an optical imager instrument, to anticipate the dark current increase or to choose a mitigation technique.

Noise Reduction Effect of Multiple-Sampling-Based Signal-Readout Circuits for Ultra-Low Noise CMOS Image Sensors.

PubMed

Kawahito, Shoji; Seo, Min-Woong

2016-11-06

This paper discusses the noise reduction effect of multiple-sampling-based signal readout circuits for implementing ultra-low-noise image sensors. The correlated multiple sampling (CMS) technique has recently become an important technology for high-gain column readout circuits in low-noise CMOS image sensors (CISs). This paper reveals how the column CMS circuits, together with a pixel having a high-conversion-gain charge detector and low-noise transistor, realizes deep sub-electron read noise levels based on the analysis of noise components in the signal readout chain from a pixel to the column analog-to-digital converter (ADC). The noise measurement results of experimental CISs are compared with the noise analysis and the effect of noise reduction to the sampling number is discussed at the deep sub-electron level. Images taken with three CMS gains of two, 16, and 128 show distinct advantage of image contrast for the gain of 128 (noise(median): 0.29 e - rms ) when compared with the CMS gain of two (2.4 e - rms ), or 16 (1.1 e - rms ).

Noise Reduction Effect of Multiple-Sampling-Based Signal-Readout Circuits for Ultra-Low Noise CMOS Image Sensors

PubMed Central

Kawahito, Shoji; Seo, Min-Woong

2016-01-01

This paper discusses the noise reduction effect of multiple-sampling-based signal readout circuits for implementing ultra-low-noise image sensors. The correlated multiple sampling (CMS) technique has recently become an important technology for high-gain column readout circuits in low-noise CMOS image sensors (CISs). This paper reveals how the column CMS circuits, together with a pixel having a high-conversion-gain charge detector and low-noise transistor, realizes deep sub-electron read noise levels based on the analysis of noise components in the signal readout chain from a pixel to the column analog-to-digital converter (ADC). The noise measurement results of experimental CISs are compared with the noise analysis and the effect of noise reduction to the sampling number is discussed at the deep sub-electron level. Images taken with three CMS gains of two, 16, and 128 show distinct advantage of image contrast for the gain of 128 (noise(median): 0.29 e−rms) when compared with the CMS gain of two (2.4 e−rms), or 16 (1.1 e−rms). PMID:27827972

Automatic arc welding of propulsion system tubing in close proximity to sensitive electronic devices

NASA Technical Reports Server (NTRS)

Lumsden, J. M.; Whittlesey, A. C.

1981-01-01

The planned final assembly of the Galileo spacecraft propulsion system tubing, which involves welding in close proximity to sensitive electronics, raised significant concerns about the effects of electromagnetic coupling of weld energy on CMOS and other sensitive integrated circuits. A test program was established to assess the potential of an orbital arc welder and an RF-induction brazing machine to damage sensitive electronic equipment. Test parameters were varied to assess the effectiveness of typical transient suppression practices such as grounding, bonding, and shielding. A technique was developed to calibrate the hazard levels at the victim-circuit location; this technique is described along with the results and conclusions of the test program.

Novel Si-Ge-C Superlattices for More than Moore CMOS

DTIC Science & Technology

2016-03-31

diodes can be entirely formed by epitaxial growth, CMOS Active Pixel Sensors can be made with Fully-Depleted SOI CMOS . One important advantage of...a NMOS Transfer Gate (TG), which could be part of a 4T pixel APS. PPDs are preferred in CMOS image sensors for the ability of the pinning layer to...than Moore” with the creation of active photonic devices monolithically integrated with CMOS . Applications include Multispectral CMOS Image Sensors

CAOS-CMOS camera.

PubMed

Riza, Nabeel A; La Torre, Juan Pablo; Amin, M Junaid

2016-06-13

Proposed and experimentally demonstrated is the CAOS-CMOS camera design that combines the coded access optical sensor (CAOS) imager platform with the CMOS multi-pixel optical sensor. The unique CAOS-CMOS camera engages the classic CMOS sensor light staring mode with the time-frequency-space agile pixel CAOS imager mode within one programmable optical unit to realize a high dynamic range imager for extreme light contrast conditions. The experimentally demonstrated CAOS-CMOS camera is built using a digital micromirror device, a silicon point-photo-detector with a variable gain amplifier, and a silicon CMOS sensor with a maximum rated 51.3 dB dynamic range. White light imaging of three different brightness simultaneously viewed targets, that is not possible by the CMOS sensor, is achieved by the CAOS-CMOS camera demonstrating an 82.06 dB dynamic range. Applications for the camera include industrial machine vision, welding, laser analysis, automotive, night vision, surveillance and multispectral military systems.

An 11-bit 200 MS/s subrange SAR ADC with low-cost integrated reference buffer

NASA Astrophysics Data System (ADS)

He, Xiuju; Gu, Xian; Li, Weitao; Jiang, Hanjun; Li, Fule; Wang, Zhihua

2017-10-01

This paper presents an 11-bit 200 MS/s subrange SAR ADC with an integrated reference buffer in 65 nm CMOS. The proposed ADC employs a 3.5-bit flash ADC for coarse conversion, and a compact timing scheme at the flash/SAR boundary to speed up the conversion. The flash decision is used to control charge compensating for the reference voltage to reduce its input-dependent fluctuation. Measurement results show that the fabricated ADC has achieved significant improvement by applying the reference charge compensation. In addition, the ADC achieves a maximum signal-to-noise-and-distortion ratio of 59.3 dB at 200 MS/s. It consumes 3.91 mW from a 1.2 V supply, including the reference buffer. Project supported by the Zhongxing Telecommunication Equipment Corporation and Beijing Microelectronics Technology Institute.

Preamplifiers for non-contact capacitive biopotential measurements*

PubMed Central

Peng, GuoChen; Ignjatovic, Zeljko; Bocko, Mark F.

2014-01-01

Non-contact biopotential sensing is an attractive measurement strategy for a number of health monitoring applications, primarily the ECG and the EEG. In all such applications a key technical challenge is the design of a low-noise trans-impedance preamplifier for the typically low-capacitance, high source impedance sensing electrodes. In this paper, we compare voltage and charge amplifier designs in terms of their common mode rejection ratio, noise performance, and frequency response. Both amplifier types employ the same operational-transconductance amplifier (OTA), which was fabricated in a 0.35um CMOS process. The results show that a charge amplifier configuration has advantages for small electrode-to-subject coupling capacitance values (less than 10 pF - typical of noncontact electrodes) and that the voltage amplifier configuration has advantages for electrode capacitances above 10 pF. PMID:24109979

Thermal annealing of radiation damage in CMOS ICs in the temperature range -140 C to +375 C

NASA Technical Reports Server (NTRS)

Danchenko, V.; Fang, P. H.; Brashears, S. S.

1982-01-01

Annealing of radiation damage was investigated in the commercial, Z- and J-processes of the RCA CD4007A ICs in the temperature range from -140 C to +375 C. Tempering curves were analyzed for activation energies of thermal annealing, following irradiation at -140 C. It was found that at -140 C, the radiation-induced shifts in the threshold potentials were similar for all three processes. The radiation hardness of the Z- and J-process is primarily due to rapid annealing of radiation damage at room temperature. In the region -140 to 20 C, no dopant-dependent charge trapping is seen, similar to that observed at higher temperatures. In the unbiased Z-process n-channels, after 1 MeV electron irradiation, considerable negative charge remains in the gate oxide.

Readout electronics for LGAD sensors

NASA Astrophysics Data System (ADS)

Alonso, O.; Franch, N.; Canals, J.; Palacio, F.; López, M.; Vilà, A.; Diéguez, A.; Carulla, M.; Flores, D.; Hidalgo, S.; Merlos, A.; Pellegrini, G.; Quirion, D.

2017-02-01

In this paper, an ASIC fabricated in 180 nm CMOS technology from AMS with the very front-end electronics used to readout LGAD sensors is presented as well as its experimental results. The front-end has the typical architecture for Si-strip readout, i.e., preamplification stage with a Charge Sensitive Amplifier (CSA) followed by a CR-RC shaper. Both amplifiers are based on a folded cascode structure with a PMOS input transistor and the shaper only uses passive elements for the feedback stage. The CSA has programmable gain and a configurable input stage in order to adapt to the different input capacitance of the LGAD sensors (pixelated, short and long strips) and to the different input signal (depending on the gain of the LGAD). The fabricated prototype has an area of 0.865 mm × 0.965 mm and includes the biasing circuit for the CSA and the shaper, 4 analog channels (CSA+shaper) and programmable charge injection circuits included for testing purposes. Noise and power analysis performed during simulation fixed the size of the input transistor to W/L = 860 μm/0.2 μm. The shaping time is fixed by design at 1 us and, in this ASIC version, the feedback elements of the shaper are passive, which means that the area of the shaper can be reduced using active elements in future versions. Finally, the different gains of the CSA have been selected to maintain an ENC below 400 electrons for a detector capacitor of 20 pF, with a power consumption of 150 μ W per channel.

Improved Space Object Orbit Determination Using CMOS Detectors

NASA Astrophysics Data System (ADS)

Schildknecht, T.; Peltonen, J.; Sännti, T.; Silha, J.; Flohrer, T.

2014-09-01

CMOS-sensors, or in general Active Pixel Sensors (APS), are rapidly replacing CCDs in the consumer camera market. Due to significant technological advances during the past years these devices start to compete with CCDs also for demanding scientific imaging applications, in particular in the astronomy community. CMOS detectors offer a series of inherent advantages compared to CCDs, due to the structure of their basic pixel cells, which each contains their own amplifier and readout electronics. The most prominent advantages for space object observations are the extremely fast and flexible readout capabilities, feasibility for electronic shuttering and precise epoch registration, and the potential to perform image processing operations on-chip and in real-time. The major challenges and design drivers for ground-based and space-based optical observation strategies have been analyzed. CMOS detector characteristics were critically evaluated and compared with the established CCD technology, especially with respect to the above mentioned observations. Similarly, the desirable on-chip processing functionalities which would further enhance the object detection and image segmentation were identified. Finally, we simulated several observation scenarios for ground- and space-based sensor by assuming different observation and sensor properties. We will introduce the analyzed end-to-end simulations of the ground- and space-based strategies in order to investigate the orbit determination accuracy and its sensitivity which may result from different values for the frame-rate, pixel scale, astrometric and epoch registration accuracies. Two cases were simulated, a survey using a ground-based sensor to observe objects in LEO for surveillance applications, and a statistical survey with a space-based sensor orbiting in LEO observing small-size debris in LEO. The ground-based LEO survey uses a dynamical fence close to the Earth shadow a few hours after sunset. For the space-based scenario a sensor in a sun-synchronous LEO orbit, always pointing in the anti-sun direction to achieve optimum illumination conditions for small LEO debris, was simulated. For the space-based scenario the simulations showed a 20 130 % improvement of the accuracy of all orbital parameters when varying the frame rate from 1/3 fps, which is the fastest rate for a typical CCD detector, to 50 fps, which represents the highest rate of scientific CMOS cameras. Changing the epoch registration accuracy from a typical 20.0 ms for a mechanical shutter to 0.025 ms, the theoretical value for the electronic shutter of a CMOS camera, improved the orbit accuracy by 4 to 190 %. The ground-based scenario also benefit from the specific CMOS characteristics, but to a lesser extent.

Gun muzzle flash detection using a CMOS single photon avalanche diode

NASA Astrophysics Data System (ADS)

Merhav, Tomer; Savuskan, Vitali; Nemirovsky, Yael

2013-10-01

Si based sensors, in particular CMOS Image sensors, have revolutionized low cost imaging systems but to date have hardly been considered as possible candidates for gun muzzle flash detection, due to performance limitations, and low SNR in the visible spectrum. In this study, a CMOS Single Photon Avalanche Diode (SPAD) module is used to record and sample muzzle flash events in the visible spectrum, from representative weapons, common on the modern battlefield. SPADs possess two crucial properties for muzzle flash imaging - Namely, very high photon detection sensitivity, coupled with a unique ability to convert the optical signal to a digital signal at the source pixel, thus practically eliminating readout noise. This enables high sampling frequencies in the kilohertz range without SNR degradation, in contrast to regular CMOS image sensors. To date, the SPAD has not been utilized for flash detection in an uncontrolled environment, such as gun muzzle flash detection. Gun propellant manufacturers use alkali salts to suppress secondary flashes ignited during the muzzle flash event. Common alkali salts are compounds based on Potassium or Sodium, with spectral emission lines around 769nm and 589nm, respectively. A narrow band filter around the Potassium emission doublet is used in this study to favor the muzzle flash signal over solar radiation. This research will demonstrate the SPAD's ability to accurately sample and reconstruct the temporal behavior of the muzzle flash in the visible wavelength under the specified imaging conditions. The reconstructed signal is clearly distinguishable from background clutter, through exploitation of flash temporal characteristics.

MMW/THz imaging using upconversion to visible, based on glow discharge detector array and CCD camera

NASA Astrophysics Data System (ADS)

Aharon, Avihai; Rozban, Daniel; Abramovich, Amir; Yitzhaky, Yitzhak; Kopeika, Natan S.

2017-10-01

An inexpensive upconverting MMW/THz imaging method is suggested here. The method is based on glow discharge detector (GDD) and silicon photodiode or simple CCD/CMOS camera. The GDD was previously found to be an excellent room-temperature MMW radiation detector by measuring its electrical current. The GDD is very inexpensive and it is advantageous due to its wide dynamic range, broad spectral range, room temperature operation, immunity to high power radiation, and more. An upconversion method is demonstrated here, which is based on measuring the visual light emitting from the GDD rather than its electrical current. The experimental setup simulates a setup that composed of a GDD array, MMW source, and a basic CCD/CMOS camera. The visual light emitting from the GDD array is directed to the CCD/CMOS camera and the change in the GDD light is measured using image processing algorithms. The combination of CMOS camera and GDD focal plane arrays can yield a faster, more sensitive, and very inexpensive MMW/THz camera, eliminating the complexity of the electronic circuits and the internal electronic noise of the GDD. Furthermore, three dimensional imaging systems based on scanning prohibited real time operation of such imaging systems. This is easily solved and is economically feasible using a GDD array. This array will enable us to acquire information on distance and magnitude from all the GDD pixels in the array simultaneously. The 3D image can be obtained using methods like frequency modulation continuous wave (FMCW) direct chirp modulation, and measuring the time of flight (TOF).

The prototype cameras for trans-Neptunian automatic occultation survey

NASA Astrophysics Data System (ADS)

Wang, Shiang-Yu; Ling, Hung-Hsu; Hu, Yen-Sang; Geary, John C.; Chang, Yin-Chang; Chen, Hsin-Yo; Amato, Stephen M.; Huang, Pin-Jie; Pratlong, Jerome; Szentgyorgyi, Andrew; Lehner, Matthew; Norton, Timothy; Jorden, Paul

2016-08-01

The Transneptunian Automated Occultation Survey (TAOS II) is a three robotic telescope project to detect the stellar occultation events generated by TransNeptunian Objects (TNOs). TAOS II project aims to monitor about 10000 stars simultaneously at 20Hz to enable statistically significant event rate. The TAOS II camera is designed to cover the 1.7 degrees diameter field of view of the 1.3m telescope with 10 mosaic 4.5k×2k CMOS sensors. The new CMOS sensor (CIS 113) has a back illumination thinned structure and high sensitivity to provide similar performance to that of the back-illumination thinned CCDs. Due to the requirements of high performance and high speed, the development of the new CMOS sensor is still in progress. Before the science arrays are delivered, a prototype camera is developed to help on the commissioning of the robotic telescope system. The prototype camera uses the small format e2v CIS 107 device but with the same dewar and also the similar control electronics as the TAOS II science camera. The sensors, mounted on a single Invar plate, are cooled to the operation temperature of about 200K as the science array by a cryogenic cooler. The Invar plate is connected to the dewar body through a supporting ring with three G10 bipods. The control electronics consists of analog part and a Xilinx FPGA based digital circuit. One FPGA is needed to control and process the signal from a CMOS sensor for 20Hz region of interests (ROI) readout.

SOI-silicon as structural layer for NEMS applications

NASA Astrophysics Data System (ADS)

Villarroya, Maria; Figueras, Eduard; Perez-Murano, Francesc; Campabadal, Francesca; Esteve, Jaume; Barniol, Nuria

2003-04-01

The objective of this paper is to present the compatibilization between a standard CMOS on bulk silicon process and the fabrication of nanoelectromechanical systems using Silicon On Insulator (SOI) wafers as substrate. This compatibilization is required as first step to fabricate a very high sensitive mass sensor based on a resonant cantilever with nanometer dimensions using the crystal silicon COI layer as the structural layer. The cantilever is driven electrostatically to its resonance frequency by an electrode placed parallel to the cantilever. A capacitive readout is performed. To achieve very high resolution, very small dimensions of the cantilever (nanometer range) are needed. For this reason, the control and excitation circuitry has to be integrated on the same substrate than the cantilever. Prior to the development of this sensor, it is necessary to develop a substrate able to be used first to integrate a standard CMOS circuit and afterwards to fabricate the nano-resonator. Starting from a SOI wafer and using very simple processes, the SOI silicon layer is removed, except from the areas in which nano-structures will be fabricated; obtaining a silicon substrate with islands with a SOI structure. The CMOS circuitry will be integrated on the bulk silicon region, while the remainder SOI region will be used for the nanoresonator. The silicon oxide of this SOI region is used as insulator; and as sacrificial layer, etched to release the cantilever from the substrate. To assure the cover of the different CMOS layers over the step of the islands, it is essential to avoid very sharp steps.

Chip-to-chip interconnects based on 3D stacking of optoelectrical dies on Si

NASA Astrophysics Data System (ADS)

Duan, P.; Raz, O.; Smalbrugge, B. E.; Duis, J.; Dorren, H. J. S.

2012-01-01

We demonstrate a new approach to increase the optical interconnection bandwidth density by stacking the opto-electrical dies directly on the CMOS driver. The suggested implementation is aiming to provide a wafer scale process which will make the use of wire bonding redundant and will allow for impedance matched metallic wiring between the electronic driving circuit and its opto-electronic counter part. We suggest the use of a thick photoresist ramp between CMOS driver and opto-electrical dies surface as the bridge for supporting co-plannar waveguides (CPW) electrically plated with lithographic accuracy. In this way all three dimensions of the interconnecting metal layer, width, length and thickness can be completely controlled. In this 1st demonstration all processing is done on commercially available devices and products, and is compatible with CMOS processing technology. To test the applicability of CPW instead of wire bonds for interconnecting the CMOS circuit and opto-electronic chips, we have made test samples and tested their performance at speeds up to 10 Gbps. In this demonstration, a silicon substrate was used on which we evaporated gold co-planar waveguides (CPW) to mimic a wire on the driver. An optical link consisting of a VCSEL chip and a photodiode chip has been assembled and fully characterized using optical coupling into and out of a multimode fiber (MMF). A 10 Gb/s 27-1 NRZ PRBS signal transmitted from one chip to another chip was detected error free. A 4 dB receiver sensitivity penalty is measured for the integrated device compared to a commercial link.

Fill-factor improvement of Si CMOS single-photon avalanche diode detector arrays by integration of diffractive microlens arrays.

PubMed

Intermite, Giuseppe; McCarthy, Aongus; Warburton, Ryan E; Ren, Ximing; Villa, Federica; Lussana, Rudi; Waddie, Andrew J; Taghizadeh, Mohammad R; Tosi, Alberto; Zappa, Franco; Buller, Gerald S

2015-12-28

Single-photon avalanche diode (SPAD) detector arrays generally suffer from having a low fill-factor, in which the photo-sensitive area of each pixel is small compared to the overall area of the pixel. This paper describes the integration of different configurations of high efficiency diffractive optical microlens arrays onto a 32 × 32 SPAD array, fabricated using a 0.35 µm CMOS technology process. The characterization of SPAD arrays with integrated microlens arrays is reported over the spectral range of 500-900 nm, and a range of f-numbers from f/2 to f/22. We report an average concentration factor of 15 measured for the entire SPAD array with integrated microlens array. The integrated SPAD and microlens array demonstrated a very high uniformity in overall efficiency.

Automated translating beam profiler for in situ laser beam spot-size and focal position measurements

NASA Astrophysics Data System (ADS)

Keaveney, James

2018-03-01

We present a simple and convenient, high-resolution solution for automated laser-beam profiling with axial translation. The device is based on a Raspberry Pi computer, Pi Noir CMOS camera, stepper motor, and commercial translation stage. We also provide software to run the device. The CMOS sensor is sensitive over a large wavelength range between 300 and 1100 nm and can be translated over 25 mm along the beam axis. The sensor head can be reversed without changing its axial position, allowing for a quantitative estimate of beam overlap with counter-propagating laser beams. Although not limited to this application, the intended use for this device is the automated measurement of the focal position and spot-size of a Gaussian laser beam. We present example data of one such measurement to illustrate device performance.

Automated translating beam profiler for in situ laser beam spot-size and focal position measurements.

PubMed

Keaveney, James

2018-03-01

We present a simple and convenient, high-resolution solution for automated laser-beam profiling with axial translation. The device is based on a Raspberry Pi computer, Pi Noir CMOS camera, stepper motor, and commercial translation stage. We also provide software to run the device. The CMOS sensor is sensitive over a large wavelength range between 300 and 1100 nm and can be translated over 25 mm along the beam axis. The sensor head can be reversed without changing its axial position, allowing for a quantitative estimate of beam overlap with counter-propagating laser beams. Although not limited to this application, the intended use for this device is the automated measurement of the focal position and spot-size of a Gaussian laser beam. We present example data of one such measurement to illustrate device performance.

5-Gb/s 0.18-μm CMOS 2:1 multiplexer with integrated clock extraction

NASA Astrophysics Data System (ADS)

Changchun, Zhang; Zhigong, Wang; Si, Shi; Peng, Miao; Ling, Tian

2009-09-01

A 5-Gb/s 2:1 MUX (multiplexer) with an on-chip integrated clock extraction circuit which possesses the function of automatic phase alignment (APA), has been designed and fabricated in SMIC's 0.18 μm CMOS technology. The chip area is 670 × 780 μm2. At a single supply voltage of 1.8 V, the total power consumption is 112 mW with an input sensitivity of less than 50 mV and an output single-ended swing of above 300 mV. The measurement results show that the IC can work reliably at any input data rate between 1.8 and 2.6 Gb/s with no need for external components, reference clock, or phase alignment between data and clock. It can be used in a parallel optic-fiber data interconnecting system.

Real-time, continuous, fluorescence sensing in a freely-moving subject with an implanted hybrid VCSEL/CMOS biosensor

PubMed Central

O’Sullivan, Thomas D.; Heitz, Roxana T.; Parashurama, Natesh; Barkin, David B.; Wooley, Bruce A.; Gambhir, Sanjiv S.; Harris, James S.; Levi, Ofer

2013-01-01

Performance improvements in instrumentation for optical imaging have contributed greatly to molecular imaging in living subjects. In order to advance molecular imaging in freely moving, untethered subjects, we designed a miniature vertical-cavity surface-emitting laser (VCSEL)-based biosensor measuring 1cm3 and weighing 0.7g that accurately detects both fluorophore and tumor-targeted molecular probes in small animals. We integrated a critical enabling component, a complementary metal-oxide semiconductor (CMOS) read-out integrated circuit, which digitized the fluorescence signal to achieve autofluorescence-limited sensitivity. After surgical implantation of the lightweight sensor for two weeks, we obtained continuous and dynamic fluorophore measurements while the subject was un-anesthetized and mobile. The technology demonstrated here represents a critical step in the path toward untethered optical sensing using an integrated optoelectronic implant. PMID:24009996

On the integration of ultrananocrystalline diamond (UNCD) with CMOS chip

DOE PAGES

Mi, Hongyi; Yuan, Hao -Chih; Seo, Jung -Hun; ...

2017-03-27

A low temperature deposition of high quality ultrananocrystalline diamond (UNCD) film onto a finished Si-based CMOS chip was performed to investigate the compatibility of the UNCD deposition process with CMOS devices for monolithic integration of MEMS on Si CMOS platform. DC and radio-frequency performances of the individual PMOS and NMOS devices on the CMOS chip before and after the UNCD deposition were characterized. Electrical characteristics of CMOS after deposition of the UNCD film remained within the acceptable ranges, namely showing small variations in threshold voltage V th, transconductance g m, cut-off frequency f T and maximum oscillation frequency f max.more » Finally, the results suggest that low temperature UNCD deposition is compatible with CMOS to realize monolithically integrated CMOS-driven MEMS/NEMS based on UNCD.« less

On the integration of ultrananocrystalline diamond (UNCD) with CMOS chip

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mi, Hongyi; Yuan, Hao -Chih; Seo, Jung -Hun

A low temperature deposition of high quality ultrananocrystalline diamond (UNCD) film onto a finished Si-based CMOS chip was performed to investigate the compatibility of the UNCD deposition process with CMOS devices for monolithic integration of MEMS on Si CMOS platform. DC and radio-frequency performances of the individual PMOS and NMOS devices on the CMOS chip before and after the UNCD deposition were characterized. Electrical characteristics of CMOS after deposition of the UNCD film remained within the acceptable ranges, namely showing small variations in threshold voltage V th, transconductance g m, cut-off frequency f T and maximum oscillation frequency f max.more » Finally, the results suggest that low temperature UNCD deposition is compatible with CMOS to realize monolithically integrated CMOS-driven MEMS/NEMS based on UNCD.« less

Trace-transform invariants of tracks of high-velocity jets from the surface of tungsten droplets in the plasma flow

NASA Astrophysics Data System (ADS)

Gulyaev, P.; Jordan, V.; Gulyaev, I.; Dolmatov, A.

2017-05-01

The paper presents the analysis of the recorded tracks of high-velocity emission in the air-argon plasma flow during breaking up of tungsten microdroplets. This new physical effect of optical emission involves two stages. The first one includes thermionic emission of electrons from the surface of the melted tungsten droplet of 100-200 μm size and formation of the charged sphere of 3-5 mm diameter. After it reaches the breakdown electric potential, it collapses and produces a spherical shock wave and luminous radiation. The second stage includes previously unknown physical phenomenon of narrowly directed energy jet with velocity exceeding 4000 m/s from the surface of the tungsten droplet. The luminous spherical collapse and high-velocity jets were recorded using CMOS photo-array operating in a global shutter charge storage mode. Special features of the CMOS array scanning algorithm affect formation of distinctive signs of the recorded tracks, which stay invariant to trace transform (TT) with specific functional. The series of concentric circles were adopted as primitive object models (patterns) used in TT at the spherical collapse stage and linear segment of fixed thickness - at the high-velocity emission stage. The two invariants of the physical object, motion velocity and optical brightness distribution in the motion front, were adopted as desired identification features of tracks. The analytical expressions of the relation of 2D TT parameters and physical object motion invariants were obtained. The equations for spherical collapse stage correspond to Radon-Nikodym transform.

Characterization of pixel sensor designed in 180 nm SOI CMOS technology

NASA Astrophysics Data System (ADS)

Benka, T.; Havranek, M.; Hejtmanek, M.; Jakovenko, J.; Janoska, Z.; Marcisovska, M.; Marcisovsky, M.; Neue, G.; Tomasek, L.; Vrba, V.

2018-01-01

A new type of X-ray imaging Monolithic Active Pixel Sensor (MAPS), X-CHIP-02, was developed using a 180 nm deep submicron Silicon On Insulator (SOI) CMOS commercial technology. Two pixel matrices were integrated into the prototype chip, which differ by the pixel pitch of 50 μm and 100 μm. The X-CHIP-02 contains several test structures, which are useful for characterization of individual blocks. The sensitive part of the pixel integrated in the handle wafer is one of the key structures designed for testing. The purpose of this structure is to determine the capacitance of the sensitive part (diode in the MAPS pixel). The measured capacitance is 2.9 fF for 50 μm pixel pitch and 4.8 fF for 100 μm pixel pitch at -100 V (default operational voltage). This structure was used to measure the IV characteristics of the sensitive diode. In this work, we report on a circuit designed for precise determination of sensor capacitance and IV characteristics of both pixel types with respect to X-ray irradiation. The motivation for measurement of the sensor capacitance was its importance for the design of front-end amplifier circuits. The design of pixel elements, as well as circuit simulation and laboratory measurement techniques are described. The experimental results are of great importance for further development of MAPS sensors in this technology.

Which Photodiode to Use: A Comparison of CMOS-Compatible Structures

PubMed Central

Murari, Kartikeya; Etienne-Cummings, Ralph; Thakor, Nitish; Cauwenberghs, Gert

2010-01-01

While great advances have been made in optimizing fabrication process technologies for solid state image sensors, the need remains to be able to fabricate high quality photosensors in standard CMOS processes. The quality metrics depend on both the pixel architecture and the photosensitive structure. This paper presents a comparison of three photodiode structures in terms of spectral sensitivity, noise and dark current. The three structures are n+/p-sub, n-well/p-sub and p+/n-well/p-sub. All structures were fabricated in a 0.5 μm 3-metal, 2-poly, n-well process and shared the same pixel and readout architectures. Two pixel structures were fabricated—the standard three transistor active pixel sensor, where the output depends on the photodiode capacitance, and one incorporating an in-pixel capacitive transimpedance amplifier where the output is dependent only on a designed feedback capacitor. The n-well/p-sub diode performed best in terms of sensitivity (an improvement of 3.5 × and 1.6 × over the n+/p-sub and p+/n-well/p-sub diodes, respectively) and signal-to-noise ratio (1.5 × and 1.2 × improvement over the n+/p-sub and p+/n-well/p-sub diodes, respectively) while the p+/n-well/p-sub diode had the minimum (33% compared to other two structures) dark current for a given sensitivity. PMID:20454596

Which Photodiode to Use: A Comparison of CMOS-Compatible Structures.

PubMed

Murari, Kartikeya; Etienne-Cummings, Ralph; Thakor, Nitish; Cauwenberghs, Gert

2009-07-01

While great advances have been made in optimizing fabrication process technologies for solid state image sensors, the need remains to be able to fabricate high quality photosensors in standard CMOS processes. The quality metrics depend on both the pixel architecture and the photosensitive structure. This paper presents a comparison of three photodiode structures in terms of spectral sensitivity, noise and dark current. The three structures are n(+)/p-sub, n-well/p-sub and p(+)/n-well/p-sub. All structures were fabricated in a 0.5 mum 3-metal, 2-poly, n-well process and shared the same pixel and readout architectures. Two pixel structures were fabricated-the standard three transistor active pixel sensor, where the output depends on the photodiode capacitance, and one incorporating an in-pixel capacitive transimpedance amplifier where the output is dependent only on a designed feedback capacitor. The n-well/p-sub diode performed best in terms of sensitivity (an improvement of 3.5 x and 1.6 x over the n(+)/p-sub and p(+)/n-well/p-sub diodes, respectively) and signal-to-noise ratio (1.5 x and 1.2 x improvement over the n(+)/p-sub and p(+)/n-well/p-sub diodes, respectively) while the p(+)/n-well/p-sub diode had the minimum (33% compared to other two structures) dark current for a given sensitivity.

Lab-on-CMOS Integration of Microfluidics and Electrochemical Sensors

PubMed Central

Huang, Yue; Mason, Andrew J.

2013-01-01

This paper introduces a CMOS-microfluidics integration scheme for electrochemical microsystems. A CMOS chip was embedded into a micro-machined silicon carrier. By leveling the CMOS chip and carrier surface to within 100 nm, an expanded obstacle-free surface suitable for photolithography was achieved. Thin film metal planar interconnects were microfabricated to bridge CMOS pads to the perimeter of the carrier, leaving a flat and smooth surface for integrating microfluidic structures. A model device containing SU-8 microfluidic mixers and detection channels crossing over microelectrodes on a CMOS integrated circuit was constructed using the chip-carrier assembly scheme. Functional integrity of microfluidic structures and on-CMOS electrodes was verified by a simultaneous sample dilution and electrochemical detection experiment within multi-channel microfluidics. This lab-on-CMOS integration process is capable of high packing density, is suitable for wafer-level batch production, and opens new opportunities to combine the performance benefits of on-CMOS sensors with lab-on-chip platforms. PMID:23939616

Lab-on-CMOS integration of microfluidics and electrochemical sensors.

PubMed

Huang, Yue; Mason, Andrew J

2013-10-07

This paper introduces a CMOS-microfluidics integration scheme for electrochemical microsystems. A CMOS chip was embedded into a micro-machined silicon carrier. By leveling the CMOS chip and carrier surface to within 100 nm, an expanded obstacle-free surface suitable for photolithography was achieved. Thin film metal planar interconnects were microfabricated to bridge CMOS pads to the perimeter of the carrier, leaving a flat and smooth surface for integrating microfluidic structures. A model device containing SU-8 microfluidic mixers and detection channels crossing over microelectrodes on a CMOS integrated circuit was constructed using the chip-carrier assembly scheme. Functional integrity of microfluidic structures and on-CMOS electrodes was verified by a simultaneous sample dilution and electrochemical detection experiment within multi-channel microfluidics. This lab-on-CMOS integration process is capable of high packing density, is suitable for wafer-level batch production, and opens new opportunities to combine the performance benefits of on-CMOS sensors with lab-on-chip platforms.

Measurement and investigation of proton irradiation-induced charge transfer inefficiency in PPD CIS at different integration times

NASA Astrophysics Data System (ADS)

Xue, Yuanyuan; Wang, Zujun; Zhang, Fengqi; Bian, Jingying; Yao, Zhibin; He, Baoping; Liu, Minbo; Sheng, Jiangkun; Ma, Wuying; Dong, Guantao; Jin, Junshan

2018-04-01

Charge transfer inefficiency (CTI) is an important parameter for photodiode (PPD) CMOS image sensors (CISs). A test system was built and used to measure the CTI of PPD CIS devices at different integration times. The radiation effects of 3 MeV and 10 MeV protons on the CTI were investigated. The experiments were carried out at the EN Tandem Van de Graaff accelerator at proton fluences in the range 1010 to 1011 p/cm2. The CTI was measured within the 2 h following proton radiations. The dependence of CTI on integration time, proton energy and fluence were investigated. The CTI was observed to increase after proton irradiation: with the effect of irradiation with 3 MeV proton being more severe than that with 10 MeV protons. The CTI was also observed to decrease with increasing integration time, which is thought to be related to the charge density in the space charge region (SCR) of the CIS devices. This work has provided a simple method to measure the CTI and helped us to understand proton radiation effects on the CTI of PPD CISs.

Targeted Deposition of Antibodies on a Multiplex CMOS Microarray and Optimization of a Sensitive Immunoassay Using Electrochemical Detection

DTIC Science & Technology

2010-03-19

multiplex array. The array had capture Abs against ricin, Bacillus globigii spores, M13 phage , a1 acid glycoprotein, and fluorescein. Initially, antigen (Ag...comply with a collection of information if it does not display a currently valid OMB control number. 1. REPORT DATE JAN 2010 2. REPORT TYPE 3

Potentiometric Dye Imaging for Pheochromocytoma and Cortical Neurons with a Novel Measurement System Using an Integrated Complementary Metal-Oxide-Semiconductor Imaging Device

NASA Astrophysics Data System (ADS)

Kobayashi, Takuma; Tagawa, Ayato; Noda, Toshihiko; Sasagawa, Kiyotaka; Tokuda, Takashi; Hatanaka, Yumiko; Tamura, Hideki; Ishikawa, Yasuyuki; Shiosaka, Sadao; Ohta, Jun

2010-11-01

The combination of optical imaging with voltage-sensitive dyes is a powerful tool for studying the spatiotemporal patterns of neural activity and understanding the neural networks of the brain. To visualize the potential status of multiple neurons simultaneously using a compact instrument with high density and a wide range, we present a novel measurement system using an implantable biomedical photonic LSI device with a red absorptive light filter for voltage-sensitive dye imaging (BpLSI-red). The BpLSI-red was developed for sensing fluorescence by the on-chip LSI, which was designed by using complementary metal-oxide-semiconductor (CMOS) technology. A micro-electro-mechanical system (MEMS) microfabrication technique was used to postprocess the CMOS sensor chip; light-emitting diodes (LEDs) were integrated for illumination and to enable long-term cell culture. Using the device, we succeeded in visualizing the membrane potential of 2000-3000 cells and the process of depolarization of pheochromocytoma cells (PC12 cells) and mouse cerebral cortical neurons in a primary culture with cellular resolution. Therefore, our measurement application enables the detection of multiple neural activities simultaneously.

Highly Sensitive Electromechanical Piezoresistive Pressure Sensors Based on Large-Area Layered PtSe2 Films.

PubMed

Wagner, Stefan; Yim, Chanyoung; McEvoy, Niall; Kataria, Satender; Yokaribas, Volkan; Kuc, Agnieszka; Pindl, Stephan; Fritzen, Claus-Peter; Heine, Thomas; Duesberg, Georg S; Lemme, Max C

2018-05-23

Two-dimensional (2D) layered materials are ideal for micro- and nanoelectromechanical systems (MEMS/NEMS) due to their ultimate thinness. Platinum diselenide (PtSe 2 ), an exciting and unexplored 2D transition metal dichalcogenide material, is particularly interesting because its low temperature growth process is scalable and compatible with silicon technology. Here, we report the potential of thin PtSe 2 films as electromechanical piezoresistive sensors. All experiments have been conducted with semimetallic PtSe 2 films grown by thermally assisted conversion of platinum at a complementary metal-oxide-semiconductor (CMOS)-compatible temperature of 400 °C. We report high negative gauge factors of up to -85 obtained experimentally from PtSe 2 strain gauges in a bending cantilever beam setup. Integrated NEMS piezoresistive pressure sensors with freestanding PMMA/PtSe 2 membranes confirm the negative gauge factor and exhibit very high sensitivity, outperforming previously reported values by orders of magnitude. We employ density functional theory calculations to understand the origin of the measured negative gauge factor. Our results suggest PtSe 2 as a very promising candidate for future NEMS applications, including integration into CMOS production lines.

Control of Ambipolar Transport in SnO Thin-Film Transistors by Back-Channel Surface Passivation for High Performance Complementary-like Inverters.

PubMed

Luo, Hao; Liang, Lingyan; Cao, Hongtao; Dai, Mingzhi; Lu, Yicheng; Wang, Mei

2015-08-12

For ultrathin semiconductor channels, the surface and interface nature are vital and often dominate the bulk properties to govern the field-effect behaviors. High-performance thin-film transistors (TFTs) rely on the well-defined interface between the channel and gate dielectric, featuring negligible charge trap states and high-speed carrier transport with minimum carrier scattering characters. The passivation process on the back-channel surface of the bottom-gate TFTs is indispensable for suppressing the surface states and blocking the interactions between the semiconductor channel and the surrounding atmosphere. We report a dielectric layer for passivation of the back-channel surface of 20 nm thick tin monoxide (SnO) TFTs to achieve ambipolar operation and complementary metal oxide semiconductor (CMOS) like logic devices. This chemical passivation reduces the subgap states of the ultrathin channel, which offers an opportunity to facilitate the Fermi level shifting upward upon changing the polarity of the gate voltage. With the advent of n-type inversion along with the pristine p-type conduction, it is now possible to realize ambipolar operation using only one channel layer. The CMOS-like logic inverters based on ambipolar SnO TFTs were also demonstrated. Large inverter voltage gains (>100) in combination with wide noise margins are achieved due to high and balanced electron and hole mobilities. The passivation also improves the long-term stability of the devices. The ability to simultaneously achieve field-effect inversion, electrical stability, and logic function in those devices can open up possibilities for the conventional back-channel surface passivation in the CMOS-like electronics.

A zinc oxide nanorod ammonia microsensor integrated with a readout circuit on-a-chip.

PubMed

Yang, Ming-Zhi; Dai, Ching-Liang; Wu, Chyan-Chyi

2011-01-01

A zinc oxide nanorod ammonia microsensor integrated with a readout circuit on-a-chip fabricated using the commercial 0.35 μm complementary metal oxide semiconductor (CMOS) process was investigated. The structure of the ammonia sensor is composed of a sensitive film and polysilicon electrodes. The ammonia sensor requires a post-process to etch the sacrificial layer, and to coat the sensitive film on the polysilicon electrodes. The sensitive film that is prepared by a hydrothermal method is made of zinc oxide. The sensor resistance changes when the sensitive film adsorbs or desorbs ammonia gas. The readout circuit is used to convert the sensor resistance into the voltage output. Experiments show that the ammonia sensor has a sensitivity of about 1.5 mV/ppm at room temperature.

Epoxy Chip-in-Carrier Integration and Screen-Printed Metalization for Multichannel Microfluidic Lab-on-CMOS Microsystems.

PubMed

Li, Lin; Yin, Heyu; Mason, Andrew J

2018-04-01

The integration of biosensors, microfluidics, and CMOS instrumentation provides a compact lab-on-CMOS microsystem well suited for high throughput measurement. This paper describes a new epoxy chip-in-carrier integration process and two planar metalization techniques for lab-on-CMOS that enable on-CMOS electrochemical measurement with multichannel microfluidics. Several design approaches with different fabrication steps and materials were experimentally analyzed to identify an ideal process that can achieve desired capability with high yield and low material and tool cost. On-chip electrochemical measurements of the integrated assembly were performed to verify the functionality of the chip-in-carrier packaging and its capability for microfluidic integration. The newly developed CMOS-compatible epoxy chip-in-carrier process paves the way for full implementation of many lab-on-CMOS applications with CMOS ICs as core electronic instruments.

Accelerated life testing effects on CMOS microcircuit characteristics

NASA Technical Reports Server (NTRS)

1977-01-01

Accelerated life tests were performed on CMOS microcircuits to predict their long term reliability. The consistency of the CMOS microcircuit activation energy between the range of 125 C to 200 C and the range 200 C to 250 C was determined. Results indicate CMOS complexity and the amount of moisture detected inside the devices after testing influences time to failure of tested CMOS devices.

Hybrid CMOS-Graphene Sensor Array for Subsecond Dopamine Detection.

PubMed

Nasri, Bayan; Wu, Ting; Alharbi, Abdullah; You, Kae-Dyi; Gupta, Mayank; Sebastian, Sunit P; Kiani, Roozbeh; Shahrjerdi, Davood

2017-12-01

We introduce a hybrid CMOS-graphene sensor array for subsecond measurement of dopamine via fast-scan cyclic voltammetry (FSCV). The prototype chip has four independent CMOS readout channels, fabricated in a 65-nm process. Using planar multilayer graphene as biologically compatible sensing material enables integration of miniaturized sensing electrodes directly above the readout channels. Taking advantage of the chemical specificity of FSCV, we introduce a region of interest technique, which subtracts a large portion of the background current using a programmable low-noise constant current at about the redox potentials. We demonstrate the utility of this feature for enhancing the sensitivity by measuring the sensor response to a known dopamine concentration in vitro at three different scan rates. This strategy further allows us to significantly reduce the dynamic range requirements of the analog-to-digital converter (ADC) without compromising the measurement accuracy. We show that an integrating dual-slope ADC is adequate for digitizing the background-subtracted current. The ADC operates at a sampling frequency of 5-10 kHz and has an effective resolution of about 60 pA, which corresponds to a theoretical dopamine detection limit of about 6 nM. Our hybrid sensing platform offers an effective solution for implementing next-generation FSCV devices that can enable precise recording of dopamine signaling in vivo on a large scale.

Advancing the technology of monolithic CMOS detectors for use as x-ray imaging spectrometers

NASA Astrophysics Data System (ADS)

Kenter, Almus; Kraft, Ralph; Gauron, Thomas; Amato, Stephen

2017-08-01

The Smithsonian Astrophysical Observatory (SAO) in collaboration with SRI/Sarnoff has been engaged in a multi year effort to advance the technology of monolithic back-thinned CMOS detectors for use as X-ray imaging spectrometers. The long term goal of this campaign is to produce X-ray Active Pixel Sensor (APS) detectors with Fano limited performance over the 0.1-10keV band while incorporating the many benefits of CMOS technology. These benefits include: low power consumption, radiation "hardness", high levels of integration, and very high read rates. Such devices would be ideal for candidate post 2020 decadal missions such as LYNX and for smaller more immediate applications such as CubeX. Devices from a recent fabrication have been back-thinned, packaged and tested for soft X-ray response. These devices have 16μm pitch, 6 Transistor Pinned Photo Diode (6TPPD) pixels with ˜135μV/electron sensitivity and a highly parallel signal chain. These new detectors are fabricated on 10μm epitaxial silicon and have a 1k by 1k format. We present details of our camera design and device performance with particular emphasis on those aspects of interest to single photon counting X-ray astronomy. These features include read noise, X-ray spectral response and quantum efficiency.

A Low-power CMOS BFSK Transceiver for Health Monitoring Systems.

PubMed

Kim, Sungho; Lepkowski, William; Wilk, Seth J; Thornton, Trevor J; Bakkaloglu, Bertan

2011-01-01

A CMOS low-power transceiver for implantable and external health monitoring devices operating in the MICS band is presented. The LNA core has an integrated mixer in a folded configuration to reuse the bias current, allowing high linearity with a low power supply levels. The baseband strip consists of a pseudo differential MOS-C band-pass filter achieving demodulation of 150kHz-offset BFSK signals. An all digital frequency-locked loop is used for LO generation in the RX mode and for driving a class AB power amplifier in the TX mode. The MICS transceiver is designed and fabricated in a 0.18μm 1-poly, 6-metal CMOS process. The sensitivities of -70dBm and -98dBm were achieved with NF of 40dB and 11dB at the data rate of 100kb/s while consuming only 600μW and 1.5mW at 1.2V and 1.8V, respectively. The BERs are less than 10 -3 at the input powers of -70dBm at 1.2V and -98dBm at 1.8V at the data rate of 100kb/s. Finally, the output power of the transmitter is 0dBm for a power consumption of 1.8mW.

Modeling of Sonos Memory Cell Erase Cycle

NASA Technical Reports Server (NTRS)

Phillips, Thomas A.; MacLeond, Todd C.; Ho, Fat D.

2010-01-01

Silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile semiconductor memories (NVSMS) have many advantages. These memories are electrically erasable programmable read-only memories (EEPROMs). They utilize low programming voltages, endure extended erase/write cycles, are inherently resistant to radiation, and are compatible with high-density scaled CMOS for low power, portable electronics. The SONOS memory cell erase cycle was investigated using a nonquasi-static (NQS) MOSFET model. The SONOS floating gate charge and voltage, tunneling current, threshold voltage, and drain current were characterized during an erase cycle. Comparisons were made between the model predictions and experimental device data.

Magnetic Random Access Memory for Embedded Computing

DTIC Science & Technology

2007-10-29

layer, w he free layer hose resistan .  ce  2. Develop and model  data  storage circuits  based  on the MTJ cells. 3. Integrated the MTJ cells into a CMOS...suggested the two methods shown in Fig. 4.5 [95]. The circuit shown at the top of the figure uses NMOS pass transistors to load data , which is the simplest... method but requires careful design to avoid charge sharing and accommodate the data -dependent loading seen at the DATA input. With additional

Scientific CMOS Pixels

NASA Astrophysics Data System (ADS)

Janesick, James; Gunawan, Ferry; Dosluoglu, Taner; Tower, John; McCaffrey, Niel

2002-08-01

High performance CMOS pixels are introduced; and their development is discussed. 3T (3-transistor) photodiode, 5T pinned diode, 6T photogate and 6T photogate back illuminated CMOS pixels are examined in detail, and the latter three are considered as scientific pixels. The advantages and disadvantagesof these options for scientific CMOS pixels are examined.Pixel characterization, which is used to gain a better understanding of CMOS pixels themselves, is also discussed.

Scientific CMOS Pixels

NASA Astrophysics Data System (ADS)

Janesick, J.; Gunawan, F.; Dosluoglu, T.; Tower, J.; McCaffrey, N.

High performance CMOS pixels are introduced and their development is discussed. 3T (3-transistor) photodiode, 5T pinned diode, 6T photogate and 6T photogate back illuminated CMOS pixels are examined in detail, and the latter three are considered as scientific pixels. The advantages and disadvantages of these options for scientific CMOS pixels are examined. Pixel characterization, which is used to gain a better understanding of CMOS pixels themselves, is also discussed.

Injection Locking Techniques for Spectrum Analysis

NASA Astrophysics Data System (ADS)

Gathma, Timothy D.; Buckwalter, James F.

2011-04-01

Wideband spectrum analysis supports future communication systems that reconfigure and adapt to the capacity of the spectral environment. While test equipment manufacturers offer wideband spectrum analyzers with excellent sensitivity and resolution, these spectrum analyzers typically cannot offer acceptable size, weight, and power (SWAP). CMOS integrated circuits offer the potential to fully integrate spectrum analysis capability with analog front-end circuitry and digital signal processing on a single chip. Unfortunately, CMOS lacks high-Q passives and wideband resonator tunability that is necessary for heterodyne implementations of spectrum analyzers. As an alternative to the heterodyne receiver architectures, two nonlinear methods for performing wideband, low-power spectrum analysis are presented. The first method involves injecting the spectrum of interest into an array of injection-locked oscillators. The second method employs the closed loop dynamics of both injection locking and phase locking to independently estimate the injected frequency and power.

Radiation Performance of Commercial SiGe HBT BiCMOS-High Speed Operational Amplifiers

NASA Technical Reports Server (NTRS)

Chen, Dakai; Pellish, Jonathan; Phan, Anthony; Kim, Hak; Burns, Sam; Albarian, Rafi; Holcombe, Bruce; Little, Bradley; Salzman, James; LaBel, Kenneth

2010-01-01

We present results on heavy-ion and proton irradiations for commercial SiGe BiCMOS operational amplifiers: LTC6400-20 from Linear Technology and THS4304 from Texas Instruments. We found that the devices are susceptible to heavy-ion-induced SETs. The SET cross-sections increase with increasing operating frequency. The LTC6400 exhibits a LET(sub th) < 7.4 MeV·sq cm/mg for frequencies ranging from 10 to 1000 MHz. The THS4304 exhibits a LET(sub th) < 4.4 MeV·sq cm/mg at 200 MHz; the LET(sub th) decreases with increasing frequency. The significance of the SETs also increases with frequency. The SETs at 1000 MHz can erase several signal cycles. We al.so found that the LTC6400 is relatively robust against 198 and 54 MeV protons. We did not observe angular sensitivity from the proton irradiations.

Thermal neutron detector based on COTS CMOS imagers and a conversion layer containing Gadolinium

NASA Astrophysics Data System (ADS)

Pérez, Martín; Blostein, Juan Jerónimo; Bessia, Fabricio Alcalde; Tartaglione, Aureliano; Sidelnik, Iván; Haro, Miguel Sofo; Suárez, Sergio; Gimenez, Melisa Lucía; Berisso, Mariano Gómez; Lipovetzky, Jose

2018-06-01

In this work we will introduce a novel low cost position sensitive thermal neutron detection technique, based on a Commercial Off The Shelf CMOS image sensor covered with a Gadolinium containing conversion layer. The feasibility of the neutron detection technique implemented in this work has been experimentally demonstrated. A thermal neutron detection efficiency of 11.3% has been experimentally obtained with a conversion layer of 11.6 μm. It was experimentally verified that the thermal neutron detection efficiency of this technique is independent on the intensity of the incident thermal neutron flux, which was confirmed for conversion layers of different thicknesses. Based on the experimental results, a spatial resolution better than 25 μm is expected. This spatial resolution makes the proposed technique specially useful for neutron beam characterization, neutron beam dosimetry, high resolution neutron imaging, and several neutron scattering techniques.

Monolithic silicon-photonic platforms in state-of-the-art CMOS SOI processes [Invited].

PubMed

Stojanović, Vladimir; Ram, Rajeev J; Popović, Milos; Lin, Sen; Moazeni, Sajjad; Wade, Mark; Sun, Chen; Alloatti, Luca; Atabaki, Amir; Pavanello, Fabio; Mehta, Nandish; Bhargava, Pavan

2018-05-14

Integrating photonics with advanced electronics leverages transistor performance, process fidelity and package integration, to enable a new class of systems-on-a-chip for a variety of applications ranging from computing and communications to sensing and imaging. Monolithic silicon photonics is a promising solution to meet the energy efficiency, sensitivity, and cost requirements of these applications. In this review paper, we take a comprehensive view of the performance of the silicon-photonic technologies developed to date for photonic interconnect applications. We also present the latest performance and results of our "zero-change" silicon photonics platforms in 45 nm and 32 nm SOI CMOS. The results indicate that the 45 nm and 32 nm processes provide a "sweet-spot" for adding photonic capability and enhancing integrated system applications beyond the Moore-scaling, while being able to offload major communication tasks from more deeply-scaled compute and memory chips without complicated 3D integration approaches.

Evaluation of a ''CMOS'' Imager for Shadow Mask Hard X-ray Telescope

NASA Technical Reports Server (NTRS)

Desai, Upendra D.; Orwig, Larry E.; Oergerle, William R. (Technical Monitor)

2002-01-01

We have developed a hard x-ray coder that provides high angular resolution imaging capability using a coarse position sensitive image plane detector. The coder consists of two Fresnel zone plates. (FZP) Two such 'FZP's generate Moire fringe patterns whose frequency and orientation define the arrival direction of a beam with respect to telescope axis. The image plane detector needs to resolve the Moire fringe pattern. Pixilated detectors can be used as an image plane detector. The recently available 'CMOS' imager could provide a very low power large area image plane detector for hard x-rays. We have looked into a unit made by Rad-Icon Imaging Corp. The Shadow-Box 1024 x-ray camera is a high resolution 1024xl024 pixel detector of 50x50 mm area. It is a very low power, stand alone camera. We present some preliminary results of our investigation of evaluation of such camera.

A K-Band Low-Power Phase Shifter Based on Injection Locked Oscillator in 0.13 μm CMOS Technology

NASA Astrophysics Data System (ADS)

Qiu, Qi-Lin; Yu, Xiao-Peng; Sui, Wen-Quan

2017-11-01

In this paper, the design challenges of the injection-locked oscillator (ILO)-based phase shifter are reviewed and analyzed. The key design considerations such as the operating frequency, locking range, and linearity of the phase shifters are analysed in detail. It is possible to optimize the phase shifter in certain parameters such as ultra-low power while meeting the requirements of a certain system. As a design example, a K-band phase shifter is implemented using a commercial 0.13 μm CMOS technology, where a conventional LC tank based topology is implemented but optimised with a good balance among power consumption, working range, sensitivity, and silicon area, etc. Measurement results show that the proposed phase shift is able to work at 22-23.4 GHz with a range of 180∘ while consuming 3.14 mW from a 1.2 V supply voltage.

A 256 pixel magnetoresistive biosensor microarray in 0.18μm CMOS

PubMed Central

Hall, Drew A.; Gaster, Richard S.; Makinwa, Kofi; Wang, Shan X.; Murmann, Boris

2014-01-01

Magnetic nanotechnologies have shown significant potential in several areas of nanomedicine such as imaging, therapeutics, and early disease detection. Giant magnetoresistive spin-valve (GMR SV) sensors coupled with magnetic nanotags (MNTs) possess great promise as ultra-sensitive biosensors for diagnostics. We report an integrated sensor interface for an array of 256 GMR SV biosensors designed in 0.18 μm CMOS. Arranged like an imager, each of the 16 column level readout channels contains an analog front- end and a compact ΣΔ modulator (0.054 mm2) with 84 dB of dynamic range and an input referred noise of 49 nT/√Hz. Performance is demonstrated through detection of an ovarian cancer biomarker, secretory leukocyte peptidase inhibitor (SLPI), spiked at concentrations as low as 10 fM. This system is designed as a replacement for optical protein microarrays while also providing real-time kinetics monitoring. PMID:24761029

Integrated Amorphous Silicon p-i-n Temperature Sensor for CMOS Photonics.

PubMed

Rao, Sandro; Pangallo, Giovanni; Della Corte, Francesco Giuseppe

2016-01-06

Hydrogenated amorphous silicon (a-Si:H) shows interesting optoelectronic and technological properties that make it suitable for the fabrication of passive and active micro-photonic devices, compatible moreover with standard microelectronic devices on a microchip. A temperature sensor based on a hydrogenated amorphous silicon p-i-n diode integrated in an optical waveguide for silicon photonics applications is presented here. The linear dependence of the voltage drop across the forward-biased diode on temperature, in a range from 30 °C up to 170 °C, has been used for thermal sensing. A high sensitivity of 11.9 mV/°C in the bias current range of 34-40 nA has been measured. The proposed device is particularly suitable for the continuous temperature monitoring of CMOS-compatible photonic integrated circuits, where the behavior of the on-chip active and passive devices are strongly dependent on their operating temperature.

Effect of drain current on appearance probability and amplitude of random telegraph noise in low-noise CMOS image sensors

NASA Astrophysics Data System (ADS)

Ichino, Shinya; Mawaki, Takezo; Teramoto, Akinobu; Kuroda, Rihito; Park, Hyeonwoo; Wakashima, Shunichi; Goto, Tetsuya; Suwa, Tomoyuki; Sugawa, Shigetoshi

2018-04-01

Random telegraph noise (RTN), which occurs in in-pixel source follower (SF) transistors, has become one of the most critical problems in high-sensitivity CMOS image sensors (CIS) because it is a limiting factor of dark random noise. In this paper, the behaviors of RTN toward changes in SF drain current conditions were analyzed using a low-noise array test circuit measurement system with a floor noise of 35 µV rms. In addition to statistical analysis by measuring a large number of transistors (18048 transistors), we also analyzed the behaviors of RTN parameters such as amplitude and time constants in the individual transistors. It is demonstrated that the appearance probability of RTN becomes small under a small drain current condition, although large-amplitude RTN tends to appear in a very small number of cells.

High-Speed Scanning Interferometer Using CMOS Image Sensor and FPGA Based on Multifrequency Phase-Tracking Detection

NASA Technical Reports Server (NTRS)

Ohara, Tetsuo

2012-01-01

A sub-aperture stitching optical interferometer can provide a cost-effective solution for an in situ metrology tool for large optics; however, the currently available technologies are not suitable for high-speed and real-time continuous scan. NanoWave s SPPE (Scanning Probe Position Encoder) has been proven to exhibit excellent stability and sub-nanometer precision with a large dynamic range. This same technology can transform many optical interferometers into real-time subnanometer precision tools with only minor modification. The proposed field-programmable gate array (FPGA) signal processing concept, coupled with a new-generation, high-speed, mega-pixel CMOS (complementary metal-oxide semiconductor) image sensor, enables high speed (>1 m/s) and real-time continuous surface profiling that is insensitive to variation of pixel sensitivity and/or optical transmission/reflection. This is especially useful for large optics surface profiling.

A high sensitive 66 dB linear dynamic range receiver for 3-D laser radar

NASA Astrophysics Data System (ADS)

Ma, Rui; Zheng, Hao; Zhu, Zhangming

2017-08-01

This study presents a CMOS receiver chip realized in 0.18 μm standard CMOS technology and intended for high precision 3-D laser radar. The chip includes an adjustable gain transimpedance pre-amplifier, a post-amplifier and two timing comparators. An additional feedback is employed in the regulated cascode transimpedance amplifier to decrease the input impedance, and a variable gain transimpedance amplifier controlled by digital switches and analog multiplexer is utilized to realize four gain modes, extending the input dynamic range. The measurement shows that the highest transimpedance of the channel is 50 k {{Ω }}, the uncompensated walk error is 1.44 ns in a wide linear dynamic range of 66 dB (1:2000), and the input referred noise current is 2.3 pA/\\sqrt{{Hz}} (rms), resulting in a very low detectable input current of 1 μA with SNR = 5.

An integrated 12.5-Gb/s optoelectronic receiver with a silicon avalanche photodetector in standard SiGe BiCMOS technology.

PubMed

Youn, Jin-Sung; Lee, Myung-Jae; Park, Kang-Yeob; Rücker, Holger; Choi, Woo-Young

2012-12-17

An optoelectronic integrated circuit (OEIC) receiver is realized with standard 0.25-μm SiGe BiCMOS technology for 850-nm optical interconnect applications. The OEIC receiver consists of a Si avalanche photodetector, a transimpedance amplifier with a DC-balanced buffer, a tunable equalizer, and a limiting amplifier. The fabricated OEIC receiver successfully detects 12.5-Gb/s 2(31)-1 pseudorandom bit sequence optical data with the bit-error rate less than 10(-12) at incident optical power of -7 dBm. The OEIC core has 1000 μm x 280 μm chip area, and consumes 59 mW from 2.5-V supply. To the best of our knowledge, this OEIC receiver achieves the highest data rate with the smallest sensitivity as well as the best power efficiency among integrated OEIC receivers fabricated with standard Si technology.

High granularity tracker based on a Triple-GEM optically read by a CMOS-based camera

NASA Astrophysics Data System (ADS)

Marafini, M.; Patera, V.; Pinci, D.; Sarti, A.; Sciubba, A.; Spiriti, E.

2015-12-01

The detection of photons produced during the avalanche development in gas chambers has been the subject of detailed studies in the past. The great progresses achieved in last years in the performance of micro-pattern gas detectors on one side and of photo-sensors on the other provide the possibility of making high granularity and very sensitive particle trackers. In this paper, the results obtained with a triple-GEM structure read-out by a CMOS based sensor are described. The use of an He/CF4 (60/40) gas mixture and a detailed optimization of the electric fields made possible to obtain a very high GEM light yield. About 80 photons per primary electron were detected by the sensor resulting in a very good capability of tracking both muons from cosmic rays and electrons from natural radioactivity.

New readout integrated circuit using continuous time fixed pattern noise correction

NASA Astrophysics Data System (ADS)

Dupont, Bertrand; Chammings, G.; Rapellin, G.; Mandier, C.; Tchagaspanian, M.; Dupont, Benoit; Peizerat, A.; Yon, J. J.

2008-04-01

LETI has been involved in IRFPA development since 1978; the design department (LETI/DCIS) has focused its work on new ROIC architecture since many years. The trend is to integrate advanced functions into the CMOS design to achieve cost efficient sensors production. Thermal imaging market is today more and more demanding of systems with instant ON capability and low power consumption. The purpose of this paper is to present the latest developments of fixed pattern noise continuous time correction. Several architectures are proposed, some are based on hardwired digital processing and some are purely analog. Both are using scene based algorithms. Moreover a new method is proposed for simultaneous correction of pixel offsets and sensitivities. In this scope, a new architecture of readout integrated circuit has been implemented; this architecture is developed with 0.18μm CMOS technology. The specification and the application of the ROIC are discussed in details.

A fully integrated direct-conversion digital satellite tuner in 0.18 μm CMOS

NASA Astrophysics Data System (ADS)

Si, Chen; Zengwang, Yang; Mingliang, Gu

2011-04-01

A fully integrated direct-conversion digital satellite tuner for DVB-S/S2 and ABS-S applications is presented. A broadband noise-canceling Balun-LNA and passive quadrature mixers provided a high-linearity low noise RF front-end, while the synthesizer integrated the loop filter to reduce the solution cost and system debug time. Fabricated in 0.18 μm CMOS, the chip achieves a less than 7.6 dB noise figure over a 900-2150 MHz L-band, while the measured sensitivity for 4.42 MS/s QPSK-3/4 mode is -91 dBm at the PCB connector. The fully integrated integer-N synthesizer operating from 2150 to 4350 MHz achieves less than 1 °C integrated phase error. The chip consumes about 145 mA at a 3.3 V supply with internal integrated LDOs.

CMOS capacitive biosensors for highly sensitive biosensing applications.

PubMed

Chang, An-Yu; Lu, Michael S-C

2013-01-01

Magnetic microbeads are widely used in biotechnology and biomedical research for manipulation and detection of cells and biomolecules. Most lab-on-chip systems capable of performing manipulation and detection require external instruments to perform one of the functions, leading to increased size and cost. This work aims at developing an integrated platform to perform these two functions by implementing electromagnetic microcoils and capacitive biosensors on a CMOS (complementary metal oxide semiconductor) chip. Compared to most magnetic-type sensors, our detection method requires no externally applied magnetic fields and the associated fabrication is less complicated. In our experiment, microbeads coated with streptavidin were driven to the sensors located in the center of microcoils with functionalized anti-streptavidin antibody. Detection of a single microbead was successfully demonstrated using a capacitance-to-frequency readout. The average capacitance changes for the experimental and control groups were -5.3 fF and -0.2 fF, respectively.

Heavy Ion Transient Characterization of a Photobit Hardened-by-Design Active Pixel Sensor Array

NASA Technical Reports Server (NTRS)

Marshall, Paul W.; Byers, Wheaton B.; Conger, Christopher; Eid, El-Sayed; Gee, George; Jones, Michael R.; Marshall, Cheryl J.; Reed, Robert; Pickel, Jim; Kniffin, Scott

2002-01-01

This paper presents heavy ion data on the single event transient (SET) response of a Photobit active pixel sensor (APS) four quadrant test chip with different radiation tolerant designs in a standard 0.35 micron CMOS process. The physical design techniques of enclosed geometry and P-channel guard rings are used to design the four N-type active photodiode pixels as described in a previous paper. Argon transient measurements on the 256 x 256 chip array as a function of incident angle show a significant variation in the amount of charge collected as well as the charge spreading dependent on the pixel type. The results are correlated with processing and design information provided by Photobit. In addition, there is a large degree of statistical variability between individual ion strikes. No latch-up is observed up to an LET of 106 MeV/mg/sq cm.

CALORIC: A readout chip for high granularity calorimeter

DOE Office of Scientific and Technical Information (OSTI.GOV)

Royer, L.; Bonnard, J.; Manen, S.

2011-07-01

A very-front-end electronics has been developed to fulfil requirements for the next generation of electromagnetic calorimeters. The compactness of this kind of detector and its large number of channels (up to several millions) impose a drastic limitation of the power consumption and a high level of integration. The electronic channel proposed is first of all composed of a low-noise Charge Sensitive Amplifier (CSA) able to amplify the charge delivered by a silicon diode up to 10 pC. Next, a two-gain shaping, based on a Gated Integration (G.I.), is implemented to cover the 15 bits dynamic range required: a high gainmore » shaper processes signals from 4 fC (charge corresponding to the MIP) up to 1 pC, and a low gain filter handles charges up to 10 pC. The G.I. performs also the analog memorization of the signal until it is digitalized. Hence, the analog-to-digital conversion is carried out through a low-power 12-bit cyclic ADC. If the signal overloads the high-gain channel dynamic range, a comparator selects the low-gain channel instead. Moreover, an auto-trigger channel has been implemented in order to select and store a valid event over the noise. The timing sequence of the channel is managed by a digital IP. It controls the G.I. switches, generates all needed clocks, drives the ADC and delivers the final result over 12 bits. The whole readout channel is power controlled, which permits to reduce the consumption according to the duty cycle of the beam collider. Simulations have been performed with Spectre simulator on the prototype chip designed with the 0.35 {mu}m CMOS technology from Austriamicrosystems. Results show a non-linearity better than 0.1% for the high-gain channel, and a non-linearity limited to 1% for the low-gain channel. The Equivalent Noise Charge referred to the input of the channel is evaluated to 0.4 fC complying with the MIP/10 limit. With the timing sequence of the International Linear Collider, which presents a duty cycle of 1%, the power consumption of the complete channel is limited to 43 {mu}W thanks to the power pulsing. The total area of the channel is 1.2 mm{sup 2} with an analog memory depth of 16. (authors)« less

Interactions of hydrogen with amorphous hafnium oxide

NASA Astrophysics Data System (ADS)

Kaviani, Moloud; Afanas'ev, Valeri V.; Shluger, Alexander L.

2017-02-01

We used density functional theory (DFT) calculations to study the interaction of hydrogen with amorphous hafnia (a -HfO2 ) using a hybrid exchange-correlation functional. Injection of atomic hydrogen, its diffusion towards electrodes, and ionization can be seen as key processes underlying charge instability of high-permittivity amorphous hafnia layers in many applications. Hydrogen in many wide band gap crystalline oxides exhibits negative-U behavior (+1 and -1 charged states are thermodynamically more stable than the neutral state) . Our results show that in a -HfO2 hydrogen is also negative-U, with charged states being the most thermodynamically stable at all Fermi level positions. However, metastable atomic hydrogen can share an electron with intrinsic electron trapping precursor sites [Phys. Rev. B 94, 020103 (2016)., 10.1103/PhysRevB.94.020103] forming a [etr -+O -H ] center, which is lower in energy on average by about 0.2 eV. These electron trapping sites can affect both the dynamics and thermodynamics of the interaction of hydrogen with a -HfO2 and the electrical behavior of amorphous hafnia films in CMOS devices.

Fully integrated low-noise readout circuit with automatic offset cancellation loop for capacitive microsensors.

PubMed

Song, Haryong; Park, Yunjong; Kim, Hyungseup; Cho, Dong-Il Dan; Ko, Hyoungho

2015-10-14

Capacitive sensing schemes are widely used for various microsensors; however, such microsensors suffer from severe parasitic capacitance problems. This paper presents a fully integrated low-noise readout circuit with automatic offset cancellation loop (AOCL) for capacitive microsensors. The output offsets of the capacitive sensing chain due to the parasitic capacitances and process variations are automatically removed using AOCL. The AOCL generates electrically equivalent offset capacitance and enables charge-domain fine calibration using a 10-bit R-2R digital-to-analog converter, charge-transfer switches, and a charge-storing capacitor. The AOCL cancels the unwanted offset by binary-search algorithm based on 10-bit successive approximation register (SAR) logic. The chip is implemented using 0.18 μm complementary metal-oxide-semiconductor (CMOS) process with an active area of 1.76 mm². The power consumption is 220 μW with 3.3 V supply. The input parasitic capacitances within the range of -250 fF to 250 fF can be cancelled out automatically, and the required calibration time is lower than 10 ms.

Fully Integrated Low-Noise Readout Circuit with Automatic Offset Cancellation Loop for Capacitive Microsensors

PubMed Central

Song, Haryong; Park, Yunjong; Kim, Hyungseup; Cho, Dong-il Dan; Ko, Hyoungho

2015-01-01

Capacitive sensing schemes are widely used for various microsensors; however, such microsensors suffer from severe parasitic capacitance problems. This paper presents a fully integrated low-noise readout circuit with automatic offset cancellation loop (AOCL) for capacitive microsensors. The output offsets of the capacitive sensing chain due to the parasitic capacitances and process variations are automatically removed using AOCL. The AOCL generates electrically equivalent offset capacitance and enables charge-domain fine calibration using a 10-bit R-2R digital-to-analog converter, charge-transfer switches, and a charge-storing capacitor. The AOCL cancels the unwanted offset by binary-search algorithm based on 10-bit successive approximation register (SAR) logic. The chip is implemented using 0.18 μm complementary metal-oxide-semiconductor (CMOS) process with an active area of 1.76 mm2. The power consumption is 220 μW with 3.3 V supply. The input parasitic capacitances within the range of −250 fF to 250 fF can be cancelled out automatically, and the required calibration time is lower than 10 ms. PMID:26473877

Multi-level Capacitive Memory Effect in Metal/Oxide/Floating-Schottky Junction

NASA Astrophysics Data System (ADS)

Choi, Gahyun; Jung, Sungchul; Yoon, Hoon Hahn; Jeon, Youngeun; Park*, Kibog

2015-03-01

A memory computing (memcomputing) system can store and process information at the same physical location simultaneously. The essential components of memcomputing are passive devices with memory functionality, such as memristor, memcapacitor, and meminductor. We report the realization of a Schottky contact memcapacitor compatible with the current Si CMOS technology. Our memcapacitor is formed by depositing a stack of metal and oxide thin films on top of a Schottky contact. Here, the metal electrode of the Schottky contact is floating. The working principle of our memcapacitor is based on the fact that the depletion width of the Schottky contact varies according to the amount of charge stored in the floating metal electrode. The voltage pulse applied across the Metal/Oxide/Floating-Schottky junction controls charge flow in the Schottky contact and determines the amount of charge stored eventually. It is demonstrated experimentally that our memcapacitor exhibits hysteresis behaviors in capacitance-voltage curves and possesses multiple capacitance values that are switchable by the applied voltage pulse. Supported by NRF in South Korea (2013R1A1A2007070).

Design and evaluation of wide-range and low-power analog front-end enabling body-implanted devices to monitor charge injection properties

NASA Astrophysics Data System (ADS)

Ito, Keita; Uno, Shoma; Goto, Tatsuya; Takezawa, Yoshiki; Harashima, Takuya; Morikawa, Takumi; Nishino, Satoru; Kino, Hisashi; Kiyoyama, Koji; Tanaka, Tetsu

2017-04-01

For safe electrical stimulation with body-implanted devices, the degradation of stimulus electrodes must be considered because it causes the unexpected electrolysis of water and the destruction of tissues. To monitor the charge injection property (CIP) of stimulus electrodes while these devices are implanted, we have proposed a charge injection monitoring system (CIMS). CIMS can safely read out voltages produced by a biphasic current pulse to a stimulus electrode and CIP is calculated from waveforms of the acquired voltages. In this paper, we describe a wide-range and low-power analog front-end (AFE) for CIMS that has variable gain-frequency characteristics and low-power analog-to-digital (A/D) conversion to adjust to the degradation of stimulus electrodes. The designed AFE was fabricated with 0.18 µm CMOS technology and achieved a valuable gain of 20-60 dB, an upper cutoff frequency of 0.2-10 kHz, and low-power interleaving A/D conversion. In addition, we successfully measured the CIP of stimulus electrodes for body-implanted devices using CIMS.

SEMICONDUCTOR INTEGRATED CIRCUITS: An asymmetric MOSFET-C band-pass filter with on-chip charge pump auto-tuning

NASA Astrophysics Data System (ADS)

Fangxiong, Chen; Min, Lin; Heping, Ma; Hailong, Jia; Yin, Shi; Forster, Dai

2009-08-01

An asymmetric MOSFET-C band-pass filter (BPF) with on chip charge pump auto-tuning is presented. It is implemented in UMC (United Manufacturing Corporation) 0.18 μm CMOS process technology. The filter system with auto-tuning uses a master-slave technique for continuous tuning in which the charge pump outputs 2.663 V, much higher than the power supply voltage, to improve the linearity of the filter. The main filter with third order low-pass and second order high-pass properties is an asymmetric band-pass filter with bandwidth of 2.730-5.340 MHz. The in-band third order harmonic input intercept point (IIP3) is 16.621 dBm, with 50 Ω as the source impedance. The input referred noise is about 47.455 μVrms. The main filter dissipates 3.528 mW while the auto-tuning system dissipates 2.412 mW from a 1.8 V power supply. The filter with the auto-tuning system occupies 0.592 mm2 and it can be utilized in GPS (global positioning system) and Bluetooth systems.

A high-throughput flow cytometry-on-a-CMOS platform for single-cell dielectric spectroscopy at microwave frequencies.

PubMed

Chien, Jun-Chau; Ameri, Ali; Yeh, Erh-Chia; Killilea, Alison N; Anwar, Mekhail; Niknejad, Ali M

2018-06-06

This work presents a microfluidics-integrated label-free flow cytometry-on-a-CMOS platform for the characterization of the cytoplasm dielectric properties at microwave frequencies. Compared with MHz impedance cytometers, operating at GHz frequencies offers direct intracellular permittivity probing due to electric fields penetrating through the cellular membrane. To overcome the detection challenges at high frequencies, the spectrometer employs on-chip oscillator-based sensors, which embeds simultaneous frequency generation, electrode excitation, and signal detection capabilities. By employing an injection-locking phase-detection technique, the spectrometer offers state-of-the-art sensitivity, achieving a less than 1 aFrms capacitance detection limit (or 5 ppm in frequency-shift) at a 100 kHz noise filtering bandwidth, enabling high throughput (>1k cells per s), with a measured cellular SNR of more than 28 dB. With CMOS/microfluidics co-design, we distribute four sensing channels at 6.5, 11, 17.5, and 30 GHz in an arrayed format whereas the frequencies are selected to center around the water relaxation frequency at 18 GHz. An issue in the integration of CMOS and microfluidics due to size mismatch is also addressed through introducing a cost-efficient epoxy-molding technique. With 3-D hydrodynamic focusing microfluidics, we perform characterization on four different cell lines including two breast cell lines (MCF-10A and MDA-MB-231) and two leukocyte cell lines (K-562 and THP-1). After normalizing the higher frequency signals to the 6.5 GHz ones, the size-independent dielectric opacity shows a differentiable distribution at 17.5 GHz between normal (0.905 ± 0.160, mean ± std.) and highly metastatic (1.033 ± 0.107) breast cells with p ≪ 0.001.

High-content analysis of single cells directly assembled on CMOS sensor based on color imaging.

PubMed

Tanaka, Tsuyoshi; Saeki, Tatsuya; Sunaga, Yoshihiko; Matsunaga, Tadashi

2010-12-15

A complementary metal oxide semiconductor (CMOS) image sensor was applied to high-content analysis of single cells which were assembled closely or directly onto the CMOS sensor surface. The direct assembling of cell groups on CMOS sensor surface allows large-field (6.66 mm×5.32 mm in entire active area of CMOS sensor) imaging within a second. Trypan blue-stained and non-stained cells in the same field area on the CMOS sensor were successfully distinguished as white- and blue-colored images under white LED light irradiation. Furthermore, the chemiluminescent signals of each cell were successfully visualized as blue-colored images on CMOS sensor only when HeLa cells were placed directly on the micro-lens array of the CMOS sensor. Our proposed approach will be a promising technique for real-time and high-content analysis of single cells in a large-field area based on color imaging. Copyright © 2010 Elsevier B.V. All rights reserved.

Multiplane and Spectrally-Resolved Single Molecule Localization Microscopy with Industrial Grade CMOS cameras.

PubMed

Babcock, Hazen P

2018-01-29

This work explores the use of industrial grade CMOS cameras for single molecule localization microscopy (SMLM). We show that industrial grade CMOS cameras approach the performance of scientific grade CMOS cameras at a fraction of the cost. This makes it more economically feasible to construct high-performance imaging systems with multiple cameras that are capable of a diversity of applications. In particular we demonstrate the use of industrial CMOS cameras for biplane, multiplane and spectrally resolved SMLM. We also provide open-source software for simultaneous control of multiple CMOS cameras and for the reduction of the movies that are acquired to super-resolution images.

Survey of key technologies on millimeter-wave CMOS integrated circuits

NASA Astrophysics Data System (ADS)

Yu, Fei; Gao, Lei; Li, Lixiang; Cai, Shuo; Wang, Wei; Wang, Chunhua

2018-05-01

In order to provide guidance for the development of high performance millimeter-wave complementary metal oxide semiconductor (MMW-CMOS) integrated circuits (IC), this paper provides a survey of key technologies on MMW-CMOS IC. Technical background of MMW wireless communications is described. Then the recent development of the critical technologies of the MMW-CMOS IC are introduced in detail and compared. A summarization is given, and the development prospects on MMW-CMOS IC are also discussed.

Single-event transient imaging with an ultra-high-speed temporally compressive multi-aperture CMOS image sensor.

PubMed

Mochizuki, Futa; Kagawa, Keiichiro; Okihara, Shin-ichiro; Seo, Min-Woong; Zhang, Bo; Takasawa, Taishi; Yasutomi, Keita; Kawahito, Shoji

2016-02-22

In the work described in this paper, an image reproduction scheme with an ultra-high-speed temporally compressive multi-aperture CMOS image sensor was demonstrated. The sensor captures an object by compressing a sequence of images with focal-plane temporally random-coded shutters, followed by reconstruction of time-resolved images. Because signals are modulated pixel-by-pixel during capturing, the maximum frame rate is defined only by the charge transfer speed and can thus be higher than those of conventional ultra-high-speed cameras. The frame rate and optical efficiency of the multi-aperture scheme are discussed. To demonstrate the proposed imaging method, a 5×3 multi-aperture image sensor was fabricated. The average rising and falling times of the shutters were 1.53 ns and 1.69 ns, respectively. The maximum skew among the shutters was 3 ns. The sensor observed plasma emission by compressing it to 15 frames, and a series of 32 images at 200 Mfps was reconstructed. In the experiment, by correcting disparities and considering temporal pixel responses, artifacts in the reconstructed images were reduced. An improvement in PSNR from 25.8 dB to 30.8 dB was confirmed in simulations.

Design and Performance of a Pinned Photodiode CMOS Image Sensor Using Reverse Substrate Bias.

PubMed

Stefanov, Konstantin D; Clarke, Andrew S; Ivory, James; Holland, Andrew D

2018-01-03

A new pinned photodiode (PPD) CMOS image sensor with reverse biased p-type substrate has been developed and characterized. The sensor uses traditional PPDs with one additional deep implantation step to suppress the parasitic reverse currents, and can be fully depleted. The first prototypes have been manufactured on an 18 µm thick, 1000 Ω·cm epitaxial silicon wafers using 180 nm PPD image sensor process. Both front-side illuminated (FSI) and back-side illuminated (BSI) devices were manufactured in collaboration with Teledyne e2v. The characterization results from a number of arrays of 10 µm and 5.4 µm PPD pixels, with different shape, the size and the depth of the new implant are in good agreement with device simulations. The new pixels could be reverse-biased without parasitic leakage currents well beyond full depletion, and demonstrate nearly identical optical response to the reference non-modified pixels. The observed excessive charge sharing in some pixel variants is shown to not be a limiting factor in operation. This development promises to realize monolithic PPD CIS with large depleted thickness and correspondingly high quantum efficiency at near-infrared and soft X-ray wavelengths.

Design and Performance of a Pinned Photodiode CMOS Image Sensor Using Reverse Substrate Bias †

PubMed Central

Clarke, Andrew S.; Ivory, James; Holland, Andrew D.

2018-01-01

A new pinned photodiode (PPD) CMOS image sensor with reverse biased p-type substrate has been developed and characterized. The sensor uses traditional PPDs with one additional deep implantation step to suppress the parasitic reverse currents, and can be fully depleted. The first prototypes have been manufactured on an 18 µm thick, 1000 Ω·cm epitaxial silicon wafers using 180 nm PPD image sensor process. Both front-side illuminated (FSI) and back-side illuminated (BSI) devices were manufactured in collaboration with Teledyne e2v. The characterization results from a number of arrays of 10 µm and 5.4 µm PPD pixels, with different shape, the size and the depth of the new implant are in good agreement with device simulations. The new pixels could be reverse-biased without parasitic leakage currents well beyond full depletion, and demonstrate nearly identical optical response to the reference non-modified pixels. The observed excessive charge sharing in some pixel variants is shown to not be a limiting factor in operation. This development promises to realize monolithic PPD CIS with large depleted thickness and correspondingly high quantum efficiency at near-infrared and soft X-ray wavelengths. PMID:29301379

Portable design rules for bulk CMOS

NASA Technical Reports Server (NTRS)

Griswold, T. W.

1982-01-01

It is pointed out that for the past several years, one school of IC designers has used a simplified set of nMOS geometric design rules (GDR) which is 'portable', in that it can be used by many different nMOS manufacturers. The present investigation is concerned with a preliminary set of design rules for bulk CMOS which has been verified for simple test structures. The GDR are defined in terms of Caltech Intermediate Form (CIF), which is a geometry-description language that defines simple geometrical objects in layers. The layers are abstractions of physical mask layers. The design rules do not presume the existence of any particular design methodology. Attention is given to p-well and n-well CMOS processes, bulk CMOS and CMOS-SOS, CMOS geometric rules, and a description of the advantages of CMOS technology.

High-sensitivity silicon nanowire phototransistors

NASA Astrophysics Data System (ADS)

Tan, Siew Li; Zhao, Xingyan; Dan, Yaping

2014-08-01

Silicon nanowires (SiNWs) have emerged as a promising material for high-sensitivity photodetection in the UV, visible and near-infrared spectral ranges. In this work, we demonstrate novel planar SiNW phototransistors on silicon-oninsulator (SOI) substrate using CMOS-compatible processes. The device consists of a bipolar transistor structure with an optically-injected base region. The electronic and optical properties of the SiNW phototransistors are investigated. Preliminary simulation and experimental results show that nanowire geometry, doping densities and surface states have considerable effects on the device performance, and that a device with optimized parameters can potentially outperform conventional Si photodetectors.

77 FR 26787 - Certain CMOS Image Sensors and Products Containing Same; Notice of Receipt of Complaint...

Federal Register 2010, 2011, 2012, 2013, 2014

2012-05-07

... INTERNATIONAL TRADE COMMISSION [Docket No. 2895] Certain CMOS Image Sensors and Products.... International Trade Commission has received a complaint entitled Certain CMOS Image Sensors and Products... importation, and the sale within the United States after importation of certain CMOS image sensors and...

Expansion of CMOS array design techniques

NASA Technical Reports Server (NTRS)

Feller, A.; Ramondetta, P.

1977-01-01

The important features of the multiport (double entry) automatic placement and routing programs for standard cells are described. Measured performance and predicted performance were compared for seven CMOS/SOS array types and hybrids designed with the high speed CMOS/SOS cell family. The CMOS/SOS standard cell data sheets are listed and described.

CMOS sensors for atmospheric imaging

NASA Astrophysics Data System (ADS)

Pratlong, Jérôme; Burt, David; Jerram, Paul; Mayer, Frédéric; Walker, Andrew; Simpson, Robert; Johnson, Steven; Hubbard, Wendy

2017-09-01

Recent European atmospheric imaging missions have seen a move towards the use of CMOS sensors for the visible and NIR parts of the spectrum. These applications have particular challenges that are completely different to those that have driven the development of commercial sensors for applications such as cell-phone or SLR cameras. This paper will cover the design and performance of general-purpose image sensors that are to be used in the MTG (Meteosat Third Generation) and MetImage satellites and the technology challenges that they have presented. We will discuss how CMOS imagers have been designed with 4T pixel sizes of up to 250 μm square achieving good charge transfer efficiency, or low lag, with signal levels up to 2M electrons and with high line rates. In both devices a low noise analogue read-out chain is used with correlated double sampling to suppress the readout noise and give a maximum dynamic range that is significantly larger than in standard commercial devices. Radiation hardness is a particular challenge for CMOS detectors and both of these sensors have been designed to be fully radiation hard with high latch-up and single-event-upset tolerances, which is now silicon proven on MTG. We will also cover the impact of ionising radiation on these devices. Because with such large pixels the photodiodes have a large open area, front illumination technology is sufficient to meet the detection efficiency requirements but with thicker than standard epitaxial silicon to give improved IR response (note that this makes latch up protection even more important). However with narrow band illumination reflections from the front and back of the dielectric stack on the top of the sensor produce Fabry-Perot étalon effects, which have been minimised with process modifications. We will also cover the addition of precision narrow band filters inside the MTG package to provide a complete imaging subsystem. Control of reflected light is also critical in obtaining the required optical performance and this has driven the development of a black coating layer that can be applied between the active silicon regions.

Optimized sensitivity of Silicon-on-Insulator (SOI) strip waveguide resonator sensor

PubMed Central

TalebiFard, Sahba; Schmidt, Shon; Shi, Wei; Wu, WenXuan; Jaeger, Nicolas A. F.; Kwok, Ezra; Ratner, Daniel M.; Chrostowski, Lukas

2017-01-01

Evanescent field sensors have shown promise for biological sensing applications. In particular, Silicon-on-Insulator (SOI)-nano-photonic based resonator sensors have many advantages for lab-on-chip diagnostics, including high sensitivity for molecular detection and compatibility with CMOS foundries for high volume manufacturing. We have investigated the optimum design parameters within the fabrication constraints of Multi-Project Wafer (MPW) foundries that result in the highest sensitivity for a resonator sensor. We have demonstrated the optimum waveguide thickness needed to achieve the maximum bulk sensitivity with SOI-based resonator sensors to be 165 nm using the quasi-TM guided mode. The closest thickness offered by MPW foundry services is 150 nm. Therefore, resonators with 150 nm thick silicon waveguides were fabricated resulting in sensitivities as high as 270 nm/RIU, whereas a similar resonator sensor with a 220 nm thick waveguide demonstrated sensitivities of approximately 200 nm/RIU. PMID:28270963

A High-Performance Application Specific Integrated Circuit for Electrical and Neurochemical Traumatic Brain Injury Monitoring.

PubMed

Pagkalos, Ilias; Rogers, Michelle L; Boutelle, Martyn G; Drakakis, Emmanuel M

2018-05-22

This paper presents the first application specific integrated chip (ASIC) for the monitoring of patients who have suffered a Traumatic Brain Injury (TBI). By monitoring the neurophysiological (ECoG) and neurochemical (glucose, lactate and potassium) signals of the injured human brain tissue, it is possible to detect spreading depolarisations, which have been shown to be associated with poor TBI patient outcome. This paper describes the testing of a new 7.5 mm 2 ASIC fabricated in the commercially available AMS 0.35 μm CMOS technology. The ASIC has been designed to meet the demands of processing the injured brain tissue's ECoG signals, recorded by means of depth or brain surface electrodes, and neurochemical signals, recorded using microdialysis coupled to microfluidics-based electrochemical biosensors. The potentiostats use switchedcapacitor charge integration to record currents with 100 fA resolution, and allow automatic gain changing to track the falling sensitivity of a biosensor. This work supports the idea of a "behind the ear" wireless microplatform modality, which could enable the monitoring of currently non-monitored mobile TBI patients for the onset of secondary brain injury. ©2018 The Authors. Published by Wiley-VCH Verlag GmbH & Co. KGaA.

Mapping Electrical Crosstalk in Pixelated Sensor Arrays

NASA Technical Reports Server (NTRS)

Seshadri, S.; Cole, D. M.; Hancock, B. R.; Smith, R. M.

2008-01-01

Electronic coupling effects such as Inter-Pixel Capacitance (IPC) affect the quantitative interpretation of image data from CMOS, hybrid visible and infrared imagers alike. Existing methods of characterizing IPC do not provide a map of the spatial variation of IPC over all pixels. We demonstrate a deterministic method that provides a direct quantitative map of the crosstalk across an imager. The approach requires only the ability to reset single pixels to an arbitrary voltage, different from the rest of the imager. No illumination source is required. Mapping IPC independently for each pixel is also made practical by the greater S/N ratio achievable for an electrical stimulus than for an optical stimulus, which is subject to both Poisson statistics and diffusion effects of photo-generated charge. The data we present illustrates a more complex picture of IPC in Teledyne HgCdTe and HyViSi focal plane arrays than is presently understood, including the presence of a newly discovered, long range IPC in the HyViSi FPA that extends tens of pixels in distance, likely stemming from extended field effects in the fully depleted substrate. The sensitivity of the measurement approach has been shown to be good enough to distinguish spatial structure in IPC of the order of 0.1%.

PFM2: a 32 × 32 processor for X-ray diffraction imaging at FELs

NASA Astrophysics Data System (ADS)

Manghisoni, M.; Fabris, L.; Re, V.; Traversi, G.; Ratti, L.; Grassi, M.; Lodola, L.; Malcovati, P.; Vacchi, C.; Pancheri, L.; Benkechcache, M. E. A.; Dalla Betta, G.-F.; Xu, H.; Verzellesi, G.; Ronchin, S.; Boscardin, M.; Batignani, G.; Bettarini, S.; Casarosa, G.; Forti, F.; Giorgi, M.; Paladino, A.; Paoloni, E.; Rizzo, G.; Morsani, F.

2016-11-01

This work is concerned with the design of a readout chip for application to experiments at the next generation X-ray Free Electron Lasers (FEL). The ASIC, named PixFEL Matrix (PFM2), has been designed in a 65 nm CMOS technology and consists of 32 × 32 pixels. Each cell covers an area of 110 × 110 μm2 and includes a low-noise charge sensitive amplifier (CSA) with dynamic signal compression, a time-variant shaper used to process the preamplifier output signal, a 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) and digital circuitry for channel control and data readout. Two different solutions for the readout channel, based on different versions of the time-variant filter, have been integrated in the chip. Both solutions can be operated in such a way to cope with the high frame rate (exceeding 1 MHz) foreseen for future X-ray FEL machines. The ASIC will be bump bonded to a slim/active edge pixel sensor to form the first demonstrator for the PixFEL X-ray imager. This work has been carried out in the frame of the PixFEL project funded by Istituto Nazionale di Fisica Nucleare (INFN), Italy.

Design and performances of a low-noise and radiation-hardened readout ASIC for CdZnTe detectors

NASA Astrophysics Data System (ADS)

Bo, Gan; Tingcun, Wei; Wu, Gao; Yongcai, Hu

2016-06-01

In this paper, we present the design and performances of a low-noise and radiation-hardened front-end readout application specific integrated circuit (ASIC) dedicated to CdZnTe detectors for a hard X-ray imager in space applications. The readout channel is comprised of a charge sensitive amplifier, a CR-RC shaping amplifier, an analog output buffer, a fast shaper, and a discriminator. An 8-channel prototype ASIC is designed and fabricated in TSMC 0.35-μm mixed-signal CMOS technology, the die size of the prototype chip is 2.2 × 2.2 mm2. The input energy range is from 5 to 350 keV. For this 8-channel prototype ASIC, the measured electrical characteristics are as follows: the overall gain of the readout channel is 210 V/pC, the linearity error is less than 2%, the crosstalk is less than 0.36%, The equivalent noise charge of a typical channel is 52.9 e- at zero farad plus 8.2 e- per picofarad, and the power consumption is less than 2.4 mW/channel. Through the measurement together with a CdZnTe detector, the energy resolution is 5.9% at the 59.5-keV line under the irradiation of the radioactive source 241Am. The radiation effect experiments show that the proposed ASIC can resist the total ionization dose (TID) irradiation of higher than 200 krad(Si). Project supported by the National Key Scientific Instrument and Equipment Development Project (No. 2011YQ040082), the National Natural Science Foundation of China (Nos. 11475136, 11575144, 61176094), and the Shaanxi Natural Science Foundation of China (No. 2015JM1016).

The design of high dynamic range ROIC for IRFPAs

NASA Astrophysics Data System (ADS)

Jiang, Dazhao; Liang, Qinghua; Zhang, Qiwen; Chen, Honglei; Ding, Ruijun

2015-10-01

The charge packet readout integrated circuit (ROIC) technology for the IRFPAs is introduced, which can realize that every pixel achieves a very high capacity of the electrons storage, and it also improves the performance of the SNR and reduces the saturation possibility of the pixels. The ROIC for the LWIR requires ability that obtaining high capacity for storing electrons. For the conventional ROIC, the maximum charge capacity is determined by the integration capacitance and the operating voltage, it can achieve a high charge capacity through increasing the area of the integration capacitor or raising the operating voltage. And this paper would introduce a digital method of ROIC that can achieve a very high charge capacity. The circuit architecture of this approach includes the following parts, a preamplifier, a comparator, a counter, and memory arrays. And the maximum charge capacity of the pixel is determined by the counter bits. This new method can achieve a high charge capacity more than 1Ge- every pixel and output the digital signal directly, while that of conventional ROIC is less than 50Me- and output the analog signal from the pixel. In this new circuit, the comparator is a important module, as the integration voltage value need compare with threshold voltage through the comparator all the time during the integration period, and we will discuss the influence of the comparator. This work design the circuit with the CSMC 0.35um CMOS technology, and the simulation use the spectre model.

A Single-Chip Solar Energy Harvesting IC Using Integrated Photodiodes for Biomedical Implant Applications.

PubMed

Chen, Zhiyuan; Law, Man-Kay; Mak, Pui-In; Martins, Rui P

2017-02-01

In this paper, an ultra-compact single-chip solar energy harvesting IC using on-chip solar cell for biomedical implant applications is presented. By employing an on-chip charge pump with parallel connected photodiodes, a 3.5 × efficiency improvement can be achieved when compared with the conventional stacked photodiode approach to boost the harvested voltage while preserving a single-chip solution. A photodiode-assisted dual startup circuit (PDSC) is also proposed to improve the area efficiency and increase the startup speed by 77%. By employing an auxiliary charge pump (AQP) using zero threshold voltage (ZVT) devices in parallel with the main charge pump, a low startup voltage of 0.25 V is obtained while minimizing the reversion loss. A 4 V in gate drive voltage is utilized to reduce the conduction loss. Systematic charge pump and solar cell area optimization is also introduced to improve the energy harvesting efficiency. The proposed system is implemented in a standard 0.18- [Formula: see text] CMOS technology and occupies an active area of 1.54 [Formula: see text]. Measurement results show that the on-chip charge pump can achieve a maximum efficiency of 67%. With an incident power of 1.22 [Formula: see text] from a halogen light source, the proposed energy harvesting IC can deliver an output power of 1.65 [Formula: see text] at 64% charge pump efficiency. The chip prototype is also verified using in-vitro experiment.

Hybrid CMOS/Molecular Integrated Circuits

NASA Astrophysics Data System (ADS)

Stan, M. R.; Rose, G. S.; Ziegler, M. M.

CMOS silicon technologies are likely to run out of steam in the next 10-15 years despite revolutionary advances in the past few decades. Molecular and other nanoscale technologies show significant promise but it is unlikely that they will completely replace CMOS, at least in the near term. This chapter explores opportunities for using CMOS and nanotechnology to enhance and complement each other in hybrid circuits. As an example of such a hybrid CMOS/nano system, a nanoscale programmable logic array (PLA) based on majority logic is described along with its supplemental CMOS circuitry. It is believed that such systems will be able to sustain the historical advances in the semiconductor industry while addressing manufacturability, yield, power, cost, and performance challenges.